1992_NEC_DSP_and_Speech_Processor_Products 1992 NEC DSP And Speech Processor Products
User Manual: 1992_NEC_DSP_and_Speech_Processor_Products
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DIGITAL SIGNAL PROCESSOR (DSP)
AND SPEECH PROCESSOR PRODUCTS
DATA BOOK
NEe
NEe Electronics Inc.
fttlEC
1992
Digital Signal Processor (DSP)
and
Speech Processor Products
Data Book
March 1992
Document No. 50052-1
©1992 NEG Electronics Inc./Printed in the U.S.A.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Electronics Inc. The information in this document is subject to change without notice. Devices sold
by NEC Electronics Inc. are covered by the warranty and patent indemnification provisions appearing in NEC
Electronics Inc. Terms and Conditions of Sale only. NEC Electronics Inc. makes no warranty, express, statutory,
implied, or by description, regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. NEC Electronics Inc. makes no warranty of merchantability or fitness for any
purpose. NEC Electronics Inc. assumes no responsibility for any errors that may appear in this document. NEC
Electronics Inc. makes no commitment to update or to keep current the information contained in this document.
t-IEC
ii
t-{EC
Selection Guides
Reliability and Quality Control
Digital Signal Processors
Speech Processors
Development Tools
Package Drawings
iii
NEe
iv
NEe
Contents
Section 1
Selection Guides
Section 3
Digital Signal Processors
Single-Chip Microcomputers
1-1
V-Series and RISC Microprocessors and
Peripherals
1-8
1-11
DSP and Speech Products
1-13
1-15
1-18
1-20
1-24
1-26
1-28
3a
Digital Signal Processors
~PD77C25/77P25
Intelligent Peripheral Devices (IPD)
Development Tools for Micro Products
V-Series Microprocessors
75xx Series Single-Chip Microcomputers
75xxx Series Single-Chip Microcomputers
78xx Series Single-Chip Microcomputers
K2 (782xx) Series Single-Chip
Microcomputers
K3 (783xx) Series Single-Chip
Microcomputers
DSP and Speech Products
PG-1500 Programming Adapters
~PD77C20A,7720A,77P20
3b
Digital Signal Processor
~PD77220, 77P220
24-Bit Fixed-Point Digital Signal Processor
3c
~PD77230A,77P230
3d
32-Bit Floating-Point Digital Signal Processor
(150 ns cycle time)
~PD77240
3e
32-Bit Floating-Point Digital Signal Processor
(90 ns cycle time)
~PD77810
3f
Modem Digital Signal Processor
1-30
1-32
~PD7281
39
Image Pipelined Processor
~PD9305
3h
Memory Access and General Bus Interface for
the I1PD7281
Section 2
Reliability and Quality Control
Built-inTQC
2-1
Approaches to TQC
2-1
Implementation of Quality Control
2-3
Reliability Theory
2-5
Failure Analysis
2-9
Summary
2-9
ADPCM Speech Processors
Figure 1. NEC's Quality Control System
2-2
~PD7759
Figure 2. New Product Development
2-3
ADPCM Speech Processor
Figure 3. Electrical Testing and Screening
2-5
Figure 4. Reliability Life (Bathtub) Curve
2-5
Appendix 1A. Typical QC Flow for CMOS
Fabrication
2-10
Appendix 1B. Typical QC Flow for PLCC
Assembly/Test
2-11
Appendix 2. Typical Reliability Assurance
Tests
2-13
Appendix 3. New Product/Process Change
Tests
2-13
Appendix 4. Failure Analysis Flowchart
2-14
Section 4
Speech Processors
~PD77C30
4a
ADPCM Speech Encoder!Decoder
~PD7755/56/P56/57158
~PD77501
4b
4c
4d
ADPCM Record and Playback Speech
Processor
~PD77522
4e
ADPCM Codec
v
NEe
Contents
Section 5
Development Tools
Section 5
Development Tools
Third-Party Development Tools
5-1
p--PD-n-C-'20.-'---IA-,-7-7-'2-'-OA-,-77-PZ-O-11-ig-i-ta-'-S-ig-n-B-, - - - Processors
pPD775x ADPCM Speech Processors and
pPD77501 ADPCM Record and P'ayback Speech
Processor
NV-300
So
Speech Analysis Tool for J.lPD775x and
J.lPD77501
EVAKIT-7720B
J.lPD7720 Standalone Emulator
Sa
ASM77
J.lPD7720 Absolute Assembler
Sb
pPD77C25/77P25 Digita' Signa' Processor
EVAKIT-77C25
J.lPD77C25 Standalone Emulator
Sc
RA77C25
J.lPD77C25 Relocatable Assembler Package
Sd
SM77C2S
PC-Based Simulator for J.lPD77C25 and
J.lPD77C20
Se
EVAKIT-77220
J.lPD77220 Standalone Emulator
Sf
EVAKIT-77230
J.lPD77230 Standalone Emulator
S9
DDK-77220A
J.lPD77220 Evaluation Board
Sh
RA77230
J.lPD77220/J.lPD77230 Relocatable Assembler
Package
Si
SM77230
PC-Based Simulator for J.lPD77220/J.lPD77230
Sj
pPD77240 Digita' Signa' Processor
IE-77240
In-Circuit Emulator for the J.lPD77240
5k
RA77240
Relocatable Assembler Package
SI
pPD778tO Modem Digita' Signa' Processor
RA7781 0
Relocatable Assembler Package for the
J.lPD77810
vi
Sp
EB-77Sx
Demonstration and Evaluation Box for
J.lPD775x
5q
PG-1S00 Series
EPROM Programmer
Sr
Section 6
Package Drawings
pPD77220/P220, pPD77230/P230 Digita' Signa'
Processors
IE-77810
In-Circuit Emulator for the J.lPD77810
NV-31 0
Speech Analysis Tool for J.lPD775x
Sm
Sn
Package/Device Cross Reference
6-1
18-Pin Plastic DIP (300 mil) (A, C Outine)
6-3
18-Pin Plastic DIP (300 mil) (SA Outline)
6-3
20-Pin Plastic DIP (300 mil)
6-4
24-Pin Plastic SOP (450 miQ
6-4
28-Pin Plastic SOP (450 mil)
6-S
28-Pin Plastic DIP (600 miQ
6-5
28-Pin Ceramic DIP (600 mil)
6-6
28-Pin Cerdip (600 mil)
6-7
28-Pin PLCC
6-8
32-Pin SOP (525 mil)
6-8
40-Pin Plastic DIP (600 mil)
6-9
40-Pin Ceramic DIP (600 miQ
6-10
44-Pin PLCC
6-11
52-Pin Plastic QFP
6-12
68-Pin Ceramic PGA (A Outline)
6-13
68-Pin Ceramic PGA (A-1 Outline)
6-14
68-Pin PLCC
6-1S
8O-Pin Plastic QFP
6-16
132-Pin Ceramic PGA
6-17
ftIEC
Numerical Index
Device, "PO
7281
7720A
77220
77230A
77240
77501
77522
7755
7756
7757
7758
7759
77810
77C20A
77C25
77C30
np20
77P25
77P220
77P230
77P56
9305
Contents
Section
39
3a
3c
3d
3e
4d
4e
4b
4b
4b
4b
4c
3.
3a
3b
4a
3a
3b
3c
3d
4b
3h
vii
Contents
viii
ttlEC
1't{EC
Se.ection Guides
NEe
Selection Guides
Section 1
Selection Guides
Part Numbering System
1-1
"PD72001 L
1-8
"p
Intelligent Peripheral Devices (IPD)
1-11
DSP and Speech Products
1-13
D
72001
L
Single-Chip Microcomputers
V-Series and RISC Microprocessors and
Peripherals
Development Tools for Micro Products
V-Series Microprocessors
75xx Series Single-Chip Microcomputers
75xxx Series Single-Chip Microcomputers
78xx Series Single-Chip Microcomputers
K2 (782xx) Series Single-Chip
Microcomputers
K3 (783xx) Series Single-Chip
Microcomputers
DSP and Speech Products
. PG-1500 Programming Adapters
1-15
1-18
1-20
1-24
1-26
1-28
1-30
1-32
Typical microdevice part number
NEC monolithic silicon integrated circuit
Device type (D = digital MOS)
Device identifier (alphanumeric)
Package type (L = PLCC)
A part number may include an alphanumeric suffix
that identifies special device characteristics; for
example, pPD72001L-11 has an 11-MHz CPU clock
rating.
ttrEC
Single-Chip Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xx Series
Device
("PO)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
I/O
Package t
Pins
7502A
LCD controller/driver
0.41
2.5 to 6.0
2K
128
23
QFP
64
750M
LCD controller/driver
0.41
2.5 to 6.0
4K
224
23
QFP
64
7507B
General-purpose
0.5
2.2 to 6.0
2K
128
32
SDIP
QFP
40
44
7508B
General-purpose
0.5
2.2 to 6.0
4K
224
32
SDIP
QFP
40
44
7533
ND converter
0.51
2.7 to 6.0
4K
160
30
DIP
SDIP
QFP
42
42
44
75CG33
Piggyback EPROM; ND
converter
0.51
4.5 to 5.5
4K
160
30
Ceramic DIP
42
7554
Serial I/O; external
clock or RC oscillator
0.71
2.5 to 6.0
lK
64
16
SDIP
SOP
20
20
7554A
Serial I/O; external
clock or RC oscillator
0.71
2.0 to 6.0
lK
64
16
SDIP
SOP
20
20
75P54
Serial I/O; external
clock or RC oscillator
0.71
4.5 to 6.0
lKOTPROM
64
16
SDIP
SOP
20
20
7564/7564A
Serial I/O; ceramic
oscillator
0.71
2.7 to 6.0
lK
64
15
SDIP
SOP
20
20
75P64
Serial I/O; ceramic
oscillator
0.71
4.5 to 6.0
lKOTPROM
64
15
SDIP
SOP
20
20
7556
Comparator; external
clock or RC oscillator
0.71
2.5 to 6.0
lK
64
20
SDIP
SOP
24
24
7556A
Comparator; external
clock or RC oscillator
0.71
2.0 to 6.0
lK
64
20
SDIP
SOP
24
24
75P56
Comparator; external
clock or RC oscillator
0.71
4.5 to 6.0
lKOTPROM
64
20
SDIP
SOP
24
24
7566/7566A
Comparator; ceramic
oscillator
0.71
2.7 to 6.0
lK
64
19
SDiP
SOP
24
24
75P66
Comparator; ceramic
oscillator
0.71
4.5 to 6.0
lKOTPROM
64
19
SDIP
SOP
24
24
t
Plastic unless ceram ic (or cerdip) is specified.
4-Bit, Single-Chip CMOS Microcomputers; 75xxx Series
Device ("PO)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
I/O
Package t
Pins
75004
General-purpose
4.19
2.7 to 6.0
4K
512
34
SDIP
QFP
42
44
75006
General-purpose
4.19
2.7 to 6.0
6K
512
34
SDIP
QFP
42
44
75008
General-purpose
4.19
2.7 to 6.0
8K
512
34
SDIP
QFP
42
44
4.19
4.5 to 5.5
8KOTPROM
512
34
SDIP
QFP
42
44
75P008
Genera~purpose;
on-
chip OTPROM
75028
ND converter
4.19
2.7 to 6.0
8K
512
48
SDIP
QFP
64
64
75P036
ND converter; on-chip
4.19
2.7 to 6.0
16KOTPROM
1024
48
SDIP
QFP
64
64
OTPROM
50580
1-1
-~
-
------_.-
•
t'tfEC
Single-Chip Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xxx Series (cont)
Clock
(MHz)
Supply
Voltage (V)
ROM (Xa)
RAM (X4)
I/O
Package
NO converter; 1K x 4
EEPROM
4.19
2.7 to 6.0
8K
512
48
SOIP
QFP
64
64
75P048 *
NO converter; 1K x 4
EEPROM; on·chip
OTPROM
4.19
2.7 to 6.0
8KOTPROM
512
48
SOIP
QFP
64
64
75104
High·end with 8·bit
instruction
4.19
2.7 to 6.0
4K
320
52
SOIP
QFP
64
64
75104A
High·end with 8·bit
instruction
4.19
2.7 to 6.0
4K
320
52
QFP
64
75106
High·end with 8·bit
instruction
4.19
2.7 to 6.0
6K
320
52
SOIP
QFP
64
64
75108
High·end with 8·blt
Instruction
4.19
2.7 to 6.0
8K
512
52
SOIP
QFP
64
64
75108A
High·end with 8·bit
instruction
4.19
2.7 to 6.0
8K
512
52
QFP
64
75108F
High·end with 8·bit
Instruction; high speed
4.19
2.7 to 5.0
8K
512
52
QFP
64
75Pl08
High·end with 8·bit
Instruction; on.chip
OTPROM or UVEPROM
4.19
4.5 to 5.5
8KOTPROM
512
52
SOIP
QFP
64
64
8KUVEPROM
512
52
Shrink cerdip
64
75Pl08B
High·end with 8·bit
instruction; on·chip
OTPROM
4.19
2.7 to 6.0
8KOTPROM
512
52
SOIP
QFP
64
64
75112
High·end with 8·bit
instruction
4.19
2.7 to 6.0
12K
512
52
SOIP
QFP
64
64
75112F
High·end with 8·bit
instruction; high speed
4.19
2.7 to 5.0
12K
512
52
QFP
64
75116
High·end with 8·bit
instruction
4.19
2.7 to 6.0
16K
512
52
SOIP
QFP
64
64
75116F
High-end with 8·bit
instruction; high speed
4.19
2.7 to 5.0
16K
512
52
QFP
64
75P116
High·end with 8·bit
instruction; on·chip
OTPROM
4.19
4.5 to 5.5
16KOTPROM
512
52
SOIP
QFP
64
64
75116H
High·end with 8·bit
instruction; high
speed; low voltage
4.19
1.8 to 5.0
16K
768
52
QFP
64
75117H
High·end with 8·bit
instruction; high
speed; low voltage
4.19
1.8 to 5.0
24K
768
52
QFP
64
75P117H*
High·end with 8·bit
instruction; high
speed; low voltage; on·
chip OTPROM
4.19
1.8 to 5.0
24KOTPROM
768
52
QFP
64
75206
FIP controller/driver
4.19
2.7 to 6.0
6K
369
28
SOIP
QFP
64
"4
75208
FIP controller/driver
4.19
2.7 to 6.0
8K
497
28
SOIP
QFP
64
64
Device (p.PD)
Features
75048
* Under development; consult your NEe Sales Office for availability.
1·2
t
Pins
fttIEC
Single-Chip Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xxx Series (cant)
Device ("PO)
Features
Clock
(MHz)
Supply
VoltageM
ROM (X8)
RAM (X4)
I/O
Package
75212A
FIP controller/driver
4.19
2.7 to 6.0
12K
512
28
SDIP
QFP
64
64
75216A
FIP controller/driver;
on-chip OTPROM
4.19
2.7 to 6.0
16K
512
28
SDIP
QFP
64
64
75P216A
FIP controller/driver;
on-chip OTPROM
4.19
4.5 to 5.5
16KOTPROM
512
28
SDIP
64
75217
FIP controller/driver
4.19
2.7 to 6.0
24K
768
28
SDIP
QFP
64
64
75218
FIP controller/driver
6.0
2.7 to 6.0
32K
1024
28
SDIP
QFP
64
64
75P218
FIP controller/driver;
on-chip OTPROM or
UVEPROM
6.0
2.7 to 6.0
32KOTPROM
1024
28
SDIP
QFP
64
64
32KUVEPROM
1024
28
Ceramic LCC
64
75236
FIP controller/driver;
ND converter
4.19
2.7 to 6.0
16K
768
40
QFP
94
75237
FIP controller/driver;
A/D converter
6.0
2.7 to 6.0
24K
1024
40
QFP
94
FIP controller/driver;
6.0
2.7 to 6.0
32K
1024
40
QFP
94
6.0
2.7 to 6.0
32KOTPROM
1024
40
QFP
94
32KUVEPROM
1024
40
Ceramic LCC
94
8K
512
28
SDIP
QFP
64
64
75238
t
Pins
NO converter
75P23B
FIP controller/driver;
NO converter; on-chip
OTPROM or UVEPROM
75268
FIP controller/driver
4.19
2.7 to 6.0
75304
LCD controller/driver
4.19
2.7 to 6.0
4K
512
32
QFP
80
75306
LCD controller/driver
4.19
2.7 to 6.0
6K
512
32
QFP
80
75308
LCD controller/driver
4.19
2.7 to 6.0
8K
512
32
QFP
80
75308B
LCD controller/driver;
low voltage
4.19
2.0 to 6.0
8K
512
32
QFP
80
75P308
LCD controller/driver;
on-chip OTPROM or
UVEPROM
4.19
4.75 to 5.25
8KOTPROM
512
32
QFP
80
8KUVEPROM
512
32
Ceramic LCC
80
75312
LCD controller/driver
4.19
2.7 to 6.0
12K
512
32
QFP
80
75316
LCD controller/driver
4.19
2.7 to 6.0
16K
512
32
QFP
80
75P316
LCD controller/driver;
on-chip OTPROM
4.19
4.75 to 5.25
16KOTPROM
512
32
QFP
80
75P316A
LCD controller/driver;
on-chip OTPROM or
UVEPROM
4.19
2.7 to 6.0
LCD controller/driver;
4.19
75328
16KOTPROM
512
32
QFP
80
16KUVEPROM
512
32
Ceramic LCC
80
2.7 to 6.0
8K
512
36
QFP
80
4.19
4.5 to 5.5
8KOTPROM
512
36
QFP
80
4.19
2.7 to 6.0
16K
768
36
QFP
80
NO converter
75P328
LCD controller/driver;
NO converter; on-chip
OTPROM
75336
LLCD controller/driver;
ND converter; high-end
1-3
•
NEe
Single-Chip Microcomputers
4~Bit,
Single-Chip CMOS Microcomputers; 75xxx Series (cont)
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
I/O
Package
LCD controller/driver;
ND converter; highend; on-chip OTPROM
4.19
2.7 to 6.0
16KOTPROM
768
36
QFP
80
75348
LCD controller/driver;
DTMF, high-end
4.19
2.0 to 6.0
8K
1024
32
QFP
100
75352
LCD controller/driver;
DTMF, high-end
4.19
2.0 to 6.0
12K
1024
32
QFP
100
75402A
Low-end
4.19
2.7 to 6.0
2K
64
22
DIP
SDIP
QFP
28
28
44
75P402
Low-end; on-chip
OTPROM
4.19
4.5 to 5.5
2KOTPROM
64
22
DIP
SDIP
QFP
28
28
75512
High-end;
converter
ND
4.19
2.7 to 6.0
12K
512
64
QFP
80
75516
High-end;
converter
ND
4.19
2.7 to 6.0
16K
512
64
QFP
80
75P516
High-end; ND
converter; on-chip
OTPROM or UVEPROM
4.19
4.75 to 5.5
16KOTPROM
512
64
QFP
80
16K UVEPROM
512
64'
Ceramic LCC
80
75517
High-end; ND
converter; high-speed
6.0
2.7 to 6.0
24K
1024
64
QFP
80
75518
High-end; ND
converter; high-speed
6.0
2.7 to 6.0
32K
1024
64
QFP
80
75P518
High-end; ND
converter; high-speed;
on-chip OTPROM and
UVEPROM
6.0
2.7 to 6.0
32KOTPROM
1024
64
QFP
80
32K UVEPROM
1024
64
Ceramic LCC
80
75616
LCD controller/driver;
DTMF, high-end; NO
converter
6.0
2.0 to 6.0
16K
1536
32
QFP
100
75617
LCD controller/driver;
DTMF, high:end; ND
converter
6.0
2.0 to 6.0
24K
1536
32
QFP
100
75P618
LCD controller/driver;
DTMF, high-end; ND
converter; on-chip
OTPROM
6.0
2.0 to 6.0
32KOTPROM
2048
32
QFP
100
Device ("PO)
Features
75P336
t
Pins
44
t Plastic unless ceramic (or cerdip) is specified.
a-Bit, Single-Chip CMOS Microcomputers; 78xx Series
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
ND converter
15
4.5 to 5.5
External
256
32
QUIP
SDIP
QFP
PLCC
64
64
64
68
ND converter
15
4.5 to 5.5
4K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
Device ("PO)
Features
78Cl0A
CMOS;
78CllA
CMOS;
1-4
t
Pins
NEe
Single-Chip Microcomputers
8-Bit, Single-Chip CMOS Microcomputers; 78xx Series (cont)
Device ("PO)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
78Cl2A
CMOS; A/D converter
15
4.5 to 5.5
8K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
t
Pins
78C14/8C14A
CMOS; AID converter
15
4.5 to 5.5
16K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
78CP14
CMOS; AID converter;
on-chip OTPROM or
LNEPROM
15
4.75 to 5.25
16KOTPROM
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
16KLNEPROM
256
40
Ceramic QUIP
Shrink cerdip
64
64
78C17
CMOS; AID converter
15
4.5 to 5.5
External
1024
40
QUIP
SDIP
QFP
64
64
64
78C18
CMOS; AID converter
15
4.5 to 5.5
32K
1024
40
QUIP
SDIP
QFP
64
64
64
78CP18
CMOS; AID converter;
on-chip OTPROM or
UVEPROM
15
4.75 to 5.25
32KOTPROM
1024
40
QUIP
SDIP
QFP
64
64
64
32KUVEPROM
1024
40
Ceramic LCC
64
t
Plastic unless ceramic (or cerdip) is specified.
8-Bit, Single-Chip CMOS Microcomputers; 782xx (K2) Series
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
8K
384
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78213
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
External
512
36
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78214
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
16K
512
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78P214
CMOS; AID converter;
advanced peripherals;
on-chip OTPROM or
UVEPROM
12
4.5 to 5.5
16KOTPROM
512
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
16KUVEPROM
512
54
Shrink cerdip
64
78217A
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
SDIP
QFP
64
64
Device ("PO)
Features
78212
External
1024
36
t
Pins
1-5
I
..
ttlEC
Single-Chip Microcomputers
8-Bit, Single-Chip CMOS Microcomputers; 782xx (K2) Series (cont)
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
CMOS; NO converter;
advanced peripherals
12
4.5 to 5.5
32K
1024
54
SOIP
QFP
64
64
78P218A
CMOS; NO converter;
advanced peripherals;
on-chip OTPROM or
UVEPROM
12
4.5 to 5.5
32KOTPROM
1024
54
SOIP
QFP
64
64
32K UVEPROM
1024
54
Shrink cerdip
64
78220
CMOS; analog
comparator; large I/O
12
4.5 to 5.5
External
640
53
PLCC
QFP
84
94
78224
CMOS; analog
comparator; large
12
4.5 to 5.5
16K
640
71
PLCC
QFP
84
94
12
4.5 to 5.5
16KOTPROM
640
71
PLCC
QFP
84
94
80
94
Device ("PO)
Features
78218A
78P224
CMOS; analog
comparator; large
on-chip OTPROM
VO
VO;
t
Pins
78233
CMOS; rea~tlme
outputs; NO and O/A
converters
12
4.5 to 5.5
External
640
46
QFP
QFP
PLCC
84
78234
CMOS; reaHime
outputs; NO and O/A
converters
12
4.5 to 5.5
16K
640
64
QFP
QFP
PLCC
80
94
84
78237
CMOS; rea~time
outputs; NO and O/A
converters
12
4.5 to 5.5
External
1024
64
QFP
QFP
PLCC
80
94
84
78238
CMOS; real-time
outputs; NO and O/A
converters
12
4.5 to 5.5
32K
1024
64
QFP
QFP
PLCC
80
94
84
78P238
CMOS; real-time
outputs; NO and O/A
converters; on-chip
OTPROM or UVEPROM
12
4.5 to 5.5
32KOTPROM
1024
64
QFP
QFP
PLCC
80
94
84
32K UVEPROM
1024
64
Ceramic LCC
94
78243
CMOS; NO converter;
EEPROM
12
4.5 to 5.5
External
512
512
EEPROM
36
SOIP
QFP
64
64
78244
CMOS; NO converter;
EEPROM
12
4.5 to 5.5
16K
512
512
EEPROM
54
SOIP
QFP
64
64
t
Plastic unless ceramic (or cerdip) is specified.
8/16-Bit, Single-Chip CMOS Microcomputers; 783xx (K3) Series
Device
!!,PO)
Features
78310A
Rea~time
78312A
1-6
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
motor control
12
4.5 to 5.5
External
256
48
SOIP
QUIP
QFP
PLCC
64
64
64
68
Real-time motor control
12
4.5 to 5.5
8K
256
48
SOIP
QUIP
QFP
PLCC
64
64
64
68
t
Pins
t-IEC
Single-Chip Microcomputers
8/16-Bit, Single-Chip CMOS Microcomputers; 783xx (K3) Series
Device
(,uPD)
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X8)
I/O
Package
Real-time motor
control; on-chip
OTPROM or UVEPROM
12
4.5 to 5.5
8K UVEPROM
256
48
Shrink cerdip
Ceramic OUIP
64
64
8KOTPROM
256
48
SOIP
OUIP
OFP
PLCC
64
64
64
68
78320
Real-time control; NO
converter
16
4.5 to 5.5
External
640
37
OFP
PLCC
74
68
78322
Real-time control; NO
converter
16
4.5 to 5.5
16K
640
55
OFP
PLCC
74
68
78P322
Real-time control; NO
converter; on-chip
OTPROM or UVEPROM
16
4.5 to 5.5
16K OTPROM
640
55
OFP
PLCC
74
68
16K UVEPROM
640
55
Ceramic LCC
Ceramic LCC
68
74
Rea~time
control; NO
16
4.5 to 5.5
External
1024
37
OFP
PLCC
74
68
78324
Real-time control; NO
converter
16
4.5 to 5.5
32K
1024
55
OFP
PLCC
74
68
78P324
Real-time control; NO
converter
16
4.5 to 5.5
32KOTPROM
1024
55
OFP
PLCC
74
68
32K UVEPROM
1024
55
Ceramic LCC
Ceramic LCC
68
74
78P312A
78323
Features
converter
t
Pins
78327
Real-time control; NO
converter; enhanced
real-time output
16
4.5 to 5.5
External
512
34
SOIP
OFP
64
64
78328
Real-time control; NO
converter; enhanced
real-time output
16
4.5 to 5.5
16K
512
52
SOIP
OFP
64
64
78P328
Real-time control; NO
converter; enhanced
real-time output; onchip OTPROM or
UVEPROM
16
4.5 to 5.5
16K OTPROM
512
52
SDIP
OFP
64
64
16K UVEPROM
512
52
Ceramic SOIP
64
78330
Real-time control; NO
converter, enhanced
real-time pulse unit
16
4.5 to 5.5
External
1024
52
OFP
PLCC
94
84
78334
Real-time control; NO
converter, enhanced
real-time pulse unit
16
4.5 to 5.5
32K
1024
70
OFP
PLCC
94
84
78P334
Real-time control; NO
converter, enhanced
rea~time pulse unit;
on-chip OTPROM or
UVEPROM
16
4.5 to 5.5
32KOTPROM
1024
70
OFP
PLCC
94
84
32K UVEPROM
1024
70
Ceramic LCC
Ceramic LCC
94
84
78350
High speed; multiply
and accumulate
instruction
25
4.5 to 5.5
External
640
30
OFP
64
78P352
High speed; multiply
and accumluate
instruction; on-chip
OTPROM
25
4.5 to 5.5
32K OTPROM
640
50
OFP
64
1-7
-.
V-Series and RiSe Microprocessors and Peripherals
NEe
V-Series CMOS Microprocessors
Device,
"PO
Features
Data Bits
Clock (MHz)
Packaget
Pins
70108 (V20)
8088 compati ble; enhanced
8/16
eorl0
DIP
Ceramic DIP
QFP
PLCC
40
40
52
44
70108H (V20H)
Fully static; pin compatible with 80C88
enhanced microprocessor
8/16
10,12,16
DIP
QFP
PLCC
40
52
44
70116 (V30)
8086 compatible; enhanced
16
8 or 10
DIP
Ceramic DIP
QFP
PLCC
40
40
52
44
70116H (V30H)
Fully static; pin compatible with 80C86
enhanced microprocessor
16
10,12,16
DIP
QFP
PLCC
40
52
44
70208 (V40)
MS-DOS, V20 compatible CPU with peripherals
8/16
80rl0
Ceramic PGA
PLCC
QFP
68
68
80
70208H (V40H)
Fully static; low power; 80C88 compatible CPU
plus peripherals
8/16
10,12,16
Ceramic PGA
PLCC
QFP
68
68
80
70216 (V50)
MS-DOS, V30 compatible CPU with peripherals
16/16
80rl0
PGA
PLCC
QFP
68
68
80
70216H (V50H)
Fully slatic; low power; 80C88 compatible CPU
plus peripherals
16
10,12,16
Ceramic PGA
PLCC
QFP
68
68
80
70136 (V33)
Hardwired, enhanced V30
8 and 16
dynamic
12 or 16
PGA
PLCC
68
68
70236 (V53)
V33 core-based; high-integration; DMA, serial
interrupt controller, etc.
8 and 16
dynamic
10,12,16
Ceramic PGA
QFP
132
120
70320 (V25)
MS-DOS compatible mlcrocontroller;-highintegration; DMA, serial
interrupt controller,
etc.
8/16
50r8
PLCC
QFP
84
94
70330 (V35)
MS-DOS compatible microcontroller; highintegration; DMA, serial
interrupt controller,
etc.
16
6
PLCC
QFP
64
70325 (V25 Plus)
MS-DOS compatible microcontroller; highintegration; high-speed DMA
8/16
8 or 10
PLCC
QFP
84
94
70335 (V35 Plus)
MS-DOS compatible microcontroller; highintegration; high-speed DMA
16
80r 10
PLCC
QFP
84
94
70327 (V25
Software Guard)
MS-DOS compatible microcontroller; highintegrationj software protection
8/16
8
PLCC
QFP
84
94
70337 (V35
Software Guard)
MS-DOS compatible microcontroller; highintegration; software protection
16
8
PLCC
QFP
84
94
va,
va,
va,
t Plastic unless ceramic (or cerdip) is specified.
1-8
94
ttlEC
V-Series and RiSe Microprocessors and Peripherals
V-Series CMOS System Support Products
Device,
Clock (MHz)
Package t
Pins
20
DIP
SOP
18
20
8
10
DIP
QFP
PLCC
40
40
44
Serial Control Unit
8
8/10
DIP
QFP
PLCC
28
44
28
71054
Programmable Timer/Controller
8
8/10
DIP
QFP
PLCC
24
44
28
71055
Parallel Interface Unit
8
8/10
DIP
QFP
PLCC
40
44
44
71059
Interrupt Control Unit
8
8/10
DIP
QFP
PLCC
28
44
28
71071
DMA Controller
8/16
8/10
DIP
Ceramic DIP
QFP
PLCC
48
48
52
52
71082
Transparent Latch
8
8
DIP
SOP
20
20
71083
Transparent Latch
8
8
DIP
SOP
20
20
71084
Clock Pulse Generator/Driver
25
DIP
SOP
18
20
71086
Bus Buffer/Driver
8
DIP
SOP
20
8
DIP
SOP
20
20
8/10
DIP
SOP
20
20
QFP
120
"PO
Features
71011
Clock Pulse Generator/Driver
71037
Programmable DMA Controller
71051
Data Bits
8
71087
Bus Buffer/Driver
71088
System Bus Controller
71101
Complex Peripheral Unit; serial, parallel, timer,
interrupt
8
10
8
18
71641
Cache Memory Controller
8/16/32
25
PGA
132
72291
Floating Point Coprocessor for V33/V53
16
16
PGA
68
9335
Numeric Interface Adapter for V40/v50 <+ iB087
8
DIP
20
t
Plastic unless ceramic (or cerdip) is specified.
1-9
NEe
V-Series and RiSe Microprocessors and Peripherals
Rise Microprocessors and Peripherals
Device
Name
Clock
Package
Pins
pPD30310 (V R3000A)
RISC Microprocessor
25 MHz
25,33 MHz
40 MHz
PQFP
PPGA orCPGA
CPGA
160
175
175
pPD30311 (VR3010A)
Floating-Point Prooessor
25 MHz
25,33 MHz
40 MHz
PQFP
PPGA orCPGA
CPGA
64
84
160
pPD30361 (V R3600)
RISC Microprooessor
25,33 MHz
40 MHz
PPGA
CPGA
175
175
pPD30362 (V R3600)
RISC Mioroprooessor
25,33.MHz
40 MHz
PPGA
CPGA
175
175
208
pPD31311
Bus Interfaoe Unit
25,33 MHz
PPGA
pPD46710
16K x 10-Bit x 2 SRAM
Acoess time: 12, 15 20 ns
PLCC
52
Access time: 12, 15, 20 ns
PLCC
68
pPD46741
'8K x 20-Bit x 2 SRAM
pPD30400 (VR4000PC)
RISC Microprooessor
50, 66, 75 MHz
CPGA
179
pPD30401 (V R400OSC)
RISC Microprocessor
50, 66, 75 MHz
CPGAorLGA
447
pPD30402 (VR4000MC)
RISC Microprocessor
50, 66, 75 MHz
CPGAor LGA
447
1-10
NEe
Intelligent Peripheral Devices (IPD)
Communications Controllers
Device,
,.PD
Maximum
Data Rate
Name
Description
Packaget
Pins
72001
CMOS, Advanced
Multiprotocol Serial
Communications
Controller
Functional superset of 8530; 8086/V30
interface; two ful~duplex serial channels; two
DPLLs; two baud-rate generators per channel;
loopback test mode; short frame and mark idle
detection
2.5 Mbls
DIP
OFP
PLCC
40
52
52
72002
CMOS, Advanced
Multiprotocol Serial
Communications
Controller
Low-cost, single-channel version of 72001 ;
software compatible; direct interface to 710711
8237 DMA controllers
2.5 Mbls
DIP
OFP
PLCC
40
44
44
72103
CMOS, HDLC Controller
Single full-duplex serial channel; on-chip DMA
controller
4 Mb/s
SDIP
PLCC
QFP
64
68
80
Graphics Controllers
Device,
,.PD
Maximum
Drawing Rate
Package t
Pins
General-purpose, high-integration controller;
hardwired support for lines, arc/circles,
rectangles, and graphics characters; 1024xl024
pixel display with four planes
500 ns/dot
Ceramic DIP
40
Graphics Display
Controller
CMOS 7220A with 2M video memory; dual-port
RAM control; write-masking on any bit;
enhanced external sync
500 ns/dot
DIP
QFP
40
52
72120
Advanced Graphics
Display Controller
High-speed graphics operations including paint,
area fill, slant, arbitrary angle rotate, up to 16x
enlargement and reduction; dua~port RAM
control; CMOS
500 ns/dot
PLCC
OFP
84
94
72123
Advanced Graphics
Display Controller II
Enhanced 72120; expanded command set;
improved painting performance; laser printer
interface controls; CMOS
400 nsldot
PLCC
QFP
84
94
Name
Description
7220A
High-Performance
Graphics Display
Controller
72020
Advanced Compression/Expansion Engine
Device,
,.PD
Name
Description
Package t
Pins
72185
Advanced Compression/
Expansion Engine
(ACE E)
High-speed CCITT Group 3/4 bit-map image compression/expansion
(A4 test chart, 400 PPI x 400 LPI in under 1 second); 32K-pixelline
length; 32-megabyte image memory; on-chip DMA and refresh timing
generator; CMOS
SDIP
PLCC
QFP
64
68
80
72186
High-Speed Advanced
Compression/Expansion
Engine
High-speed upgrade of 72185 (A4 test chart, 400 PPI x 400 LPI in 0.5
second average); software compatible with 72185; separate image
address and data buses
QFP
100
t Plastic unless ceramic (or cerdip) is specified.
1-11
t-fEC
Intelligent Peripheral Devices (IPD)
Floppy-Disk Controllers
Device,
Maximum
Transfer
Rate
"PO
Name
Description
Package t
Pins
765A/B
Floppy-Disk Controller
Industry-standard controller supporting IBM
3740 and IBM System 34 double-density
format; enhanced 765B supports multitasking
applications
500 kb/s
DIP
40
72064
Floppy-Disk Controller
CMOS; all features of 72068 with complete AT
register set and 48-mA drivers. Pin compatible
with WD 37C65/A/B but with higher
performance DPLL and reliable multitasking
operation
500 kb/s
PLCC
QFP
44
52
72065i65B
CMOS Floppy-Disk Controller
100% 765A/B microcode compatible;
compatible with 80ax microprocessor families
500 kb/s
DIP
PLCC
QFP
40
44
52
72070
High-Capacity Universal
Floppy-Disk Controller (UFDC)
Single-chip FDC solution for high-capacity
FODs of various types, conventional FDDs;
DPLL; 1.25 Mb/s data rate; perpendicular
recording format
24 MHz
QFP
64
SCSI Controllers
Device,
"PO
Maximum
Read/Write
Clock
Name
Description
Packaget
Pins
72111
Small Computer System
Interface (SCSI)
Controller
Selectable a/16-bit data bus width; 16 high-level
commands for reduced CPU load; singlecommand automatic execution; 4-Mb sync/
async; CMOS
16 MHz
SDIP
PLCC
QFP
64
68
74
72611
Small Computer System
Interface-2 (SCSI-2)
Controller
8/16/32-blt host data bus; supports fast SCSI,
command queuing, single and automatic
execution
20 MHz
QFP
100
t Plastic unless ceramic (or cerdip) is specified.
1-12
ftlEC
DSP and Speech Products
Digital Signal Processors
Device,
"PO
Description
Instruction
Cycle (ns)
Instruction
ROM (Bits)
Data ROM
(Bits)
Data RAM
(Bits)
Package
772fJA
16-bit fixed point DSP; NMOS
240
512 x 23
510x 13
128x 16
DIP
28
77C20A
16-bit fixed-point DSP; CMOS
244
512 x 23
510 x 13
128x 16
DIP
PLCC
SOP
PLCC
28
28
32
44
77P20
16-bit fixed-point DSP; NMOS
244
512 x 23
UVEPROM
510 x 13
UVEPROM
128x 16
Cerdip
28
77C25
16-blt fixed-point DSP; CMOS
122/100
2048 x 24
1024 x 16
256 x 16
DIP
SOP
PLCC
28
32
44
77P25
16-bit fixed-point DSP; CMOS
122/100
t
Pins
2048 x 24
OTPROM
1024 x 16
OTPROM
256 x 16
DIP
SOP
PLCC
28
32
44
2048 x 24
UVEPROM
1024 x 16
UVEPROM
256 x 16
Cerdip
28
77220
24-bit fixed-point DSP; CMOS
122/100
2048 x 32
1024 x 24
512 x 24
Ceramic PGA
PLCC
68
68
77P220L
24-bit fixed-point DSP; CMOS
122/100
2048 x 32
OTPROM
1024 x 24
OTPROM
512 x 24
PLCC
68
77P220R
24-bit fixed-point DSP; CMOS
122/100
2048 x 32
UVEPROM
1024 x 24
UVEPROM
512 x 24
Ceramic PGA
68
77230AR
32-bit floating-point DSP; CMOS
150
2048 x 32
1024 x 32
1024 x 32
Ceramic PGA
68
77230AR-003
32-bit floating-point DSP; CMOS;
standard library software
150
nla
nla
nla
Ceramic PGA
68
77P230R
32-bit floating-point DSP; CMOS
150
2048 x 32
UVEPROM
1024 x 32
UVEPROM
1024 x 32
Ceramic PGA
68
77240
32-bit floating-point DSP; CMOS
90
64Kx 32
external
nla
16M x 32
external
Ceramic PGA
132
77810
16-bit fixed-point modem DSP;
CMOS
181
2048 x 24
1024 x 16
256 x 16
Ceramic PGA
PLCC
68
68
7281
Image pipelined processor; NMOS
5-MHz clock
nla
nla
512 x 18
Ceramic DIP
40
9305
Support device for IIPD7281
processors; CMOS
10-MHz clock
nla
nla
nla
Ceramic PGA
132
t Plastic unless ceramic (or cerdip) is specified,·
1-13
•
I
I
!
NEe
DSP and Speech Products
Speech Processors
Name
Technology
Bit Rate
(kb/s)
Packaget
Pins
77C30
ADPCM Speech Encoder/Decoder
NMOS
32, 24
DIP
PLCC
28
44
7755
ADPCM Speech Processor
CMOS
10-32
96K
DIP
SOP
18
24
7756
ADPCM Speech Processor
CMOS
10-32
256K
DIP
SOP
18
24
77P56
ADPCM Speech Processor
CMOS
10-32
256K
OTPROM
DIP
SOP
20
24
7757
ADPCM Speech Processor
CMOS
10-32
512K
DIP
SOP
18
24
7758
ADPCM Speech Processor
CMOS
10-32
1M
DIP
SOP
18
24
7759
ADPCM Speech Processor
CMOS
10-32
1024K
External RAM
DIP
QFP
40
52
77501
ADPCM Record and Playback Speech Processor
CMOS
12,18,24
16M DRAM
1M SRAM
External RAM
QFP
80
77522
ADPCM Codec
CMOS
32
SOP
28
Device,
"PO
t Plastic unless ceramic (or cerdip) is specified.
1-14
Data ROM
(Bits)
ftIEC
Development Tools for Micro Products
V-Series Microprocessors
Device
(Note 1)
Full
Emulator
Full
Emulator
Probe
Relocatable
Assembler
(Note 11)
C Compiler
(Note 12)
/1PD70136GJ-12
IE-70136A016
DDK-70136
RA70136
CC70136
/1PD70136GJ-16
EP-70136L-PC
(Note 2)
DDK-70136
RA70136
CC70136
IE-70136-PC
EP-70136L-PC
DDK-70136
RA70136
CC70136
EP-70136L-A,
IE-70136-PC
EP-70136L-PC
DDK-70136
RA70136
CC70136
IE-70136A016
EP-70136L-A
(Note 3)
IE-70136-PC
EP-70136L-PC
(Note 3)
DDK-70136
RA70136
CC70136
pPD70136R-16
IE-70136A016
EP-70136L-A
(Note 3)
IE-70136-PC
EP-70136L-PC
(Note 3)
DDK-70136
RA70136
CC70136
pPD7020BGF-B
IE-7020BA010
EB-V40MINIIE
EB-7020B
RA70116
CC70116
/1PD7020BGF-10
IE-7020BA010
EB-V40MINIIE
EB-7020B
RA70116
CC70116
/1PD7020BL-B
IE-7020BA010
IE-70000295B
EB-V40MINIIE
ADAPT6BPGA
6BPLCC
(Note 4)
EB-70208
RA70116
CC70116
/1PD7020BL-10
IE-7020BA010
IE-70000295B
EB-V40MINIIE
ADAPT6BPGA
6BPLCC
(Note 4)
EB-7020B
RA70116
CC70116
pPD7020BR-B
IE-702OBA010
IE-700002959
EB-V40MINIIE
(Note 4)
EB-7020B
RA70116
CC70116
pPD7020BR-10
IE-7020BA010
IE-700002959
EB-V40MINIIE
(Note 4)
EB-7020B
RA70116
CC70116
/1PD70216GF-B
IE-70216A010
EP-7032OJ
EB-V50MINIIE
EB70216
RA70116
CC70116
/1PD70216GF-10
IE-70216A010
EP-70320J
EB-V50MINIIE
EB70216
RA70116
CC70116
pPD70216L-B
IE-70216A010
IE-70000295B
EB-V50MINIIE
ADAPT6BPGA
6BPLCC
(Note 4)
EB70216
RA70116
CC70116
pPD70216L-10
IE-70216A010
IE-700002958
EB-V50MINIIE
ADAPT6BPGA
6BPLCC
(Note 4)
EB70216
RA70116
CC70116
pPD70216R-B
IE-70216A010
IE-700002959
EB-V50MINIIE
(Note 4)
EB70216
RA70116
CC70116
pPD70216R-10
IE-70216A010
IE-700002959
EB-V50MINIIE
(Note 4)
EB70216
RA70116
CC70116
/1PD70236GD-10
IE-70236-BX
EV-9500GD120
(Note 16)
DDK-70236
RA70136
CC70136
pPD70236GD-12
IE-70236-BX
EV-9500GD120
(Note 16)
DDK-70236
RA70136
CC70136
pPD70236GD-16
IE-70236-BX
EV-9500GD120
(Note 16)
DDK-70236
RA70136
CC70136
Mini-IE
Emulator
Mini-IE
Probe
Evaluation
Boards
EP-70136L-A
(Note 2)
IE-70136-PC
EP-70136L-PC
(Note 2)
IE-70136A016
EP-70136L-A
(Note 2)
IE-70136-PC
/1PD70136L-16
IE-70136A016
EP-70136L-A
/1PD70136L-12
IE-70136A016
/1PD70136R-12
EPROM
Device
1-15
ftt{EC
Development Tools for Micro Products
V-Series Microprocessors (cont)
Relocatable
Assembler
(Note 11)
Full
Emulator
Full
Emulator
Probe
IlPD70236R·10
IE·70236·BX
(Note 15)
DDK·70236
RA70136
CC70136
IlPD70236R-12
IE·70236-BX
(Note 15)
00K-70236
RA70136
CC70136
Device
(Note 1)
Minl·IE
Emulator
Mlnl·IE
Probe
Evaluation
Boards
EPROM
Device
C Complier
(Note 12)
IlPD70236R·16
IE·70236·BX
(Note 15)
DDK-70236
RA70136
CC70136
IlPD70320GJ
IE-70320A006
EP·70320GJ
(Note 5)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK·70320
RA70320
CC70116
IlPD70320GJ·B
IE·70320·
ADOB
EP-70320GJ
(Note 5)
EB·V25MINIIE-P
EP-70320GJ
(Note 6)
DDK-7032O
RA70320
CC70116
IlPD70320L
IE-70320A006
EP·70320L
EB·V25MINIIE-P
(Note 7)
DDK-7032O
RA70320
CC70116
IlP070320L·B
IE·70320·
AOOB
EP-70320L
EB·V25MINI·
IE-P
(Note 7)
DDK-70320
RA70320
CC70116
IlPD70322GJ
IE·70320A006
EV·9500GJ·
94
(Note 14)
EB·V25MINIIE-P
EP-70320GJ
(Note 6)
DDK·7032O
RA70320
CC70116
IlPD70322GJ·B
IE·70320AOOB
EP-70320GJ
EB·V25MINI·
IE-P
EP-70320GJ
DDK-70320
RA70320
CC70116
IlPD70322L
IE-70320A006
(Note 13)
EB-V25MINIIE-P
(Note 7)
DDK-70320
70P322K
(Note 10)
RA70320
CC70116
IlPD70322L-B
IE-70320AOOB
(Note 13)
EB-V25MINIIE-P
(Note 7)
DDK-70320
70P322K
(Note 10)
RA70320
CC70116
IlPD70325GJ·B
IE·70325-BX
EV-9500GJ-
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DOK·70325
RA70320
CC70116
94
(Note 14)
IlP070325GJ·1Q
IE-70325-BX
(Note B)
EV-9500GJ94
(Note 14)
EB-V25MINIIE-P
EP-7032OGJ
(Note 6)
DOK-70325
RA70320
CC70116
IlPD70325L·B
IE·70325-BX
(Note 13)
EB-V25MjNI,
IE-P
EP-70320GJ
(Note 6)
DDK-70325
RA70320
CC70116
IlPD70325L-10
IE-70325-BX
(Note B)
(Note 13)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK-70325
RA70320
CC70116
IlPD70327GJ·B
(Note 9)
IE-70320·
ADOB
EP-70320GJ
(Note 5)
EB·V25MINIIE-P
EP-70320GJ
(Note 6)
RA70320
CC70116
IlP070327L-B
(Note 9)
IE-70230ADOB
EP-70320L
EB-V25MINIIE-P
(Note 7)
RA70320
CC70116
IlPD70330GJ·B
IE-70330ADOB
EP-70320GJ
(Note 5)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
DDK·70330
RA70320
CC70116
IlPD70330L·B
IE·70330AOOB
EP·70320L
EB-V35MINIIE-P
(Note 7)
ODK-70330
RA70320
CC70116
IlPD70332GJ·B
IE-70SS0A006
EP-7032OGJ
(Note 5)
EB-V35MINIIE·P
EP·70320GJ
(Note 6)
ODK·70330
RA70320
CC70116
IlPD70332L-B
IE·70330A006
EP-70320L
EB-V35MINIIE·P
(Note 7)
DDK-70330
RA70320
CC70116
IlPD70335GJ·B
IE·70335-BX
EV·9500GJ·
94
(Note 14)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
1-16
70P322K
(Note 10)
ttiEC
Development Tools for Micro Products
V-Series Microprocessors (cont)
Device
(Note 1)
Full
Emulator
IlPD70335GJ-l0
IE-70335-BX
(Note 8)EV9500GJ-94
(Note 14)
IlPD70335L-8
Full
Emulator
Probe
Relocatable
Assembler
(Note 11)
C Compiler
(Note 12)
DDK-70330
RA70320
CC70116
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
EP-70320GJ
(Note 5)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
RA70320
CC70116
EP-70320L
EB-V35MINIIE-P
(Note 7)
RA70320
CC70116
Mini-IE
Emulator
Mini-IE
Probe
Evaluation
Boards
EV-9500GJ94
(Note 14)
EP-V35MINIIE-P
EP-70320GJ
(Note 6)
IE-70335-BX
(Note 13)
EB-V35MINIIE-P
IlPD70335L-l0
IE-70335-BX
(Note 8)
(Note 13)
IlPD70337GJ-8
(Note 9)
IE-70330A008
IlPD70337L-8
(Note 9)
IE-70330A008
EPROM
Device
Notes:
(1) Packages:
GF
GJ
K
L
R
80-pin
74-pin
84-pin
68-pin
68-pin
plastic QFP
or 94-pin plastic QFP
ceramic LCC with window
or 84-pin plastic LCC
PGA
(2) The EP-70136GL-A and EP-70136L-PC contain both a 68-pin
PLCC probe and an adapter which converts the 68-pin PLCC
probes to a 74-pin QFP footprint.
(3) 68-pin PGA parts are supported by using the EP-70136L-A
PLCC probe or EP-70136L-PC PLCC probe, plus a PLCC socket
with a PGA-pinout. A PLCC socket of this type is supplied with
the EP-70136L-A.
(4) The EB-V40 MINI-IE and EB-V50 MINI-IE support PGA packages
directly; the ADAPT68PGA68PLCC adapter converts the PGApinout on the MINI-IE to a PLCC footprint. This adapter is
supplied with the MINI-IE.
(5) The EP-70320GJ is an adapter to the EP-70320L, which converts
84-pin PLCC probes to a 94-pin QFP footprint. For GJ parts, both
the PLCC probe and the adapter are needed.
(6) The EP-70320GJ adapter oan be used to convert the supplied
84-pin PLCC oable of the EB-V25 MINI-IE-P or EB-V35 MINI-IE-P
to a 94-pin QFP.
(7) The EB-V25 MINI-IE-P and EB-V35 MINI-IE-P are supplied with an
84-pin PLCC cable.
(8) Contaotyour looal NEC Sales Offioe forthe latest information on
10-MHz emulation.
(9) Development for the IlPD70327 or IlPD70337 oan be done using
the appropriate IlPD70320 or IlPD70330 tools; however, debugging the programs in the Software Guard mode is not supported
at this time.
(11) The following relocatable assemblers are available:
RA70116-D52
For V20®{V30®/
(MS-DOSI!!J
RA70116-VVT1
V40'M{V50'·
(VAX®{VMSI!!J
RA70116-VXTl
(VAX/UNIX®4.2 BSD or
Ultrix'M)
RA70136-D52
(MS-DOS)
RA70136-VVTl
(VAX/VMS)
RA70136-VXT1
(VAX/UNIX 4.2 BSD or
Ultrix)
RA70320-D52
(MS-DOS)
RA70320-VVTl
(VAX/VMS)
(VAX/UNIX 4.2 BSD or
RA70320-VXTl
Ultrix)
(12) The following C oompilers are available:
(MS-DOS)
CC70116-D52
For V20®{V30®/
CC70116-VVTl V40'·{V50~
(VAX/VMS)
CC70116-VXTl
(VAX/UNIX 4.2 BSD or
Ultrix)
For V33~{V53'M
CC70136-D52
(MS-DOS)
CC70136-VVTl
(VAX/VMS)
CC70136-VXTl
(VAX/UNIX 4.2 BSD or
Ultrix)
(13) 84-pin PLCC probe shipped with IE-70325-BX and IE-70335-BX.
(14) The EV-9500GJ-94 is an adapter that converts the 84-pin PLCC
probe to a 94-pin QFP. Target sockets must also be purchased to
mate to this adapter. Target sookets are sold in paoks of five as
part number EV-92006-94x5.
(15) The IE-70236-BX is shipped with the 132-pin PGA probe.
(16) The EV-9500GD-120 is an adapter that converts the 132-pin PGA
probe to a 120-pin QFP. Target sockets must also be purchased
to mate to this adapter. Target sookets are sold in paoks of five as
part number EV-9200GD-120.
(10) The IlPD70P322K EPROM device can be used for bothllPD70322
and IlPD70332 emulation. The IlPD70P322K EPROM device can
be programmed by using the PA-70P322L Programming Adapter
and the PG-1500 EPROM Programmer.
1-17
ttlEC
Development Tools for Micro Products
75xx Series Sing Ie-Chip Microcomputers
Device (Note 1)
Emulator·
Add·on Board·
System
Evaluation
Board
JlPD7502AGF·3B8
EVAKIT·7500B
EV·7514
SE·7514·A
JlPD7503AGF·3B8
EVAKIT·7500B
EV·7514
SE·7514·A
JlPD7507BCU
EVAKIT·7500B
ASM75
JlPD7507BGB-3B4
EVAKIT·7500B
ASM75
JlPD750BBCU
EVAKIT·7500B
ASM75
JlPD750BBGB·3B4
EVAKIT·7500B
JlPD7533C
EVAKIT·7500B
EV·7533
JlPD7533CU
EVAKIT·7500B
EV·7533
ASM75
JlPD7533G·22
EVAKlT·7500B
EV·7533
ASM75
JlPD75CG33E
EVAKIT·7500B
EV·7533
JlPD7554CS
EVAKIT·7500B
EV·7554A
SE·7554·A
,.,PD75P54CS
PA·75P54CS
ASM75
JlPD7554G
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P54G
PA·75P54CS
ASM75
JlPD7554ACS
EVAKIT·7500B
EV·7554A
SE·7554·A
JlP D75P54CS
PA·75P54CS
ASM75
JlPD7554AG
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P54G
PA·75P54CS
ASM75
JlPD75P54CS
EVAKlT·7500B
EV·7554A
JlPD75P54G
EVAKIT·7500B
EV·7554A
JlPD7556CS
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P56CS
PA·75P56CS
ASM75
JlPD7556G
EVAKlT·7500B
EV·7554A
SE·7554·A
JlPD75P56G
PA·75P56CS
ASM75
JlPD7556ACS
EVAKlT·7500B
EV·7554A
SE·7554·A
JlP D75P56CS
PA·75P56CS
ASM75
JlPD7556AG
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P56G
PA·75P56CS
ASM75
JlPD75P56CS
EVAKlT·7500B
EV·7554A
JlPD75P56G
EVAKIT·7500B
EV·7554A
JlPD7564CS
EVAKlT·7500B
EV·7554A
SE·7554·A
JlPD75P64CS
PA·75P54CS
ASM75
JlPD7564G
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P64G
PA·75P54CS
ASM75
JlPD7564ACS
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P64CS
PA·75P54CS
ASM75
JlPD7564AG
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P64G
PA·75P54CS
ASM75
JlPD75P64CS
EVAKIT·7500B
EV·7554A
JlPD75P64G
EVAKIT·7500B
EV·7554A
JlPD7566CS
EVAKIT·7500B
EV·7554A
SE·7554·A
JlP D75P66CS
PA·75P56CS
ASM75
JlPD7566G
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P66G
PA·75P56CS
ASM75
JlPD7566ACS
EVAKIT·7500B
EV·7554A
SE·7554·A
JlP D75P66CS
PA·75P56CS
ASM75
JlPD7566AG
EVAKIT·7500B
EV·7554A
SE·7554·A
JlPD75P66G
PA·75P56CS
ASM75
1·18
EPROM/OTP
Device
PG·1500
Adapter
(Note 2)
Absolute
Assembler
(Note 3)
ASM75
ASM75
ASM75
JlPD75CG33E
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
NEe
Development Tools for Micro Products
75xx Series Single-Chip Microcomputers (cont)
Syatem
Evaluation
Board
EPROM/OTP
Device
PG-1500
Adapter
(Note 2)
Absolute
Assembler
(Note 3)
Device (Note 1)
Emulator·
Add-on Board·
JlPD75P66CS
EVAKIT-7500B
EV-7554A
ASM75
JlPD75P66G
EVAKIT-7500B
EV-7554A
ASM75
Notes:
(1) Packages:
C
CS
CU
E
G
G-22
GB-3B4
GF-3B8
42-pin plastic DIP C/lPD7533)
20-pin plastic shrink DIP
C/lPD7554/54A!P54/64/64A!P64)
24-pin plastic shrink DIP
C/lPD7556/56A/P56/66/66A/P66)
40-pin plastic shrink DIP C/lPD7507B/08B)
42-pln plastic shrink DIP C/lPD7533)
42-pin ceramic piggy-back DIP C/lPD7533)
20-pin plastic SO C/lPD7554/54A!P54/64/64A!P64)
24-pin plastic SO C/lPD7556/56A!P56/66/66A/P66)
44-pin plastic OFP (1.45 mm thick)
44-pin plastic OFP (2.7 mm thick)
64-pin plastic OFP (2.7 mm thick)
(2) By using the specified adapter, the PG-1500 EPROM programmer
can be used to program the OTP device.
(3) The ASM75 Absolute Assembler is provided to run under the
MS-DOS® operating system. (ASM75·D52).
1·19
NEe
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers
Device (Note 5)
Emulator*
pPD75004CU
IE-75000-R
EP-75008CU-R
pPD75004GB-3B4
IE-75000-R
EP-7500SGB-R
pPD75006CU
IE-75000-R
EP-7500SCU-R
pPD75006G B-3B4
IE-75000-R
EP-7500SGB-R
pPD7500SCU
IE-75000-R
EP-7500SCU-R
pPD7500SG B-3B4
IE-75000-R
EP-7500SGB-R
IE-75000-R
EP-75008CU-R
pPD75POO8CU
Emulation Probe*
pPD75POO8GB
IE-75000-R
EP-75008GB-R
pPD75028CW
IE-75000-R
EP-75028CW-R
pPD75028GC-AB8
IE-75000-R
EP-7502SGC-R
pPD75P036CW
IE-75000-R
EP-7502SCW-R
Optional Socket
Adapter (Note 1)
EV-9200G-44
EV-9200G-44
EV-9200G-44
EPROM/OTP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
pPD75POOSCU
RA75X
ST75X
pPD75POOSGB
RA75X
ST75X
pPD75POOSCU
RA75X
ST75X
pPD75POOSGB
RA75X
ST75X
pPD75POOSCU
RA75X
ST75X
pPD75POOSGB
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
pPD75P036CW
RA75X
ST75X
pPD75P036GC
RA75X
ST75X
RA75X
ST75X
EV-9200G-44
EV-9200GC-64
RA75X
ST75X
pPD75P048CW
RA75X
ST75X
pPD75P048GC
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
pPD75P10SCW/
DW/BCW
pPD75P116CW
RA75X
ST75X
EV-9200G-64
pPD75P10SG
pPD75P116GF
RA75X
ST75X
EP-7510SGF-R
EV-9200G-64
pPD75P10SG/BGF
pPD75P116GF
RA75X
ST75X
IE-75000-R
EP-75108AGC-R
EV-9200GC-64
IE-75000-R
EP-75108CW-R
pPD75106G-1 B
IE-75000-R
EP-7510SGF-R
pPD75106GF-3BE
E-75000-R
EP-7510SGF-R
pPD7510SCW
IE-75000-R
EP-75108CW-R
pPD7510SG-1 B
IE-75000-R
EP-75108GF-R
pPD7510SGF-3BE
IE-75000-R
pPD7510SAG-22
pPD7510SAGC-ABS
pPD7510SFGF-3BE
pPD75P036GC-AB8
IE-75000-R
EP-75028GC-R
pPD75048CW
IE-75000-R
EP-7502SCW-R
pPD7504SGC-AB8
IE-75000-R
EP-7502SGC-R
pPD75P048CW
IE-75000-R
EP-75028CW-R
pPD75P048GC-AB8
IE-75000-R
EP-7502SGC-R
pPD75104CW
IE-75000-R
EP-75108CW-R
pPD75104G-1 B
IE-75000-R
EP-7510SGF-R
pPD75104GF-3BE
IE-75000-R
pPD75104AGC-ABS
pPD75106CW
EV-9200GC-64
EV-9200GC-64
RA75X
ST75X
pPD75P10SCW/
DW/BCW
pPD75P116CW
RA75X
ST75X
EV-9200G-64
pPD75P10SG
pPD75P116GF
RA75X
ST75X
EV-9200G-64
pPD75P108G/BGF
pPD75P116GF
RA75X
ST75X
pPD75P10SCW/
DW/BCW
pPD75P116CW
RA75X
ST75X
EV-9200G-64
pPD75P10SG
pPD75P116GF
RA75X
ST75X
EP-7510SGF-R
EV-9200G-64
pPD75P10SG/BGF
pPD75P116GF
RA75X
ST75X
IE-75000-R
EP-75108AGC-R
EV-9200GC-64
RA75X
ST75X
IE-75000-R
EP-75108AGC-R
EV-9200GC-64
RA75X
ST75X
IE-7500-R
EP-75108GF-R
EV-9200G-64
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
pPD75P108BCW
IE-75000-R
EP-7510SCW-R
pPD75P108BGF
IE-75000-R
EP-75108GF-R
1-20
EV-9200GC-64
EV-9200G-64
pPD75P10SBGF
pPD75P116GF
NEe
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers (cont)
Emulation Probe*
Optional Socket
Adapter (Note 1)
EPROM/OTP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
Device (Note 5)
Emulator*
/lPD75P10BCW
IE-75000-R
EP-7510BCW-R
RA75X
ST75X
/lPD75P10BDW
IE-75000-R
EP-7510BCW-R
RA75X
ST75X
/lPD75P10BG-1 B
IE-75000-R
EP-7510BGF-R
RA75X
ST75X
/lPD75112CW
IE-75000-R
EP-7510BCW-R
/lPD75P116CW
RA75X
ST75X
/lPD75112GF-3BE
IE-75000-R
EP-7510BGF-R
EV-9200G-64
/lPD75P116GF
RA75X
ST75X
/lPD75112FGF-3BE
IE-75000-R
EP-7510BGF-R
EV-9200G-64
/lPD75P116GF
RA75X
ST75X
/lPD75116CW
IE-75000-R
EP-7510BCW-R
/lPD75P116CW
RA75X
ST75X
/lPD75116GF-3BE
IE-75000-R
EP-7510BGF-R
EV-9200G-64
/lPD75P116GF
RA75X
ST75X
/lPD75116FGF-3BE
IE-75000-R
EP-75108GF-R
EV-9200G-64
/lPD75P116GF
RA75X
ST75X
/lPD75P116CW
IE-75000-R
EP-7510BCW-R
RA75X
ST75X
/lPD75P116GF
IE-75000-R
EP-7510BGF-R
EV-9200G-64
/lPD75116HGC-ABB
IE-75000-R
EP-7510BAGC-R
EV-9200GC-64
/lPD75117HGC-ABB
IE-75000-R
EP-7510BAGC-R
EV-9200GC-64
/lPD75P117HGC-ABB
IE-75000-R
EP-7510BAGC-R
EV-9200GC-64
/lPD75206CW
IE-75000-R
EP-75216ACW-R
/lPD75206G-1B
IE-75000-R
EP-75216AGF-R
/lPD75206GF-3BE
IE-75000-R
EP-75216AGF-R
/lPD7520BCW
IE-75000-R
EP-75216ACW-R
EV-9200G-64
RA75X
ST75X
/lPD75P117HGC
RA75X
ST75X
/lPD75P117HGC
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
EV-9200G-64
RA75X
ST75X
EV-9200G-64
RA75X
ST75X
RA75X
ST75X
/lPD75P216ACW
/lPD75P216ACW
/lPD7520BG-1 B
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
ST75X
/lPD75208GF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
ST75X
/lPD75212ACW
IE-75000-R
EP-75216ACW-R
RA75X
ST75X
/lPD75212AGF-3BE
IE-75000-R
EP-75216AGF-R
RA75X
ST75X
/lPD75216ACW
IE-75000-R
EP-75216ACW-R
RA75X
ST75X
/lPD75216AGF
IE-75000-R
EP-75216AGF-R
RA75X
ST75X
/lPD75P216ACW
IE-75000-R
EP-75216ACW-R
/lPD75P216ACW
RA75X
ST75X
/lPD75217CW
IE-75000-R
EP-75216ACW-R
/lPD75P21BCW
RA75X
ST75X
/lPD75217GF-3BE
IE-75000-R
EP-75216AGF-R
/lPD75P21BGF/KB
RA75X
ST75X
/lPD7521BCW
IE-75000-R
EP-75216ACW-R
/lPD75P21BCW
RA75X
ST75X
/lPD7521BGF-3BE
IE-75000-R
EP-75216AGF-R
/lPD75P21BGF/KB
RA75X
ST75X
/lPD75P21BCW
IE-75000-R
EP-75216ACW-R
RA75X
ST75X
/lPD75P21BGF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
ST75X
/lPD75P21BKB
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
ST75X
/lPD75236GJ-5BG
IE-75000-R
EP-7523BGJ-R
EV -9200G-94
/lPD75P23BGJ/KF
RA75X
ST75X
/lPD75237GJ-5BG
IE-75000-R
EP-7523BGJ-R
EV-9200G-94
/lPD75P23BGJ/KF
RA75X
ST75X
/lPD7523BGJ-5BG
IE-75000-R
EP-7523BGJ-R
EV-9200G-94
/lPD75P23BGJ/KF
RA75X
ST75X
/lPD75P23BGJ-5BG
IE-75000-R
EP-7523BGJ-R
EV-9200G-94
RA75X
ST75X
/lPD75P238KF
IE-75000-R
EP-7523BGJ-R
EV-9200G-94
RA75X
ST75X
/lPD7526BCW
IE-75000-R
EP-75216ACW-R
RA75X
ST75X
/lPD7526BGF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
ST75X
/lPD75304GF-3B9
IE-75000-R
EP-7530BGF-R
EV-9200G-BO
RA75X
ST75X
/lPD75P216ACW
EV-9200G-64
/lPD75P216ACW
EV-9200G-64
EV-9200G-64
EV-9200G-64
/lPD75P216ACW
/lPD75P308GF/K
1-21
ftiEC
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers (cont)
EPROM/OTP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
Device (Note 5)
Emulator*
Emulation Probe*
Optional Socket
Adapter (Note 1)
JlPD75306GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPD75P308GF/K
RA75X
ST75X
JlPD75308GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPD75P308GF/K
RA75X
ST75X
JlPD75308BGF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPDP316AGF/AK
RA75X
ST75X
JlPD75P308GF
iE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
JlPD75P308K
IE-75000-R
EP-75308GF-R
EV-9200G-60
RA75X
ST75X
JlPD75312GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-60
JlPD75P316GFI
AGF/AK
RA75X
ST75X
JlPD75316GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-60
JlPD75P316GFI
AGF/AK
RA75X
ST75X
JlPD75P316GF
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
JlPD75P316AGF
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
JlPD75P316AK
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
JlPD75328GC-3B9
IE-75000-R
EP-75328GC-R
EV-9200GC-80
RA75X
ST75X
JlPD75P328GC-3B9
IE-75000-R
EP-75328GC-R
EV-9200GC-80
RA75X
ST75X
JlPD75336GC-389
IE-75000-R
EP-75336GC-R
EV-9200GC-80
RA75X
ST75X
JlPD75P336GC-3B9
IE-75000-R
EP-75336GC-R
EV-9200GC-60
RA75X
ST75X
JlPD75348GF-3BA
IE-75001-R
EP-75617GF-R
EV-9200G-100
JlPD75P618GF
RA75X
ST75X
JlPD75352GF-3BA
IE-75001-R
EP-75617GF-R
EV-9200G-l00
JlPD75P618G F
RA75X
ST75X
JlPD75402AC
IE-75000-R
EP-75402C-R
JlPD75P402C
RA75X
ST75X
JlPD75402ACT
IE-75000-R
EP-75402C-R
JlPD75P402CT
RA75X
ST75X
JlPD75402AGB-3B4
IE-75000-R
EP-75402GB-R
JlPD75P402GB
RA75X
ST75X
JlPD75P402C
IE-75000-R
EP-75402C-R
RA75X
ST75X
JlPD75P402CT
IE-75000-R
EP-75402C-R
RA75X
ST75X
JlPD75P402GB-3B4
IE-75000-R
EP_75402GB-R
EV-9200G-44
RA75X
ST75X
JlPD75512GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-80
JlPD75P516GF/K
RA75X
ST75X
JlPD75516GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-80
JlPD75P516GF/K
RA75X
ST75X
JlPD75P516GF
IE-75000-R
EP-75516GF-R
EV-9200G-80
RA75X
ST75X
JlPD75P516K
IE-75000-R
EP-75516GF-R
EV-9200G-80
JlPD75517GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-80
JlPD75P518GF/K
RA75X
ST75X
JlPD75518GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-60
JlPD75P51BGF/K
RA75X
ST75X
JlPD75P518GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-BO
RA75X
ST75X
JlPD75P51BK
IE-75000-R
EP-75516GF-R
EV-9200G-80
RA75X
ST75X
1-22
EV-9200G-44
JlPD75P328GC
JlPD75P336GC
NEe
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers (cant)
EPROM/OTP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
Device (Note 5)
Emulator'
Emulation Probe'
Optional Socket
Adapter (Note 1)
pPD75616GF-3BA
IE-75001-R
EP-75617GF-R
EV-9200G-l00
pPD75P61SGF
RA75X
S175X
pPD75617GF-3BA
IE-75001-R
EP-75617GF-R
EV-9200G-l00
pPD75P61SGF
RA75X
S175X
pPD75P61SGF-3BA
IE-75001-R
EP-75617GF-R
EV-9200G-l00
RA75X
S175X
Notes:
(1) The EV-9200G-XX is an LCC socket with the footprint of the flat
package. One unit is supp lied with the probe. Additional units
are available as replacement parts in sets of five.
(2) All EPROM/OTP devices can be programmed using the NEC
PG-1500. Refer to the PG-1500 Programming Socket Adapter
Selection Gu ide for the appropriate socket adapter.
(3) The RA75X relocatable assembler package is provided for the
following operating system:
RA75X-D52 (MS-DOS,",
(4) The S175X structured assembler preprocessor is provided with
RA75X.
(5) Packages:
C
2S-pin plastic DIP
CT
2S-pin plastic shrink DIP
CU
42-pin plastic shrink DIP
CW
64-pin plastic shrink DIP
DW
64-pin ceramic shrink DIP with window
G-l B
64-pin plastic QFP (2.05 mm thick)
G-22
64-pin plastic QFP (1.55 mm thick)
GB-3B4
44-pin plastic QFP
GC-ABS
64-pin plastic QFP (2.55 mm thick)
GC-3B9
SO-pin plastic QFP
GF-3BA
100-pin plastic QFP
GF-3BE
64-pin plastic QFP (2.77 mm thick)
SO-pin plastic QFP
GF-3B9
GJ-5BGK 94-pin plastic QFP
KB
64-pin ceramic LCC
KF
94-pin ceramic LCC
• Required tools.
1-23
NEe
Development Tools for Micro Products
78xx Series Sing Ie-Chip Microcomputers
Device (Note 1)
t
Relocatable
Assembler
(Note 8)
C Complier
(Note 8)
Emulator"
Emulation Probe"
IE-78Cl1-M
EV-9001-64
(Note 3)
RA87
CC87
j1PD78Cl0AGQ36
IE-78Cll-M
(Note 4)
RA87
CC87
j1PD7BC10AGF
IE-78Cll-M
(Note 5)
RA87
CC87
j1PD7BC10AL
IE-78Cll-M
(Note 7)
RA87
CC87
j1PD78CllACW
IE-78Cll-M
EV-9001 -64
(Note 3)
j1PD78CP14CW/DW
(Note 6)
PA-78CP14CW
RA87
CC87
j1PD78CllAGQ-36
IE-78Cl1-M
(Note 4)
j1PD78CP14G36/R
(Note 6)
PA-78CP14GQ
RA87
CC87
j1PD78Cl1AGF-3BE
IE-78Cl1-M
(Note 5)
j1PD7BCP14GF
(Note 6)
PA-78CP14GF
RA87
eC87
j1PD78CllAL
IE-78Cl1-M
(Note 7)
j1PD78CP14L
(Note 6)
PA-78CP14L
RA87
eC87
j1PD78C12ACW
IE-78Cll-M
EV-9001-64
(Note 3)
j1PD78CP14CW/DW
(Note 6)
PA-78CP14CW
RA87
CC87
j1PD78C12AGQ
IE-78Cll-M
(Note 4)
j1PD78CP14G36/R
(Note 6)
PA-78CP14GQ
RA87
eC87
j1PD78C12AGF
IE-78Cll-M
(Note 5)
j1PD78CP14GF
(Note 6)
PA-78CP14GF
RA87
CC87
j1PD78C12AL
IE-78Cl1-M
(Note 7)
j1PD78CP14L
(Note 6)
PA-78CP14L
RA87
CCB7
j1PD78C14CW
IE-78Cll-M
EV-9001-64
(Note 3)
j1PD78CP14CW/DW
PA-78CP14CW
RA87
CC87
j1PD78C14G-36
IE-78Cl1-M
(Note 4)
j1PD78CP14G36/R
j1PD78CG14E
PA-78CP14GQ
RA87
CC87
j1PD7BC14G-l B
IE-78Cl1-M
(Note 5)
j1PD78CP14GF
PA-78CP14GF
RA87
CC87
j1PD78C14GF
IE-7BC11-M
(Note 5)
j1PD78CP14GF
PA-7BCP14GF
RAB7
CC87
j1PD78C14L
IE-78Cl1-M
(Note 7)
j1PD78CP14L
PA-7BCP14L
RAB7
CC87
j1PD78C14AG-ABB
IE-78Cl1-M
(Note 5)
j1PD78CP14CW
IE-78Cl1-M
EV-9001-64
(Note 3)
j1PD78CP14DW
IE-78Cl1-M
j1PD78Cl0ACW
EPROM/OlP Device
PG-1500
Adapter (Note 2)
RA87
eC87
PA-78CP14CW
RA87
CC87
EV-9001-64
(Note 3)
PA-7BCP14CW
RA87
CC87
j1PD7BCP14G36
IE-7BC11-M
(Note 4)
PA-78CP14GQ
RAB7
eCB7
j1PD78CP14GF
IE-78Cl1-M
(Note 5)
PA-78CP14GF
RAB7
Ce87
j1PD78CP14L
IE-78Cll-M
(Note 7)
PA-78CP14L
RA87
eC87
j1PD78CP14R
IE-78Cl1-M
(Note 4)
PA-78CP14GQ
RA87
eC87
j1PD78C17eW
IE-7BCll-M
EV-9001-64
(Note 3)
RA87
eC87
j1PD78C17GQ36
IE-78Cll-M
(Note 4)
RAB7
CC87
j1PD7BC17GF
IE-7BC11-M
(Note 5)
RAB7
eCB7
j1PD78C18eW
IE-?BC11-M
EV-9001-64
(Note 3)
j1PD78CP18CW
(Note 6)
PA-78CP14CW
RA8?
CC87
j1PD7BC18GQ
IE-78Cll-M
(Note 4)
j1PD78CP18GQ
(Note 6)
PA-7BCP14GQ
RA87
eCB7
1-24
NEe
Development Tools for Micro Products
78xx Series Single-Chip Microcomputers (cont)
Device (Note 1)
t
pPD78C18GF
Relocatable
Assembler
(Note 8)
C Compiler
(Note 8)
RA87
CC87
RA87
CC87
Emulator"
Emulation Probe"
EPROM/OTP Device
IE-78Cll-M
(Note 5)
pPD78CP18GF
(Note 6)
PA-78CPI4GF
pPD78CP18KB
(Note 6)
PA-78CPI4KB
IE-78Cll-M
pPD78CP18CW
PG-1S00
Adapter (Note 2)
EV-9001-64
(Note 3)
PA-78CPI4CW
pPD78CP18GQ
IE-78Cll-M
(Note 4)
PA-78CPI4GQ
RA87
CC87
pPD78CP18GF
IE-78Cll-M
(Note 5)
PA-78CPI4GF
RA87
CC87
pPD78CP18KB
IE-78Cl1-M
(Note 5)
PA-78CPI4KB
RA87
CC87
.,
" Requ ired tools
t For all pPD78Clx devices, you may use the DDK-78Cl0 for
evaluation purposes.
Notes:
(1) Packages:
CW
DW
G-l B
G-36
G-AB8
GF-3BE
GQ-36
KB
L
R
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
68-pin
64-pin
plastic shrink DIP
ceramic shrink DIP with window
plastic QFP (resin thickness 2.05 mm)
plastic QUIP
plastic QFP (interpin pitch 0.8 mm)
plastic QFP (resin thickness 2.7 mm)
plastic QUIP
ceramic LCC with window
PLCC
ceramic QUIP with window
(2) By using the specified adapter, the PG-1500 EPROM programmer
can be used to program the EPROM/OTP device.
(3) 64-pin shrink DIP adapter which plugs into the EP-7811 HGQ
emulation probe supplied with each IE.
(4) The emulation probe for the 64-pin QUIP package (EP-7811 HGQ)
is supplied with the IE.
(5) No emulation probe available.
(6) The pPD78CPI4/CPI8 EPROM/OTP devices do not have pull-up
resistors on ports A, B, and C.
(7) The optional AS-QIP-PCC-D781X QUIP-to-PLCC adapter can be
used with the EP-7811 HGQ emulation probe supplied with each
IE.
(8) The following relocatable assemblers and C compilers are available:
RA87-D52
(MS-DOS®)
Relocatable assemRA87-VVTl
01AX®NMS®)
biers for 78xx
series
CCMSD-15DD-87
CCMSD-15DD-87-16
CCVMS-OTI6-87
CCUNX-OTI6-87
(MS-DOS)
(MS-DOS;
extended memory)
01AXNMS)
01AX/UNIX®;
4.2 BSD or Ultrix'")
C Compilers
78xx Series
for
1-25
ttlEC
Development Tools for Micro Products
K2 (J£PD782xx) Series Single-Chip Microcomputers
Device
(Notes 1,2)
Evaluation Board
(Note 3)
Low-End
Emulator
Emulation
System
Emulation
Probe
(Note 4)
I1PD78212CW
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240CW-R
I1PD78212GC
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GC-R
EV-9200GC-64
I1PD78P214GC
I1PD78212GJ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GJ-R
EV-9200G-74
I1PD78P214GJ
I1PD78212GQ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GO-R
I1PD78P214GQ
I1PD78212L
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240LP-R
I1PD78P214L
I1PD78213CW
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240CW-R
I1PD78213GC
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GC-R
EV-9200GC-64
I1PD78213GJ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GJ-R
EV-9200G-74
I1PD78213G36
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GQ-R
I1PD78213L
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240LP-R
I1PD78214CW
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240CW-R
I1PD78214GC
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GC-R
EV -9200GC-64
I1PD78P214GC
I1PD78214GJ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GJ-R
EV-9200G-74
I1PD78P214GJ
I1PD78214G36
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GQ-R
I1PD78P214GQ
I1PD78214L
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240LP-R
I1PD78P214L
I1PD78P214CW
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240CW-R
I1PD78P214DW
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240CW-R
I1PD78P214GC
DDB-78K2-21X.
EB-78210-PC
IE-78240-R
EP-78240GC-R
EV -9200GC-64
I1PD78P214GJ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GJ-R
EV-9200G-74
I1PD78P214GQ
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240GO-R
I1PD78P214L
DDB-78K2-21X
EB-78210-PC
IE-78240-R
EP-78240LP-R
I1PD78217ACW
EB-78240-PC
IE-78240-R
EP-78240CW-R
I1PD78217AGC
EB-78240-PC
IE-78240-R
EP-78240GC-R
I1PD78218ACW
EB-78240-PC
IE-78240-R
EP-78240CW-R
I1PD78218AGC
EB-78240-PC
IE-78240-R
EP-78240GC-R
I1PD78P218ACW
EB-78240-PC
IE-78240-R
EP-78240CW-R
I1PD78P218ADW
EB-78240-PC
IE-78240-R
EP-78240CW-R
I1PD78P218AGC
EP-78240-PC
IE-78240-R
Optional
Socket Adapter
(Note 5)
EPROM/OTP
Device
(Note 6)
I1PD78P214CW/DW
I1PD78P214CW/DW
I1PD78P218ACW/DW
EV-9200GC-64
I1PD78P218AGC
EV-9200GC-64
I1PD78P218AGC
I1PD78P218ACW/DW
EP-78240GC-R
EV-9200GC-64
I1PD78220GJ
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230GJ-R
EV -9200G-94
I1PD78220L
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230LO-R
I1PD78224GJ
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230GJ-R
I1PD78224L
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230LO-R
I1PD78P224GJ
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230GJ-R
I1PD78P224L
DDB-78K2-22X
EB-78220-PC
IE-78230-R
EP-78230LO-R
I1PD78233GC
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GC-R
EV -9200GC-80
I1PD78233GJ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV -9200G-94
I1PD78233LQ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230LQ-R
I1PD78234GC
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GC-R
EV-9200GC-80
I1PD78P238GC
I1PD78234GJ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV-9200G-94
I1PD78P238GJ/KF
I1PD78234LQ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230LO-R
1-26
EV-9200G-94
I1PD78P224GJ
I1PD78P224L
EV -9200G-94
I1PD78P238LQ
NEe
Development Tools for Micro Products
K2 (JLPD782xx) Series Single-Chip Microcomputers (cont)
Device
(Notes 1, 2)
Eval uation Board
(Note 3)
Low-End
Emulator
Emulation
System
Emulation
Probe
(Note 4)
Optional
Socket Adapter
(Note 5)
IlPD78237GC
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-7B230GC-R
EV -9200GC-80
IlPD78237GJ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV -9200G-94
IlPD78237LQ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-7B230LQ-R
EPROM/OTP
Device
(Note 6)
IlPD78238GC
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-7B230GC-R
EV-9200GC-BO
IlPD78P23BGC
IlPD78238GJ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV-9200G-94
IlPD7BP23BGJ/KF
IlPD78238LQ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230LQ-R
IlPD78P238GC
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GC-R
EV-9200GC-80
IlPD78P238GJ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV -9200G-94
IlPD78P238KF
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230GJ-R
EV -9200G-94
IlPD78P238LQ
DDB-78K2-23X
EB-78230-PC
IE-78230-R
EP-78230LQ-R
IlPD78243CW
EB-78240-PC
IE-78240-R
EP-7B240CW-R
IlPD78243GCAB8
EB-78240-PC
IE-78240-R
EP-78240GC-R
IlPD78244CW
EB-78240 -PC
IE-78240-R
EP-78240CW-R
IlPD78244GC
EB-78240-PC
IE-78240-R
EP-78240GC-R
IlPD78P238LQ
EV-9200GC-64
EV-9200GC-64
Notes:
·(1) The following software packages are available for the K2 Series.
RA78K2 Relocatable Assembler Package: RA78K2-D52
(MS-DOS,",
ST78K2 Structured Assembler Preprocessor: provided with
RA78K2
CC78K2 C-Compiler package: CC78K2-D52 (MS-DOS)
(2) Packages:
CW
DW
G36
GC
GC
GC-AB8
GJ
GJ
GQ
KF
L
LQ
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin plastic QUIP (JlPD78213/214)
64-pin plastic QFP
(JlPD78212/213/214/P214/217A/218A/P218A/244)
80-pin plastic QFP (pPD7B233/234/237/238/P238)
64-pin plastic QFP
94-pin plastic QFP (JlPD78220/224/P224/233/234/
237/238/P238)
74-pin plastic QFP (JlPD7B212/213/214/P214)
64-pin plastic QUIP (JlPD78212/P214)
94-pin ceramic LCC with window
68-pin PLCC (JlPD78213/214/P214L)
84-pin PLCC (JlPD78220/224/P224L)
84-pin PLCC
(3) The DDB-78K2-2xx Evaluation Board is shipped with the RA78K2
Relocatable Assembler Package and the ST78K2 Structured
Assembler Preprocessor.
(4) This emulation probe can be used with both the EB-7B2xx-PC
low-end emulator and the IE-782xx-R emulation system.
(5) The EV-9200Gx-YV is an LCC socket with the footprint of the flat
package. One unit is supplied with the probe. Additional units
are available as replacement parts in sets of five.
(6) All EPROM/OTP devices can be programmed using the NEC
PG-1500. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate programming adapter.
MS-DOS is a registered trademark of Microsoft Corporation.
1-27
•
ttt{EC
Development Tools for Micro Products
K3 (JLPD783xx) Series Single-Chip Microcomputers
Device (Notea 1, 2)
Evaluation
Board (Note 3)
Emulation
System
Emulation Probe
IlPD78310ACW
DDK-78310A
IE-78310A-R
EP-783l0CW (Nole 6)
IlPD783l0AGF3BE
DDK-783l0A
IE-78310A-R
EP-78310GF
IlPD78310AGQ-36
DDK-7831OA
IE-78310A-R
EP-783l0GQ (Note 7)
IlPD78310AL
DDK-78310A
IE-78310A-R
EP-78310L
IlPD78312ACW
DDK-78310A
IE-78310A-R
EP-78310CW (Note 6)
IlPD78312AGF
DDK-78310A
IE-78310A-R
EP-783l0GF
IlPD78312AGQ
DDK-78310A
IE-78310A-R
EP-78310GQ (Note 7)
jlPD78P3l2AGQ/RQ
jlPD78P312AL
IlPD78312AL
DDK-78310A
IE-78310A-R
EP-78310L
IlPD78P312ACW
DDK-78310A
IE-78310A-R
EP-78310CW (Note 6)
IlPD78P312ADW
DDK-78310A
IE-78310A-R
EP-78310CW (Note 6)
IlPD78P312AGF
DDK-783l0A
IE-78310A-R
EP-78310GF
IlPD78P312AGQ-36
DDK-78310A
IE-783l0A-R
EP-78310GQ (Note 7)
IlPD78P312AL
DDK-78310A
IE-78310A-R
EP-78310L
IlPD78P312ARQ
DDK-78310A
IE-78310A-R
EP-783l0GQ (Note 7)
IlPD78320GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
jlPD78320L
EB-78320-PC
IE-78327-R
EP-78320L-.R
IlPD78322GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
jlPD78322L
EB-78320-PC
IE-78327-R
EP-78320L-R
jlPD78P322GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
jlPD78P322KC
EB-78320-PC
IE-78327-R
EP-78320L-R
jlPD78P322KD
EB-78320-PC
IE-78327-R
EP-78320GJ-R
IlPD78P322L
EB-78320-PC
IE-78327-R
EP-78320L-R
IlPD78323GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
IlPD78323LP
EB-78320'PC
IE-78327-R
EP-78320L-R
IlPD78324GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
IlPD78324LP
EB-78320-PC
IE-78327-R
EP-78320L-R
IlPD78P324GJ
EB-78320-PC
IE-78327-R
EP-78320GJ-R
IlPD78P324KC
EB-78320 -PC
IE-70327-R
EP-78320L-R
jlPD78P324KD
EB-78320-PC
IE-78327-R
EP-78320GJ-R
jlPD78P324LP
EB-78320-PC
IE-78327-R
EP-78320L-R
Optional Socket
Adapter (Note 4)
EV-9200G-64
jlPD78P312ACW/DW
EV-9200G-64
jlPD78P312AGF
EV-9200G-64
EV-9200G-74
EV-9200G-74
IlPD78P322GJ/KD
jlPD78P322L/KC
EV-9200G-74
EV-9200G-74
EV-9200G-74
EV-9200G-74
jlPD78P324GJ/KD
jlPD78P324LP/KC
EV-9200G-74
EV-9200G-74
jlPD78327CW
EB-78327-PC
IE-78327-R
EP-78327CW-R
IlPD78327GF
EB-78327-PC
IE-78327-R
EP-78327GF-R
IlPD78328CW
EB-78327 -PC
IE-78327-R
EP-78327CW-R
IlPD78328GF
EB-78327-PC
IE-78327-R
EP-78327GF-R
jlPD78P328CW
EB-78327-PC
IE-78327-R
EP-78327CW-R
IlPD78P328DW
EB-78327-PC
IE-78327-R
EP-78327CW-R
I1PD78P328GF
EB-78327-PC
IE-78327-R
EP-78327GF-R
EV-9200G-64
I1PD78330GJ
EB-78330-PC
IE-78330-R
EP-78330GJ-R
EV-9200G-94
IlPD78330LQ
EB-78330-PC
IE-78330-R
EP-78330LQ-R
IlPD78334GJ
EB-78330-PC
IE-78330-R
EP-78330GJ-R
1-28
EPROM/OTP
Device (Note 5)
EV-9200G-64
jlPD78P328CW/DW
EV-9200G-64
EV-9200G-94
jlPD78P328GF
IlPD78P334GJ
NEe
Development Tools for Micro Products
K3 C#&PD783xx) Series Single-Chip Microcomputers (cant)
Device (Notes 1, 2)
Evaluation
Board (Note 3)
Emulation
System
Emulation Probe
Optional Socket
Adapter (Note 4)
pPD78334LQ
EB-78330-PC
IE-78330-R
EP-78330LQ-R
pPD78P334GJ
EB-78330-PC
IE-78330-R
EP-78330GJ-R
pPD78P334KE
EB-78330-PC
IE-78330-R
EP-78330LQ-R
pPD78P334LQ
EB-78330-PC
IE-78330-R
EP-78330LQ-R
pPD78350GC
EB-78350-PC
IE-78350-R
EP-78240GC-R
EV-9200GC-64
pPD78P352GC
EB-78350-PC
IE-78350-R
EP-78240GC-R
EV-9200GC-64
EPROM/OTP
Device (Note 5)
pPD78P334LQ/KE
EV-9200G-94
III
pPD78P352GC
I
!
Notes:
(1) The following software packages are available for the K3 series:
RA78K3 Relocatable Assembler Package: RA78K3-D52
(MS-DOS.,
ST78K3 Structured Assembler Preprocessor: provided with
RA78K3
CC78K3 C-Compiler Package: CC78K3-D52 (MS-DOS)
(2) Packages:
CW
DW
GC-3BE
GF-3BE
GJ-5BG
GJ-5BJ
GQ-36
KC
KD
KE
L
LP
LQ
RQ
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin plastic QFP (14 x 14 mm)
64-pin plastic QFP (14 x 20 mm)
94-pin plastic QFP
74-pin plastic QFP (20 mm x 20 mm)
64-pin plastic QUIP
68-pin ceramic LCC with window
74-pin ceramic LCC with window
84-pin ceramic LCC with window
44-pin PLCC (pPD71 P301 L)
68-pin PLCC
(pPD78310A/312A/P312AL, pPD7832O/3221.)
68-pin PLCC
84-pin PLCC
64-pin ceramic QUIP with window
(3) Evaluation boards are shipped with the RA78K3 Relocatable
Assembler Package and the ST78K3 Structured Assembler Preprocessor.
(4) The EV-9200G-xx is an LCG socket with the footprint of the flat
package. One unit is supplied with the probe. Additional units
are available as replacement parts in sets of five.
(5) All EPROM/OT? devices can be programmed using the NEG
PG-1500. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate programming adapter.
(6) The emulation probe for the 64-pin shrink DIP package (EP78310GW) is supplied with the IE.
(7) The emulation probe for the 64-pin QUIP package (EP-78310GQ)
is supplied with the IE.
MS-DOS is a registered trademark of Microsoft Corporation.
1-29
NEe
Development Tools for Micro Products
DSP and Speech Products
Device
(Note 6)
Emulator
JlPD77P20D
EVAKIT-7720B
ASM77
SM77C25
JlPD77C20AC
EVAKIT-77C25
ASM77
JlPD77C20AGW
EVAKIT-77C25
Evaluation
Board
Assembler
(Note 1)
Simulator
(Note 2)
EPROM/OTP
Device
PG-1500 Adapter
(Note 3)
SM77C25
JlPD77P20D
(Note 5)
ASM77
SM77C25
JlPD77P20D
JlPD77C20AL
EVAKIT-77C25
ASM77
SM77C25
JlPD77C20ALK
EVAKIT-77C25
ASM77
SM77C25
JlPD77220L
EVAKIT-77230
RA77230
SM77230,
SIM77230
JlPD77220R
EVAKIT-77230
RA77230
SM77230,
SIM77230
JlPD77P220L
EVAKIT-77230
RA77230
SM77230
SIM77230
PA-77P220L
JlPD77P220R
EVAKIT-77230
RA77230
SM77230,
SIM77230
PA-77P230R
JlPD77230AR
EVAKIT-77230
RA77230
SM77230,
SIM77230
JlPD77P230R
PA-77P230R
JlPD77230AR-003
EVAKIT-77230
RA77230
SM77230,
SIM77230
JlPD77P230R
PA-77P230R
JlPD77P230AR
EVAKIT-77230
RA77230
SM77230,
SIM77230
JlPD77P230R
PA-77P230R
PA-77P25C
DDK-77220
(Note 7)
DDK-77220
(Note 7)
IE-77240
JlPD77P220R (EPROM)
JlPD77P220L (OTP)
JlPD77240R
IE-77240
RA77240
SIM77240
JlPD77C25C
EVAKIT-77C25
RA77C25
SM77C25
JlPD77P25C/D
JlPD77C25GW
EVAKIT-77C25
RA77C25
SM77C25
JlPD77P25GW
JlPD77P25L
PA-77P230R
JlPD77C25L
EVAKIT-77C25
RA77C25
SM77C25
JlPD77P25C
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25C
JlPD77P25D
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25C
JlPD77P25GW
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25GW
JlPD77P25L
EVAKIT-77C25
RA77C25
SM77C25
JlPD7755C
NV-300 System
(NoteS)
EB-775x
JlPD77P56CR
PA-77P56C
JlPD7755G
NV-300 System
(NoteS)
EB-775X/NV-310
JlPD77P56G
(Note 9)
PA-77P56C
JlPD7756C
NV-3OD System
(NoteS)
EB-775X/NV-310
JlPD77P56CR
(Note 9)
PA-77P56C
JlPD7756G
NV-300 System
(Note S)
EB-775X/NV-310
JlPD77P56G
(Note 9)
PA-77P56C
JlPD77P56CR
NV-300 System
(NoteS)
EB-775X/NV-310
PA-77P56C
JlPD77P56G
NV-3OD System
(NoteS)
EB-775X/NV-310
PA-77P56C
JlPD7757C
NV-300 System
(NoteS)
EB-775X/NV-310
JlPD7757G
NV-300 System
(Note S)
EB-775X/NV-310
JlPD7759C
NV-300 System
(NoteS)
EB-775X/NV-310
1-30
PA-77P25L
PA-77P25L
NEe
Development Tools for Micro Products
DSP and Speech Products (cont)
Device
(Note 6)
Emulator
IlPD7759GC
NV-300 System
(Note 8)
IlPD77501GC
NV-300 System
(Note 8)
Evaluation
Board
Assembler
(Note 1)
Simulator
(Note 2)
EPROM/OTP
Device
PG-1500 Adapter
(Note 3)
EB-775x/NV-310
IlPD77810L
IE-77810
RA77810
IlPD77810R
IE-77810'
RA7781 0
Notes:
(1) The following assemblers are available:
ASM77-D52
Assembler for 7720 (MS-DOSI!!\
RA77C25-D52
Assem bier for 77C25 (MS-DOS)
RA77C25-VVT1 Assembler for 77C25 rJAX®/VMS®j
RA7723O-D52
Assembler for 77230 (MS-DOS)
RA77230-VVT1 Assembler for 77230 (VAX/VMS)
RA77230-VXT1 Assembler for 77230 rJAX/UNIX® 4.2 BSD or
Ultrix'")
(2) The following simulators are available:
SIM7723O-VVT1 Simulator for 77230 rJAX/UNIX)
SIM77230-VXT1 Simulator for 77230 rJAX/UNIX 4.2 BSD or
Ultrix)
SM77C25
Simulator for 77C25 (IBM-PC)
SM77230
Simulator for 77220, 77230 (IBM-PC)
SIM77240
Simulator for 77240 (IBM-PC)
(3) By using the specified adapter, the NEC PG-1500 EPROM
programmer can be used to program the EPROM/OTP device.
(4) Please check with your NEC Sales Representative on the availability of a PLCC emulation probe.
(5) TheIlPD77P20D can be programmed using the EVAKIT-7720B.
(6) Packages:
C
18, 28, or 40-pin plastic DIP
o
28-pin ceramic DIP
G
24-pin plastic SOP
GC
52-pin plastic QFP
L
44-or 68-pin PLCC
LK
28-pin PLCC
R
68-pin ceramic PGA
GW
32-pin SOP
(7) DDK-77220 is supported by Hypersignal WorkstationlWindow, a
DSP software platform from Hyperception.
(8) The NV-300 current version is Version 3.0. An upgrade from
previous versions (hardware and software) is available under the
designation NV-301.
(9) The NV-310 emUlation board includes a simple 77P56 programmer module.
1-31
NEe
Development Tools for· Micro Products
PG-1S00 Programming Adapters
Adapter Module
(Note 2)
Target Chip
Socket Adapter
(Note 1)
Adapter Module
(Note 2)
JlPD27256 (21 V)
JlPD27256A (12.5 V)
JlPD27C256 (21 V)
OZlA Board
JlPD75P316AK
JlPD75P328GC
JlPD75P336GC
PA-75P308K
PA-75P328GC
PA-75P328GC
04A Board
04A Board
04A Board
027A Board
027A Board
027A Board
(Note 3)
PA-75P402CT
PA-75P402GB
OZlA Board
/lPD27C256A (12.5 V)
JlPD27C512
JlPD27Cl000
JlPD75P402C
JlPD75P402CT
JlPD75P402GB
JlPD27Cl000A
JlPD27Cl00l
/lPD27Cl00l A
027A Board
027A Board
027A Board
JlPD75P516GF
JlPD75P516K
JlPD75P518GF
PA-75P516GF
PA-75P516K
PA-75P516GF
04A Board
04A Board
04A Board
PA-75P516K
PA-75P516GF
04A Board
04A Board
JlPD27Cl024
JlPD27Cl024A
027A Board
027A Board
JlPD75P518K
JlPD75P618GF
JlPD78CP140N
JlPD78CP14DW
JlPD78CP14G36
PA-78CP14CW
PA-78CP14CW
PA-78CP14GQ
027A Board
027A Board
027A Board
JlPD78CP14GF
JlPD78CP14L
JlPD78CP14R
PA-78CP14GF
PA-78CP14L
PA-78CP14GQ
OZlA Board
JlPD78CP180N
JlPD78CP18GQ
JlPD78CP18GF
PA-78CP14ON
PA-78CP14GQ
PA-78CP14GF
027A Board
027A Board
027A Board
JlPD78CP18KB
PA-78CP14KB
027A Board
Target Chip
Socket Adapter
(Note 1)
Standard 27xxx EPROM Devices
027A Board
027A Board
V-Series Devices
PA-70P322L
027A Board
JlPD75P54CS
JlPD75P54G
JlPD75P56CS
PA-75P54CS
PA-75P54CS
PA-75P56CS
04A Board
04A Board
04A Board
JlPD75P56G
JlPD75P64CS
JlPD75P64G
PA-75P56CS
PA-75P54CS
PA-75P54CS
04A Board
04A Board
04A Board
JlPD75P66CS
JlPD75P66G
PA-75P56CS
PA-75P56CS
04A Board
04A Board
JlPD70P322K
75xx Series Devices
75xxx Series Devices
JlPD75POO8CU
JlPD75POO8GB
JlPD75P0380N
PA-75POO8CU
PA-75POO8CU
PA-75P038CW
04A Board
04A Board
04A Board
JlPD75P036GC
JlPD75P048CW
JlPD75P048GC
PA-75P038GC
PA-75P038CW
PA-75P038GC
04A Board
04A Board
04A Board
JlPD75Pl08BON
JlPD75P108CW
JlPD75P108DW
PA-75Pl080N
PA-75Pl080N
PA-75Pl080N
04A Board
04A Board
04A Board
JlPD75P108BGF
JlPD75Pl08G
JlPD75Pl16CW
PA-75P116GF
PA-75Pl08G
PA-75Pl08CW
04A Board
04A Board
04A Board
JlPD75Pl16GF
JlPD75P117HGC
JlPD75P216ACW
PA-75P116GF
PA-75Pl17HGC
PA-75P216ACW
04A Board
04A Board
04A Board
JlPD75P218CW
JlPD75P218GF
JlPD75P218KB
PA-75P216ACW
PA-75P218GF
PA-75P218KB
04A Board
04A Board
04A Board
JlPD75P238GJ
JlPD75P238KF
JlPD75P308GF
PA-75P238GJ
PA-75P238KF
PA-75P308GF
04A Board
04A Board
04A Board
JlPD75P308K
JlPD75P316GF
JlPD75P316AGF
PA-75P308K
PA-75P308GF
PA-75P308GF
04A Board
04A Board
04A Board
1-32
027A Board
027A Board
78xx Series Devices
027A Board
027A Board
K2 (782xx) Series Devices
JlPD78P214CW
JlPD78P214DW
JlPD78P214GC
PA-78P214CW
PA-78P214ON
PA-78P214GC
027A Board
027A Board
027A Board
JlPD78P214GJ
JlPD78P214GQ
JlPD78P214L
PA-78P214GJ
PA-78P214GQ
PA-78P214L
OZlA Board
JlPD78P218AON
JlPD78P218ADW
JlPD78P218AGC
PA-78P214ON
PA-78P214ON
PA-78P214GC
027A Board
027A Board
027A Board
JlPD78P224GJ
JlPD78P224L
JlPD78P238GC
PA-78P224GJ
PA-78P224L
PA-78P238GC
027A Board
027A Board
027A Board
JlPD78P238GJ
JlPD78P238KF
JlPD78P238LQ
PA-78P238GJ
PA-78P238KF
PA-78P238LQ
027A Board
027A Board
027A Board
027A Board
027A Board
K3 (783xx) Series Devices
JlPD78P312A0N
JlPD78P312ADW
JlPD78P312AGF
PA-78P312CW
PA-78P312ON
PA-78P312GF
027A Board
027A Board
027A Board
JlPD78P312AGQ
JlPD78P312AL
JlPD78P312ARQ
PA-78P312GQ
PA-78P312L
PA-78P312GQ
027A Board
027A Board
027A Board
JlPD78P322GJ
JlPD78P322KC
JlPD78P322KD
PA-78P322GJ
PA-78P322KC
PA-78P322KD
027A Board
027A Board
027A Board
NEe
Development Tools for Micro Products
PG-1500 Programming Adapters (cont)
Target Chip
Socket Adapter
(Note 1)
Adapter Module
(Note 2)
K3 (7S3xx) Series Devices (cont)
/lPD78P322L
/lPD78P324GJ
/lPD78P324KC
PA-78P322L
PA-78P324GJ
PA-78P324KC
027A Board
027A Board
027A Board
/lPD78P324KD
/lPD78P324LP
/lPD78P328CW
PA-78P324KD
PA-78P324LP
PA-78P328CW
027A Board
027A Board
027A Board
/lPD78P328DW
/lPD78P328GF
/lPD78P334GJ
PA-78P328CW
PA-78P328GF
PA-78P334GJ
027A Board
027A Board
027A Board
/lPD78P334KE
/lPD78P334LO
/lPD78P352GC
PA-78P334KE
PA-78P334LO
PA-78P352GC
027A Board
027A Board
027A Board
•
DSP and Speech Products
/lPD77P25C
/lPD77P25D
/lPD77P25GW
PA-77P25C
PA-77P25C
PA-77P25GW
027A Board
027A Board
027A Board
/lPD77P25L
/lPD77P220L
/lPD77P220R
PA-77P25L
PA-77P220L
PA-77P230R
027A Board
027A Board
027A Board
/lPD77P230R
/lPD77P56CR
/lPD77P56G
PA-77P230R
PA-77P56C
PA-77P56C
04A Board
04A Board
027A Board
Notes:
(1) Adapters must be purchased separately.
(2) The 27A and 04A Adapter Modules are shipped with the PG-1500.
(3) The IlPD75P402C does not require a programming socket
adapter. It can be plugged directly into the 027A board.
1-33
Development Tools for Micro Products
1-34
NEe
NEe
Reliability and Quality Control
NEe
Reliability and Quality Control
Section 2
Reliability and Quality Control
Built-in TQC
2-1
Approaches to TQC .
2-1
Implementation of Quality Control
2-3
Reliability Theory
2-5
Failure Analysis
2-9
Summary
2-9
Figure 1. NEC's Quality Control System
2-2
Figure 2. New Product Development
2·3
Figure 3. Electrical Testing and Screening
2-5
Figure 4. Reliability Life (Bathtub) Curve
2-5
Appendix 1A. Typical QC Flow for CMOS
Fabrication
2-10
Appendix 1B. Typical QC Flow for PLCC
Assembly!Test
2·11
Appendix 2. Typical Reliability Assurance
Tests
2-13
Appendix 3. New ProducVProcess Change
Tests
2-13
Appendix 4. Failure Analysis Flowchart
2-14
NEe
Reliability and Quality Control
NEG Electronics Inc.
As large-scale integration (LSI) reaches a higher level
of density, the reliability of individual devices imposes a
more profound impact on system reliability. As a result,
great emphasis has been placed on assuring device
reliability.
Conventionally, performing reliability tests and using
feedback from the field have been the only methods of
monitoring and measuring reliability. As LSI density
increases, however, it has become more difficult to
activate internal circuit elements in a device from
external terminals and to detect their degradation.
Testing and feedback alone cannot provide enough
information to ensure today's demanding reliability
requirements.
To guarantee and improve high levels of reliability for
large-scale integrated circuits, a new philOSOPhy and
methodology are needed for reliability assurance.
Ouality and reliability must not only be monitored and
measured but, most importantly, must be built into the
product.
BUlLT·IN TQC
NEC has introduced the concept oftotal quality control
(TOC) across its entire semiconductor product line to
implement this philosophy. Rather than performing
only a few simple quality inspections, quality control
has become an integral part of each process step
involving production, engineering, quality control
staffs, and all management personnel. Figure 1 is a
flowchart that shows how these activities form a comprehensive quality control system at NEC.
In addition to TOC, NEC has introduced a prescreening method into the production line that eliminates potentially defective units. This combination of
building in quality and screening out projected early
failures has resulted in superior quality and reliability.
Most large-scale integrated circuits use high-density
MaS technology with state-of-the-art high performance due to improved fine-line generation techniques. When physical parameters are reduced, circuitdensity and performance increase while active circuit
power dissipation decreases. The information presented here will show that this advanced technology
combined with the practic'9 of TOC yields products as
reliable as those from previous technologies.
APPROACHES TO TQC
TOC activities are geared toward total customer satisfaction. The success of these activities depends on
managements commitment to enhancing employee
development, maintaining a customer-first attitude,
and fulfilling community responsibilities.
TOC is implemented in the following steps. First, quality control is embedded into each process, allowing
early detection of possible failure mechanisms and
immediate feedback. Second, the reliability and quality
assurance policy is upheld through company-wide
quality control activities. Third, emphasis is placed on
research and development efforts to achieve even
higher standards of device quality and reliability.
Fourth, extensive failure analysis is performed periodically, and appropriate corrective actions are taken as
preventative measures.
Process control limits are based on statistical data
gathered from this analysis and used to determine the
effectiveness of the in-process quality control steps.
New standards are continuously upgraded, and the
iterative process continues. The goal is to maintain the
superior product quality and reliability that has become synonymous with the NEC name.
Zero Defects Program
One of the quality control activities that involves every
staff level is the Zero Defects (ZO) Program. The purpose of the ZO Program is to minimize, if not prevent,
defects due to controllable causes. These activities are
organized by groups of workers around these four
premises.
• A group must have a target or purpose to pursue.
• Several groups can be organized to pursue a
common target.
• Each group must have a responsible leader.
• Each group is well supported by management.
2-1
NEe
Reliability and Quality Control
Figure t.
Dept
NEC'S Quality Control System
ManufacbJ~ng FacUlty
InspectlorVManufacbJring
Customer
I
Deve,:merri
Market
Research
Needs
I
Technology
t
-;:=:1
Sales
Plan
t
I
I
New Device Development and Sales CommHtee
t
h
.1 Device
Development(
Design
1Clrcutt Design
Product/Process Design
t
I
I
I
Design Review
~
SpeclEng. Support
Trial Producllon Run
I
t
I
H
Characterization!
Evaluation
ReUabHIty
Eveluation
~
I
I
1
Mess ProducllorV"Sales Committee
J
I
J
I
Rellabllty
Evaluation
~
I
Preparation of Spec for
MaufaclurlngffesUng"QA
t
I
Procurement of
PartslMaleriais
t
Incoming
Inspection
Warehousing
y
Shipping
~
I
InvesUgetioriAnalyslsfCounlermeesure
Dlrecllon of Lot
(
Use
Complaint
(FIeld Deta)
1
Archweof~
Order
I
f
~
Receipt
CoDeclion
-
t
Eleclrical Test
ReliablUty Test
QA InspiPacking
+
1
t
Manufacluring
r-J
'\
.J
Data Collection
}->-
In-Process Quality Monitoring;
In-Process Inspecllon;
Envlronmerri and Equipment
ControVCallbrallon;
Lot Control;
Correcllve Actions;
Data Analysis; Feedback; Etc.
83AD-1614B
2-2
t\fEC
The groups target is selected from items relating to
specifications, inspections, operation standards, etc.
When past data is available, a Pareto diagram is created and reviewed to select an item most in need of
quality improvement. Target defects related to this item
are clearly defined. Records are analyzed to compute
numerical equivalents of the defects. Then, action is
taken to control these defects.
Statistical Approach
Reliability and Quality Control
Figure 2_ New Product Development
-clrcun
Design
LSI Design
-Mask
Pattem
Layout
• Process
and Product
Manufacturing
- Package
Design
Another approach to quality control is statistical analysis. NEC uses statistical analysis at each stage of LSI
product development, trial runs, and mass production.
Some implementations of this statistical approach are:
• Process comparisons
• Control charts
• Data analysis
- Correlation, regression, multivariance, etc.
• Cp/Cpk studies
- Variables and attributes data (performed
monthly)
Process control sheets and other QC tools are used to
monitor important parameters such as Cp, Cpk, X, X-A,
electrical parameters, pattern dimensions, bond
strength, test percentage defects, etc. The results of
these studies are monitored by the production staff,
QC engineers, and other associated engineers. If any
out-of-control or out-of-specification limit is observed,
corrective procedures are quickly taken.
IMPLEMENTATION OF QUALITY CONTROL
Building quality into a product requires early detection
of possible failure mechanisms and immediate feedback to remove such problems. A fixed quality inspection station often cannot provide prompt and accurate
feedback about the process steps prior to the inspection. Quality control functions have therefore been
distributed into each process step including the conceptual stage. The most significant areas where quality
control has been placed include:
•
•
•
•
•
•
•
•
Product development
Incoming material inspection
Wafer processing
Chip mounting and packaging
Electrical testing and infant mortality screening
Outgoing material inspection
Reliability assurance tests
Process/product changes
83RD-7612A
2-3
t'tIEC
Reliability and Quality Control
Product Development
New product development includes the product concept, device proposal review, physical element design
and organization, engineering evaluation, and, finally,
product transfer to manufacturing. Quality and reliability are considered at every step. The new product
development flow at NEe is shown in figure 2.
Design is the first and most important step in new
product development. NEe believes that the foundation of device quality is determined at the design stage.
The four steps involved are circuit design, mask pattern
layout, package design, and the setting of process and
product manufacturing conditions. Design standards
have been established at NEe to maximize quality and
reliability.
After completion of the design, a design review is
performed to check for conformity to design standards
and to consider other factors influencing reliability and
quality. At this stage, modification or re-design may be
necessary. NEe believes that design reviews are essential for product modifications as well as newly designed products.
Once a design successfully passes its review, a trial run
takes place in which the products electrical and mechanical characteristics, quality, and reliability are
evaluated.
Additional runs are performed in which process conditions are varied deliberately, causing characteristic
factors to change in mass production. These samples
are evaluated to determine the best combination of
process conditions. Reliability tests are then conducted to check the new products electrical and mechanical stress resistance. If no problems are found at
this stage, the product is approved for mass production.
Mass production begins after the product design department prepares a schedule that includes reliability
and quality control steps. The standards for production and control steps are continuously re-examined
for possible improvement, even after mass production
has started.
Incoming Material Inspection
NEe has the following programs to control incoming
materials:
•
•
•
•
Vendor/material qualification system
Purchasing specifications for materials
Incoming materials inspection
Inspection data feedback
2-4
• Meetings with vendors concerning quality
• Vendor audits
If any parts or materials are rejected at incoming
inspection, they are returned to the vendor with a
rejection notification form specifying the failure items
and modes. The results ofthese inspections are used to
rate the vendors for future purchasing.
In-Process Quality Inspection
Typical in-process quality inspections performed at
wafer fabrication, chip mounting and packaging, and
device testing stages are listed in appendix 1A and
appendix 1B.
Electrical Testing and Screening
At the first electrical test, dc parameters are tested
according to electrical specifications on 100% of each
lot. This is a prescreening prior to any infant mortality
test. At the second electrical test, ac functional tests as
well as dc parameter tests are performed on 1000"{' of
each lot. If the percentage of defective units in a lot is
unacceptably high in this test, the lot is subjected to an
infant mortality rescreen. During this time, any defective units undergo extensive failure analysis. The results of these analyses are fed back into the process
through corrective actions.
Figure 3 is a flowchart of the typical infant mortality
screening and electrical testing.
Outgoing Inspection
Prior to warehouse storage or shipment, lots are subjected to an outgoing inspection according to the
following sampling plan:
• Electrical
- Dc parameters, lot tolerance parts defective
(LTPD) 3%
- Ac functional LTPD 3%
• Appearance
- Major LTPD 3%
- Minor LTPD 7%
fttIEC
Reliability and Quality Control
Figure 3. Electrical Testing and Screening
• Dc parameter tesUng
• Full Ac/dc testklg W
no 100% bum·ln
tain period of time. The concept of probability, the
definition of required function, and the knowledge of
how time affects the item of concern are therefore
necessary tools for the study of reliability.
Definition of a required function, by implication, treats
the definition of a failure. Failure of a device is defined
as the termination of a device's ability to perform its
required function. A device has failed if it is unable to
meet guaranteed values given in its electrical specifications.
• When required
• Dc parameter tesUng
• Ac luncllonal testing
No
Failures are categorized by the period of time in which
they occur. The critical times used in the discussion of
device reliability and failure are the periods of early,
random, and wearout failures. Probability is used to
quantitatively estimate reliability levels during these
periods as well as overall reliability. The relevant theories and methods of calculation will be discussed later.
Regarding individual devices, specific failure mechanisms seen in life tests and in infant mortality screening
tests are the parameters of concern in the determination of overall device failure rates, thus reliability levels.
• Electrical tests
• Appearance
• Dimensions
Regarding systems, the sum of individual device fai lure
rates is the expected failure rate of the system hardware.
83RD-7611A
Reliability Assurance Tests
Prior to shipment, representative samples from each
process family are taken on a regular basis and subjected to monitoring reliability tests. This testing is
performed to confirm that NECs products continually
meet their field reliability targets.
Life Distribution
The fundamental principles of reliability engineering
predict that the failure rate of a group of devices will
follow the well-known bathtub curve in figure 4.
Figure 4. Reliability Ute (Bathtub) Curve
Process/Product Changes
As mentioned previously, a design review occurs for
product changes as well as for new products. Once a
design is approved and processes are altered for max·
imum quality, qualification testing is performed to
check reliability. If the test results are acceptable, the
product is internally qualified for mass production.
The typical reliability qualification tests performed at
NEC are listed in appendix 3.
RELIABILITY THEORY
.
'Ii
a:
I
Wearoul
Period
Random Fanure Period
~
l!
__________________________ ~
~i
TIme
Reliability is defined as a characteristic of an item
expressed by the probability that it will perform a
required function, under specific conditions, for a cer-
2-5
•
I
I
I
Reliability and Quality Control
The curve is divided into three regions: infant mortality,
random failures, and wearout failures.
The infant mortality section of the curve, where the
failure rate is declining rapidly, represents the Elarly-life
device failures. These failures are usually associated
with one or more manufacturing defects.
After a period of time, the failure rate reaches a low
value. This random failure area of the curve represents
the useful portion of a device's life. During this random
failure period, a slight decline is observed due to the
depletion of potential random failures from the general
population.
Wearout failures occur at the end of useful device life.
These failures are observed in the rapidly rising failure
rate portion of the curve; devices are wearing out both
physically and electrically.
Therefore, for a device that has a very long life expectancy compared to the system that contains it, the
areas of concern will be the infant mortality and random failure portions of the bathtub curve.
Failure Distribution at NEe
To eliminate infant mortality failures, NEC subjects its
products to production burn-in whenever necessary.
This burn-in is performed at an elevated temperature
on 100% of the devices involved and is designed to
remove potentially defective units.
After elimination of early device failures, a system will
be left to the random failures of its components. To
make proper projections of the failure rate·of a system
in the operating environment, random failure rates
must be predicted for the system's components.
To qualitatively study random failures, integrated circuits returned from the field, as well as in-house life
testing failures, undergo extensive failure analyses at
respective NEC manufacturing divisions. Failure mechanisms are identified and resulting data is fed back to
appropriate production and engineering groups. Longterm failure rates are determined from this data to
quantitatively study this random failure population.
Infant Mortality Failure Screening
Establishing infant mortality screening requires knowledge of likely failure mechanisms and their associated
activation energies.
2-6
NEe
Typical problems associated with infant mortality failures are manufacturing defects and process anomalies, which consist of contamination, cracked chips,
wire bond shorts, or bad wire bonds. Since these
problems can result from a number of possible failure
mechanisms, the activation energy for infant mortality
can vary considerably. Correspondingly, the effectiveness of an infant mortality screening condition (preferably at some stress level to shorten the screening
time) varies greatly with the failure mechanism.
For example, failures due to ionic contamination have
an activation energy of approximately 1.0 eV. Therefore, a 15-hour stress at 1250C junction temperature
would be the equivalent of approximately 314 days of
operation at a junction temperature of 55°C. On the
other hand, failures due to oxide defects have an
activation energy of approximately 0.3 eV. A 15-hour
stress at 125°C junction temperature in this case would
be the equivalent of approximately 4 days of operation
at 55°C junction temperature. The condition and duration of infant mortality screening is determined by the
economic factors involved in the screening and by the
allowable rate of component failure. A component
failure causes a system failure.
Empirical data gathered at NECindicates that any
early fai lures generally occur after less than 4 hours of
stress at 125°C ambient temperature. This fact is supported by the bathtub curve created from actual life
test results. The failure rate after 4 hours of such stress
testing shows random distribution as opposed to the
rapidly decreasing failure rate observed in the early life
portion of the curve.
Whenever necessary, NEC has adopted this infant
mortality burn-in at 125°C as a standard production
screening procedure. NEC believes it is imperative that
failure modes associated with such infant mortality
screens be understood and fixed at the manufacturing
level. Failure analysis is performed on all infant mortality failures for this purpose. This in-line data coupled
with data accumulated from the field is used to introduce corrective actions and quality improvement measures. If the early-life failures of a device can be
minimized or eliminated and countermeasures appropriately monitored, then such screens can be eliminated. The result of such practices is that field reliability of NEC devices is an order of magnitude higher than
NEC's long-term failure rate goals.
NEe
Table 1.
Reliability and Quality Control
Typical Reliability Test Results
Name
Type
HTB
T/H
PCT
T/C
Micro
(Note 1)
NMOS
9/23817
(15 FIl)
3/13625
0/5034
0/1817
CMOS
7/20361
(6.6 FIT)
6/15155
8/16727
0/5913
DRAM (Note 2)
9/13072
(8.2 FIl)
2/12796
4/8477
3/3085
1 Meg DRAM (Note 3)
24/13459
(68 FIl)
0/5414
0/2920
0/2100
4 Meg DRAM (Note 4)
4/2150
(4.2 FIT)
0/550
0/550
0/760
SRAM (Note 5)
0/3966
(6.6 FIT)
0/275
0/316
0/305
1 Meg SRAM (Note 5)
0/458
(5.8 FIl)
1/3026
0/3838
0/1350
CMOS
7/6146
(43 FIT)
2/2848
4/9159
6/5738
ECl
0/1368
(8 FfT)
SiCMOS
3/2801
(29 FIT)
Memory
(HTOl)
ASIC
(Note 6)
0/246
0/3505
0/4370
0/5555
Note:
Information in the table
numbers:
(1) IRQ-3Q-22833
(2) TRQ-89-01-OO21
(3) TRQ-89-01-0021
above has been extracted from NEC report
(4) IRQ-2Q-70117
(5) TRQ-90-11-0085
(6) TRQ-91-02-0093
Accelerated Reliability Testing
NEC performs extensive reliability testing at both preproduction and post-production levels to ensure that
all products meet NEC's minimum expectations and
those of the field.
Assume an electronic system contains 1000 integrated
circuits and that 1% system failures per month can be
tolerated by this system. The allowable failure rate per
component is then calculated as follows:
1% failures
720 hours x 1000 pieces
(0.0014) % failures
1000 hours
14 FITs
The rate of 14 FITs corresponds to one failure in 85
devices during an operating test of approximately
10,000 hours. To demonstrate this reliability level in a
reasonable amount of time, a test condition is apparently required to accelerate the time-to-failure in a
predictable and understandable way.
ure. Other stressful environmental conditions are voltage, current, humidity, vibration, or some combination
of these. Appendix 2 lists typical accelerated reliability
assurance tests performed at NEC on molded integrated circuits. Table 1 shows the results of some of
these tests for various process types.
Reliability Assurance Tests
NEC's life tests consist of the high-temperature
operating/bias life (HTOLJHTB), the high-humidity storage life (HHSL), the high-temperature, high-humidity
(T/H = HHSL + bias), and the high-temperature storage
life (HTSL). Additionally, NEC performs various environmental and mechanical tests.
HTOL/HTB Test. These tests are used to accelerate
failure mechanisms by operating devices in a dynamic
(operating life) or static (bias) condition at an elevated
temperature of 125°C. The data obtained is translated
to a lower temperature to estimate device life expectancy using the Arrhenius relationship explained later.
The most common method for decreasing time-tofailure is the use of high temperature to accelerate
physiochemical reactions that can lead to device fail2-7
.i
NEe
Reliability and Quality Control
HHSL and T/H Tests. Integrated circuits are extremely
sensitive to the effects of humidity such as electrolytic
corrosion between biased lines. The high-temperature
and high-humidity tests are performed to detect failure
mechanisms accelerated by temperature and humidity,
such as leakage related problems and drifts in device
parameters due to process instability.
HTSL Test. Another common test is the hightemperature storage life test in which devices are
subjected to elevated temperatures with no applied
bias. This test is used to detect process instability and
stress migration problems.
Environmental Tests. Other environmental tests such
as the pressure cooker test (PCl) or the temperature
cycling test (T/C) detect problems related to the package and/or interactions between materials as well as
the degradation of environmentally sensitive device
characteristics.
Failure Rate Calculation/Prediction
To predict the device failure rate from accelerated life
test data, the activation energies of the failure mechanisms involved should be considered. In some cases,
an average activation energy is assumed to accomplish a quick first-order approximation. NEC assumes
an average activation energy of 0.7 eV for most products (0.3 eV for high-density memory devices). This
average value has been assessed from extensive reliability test results and yields a conservative failure rate.
Since most semiconductor failures are temperature
dependent, the Arrhenius relationship is used to normalize failure rate predictions at a system operation
temperature of 55°C. ·It assumes that temperature dependence is an exponential function that defines the
probability of failure occurrence, and that degradation
of a performance parameter is linear with time. The
Arrhenius model includes the effects of temperature
and activation energies of the failure mechanisms in
the following Arrhenius equation:
A= exp-EA(TJ1-TJV
k(TJ1)(TJV
Where:
A(l) = Acceleration factor
EA = Activation energy
TJl = Junction temperature (in K) at TAl = 550C
TJ2 = Junction temperature (in K) at TA2 = 125°C
k = Boltzmann's constant = 8.62 x 10-5 eV/K
Because the thermal resistance and power dissipation
of a particular device type cannot be ignored, junction
temperatures (TJl and TJ2) are used instead of ambient
temperatures (TAl and TAV. We calculate junction tem2-8
peratures using the following formula:
TJ = TA + (thermal resistance)(power diss. at TA>
With this information, a temperature acceleration factor can be calculated.
In some cases, the effect of voltage acceleration on
failure rate must also be considered. Voltage acceleration can be characterized by the following equation:
A(V) = exp H3(Vd - Vs))
Where:
Vd = Operating voltage (5.5 V)
Vs = Life test stress voltage (7 V)
f3 = Empirically determined constant (dependent on
electric field constant and oxide thickness)
The constant f3 has been given the value"" 1, which is
a conservative figure. Therefore, the overall acceleration factor will be determined as the product:
A(T,V) = A(l) * A(V)
To estimate long-term failure rate, the acceleration
factor must be multiplied by the actual time to determine the simulated test time. From the hightemperature operating or bias life test results, failure
rates can then be predicted at a 60% confidence level
using the following equation:
L
=
(X2)1Q5
2T
Where:
L = Failure rate in %/1000 hours
X2 = The tabular value of chi-squared distribution at a
given confidence level and calculated degrees of
freedom (2f + 2, where f = number of failures)
See note below.
T = # of equivalent device hours = (# of devices) x (#
of test hours) x (acceleration factor)
Note: Since the failures of concern here are the long-term
failures, not the infant mortality failures (that is, the end
of the downward slope and the middle constant section of the bathtub curve in figure 4), X2 1s determined
by assuming a one-sided, fixed time test.
Another method of expressing failures is in FITs (failures in time). One FIT is equal to one failure in 109
hours. Since L is already expressed as %/1000 hours
(10-5 failure/hr), an easy conversion from %/1000 hours
to FIT would be to multiply the value of L by 104.
tVEC
Reliability and Quality Control
To accurately determine this failure rate, a statistically
large sample size must be accumulated. Depending on
the accuracy needed, the following conditions should
be imposed:
• A minimum of 1.2 million device hours (equal to
sample size multiplied by test period) at 125°C
should be accumulated to accurately predict a failure rate of 0.02"A. per 1000 hours at 55OC, with a 60%
confidence level.
• A minimum of 3 million device hours at 1250C should
be accumulated to accurately predict a failure rate
of 0.01% per 1000 hours at 55°C, with a 60% confidence level.
Failure Rate Calculation Example. As an example of
how this failure rate is calculated, assume a sample of
960 pieces was subjected to 1000 hours at 125°C burnin. One reject was observed. Given that the acceleration factor was calculated to be 34.6 using the Arrhenius equation, what is the failure rate normalized to
550C using a confidence level of 60%? Express the
failure rate in FITs.
Solution:
For n
2f
= + 2 = 2(1) + 2 = 4, X2 = 4.046
Then L = (X2)105 (%/1000 hours)
2T
(X2)105 (%/1000 hours)
2(# devices)(# test hours)(accel. factor)
(4.046)105
2(960)(1000)(34.6)
Therefore, FIT
= 0.0061 (%/1000 hours)
= (0.0061)(104) = 61
Failure Rate Goals
Reject rates at customer's incoming inspection, infant
mortality rates, and long-term failure rates are monitored and checked against quality and reliability targets. Long-term failure rate goals are based on mask
and process designs. NEC's quality and reliability targets are listed in table 2.
Table 2. Quality and Reliability Targets
Memory
Year
EClRAM
Micro
ASIC
BiCMOS
MOS
ECl
CMOS
Reject Rate at Customer's
Incoming Equipment Inspection (PPM)
1991
30
30
70
300
80
80
1992
30
30
50
200
50
60
Long-Term Reliability (FIT)
1991
30
30
30
300
30
90
1992
30
30
20
300
30
80
Infant Mortality
1991
30
30
40
300
50
270
1992
30
30
30
300
50
240
FAILURE ANALYSIS
At NEC, failure analysis is performed not only on
reliability testing and field failures, but also on products that exhibit defects during production. This data is
closely checked for correlation process quality information, inspection results, and reliability test data.
Information derived from these failure analyses is fed
back into the process.
Since many failure mechanisms can be exhibited by
LSI devices, highly advanced analytical tools and
methodologies are required to investigate such LSI
failures in detail. The standard failure analysis flowchart relati ng to the returned products from customers
is shown in appendix 4.
SUMMARY
Building quality and reliability into products by forming
a total quality control system is the most efficient way
to ensure product success.
The combination of building quality into products,
effective prescreening of potential failures, and monitoring of reliability through extensive testi ng has established a singularly high standard for NEC's large-scale
integrated circuits, as demonstrated in the most recent
year's production.
The companys quality control program supports continuous research and development activities, extensive
failure analysis, and process improvements. With this
extensive program, NEC continuously sets and maintains higher standards of quality and reliability.
2-9
NEe
Reliability and Quality Control
Appendix fA.
Typical QC Flow for CMOS Fabrication
Waler FabrtcaUon Process QC FloW (CMOS)
Flow
Process Material
In-process InspecUonlquailty Monitor
Silicon Waler
Incoming
Inspecllon
Resistivity (sampling by lot)
Dimension (sampOng by lot)
VIsual (sampling by lot)
Wei
FormaUon
OxIdaUon
Photo Uthography
Ion Implantation
Reid
FormeUon
OxIda thickness (sampling by lot)
Alignment and etching accuracy (sampUng by lot)
Layer reslstanoa (sampling by lot)
DeposlUon
Photo Uthography
Deposit thickness (sampling by 101)
AlIgnment and etching accuracy (sampling by lot)
OxIdation
Channel Stopper
FormaUon
OxIde thickness (sampling by lot)
Photo Uthography
Alignment and etching accuracy (sampUng by lot)
Ion ImplantaUon
OxIdaUon
Gate
Formation
Deposition
Doping
Photo Uthography
Layer resistanoa (sampling by lot)
OxIda thlckneaa (sampling by lot)
Deposit thickness (sampling by 101)
Layer resistance (sampling by lot)
Alignment and etching accuracy (sampling by lot)
Gate electrode width (sampling by lot)
pin SO FormaUon
Photo Uthography
Ion ImplantaUon
Anneal
Alignment and etching accuracy (sampling by lot)
Layer resistance (sampling by lot)
Contact
Hole
DeposlUon
Photo uthography
Deposit thickness (aampllng by lot)
,Alignment and etching accuracy (sampling by lot)
MetalllzaUon
Metal DeposlUon
Photo Uthography
Alloy
Metal thickness (sampling by lot)
Alignment and etching accuracy (sampling by lot)
Paramel~c tesl
(sampling by lot)
PasslvaUon
DeposlUon
Photo Uthography
WalerSort
ConIacl hole and rnetalllzaUon
2-10
Deposft thickness (sampling by lot)
Alignment and etching accuracy (sampUng by lot)
Electrical _
steps are repeated \WIoa.
_I)."""
NEe
Appendix 1B.
Reliability and Quality Control
Typical QC Flow for PLCC Assemblyflest
InspecUon of Manufactu~ng CondlUons
Procass/Mate~als
InspecUon
Item
Frequency
Instrument
Inspection of Manufacturing Qualities
Inspected
by
InspacUon
Item
Frequency
Instrument
Inspected
by
Wafer Visual
1000/.
Naked Eye
Operator
So~Wafers
1
2
Wafer Visual
3
Dicing
4
Break and Expand
5
Ole VlsuailnspacUon
Table Spaed
01 Water
Blede Height
Every
Shift
Indicators
Gauges
P.C.
Sawing
Dimensions
Before
Running
Mlcroscopa
With AHer
.Eyeplece
Operator
Wafer Break
CondlUons
Every
Shift
Indicators
Gauges
P.C.
Wafer Visual
1000/.
Naked Eye
Operator
Ole
Visual
Every Lot
Sampling
(Or 100%)
Mlcroscopa
Operator
Ole VIsual
Epoxy
Coverage
Every
Magazine
Naked Eye
Oparator
Every Shift
MlclDScopa
Wafer Expand
Conditions
Lead Frames
Ole Attached
Conditions
7
Ole Attached
Temparature
Epoxy Cure
(Not Done for Gold
Ole Attached product)
Heat
Temperature
N2Aow
Every
Shift
Indicators
Gauges
P.C.
8
Shear
Strength
Every
Shift
Bonding
Conditions
Every
Shift
Indicators
P.C.
VIsual
Every
Magazine
Mlcroscopa
Oparator
Temperature
Every
Week
Thennocouple
P.C.
Wire Pull
Test
Every
Shift
Tension
Gauge
Oparator
Ole
VIsual
Every Lot
Sampling
(Or 100%)
Mlcroscopa
Inspector
VIsual
1000/.
Naked Eye
Operator
VIsual
Every Lot
Naked Eye
Oparator
6
9
10
AneWlre
Wire Bonding
Every
Shift
Indicators
Thennocouple,
Potentiometer
P.C.
end
Dynamometer Operator
PotenUometer
11
~
13
Pre-Seal VIsual
InspacUon
Molding Compound
Molding
Temparature
of Pellet,
ExplraUon Date
Temparature
Proftle of
Ole Sat
Thennocouple
P.C.
Every Shift Thennocouple,
Potentiometer
P.C.
Every
Shift
Preheat
Temperature
Pressure
Cure TIme
14
Mold Aging
Temperature
Every Shift
Indicator
P.C.
Indicators
P.C.
Deftashlng
Deftashlng
Conditions
Every Shift
15
TltraUon
Tech.
ConcentraUon Every Week
Density
16
PlaUng
Every Week Density Meter
Tech.
Water Jet
Pressure
EveryDay
Gauge
Tech.
PlaUng
CondlUons
EveryDay
Indicators
P.C.
TltraUon
Tech.
ConcentraUon Every Weak
83RD-1615B
2-11
ftt{EC
Reliability and Quality Control
Appendix 1B.
Typical QC Row for PLCC Assemblyffest (cont)
Inspection of Manufaclurtng CondIUons
ProcesslMaterials
Inspection
Item
17
~
Martdng Ink
Marking
20
Mark Cure
21
Lead Forming
22
Anal Assembly InspecUon
23
Arst Electrical SorUng
24
Bum-In (When Necessary)
25
Arst E1ectrtcal Sorting
26
Inspection of Manufaclurtng Qualilas
Inspected
InspecUon
by
Item
ReUabHlty Assurance Test
In-Warehouse InspecUon
Frequency
Instrument
Inspected
by
VIsual
PlatIng
ThIckness
ComposlUon
Solderability
Every Lot
Naked Eye
Technician
Every Lot
Every Lot
OnceIDay
X·ray
X-ray
Naked Eye
Technician
Technician
Technician
Marldng
Conditions
Every Shift
Indlcalora
P.C.
VIsual
Every Lot
Naked Eye
Operator
T~rature
Every
Thannocouple
P.C.
Marking
Permanency
TwlcelShlfi
AutomeUc
Tester
Operator
Test Jig.
Caliper
Operator
Visual
Every Lot
Naked Eye
Operator
VIsual
Every Lot
Magnifying
Lamp
Operator
Electrlcel
Charactertstlcs
100'Y.
ICTesler
Operator
EIectrtcaI
100%
ICTesler
Operator
EIectrtcaI
Charactertstlcs
Every Lot
ICTester
Inspector
Visual (MaJor)
Every Lot
Naked Eye
end
MICIOSCOpe
Inspector
Visual (Minor)
Every Lot
Naked Eye
Inspector
ShIft
Dimensions
27
Inslrument
PIsUng Inspec1lon
19
26
Frequency
Every Shift
(Bcifore
Rumlng)
P.M. Check
EveryDay
P.M. Jig.
Sample
Check
Before
TesUng
Test
Samples
Operator
Operator
Bum-In
Conditions
Every
Betch
Indicator
P.C.
EveryDay
P.M. Jig.
Before
TesUng
Test
Samples
Operator
Operator
Charactertsucs
Every
Month
Every Dey
P.M. JIg.
Before
TesUng
Test
Samples
Warehousing
83RD-761B1
2-12
NEe
Reliability and Quality Control
Appendix 2. Typical Reliability Assurance Tests
Test
High-temperature operating/bias life (Note 1)
High-temperature storage life (Note 1)
High-temperature/high-humidity (Note 1)
Symbol
MI L·STD-883C
Method
HTOL/HTB
laOS
TA
HTSL
1008
TA = 150°C (17S0 or 200°C in some cases)
TA
17H
High-humidity storage life (Note 1)
Pressure cooker (Note 1)
PCT
17C
12SoC; Voo specified per device type
= 8SoC; RH = 85%; Voo = S.S V
TA = 8SoC; RH = 85%
HHSL
Temperature cycling (Note 1)
Test Conditions
=
TA
=
12SoC; P = 2.S atm; RH
1010
-65°C to
+ lS00C;
=
100%
1 hour/cycle
Lead fatigue (Note 2)
CS
2004
90-degree bends; S bends without breaking
Solderability (Note S)
C4
200S
2S00C; 5 sec; rosin base flux
Soldering heal/temperature cycle/
thermal shock (Note 1)
C6
1010
1011
(Note 4)
10 sec @ 2S00C; rosin base flux
Ten l-hour cycles @ -6SoC to + lS0°C
Fifteen la-minute cycles @ O°C to + 100°C
Notes:
(1) Electrical test per data sheet is performed. Devices that exceed
the data sheet limits are considered rejects.
(2) Broken lead is considered a reject.
(S) Less than 95% coverage is considered a reject.
(4) MIL-STD-7S0A, method 20S1.
Appendix 3. New Product/Process Change Tests
Newly
Developed
Product
Shrink
Die
New
Package
Test
Sample Size
Wafer
Assembly
High-temperature
operating/bias life
20 - 50 pieces;
1 -lots
a
a
a
a
a
See appendix 2;
1000H
High-temperature
storage life
10 - 20 pieces;
1 - Slots
a
a
a
a
a
T = lS0°C (plastic);
T = 17SoC (ceramic);
1000H
High-temperature/
high-humidity bias life
(plastic package)
20 - SO pieces;
1 - Slots
a
a
a
a
a
See appendix 2;
1000H
Pressure cooker
(plastic package)
10 - 20 pieces;
1 - Slots
a
a
a
a
a
See appendix 2; 288H
Thermal environmental
10 - 20 pieces;
1 - Slots
a
x
a
x
a
See appendix 2
Mechanical environmental
(ceram ic package)
10 - 20 pieces;
1 - Slots
a
x
a
X
a
20G, 10 - 2000Hz;
1500G, O.S ms;
20000G, 1 min
Lead fatigue
S pieces; 1 - 3
lots
X
X
X
See appendix 2
Solderability
5 pieces; 1 - S
lots
X
X
X
See appendix 2
ESD
20 pieces; 1 - S
lots
a
0
a
X
(1) C = 200 pF, R
(2) C = 100 pF,
R = 1.S k
Long term 17C
10 - 50 pieces;
1 - Slots
a
a
a
a
See appendix 2;
1000 cy
a
Test Conditions
=
a
Notes:
0: Performed.
X: Perform if necessary.
-: Not performed.
2-13
•
Reliability and Quality Control
Appendix 4.
Failure Analysis Flowchart
1+-----
InforrnaUon ""Iuested
• FaBul8 slluaUon:
where, how, when, why
• Ddac funcUon tesIIng
by testar/Curvetracer
Vas
• Test correlallon
may be needed
• Specffic tests: X-I8Y nuoroscope,
hennetlcal test, dew-polnl test,
curvell8cer check, etc.
• Decapsulation, Intemal visual
check, electltcal maasurement,
clrcuR analysis
• EtchIng Iho passlvaHon, etc.
SEM, XMA, Cross-sectIon, etc.
• EstlmaUon of causes
• Countenneasuras
• Corrective AcUon
2-14
ttlEC
f't{EC
Digital Signal Processors
ttfEC
Digital Signal Processors
Section 3
Digital Signal Processors
I'PD17C20A, 1720A, 17P20
Digital Signal Processors
3a
I'PD17C25n7P25
Digital Signal Processor
3b
I'PD17220, 77P220
24-Bit Fixed-Point Digital Signal Processor
3c
I'PD17230A, 17P230
32-Bit Floating-Point Digital Signal Processor
(150 ns cycle time)
3d
I'PD17240
32-Bit Floating-Point Digital Signal Processor
(90 ns cycle time)
3e
I'PD7781 0
Modem Digital Signal Processor
3f
I'PD7281
Image Pipelined Processor
39
I'PD9305
Memory Access and General Bus Interface for
the/JPD7281
3h
t-IEC
~PD77C20A,7720A,77P20
NEG Electronics Inc.
Description
The pPD77C20A, pPD7720A, and pPD77P20-three signal processing interface (SPI) chips that are functionally the same-are advanced architecture microcomputers optimized for signal processing algorithms.
Their speed and flexibility allow these SPls to efficiently implement signal processing functions in a wide
range of environments and applications.
The 7720A SPI, a revision of the 7720, the original mask
ROM chip, uses a third less power than the 7720.
The 77C20A is a CMOS pin-for-pin compatible version
of the NMOS version, 7720A. This advanced architecture CMOS microcomputer has power requirements 80
percent less than the 7720A, making the 77C20A appropriate for portable applications and other designs
requiring low power and low heat dissipation.
Digital Signal Processors
- Data ROM (510 x 13 bits)
- Data RAM (128 x 16 bits)
o 16 x 16-bit multiplier; 31-bit product with every
instruction
o Dual 16-bit accumulators
o External maskable interrupt
o Four-level stack for subroutines and/or interrupt
o Multiple I/O capabilities
-Serial: 8- or 16-bit (480 ns/bit)
- Parallel: 8- or 16-bit
-DMA
o Compatible with most pPs, including:
-pPD8080
-pPD8085
- pPD8086/88
-pPD780 (Z8Q®)
Minor differences between 7720A and 77C20A are described in the Instruction Timing section.
o Single +5-volt power supply
The 77P20 is an ultraviolet erasable and electrically
programmable (EPROM) version of the 7720A. Program
and data ROM, masked for the 7720A, are implemented
in EPROM for the 77P20. The 77P20 is useful in prototype applications or in systems where product quantities are insufficient for masked ROM development.
o Extended temperature range
Since the inception of 7720 and its companion EPROM
version, 77P20, there have been several mask revisions
to improve manufacturability and function. A 77P20
must always be used to verify the functions of a user's
system before ROM code for 77C20A or 7720A is
submitted, but certain early versions of 77P20 must not
be used for final verification. Refer to the section on
pPD77P20 for details.
Features
o Low-power CMOS: 24 mA typical current use
(77C20A)
o Fast instruction execution: 240 ns with 8.333-MHz
clock
o 16-bit data word
o Multioperation instructions for fast program
execution: multiply, accumulate, move data, adjust
memory pointers-all in one instruction cycle
o Modified Harvard architecture with three separate
memory areas
- Program ROM (512 x 23 bits)
o NMOS technology (7720A, 77P20)
Applications
o Portable telecommunications equipment
o Digital filtering
o High-speed data modems
o Fast Fourier transforms (FFT)
o Speech synthesis and analysis
o Dual-tone multi frequency (OTMF) transmitters/
receivers
o Equalizers
o Adaptive control
o Numerical processing
Performance Benchmarks
o Second-order digital filter (biquad): 2.21 ps
o Sin/cos of angles: 5.16ps
o piA law to linear conversion: 0.49 ps
o FFT
- 32-point complex: 0 7 ms
-64-point complex: 1.6 ms
Z80 is a registered trademark of Zilog Corporation.
NEe
pPD77C20A, 7720A, 77P20
Ordering Information
Part Number
Package
J1PD77C20AC
28-pin plastic DIP
32-PinSOP
Max
Frequency
of Operation
Normal
Temperature
Range
NC
8.33 MHz
-40 to +85'C
DACK
Ao
DRO
C§
Po
Ri5
NC
VCC
VCC
ALK
28-pin PLCC
AL
44-pin PLCC
P1
WR
AGW
32-pin SOP
Do
SORa
J1PD7720AC
28-pin plastic DIP
8.33 MHz
-10 to +70'C
J1PD77P20D
28-pin cerdip
8.196 MHz
-10 to +70'C
Pin Configurations
28-Pin DIP, Plastic and Ceramic
NCNppNCC (1)
D1
SO
D2
SI
D3
SOEN
D4
SIEN
DS
SCK
D6
INT
D7
GND
ClK
GND
NC
RST
83RD-7448A
VCC
DACK
Ao
DRO
C§
Po
lID
P1
WR
Do
SORa
D1
SO
44-PinPLCC
o 1t5
r..l UU
r..l
00:
« () ()
of/) ()
za..ooz»z«oz
()
D2
SI
D3
SOEN
D4
SIEN
NC
Ds
SCK
Ri5
D6
INT
WR
D7
RST
SORa
GND
ClK
SO
NC
Not•• :
(1) No connection: 77C20A, 7720A
Must be connected for EPROM version; consult 77P20 specifications.
83RD-7364A
SI
NC
31
SOEN
SIEN
NC
28-PinPLCC
83RO-7365A
CS
SCK
AO
INT
VCC
NC
o
RST
ClK
GND
D7
D6
49NR-494A
2
NEe
~PD77C20A,7720A,77P20
Pin Identification
DRQ (DMA Request)
Symbol
This output signals that the SPI is requesting a data
transfer on the data bus.
Function
Status/data register select input
CLK
Single-phase master clock input
CS
Chip select input
Three-state I/O data bus
DACK
DMA request acknowledge input
DRQ
DMA request output
INT
Interrupt Input
General-purpose output control lines
RD
Read control signal input
RST
Reset input
SCK
Serial data I/O clock input
SI
Serial data input
SIEN
Serial input enable input
SO
Three-state serial data output
SOEN
Serial output enable input
SORQ
Serial data output request
WR
Write control signal input
GND
Ground
INT (Interrupt)
A low-to-high transition on this pin executes a call
instruction to location 100H if interrupts were previously enabled.
Po, P1
These pins are general-purpose output control lines.
RD (Read Control Signal)
This input latches data from the data or status register
to the data port where it is read by an external device.
RST (Reset)
This input initializes the SPI internal logic and sets the
PC to O.
SCK (Serial Data I/O Clock)
Vee
+5 V power supply
When thi.s input is high, a serial data bit is transferred.
NC/Vpp/Vee
No connection (77C20A, 7720A)/
programm ing voltage (77P20)
SI (Serial Data Input)
PIN FUNCTIONS
AO
(Status/Data Register Select)
This input selects data register for read/Write (low) or
status register for read (high).
CLK
This is the single-phase master clock input.
CS (Chip Select)
This input enables data transfer through the data port
with RD or WR.
Do-D7 (Data Bus)
This three-state I/O data bus transfers data between
the data register or status register and the external
data bus.
DACK (DMA Request Acknowledge)
This pin inputs 8- or 16-bit serial data words from an
external device such as an AID converter.
SIEN (Serial Input Enable)
This input enables the shift clock to the serial input
register.
SO (Serial Data Output)
This three-state port outputs 8- or 16-bit data words to
an external device such as a D/A converter.
SOEN (Serial Output Enable)
This input enables the shift clock to the serial output
register.
SORQ (Serial Data Output Request)
This output specifies to an external device that the
serial data register has been loaded and is ready for
output. SORQ is reset when the entire 8- or 16-bit word
has been transferred.
This input indicates to the SPI that the data bus is ready
for a DMA transfer (DACK = CS and Ao = 0).
3
ttiEC
pPD77C20A, 7720A, 77P20
WR (Write Control Signal)
NCNppNee
This input writes data from the data port into the data
register.
This pin is not internally connected in the 77C20A and
772OA. In the 77P20, this pin inputs the programming
voltage (Vpp) when the part is being programmed.
GND
This is the connection to ground.
Vee (Power Supply)
This pin is the
This pin must be connected to Vee for proper 77P20
operation. Consult the section on the pPD77P20 for
details.
+ 5·volt power supply.
Block Diagram
DACK
DMA
Interface
Logic
ORO
Serial
110
Read Write
Control Logic
AD
WR
Flag A
Flag B
S
A
1
S
B
1
S
A
0
S
B
0
C
A
C
B
;';';=:
Z
A
Z
B
cs
0
V
A
0
1
0
Data
0
V
B
0
V
B
S10x 13
1
0
X.-
Ao
ROM
Po
P1
D
INT_
VCCGND_
Interrupt
83RD-7366B
4
t-IEC
FUNCTIONAL DESCRIPTION
The primary bus (unshaded in the block diagram)
makes a data path between all of the registers (including I/O), memory, and the processing sections. This bus
is referred to as the lOB (internal data bus). The multiplier input registers K and L can be loaded not only
from the lOB but alternatively via buses (darkened in
the block diagram) directly from RAM to the K register
and directly from data ROM to the L register. Output
from the multiplier in the M and N registers is typically
added via buses (shaded in the block diagram) to
either accumulator A or B as part of a multioperation
instruction.
The SPI is a complete 16-bit microcomputer on a single
chip. ROM space provides program and coefficient
storage; the on-chip RAM may be used for temporary
data, coefficients, and results. A 16-bit arithmetic/logic
unit (ALU) and a separate 16 x 16-bit, fully-parallel
multiplier provide computational power. This combination allows the implementation of a "sum of products"
operation in a single 240-ns instruction cycle. In addition, each arithmetic instruction allows a number of
data movement operations to further increasethroughput.
Two serial I/O ports interface to codecs and other
serial-oriented devices; a parallel port provides both
data and status information to conventional microprocessors. Handshaking signals, including DMA controls,
allow the SPI to act as a sophisticated programmable
peripheral as well as a standalone microcomputer.
MEMORY
Memory is divided into three types: instruction ROM,
data ROM, and data RAM. The 512 x 23-bit words of
instruction ROM are addressed by a 9-bit program
counter that can be modified by an external reset,
interrupt, call, jump, or return instruction.
The data ROM is organized in 510 x 13-bit words that are
addressed through a 9-bit ROM pointer (RP register).
The RP may be modified simultaneously with arithmetic instructions so that the next value is available for
the next instruction. The data ROM is ideal for storing
the necessary coefficients, conversion tables, and
other constants for your processing needs. .
Do not use data ROM locations 0 and 1 in the 77C2OA
or 7720A. These locations are reserved for storage of
test pattern data (When submitting code, set these
locations to 0). Note that 77P20 allows use of these
locations, but using them is not advised.
pPD77C20A, 7720A, 77P20
The data RAM is 128 x 16-bit words and is addressed
through a 7-bit data pointer (DP register). The DP has
extensive addressing features that operate simultaneously with arithmetic instructions, eliminating additional time for addressing or address modification.
ARITHMETIC CAPABILITIES
One of the unique features of the SPI's architecture is
its arithmetic facilities. With a separate multiplier, ALU,
and multiple internal data paths, the SPI is capable of
carrying out a multiply, an add, or other arithmetic
operation, and a data move between internal registers
in a single instruction cycle.
AW
The ALU is a 16-bit two's complement unit capable of
executing 16 distinct operations on virtually any of the
SPI's internal registers, thus giving the SPI both speed
and versatility for efficient data management.
Accumulators (ACCA/ACCB)
Associated with the ALU are two 16-bit accumulators,
each with its own set of flags, which are updated at the
end of eaph arithmetic instruction (except NOP). Table
1 shows the ACC A/B flag registers. In addition to zero
result, sign, car'ry, and overflow flags, the SPI incorporates auxiliary overflow and sign flags (SA1, 5B1, OVA1,
OVB1). These flags enable the detection of an overflow
condition and maintain the correct sign after as many
as three successive additions or subtractions.
Table ,_ ACC AlB Rag Registers
Flag A
SAl
SAO
CA
ZA
OVA1
OVAO
Flag B
SBl
SBC
CB
ZB
OVBl
OVBC
Sign Register (SGN)
When OVA 1 is set, the SA 1 bit will hold the corrected
sign of the overflow. The SGN register will use SA1 to
automatically
generate
saturation
constants
7FFFH(+) or 8000H(-) to permit efficient limiting of a
calculated value. The SGN register is not affected by
arithmetic operations on accumulator B, but flags SB 1,
5BO, CB, ZB, OVB1, and OVBO are affected.
Multiplier
Thirty-one bit results are developed by a 16 x 16-bit
two's complement multiplier in 240 ns. The result is
automatically latched to two 16-bit registers, M and N,
at the end of each instruction cycle. The sign bit and 15
higher bits are in M and the 15 lower bits are in N; the
5
•
I
t-lEC
pPD77C20A, 7720A, 77P20
LSB in N is zero. A new product is available for use after
every instruction cycle, providing significant advantages in maximizing processing speed for real-time
signal processing.
Serial I/O
The SPI contains a four-level program stack for efficient
program usage and interrupt handling.
The two shift registers (SI, SO) are softwareconfigurable to single- or double-byte transfers. The
shift registers are externally clocked (SCI<) to provide a
simple interface between the SPI and serial peripherals
such as AID and D/A converters, codecs, or other SPls.
Figure 2 shows serial I/O timing
Interrupt
Figure 1. BPI Communication Ports
Stack
The SPI supports a single-level interrupt. Upon sensing
a high level on the INT pin, a subroutine call to location
100H is executed. The EI bit of the status register
automatically resets to D, disabling the interrupt facility
until it is reenabled under program control.
,_oo{
Interface
10 Extemal
Data Bus
INPUT/OUTPUT
General
DMA
Interface
The SPI has three communication ports as shown in
figure 1: two serial and one 8-bit parallel, each with its
own control lines for interface handshaking. Parallel
port operation is software-configurable to be in either
polled mode or DMA mode. A general-purpose, twoline output port rounds out a full complement of interface capability.
6
-
SPI
Do-D7
AD
so
WR
SORO
SOEN
CS
SCK
AO
SI
SIEN
Interrupt
Reset
RST
Clock
ClK
Po
P,
l~oo
Interface
} General
Purpose
OutpUt Port
83RD-7367A
fttIEC
pPD77C20A,7720A,77P20
Figure 2. Serial If0 Timing
SCK
-.II
,-------------
SORO _ _
\~--------~S)rS----------~1
Output Data _ _H...;i9;...h_Z_--<
SOACK*
[Note 3]
,-------------------------,
I
I
J
(Next Data Set)
I
I
r------,
so Load * ~
I
I
I
I
,
I
Input Data
\~- _ _ _ _ _--,I
~~*
n
---------------------------------------------~
~----
L
SlACK *
Notes:
[I] Data clocked out on falling edge of SCK.
[2] Data clocked in on rising edge of SCK.
[3] Broken line denotes consecutive sending of next data.
[*] Internal signal
83AD-13688
Parallel I/O
DMA Mode Option
The 8-bit parallel I/O port may be used for transferring
data or reading the SPI's status as shown in table 2.
Data transfer is handled through a 16-bit data register
(DR) that is software-configurable for double- or singlebyte data transfers. The port is ideally suited for operating with 8080, 8085, and 8086 processor buses and
may be used with other processors and computer
systems.
Parallel data transfers may be controlled (optionally)
via DMA control lines ORO and DACK OMA mode
allows high-speed transfers and reduced processor
overhead. When in DMA mode, DACK input resets ORO
output when data transfer is completed. OACK does
not affect any status register bit or flag bit.
7
NEe
pPD77C20A, 7720A,7.7P20
Table 2. Parallel R/W Operation
Table 3. Status Register Rags (cont)
cs
Operation
Flag
Description
No effect on internal operation; 00-07 are
at high impedance levels.
DRC (DR controQ
DRC = 0 (16-bit mode)
DRC = 1 (a-bit mode)
SOC (SO ControQ
SOC = 0 (16-blt mode)
SOC = 1 (6-bit mode)
Ag
WR
RD
X
X
X
X
X
0
0
0
0
0
Data from 00-07 is latched to DR
(Note 1)
0
Illegal (SR Is read only)
0
0
X
0
SIC (SI
Contents of DR are output to 0 0-07
(Note 1)
0
0
0
Eight MSBs of SR are output to 00-07
0
Illegal (may not read and write
simultaneously)
Notes:
Status Register
The status register (figure 3) is a 16-bit register in which
the eight most significant bits may be read by the
system's microprocessor for the latest parallel data I/O
status. The ROM and DRS bits can only be affected by
parallel data moves. The other bits can be written to (or
read) by the SPI's load immediate (LDI) or move (MOV)
instructions. The EI bit is automatically reset when an
interrupt is serviced.
Figure 3. Status Register (SR)
15
RQM
I
14
USFI
I
13
USFO
I
12
11
10
DRS
DMA
DRC
I
9
SOC
I
a
SIC
MSB
7
6
5
4
3
2
EI
o
o
o
o
o
o
PI
PO
LSB
Table 3. Status Register Rags
Flag
Description
RQM (Request
for Master)
A read or write from DR to lOB sets RQM =
1.
An external read (write) resets RQM = O.
USFI and USFO
(User Flags 1
and 0)
General-purpose flags which may be read by
an· external processor for user-defined
signaling
DRS (DR Status)
For 16-bit DR transfers (DRC = 0). DRS = 1
after first a bits have been transferred. DRS
= 0 after all 16 bits have been transferred.
DMA (DMA Enable)
DMA
DMA
8
SIC = 0 (IS-bit mode)
SIC 1 (a-bit mode)
=
= 0 (interrupts disabled)
= 1 (interrupts enabled)
EI (Enable
Interrupij
EI
EI
PO, PI
(Ports 0 and 1)
PO and PI directly control the state of
output pins Po and PI
INSTRUCTIONS
(1) Eight MSBs or a LSBs of data register (DR) are used, depending
on DR status bit (DRS). The condition of DACK = 0 is equivalent
toAg = CS = o.
I
Contro~
= 0 (Non-DMA transfer mode)
= 1 (DMA transfer mode)
The SPI has three types of instructions: Load Immediate, Branch, and the multifunctionOP instruction. Each
type takes the form of a 23-bit word and executes in
240ns.
Instruction Timing
To control the execution of instructions, the external
a-MHz clock is divided into four phases for internal
execution. The various elements of the 23-bit instruction word are executed in a set order. Multiplication
automatically begins first. Also, data moves from
source to destination before other elements of the
instruction. Data being moved on the internal data bus
(lOB) is available for use in ALU operations (if P-select
field of the instruction specifies lOB). However, if the
accumulator specified in the ASL field is also specified
as the destination of the data move, the ALU operation
becomes an NOP as the data move supersedes the
ALU operation.
Pointer modifications occur at the end of the instruction cycle after their values have been used for data
moves. The result of multiplication is available at the
end of the instruction cycle for possible use in the next
instruction. If a return is specified as part of an OP
instruction, it is executed last.
An assembly language OP instruction may consist of
what looks like one to six lines of assembly code, but all
of these lines are assembled together into one 23-bit
instruction word. Therefore, the order of the six lines
makes no difference in the order of execution described above. However, for understanding the SPl's
operation and to eliminate confUSion, write assembly
code in the order described; that is, data move, ALU
operations, data pointer modifications, and then
return.
ttlEC
pPD77C20A,7720A,77P20
Minor differences exist between 7720A and 77C20A in
internal instruction execution timing. Using normal
programming instruction statements, the differences
will not appear. However, an instruction such as the
following will yield a difference between NMOS and
CMOS operation.
Besides the arithmetic functions, these instructions
can also (1) modify the RAM data pointer DP, (2) modify
the data ROM pointer RP, and (3) move data along the
on-chip data bus from a source register to a destination
register. The possible source and destination registers
are listed in tables 6 and 7, respectively.
OP MOV @MEM,B XOR ACCB, RAM
The difference in the two instructions of this type is that
AT executes a subroutine or interrupt return at the end
of the instruction cycle, but the OP does not. Tables 8,
9, 10, and 11 show the ASL, DPL, DPH, and RPDCR
fields, respectively.
The instruction, which is acceptable using the NEC
assembler (AS77201), has an inherent conflict in that
data is simultaneously being moved into memory and
fetched in one instruction. ALU instructions involving
either ACCA or ACCB should not be used. In summary,
observe the following rules.
(1) DST should not be @MEM when PSEL is RAM.
22
(2) When SRC is NON, DST must be @NON.
21
H
HOP
(3) A should not be used as both DST and ASL.
(4) B should not be used as both DST AND ASL.
I
OP/RT Instruction Field Specification
11
9
DPH-M
20
19
I P-Select I
15
18
ALU
14
12
13
IASLI
DPL
= 00; RT = 01
8
I•I
4
7
o
3
SRC
DST
• RPDCR
Figure 4 illustrates the OP/RT instruction field specification. There are two instructions of this type, both of
which are capable of executing all ALU functions listed
in table 4. The ALU functions operate on the value
specified by the P-select field (see table 5).
Table 4. AWField
0 18
0,7
0,6
0 15
ALU Function
NOP
0
0
0
0
No operation
0
0
Mnemonic
OR
0
0
AND
0
0
XOR
0
0
SUB
0
0
ADD
0
0
SBB
0
ADC
0
0
DEC
0
0
INC
0
0
CMP
0
SHRl
0
0
SHL2
0
XCHG
/::,.
-
0
0
SHL1
SHL4
0
0
0
SA1,S81
SAO, SBO
OR
x
AND
x
Exclusive OR
CA,CB
ZA,ZB
OVA1, OVBl
OVAO, OVBO
6.
0
6.
0
0
6.
0
6.
0
0
x
6.
0
6.
0
0
Subtract
6.
6.
6.
6.
6.
6.
ADD
6.
6.
6.
6.
6.
6.
Subtract with borrow
6.
6.
6.
6.
6.
6.
Add with carry
6.
6.
6.
6.
6.
6.
Decrement ACC
6.
6.
6.
6.
6.
6.
Increment ACC
6.
6.
6.
6.
6.
6.
Complement ACC
(one's complement)
x
6.
0
6.
0
0
1-Bit right shift
X
6.
6.
/::,.
0
0
I-Bit left shift
x
/::,.
/::,.
/::,.
0
0
2-Bit left shift
x
/::,.
0
/::,.
0
0
4·Bit left shift
X
/::,.
0
/::,.
0
0
8-Bit exchange
x
/::,.
0
/::,.
0
0
May be affected, depending on the results.
Previous status can be held.
•
.
Figure 4. OPIRT Instruction Field
0 Reset
x Indefinite
9
•
.
NEe
~PD77C20A,7720A,77P20
Table 5. P-Select Field
Mnemonic
0 20
019
RAM
0
0
IDB
0
M
Table 7. DST Field (cont)
0
AWlnput
Mnemonic
RAM
@SOL
Internal Data Bus (Note 1)
M Register
N Register
N
03
02
01
Do
1
0
0
0
@SOM
0
0
@K
0
@KLR
0
SO serial out MSB (Note 2)
@KLM
0
(1) Any value on the on-chip data bus. Value may be selected from
any of the registers listed in tabie 6 source register selections.
@L
0
06
04
0
0
0
0
0
0
B
0
0
TR
0
0
DP
0
0
0
NON
0
A
RP
0
RO
0
SGN
0
0
0
0
0
0
DRNF
0
SR
0
SIM
0
SiL
0
K
0
Notes:
Hi RAM .... K, lOB .... L (Note
4)
No register
RAM
No register
(1) LSB is first bit out.
ACCA (Accumulator A)
(2) MSB is first bit out.
ACCB (Accumulator B)
(3) Internal data bus to K, and ROM to L register.
TR temporary register
(4) Contents of RAM address specified by OP6 = 1, is placed in K
register, lOB is piaced in L (that is, 1, OPs, OP4 OPa-DPo).
DP data pointer
RP ROM pointer
TableS. ASLFieid
RO ROM output data
Mnemonic
SGN sign register
ACCA
0
DR data register
ACCB
0
SR status register
Table 9. OPLField
SI serial in MSB (Note 2)
Mnemonic
SI serial in LSB (Note 3)
K register
L register
OPOEC
0
DR
Source Regl ster
0
L(Mult)
@MEM
Os
07
K(Mult)
0
@NON
Mnemonic
0
lOB .... K, ROM -+ L (Note 3)
Notes:
Table 6. SRCField
Destination Register
SO serial out LSB (Note 1)
ACC Selection
0 14
0
ACCA
ACCB
DR no flag (Note 1)
0
0
L
MEM
RAM
0 13
0 12
OPNOP
0
0
OPINC
0
Low DP Modify (OP3-OPO)
No operation
Increment OPL
0
Decrement DPL
Clear DPL
OPCLR
Notes:
(1) DR to lOB, ROM not set. In OMA, ORO not set.
Table 10. OPHField
(2) First bit in goes to MSB, last bit to LSB.
Mnemonic
011
010
09
High OP Modify
(3) First bit goes to LSB, last bit to MSB (bit reversed).
MO
0
0
0
M1
0
0
Exclusive OR of DPH (DP6"0P4)
with the mask defined by the
three bits (011-D9) of the DPH
field
Table 7. OS T Field
Mnemonic
03
02
01
Do
@NON
0
0
0
0
@A
0
0
0
@B
0
0
@TR
0
0
@OP
0
0
@RP
0
0
@DR
0
@SR
0
10
0
0
M2
0
Destination Register
M3
0
No register
M4
0
ACCA (Accumulator A)
M5
0
ACCB (Accumulator B)
M6
TR temporary register
M7
OP data pointer
RP ROM pointer
0
0
DR data register
SR status register
0
0
fttfEC
Table 11.
pPD77C20A,7720A,77P20
RPDCR Field
Mnemonic
08
RPNOP
o
Table 13. BRCH/CND Fields
RPDEC
RP Operation
Mnemonic 0 20 0 19 0 18 017 0 16 0 15 0 14 D13 Conditions
No operation
JMP
Decrement RP
CALL
1
0
0
o
0
0
0
0
0
No condition
o
0
0
0
0
No condition
0
0
0
CA = 0
o
0
0
o
0
000
o
0
0
0
0
0
0
Jump/Call/Branch
JCA
Figure 5 shows the JP instruction field specification.
Three types of program counter modifications accom·
modated by the processor are listed in table 12. All the
instructions, if unconditional or if the specified condition is true, take their next program execution address
from the next address field (NA); otherwise PC = PC +
1.
JNCB
o
o
o
JCB
o
o
JNZA
o
o
0
0
0
JZA
o
o
o
0
0
0
o
0
0
o
0
0
Forthe conditional jump instruction, the condition field
specifies the jump condition. Table 13 lists all the
instruction mnemonics of the jump/call/branch codes.
BRCH or CND values not in table 13 are prohibited.
JNOVAO
o
o
o
0
JOVAO
o
JNOVBO
o
JOVBO
o
o
o
o
Load Data (LDI)
JNOVAl
o
o
0
o
JOVAl
o
0
0
JNOVBl
o
o
o
o
0
JNCA
JNZB
JZB
Figure 6 shows the LD instruction field specification.
The load data instruction will take the 16-bit value
contained in the immediate data field (ID) and place it
in the location specified by the destination field (DS1)
See table 7.
JOVBl
Figure 5. JP Instruction Field
JNSBO
o
o
o
o
o
JSBO
JNSAl
22
20
17
11 10 1 BRCH 1
o
4 3
13 12
NA
CND
JNSAO
Figure 6.
22
LD Instruction Field
20
5
ID
Table 12.
1-1
BRCH Field
Branch Instruction
o
o
o
o
Unconditional jump
Subroutine call
o
o
3
DST
0
0
0
0
0
0
0
0
0
0
o
0
o
o
o
o
o
o
o
o
o
o
o
JDPLO
o
o
o
o
o
JSBl
o
o
JDPLF
o
ZB = 0
0
OVAO = 0
OVAO = 1
OVBO = 1
0
OVAl = 0
OVAl = 1
OVBl = 0
JNSIAK
JSIAK
o
o
JNSOAK
o
JSOAK
JNROM
o
o
JROM
o
0
SAO=O
SAO = 1
o
SBO = 0
o
SAl = 0
SBO = 1
o
o
SAl = 1
o
o
SBl = 0
SBl = 1
o
o
o
o
o
o
o
o
0
OVBl = 1
0
o
ZA=O
ZA=l
0
0
o
o
0
OVBO = 1
0
1
0
0
0
JNSBl
=
ZB = 1
0
0
JSAl
CB
CB = 1
o
JSAO
CA = 1
0
0
0
DPL = 0
o
SI ACK = 0
o
DPL
=
FH
SlACK = 1
o
o
0
SO ACK = 0
SO ACK = 1
o
ROM = 0
ROM
= 1
Conditional jump
11
NEe
pPD77C20A, 7720A, 77P20
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Capacitance
Supply voilage, Vee
77C2OA
7720A
77P2O
Parameter
Symbol
-0.5 to +7.0 V
-0.5 to +7.0 V
-0.3 to +7.0 V
ClK, SCK
capacitance
c¢
Programming voltage, Vpp (77P2O)
-0.3 to +22V
Input pin
capacitance
Input voltage, VI
77C20A
7720A
77P2O
-0.5 to Vee + 0.5 V
-0.5 to +7.0 V
-0.3 to +7.0 V
Output voltage, Vo
77C20A
7720A
77P20
-0.5 to Vee + 0.5 V
-0.5 to +7.0 V
-0.3 to +7.0 V
Operating temperature, TOPT
77C2OA
7720A,77P20
Output pin
capacitance
Min
COUT
Max
Unit
Conditions
20
pF
fc .. 1 MHz
10
pF
20
pF
-40 to +85'C
-10 to +70'C
Storage temperature, TSTG
-65 to +150'C
Exposing the device to stresses above those listed In Absolute
Maximum Ratings could cause permanent damage. The device is not
meant to be operated under conditions outside the limits described
in the operational sections ofthis specification. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA
= -10 to +70'C; Vee = +5 V ±5%
Parameter
Symbol
Input low voltage
77C2OA
7720A, 77P20
VIL
Input high voltage
77C2OA
7720A,77P20
VIH
ClK low voltage
77C20A
7720A,77P20
VrpL
ClK high voltage
77C2OA
7720A,77P20
VrpH
Output low voltage
VOL
Output high voltage
VOH
Max
Unit
-0.3
-0.5
0.8
0.8
V
V
2.2
2.0
Vee + 0.3
Vee + 0.5
V
V
-0.3
-0.5
0.45
0.45
V
3.5
3.5
Vee + 0.3
Vee + 0.5
V
V
Min
Typ
0.45
2.4
Conditions
V
VIOL
= 2.0mA
V
=-400 jlA
IOH
Input load current
ILIL
Input load current
IUH
10
ILOL
-10
jlA
VOUT = 0.47 V
ILOH
10
jlA
VOUT .. Vee
Output float leakage
Output float leakage
12
-10
t't{EC
pPD77C20A, 7720A, 77P20
DC Characteristics (cont)
Parameter
Symbol
Power supply current
77C20A
7720A
77P20
IcC
Vpp current (17P20 only)
Ipp
Min
Typ
Max
Unit
Conditions
24
120
270
40
170
350
rnA
rnA
rnA
fClK
70
rnA
Program mode max pulse
current (Note 1)
3.0
rnA
Program verify, inhibit (Note 2)
0.5
= 8.192 MHz
Notes:
(1) Vpp = 21 :t 0.5V
(2) For K-Ievel parts:
•
Vpp max = Clcc - 0.6 V) + 0.25 V
Vpp min = ClCC-0.6V) -0.25V
For all other step levels: Vpp max = VCC + 0.25 V
Vpp min = VCC - 0.85 V
AC Characteristics
TA = -10to +70·C; VCC
= +5V :t5%
Parameter
Symbol
ClK cycle time
17C20A,172OA
17P20
¢CY
Min
Typ
120
122
Max
Unit
2000
2000
ns
ns
60
Conditions
Note 4
ClK pulse width
¢D
ClK rise time
CPR
10
ns
Note ,1
ClKfalitime
¢F
10
ns
Note 1
Address setup time for RD
tAR
0
ns
Address hold time for RD
tRA
0
ns
RD pulse width
tRR
250
Data delay from RD
tRo
Read to data floating
tOF
ns
ns
10
150
ns
Cl
100
ns
Cl
Address setup time for WR
tAW
0
ns
Address hold time for WR
tWA
a
ns
WR pulse width
tww
250
ns
Data setup time for WR
tow
150
ns
Data hold time for WR
two
0
ns
RD, WR, recovery time
tfl,f
250
ORO delay
tAM
DACK delay time
tOACK
DACK pulse width
17C20A
7720A
17P20
too
SCK cycle time
SCK pulse width
SCK riselfall time
tRSc/tFSC
150
= 100 pF
= 100 pF
ns
Note 2
ns
Cl
CPO
Note 2
250
250
250
2000
50,000
ns
ns
tSCY
480
DC
ns
tSCK
230
= 100 pF
ns
20
ns
13
[
I
ftlEC
pPD77C20A, 7720A, 77P20
AC Characteristics (cont)
Parameter
Symbol
SORQ delay
tORQ
30
SOEN hold time
tcso
30
tsoc
50
SOEN setup time
SO delay from SCK
= low
Min
tacK
Typ
Max
Unit
Conditions
150
ns
CL = 100pF
ns
ns
150
ns
SO delay from SCK before
1st bit (Note 3)
tOZAQ
20
300
ns
Note 2
SO delay from SCK
tozsc
20
300
ns
Note 2
SO delay for SOEN
tOZE
20
180
ns
Note 2
SOEN to SO floating
tHZE
20
200
ns
Note 2
SCK to SO floating with
SORQ high
tHZSC
20
300
ns
Note 2
SO delay from SCK for
last bit
tHZAQ
70
300
ns
Note 2
SIEN, SI setup time
toc
55
ns
Note 2
30
ns
SIEN, SI hold time
tco
Po, PI delay
top
RST pulse width
tAST
4
CPCY
tiNT
8
CPCY
INT pulse width
CPCY
+ 150
Notes:
(1) Voltage at timing measuring point: 1.0 V and 3.0 V.
(2) Voltage at ac timing measuring point:
VIL .. VOL - 0.8 V
VIH VOH
2.0V
=
=
(3) SO goes out of tristate, but data is not valid yet.
(4) Pulse width Includes ClK rise and fall times. Refer to Clock
Timing Waveform.
14
ns
NEe
pPD77C20A, 7720A, 77P20
Timing Waveforms
DMA Operation
--'
Clock
~A
""""'"
ORO
/
r
83R[).7373A
--
16-Bit Transfer Mode
ClK
••,Ul-737OA
Read Operation
OACK
_ _ _ _ _ _ _ __
AO'CS'~
tAR
F
OACK
ORO
83RD-7374A
tAA
Port Output
. -----~~--'~~--
ClK
""'
83RO-7371A
Write Operation
83RD-7375A
83Rl>7372A
15
t-IEC
pPD77C20A,7720A,77P20
Timing Waveforms (cant)
Serial Output, Case 2
Read/Write Cycle
eo,",
-VtoE«~--------_tR_v==:::::::::l~
13R().73nA
Interrupt
I
OT
'M~}-I
----1toE---'
.
83RO-737BA •
SERIAL TIMING
Serial Output, Case 1
Figure 7 shows serial output timing when SOEN is
asserted in response to SORQ when SCK is low. If
SOEN is held inactive until after SORQ is asserted, and
then SOEN is asserted while SCK is low (SOEN should
be held inactive until the period of t cso after the falling
edge of SCI<), SO will become active but not valid tozso
after the next rising edge of SCK SO will become valid
with the first bit tOOK after the next falling edge of SCK
for use by an external device at the subsequent rising
edge ofSCK
Subsequent bits will be shifted out tOOK after subsequent falling edges of SCK for use at subsequent rising
edges of SCK The last bit to be shifted out will also
follow this pattern and will be held valid tHZRQ after the
corresponding rising edge of SCK at which it is to be
used. SORQ will be held tORQ after this same rising
edge of SCK and then removed. SOEN should be
released at least tsoo before the next falling edge of
SCK
16
Figure 8 shows timing for serial output when SOEN is
asserted in response to SORQ when SCK· is high. If
SOEN is held inactive until after SORQ is asserted, and
then SOEN is asserted while SCK is high (at least tsoo
before the falling edge of SCI<), SO will become active
but not valid tozE after the falling edge of SOEN. SO will
become valid tOOK after the falling edge of SCK for use
by an external device at the subsequent rising edge of
SCK
Note that although figure 8 shows SOEN being asserted during a different SCK pulse than the one in
which SORQ is asserted, it is permissible for these to
occur during the same pulse of SCK as long as SOEN is
still asserted tsoo before the falling edge of SCK The
timing for the second through the last bits is identical to
the timing shown in figure 7.
Serial Output, Case 3
Figure 9 shows output timing when SOEN is active
before SORQ is high. If SOEN is held active before
SORQ is high, data will be shifted out whenever it
becomes available in the serial output register (assuming previous data is already shifted out). In this case,
SORQ will rise tORQ after a rising edge of SCK SO will
become active (but not valid yet) tOZRQ after the same
rising edge of SCK The first valid SO bit occurs tOOK
after the next fall ing edge of SCK for use by an external
device at the subsequent rising edge of SCK
Subsequent bits will be shifted out tOOK after subsequent falling edges of SCK for use at subsequent rising
edges of SCK The last bit to be shifted out will also
follow this pattern and will be held valid tHZRQ after the
corresponding rising edge of SCK at which it is to be
used. SORQ will be held tORQ after this same rising
edge of SCK and then removed.
tt1EC
pPD77C20A, 7720A, 77P20
Figure 7. Serial Output Case 1: SOEN Asserted in Response to SORQ When SCK Is Low
!+----:tSCy'---.,
SCK
tORa
SORa
•
tOCK
SO --------------~
First Bit
Valid
Figure B. Serial Output Case 2: SOEN Asserted in Response to SORQ When SCK Is High
SCK
SORa
so
---------+<1
83RC·738oa
17
I
NEe
I'PD77C20A, 7720A, 77P20
Figure 9. Serial Output Case 3: SOEN Active Before SORQ Is High
SCK
SORO
SOEN--------r-------+---------------~----------~~--~~------~---------
tOZRO
so----~
83RD-7381B
Serial Output, Case 4A
Avoid releasing SOEN in the middle of a transfer (that is,
before the last bit is shifted out), since this will stop the
output shift operation. When SO EN is again asserted,
the remainder of the transfer will be shifted out before
the next transfer can begin. The next transfer will begin
immediately without any indication of the byte!word
boundary. If SO EN is released while SCK is high (figure
10) at leasttsoc before the falling edge of SCK, then SO
will go inactive tHZE after SOEN is released (which may
be before or after the falling edge of SCI<).
Serial Output, Case 48
If SOEN is released while SCK is low (figure 11) at least
tcso after the falling edge of SCK, then the next bit will
be shifted out tocK after the falling edge of SCK for
useat the subsequent rising edge of SCK. SO will then
go inactive tHzsC after this rising edge of SCK.
Note: For all its uses, SOEN must not change state within
Isoc before or Icso after the falling edge of S CK;
otherwise, the results will be indeterminate.
Serial Input
Serial input timing (figure 12) is much simpler than
serial output timing. Data bits are shifted in on the
rising edge of SCK if SIEN is asserted. Both SIEN and
SI must be stable at least toc before and tco after the
rising edge of SCK; otherwise the results will be indeterminate.
Figure 10. Serial Output Case 4A: If SOEN Is Released in the Middle of a Transfer During SCK High
SCK _ _---J/
}=,«=:)----J/
So--------------V-rui-d-/~~~--------~H~i9h~-Z~------------------------83RD-73828
18
t't{EC
pPD77C20A, 7720A, 77P20
Figure 11. Serial Output Case 48: If SliEfIls Released in the Middle of a Transfer During SCK Low
/
SCK
~ -ICSO
/
so
~'OC'l
Valid
~'~~1
Valid
High-Z
83RD-73838
Figure 12. Serial Input
SCK
mu~
I
I
I
f- I-IOC
I
I+--ICO_
V
\
)
Valid
ICO_
IOC
ICO
Sl
(
)
Valid
K
83RD-7384B
Serial Timing Example
Figure 13 shows serial timing of cascaded SPls with a
common SCK. SO from the first SPI equals SI of the
second, and the first SPI's SORQ inverts to become
SIEN of the second. SOEN of the first SPI is always
asserted.
When cascading two SPls in the described configuration, most of the timing involved is directly copied from
the case of serial output with SOEN always enabled
(figure 13). It must be shown that the results will be
suitable for the serial input timing of the second SPI.
(1)
(2)
SORQ(1) is released tORQ after the last useful
rising edge of SCK and is inverted (inverter has
tpHL delay time) to become SIEN(2), which must
remain stable tco after the rising edge of SCK.
tORQ (min) +
tpLH (min) ;::
;::
;::
tpLH (min) ;:: tco (min)
tco (min) - tORQ (min)
30-30
0 (no problem, assuming causality)
Note: This also shows tpH L (min) ~ 0 for the rising edge of
SORQ.
SORQ(1) rises tORQ after a rising edge of SCK, and
it is inverted (inverter has tpHL delay time) to
become SIEN(2), which must be stable toc before
the next rising edge of SCK. It also must not
change until tco after this first rising edge of SCK
as shown by case 2 in figure 8.
tORQ (max)
tpHL (max)
~'!
+ tpHL + toc (min)
:$ tsCY (min)
tsCY (min) - toc (min) - tORQ (max)
:$ 480 - 55 - 150
:$ 275 ns (readily achieved by 74LS14,
for example)
:$
19
NEe
pPD77C20A, 7720A, 77P20
Figure 13. Serial Timing Example
i+----tSCy'---~
:~~-tSCK
SCK (t&2)
S~N(I)--------~------+-------~------------------~7--~r-------t----------
tORO
SORO(I)
SIEN(2)
tOZRO
SO(I) = SI(2)
------------11
Active,
Not Valid
First Sit
Valid
83RD-73858
(3)
80(1) is valid tOCK after a falling edge of 8CK;
since it becomes 81(2), it must be valid toc before
the next rising edge of 8CK,
tOCK (max) + tDC (min) :S tSCK (min)
150 + 55 :S 230
205 :S 230 (this condition is
satisfied)
(4)
80(1) remains valid tHZRQ after the last useful
rising edge of 8CK; since it becomes 81(2), it must
remain valid tCD after this rising edge of 8CK
tHZRQ (min) ~ tco (min)
70 ~ 30 (this condition is satisfied)
Note: The above calculations may need to be adjusted for
rise and fall times, since tsCY and tscK are measured for
midpoints of wave slopes.
I'PD77P20 UV ERASABLE EPROM VERSION
Function
The np20 operates from a single +5-volt power supply
and can accordingly be used in any nC20A/772OA
masked ROM application,
20
Use of Evakit-7720
The following sections describe electrical conditions
that are required for programming the 77P20, However,
the Evakit-7720, NEC's hardware emulator development tool for the nC20A/7720A/77P20, meets the electrical and timing specifications presented below, When
the Evakit-7720 is used for programm ing 77P2O, all data
transfers and formatting are handled automatically by
Evakit's monitor program, Please refer to the Evakit7720(8) User's Manual for programming procedures.
The information presented below in the sections on
Configuration, Operation, and Programming (and the
various subsections) is required only for users who do
NOT intend to use an Evakit to program the 77P20,
Configu ration
Data transfer for programming and reading the internal
ROM is partitioned into three bytes for each 23-bit wide
instruction location and into two bytes for each 13-bit
wide data location, Partitioning of data transfer into
and out of the data port is shown in figure 14,
NEe
~PD77C20A,7720A,77P20
Figure 14. Instruction ROM Format
Figure 17.
MSB
I 22 I 21 I
20 1 19 1 18 117 1 16 1 15 114 1 13 112
I
LSB
111 110
I9 I8 I7 I6 I5
4
I3
2
I1 I0 I
The instruction ROM data is transferred through the
data port as a high byte, middle byte, and low byte as
shown in figure 15. Bit 7 of the middle byte should be
assigned a value of zero. Data is presented to the data
port in a bit-reversed format. The LSB through the MSB
of an instruction ROM byte is applied to the MSB
through the LSB of the data port, respectively.
Figure 16 shows the data ROM format. The data ROM
data is transferred through the dlita port as a low byte
and a high byte as shown in figure 17. Bits 0, 1, and 2 of
the low byte should be assigned a value of zero. Data is
presented to the data port in corresponding order. The
MSB through the LSB of a data ROM byte is applied to
the MSB through the LSB of the data port, respectively.
Initially and after each erasure, all bits of the 77P20 are
in the zero state.
Transfer of Instruction ROM Data
Data Port
7
6
5
4
32
High Byte
15
16
17
18
19
20
9
I 10
111
12
I
I
Low Byte
I
I
6
I
I4
11
12
Low Byte
.I
0
I
3
2
3
I I I
I1 I0 I
8
0
2
7
*
I
I
6
•
I
I
5
.
I
I
In order to read or write the instruction or data ROMs,
the mode of operation of the 77P20 must be initially set.
At the RST trailing edge, the RD, WR, and CS should be
logical zero and the DACK, Ao, and SI signals should be
set to determine the mode of operation accordingly, as
set out in table 14.
8
1
I
I
2
3
22
I 13 I 14 I
I
I
Table 14. pPD77P20 Operation Mode
o
o
o
AO
81
o
o
o
Write mode instruction and data ROM
Read the instruction ROM
o
Read the data ROM
Once set, the 77P20 will remain in the selected mode. A
reset is required to transfer to another mode.
Write Mode
The individual instruction ROM and data ROM bytes are
specified by control signals RD, Ao, SI, and INT as set
out in table 15. Before writing the EPROM location, the
bytes should be loaded accordingly.
Table 15.
RD
Write Mode Specification of ROM
Bytes
Ao
81
INT
0
0
1
0
4
0
Figure 16. Data ROM Format
,
Write instruction byte, high
Write instruction byte, middle
Write instruction byte, low
0
0
0
Write data byte, low
Write data byte, high
LSB
I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 I
..
I
0
MSB
I
I
4
9
0
21
• Set to 0 as dummy data.
112111 110
5
10
* Set to 0 as dummy data.
DACK
Data ROM
Middle Byte
7
High Byte
Operating Modes
Instruction ROM
Figure 15.
Transfer of Data ROM Data
Data Port
Read Mode
The instruction ROM and data ROM bytes are specified
by the control signals RD, P.o, SI, and INT as set out in
table 16. Reading is accomplished by setting the control signals accordingly.
21
pPD77C20A,7720A,77P20
Table 1B- Read Mode Specification of ROM Bytes
SI
INT
Ao
RD
0
0
0
0
0
Read instruction byte, high
0
0
Read instruction byte, low
0
0
Read instruction byte, middle
0
0
Read data byte, high and low
The instruction ROM and data ROM are addressed by
the 9-bit program counter and the 9-bit ROM pointer
respectively. The PC is reset to OOOH and is automatically incremented to the end address 1FFH. The RP is
reset to 1FFH and is automaticaly decremented to
OOOH.
Erasing
Programming can occur only when all data bits are in
an erased or low (0) level state. Erase 77P20 programmed data by exposing it to light with wavelengths
shorter than approximately 4000 angstroms. Note that
constant exposure to direct sunlight or room level
fluorescent lighting could erase the 77P20. Consequently, if the 77P20 will be exposed to these types of
lighting conditions for long periods of time, mask its
window to prevent unintentional erasure.
NEe
set to a TTL high-level signal. The device is now in a
programming mode and will stay in this mode, allowing
ROM locations to be sequentially programmed.
Programming Mode of Instruction ROM. Instruction
ROM locations are sequentially programmed from address OOOH to address 1FFH. The location address is
incremented by the application of CLK for a duration of
tCY' Data bytes for each location as specified by
control signals RD, Ao, SI, and INT (table 15) are clocked
into the device by the falling edge of RD.
After the three bytes have been loaded into the device,
Vpp is raised to 21 V ±O.S V, tvs prior to CS/PROG
transitioning to a TTL high-level signal. Vpp is held for
the duration of tpRPR plus tpRV before returning to the
Vcc level. After tpRCL, the instruction ROM address can
be incremented to program the next location. Figure 18
shows the programming mode of instruction ROM
timing.
Programming Mode of Data ROM. Data ROM locations
are sequentially programmed from address 1F FH to
address OOOH. The location address is decremented by
the application of CLK for tCY' The data,Eytes for each
location as specified by control signals RD, Ao, SI, and
INT are clocked into the device by the falling edge of
RD.
The recommended erasure procequre for the 77P20 is
exposure to ultraviolet light with wavelength of 2537
angstroms. The integrated dose (i.e., UV intensity x
exposure time) for erasure should not be less than 15
W·s/cm 2 . The erasure time is approximately 20 minutes
using an ultraviolet lamp with a power rating of
12,000/1W/cm2 .
After the two bytes have been loaded into the device,
Vpp is raised to 21 V, ±O.S V tVPR prior to CS/PROG
transitioning to a TTL high-level signal. Vpp is held for
the duration of tpRPR plus tpRV before returning to the
Vcc level. After tpRCL, the data ROM address can be
decremented to program the next location. Figure 19
shows programming mode of data ROM timing.
During erasure, place the 77P20 within 1 inch of the
lamp tubes. If the lamp tubes have filters, remove the
filters before erasure.
Read Mode. A read should be performed to verify that
the data was programmed correctly. Prior to entering
read mode, the device must be reset.
Programming
Read Mode of Instruction ROM. This mode is entered
by holding the WR signal at a TTL low level with the SI
signal at a TTL high level and all other specified inputs
(RD, CS/PROG, DACK, Ao, INl) at TTL low levels for
tcoRS prior to the falling edge of RST. WR is then held for
tRSW before being set to a TTL high level. The device is
now in the instruction ROM read mode and will stay in
this mode until reset.
Programming of the 77P20 is achieved with a single
SO-ms TTL pulse. Total programming time forthe 11,776
bits of instruction EPROM and also for the 6630 bits of
data EPROM is 26 seconds. Data is entered by programming a high level in the chosen bit locations. Both
instruction ROM and data ROM should be programmed
since they cannot be erased independently. Both instruction ROM and data ROM programming modes are
entered in the same manner.
The device must be reset initially before it can be
placed into the programming mode. After reset, the WR
signal and all other inputs (RD, CS/PROG, DACK, Ao, SI,
and INl) should be a TTL low signal tAS prior to the
falling edge of RST. WR is then held for tRH before being
22
Instruction ROM locations are sequentially read from
address OOOH through 1FFH. Application of CLKfortCY
will increment the location address. The three data
bytes will be read as specified by the control signals
RD, Ao, SI, and INT (table 16). Figure 20 shows read
mode of instruction ROM timing.
NEe
pPD77C20A,7720A,77P20
Figure 18. Programming Mode 01 Instruction ROM
,!;:sn
CLKV \
IpRCL
RST
II
..
IRR1
teORS
r'~
CSIPROG
H
~
AO
~
~
SI
~
~
INT
,
,
,
I
)
,
I
S
DBO-DB7
IPRPR~--i------
I
II
1,1
I
-----------------
J
I~ ~IPRV
_____
l __ ~
~
High
Middle
IRD~ IVpp
foIIl.;-..------Add'ess OOOH
Low
Jr-----,J ~------:
IVPR
~
..-
-------l.~I
001H-1FFH
83R[)'7386B
23
NEe
pPD77C20A,7720A,77P20
Figure 19. Programming Mode of Data ROM
,1~5T1
CLKV
\
tpRCL
R5T
I I
CS/PROG
H--+----
~Hr-------:--------:----i-+_tRc-+-r
~cK----~H~----~------~--------+I~I----~--r___+_~----------------....
51
,
,
INT
,
AO
II
I
00,-00, -----------------<
"',
J
,
,
~
-]:------< '- ~
",--+II<-- .~_~:::_JL _________"
'- ("."
----~Hl~----------_+-----------------J~
"i--~---Address 1FFH
fooIl
I~ ~tPRV
~I
.1"
~c
1FEH-ooOH
83RD·73878
24
ftlEC
pPD77C20A,7720A,77P20
Figure 20. Read Mode of Instruction ROM
ClK
tr\;;u
S
IRSCl
JV
I
I
I
I
I
I
ICY
\
RST
,
IRSW-
s
J\J
H
--
~"';,
f
,
ICORS- :++
S
CStPROG
H
AO
SI
INT
IICLD
DBO-DB7 - - - - - - - -
""'I~f__----Address OOOH------+1~ 001 H-lFFH
83F1D-7388B
25
NEe
pPD77C20A,7720A,77P20
Figure 21. Read Mode of Data ROM
,1~ST1
ClKV
\
tRSCl
tCY
RST
tRV1
tCORS
CS/PROG
--~s;s-s-_---:___+I--i-I_---+__---::---i-------+-------------
II
H
,
S
AO
s
SI
s
s,
INT
s
s
II
I
,
,
DBO-DB7 _ _ _ _ _ _ _ _
''''~
r""
r
~
r: ~_kjCX'_______'low
---G}{
1FEH-OOOH
83RD-7389B
Read Mode of Data ROM. Figure 21 shows read mode
of data ROM timing. This mode is entered by holding
the WR signal at a TTL low level with the Ao signal at a
TTL high level and all other specified inputs (RD,
C5IPROG, DACK, 51, INl) at TTL low levels for teoRS
prior to the falling edge of R5T. WR and Ao are then held
for teoRs priorto the falling edge of R5T. WR and Ao are
then held for tRSW before being set to a TTL high level
26
and TTL low level, respectively. The device is now in the
data ROM read mode and will stay in this mode until it
is reset.
Data ROM locations are sequentially read from address
1FFH through OOOH. Application of CLK for tey will
decrement the location address. After the address has
been decremented, the low byte of the current location
NEe
pPD77C20A, 7720A, 77P20
will be available at the data port subsequent to a tClD
delay. Application of RD will present the high byte tRD1
from the falling edge of the RD pulse. RD Is then applied
for tRV1 to complete reading of the current location.
Read Operation, AC Characteristics
TA = 25°C ±5°C; VCC = 5 V ±5%; Vpp = VCC + 0.25 V max;
VPP = VCC - 0.85 V min
Parameter
Symbol
Data access time from
ClK
tCLD
Min
Max
Unit
IlS
Data delay time from
SI,IN!
tcoo
Ils
Data flat time from SI,
IN!
!cOOF
SI, INT pulse width
!coco
RD recovery time
tF\V1
Data access time from
RD ~
tR01
Data float time from
RD!
tOF1
0
ns
500
Ils
ns
150
Conditions
Ell
ns
ns
10
Programming Operation, AC Characteristics
TA = 25°C ±5°C; VCC = 5 V ±5%; Vpp = 21 V ±0.5 v
Parameter
Symbol
Min
ClK cycle time
tCY
240
ns
tCLR
2
Ils
tRSCL
6
tpRCL
200
Ils
ns
6
Ils
ClK setup time to RD
~
ClK hold time from RST ~
ClK hold time from PROG
~
Control signal set-up time to RST ~
tCORS
WR hold time from RST ~
tRSW
Data set-up time from RD
Data hold time from RD
~
~
Max
Unit
Ils
100
ns
Ils
tRR1
SI, INT set-up time from RD !
tCOR
100
ns
SI, INT hold time from RD
tRCO
100
ns
tRPR
100
ns
tpRR
2
Ils
tyPR
2
Ils
tpFII
2
Il s
RST pulse width
tRST1
4
tCY
PROG pulse width
tpRPR
45
~
RD set-up time to PROG t
RD hold time from PROG
~
Vpp set-up time to PROG !
Vpp hold time from PROG
j
Conditions
Ils
tOR1
tRO
RD pulse width
Typ
Operation Mode
The 77P20 may be utilized in an operation mode after
the instruction ROM and data ROM have been programmed. Since it was first introduced in 1982, the
77P20 has undergone several mask revisions to improve manufacturability and/or function. And since the
purpose of the 77P20 is to run any program that may be
programmed in the masked ROM 77C20A/7720A, it is
50
55
ms
important to know how to determine the step levels and
the differences between them.
Step Level
The markings on the pPD77P20 package consist of
three lines, as follows:
27
ttlEC
pPD77C20A, 7720A, 77P20
NEC JAPAN
Manufacturer
Dnp20D
Part Number
nnnnXnnnn
Date code
supporting CP/M® and CP/M-86®, ISIS-II®, or MS-DOS®
operating systems. Additionally, the ASM77 Absolute
Assembler is offered in Fortran source code for mini
and main frame computer systems.
In the date code, "X" identifies the step level of the part.
Parts marked with step level K, E, or P should not be
used for final system test by customers who are planning to submit code for the masked ROM 77C20A/
7720A.
On all other np20 step versions, a slight functional
change was made, and the change is incorporated in
the nC20Am20A. The change allows the serial clock
(SCI<) to run asynchronously with ClK. Specified versions of 77P20 (i.e. K, E, P) and all Evakit-7720s and
Evakit-7720Bs (Evaluation Systems for nC20A!7720A/
np20) require that SCK run synchronously with ClK.
Because this functional change results in a slight
change in internal serial timing, it is mandatory that
code to be submitted for 77C20Am20A be verified in
customer's system using versions of 77P20 other than
those listed above (i.e. K, E, P).
Pin 1 Connection
The K mask version requires that the programming
voltage Vpp be supplied in a different manner than for
all later versions, as shown in figure 22. A silicon
junction diode of 0.6 V forward voltage fYF) should be
used. R should be 800 to 18000 to satisfy the Vpp and
Ipp requirements.
In all mask versions other than K, pin 1 must be
connected directly to Vcc.
Figure 22.
Vpp Circuitry for K Mask Version
Once software development is complete, the code can
be completely evaluated and debugged in hardware
with the Evakit-7720 Evaluation System. The Evakit
provides true in-circuit real-time emulation of the SPI
for debugging and demonstrating your final system
design. Code may be down-loaded to the Evakit from a
development system via an RS232 port using the EVA
communications program. This program is available in
executable form for ISIS-II systems and many CP/M,
CP/M-86, and MS-DOS systems. The EVA communications source code is also available for adapting the
program to other systems.
The Evakit also serves to program the 77P20, a fullspeed EPROM version of the SPI. The np20 may also
be programmed using DATA I/O "Unisite" and "2900
Programming Systems." Library routines for common
DSP routines such as N-stage IIR (biquadratic) and FIR
(transversal filters) are available on disk (free). Other
hardware interface test routines as well as a Software
Development Took Kit are also available.
Further operational details of the SPI can be found in
the pPD77C20A/772OAmp20 Signal Processing Interface Design Manual. Operation of the SPI development
tools is described in the Absolute Assembler User
Manual, the Simulator Operating Manual, and the
Evakit- 7720 User's Manual.
SYSTEM CONFIGURATION
Figures 23, 24, 25, and 26 show typical system applications for the 77C20A/7720A/77P20 SPI.
R
,......'M.._.---II4---_-o
+5V± 5%
Figure 23.
Spectrum Analysis System
vee
SPI
Sml.m
• Microphone
• Thermal
• Pressure
• Light
Vpp _ vee - (0.6 ± O.25)V
Ipp = 0.5 to 3.5 rnA
Product Example
e.
83RD·739OA
\,
28
,I
'-••••\.........1
DEVELOPMENT lOOLS
For software development, assembly into object code,
and debugging, an absolute assembler and simulator
are available. The ASMn Absolute Assembler and
SM77C25 Simulator for analyzing development code
and I/O timing characteristics are available for systems
i
BPF = Bandpass filter
Freq
83R0-738tA
CP/M and CP/M-86 are registered trademarks of Digital Research
Corp. ISIS·1I is a registered trademark of Intel Corp. MS-DOS is a
registered trademark of Microsoft Corp.
NEe
Figure 24.
pPD77C20A,7720A,77P20
Analog-to-Analog DIgital Processing
System Using a SIngle SPI
Analog
In
Figure 26.
Signal Processing System Using SPls
as a Complex Computer Peripheral
Host
CPU
Analog
Out
Memory
SCK
51
L----'"".--..~I
SIEN
SO
SOEN
I~-"'-'~L-----'
System Bus
RF = Reconstruction
filter
BPF
~
Bandpass filter
83RD·7392A
Figure 25.
DROl
Analog
In
1lI
~·
DMA
Controller
Signal Processing System Using
Cascaded SPls and Serial
Communication
.,
DRO(n)
Analog
SPI
Out
SO
DACK (n)
83RD-7394A
BPF ~ Bandpass filter
RF = Reconstruction filter
83RD·7393A
29
W
1"
pPD77C20A,7720A,77P20
30
tt1EC
NEe
IlPD77C25/77P25
Digital Signal Processor
NEC Electronics Inc.
Description
o Drop-in compatible with 77C20A/7720A/77P20
ThepPD77C25 andpPD77P25 Digital Signal Processors
(DSP) are significant upgrades to the pPD772O--the
original member of NEC's DSP family. pPD77C25 is the
mask ROM version; pPD77P25 has an OTP ROM or a
UVEPROM. All versions are CMOS and identical in
function. Unless contextually excluded, references in
this data sheet to 77C25 include 77P25
o 16-bit data word
The 77C25 executes instructions twice as fast as the
77C20A/7720A. Additional instructions allow the 77C25
to execute common digital filter routines more efficiently and at more than twice the speed of a 7720
implementation.
In addition to doubled execution speed, the 77C25 has
four times the instruction ROM space .and twice the
data ROM and RAM space of the 7720. Real savi ngs are
now possible, especially where one 77C25 can do the
work of and replace two or more 7720s.
The external clock frequency (8.3 MHz maximum) remains the same as for 77C20A/7720A while the internal
instruction execution speed is doubled. For most applications, the 77C25 is plug-in compatible with the
77C20A/7720A/77P20.
The feature that distinguishes digital signal processing
chips from general-purpose microcomputers is the onchip multiplier necessary for high-speed signal processing algorithms. The 77C25 multiplier is very sophisticated, especially for a low-cost DSP chip; both
multiplier inputs can be loaded simultaneously from
two separate memory areas. These loading operations
are only two of nine operations that can occur during
one 122-ns instruction cycle.
o Multioperation instructions for fast program
execution: any part, any combination, or all of the
following operations may constitute one
instruction that executes in 122 ns.
-Load one multiplier input
- Load the other multiplier input
- Multiply (automatic)
- Load product to output registers (automatic)
-Add product to accumulator
- Move RAM column data pointer
ove
M RroOwMPoi~ter
-- MM ove RAd
ata
pOinter
- Return from subroutine
o Modified Harvard architecture with three separate
memory areas
-Instruction ROM (2048 x 24 bits)
- Data ROM (1024 x 16 bits)
- Data RAM (256 x 16 bits)
o 16 x 16-bit multiplier; 31-bit product with every
instruction
o Dual 16-bit accumulators
o External maskable interrupt
o Four-level stack for subroutines and/or interrupt
o Multiple I/O capabilities
-Serial: 8 or 16-bit (244 ns/bit)
- Parallel: 8 or 16-bit
-DMA
o Compatible with most microprocessors, including:
-pPD8080
-pPD8085
- pPD8086/88
- pPD780 (Z8Q®)
-pPD78xx family
For a typical DSP filter application involving many
successive multiplications, the 77C25 provides a new
multiplication product for addition to a sum of products
every 122 nanoseconds. Additionally, during the same
instruction, memory data pointers are manipulated,
and even a return from subroutine may be executed.
Table 1 compares 77C25 with 77C20A.
o Single + 5-volt power supply
zao is a registered trademark of Zilog Corporation.
Features
Applications
o Low-power CMOS: 25 mA typical current use
(77C25)
o Portable telecommunications equipment
o Fast instruction execution: 122 ns with 8.192-MHz
clock
o High-speed data modems
o All instructions execute in one instruction cycle
50014·1
o Packages: 28-pin DIP, 32-pin SOP, 44-pin PLCC
o Digital filtering
o Fast Fourier transforms (FFT)
. , ' ,,
NEe
IJPD77C25/77P25
o Speech synthesis and analysis
Table
o Dual-tone multi frequency (DTMF) transmitters/
receivers
o Equalizers
t. Comparison of77C25 With 77C2OA (cont)
77C25/77P25
77C20A/77P20
JDPLNO
Additional
instructions
JDPLNF
o Adaptive control
Modification of RAM
column data pointer
M8-MF
o Numerical processing
Performance Benchmarks
DMA mode
Fully implemented
Partially
implemented
o Second-order digital filter (biquad): 1.1 /1s
Package
28·pin DIP
28·pin DIP
o Sin/cos of angles: 2.58/1s
44-pin PLCC
44·pin PLCC
o /1-law or A-law to linear conversion: 0.24/1S
o FFT
- 32-point complex: 0.35 ms
- 64-point complex: 0.8 ms
32-pin SOP
Ordering Information
Part Number
/lPD77C25C·xxx
Package
ROM
Operating
Temperature
Range
28-pin plastic DIP
Mask
-40 to + 85°C
OTP
-10 to +70°C
C25GW-xxx
32-pin SOP
C25L-xxx
44-pin PLCC
/lPD77P25C
28-pin plastic DIP
P25D
28-pin ceramic DIP UVEPROM
P25GW
32-pin SOP
OTP
P25L
44-pin PLCC
OTP
77C25/77P25
77C20A/77P20
CMOS/CMOS
CMOS/NMOS
Instru ction cycle
122 ns
244 ns
Instruction ROM
2048 x 24 bits
512 x 23 bits
Data ROM
1024 x 16 bits
510 x 13 bits
Data RAM
256 x 16 bits
128 x 16 bits
Fixed-point
multiplier
16 bitsx 16 bits -+ 31
bits
16 bits x 16 bits .... 31
bits
ALU
16-bit fixed-point
16-bit fixed-point
Accumulator
2 x 16 bits
2 x 16 bits
Host CPU interface
8-bit bus
8-bit bus
Serial interface
One input and one
output
One input and one
output
4 MHz
2 MHz
Temporary registers
Two
One
2
5V
5V
Power consumption
50 mA (max) @ 8.192
MHz
40 mA (max) @ 8.192
MHz
Power saving mode
(when idle)
Yes
No
Since the 77C25 executes an instruction in one external clock cycle (versus two cycles of the same 8.192MHz clock for 77C20A), the 77C25 may be substituted
for a 77C20A (or 7720A or 77P20) in a circuit without
modification of that circuit. Hardware/software that
implements data transfers-both serial and parallelbetween the 77C25 and other devices in an existing
7720 design should use the handshake protocol described in the 77C25 User's Manual.
Pin Configurations
Table t. Comparison of 77C25 With 77C20A
Technology
Power supply
28-PinDIP
NCNpp
DACK
,
2
VDD
Ao
Cs
RD
WR
SORa
so
SI
SOEN
SIEN
SCK
INT
RST
ClK
49NR-304A
NEe
pPD77C25/77P25
Pin Configurations (cont)
Pin Identification
32-PinSOP
NC
NCNpp
OACK
ORO
Po
PI
Do
01
02
03
04
Os
Os
07
GNO
GNO
Chip select input
Three-state I/O data bus
AD
OACK
OMA request acknowledge input
WR
SORa
ORa
OMA request output
INT
Interrupt input
51
SOEN
SIEN
SCK
INT
RST
CLK
NC
a.
0 a. C C
/><
o oll:<~ CC0,f'CIlO
z
c..ccz»z
uz
o
-
'""" '""" "" ""
0
PI
DO
NC
01
02
03
04
NC
31
Os
NC
C 0
~ Z
Single-phase master clock input
00-0 7
44-PinPLCC
°Z c"'.jC~
ClK
Ao
so
~ C\j ~ gJ
Status/data register select input
CS
B3NR-8079A
<
d
II:
~ O!z
><
NC
RO
WR
SORa
SO
NC
51
NC
SOEN
SIEN
NC
po. PI
General-purpose output control lines
RO
Read control signal input
RST
Reset input
SCK
Serial data I/O clock input
SI
Serial data input
SIEN
Serial input enable input
SO
Three-state serial data output
SOEN
Serial outPl-lt enable input
SORa
Serial data output request
WR
Write control signal input
GNO
Ground
VOO
+5 V power supply
NC/Vpp
77C25: no connection
77P25: +12.5 V programming
77P25: +5 V for normal operation
m\:
PIN FUNCTIONS
Ao
(Status Data Register Select)
This input selects data register for read/write (low) or
status register for read (high).
ClK
This is the single-phase master clock input.
Z _ ~
83NR-a076A
CS (Chip Select)
This input enables data transfer through the data port
with RD or WR.
00-07 (Data Bus)
This three-state I/O data bus transfers data between
the data register or status register and the external
data bus.
OACK (OMA Request Acknowledge)
This input indicates to the 77C25 that the data ous is
ready for a DMA transfer (DACK = CS and Ao = 0).
3
NEe
pPD77C25/77P25
DRQ (DMA Request)
SO (Serial Data Output)
This output signals that the 77C25 is requesting a data
transfer on the data bus.
This three-state port outputs 8- or 16-bit data words to
an external device such as a D/A converter.
INT (Interrupt)
SOEN (Serial Output Enable)
A low-to-high transition on this pin executes a call
instruction to location 100H if interrupts were previously enabled.
This input enables the shift clock to the serial output
register.
SORQ (Serial Data Output Request)
Po, P1
These pins are general-purpose output control lines.
RD (Read Control Signal)
This output specifies to an external device that the
serial data register has been loaded and is ready for
output. SORQ is reset when the entire 8- or 16-bit word
has been transferred.
This input latches data from the data or status register
to the data port where it is read by an external device.
WR (Write Control Signal)
RST (Reset)
This input writes data from the data port into the data
register.
This input initializes the 77C25 internal logic and sets
the PC to O.
GND
This is the connection to ground.
SCK (Serial Data I/O Clock)
When this input is high, a serial data bit is transferred.
SI (Serial Data Input)
This pin inputs 8- or 16-bit serial data words from an
external device such as an AID converter.
Voo (Power Supply)
This pin is the + 5-volt power supply.
NCNpp
SIEN (Serial Input Enable)
This pin is not internally connected in the 77C25. In the
77P25, this pin inputs the programming voltage (Vpp)
when the part is being programmed.
This input enables the shift clock to the serial input
register.
This pin must be connected to Voo for normal 77P25
operation.
4
NEe
IIPD77C25/77P25
Block Diagram
DACK _ _
DMA
Interface
Logic
DRO_
r-"'k-- SOEN
'SO~SORO
Instruction
ROM
2048 x 24
[EPROM] *
Multiplier
16 x 16 -->31
L
.J
:e±'
:K
r-'
Isd
Serial
110
~SIEN
LI.J
L--SI
,
Read Write
Control Logic
Ro
WR
CS
Flag A
FlagB
S
A
1
S
A
0
C
A
S
S
B
0
C
B
B
1
*VPP_
CLK_
RST_
Z
0
0
A
V
A
1
V
A
0
Z
0
0
B
V
B
1
V
B
0
AO
Data
ROM
1024 x 16
[EPROM]*
D
Port
Po
P1
INT _ _
VDDGND_
Interrupt
*I'PD77P25
83NR-80nB
DATA BUSES
The primary bus (unshaded in the block diagram)
makes a data path between all of the registers (including I/O), memory, and the processing sections. This
bus is referred to as the lOB (internal data bus). The
multiplier input registers K and L can be loaded not
only from the lOB but alternatively via buses (darkened
in the block diagram) directly from RAM to the K
register and directly from data ROM to the L register.
Output from the multiplier in the M and N registers is
typically added via buses (shaded in the block diagram) to either accumulator A or B as part of a mUltioperation instruction.
MEMORY
Memory is divided into three types: instruction ROM,
data ROM, and data RAM. The 2048 x 24-bit words of
instruction ROM are addressed by an 11-bit program
counter that can be modified by an external reset,
interrupt, call, jump, or return instruction.
5
NEe
pPD77C25/77P~5
The data ROM is organized in 1024 x 16-bit words that
are addressed through a 10-bit ROM pointer (RP register). The RP may be modified simultaneously with
arithmetic instructions so that the next value is available for the next instruction. The data ROM is ideal for
storing the necessary coefficients, conversion tables,
and other constants for signal and math processing.
The data RAM is 256 x 16-bit words and is addressed
through an 8-bit data pointer (DP register). The DP has
extensive addressing features that operate simultaneously with arithmetic instructions, eliminating additional time for addressing or address modification.
Thirty-one bit results are developed by a 16 x 16-bit
two's complement multiplier in 122 ns. The result is
automatically latched to two 16-bit registers, M and N,
at the end of each instruction cycle. The sign bit and 15
higher bits are in M and the 15 lower bits are in N; the
LSB in N is zero. A new product is available for use after
every instruction cycle, providing significant advantages in maximizing processing speed for real-time
signal processing.
Stack
The 77C25 contains a four-level program stack for
efficient program usage and interrupt handling.
ARITHMETIC CAPABILITIES
One of the unique features of the 77C25 architecture is
its arithmetic facilities. With a separate multiplier, ALU,
and multiple internal data paths, the 77C25 is capable
of carrying out a multiply, an add or other arithmetic
operation, and a data move between internal registers
in a single instruction cycle.
ALU
The ALU is a 16-bit two's complement unit capable of
executing 16 distinct operations on data routed via the
P and Q ALU inputs.
Accumulators (ACCAIACC B)
Associated with the ALU are two 16-bit accumulators,
each with its own set of flags, which are updated at the
end of each arithmetic instruction. Table 2 shows the
ACC AlB flag registers. In addition to zero result, sign,
carry, and overflow flags, the 77C25 incorporates auxiliary overflow and sign flags (SA1, SB1, OVA1, OVB1).
These flags enable the detection of an overflow condition and maintain the correct sign after as many as
three successive additions or subtractions.
Table 2_ ACC AlB Rag Registers
Flag A
SAl
SAO
CA
ZA
OVAl
OVAO
Flag B
SBl
SBO
CB
ZB
OVBl
OVBO
Sign Register (SGN)
When OVA1 is set, the SA1 bit will hold the corrected
sign of the overflow. The SGN register will use SA1 to
automatically
generate
saturation
constants
7FFFH(+) or 8000H(-) to permit efficient limiting of a
calculated value. The SGN register is not affected by
arithmetic operations on accumulator B, but flags SB1,
SBO, CB, ZB, OVB1, and OVBO are affected.
6
Multiplier
Interrupt
The 77C25 supports asingle-Ievel interrupt. Upon sensing a high level on the INTterminal, a subroutine call to
location 100H is executed. The EI bit of the status
register automatically resets to 0, disabling the interrupt facility until it is reenabled under program control.
INPUT/OUTPUT
The 77C25 has three communication ports as shown in
figure 1: two serial and one 8-bit parallel, each with its
own control lines for interface handshaking. Parallel
port operation is software-configurable to be in either
polled mode or DMA mode. A general-purpose, twoline output port rounds out a full complement of interface capability.
Serial I/O
The two shift registers (SI, SO) are softwareconfigurable to single- or double-byte transfers. The
shift registers are externally clocked (SCI<) to provide a
simple interface between the 77C25 and serial peripherals such as AID and D/A converters, codecs, or other
77C25's. Figure 2 shows serial 1/0 timing
NEe
IIPD77C25/77P25
Note: The ROM bit of the status register is affected by
read/write operations in DMA mode the same as nonDMA mode. (In 7720 operation, ROM is not affected
when in DMA mode.)
Figure 1. 77C25 Communication Ports
77C25
00-0 7
so
AD
WR
CS
AO
OMA
Interface
Interrupt
Reset
Clock
OACK
ORO
INT
RST
ClK
SCK
)_00
X
Interface
SI
SIEN
Po
P,
Table 3. Parallel R/W Operation
CS Ao WR RD Operation
} General
Purpose
Output Port
83NFI.-8078A
X
X
0
0
0
0
0
X
X
No effect on internal operation; Do-D7 are
at high impedance levels.
0
Contents of DR are output to Do-D7 (Note
1)
0
Data from Do-D7 is latched to DR (Note 1)
Illegal (SR is read only)
0
0
X
0
0
0
Eight MSBs of SR are output to Do-D7
0
Illegal (may not read and write
simultaneously)
Parallel I/O
The 8-bit parallel I/O port may be used for transferring
data or reading the 77C25 status as shown in table 3..
Data transfer is handled through a 16-bit data register
(DR) that is software-configurable for double- or si nglebyte data transfers. The port is ideally suited for operating with 8080, 8085, and 8086 processor buses and
may be used with other processors and computer
systems.
DMA Mode Option
Parallel data transfers may be controlled (optionally)
via DMA control lines DRO and DACK. DMA mode
allows high-speed transfers and reduced processor
overhead. When in DMA mode, DACK input resets DRO
output when data transfer is completed.
Notes:
(1) Eight MSBs or LSBs of data register (DR) are used, depending on
DR status bit (DRS). The condition of DACK = 0 is equivalent to
Ao = cs = o.
Status Register
The status register, (figure 3, table 4) is a 16-bit register
in which the 8 most significant bits may be read by the
system's microprocessor for the latest parallel data I/O
status. The ROM and DRS bits can only be affected by
parallel data moves. The other bits can be written to (or
read) by the 77C25 load immediate (LD) or move (MOV)
instruction. The EI bit is automatically reset when an
interrupt is serviced.
7
fttfEC
pPD77C25/77P25
Figure 2. Serial If0 Timing
SCK
SORa _ _
...J!
\-------------
\'------~SISS- _ _ _ _ _....L.!___________ _
,..----- HlghZ
.."------
..
Output Data _ _.;.H;;.:lg:;.;h.;;Z;..._-<
SOACK"
SOLoed"
[Note3J
,-------------------------,
J
:
(Next Data Set)
:
I
I
r------,
~
I
I
I
I
I
,
Input Data
\'---_ _ _ _ _ _---J!
~~"
n
------------------------------~
SlACK"
'----
L
Notas:
[IJ Data clocked out on failing edge of SCK.
[2J Data clocked In on rising edge of SCK.
[3J Broken line denotes consecutive sending of next data.
[*J Internal signal
83R[).73688
8
tttrEC
pPD77C25/77P25
Figure 3. Status Register
15
14
13
12
I ROM I USF1 I USFO I DRS
11
10
9
8
DMA
DRC
SOC
SIC
P1
PO
MSB
7
6
5
4
3
2
EI
0
0
0
0
0
0
LSB
Table 4. Status Register Rags
the instruction specifies lOB). However, if the accumulator specified in the ASL field is also specified as the
destination of the data move, the ALU operation becomes a NOP, as the data move supersedes the ALU
operation.
Pointer modifications occur at the end of the instruction cycle after their values have been used for data
moves. The result of multiplication is available at the
end of the instruction cycle for possible use in the next
instruction. If a return is specified as part of an OP
instruction, it is executed last.
Flag
Description
ROM (Request
for master)
A read or write from DR to IDB sets ROM = 1.
An external read (write) resets ROM = O.
USFI and USFO
(User flags 1
and 0)
General·purpose flags that may be read by an
external processor for user-defined signaling
DRS (DR
status)
For 16-bit DR transfers (DRC = 0). DRS = 1
after the first 8 bits have been transferred. DRS
= 0 after all 16 bits have been transferred.
DMA(DMA
enable)
DMA = 0 (Non-DMA transfer mode)
DMA = 1 (DMA transfer mode)
An assembly language OP instruction may consist of
what looks like one to six lines of assembly code, but all
of these lines are assembled together into one 24-bit
instruction word. Therefore, the order of the six lines
makes no difference in the order of execution described above. However, for understanding nC25 operation and to eliminate confusion, assembly code
should be written in the order described; that is: data
move, ALU operations, data pointer modifications, and
then return.
DRC(DR
control)
DRC = 0 (16-bit mode)
DRC = 1 (8-bit mode)
OP/RT Instructions
SOC (SO
control)
SOC = 0 (16-bit mode)
SOC = 1 (B-bit mode)
SIC (SI control)
SIC = 0 (16-bit mode)
SIC = 1 (8-bit mode)
EI (Enable
interrupt)
EI = 0 (interrupts disabled)
EI = 1 (interrupts enabled)
PI, PO (Ports 0
and 1)
PO and PI directly control the state of output
pins Po and P,
Temporary Registers
The nC25 has two 16-bit temporary registers.
INSTRUCTIONS
The nC25 has three types of instructions: OPIRT
(operation/return), JP Oump), and LD (load immediate).
Each type takes the form of a 24-bit word and executes
in 122 ns.
Figure 4 illustrates the OP/RT (operation/return) instruction field specification. This is really one instruction type capable of executing all ALU functions listed
in table 6.
The ALU functions operate on the value specified by
the P-select field (table 5).
The AT indicates an option in bit 022 that causes a
return from subroutine or interrupt service.
Besides the arithmetic functions, this instruction can
also (1) modify the RAM data pointer DP, (2) modify the
data ROM pointer RP, and (3) move data along the
on-Chip data bus from a source register to a destination
register. Tables 7, 8, 9, and 10 show the ASL, DPL, DPH,
and RPDCR fields, respectively. The possible source
and destination registers are listed in tables 11 and 12.
Instruction Timing
To control the execution of instructions, the external
8-MHz clock is divided into phases for internal execution. The various elements of the 24-bit instruction
word are executed in a set order. Multiplication automatically begins first. Also, data moves from source to
destination before other elements of the instruction.
Data being moved on the internal data bus (lOB) is
available for use in ALU operations (if P-select field of
9
_!
BIll:!
NEe
pPD77C25/77P25
Table 5. P-Select Field
Mnemonic
ALU Input
o
o
o
RAM
IDB
RAM
• Internal data bus
o
M
M register
N
N register
• Any valu'e on the on-chip data bus. Value may be selected from any
of the source registers listed in table 11.
Figure 4. OP/RT Instruction Field
Zl
22 21
3l
19
18
17
16
15
14
13
12
11
10
9
A
OP 0
RT 0
0
PSelect
ALU
S
L
8
7
6
5
4
3
2
0
R
P
DPL
D
DPH-M
C
DST
SRC
R
Seme as OP Instruction
1
49M.()OOO58B
Table 6. ALU Field
Mnemonic
0 19
0 18
0 17
016
ALU Function
NOP
0
0
0
0
No operation
OR
0
0
0
AND
0
0
XOR
0
0
SUB
0
0
ADD
0
0
SBB
0
ADC
0
0
0
0
DEC
0
0
INC
0
0
CMP
0
SHRl
0
0
0
SHL1
0
SHL2
0
SHL4
XCHG
0
0
SAl, SBl
SAO,SBO
CA,CB
ZA,ZB
OVA1,OVBl
OVAO,OVBO
OR
x
!:::.
0
!:::.
0
0
AND
x
!:::.
0
!:::.
0
0
Exclusive OR
x
!:::.
0
!:::.
0
0
Subtract
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
Add
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
Subtract with borrow
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
Add with carry
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
DecrementACC
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
Increment ACC
!:::.
!:::.
!:::.
!:::.
!:::.
!:::.
Complement ACC
(one's complement)
x
!:::.
0
!:::.
0
0
1-bit right shift
x
!:::.
!:::.
!:::.
0
0
1-bit left shift
x
!:::.
!:::.
!:::.
0
0
2-bit left shift
x
!:::.
0
!:::.
0
0
4-bit left shift
x
!:::.
0
!:::.
0
0
8-bit exchange
x
!:::.
0
!:::.
0
0
Symbols:
!:::. May be affected, depending on the results
-
Previous status can be held
o Reset
x Indefinite
Table 7. ASL Field
Mnemonic
ACCA
ACCB
10
0,5
ACC Selection
0
ACCA
ACCB
NEe
IIPD77C25/77P25
Table 8. DPL Field
Mnemonic
OPNOP
0'4
0
OPINC
0
Table 11. SRC Field (cont)
0'3
0
DPDEC
0
OPCLR
Low OP Modify (OP 3·OPO>
Mnemonic
No operation
SIM
Increment OPL
SIL
0
Decrement DPL
K
0
Clear DPL
L
07
06
05
0
04
Source Register
1
SI serial in MSB (Note 3)
0
SI serial in LSB (Note 4)
K register
0
L register
RAM
MEM
Table 9. DPH Field
09
High OP Modify
Notes:
0
0"
0
0'0
MO
0
0
(1) Contents of TRB register are also output if NON is specified.
Ml
0
0
0
M2
0
0
Exclusive OR of DPH
(DPrDP4) with the mask
defined by the 4 bits
(012-D9) of the OPH field
M3
0
0
M4
0
0
M5
0
0
M6
0
M7
0
Mnemonic
0'2
0
M8
0
0
0
M9
0
0
MB
0
0
Jump Instructions
Figure 5 shows the JP instruction field specification.
Bits 0 21 • 0 20 • and 0 19 of the BRCH field identify the
three types of instructions: unconditional jump (100).
subroutine call (101). and conditional jump (010). Table
13 lists the instruction mnemonics for the complete
BRCH field. bits 021-013.
0
0
MC
0
MD
0
All the instructions in table 13-if unconditional or if the
specified condition is true-take their next program
execution address from the next address field (NA) in
figure 5. Otherwise. PC = PC + 1.
0
0
ME
MF
Table
(3) First bit in goes to MSB, last bit to LSB.
(4) First bit goes to LSB, last bit to MSB (bit reversed).
0
MA
(2) DR to lOB, ROM not set. In OMA, ORO not set.
Load Data (LD) Instructions
to. RPDCR Field
Figure 6 shows the LO instruction field specification.
Mnemonic
Os
RPNOP
0
RP operation
No operation
RPDEC
Decrement RP
Table 11. SRC Field
Mnemonic
07
06
05
04
Source Regi sler
NONfTRB
0
0
0
0
TRB (Note 1)
A
0
0
0
B
0
0
TR
0
0
DP
0
0
0
RP
0
RO
0
SGN
0
ACCA (Accumulator A)
0
ACCB (Accumulator B)
TR temporary register
0
DP data pointer
RP ROM pointer
0
RO ROM output data
SGN sign register
DR
0
0
DRNF
0
0
SR
0
0
DR data register
0
SR status register
DR no flag (Note 2)
The load data instruction will take the 16-bit value
contained in the immediate data field (10) and place it
in the register specified by the destination field (OSl).
This is the same as the OSTfieid (table 12) in the OP/RT
instruction.
Table
t2. DST Field
Mnemonic
03
02
0,
Do
@NON
0
0
0
0
@A
0
0
0
@B
0
0
@TR
0
0
@OP
0
0
@RP
0
0
@DR
0
@SR
0
@SOL
Destination Register
No register
ACCA (Accumulator A)
0
ACCB (Accumulator B)
TR temporary register
0
DP data pointer
RP ROM pointer
0
DR data register
SR status register
0
0
0
SO serial out LSB (Note 1)
11
•
NEe
pPD77C25/77P25
Table 12. OST Field (cont)
Mnemonic
DO
@SOM
o
@K
o
o
@KLR
o
o
@KLM
o
@L
o
o
Destination Regl ster
Mnemonic
SO serial out MSB
(Note 2)
@MEM
o
RAM
K (Mult)
Notes:
IDB -+ K, ROM .... L
(Note 3)
(1) LSB is first bit out.
Hi RAM .... K, IDB .... L
(Note 4)
(3) Internal data bus to K, and ROM to L register.
L register
@TRB
Destination Register
DO
D3
(2) MSB is first bit out.
(4) Contents of RAM address specified by DP s = 1 is placed in K
register, IDB is placed in.L (that is: 1, DP5, DP4, DP3-DPO).
TRB register
Figure 5. JP Instruction Field Specification
23
22
21
20
19
18
17
16 15 14
13
12 11
10
9
8
7
6
5
4
49M-000059B
Figure 6. LO Instruction Field Specification
23
22
21
20
19
18
17
16 15 14 13 12 11
10
9
8
6
7
5
4
3
2
o
49M-oDOO608
Table 13. BRCH Field
Mnemonic
JMP
CALL
JNCA
JCA
JNCB
JCB
JNZA
JZA
JNZB
Conditions
Mnemonic
o0
o1
000
000
No condition
JNOVBl
000
000
No condition
JOVBl
a1
o1
o1 a
o1 a
a1a
o1 0
01 a
o1 0
o1 0
oa0
000
CA =
a
JNSAO
01 0
aD
000
000
a
1 0
CA = 1
JSAo
0
00
o1
CB=
0
1
a0
1 a
001
000
ZA =
o1
a1
a1
a1
ZA = 1
JSAl
1
a1 0
a0
ZB = 0
JNSBl
o1 0
a1a
0
o0
oa
oa
1
1 1 0
ZB
JSBl
01
1 1 0
SBl = 1
0
0.1 0
000
OVAO = 0
JDPLO
010
a0
a0
a1
a1
a1
a1
o
0
DPL = 0
a
1 0
OVAO
=1
JDPLNa
o
1
DPL" a
0
00
OVBO
1
a
OVBO
=0
=1
0
0
JDPLNF
a0
a1
0
OVAl = 0
JNSIAK
0
OVAl = 1
JSIAK
a
a
a
a
a
aa
aa
000
o0
JNOVAO
o1
o1
JOVAO
01 0
a
JNOVBo
JOVBO
o1
o1
0
o1
o1
JNOVAl
o1 a
01
JOVAl
o1
01
JZB
12
0
0
0
1
1 0
a
CB = 1
a
=1
JNSBO
JSBO
JNSAl
JDPLF
Conditions
0
01 1
0
01
0
0
a
1 0
1 00
OVBl = 0
1 0
OVBl = 1
SAO = 0
0
SAO = 1
00
SBa = a
1 0
SBa = 1
aa0
a10
1 a0
SAl = 0
1 0
1 0
o1
1 0
1
01
1 0
a
a
1 0
1 0
SAl = 1
SBl = 0
DPL = FH
DPL" FH
a0
SlACK = 0
1 1 0
SlACK = 1
1
NEe
pPD77C25/77P25
ELECTRICAL SPECIFICATIONS
Table 13. BRCH Field (cont)
Mnemonic
JNSOAK
°21-°19
°18-°16
°15-°13
Conditions
Absolute Maximum Ratings
01 0
000
SOACK = 0
TA = 25"C unless otherwise specified
o 1 0
SOACK = 1
Supply voltage, Voo
-0.5 to +7.0 V
~------------------------Vpp (77P25)
-0.5 to + 13.5 V
JSOAK
o 1 0
JNROM
01 0
00
ROM = 0
JROM
01 0
1 0
ROM = 1
Input voltage, VI
- 0.5 to Voo + 0.5 V
~--------------------~---VRST (77P25)
-0.5 to + 13 V
Output voltage, Vo
- 0.5 to Voo + 0.5 V
Storage temperature, TSTG
-65 to 150"C
Operating temperature, TOPT
77C25/77C25-10
77P25 (Normal operation)
77P25 (PROM mode)
-40 to +80"C
-10 to +70"C
+20 to +30"C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage.
Recommended Operating Conditions
.I
Parameter
Symbol
Supply voltage
Voo
Vpp*
Max
Unit
4.5
5.0
5.5
V
6.0
6.25
V
Programming"
4.5
5.0
5.5
V
Reading and normal operation
12
12.5
Programming
V
0.8
V
VIH
2.2
VOO + 0.3
V
VllC
-0.3
0.5
V
VIHC
3.5
Vee +0.3
V
Vll
Conditions
5.7
12.8
Input voltage, high
ClK input voltage, high
Typ
-0.3
Input voltage, low
ClK input voltage, low
Min
Normal operation
Input voltage for setting PROM mode
VRST"
11.5
12.0
12.5
V
Reading and writing
Operating temperature
TOPT
-40
+25
+85
"C
77C25/77C25-10
-10
+25
+70
"C
Normal operation"
+20
+25
+30
"C
PROM mode"
* For I1PD77P25
13
NEe
pPD77C25/77P25
DC Characteristics, Normal
= -40 to +85'C (77C25{77C25-10), -10 to 70'C (77P25); Voo =
TA
Parameter
Symbol
Output Yoltage, low
VOL
Output Yoltage, high
VOH
Input leakage cui rent, low
IUl
Min
4.5 to 5.5 V
Typ
Max
Unit
0.45
V
IOl
V
IOH
= 400 llA
-10
IlA
VIN
= OV
0.7V oo
Conditions
= 2.0mA
Input leakage current, high
IUH
10
IlA
VIN = Voo
Output leakage current, low
IlOl
-10
IlA
Output leakage current, high
ILOH
10
IlA
Supply current (77C25)
100
25
50
mA
15
25
mA
= 0.47 V
= Voo
fClK = 8.192 MHz
fClK = 8.192 MHz; RST = 1
35
60
mA
fClK
20
35
mA
fClK = 8.192 MHz; RST
Supply current (77P25)
100
mA
Ipp
DC Characteristics, PROM Mode
= +20 to +30'C; voo = 5.75 to 6.25 V
TA
Parameter
Symbol
Max
Unit
Conditions
30
pA
VRST = 12.0
± 0.5V
Icc
60
mA
Ipp
30
mA
Input leakage
current
IRST
Supply current
Min
Typ
Capacitance
= 25'C; voo = 0 V
TA
Parameter
Symbol Typ
ClK, SCK capacitance
Ccp
20
pF
Input capacitance
CIN
20
pF
Output capacitance
COUT
20
pF
14
Max
Unit Conditions
fc
= 1 MHz
VOUT
VOUT
= 8.192 MHz
=1
t-{EC
pPD77C25/77P25
AC Characteristics
TA = -40 to 85"C (77C25/77C25-10), -10 to
Parameter
+ 70"C
Symbol
(77P25);
Voo = 4.5 to 5.5 V
Min
Typ
Max
Unit
120
100
122
100
2000
2000
ns
ns
Conditions
Clock
ClK cycle time
77C25/77P25
77C25-10
tCYC
elK pulse width
77C25
77P25
77C25-10
tcc
Measuring at 2 V
55
60
45
ns
ns
ns
ClK rise time
tCR
10
ns
ClKfalitime
tCF
10
ns
SCK cycle time
77C25/77P25
77C25-10
tCYS
SCK high pulse with
77C25/77P25
77C25-10
tSSH
SCK low pulse width
77C25/77P25
77C25-10
tSSl
SCK rise time
tSR
20
ns
SCK fall time
tSF
20
ns
240
200
244
200
Measuring at 1 and 3 V
ns
ns
100
80
ns
ns
100
80
ns
ns
Ell
Host Interface Timing
AD, CS, DACK setup time for RD
tSAR
0
ns
AD, CS, DACK hold time for RD
tHRA
0
ns
RD pulse width
77C25/77P25
77C25-10
!wRD
120
100
ns
ns
AO, CS, DACK setup time for WR
tSAW
0
ns
AO, CS, DACK hold time for WR
tHWA
0
ns
WR pulse width
77C25/77P25
77C25-10
!wWR
120
100
ns
ns
Data setup time for WR
77C25/77P25
77C25-10
!sow
100
80
ns
ns
Data hold time for WR
IHWO
0
ns
RD, WR recovery time
77C25/77P25
77C25-10
tRV
100
80
ns
ns
DACK hold time for DRQ
tHRQA
0.5tCYC
ns
RD, WR setup time for ClK
tSRWC
50
ns
Note 1
RD, WR hold time for ClK
tHCRW
50
ns
Note 1
Host Interface Switching
RD ~ -+ data delay time
77C25/77P25
77C25-10
tOR 0
100
80
ns
ns
15
ttiEC
pPD77C25/77P25
AC Characteristics (cent)
Parameter
Symbol
RD t --+ data float time
77C25n7P25
77C25-10
tFRO
ClK t --+ DRQ delay time
77C25n7P25
77C25-10
tOCRQ
DACK I --+ DRQ delay time
77C25n7P25
77C25-10
tOARQ
ClK t --+ PO, P1 delay time
77C25n7P25
77C25-10
tocp
Min
10
10
Typ
Max
Unit
65
50
ns
ns
80
65
ns
ns
110
90
ns
ns
100
80
ns
ns
Conditions
Interrupt Reset Timing
RST setup time for ClK
77C25n7P25
77C25-10
IsRSC
RST hold time for ClK
77C25n7P25
77C25-10
tHCRS
RST pulse width
tRST
Note 1
50
40
ns
ns
50
40
ns
ns
2tCYC
ns
System reset
3tCYC
ns
Enter power saving state
50
40
ns
ns
50
40
ns
ns
Note 1
iNT setup time for ClK
77C25n7P25
77C25-10
tSINC
Note 1
INT hold time for ClK
77C25n7P25
77C25-10
tHCIN
INT pulse width
tiNT
3tCYC
ns
INT recovery time
tRINT
2tCYC
ns
Note 1
Interrupt Reset Switching
ClK! --+ reset state delay time
77C25n7P25
77C25-10
tOCRS
100
80
ns
ns
Serial Interface Timing
SIEN, SI setup time for SCK
77C25n7P25
77C25-10
Iss IS
SIEN, SI hold time for SCK
77C25n7P25
77C25-10
tHSSI
SOEN setup time for SCK
77C25n7P25
77C25-10
IsSES
SOEN hold time for SCK
77C25n7P25
77C25-10
tHSSE
ClK setup time for SCK
77C25n7P25
77C25-10
Iscs
16
50
40
ns
ns
30
20
ns
ns
50
40
ns
ns
30
25
ns
ns
50
40
ns
ns
Note 1
t'tlEC
pPD77C25/77P25
AC Characteristics (cant)
Parameter
Symbol
ClK hold time for SCK
nC25{77P25
tHSC
Min
Unit
50
40
ns
ns
50
40
ns
ns
Conditions
50
40
ns
ns
Nole 1
tssc
nC25·10
SCK hold lime for ClK
nC25{77P25
Max
Note 1
nC25·10
SCK setup time for ClK
nC25{77P25
Typ
Nole 1
tHCS
nC25·10
Serial Interface Switching
SCK t -+ SORQ delay lime
nC25{77P25
IOSSQ
30
20
nC25·10
SCK ~ -+ SO delay lime
nC25{77P25
150
120
ns
ns
60
50
ns
ns
..
tOSLSO
nC25·10
SCK ~ ... SO hold time
nC25{77P25
77C25·10
tHSLSO
SCK ~ ... SO float time
77C25{77P25
tFSSO
0
0
ns
ns
60
50
nC25·10
ns
ns
Notes:
(1) Setup and hold requirement for asynchronous signal only guar·
antees recognition at next ClK.
PROM Program Timing
TA = 25 ±5°C; V,HR = 12.0 ±0.5 v
Parameter
Typ
Max
Unit
Symbol
Min
CE setup time for RST
tsRSCE
2
/1s
OE setup time for RST
tSRSOE
2
/15
Conditions
Data Read
VOO = 5.0 ±0.5 V
Vpp = Voo
Data Read Switching
Address to output delay
tOAO
200
ns
CE to output delay
toco
200
ns
OE to oulput delay
tOOOR
75
ns
OE high to output float
Address to output hold
tFCO
0
tHAO
0
ns
60
VOO = 5.0 ±0.5 V
Vpp = VOO
ns
Data Write
CE setup time for RST
tSRSCE
2
/1s
CE setup time for address
tSAC
2
/1s
CE setup time for data
tsoc
2
/1s
CE setup time for Vpp
tsvPC
2
/1s
CE setup time for VOO
tsVOC
2
/1s
OE setup time for data
tsoo
2
/1s
VOO = 6.0 ±0.25 V
Vpp = 12.5 ±0.3 V
17
!\fEe
JlPD77C25/77P25
PROM Program Timing (cont)
Parameter
Min
Symbol
Address hold time
tHCA
Data hold time
Max
Typ
2
tHCO
2
Initial program pulse width
twco
0.95
Overprogram pulse width
tWC1*
Unit
Conditions
Jls
Jls
1.05
ms
2.85
78.75
ms
0
130
ns
150
ns
1.0
Dsts Write Switching
OE to output float time
tFOO
OE to output delay
tDOOW
VOD = 6.0 ±0.25 V
Vpp = 12.5 ±0.3 V
tWC1 = 3ntwco assuming initial program pulse is applied n times.
Timing Waveforms
Input/Output Voltage Reference Levels
Input 2.4 V
0.4 V
Output
Host Read Operation
=x
2.2 V
2.2VX=
.::;0.;::,8..:.V_ _ _~0.8::..V.:..;
--~
OACK. CS
V--
-Y2.2V
2.2V
---A.::;0.;::,8..:.V_ _ _::;0.8::..V.:..;A-49M-OOOO44A
Clock Timing
DO' D7
-------t
" _ _ _- - T
49M-OOOO46A
CLK
Host Write Operation
--~
OACK.CS
SCK
tWWR
WR
I
t SDW -+
__________• ______fC_tH_~
____
°0·D7
18
----------
49M-000047A
NEe
IlPD77C25/77P25
Normal Operation, 8-Bit Mode
Internal Timing
Instruction
execu1e timing
--V
A
ROM flag
[N01e 1J
X
X
. '-.___-J.
x
X
'-._ _ _--'
/
----I
\
[Note2J
X
/
External Timing
CLK
Ao.CS
RD,WR
Notes:
[1J Setting ROM flag to "1" [MOV@DR, XXX or MOV XXX, DRJ
[2J The ROM flag is recognized as "0" from this instruction
49NR-273B
19
tttrEC
JlPD77C25/77P25
NormalOperation, 16-8it Mode
Internal Timing
Instruction
execute
timing
ROM flag
==x.
[Note 1]
X'-_-JX. . . _--JX. . ._--JX'-_-JX'-_-JX
[Note 2]
)(
/
_ _---J
External Timing
ClK
Ao, CS
RD,WR
Notes:
[1] Setting ROM flag to "1" [MOV@DR, XXX or MOV XXX, DR]
[2] The ROM flag is recognized as "0" from this instruction
49NR-274B
Port Operation
Internal Timing
Instruction
execute
timing
External Timing
CLK
PO,Pl
Note:
[1] Selling Po or Pl [LDI@SR, fmm]
49M-OOOO48A
NEe
,.,PD77C25/77P25
DMA Operation, 8-Bit Mode
Internal Timing
----v
Instruction
executenmlng - - "
ROM flag
[Note t]
X
X
X
X
_ \.
_ _ _ _--J_ \.
_ _ _ _--J_ \.
_ _ _ _-.I
/
-----'
[Note 2]
X
/
External Timing
.....
ClK
m.I:I~
ORO
I
DACK
RD,WR
Notes:
[1] Setting ROM flag to "1" [MOV@DR,XXXorMOVXXX, DR]
[2] The ROM flag is recognized as ''0'' from this instruction
49M-00OO5OB
21
NEe
pPD77C25/77P25
DMA Operation, 16-8;1 Mode
Internal Timing
ex~~:~~:~~==X
RaMl/ag
[NotelJ
x"'___-Ix"'___-Ix"'___-Ix"'___--Ix. .___~E
/
----'
External Timing
CLK
ORO
DACK
RD.WR
Notes:
22
[lJ Setting ROM flag to .~. [MOV@DR. XXX or MeV XXX. DRJ
[2J The ROM flag is recognized as "0" from this instruction
\'-----11
ttiEC
IIPD77C25/77P25
Reset Operation
Internal Timing
rnsetruxecctuliOen
timing
r~i~:
---v
---A____J.X1..._ _ _ _.....JX
NOP
X
NOP
X
NOP
X
NOP
X
)(
I..._ _
IO_Hl___
_____________"~________________________-L~
_ __
External TIming
CLK
III
RST
\ - - - - - - - --tRST--I--------i
roo
I
I
tOCRS
PO, P1
)
r
tOCRS
~~-----------~-A------~Of~----------------'~--so
r
49NA·27SB
23
t-{EC
pPD77C25/77P25
Interrupt Operation
Internal Timing
Instruction
execute
timing
Elbit
\'-------/
/
-----'
\'-----
External Timing
ClK
INT
Notes:
[1] Setting EI bit to "1" [lOI@SR, Imm]
[2] EI bit can be set to "1" from this instruction
49NR-2768
PROM Read Timing
VIHR
RST
---.J
VIH
~
-tOAO-
\
CE
!.--toco-
~
tSRSCE
VIH
OE
Vil
1\
l-tOOOR-Oo
~
!--------tSRSOE
VIH
07- 0 0
Vil
«~
~)~
49NR-282B
24
NEe
IIPD77C25/77P25
PROM Program Timing
RST
A13 -AO
vpp
vpp
VOO
tHCO
VOO +1
r+-----+--~--------+_~;.--r_----+_--+_----
VOO
tsoc
tHCA
~---+--------~~;.
CE
;.~-----------------
OE
VIL
49NFI-2818
SERIAL TIMING
Figure 7. Serial Input Operation
Serial Output Case 1: SOEN Asserted in
Response to SORQ
SCK
Sl
Figure 8 shows timing for serial output when SOEN is
asserted in response to SORa. If SOEN is held inactive
until after SORa is asserted, and then SOEN is asserted at least tSSES before the falli ng edge of SCK, SO
will become valid tDSLSO after the falling edge of SCK
for use by an external device at the subsequent rising
edge of SCK.
_---<>C
49M~00052A
Note that, although figure 8 shows SOEN being asserted during a different SCK pulse than the one in
which SORa is asserted, it is permissible for these to
occur during the same pulse of SCK as long as SOEN is
still asserted tssES before the falling edge of SCK.
25
t\'EC
pPD77C25/77P25
Figure 8. Serial Output Case 1
SCK
SORO
SOEN
so
-----------(1
49M-000053B
Serial Output Case 2: SOEN Active Before SORQ
Is High
Figure 9 shows output timing when SOEN is active
before SORQ is high. If SOEN is held active before
SORQ is high, data will be shifted out whenever it
becomes available in the serial output register (assuming previous data is already shifted out). In this case,
SORQ will risetossQ after a rising edge of SCK. Thefirst
SO bit occurs tosLSO after the next falling edge of SCK
for use by an external device at the subsequent rising
edge of SCK.
Subsequent bits will be shifted out tosLSO after subsequent falling edges of SCK for use at subsequent rising
edges of SCK. The last bit to be shifted out will also
follow this pattern, and will be held valid tFSSO after the
corresponding falling edge of SCK at which it is to be
used. SORQ will be held tOSSQ after this same rising
edge of SCK, and then removed.
Serial Output Case 3: SOEN Released During a
Transfer
If SOEN is released while SCK is in the middle of a
transfer, as shown in figure 10, at least tHssE after the
falling edge of SCK, then the next bit will be shifted out
tOSLSO after the falling edge of SCK for use at the
subsequent rising edge of SCK. SO will go inactive
tFSSO after the falling edge of SCK.
Note: For all its uses, SOEN must not change state within
tSSES before or tHSSE after the falling edge of SCK;
otherwise the results will be indeterminate.
Figure 9. Serial Output Case 2
SCK
SORO
SOEN
tFSSO
tDSLSO
so
First bit
Last bit
valid
valid
49t.1-OOOO54B
26
NEe
pPD77C25/77P25
Figure 10. Serial Output Case 3
SCK
SOEN
so
49M-OOOO5SB
Serial Input
Serial input timing (figure 11) is much simpler than
serial output timing (figure 12). Data bits are shifted in
on the rising edge of SCK if SIEN is asserted. Both SIEN
and SI must be stable at least tsslS before and tHSSI
after the rising edge of SCK; otherwise the results will
be indeterminate.
Figure ". Serial Input Timing Example
Inlemal TIming
Instruction
execute
timing
n
SIAKflag
--------------------------~)~1~--------------------j
~-------------------
Extemal TIming
Noles:
[1] Setting SIAK flag 10 "0" [MOV XXX. Sij
The SIAK flag is recognized as ·~·from Ihis instruction
49NR-277B
27
NEe
pPD77C25/77P25
Figure 12_ Serial Output Timing Example
Internal Timing
Instruction
execute
timing
SOAK flag
/
------'
\~--~hrr----------------
External Timing
ClK
SCK
SORQ
SOEN
tFsso3
so
Notes:
X _-------
[1) Setting SOAK flag to "1" [MOV@SO.XXX.)
[2) The SOAK flag is recognized as ''0. from this instruction
49NR·278B
!-,PD77P25 PROM
The pPD77P25 has a PROM-one-time programmable
(OTP) or ultraviolet erasable (UVE)-consisting of a 2K
x 24-bit instruction ROM and a 1K x 16-bit data ROM.
Figure 13. Instruction ROM
24bils
23
Internal word address
Data is written to or read from the PROM in 8-bit bytes.
Because instruction words are 24 bits and data words
are 16 bits, special byte addresses are assigned to the
instruction ROM (OH-1FFFH) and data ROM (2000H27FFH) as shown in figures 13 and 14.
Each internal word address of the instruction ROM is
equivalent to three byte addresses used by external
devices plus one dummy byte address. For example, in
figure 13, internal word address OH corresponds to byte
addresses OH, 1H, and 2H plus dummy byte address
3H (not shown).
28
~~ I
··
·
15
7
OH
1H
4H
5H
I
I
I
I
7FEH
Note:
Numeric values within the boxes are byte addresses af
the instruction ROM viewed from an external device
49NR-279A
NEe
,.,PD77C25/77P25
Figure 14. Data ROM
(4) Output the programmed data to the data bus (0 0 0 7) by applying 0 to OE while CE is 1 (program
verify mode).
-16bits--
Internal word address
OH
1-="'-'--+--""""'-'---1
1H
1-="'-'--+--"""""-'---1
•
I
•
I
•
I
(5) Repeat steps 2 through 4, 25 times maximum until
the data is properly written to the specified address.
(6) After verifying that the data has been properly
programmed, apply additional pulses by setting
OE to 1 (clear CE to 0). The pulse width is 3X ms if
the number of repetitions in steps 3 and 4 is X.
3FEH 1-'-'-'-''-'-'--+-=-=--==---1
3FFH L.....,;;;.;.;..;;;;.;.........:;;;.;.;..;.:.....
MSB
Note:
Numeric values within the boxes are byte addresses
of the data ROM viewed from an external device
49NR-280A
UVEPROM Erasure
Data in a UVEPROM can be erased by exposure to light
with a wavelength shorter than 400 nm. Usually, ultraviolet light with a 254-nm wavelength is used. The
erasure process, which sets all data bits to 1's, must
take place before data is programmed to a UVEPROM.
The total light quantity required to completely erase the
written data is 15 Ws/cm 2 , equivalent to exposure to a
UV lamp with a rating of 12,000 pW/cm 2 for about 20
minutes. A longer time may be necessary because of
such factors as the age of the UV lamp and stains on the
package window. The window must be positioned
within 1 inch of the UV lamp.
If the UVEPROM is exposed to direct sunlight or fluorescent light for a long time, the data might be destroyed. To prevent this, mask the window with a cover
or film after the erasure process.
Data Programming Procedure
Followi ng is the procedure for programming the 77P25.
Table 15 shows the reassigned pin functions when
writing/reading the PROM.
Since the area from byte address 2800H to 3F FFH is for
internal testing, the area for the instruction ROM and
data ROM must be set from byte address OH to 27F FH.
Set the data to dummy byte addresses in the instruction ROM area to FFH in the normal programming.
(1) Apply + 12.5 V to RST (pin 16), + 6 V to Voo, and
+ 12.5 V to Vpp. This causes the PROM to enter
program mode.
(2) Specify the desired ROM byte address from
address input pins Ao to A 13.
The above procedure completes writing one byte of
data. If the data will not be properly programmed even
after steps 2 to 4 have been repeated more than 25
times, the 77P25 is defective.
Table 14. Pin Functions for PROM Programming/
Reading
Program
Mode
Normal
Mode
Ao
Ao
A1
WR
A2
SORO
A3
SO
A4
Sl
A5
SOEN
A6
SIEN
A7
SCI
As
INT
Ag
ClK
Function
Input address (viewed from external device)
for programming/reading PROM (instruction
ROM and data ROM).
A10
P1
A11
Po
A12
ORO
A 13
DACK
0 0-0 7
0 0-0 7
Input/output data for PROM (instruction
ROM and data ROM)
PROM program strobe signal (active low)
CE
CS
OE
RO
PROM read strobe signal (active low)
vpp
vpp
Power pin for programming PROM; apply
+12.5 V for writing and +5 V for reading.
voo
Voo
Power pin; apply +6 V for programming and
+5 V for reading.
GNO
GNO
Ground pin
RST
Sets PROM program or read mode. Mode is
set when +12.5 V is applied.
(3) Program the data on the data bus (0 0-0 7) by
applying 0 to CE while OE is 1 (program mode).
29
NEe
IIPD77C25/77P25
Data Reading Procedure
(1) Apply + 12.5 V to RST, +5.0 V to VDD, and +5.0 V to
Vpp. This causes the PROM to enter read mode.
(2) Specify the desired ROM byte address from the
address input pins Ao to A13.
(3)
Data will be output to the data bus (00-07) by
clearing OE and CE to O.
By connecting to a PROM programmer, the EVAKIT is
also used to prepare 77P25 PROMs intended for prototyping and small volume applications. A program
adaptor, PA-77P25, is provided for use with the data I/O
programmer.
Code submittal for the mask ROM pP077C25 is accomplished by preparing a 27C256A or pP077P25 PROM
using the same programming device.
Instruction ROM Code Protection
SYSTEM CONFIGURATION
A word of the instruction ROM can be protected if data
FEH is programmed to a dummy byte address. For
example, byte addresses OH, 1H, and 2H (word address OH) are protected if FEH is programmed to
dummy byte address 3H. Following is the procedure for
protecting the instruction ROM.
Figures 15, 16, 17, and 18 show typical system applications for the 77C25.
(1) Set data FFH to the dummy addresses; then perform the data program procedure.
Figure 15. Spectrum Analysis System
77C25
~
• Microphone
• Thermal
• Pressure
• light
(2) Verify the programmed data by the data read procedure.
Product Example
Pe.
••
\
DEVELOPMENT TOOLS
i
i...•.\..........I.
(3) Set data FEH to the dummy addresses; again perform the data program procedure.
~
BPF = Bandpass filter
Freq
83NR·8072A
For software development and assembly into object
code, a relocatable assembler (RA77C25) is available.
This software is available to run on MS-OOS®, CP!M®,
VAX®NMS®, and VAX/UNIX® systems.
For debugging, a hardware emulator (EVAKIT-77C25)
provides in-circuit, real-time emulation of the 77C25.
Features of the EVAKIT-77C25 include break!step emulation, symbolic debugging, and on-line assembly!
disassembly of code.
The EVAKIT-77C25 connects via a probe to the target
system for test and demonstration of the final system
design. It also connects to the host development system via an RS-232 port. Using Kermit or NEC's EVA
communications program, code can be downloaded or
uploaded between development system and EVAKIT.
MS-DOS is a registered trademark of Microsoft Corporation.
CP/M is a registered trademark of Digital Research. Incorporated.
VPJ( and VMS are registered trademarks of Digital Equipment Corporation.
UNIX is a registered trademark of UNIX System Laboratories, Incorporated.
30
Figure 16. Analog-to-Analog Digital Processing
System Using a Single 77C25
Analog
In
Analog
OUt
so '----'-----,
. - - - ' - _...... SI
L -..." -
,.-,
SIEN
SOEN ,- , . - ...........
SORQ
RF == Reconstruction
filter
BPF = Bandpass filter
8aNR-8073A
fttIEC
JlPD77C25/77P25
Figure 17. Signal Processing System Using
Cascaded 77C25's and Serial
Communication
Analog
Figure 18. Signal Processing System Using
77C25's As a Complex Computer
Peripheral
Analog
Out
In
Host
Memory
CPU
System Bus
OR01
OACK1
BPF = Bandpass filter
RF = Reconstruction filter
•
OMA
Controller
ORO(n)
83NR-8074A
nC25
so
DACK (n)
83NR-8075A
31
pPD77C25/77P25
32
ttt{EC
t-IEC
NEC Electronics Inc.
Description
The J.lPD77220 is a highly accurate digital signal processor (DSP). The pPD77220 has a mask ROM; the
J.lPD77P220 has a one-time programmable (OTP) or an
ultraviolet erasable (UVE) PROM. There are also two
speed versions, 8 and 10 MHz. The part numbers of
10-MHz versions have a -10 suffix. The 8- and 10-MHz
units process 24-bit fixed-point data at 122 and 100 nsf
instruction.
Note: Unless excluded by context, J.lPD77220 means both
the J.lPD77220 and the J.lPD77P220.
The internal circuit consists of a multiplier (24 x 24
bits), instruction ROM (2K words x 32 bits), data ROM
(1K words x 24 bits), and two independent data RAMs
(256 words x 24 bits each).
The J.lPD77220 has two operation modes: master and
slave. These modes can be set using external pins. In
master mode, an external 8K-word memory can be
added, and 4K words in the memory can be used as an
instruction area. In slave mode, the J.lPD77220 operates
as an I/O processor for the host CPU. An external
8K-byte data memory can be added.
Features
o Processes 24-bit fixed-point data
- 24-bit fixed-point multiplication circuit
24 bits x 24 bits -+ 47 bits
-47-bit ALU with eight working registers
- 47-bit barrel shifter
o High-speed operation and efficient data transfer
-Instruction cycle 122 or 100 ns
- Three-stage pipeline processing
- Dedicated data buses in the internal RAM,
multiplication circuit, and ALU
50119-1
JlPD77220,77P220
24·Bit Fixed-Point
Digital Signal Processor
o Architecture suitable for digital signal processing
- Two built-in independent data RAMs and data
RAM pointers
- Each data RAM pointer consists of a base
pointer and index register: the base pointer
performs a ring count operation in any range
- Data ROM pointer steps forward in two-step
increments (2N) in addition to normal
autoi ncrement!autodecrement addressi ng
o Flexible external interfaces
o Two modes of operation: master or slave
-In master mode, 4K words by 32-bit instruction
area
- High-speed access to external memory
Master mode: 4K words by 24 bits
Slave mode: 4K words by 8 bits
o CMOS process
o Single
+ 5-volt single power supply
o 68-pin PGA array and PLCC packages
Ordering Information
Part Number
Package
Max Speed
ROM
IlPD77220R
S8-pin PGA
8 MHz
Mask
8 MHz
L
S8-pin PLCC
R-l0
S8-pin PGA
10 MHz
L-l0
S8-pin PLCC
10MHz
IlPD77P220R
L
S8-pin PGA
8 MHz
UVE
68-pin PLCC
8 MHz
OTP
R-l0
S8-pin PGA
10 MHz
UVE
L-l0
S8-pin PLCC
10MHz
OTP
..
NEe
IIPD77220, 77P220
Pin Configurations
6B-PinPLCC
DO
SORQ
SOCK
SICK
SO
Voo
SI
SOEN
SIEN
GNO
A7
AS
AS
GNO
Al0
All
AX
VOO
D8 (VOO)
D9(V01)
010 (U02)
GNO
011 (U03)
013 (U05)
CLKOUT
X2
Xl
NoI8a,
The symbOl In ( ) denotes !he pin symbol applicable 10 !he pin In !he Slave mode.
The Vpp pin Is only u88d for !he I'PD77P220.
2
012 (U04)
014 (U06)
015(U07)
NEe
pPD77220,77P220
Pin Configurations (cant)
68-Pin Ceramic PGA
Bottom View
Top View
11
r
10
""\
9
8
7
8
5
4
3
2
.J
IA
1
B
C
0
E
F
G
J
H
K
L
000000000
0©0000000©0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
O©OOOOOOO©O
000000000 ,,'
r~
L
J
K
H
G
F
E
0
C
B
A
Mark
To..,.,aI Symbol
To.".,alSymboI
TennklaJ
No.
Slave
Master
Modo
Modo
TerrrInaI
No.
Mastar
Mode
Slave
Mode
Telll'lnaJ Symbol
To....nal Symbol
To....nal
No.
Master
Modo
023
Slavo
Modo
TonnklaJ
No.
V015
Moster
Modo
I
Slave
Mode
A2
A7
Bg
01S
V05
FlO
i<4
Veo
AS
Ag
Bl0
014
VOS
F11
Vpp
I-----j Uf----<
~T~
83ML-6887A
B3ML_
15
~
NEe
pPD77220, 77P220
Figure 3. Switching Characteristics
Input Waveform
2.4 V
0.4 V
X
V--
X
V--
2.2V
2.2V
\..."'0"'.8...:.V_ _ _ _ _-'0;;.:.8'-'V_A--
_ _ _--'.
Output Waveform
_ _ _--'.
2.2V
2.2V
\..
. ..;,0..;,.8_V_ _ _ _ _O_.8"--'V" - - 83ML..fi901lA.
Figure 4. Clock Input/Output
t=
Clock Input
X1
tCYX
1
----~t,~"Jt=,=-=f
\1
1
:. r'=
Clock Output
X1
,~, -
\,------,1
\'-----JI
:r~'
~_____t_HX_C_~--,t
I
CLKOUT
X1
14----------------------------tCYS--------------------------~~
SCK
[Note 1]
SICK,
SOCK
[Note 2]
~-----------tSSH------------.~1 ~-----------tSSL------------~
Notes:
At output Urne
At output Ume (Input asynchronous with X1 Is possible.)
[1]
[2]
83Ml-6901B
16
NEe
pPD77220, 77P220
Figure 5. Instruction Read Operation (Master Mode Only)
X1
CLKOUT
00-031 - - - - {
83ML.....,.
17
ttlEC
IIPD77220, 77P220
Figure 6. Data Read Operation
Xl
CLKOUT
t------tWR1,tWA2 - - - - + j
1+---+1 tSR01, tSR02
0 31 - - - - - - " " " "
Do[Note 1)
00-0 7
[Note 2)
Notes:
[1) Master Mode
[2) Slave Mode
..ML.......
18
NEe
,.,PD77220, 77P220
Figure 9. Host Read Operation
\--i
ISCR"
IWHRO
IHRC
IHRV
•
\
_IOHRI _ _
~ IFHRI
83ML-6883B
Figure 10. Host Write Operation
ISCW
I
!-----.
-+
I--
IHWC
IHRV
IWHRO
\
\
100-I015--F-~~ISIHW_ _ _ IHHWI
20
NEe
,.,PD77220, 77P220
Figure 11. ROM Port
X1
CLKOUT
RQM
.~
HRD,HWR
I
PO, PI
'...----tDxp----l~.
P2,P3
----~X.-------83Ml.Q!948
Figure 12. Interrupt Reset Timing Chart
RESET
NMI,INT
s
tRINT==I
~
'------
tiNT
83ML-68918
21
NEe
IIPD77220, 77P220
Figure 13. Serial In
1---tCYS---J
SCK
(SICK) _ _--'
Figure 14. Serial OUT 1 (SOEN Interrupt Control)
SCK
SORQ
R
___~r=
'---I
so
22
•
tDSHSO
_
VALID
K
tHSHSO
VALID
X,...---:r--'. . __
VALI_D_..Jt-
83ML-6898B
NEe
IIPD77220, 77P220
Figure 15. Serial OUT 2 (SOEN Control: SOEN Low AT SCK is Low Level
SCK
..
SORQ
I
so--------------~
VALID
83ML-68978
Figure 16. Serial OUT 3 (SOEN Control: SOEN Low AT SCK is High Level
SCK
SORQ
so------------------------~
VALID
83ML.fi898B
23
NEe
pPD77220,77P220
DATA FORMAT
Figure 17. Fixed-Point Data Format
The pPDn220 can process fixed-point data Data is
represented by a 2's complement, and the highestorder bit of fixed-point data indicates the sign. See
figure 4. Table 3 shows the 24-bit fixed-point data
format. Table 4 shows the 47-bit fixed point data.
Numeric data is processed in fixed-point data format,
and the decimal point is positioned between the sign
bit and the following bit.
47 Bits
47-BlIBus ~
~~r~~L-
__________________________
~
Sign
24 BIts
24-8ftBus ~
R~~r~~L-
______________~
SIgn
Table 3. 24-8it Fixed-Point Internal Data Format
Value
Binary Notation
Hexadecimal Notation
Conversion to Decimal Number
Maximum Positive Value
0111 ..... 1111
7FFFFFH
1.0 - 2.23 - 1.0
0111 ..... 1110
7FFFFFH
1.0 - 2"22
1.0-2-1 = 0.5
0100 ..... 0000
Minimum Positive Value
0000 ..... 0001
Zero
0000 ..... 0000
Maximum Negative Value
1111 ..... 1111
000001H
0.0
FFFFFFH
1000 ..... 0001
~
-1.2xl0-7
-(2-1) = -0.5
1100 ..... 0000
Minimum Negative Value
-(2"23)
800001H
-1.0+ 2-23
-1.0
1000 ..... 0000
Table 4. 47-8it Fixed-Point Internal Data Format
Value
Binary Notation
Hexadecimal Notation
Conversion to Decimal Number
Maximum Positive Value
0111 ..... 1111
7FFFFFFFFFFEH
1.0-2"46 -1.0
0111 ..... 1110
7FFFFFFFFFFCH
1.0 - 2"45
0100 ..... 0000
400000000000H
1.0-2"1 = 0.5
Minimum Positive Value
0000 ..... 0001
000000000002H
2-46 = 1.4 x 10-14
Zero
0000 ..... 0000
OOOOOOOOOOOOH
0.0
Maximum Negative Value
1111 ..... 1111
FFFFFFFFFFFEH
_(2"46)
1100 ..... 0000
COOOOOOOOOOOH
-(2- 1) = -0.5
1000 ..... 0001
800000000002H
-1.0
1000 ..... 0000
800000000000H
-1.0
Minimum Negative Value
+
= -1.4 x 10-14
2- 46
Conversion of data (47 bits) into hexadecimal format ranges from the highest-order bit (sign bit) to the lowest-order bit sequentially.
24
fttIEC
pPD77220,77P220
INSTRUCTIONS
Table 5.
All pPD77220 instructions consist of a 32-bit word. The
instructions fall into three categories:
Symbol
(31·27)
Operation
NOP
00000
No operation
INC
00001
Increment
DEC
00010
Decrement
ABS
00011
Absolute
NOT
00100
Not
NEG
00101
Negate
SHLC
00110
Shift left with carry for double
precision
SHRC
00111
Shift right with carry for
double precision
01000
Rotate left
• Operation instructions
• Branch instructions
• Load instructions
Operation Instructions
An operation (OP) instruction is an ALU operation
instruction where 22 different operations may be specified in the upper five bits. Figure 5 shows the bit format.
Pointer modifications may be specified in the CNT
field. Transfers may also be specified within the SRC
and DST fields of an OP instruction. When all fields are
specified in an OP instruction, several different tasks
are performed simultaneously.
OP Field. The 5-bit OP field specifies the operation
type in the ALU. Table 5 lists the 22 types of operations
it may contain.
CNT (Control) Field. The CNTfieid is 12 bits long and
specifies a pointer, flag operation, register switch-over,
data transfer format, and loop counter decrement.
The control field bit configuration is shown in figure 6.
The field has 22 types of subfields. Table 6 describes
the subfields.
OP Field Specifications
OP Field
ROL
Table 5.
Symbol
OP Field Specifications
OP Field
(31-27)
ROR
01001
Rotate right
SHLM
01010
Shift left multiple (see note)
SHRM
01011
Shift right multiple (see note)
SHRAM
01100
Shift right arithmetic multiple
see note)
CLR
01101
Clear
ADD
10000
Add fixed-point data
SUB
10001
Subtract fixed-point data
ADDC
10010
Add fixed-point data with
carry
SUBC
10011
Subtract fixed-point data with
carry
Figure 1B. Operation Instruction Format
31
I , Ii ' I , , , , 'i:
o
' ,,,I i I ,a, I 'r" I ,ii, ,
Operation
CMP
10100
Compare
AND
10101
AND
OR
10110
OR
XOR
10111
Exclusive OR
83ML06982A
Multiple value is in SVR or specification value of SHV bit.
25
.-
NEe
IIPD77220, 77P220
Table 6. Control Field Specifications
Group
Field
Function
Interrupt
EM
Enables/disables maskable interrupt
BM
Sets and clears maskable interrupt input flag
PSW
FIS
PSW control
FC
Switches over PSWO, PSWl
ROM pointer
RP
Rules ROM pointer count operations
RPC
Specifies n value in ROM pointer operation
RPS
Specifies low,order nine bits of data ROM
address
MO
Specifies base pointer 0 and Index register 0
Ml
Specifies base pointer 1 and index register 1
DPO
Rules count operations of base pointer 0 and
index register 0
DPl
Rules count operations of base pointer 1 and
index register 1
BASEO
Specifies counter length of modulo counter
base pointer 0
BASEl
Specifies counter length of modulo counter
counter base pointer 1
WI
Specifies transfer format when working register
is specified in the DST field
WT
Specifies transfer format when working register
is specified in the SRC field
Shift specification
SHY
Specifies amount of shift for 47 -bit fixed-point
data
Data memory access
RW
Specifies input/output operation for external
memory
EA
Address register increment and decrement
P2
Controls signal,output of pins with the same
name
P3
Controls signal output of pins with the same
name
Loop counter
L
Loop counter decrement
Jump
NAL
Specifies unconditional jump address
RAMO/RAMl pointers
Data format conversion
General-purpose output port
* Effective starting with current instruction.
-->
Effective starting with the next instruction.
26
Effective
*/-
*/-
NEe
pPD77220, 77P220
P Field. The 2-bit P field (bits 14, 13) specifies the
source of input to the register, which is used as an input
to the ALU for operations requiring two operands. The
internal data bus, MPY output, RAMO, or RAM1 can be
specified. Table 7 shows the field specifications.
Table 7_ P Field Specifications
Q Field. The 3-bit Q field (bits 12-10) specifies the
source of input to the Q register, which is the second of
two ALU input registers.
One of the working registers, WRO to WR7, must be
specified in the Q field. The result of the operation is
placed in the working register specified in the Q field.
Table 8 provides the Q field specifications.
Symbol
Bit 14
Bit 13
Input of P Register
19
0
0
PU bus
TableB.
M4
0
Multiplier output register (MPY output)
Symbol
Bit 12
Bit 11
Bit 10
Register
AAM block 0
WAO
0
0
0
Working register 0
AAM block 1
WA1
0
0
WR2
0
WA3
0
RAMO
0
RAM1
Figure 19. CNT Field Bit Configuration
31
'Z1
15
I,Ii ' ! , , , , ,c" ',
!
12
!
!
--
/'
23
21
22
0
ila, ! 'r.' ! ,S,' ,
/'
24
4
9
!
17
18
16
--
15
26
25
0
0
0
1
0
0
EA
0
1
0
1
RP
MO
OPO
FC
0
1
1
0
RP
Ml
DP1
FC
20 119
Ml
MO
0
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
OPl
OPO
OPl
OPO
RP
MO
BASE 0
M1
-
P21 EM
BM
I
RW
1
0
1
0
0
WI
1
0
1
0
1
-
1
0
1
1
0
FIS
1
0
1
1
1
1
1
0
RPS
1
1
1
NAL
0
WA5
0
WR7
Working register 2
Working register 3
WR4
WA6
Working register 1
0
0
Working register 4
Working register 5
0
Working register 6
Working register 7
SR C (Source) Field. The 5-bit SRC field (bits 9-5) holds
the source register for a transfer instruction. Table 9
lists the 32 types of registers that may be specified in
this field.
FC
FC
BASEl
RPC
P3
L
a Field Specifications
L
FC
L
FC
L
Fe
L
FC
WI
i.
FC
-
L
-
SHV
B3ML-6983A.
27
~
NEe
I'PD7722Q, 77P220
Table 9. SRC Field Specifications
Table 10. DST Field Specifications
Symbol
SRC Field (9-5)
Selected Source Register
Symbol
DST Field (4-0)
Selected Destination Register
NON
00000
Non-select ion
NON
00000
Non-selection
RP
00001
ROM'pointer
RP
00001
AOM pointer
PSWO
00010
Program status word 0
PSWO
00010
Program status word 0
PSWl
00011
Program status word 1
PSWl
00011
Program status word 1
SVR
00100
SVR (shift value register)
SVR
00100
SVA (shift value register)
SR
00101
Status register
SA
00101
Status register
LC
00110
Loop counter
LC
00110
Loop counter
STK
00111
Stack
STK
00111
Stack
M
01000
M register
LKRO
01000
L register (RAM 0 to K register)
ML
01001
Low 24 bits of M register
KLAl
01001
K register (RAM 1 to L register)
ROM
01010
Data ROM
TA
01011
Temporary register
TR
01011
Temporary register
AA
01100
Address regi ster
AR
01100
Address register
SO
01101
Serial output register
SI
01101
Serial input register
DA
01110
Data register
DR
01110
Data register
DAS
01111
Data register for slave
DRS
01111
Data register for slave
WAO
10000
Working register 0
WRO
10000
Working register 0
WAl
10001
Working register 1
WRl
10001
Working register 1
WR2
10010
Working register 2
WR2
10010
Working register 2
WA3
10011
Working register 3
WA3
10011
Working register 3
WA4
10100
Working register 4
WA4
10100
Working register 4
WA5
10101
Working resister 5
WR5
10101
Working resister 5
WA6
10110
Working register 6
WA6
10110
Working register 6
WR7
10111
Working register 7
WF1I
10111
Working register 7
AAMO
11000
AAMO
RAMO
11000
RAMO
RAMl
11001
RAM 1
RAMl
11001
RAM 1
BPO
11010
Base pointer 0
BPO
11010
Base pointer 0
BPl
11011
Base pointer 1
BPl
11011
Base pointer 1
IXO
11100
Index register 0
IXO
11100
Index register 0
1X1
11101
Index register 1
IXl
11101
Index register 1
K
11110
K register
K
11110
K register
L
11111
L register
L
11111
L register
Branch Instructions
DST (Destination) Field_ The DST field (bits 4-0) is 5
bits long and specifies the destination register for a
transfer instruction. Table 10 lists the 31 destinations
that may be specified in the DST field.
Branch instructions specify a conditional jump, an
unconditional jump, subroutine call, or return. The
format of the branch instruction, consisting of five
fields, is shown in figure 7.
Note that the SRC and DST fields may be included as
part of the branch instruction. This data transfer will
take place regardless of any condition upon which a
jump may be dependent.
28
NEe
,.,PD77220, 77P220
B Field. This field (bits 31-28) indicates a branch instruction. The value of this field is always 1lOt
C Field. This 5-bit field (bits 14-10) indicates the nature
of the branch instruction. Table 11 summaries the
branch conditions that can be specified.
Table 11.
Branch Condition Summary
Symbol
C Field (14-10)
JMP
00000
Jump with no condition
CALL
00001
Subroutine call
Jump with Condition
RET
00010
Return
JNZRP
00011
Jump if ROM pointer is not zero
JZO
00100
Jump if zero flag 0 is set
JNZO
00101
Jump if zero flag
JZl
00110
Jump if zero flag 1 is set
SRC Field. The SRC field (bits 9-5) specifies a type of
source register for a transfer instruction. There are 32
possible types.
JNZI
00111
Jump if zero flag 1 is reset
JCO
01000
Jump if carry flag 0 is set
JNCO
01001
Jump if carry flag 0 is reset
CST Field. The CST field (bits 4-0) indicates the type of
destination register to be used for a transfer instruction. There are 31 possible types.
JCl
01010
Jump if carry flag 1 is set
JNCI
01011
Jump if carry flag 1 is reset
JSO
01100
Jump if sign flag 0 is set
Load Instructions
JNSO
01101
Jump if sign flag 0 is reset
JSl
01110
Jump if sign flag 1 is set
JNSl
01111
Jump if sign flag 1 is reset
JVO
10000
Jump if overflow flag
JNVO
10001
Jump if overflow flag 0 is reset
JVl
10010
Jump if overflow flag 1 is set
JNVl
10011
Jump if overflow flag 1 is reset
JNFSI
10110
Jump if Sl register is not full
JNESO
10111
Jump if SO register is not empty
JIPO*
11000
Jump if input port 0 is on
JIP1*
11001
Jump if input port 1 is on
JNZIXO
11010
Jump if index register 0 is nonzero
JNZIXl
11011
Jump if index register 1 is nonzero
JNZBPO
11100
Jump if base pointer 0 is nonzero
JNZBPI
11101
Jump if base pointer 1 is nonzero
JRDY
11110
Jump if ready is on
JRQM*
11111
Jump if request for master is on
NA Field. The destination address of the branch is
contained in the 13-bit NA field (bits 27-15). Note that
the most significant bit of the NA field is used to
determine whether the destination address is in internal or external instruction memory.
The load instruction consists of three fields as shown in
figure 8. This instruction loads 24-bit data specified in
the 1M field into the register specified in the DST field.
The data is input to each register through the main bus.
The value of the LDI field is always 111.
Figure 20. Branch Instruction Format
Figure 21. Load Instruction Format
Ii
[1'1"
I
I
I
I
I
I
I
I
I jl
I
I
I
I
I
I
I
I
I
I
I
'1l':!1
a is reset
•
a is set
* Valid for slave mode only.
29
I
I
~EC
pPD77220, 77P220
PROM INTERFACE
UVEPROM Erasure
The pP077P220 has a PROM-one-time programmable
(OTP) or ultraviolet erasable (UVE)-consisting of a
2K-word x 32-bit instruction ROM and a 1K-word x
24-bit data ROM.
Data in the UVEPROM can be erased by exposure to
light with a wavelength shorter than 400 nm. Usually,
ultraviolet light with a 254-nm wavelength is used. The
erasure process, which sets all data bits to 1's, must
take place before data is programmed to a UVEPROM.
The 32-bit instruction words and 24-bit data words
require special byte addresses because data is written
to and read from the PROM in 8-bit bytes. Figure 22
shows the special byte addresses assigned to the data
ROM (2000H to 2003H).
Each internal word address for the data ROM is equivalent to three byte addresses used by external devices
plus one dummy byte address. For example, in figure
23, the internal word address OH corresponds to 3 byte
addresses (2001H to 2003H) plus one dummy byte
address (2000H)
Figure 22. Instruction ROM Memory Map
0(
IntemaJ word address
I=
~
I
··· II
··
15
1H
2H
4H
5H
6H
I
0
7
OH
I
3H
I I
7H
I
I
7FEH
1FF8H
II
1FF9H
II
1FFAH
II
1FFBH
lI
7FFH
1FFCH
I
1FFDH
I
1FFEH
I
1FFFH
I
MSB
Nota: The number In each box Indlcataa the byte address of
the InstrucUon ROM 89 viewed from outside.
Figure 23. Data ROM Memory Map
dummy """0(;----24 blts---~
...
byte 23
Intame) word address
15
7
0
I
I
I
!= I := I := I := I:: I
: I
-=::--1:I
: III-=-+-=".,.-11---:....,..,.-+I
3FEH
I
2FF8H
2FF9H
I
2FFAH
3FFH
I
2FFCH
2FFDH
I
2FFEH
MSB
Nota: The number In each box lndlcataa the byte address of
the data ROM 89 viewed from outside.
30
I
I
If the UVEPROM is exposed to direct sunlight or fluorescent light for a long time, the data might be destroyed. To prevent this, mask the window with a cover
of film after the erasure process.
Data Programming Procedure
32 bits
23
31
The total light quantity required to completely erase the
written data is 15Ws/cm2 , equivalent to exposure to a
UV lamp with a rating of 12,000 pW/cm 2 for about 20
minutes. A longer time may be necessary due to factors
such as the age of the UV lamp and stains on the
package window. The window must be positioned
within 1 inch of the UV lamp.
2FFBH
2FFFH
I
This section describes how to program the PROM.
Table 12 shows the reassigned pin functions when in
PROM program/read mode. Figure 24 shows the onchip PROM program timing.
Since no PROM cell exists for the data ROM dummy
byte addresses, set the dummy byte addresses to FFH,
the default data for normal programming. The data
programming procedure is as follows:
(1) Enter PROM .E!£9ram mode by applying + 12.5
±0.5 V to the SIEN/PROG PIN, +6 V to the Voo pin,
and + 12.5 ±0.3 V to the Vpp pin.
(2) Specify the desired ROM byte address from the
address input pins Ao - A13·
(3) Program the data on the data bus (Do - 0 7) by
applying 0 to the CE pin and 1 to the OE pin.
(Program mode.)
(4) Output programmed data to the data bus (Do - 07)
by applying 0 to the OE pin and 1 to the CE pin.
(Program verify mode.)
(5) Repeat steps 2 through 4 to a maximum of 25 times
until the data is properly written to the specified
address.
(6) After verifying that the data has been properly
programmed, apply an additional overprogram
pulse by setting OE to 1 (clear CE to 0). The
overprogram pulse width is determined by multiplying the initial pulse width by 3X ms, where X equals
the number of times steps 3 and 4 were repeated.
The above procedure completes writing one byte of
data If steps 2 to 4 have been repeated more than 25
times and the data has not programmed properly, the
pP077P220 is defective.
NEe
Table 12.
IIPD77220,77P220
Pin Functions for PROM
Program Mode
Normal M!S Mode
Function
ArrAs
Ao-As
Input address pins
(viewed from external
device) for programming!
reading PROM
(instruction ROM and
data ROM).
Ag
INT
A10
A10
A11
A11
A12
AX
A13
Ag
00- 07
00- 07
Input/output data pins for
PROM (instruction ROM
and data ROM).
CE
D2s!HWR
PROM program strobe
signal (active low)
OE
°24!HRO
PROM read strobe signal
(active low)
Vpp
Vpp
Power pin to read or
program PROM; apply
+ 12.5 V for programming
and +.5 V for reading.
Voo
Voo
Power pin; apply + 6 V for
programming and +5V
for reading.
GNO
GNO
Ground terminals
PROG
SIEN
Sets PROM program or
read mode; apply + 12.5 V
to set PROM program!
read mode.
Data Reading Procedure
This section describes the data reading procedure.
Figure 25 shows the on-chip PROM read timing. The
programming procedure is as follows:
(1) Enter the PROM read mode by applying + 12.5
±O.5 V to SIEN/PROG pin, + 5 V to the VDD pin, and
+ 5 V to the Vpp pin.
(2) Specify the desired ROM byte address from the
address input pins Ao - A13.
(3) Output data to the data bus (Do - D7) by clearing OE
and CE to O.
31
NEe
pPD77220, 77P220
PROM ELECTRICAL SPECIFICATIONS
This section lists the electrical specifications of the
pPD77P220 while in PROM program/read mode.
Data Program Timing Requirements
= 6 ±0.25 V; Vpp = 12.5 ±O.S V; VpROG =
TA = 25 ±5"C; VDD
12.0 ±0.5 V
Parameter
Symbol
Min
CE setup time for SIEN/PROG
tSRSCE
2
CE setup time for address
tSAC
2
Jis
CE setup time for data
tsDC
2
Jis
CE setup time for Vpp
tsvPC
2
Jis
CE setup time for VDD
tsVDC
2
Jis
OE setup time for data
tSDO
2
Jis
Address hold time
tHCA
2
Jis
Data hold time
tHCD
2
Jis
Initial program pulse width
!wCD
0.95
Overprogram pulse width
!wC1'
2.85
Typ
Max
Unit
Jis
1.0
1.05
ms
78.75
ms
·tWC1 = SntWCO assuming initial program pulse is applied n times.
Data Program Switching Characteristics
= 6 ±0.25 V; Vpp = 12.5 ±O.S V; VpROG =
TA = 25 ±5"C; VDD
Parameter
Symbol
Min
Typ
o
OE to output float time
OE to output delay
12.0 ±0.5 V
tDODW
Max
Unit
1S0
ns
250
ns
Data Program Read Timing Requirements
TA = 25 ±5"C; VDD = Vpp = 5 ±0.5 V; VpROG = 12.0 ±0.5 V
Parameter
Symbol
Min
CE setup time for SIEN/PROG
IsRSCE
2
Jis
OE setup time for SIEN/PROG
tSRSOE
2
Jis
Typ
Max
Unit
Data Read Switching Characteristics
= Vpp = 5 ±0.5 V; VPROG = 12.0 ±0.5 V
TA = 25 ±5"C; VDD
Parameter
Symbol
Max
Unit
Address to output delay
toAD
200
ns
CE to output delay
toCD
200
ns
OE to output delay
tDODR
100
ns
OE to high to output float
!fCD
o
65
ns
Address to output hold
If.tAD
o
32
Min
Typ
ns
NEe
pPD71220, 77P220
Figure 24. On-Chip PROM Program Timing
+12.0 V ±0.5 V
SIENIPROG
~
+5 V
+12.5 V ±0.3 V
VPP~
+5V
+6 V
Voo------lr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +5V
______________x=
>-< r~'---------><
(~
Ao-A13
00 - D-]
\
CE
....
/
\
OE
\
r"
83RD-B282B
Figure 25. On-Chip PROM Read Timing
+12.0 V ±0.5 V
SIENIPROG
~
+5V
VpP __________________________________________________________________________
+5V
Voo __________________________________________________________________________
+5V
Ao- A1 3 - - - (....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
x=
~-D-]--------------------------~(~________________________~)r------
\~------------~;-
\'----------'/
83RO-82838
33
pPD77220, 77P220
34
t-IEC
fttlEC
NEC Electronics Inc.
pPD77230A,77P230
32-Bit Floating-Point
Digital Signal Processor
Description
o Eight-level stack accessible to internal bus
The IlPD77230A Digital Signal Processor (DSP) is the
high-end member of a new third-generation family of
32-bit DSPs. This CMOS chip implements 32-bit full
floating-point arithmetic, and is intended for digital
signal processing and other applications requiring
high speed and high precision.
o Two interrupts: maskable and nonmaskable (NMI)
The IlPD77230A has on-chip instruction and data ROM.
These ROM areas can be mask ROM (pPD77230AR) or
EPROM (pPD77P230R). The mask ROM is also available
as a standard part with a standard, general-purpose
DSP library (PPD77230AR-003).
o Serial I/O (4 MHz)
o Master/slave mode operation
o Three-stage instruction pipeline
o Single +5-volt power supply
o Approximately 1.2 watts
Ordering Information
Part Number
ROM
Package Type
I'PD77230AR
Mask ROM
68-pin ceramic PGA
All instructions execute in one instruction cycle. The
IlPD77230A executes a 32-bit by 32-bit floating-point
multiply with 55-bit product, sum of products, data
move, and multiple data pointer manipulations-all in
one 150-ns instruction cycle.
I'PD77230AR-003
Mask ROM
(Standard library)
I'PD77P230R
EPROM
Note: Unless contextually excluded, references in this
data sheet to j1PD77230 mean j1PD77230A and
j1PD77P230.
o General-purpose digital filtering (FIR, IIR, FFT)
Features
o Fast instruction cycle: 150 ns using 13.3-MHz clock
o All instructions execute in one cycle
o 32- x 32-bit floating-point arithmetic
o Large on-chip memory (32-bit words)
-1 K data RAM (two 512-word blocks)
- 1K data coefficient ROM
- 2K instruction ROM
o 8K- x 32-bit external memory; 4K may be
instruction memory
o 1.5-llm CMOS technology
o 32-bit internal bus
o 55-bit ALU bus
o Dedicated internal buses for RAM, multiplier, and
ALU
Applications
o High-speed data modems
o Adaptive equalization (CCITT)
o Echo cancelling
o High-speed controls
o Image processing
o Graphic transformations
o Instrumentation electronics
o Numerical processing
o Speech processing
o Sonar/radar signal processing
o Waveform generation
Floating-Point Performance Benchmarks
Second-order digital filter (biquad)
0.91's
32-tap finite impulse response filter
5.251'5
Fast Fourier transform (F F1)
o Eight accumulators/working registers (55 bits)
32-point complex (radix 2)
o 47-bit bidirectional barrel shifter
512-point complex FFT
o Two independent data RAM pointers
o Modulo 2n incrementing for circular RAM buffers
1024-point complex FFT
11.78 ms
4096-point complex FFT
69.51 m5
o Base and index addressing of internal RAM
o Data ROM capable of 2n incrementing
o Loop counter for repetitive processing
50256·1
Square root
0.15 ms
4.7 ms
6.01's
IDe
~EC
pPD77230A,77P230
Pin Configuration
Pin Identification (cont)
68-Pin Ceramic PGA
L K J
H G FED C B A
00000000011
0@0000000@010
010
A8
0 11
A9
012
A10
0 15
81
As
Ao
L5
SI
MIS
L6
SIEN
RESET
E10
~1
1/0 13
L7
E11
022
1/014
L6
RO
0
007
F1
INT
L9
CLKOUT
F2
NMI
L10
X1
o
0
o
o
o
0
005
0
004
0
0
0
3
o
@
@
0
2
Master
08
E1
E2
008
A7
A7
SO
009
No.
A6
Master
L4
0
A2
A5
No.
110 12
0
006
BollomVlew
0
0
0
0
0
0
0
•
·Slave
·Slave
..
If not specified, slave-mode pins are the same In master·mode.
Pin Function Summary
Pin Identification
A4
·Slave
Ow
o
o
49-001663A
Ag
Master
011
o
OOOOOOOOO()1
A3
No.
No.
Master
·Slave
F10
0 23
1/°15
Symbol
1/0
Ao· A11
0
Ax
0
Highest bit of memory address
CLKOUT
0
Internal system clook
CS
Funct.ion
Address bus to external memory
Chip seleot
00- 0 7
1/0'
Oata bus for aocess to external memory in
slave mode.
0 0 - 031
1/0'
Oata bus for access to external memory (data
or instruction) in master mode.
F11
NC (No connection)
AlO
G1
07
AX
G2
06
1/°0
Gl0
024
HRO
GNO
Ground (Conneot ground to all GNO pins.)
1/°2
G11
025
HWR
HRO
Host CPU read
1/°3
H1
05
HWR
1/°4
H2
04
1/0 0- 1/°15
I/O]
H10
026
CS
INT
Maskable interrupt
H11
0 27
RQM
NMI
Nonmaskable interrupt
Host CPU write
1/0·
Port to host CPU data bus
82
A5
J1
03
MIS
Operation mode select
83
As
J2
O2
PO, P1
General-purpose input port
84
GNO
J10
0 28
PO
P2, P3
0
General-purpose output port
85
A11
J11
029
P1
RO
0
Controls data read from external memory
86
Voo
K1
01
RESET
87
Og
K2
SORQ
RQM
88
GNO
K3
SICK
SI
89
0 13
1/05
K4
Voo
SICK
810
0 14
1/0 6
K5
SOEN
SIEN
811
016
1/0 8
K6
GNO
SO
O·
Serial output data
C1
A4
K7
WR
SOCK
I/O
Clock for serial output data
C2
A3
K8
Voo
SOEN
C10
017
1/°9
K9
X2
SORQ
C11
018
1/0 10
K10
030
P2
Voo
01
A2
K11
031
P3
WR
02
A1
010
°19
2
1/0 1
1/0 11
System reset
0
Oata readlwrite request
Serial input data
I/O
Clock for serial input data
Serial input data enable
Serial output data enable
0
Serial output request
0
Controls data write to external memory
+5-volt power (Connect +5 Vto all VOD pins.)
L2
00
X1, X2
L3
SOCK
• These pins have a high-impedance inactive state.
External clock (X1) or crystal (X1, X2)
NEe
PIN FUNCTIONS
Paragraphs below supplement the brief descriptions in
the preceding table. Pin symbols are in alphabetical
order within several master and slave mode categories.
pPD77230A,77P230
in the serial output register, this signal becomes 1. It
will become 0 after data has been output.
X1, X2 (External Clock). Connection to external oscillator crystal (X1, X2) or external clock (X1).
Master and Slave Modes
Master Mode, External Memory Interface
CLKOUT (System Clock). Outputs internal system
clock. Output signal frequency is half the oscillation
frequency of crystal connected across X1 and X2 pins.
Ao - A11 (Address Bus). Address bus for access to
external memory. When accessing external instruction
memory, the lower 12 bits of the program counter are
output to these pins. When accessing external data
memory, the lower 12 bits of the external address
register are output to these pins.
INT (Maskable Interrupt). Inputs maskable interrupt
signal, which is active-low and must be at least three
system clock pulses wide. Interrupt signal is detected
at falling edge. Interrupt address is 100H.
MIS (Mode Select). Selects operation mode. Operation mode must not be switched during operation,
however. Master = 0; slave = 1.
NMI (Nonmaskable Interrupt). Inputs nonmaskable
interrupt signal, which is active-low and must be at
least three system clock pulses wide. Interrupt signal is
detected at falling edge. Interrupt address is 10H.
RESET (System Reset). Inputs internal system reset
signal, which is active-low and must be at least three
system clock pulses wide.
SI (Serial Input Data). Inputs serial data synchronized
with falling edge of SICK.
Ax (Highest Address Bit). Outputs the highest bit of
the memory address. When accessing external i nstruction memory, the highest bit of the program counter
(PC 1;z) is output to this pin. When accessing external
data memory, the highest bit of the external address
register is output to this pin. High-speed memory area
= 0; low-speed memory area = 1.
Do - 031 (Data Bus). These pins form a 32-bit, threestate data bus for external memory (data or instruction).
RD (Data Read). Controls data read from external
memory. This signal becomes 0 after the output address is valid, and data is input at the rising edge to the
data port formed by pins Do to 031.
SICK (Serial Input Clock). Inputs or outputs clock for
serial input data. Serial data is internally latched at the
falling edge of the clock that is input to or output from
this pin. Whether the clock is to be input from an
external source or the internal clock is to be output is
determined by the status register setting.
WR (Data Write). Controls data write to external memory. This signal becomes 0 after the output address is
valid and data is output to the data port formed by pins
Do to 0 31 ,
SIEN (Serial Input Enable). Enables SI pin to input
serial data. This pin is active-low.
Ao - A11 (Address Bus). Address bus for accessing
external memory. When accessing external data memory, the lower 12 bits of the external address register
are output to these pins.
SO (Serial Output Data). Outputs serial data synchronized with rising edge of SOCK pin. When inactive, this
pin becomes high impedance.
SOCK (Serial Output Clock). Inputs or outputs clock
for serial output data. The serial output data is synchronized with the clock that is input to or output from
this pin. Whether the clock is to be input from an
external source or the internal clock is to be output is
determined by the status register setting.
SOEN (Serial Output Enable). Enables SO pin to
output serial data. This pin is active-low.
SORQ (Serial Output Request). Outputs serial output
request signal, which is active-high. When data is ready
Slave Mode, External Memory Interface
Ax (Highest Address Bit). When accessing external
data memory, the highest bit of the external address
register is output to this pin. High-speed memory area
= 0; low-speed memory area = 1.
Do - 0 7 (Data Bus). These pins form an 8-bit, threestate data bus for external data memory access. Data
may be transferred in one of four formats (1-, 2-, 3-, or
4-byte words), depending on the status register setting.
RD (Data Read). Controls data read from external
memory. This signal becomes 0 after the output addresS is valid, and data is input at the rising edge to the
data port formed by pins Do to 07.
3
NEe
pPD77230A,77P230
WR (Data Write). Controls data write to external memory. This signal becomes 0 after the output address is
valid, and data is output to the data port formed by pins
Do to D7.
Slave Mode, Host CPU Interface
CS (Chip Select). Active-low chip select input signal.
When this pin becomes 0, the host CPU may perform
read/write operations on the 16-bit port formed by pins
1/0. 0 to 1/015'
HRD (Host CPU Read). Active-low host read input
signal. In conjunction with CS, this signal allows the
host CPU to read data from the DRS register via the
16-bit port formed by pins 1/0.0 to 1/015.
HWR (Host CPU Write). Active-low host write input
signal. In conjunction with CS, this signal allows the
host CPU to write data into the DRS register via the
16-bit port formed by pins 1/0.0 to 1/0.15,
parallel with ALU operations and in parallel with data
transfer operations, which make use of the main bus.
There is a sub-bus connecting the ALU input to the
55-bit multiplier output and another sub-bus that can
route the working registers' contents back to the ALU
input.
Architecture
The pPD77230 has a Harvard architecture with separate memory areas for program storage and data
storage as well as separate multiple buses. A threestage instruction execution pipelining scheme performs instruction fetch and execution in parallel. All
instructions are executed in a single cycle, even if the
instruction is stored in the exernal instruction memory
expansion area
Instruction Memory
RQM (ReadIWrite Request). Requests host CPU to
read or write data via the host CPU data bus.
The pPD77230 has an internal instruction RCM that
holds 2K 32-bit instruction words. An additional 4Kword external memory expansion is also available. A
13-bit program counter (PC) contains the current instruction address; the most significant bit of the PC
determines whether on-Chip or external instructions
are to be fetched. An eight-level stack holds subroutine
and interrupt return addresses, and it is accessible
to/from the main internal bus.
Slave Mode, I/O Port
Data Memory
po, P1 (Input Port). These pins form a general-purpose
input port. Status of either of these pins may be tested
by a conditional branch instruction.
The data ROM area on the pPD77230 holds 1K 32-bit
words. The RCM pointer (RP) contains the current ROM
address, which can also be specified within an instruction field. The ROM pointer has auto-increment and
auto-decrement features and an add 2" to the RP
option.
1/0.0 • 1/0.15 (Data Port). These pins form an I/O port to
the host CPU bidirectional data bus. It is used for input
to or output from the DRS register under control of host
CPU signals CS, HWR, and HRD. Data transfer format
can be specified in the status register as either a 16-bit
or a 32-bit transfer.
P2, P3 (Output Port). These pins form a generalpurpose output port. Data output by these pins can be
set directly by an instruction and will be retained until
explicitly changed.
FUNCTIONAL DESCRIPTION
Figure 1 is the functional block diagram of the
pPD77230 in its master mode configuration. The main
internal bus (32 bits) ties together all the functional
blocks of the pPDm30, including the ALU area The
55-bit processing unit (PU) bus links the ALU input to
the 55-bit multiplier output register and the eight 55-bit
worki ng registers. Thus, the full 55 bits of precision can
be maintained during extensive calculations.
In addition to the main bus and the PU bus, there is a
sub-bus linking each of the two RAM areas to both the
ALU input and the multiplier input registers. This allows
simultaneous loading of the multiplier input registers in
4
There are two separate and independently addressable
data RAM areas, each 512 words by 32 bits. Each RAM
area can be addressed by a base register, an index
register, or the sum of the two. The base register and/or
the index register may be incremented, decremented,
or cleared. In addition, the base pointer can operate in
a modulo count mode, and the index register contents
may be replaced by the sum of the index and base
registers.
Data memory may be expanded by the addition of 8K
words of external memory. External data memory is
divided into a high-speed half, which is accessed in two
instruction cycles, and a low-speed half, which is accessed in four instruction cycles. Both high-speed and
low-speed memory accesses occur in parallel with
normal program execution.
NEe
Multiplier and ALU
The floating-point multiplier has two 32-bit input registers, called the K and L registers, which are accessible
both to and from the main bus. The multiplier produces
the 55-bit product of the K and L register contents
automatically in a single instruction cycle (there is no
multiply instruction). The 55-bit result is stored in the M
register in 8-bit exponent, 47-bit mantissa format. The
contents of the M register can be transferred to the
main bus (32 bits) or to the ALU via the processing unit
bus (55 bits). The multiplier con sists of a 24- by 24-bit
fixed-point multiplier and an exponent adder, so that it
can also be used for fixed-point multiplications.
The 55-bit floating-point ALU is capable of a full set of
arithmetic and logical operations (see Instruction Set
section). There is a 47-bit bidirectional barrel shifter,
which can perform general-purpose shifting in addition to the mantissa alignments required for floatingpoint arithmetic. A separate exponent ALU (EAU) determines shift values in floating-point work. The ALU
status is reflected in one of two identical processor
status words (PSW) that contain carry, zero, sign, and
overflow flags. The results of the ALU operation are
stored in one of eight 55-bit accumulators or "working
registers. "
There are two 55-bit input registers to the ALU called
the P register and the Q register. The Q register input is
selected from one of the eight working registers, while
the P register input is selected from among the 32-bit
main bus, data RAM 0, data RAM 1, and the 55-bit M
register.
A loop counter is included in the design of the
pPD77230. This loop counter is a 10-bit register, attached to the main bus, which can be decremented by
a control bit built into an ordinary ALU instruction.
When the loop counter is decremented to zero, the
instruction following the one that decremented it will
be skipped.
System Control
The master system clock may be provided to the
pPD77230 via either an external crystal or an already
available clock signal. The internal clock of the
pPD77230 contains two phases and is obtained by
dividing the master clock frequency by 2. If desired, the
serial input and output clocks can be derived from the
master clock by dividing it by 8.
pPD77230A,77P230
upon (or disregarded) at a later time. The status of the
interrupts and other aspects of the pPD77230 are determined by or reflected in the 20-bit status register.
Serial I/O
The serial input and output circuitry in the pPD77230 is
designed for easy interfacing to codecs and other
JlPD77230s. The input and output circuits are independently clocked by either an internal clock or an external
clock up to 4 MHz. The length of the serial input and
output data words can be independently programmed
to be 8, 16, 24, or 32 bits.
The parallel I/O capabilities in the pPD77230 can be
used for external instruction and data memory expansion and for interaction with a host processor. The
difference between master mode and slave mode operation must be defined to further discuss the nature
of the parallel interface in the pPD77230.
Master/Slave Modes
The master mode parallel interface is shown in figure 1.
In this mode, the pPDn230 is intended to act as a
standalone processor with the parallel interface allowing access to external memory, memory-mapped I/O
devices, and/or a system-level bus. Master mode operation allows for external instruction memory expansion and external data memory expansion. There is an
8K external memory space. The lower 4K can be shared
between instructions and data, while the upper 4K can
be used for data only.
The slave mode parallel interface is shown in figure 2. In
this mode, the pPDn230 is a "peripheral" to a host
processor. The full 8K external memory space is available for data memory expansion, but instruction memory expansion is not allowed in slave mode. The 8-bit
external data bus is used to assemble words in the
data register (DR), which can be 8, 113, 24, or 32 bits
wide. Communication with the host occurs across the
16-bit host data bus. Word lengths of 16 or 32 bits can
be transferred between the pPD77230 and the host.
Four pins can be used in slave mode as generalpurpose I/O ports: two input pins and two output pins.
Figure 3 shows the functional pin groups in master
mode and slave mode.
Both a maskable and nonmaskable interrupt are available in the pPD77230. The maskable interrupt can be
"memorized," so that if an interrupt occurs while it is in
the interrupt disabled condition, then it may be acted
5
ED'
I
•
NEe
pPD77230A,77P230
Figure t. Master Mode Block Diagram
FMPY
32 x 32 bits
__ 55blts
SICK
VDD--
Mis
I
GND
---J-
WR~
RD ~I"'>----~
~
X1 - - CLK
~ _ _ GEN
CLKOUT
~1
WRO
WR4
.2
SCK
WR1
WRS
Main Bus
WR2
WR6
WAS
WR7
83FM·8012B
6
NEe
pPD77230A,77P230
Figure 2. Slave Mode Block Diagram
1100- 11015 - - -
P3
P2
P1_
PO-
~D-r
MIS
L
GND--
7
WR~
RD~
6
5
4
3
STK
2
~
---=-__
Xl
CLKOUT
.1
CLK
.2
GEN
SCK
:ii:I.-j----J
:j !~
Main Bus
WRO
WR4
WR1
WR5
WR2
WR6
WR3
WR7
83FM-8015B
7
NEe
pPD77230A,77P230
INSTRUCTION SET
Figure 3. Functional Pin Groups
A.
All pP077230 instructions consist of a single 32-bit
word. Figure 4 shows the bit format for the three basic
types of instructions.
Master Mode
Clock {
}
Seriallnpul
OP Type Instruction
}--
Reset and {
Interrupt
This is an ALU operation instruction where 26 different
operations may be specified in the upper five bits
(figure 4). Pointer modifications may be specified in the
CNT field. Transfers may also be specified within an
OP instruction by use of the SRC and OSTfields. When
all fields are specified in an OP instruction, several
different tasks are performed at once. The high five bits
make up the OP field, summarized in table 1.
1
Exlernal Memory
Interface
B.
Clock {
Table 2 summarizes the effect on bits in the PSW
resulting from ALU operations.
Slave Mode
}
Control Field (CNT)
Serial Inpul
This 12-bit field contains specifications for control
modes and pointer modifications. Figure 5 summarizes
the bit field format, table 3 summarizes the function of
C NT field groups, and table 4 summarizes the function
of each mnemonic within the 23 groups. Table 5 shows
the possible combinations of control field instructions
according to the 15 lines in the table on figure 5; for
Etxample, case 1 includes the MO, M1, OPO, and OP1
instructions.
Reseland {
Interrupt
Ho,lCPU
Inlertace
Jl
1
Exlemal Memory
Interface
General-PurpOIe {
1/0 Porta
83-0D3771B
Figure 4. Instruction Type Formats
A.
OP l)'pe Instruction
27 26
31
DP [5]
5 4
SRC[5]
CNTI12]
B.
Branch l)'pe Instruction
10 9
15 14
NA113]
C[5]
c.
r
8
29 28
1
OST [5]
5 4
SRC IS]
OSTI5]
Load l)'pe Instruction
1M 124]
OST [5]
83-0037728
NEe
~PD77230A,77P230
Table 1. OP Field Specifications
Mnemonic
OP Field (31.27)
NOP
INC
DEC
ABS
NOT
Table 2. Effects of ALU Operations on PSW Rags
(cont)
Operation
Contents of PSW
No operation
00000
Increment
00001
Decrement
00010
Absolute value
00011
Not-one's complement
00100
NEG
00101
Negate-two's complement
SHLC
00110
Shift left with carry
SHRC
00111
Shift right with carry
ROL
01000
Rotate left
ROR
01010
Shift left multiple
01011
Shift right multiple
CLR
Shift right arithmetic multiple
Clear
01101
01110
Normalize
CVT
01111
Convert floating point format
ADD
10000
Fixed-point add
Fixed-point subtract
10001
0
SHRAM
0
$
$
0
ADDC
10010
Fixed-point add with carry
SUBC
10011
Fixed-point subtract with borrow
CMP
10100
Compare (floating-point)
AND
10101
Logical AND
OR
10110
Logical OR
10111
Logical exclusive OR
ADDF
11000
Floating-point add
SUBF
11001
Floating-point subtract
NORM (NORM.)
$
0
(ROUNDING)
$
$
$
$
$
0
$
$
$
0
$
$
$
0
$
$
0
ADD
$
$
$
$
X
$
SUB
$
$
$
$
ADDC
$
$
$
$
SUBC
$
$
$
$
$
$
$
$
AND
0
$
$
0
OR
0
$
$
0
XOR
0
$
$
0
$
ADDF
$
$
$
$
$
SUBF
$
$
$
$
$
Figure 5. Control Field Bit Format
D~2r
>
IT,J 0
CNT(12]
"
/./
/./
NOP
*
Z
S
OVFM
"
././
v/
*
INC
$
$
$
$
0
0
Ml
DPO
DEC
$
$
$
$
0
1
0
0
EA
DPO
ABS
$
$
0
$+
0
1
0
1
AP
MO
DPO
0
1
1
0
AP
Ml
DPl
AP
MO
NEG
SHLC
SHRC
*
*
26
" ,
./
*
NOT
•
$ Flag will be affected by result of operation.
o Flag will be reset to O.
Contents of PSW
C
0
0
Table 2. Effects of ALU Operations on PSW Rags
OVFE
0
$
0
1 Flag will be reset to 1.
* Previous condition of flag will be preserved.
+ ~ original mantissa was BO---OH, OVFM = 1 after operation.
XOR
ALU Operation
0
CLR
CMP
NORM
SUB
OVFM
$
(FIX M.A.)
SHRM
01100
S
$
CVT
SHLM
SHRAM
Z
0
OVFE
(FLT-FIX)
Rotate right
01001
C
SHRM
ALU Operation
25
23
2'
22
MO
21
I
20
0
$
$
0
0
1
1
1
$
$
$
$+
1
0
0
0
0
BASO
1
0
0
0
1
APC
19
I
18
17
I
L
I
1&
"15
DPl
DPl
Ml
FC
FC
L
BASl
FC
FC
I
L
FC
BM
L
FC
I
L
FC
$
$
$
0
1
0
0
1
0
P31p2
$
$
$
0
1
0
0
1
1
AW
1
0
1
0
0
WT
I
L
FC
1
0
1
0
1
NF
WI
L
FC
FIS
FD
L
ROL
0
ROR
0
SHLM
0
1 EM
I
$
0
*
$
0
1
0
1
1
0
$
$
0
1
0
1
1
1
1
1
0
APS
1
1
1
NAL
SHY
83-003773A
9
NEe
pPD77230A,77P230
* Effective starting with current instruction.
Table 3. Control Field Function Summary
Field
Interrupt
EM, BM Enable and disable maskable
interrupt, and control interrupt
memorization.
Operation
FIS
PSW control (select and clear)
EM, BM Field (19017)
FC
Select other PSW
EM
BM
RP
Controls ROM pointer
operation
No operation
(NOP)
(NOP)
000
Clear booking flag
(NOP)
CLRBM
001
Specifies n value for special
manipulation of ROM pointer
Set booki ng 1lag
(NOP)
SETBM
a 10
Interrupt disabled
DI
(NOP)
all
PSW
Data ROM
poiner
RPC
Data RAMO
and RAMl
pointers
Interrupt enabled
EI
(NOP)
100
Interrupt enabled and
clear booking flag
EI
CLRM
101
Ml
Specifies RAMl addressing
mode
Interrupt enabled and set
booking flag
EI
SETBM
110
DPO
Controls modification of base
pointer a and index register a
DPl
Controls modification 01 base
pointer 1 and index register 1
BASEO
Specifies counter length of
modulo count operation of base
pointer a
111
Use prohibited
* Default:
interrupt disabled and clear booking flag.
• Writing (NOP) is not necessary, just useful for remembering the
available combinations and their effects.
RS Field (21-19)
Flag Initialize and select
Specifies counter length of
modulo count operation of base
pointer 1
(NOP)
000
Specify PSW a for
operation (default)
SPCPSWO
001
FD
Controls conversion mode for
floating point CVT.
Specify PSW 1 for
operation
SPCPSWl
010
WI
Controls transfer format when
working register is specified in
DSTfield.
Clear PSW a
CLRPSWO
100
Clear PSW 1
CLRPSWI
101
CLRPSW
110
(NOP)
a
Controls transfer format when
working register is specified in
SRCfield.
No operation
-+
Controls amount of shift for 47·
bit mantissa
RW
Specifies read/Wrlte operation
for external memory.
EA
Increments or decrements
external address register
Controls state of P2 pin
P3
Controls state of P3 pin
Loop
counter
L
Decrements loop counter
Jump
NAL
Specifies unconditional local
jump address
Clear PSW a and PSW 1
FC Bit (15)
Flag change operation
Specifies normalization,
normalization with rounding,
floating·point to fixed·point
conversion, or digit alignment.
P2
10
Maskable interrupt
Code
Specifies RAMO addressing
mode
Shift
SHV
specification
Generalpurpose
output port
*
Mnemonic
MO
Normalization NF
specification
access
Table 4. Control Field Mnemonic Summary
Specifies 9 lower bits of data
ROM address
WT
Data
memory
Effective
RPS
BASEl
Data format
conversion
Function
-+ Effective starting with next instruction.
Group
No operation
Exchange PSW for
operation
•
*
XCHPSW
RP Field (22, 21)
ROM pointer modification
No operation
(NOP)
00
Increment ROM pointer
INCRP
01
Decrement ROM pointer
DECRP
10
Increment specified
bit of ROM pointer (that
is, add 2N)
INCBRP
11
BITRP imm
(imm)B
RPC Field (21·18)
Speoify N for adding 2N to
ROM pointer *imm (= n) is
a through 9
~EC
~PD77230A,77P230
Table 4. Control Field Mnemonic Summary
(cont)
Operation
Operation
Mnemonic
Code
SPCRA imm
(imm)B
RPS Field (23-15)
Specify immediate ROM
address *0 " imm " 511
Mnemonic
MCNBPO imm
Specify modulo count
number (2N) for
incrementing base pointer 0
*imm (=n) is 1 through 7; 0 specifies ordinary count
MO Field
BASE1 Field (18-16)
Specify RAM pointer
MCNBPl imm
(NON)
00
Specify modulo count
number (2N) for
incrementing base pointer 1
Base pointer 0
SPCBPO
01
*imm (=n) is 1 through 7; 0 specifies ordinary count
Index register 0
SPCIXO
10
Base pointer 0 + index
register 0 (default)
SPCBIO
11
No change in specification
M1 Field
Specify RAM pointer
No change in specification
FO Field
No change of specification
(NON)
00
Conversion of ASP format
to IEEE format (default)
SPIE
01
IESP
10
(NON)
00
SPCBPl
01
Conversion of IEEE
format to ASP format
Index register 1
SPCIXl
10
Use p roh i bi ted
Base pointer 1 + index
register 1 (default)
SPCBll
11
WI Field (18, 17)
(NON)
00
Transfer low 24 bits of
mantissa to high 24 bits
BWRL24
01
BWRORD
10
No change of specification
Pointer modification operation
Decrement base pointer 0
-
11
Specification of transfer format when data is moved from IB to WR
OPO Field
Increment base pointer 0
(imm)B
Data conversion format specification
Base pOinter 1
No operation
Code
(imm) B
(NaP)
000
INCBPO
001
Ordinary transfer (default)
010
Use prohibited
DECBPO
11
CLRBPO
011
WT Field (21-19)
Store base + index to
index register 0
STIXO
100
Specification of transfer format when data is moved from WR to IB
Increment index register 0
INCIXO
101
Decrement index register
0
DECIXO
110
Clear index register 0
CLRIXO
111
Clear base pointer 0
OP1 Field
Pointer modification operation
(NaP)
000
Increment base pointer 1
INCBPl
001
Decrement base pointer 1
DECBPl
010
Clear base pointer 1
CLRBPl
011
Store base + index to
index register 1
STIXl
100
No operation
No change of specification
(NON)
000
Ordinary transfer (default)
WRBORD
001
Low 24 bits of mantissa to
high 24
WRBL24
010
Low 23 bits (bit 23 = 0) to
high 24
WRBL23
011
Exponent part to mantissa
low 8 bits
WRBEL8
100
Mantissa low 8 bits to
exponent part
WRBL8E
101
Exchange high 8 bits of
mantissa with low 8 bits
of mantissa
WRBXCH
110
Bit reverse entire mantissa
WRBBRV
111
Increment index register 1
INCIXl
101
NF Field (21-19)
Decrement index register
1
DECIXl
110
Normalization format specification
Clear index register 1
CLRIXl
111
BASEO Field (21-19)
No change of specification
Truncating normalization
(default)
(NON)
000
TRNORM
010
11
ttlEC
pPD77230A,77P230
Table 4. Control Field Mnemonic Summary
~onQ
.
Operation
Operation
Mnemonic
Code
Rounding normalization
RDNORM
100
Convert floating-point to
fixed-point
FLTFIX
110
Fixed-point multiple
alignment (multiple value
is in SVR)
FIXMA
Code
DECAR
10
Use prohibited
11
P2 Bit (20)
111
SHV Field (21.15)
Set shift value to SVR
P2 pin control (slave mode only)
Clear output port pin 2
CLRP2
Set output port pin 2
SETP2
o
P3 Bit (21)
imm bits left shift
(default)
SETSVL imm
o (imm)B
imm bits right shift
SETSVR imm
1 (imm)B
·0 s imm s 46
P3 pin control (slave mode only)
Clear output port pin 3
CLRP3
Set output port pin 3
SETP3
o
L Bit (16)
RW Field (21, 20)
Loop counter operation
Operation for external data memory
No operation
(NOP)
00
Read
RD
01
Write
WR
10
Use prohibited
No operation
(NOP)
Decrement loop counter
DECLC
Local branch; jump to imm
address in local block
·s imm s 511
11
EA Field (22, 21)
No operation
(NOP)
00
Increment external
address register
INCAR
01
Table 5. Control Field Instruction Combinations
Case 1
SPCBPO
SPCIXO
SPCBIO
SPCBP1
SPClXl
SPCBll
INCBPO
DECBPO
CLRBPO
STIXO
INCIXO
DECIXO
CLRIXO
Case 2
INCAR
DECAR
INCBPO
DECBPO
CLRBPO
STIXO
INCIXO
DECIXO
CLRIXO
INCBP1
DECBPl
CLRBPl
STlXl
INCIXl
DEClXl
CLRIX1
Case 3
INCRP
DECRP
INCBRP
SPC.BPO
SPCIXO
SPCBIO
INCBPO
DECBPO
CLRBPO
STIXO
INCIXO
DECIXO
CLRIXO
o
NAL Bit (23-15)
Operation for external address register
12
Mnemonic
Decrement external
address register
INCBP1
DECBP1
CLRBP1
STIX1
INCIX1
DECIX1
CLRIX1
XCHPSW
JBLKimm
(imm)B
NEe
pPD77230A,77P230
Table 5. Control Field Instruction Combinations (cont)
Case 4
INCRP
DECRP
INCBRP
SPCBP1
SPCIX1
SPCBI1
INCBP1
DECBP1
CLRBP1
STIX1
INCIX1
DECIX1
CLRIX1
XCHPSW
Case 5
INCRP
DECRP
INCBRP
SPCBPO
SPCIXO
SPCBIO
SPCBP1
SPCIX1
SPCBI1
DECLC
XCHPSW
CLRBM
SETBM
DECLC
Case 6
MCNBPO imm
MCNBP1 imm
XCHPSW
Case 7
BITRP imm
DECLC
XCHPSW
Case 8
CLRP2
SETP2
CLRP3
SETP3
EI
DI
Case 9
RD
SR
DECLC
XC HPSW
Case 10
WRBORD
WRBL24
WRBL23
WRBEL8
WRBL8E
WRBXCH
WRBBRV
DECLC
XCHPSW
Case 11
TRNORM
RDNORM
FLTFIX
FIXMA
BWRL24
BWRORD
DECLC
Case 12
SPCPSWO
SPCPSW1
CLRPSWO
CLRPSW1
CLRPSW
SPIE
IESP
DECLC
Case 13
SETSVL imm
SETSVR imm
Case 14
SPCRA imm
Case 15
JBLK imm
XCHPSW
B:
I
XCHPSW
P Field
Table 6. P Field Specifications
The two-bit P field specifies the source of input to the P
register, which is used as an input to the ALU for
operations requiring two operands. See table 6.
Mnemonic
P Field (14, 13)
Input of P Register
o0
o1
Internal bus
M
RAMO
1 0
RAM block 0
RAM1
11
RAM block 1
IB
Multiplier output register
13
NEe
pPD77230A,77P230
Q Field
Table B. SRC Field Specifications
The three-bit Q field specifies the source of input to the
Q register, which is the other of two ALU input registers.
See table 7.
Mr.emonic
Table 7_ Q Field Specifications
Mnemonic
Q Field (12-10)
Regis1er
WRO
000
Working register 0
WRl
001
Working register 1
WR2
010
Working register 2
WR3
011
Working register 3
WR4
100
Working register 4
WR5
101
Working register 5
WR6
110
Working register 6
WR7
111
Working register 7
Source Field
Table 8 lists 32 source registers that may be specified
in the source field.
Destination Field
Table 9 lists 32 destinations that may be specified in
the DST field. Note that the LKRO and KLR1 specifications will simultaneously load both the K and L registers as destinations.
Branch Instruction
The branch instruction type is used for a jump, conditional jump, call, or return. The format of the branch
instruction is shown in figure 4. The destination address of the branch is contained in the 13-bit NA field.
Note that the most significant bit of the NA field is used
to determine whether the destination address is in
internal or external instruction memory. The five-bit C
field summarized in table 10 determines the nature of
the branch.
Note also that an SRC and DST may be included as
part of the branch instruction. This data transfer will
take place regardless of any condition upon which a
jump may be dependent.
LDI Instuction
Figure 4 shows the format of the LDI instruction type.
The 24-bit 1M (immediate) field contains the data that
will be loaded into the register specified by the DST
field. It is also possible to load a 32-bit floating-point
number using this instruction in conjunction with the
TRE destination field specification.
14
SRC Field (9-5)
Selected Source Register
NON
00000
No source selected
RP
00001
ROM pointer
PSWO
00010
Program status word 0
PSWI
00011
Program status word 1
SVR'
00100
SVR (shift value register)
SR
00101
Status register
Le
00110
Loop counter
STK
00111
Top of stack
M
01000
M register (multiplier output)
ML
01001
Low 24 bits of M register
ROM
01010
Data ROM output
TR
01011
Temporary register
AR
01100
External address register
Sl
01101
Serial input register
DR
01110
Data register
DRS
01111
Data register for slave
WRO
10000
Working register 0
WRl
10001
Working register 1
WR2
10010
Working register 2
WR3
10011
Working register 3
WR4
10100
Working register 4
WR5
10101
Working register 5
WR6
10110
Working register 6
WR7
10111
Working register 7
RAMO
11000
RAM block 0
RAMl
11001
RAM block 1
BPO
11010
Base pointer 0
BPl
11011
Base pointer 1
IXO
11100
Index register 0
IXl
11101
Index register 1
K
11110
K register
L
11111
L register
NEe
pPD77230A,77P230
Table 9. OST Field Specifications
Table 10. Branch Condition Summary (C Field)
Mnemonic
Selected Destination Register
Mnemonic
DST Field (4·0)
C Field (14·10)
Jump with Condition
NON
00000
No destination selected
JMP
00000
Jump unconditionally
RP
00001
ROM pointer
CALL
00001
Subroutine call
PSWO
00010
Program status word 0
RET
00010
Return from interrupt or subroutine
PSWl
00011
Program status word 1
JNZRP
00011
Jump if ROM pointer not zero
SVR
00100
SVR (shift value register)
JZO
00100
Jump if zero flag 0 is set
SR
00101
Status register
JNZO
00101
Jump if zero flag 0 is reset
LC
00110
Loop counter
JZl
00110
Jump if zero flag 1 is set
STK
00111
Top
JNZl
00111
Jump if zero flag 1 is reset
LKRO
01000
L register (RAM 0 to K register)
JCO
01000
Jump if carry flag 0 is set
KLRl
01001
K register (RAM 1 to L register)
JNCO
01001
Jump if carry flag 0 is reset
TRE
01010
Exponent part of temporary register
JCl
01010
Jump if carry flag 1 is set
TR
01011
Temporary register
JNCl
01011
Jump if carry flag 1 is reset
AR
01100
External address register
JSO
01100
Jump if sign flag 0 is set
SO
01101
Serial output register
JNSO
01101
Jump if sign flag 0 is reset
0\ •• ack
III
DR
01110
Data register
JSl
01110
Jump if sign flag 1 is set
DRS
01111
Data register for slave
JNSl
01111
Jump if sign flag 1 is reset
WRO
10000
Working register 0
JVO
10000
Jump if overflow flag 0 is set
WRl
10001
Working register 1
JNVO
10001
Jump if overflow flag 0 is reset
WR2
10010
Working register 2
JVl
10010
·Jump if overflow flag 1 is set
WR3
10011
Working register 3
JNVl
10011
Jump if overflow flag 1 is reset
WR4
10100
Working register 4
JEVO
10100
WAS
10101
Working register 5
Jump if exponent overflow
flag 0 is set
WR6
10110
Working register 6
JEVl
10101
Jump if exponent overflow
flag 1 is set
WPIl
10111
Working register 7
JNFSI
10110
Jump if SI register is not full
RAMO
11000
RAM block 0
JNESO
10111
Jump if SO register is not empty
RAMl
11001
RAM block 1
JIPO
11000
Jump if input port 0 is on
BPO
11010
Base pointer 0
JIPl
11001
Jump if input port 1 is on
BPl
11011
Base pointer 1
JNZIXO
11010
Jump if index register 0 nonzero
IXO
11100
Index register 0
JNZIXl
11011
Jump if index register 1 nonzero
IXl
11101
Index register 1
JNZBPO
11100
Jump if base pointer 0 nonzero
K
11110
K register
JNZBPl
11101
Jump if base pointer 1 nonzero
L
11111
L register
JRDY
11110
Jump if ready is on
JROM
11111
Jump if request for master is on
15
NEe
pPD77230A,77P230
SYSTEM CONFIGURATIONS
The pPD77230 may be configured in a variety of ways,
from simple to complex systems. Figure 6 is the simplest example showing the pPD77230 as a standalone
processor performing a. preset filtering function. The
only other devices needed are A/D and 0/A converters
which can be a single-chip cOmbo device as shown i~
the figure plus necessary clock and timing circuitry.
Figure 7 shows the same standalone operation with
external memory and memory-mapped I/O to implement various control functions along with processing
the signal itself.
Figure 8 shows a pPD77230 in a slave mode as a
peripheral to a host processor. Note that in slave mode
the pPD77230 can still be the "master" of its local bU~
with the four general-purpose I/O pins available for use.
Figure 9 shows how to cascade multiple pPD77230S to
increase system throughput. The cascading is done by
using only the serial ports so that the pPD77230s
themselves can be in any mode of operation desired.
For example, they may all be in master mode, they may
all be slaves to the same host processor, they may all
be slaves to different hos"ts, or one may be the master
with the others as slaves to it.
Figure 8. Slave pPD77230 as Peripheral to
Host Processor
Figure 6. Standa/one pPD77230 With Codec
Clock
and
Timing
Control
Analog
1-----
Input
Analog Output
83-003774A
High
~~:
Figure 7. Standalone pPD77230 With Codec,
External Memor~ and I/O
Local
Address Bus [13]
Speed
Local
Data
Clock
Memory
and
Timing
Control
Analog Input
81
80
Clock
and
Timing
Control
Analog
Input
1 - - - Analog Output
83-OO3775A
16
NEe
~PD77230A,77P230
Figure 9. pPD77230S Cascaded Through Seriall!O
Ports
SI
S'i"EN
pPD77230
so
AID
Converter
or
Codec
Codec
Converter
Analog In
Analog Out
or
DIA
83·003777A
Figure 10. Large System With Many Options
Address
Con~~BusLr-----------.-------------.~r-------------~-----------r------~
Data Bus '-:-__--.-________,.-__.--______-:-__,.-__. - - , -______-,-__-,-______-:-__- .__...1
Analog
AID
Analog
In
Converler
Out
Loesl
Memory
Local
Memory
83·0037788
Figure 10 shows an arbitrarily large system with cascading master mode and slave mode pPD77230s. In
this example, the master pPD77230 might do little
actual Signal processing. Instead, it wi" be an overall
system controller gathering information from inputs in
the I/O block, from the slave pPD77230 I/O ports, and
from its own processing of the signal. It will then control
the other pPD77230s and the system outputs of the I/O
block.
17
fttIEC
pPD77230A,77P230
DC Characteristics,
SUPPORT TOOLS
The pPD77230 has a wide variety of development and
software support tools. Both absolute and relocatable
assemblers, with powerful pre-assembler options, are
available. In addition, a software simulator and incircuit emulator will aid the designer in performance
evaluation and hardware integration. The software
tools options are as follows:
• Assembler: MS-DOS®, CP/M®-86, VAX®NMS®, VAX/
UNIX®
• Simulator: VAXNMS, VAX/UNIX
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
TA = 25'C
-0.5 to + 6.5 V
Supply voltage, Von
Voltage on any input pin, VI
-0.5 to Voo + 0.5 V
Voltage on any output pin, Vo
-0.5 to Voo + 0.5 V
Storage temperature, TSTG
-65 to +150'
TA = -10 to + 70'C; Voo = 5 V ±5%
Parameter
Symbol Min Typ Max Unit Conditions
Low-level output VOL
voltage
High-level output VOH
voltage
0.45
0.7
VOO
V
'IOL = 2.0 mA
V
IOH = -400J.lA
Low-level input
current
IlL
-400
J.lA
VIN = OV;
RESET, SICK,
SOCK
High-level input
current
IIH
400
J.lA
VIN = Voo;
MIS
Low-level input
leak current
ILiL
-10
J.lA
VIN = OV,
except RESET,
SICK, SOCK
High-level input
leak current
ILiH
10
J.lA
VIN = Voo,
except MIS
Low-level output
leak current
ILOL
-10
J.lA
VOUT=OV
High-level output ILOH
leak current
10
J.lA
VOUT = Voo
400
J.lA
External clock
input
300
mA fcYX =13.3333
MHz
X1 input current
IIXI
Supply current
100
Note: Voltages are with respect to ground.
200
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VOO
4.75
5.0
5.25
V
Low-level input
voltage
VIL
-0.3
0.8
V
High-level input
voltage
VIH
2.2
Voo +0.3
V
Low-level X1 input
voltage
VI LX
-0.3
0.5
V
High-level X1 input
voltage
VIHX
3.9
VOO +0.3
V
Operating free-air
temperature
ToPT
-10
70
'C
25
Capacitance
Parameter
Symbol
Input
capacitance
CIN
COUT
Min
Typ
Symbol Min
Typ
Max
Unit Conditions
Input clock
frequency
13.3333 13.513 MHz
fcYX
C1, C2
capacitance
15
pF
External Clock
X1 cycle time
tcyx
74
X1 high pulse
width
txxH
27
75
1000
ns
ns
X1 low pulse
width
txxL
27
ns
Max
Unit
Conditions
X1 rise time
txR
10
ns
10
pF
fC = 1 MHz
X1 fall time
txF
10
ns
SICK, SOCK
cycle time
tCYS
242
SICK, SOCK
high pulse
width
tSSH
101
ns
SICK, SOCK
tssL
low pulse width
101
ns
20
pF
MS-DOS is a registered trademark of Microsoft Corporation.
CPIM is a registered trademark of Digital Research, Incorporated.
VPIX. and VMS are registered trademarks of Digital Equipment Corporation.
UNIX is a registered trademark of UNIX System Laboratories, Incorporated.
18
Parameter
Internal Clock
TA = 25'C; voo = ov
Output
capacitance
Clock Timing
TA = -10 to + 70'C; Voo = 5 V ±5%; CL = 100 pF
SICK, SOCK
rise time
'tsR
244
ns
20
ns
Measured at
1.0Vand
3.0V
f'tIEC
pPD77230A,77P230
Clock Timing (cont)
Parameter
External Memory Access Timing
Symbol Min
SICK, SOCK
fall time
Typ
Max
20
tSF
Unit Conditions
ns
Switching
toxc
X1 t-+
CLKOUT hold
time
tHXC
SCK cycle time
tCYS
8tCYX
ns
SCK high pulse
width
tSSH
4tcyx
-65
ns
4tCYK
-65
ns
50
0
tSSL
ns
ns
SCK rise time
tSR
20
ns
SCKfalitime
tSF
20
ns
S1 .... SCKt
delay time
tOKS
120
ns
Symbol
= 5 V ±5%; CL = 100 pF
Min
Max
Unit
Conditions
Instruction
read
10
Internal Clock
liD
t::J
X2
Extemal Clock
~TJ
NC
Data setup
time for
address
tSADI
2tCYX
-95
ns
Data setup
timefor RD
tSROI
2tCYX
-35
ns
Data hold
time for RD
tHRDI
Data setup
time for
address
tSA01
4tCYX
-135
ns
High-speed
tSAD2
8tcyx
-135
ns
Low-speed
Data hold
time for RD
tHRD
0
ns
0
ns
ID~
Switching
Clock Circuits
~
C2
+ 70"C; VOO
Parameter
Setup and Hold
X1 t ....
CLKOUT delay
time
SCK low pulse
width
TA = -10 to
X2
X1 t .... RD
delay time
tOXRO
70
ns
X1 t .... WR
delay time
tOXWR
70
ns
Address
setup time
for RD
tSAR
Address
hold time for
RD
tHRA
RD pulse
width
twRI
ns
tCy,,60
5
ns
tCyx-30
ns
Instruction
read
twR1
3tCy,,30
ns
High-speed
twR2
7tcyx-30
ns
Low-speed
Address
setup time
forWR
tSAW
tcvx- 55
ns
Address
hold time for
WR
tHWA
WR pulse
width
tWW1
3tcy,,50
ns
twW2
7tCy,,50
ns
Low-speed
Data setup
timeforWR
tSDW1 3tcyx-100
ns
High-speed
tSOW2 7tCvx-100
ns
Low-speed
83YL·8211A
ns
5
WRI ....
data delay
time
towo
0
WR t .... data
float time
tFWO
10
RD, WR
recovery
time
tFl/
tcvx- 35
High-speed
ns
50
ns
ns
19
NEe
pPD77230A,77P230
Host Interface Timing, Slave Mode
= -10 to + 70"C; VOO = 5 V ±5%; Cl = 100 pF
Interrupt Reset Timing
= -10 to + 70"C; VOO = 5 V ±5%
TA
Parameter
Symbol
TA
Parameter
Symbol
Setup and Hold
NMI, INT pulse width
tiNT
6tcyx
ns
CS setup time for
HRD
tSCA
0
ns
NMI, INT hold time for
RESETt
tHANI
6tcyx
ns
CS hold time for HRD
tHAC
0
ns
NMI, INT recovery
time
tAINT
6tcyx
ns
RESET pulse width
tRST
6tCYX
ns
Min
Max
Unit
HRD pulse width
tWHAO
150
ns
CS setup time for
HWR
tscw
0
ns
CS hold time for HWR
tHWC
0
ns
HWR pulse width
IwHWR
150
ns
Parameter
Data setup time for
HWR
tSIHW
100
ns
Setup and Hold
Data hold time for
HWR
tHHWI
0
ns
HRD, HWR recovery
time
tHRV
100
ns
HRD, HWR hold time
for ROM
tHAH
tcyx
ns
PO, PI setup time for
XI
tspx
tcyx
PD, PI hold time for
Xl
tHXP
tcyx
Serial Interface Timing
= -10 to + 70"C; VOO = 5 V ±5%; Cl =
TA
Symbol
Unit
100 pF
Min
Max
Unit
tSSIS
55
ns
SIEN, SI hold time for
tHSSI
30
ns
SOEN setup time for
SCKt
tSSES
50
ns
ns
SOEN hold time for
SCK
tHSSE
30
ns
ns
SIEN, SOEN recovery
time
tsRV
tcys
ns
100
ns
SCK ~ -+ SORO delay
time
65
ns
SOEN
time
SCK~
Switching
tOSSQ
HRD 1 .... data delay
time
tOHAI
HRD t .... data float
time
tFHAI
XlI .... ROM t delay
time
tOXAH
100
ns
SOEN t
time
tOXAl
100
ns
SCK t -+ SO delay
time
tOSlSO
ns
SCK t .... SO hold
time
tHsHSO
ns
SCK 1-+ SO delay
time
tOSHSO
SCK t -+ SO float
time (SORO I)
tFSSO
~
delay
HRD, HWR t ....
ROM 1 delay time
tOHA
XI t -+ P2, P3 delay
time
toxp
20
Max
SIEN, SI setup time
for SCK ~
Switching
XI 1 -+ ROM
time
Min
10
2tcyx
+ 100
100
~
.... SO delay
-+
SO float
30
tOSESO
tFSESO
10
150
ns
60
ns
100
ns
60
ns
0
10
ns
60
ns
100
ns
NEe
pPD77230A,77P230
Timing Measurement Paints
Input
2.4V - - - V 2 . 2 V
2. 2V
V--
O.4V ---A..::O:::.8.:..V_ _--=O:::.8..;..V~
Output
~2.2V
2.2V:--A..;.O.;.;;.8.;;......V_ _..;;.O._8~V~
49-001649A
Clock Timing Waveforms
Master Clock
Xl
Clock Output
_--J/
49-001647A
21
NEe
pPD77230A,77P230
Clock Timing Waveforms (cont)
Switching
~---------------------------~YS'----------------------------~
SCK[1)
SICK, SOCK [2)
1+------------ltSSH-------------I i 4 - - - - - - - - - - - : t S S L - - - - - - - - - . j
tSR
tSF
Notes: [1] SCK is an output
[2] SICK and SOCK are inputs [asynchronous with X11
49-0016488
External Memory Access Timing Waveforms
Instruction Read (Master)
49-0016528
22
NEe
pPD77230A,77P230
External Memory Access Timing Waveforms (cont)
Data Read
I
"
CLKOUT~
to~XRO~
________
A11- AO,AX
r-
tOXRO--!
I
~~----~~----~
RO
tWR1,tWR2
tSAD1, tSAD2
031- 0 0 [1] _________
07- 0 0[2]
't" '
---l}-------~Ir--..\.\------------~~~---------
_
(
~--------
Notes: [1] Master mode
[2] Slave mode
49-001651B
23
NEe
pPD77230A,77P230
External Memory Access Timing Waveforms (cant)
Data Write
X1
CLKOUT
WR
tDWD
tSDW1. tSDW2
D31-DO[1]
D7-DO[2]
Notes: [1] Master mode
[2] Slave mode
49-0016508
Read~
Write
RD
\
WR
{.1
49-0016568
Write~Read
WR
\
{.-=\
RD
49-0016578
24
NEe
~PD77230A,77P230
Host Interface Timing Waveforms, Slave Mode
RQMPort
X1
CLKOUT \
/
\
'---.- + '
\'----+,/
/
"----i-'
\
I
RQM
..
,
F
.1·~1----
-"""""""1
I·
~_ _ _ __
-
49-0016606
Host Write
Host Read
~
-:J--------
~:J-
tDHRI
k
tHHWI
ftSIH~
_____
1015-100 - - - - - - - < 1
49-001658A
10tll-100_ _ _ _ _..J
_'_ __
49-001659A
25
ttlEC
pPD77230A,77P230
Interrupt Reset Timing Waveform
Reset
Interrupt
----------------------~
49-0016618
Serial Interface Timing Waveforms
Seriaiin
51
:X,----)(
49·001662A
26
NEe
pPD77230A,77P230
Serial Interface Timing Waveforms (cont)
Serial Out, Case 1 (SOEN interrupt control)
5CK
50RQ _ _ _ _J
so
------<1
m
Valid
49-0016539
Serial Out, Case 2 (SOEN control: SOEN low at SCI( low)
5CK
50RQ _ _ _ _ _JlljtD5H50
tDSESO--i
50------41
Valid
49-001654B
27
NEe
pPD77230A,77P230
Serial Interface Timing Waveforms (cont)
Serial Out, Case 3 (SOEN control: SOEN low at SCK high)
SCK
SORQ
tF550
50
-----------<1
valid
49-001655B
28
NEe
IIPD77240
32-Bit Floating-Point
Digital Signal Processor
NEC Electronics Inc.
Description
The JiPD77240 Digital Signal Processor (DSP) has been
developed for applications that demand high speed,
high precision, and a large data address area. Operations on 32-bit floating-point data (8-bit exponent,
24-bit mantissa) or 24-bit fixed-point data are executed
at 90 ns per instruction.
The instruction area is 64K x 32-bit words, and the data
area is 16M x 32-bit words. These large memory areas
open a wide range of application fields, such as computer graphics.
Internal circuitry includes a multiplier (32 x 32 bits),
instruction decoder, ALU (55 bits), and two independent data RAMs (each 512 x 32-bit words). An on-chip
library of commonly used DSP utility programs is
accessed as subroutine calls.
Also, there are two input ports and two generalpurpose output ports for system expansion, such as
handshaking with the host CPU, external device control, memory bank switching, etc.
Note: A table at the end of this data sheet compares the
JJPD77240 with its predecessor, the JJPD77230A.
Features
o 32-bit floating-point or 24-bit fixed-point data
operations
-32-bit floating-point multiplication circuit (8-bit
exponent + 24-bit mantissa) x 8-bit exponent
+ 24-bit mantissa) ..... (8-bit exponent + 47-bit
mantissa)
- 55-bit floating-point ALU and eight 55-bit
working registers
-47-bit barrel shifter
o Fast operations and efficient data transfer
- 90-ns instruction cycle
- Three-stage pipelining
- Dedicated data bus for on-chip RAM, multiplier,
and ALU
o Architecture specially suited to digital signal
processing
- Two independent on-chip data RAMs and data
RAM pOinters
-On-chip data RAM pointer comprises base
pointer and index register; base pointer can use
ring counting within any desired range.
50543
- Data ROM pointer operations include 2n-step
incrementing in addition to normal increment!
decrement operations
o External interface maintains Harvard architecture
with separate paths to instruction and data
memory areas.
- Usable instruction area: 64K x 32-bit words
- Usable data area: 16M x 32-bit words
-Address register specifying data area address
has provision for addition to base register as
well as increment/decrement operations.
o On-chip utility programs (subroutines)
-34 vector/matrix operations
- Data transfer to/from RAM with/without IEEE
format conversion
- Conversion: radians/degrees
- Scalar functions:
Floating-point division
Exponential, logarithmic
Trigonometric
o CMOS technology
o Single 5-volt power supply
o 132-pin ceramic PGA
Applications
o Graphics processing
o Image compression
o Numerical processing
o Speech processing
o General-purpose digital Signal processing
o Digital filtering (FIR, IIR) and FFT
o Instrumentation electronics
o High-speed controls
Ordering Information
Part Number
Package
JlPD77240R
132-pin ceramic PGA
tttfEC
pPD77240
Pin Configuration
132-Pin Ceramic PGA
cccccccccccccc
CCCCCOOCCCCCCC
OCOCCOCCOCOOOO
Bottom
View
14
13
12
ccc
oco
ceo
ceo
10
000
000
9
COC
COC
ceo
ceo
OOC
OOC
Pin
ceo
"'"ecce
ceo
coc
ooococccooccco
CCOCCCOCOCCCCC
oooooocccococo
Orienta~on
P N M L
K
J
H G F E 0
C B A
11
8
Top
7
View
6
5
4
3
2
Index Mark
/
ABC o
E
F G H J
K
L M N P
83FM-7951B
Pin-to-Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Pin
Symbol
A1
A2
A3
A4
011
013
0 16
017
C1
C2
C3
C4
05
Og
GNO
~
Voo
F3
F12
F13
F14
1010
1012
1013
L1
L2
L3
L12
A12
Ag
GNO
. 1031
N9
N10
N11
N12
IAa
IA1
RESET
CLOCK
A5
A6
A7
A8
~
0 22
0 25
026
C5
C6
C7
C8
014
016
0 23
027
G1
G2
G3
G12
A21
A22
A23
1014
L13
L14
M1
M2
1~8
1025
A11
A7
N13
N14
P1
P2
GNO
1029
A9
A10
A11
A12
026
0 30
IPO
C9
C10
C11
C12
031
OP1
10 1
GNO
G13
G14
H1
H2
1015
1016
A20
A19
M3
M4
M5
M6
GNO
A5
A1
IA13
P3
P4
P5
P6
Ao
103
107
04
07
H3
H12
H13
H14
A 16
1019
1016
1017
M7
M8
M9
M10
IA9
IA5
P7
Voo
P8
IA7
lAo
P9
I~
NMI
P10
~
P11
P12
P13
P14
RO
WR
INT
OP~
Symbol
A13
A14
91
92
IC
06
GNO
C13
C14
01
02
93
94
95
96
012
015
0 19
~1
03
012
013
014
010
GNO
105
106
J1
J2
J3
J12
A17
A16
A14
1~3
M11
M12
M13
M14
Voo
97
98
99
910
~4
E1
E2
E3
E12
01
03
06
106
J13
J14
K1
K2
1021
A6
A15
A13
N1
N2
N3
N4
E13
E14
F1
F2
109
10 11
9USFREZ
K3
K12
K13
K14
A 10
1027
1024
1~2
N5
N6
N7
N8
911
912
913
914
2
I~
Voo
0 29
IP1
IC
100
Voo
104
Do
I~
GNO
1030
1026
Voo
A4
A2
IS15
IA11
lAs
lAs
As
Aa
IA14
1A12
IA10
Voo
NEe
IIPD77240
Symbol-to-Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Ao
A1
A2
Aa
P3
M5
N4
P2
Do
01
~
03
F2
El
F3
E2
lAo
IA1
IA2
IAa
M9
Nl0
Pl0
N9
100
10 1
102
103
612
Cll
A14
C13
6USFREZ
CLOCK
INT
IPO
Fl
N12
P13
All
A.,
N3
M4
Pl
M2
04
05
06
07
01
Cl
E3
02
1A4
IA5
P9
104
105
106
10]
614
013
E12
C14
IPI
NMI
OPl
610
Ml0
A12
Cl0
Nl
L2
08
lAg
~
IA10
IA11
N7
M7
P6
N6
108
010
011
61
C2
03
Al
1010
10 11
014
E13
F12
E14
RO
RESET
WR
IC
Pll
Nll
P12
A13
63
A2
C5
64
IA12
1A13
1A14
IA15
P5
M6
P4
N5
1012
10 13
1014
1015
F13
F14
G12
G13
IC
VDD
VDD
VDD
611
68
813
C4
A5
~
A7
As
Ag
Og
I~
IA7
MB
NB
PB
tOg
OP~
A10
A11
K3
A12
A13
A14
A15
L1
K2
J3
Kl
012
0 13
0 14
015
A16
A17
A18
A19
J2
Jl
H3
H2
016
017
0 18
019
A3
A4
C6
65
1016
10 17
1018
1019
G14
H14
H13
H12
VDD
VDD
VDD
VDD
Mll
N2
P7
P14.
~o
Hl
Gl
G2
G3
020
~1
0 22
~3
A5
66
A6
C7
I~
1~1
1~3
J14
J13
K14
J12
GND
GNO
GNO
GNO
62
C3
C12
012
0 24
67
A7
A8
C8
1024
1~5
1~6
1027
K13
L14
M14
K12
GNO
GND
GNO
GNO
L3
M3
M12
N13
A9
69
Al0
C9
1~8
1029
1030
1031
L13
N14
M13
L12
A21
~
A23
Ml
~5
~6
027
~8
029
030
031
1022
3
tttlEC
pPD77240
Pin Functions
Symbol
Function
External data memory address output; becomes
high impedance when BUSFREZ is driven low.
BUSFREZ
CLOCK
External data memory break input. When this pin
is driven low, pins Ao - A31 and Do - 0 31 become
high impedance.
External clock input; 11.1111 MHz maximum
External instruction memory address bus; outputs
program counter (PC) value; becomes high
impedance on RESET input.
100- 1031
External instruction memory data bus input.
INT
Maskable interru pt input; keep low at least three
system clock cycles. INT should be driven high
during reset and within four system clock cycles
after rise of RESET signal. Falling edge detection;
interrupt address SH.
IPO,IP1
Genera~purpose
NMI
Nonmaskable interrupt input; keep low at least
three system clock cycles. NMI should be driven
high during reset and within four system clock
cycles after rise of RESET signal. Falling edge
detection; interrupt address 4H.
input port; pin status is judged
by branch instruction.
OPO,OP1
Genera~purpose output port; pin status can be set
and checked by bits 2 and 3 of status register SA.
RD
External data memory read strobe output; when
RD is low, data is input via the data bus. RD is
high during hardware reset and is not influenced
by BUSFREZ.
RESET
Internal system reset signal input; keep low at least
three system clock cycles.
WR
External data memory write strobe output; when
WR is low, data is output via the data bus. WR is
high during hardware reset and Is not influenced
by BUSFREZ.
voo
+ 5-volt power supply input; connect all Voo pins
to +5 volts.
GND
Connect all GND pins to ground.
IC
Internal connection; leave this pin open. Caution:
When any signal is applied to or read out from this
pin, normal operation of the IJPD77240 is not
assured.
FUNCTIONAL DESCRIPTION
The block diagram shows the internal 32-bit main bus
connecting to all functional blocks, including the ALU
area. Blocks are described in the Internal Functions
table.
The 55-bit processing-unit (PU) bus links the ALU input
to the 55-bit multiplier output register and the eight
55-bit working registers. Thus, the full 55 bits of precision can be maintained during extensive calculations.
4
In addition to the main bus and the PU bus, there is a
sub-bus linking the two RAM areas to both the ALU
input and the multiplier input registers. This link allows
simultaneous loading of the multiplier input registers in
parallel with ALU operations and in parallel with data
transfer operations that make use of the main bus.
There is a sub-bus connecting the ALU input to the
55-bit multiplier output and another sub-bus that can
route the working registers' contents back to the ALU
input.
Architecture
The pPD77240 has a Harvard architecture with separate memory areas for program storage and data
storage as well as separate multiple buses. A three
stage instruction execution pipelining scheme performs instruction fetch and execution in parallel. All
instructions are executed in a single cycle regardless
of whether the instruction is stored internally or in
external memory.
Instruction Memory
Internal instruction ROM holds 2K words x 32 bits
pre-programmed with library functions that perform
vector/matrix operations, scalar functions, conversions, etc. The addresses of these subroutines are in
the high 2K of the 64K-word instruction memory address space.
Data Memory
pPD77240 has three data memory areas: internal data
ROM, internal data RAM, and external data RAM. Data
ROM holds 1K words x 32 bits pre-programmed with
table lookup data and constants accessed by the internallibrary routines as well as by user programs.
Internal data RAM consists of two separate and independently addressable areas, each 512 words x 32 bits.
Each RAM area can be addressed by a base register, an
index register, or the sum of the two. The base register
and/or index register may be incremented, decremented, or cleared. In addition, the base pointer can
operate in a modulo count mode, and the index register contents may be replaced by the sum of the index
and base registers. Data stored in RAMO and RAM1 can
be simultaneously input to the multiplier.
External data RAM may contain up to 16M words x 32
bits for data exchange with other devices and processing large volumes of data. External RAM is addressed
by the 24-bit AR register.
NEe
Multiplier and AW
The floating-point multiplier has two 32-bit input registers (K and L), which are accessible both to and from
the main bus. The multiplier produces the 55-bit product of the K and L register contents automatically in a
single instruction cycle (there is no multiply instruction).
The 55-bit result is stored in the M register in a-bit
exponent, 47-bit mantissa format. The contents of the
M register can be transferred to the main bus (32 bits)
or to the ALU via the processing unit bus (55 bits). The
multiplier consists of a 24- by 24-bit fixed-point mUltiplier and an exponent adder, so that it can also be used
for fixed-point multiplications.
The 55-bit floating-point ALU is capable of a full set of
arithmetic and logical operations (see "Instructions"
section). There is a 47-bit bidirectional barrel shifter,
which can perform general-purpose shifting in addition to the mantissa alignments required for floatingpoint arithmetic.
pPD77240
disabled condition, then it may be acted upon (or
disregarded) at a later time. Interrupt status can be
read from the SR register; status is changed by control
field manipulation in an OP instruction.
Control of two general-purpose output pi ns is effected
by writing to the SR register. The states of two generalpurpose intput pins are tested by conditional branch
instructions.
Mode Register
Addition of the 32-bit mode register (MR) is a significant
enhancement over pPOn230 architecture. The various
bit fields of the mode register are usually set/cleared by
control field (CNT) instructions. The register can be
read and written, saved and restored. This feature is
useful for interrupt handling and other subroutines, as
well as during debugging. The mode register records
the state of RAM and ROM addressing specifications,
PU specifications for format and normalization processing, and for interfacing the PU bus with the main
bus.
A separate exponent ALU (EAU) determines shift values in floating-point work. The ALU status is reflected
in one of two identical processor status words (PSW)
that contain carry, zero, sign, and overflow flags. The
results of the ALU operation are stored in one of eight
55-bit accumulators or "working registers."
There are two 55-bit input registers to the ALU called
the P register and the Q register. The Q register input is
selected from one of the eight working registers, while
the P register input is selected from among the 55-bit
PU bus, the 32-bit main bus, data RAMO, data RAM1,
and the 55-bit M register.
Loop Counter
A loop counter is included in the design of the
pP077240. This 32-bit register connects to the main bus
and can be used for general-purpose storage as well as
a loop counter. When used as a loop counter, only the
low 10 bits are active; the upper 22 bits are not affected.
The count can be decremented by a control field bit
during an operation (OP) instruction. When the loop
counter is decremented past zero, the instruction following the decrementing will be skipped.
System Control
An external clock drives internal clocking at the same
rate (single phase).
Two interrupts are provided: one maskable, one nonmaskable. The maskable interrupt can be "memorized,"
so that if an interrupt occurs while it is in the interrrupt
5
t-IEC
IIPD77240
Internal Functions
Symbol
Name
Description
Symbol
Name
Oescrl plion
ALU
Arithmetic
logic unit
Logical operation oircuit for 47-bit
mantissa data
M
M register
55-bit register holding FMPY
multiplication result
AP
Address port
24-bit address port for data
memor.y
MR
Mode
register
AR
Address
register
24-bit register specifying data
memory address
32-bit reg·ister showing
specification or operation status of
internal status, such as on-Chip
data RAM pointer specification
BPO
Base
pointer 0
Register specifying RAMO base
address
P
P register
55-bit register holding ALU and
EAU input data
BPl
Base
pointer 1
Register specifying RAMl base
address
PC
.Program
counter
16-bit register specifying
instruction memory address
BR
Base
register
32-bit base register for data
memory address register AR
PORT
Port
Genera~purpose
BSHIFT
Barrel
shifter
Barrel shifter for P and Q register
mantissa
PSWO,
PSWl
Program
status word
0, word 1
Registers indicating ALU/EAU
operation result status
CLKGEN
Clock
generator
Internal system clock generation
circuit
Q
Q register
55-bit register holding ALU and
EAU input data.
Decoder
Instruction
decoder
Instruction decoding circuit
RAMO,
RAMl
Data RAM
0,1
Data storage RAMO and RAMl
(each 512 words x 32 bits)
DP
Data port
32-bit data port for data memory
DR
Data
register
32-bit register for interface.
between DP and internal data bus
(main bus)
DRaM
Data ROM
ROM holding fixed data (1 K words
x 32 bits)
EAU
Exponent
arithmetic
unit
8-bit exponent data operation
circuit
Exchange
Data
exchanger
Selects P or Q mantissa data as
input to barrel shifter.
FMPY
Floatingpoint
multiplier
32-bit floating-point data multiplier
(8-bit exponent, 24-bit mantissa);
32 bits x 32 bits -+ 55 bits
lAP
Instruction
address port
16-bit address bus for instruction
memory
lOP
Instruction
data port
32-bit data bus for Instruction
memory
INT CNT
Interrupt
controller
External interrupt control circuit
IROM
Instruction
ROM
ROM holding on-chip, fixed utility
programs (2K words x 32 bits)
IXO
Index
register 0
Register specifying RAMO index
address
IXl
Index
register 1
Register specifying RAMl index
address
K
K register
32-bit register holding FMPY input
data
L
L register
32-bit register holding FMPY input
data
LC
Loop
counter
32-bit program loop count setting
register
6
input-output port
RP
ROM pointer
Register specifying ROM address
R/W CNT
Read/write
control
circuit
Data memory read/Write control
circuit
SAC
Shift and
count circuit
Shift amount detection circuit for
Q register mantissa data
SP
Stack
pointer
Pointer indicating stack address
SR
Status
register
22-bit register showing generalpurpose output port selting,
confirmation and error status, and
maskable interrupt operating
status
STK
Stack
Eight-level, 16-bit stack
SVR
Shift value
register
Shift amount selting register
TR
Temporary
register
32-bit genera~purpose register
WRIC
Working
register
interface
circuit
Specifies data transfer format
between working registers and PU
bus
WROto
WR7
Working
register
Oto 7
Registers holding ALU and EAU
operation results
NEe
pPD77240
"PD77240 Block Diagram
FMPY
32 x 32 bits
~55bits
00-0 31
~B~B+------+-
•
"'''-GjGj ·1
.•
1
•
0------1---
01------'
~.-~------------~
I=I~'I
!!-G
55-Bit
PU Bus
7
WR
---fRiWl1+_.o----,
RO~
6
5
4
3
2
STK
IcLi Valid from the next instruction.
9
NEe
IIPD77240
Figure 3. CNT Field ofthe Operation Instructions
Table 4. Q Field Contents
Mnemonic
26
25
24
23
21
22
20
1
19
17
18
16
15
0
0
Ml
DPO
DPI
0
1
0
0
EA
DPO
DPI
0
1
0
1
RP
MO
DPO
FC
0
1
1
0
RP
Ml
DPI
FC
0
1
1
1
RP
MO
MO
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
-
1
0
0
1
1
RW
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
Ml
L
BASEl
BASEO
-
RPC
FC
FC
L
FC
L
FC
APM
L
FC
WT
-
L
FC
NF
WI
L
FC
FIS
FD
L
-
BM
IEM
I
1
0
1
1
1
0
RPS
SHY
1
1
1
NAL
1
83FM·7958A
P Field. The 2-bit P field specifies the input data to the
P register object of the operation when a dyadic operation is executed. See table 3.
Table 3. P Field Contents
Mnemonic
P Field Bits 14-13
Input Data to P Register
IB
M
00
01
PU bus
*FMPY output data
RAMO
RAMI
1 0
11
RAMO
RAMI
* In the SRC field, M refers to M register data.
Q Field. The 3-bit Q field specifies one of the working
registers, WRO through WR7. See table 4.
(1) A monadic (one-operand) operation is performed
on the data in the working register specified by the
Q field and the result is stored in the same working
register.
(2) A dyadic (two-operand) operation is performed on
the data specified by the Q field and the P field, and
the result is stored in the working register specified
by the Q field.
Q Field Bits 12-10
Working Register
o0
oa
WRO
WR1
WR2
WR3
0
1
a 1 a
a 1 1
0
a a
a 1
1 0
11
4
5
WR4
WR5
WR6
WR7
2
3
6
7
SRC Field. The 5-bit SRC field specifies the source
register in a transfer instruction. Table 5 lists the 32
selections.
DST Field. The 5-bit DSTfieid specifies the destination
register in a transfer instruction. Table 6 lists the 32
selections.
Table 5. SRC Field Contents
Mnemonic
SRC Field
Bits 9-5
Selected Regi ster
·Bus
NON
RP
PSWO
PSW1
a a
oa
a a
a a
Nonselection
ROM pointer
Program status worda
Program status word1
Main
Main
Main
SVR
SR
LC
STK
oa
Shift value register
Status register
Loop counter
Stack
Main
Main
Main
Main
M
ML
ROM
TR
01
a 1
a 1
o1
# M register
Low 24 bits of M register
Data ROM
Temporary register
PU
PU
Main
Main
AR
BR
DR
MR
o1
o1
o1
o1
Address register
Address base register
Data register
Mode register
Main
Main
Main
Main
a
a
a
a
1
a a 1
a 0 1
oa 1
a
a
1
1
0
1
0
1
a a
a 1
1 a
11
a a
a a
a 1
01
a
1
a
1
a a
01
1 0
11
WRO
WR1
WR2
WR3
a a a 0
0001
o010
o011
Working
Working
Working
Working
registerO
register1
register2
register3
PU
PU
PU
PU
WR4
WR5
WR6
WR7
a 1
a 1
01
01
Working
Working
Working
Working
register4
register5
register6
register7
PU
PU
PU
PU
RAMO
RAM1
BPO
BP1
IXO
IX1
K
L
a 0
a 1
1 0
11
000
a 0 1
o1 0
o1 1
00
a 1
1 a
11
RAMO
RAM1
Base pointerO
Base pointer1
Main
Main
Main
Main
Index registera
Index register1
K register
L register
Main
Main
Main
Main
* Bus connected to selected registe,
# In the P field, M indicates FMPY output data.
10
NEe
IIPD77240
Table 6. DST Field Contents
Figure 4. Branch Instruction Format
Mnemonic
DST Field
Bits 4-0
Selected Register
*Bus
NON
RP
pswa
PSWI
00
a a
a a
a a
a
a
a
a
a 0
01
1 a
1 1
Nonselection
ROM pointer
Program status worda
Program status wordl
Main
Main
Main
SVR
SR
LC
STK
00
a a
a a
a a
1
1
1
1
a a
a 1
1 a
11
Shift value register
Status register
Loop counter
Stack
Main
LKRa
KLRI
TRE
TR
01
01
01
01
a 0
a a
a 1
01
L register (RAMO to K register)
K register (RAMI to L register)
Exponent part of TR register
Temporary register
PU
PU
Main
Main
AR
BR
DR
MR
a 1
01
01
01
a a
a 1
1 a
11
Address register
Address base register
Data register
Mode register
Main
Main
Main
Main
a
a
1
1
a
1
a
1
Working
Working
Working
Working
registerO
registerl
register2
register3
PU
PU
PU
PU
1 a 1 a a
1 a 1 a 1
1 a 1 1 a
a 1 11
Working
Working
Working
Working
register4
register5
registerS
register?
PU
PU
PU
PU
WRa
WRI
WR2
WR3
WR4
WR5
WR6
WR?
RAMO
RAMI
BPa
BPI
lXa
IXI
K
L
a
a
a
a
a
a
a
a
a a
a a
a 1
01
a
1
a
1
a
1
a
1
a a
01
1 a
11
NA
(13)
main
Main
Main
RAMO
RAMI
Base pointerO
Base pointerl
Main
Main
Main
Main
Index registerO
Index registerl
K register
L register
Main
Main
Main
Main
B Field. The 4·bit B field indicating a branch instruc·
tion is always binary 1101.
NA Field. This field contains the 13-bit displacement
value (+4096 to -4096) added to the current PC value to
give the branch destination address.
NAH Field. This field contains a 3·bit prefix that is
combined with the NA field of the immediately follow·
ing branch instruction to create a 16·bit displacement
value, -f32K to -32K
C Field. The 5·bit C field specifies one of the 28 kinds
of branch instructions described in table 7.
SRC Field. The 5·bit SRC field specifies the source
register in a transfer (move) instruction. See table 5.
DST Field. The 5·bit DST field specifies the destina·
tion register in a transfer (move) instruction. See
table 6.
* Bus connected to selected register.
Branch Instructions
Branch instructions specify unconditional jump, con·
ditional jump, subroutine call, and return. Transfer
processing can be performed at the same time. Figure
4 shows the format of the branch instruction and the
long branch prefix instruction. The latter is used to
extend the displacement value of the branch destina·
tion address.
11
NEe
pPD77240
ELECTRICAL SPECI FICATIONS
Table 7. C Field Contents
Mnemonic
C-Fleld
Bits 14-10
Branch Condition
JMP
CALL
RET
JNZRP
00000
0000 t
0001 0
0001 1
Branch with no condition.
Subroutine call.
Return
If ROM pointer is not zero.
JZO
JNZO
JZl
JNZI
001
001
001
001
If zero flagO
If zero flagO
If zero flagl
If zero flagl
JCO
JNCO
JCl
JNCI
01 o 0 0
01 001
01 01 0
01 01 1
JSO
JNSO
JSl
JNSI
01
01
01
01
00
01
1 0
11
If carry
If carry
If carry
If carry
00
o1
1 0
11
If sign
If sign
If sign
If sign
is
is
is
is
flagO
flagO
flagl
flagl
flagO
flagO
flagl
flagl
Absolute Maximum Ratings
TA = +25'C
set.
reset.
set
reset.
Parameter
is set.
is reset.
Is set.
is reset.
01 00
01 01
1 000
1 0 0 1
Hexponent overflow flagO is set.
If exponent overflow flagl is reset.
H input portO Is on.
If if input porn is on.
JNZIXO
JNZIXI
JNZBPO
JNZBPI
PRE
101 0
1 0 1 1
1 1 00
1 1 01
1111
If index registerO is not zero.
H index reglsterl Is not zero.
If base pointerO is not zero.
If base pointerl is not zero.
Prefix for long branch
is set.
is reset.
is set.
is reset.
Note: A result is not assured if an object code not specified above Is
used.
Load Instructions
A load instruction consists of three fields as shown in
figure 5. The register (or other element) specified by the
DST field (table 5) is loaded with the 24-bit data contents ofthe 1M field. The data path into the register is via
the 24 mantissa bits of the main bus.
The LDI field is always binary 111.
Figure 5. Load Instruction Format
Branch
~~~;
iii iii iii i
51
i~~~i
I
0
83FM-7955A
12
-10 to +70'C
-65 to
+ 15O'C
Symbol
Min
Typ
Max
5.0
5.25
Unit
V
Voo
4.75
Low-level input
voltage
VIL
-0.3
+0.8
V
High-level input
voltage
VIH
2.2
VOO +0.3
V
Low-level clock input
voltage
VILC
-0.3
+0.5
V
High-level clock input
voltage
VIHC
3.9
VOO +0.3
V
Power supply voltage
JEVO
JEVI
JIPO
JIPI
i
-0.5 to Voo + 0.5 V
Recommended Operating Conditions
is set.
is reset.
is set.
is reset.
If overflow flagO
H overflow flagO
If overflow flagl
H overflow flagl
291 i i i i i i i i i
Output voltage, Vo
Storage temperature, TSTG
o0 0 0
0001
001 0
00 1 1
11~~:
-0.5 to Voo + 0.5 V
Operating temperature, TOPT
JVO
JNVO
JVl
JNVI
31
-0.5 to + 6.5 V
Power supply voltage, Voo
Input voltage, VI
Capacitance
= + 25'C; voo = 0 V; fc =
TA
1 MHz
Parameter
Symbol
Max
Unit
Input
capaci tance
CI
10
pF
Output
capacl tance
Co
20
pF
Typ
Conditions
Unmeasured pins
returned to 0 V
NEe
pPD77240
DC Characteristics
TA= -10to+70"C;Voo= 5V±5%
Parameter
Symbol
Low-level output voltage
VOL
High-level output voltage
VOH
Low-level input leakage current
ILiL
Min
Typ
Max
Unit
0.45
V
Conditions
IOL = 2.0 mA
V
0.7VOO
IOH = -400/JA
-10
/JA
VIN = OV
High-level input leakage current
ILiH
10
/JA
VIN = VOO
Low-level output leakage current
IlOL
-10
/JA
VOUT = OV
High-level output leakage current
IlOH
10
/JA
VOUT = Voo
Clock input current
IIICI
400
/JA
Power supply current
100
460
mA
AC Characteristics
TA = -10to +70"C; voo = 5 V ±5%;
Parameter
cl
320
fCY = 11.1111 MHz
= 100 pF
Symbol
Min
Max
Unit
Conditions
Clock Timing
Clock cycle time
tec
90
1000
ns
Clock high-level width
twCH
45
500
ns
45
Clock low-level width
twCL
500
ns
Clock rise time
tRC
5
ns
Clock fall time
tFC
5
ns
Test points at
1.0 and 3.0 V
Instruction Resd Timing
Data setup time to CLOCK
~
tSUIOC
15
Data hold time from address fixed
ns
tHAIO
5
CLOCK I to address delay time
tOCIA
CLOCK ~ to address hold time
tHCIA
0
ns
isuoc
15
ns
tHRO
5
ns
ns
35
When an
instruction is
read
ns
Dsts Read/Write Timing
Data setup time to CLOCK
Data hold time from RD
t
t
CLOCK ~ to address delay time
tOCA
CLOCK ~ to address hold time
tHCA
35
tOCR
CLOCK t to RD hold time
tHcR
0
RD low-level width
twR
70
CLOCK t to WR ~ delay time
tocw
CLOCK t to WR hold time
tHCW
0
WR low-level width
tww
70
CLOCK
t to data delay time
25
CLOCK ~ to output data hold time
tHca
CLOCK ~ to output float time
tocoz
RD, WR recovery time
tflv'
ns
ns
ns
ns
45
ns
ns
0
60
70
ns
ns
25
toco
access
ns
0
CLOCK t to RD ~ delay time
ns
Applies to
external data
memory
ns
ns
Continuous
operation
13
•
I
!\fEe
pPD77240
AC Characteristics (cant)
Parameter
Symbol
Min
Unit
Max
Conditions
Interrupt, Reset Timing
RESET setup time to CLOCK I
tsURSTCL
RESET low-level width
twRST
NMI, INT input disable time from RESET t
NMI, INT low-level width
NMI, INT recovery time
RESET I to
H~Z
data float time
30
ns
4tcc
ns
tOISRSTINT
4tcc
ns
twlNT
3tcc
ns
tFtlINT
3tcc
ns
tORSTDZ
Hi-Z data fixed time
ns
3tcc
3tcc
toculV
+
tFC
+ 30
ns
Input, Output Port Timing
IPO, IPI setup time to CLOCK I
35
tsUIP
IPO, IPI hold time from CLOCK I
ns
35
ns
CLOCK I to' OPO, OP1 delay time
40
ns
BUSFREZ Timing
BUSFREZ low-level width
tWBFR
3tcc
ns
BUSFREZ setup time to CLOCK I'
tsUBFR
10
ns
BUSFREZ input disable time from RESET t
tOISRSTBFR
4tcc
ns
tOISBFRRST
4tcc
RESET release disable time from BUSFREZ
t
ns
CLOCK 1 to data output float time
tOBFROZ
60
ns
CLOCK 1 to address output float time
tOBFRAZ
60
ns
CLOCK I to data output delay time
tOBFRO
45
ns
CLOCK 1 to address output delay time
tOBFRA
40
ns
Timing Waveforms
Voltage Thresholds for Timing Measurements
Clock Input
Input Waveform
2.4V--V2.2V
0.4 v
2.2V
V
2.2V
0.8V
X=
I
--A..:O:;;.8:..:V:..-_ _ _ _---:O:;;.8:..:V:..-A--
=x
Output Waveform
2.2 V
0.8V
83FM-7944A
I1PD77240
External
Clock Source
1-----l~~1 CLOCK
CLOCK
IWCH
~--l~r.-tWCL
_l-tRC
83FM-7945A
14
NEe
,.,PD77240
Instruction Read
'='i .c.!.
\'---------11
~_ _ _ _ _---I-
IAO-IA15
0- 31 ________
10 10
.,!i_'-i-~-_-_-_t-~ -I~-C_=1:;:,·:=-~ i'"I-
X'-'______
:~ ~~~ -<,..____----.)-__________
_
'
~_ _ _
{ _J-_-,_ _
, ~~;.\M'.
~,
_
83FM-7946B
I
Data Read
~
~tHCR"
I+-tOCR
\
0:
tWR
tsuoc-
Hi-Z
--------------------------4
f\-
I
1-
tRV
~
tHRO
~------------------83FM 7947B
15
NEe
JlPD77240
Data Write
,,=
'a'a
,I
;....------,~'----X
\ :r:
i:''"'~-..l..-I------_-..l..-I_-----1--l...-K~============~
-1
{,row
'WN
~ ['~.
/
tHCA
I
"",, _________!'c~=~:~--------tHCQ---rol--- ______________ _
83FU-794SB
Read/Write
Read.to-Write Operation
Wrlte-to-Read Operation
\\.-_---{
'~1'________J/,...-83FM·7949B
16
tt{EC
pPD77240
Interrupt, Reset
CLOCK~
RESET
\'"---~J-------'I
~.........----tWRST'-------j~
_ 'm
~~~
L
-lD'SRST'NT
-"~'~ 1r _____ ~L __ ~=1:--I~
-_tW_I_NT_-_-_-_-_-_...,_~_ _ _ _ _ _ _ _ __
E-_-_-_-_-_
O~.OP1 _______~~
.~
83FM-79508
Input/Output Port
CLOCK
~~~'~ru.'-------Jk""l'---/_\'-------'_1_
)
1~.IP1
,---.j1.
DOP
OPO.OP1--------------)(-------------------------t
1.
+
..
1
83FM-79S1B
17
•
ttlEC
pPD77240
BUSFREZ
CLOCK
-~~~t-s_U~B~F-R_-_-_-tWB-F-R----+,-;!J ~ ,~,
li"'oE_f-__
t_O_B_FR_A_Z_-i_..:.-~~---------~~-------,------
Ao-A23 ____________
-I _
00-
0
ItOBFRO
~{~---------'!:~-------=1-----
31 _ _ _ _ _ _ _ _ _ _ _t_OB_F_RO_Z___
RESET
BUSFREZ
Ji
\
___________
_
--'/j--tOISBFRRST~-tOISRSTBFR=1'_
~
_______
.
83FM·79S2B
p.PD77230A and p.PD77240 Comparison
Item
,u.PD77230A
,u.PD77240
Operation mode
Master and slave modes
Master mode
Most functions are derived from 77230A master
and slave mode functions.
2
Host I/O pins
CS, HRD, HWR, RQM, and 1/00 -1/015
Not available
Data input/output with another CPU is via the
external data memory area.
3
Seriall{O pins
SICK, SIEN, SI, SOCK, SORQ, SOEN, and SO
Not available
Data input/output with another device is via the
external data memory area.
4
Low-speed area of
external data memory
External data memory access timing is divided by
the memory address into two parts:
• High-speed access area requiring two instruction
cycles per read or write operation .
• Low-speed access area requiring four instruction
cycles per read or write operation.
All external data memory accesses can be made in
two instruction cycles.
5
External clock
External clock, if required, must be twice the
internal clock frequency.
Internal clock can be controlled by an external
crystal.
External clock must be the same frequency as the
internal clock.
18
NEe
I'PD77240
"PD77230A and "PD77240 Comparison (cont)
Item
"PD77240
6
ROY function
Available
Not available
All external data memory accesses are terminated
in two instruction cycles.
7
Instruction cycle
150 ns max (6.66 MHz)
90 ns max (11.11 MHz)
8
External memory pins
Pins Do - 031 and Ao - A31 serve external
instruction memory and data memory.
While a program in instruction memory is being
executed, data memory cannot be accessed.
Pins 100 - 1031 and lAo - IA15 serve external
instruction memory; pins Do - 0 31 and Ao - A23
serve external data memory.
While a program in instruction memory is being
executed, data memory can be accessed.
Instruction memory
6Kwords max
On-chip memory: 2K words
External addition: 4K words max
64K words max
On-chip memory: 2K words
External addition: 62K words max
9
area
10
External data memory
area
8K words (32K bytes) max
4K words are shared with external instruction
memory
16M words (64M bytes) max
All words are dedicated to data memory.
11
Address and library
program of on-chip
instruction memory
OH to 7FFH: user programmable
F800H to FFFFH: library program is loaded.
• Primary math functions (sin, exp, etc.)
• Vector matrix operation library
12
loop counter (lC)
10-bit configuration
10-bit down counter
32-bit configuration
High-order 22-bit latch + low-order 10-bit down
counter.
In decrement by DEClC instruction, only the loworder 10-bit data changes.
13
Branch operation
Absolute address branch
• Branch instructions (JMP and others): branch to
all areas (OH to 7FFH, 1000H to 1FFFH)
• CNT field NAl bit (JBlK): branch in block every
200H. When PC = 470H, branch to 400H to
5FFH.
Relative address branch
• Branch instructions (JMP and others):
PC <- current PC + jdisp Odisp; signed
displacement -4096 to 4095) .
When PC = 1470H, branch to 470H to 246FH.
• long branch prefix instruction (PRE instruction):
branch to all address areas (OH to F F F FH) in
combination with the above branch instruction.
• CNT field NAl bit (JBlK): PC <- current PC +
jdisp Odisp; signed displacement -256 to +255).
When PC = 470H, branch to 370H to 46FH.
14
NMI, INT interrupt
address
NMI: subroutine call at address 10H.
INT: subroutine call at address 100H.
NMI: subroutine call at address 4H.
INT: subroutine call at address BH.
15
SVR (shift value
register)
When the hardware is reset, the register contents
are undefined.
Initialized to OOH by hardware reset.
16
Package
68-pin PGA
132-pin PGA
17
Voo and GND pins
3 Voo pins; 3 GND pins
7 Voo pins; 8 GND pins
18
General-pu rpose input
and output ports
Input: PO, P1
Output: P2, P3
Data at the output ports is set by bits P2 and P3
in the CNT field
Input: IPO, IP1
Output: OP~, OP1
Data at the output ports is set by transferring bits
OPO and OP1 from the status register.
19
Hardware reset tim ing
Interrupt input is disabled in three instruction
cycles after hardware reset.
Interrupt input is disabled in four instruction cycles
after hardware reset.
20
RD/WR signal
Active low for 1.5 instruction cycles.
When "MOV WRO, DR RD;" is executed, the WRO
contents are undefined.
Active low for 1 instruction cycle.
When "MOV WRO, DR RD;" is executed, the DR
contents are transferred to WRO before RD
instruction execution.
21
Address port in RD/
WR operation
AR contents cannot be changed in execution of
RD/WR instruction.
AR contents can be changed in execution of RD/
WR instruction (read/write operations are carried
out with the contents before change).
19
NEe
fJ PD77240
p.PD77230A AND "PD77240 COMPARISON (cont)
Item
"PD77230A
"PD77240
22
Timing when data
transferred to address
register AR becomes
valid
The data becomes valid when the external data
memory address from the next instruction cycle of
data is transferred to AR.
Example: LDI AR, 1000H;
RD;
Contents at address 1000H of the external data
memory can be read to DR.
Data in CNT field operations becomes valid from
the next instruction cycle of the executed
instruction cyole.
The data beoomes valid when the eJol
Pin
Syni:>ol
Pin
Syrrool
Pin
Symbol
A2
PE
B9
SBAUO
FlO
PA7
K4
P03
A3
S02
Bl0
STEXT
Fll
GNO
KS
PO,
A4
SOlEN
Bll
PAO
Gl
Xl
Ke
POO
AS
SICK
Cl
PFO
G2
X2
K7
PCs/RO
A6
VOO
C2
OACK
Gl0
PBO
K8
PC3/A3
A7
RBAUO
Cl0
PAl
Gil
PB,
Kg
PC1IA,
A8
RxO
Cll
PA2
HI
CLKO
Kl0
PBS
A9
STINT
01
OALO
H2
INT
Kll
PB7
Al0
TxO
02
OADT
Hl0
PB2
L2
IC[Nole2]
Bl
PFI
010
PA3
Hll
PB3
L3
POe
P04
'1
<"
2
3
4
5
6
7
8
9
10
11
B2
PF2
011
PA4
Jl
RST
L4
B3
S02ST
El
AOST
J2
PU [Note 1]
L5
P02
B4
SOIRa
E2
ADCK
Jl0
PB4
L6
VOO
BS
SOl
El0
PAs
Jl1
PBS
L7
PCSIWR
BS
SllEN
Ell
PAs
Kl
IC [Note 2J
L8
PC4ICS
B7
Sil
Fl
ADIN
K2
P07
L9
PC21A2
B8
RT
F2
GNO
K3
Pes
Ll0
PCO/AO
A
B
C
D
E
F
H
K
G
Notes:
[1] In normal operation ocnneet the Pull Up (PU) pin to the VOD Pin through a pull up resistor.
[2] In normal operation the Internal Connection (IC) pin must be open.
63ML·59048
2
NEe
I'PD77810
Pin Identification
Symbol
I/O
Function
Symbol
I/O
Function
General-Purpose Parallel Porl
General-Purpose Serial Porl (conI)
Ao-A3f
SOfEjij
In
Serial Output 1 Enable: Enable pin for 501 serial
input. When this pin Is 0, 501 serial output is
enabled.
SOlRQ
Out
Serial Output 1 Request: Request pin for 501
serial output. This pin Is set to 1 when a serial
output Instruction to 501 Is executed. When
inverted, 501 RQ can be input to SOfEjij.
502
Out
Serial Output 2: DSP serial output pin (16 bits).
This pin outputs serial data with an Instruction In
synchronization with the falling edge of the ~
serial clock when S02ST is 1.
S02ST
Out
Serial Output 2 Strobe: Request pin for 502 serial
output. This pin Is set to 1 when a serial output
instruction to 502 is executed.
In
PCo-PC3
Address AO to A3: Address input. Used to specify
the C-RAM address.
~/PC4
In
Chip Select: Chip Select Input.
00-0 7/
PDo-PD7
I/O
Data Bus 00-07: Data Bus. When specified as a
bus by the PCMR register, 00-07 are used as a
tri-state data bus. In this case, port C is used as
an address bus or control bus, or inputs a Chip
Select signal.
PAo-PA7
I/O
Port A: 8-blt general-purpose I/O port. I/O is
selectable on a four-bit basis. It can be specified
by the PTMR register.
PBo-P~
I/O
Port B: 8-blt general-purpose I/O port. I/O Is
selectable on a two-bit basis. It can be specified
by the PTMR register.
PCo-PCa
I/O
Port C: 7 -bit genera~purpose I/O port. I/O is
selectable as a general-purpose I/O port on a bit
basis. Port C Inputs an address or a read/write
signal from the host computer when port 0 is
used as the bus. I/O can be specified by the
PCMR register.
I/O
PE
RD/PC5
Port 0: 8-bit general-purpose I/O port. I/O Is
selectable as a general-purpose I/O port on a bit
basis. It can be specified by the PDMR register.
Port 0 has a data bus function, transferring data
to and from an external unit in the 16-byte C-RAM
space. The bus/port can be specified by the
PCMR register.
In
Port E: l-bit general-purpose input port.
Out
Port F: 3-bit general-purpose input port.
In
Read Strobe: Used to input Read Strobe from the
host computer.
In
Write Strobe: Used to Input Write Strobe from the
host computer.
General-Purpose Serial Pori
511
501
In
Serial Input 1: General-purpose serial input pin (16
bits).
The pin reads data Input to SIT in synchronization
with the rising edge olthe SlCRserial clock when
the 81 EN pin Is O.
In
Serial ClockforSll and 501: Input pin forSll and
501 serial clock. The I/O serial data Is in
synchronization with SlCR.
In
Serial Input 1 Enable: 511 serial Input enable pin.
When this pin is 0, 511 serial input Is enabled.
Out
Serial Output 1: General-purpose serial output
pin (16 bits).
The pin outputs data in synchronization with the
failing edge of the SlCR serial clock when the
SOfEjij pin Is 0.
AID and D/A Serial Interface
ADCK
Out
AID Serial Clock: AID conversion serial clock.
Data is Input to the ADIN pin in synchronization
with the falling edge of the ADCK.
ADI N
In
AID Data Input Input pin for AID conversion data.
Data input to this ADIN pin is input from MSB in
synchronization with the rising edge of the ADCK
serial clock when ADST is 1.
The ADIN pin is serial Input of the DSP portion.
ADST
Out
AID Start Strobe: Output pin for AID conversion
start strobe. This ADST pin is enable signal for
the ADiN serial input. It can combine receive PLL
withADCK
5ACK
Out
D/A Serial Clock: D/A conversion serial clock.
Data Is output from the DAOT pin In
synchronization with the falling edge of DACK,
DALD
Out
D/A Data Load Strobe: Output pin for D/A
conversion load strobe. This pin can combine
transmit PLL together with DAO'R
DAOT
Out
D/A Data Output: Output pin for D/A conversion
data. The pin outputs DIA conversion data from
MSB in synchronization with the falling edge of
the 5ACK serial clock when DALD pin output is 1.
Serial Control
AX Baud Rate Clock: Received data baud rate
clock output. This pin Is also used as an input port
(PGol depending on the PLLMRl mode setting.
RBAUD
(PGol
I/O
RT
Out
AX Clock: Received data bit rate clock output.
RxD
Out
Received Data: Received data serial output or
output port. The received data Is outputfrom LSB
using the bit string synchronous to the RT
received clock as a start-stop signal.
3
III
tt1EC
"PD77810
Pin Identification (cont)
Symbol
I/O
Capacitance
TA = 25
Function
Ssr.' Control (contJ
SBAUD
(PG 1)
I/O
TX Baud Rate Clock: Transmitted data baud rate
clock output. This pin is also used as an Input port
(PG1) depending on the PLLMRI mode setting.
STEXT
In
TX Clock External: Transmitted data bit rate clock
Input
STINT
Out
TX Clock Internal: Transmitted data bit rate clock
output.
TxD
In
Transmitted Data: Transmitted data serial input or
Input port The transmitted data Is Inputfrom LSB
using the start-stop signal Input to the TxD pin as
a transmit clock or In synchronization with STINT
orSTEXT.
Cin:uit Control
CLKO
Out
Clock Out: CLKO is a 3.6864 MHz (50% duty)
output pin, one third of a system clock
(11.0592 MHz).
INT
In
Interrupt: Maskable Interrupt Input. The Interrupt
address is 14H.
l'iS'i'
In
Reset: Low-Ievel active system reset input. l'iS'i'
takes priority over any other operations. After
reset, the GPP and DSP start programs from
address O.
X1
In
X2
Out
Crystal oscillator (11.0592MHz ± 100 ppm)
connector.
Voo
Power Supply: +5 V ± 10%.
GND
Ground: GND (common).
Absolute Maximum Ratings
TA = 25·C
Supply voltage, Vee
-0.5 to +7.0 V
Input voltage, VI
-0.5 to Vee +0.5 V
Output voltage, Vo
-0.5to Voe +0.5 V
Operating temperature, TOPT
Storage temperature, TSTG
-10to +70·C
-86 to +150·C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
4
·c; Voe =
0V
Parameter
Symbol
Max
Unit
Xl,SCK
capacitance
Cq,
Min
20
pF
Input
capacitance
CI
20
pF
Output
capacitance
Co
20
pF
Conditions
fe = 1 MHz. All pins
are grounded except
measuring pins.
DC Characteristics
TA = -10 to +70 ·C; Vee = +5V ±10%; fose = 11.0592 MHz
Parameter
Symbol Min Typ
Input voltage,
low
VIL
-0.3
Max
0.8
Unit Conditions
V
Input voltage,
high
VIH
2.2
Voo
+ 0.3
V
XI Input voltage VILe
low
-0.3
0.8
V
XI Input voltage VIHC
high
2.2
Vee
+ 0.3
V
0.45
V
IOL = 2.0mA
V
IOH = - 400 ,.A
Output voltage
low
VOL
Output voltage,
high
VOH
Input leak .
current, low
ILIL
-10
I4A
VI = OV
Input leak
current, high
ILiH
10
I4A
VI =Veo
Output leak
current, low
ILOL
-10
I4A
Vo = 0.47V
Output leak
current, high
ILOH
10
I4A
Vo = Voo
Supply current
100
0.7
Voo
60
rnA
NEe
AC Characteristics
TA = -10 to +70 'C; Voo =
p.PD77810
+5 V ±10%
Parameter
Symbol
Xl cycle time
tC'IC
90
ns
Xl pulse width, high
tCCH
35
ns
Xl pulse width, low
tCCL
35
Xl rise time
tCR
10
ns
Xl'alltime
tCF
10
ns
CLKO cycle time
tCOCY
271
CLKO width, high
tCOCH
115
ns
CLKO width, low
tCOCL
115
ns
Address set time for RD
tAR
0
ns
Address hold time for RD
tRA
0
ns
RDwidth
tRR
170
ns
Data access time RD
tRo
Min
Typ
Max
Unit
110
ns
CL
CL
Access set time lor WR
tAW
0
ns
Address hold time for WR
tWA
0
ns
tww
150
ns
ns
50
tow
100
Data hold time WR
two
0
ns
RD and WR recovery time
tRV
180
ns
ADCK cycle time
tAoCY
1065
ns
ns
= loopF
= 20pF, RL = 2kll
lis
tAoCH
532
ADCK pulse width, low
tAoCL
532
DACK cycle time
toACY
1085
ns
DACK pulse width, high
tOACH
532
ns
DACK pulse width, low
tOACL
Serial 110 request delay time
toRO
50
Serial input set time for SCi<
toc
50
ns
Serial input hold time for SCi<
tco
30
ns
SOl EN set time lor SCi<
tsoc
50
ns
SOl EN hold time for ~
tcso
30
ns
Serial output delay time for SCi<
toCK
Serial output hold time lor SCi<
tHCK
Serial output float time for SCi<
tHZCK
Reset pulse width
tRST
10
INT pulse width
tiNT
8
high
532
ns
150
60
ns
ns
ns
0
60
.I
I
ns
0
ABCR pulse width,
(Note 4)
ns
tOF
Data set time WR
11.0592 MHz ± 100 ppm
ns
Data Iloat time for RD
WR pulse width
Conditions
ns
"s
tC'IC
Notes:
(1) SCK Includes Sl CK, ADCK, and DACK.
(2) Serial Input includes ADIN and Sil.
(3) Serial output Includes DAOT, SOl, and S02.
(4) Voltage at timing measuring point 1.0 V and 3.0 V.
5
NEe
"PD77810
Timing waveforms
Reset
ClocIc
1
~
t'"~J __
,.1
Interrupt
Relld Operation
AO-A3
cs
~
~
~
'" \=_'Mf'M-
---------- -----
eo."" -- - -- - -- -- - -
~""---=<
' ' 3----------
83ML-S838B
Write Operation
83ML-5S39B
6
1ttfEC
"PD77810
Timing Waveforms (cant)
RelldlWrite Cycle Timing
\'-------
:: ---~\'-----'1I+-:-----tRV-----~}'------83ML-S974B
AID Seriallnpul
III
ADST
ADSI
D/A Serial Output
DALD - - - -
DACK
~t_tDCK
DASO - - - - - -
-<-.)l
MSB
__
______-J)(~__
~ ~:=J<
L_SB__
~
7
1'tIEC
"PD77810
Timing waveforms (cont)
Serl."nput SI1
SI1
Serl., Output S01
S01RQ
S01
~-------->e:
___
r--_ _ _--.:I_IH_ZCK
)(~ LS_B__~t·
;......-----'
83ML-58448
Seri., Output S02
S02ST
S02
'---LS-B--..,f- ~
83ML-604OB
8
ttlEC
p.PD77810
Block Diagram
CLKO
X1
X2
ill
TxD
~
RxD
r~~---- GPP --~--~-~-""'"
(J,1COM78K!1)
RT
RBAUD
ADST
ADCK
SBAUD
STINT
STEXT
' - - - ' - 0 _ PE
PFO-PF2
~--INT
U
_ _ RST
ADIN-----~
S02ST
-------+----,
-VDD
-GND
SOl
83ML5820B
9
NEe
"PD77810
Figure 1 shows an overview of the ILPD7781O. Figure 2
shows the functional pin groups of the ILPD77810.
"PD77810 Functional Units
The ILPD77810 contains the following functional units:
DSP FUNCTIONAL DESCRIPTION
• DSP (p,PD77C25)
Figure 3 is the block diagram of the DSP. The DSP
consists of the following:
• GPP (p,COM78K11)
• Modem Function Block
- Tir,ners: WDTMR and TMR
- Control RAM
- Scrambler and Descrambler
- UART, SAC, and ASC
- Phase-Locked Loops: TxPLL and RxPLL
- Interface to AID and D/A
-Serial 1/0
- Parallel 1/0
• Multiplier
• ALU Peripheral
• Data Memory with Data ROM and RAM
• Instruction ROM
• Parallel Interface
• Serial Interface
• G-bus Interface
Figure 1. Overview of the pPD7781D
. . . . - - - - - , . - CLKO
TxD
XO
TxPLL
511
501
Port D
SlCK
SllEN
SOlEN
SOlRO
PortE
DSP
_
q
Port F
Ie:>
r-r--
PDO-PD7/DO -D7
PE
PFO-PD2
RST
--. Voo
_GND
S02ST
ADIN
S02
83ML·597SB
10
tt{EC
p.PD77810
Figure 2. Functional Pin Groups of tlJ!1 pPD77810
11.0592 MHz
XI
X2
Instruction ROM. The instructiDn ROM is a 2048 word x
24 bit mask programmable ROM that stores programs.
Its addressing is generated by the Program Counter
(PC).
+5 V
VDD
CLKO
RST
INT
Clock OUI
Interrupt
TxD
Parallel
Port
STEXT
STINT
SBAUD
RxD
RT
RBAUD
}
Receive Data
Interface
Control
Sil
SllEN
Program Counter [PC]. The program counter is an
11-bit binary counter that addresses the instruction
ROM. The PC is Incremented during every instruction
fetch cycle and instructions are read from the ROM
sequentially. When a jump or subroutine call instruction
is executed, the contents of the address field (NA field)
of the instruction are transferred to the PC. When a
return instruction is executed, the contents of the stack
register are transferred to the PC and when a interrupt is
issued, the fixed address 100H is transferred. During a
reset, the PC is set to the start address OOOH.
Stack. The 4 x 11 bit stack memory stores the return
address when a subroutine call instruction is executed
or an interrupt is issued. It has a four-level last-in first-out
(LIFO) memory. When a return instruction is executed,
the return address is read from the stack memory to the
PC.
SOl
SOlEN
SOIRO
SICK
DSP Internal Functions
Serial VO
Port
RAM. The 256 word x 16 bit RAM stores data. Its address
is set by the data pointer (DP). Data is transferred
between the RAM and internal data bus and also to the
AW P input. Data at the RAM address specified as OPe
=1 can be directly output to the K register.
83ML-5846A
Differences Between the "PD77810 and "PD7720
and "PD77C25 Families.
Data Pointer lOP]. The 8-bit data pointer specifies the
RAM address. The DP is connected to the. low-order
eight bits of the internal data bus and is transferred to
and from other registers via the bus.
The OSP was designed on the basis of the "P07720 and
"PD77C25 16-bit signal processor families, allowing the
"PD77810 to be compatible with these families at the
assembler source program level. Table 1 lists the differences between the "PD77810 and the "PD7720 and
"PD77C25 families.
11
III"·
:'11
".
NEe
"PD77810
Figure 3. DSP BlocIc Dllll/l'llm
Instruction
ROM
2048 <24
oata
S02ST
Multiplier
16X16 __31
RAM
256,< 16
INT
ADST
Stack
11 bits
<
4 levels
G-Bu.
FLAG A
FLAGB
ClK _
RST _
a a
v
a
a
s S c z va Va
B B
B B B B
1 a
1 a
S S
C Z
V
A A
A A A A
1
1
FF61H
FF62H
8
FF63H
83Ml·5834B
Tllble 1. Dlllerent:ell Between the pPD77B1D lind the pPD772D lind pPD77C25 Families
Member
Memory
Registers
"PD7720
"PD77C25
"PD77810 DSP
Instruction ROM
512 x23 bits
2048 x 24 bits
2048 x 24 bits
Data ROM
510 x 13 bits
1024 x 16 bits
1024 x 16 bits
RAM
126 x 16 bits
256 x 16 bits
256 x 16 bits
PC
9 bits
11 bits
11 bits
STACK
9 bits x 4 levels
11 bits x 4 levels
11 bits x 4 levels
RP
9 bits
10 bits
10 bits
RO
13 bits
16blta
16 bits
DP
7 bits
8 bits
8 bits
TRB
TRB
24 bits
(DPWM field, 4 bits)
24 bits
(DPWM field, 4 bits)
JDPLNO
JDPLNF
M8-MF
(DP modified)
JDPLNO
JDPLNF
M8·MF
(DP mOdified)
Additional register
Instruction length
Additional Instruction
12
23 bits
(DPWM field, 3 bits)
t-{EC
"PD77810
Table t. Differences Between the pPD778tO and the pPD7720 and pPD77C25 Rlmilies (conI)
Member
"PD77C25
"PD77810 DSP
DMAmode
Available
Available
Unavailable
Operation clock
Qnstruction cycle)
8.192 MHz
(244 ns)
8.192 MHz
(122 ns)
5.5296 MHz
(181 ns)
Other
• SR (status regi ster) bits 0
and 1 have been changed to
RxPLL decremental data
setting port output.
• SR (status register) bit 11 has
been changed to USFO.
The high-order four bits (D PH) of D P can be mod ified by
exclusive OR of four bits of the DPHIM field in an
instruction.
The low-order four bits (DPLl of DP are assigned to an
increment/decrement counter. The DP increments, decrements, or clears D PL field of an instruction.
Data ROM. The 1024 word x 16 bits mask ROM stores
fixed data; for example, digital filter coefficients and
data used to decode wlaw or A-law compressed nonlinear data. The data ROM address is set by the RP
register. ROM data is output to the internal data bus via
the RO register.
Addresses 0 and 1 that were not accessible to the
p.PD7720 family user are available for the p.PD77810.
ROM Pointer [RP]. The ROM pointer specifies the data
ROM address. RP consists of a 10-bit decrementcounter.
It can transfer data to and from the low-order ten bits of
the internal data. The RP register can be decremented by
the RPDCR bit of an instruction.
ROM Output Buffer [RO]. The ROM output buffer (RO)
is a 16-bit register that stores the ROM output data. RO
data is output to the internal data bus or directly output
to the L register.
Multiplier. The parallel multiplier using the Second Order Booth algorithms multiplies 16-bit data of two's
compliments notation. The result is a sign bit plus 30 bits
of data. The sign bit plus the low-order 15 bits are output
to the M register and the lower-order 15 bits without the
sign bit are output to the high-order of the N register. Bit
o of the N register is set to O. The multiplier inputs data
from the K and L registers.
K and L Registers. The K and L registers are 16-bit
registers that store the multiplier and multiplicand that
are to be input to the multiplier. The K register also inputs
RAM output data and the L register inputs data ROM
output data. Immediately after input data is set in the K
and L registers, it is input to the multiplier for processing.
M and N Registers. The M and N registers are multiplier
output registers. Of the multiplier result, the signed bit
and the high-order 15 bits are output to the M register
and the low-order 15 bits are output to the high-order of
the N register. Bit 0 of the N register is set to O. The M and
N register output is connected to the ALU P input.
ALU. AccA and Acc B. The ALU is a 16-bit arithmetic
and logical unit, which performs the following operations for its P and Q data inputs:
-OR
-AND
- XOR (Exclusive OR)
-SUB
-ADD
- Shift [AccA, AceB only]
- 1's complement [AceA, AceB only]
P input: RAM, internal data bus, M register, N register,
shift register, OOOOH
Q input: AecA, AceB
AccA and AccB are 16-bit registers that store the result
of the ALU operation. It can also input data from the
internal data bus. The ASL bit of an instruction specifies
whether the ALU output is input to AecA or AceB.
Register data can be output to the internal data bus or to
the shift register together with the ALU Q input.
13
-1.1.;
~"
N"EC
"PD77810
Shift. The shift register shifts 16-bits of data that is input
from AccA and AccB. One-bit right shifting. left shifting
on one-, two. and four bit basis. and 8-bit replacement
are available.
Flag A and Flag B Registers. Flag A is a register used to
store flags generated when AccA is selected. Similarly,
flag B is the register which stores flags when AccB is
selected. Table 2 shows the flags changed by the results
of ALU operations. The flag A and flag B register contain
flag bits as shown below.
F~GA ~IS_A_1~_S_A_O~__
CA__~~
__~_O_VA_1_1L-0_VM~1
F~GB ~IS_B_1~__
SM
__~_C_B~__Z_B~__
OV_B_1-L1_o_VM~1
CA and CB [Carry): CA and CB are flags that store the
carries that occur from the results of an operation. The
operations are SUB. ADD. SB B. ADC. DEC. and INC.
ZA and ZB [Zero): When data to be stored in the Acc is
o after an operation. excluding NOP. a 1 is set in the ZA
or ZB flag.
SAO and SBO [Sign 0): SAO and SBO store the MSB of the
data to be stored in Acc. when an operation excluding
NOP is executed.
OVAO and OVBO [Overflow 0): OVAO and OVBO store the
exclusive ORed results of carries that occur in AW bits
15 and 14 when SUB. ADD. SBB. ADC. DEC. or INC is
executed.
OVA1 and OVB1 [Overflow 1): OVA1 and OVB1 flags are
designed for effective overflow processing from the
results of up to three operations. The operations are
SUB. ADD. SB B. ADC. DEC, and INC.
SA1 and SB1 [Signt): SAt and SBt are used in conjunction with OVAt and OVBt flags. The flags are designed
for effective overflow processing and indicate the directionin which the overflow occurred.
14
Table 2. Rags Changed by Results of AW
Operations
Mnemonic
NOP
SA11
SB1
SAOI
SBO
CAl
ZAI
CB
ZB
OVA11
OVB1
OVAOI
OVBO
•
•
•
•
•
•
OR
x
AND
x
XOR
x
$
o
o
o
$
o
o
o
SUB
ADD
$
$
$
$
$
$
$
$
$
$
$
$
see
$
$
$
$
$
$
ADC
DEC
INC
$
$
$
$
$
$
$
$
$
$
o
o
o
$
$
$
$
$
$
$
$
$
$
$
$
CMP
x
$
o
$
SHR1
x
$
$
$
o
o
SHL1
SHL2
SHL4
XCHG
x
x
x
$
$
$
$
$
x
$
o
o
o
o
o
o
o
o
o
$
$
$
o
o
o
o
Symbols:
$ = The flag Is changed by the result of operation.
• = The flag remains unchanged.
o = Flag Is reset.
X = Undefined
Temporary Register [TR and TRB).TR and TRB are
16-bit general-purpose registers that can be used to
latch data temporarily.
Sign Register [SGN).The SGN register stores 8000H
when the SA1 flag is 0 and 7FFFH when it is 1. If an
overflow occurs, overflow correction can be performed
with only one instruction.
Status Register [SR).The SR register stores interface
information for the GPP. Internally, it is handled as a
16-bit register. Of the 16 bits of data, eight bits can be
read by the GPP by specifying the SFR address FF62H
orFF6H.
~EC
"PD77810
The SR register consists of 16-bits as shown below.
MSB
LSB
IRaM I USF2 I USF1 I DRS I USFO I DRC I SOC I SIC I
MSB
I 8
LSB
I
0
I
0
I
0
o
o
I RF1
I RFO I
RFO and RF 1: RFO and RF 1 correspond to output ports
RFO and RF 1. The values set in the bits are output
directly to the ports.
Bits RFO and RF1 specify the value to be set in the
decrementer in RxPLL of the modem function block.
EI [Enable Interrupt]: The EI bit specifies whether an
interrupt request input to the INT pin is enabled.
0= Disabled
1 = Enabled
SIC [SI Control]: The SIC bit specifies the length of serial
data to be input to the ADIN AID conversion input pin.
= Serial input data is 16 bits
1 = Serial input data is a bits
o
SOC [SO Control]: The SOC bit specifies the length of
serial data to be output to the SO serial output pin.
o = Serial output data is 16 bits
1 = Serial output data is a bits
DRC [DR Control]: The DRC bit sets the DR register
configuration for GPP as eight or 16 bits.
= The DR register is treated as a 16-bit register
1 = The DR register is treated as a a-bit register.
o
DRS [DR Status]: The DRS bit indicates the DR register
transfer status.
= End of data transfer
1 = Data is being transferred
o
When DRC
= 1, the DRS bit is always set to O.
USFO, USF1, and USF2 [User's Flag]: USFO, USF1, and
USF2 are flag bits which can be used freely. They are
used as a status bit in an interface with an external unit.
Request for Master [ROM]: ROM is a flag bit used to
transfer data between the DR register and GPP.
Data Register [DR]. DR is a 16-bit register used to
transfer data to and from the GPP. One of its sides is
connected to the a-bit bus and reads or writes data from
an external unit in two operations. Internally, it transfers
data in one operation (16 bits). When the DR register is
defined as an 8-bit register by the DRC bit, only the
low-order eight bits of DR can be transferred.
Serial Input Register [SI]. The SI register inputs serial
data from an external unit. Serial data is input to DSP
ADSI from the ADIN pin at the rising edge of the ADCK
serial clock, converted to parallel data by SI, and output
to the internal data bus with an instruction. Serial data
can be handled from either the LSB or MSB.
Serial Output Register [SO]. The SO register loads
parallel data to be output from the internal data bus,
converts to serial data, and outputs to an external unit.
Serial data can be handled from the either the LSB or
MSB. It is output at the rising edge of the ADCK serial
clock.
Interrupt. An interrupt is accepted with an instruction
from the GPP, when interrupt is enabled (EI bit of SR
register = 1). Program control jumps to the interrupt
address 100H and executes an interrupt process.
Reset [RST]. RST initializes the following by SFR
INTDSPO (0) of the GPP:
III
• PC
• Flags A and B
• SR register
• ADSI ASK flag and SO ACK flag
DSP Instructions
All DSP instructions consist of a single 24-bit word. Four
types of instructions are available and are distinguished
by the OP code which are the highest two bits of an
instruction.
• OP instruction:
Normal operations and transfer
• RT instruction:
Return instruction
• JP instruction:
Jump instructions including
unconditional jump, conditional
jump, and subroutine call
Immediate data load instruction
• LD instruction:
See table 3 for DSP instruction codes.
OP Instruction. The OP instruction has the following
functions:
• Performs operations specified by six fields and two
bits.
• Increments the current address set in the program
counter by one.
23
22
I0
0
15
IASL
21
14
16
ALU
1312
9
DPHiM
DPL
SRC
I
8
R
D6RI
4 3
7
I
2019
P·Select
0
I
DST
15
tt(EC
"PD77810
P-SELECT Field: The P-SELECT field selects ALU P
input. See table 4 for P-SELECT field specifications.
ALU Field: The ALU field specifies an ALU operation. See
table 5 for ALU field specifications.
ASL [Ace Selection] Bit: The ASL bit specifies whether
AccA or AccB is selected to the ALU input/output. See
table 6 for ASL bit specifications.
DPL Field: The DPL field specifies the operation of the loworder four bits of the data pointer. The changed DPL is valid
from the next instruction. See table 7 for DPL field specifications.
DPH/MP [DPH Modify] Field: The DPH/M field modifies the
high-order four bits of the data pointer. The OP instruction
performs exclusive OR of DPHfour bits with the value in the
field for each bit. The modified DPH value is valid from the
next instruction. See table 8 for DPH/M field specifications.
RPDCR [RP Decrement] Bit: The RPDCR bit specifies
whether RP data is decremented or not decremented. The
decremented value is valid from the next instruction. See
table 9 for RPDCR bit specifications.
SRC [Source] Field: The SCR field specifies the register
that outputs data to the internal data bus. See table 10 for
SCR field specifications.
DST [Destination] Field: The DST field specifies the register that inputs data from the internal data bus. This is
source data from the register specified in the SRC field.
See table 11 for DST field specifications.
RT Instruction. The RT instruction has the following
functions:
• Performs operations specified by six fields and two bits,
similar to the OP instruction. Therefore, RT has the
same function as that of the OP instruction.
• Sets the program counter as the stacked return address. See table 4 through table 11 for RT instruction
specifications.
23
22 21
01
15
I ASL
2019
ALU
13 12
7
OPH/M
B
I RPDCRI
43
SCR
I
22 21
10
I
0
OST
2 1
12 11
BRCH
o
NA
BRCH (Branch) Field: The BRCH field selects the instruction to be executed from unconditional jump, conditional
jump, and subroutine call. See table 12 for BRCH field
specifications.
NA (Next Address) Field: The NA field specifies the address of the jump destination. See table 13 for NA field
specifications.
LD Instruction. The LD instruction transfers imediate data
to the specified register.
23
I
22 21
11
I
6 5
o
4 3
ID
DST
10 (Immediate Data) Field: The 16-bit 10 field sets immediate data. Immediate data is transferred to the register
specified in the DST field. See table 14 for ID field specifications.
.
DST (Destination) Field: The DST field specifies the register where data in the 10 field is transferred. The DST field is
the same as that of the OP instruction. See table 11 for DST
field specifications.
Table 3.
DSP Instruction Codes
OPFleid
Instruction
OP
RT
23
22
o
o
o
Meening
Operation and transfer
Return
JP
o
Jump
LD
1.
Immediate data loading
Table 4.
P-Se/ect Field Specifications
P-Select Field
21
20
RAM
0
0
IDB
0
Mnemonic
9
OP L
23
16
P-Select
14
JP Instruction. The JP instruction includes three functions, such as unconditional jump, conditional jump, and
subroutine call.
M
N
ALU-P Input"
RAM
Internal data bus
0
Mregister
Nregister
Note:
• The input is valid when the ALU field specifies an instruction other than
Shift, INC Acc, DEC Acc , and Complement Acc.
16
NEe
Table 5.
I'PD77810
ALU Field Specifications
AlUFleld
Mnemonic
19
18
17
16
NOP
0
0
0
0
OR
0
0
0
AND
0
0
XOR
0
0
SUB
0
0
ADD
0
0
SBB
0
ADC
0
OR
(Ace>-(AcclV(P)
0
AND
(Accl-(Accl V (P)
Exclusive OR
(Accl-(Accl¥(P)
0
Subtract
(Accl-(Accl- (P)
0
DEC
0
0
INC
0
0
CMP
0
SHR1
0
0
0
0
SHL2
0
SHl4
0
(Accl-(Accl- (P) - (C)
Add with carry
(Accl-(Accl + (P) + (C)
Decrement Ace
(Accl-(Accl - 1
Increment Ace
(Ace>- (Accl + 1
Complement Ace (1 's complement)
(Ace>-(Accl
4-bit l-shift
= Carry flag not selected by the ASl bit.
ASL Bit Specifications
ASl Bit 15
ACCA
TableS.
DPHIM Field Specifications
Ace Selection
0
ACCB
DPL Field Specifications
DPLFleld
DPH/MField
Mnemonic
12
11
10
9
MO
0
0
0
0
Ml
0
0
0
M2
0
0
M3
0
0
13
Operation
M4
0
0
DPNOP
0
0
No operation
M5
0
0
DPINC
0
Increment DPL
M6
0
Decrement DPL
M7
0
ClearOPL
M8
0
0
M9
0
0
MA
0
MB
0
DPClR
(oP7 oPe oPs oP4 ) ...... (0 010)
(OP7 0Pe OPs OP4 )-¥-(0 1 00)
(OP7 0P6 OPs OP4)-¥(0 101)
(oP7 oP6 oPs oP4 ) ...... (0 1 10)
(oP7 oP6 DPs oP4 ) ...... (0 1 1 1)
0
(OP7 0P6 0Ps OP4 )-V-(1 000)
(oP7 oP6 DPs oP4)
...... (1
001)
0
(OP7 0P6 0Ps OP4 )"V-(1 010)
0
(OP7 0P6 0Ps OP4 )-¥-(1 1 00)
(OP7 0P6 0Ps OP4 )-¥(1 011)
0
MO
0
MF
0
0
MC
ME
(OP7 0Pe OPs OP4 )-¥-(0 0 0 0)
(OP7 0Pe OPs OP4 )"V-(0 01 1)
14
0
Exclusive OR
(OP7 0Pe OPs OP4 )-¥-(0 0 0 1)
0
Mnemonic
DPDEC
IIIlt
l-bitl-shift
8-bH exchange
Symbols:
P = Input selected in the P-Select field; C
Table 7.
(Accl-(Accl + (P)
Subtract with borrow
2-bit l-shift
0
XCHG
Table 6.
Add
1-bitR-shift
SHU
Mnemonic
Operation
No operation
(OP7 0P6 DPs OP4 )-¥-(1 1 01)
0
(OP7 OPe DPs OP4 ) "V- (1 1 1 0)
(oP7 oP6 oPs oP.) ...... (1 1 1 1)
17
t-IEC
I'PD77810
Table 9.
RPDCR Bit Specifications
Mnemonic
RPDCRBlt8
0
RPNOP
RPDEC
Table 10.
Table 11.
DST Field Specifications
No operation
Mnemonic
3
2
Decrement RP ,
@ NON
0
0
0
@ A
0
0
0
@ B
0
0
@ TR
0
0
Operation
SCR Field Specifications
SRCFleld
DSTFleld
0
7
6
5
4
Source Reglater
@ DP
0
0
NON,TRB(Note1)
0
0
0
0
TRB
@ RP
0
0
A
0
0
0
Acc A
@ DR
0
0
B
0
0
0
0
0
DP
0
0
RP
0
0
RO
0
SGN
0
DR
0
0
DRNF
0
0
SR
0
SIM
0
0
K
0
MEM
@ SR
@ SOL
0
0
DP
@ SaM
0
0
RPregister
@ K
0
0
ROregister
@ KLR
0
SGN register
@ KLM
0
0
DR register
@ L
0
DR register (Note 2)
@ TRB
0
SIL
L
Ace B
TR
0
0
0
DP(datapointer)
0
DR register
RPregister
SRregister
0
SO register serial out LSB (Note 1)
SO register serial out MSB (Note 2)
0
Kregister
KLR(Note3)
0
KLM(Note4)
0
TRB register
Lregister
SRregister
@ MEM
Notes:
(1) For 16·bit serial data, serial data is output from the LSB of the inter·
nal data bus sequentially.
(2) For 16·bit data, serial data is outputfrom the MSB olthe internal data
bus sequentially.
(3) The K register stores data on the internal data bus and the L register
stores the RO register (ROM) output.
(4) The L register stores data on the internal data bus and the K register
stores RAM data specified by DPe = 1 (DP7 , 1, DP5 , DP4 , DP3 , DP2 ,
DP" and DPa).
ADS I register (Note 4)
Lregister
RAM
Notes:
(1) TRB register data is output to the internal data bus even when NON
is specified,
(2) DR register data is output to the internal data bus but the ROM flag
is not set.
(3) For 16·bit data, the first serial input data is output to the highest bit
(MSB) and the last is output to the lowest bit (LSB),
(4) For 16·bit data, the first serial input data is output to the LSB of the
internal data bus and the last is output to the MSB,
18
0
ADSI register (Note 3)
Kregister
0
No register
Ace A (accumulator A)
Ace B (accumulator B)
TR (temporary register)
Mnemonic
TR
Destination Register
0
RAM
t-.'EC
Table 12.
"PD77810
BRCH Field Specifications
BRCHField*
Mnemonic
21
JMP
Conditions
0
0
0
CALL
JNCA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unconditional
0
0
0
0
0
0
CA ~ 0
0
0
CA ~ 1
0
CB ~ 0
0
CB ~ 1
JCA
0
0
0
0
0
JNCB
0
0
0
0
0
JCB
0
0
0
0
0
JNZA
0
0
0
0
0
JZA
0
0
0
0
0
0
JNZB
0
0
0
0
JZB
0
0
0
0
JNOVAO
0
0
0
0
0
JOVAO
0
0
0
0
0
JNOVBO
0
0
0
0
0
0
0
0
0
0
JNOVA1
0
0
0
0
JOVA1
0
0
0
0
JNOVB1
0
0
0
JOVB1
0
0
0
JNSAO
0
0
0
0
0
JSAO
0
0
0
0
0
JNSBO
0
0
0
0
JSBO
0
0
0
0
JNSA1
0
0
0
0
JSA1
0
0
0
0
JNSB1
0
0
0
0
0
ZA ~ 0
0
ZA ~ 1
0
ZB ~ 0
0
ZB ~ 1
0
OVAO
~
0
0
OVAO
~
1
0
OVBO~O
0
OVBO ~ 1
0
OVA1
~
0
0
OVA1
~
1
0
OVB1
~O
0
OVB1
~
0
SAO
0
SAO ~ 1
0
SBO
0
SBO ~ 1
0
SA1
~
0
SA1
~
1
0
0
SB1
~
0
0
SB1
~
1
0
DPL ~ 0
0
0
JOVBO
Unconditional
0
0
0
0
0
JSB1
0
0
JDPLO
0
0
0
0
0
JDPLNO
0
0
0
0
0
~
~
1
0
0
0
DPLI'O
J_D_P_L_F_________O
_______________O______________________
O_______O_______________
O_______
D_PL~~_F(HEX)
JDPLNF
0
0
0
JNSIAK
0
0
0
0
JSIAK
0
0
0
JNSOAK
0
0
0
JSOAK
0
0
0
JNROM
0
0
JROM
0
0
DPLI' F (HEX)
0
0
0
0
SIACK~O
0
SIACK~
0
SO ACK
~
0
0
SO ACK
~
1
0
ROM
~
0
0
ROM
~
1
1
Note:
• The BRCH field values not listed in this table are prohibited.
19
fttfEC
"PD77810
Table 13.
Memory Map
NA FIeld SpecifIcations
NAFleid
12
11
10
9
8
7
8
5
4
3
2
Jump Address
0
0
0
0
0
0
0
0
0
0
0
Address 0
The general purpose processor (GPP) has a 64 K byte
address space (16-bit address). Figure 5 shows memory
mapping of the GPP.
0
0
0
0
0
0
0
0
0
0
Address 1
The GPP address space consists of the following:
0
0
0
0
0
0
0
0
0
Address 2
• 16,384 byte internal program memory (INT-ROM) space.
0
• 192 byte internal data memory (INT-RAM) space.
Address 2047
• 256 byte special function register (SFR) space.
Table 14.
ID Field Specifications
IDFleid
21 20 19 18 17 18 15 14 13 12 11 10 9 8 7 8
o
0
0
0
0
0
0
0
0
0
o
0
0
0
0
0
0
0
0
o
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
HEX
0
0 0 0 0 0 0000
0
0
0 0 0 0 1 0001
0
0
0 0 0 1 0 0002
1
1
1 1 1 1 1 FFFF
GPP FUNCTIONAL DESCRIPTION
Figure 4 is the block diagram of the GPP.
Figure 4. GPP Block DIagram
GPP
(I1COM78K11)
INT· ROM
C·RAM
16K.8
16.8
8
8
83ML-!821A
20
Internal Program Memory Space [INT-ROM]. A 16,384
word x 8-bit mask programmable ROM occupies an area
of addresses from OOOOH to 3FFFH. The ROM can be used
for storing programs and data. The internal program memory space is allocated as follows:
Vector Table Area: The 22 bytes from OOOOH to 0015H
holds vectors for reset and interrupts. The low-order eight
bits of a 14-bit address are stored in an even-numbered
address and the high order six bits are stored in an oddnumbered address. See table 15 for the interrupt-vector
address.
NEe
Figure 5.
"PD77810
GPP Memory Mapping
,,
,,
,,
Address
OOOOH
'\.._-
----
OOOOH
-
RESET
0OO2H
INT-ROM
(Program
Memory
Space)
16384 x 8 Bits
NMIWD
0004H
0015H
Interrupt Vector
Address Table Area
0040H
CALLT Instruction
Table Area
64 X8 Bits
007FH
0080H
07FFH
0800H
Program Area
~
B
T
!> CALLF Instruction
ntryArea
OFFFH
1000H
3FFFH
4000H
FE3FH
No Built-In
Memory
Space
1\,
T
Program Area
\,--~!~~-.I.---------I,,
FE40H
\\\\~-------r-------.,
INT-RAM
(Data Memory Space)
192 x 8 Bits
FE40H
Data Memory Area
160 x 8 Bits
FEOFH
FEEOH
FEFFH
General -Purpose
Register Group
(4 Banks) 32 x 8 Bits
FEFFH
FFOOH
SFR
(Special Function
Register Area)
256 x 8 Bits
\
\\
,, ,,
_------'
\', \,. --------.....
'--------"r-------...,
FFFFH
\
FF90H
C-RAM Area
\'-:::~~_...L._ _1_6_X_8_B_it_S_
_J
83ML-5B22B
21
t-{EC
"PD77810
Table 15.
Interrupt Vector Address
Interrupt Source
Interrupt Vector Address
Flag Name
OOOOH
0002H
Condition
Reset (RESET) input
NMIWD
Watch dog timer
0004H
1ST
STINT rising edge
0006H
IRT
RT rising edge
0008H
IIU
Data was input to URTI, or a break signal was detected.
OOOAH
IOU
OOOCH
IFIFO
Data was input to URTO
Data was read from FIFO, or four levels of FIFO data were output.
OOOEH
IAT
TMRAisO
0010H
18T
TMR8isO
0012H
IS1
DataisinputtoSI1
0014H
INT
Interrupt (INT) input
CAllT Instruction Table Area: A 64-byte area from 0040H
to 007FH stores a one-byte call instruction (CAllT) subroutine entry address.
CAllF Instruction Entry Area: An area from 0800H to
OFFFH stores a two-byte call instruction (CAllF) which
calls a subroutine directly.
Internal Data Memory Space (INT-RAM). A memory
area from FE40H to FEFFH is allocated to a 192-byte RAM.
In the RAM's 32-byte area from FEEOH to FEFFH a fourbank general-purpose register group is mapped. Data
memory is also used as stack memory.
Special Function Register (SFR) Space, A 61-byte area
within a 256- byte area from FFOOH to FFFFH stores a special function register (SFR) of on-chip peripheral hardware.
The addresses not mapped with SFR are not accessible.
C-RAM is also mapped within the SFR space.· Note that it
is possible for C-RAM to be externally accessible. See liD
port and C-RAM.
C- RAM which is able to write externally in the slave mode,
is also allocated in the SFR space.
Registers
Program Counter [PC]. the program counter is a 14-bit
binary counter containing address information of the next
program to be executed. It is incremented automatically
depending on the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate
data or the contents of a register is set in the counter.
22
When the RESET signal is input, the PC is initialized with
the data at addresses OOOOH and 0001 H in INT -ROM; the
data at address OOOOH are placed in the low-order eight
bits of the PC, and the low-order six bits of the data at
0001 H are placed in the high-order six bits of the PC. See
Figure 6.
Figure 6. Program Counter Configuration
I
pclpc 131pc 121pc 111pc 101 PC g PC 81
PCt-I
pcl PC 71 PC 61 PC 51 pC41 pC31 pC21 PC 11 PC 01
PCl
Program Status Word [PSW]. The program status word is
an 8-bit register consisting of flags. See Figure 7. It can be
read or written on an eight-bit basis. The flags area is
operated by bit operation instructions. The PSW data is
saved into a stack area when an interrupt request is issued
or a PUSH instruction is executed and is restored with a
RETI or POP instruction.
When RESET is input, all flags are cleared and PSWisset
to02H.
t-iEC
Figure 7.
pswi
"PD77810
Program Status Word Configuration
7
6
IE
Z
I
5
4
RBs11 AC
3
2
0
RBsol
0
CY
I
Auxiliary Carry Flag [AC]: The auxiliary carry flag is set to 1
when a bit 3 carry occurs atthe end of an operation or when
a bit 3 borrow occurs. Otherwise it is reset to O. The AC flag
is used when a BCD correct instruction is executed.
Zero Flag [2]: The zero flag is setto 1 when the result of an
operation isO.lfthe result of an operation is not 0, theZflag
is reset to O. The Z flag can be tested with a conditional
branch instruction.
Note: Bit 2 and Bit 1 must be set as follows:
Bit2 =0
Bit 1 = 1
Interrupt Request Enable Flag [IE]: The interrupt request
enable flag controls whether a CPU interrupt request
(maskable vector interrupt) is accepted. When the flag is
set to 0, the processor is set to the 01 state and all interrupts except a non-maskable interrupt (watch dog timer
interrupt) are disabled. When the flag is set to 1, the processor is set to the EI state and interrupt requests are controlled by the interrupt mask flag for each interrupt request.
The EI flag is set to 1 when an EI instruction is executed
and reset to 0 when a 01 instruction is executed or an interrupt is accepted.
Carry Flag ICY]: The carry flag (CY) stores overflow or
underflow when arithmetic instructions are executed. The
flag stores the value shifted out when a shift rotate instruction is executed and performs as a bit accumulator when a
bit operation instruction is executed.
Register Bank Select Flags [RBSo and RBS1]: RBSo and
RBS1 are used to select one ofthe four register banks. See
table 16.
Table 16.
Register Sank Selection
o
o
RBSo
Register Bank
o
Register bank 0
o
Register bank 2
Stack Pointer [SP]. The stack pointer is an 8-bit register
used to retain the low-order eight bits ofthe return address
in a stack area (LIFO form). The high-order eight bits of an
address in this area are always FEH. The stack memory is
allocated to any area in data memory (FE40H to FEFFH).
When the SP value is set SP data is not stored from OOH to
3FH. SP data is decremented when a write (save) operation is performed to stack memory and incremented when
data is read (restored) from stack memory. SP is accessible with a dedicated instruction. SP data is not acted upon
when RESET is input. RESET must initialize the SP before
a subroutine call. See Figures 8, 9, and 10.
Register bank 1
Register bank 3
Figure 8. Stack Pointer Configuration
I
7
6
543
2
1
0
I I
SP SP 71 SP 61 SP 51 SP 41 SP 31 SP 21 SP 1 SP 0
Figure 9. Data Saved to the Stack Memory
••
SP 2
SP 1
SP~
PUSH Instruction
CALL, CALLF, and
CALLT Instructions
Interrupt
Stack Memory
Stack Memory
Stack Memory
PC7-PCO
PC7-PCO
Low order of
register pair
High order of
register pair
••
SP 2
SP 1
SP~
00
I PC13-PC8
I
00
I PC13-PC8
I
PSW
23
III. '
fttlEC
#,PD77810
Figure 10. Data Restored From the Stack Memory
SP~
t
SP+ 1
t
SP+2
POP Instruction
RET Instruction
RETllnstruction
Stack Memory
Stack Memory
Stack Memory
Low order of
register pair
High order of
register pair
SP~
t
SP+ 1
t
00
t
SP+1
t
SP+2
t
SP+3
I PC 13-PC8
I
SP+2
General-Purpose Registers. General-purpose registers
are mapped to special addresses in the INT-RAM (FEEOH
to FEFFH). The registers consist of four bank registers;
each having eight a-bit registers (X, A, e, B, E, D, L, and
H). The actual register bank in operation is determinedby
RBSO and RBS1 of PSW.
Normally, general-purpose registers are operated on an
eight-bit basis. These can also be operated on a 16-bit
basis as a pair of a-bit registers (AX, Be, DE, and HL).See
Figure 11.
.
Registers have functional names (X, A, e, B, E, D, L, H, AX,
Be, DE, and HL) as well as absolute names (RO to R7 and
RPO to RP3). See table 17 for the relationship between
functional names and absolute names.
Table 17.
The GPP has four register banks and the user can use
different register banks for efficient programming of normal
and interrupt operations.
PC7-PCO
00
I PC 13-PC8
I
PSW
Relationship Between Functional Names
and Absolute Names
Functional Name
Absolute Name
X
RD
R1
R2
R3
R4
RS
R6
R7
RPD
RP1
RP2
RP3
A
C
B
E
D
L
H
AX
BC
The general-purpose register area is accessible by
specifying a normal data memory address. It does not
have to be used as a register area.
24
SP~
PC7·PCO
DE
HL
t-{EC
"PD77810
Figure 11. General·Purpose Register Configuration
8-b~
Register
Processing
FEEOH
A EIH
B E3H
C E2H
E E4H
H E7H
L E6H
A E9H
X E8H
B
EBH
D EDH
C EAH
H EHF
L EEH
A F1H
X FOH
E ECH
B F3H
C F2H
D F5H
E F4H
H F7H
A F9H
X F8H
B FBH
C FAH
H FFH
t
X EOH
D E5H
DFOH
FEFFH
16-bit Register
Pair Processing
L F6H
E FCH
L FEH
Register Bank 3
(RBS 1, 0 = 11)
•
· · . ·. ·····t. ···· . ·. ·
Register Bank 2
(RBS 1, 0 = 10)
. . . . . . .t. . . . . . .
t
,
Register Bank 1
(RBS 1, 0 = 01)
............. ........... .
Register Bank 0
(RBS 1, 0 = 00)
•
............................
tv<
EOH
BC
E2H
DE
E4H
HL
E6H
tv<
E8H
BC
EAH
DE
ECH
HL
EEH
tv<
FOH
BC
F2H
DE
F4H
HL
F6H
tv<
F8H
BC
FAH
DE
FCH
HL
FEH
•
Special Function Register [SFR]
The special function registers are assigned to special functions like the built-in peripheral hardware mode register
and control registers. They are mapped to 61 bytes in the
256-byte area from FFOOH to FFFFH.
Note that only addresses assigned for the SFR are access·
ible. If an address not assigned for the SFR is accessed,
the processor may malfunction.
Table 18 lists the SFRs.
SFRs are instruction operands which can be used for
transfer instructions, bit operation instructions, and arith·
metic instructions.
25
NEe
#,PD77810
Table 18.
Special Function Register (SFR) Ust
Mnemonic
R/W
Status
atReaet
Port mode register (PTMR)
PTMR
R/W
3FH
FF28H (8-bits)
Port C mode register (PCMR)
PCMR
7FH
FF29H (8-bits)
Port 0 mode register (POMR)
FF2AH (8-bits)
Functional Area
Port
Interrupt
SFRName
POMR
FFH
Port A (PORTA) (Note 1)
PA
OOH
FF2CH (8-bits)
Port B (PORTB) (Note 1)
PB
OOH
FF20H (8-bits)
Port C (PORTC) (Note 1)
PC
OOH
FF2EH (low-order 7 -bits)
Port 0 (PORTO) (Note 1)
PO
OOH
FF2FH (8-bits)
Port E (PORTE)
PE
R
OH
FF57H (low-order 1-bit)
Port F (PORTF)
PF
R/W
OH
FF5CH (low-order 3-bits)
Interrupt request flag register (IFO)
IFO
R/W
OOH
OOH
FFEOH (1S-bits)
FFE1H
FFH
FFH
FFE4H (1S-bits)
FFE5H
Interrupt mask register (MKO)
Scrambler/descrambler
Transmit PLLlreceive PLL
Serial communication
interface ASC, SAC, UART
AID, O/A interface
Serial 1/0
Timer
MKO
OSP interrupt register (INTOSP) (Note 8)
INTDSP
Mode register (SCRMR)
SCRMR
Scrambler port (SCR) (Note 3)
SCR
Oescrambler port (DSC) (Note 3)
DSC
OH
R/W
OOH
Undefined
FF64H (low-order 2-bits)
, FF40H (8-bits)
FF41 H (low-order 1-bit)
FF42H (low-order 1-bit)
Scrambler control register (SCRM)
SCRM
OH
FFS5H (low-order 4-bits)
Descrambler control register (DSCM)
DSCM
OH
FFSSH (low-order 3-bits)
PPL mode register 1 (PLLMR1)
PLLMR1
PPL mode register 2 (PLLMR2)
PLLMR2
SBAUO, RBAUO status register (BAUOSR)
BAUDSR
ASMR
Synchronousl asynchronous mode register (ASMR)
UART mode register (URTMR)
URTMR
UARTstatus register (URTSR) (Note 4)
URTSR
R/W
OOH
FF44H (8-bits)
33H
FF7EH (8-bits)
R
OH
FF45H (low-order 2-bits)
R/W
OOH
FF49H (8-bits)
OOH
FF4AH (low-order7-bits)
OH
FF4BH (low-order4-bits)
R
ASC register (ASCR)
ASCR
SAC register (SACR)
SACR
URO register (URO)
URO
URI register (URI)
URI
R
D/A mode register (OAMR)
OAMR
R/W
Undefined
FIFO read address (FFRA)
FIFO write address (FFWA)
R/W
FF4CH (8-bits)
FF40H (8-bits)
FF3EH (8-bits)
FF3FH (8-bits)
OOH
FF4EH (low-orderS-bits)
FFRW
OH
FF4FH (high-order3-bits)
FFRW
OH
FF4FH (low-order 3-bits)
FIFO (FIFO) (Note 5)
FIFO
Undefined
FF54H (1S-bits)
FF55H
Status register (S1 SR)
S1SR
R
OH
FF5SH (2-bits)
Serial input port 1 (SI1)
SI1
R/W
OOOOH
FF58H (1S-bits)
FF59H
Serial output port 1 (S01)
S01
OOOOH
FF5AH (1S-bits)
FF5BH
R/W
Timer mode register (TMMR) (Note S)
TMMR
OOH
FF50H (8-bits)
Timer A (TMRA)
TMRA
FFH
FF5EH (8-bits)
WOMSR
OOH
FFSOH (8-bits)
Watch dog timer control register (WOMSR) (Note 7)
26
Address
~EC
Table 18.
I'PD77810
Special Function Register (SFR) List (cont)
Mnemonic
R/W
Status
at Reset
Data register (DR) (Note 2)
DR
R/W
Undefined
FF60H (16-bits)
FF61H
Status register (SR)
SR
R
OOH
FF62H (8·bits)
FF63H
R/W
Undefined
FF90H (8-bits)
FF9FH (8·bits)
SFRName
Functional Area
DSP interface
C-RAM
Control RAM (C-RAM)
Notes:
(1) Write operation is invalid when the register is used as an input port.
(2) The DSP status (RQM flag) is changed by a Read/Write signal.
(3) The shift register of the scrambler/descrambler is shifted one bit by a
Write signal to the SCR and DSC.
(4) URTSR is reset after it is read.
(5) The FFWA write address is incremented by a Write signal to the FIFO.
(6) This register is reset to 0 by TMRA.
(7) The write operation is performed with special instructions (MOV
WDMSR, #byte).
(8) INTDSP is reset six clocks after it is set to 1.
(9) The 16-bit SFR registers must be accessed one byte at a time. For
high byte access the symbol H is appended to the SFR mnemonic
and for the low byte access the symbol L is used.
Address
interrupt mask register [MKOj. The interrupt source state
can be checked by the interrupt request flag register [IFOj.
Maskable vector interrupt operations are explained below.
The interrupt enable state indicates thatthe IE bit of PSW is
1 and the corresponding bit of the interrupt mask register
MKOisO.
• When an interrupt source is detected, the corresponding bit of IFO is set.
• When interrupt processing starts, the corresponding bit
of IFO is reset.
• When an interrupt source is detected while interrupt is
enabled, interrupt processing starts.
Interrupt Functions
The GPP has one non-maskable interrupt and nine maskable vector interrupts.
The vector interrupt saves status information (PC and
PSW information) of the program being executed. The
status information is stored in memory specified by the
stack pointer when an interrupt request is accepted. Then
data is stored at the address of the interrupt request (vector
table address) in the PC as vector address information and
starts the interrupt service program. Control is returned
from the interrupt service program by transferring the program counter value and status information from stack
memory to the PC and PSW with the RETI instruction.
• If two or more interrupt sources are detected, priority is
given to the lowest interrupt vector address.
• If an interrupt request is detected during interrupt processing, it is nested when interrupt is enabled.
The GPP has a total of ten interrupt request sources; nine
maskable interrupts and one non-maskable interrupt. Of
the ten sources the maskable interrupt request sources are
listed in table 19.
Table 20 lists the interrupt vector table addresses. Table 21
lists the IFO and MKO SFR addresses.
Maskable Vector Interrupt. Maskable vector interrupt
processing indicates when an interrupt is enabled by the
Table 19.
Maskable Interrupt Request Sources
Interrupt Source
Interrupt Signal
Condition
TxPLL
1ST
PxPLL
IRT
RT rising edge
TIMRA
IAT
TimerTMRA is set to 0
IBT
TimerTMRBissettoO
TIMRB
FIFO
IFIFO
STINT rising edge
Data was read from FIFO. Or. four levels of FIFO data were outputfrom FIFO.
SI1
IS1
DatawasinputtoSll
UART
IIU
Data was inputto URTI. Or, a break signal was detected.
External
IOU
URTO data was output
INT
External interrupt
27
t-IEC
"PD77810
Table 20.
Interrupt
Requestlype
Interrupt Vector Table Address
Maskable
Table 21.
IFO
MKO
Interrupt Request Signal
Corresponding Bit
Corresponding Bit
15T
0
0
0006H
2
IRT
0004H
Non-maskable
Mnemonic
Default
Priorities
Vector
Table Address
0008H
3
IIU
2
2
OOOAH
4
IOU
3
3
OOOCH
5
IFIFO
4
4
OOOEH
6
IAT
5
5
0010H
7
IBT
6
6
0012H
8
151
7
7
0014H
9
INT.
8
8
0OO2H
0
Watch dog timer interrupt
IFO and MKO, SFR Addresses
SFR Address
Function
IFO
FFEO, FFEl H
Interrupt request Hag register (16-bits)
MKO
FFE4, FFE5H
Interrupt mask register (16-bits)
Interrupt Request Flag Register [FO): The interrupt request
flag register is a 16-bit register. It consists of the interrupt
source flags listed in table 20. :The flags in the interrupt
request flag register are set when a corresponding interrupt source is detected and reset when it is processed.
Flags are reset to 0 when RST is input. The low-order
seven bits are always O.
Interrupt Mask Register [MKO): The interrupt mask register
is a 16-bit register. It sets even if interrupt is enabled when
an interrupt source flag is set. See table 20 for interrupt
source flags. The flags of the MKO are set to 0 to enable
interrupt and set to 1 to disable interrupt.
The low-order seven bits are always 1. Flags are initialized
to 1 when RST is input.
Vector Interrupt Processing: The vector interrupt processing sequence is shown in Figure 12. It is automatically
executed internally. The latency in the interrupt process
routine gaining control is 18 clocks (approximately 3.3 IJ.s).
Figure 12. Vector Interrupt Operation
r-
Execution of instruction when an
interrupt source is detected.
Interrupt Process Routine
Automatic
Saving
r--18CIOCks--+j
Set
Reset
Interrupt
Request
Flag
(lFO)
Interrupt Request Detected
28
:
I
I
RETI
Execution
Program
Execution
NEe
I'PD77810
Non-Maskable Interrupt. The processor has a watch dog
timer interrupt function as a non-maskable interrupt. This
interrupt is executed immediately when a source is detected.
Interrupt execution does not affect the IE flag of PSW.
Register Addressing: Addresses a general-purpose register mapped at a specific address in data memory. The
general-purpose register in the register bank specified by
RBSO and RBS1 flags in the PSW is registered.
Interrupt to the DSP. The GPP has reset and interrupt
functions to the DSP. These functions are specified by the
2-bit INTDSP register. INTDSP is initialized to 0 when
Reset is input. See table 22 and table 23.
Coding example follows:
Table 22.
XCH A,r
To specify the C register as r, code as follows:
XCH A,C
INTDSP Function
INTDSP
Function
INTDSP
(bill)
When INTDSP is set to 1 an interrupt request is issued to
the DSP. After being issued INTDSP resets automatically.
INTDSO
(bit 0)
When INTDSO is a 1. DSP is reset
Table 23.
INTDSP SFR Address
Short and Direct Addressing: Addresses an area from
FE40H to FEFFH in the internal data memory and an area
from FFOOH to FF1 FH in the SFR. To access 16-bit data,
2-byte data specified by continuous even-numbered and
odd-numbered addresses is specified.
Coding example follows:
Mnemonic
SFRAddreSB
INTDSP
FF64H
ADDC saddr, A
Function
•
To specify address FE50H as saddr, code as follows:
DSP reset/interrupt request register
AD DC OFE50H, A
SFR Addressing: Addresses a special function register
(SFR) mapped to the SFR area (FFOOH to FFFH).
Addressing
GPP addressing includes the following:
Coding example follows:
• Data memory addressing
MOV A, sfr
• Instruction addressing
Data Memory Addressing. Figure 13 shows the data memory map, SFR memory map, and applicable addressing.
To specify the PTMR register as sfr, code as follows:
MOV A,PTMR
Figure 13. Data Memory Map and Addressing
FE40H
Internal RAM
FEEOH
FEFFH
FFOOH
FF1FH
FF20H
---------General Purpose
Register Group
Short and
Direct
Addressing
t
Stack
AddrlSSing
Register
Addressing
t
Register
Indirect
Addressing
([HL]).
Indexed
Addressing
----------SFRArea
ReJster
Indirect
Addressing
([01. [El. [E+]).
SFR Addressing
FFFFH
Note:
Register Indirect addressing (HL) and indexed addressing. addresses the built-in ROM. These are applicable to the read table data.
83ML-5824B
29
<.
,/
ttlEC
"PD77810
Register Indirect Addressing: Addresses data memory
indirectly by the contents of the register stored in the
operand. The register in the register bank specified by the
RBSO and RBS1 flags in the PSW is specified. Only when
the E register is specified with the MOV instruction are the
contents of the register automatically incremented by one
after the instruction is executed. In this case, the operand is
coded as [E +]. Register indirect addressing using the HL
register pair can address the overall space including the
internal ROM.
Coding example follows:
SUB A, [r4)
To specify the E register a r4, code as follows:
SUB A, [E)
Indexed Addressing: Addresses data as the result of an
addition of 16-bit immediate data and 8-bit register data.
The 8-bit register is in the register bank specified by the
RBSO and RBS1 flags of the PSW. This technique can
address the overall space including the internal ROM.
Coding example follows:
Relative addressing is applicable for the BR S addr 14
instruction and a branch instruction.
Immediate Addressing: Immediate data in an instruction
word is transferred to the PC and program control branches
to the address set in the PC.
Immediate addressing is applicable for the CALL laddr14,
BR laddr14, and CALLF laddr11 instructions. For the
CALLF laddr11 instruction, program control branches to
the fixed area of the low-order 2-bit address.
Table Indirect Addressing: The contents of a specific location table (branch destination address) addressed by
immediate data of the low-order five bits of an instruction
code are transferred to the PC and program control
branches to the address set in PC.
Table indirect addressing is applicable for the CALLT
[addr5) instruction.
Register Addressing: The contents of a register pair (RP3
to RPO) specified by an instruction word is transferred to
the PC and program control branches to the address set
in PC. Register addressing is applicable for the BR rp
instruction.
MOV A, word [r1)
To specify FEAOH as word and the B register as r1, code
as follows:
MOV A, OFEAOH [B]
Stack Indirect Addressing: Addresses internal memory
data (FE40H to FEFFH) indirectly by the contents of the
stack pointer (SP).
This technique is applicable when executing PUSH and
POP instructions, save or restore operations by interrupt
processing, and subroutine call and return.
Coding example follows:
PUSH rp
To specify the DE register pair as rp, code as follows:
PUSH DE
Instruction Addressing. The instruction address is determined by the program counter (PC) value. Normally, the
PC is automatically incremented by one (for one byte)
depending on the number of bytes to be fetched every time
an instruction is executed. If a branch instruction is executed, branch destination information is set in the PC by
distinct addressing, as shown below:
Relative Addressing: The first address of a subsequent
instruction is added by 8-bit immediate data (displacement
value: jdisp) of an instruction code and transferred to the
PC. Then program control branches to the address set in
the PC. The displacement value is handled as signed two's
complements (-128 to + 128) and bit 7 is used as a sign bit.
30
INSTRUCTION SET
Tables 24 through 27 and figure 14 define the operands,
symbols, and codes that appear in table 28. Table 28
lists the instruction encodings and shows all the legitimate combinations of operands. The instruction set
terminology is as follows:
Operands and Coding Requirements: In the operand field
of an instruction, operands are accepted according to their
value. An operand having two or more values can have
only one selected. Uppercase letters and symbols like +,
#, !, $, I, and [ ) are keywords and must be written as they
are presented. The symbols have the following meanings:
+
#
$
1
[I
Automatic increment
Immediate data
Absolute address
Relative address
Bit reverse
Indirect addressing
For immediate data, write an appropriate numeric value or
label. When a label is used, it must be defined elsewhere.
The clock column symbols are as follows:
• n in the clock column of a shift rotate instruction indicates
the number of bits to be shifted.
• The value enclosed in ( ) in the clock column of a conditional branch instruction indicates the number of
clocks when program control does not branch.
fttIEC
• When accessing SFR by register indirect addressing
([HL]) and indexed addressing (word [r1]), the number
of clocks is set to the one shown after a slash (/) in the
column.
• If the result of word +r1 overflows in indexed addressing, the number of clocks is increased to the value
enclosed in ( ).
Table 24.
Operand Values
I'PD77810
Table 25.
Abbreviations (cont)
Identifier
Description
RPOto RP3
Register pair 0 to register pair3 (absolute names)
PC
Program counter
SP
Stack pointer
PSW
Program status word
CY
Carry flag
AC
Auxiliary carry flag
z
Zero flag
RBSOtoRBSl
Register bank select flag
Operand
Value
r
rl
r2
r3
r4
rp
x (RO), A (Rl), C (R2), B (R3), E (R4), 0 (RS), L (RS), H (R7)
A,B
B,C
D,E,E+
D,E
AX (RPO), BC (RP1), DE (RP2), HL (RP3)
IE
Interrupt request enable flag
WDMSR
Watch dog timer control register
( )
sfr
sfrp
Special function register abbreviation (see table lS)
Special function register abbreviation (lS-bitoperable
register, see table lS)
Memory data indicated by the address in ( ) or register
data
xxH
Hexadecimal number
saddr
saddrp
FE40H to FEl FH immediate data or label
FE40H to FEl FH immediate data (bit 0 = 0) or label (for
lS-bit data)
!addr14
OOOOH to 3FFFH immediate data or label: immediate
addressing
OOOOH to 1FFFH immediate data or label: relative
addressing
800H to FFFH immediate data or label
40H to 7EH immediate data (bit 0 = 0) or label
$addr13
addr11
addrS
word
byte
bit
n
lS-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bitimmediatedata(Ot07)
RBn
RBOtoRB3
Note:
rand rp can be coded with a functional name (X, A, C, B, E, 0, L, H, AX,
BC, DE, and HL) as well as an absolute name (ROtoR7and RPOto RP3).
Table 25.
Abbreviations
Identifier
Description
A
A register (8-bit accumulator)
X
X register
B
Bregister
C
Cregister
o
o register
E
Eregister
H
Hregister
L
Lregister
ROtoR7
Register Oto register 7 (absolute names)
AX
Register pair AX (lS-bit accumulator)
BC
Register pair BC
DE
Register pair DE
HL
Register pair HL
High-order and low-order 8-bits of 16-bit register pair
Table 26.
Flag Symbols
Symbol
Description
(Blank)
Flag not affected
o
Data was cleared to 0
x
Data was set or cleared according to the result of operation
R
The previous saved value was restored
Table 27.
Instruction Code Field Identifiers
Data was set to 1
Identifier
Description
Bn
Immediate data corresponding to bits
Nn
Immediate data corresponding to n
Data
8-bit immediate data corresponding to bytes
Low/high/byte
16-bit immediate data corresponding to words
Saddr-offset
Low-order 8-bit offset data of 16-bit address corresponding to saddr
Sfr-offset
Low-order S-bit offset data of 16-bit address of
special function register (sfr)
Low/high offset
16-bit offset data corresponding to words in
indexed addressing
Low/high addr
16-bit immediate data corresponding to addr 14
jdisp
Signed two's complements of the difference between the first address of the following instruction
and the branch destination address (S-bits)
fa
Low-order l1-bits of immediate data corresponding to addr 11
ta
Low-order S-bits of immediate data corresponding
to (addrS x 1/2)
31
•
NEe
#,PD77810
Figure 14. Operand Register Selection Codes
rl
r2
R5
Register
R2
Rl
RO
R6
0
R5
0
R4
0
RO
X
0
0
1
RI
A
0
I
0
R2
C
0
I
I
R3
B
RI
RO
I
0
0
R4
E
0
I
0
1
R5
1
I
0
R6
I
I
I
R7
H
PI
Po
P2
PI
P6
P5
0
0
Register
RO
Register
0
A
0
C
1
B
1
B
r3
r4
Register
RI
0
E
~
D
I
E+
r--:L
R4
Register
0
L
I
0
D
0
E
I
0
rp
Register-Pair
RPO
AX
BC
0
I
RPI
I
0
RP2
DE
I
I
RP3
HL
Example of Machine Code and Operands: When both the
first and second operands are arranged as registers or
register pairs in the operand field, the instruction code is
structured as follows:
Of a register byte, the high-order four bits are used to
specify the second operand and the low-order four bits are
used to specify the first operand.
MOV r, r
To specify the first operand as A register and the second
operand as L register, code as follows:
MOV A,L
In this case, the instruction code is set as shown below.
Instruction
Code
MSB
I° I ° I ,
Instruction
Code
MSB
LSB
0
0
0
0
,..-JL....--..l._,..-J_._Z2-..1._',.....J. Code Specifies
L--.L-.-....I-_..L-
LSB
A Register
L-_ _ _ _ _ _ _ _ _ Code Specifies
83ML·6142A
L Register
83ML·6141A
32
NEe
Table 28.
"PD77810
Instruction Encodlngs
Instruction Code
81/83
Mnemonic Operand
Flags
82/84
8ytes
Clocks
ZACCY
Operation
8·Blt Data Transfer Instructions
MOV
r,#byte
1011 1R2R1Ro
saddr, #byte
0011 1010
~
Data
2
2
r
Saddr·offset
3
3
(saddr)
byte
Sir-offset
3
5
sir
ORaRs~ OR2R1Ro
2
~
byte
Data
sir, #byte (Note 1)
00101011
~
byte
Data
r,r
0010 0100
A,r
1101 0~R1Ro
2
r~r
2
A~r
A,saddr
0010 0000
Saddr-offset
2
2
A~
saddr,A
0010 0010
Saddr·offset
2
3
(saddr)
A,slr
0001 0000
Slr·offset
2
4
A~slr
slr,A
0001 0010
Sir-offset
2
5
sfr~A
A, [r3] (Note 2)
0111 11R1Ro
5/6
A
[r3], A (Note 2)
0111 10R1Ro
5/6
(FEOOH + r3)
A,[HL)
0101 1101
5/7
A~(HL)
[HL],A
0101 0101
A, word [r1]
0000 1010
00Rs1 0000
Low offset
High offset
0000 1010
10R5 1 0000
Low offset
High offset
00101011
1111 1110
word [r1],A
PSW,#byte
5/7
~
(saddr)
~A
•
(FEOOH + r3) r3=40H-FFH
~
A r3=40H-FFH
(HL)~A
~
4
7(8)1
9(10)
A
(word + r1)
4
7(8)1
9(10)
(word + r1)
3
5
PSW~
~
A
byte
X X X
Data
XCH
PSW, A
0001 0010
1111 1110
2
5
PSW~A
A,PSW
0001 0000
1111 1110
2
4
A~PSW
4
A ...... r
A,r
1101 1R2R1Ro
A,saddr
0010 0001
Saddr·offset
2
4
A ...... (saddr)
A,slr
0000 0001
00100001
3
10
A ...... sir
A,[r4)
0111 1R211
8
A ...... (FEOOH + r4) r4=40H-FFH
X X X
Sfr-offset
Notes:
(1) When sir is coded as WDMSR, MOV is used as another dedicated
instruction. In this case, the numbers 01 bytes and clocks are different
Irom MOV (see CPU control instruction).
(2) When r3 is coded as E+, the E register is automatically incremented
by one after the instruction is executed and the number of clocks is
setto 6.
33
t¥EC
p.PD77810
Table 28.
Instruction Encodings (cont)
Instruction Code
Mnemonic Operand
Bl/B3
Flags
B2/B4
Bytes
Clocks
Operation
Low byte
3
3
rp +- word
0000 1100
Saddr·offset
4
4
(saddrp + 1) (saddrp) +- word
Low byte
High byte
4
8
sfrp +- word
16· Bit Data Transfer Instructions
MOVW
rp,#word
0110
OP2P10
ZACCY
High byte
saddrp, #word
0000 1011
Sfr-offset
Low byte
High byte
rp,rp
0010 0100
OPaP50 1P2P1O
2
4
rp +- rp
AX,saddrp
0001 1100
Saddr-offset
2
6
AX .... (saddrp + 1) (saddrp)
saddrp,AX
0001 1010
Saddr-offset
2
5
(saddrp + l)(saddrp) .... AX
AX,sfrp
0001 0001
Sfr-offset
2
10
AX +- sfrp
sfrp, AX
0001 0011
Sfr-offset
2
9
sfrp +- AX
sfrp,#word
8· Bit Operation Instructions
ADD
A,#byte
1010 1000
Data
2
2
A, CY +- A + byte
X X X
saddr, #byte
0110 1000
Saddr-offset
3
3
(saddr), CY +- (saddr) + byte
X X X
0000 0001
0110 1000
4
9
sfr, CY +- sfr + byte
X X X
Sfr-offset
Data
Data
sfr, #byte
r,r
1000 1000
0ReR5 ", OR2R1Ro
2
3
r,CY +- r+ r
X X X
A,saddr
1001 1000
Saddr-offset
2
3
A, CY +- A + (saddr)
X X X
A,sfr
0000 0001
1001 1000
3
7
A,CY+-A+sfr
X X X
A, CY +- A + (FEOOH + r4)
r4=40H-FFH
X X X
Sfr-offset
ADDC
A,[r4]
0001 0110
011R4 1000
2
1
A,[HL]
0001 0110
0101 1000
2
8/10
A,CY +- A+ (HL)
X X X
A, #byte
1010 1001
Data
2
2
A,CY +- A+ byte + CY
X X X
saddr, #byte
0110 1001
Saddr-offset
3
3
(saddr), CY +- (saddr) + byte + CY
X X X
0000 0001
0110 1001
4
9
sfr, CY +- sfr + byte + CY
X X X
Sfr-offset
Data
Data
sfr, #byte
r,r
1000 1001
0ReR5", OR2R1Ro
2
3
r, CY +- r + r + CY
X X X
A,saddr
1001 1001
Saddr-offset
2
3
A, CY +- A + (saddr) + CY
X X X
A,sfr
0000 0001
1001 1001
3
7
A,CY +- A+ sfr+ CY
X X X
A, CY +- A + (FEOOH + r4) + CY
r4=40H-FFH
X X X
A, CY +- A+ (HL) + CY
X X X
Sfr-offset
34
A,[r4]
0001 0110
011", 1001
2
7
A,[HL]
0001 0110
0101 1001
2
8/10
NEe
Table 28_
"PD77810
Instruction Encodings (cont)
Instruction Code
Mnemonic Operand
B1/B3
Flags
B2/B4
Bytes
Clocks
Operation
ZACCV
8-Bit Operation Instructions (cont)
SUB
A,#byte
10101010
Data
2
2
A,CV ... A-byte
X X X
saddr, #byte
01101010
Saddr-offset
3
3
(saddr), CV ... (saddr) - byte
X X X
0000 0001
0110 1010
4
9
sfr, CY ... sfr-byte
X X X
Sfr-offset
Data
Data
sfr,#byte
r,r
1000 1010
ORsRs~ OR2Rl Ro
2
3
r,CY ... r-r
X X X
A,saddr
1001 1010
Saddr-offset
2
3
A, CV ... A-(saddr)
X X X
A,sfr
0000 0001
1001 1010
3
7
A,CY ... A-sfr
X
1010
2
7
A, CY ... A-(FEOOH + r4)
r4=40H-FFH
X X X
0101 1010
2
8/10
A,Cy ... A-(HL)
X X X
X X
Sfr-offset
SUBC
A, [r4]
0001 0110
A, [HL]
0001 0110
011~
~f
A, #byte
1010 1011
Data
2
2
A, CY ... A-byte-CY
X X X
saddr, #byte
0110 1011
Saddr-offset
3
3
(saddr), CY ... (saddr)-byte-CY
X X X
0000 0001
0110 1011
4
9
sfr, CY ... sfr-byte-CY
X X X
Sfr-offset
Data
1000 1011
ORsR5~ OR2Rl Ro
2
3
r,CY ... r-r-CY
X X X
A,saddr
1001 1011
Saddr-offset
2
3
A, CY ... A-(saddr)-CY
X X X
A,sfr
00000001
1001 1011
3
7
A, CY ... A-sfr-CY
X X X
1011
2
7
A,CY ... A-(FEOOH + r4)-CY
r4=40H-FFH
X X X
Data
sfr, #byte
r,r
Sfr-offset
AND
011~
A, [r4]
0001 0110
A, [HL]
0001 0110
0101 1011
2
8/10
A, CY ... A-(HL)-CY
X X X
A,#byte
10101100
Data
2
2
A ... AAbyte
X
saddr, #byte
01101100
Saddr-offset
3
3
(saddr) ... (saddr) A byte
X
0000 0001
0110 1110
4
9
sfr ... sfr A byte
X
Sfr-offset
Data
Data
sfr,#byte
r,r
1000 1100
ORsR5~ OR2Rl Ro
2
3
r ... rAr
X
A,saddr
1001 1100
Saddr-offset
2
3
A ... AA(saddr)
X
A,sfr
0000 0001
1001 1100
3
7
A ... AAsfr
X
A ... AA(FEOOH+ r4) r4=40H-FFH
X
Sfr-offset
A, [r4]
0001 0110
011R4 1100
2
7
A, [HL]
0001 0110
0101 1100
2
8/10
EII~
A ... AA(HL)
35
NEe
p.PD77810
Table 28.
Instruction Encodlngs (cont)
Instruction Code
Mnemonic Operand
B1/83
Flags
B2/84
Byles
Clocks
Operstion
ZACCY
8·Blt Operation Instructions (cont)
OR
A,#byte
10101110
Data
2
2
A ... AVbyte
X
saddr, #byte
0110 1110
Saddr-offset
3
3
(saddr) ... (saddr) V byte
X
sfr,#byte
00000001
0110 1110
4
9
sir ... sir V byte
X
Sir-offset
Data
Data
r, r
10001110
ORsR5~ OR2R1Ro
2
3
r ... rVr
X
A,saddr
1001 1110
Saddr-offset
2
3
A ... A V (saddr)
X
A,slr
0000 0001
1001 1110
3
7
A ... AVsfr
X
Sir-offset
XOR
A,!r4]
0001 0110
1110
2
7
A ... AV(FEOOH + r4) r4= 40H-FFH
X
A,!HL]
0001 0110
0101 1110
2
8/10
A ... AV(HL)
X
A,#byte
1010 1101
Data
2
2
A ... A¥byte
X
saddr, #byte
0110 1101
Saddr-offset
3
3
(saddr) ... (saddr)¥byte
X
slr,#byte
0000 0001
0110 1101
4
9
sir'" sfr¥byte
V
Sir-offset
Data
011~
Data
r, r
10001101
ORsR5~ OR2R1Ro
2
3
r ... r¥r
X
A,saddr
1001 1101
Saddr-offset
2
3
A ... A¥(saddr)
X
A,slr
0000 0001
1001 1101
3
7
A ... A¥sfr
X
A ... A¥(FEOOH + r4) r4=40H-FFH
X
A ... A¥(HL)
X
Sir-offset
CMP
1101
2
7
0101 1101
2
8/10
Data
2
2
A~byte
X X X
Saddr-offset
3
3
(saddr)-byte
X X X
0000 0001
0110 1111
4
7
sfr-byte
X X X
Sir-offset
Data
r,r
10001111
ORsR5~ OR2R1Ro
2
3
r-r
X X X
A,saddr
1001 1111
Saddr-offset
2
3
A-(saddr)
X X X
A,sfr
0000 0001
1001 1111
3
7
A-sfr
X X X
A-(FEooH + r4) r4=40H-FFH
X X X
A-(HL)
X X X
A,!r4]
0001 0110
A,!HL]
0001 0110
A,#byte
1010 1111
saddr, #byte
01101111
011~
Data
sfr, #byte
Sfr-offset
A,!r4]
0001 0110
A,!HL]
0001 0110
1111
2
7
0101 1111
2
8/10
Low byte
3
4
AX, CY ... AX + word
X X X
011~
16·Blf Operation Instructions
ADDW
AX,#word
0010 1101
High byte
AX,rp
1000 1000
0000 1P2P10
2
6
AX,Cy ... AX+rp
X X X
AX,saddrp
0001 1101
Saddr-offset
2
7
AX, CY ... AX + (saddrp + 1) (saddrp)
X X X
AX,sfrp
0000 0001
0001 1101
3
13
AX, CY ... AX + slrp
X X X
Sir-offset
36
NEe
Table 28.
p.PD77810
Instruction Encodings (cant)
Instruction Code
Mnemonic Operand
B11B3
Flags
B21B4
Bytes
Clocks
Operation
ZACCY
Low byte
3
4
AX, CY .... AX -word
X X X
16-8it Operation Instructions (cont)
SUBW
AX,#word
0010 1110
High byte
AX,rp
1000 1010
0000 1P2P10
2
6
AX,CY .... AX-rp
X X X
AX,saddrp
0001 1110
Saddr·offset
2
7
AX,CY .... AX-(saddrp + 1)(saddrp)
X X X
AX,sfrp
0000 0001
0001 1110
3
13
AX,CY .... AX-slrp
X X X
Low byte
3
3
AX-word
X X X
SIr-offset
CMPW
AX,#word
00101111
High byte
AX,rp
1000 1111
0000 1P2P10
2
5
AX-rp
X X X
AX,saddrp
0001 1111
Saddr-offset
2
6
AX-(saddrp + 1)(saddrp)
X X X
AX,slrp
0000 0001
0001 1111
3
12
AX-slrp
X X X
SIr-offset
Multiplication/Division Instructions
MULUW
0000 0101
0000 OR2R1 Ro
2
43
AX(high·order 16bils), r
(low·order8bits) .... AXxr
DIVUW
0000 0101
0001 1R2R1 Ro
2
71
AX (dividend), r (remainder) .... AX -.- r
2
r .... r+1
X X
Saddr·offset
2
2
(saddr) .... (saddr) + 1
X X
2
r .... r-1
X X
Saddr-offset
2
2
(saddr) .... (saddr)-1
X X
Increment and Decrement Instructions
INC
1100 OR2R1Ro
saddr
0010 0110
saddr
00100111
INCW
rp
0100 01P1PO
3
rp .... rp+1
DECW
rp
0100 11P1PO
3
rp .... rp-1
DEC
1100 1R2R1Ro
Shift Rotate Instructions
ROR
r,n
0011 0000
01N2N1 NoR2R1Ro
2
3+2n
(CY,r7 .... rO,rm-1 .... rm)xntimes
n=0-7
X
ROL
r,n
0011 0001
01N2N1 NoR2R1Ro
2
3+2n
(CY,ro .... r7, rm+1 .... rm)xntimes
n=0-7
X
RORC
r,n
0011 0000
OON2N1 NoR2R1Ro
2
3+2n
(CY .... rO,r7 .... CY,rm_1 .... rm)
xntimes n=0-7
X
ROLC
r,n
0011 0001
00N2N1 NoR2R1Ro
2
3+2n
(CY .... r7, ro .... CY, rm+1 .... rm)
xntimes n=0-7
X
SHR
r,n
0011 0000
10N2N1 NoR2R1Ro
2
3+2n
(CY .... ro, r7 .... 0, rm-1 .... rm)
xntimes n = 0-7
X 0
X
SHL
r,n
0011 0001
10N2N1 NoR2R1Ro
2
3+2n
(CY .... r7, ro .... 0, rm+1 .... rm)
xntimes n = 0-7
X 0
X
SHRW
rp,n
0011 0000
11N2N1 NOP2P1O
2
3+3n
(CY .... rpo, rp15 .... 0, rPm-1 .... rPm)
xntimes n=0-7
X 0
X
SHLW
rp,n
0011 0001
11N2N1 NoP2P10
2
3+3n
(CY .... rp15, rp <- 0, rpm+1 <- rpm)
xntimes n=0-7
X 0
X
ROR4
[r4]
00000101
100010R1 0
2
22
AS-O .... (FEOO + r4)S-O' (FEOO + r4)7_4
so
TxD
RD
RxD
RS
PCo
ER
PC1
CS
PC2
DR
CD
PCs
PC4
CI
PCs
PBs
P~o
PB4
PDO-PD7
(ALE)
PCe
(WR)
PB7
4-Wirel
2-Wire
RD1
PAo
I
PA7
DAOT
DACK
DALD
OM
AFE'
1--*'---1 :>0-....1 START
1 - - - - - -.... 1 READ
I
ROB
T01
AOUT
TIP
TRN
Telephone
Line
I
TOB
1--1----.1
WRITE
1------"
MODE
1-----,/
AIN
ReV
RING
PT
DT
LT
GT
B bits
LED Indicator
Mode Switch
Audio
Monitor
Note:
• Under development
83ML-5980B
62
t-IEC
JlPD7281
IMAGE PIPELINED
PROCESSOR
NEe Electronics Inc.
Description
Pin Configuration
The NEG pPD7281 Image Pipelined Processor is a
high-speed digital signal processor specifically
designed for digital image processing such as
restoration, enhancement, compression, and pattern
recognition. The pPD7281 employs token-based dataflow and pipelined architecture to achieve a very high
throughput rate. A high-speed on-chip multiplier
speeds calculations. More than one pPD7281 can
easily be cascaded with a minimum amount of interface
hardware to increase the throughput rate even further.
The pPD7281 is designed to be used as a peripheral
processor for minicomputers or microcomputers,
thereby relieving the host processor from the burden of
time-intensive computations. The pPD7281 has a very
powerful instruction set designed specifically for digital
image processing algorithms. The Image Pipelined
Processor can also be used as either a general purpose
digital signal processor or a numeric processor.
D
D
D
D
D
D
D
Token-based data-flow architecture
Internal pipelined ring architecture
Powerful instruction set for image processing
17 x 17-bit (including sign bits) fast multiplier:
200 ns
High-speed data I/O handling
- Asynchronous two-wire handshaking protocols
- Separate data input and output pins
Easy multiple-processor configuration
Rewritable program stores
On-chip memories:
- Link Table (LT): 128 x 16 bits
- Function Table (FT): 64 x 40 bits
- Data Memory (DM): 512 x 18 bits
- Data Queue (DQ): 32 x 60 bits
- Generator Queue (GQ): 16 x 60 bits
- Output Queue (OQ): 8 x 32 bits
NMOS technology
Single +5 V power supply
40-pin DIP
Applications
D
D
D
D
D
D
D
D
D
Digital image restoration
Digital image enhancement
Pattern recognition
Digital image data compression
Radar and sonar processing
Fast Fourier Transforms (FFT)
Digital filtering
Speech processing
Numeric processing
NECEL-oOOO76
rACK
OACK
IREO
OREQ
10815
000lS
10814
00814
IOBn
00813
IDB12
ODB12
IDB11
O DB11
..
008 10
O DB9
00B8
I'
0087
I
ODB6
OoBs
0084
0083
Features
D
D
D
D
Vee
RESET
IDB2
ODB2
IDBl
ODBl
lOBo
OOBo
GND
elK
49-000064A
Performance Benchmarks
Operation
Rotation
I/1P07281 3/1PD72815
1.5 sec
Note
0.6 sec
512 x 512 binary image
1/2 Shrinking
80 ms
30 ms
512 x 512 binary image
Smoothing
1.1 sec
0.4 sec
512 x 512 binary image
3x3 Convolution
3.0 sec
1.1 sec
512 x 512 grey scale image
64-stage FIR
Filter
SOps
18ps
17-bit fixed point
cos(x)
40ps
15ps
33-bit fixed point
Ordering Information
Part Number
Package Type
pP072810
40-pin ceramic DIP
t-{EC
pPD7281
Architecture
Pin Identification
At
No.
Signal
liD
RESET
In
2
lACK
Out
3
IREa
In
Input Request: This input
signal requests a data transfer
from an external device to
IIPD7281.
IDB15 -IDBO
In
16-bit input data bus: 32-bit
input data tokens are input to
the Input Controller as two 16bit words.
4-19
20
GND
21
ClK
22-37
Description
System Reset: A low signal on
this pin initializes IIPD7281.
During the reset, a4·bit module
number should be placed on
IDB15 - IDB I2·
High
Input Acknowledge: This
acknowledge signal is output
by the IIPD7281 to notify the
external data source that a 16bit .data transfer has been
completed.
Power ground
In
ODB15 - OD80 Out
38
OREa
Out
39
OACK
In
40
Vee
2
RESET
System clock input (10 MHz:
target spec)
High 16-bit output data bus: 32-bit
Impedance output data tokens are output
by the Output Controller as
two 16-bit words.
High
Output Request: This signal
informs an external device that
a 16-bit data word is ready to
be transferred out of IIPD7281.
Output Acknowledge: This
acknowledge signal input by
the external data destination
notifies IIPD7281 that a 16-bil
data transfer may occur.
+5 V power supply
The pPD7281 utilizes a token-based, data-flow
architecture. This novel architecture not only provides
multiprocessing capability without complex external
hardware, but also offers high computational efficiency
within each processor. Taking advantage of the multiprocessing capability of data-flow architecture, almost
any processing speed requirements can be satisfied by
using as many pPD7281s as needed in the system.
Within each pPD7281 , the data-flow architecture
provides high computational efficiency through
concurrent operations. For example, while the
Processing Unit (or ALU) spends its time for actual
computations only, the internal memory address
calculations, internal memory read and write
operations and input/output operations are all being
done concurrently. Furthermore, in contrast to
conventional von Neumann processors, a data-flow
processor doesn't fetch instructions, perform
subroutine stack operations or do data transfers
between registers. Therefore, it does not spend the
time required for these operations.
The pPD7281 also utilizes an internally pipelined
architecture. As shown in the block diagram, a circular
pipeline is formed by five functional blocks: the Link
Table (L T), the Function Table (FT), the Data Memory
(OM), the Queue (Q), and the Processing Unit (PU). A
token entered through the Input Controller (IC) is
passed on to the Link Table to be processed around the
pipelined ring as many times as needed. When a token
is finished being processed, it is queued into Output
Queue (OQ) and then output via the Output Controller
(OC).
t-IEC
pPD7281
Block Diagram
IDBtS -lOBo
IREO---....:...·I
r--r-."
oos,s- OOBO
t----OREO
IC
32
Ie: Inpul Controller. Controls input data tokens and determines whether or nol an input data
token should be senl to the circular pipeline lor processing.
OC: Output Controller, Conlrols output data tokens.
L T: Link Table [128 words x 16 bits1. Stores instruction parameters.
FT: function Table [64 words x 40 bits[. Stores instruction parameters.
OM: Dala Memory [512 words x 18 bits). Siores constants or temporary data.
0: Queue [48 words x 60 bits[. FIFO queue. Data Qu'!ue: 32 words x 60 bits.
Generator Queue: 16 words x 60 bits.
PU: Processing Unit. Executes logical, arithmetic and bit operalions.
00: Output Queue [8 words
II
32 bits]. FIFO queue lor the output tokens.
AG/FC: Address Generator and Ftow Controller. Generates addresses tor OM and controls the
flow of tokens.
RC: Refresh Controller. Generates relresh tokens lor internal DRAMs.
49-0001328
Absolute Maximum Ratings
Capacitance
TA =+25°C
TA =+25°C
Supply voltage, Voo
-0.5 V to +7.0 V
Input voltage, VI
-0.5 V to +7.0 V
Parameter
Output voltage, Vo
-0.5 V to +7.0 V
Operating temperature, TOPT1 (2 mls air flow)
Operating temperature, TOPT2 (No air flow)
Storage temperature, T8TG
limits
Symbol
Min
Max
ClK capacitance
CK
20
O°C to +70°C
Input capacitance
C1
10
O°C to +45°C
Output capacitance
Co
20
Unit
Test
Conditions
pF fc = 1 MHz
pF (All other pins
atO V)
pF
-65°C to +150°C
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3
t-{EC
pPD7281
DC Characteristics
AC Characteristics {cont}
TA = O°Cto +70°C,·Voo = 5 V ±10%
TA = O°C to +70°C, Voo = 5 V ±10%
Limits
Parameter
Symbol Min Typ
Input low
voltage 1
(RESET, IOBI5-0)
VIL1
Input high
voltage 1
(RESET, IOBI5-o)
VIHI
2.0
Input low
voltage 2
(IREa, OACK, ClK)
VIl2
-0.5
Input high
VIH2
3.5
voltag~
Max
Unit
0.7
V
-0.5
Test
Conditions
Voo+0.5 V
0.45
V
Voo+0.5 V
(IREO, OACK, ClK)
Output low
voltage
VOL
Output high
voltage
VOH
0.45
2.4
Input leakage
current
III
Output leakage
current
ILO
±10
Supply current
100
320
±10
500
ns
Data hold time
(after IREa up)
tHID
0
ns
OREa delay time 1 tOOOH
(from OACK down)
15
35
ns
OREa delay time 1 tOOOl
(from OACK up)
15
45
ns
Min time between
transitions on
OREa and OACK
tOOA
15
ns
10
ns
oV::;; VI::;; VOO
Data access time tOOD
(after OREa down)
25
ns
J1A
oV::;; Vo::;; Voo
Data float time
(after OREa up)
35
ns
J1A
rnA
Unit
500
ns
40
ns
ClK pulse width
low
tWKl
40
ns
10
ns
10
ns
lACK d~ time 1 tOIAL1
(from IREO down)
(Note 1)
20
50
ns
lACK delay time 1 tOIAHI
(from IREa up)
(Note 2)
20
55
ns
lACK delay time 2 tOIAL2
(from IREa down)
20
70
ns
lACK delay time 2 tOlAH2
(from IREa up)
20
70
ns
Min time between
transitions on
IREa and lACK
tHIO
15
IREa rise time
tlOR
ns
ns
Test
Conditions
Measured at
2V
tFOD
10
Pre RESET
high time
tRVRST
tClK
RESET low time
tWRST 6tClK
Module number
tOMO
data setup time
(after RESET down)
Module number
data hold time
(after RESET up)
tHMO
Reset delay
from ClK down
tORST
ns
ns
2tClK
0
Conditions
ns
10
tWKH
4
40
tOAF
Max
10
tSID
tOAR
ClK pulse width
high
tKF
ns
tlOF
Data set up time
(before IREa up)
OACK fall time
100
ClK fall time
10
IREa fall time
OACK rise time
tClK
tKR
Unit
IOH =-400J1A
ClK cycle time
ClK rise time
Test
Max
V
Limits
Typ
Typ
10l =2.0 rnA
AC Characteristics
Symbol Min
Symbol Min
V
TA = O°C to +70°C, Voo = 5 V ±10%
Parameter
Limits
Parameter
ns
ns
(1/2)tClK ns
Notes:
(1) "Down" = on falling edge
(2) "Up" = on rising edge
(3) Output load capacitance: lACK, OREQ = 50 pF; ODBI5-0 =
100 pF
t-iEC
JlPD7281
Timing Waveforms
AC Test Input Voltage
-
RESET, IDB
AC Test Output Voltage
~-0.8
..-- Test Points
<~
OREa,lACK. ODB
-
0.8
~-.
0.45
~ Test
--~
0.45
Points ---..
83-001866A
--~--
eLK, IREO, OACK
.--- Test Points
0.45
<~
0.45
Module Number and RESET Timing
83-001865A
·-I----o.~--twRST------..
Clock Timing
elK
83-001868A
Input Handshake Timing
tlOA
+---tOIAL1________..
.....--tOIAH1-----+-
+------tOIAL2------'
4 - - - - - 1510--------+-
......--tOIAH2-----+
...--1510------+
+-tHID
+--tHID
83-001869A
Output Handshake Timing
-+-----tDOOH~
~
\
I
.... tOOA ......
• tOCA"
\
00815-0080
---- -
-~
-- tOOD
/
--
I--
\
/
--- tOOD
I'--........ tOOA ......
+--tOOA ....
ir-------- --<
tFOD
+---- looaL------+-
+--tDOQH-----'
-+-----tOOQL- - . . .
j
-1-t
......--tOAF
oAR
--
)-------------tFOD
----
83-0018706
5
fttfEC
pPD7281
Functional Description
As shown in the block diagram, the IlPD7281 consists
of 10 functional blocks. Before any processing occurs,
the host processor down-loads the object code into
the Link Table and the Function Table of the IlPD7281
by using specially formatted input tokens. At this time,
constants may also be sent to the Data Memory to be
stored. The contents of the Link Table and the Function
Table are closely related to a computational graph.
When a computational process is represented
graphically, it usually forms a directed data-flow graph.
In such a graph, the arcs (or edges, links, etc.)
represent the entries in the Link Table and the nodes
represent the entries in the Function Table. An arc
between any two nodes has a data value, called a "token",
and is identified by a corresponding entry in the Link
Table. A node in the directed data-flow graph signifies
an operation, and the type of operation is logged into
the Function Table along with the identification information about the outgoing arc.
A minimal amount of interface hardware is required to
configure pPD7281s in a multiprocessor system. As
many as 14 IlPD7281s can be cascaded together, as
Figure 1.
shown in figure 1. Each IlPD7281 must be assigned a
Module Number (MN) during reset. Figure 2 shows the
timing diagram for assigning the module number.
When any token enters a IlPD7281, regardless of the
total number of IlPD7281s used in the system, the
Input Controller of that IlPD7281 discerns whether or
not the entering token is to be processed by checking
the Module Number (MN) field of the token. If the
Module Number is not the same as the Module Number
assigned during reset, the token is passed to the
Output Controller so that it can be sent out via the
Output Data Bus. However, if the token has the same
Module Number, then the Input Controller strips off
the MN field and sends the remaining part of the token
to the Link Table for processing.
Once a token enters the circular pipeline by accessing
the Link Table, it requires seven pipeline clock cycles
for the token to fully circulate around the ring. One
pipeline clock cycle is needed for the Link Table, the
Function Table, or the Data Memory to process an
incoming token, and two pipeline clock cycles are
needed for the Queue or the Processing Unit to
process a token. The Queue requires one pipeline
Connecting Multiple IlPD7281s
OulpUI
{
OACK
lACK
OACK
OREQ
IRED
OREQ
IREO
00815
108 15
0 08 15
10815
00814
10814
0 0814
10814
lACK} Inpul
Handshake
Handshake
Lines
Lines
r-
• • •
• • •
Input Data Bus
Output Data Bus
L ODB.
lOBo
OOSo
Chip liN
108 0 -
Chip#N+1
I\~JOOO14(}\3
Figure 2.
Timing Diagram for Assigning Module
Numbers During RESET
Fi'EsiT
ODS (16) Don't Ca
MNR(4)* High
High Impedance
Module Number
Impedance
MNR(4): 108'5-108'2
*From external hardware
6
49-000065A
ttlEC
pPD7281
clock cycle to write and one cycle to read. Similarly,
the Processing Unit requires one pipeline clock cycle
to execute and one clock cycle to output the result. In
other words, both the Processing Unit and the Queue
are made of two-stage pipelines. Therefore, when
seven tokens exist simultaneously in the circular
pipeline, the pipeline is full and full parallel processing
is achieved.
in figure 3. A data token flowing within the circular
pipeline must have at least a 7-bit Identifier (ID) field
and an 18-bit data field. The ID field is used as an
address to access the Link Table memory. When a
token accesses the LT memory, the ID field of the
token is replaced by a new ID (shown as ID' in figure 3)
previously stored in the LT memory. As a result, every
time a data token accesses LT memory, its ID field is
renewed. The data field of a token consists of a control
bit, a sign bit and a 16-bit data. A token may have up to
two data fields, as well asotherfields (OPcode, control,
etc.) if necessary.
When a data token flows through each functional
block in a given pPD7281, the format of the token
changes significantly. The actual transitions of a token
format through different functional blocks are shown
Figure 3.
I/O Token [32J
LTToken 12BI
•
Token Formats and Transitions
I
I~i
1
MN
[01
ID
16
CTLF
ID
OATA
,.
CTLF
L T Contents
DATA
DATA
,.
FT Contents
FTL
16
10
FTR
FTT
12
1 1
16
FTL (Lower 12 bits]
C S
DATA
,.
W-----L---t==::;:::==:J'c=;:=:::j~-----------1...l....L-----------""iDM
cynlents
DATA
12
16
16
11
CATAs
FTL [Lower 12 bits)
Ca
12
S8
16
11
16
FTL[Lower 12 bits]
DATAS
S8
C8
12
1 1
16
1 1
16
.y-r-=-____D_A_T_A8_ _ _ _ _...J
o Q Token [S9J L.J._ _ _ _ _"'--"-r'-_ _
FT_L_IL_o_w_e'_'_2_b_It._1_-"-......-'-;;_ _ _ _ _D_A_T_A_A_ _ _ _ _
PUF
1/0 Token
LT Token
FT Token
OM Token
Q Token
PU Token
00 Token
MN
ID
ID·
10"
CTLF
DATA
FTA
c.
SA
Input or Output Token
A token accessing the Link Table
A token accessing the Function Table
A token accessing the Data Memory
A token accessing the Queue
A token accessing the Processing Unit
A token accessing the Output Queue
Modul;! Number
Identifier for an input or output token
Identifier for a token which exits LT for the first time
Identifier for a token which exits LT for the second time
Control field
l6·blt data field
Function Table Address
Sa
CB
SEL
FTRC
FTL
FTR
FTT
PUF
C
CA
Ca
S
SA
Sa
DATAA
CATAB
SELection field
Function Table Righi field Control bit
Function Table Left field
Function Table Right field
Function Table Temporary field
Processing Unit Flags
Control bit for a l6·bit data
Control bit for a l&.bit data from A side
Control bit for a l6·bit data 'rom B side
Sign·bit for a l6·bit data
Sign·bit for a l6-bit data from A side
Sign·bit for a l6-blt data from B side
16·bit data from A side
l6·bit data from B side
49-0001336
7
I
t-IEC
JlPD7281
Input Controller [IC]
A 32-bit token is entered into a JlPD7281 in two 16-bit
halves using a two-signal request/acknowledge handshake method, as shown in figure 4. The input/output
token format is shown in figure 1. After a token is
accepted by the IC, the MN field of the token is
compared to the Module Number of JlPD7281 which
was assigned at reset. If the Module Number of the
accepted token is not the same, the IC passes the
token directly to the Output Controller. If the MN field of
the accepted token is the same, then the IC strips off
the Module Number and sends the remaining part of
the token to the Link Table. The IC also monitors the
status of the Processing Unit. If it is busy, the IC delays
accepting another token until it is no longer busy. The
IC also accepts the refresh tokens from the Refresh
Controller (RC) and sends them to the Link Table.
Figure 4.
consist of a 6-bit Function Table Address (FTA), a 7-bit
10, a 1-bit Function Table Right Field Control (FTRC),
and a 2-bit Selection (SEL) field. When a token
accesses LT memory, its 10 field is replaced by the new
ID field contained in the memory location being
accessed. Therefore, every time a token accesses LT
memory, it is given a new ID. The FTA field is used to
access FT memory locations. The FTRC bit and the
SEL field are used to specify the type of instruction. By
using specially formatted tokens, the contents of the
LT can either be set during a program download or be
read during a diagnosis.
Function Table [FT]
The FT isa 54 x 40-bit dynamic RAM. Asforthe case of
the Link Table, the contents can either be set during a
program download or be read during a diagnosis by
using specially formatted tokens.
Each FT memory location consists of a 14-bit Function
Table Left field (FTL), a 15-bit Function Table Right
field (FTR), and a 10-bit Function Table Temporary
field (FTT). These fields contain control information
for different types of instructions.
Handshake Timing Waveforms
IREQ
Address Generator and Flow Controller [AG/FC]
lACK
lOBo
~
10815
High
Low
Input Token Timing
008 0.00815
*target spec
High
49-000069A
Low
Output Token Timing
49-000070A
The AG/FC generates the addresses to access the
Data Memory (DM) and controls the writing of data to
and the reading of data from the Data Memory. AG/FC
determines whether the incoming token contains a
one-operand instruction or a two-operand instruction.
One-operand instruction tokens can be sent directly to
the Queue. However, if the token contains a twooperand instruction, then both operands must be
available before they can be sent to the Queue. For a
two-operand instruction, the token which arrives atthe
Data Memory first is temporarily stored until the
second operand token arrives. When the second
operand token exits the Function Table, the AG/FC
generates the Data Memory address which contains
the first operand. Then, the second operand token and
the first operand data read out from the Data Memory
are sent to the Queue together.
Data Memory [OM]
Output Controller rOC]
The OC outputs 32-bit tokens in two 16-bit halves
using a two-signal request/acknowledge handshake
method, as shown in figure 4. The types of tokens
output by the OC are as follows: output data tokens
from the Output Queue, error status data tokens
generated internally by OC, DUMP tokens, and passing
data tokens from the Input Controller.
Link Table [LT]
The LT is a 128 x 16-bit dynamic RAM. The ID field of
an incoming LT token is used to access the LT
memory. The contents of an LT memory location
8
The OM isa512x 18-bitdynamic RAM which is used to
queue the first operand for a two-operand instruction
until the second operand arrives. DM can also be used
as a temporary memory or as a buffer memory for 1/0
data.
Queue [Q]
The Q is a FIFO memory configured with a 48 x 50-bit
dynamic RAM. The Q is used to temporarily store the
Processing Unit-bound and the Output Queue-bound
tokens. The Q is fu rther divided into two different FI Fa
memories: a 32 x 50-bit Data Queue (DQ) and a 16 x
50-bit Generator Queue (GQ). The DQ is used for the
t-{EC
PU, OUT and AG/FC instructions. The DQ temporarily
stores the PU and AG/FC tokens before they are sent
to the Processing Unit for processing. The DQ also
temporarily stores the Output Queue tokens before
they are sent to the Output Queue. The GQ is used for
Generate (GE) instructions only. The DQ will not
output tokens to the Output Queue if it is full, and the
DQ or GQ will not output tokens to the Processing Unit
if the Processing Unit is busy.
In orderto control the numberof tokens in the circular
pipeline to prevent Q overflow, the Q is further restricted
by the following two situation rules: when the DQ has
eight or more tokens stored, the read from the GQ is
inhibited, and when the DQ has fewerthan eight tokens
stored, the read from the GQ has a higher priority than
the read from the DQ. Since instructions stored in the
GQ generate tokens, restricting the number of GQ
tokens is important in order to keep the Q from
overflowing. In case the internal processing speed is
slower than the rate of incoming data tokens, the DQ
posseses a potential overflow condition. To prevent
overflow, the processor is put into restrict/inhibit mode
when the DQ reaches a level greater than 23.
Output Queue [OQ]
The OQ is a first-in first-out (FIFO) memory configured
in an 8 x 32-bit static RAM. The OQ is used to
temporarily store the output data tokens from the Data
Queue so that they can be output by the Output
Controller via the output data bus. When OQ is full, it
sends a signal to the Data Queue to delay accepting
further tokens.
Processing Unit [PU]
The PU executes two types of instructions: PU and GE.
PU instructions include logical, arithmetic (add, subtract
and multiply), barrel-shift, compare, data-exchange,
bit-manipulation, bit-checking, data-conversion, doubleprecision adjust, and other operations. The control
information for a PU instruction is contained in the
Function Table Left field of the PU token. The GE
instructions are used to generate a new token, multiple
copies of a token, or block copies of a token. They can
also be used to set the Control field (CTLF) of a token
and to generate external memory addresses. If the
current PU operation cannot be completed within a
pipeline clock cycle, the PU sends a signal to the
JlPD7281
Queue and the Input Controller to prevent them from
releasing any more tokens.
Refresh Controller [RC]
The RC automatically generates refresh tokens for the
dynamic RAMs used in the circular pipeline, i.e. the L T,
FT, DM, and Q. Each RC token, generated periodically,
is sent to the Input Controller and is propagated
through the L T, FT, DM and Q, in that order. The RC
tokens are deleted after reaching the Q.
Operation Modes
There are three different modes in which the pPD7281
can operate: Normal, Test, and Break (see figure 5).
After an external hardware reset, the pPD7281 is in the
Normal mode of operation. The pPD7281 can enter the
Test mode for program debugging by inputting a
SETBRK token (see figure 6) while the processor is in
the Normal mode. If an overflow occurs in the Data
Queue or the Generator Queue, the processor enters
into the Break mode so that the internal contents of the
processor can be examined; see table 1. Table 2
describes the effects of software and hardware resets.
Table 1.
DUMPD Output Token Format
CTLF
MN
Z
10
0000
a
a
0000 000
0111 xxxxx(5) GO Size(5 bits) DO Size(6 bits)
0000 001
0111 xxxx(4) u(l)
0000 0
0000010
0111
0000
DATA (16-bitfield)
10(7) CTLF(4)
DATA(16)
a
0000011
0111 xxx (3) u(1) 10(7) x(1) CB, SB, CA, SA
0000 0
0000100
0111 xx(2) FTL (Lower 12 bits) xx(2)
0000 0
0000101
0111
OATAA(16)
0000 0
0000110
0111
OATAB(16)
0000 0
0000111
0111 xxxxxxxxx(9)
0000
x: Don't care
Table 2.
10(7)
u: Unused
Effects of Reset OperatIon
Hardware Reset
Software Reset
MN
/JP07281 reads in MN
No Change
High/Low Word Flip-flop
Reset
No Change
Input Inhibit Control
Reset (No constraint)
No Change
LT Break State
Reset
Reset
Internal Operation
Stopped
Stopped
00, GO, and 00 Pointers
Set to 0
Set to 0
9
ttlEC
tJ PD7281
Figure 5.
p.PD7281 Operation Modes
Normal Mode
RunandPAGM
DOWNLOAD
Break Mode
Tesl Mode
Outputl Error Token
Program Debugging Mode
Queue Overflow
Sets Break Condition
May Us. DUMP
to Examine Contents
CBRK Token
Break Condition
49-00006SA
Figure 6.
SETBRK (Set Break Condition) and SETMD (Set Mode) Token Formats
SETBRK Token Format
ID
COUNT
1 :::: Timer Count
o = Event Count
Event Counl: Breaks atter the I 0 Unk Table entry has been accessed a specified number of times.
Timer Counl: Breaks after a specified number of Intemal pipeline clock cycles.
49-000067A
SETMD
'Set Model
Token Format
o
15
I
ID
MN
111
15 14 13 12 11
0
IIII
0
43
Refresh Counf
I
IIRSD
~----------------------~~~--~--~~--.-~
"""" Input Control
o 0 = No Input Restriction
o
1 :::: Input Inhibited
1 0 = Input Restricted
1 1 = Not Allowed
Refresh Count _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
To generate relresh cycles [2m. min] for LT, FT, OM and Q.
Refresh Counter mUlt be adlulted tor different external clock frequencies.
Oefaull Value := OAH (for 10MHz external clock I
IIRSO IInputlnhibil Regisler Set O a l a ] _ - - - - - - - - - - - - - - - - - - - - '
Every
nth
pipeline clock cycle, the Input inhibit is released, were n
= (IIRSOI x 8
49-0001348
10
ttlEC
JlPD7281
Input/Output Tokens
Table and the Function Table using SETLT, SETFTR,
SETFTL and SETFTT input tokens. The contents ofthe
Function Table and the Link Table can also be read
using RDLT, RDFTR, RDFTL and RDFTT tokens. In
order to write or read a value to and from the Data
Memory, a program must be down-loaded and executed. Once object code is down-loaded into the
pPD7281, data tokens are input to the processor,
thereby initiating the processing. For a description of
the input and output tokens, see tables 3 and 4.
The only way any external device can communicate
with thepPD7281 is by using the I/O tokens (see figure
7). Both the input and the output tokens have the same
format so that a token may flow through a series of
multiple processors without a format change. A 32-bit
I/O token is divided into upper and lower 16-bit words
and input to or output from the pPD7281 a 16-bit word
at a time. Object code is down-loaded into the Link
Figure 7.
Input/Output Token Format
I,
High Word
I.
I
121110
MN
10
Iz I
I
01.
CTLF
0
Dala
II
MN: Module Number
II
Low Word
"
43
I
I
Z: Always Zero
CTLF: Control Field
10: Identifier
49-000068A
Table 3.
Input Token Format
Input Token
High Word (161
MN(4)
15
12
Z(I)
11
SETLT
MN
0
SETFTR
MN
SETFTL
Low Word (16)
10(7)
Remarks
DATA (16)
CTLF (4)
3
0
15
LT address
1 1 00
Data to be set in LT
SetLT
0
FT address
1 1 01
Data to be set in FTR
Set FT Right Field
MN
0
FT address
1110
Data to be set in FTL
Set FT Left Field
SETFn
MN
0
FT address
1111
Data to be set in FTT
Set FT Temporary Field
RDLT
MN
0
LT address
1 000
Read LT
RDFTR
MN
0
FT address
1 001
Read FT Right Field
RDFTL
MN
0
FT address
1010
Read FT Left Field
RDFn
MN
0
FT address
1 01 1
Read FT Temporary Field
4
10
0
CRESET
MN
0
01 00
SETMD
MN
0
o 1 01
Mode set data
Set Operation Mode
SETBRK
MN
0
ID
01 1 0
M(1)
Set Break Condition
DUMP
MN
0
xxxx(4) DUMP (3)
o1 1 1
Dump
01 00
Command Break
CBRK
0000
0
VAN
1111
0
PASS
MN*
0
EXEC
MN
0
Command Reset
Count (15)
Vanish Data
Pass Data
ID
00 C S
Data
Normal Execution Data
* When MN is not the current module number
x: Don't care
11
ttfEC
JlPD7281
Table 4.
Output Token Format
output Token
Lower-Order Word (16)
Upper-Order Word (16)
Z (1)
11
LTRDD
0000
0
LT address
1 000
Data read from LT
FT Read Data
FTRRDD
o0 0 0
0
FT address
1 001
Data read from FTR
FT Right Field Read Data
FTLRDD
0000
0
FT address
1010
Data read from FTL
FT Left Field Read Data
FTTRDD
0000
0
FT address
101 1
Data read from FTT
FT Temporary Field Read Data
PASSD
MN
0
ID
CTLFD
Data
Pass Data
o0 0 0
o0 0 0
0
0
o 000 0 o 0
o 0 0 0 DUMP(3)
o 1 00
o1 1 1
Dump data
Dumped Data
0
ID
00 C S
Data
Output Data
ERR
DUMPD
OUTO
MN
CTLF (4)
Remarks
MN(4)
15
12
10171
10
4
DATA (16)
0 15
3
0
MN(4)MODE(4) 000 STATUS(5) Error Data
Instruction Set Summary
Tables 5 through 8 summarize the instruction set.
TableS.
AGIFC Instructions
Table 6.
PU Instructions (cont)
Instruction
Mnemonic
Instruction
Queue
MUL
Multiply
Read cyclic short
NOP
No operation
RDCYCL
Read cyclic long
ADDSC
Add and shift count
WRCYCS
Write cyclic short
SUBSC
Subtract and shift count
Write cyclic long
MULSC
Multiply and shift count
RDWR
Read/Write Data Memory
NOPSC
NOP and shift count
RDIDX
Read Data Memory with index
INC
Increment
PICKUP
Pickup data stream
DEC
Decrement
COUNT
Count data stream
SHR
Shift right
CONVO
Convolve
SHL
Shift left
CNTGE
Count generation
SHRBRV
Shift right with bit reverse
DIVCYC
Divide cyclic
SHLBRV
Shift left with bit reverse
DIV
Divide
CMPNOM
Compare and normalize
DlST
Distribute
CMP
Compare
SAVE
Save ID
CMPXCH
Compare and exchange
CUT
Cut data stream
GETl
Get one bit
Mnemonic
QUEUE
RDCYCS
WRCYCL
Table 6.
PU Instructions
Mnemonic
Instruction
OR
Logical OR
AND
Logical AND
XOR
Logical EXCLUSIVE·OR
ANDNOT
Logical INVERT an operand then AND: (A.B)
NOT
Invert
ADD
Add
SUB
Subtract
12
SEn
Set one bit
CLRl
Clear one bit
ANDMSK
Mask a word with logical AND
ORMSK
Mask a word with logical OR
CVT2AB
Convert 2's complement to sign·magnitude
CVTAB2
Convert sign·magnitude to 2's complement
ADJL
Adjust long (for double precision numbers)
ACC
Accumulate
COPYC
Copy control bit
NEe
Table 7.
IlPD72 81
AG/FC Instructions
GE Instructions
There are 16 AG/FC instructions (see table 10). They
can be grouped into three types: Address Generator
(AG), Flow Controller (FC), and AG/FC type.
Mnemonic
Instruction
COPYBK
Copy block
COPYM
Copy multiple
SETCTL
Set control field
Table 8.
AG type: RDCYCS, RDCYCL, WRCYCS, WRCYCL,
RDWR, RDIDX
FC type: PICKUP, COUNT, CUT, DIVCYC, DIV, DIST,
CONVO, SAVE, CNTGE
OUT Instructions
Mnemonic
Instruction
OUT1
Output 1 token
AG/FC type: QUEUE
Output 2 tokens
A 4-bit OP code in the Function Table right field
specifies the instruction to be executed.
OUT2
There are four different types of instructions which can
be specified by the SEL field of an FT token. See table 9.
Table 9.
SEL Field of an FT Token
SEL Type
FTR
Description
11
AG/FC
Executes instructions specified by the Function Table
Right field while monitoring the Function Table
Temporary field.
01
PU
Performs arithmetic, logical, barrel-shift, bitmanipulation, data-conversion, etc.
10
GE
Generates a block or multiple new tokens from a token.
Sets the control field of a token. Increments or
decrements the data field of a token.
00
OUT
Outputs data tokens from the circular pipeline to the
Output Queue after the tokens are finished being
processed.
Figure 8.
I
15
14
13
OP code
12
10
I
9
8
7
6
1
0
~anes with Instruction
Field'--~~~~~~L.~~~~~~~~~~~----'
QUEUE
For a two-operand instruction, a QUEUE instruction is
used to temporarily store the first operand token in the
Data Memory until the second operand token arrives.
The maximum Queue size is 16. See figure 8.
QUEUE Instruction
~~~~~~~~~FTR~~~~~~
15
o
--+-o
43
1211
9
,
0
1
---I
43
7
,
, ,
QUEUE Size
OM Base (x 21)
- - - - FTT ------8
A/B.W/RI
Read Counter
Write Counter
LlC) OOOJ1S!·
D2
D'
QUEUE
ADD
()
Note: See Data-flow Graph Explanation [figure 27] for the explanation of figures.
13
~EC
pPD7281
Figure 9.
RDCYCS [Read Cyclic Short]
RDCYCS reads 18-bit data words from the Data
Memory cyclically (see figure 9). The first data to be
read is specified by the DM Base address. The last data
to be read is specified by the buffer size. The Read
Counter (RC) contains the offset address from Data
Memory Base (DMB) address. It is incremented each
time the Data Memory is accessed. The maximum
buffer size is 16.
RDCYCS Instruction Operation
--
DM
-rOM Base
=
0;
.~
_L...
--
49-000074A
RDCYCS Instruction Field Format
I-
43
1211
o
0
./
FTT
FTR
15
09
43
I
0 I
I
OM BASE [x 2']
Read Counter
Buffer Size
49-000073A
RDCYCL [Read Cyclic Long]
range. The first data to be read is specified by the DM
Base address. The last data to be read is specified by
the buffer size. The maximum buffer size is 256.
RDCYCL reads 18-bit data words from the Data Memory
in a cyclic manner like RDCYCS but has a longer cyclic
RDCYCllnstruction Field Format
/15
1211
o
FTR
-I-
87
09
0: OM Base (x 25] :
I
,
Buffer Size
./
FTT
87
Read Counter
49-00007SA
WRCYCS [Write Cyclic Short]
WRCYCS writes 18-bit data words into the Data
Memory cyclically. The first the Data Memory address
is specified by the DM Base address. The last address
is specified by the buffer size. The maximum buffer
size is 16.
WRCYCS Instruction Field Format
./
FTR
15
43
1211
o
0
I
11
OM Base [x 21]
09
Buffer Size
./
FTT
43
Write Counter
49-000076A
WRCYCL [Write Cyclic Long]
WRCYCL writes 18-bit data words into the data memory
in a cyclic mannersimilarto WRCYCS but has a longer
14
cyclic range. The first DM address is specified by the
DM Base address. The last address is specified by the
buffer size. The maximum buffer size is 256.
NEe
JlPD7281
WRCYCL Instruction Field Format
FTT
FTR
I'
15
1211
87
87
09
,
o
Buffer Size
1: OM Base Ix 251 ,:
RDWR [Read/Write Data Memory]
RDWR is used to write or read data to and from the
Data Memory. This instruction reads/modifies/writes
the Data Memory with the Address Register as index.
If a token arriving at the instruction has FTRC bit = 0,
then the instruction performs a DM read operation. If it
has FTRC bit = 1, then the instruction performs a DM
write operation.
Write Counter
the lower eight bits of the data field of the token, and
the DM Base address. After the read operation, the
lower eight bits of the token's data field is added to the
value of AR. Additionally, the data field of the token is
replaced by the contents read from the Data Memory
location.
For a token with the FTRC bit = 0, the actual DM
address location to be read is determined by the sum of
the following three values: 8-bit Address Register (ARl,
If a token with FTRC bit = 1 is used along with RDWR, a
write operation is performed. The Data Memory address
location is determined by the sum of 8-bit AR and DM
Base address. The 18-bit data from the token is written
into the DM address calculated. After the write
operation, AR is reset to DOH.
FTRC=O
FTRC= 1
Before Read Operation
8
I I
I I
0
0
Belore Write Operation
7
8
0
7
I I
I
AR
Aft
0
+1
Lower 8 Bits of Dala Field
1
OM Base Address
0
+LI____________D_M_B_••_._Ad_d_re_••__________~~
I0 I
OM
OM Address
Address
After Write Operation
7
I
After Read Operation
I
AR
+1
I
0
0
7
Aft
Lower 8 8ils of Data Field
49-000080A
7
Aft
49-000079A
R DWR Instruction Field Format
15
FTT
FTR
I'
12 11
4 3
OM Base
Ix 21J
o9
-I
8 7
Address Register
49-000078A
15
~
I
ttlEC
pPD7281
RDIDX [Read Data Memory with Index]
RDIDX is used to read the contents of the Data
Memory. This instruction is most useful when a part of
the Data Memory is used as a look-up table. The
RDIDX instruction performs different operations
depending upon the FTRC bit of the token using the
instruction. If the FTRC bit = D, then the instruction
reads a Data Memory location. The DM address
location to be read is determined by the sum of the
following three values: the a-bit AR, the lower eight bits
of the token's data field, and the DM Base address.
After the read operation, the data field of the token is
replaced by the contents of the Data Memory location
read. The value of AR is reset to zero after the
operation.
If the FTRC bit = 1, no operation is performed on the
Data Memory. However, the token's AR contents are
replaced by the modu10-256 sum of the lower eight bits
of data field and the current contents of AR.
FTRC= 1
FTRC=O
Before Read Operation
8
7
0
8
AR
0
I [
I I
AR
[
7
7
0
I
I I
Lower 8 Bits of Data Field
8
0
+L[__________L_o_we_r_8_Bi_t._Of_D_.t_._Fi_eld__________~1
0
0
+1
OM Base
AR
0
49-000081 A
0
I
OM Address
Alter Read Operation
7
0
1
o[
0
7
[
AR
R 01 OX Instruction Field Formal
I·
FTR
o
----------------~---------FTT----- 43
1211
15
1
0
1
iI
OM Base Ix 21]
09
--1
87
Address Register [AR1
49-000082A
16
!\fEe
pPD7281
PICKUP [Pickup Data Stream]
Size (CS) of the Function Table Right field.
This instruction picks up every (n+1 )th token from a stream
of i ncomi ng tokens and increments the (n+ 1)th token's I D
field by one. The number n is specified by the Count
Note: These figures use the data-flow graph convention. See figure
27, Data-flow Graph Explanation forthe explanation offigures.
Figure 10 illustrates the PICKUP instruction with CS=3.
PICKUP Instruction Field Format
FTT
FTA
I'
15
1211
87
I
1
0
01
09
Count Size
'I
87
[CSI
Counter
[el
49-00008SA
Figure 10.
Pickup Instruction
I
r
PICKUP
L
r
4
I
I
I
PICKUP
(
OUT2
OUT1
(
ID
CD 8
CD 4
10+1
49-000083A
COUNT [Count Data Stream]
COUNT copies every (n+1)th token from a stream of
incoming tokens and increments the copied token's ID
49-0DOO84A
field by one. The number n is specified by CS of the
Function Table Right field. Figure 11 illustrates the
COUNT instruction with CS = 3.
COUNT Instruction Field Format
FTA
I'
15
1211
o
1:
I
FTT
I·
09
87
Count Size (CS]
.I
CS~3
'I
87
Counter [e]
49-0001368
17
NEe
pPD7281
Figure 11.
COUNT Instruction
I
I
COUNT
r
I
(~8
COUNT
L
.1'"
I
OUT.
OUT1
~,
49-000087A
CONVO[Convolve]
49-000124A
Figure 12.
CONVO instruction is used to perform cumulative
operations such as :rAj or IIAj. The CONVO instruction
is best suited for convolving two sequences of the
same length. Figure 12 illustrates the CONVO instruction by computing
CONVO Instruction
CS=2n-1
IN'
IN.
n
SUM = LAi Bj.
j=l
The Aj sequence is input to IN1 while the Bj sequence
is input to IN2. Togetherthey are queued and multiplied
to form the Cj sequence. The Cj'S arriving at CONVO
instruction are queued and added together to form the
final answer SUM. The length of the summation, n, is
specified by the CS.
SUM
n
AIBI
i - 1
= !
49-00008!lA
CONYO Instruction Field Format
I'
'5
1211
FTR
,I
87
09
Count Size [eS]
FTT
'I
,
87
Counter
0
Ie]
49-000089A
18
NEe
/lPD7281
Figure 13.
CNTGE [Count Generation]
CNTGE is normally used with COPYBK (Copy Block)
to generate more than 16 copies of a single token (see
figure 13). This instruction has both the dead (inactive)
state and the wait (active) state. The instruction starts
in the dead state. The FTRC bit = 0 tokens that arrive
du ring the dead state of instruction are output to the I D
+ 2 token stream. It enters the wait state when a token
with FTRC bit = 1 arrives and the token is output to I D
token stream. Once the instruction is in the wait state,
it counts the number of tokens arriving with FTRC bit =
0, outputting them to the ID token stream, until the
number exceeds the number specified by CS.lf Counter
(C) reaches the number specified by Count Size (CS),
the instruction automatically enters the dead state.
Tokens with the FTRC bit = 1 arriving at CNTGE while
the instruction is in the wait state are deleted by the
instruction. Once the instruction enters the dead state,
it can be reactivated by the arrival of a token with FTRC
bit = 1.
CNTGE Instruction
,P
CNTGE
CS=2
GS = 3
COPYBK
,
,(
{'(;~ ~
G$=3
,(
10
+2
~CS=2
{ ,~
'CD
,(
~~
cS=',CD
10+1
GS=3
{r, Cs=o
ID
49-000091A
CNTGE Instruction Field Format
,I,
FTR
'5
1
12 11
1
1
I
0 I
I
.7
o
Count Size [eS]
FTT
9 8
I
WID:
7
Counter
Ie] .
4'1·000090A
19
t-{EC
JlPD7281
Figure 14.
DIVCYC [Divide Cyclic]
DIVCYCdividesan incoming stream of tokens into two
streams of tokens: an ID token stream and an ID + 1
token stream. The pattern in which the incoming
tokens are divided is specified by the Divide Size (DS)
and Count Size (CS). The DS specifies cycle size
whereas CS specifies the number of consecutive
tokens to be in the ID stream. The first CS + 1 tokens
are output to the ID token stream. The following
consecutive (DS - CS) tokens are output to the ID + 1
token stream.
DIVCYC Instruction
DS~7
CS~
2
13
12
11
10
9
8
7
8
5
4
3
2
1
I
Figure 14 illustrates the DIVCYC instruction with
DS = 7 and CS = 2. Note that an incoming stream of
tokens is divided into a stream of ID tokens and a
stream of ID + 1 tokens with a cycle of 8 tokens. Since
CS = 2, the number of ID tokens in one cycle is 3, the
number of ID + 1 tokens in a cycle is 5.
DlVCYC
13
1)12
D~·;"10
•
I
)8}
1)7
~:
DS-CS~5
CS+1~3t~!
10
10
+1
49-000093A
DIVCYC Instruction Field Format
15
FTT
FTR
I·
1211
87
43
Count Size [CS]
! Divide Size (OS]
09
87
'I
43
Counter
Ie]
Counter
Ie]
49-000092A
20
NEe
IIPD7281
DIV [Divide]
Figure 15.
DIV Instruction
OIV with CS = n divides an incoming stream of tokens
with FTRC bit = 0 into two streams of tokens: 10 tokens
and 10 + 1 tokens. The first (n + 1) incoming tokens with
FTRC bit = 0 are output as the 10 tokens, and the rest of
the incoming tokens with FTRC bit = 0 are output as
10 + 1 tokens. An incoming token with FTRC bit = 1 is
used to reinitialize the OIV instruction. The stream of
input tokens with FTRC bit = 0 after the reinitialization
is again divided into a stream of (n + 1) 10 tokens followed
by 10 + 1 tokens. A token with FTRC bit = 1 which
reinitializes the OIV instruction is deleted from the
output token stream. A OIV instruction with CS = 3 is
illustrated in figure 15. The 10th and 16th input tokens
have FTRC bit = 1, so they reinitialize the OIV
instruction.
FTRC=O
IN1
FTAC=l
IN.
(
16
10
CS=3
I
DIV
ID
10
+1
Note: Tokens [10] and {16] are deleted
49·000094A
DIV Instruction Field Formal
FTT
FTR
1211
15
,
1
0
1
1
:
o9
87
Count Size leS]
'I
8 7
,
,
,
S/FI, - I
Counter Ic]
49-00009BA
21
t\'EC
JlPD7281
DIST [Distribute 1
Figure 16.
DIST is used to divide a stream of incoming tokens
with the same 10 into more than one stream of tokens
with different IDs (see figure 16). The ~IO size
determines the maximum number of output token
streams the instruction can have. ~IO is the value
added to an incoming token's 10 field to form the 10
field of the output token. The ~IO field is initially set to
zero, and it is incremented by one after a token with
FTRC bit = 1 passes through the instruction. However,
a token with FTRC bit = 0 has no effect on the value of
~IO field. If the value of ~IO before being incremented
by a token with the FTRC bit = 1 is equal to the
contentsofthe ~IO size field, the ~IOfield will be reset
to zero.
DIST Instruction
Inltl.'8t8te:~ID = 0
When6'DSlze=3
FTRC~O
FTRC~1
es, or when S/F = 1, C - C+l,
token not deleted
... _-_ .. _- ..... _-_._-_ .. __ .... __ .. __ .. _-_ .. _----_._-_._-_. __ .__ .---------.---------- ....................................
0
..........
S/F - 0, C - 0, token deleted
When C:s CS, C - C + 1; when C> CS, distribute,
..Q=Q.±.1;..~.=Q:\AI.~~~.~"".Q§.'.~ .._:::~...
1
C - C + DATA, token deleted
0
1
When S/F=O and C:s CS, C - C+l; when S/F = 0
and C> CS, or when S/F = 1, distribute, C - C + 1;
.................... ......... ...........
S/F - 0, C - 0, token deleted
0
ID - (ID + AID) modulo AID size
1
(4)
When "ID '" ,,10 size, ID-(ID+AID) modulo AID size,
AID - AID + 1. When AID = AID size, AID - 0
counterl
(7)
(1)
When CS '" C, 10 -10 + C (modulo 2), C - C + 1;
when CS = C, ID -10 + 2, C - 0
Count Size
S
I (1)
Counter
(8)
F
(8)
0 0 1 0 (8)
(DMB
+ WC) - DATA, we - wc + 1, delete token
_-_. --_ .. __ .......
_........
0
(2)
AID
Size
(DMB + WC) - DATA, we - wc + 1, when BS = WC,
token not deleted
1
1
DIVCYC
(DMB + WC) - DATA, WC - WC + 1, delete token
.. __ .. _--_ ....... __ .. __ . __ ... __ ... __ ............
(AR) (8)
(2)
Count Divide
Size Size (2)
(4)
(4)
Operation
FTRe
(II
.......... ................................................................
.......... ...................................
(6)
(4)
CONVO
1 1 1 1 (4)
Count Size
(8)
(2)
SAVE
0 1 1 0
(12)
(2)
CNTGE
1 1 1 0 (4)
Count
Size
(8)
W
I (1)
0
AID
10 Stack Register
0
IDSR - Lower 8-bit of DATA
(8) (IDSR)
1
10 -IDSR
Counter
0
When dead, ID -ID + 2; when wait, if C = CS, C - 0,
WID = 0; when wait, if C'" CS, C - C + 1
1
When dead, initialization; when wait, delete token
(8)
25
NEe
pPD7281
PU Instructions
131211
FTLlielO
IFlLI~1
109
OUT
8 7
1~lil
6
54
PNZ
I
3
2
OP
1
0
I
F/L: Full/Lett
XCH: Exchange
OUT:Output
SRC: Branch Control
CNOP: C·Bit NOP
PNZ; Positive, Negative, or Zero
OP: Op code
XCH [Exchange]: This bit controls the exchange
operation. Operands will be exchanged just before the
two tokens enter the QUEUE when XCH = 1.
OUT [Output]: There are four different PU output
token formats. The two OUT bits specify the output
token format. See table 11.
Table 11.
OUT Bits
First Output
DATA"C,S
10
10
X1
01
1
ID
y2
10
2
10
X
ID + 1
X
11
2
10
X
ID + 1
Y
00
49-000109A
PU instructions (see table 20) are stored inthe Function
Table Left field of the Function Table memory. The bits
o through 11 are used as control information for the
Processing Unit. The bits 12 and 13 are deleted before
the token arrives at the Processing Unit. Two operands
from the A and B sides are operated on by the
Processing Unit and the result is output to the X and Y
sides (see figure 19).
Figure 19.
The Processing Unit
AS,ide
8 side
Second Output
DATA,C,S
No. of Outputs
OUT Bits
Notes: 1, This is
side, It
2. This is
side. It
10
the 18-bit result of the operation output to the X
includes the Cx and Sx bits.
the 18-bit result of the operation output to the Y
includes the Cy and Sy bits,
BRC [Branch Control]: The BRC bit controls the flow
of the PU output data token. The output data token
may be output to either the I D token stream or the
I D + 1 token stream. When the BRC bit is set to 1 and
the C bit of the PU output data token is also 1, the output
data token is sentto the ID + 1 token stream. Butwhen
the BRC bit is set to 1 and the C bit of the output data
token is 0, the token is sent to the ID token stream.
Therefore, using the BRC bit implements a conditional
branch on C.
CNOP Bit: This bit informs the ProceSSing Unit whether
or not the incoming token should be processed. If the
CNOP bit is set, and the CA bit is not equal to the CB bit,
then the token passes through the Processing Unit
with no operation performed. See table 12.
Table 12.
CHOP Bit
PU Operation
o
o
o
49-000110A
Bit Assignments
F/L [Full/Left]: F/L bit = 0 indicates that the PU
instruction is a one-operand instruction, and only the
Function Table Left field is meaningful. F/L bit = 1
indicates that the PU instruction is a two-operand
instruction, and both the Function Table Left field and
the Function Table Right field are meaningful. Therefore,
when F/L bit = 1, the PU instruction is used in
conjunction with an AG/FC instruction.
26
Processing specified by the OP code is
performed.
Token passes through the Processing Unit as
NOP.
o
Token passes through the ProceSSing Unit as
NOP,
Processing specified by the OP code is
performed,
PNZ [Positive, Negative, Zero] Field: The PNZ field is
used to test the resulting condition of the PU operation.
If the resulting condition matches the condition set by
the PNZ field, then the C bit of the output data token is
set to 1. See table 13.
ttlEC
Table 13.
PNZ Field
p N Z
0 0
Condition
0
0
Cx
o No condition set
Cy
1
1
Result of operation.., 0
0
0
o Result of operation < 0
1
1
Result of operation;:, 0
0
0
1 Result
of operation ~ 0
-----_._-_ .... __ .. __._ .......
Result of operation> 0
1
0
Result of operation ~ 0
0
1
1
0
0
o-_Result
of operation.., 0
1 1
..... ............ ......... _-_ ............ ............. -_ ......
__
__
1 Overtlow generated
0
0
1
1
0
0
.... -............ _--......... _.. -.- ..........................
No overflow generated
LT
Table 14.
OP Code Field
Mnemonic
Dpcode
OR
00000
False
AND
00001
True
XOR
00010
False
ANDNOT
00011
True
NOT
01100
ADD
11000
True
False
GT
0
Result of operation < 0
Result of operation = 0
EQ
0
0 1 Result of operation;:, 0
OP Code Field: This 5-bit OP code field specifies the PU
operations to be performed. See table 14
InstructloR
LE
o Result
of operation> 0
------_ ....... _-_ ..........._----_ ......... ------_ ... _-----_ .. _-_.-
__
Assembler
Description
CA CB
=0
0 0 1 Result of operation
0
pPD7281
Logical
Arithmetic
True
ADDSC
False
GE
NE
OVF
11001
True
SUBSC
11101
False
MUL
11010
True
MULSC
11110
False
NOP
11011
True
NOPSC
11111
False
INC
01010
Shift
DEC
01011
SHL
00100
SHLBRV
00101
SHR
Compare
Bit manipulation
00111
CMPNOM
01000
CMP
01001
CMPXCH
10001
SET1
Bit check
Data conversion
00110
----- .... -----.----- ... __ .. -.
SHRBRV
GET1
10101
._----------_ .. _-------_ ........
10110
._----------_ .. _-----------
CLRl
10111
ANDMSK
._-_._-_ ...... __ ._-_ ....
01101
ORMSK
10000
CVT2AB
01110
--------_ ....... _-------
CVTAB2
01111
Double precision adjust
ADJL
10100
Accumulative addition
ACC
10010
COPYC
10011
C bit copy
•
11100
SUB
._------_. __ .... __ .__ ._--_ .....
27
!
t\'EC
pPD7281
Logical Instructions
These instructions perform 16-bit logical operations
on DATAA and DATAs. Usually there are no changes
in C and S bits between the input token and the output
token, however C bits can be affected by PNZ condition
when specified.
OR, AND, XOR: These instructions perform 16-bit
logical OR, AND, and XOR operations using input data
tokens from the A and B sides of the Processing Unit.
The 16 bit result is output to the X side.
ANDNOT: This instruction first complements DATAA
and then performs logical AND operation with DATAs.
The 16-bit result is output to the X side.
NOT: This is a one-operand instruction which requires
16-bit data input from the A side only. The B side input
is ignored. This instruction complements the 16-bit
input data from the A side. The 16-bit result is output to
the X side.
the number of zeros as DATAy (see table 15). These
instructions are provided for easy floating point
processing.
ADDSC, SUBSC, NOPSC: These instructions perform
addition, subtraction, or no operation. The number of
preceding zeros in DATAx of the result is output as
DATAy. If an overflow oran underflow occurs as a result
of an operation, DATAy contains + 0001 H (Sy = 0) or
-0001 H (Sy = 1), respectively.
MULSC: This instruction performs a normal multiplication operation using the two 17-bit data. The
upper order 16-bit data and its sign bit are output as
DATAx and Sx, but the lower 16-bitdata is not output as
DATAy. Instead, the number of preceding zeros in
DATAx are counted and output as DATAy. The Sy bit is
always zero.
Table 15.
Shift Count Operation
se Output (Y)
DATAX Altar Operation
Arithmetic Instructions
15 14 13 12 11 10 9 B 7 6 5 4 3 2 1 0
These instructions perform 17-bit (including the sign
bit) arithmetic operations on DATAA and DATAs. When
a PNZ condition is specified, the C bits of output data,
Cx and Cy, reflect the setting. However, if no PNZ
condition is specified (Le., PNZ = 000), then Cx - CA
and Cy - Cs.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ADD, SUB: These instructions perform addition or
subtraction on DATAA and DATAs along with the sign
bits, SA and Ss. The result is output to the X side.
DATAy is normally OOOOH. However, if an overflow
occurs, then DATAy is equal to +0001H (Sy = 0). If an
underflow occcurs, then the DATAy is equal to - 0001 H
(Sy= 1).
MUL: This instruction multiplies DATAA and DATAs.
The correct sign bit for the product is determined from
SA and Ss. The 33-bit result including a sign bit is
output as two 17-bit words, Sxand DATAx, followed by
Sy and DATAy. DATAx is the upper 16-bit word and
DATAy is the lower 16-bit word. Sx holds the resulting
sign bit, and Sy is a mere duplicate of Sx.
NOP: This instruction performs no operation on the
input token. The input data from A and B sides are
output to the X and Y sides, respectively, without any
change in their contents. If any control other than the
OP code (such as PNZ control, BRC control, etc.) has
been specified, the output complies with the control.
Shift Count Instructions
These four Shift Count (SC) instructions first perform
the normal operations, then count the number of
leading zeros in DATAx of the result, and finally output
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
x
1 x x
x x x
x x x x
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
x
x x
x x
x x
x x
x x
x x
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
x
x x
x x x
x x x
x x x
x x x
x x x
x x x
x x x
x x x
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
Sy
Y Oata
0 0 0 0
0 0 1 0
0 1 x 0
1 x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
x x x 0
o0 1
000
o0 0
o0 0
0
F
E
D
0 0 C
000 B
o0 0 A
o0 0 9
000 8
0 0 7
0 0 6
0 0 5
004
0 0 3
0 0 2
000 1
000 0
o
o
o
o
o
o
o
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H*
Notes: • When an overflow or underflow has occurred
x don't care
Increment and Decrement Instructions
INC, DEC: These instructions increment or decrement
the 17-bit data from the A side (SA and DATAA), and
outputs the result to X side as Sx and DATAx. The Sy
and DATAy are normally zero. However, if an overflow
or an underflow occurs, then the Y side outputs + 0001 H
(Sy = 0) or - 0001 H (Sy = 1), respectively.
Shift Instructions
SHR [Shift Right], SHL [Shift Left]: SHR or SHL
instructions perform a barrel-shifting operation on the
16-bit data, DATAA. The actual number of shifts and
the direction is further specified by the lower five bits
of DATAs and Ss, respectively. See figure 20 for
detailed operation explanations.
r-lEC
Figure 20.
JlPD7281
SHR and SHL
Left Shift [SHl execution]
Righi ShilllSHR execution]
Lower 5 bits
Sa of DATAB
lowerS bits
DATAy
DATAx
Sa of DATAB
[No.ol shilts]
o
00000
I
o
00001
[0]
o
0001 0
10 0 I
0 ...0
A1SA14· .. A1AO
0 ... 0
A1SA14 ...Al
0 ... 0
A1S ...A2
0...0
o
001 00
o
00101
o
00110
o
00111
o
01000
o
01001
o
01010
o
01011
o
01100
o
01101
o
01110
o
01111
o
lXXXX
0... 0
A1S... AlI
0•.. 0
A15. .AS ~ I A, . .Ao I
~
~A;:S=. ~."'::::':::;:::=:::;O.=. O;==~
0 ... 0
0... 0
A15 ...
0... 0
0 ... 0
A15 ... A7
~==:;:=====~
A6 ... AO
0 ... 0
~=0=. =.0=~==A='=S.=.A=8~ ~=A=7.=.A=O==~==0=. .=0=~
~=====;~~
~=====::::;::=~
0 ... 0
A1S ... Ag
As .•. Ao
0 ... 0
Ag ... AO
0 ... 0
0•.. 0
0 ..•0
0 ... 0
0 ... 0
1 0 ...0
0 ... 0
0 ... 0
0 ...0
001 00
Al1 ... Ao
1r:1
0... 0
A1D ... AD
00110
0 ... 0
A6 ...AO
01100
JA3...
0 ... 0
o1101 IA,"'I
01110
I~~I
01111 itI
1 XXXX
0 ..•0
A1S ... A,
o
00100
o
00101
o
00110
o
00 111
o
01000
o
o
01010
01001
o 01 11
o 01100
o 01101
o 01110
A1S ... As
1001
1
0 ... 0
A12 ...Ao
0... 0
I
0 ... 0
0 ...0
0...0
Al0... Ao
0... 0
~::;:=~~
Ag ... Ao
0 ...0
~==::;~~
0 ...0
~~==Aa=
. .=AO=:;::==O=.=.O=~
0 ...0
0 ... 0
0 ... 0
A7 ... AO
~=::::;=:=;:::;=~
~=A='.=. A=O~====O=. .=O=~
As...Ao
0 ...0
0 ... 0
0 ...0
~I=A='.=.A=O:I;::::==o=. .=o==~
~IA=3:. .A=O~I~===0.=. 0==~
0 ... 0
0 ...0
0.. 0
0...0
00000
1
00001
[o[
I~I
A15A14 ... Al
01
00011
0..,0
01000
0... 0
A1SA14..,A1Ao
00010
I
0 ... 0
A1S ... A4
0 ...0
A1S...As
A1S... ~
0 ... 0
0 ... 0
As ... Ao
A15 ...A7
0...0
As ... AO
A15 ...Aa
A7 ... AO
A15.. ~
0..,0
I A15. .A I
01011
0 ... 0
IA15..,Al1I
0. .0
011 01
01110
0. .0
01111
UXXX
0 ...0
Als..·Aa
0. .0
0 ... 0
0 ... 0
I~~I
A15..,A2
01010
011 00
49-000137C
A13. .AO
1 XXXX
0 ...0
0•.. 0
0 ... 0
0 ...0
IA'·Aol
0. .0
I I
~I~~~:;:I====O=. =.O===~ 1001
o 01111 ~~=====O.=. O===~ [01
01001
0 .•.0
0. .0
Aol
00011
00111
0 ... 0
As... Ao
01011 I A,. .Ao I
00010
o
00110
0 ... 0
A7 ... AO
01001
o
o0 1 0 1
0 ..•0
~
01010
00001
00100
0 ..•0
Ag •.. AD
01000
00000
o
o
0... 0
00101
o
0
0•..0
0 ...0
0 ...0
00111
DATAy
DATAX
[No.olshiHs)
lO
0..,0
~
. .O
0 ...0
0 ... 0
0 ... 0
IA15..A121
1~5·~31
As ... Ao
Ag ... AO
Al0 ... AO
All ... Ao
A12 .. · A O
0 ... 0
0 ... 0
0 ... 0
0... 0
0 ...0
0 ... 0
0 ...0
1 0 ... 0 I
~
Iij1
I
49·00Q138C
29
NEe
pPD7281
SHRBRV [Shift Right with Bit Reverse). SHLBRV
[Shift Left with Bit Reverse): SHRBRVorSHLBRV first
reverses the order of the bits in DATAA and then
performs a normal SHR or SHL operation, respectively.
See figure 21.
Figure 21.
Bit Reversal Operations In SHRBR V and
SHLBRV
MSB
LSB
Before
A'51413121110987654321Ao
Compare Instructions
The Compare instructions (see table 16) are different
from other PU instructions in that PNZ conditions
must be specified along with the instructions. When a
compare instruction is used along with a specified
PNZ field, the Processing Unit performs a subtract
operation. This subtract operation produces a set of
PNZ flags, which are compared against the PNZ field
specified by the instruction. When these two PNZ
fields coincide, the specified PNZ conditions are said
to be true. When they do not coincide, the specified
PNZ conditions are said to be false (see table 17). The
output data from the Processing Unit differs significantly depending on the PNZ conditions. The following
three instructions compare the 17-bit data (SA and
DATAA) from the A side against the 17-bit data (Ss and
DATAs) from the B side.
MSB
LSB
A01234567891D11121314A,s
After
49-000318A
Table 17.
PNZ Field Conditions for Compare
Instructions
PNZ
Condition
True/
False Func;tion
o 0 1 SA DATAA = S8 DATA8
SA DATAA'" S8 DATA8
o 1 0 SA DATAA < S8 DATAB
SA DATAA;::: S8 DATA8
Mnemonic
True Equal
EQ
False Not equal
True Less than
LT
False Greater or equal
o 1 1 SA ......................................................
DATAA ~ S8 DATAB
True Less or equal
-------_ .. _--------_.SA DATAA> S8 DATA8
CMPNOM [Compare and normalize): If the specified
PNZ conditions are false, then the control bits, sign
bits and data for both the X and Y sides are set to zero.
If the PNZ conditions are true, then Cx and Cy are set
to one, Sx and Sx are set to zero, DATAx is set to
0001 H, and DATAy is set to OOOOH.
1 0 0 SA DATAA > S8 DATA8
CMP [Compare): This instruction outputs the 17-bit
data words from the A and B sides to the X and Y sides
without any change in their contents. It only alters the
control bits. If the specified PNZ conditions are true,
then Cx and Cyare set to one. If the PNZ conditions are
false, then Cx is set to one and Cy is set to zero.
SA DATAA = S8 DATAB
LE
False Greater than
True Greater than
GT
False less or equal
1 0 1 SA DATAA;::: S8 DATAB
SA DATAA < S8 DATAB
1 1 0 SA DATAA .., S8 DATAB
True Greater or equal
GE
False Less than
True Not equal
...... --.. -.............-.._- ... -......-..... -....-...............................................
NE
False Equal
Note: The significance of the PNZ bits when Compare instructions
are executed differs from that of other instructions. Here, the
use of PNZ = 111 or 000 is prohibited.
CMPXCH [Compare and exchange): If the specified
PNZ conditions are true, then both the input data from
the A side and B side are unchanged and output to the X
side and Y side, respectively, including their sign bits
and the control bits. However, if the PNZ conditions
are false, then the input data from the A side is
exchanged with the input data from the B side, including the control and sign bits.
Table 16.
Compare Instructions
CMP
CMPXCH
30
Notes
S8
B
0
o
.DATAX
OOOOH
o
DATAy
OOOOH
CA
SA
A
C8
S8
B
1
0
0001 H
1
0
OOOOH
When PNZ is true
CA
SA
A
C8
S8
B
0
SA
A
0
S8
B
When PNZ is false
CA
SA
A
CB
S8
B
SA
A
S8
B
When PNZ is true
. .CA~.~. . . .~~SA. . . . . .~A . . . . . .C8c.~. . . . S8s.~. . . . . . ~B. . . . . . c.~C8. . . . s.~S8. . . . . . ~A. . . . . . CA~.~. . . . S8~.8
A
CA
CMPNOM
Output
Input
Mnemonic
SA
DATAA
Ca
A
C8
CA
SA
..................................
-......... -.-- ....
Sa
DATAa
eX
Sx
Cy
0
Sy
When PNZ is False
..................................-- .. -- .... ---- .... -----------_ ......................................-.-----.-.--------.----------.--_._-----.-----_._-----_. __ .. _---_ ..............................................._-_ ....... _-.-.---- .. ............ ~.....................~~.~.~..~~.~.!~.!.~~~
...........................
When PNZ is false
ttt{EC
j1PD7281
Bit Manipulation Instructions
GET1 [Get one bit]: This instruction is used to read a
particular bit from DATAA (see table 18). A bit of DATAA
specified by the lower 4 bits of DATAB is output as the
least significant bit of DATAx. All other bits of DATAx
are set to zero. DATAy is also set to zero. The control
bits and the sign bits of DATAx and DATAy are as
follows: Cx - CA, Cy - CB, Sx - SA, Sy - O.
SET1 [Set one bit]: This instruction is used to set a
particular bit of DATAA. The bit of DATAA to be set is
specified by the lower 4 bits of DATAB. After the bit is
set, the 16-bit result is output as DATAx. DATAy is
always output as zero. The control bits and the sign bits
of DATAx and DATAy are as follows: Cx - CA, Cy - CB,
Sx - SA, Sy - O.
CLR1 [Clear one bit]: This instruction is used to reset a
particular bit of DATAA. The bit of DATAA to be reset is
specified by the lower 4 bits of DATAB. After the bit is
reset (cleared), the 16-bit result is output as DATAx.
DATAy is always output as zero. The control bits and
the sign bits of DATAx and DATAy are as follows: CxCA, Cy - CB, Sx - SA, Sy - O.
Table 18.
3
D
DATAA Bit Position
0
0
0
0
Bit Addressing
DATAa Bit
2
1
0
0
0
1
----"
0
1
0
0
0
0
7
0
0
ORMSK [Mask a word with logical OR]: This instruction
tests certain bits in DATAA. The bits in DATAA to be
tested are first masked with a bit pattern in DATAB.
Only those bits in DATAA corresponding to the one bits
of DATAB are considered. Then only those masked bits
of DATAA are ORed together to set or reset the control
bits, Cx and Cy. If the result of the OR operation is 1,
then both Cx and Cy are set to 1. If the result of the
operation is 0, then the both Cx and Cy are set to O. The
rest of the output data fields are the following: Sx - SA,
Sy - SB, DATAx - DATAA, DATAy - DATAB.
Data Conversion Instructions
CVT2AB [Convert two's complement to sign-magnitude]:
This instruction converts a 16-bit number in two's
complementform to a 17-bit number in sign-magnitude
form. The sign of the two's complement number is
output as the Sx bit.
CVTAB2 [Convert sign-magnitude to two's complement]: This instruction converts a 17-bit number
in sign-magnitude form to a 16-bit number in two's
complement form. This operation has the potential
danger of an overflow or an underflow. If an overflow or
an underflow occurs, the C x bit is set to 1.
Double Precision Adjustment Instruction
6
0
of DATAA are ANDed together to set or reset the
control bits, Cx and Cy . If the result of the AND
operation is 1, then both the Cx and Cy are set to 1. If
the result of the operation is 0, then the both Cx and Cy
are set to O. The rest of the output data fields are the
following: Sx - SA, Sy - SB, DATAx -DATAA, DATAyDATAB·
ADJL [Adjust long]: This instruction is used to adjust a
double precision number, in which the sign bits of the
upper and lower words are different. This situation may
occur after a double precision arithmetic operation.
The examples in table 19 illustrate the adjustments of
double precision numbers.
0
1
10
Table 19.
11
0
12
0
13
Input
Output
14
15
Bit Check Instructions
AN DMSK [Mask a word with logical AN D]: Th is i nstruction tests certain bits in DATAA. The bits in DATAA to be
tested are first masked with a bit pattern in DATAB.
Only those bits in DATAA corresponding to the one bits
of DATAB are considered. Then only those masked bits
Double Precision Adjustment Examples
Input/Output
Input
Output
Input
Output
High (A data)
Low (8 data)
High (X data)
Low (Y data)
Sign
Data
0
0
0
0
1234H
5678H
1234H
5678H
High (A data)
Low (8 data)
High (X data)
Low (Y data)
1234H
5678H
1233H
A988H
High (A data)
Low (8 data)
High (X data)
Low (Y data)
1234H
5678H
1233H
A988H
31
Ell
!
NEe
pPD7281
Figure 22.
Accumulative Addition Instruction
ACC [Accumulate): This instruction (see figure 22)
performs cumulative additions of incoming tokens'
data fields. The incoming tokens are classified into
type 1 and type 2 tokens. A type 1 token is deleted after
the ACC operation, but a type 2 token is not. Moreover,
a type 2 token reads the contents of the ACC register,
which contains the accumulated sum of tokens. When
a type 2 token reads the contents of the ACC register,
the I D field of the token is unchanged. However, if an
overflow has occurred prior to the arrival of a type 2
token, the ID field is incremented by one. Only the
following three tokens qualify as type 2 tokens.
1. If the ACC instruction is used along with RDCYCS
instruction, and the token's FTRC bit = 1, and the
Buffer Size and Read Counter of RDCYCS instruction
are equal.
2. If the ACC instruction is used along with RDCYCL
instruction, and the token's FTRC bit = 1, and the
Buffer size and Read Counter of RDCYCL instruction
are equal.
3. If the ACC instruction is used along with COUNT
instruction, and the token's FTRC bit = 0, and the
Count Size and Counter of COUNT instruction are
equal.
ACC Instruction
All Type 1 TOkensl
:~
~~
B, Sx =
OOOOH
A- 8
B
B
°
OOOOH
Cx
Cx
11010
°
When A ~ B, Sx = 1
..... ::...........O
..........B
....-... A
........ Cy:..........o..............O
..O
..O
..O
..H
....... W
....h..e..n. A < B, Sx = 0
A - B Cy
OOOOH
When A ~ 8, Sx = 1
Cx
B
CB
When A < B, Sx =
Cy
B
WhenA-
------------------------------------~~
--------------------------------------~<
High Data
X
Low Data
Notes: (1) ~ = Output enable
(2] Internal signal
3. 8BIN 1, HALFIN 0
=
=
49-0012898
22
NEe
ILPD9305
Figure 10. Output Timing (pPD7281 to pPD9305 to Host)
INR
HL register (8)
INR
HH register (8)
Latched
INR
LL register (8)
INR
LH register (8)
CPURQ
~~------------------------------------------------------------
lOB
---~~
Notes: [1) ~= Output enable
2. 8BITOUT 1. HAlFOUT 0
=
=
49-0012868
Figure 11. Output to pPD7281, Control Data Paths
081S- IDBo
•
(2)
(3)
(4)
FIFO
015- DO
IF
(2) (3)
HWR
,
(2)
(3)
(4)
Note:
~)
(2)
(3)
Data from hoBt
Dat. Ifom 1••timPP
Irnaaa momary read do..
(4) Solf object load datI
49-0012828
23
t\'EC
jtPD9305
Figure 12. pPD7281, Input Control Data Flow
WDR1(1S)
WHAR1(S)
RHAR1(S)
J
(4)
Note:
(1) Reter to Table 3 for
token type definitions
49-0012908
24
NEe
JlPD9305
Figure 13. Image Memory Read Timing (Without Refresh Request)
IREO
108(16)
Memory Access
Request Internal
Flag _ _ _ _ _ _ _ _ _- - - '
~'-----
elK
IMRD
IMA(2')
49-0012918
25
t\'EC
j.tPD9305
Figure 14. Image Memory Write Timing (Without Refresh Request)
Memory Access
/
Request Intemal
Flag _ _ _ _ _ _ _ _ _ _- J.
.elK
IMWR
IMA(2')
IMD(tS)
« <<<( <( <( <<<( <<<<( <
Image
Me~JrY
Data
»»»)
4!Hl01292C
26
t-iEC
J.tPD9305
Figure 15. Image Memory Access Request Priority Control
Memory Access
Request Token
~
Memory Access
Request Internal
Flag _ _ _ _ _ _ _ _ _ _ _ _..J
Memory Refresh
Request Internal
Flag _ _ _ _ _ _ _ _....J
•
elK
IMAD
OR
e-___
IMWR _ _ _ _ _ _ _ _ _ _ _
~~----~_+--~--------J
IMRF
49-0012938
27
I
t\fEC
p,PD9305
Figure 16. Read Data - #PD7281 Output Timing (Single Output)
108(16)
Memory Access
Request Intemal
Flag
_ _ _ _ _ _ _ _ _ _ _ _- 1
CLK
IMRD
IMO(18)
OREQ
DACK
28
2t-{
)
::
~
49-001294C
t-iEC
IIPD9305
Figure 17. Read Data - pPD7281 Output Timing (Continuous Output)
Memory Access
Request Internal
F109 _ _ _ _- '
elK
Refresh Request
Internal Flag
IMRF
IMRD
:::--------------------------------~ ~ ~
Refresh
Read 1
Read 2
Read 3
49-001299C
29
NEe
pPD9305
Figure 18. Self Object Load Timing
SOL Start
Request Token
L
Internal Flag
Showing SOL
------¥
IMA _ _ _ _ _ _ _--{
eLK
IMRD
DR~~----------~
XJXJ
DACK
0\~--
"VJ
Notes: [11 When OACK is not returned, the ,...PD9305 can retain up to two tokens. (H2)-L2 and
H3~L3 tokens). IMAD will not become active until the token is output.
2.lf a refresh request is generated during execution of self object toad, refresh is
given priority.
49-0013OOC
Figure 19. Refresh Timing
CLK
IMA9-0
Internal Flag
Showing
Refresh Request
IMRF
4(J..001295B
30
t-{EC
pPD9305
Figure 20. Read/Modify/Write Timing
Internal Flag
Showing
R/M/W
Request -----------~
elK
IMRD
..
IMWR
Table 5 shows the differences between command and
external resets.
Figure 21 shows a typical system configuration using the
ILPD9305 with several ImPPs.
Table 5. Command and External Reset
Differences
Item
RESET
Commmand Reset
1/0 data counter; Tokens in the pPD9305; Cleared
image memory access requests (except
refresh); OREQ, lACK; DMA request
Cleared
Refresh timer; refresh request; refresh
address; mode register
Default
values
No change
IPPRST pin
o(active) o(active)
Figure 21. Typical System Configuration
Image
Memory
~
m
~
.,
w
~
m
E
i
4~
't
I
~, ,~
, - - _ .... _ - - ,
:
I
I
DMAC
~----~
IL _ _ _ _ _ _ JI
49-0012966
31
pPD9305
32
t\'EC
NEe
Speech Processors
ttlEC
Speech Processors
Section 4
Speech Processors
"P077C30
4a
ADPCM Speech Encoder/Decoder
lIP 077 55/56/P56/57/58
4b
ADPCM Speech Processors
"P07759
4c
ADPCM Speech Processor
"P077501
4d
ADPCM Record and Playback Speech
Processor
pP077522
ADPCM Codec
4e
NEe
I1PD77C30
ADPCM Speech
Encoder/Decoder
NEG Electronics Inc.
Description
The /1PD77C30 is a large-scale integration (lSI) singlechip digital processor, which compresses and decompresses digitized speech signals. It is a speech
encoder/decoder that converts pulse code modulated
audio to and from adaptive differential pulse code
modulation (ADPCM). The /1PD77C30 encodes pulse
coded modulation (PCM) data into ADPCM data, and
decodes ADPCM data into PCM data. The /1PD77C30 is
ideal for office automation applications, such as voice
store and forward systems, and for various telecommunication applications. It reduces voice transmission
bandwidth and voice storage requirements by half
(from 64 kb/s to 32 kb/s). Its robust ADPCM algorithm
makes it well qualified for transmission applications
and the fact that it compresses speech by half makes it
suitable for store and forward applications.
The maximum clock (ClK) frequency for the /1PD77C30
is 8.33 MHz, which corresponds to a ClK cycle time of
120 ns.
The /1PD77C30 accepts PCM data through its serial
interface. The serial interface can be connected directly to a single-chip coder/decoder (codec) for digital
/1-law PCM input/output or to a general purpose AID or
D/A converter for linear PCM code. This programmable
serial interface supports both 8-bit logarithmic (p-Iaw)
and 16-bit linear formats. The /1PD77C30 interfaces to
the host CPU through a standard microprocessor bus
interface.
If a clock frequency of 8.33 MHz is used to encode PCM
data, then the /1PD77C30 requires 116 /1s to process
each sample, thus limiting the sampling frequency to
8.59 kHz. This implies that if the sample frequency is 8.0
kHz and the ClK is 8.33 MHz, then the internal algorithm will take approximately 93% of the time between
samples. Serial data being shifted in or out has the full
time between samples to accomplish the transfer of the
data. This is because there is an internal buffer that is
separate from the shift register and the serial input is
internally read at the rising edge of the sample clock,
while the next value is starting to be shifted in.
When the /1PD77C30 operates in the sample 4-bit encode mode, it never outputs the value OOH. However,
when it is in the sample 4-bit decode mode, it can
accept OOH as an input value and interpret it the same
as an input value of 88H.
50162-1
The /1PD77C30 performs as an intelligent peripheral
device and is controlled and programmed from the
host processor. The /1PD77C30 offers toll quality (equivalent quality to 56 kb/s /1-law PCM) speech meeting the
CCITT recommendations G.712.
The /1PD77C30 has an A-law version designated the
/1PD77C31, which is available for products marketed in
Europe.
Features
o Half-duplex ADPCM encoder or decoder
o Compression data rate
-32 kb/s/8 kHz sampling/4-bit data
- 24 kb/s/8 kHz sampling/3-bit data
o Byte data (2 x ADPCM data) handling
o Robust adaptation scheme for quantizer and
predictors
o Selectable functions
- Encoder/decoder operating mode
- ADPCM data length 3 or 4 bit
-A/D and D/A conversion /1-law or linear
o Presentable voice detection threshold
o Standard microprocessor interface to the host CPU
o Easy interface to PCM combo
o Toll quality speech at 32 kb/s (meets CCITT
recommendations G.712)
o Single +5-volt power supply
o low-power CMOS technology
o Clock frequency 8.192 MHz maximum
o Packages: 28-pin plastic DIP and 44-pin PlCC
Ordering Information
Part Number
Type
Package
IlPD77C30C
CMOS
28-pin plastic DIP (600 mil)
L
CMOS
44-pin PLCC
NEe
pPD77C30
Pin Identification
Pin Configuration
2B-Pin Plastic DIP
NO
PU
Symbol
I/O
Function
DET
Out
Signal detect: This output is asserted when
the input audio signal level exceeds the
threshold level specified.
DRa
Out
Data request: This output requests data
transfer between the pPD77C30 and host CPU.
In encoder mode, an ADPCM data read is
requested. In decoder mode, an ADPCM data
write is requested. (DRa will not work unless
encoder or decoder mode is specified). The
data request status can also be checked by
polling the ROM bit of the status register.
VOO
Ao
Cs
10
ORa
RO
WR
SORa
SO
SI
SOEN
SIEN
SOK
SMPl
RST
OlK
DET
DO
01
02
03
04
05
06
07
GNO
48f'B0401A
RD
In
Read signal: This input controls data transfer
from the IlPD77C30 to the host CPU.
WR
In
Write signal: This input controls data transfer
from the host CPU to the pPD77C30.
A/D-D/A Interface
SCK
In
Serial clock: This input provides timing for
transfer of serial data to/from the A/D and D/A
converter.
SI
In
Serial input: serial data input.
SIEN
In
Serial input enable: This input enables data
transfer on the SI pin. If not used, tie to SOEN
SIEN must be asserted for the IlPD77C30 to
44-PinPLCC
SOK
SMPl
NO
RST
OLK
NO
GNO
GNO
NO
Cs
Ao
NO
Vee
Vee
0
NO
PU
10
07
06
ORa
NO
NO
O,...C'\I(II)"'LC)tD""
,...,(Dm,....
............ ,...,...,..,....
oZc
t:;
6'0
Z
c CCCZCZ
100
C\I ('I) ~o
recognize an operation command.
SO
Out
SOEN
In
SORa
Out
Symbol
I/O
AO
In
Address 0 (regisler select): This input selects
internal registers. A high input selects the
status registers. A low input selects the data
registers.
D?" Do
I/O
Data bus: This three-state bidirectional data
bus interfaces with the host CPU data bus.
CS
In
Chip select: This input enable the RD and WR
signals.
2
Serial output request: This output indicates
that serial request output data is ready for
transfer at the SO pin.
Circuit Control
In
Clock: 8.192 MHz TTL clock input.
GND
In
Ground.
IC
Internal connection: This pin is connected
internally and should be left open.
NC
No connection: This pin is not connected.
Pullup: Pull this pin up to VOO'
RST
In
Reset: A high input to this pin initializes the
pPD77C30.
SMPl
In
Sample: This input determines the rate at
which the IlPD77C30 processes ADPCM data.
This rate must equal the sampling clock of the
AID and D/A converter. SMPl must be active
for the IlPD77C30 to recognize an operation
command.
VOO
In
+5-volt power supply
Function
Host System Interface
Serial output enable: This input e!lables data
transfer on the SO pin. If not used, tie to SIEN.
ClK
PU
Pin Identification
Serial output: Serial data outp·ut.
t-IEC
pPD77C30
Block Diagram
IVD-DIA
PCMfADPCM
I~~=erl~·~------~~(
so l22l---------I nterface ~----------~I =~ ~----------~II smru.1140(~------~~(
~glster
SOEN
.....
--------~('
SORQ 123l~---------1
0(
Host CPU
Interface .....--------~.
•
1.....-----------(;!5) AD
r-______~~ICOntrolle'l-o(o(----------------------------'---.. 1
1+-----------(;14] WR
1+---------Il!6l CS
1.....- - - - - { , 2 7 } Ao
FUNCTIONAL DESCRIPTION
The pPD77C30 has the following functional units:
• A/D-D/A interface
• PCM/ADPCM encoder/decoder
• Controller
• Data register
• Status register
• Host CPU interface
The ADPCM method is a medium bandwidth coding
technique that represents speech waveforms. The specific ADPCM used employs a robust adaptation
scheme for a quantizer and predictor to withstand
transmission bit errors. Figure 1 shows the block diagram of the algorithm. The algorithm uses a backward
adaptive quantizer and a fixed predictor so it never
generates unstable poles in a'decoder transfer function. This approach guarantees the stability of the
decoder .even with transmission errors.
either linear or p-Iaw PCM data from its serial voice
interface, encodes it to ADPCM data format, and
passes the ADPCM data through the parallel data bus
to the host system. In decoder mode, the pPD77C30
receives ADPCM data from the host CPU, decodes it to
either linear or p-Iaw format, and sends it to the output
port of the serial interface.
The pPD77C30 has serial interfaces that can connect
directly to a single-chip PCM codec. It interfaces easily
to a host CPU through its parallel bus. With its standard
microprocessor bus interface, the pPD77C30 can be
viewed as a complex peripheral circuit. Figure 2 shows
a typical system configuration.
The pPD77C30 can operate in either encoder or decoder mode, but it only be set to one of the two modes
at a time; it cannot handle simultaneous encoding and
decoding. In encoder mode, the pPD77C30 accepts
3
NEe
JlPD77C30
Figure 1. Algorithm Block Diagram
OPERATIONAL DESCRIPTION
0UIpIl1
OUlpllllnpul
(AOPCM
8'(1)
),l
O~AQ
(PCM)
~t¥
x'(I)
AP
AQ·1
j'(I)
FP
l1.'(t)
X(I) .
Host PCU Interface
In order to transfer ADPCM data, commands, and
status, the jlPD77C30 interfaces with the host CPU via
Do - D7 and through control lines CS, Ao, WR, and RD.
CS enables RD and WR. Ao selects either the data or
status register. A low input to Ao selects the data
register. This read/Write register handles both commands and ADPCM data transfer. A high input to Ao
selects the status register, a read-only register that the
CPU reads to determine the state of the jlPD77C30.
Parallel I/O Operation
Table 1 shows the status of the CS, Ao, WR, and RD pins
during parallel I/O operation. Figures 3 and 4 aretiming
diagrams that show the read and write operations for
the host CPU interface with the jlPD77C30.
Deooder Mode
Encoder Mode
AQ: Adaptive Quantlzer
AQ·1: Adaptive Inverse Quantlzer
FP: Fixed Predictor
AP: Adaptive Predictor
B3FM----------WR
v
5
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IIPD77C30
Operation Command
ORO characteristics:
- Except during initialization, the JlPD77C30 DRO
signal is high, when the status register bit ROM
is set to indicate that an ADPCM data transfer to
or from the host CPU is required.
- DRO goes low after each encoding or decoding
operation is completed.
- Because DRO remains low throughout
initialization, it cannot be used for handshaking
during initialization.
- The DRO signal may be connected to an
interrupt pin of a host CPU.
Two different approaches can be used for servicing
ADPCM 1/0 request by the JlPD77C30. The first approach is for the host CPU to repeatedly poll the status
register until ROM = 1 is found. The second approach
is for the DRO pin to go high, forcing an interrupt of the
host CPU. In either case the host CPU then reads the
data register to capture the ADPCM data.
Following a power-on reset, the host CPU polls the
ROM bit in the status register. When the ROM bit is set,
the host CPU can send an operation command to the
data register, as shown in figure 6.
Figure 6. Operation Command
7
Encoder Mode
07· 05
111
101
110
100
Decoder Mode
0 7 .05
Status Register
011
Figure 5 shows the format of the status register.
001
010
Figure 5. Status Register Format
7
I
ROM
6
I
0
I
DRS
I
0
000
1
o
SOL
SIL
2
543
DEI
lORe
I
ROM
Request for Master
0
peM input data is 16·bit (linear)
peM input data is S-bit (J.t-Iaw)
DEI
Speech Detect
0
Silence interval
Speech detected
DRS
Data Register Status
0
Data register is 16-bit (for threshold data)
Data register is S-bit (for all other data)
DRC'
Data Register Control
0
Second byte transferred
First byte transferred
SOL
Serial Output Data Length
0
peM output data is 16-bit (linear)
peM ouput data is S-bit (J.t-Iaw)
SIL
Serial Input Data Length
0
peM input data is 16-bit (linear)
peM input data is S-bit (J.t-Iaw)
• DRS indicates the status of data transfers when the data register is
configured as 16-bit (DRe 0)
6
6
5
4
3
2
o
o
o
o
o
o
PCM Data
Format
ADPCM Data
Length/Sample (bits)
p-Iaw S-bit codec
(MSBfirst)
3
4
16-bit A/D-D/A
(LSB first)
4
PCM Data
Format
ADPCM Data
Length/Sample (bits)
p-Iaw S-bit codec
(MSBfirst)
3
16-bit A/D-D/A
(LSB first)
3
3
4
4
Power-on and Reset
The JlPD77C30 operates on a single-phase, 50-50 duty
cycle clock at 8 MHz. At power-on, asserting the RST
pin for at least 3 clock cycles initializes the device,
making it ready for an operation command from the
host CPU. After the JlPD77C30 receives the command, it
stays in the specified operational mode until the next
hardware reset (high level on RS1). Thus, to change the
JlPD77C30 into different modes, reset it before writing
an operation command.
Initialization and Threshold Data
See figure 7 for the initialization sequence for the
encoder mode. See figure 8 for the initialization sequence for the decoder mode. During initialization
signal SMPL is ignored, but the SCK and SIEN signals
must be active. This is because the JlPD77C30 internal
code checks that the serial data is being transferred in
before it accepts the mode byte. Also, it is of no
consequence whether or not serial input data is valid
during initialization. This is true whether the JlPD77C30
is placed in encoder or decoder mode .
A hardware reset must be issued before a mode byte
can be sent, even when the JlPD77C30 is being powered up. A hardware reset signal also must be issued to
NEe
change modes (i.e., encoder to decoder mode). In
either of the above cases, the reset signal must be held
active for a minimum of 3 clock cycles to guarantee that
the mode byte will be accepted. As explained below,
the ROM bit of the status register should be used for
data transfer handshaking, especially during initialization. The status register at a clock frequency of 8.192
MHz is not valid until 190 ps after the trailing edge ofthe
reset pulse, and it should not be read until after that
time interval.
The DRO signal does not always follow the state of the
ROM bit in the status register. In particular, the DRO
signal remains low throughout initialization. Therefore,
it is essential during initialization to use the ROM bit of
the status register for handshaking. The DRO signal is
intended for interrupting the host CPU so that it will
transfer ADPCM data after initialization. The DRO signal remains high until the encoding or decoding operation of the pPD77C30 is complete. The ROM bit, in
contrast, is intended for data transfer handshaking
and is reset after each data port transfer is complete.
pPD77C30
Figure 7. Encoder Mode Initialization Sequence
N
Write EOH [Encoder Mode]
to Data Register
When the pPD77C30 first enters the decoder mode the
ROM bit is already set and the first byte of data sent to
the pPD77C30 will not be decoded properly. To avoid
losing the first speech sample, a dummy first byte of
ADPCM should be sent.
If the operation command places the pPD77C30 in
encoder mode, the next two bytes sent to the data
register are the threshold data The ROM bit establishes
the data transfer signaling. In decoder mode, no
threshold data is expected. The threshold data sets the
level of the audio signal at which the DET pin is
asserted. Figure 9 shows the format for the threshold
data Figure 10 shows how to determine the threshold
data
The pPD77C30 asserts DETwhen the serial input audio
Signal exceeds the threshold level specified by the
threshold data. Many silent segments exist in normal
speech signals; memory storage can be used more
efficiently if these segments are omitted. The host CPU
can perform silent segment compression by using DET.
The energy levels of 16 previous audio samples determine the state of DET. Thus DET changes at a 2 ms (16
x 8 kHz sampling) time frame. Bit 5 of the status register
reflects the state of DET.
[AO=O]
N
Write 2 Bytes 01 Threshold
Data to Data Register
Do Not PoR ORO betwaen Bytes
Send Low Byte. lIlen High Byte
N
Device Initialized in Encoder Mode
Start Reading Encoded Data
from Data Register
Use ROM or ORO Pin
for Handshaking
49TB-407A
7
NEe
pPD77C30
Figure 8. Decoder Mode Initialization Sequence
Figure 10. Typical Relationship Between Input
Level and Threshold Value
-------
I
o
OET=l
/'
.....
OET=O
/
40
I
o
100
200
300
400
500
800
700
800
i
900
Threshold Value [Hexadecimal)
N
Conditions:
[1) Input = Sinusoidal Wave [1 kHz)
[2) Input Level Is me.8Sured at the analog Input of codec [gain = OdB]
W~ta
60H [Decoder Mode)
to Data Register
ADPCM Data
[AO=OJ
N
Device Initialized In Decoder Mode
Start Writing Data Into Data
Register from Host CPU
Use ROM or ORQ Pin
for Handshaking
Figure 9. Threshold Data
Threshold Data
MSB
I
0
10141013
1-----1 1
D2
LSB
01
SIGN
Note: The ~P077C30 receives the lower 8 bits of
this data before It receives tha higher 8 bits.
8
In encoder mode, the JlPD77C30 generates one ADPCM
sample (3 or 4 bits long) each PCM sample input (8 or
16 bits long). In decoder mode, the reverse operation is
performed: the JlPD77C30 generates one PCM sample
for each ADPCM sample input. To allow efficient data
transfer to and from the host CPU, two ADPCM samples
are packed into one byte and transferred at the rate of
1 byte per every 2 samples. Figure 11 illustrates the
ADPCM data formats for 3 bits!sample and 4 bits!
sample.
The DRO pin initiates ADPCM data transfer. In encoder
mode, this pin is asserted when ADPCM data in the
data register is ready to be read by the CPU. This pin is
cleared after the host CPU reads the data, and is
reasserted when the next byte of ADPCM data becomes available. In decoder mode, this pin serves as
the data request to the host for the next byte of ADPCM
data to be sent to the data register. After the host CPU
writes the ADPCM data, this pin is cleared. The host
CPU cannot send another byte to the JlPD77C30 until
this pin is set again. (Note that the DRO pin will not
work until the JlPD77C30 is placed in encoder or decoder mode.)
The ADPCM data transfer is acknowledged by the ROM
bit in the status register. The ROM bit is set when
transfer to the host is requested for ADPCM data, and is
reset when the host read/write is complete.
fttfEC
Serial PCM Interface
The serial PCM interface can be connected directly to
a codec. SMPL, SCK, SIEN, SI, SORQ, SOEN, and SO
control the PCM interface.
SMPL is the sampling clock input. This signal must
equal the frequency of the sampli ng clock of the codec
or the A/D-D/A interface. SMPL is asserted after the
completion of serial data transfers. Thus SMPL signals
the pPD77C30 firmware to initiate processing of the
next byte of ADPCM data. SMPL is rising-edge triggered, but must be held high for at least 8 clock cycles.
Since it is edge-triggered, SMPL does not need to be
released until the next sampling cycle.
SCK determines the timing of the serial input and
output. When the pPD77C30 has data to send to the
serial interface, SORQ goes high. The data is then
clocked out to the SO pin serially at the falling edge of
SCK, to be valid for the next rising edge. When serial
data is ready to be sent to the pPD77C30 SIEN is
asserted externally, and data at the SI pin is clocked in
at the rising edge of SCK.
IIPD77C30
Figure 11_ ADPCM Data Format
ADPCM data length = 4 bits
MSB
LSB
Iroloolool~looloolrnlool
\.
J
y ) \
Precedk,9 Data
Trailing Data
ADPCM data length = 3 bits
LSB
MSB
\.
Y
Trailing Data
.J\
Preceding Data
83FM_
Figure 12 illustrates an example of the serial interface
using a combined filter and codec (combo) chip, the
pPD9514. This chip provides both the low pass filtering
function and the conversion from an analog signal to
digital PCM p-Iaw representation. The timing controller
provides the proper timing relationship between the
combo and the pPD77C30.
9
NEe
pPD77C30
Figure 12. Serial Interface Using a Combo
TIming Controller
1-----------------------------------------------------I
+6V
1
1
1
1
1~
1
i
74LS161
1
19
74LS393
17
110
n13
1
1
osc
Oc~.....!
~ CLK
74LS74
1A
2Q0
~O
Os
OA
~
14
8 MHz
13
4 MHz
p12
0 5
Q'!'"
l.!e
tV
124
Voo
Analog
~
21
AlN+
CLKX
AlNCLK4
GSX
LOOP
DGNO
FSX
AGNO
FSR
16
SIGX/ASEL
Anal",!~ PWRO+
Ox
Output
DR
20K
4
~ GSR
33K
c..Jl. PWRO- Vss
CLKSEL
OCLKR
~
Jl
OA
.1:
3
n
OIl
4
PRE
2
5
~
"PD9514D
0
O~
,!!
3 CLK
CLR
CLK
CLR
1~3
.1:
+6V
- -- r------------------- -------------
~
~
SMPL
20
~ SOEN
SIEN
-----= SCK
15
CLK
~
:ill11
16
10
21 SI
22 SO
mv
~
~
CS
16
.M...
AO ~
RO ~
WR ~
ORO .!..OET .L
07
06
05 .1L
04
03 ~
02
01
DO
~1_..
r1!L
+5V
1
10
PRE
12
or--=
o
-
~
Fliter/Coclec (Combo)
10
CLK
15
PON
Inpul~
-
RST
7
PRE
V
-----------1
1
1 A
2MHz
1
1
1_ _ _ -
74LS74
[9
CLR
11
CLR
,.! CLK
16.364
MHz
74LSl64
VOO
PU
(GNO
"PD77C30
ftlEC
pPD77C30
ELECTRICAL SPECIFICATIONS
Capacitance
TA = 25'C
Absolute Maximum Ratings
Parameter
TA = 25'C
Supply voltage, VDD
-0.5 V to +7.0 V
Input voltage, VI
-0.5 V to VDD +0.5 V
Output voltage, Vo
-0.5 V to VDD +0.5 V
Operating temperature, TOPT
Symbol Min Typ Max Unit Conditions
ClK, SCK capacitance Crp
20
Input capacitance
10
pF
Output capacitance
20
pF
Co
pF
fc = 1 MHz
-40 to + 85°C
-65 to + 150°C
Storage temperature, TSTG
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage
DC Characteristics
TA = -10 to + 70'C; VDD = + 5 V ±5%
Parameter
Symbol
Min
Input low voltage
Max
Unit
-0.3
Typ
0.8
V
Input high voltage
2.2
Vee + 0.3
V
ClK input low voltage
3.5
0.45
V
ClK input high voltage
-0.3
Vec +0.3
V
0.45
V
Output low voltage
Output high voltage
V
2.4
Conditions
.
III'
\
IOL = 2.0mA
IOH = -400/lA
-10
/lA
Input leakage high current
10
/lA
VI = VDD
Output leakage low current
-10
/lA
Vo = 0.47 V
10
/lA
Vo = VDD
40
mA
Input leakage high current
Output leakage high current
Supply current
24
IDD
VI = OV
AC Characteristics
TA = -10 to + 70'C; VDD = + 5 V ±5%
Parameter
Symbol
Min
ClK cycle time
4>CY
120
60
Typ
Max
Unit
2000
ns
Conditions
ClK pulse width
4>D
ClK rise time
4>r
10
ns
ns
(Note 1)
ClKfali time
4>,
10
ns
(Note 1)
AO, CS set time for RD
tAR
0
ns
Ao, CS hold time for RD
tRA
0
ns
RD pulse width
tRR
250
ns
AO, CS set time for WR
tAW
0
ns
AO, CS hold time for WR
twA
0
ns
WR pulse width
tww
250
ns
tow
150
ns
tWD
0
ns
tw
250
tsCY
480
Data set time for WR
Data hold time for WR
RD, WR recovering time
SCK cycle time
ns
DC
ns
11
NEe
pPD77C30
AC Characteristics (cont)
Parameter
Symbol
Min
SCK pulse lime
!sCK
230
SCK rise lime
!,sC
20
ns
SCKfall time
ttsc
20
ns
SOEN set lime for SCK
!soc
50
!sCY
-30
ns
SOEN hold time for SCK
tcso
30
!sCY
-50
ns
SIEN, SI set lime for SCK
toc
55
ISCY
-30
ns
SIEN, SI hold lime for SCK
ICO
30
!sCY
-55
ns
SIEN, SOEN pulse width high
RST pulse widlh
SMPL pulse width
ISMPl
Delay time between SMPL and SIEN (SOEN)
tox
Typ
Unit
Conditions
ns
122
cf>CY
4
cf>CY
8
-1
cf>CY
o
Oat a access time for RD
Data float time for RD
Max
I'S
150
ns
Cl = 100 pF
10
100
ns
Cl = 100 pF
30
150
ns
150
ns
SORQ delay
IORQ
SO delay time
tOCK
SO delay lime for SORQ
IOZRQ
20
300
ns
SO delay lime for SCK
tozsc
20
300
ns
SO delay lime for SOEN
20
180
ns
SO float time for SOEN
20
200
ns
SO float time for SCK
20
300
ns
SO float time for SORQ
70
300
ns
Note:
(1) AC timing measuring point voltage = 1.0 V and 3.0 V.
Timing Waveforms
Read Operation
Clock
elK
_IRR--
..F..........
83FM-8347A
12
NEe
pPD77C30
Write Operation
Reset
RST_L,~J
_ _ tww _ _
Sample
OBo-OB7-fON-~'~1c
L-__________________________________
~~~F~~~
1'"~-C,"~J _I
L.__________________________________
~~~~.
Serial Input/Output Timing
Note: In SO, the data output at the rising edge Is valid, while data output at other
Umes Is Invalid. Tharelore, the most c~Ucal data set-up and hold Umes are:
Set-up Ume = tSCK - tOCK
Hold Ume tHZAQ
=
83FM-836aB
13
NEe
pPD77C30
Read/Write Cycle Timing
AC Waveform Measurement Point (except CLK)
1
os, _ \
},"",~:=====II_R_V~~~~~-'~~
I.::
X~:
~:J(
83FM.......
Serial Input Timing
SCK~
k-----~ISMPL-----.j
SMPL
SI
80r~
83F_
Serial Output Timing
SCK~
SMPL
so
80r~
83FM.......
14
I
NEe
pPD7755/56/P56/57/58
NEC Electronics Inc.
ADPCM Speech Processors
Description
The IlPD775x speech processors utilize adaptive differential pulse-code modulation (ADPCM) to produce
high-quality, natural-sounding speech. The IlPD775x
family includes four types with a built-in ROM and one
with a one-time programmable (OTP) ROM.
ROM
IlPD7755
IlPD7756
IlPD7757
IlPD7758
OTP ROM
o Circuit to eliminate popcorn noise when entering
or releasing standby mode
o Wide operating voltage range: 2.7 to 5.5 V
o CMOS technology
o 18- and 20-pin plastic DIP
o 24-pin plastic SOP
Ordering Information
IlPD77P56
Part Number
Package
ROM (bIts)
IlPD7755C
18-pin plastic DIP
(A, C outline)
96K
55G
Note: Unless excluded by context, IlPD775x means all
types listed above; IlPD7756 includes IlPD77P56. The
IlPD7759, which uses external ROM, is also considered
part ofthellPD775x family but is covered in a separate
data sheet.
By combining melody mode, ADPCM, and pause compression, the IlPD775X achieves a compressed bit rate
that can reproduce Sound effects and melodies in
addition to speech. A built-in speech data ROM allows
reproduction of messages up to 4 seconds (PPD7755),
12 seconds (PPD7756), 24 seconds (pPD7757), or 48
seconds (pPD7758).
A wide range of operating voltages, a compact package, and a standby function permit applications of the
IlPD775x in a variety of speech output systems, including battery-driven systems.
24-pin plastic SOP
18-pin plastic DIP
(A, C outline)
IlPD7756C
56G
24-pin plastic SOP
2O-pin plastic DIP
IlPD77P56CR
IS-pin plastic DIP
(SA outline)
IlPD7757C
57G
18-pin plastic DIP
(SA outiine)
IlPD775SC
5SG
24-pin plastic SOP
Pin Configurations
fB-Pin Plastic DIP
"PD7755156157158
o Low bit rates (10 to 32 kb/s) using a combination of
ADPCM and pause compression
o Built-in speech data ROM
-IlPD7755: 96K bits
-IlPD7756/P56: 256K bits
-IlPD7757: 512K bits
-IlPD7758: 1M bits
o Sampling frequency: 5, 6, or 8 kHz
o Standby function
o Typical standby current: 1 IlA
50116-1
(VDD =
3 V)
512K
24-pin plastic SOP
o High-quality speech reproduction using ADPCM
o D/A converter with 9-bit resolution and unipolar
current waveform output
256K (OTP)
24-pin plastic SOP
P56G
Features
o Bit rates to less than 1 kb/s for sound effects,
melodies, and tones (DTMF) using melody mode
256K
REF
AVO
BUSY
RESET
GND
1M
•
"
ttlEC
pPD7755/56/P56/57/58
Pin Configurations (cont)
PIN FUNCTIONS
20-Pin Plastic DIP
AVO (Analog Voice Output)
AVO outputs speech from the D/A converter. This is a
unipolar sink-load current. No current flows in standby
mode.
~
W04
1sfD5
liD:!
1&'06
11/01
tT~
REFIM02
Io'Do
ST
BUSY (Busy)
~03
AVO
BUSYIMOO
Xl
RES~IMOl
~
GNO
VOO
NC-....;;.;;..-._.......;~VpP
83FM-8017A
CS (Chip Select)
24-Pin Plastic SOP
When the CS input goes low, ST is enabled.
"PD775x
GNO
VOO
~
RES~/(M01)
Xl
BUSY/(MOo)
Do - 07 (Data Bus)
Eight-bit input/output data bus from PROM when programming and verifying data
NC
AVO
NCI(Vpp)
CSI(MOa)
ST
REF/(M02l
NC
NC
1.,t(07)
10 - h (Message Select Code)
NC
lo'(Dol
NC
11/(01)
121(02)
1&'(D61
1sf(D51
1af(Da)
14(04)
=
Note: () AddItIons lor the "PD77P56.
83FM-801M
10 - 17 input the message number of the message to be
decoded. The inputs are latched at the rising edge of
the ST input. Unused pins should be grounded. In
standby mode, these pins should be set high or low. If
they are biased at or near typical CMOS switch input,
they will drain excess current.
MOo - MD3 (Mode Select Input)
Pin Identification
Symbol
Name
AVO
Analog voice output
BUSY
Busy output
cs
Chip select input
00- 07
PROM
MOO- M03
Operation mode selection Input from PROM
VO data bus
Message select code input
REF
O/A converter reference current Input
RESET
Reset input
ST
Start input
Xl,X2
Ceramic resonator clock terminals
Voo
+5 V power
Vpp
+ 12.5 V
GNO
Ground
NC
No connection
2
BUSY outputs the status of the pPD775x. It goes low
during speech decode and output operations. When
ST is received, BUSY goes low. While BUSY is low,
another ST will not be accepted. In standby mode,
BUSY becomes high impedance. This is an active low
output.
PROM voltage application
Operation mode selection inputs from PROM when
programming and verifying data.
RE F (0/A Converter Reference Current)
REF inputs the sink-load current that controls the D/A
converter output. REF should be connected to Voo via
a resistor. In standby mode, REF becomes high impedance.
RESET (Reset)
The RESET input initialized the chip. Use RESET following power-up to abort speech reproduction or to release standby mode. RESET must remain low at least
12 oscillator clocks. At power-up or when recovering
from standby mode, RESET must remain low at least 12
more clocks after clock oscillation stabilizes.
t-IEC
pPD7755/56/P56/57/58
ST (Start)
OPERATION
Setting the ST input low while CS is low will start
speech reproduction of the message in the speech
ROM locations addressed by the contents of 10 - 17. If
the device is in standby mode, standby mode will be
released.
The fJPD775x can operate with a Voo supply voltage in
the 2.7- to 5.5-V range. An external 640-kHz ceramic
resonator connected to pins X1 and X2 drives the
internal clock oscillator. Initialization is performed by
holding the RESET pin low for at least 12 oscillator
clock cycles.
X1, X2 (Clock)
Pins X1 and X2 should be connected to a 640 kHz
ceramic resonator. In standby mode, X1 goes low and
X2 goes high.
Voo (Power)
+5-V power supply.
Vpp (PROM Power)
+ 12.5-V high-voltage application pin for programming
and verifying data to PROM.
GND (Ground)
Ground.
When the fJPD775x has been idle (that is, when CS, ST,
or RESET have not been asserted) for more than 3
seconds, the fJPD775x goes to a standby mode. It will
automatically release from standby mode when CS
and ST are asserted again or when RESET is asserted.
AfJPD775X can store 256 different messages and up to
4 (fJPD7755), 12 (fJPD7756), 24 (fJPD7757), or 48
(fJPD7758) seconds of speech. The message selection
at pins 10 -17 is latched atthe rising edge of STwhen CS
is asserted. BUSY goes low until the selected audio
speech output is completed. While BUSY is low, a new
ST will not be accepted.
The internal D/A converter has 9-bit resolution and
unipolar current output. Current can be controlled by
the voltage applied at the REF pin.
NC (No Connection)
These pins are not connected.
I£PD775x Block Diagram
ST----,
~X1
Message
Select Input
latch Clrcutt
speech
Data Mamory
PROM Control
"PDnP56
---r::::tVpp
X2
_ _ VDD
--GND
CSI(MD3)--
RESET/(MOI) - -
System
Controller
BUSY/(MDO)
Nota: ( ) = AddlUans for the "PDnp56
49NR-488a
3
1ttIEC
pPD7755/56/P56/57/58
Absolute Maximum Ratings
ELECTRICAL SPECIFICATIONS
TA = 25'C
This section describes the electrical specifications for
thepPD775X family of processors. The pPD77P56 electrical specifications in PROM operation mode are described in the later PROM electrical specifications
section.
-0.3 to + 7.0 V
Supply voltage, Voo
Input voltage, VI
-0.3 to Voo + 0.3 V
Output voltage, Va
-0.3 to Voo + 0.3 V
PROM power voltage, Vpp
-0.3 to + 13.5 V
PROM output current, 10 (AVO pin only)
Capacitance
TA = 25'C
Parameter
Symbol
Input capaoitance
CI
Min Typ Max Unit Conditions
Output capacitance Co
10
pF
20
pF
50 mA
Operating temperature, Ton
7755/56/57/58
77P56
-10 to +70'C
-40 to +85'C
Storage temperature, TSTG
7755/56/57/58
77P56
fc=IMHz
-40 to + 125'C
-65 to + 125'C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings· could cause permanent damage.
Recommended Operating Conditions
Parameter
Symbol
Operating temperature
7755/56/57/56
Min
Max
Typ
Unit
ton
77P56
Power voltage
VOO
PROM programming voltage
Conditions
Ambient temperature
Vpp
-10
+70
'C
-40
+85
'C
2.7
5.5
V
Operation
5.75
6.25
V
PROM Programming
2.7
5.5
V
Operation
12.2
12.8
V
PROM programming
RESET pulse width
tRST
18.5
ST set-up time
tRS
12.5
J.ls
From RESETt
tCCI
2
J.ls
Voo = 2.7 to 5.5 V
teC2
350
ns
Voo = 4.5 to 5.5 V
tOWI
2
J.ls
Voo = 2.7 to 5.5 V
VOO = 4.5 to 5.5 V
ST pulse width
Data set time
J.ls
tOW2
350
ns
Data hold time
two
0
ns
CS set-up time
tes
0
ns
CS hold time
tsc
0
CLK frequency
fosc
ns
630
640
650
kHz
Note: Voltage at AC timing measuring point: VIL = VOL = 0.3 Voo and VIH = VOH = 0.7 Voo
DC Characteristics
TA = -10 to + 70'C; TA = -40 to +85'C (J.lPD77P56); Voo = 2.7 to 5.5 V; fosc = 640 kHz
Parameter
Symbol
Input voltage high
VIH
Max
Unit
0.7 Voo
Min
Typ
Voo
V
Applies to 10 - 17, ST, CS, RESET
Conditions
Input voltage low
VIL
0
0.3 Voo
V
Applies to 10 - 17, ST, CS, RESET
Output voltage high
VOH
Voo - 0.5
Voo
V
Applies to BUSY, IOH = -100 J.lA
Output voltage low
VOL1
0.4
V
Applies to BUSY, Voo = 5 V ±10%, IOL = 1.6
mA
0.5
V
Applies to BUSY, IOL = -200 J.lA
VOL2
4
0
NEe
fJPD7755/56/P56/57/58
DC Characteristics (cont)
Parameter
Symbol
Input leakage
current
Output leakage
current
Min
Typ
Max
Unit
Conditions
III
3
/lA
Applies to 10 - 17, ST, REF, CS; VI
ILO
3
/lA
Applies to BUSY; Vo
mode
= 0 to VOO
= 0 to VOO in standby
IREF1
140
250
440
/lA
= 2.7 to 5.5 V
= 2.7 to 5.5 V in standby mode
VOO = 2.7 to 3.3 V
VOO = 2.7 to 3.3 V in standby mode
Vpp = Voo
Voo = 2.7 V, RREF = 00
IREF2
500
760
1200
/lA
Voo
=
Reference input low
current
area (figure 1)
IREF3
21
30
39
/lA
Voo
=
IREF4
68
78
88
/lA
Voo
D/A converter
output current
(figure 1)
IAVO
32
34
36
IREF
D/A converter
output leakage
current
ILA
±5
/lA
Supply current
0.8
2
mA
VOO
20
/lA
VOO
600
/lA
10D4
10
/lA
Ipp
20
/lA
1001
1002
250
1003
Reference input
high current
area (figure 1)
5.5 V, RREF
=
00
2.7 V, RREF
=
50 kO
= 50 kO
Voo = 2.7 to 5.5 V, VAVO = 2.0 V,
D/A input = 1FFH
=
VAVO
5.5 V, RREF
= 0 to VOO in standby mode
III
I
TA
AC Characteristics
= -10 to + 70°C; TA = -40 to + 85°C
(PPD77P56); VDO
Parameter
Symbol
Typ
Max
Unit
10
/ls
Operation mode
4
80
ms
Standby mode, including oscillation start time
6.25
10
/ls
Standby mode
2.1
2.2
ms
Operation mode (from BUSY)
tsss
2.1
2.2
ms
Standby mode
tOA
46.5
47
ms
Entering/releasing standby mode
/lS
From end of speech output
tSBO
BUSY set time
IsB
tsso
IsBS
Speech output start time
D/A converter set-up time
= 2.7 to 5.5 V; foSC = 640 kHz
6.25
BUSY output time (from ST and/or CS)
Min
BUSY delay time
tBO
15
BUSY output stop time
tRB
9.5
/ls
3
s
Standby transition time
tSTB
2.9
Figure 1. Measuring Diagram for IREFand IAVO
Voo
L
Conditions
For RESET I
From end of speech output
Figure 2. External Oscillator
~pon5x
~pon5x
RREF
REF
IREF_
-----JAVO
IAVO83FM-801M
Ceramic rescnators:
= =
Kyocera Corp. KBR-6408 (Cl C2 220 pF)
Murata Mfg. Co. Ltd. CSB640P (C1 = C2 = 220 pF)
83FM...,..,.
5
t-IEC
pPD7755/56/P56/57/58
Timing Waveforms
Reset Mode
AC Waveform Measurement Points
[1]
/
RESET
11+-_+1 tAST
Standby Mode
[2]
Operating Mode (ST Input Pulse Mode)
.
H
~
1FFH·
AV0100H· ____________
~
too
two
]
r---------------i
tsso-
1FFHAVO 100H·
~H·
I
L
I
-j
Speech Output
83FM_
6
t-{EC
pPD7755/56/P56/57/58
Operating Mode (ST Input Hold Low Mode)
USING ONE·TIME PROGRAMMABLE ROM
The pP077P56 speech processor features a 256K-bit
one-time programmable (OTP) ROM. This section describes the PROM initialization procedure, the PROM
operation modes, the PROM programming procedure,
and the data readout verification procedure.
Initial ization
Valid
Before programming the PROM, the PROM address 0
clear mode must be set to prevent erroneous programming: set the MOo - M03 pins to high, low, high, low,
respectively. The PROM address 0 clear specifications
are also shown in the PROM Operation Modes table.
Permanent data used forthe LSI is stored in the system
area of the memory from 0001H to 0004H. This data is
SAH, ASH, 69H, and SSH. Blank check the memory at
OOOOH and from 0005H to the end address. Program the
memory from OOOOH to the end address.
AVO------<
PROM Operation Modes
To enter the PROM operation modes, connect + 6 V to
Voo and + 12.5 V to Vpp and set the ST pin to low level.
Also set AVO and X2 pins open and X1 to low level. There
are four PROM operation modes. The PROM Operation
Modes table identifies and decribes these four modes.
PROM Operation Modes
Operation Mode Specifications
Operation Mode
Oeser I ptlon
MOo
M01
M02
M03
PROM address 0 clear
This mode sets the PROM address to 0, even. if set while
switching between modes. Setting this mode out of sequence
may result in erroneous changes to data.
High
Low
High
Low
Program mode
This mode programs speech data to PROM with data on 00-
Low
High
High
High
07'
Verify mode
This mode checks the speech data stored in PROM. The data
can be verified by reading 0 0 - 0 7,
Low
Low
High
High
Inhibit mode
This precautionary mode can be used while switching between
modes. This mode can be passed through to avoid an
accidental setting of the program address 0 clear mode.
High
High or Low
High
High
7
"'
.....
..'.'
'
,
NEe
JlPD7755/56/P56/57/58
PROM Programming Procedure
PROM Data Readout Proc.edure
This procedure describes how to program the PROM.
Data can be programmed into PROM at two timing
speeds, low or high. The procedure for both speeds is
the same, except that at low speed data is programmed for 1 millisecond and at high speed data is
programmed for 250 microseconds. The PROM timing
waveforms section has diagrams that illustrate lowand high-speed timing. See figure 3 for a flow-chart
diagram of the PROM programming procedure. The
procedure is as follows:
.
The programmed processor can read out data from the
PROM. The PROM timing waveforms section has a
diagram that illustrates the data readout timing. To
verify the data, use the following procedure:
(1) Set ST pin to low level, AVO and X2 pins to open,
and Xi to low level.
(2) Apply +5 V to Voo and to Vpp.
(3) Wait 10 ps.
(4) Set PROM address 0 clear mode.
(5) Apply +6 V to Voo and + 12.5 V to Vpp
(6) Set program inhibit mode.
(7) Program data in 1 ms (lOW speed) or 250 ps (high
speed) of program mode.
(8) Set inhibit mode.
(9) Set verify mode: If data has been programmed, go
to step 10, if data has not been programmed,
repeat steps 7 to 9.
(10) For low-speed, additional programming: X x 1 ms,
where X is equal to the number of times data has
been programmed in steps 7 to 9.
(11) Set inhibit mode.
(12) Increment an address by applying a pulse to Xi
pin four times.
(13) Repeat steps 7 to 9 up to the final address.
(14) Set PROM address 0 clear mode.
(15) Change voltages Voo and Vpp to +5 V.
(16) Turn the power off.
Notes:
(1) Avoid setting the PROM address 0 clear mode when moving to
another mode.
(2) This high-speed programming procedure is different from that of
/lP027C256A.
8
(1) Set ST pin to low level, AVO and X2 pins to open,
and Xi to low level.
(2) Apply +5 V to Voo and to Vpp.
(3) Wait 10 ps.
(4) Set PROM address 0 clear mode.
(5) Apply +6 V to Voo and + 12.5 V to Vpp.
(6) Set inhibit mode.
(7) Set verify mode: Read data for one address on Do
- 07; then apply four clock pulses to the Xi pin.
Repeat for each address up to the end address.
(8) Set inhibit mode.
(9) Set PROM address 0 clear mode.
(10) Change voltages Voo and Vpp to +5 V.
(11) Turn the power off.
Note: Avoid setting the PROM address 0 clear mode when
moving to another mode.
NEe
IIPD7755/56/P56/57/58
Figure 3. PROM Programming Row Chart
•
N = maximum address
X = number of Urnes
programmed
9
I
NEe
IJPD7755156/P56/57/58
PROM ELECTRICAL SPECIFICATIONS
This section lists the electrical specifications of the
JIPD77P56 while in PROM operation modes.
DC Characteristics
TA = 25 ±5"C; Voo = 6 ±0.25 V; Vpp = 12.5 ±0.3 V
Parameter
Symbol
Min
Max
Unit
Input voltage high
VIHt
4.2
6
V
Do - D7, MDo, MDt, MD3, ST, XI
VIH2
2.5
6
V
MD2
VILt
o
o
1.8
V
Do - D7, MDo, MDt, MD3, ST, XI
VIL2
0.5
V
MD2
Output voltage high
VOH
5.5
V
Do - D7, IOH = -1 mA
Output voltage low
VOL
0.5
V
Do - D7, IOL =
Input leakage current
III
3
IlA
Do - ~, MDo, MDt, MD3, ST, VIN = 0 to VOO
Clock input current
IIHt
3
20
IlA
XI, VIN = Voo
111l
3
20
IlA
Xl,VIN= OV
IIH2
0.5
1.4
mA
MD2, VIN = VOO
0.12
0.4
mA
MD2' VIN = 2.5 V
MD2, VIN = OV
Input voltage low
MD2 input current
Supply current
Typ
IIL2
3
IlA
100
2
mA
Ipp
10
mA
Conditions
+1
mA
AC Characteristics
TA = 25 ±5"C; Voo = 6 ±0.25 V; Vpp = 12.5 ±0.3 V
Parameter
Address setup time (for MDo .)
MDt setup time (for MDo .)
Symbol
Min
Typ
Max
Unit
tAS
2
Ils
tMtS
2
Il s
Data setup time (for MDo .)
los
2
Ils
Address hold time (for MDo t)
tAH
2
Ils
Data hold time (for MDo t)
tOH
2
tOF
0
Vpp setup time (for MD3 t)
Iyps
2
VOO setup time (for MD3 I)
Iyos
2
Initial program pulse width
tpw
0.9
MDo t to data output float delay time
240
MDo setup time (for MDt I)
tMOS
MDo • to data output delay time
tov
MDt hold time (for MDo t)
tMtH
MDt recovery time (for MDo I)
Ils
130
ns
Ils
Ils
1.1
250
260
ms
Low-speed programming
Il s
High-speed programming
2
Il s
2
Ils
Ils
tMtR
2
Ils
Program counter reset time
tpCR
10
Ils
XI input high-and low-level widths
!xH, !xL
XI input frequency
Ix
Initial mode-setting time
tl
10
Ils
MHz
2
Conditions
IlS
NEe
fJ PD7755/56/P56/57/58
AC Characteristics (cont)
Parameter
Symbol
MD3 setup time (for MDl I)
tM3S
2
MD3 hold time (for MDl I)
tM3H
2
lis
MD3 setup time (for MDo I)
tM3SR
2
lis
Address to data output delay time
tOAD
2
lis
Address to data output hold time
tHAD
0
MD3 hold time (for MDo I)
tM3HR
2
lis
MD3 I to data output float delay time
tDFR
2
liS
MDo hold time (for MD2 t)
tMoHS
2
liS
tDDS
2
liS
tMoSS
2
liS
MD2
t
to data output delay time
MD2 hold time (for MDo I)
Min
Typ
Max
Unit
Conditions
lis
130
Program memory readout
ns
~..
11
t-fEC
pPD7755/56/P56/57/58
PROM Timing Waveforms
Low-Speed Data Programming Timing
Vpp
Vpp
VOO
tvos
VOO+l
Voo
VOO
-
-tXL
-E-tAH"
tAS
XI
Oo-~
- ~lInput
Input
(Data)
~
~S
MOo
iJ-
tOPW
MOl
-l
LL
I
I
I
tPCR
I-
I
MO:!
I
I
I
tMl!,!
tM1S
I
5S
I
I
5
'~~
I
I
I
I
I
I
"
II
I
155
II
MDa
55
Inhibit
addraaa (2)
PROM
oClear
(1)
Inhlbft
Program (4)
(3)
Ve~1y
(5)
Inhibit Repeat
(6)
steps 2-6 x
UmesunUI
VB~OK
(7)
Program Inhibit
(8)
(9)
t
Address
Increment
(10)
Program Inhlb11nhlbft PROM
address
Oc/ear
Repeat steps
3-10 to end
address
B3FM......
12
~EC
pPD7755/56/P56/57/58
High-Speed Data Programming Timing
VPP
VPP
VDD
-
-tVDS
VDD+1
VDD
VDD
-
-tXH
X1-+-+- - - - - - - - l
-
11
++-<1
00-0-, _ _
(Data)
Input
" - - - - ( ] Quip t
~_ _-'I1r
U
-
MOO
I
-
_tXL
"-----------f------{
Ir
I
'--_---J
+----tAS
-tMOS
-tM1R
-l
I
I
I
I
I
_tM1~
I
-
I
tM1S
I
I
I
tM3~~~
I
~-~----~----~----~----------------------------------~----~I
MD3
I
I
II
II
5
PROM Inhibit
address (2)
oclear
(1)
Program
(3)
Inhlbtt
Verify
(4)
(5)
Inhibit
(6)
Program
Address
Increment
(7)
II
Inhlb11nhlbtt PROM
address
oclear
Repeat steps
3-7 to end
address
83FM-8029B
13
NEe
IIPD7755/56/P56/57/58
Data Readout Timing
-
VPP
VPP
Voo
VOO+l
VOO
-
I - t vps
_tvos
VOO
_ _ tXH
J\'-----
Xl----~--~---------------------J
-
Do-D]--+--+----~
-tXL
-tOAD
Data output
_tOY
:,~~L1-
Data output
-I
-tHAD
tM3HR---"
H-----------
MOO
1
1
1
1
M~
1
1
1
~5
+,~"
:1
M03
--~
~~----1-------~~---------~~~5
PROM
address
oclear
(1)
Inhlb~
(2)
Verify
(3)
t
Address
Increment
(4)
Verify
t
II
Inhlb~ PROM
verify'
Address
Repeat steps
Increment
3 & 4 to end
address
address
0 clear
83FM-803OB
14
NEe
pPD7759
ADPCM Speech Processor
NEG Electronics Inc.
Description
Pin Configurations
The pPD7759 is a speech processing LSI that, with an
external ROM, utilizes adaptive differential pulse-code
modulation (ADPCM) to produce high-quality, naturalsounding speech. By combining melody mode with the
ADPCM method and pause compression, the device
achieves a compressed bit rate that can reproduce
sound effects and melodies in addition to speech
sound.
40-Pin Plastic DIP
ASDs
ASDs
ASD7
10
1,
12
13
14
Is
IS
17
AENIWR
SAA
DRO
ALE
The pPD7759 can directly address up to 1M bits of
external data ROM, or the host CPU can control the
speech data transfer. The pPD7759 is also suitable for
applications requiring small production quantities or
long messages, and for emulating the pPD7755/56/P56/
57/P57/58.
REF
Features
AVO
BUSY
RESET
GND
o High-quality speech reproduction using ADPCM
o Low bit-rates (10 to 32 kb/s) realized by combined
use of ADPCM and pause compression
o Bit rates to less than 1 kb/s for sound effects,
melodies, and tones (DTMF) using melody mode
VDD
ASD4
ASD3
AS02
ASD,
ASDo
As
A7
AS
As
A4
A3
A2
A,
Ao
cs
X2
X1
ST
MD
49TB-490A
52-Pin Plastic QFP
o Sampling frequency: 5, 6, or 8 kHz
o
o D/A converter with 9-bit resolution; unipolar
current waveform output
u~
COf"..U)LO()
vC')N..-OU
z««I
~~1
----'I'"
'''---tRAW
I..O(E----------twwL--------_~1
\
_t--tHCDO
I+-----ISDOC-----i~
00-0 7
Data Out _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. J
~
0"", _ _ _ _ _ _ _ _
Data In
.!!L _ _
~
__________~K~____
~_ '''''~_ >1=_
L
t
t
S_D_IC_____
HC_Dl_-_i
-L)--
_.!!L __
83RD·78728
17
IIPD77501
NEe
DTMF Receiver
83RD-78738
18
t-{EC
NEC Electronics Inc.
IIPD77522
ADPCM Codec
Preliminary
Description
Pin Configuration
The pPD77522 is a single-chip coder and decoder
(codec) for 32-kb/s adaptive differential pulse-code
modulation (ADPCM). The ADPCM technique conforms
to the 1988 CCITT Recommendation G.721.
28-Pin Plastic SOP (450 mil)
The serial data input to the coder and serial data
output from the decoder can directly interface a PCM
codec. The pPD77522 is ideal for application to digital
cordless telephone systems in which the data rate of
the PCM signal must be reduced.
Features
XSYNCD
RSYNCC
TEST4
XCLKD
TEST3
RClKD
TEST2
TEST1
GND
VDD
SOD
CLK
SOC
PDN
TESTO
o 32-kb/s ADPCM codec conforms to CCITT
Recommendation G.721
- Processes high-quality modem signals up to
4800 bls
- Recovers from an error in the
telecommunication circuit
- Free from sound quality degradation in
multistage digital connections
o Built-in digital signal processor (DSP)
o Simultaneous coding and decoding
o Pin-selectable PCM format: !1-law, A-law, or 16-bit
linear
o Selectable coder and decoder muting
o Direct interface with p-Iaw or A-law PCM codec
o Low operating power
- 28 mA max at 5 V
-20 mA max at 2.7 V
o Power-down mode
- 100 pA max at 5 V
-70 pA max at 2.7 V
Ordering Information
Part No.
Package
jlPD77522GU
28-pin plastic SOP (450 mil)
50559
SIC
RCLKC
FSELO
XCLKC
FSEL1
MUTEC
TSEL
MUTED
SSRD-811OA
ml:
NEe
pPD77522
Pin Identification
Pin Identification (cont)
Symbol
1/0
Function
Symbol
1/0
ClK
In
System clock, 10 to 14 MHz
TSEl
In
Function
Data input/output timing select
FSElO
In
Format select 0
XClKC
In
Transmit (output) data ciock to coder
Transmit (output) data clock to decoder
FSEl1
In
Format select 1
XClKD
In
MUTEC
In
Coder mute control
XSYNCC
in
Frame sync for coder ADPCM output
MUTED
In
Decoder mute control
XSYNCD
In
Frame sync for decoder PCM output
PDN
In
Power-down control
VDD
In
+5-volt de power
RClKC
In
PCM data clock to coder
GND
In
Signal and power ground
RClKD
In
ADPCM data clock to decoder
RSTC
In
Coder reset
RSTD
In
Decoder reset
RSYNCC
In
Frame sync for coder PCM input·
FUNCTIONAL OPERATION
RSYNCD
In
Frame sync for decoder ADPCM input
SIC
In
PCM seriai data input to coder
SID
in
ADPCM serial data input to decoder
SOC
Out
ADPCM serial data output from coder
SOD
Out
PCM serial data output from decoder
TESTO
in
Factory test; connect to ground for
normal use
TEST1-TEST4
I/O
Factory test; connect to ground for
normal use
The block diagram shows serial data signal flow
through the pPD77522, PCM-to-ADPCM on the coder
side and ADPCM-to-PCM on the decoder side. Note
that signal names are suffixed with C or D to denote the
coder or decoder side, respectively.
Figure 1 shows the equivalent circuits at input and
output pins.
Block Diagram
Mute
SIC
RCLKC
PCM
Input
Coder
soc
ADPCM
Output
RSYNCC
XCLKC
XSYNCC
MUTEC------------------------~
RSTC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Digital
Signal
Processor
RSTD---------------------------------,
MUTED------------------------,
Decoder
SOD
XCLKD
XSYNCD
CLK--1
PDN
TSEL
FSELO
FSEL1
SID
PCM
Output
ADPCM
Input
RCLKD
RSYNCD
Clock
Control
J
~CLK
-vDD
_GND
Control
Circuits
S3RD-8109B
2
NEe
JlPD77522
Data Signal Interface
Figure 1. Input and Output Circuits
+5V
tPins RCLK, XCLK,
RSVNC~VNC,
MUTE, RST, SI
Pins FSEL 1,
TSEL
Internal
circuit
CMOS
Input
Table 1. PCM and ADPCM Interfaces
tAdd suffix C or 0 to signal name for coder or
decoder application. For example RCLKC or RCLKD.
+5V
Pins CLK, FSELO,
PDN
~
PCM and ADPCM data signals are input or output
serially (MSB first) in synchronization with the frame
sync and data clock Signals listed in table 1. Frame
sync is 8 kHz and the data clock is in the 64 kHz to 2.048
MHz range.
Internal circuit
CMOS
input
Interface
Frame Sync
Data Clock
Data
PCM input to coder
RSYNCC
RCLKC
SIC
ADPCM output from coder
XSYNCe
XCLKC
SOC
ADPCM input to decoder
RSYNCD
RCLKD
SID
PCM output from decoder
XSYNCD
XCLKD
SOD
Data Signal Timing
Pins SOC, SOD
NMchannel
open-drain
output
F
~lnternal
~Clrcult
83RD-8111A
Power-Up
Following the application of power; the pPD77522 enters the standby state within 250 ps after system clock
(ClK) input. In this state, PCM or ADPCM signals may
be input. See figure 2.
low inputs at RSTC and RSTD reset the coder and
decoder, enabling operation. Reset timing is the same
as the timing in figure 2 to fetch the least significant bit
(lSB) of the SIC and SID input data. The state of the
SOC and SOD output pins at reset is high impedance
or low level.
Power-Down
Two clock cycles after a low level is applied to the PDN
pin, the pPD77522 enters the power-down mode. The
low level must be maintained for at least four clock
cycles. See figure 3.
In power-down mode, the SIC and SOD output pins are
in the high-impedance state.
Two clock cycles after a high level is applied to the PDN
pin, the pPD77522 is released from the power-down
mode. Before restarting the pPD77522, reset the coder
and decoder by low inputs at the RSTC and RSTD pins.
The first data bit of a frame may begin with the rising or
falling edge of frame sync depending on the type of •
PCM codee the pPD77522 interfaces. The selection is
:.. made by connecting the TSEl pinto + 5V (1) or ground
(0) as shown in figure 4,
PCM Codec
pPD95xx Series
pPD96xx Series
TSEl Pin
1
o
Coder Operation
When frame sync RSYNCC goes high, input data from
the PCM codec at the SIC pin is stored in an internal
register in synchronization with the trailing edge of
data clock RClKC. The data may be 8-bit companded
or 16-bit linear.
The coder converts the PCM input data to 4-bit ADPCM
output data and stores it in an internal register. When
frame sync XSYNCC goes high, the ADPCM data is
output at the SOC pin in synchronization with the
leadi ng edge of data clock XClKC. The SOC pi n returns
to high impedance when the data output is complete.
Decoder Operation
When frame sync RSYNCD goes high, 4-bit ADPCM
input data at the SID pin is stored in an internal register
in synchronization with the trailing edge of data clock
RClKD.
The decoder converts the ADPCM input data to PCM
data, 8-bit companded or 16-bit linear. When frame
sync XSYNCD goes high, the PCM data is output at the
SOD pin in synchronization with the leading edge of
data clock XClKD. The SOD pin returns to high impedance when the data output is complete.
3
Ii
NEe
pPD77522
Figure 2. Power-Up Timing
Power
supply
-----'
~_o_~______~~~
_____________•_________
~~~~nal
Unknown
r-- .._n_d_~_s_~_~
_______________________________________
~
Under processing
RSYNC
Internal
processing ________________________________- /
RCll(
RSYNC
SI
~-----------__.fl_Jl_J1.Jl_
~_
_________ ------1-1______________________
~===========~----------------£'
Coder
4bits
______________________Dec..,oder 8 bits
RST
Note:
Add suffix C or 0 to signal name for coder or
decoder application. For example, RCLKC or RCLKD.
1
:
Latch
L-__________________~I~:-------------------
1
1
83RD-8112B
4
t-lEC
pPD77522
Figure 3. Power-Down Timing
, rlI' rl
I
I
ClK
I
I
L_J
I
I
I
J
L_J
.-----....;.:- - - - - - - - - - - - I
I
I
I
S~~
No_r_m_~
_______
______
_'~~
_______________p_aw
__e_r_D_aw_n________________
_'~~ _r:---------N-or-m-~----------__
:e
....
.,.~
RCLK~ _ _ _ _ _ _ _ _ _ _ _ ~
RSYNC
~ _________ _
I
I
I
SI~===========~I------------------Coder
4bits
_______________________D...,ocooer 8 b~s
RST
Nole:
Add suffix C or D to signal name for coder or
decoder application. For example, RCLKC or RClKD.
L-_ _ _ _ _ _ _ _ _
I
:
6' Latch
~I~=-----------I
I
83RD-81138
5
ttiEC
pPD77522
Figure 4. Data Signal Timing
TSEL=1
RCLK
RSYNC~
I
I(
SI
~I
Coder 8116 bits; dea>der 4 bits
MSB
X
X
X
LSB
X
LSB
)
XCLK
XSYNC~
I
I(
SO
~I
Coder 4 bits; deaxler 8116 bits
MSB
X
X
)
TSEL=O
RCLK
RSYNC~
.~
~I
Coder 8116 bits; decoder 4 bits
MSB
X
X
X
LSB
X
LSB
)
XCLK
XSYNC~
w~
~I
Coder 4 bits; deaxler 8116 bits
MSB
X
X
)
Not.:
Add suffix C or 0 to signal name for coder or
deooder application. For example, RCLKC or RCLKD.
83RD-8114B
6
t-(EC
fJ PD77522
Input-to-Output Delay
Muting
Input data to the coder or decoder is latched on the
trailing edge of the receive data clock and output on the
leading edge of the transmit data clock. If the clocks are
synchronized, there will be a one-half clock cycle delay
between data input and output.
Pins MUTEC and MUTED control muting of the PCM
signal at the coder input and decoder output, respectively. A low level at the pin cuts off the signal within 1
ms; a high level inhibits muting.
Internal Timing
I/O Data Format
The I/O data format at the PCM interface is coordinated with the companding characteristic of the PCM
codec by connecting pins FSELO and FSEL 1 to + 5 V
(1) and GND (0) as shown below.
FSELO
1
1
0
0
FSEL1
1
0
1
0
I/O Data Format
A-law with even-bit inverter
A-law
p-Iaw
16-bit linear
Encoding or decoding (analysis processing) starts on
completion of serial data input. Processed data is
immediately transferred to the intermediate register.
Simultaneously, the previously processed data sample
is transferred to the output register. See figure 5.
The output register contents exit serially in synchronization with the rising edge of the output SYNC signal if
SYNC leads SCK, or the rising edge of serial clock SCK
if SCK leads SYNC.
SYSTEM CONFIGURATION
Figure 6 is an example of a basic system with serial
interfaces. The system uses the pPD9604/pPD9605 as a
PCM codec and the pPD78C14 as a control CPU.
7
NEe
JlPD77522
FigureS. Processing Timing
Input SYNC
n
~
t n+1
tn
Input==>(
register
Data (n)
X
X
Data (n + 1)
(
Process ( n + 1)
OUlput==>(
(process ( n + 3)
tn+1
X
X
Data (n)
X
~~~~gg~~______________~n~
tn+2
Data (n + 1)
~n
Data(n-1)
register
Data(n+3)
0
)
tn
~n-1
X
Data (n + 2)
Process ( n + 2)
0
Intermediate
register
t n+3
t n+2
Process n
Analysis
processing
n
n
~n+1
X
Data (n)
X
Data (n + 2)
~ n+2
Data (n + 1)
X
Data(n+2)
______________~r-l~______________~r-l~_________
SOC
SOD
Data (n-2)
XSYNCC
XSYNCD
Data (n -1)
n
n
--------~
Data (n)
~----------~
Data(n + 1)
n
~----------~
~---------------------
~g------------<
Data (n -1)
Serial Data Input End Timing
At the trailing edge of the 4th serial clock pulse (for decoding) or the
8th or 16th (for encoding) after the leading edge of the input SYNC
signal, serial data Input Is completed. Thus, the lower the serial
clock frequency, the greater a delay of the serial data end ~mlng to
the input SYNC signal.
Data(n)
Data (n + 1)
Analyzed Data Transfer Timing
This transfer timing is the same as the serial data input end timing
provided data will be delayed by one pulse period. In other
words, ion isconcurrentwith tn+ 1.
n Sample number
Analysis Processing End Timing
The analysis processing time is not fixed.
Processing will be completed by the end of the next serial
data Input.
83R[)..8115B
8
ttiEC
pPD77522
Figure 6. System Configuration
SCK
SYNC
CLK
Clock
Generator
8kHz
64 kHz to 2.048 MHz
PCM Codec
,.
-'"
-
oL..
Dx
CLKX
FSx
AIN
AOUT
+5V
J
fLPD9604/05
DR
CLKR
FSR
- 1
I
J
1
~
>-::;-0-
+5V
L
-5V
~
r
r
SIC
RCLKC
RSYNCC
SOC
XCLKC
XSYNCC
SOD
XCLKD
XSYNCD
SID
RCLKD
RSYNCD
TSEL
TESTO
TEST1
TEST2
TEST3
TEST4
>-~ FSELO
>-0
LOOP
VDD
+5V
FSEL1
PDN/BS
I
DGND
AGND
DGSx
DGSR
fLPD78C14
Microcomputer
RxD
I--<
r--- .........
SCK
TxD
~
ICPU
r------<
r------<
r------<
r------<
n
RSTC
VDD
GND
MUTEC
1:7
vss
~
fLPD77522
ADPCM Codec
RSTD
PDN
Port
MUTED
CLK
I
:-l
10 to 14 MHz
83RO-8117B
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Recommended Operating Conditions
= -40 to + 65°C
TA
TA = +25°C
-0.5 to +7.0 V
Power supply voltage, VDD
Input voltage, VI
-0.5 to VDD + 0.5 V
Open drain output voltage, V0
- 0.5 to + 6.0
V
Parameter
Symbol
Min
Operating
voltage
VDD1
2.7
5.5
V
fCLK = 10 to
11 MHz
V DD2
4.0
5.5
V
fCLK = 10 to
14 MHz
0.3 V DD
V
VDD = 2.7
to 5.5 V
-40 to + 65°C
Operating temperature, TOPT
- 65 to + 150°C
Storage temperature, TSTG
Capacitance
TA = +25°C
Parameter
Symbol
Input capacitance
CIN
10
pF
Output capacitance
COUT
15
pF
I/O capac i t ance
Cvo
20
pF
Min
Max
Unit
Low-level
input
voltage
V IL
High-level
input
voltage
VIH
0.7 VDD
Typ
Max
Unit Conditions
V
VDD
=
2.7
to 5.5 V
9
ttlEC
pPD77522
DC CharacteristiCs
+ 85°C; fClK =
TA = -40 to
11 MHz; Voo = 2.7 to 5.5 V
Parameter
Symbol
Current consumption
1001
Current consumption in power down mode
10D2
Min
Typ
Max
Unit
Conditions
20
28
mA
twc = 91 ns, Voo = 5.0 V
15
20
mA
twc = 91 ns, Voo = 2.7 V
100
JiA
VOO = 5.0 V
70
JiA
Voo = 2.7 V
0.45
V
IOl= 2mA
low-level output voltage
VOL
High-level output voltage
VOH
low-level input leakage current
III
10
JiA
Vil = OV
High-level input leakage current
IIH
-10
J1A
VIH = Voo
AC CharacteristiCs
+ 85°C; Voo =
TA = -40 to
V
VoO-0.3
IOH = -20 JiA
2.7 to 5.5 V
Parameter
Symbol
Max
Unit
91
100
ns
VOO = 2.7 to -5.5 V
72
100
ns
Voo = 4.0 to -5.5 V
twCl
40
50
ns
See timing charts
ClK high pulse width
twCH
40
50
ns
ClK rise time
tclH
10
ns
ns
kHz
ClK cycle time
twc
ClK low pulse width
ClKfalitime
Min
Typ
tCHl
10
Transmit clock frequency
tXClK
2048
Receive clock frequency
tAClK
2048
Transmit sync signal frequency
txSYNC
8
Receive sync signal frequency
tRSYNC
8
kHz
kHz
kHz
twxSl
XClK
Transmit sync signal high pulse width
twxsH
XClK
Transmit sync signal low pulse width
twRSl
RClK
Receive sync signal high pulse width
twASH
Transmit sync signal low pulse width
Transmit sync signal set time
tsxs
Transmit sync signal hold time
tHXS
8
ns
Receive sync signal set time
ns
tsRS
140
ns
Receive sync signal hold time
tHAS
8
ns
SI, RST, MUTE set time
tso
40
ns
tHO
8
ns
Serial mode; SO delay time vs XSYNC
SO delay time vs XClK t
t
tpDS
90
ns
tpoc
130
ns
Note: The voltage at the measurement point is 1/2 V ~O.
10
Measured at 1/2 VOO
RClK
140
SI, RST, MUTE hold time
Conditions
Measured at 1/2 VOO (vs XClK)
Measured at 1/2 VOO (vs RClK)
Rl = 1000 0; Cl = 100 pF
1ttfEC
pPD77522
Timing Waveforms
Clock Input
tCLH
10%
VIL----1
~---tWCL---__r----tWCHI---~
~--------twc-------~
Serial Data Input
J
{,------,I
tWRC
E
RCLK
}_.--/
~
tWRSH
RSYNC
SI,RST,
MUTE
~S,r,------.l/
t WRSL _ )
------- ~_ .i~"~__J"-------;S)S----'
X
X
X
'-------~ ~tSD
~Ic
tHD~
:x---
Serial Data Output
XCLK
{
XSYNC
83R0-8116B
11
pPD77522
12
fttfEC
tttlEC
Development Tools
fttlEC
Development Tools
Section 5
Development Tools
Third-Party Development Tools
5-1
pPD77C2OA, 7720A, 77P20 Digital Signal
Processors
EVAKIT-7720B
pPDn20 Standalone Emulator
5a
ASM77
pPD7720 Absolute Assembler
Sb
pPD77C25/77P25 Digital Signal Processor
EVAKIT-77C2S
pPD77C25 Standalone Emulator
Sc
RA77C2S
pPD77C25 Relocatable Assembler Package
Sd
SM77C2S
PC-Based Simulator for pPD77C25 and
pPD77C20
Se
pPD77220/P220, pPD77230/P230 Digital Signal
Processors
pPD77240 Digital Signal Processor
IE-77240
In-Circuit Emulator for the pPD77240
Sk
RA77240
Relocatable Assembler Package
SI
pPD778tO Modem Digital Signal Processor
IE-77810
In-Circuit Emulator for the pPD77810
Sm
RA7781 0
Relocatable Assembler Package for the
pPD77810
Sn
pPD775x ADPCM Speech Processors and
pPD7750t ADPCM Record and Playback Speech
Processor
NV-300
Speech Analysis Tool for pPD775X and
pPD77501
50
EVAKIT-77220
pPD77220 Standalone Emulator
5f
NV-31 0
Speech Analysis Tool for pPD775x
Sp
EVAKIT-77230
pPD77230 Standalone Emulator
S9
EB-77Sx
Demonstration and Evaluation Box for
pPD775x
Sq
DDK-77220A
pPD77220 Evaluation Board
Sh
PG-1S00 Series
EPROM Programmer
Sr
RA77230
pPD77220/pPDn230 Relocatable Assembler
Package
Si
SM77230
PC-Based Simulator for pPD77220/pPD77230
Sj
t-IEC
Development Tools
THIRD-PARTY DEVELOPMENT TOOLS
This list summarizes the development tools of these
companies at this time. NEC makes no recommendation for any of these tools; this list is provided for
information only. Contact the third-party company directly for further information on product features, availability, and pricing.
Company
Description
Host
NEC Device
Data VO
10525 Willows Road NE
P.O. Box 97046
Redmond, WA 98703-9746
(206) 867-6899
(800) 247-5700 ext. 600
EPROM/OTP Programmer
PC-DOS®
JlPD77P20D
JlPD77P230R
JlPD77P25C/D/L
JlPD77P56CR
Elan Digital Systems
538 Valley Way
Milpitas, CA 95035
(408) 946-3864
(800) 541 -3526
OTP Programmer
PC-DOS
JlPD77P56CR
JlPD77P56G
Hyperception, Inc.
9550 Skillman LB 125
Dallas, TX 75243
(214) 343-8525
DSP Development
Software/System
PC-DOS
(DDK-77220)
JlPD77220
Intermetrics Microsystems
Software, Inc.
733 Concord Avenue
Cambridge, MA 02138-1002
(617) 661 -0072
(800) 356-3594
C Compiler and Assembler
(C Source Debugger)
VAX®/VMS®
VAX/UNIX®
Sun·M/UNIX
Apollo®
HP®"UX·M
(MS-DOSIilj
JlPD77220
JlPD77230
JlPD77240
(IE-77240)
Signalogic, Inc.
9704 Skillman #111
Dallas, TX 75243
(214) 343-0069
DSP Development Software
PC-DOS
JlPD77220
Signix Corporation
19 Pelham Island Road
Wayland, MA 01778
(508) 358-5955
DSP Development Software
PC-DOS
JlPD77C20A
JlPD77C25
Xeltek
764 San Aleso Avenue
Sunnyvale, CA 94086
(408) 745-7974
EPROM/OTP Programmer
PC-DOS
JlPD77P56
JlPD77P25
•
(Hypersigna~Macro)
PC-DOS is a registered trademark of International Business
Machines Corporation.
VAX and VMS are registered trademarks of Digital Equipment Corporation.
UNIX is a registered trademark of UNIX System Laboratories, Incorporated.
Sun is a trademark of Sun Microsystems, Incorporated.
Apollo is a registered trademark of Apollo Computer, Incorporated.
HP is a registered trademark and UX is a trademark of HewlettPackard Company.
MS-DOS is a registered trademark of Microsoft Corporation.
5-1
I
Development Tools
5-2
ttlEC
t\'EC
NEG Electronics Inc.
Description
The EVAKIT-7720B is a standalone emulator for NEC's
JlPD7720A, JlPD77P20, and JlPD77C20A digital signal
processing interfaces (SPI). The EVAKIT-7720B provides complete hardware emulation and software debug capabilities for the SPI. Real-time and single-step
emulation capability, a powerful on-board system monitor, and a user-specified breakpoint create a powerful
debug environment.
The EVAKIT-7720B is controlled over a serial line from a
terminal or host computer system. User programs are
downloaded into the instruction ROM and data ROM
emulation memory through a serial line or read from an
EPROM device. An on-board programmer for JlPD2732
and JlPD2732A EPROMs provides an easy means for
submitting your final code for production. You can also
use the EVAKIT-7720B to program the JlPD77P20
EPROM version of the part for final system test and
evaluation.
Features
o Real-time single-step emulation capability
- Real-time program execution at 8 MHz
- Real-time program execution with address
breakpoint and loop counter (up to 256 loops)
- Real-time program execution for a number of
steps
- Single-step program execution with display of
address, instruction, registers and flags
o On-board emulation memory:
Instruction ROM, data ROM and internal RAM
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
50345
EVAKIT-7720B
pPD7720 Standalone Emulator
o Powerful system monitor
- Display/change/initialize instruction and data
ROM
- Display/change/initialize internal RAM
- Display/modify internal registers
- Read/write/display/verify/blank check EPROM
device
- Upload/download/verify instruction and data
ROM
- Perform self-diagnostics
- Reset emulation chip
o Supports two operating modes
- External terminal controlled
- Host computer system controlled
o Emulator controller for IBM PC®, PC/XT®, PC/AT® or
compatibles
o Serial interface: RS-232C, TTL, or 20 mA current
loop
o EPROM programming capability (JlPD2732,
JlPD2732A, JlPD77P20)
o Requires an external power supply
Ordering Information
Part Number
Description
EVAKIT·7720B
Standalone emulator for f.lPD7720A/P20/C20A
#,PD7720 Standalone Emulator
EVAKIT·7720B
2
t't{EC
ttlEC
NEC Electronics Inc.
Description
The ASM77 Absolute Assembler converts symbolic
source code for the NEC p.PD7720A/77P20/77C20A Digital Signal Processing Interfaces (SPI) into executable
absolute address object code. Two separate assemblers
are provided: one assembles the source program for the
Instruction ROM; the other assembles the source program for the Data ROM. An object code file is produced
in ASCII hexadecimal format and may be downloaded to
an EPROM programmer or the NEC stand-alone emulator, the EVAKIT-7720B.
The NEC ASM77 assembler is available for operation on
an MS-DOS computer system with at least one disk
drive and 128KB of installed system memory.
ASM77
"PD7720 Absolute Assembler
Ordering Information
Part Number
Description
ASM77-D52
MS-DOS, 5.25" Double Density Disk
ASM77 Block Diagram
Table
File
ASM77
Jl.PD7720 Assembler
(Instruction or Data)
Features
o
o
o
o
o
Absolute address object code output
Free format statements
Separate assemblers for instruction and data ROMs
User-selectable and directable output files
Runs under the MS-DOS operating system
Object
Code
File
r-:I
L:.J
83ML·G094A
!
MS-DOS Is a registered trademark of Microsoft Corporation
50183
I
ASM77
2
NEe
t-IEC
NEG Electroni cs Inc.
Description
The EVAKIT-77C25 is a standalone emulator for NEC's
pPD77C25 and pPD77P25 digital signal processing interfaces (SPI+). The EVAKIT-77C25 provides complete
hardware emulation and software debug capabilities
for the SPI+. Real-time and single-step emulation capability, coupled with sophisticated breakpoint capability, real-time tracer and a powerful on-board system
monitor, create a powerful debug environment. A line
assembler and symbolic disassembler, full register and
memory control and complete upload/download capabilities simplify the task of debugging hardware and
software.
An on-board EEPROM is available for storage of the
current debug environment during EVAKIT power
down. Using the freeze (FRZ) command, the current
contents of the instruction and data ROM, the internal
RAM, the SPI+ registers, the break registers and registered command strings are saved to the EEPROM.
The Melt (MLl) command restores this information.
The EVAKIT-77C25 is controlled via serial line from a
local terminal or host computer system. User programs
can be uploaded from or downloaded to the Instruction
and data ROM emulation memory through a serial line
from a local host computer, a remote host computer
system, or an external EPROM programmer. NEe provides an emulator controller program for use on an IBM
PC®, PC/XT®, PC/AT® or compatible local host computer. To transfer data to/from a remote host computer
system, the EVAKlT-77C25 can be placed into terminal
emulation mode and be used as a terminal for the
remote system. Data can also be read from or written to
an external EPROM programmer under the control of
the on-board monitor.
Features
o Real-time and single-step emulation capability
- Real-time program execution with/without
breakpoint
-Single-step program execution with trace
display
IBM PC, PC/XT and PC/AT are registered trademarks of International
Business Machines Corporation.
50343
EVAKIT-77C25
pPD77C25 Standalone Emulator
o Subcommands available during real-time
emulation
- Generate an interrupt to the emulation chip
- Read/display status register
- Read/write the data register
- Reset the emulation chip
o On-board emulation memory
-Instruction ROM: 2k x 24 bits
-Data ROM: 1k x 16 bits
- Data RAM: 256 x 16 bits
o Symbolic debug capability
- Symbols may be used to specify addresses for
commands
-Symbolic disassembler
- Symbol table clear command
o Powerful system monitor
- Display/change/initialize instruction and data
ROM
- Display/change/initialize internal data RAM
- Display/modify general and status registers
- Transfer data to/from external EPROM
programmer
- Upload/download instruction and data ROM
code
- Line assembler
- Display break registers
- Reset emulation chip
- Set internal/external clock
- Mask interrupt (INl) signal from probe
o Sophisticated breakpoint capability
- Break on address and pass count (up to 65,535
passes)
- Break on being in or out of address range
- Breakpoints specified on command line or
preset in the break address, address range, and
mode registers
- Up to 37 break addresses or address ranges can
be set
o Real-time program trace feature
- Store 4092 clocks worth of information
- Traces program counter, data bus, RD, WR,CS,
AD, DRQ, DACK, RST, INT, PO, P1, SCK, SI, SIEN,
SO, SOEN, and SORQ
- Displays trace with/Without mnemonics
- Trace buffer pointer and search capability
o EEPROM for temporary storage of instruction and
data ROM, internal RAM and registers, break
registers, command strings
.",
NEe
EVAKIT-77C25
"PD77C25 Standalone Emulator
o On-line help facility
o Three RS-232C serial ports
-CH1: Terminal or local host system
-CH2: Remote host system
- CH3: EPROM programmer
o Emulator controller for IBM PC, PC/XT, PC/AT or
compatibles
Ordering Information
Part Number
Description
EVAKIT·77C25
Standalone emulator for IlPD77C25/P25
2
fttlEC
EVAKIT-77C25
Block Diagram
Monitor
Work
ROM
RAM
SUpervisor
CPU
~PD70116
Instruction
Data
Memory
Memory
Trace
Memory
EYACHIP
Probe
VF
~PDnC26
Control
Clrcuft
ErnulaUon Probe
83ML~OOB
3
EVAKIT-77C25
4
1tiEC
NEe
RA77C25
pPD77C25 Relocatable
Assembler Package
NEC Electronics Inc.
Description
The RA77C25 Relocatable Assembler Package converts symbolic source code for the pPD77C25 and
pPD77P25 Digital Signal Processors into executable
absolute address object code. It can also be used for
pPD7720A/77C20A/77P20 program development by
creating a pPD7720 hex-format object module using
the hex converter.
The relocatable assembler package consists of five
separate programs: an assembler (RAnC25), a linker
(LK77C25), a hexadecimal format object code converter (OCnC25), a librarian (LB77C25), and a hex
converter (HC7720).
Hcmo converts a pPD77C25 hex-format object module file output by the object converter to the format of
a pPD7720 hex-format object module output by the
pPDn20 absolute assembler. For code with the
pPD7720 as the target, error checking for mnemonics
included in the pPD77C25 but not in the pPD7720,
address space and RAM-to-RAM transfer functions are
only performed by hex converter. File format can be
separate IROM and DROM hex-format object module
files or acombined IROM and DROM object module file.
Features
o Absolute address object code output
o User-selectable and directable output files
RA77C25 translates a symbolic source module file with
"include" files into a relocatable object module. The
assembler produces a relocatable object module file
and a listing file that can contain the assembly list,
symbol list, and cross-reference list. If absolute addresses have been specified in the source module file
and no relocatable segments or external variables or
labels are referenced, the assembler can output an
ASCII hexadecimal format object file and a symbol
table file directly.
o Extensive error reporting
LKnC25 combines relocatable object modules, library
modules when necessary, and other linker load modules and converts them into an absolute load module.
The linker produces a link map and an absolute load
module.
Ordering Information
OC77C25 converts an absolute object module from
RA77C25 or an absolute load module from LKnC25
into an ASCII hexadecimal format object file and a
symbol table file.
LB77C25 allows commonly used relocatable object
modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input of the linker,
the linker extracts only those modules required to
resolve external references from the file and relocates
and links them.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
UNIX is a registered trademark of UNIX System Laboratories, Incor·
porated.
Ultrix is a trademark of Digital Corporation.
50146·1
o Macro capability
o Conditional assembly directives
o Powerful librarian
o Runs under the following operating systems:
-MS-DOS@
-VAX@NMS@
- VAX/UNIX® 4.2BSD or Ultrix™
Description
RA77C25-D52
MS-DOS, 5.25" double density diskette
RA77C25-VVT1
VAX/VMS, g-track 1600 BPI magnetic tape
RA77C25-VXT1
VAX/UNIX 4.2BSD or Ultrix, g-track 1600BPI
magnetic tape
NEe
RA77C25
Block Diagram
9
ld t-~---------I
~
Source Module Ale
Include Ale
Object
Module Ale
RA77C25
Assembler
I-~ 9
L-~I__~I~
Assemble Us!
Symbol Ust
Cross-reference List
LB77C25
Ubrarian
,-.-
L-~~
I
I
I
I
I
I
:
1----1
:
I
I
I
I
I
,----------------1--------1--- 1
u
I
Ubrary Us!
LK77C25
Unl7963
026: OP MOV @MEM.B
OB2: 6179
1027:)OP MOV @NON.TR:AND ACCB.IDB
OB3: 7963
1028: JNZB 02C
IOB4: 0000
1029: OP MOV @B.MEM:SHLI ACCA
lOBS: 0000
I 02A: OP SHU ACCB
OB6: 0000
102B: JMP 026
OB7: 0000
DRAM------i
102C: OP MOV @B.MEM
102D: LDI @TR.7FFF
00:)7963
102E: OP MOV @MEM.A:OR ACCA.IDB
1 01: 0000
02: 0000
I02F: OP MOV @NON.TR:AND ACCB.IDB
1030: JZB 03F
03: 0000
1031: OP MOV @K.B:DPINC
04: 0000
1032: CALL 040
05: 0000
1033: OP MOV @K.A:AND ACCA.IDB:DPDEC
06: 0000
I
I
I
I
I
I
IFI-HelpIF2-NextIF3-LastIF4-TraceIF5-5tepIF6-GoIF7-RunIF8-BrkptIF9-FilesIF10-Cmds
'
,
I
,
,
,
,
I
ISM) read hex div_tst
I
I SM>
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I
I
I
Block Diagram
Files
Files
Parallel Input Data
PID
cs
SOEN
SID
Serial Input Data
Parallel Output Data
POD
WR
SORa
SOD
Serial Output Data
Parallel 110 Timing
PIT
AD
SO
SIT
Serial Input Timing
DR
SIEN
SOT
Serial Output Timing
SM77C25
Simulator
,NT
2
SI
SCK
ORO
PO
DACK
P1
-
83RD-B312B
NEe
NEG Electronics Inc.
Description
The EVAKIT-77220 is a standalone emulator for NEC's
pPD77220 and pPD77P220 24-Bit Fixed Point Digital
Signal Processors. The EVAKIT-77220 provides complete hardware emulation and software debug capabilities for the pPDn220/P220. The device includes realtime and single-step emulation capability with
sophisticated breakpoint capability, real-time tracer,
and a powerful debug environment. A symbolic line
assembler and disassembler, full register and memory
control and complete upload/download capabilities
simplify the task of debugging your hardware and
software.
The EVAKIT-77220 is controlled via serial line from a
local termi nal or host computer system. User programs
can be uploaded from or downloaded to the instruction
and data ROM emulation memory through a serial line
from either a local host computer, a remote host computer system, or an external EPROM programmer. NEC
provides an emulator controller program for use on an
IBM PC®, PCIXT@>, PC AT@ or compatible local host
computer. To transfer data to or from a remote host
computer system, the EVAKIT-77220 can be placed into
terminal emulation mode and used as a terminal for the
remote system. Data can also be read from or written to
an external EPROM programmer under the control of
the monitor.
Features
o On-board emulation memory for:
-Instruction ROM, data ROM, and internal data
RAM
- External emulation RAM: fast/slow speed
o Selectable clock: internal or external
o Real-time and single-step emulation capability
- Real-time program execution with/Without
breakpoint
-Single-step program execution with trace
display
o Console I/O available during real-time emulation
to:
- Generate INT and NMI signals to emulation chip
- Generate HWR, PO and P1 signals to emulation
chip
- Display HRD, P2, P3 and ROM signals from
emulation chip
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
50142
EVAKIT· 77220
IIPD77220 Standalone Emulator
o Memory manipulation commands
- Change/display/fill/move/search date in:
Internal instruction/data ROM
Internal data RAM
External emulation RAM
o Register manipulation commands
- Change/display general and status registers
- Read/Write DRS, read SI, and write SO registers
o Powerful system utilities
- Transfer data to/from external EPROM
programmer
- Upload/download instruction/data ROM code
and symbols
- Transfer external memory contents between
EVAKIT/prototype
- Reset emulation chip
-Specify internal/externallNT, NMI, and Reset
signals
- External memory mapping: internal/user, fast/
slow
o Symbolic debug capability
-Symbols may be used to specify addresses in
commands
-~ymbolic line assembler and disassembler
-Symbolic add/change/display/delete commands
o Sophisticated breakpoints for master and slave
modes
-Instruction memory address or specified
instruction
-Internal data RAM address or specifies data
value
- External memory address or specified data
value
- Loop counter borrow
- External break signal from probe
- Up to 65536 passes
- Read/Write data from host system (slave mode
only)
- Breakpoints specified on command line or
preset in ten logical break registers
o Real-time program trace feature
- Store 2048 clocks worth of information
- Trace starts with emulation or on an address
- Traces program counter, ROM counter, loop
counter borrow, internal bus, SIAK, SOAK, most
external pins
- Displays trace with/Without mnemonics
- Trace buffer pointer and search capability
..
I
!ttlEC
EVAKIT-77220
EVAKIT-77220 Block Diagram
o On-line help facility
o Automatic command execution from macro
command table
o Three RS-232C serial ports
-CH1: Terminal or local host system
-CH2: Remote host system
- CH3: EPROM programmer
o Emulator controller for IBM PC, PC/XT, PC AT or
compatibles
Ordering Information
Part Number
Description
EVAKIT-77220
Standalone emulator for /lPD77220/P220
I'PD77220 Standalone Emulator
2
Driver Boards
Control Boards
. System CPU, V30
SystamROM
SystamRAM
Senal VO
tnterrupt ControHer
nmer
Trace
Control
Signals
Emulation Chip
EmulaUon Memory
Instruction ROM
Data ROM
Extemal RAM
Break C/!l;ultry
Trace Clll:Ultry
ExtemaJ
Control
SIgnal
EmulaUon
Probe
D
System Bus
D
83ML-eooeA
NEe
NEG Electronics Inc.
Description
The EVAKIT-n230 is a standalone emulator for NEC's
IlPD77220 24-bit fixed point digital signal processor
and IlPDn230 32-bit floating point advanced signal
processor (ASP). The EVAKIT-n230 provides complete
hardware emulation and software debug capabilites
for the ASP. Real-time and single-step emulation capability, coupled with sophisticated breakpoint capability, real-time tracer and a powerful on-board system
monitor, create a powerful debug environment. A symbolic line assembler and disassembler, full register and
memory control and complete upload/download capabilities simplify the task of debugging hardware and
software.
The EVAKIT-m30 is controlled via serial line from a
local terminal or host computer system. User programs
can be uploaded from or downloaded to the instruction
and data ROM emulation memory through a serial line
from a local host computer, a remote host computer
system, or an external EPROM programmer. NEC provides an emulator controller program for use on an IBM
PC®, PCjXT®, PC/AT® or compatible local host computer. To transfer data to/from a remote host computer
system, the EVAKlT-77230 can be placed into terminal
emulation mode and be used as a terminal for the
remote system. Data can also be read from or written to
an external EPROM programmer under the control of
the monitor.
Features
o On-board emulation memory for
-Instruction ROM, data ROM, internal data RAM
- External emulation RAM: fast/slow speed
o Selectable clock: 13.37/6.68/3.34 MHz internal or
external
o Real-time and single-step emulation capability
- Real-time program execution with/without
breakpoint
-Single-step program execution with trace
display
o Console I/O available during real-time emulation to
- Generate INT and NMI signals to emulation chip
pcnn:
IBM PC,
and PC/AT are registered trademarks of International
Business Machines Corporation.
50347
EVAKIT-77230
pPD77220/230 Standalone Emulator
- Generate HWR, PO and P1 signals to emulation
chip
- Display HRD, P2, P3 and ROM signals from
emulation chip
o Memory manipulation commands: Change/display/
fill/move/search data in
Internal instruction/data ROM
Internal data RAM
External emulation RAM
o Register manipulation commands
- Change/display general and status registers
- Read/write DRS, read SI, and write SO registers
o Powerful system utilities
- Transfer data to/from external EPROM
programmer
- Upload/download instruction/data ROM code
and symbols
- Transfer external memory contents between
EVAKIT/prototype
- Reset emulation chip
-Specify internai/externaIINT, NMI, and reset
signals
- External memory mapping: internal/user, fast/
slow
..
I
o Symbolic debug capability
-Symbols may be used to specify addresses in
commands
- Symbolic line assembler and disassembler
- Symbol add/change/display/delete commands
o Sophisticated breakpoints for master and slave
modes
-Instruction memory address or specified
instruction
-Internal data RAM address or specified data
value
- External memory address or specified data
value
- Loop counter borrow
- External break signal from probe
- Up to 65536 passes
- Read/write data from host system (slave mode
only)
- Breakpoints specified on command line or
preset in ten logical break registers
o Real-time program trace feature
- Store 2048 clocks worth of information
- Trace starts with emulation or on an address
NEe
EVAKI"(:77230
- Traces program counter, ROM counter, loop
counter borrow, internal bus, SIAK, SOAK, and
most external pins
- Displays trace with/without mnemonics
- Trace buffer pointer and search capability
o On-line help facility
o Automatic command execution from Macro
command table
o Three RS-232C serial ports
-CH1: Terminal or local host system
- CH2: Remote host system
- CH3: EPROM programmer
o Emulator controller for IBM PC, PCIXT, PC/AT or
compatibles
Block Diagram
Control Boards
System CPU - V30
System ROM
System RAM
SerlaJVO
Interrupt Controller
Timer
Driver Boards
Trace
Control
Signals
EmulaUon Chip
EmulaUOn Memory
Instruction ROM
Data ROM
ExtemaJ RAM
Break Circuitry
Trace ClrcuHry
ErnulaUOn
Probe
D
SysIBmBus
D
83ML-6099A.
Ordering Information
Part Number
EVAKlT-77230
Description
Standalone emulator for JlPD77230/P230 and
JlPD77220/P220
2
External
Control
Signal
I'PD77230 Standalone Emulator
NEe
DDK-77220A
pPD77220 Evaluation Board
NEG Electronics Inc.
Description
Applications
The DDK-77220A Evaluation Board for the NEC
pPD77220/77P220 Digital Signal Processor (DSP) provides a low-cost hardware evaluation and development
tool for high-speed digital processing applications. The
DDK-m20A board features a preprogrammed DSP
that contains built-in ROM routines for: FFT, FIR, and
IIR filters; math functions such as SIN, COS, LOG, and
EXP; and serial I/O and others. This board provides an
easy-to-use DSP hardware implementation that allows
a user to become adept at writing DSP programs.
o General-purpose digital signal processing
(FIR, IIR, FF17IFFT)
The DDK-m20A board is a peripheral processor that
occupies a single slot in an IBM PC AT® or compatible.
The DDK board package includes a hardware user's
manual, host software drivers, DSP assembler software (RA77230), DSP programming examples, and additional literature. This DDK package provides a fast
and efficient means for evaluating the DSP in an
application.
Features
o pPD77P220 - 24-Bit Fixed-Point Digital Signal
Processor
o 8K x 32 bit, high-speed external instruction
memory
o 32K x 24 bit, low-speed external data memory
o 8 kHz analog front end
o Daughter board expansion interface
o Programmable address breakpoint
o Hyperception Hypersignal Windows
IBM PC AT is a registered trademark of International Business
Machines Corporation.
50572
o High-speed data modems
o Adaptive equalization (CCITT)
o Echo cancellation
o Numerical processing
o Speech processing
o Instrumentation electronics
o High-speed controls
o Waveform generation
Ordering Information
Part No.
Description
DDK-77220A
Development/Evaluation Board for /1PD77220/
77P220 (IBM based)
DDK-77220A Evaluation Board
NEe
DDK·77220A
Block Diagram
Daughter - BoaRllnterface
"PD77220
---
~
I
Memory
Analog
Arbiter
Break·Polnts
VO
i
,
PC Command Set
PC AT Interface
Application
DSP-Unk
Per1pheral
Hyperslgnal
Windows
,
Host
2
DDK.-7722OA
~
DT-Connect
Peripheral
~
User-Deflned
Peripheral
ttiEC
NEe Electronics Inc.
Description
The RA77230 Relocatable Assembler package converts
symbolic source code for ~PD77220, ~PD77P220,
~PD77230, and ~PD77P230 Advanced Signal Processors
into executable absolute address object code. The Relocatable Assembler package consists of four separate
programs: an assembler (RA77230), a linker (LK77230), a
hexadecimal format object code converter (OC77230),
and a librarian (LB77230).
RA77230 source code modules can be written in either
preassembly language or assembly language. Preassembly language allows programs to be written more simply.
You do not need to consider the fields of an instruction or
their combination, or pay attention to the execution
timing of the ~PD77220/230. The assembler optimizes
the code for you. However, by using assembly language
and paying close attention to the instruction fields and
their combination, and the execution timing of the chips,
much more efficient programs can be written. Since
RA77230 can generate an assembly language source file
from a preassembly language source file, you can manually optimize this code and write both simple and
efficient programs.
RA77230 translates a symbolic source module file containing preassembly or assembly language source code
with include files into a relocatable object module. The
assembler produces a relocatable object module file, a
preassembly language list, and a listing file that can
contain the assembly list, symbol list, and crossreference list.
LK77230 combines relocatable object modules, library
modules, and other linker load modules and converts
them into an absolute load module. The linker produces
a link map and an absolute load module. OC77230
converts an absolute object module from RA77230 or an
absolute load module from LK77230 into an ASCII hexadecimal format object file.
LB77230 allows commonly used relocatable object modules to be stored in one file and linked to multiple
programs, greatly increasing programming efficiency.
When a library file is included as input to the linker, the
MS-DOS is a registered trademark of Microsoft Corporation.
VJ;;X and VMS are registered trademarks of Digital Equipment
Corporation.
Ultrlx Is a trademark of Digital Equipment Corporation.
UNIX Is a trademark of AT&T.
S0157
RA77230
pPD77220/pPD77230 Relocatable
Assembler Package
linker only extracts those modules required to resolve
external references from the file and relocates and links
them.
Features
o Assembles preassembly and assembly language
source code
o Produces absolute address object code
o Supports master/slave modes
o User-selectable and directable output files
o Extensive error reporting
o Macro capability
o Conditional assembly directives
o Powerful librarian
o Runs under the following operating systems:
-MS-DOS4!)
-VAXNMS4!)
- VAX/UNIX'" 4.2BSD or Ultrix lM
Ordering Information
Part Number
Description
RA77230-D52
MS-DOS, 5.25" double density diskette
RA77230-VVT1
VAX/VMS, 9-track 1600 BPI magnetic tape
RA77230-VXT1
VAX/UNIX 4.28SD or Ultrlx, 9-track 1600 BPI
magnetic tape
RA77230
RA77230 Block Diagram
D,~
Y List
preas[i]sembl
Q (DescriPtio~~~
l2:::!J
Preassem
}
SOI~~tUDE
Module File
File
~
Assembly
language
Language)
I
Q
l2:::!J
"{i
~
File
i,
I
~
(Description in uage)
Assembler Lang
Source Module, File
INCLUDE File
Assembly List
Symbol List List
Cross-reference
D
Link Map
/
libraI)' List
Libral)'File
[i]
/
Load
Module
File
HEX-Format,
Object Module F"_e_ _ _ _ _ _ __
83ML-61038
2
t-{EC
NEG Electronics Inc.
Description
The SM77230 Simulator is a software tool for analyzing
program code and I/O timing for two NEC digital signal
processors: pPD77230 32-bit floating-point and
pPD77220 24-bit fixed-point. SM77230 simulates the
operation of pPD77230/220 using your instruction and
data ROM codes. Optionally, specially prepared serial
input and output timing, serial input data, parallel
timing, and parallel input data files may be used. The
simulator can then output to serial and parallel output
data files.
pPD77220 simulation is accomplished by assembling
source code with the 77220 switch option. This option
will allow only legal 77220 code to be assembled.
(77220 source code is a subset of 77230.) SM77230
does not have a mode switch for just 77220 operation.
Features
D
All pPD77230 processor functions can be
simulated.
D
All input pins are simulated by separate timing and
data files. The status of all output pins can be
written to output and data files.
D
Screen swapping by function keys to show all
memory contents, internal and external.
Instruction code can appear as hex code or
assembly language.
D
Status continuously updated at top of screen.
D
Register, RAM, and ROM contents can be
displayed in hex, binary, integer, and scientific real
notation; RAM and ROM areas also in ASCII
notation.
MS-DOS is a registered trademark of Microsoft Corporation.
SM77230
PC-Based Simulator
For pPD77230 and pPD77220
D
Symbolic simulation and debugging ability.
D
In-line assembler and disassembler.
D
Running, stepping, and tracing through programs
possible.
D
Powerful breakpoint settings.
D
Loading of linker, hex and binary files; storing of
hex and binary files supported.
D
Log and resource files for processing retrieval and
status storage.
D
Batch files for stored command sequences.
D
Abbreviated commands.
D
Step count allows accurate determination of
execution timing
D
Powerful help menu.
Ordering Information
Part Number
Description
SM77230-D52
MS-DOS!!>, 5.25" double-density disk
•
NEe
SM77230
Sample Screen Display
I
o NMI:
IClock: 12.50 MHz Step:
OINT:
State: Awaiting Execution Start Command
a
PC: 0000
MODE: MASTER
uPD77230 Signal Processor Simulator. Version 1.91
Copyright (C) 1986.1987.1988 by ATAIR ECHTZEITSYSTEME. all rights reserved
Copyright (C) 1986.1987 by Thomas GATTERWEH. all rights reserved.
177552 bytes available
SM> reg
PC: 0000
IB: FFFFFFFFFFFFFE
I R: NOP
WRO: 00000000000000 PSWS: PSWO
SI: 00000000
SP: a STKO: IFFF
WR1: 00000000000000
OE C Z S OM SO: 00000000
STK1: 1FFF
WR2: 00000000000000 PSWO: 0 0 0 o a TR: 00000000
FD: SPIE
STK2: IFFF
WR3: 00000000000000 PSWI: 0 0 0 OaK: 00000000
STK3: IFFF
NF: TRNORM
WR4: 00000000000000 SR: 00000
L: 00000000
WI: BWRORD
STK4: IFFF
WR5: 00000000000000 SVR: 00
M: 00000000000000
WT: WRBORD
STK5: IFFF
WR6: 00000000000000 AR: 0000
DR: 00000000
STK6: IFFF
IWR7: 00000000000000 LC: 000
EM: 01 BM: NO_BOOKING
STK7: IFFF
IBPO: 000 IXO: 000 BASED: 0 MO: BIO -> 000 (30020074)
IBPI: 000 IX1: 000 BASEl: 0 M1 : BIl ~> 000 (043C0075)
I RP: 000 RPS: 000 RPC:
0: ROM: RP -> 000 (930000C7)
I
ISM> help
I
ITopics available:
IABBREV
BATCH_FILES
ICOMMANDS
CONTINUE
I EXIT
BREAK
DROM
GO
MASTER
RAMO
EXM
I I ROM
10PEN
IRESET
ISYMBOL
LOG
PORT
SCREEN_SWAP
TRACE
SET
CALCULATE
ECHO
HELP
NMI
RAMI
SLAVE
WRITE
@
CLOCK
EDIT_KEYS
INT
NOSTOP
READ
STEP
CLOSE
ERROR
IO_FILES
NUMBERS
REGISTER
STOP
I
SM77230 Block Diagram
External
Memory
Serial Output Timing
i---iAX
SOEN
1<===1 AR
SOCK
14-----1
SORa / - - - - '
SO 1----++1
AD
i - - - i WR
Serial OUtput Data
1<===>1 DATA
Serial Input Data
Command
Input
i
S:..-N'......"••••N'........" ........N
INT
MIS
NMI
...·....,,·N'...=-=.......
~=
...• ..
RESET
SOD
Serial OUtput Data
POD
Parallel Output Data
SOT
Serial OUtputTlmlng
SID
Serial Input Data
PID
Parallel Input Data
!
I
VN'="Av.-.v.~"N'.......v.
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