1992_National_Clock_Generation_and_Support_Design_Handbook 1992 National Clock Generation And Support Design Handbook

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~ National

Semiconductor

CLOCK GENERATION
AND SUPPORT
HANDBOOK
1992 Edition

Definitions and Test Philosophy
Performance Data
Selection Criteria and Datasheets
Physical Dimensions

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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

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TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice, to change said circuitry or specifications.

-I

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Clock Generation & Support
(CGSTM) Family

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Introduction
National Semiconductor has developed this handbook to
help customers with the design of high-speed clock applications. It contains complete and comprehensive device performance data to assist designers and component engineers
in their unique clock distribution applications. Included are
skew performance specifications developed by National
Semiconductor and discussion of the significance of these
specifications as they relate to the end system. Also shown
are the Clock Generation and Support (CGS) product's typical and maximum specifications and product functionality
and additional characterization data such as power vs frequency, skew performance for unbalanced loads, and derating curves which show the skew performance for balanced
output loads across frequency and load. A discussion on
clock modeling and its importance in system design along
with the required information for modeling is also provided.
Finally, criteria for selection is presented with data sheets for
National's currently available CGS products.
Clock Generation and Support has become one of the key
design areas enabling today's CISC and RISC based systems to obtain maximum operating frequencies. The primary
goal of the system clock is to deliver a clock signal to each
component's input pins which meets the system's requirements for: signal skew; acceptable waveshape (rise and fall
time, overshoot, undershoot, voltage swings), and stability
(cycle-to-cycle). The components of clock skew include both
intrinsic skew (pin-to-pin skew within a single chip) and extrinsic skew (clock skew generated from trace routing and
loading).
National's CGS product strategy is to develop devices to
meet customer needs for high speed clock generation and
support applications. What CGS offers today is a series of
optimal solutions for clock distribution applications requiring
devices with high fanout and with guaranteed skew specifications.
For any additional information on device performance or future product availability please contact the National Customer Response Center at 1-800-CRC-9959 or your local sales
office.

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Table of Contents
Section 1
Definitions and Test Philosophy ................. 1-1
Contains test philosophy and definitions of parameters.

Section 2 Performance Data . ................... . 2-1
Contains product performance specifications, characterization data, skew performance studies, temperature vs. Vee
curves and power performance.
Section 3 Selection Criteria . .................... . 3-1
Contains Clock Generation and Support applications, selection criteria and product datasheets.
Section 4 Physical Dimensions .................. 4-1
Contains ordering codes and packaging nomenclature.

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Product Status Definitions

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Definition of Terms
Data Sheet Identification

Product Status

Advance Information

Formative or
In Design

This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.

Preliminary

First
Production

This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.

No
Identification
Noted

Full
Production

This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.

Definition

National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

v

Alpha-Numeric Index
100115 Low Skew Quad Clock Driver ....................................................... 3-20
100310 Low Skew 2:8 Differential Clock Driver ............................................... 3-24
100311 Low Skew 1:9 Differential Clock Driver ............................................... 3-25
100315 Low Skew Quad Differential Clock Driver ............................................. 3-30
CGS74B303/304/305 Octal Divide-by-2 Circuits/Clock Drivers .................................. 3-9
CGS74B2525 1-to-8 Minimum Skew Clock Driver (Bipolar) ..................................... 3-10
CGS74C2525/2526 1-to-8 Minimum Skew Clock Driver (CMOS) ................................ 3-14
CGS74CT2525/2526 1-to-8 Minimum Skew Clock Driver (CMOS TTL Compatible) ................ 3-14

vi

Section 1
Definitions and
Test Philosophy

Section 1 Contents
Test Philosophy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sources of Clock Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tOSLH ... ......... ........................................ ........ ...... ...........
tOSHL'" ................. ........ ...........•.............. ...... ...... ...........

tps .................................... :..........................................

1-3
1-3
1-4
1-4
1-5
1-5
1-5
1-6

tOST .... ................. .•.................•.............. ............ ...........

1-7

tpv ...............................................................................

1-8

1-2

'ZI National
~ Semiconductor

Definitions and Test Philosophy
Test Philosophy
Minimizing output skew is a key design criteria in today's high-speed clocking schemes. National has incorporated new skew
specifications into the eGS family of devices. National's test philosophy is to fully test guarantee all the available skew specifications in order to help clock designers optimize their clock budgets. In addition to these specifications, National's eGS family also
provides extensive bench performance data for skew, rise and fall times, and duty cycle over various output and input conditions
in order to provide designers real-life performance data.
This section provides general definitions and examples of skew and then discusses National's eGS bench performance methods and examples. The actual performance data can be found in Section 3.
CLOCK SKEW
Skew is the variation of propagation delay differences between output clock signal(s).

Example:
If signal appears at out # 1 in 3 ns and in 4 ns at output # 5, the skew is 1 ns.
1 INPUT

CLOCK
DRIVER

.....

---1L/
CLOCK-IN

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::
::
::
::
::
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8 OUTPUTS
CLOCK-OUT

1

2
3

lJ:V

4
5

5

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_8

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SKEW
DUE TO DELAY
UNCERTAINTY
TL/F/l0942-53

FIGURE 1-1_ Clock Output Skew
Without skew specifications, a designer must approximate timing uncertainties. Skew specifications have been created to help
clock designers define output propagation delay differences within a given device, duty cycle and device-to-device delay
differences.

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SOURCES OF CLOCK SKEW
Total system clock skew includes intrinsic and extrinsic skew. Intrinsic skew is defined as the differences in delays between the
outputs of device(s). Extrinsic skew is defined as the differences in trace delays and loading conditions.

:E

INTRINSIC SKEW

EXTRINSIC SKEW

CLOCK-OUT

JL

OUT

CLOCK-IN

~

SKEW DUE TO
DEVICE AND TRACE/LOAD DELAYS

TLlF/l0942-54

FIGURE 1·2. Sources of Clock Skew
Example: 50 MHz Clock signal distribution on a PC Board.

50 MHz signals produces 20 ns clock cycles
Total system skew budget = 10% of clock cycle * = 2ns
If extrinsic skew = 1 ns

~
~

2 ns
- 1 ns

Device skew (intrinsic skew) must be less than 1 nsf +-

1 ns

·Clock Design Rule of thumb.

CLOCK DUTY CYCLE
• Clock Duty Cycle is a measure of the amount of time a signal is High or Low in a given clock cycle.

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tiT· 100%

FIGURE 1·3. Duty Cycle Calculation
Clock Signal

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CLOCK CYCLE

Example:
tHIGH and tLOw are each 50% of the clock cycle therefore
the clock signal has a Duty Cycle of 50/50%.
TL/F/l0942-55

FIGURE 1-4. Clock Cycle
• Clock skew effects the Duty Cycle of a signal.
Clock

+ Skew
Example: 50 MHz clock distribution on a PC board.
Skew must be guaranteed less than 1 ns at 50 MHz to
achieve 55/45% Duty Cycle requirements of core silicon!

TL/F/l0942-56

FIGURE 1·5. Clock Skew

TABLE 1·1
System
Frequency

Skew

tHIGH

tLOW

50MHz
50MHz
50MHz

o ns
2 ns
1 ns

10 ns
12 ns
11 ns

10 ns
8 ns
9 ns

50/50%
60/40%
55/45%

+-

Ideal Duty Cycle (50/50%) occurs for zero skew.

33 MHz

2ns

17 ns

15 ns

55/45%

+-

Note that at lower frequencies, the skew budget is not as tight
and skew does not effect the Duty Cycle as severely as seen at
higher frequencies.

Duty Cycle

1-4

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Definition of Parameters

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tOSLH, tOSHL (Common Edge Skew)
tOSHL and tOSLH are parameters which describe the delay from one driver to another on the same chip. This specification is the
worst-case number of the delta between the fastest to the slowest path on the same chip. An example of where this parameter
is critical is the case of the cache controller and the CPU, where both units use the same transition of the clock. In order for the
CPU and the controller to be synchronized, tOSLH/HL needs to be minimized.
Definition

Output Skew for Low-to-High Transitions:

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tOSHL, tOSLH (Output Skew for High-to-Low Transitions):

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Propagation delays are measured across the outputs of any
given device.

OUTPUT 2
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TLIF/10942-57

FIGURE 1·6. tOSLH, tOSHL
TABLE 1·11. Guaranteed Specifications. Useful in applications requiring high fanout drivers with synchronous outputs.
Device

tOSHL or tOSLH

Conditions

CGS74B2525
CGS74C2525
CGS74CT2525
CGS74C2526
CGS74CT2526
100115

1 ns
700ps
700 ps
700 ps
700 ps
75 ps

50 pF, 500n, O°C to + 70°C, Vee 4.5V to 5.5V
50 pF, 500n, O°C to + 85°C, Vee 4.5V to 5.5V
50 pF, 500n, O°C to + 85°C, Vee 4.5V to 5.SV
50 pF, 500n, O°C to + 85°C, Vee 4.5V to S.SV
50 pF, 500n, O°C to + 85°C, Vee 4.5V to S.SV
50n, DOC to + 7DoC, VEE -4.2V to -4.8V

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Definition of Parameters (Continued)

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tps (Pin Skew or Transition Skew)

-

tps, describes opposite edge skews, i.e., the difference between the delay of the low-to-high transition and the high-to-Iow
transition on the same pin. This parameter is measured across all the outputs (drivers) on the same chip, the worst (largest
delta) number is the guaranteed specification. Ideally this number needs to be 0 ns. Effectively, 0 ns means that there is no
degradation of the input signal's Duty Cycle.

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Many of today's microprocessors require a minimum of a 45:55 percent Duty Cycle. System clock designers typically achieve
this in one of two ways. The first method is with an expensive crystal oscillator which meets the 45:55 percent Duty Cycle
requirement. An alternative approach is to use a less expensive crystal oscillator and implement a divide by two function. Some
microprocessors have addressed this by internally performing the divide by two.

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Since Duty Cycle is defined as a percentage, the room for error becomes tighter as the system clock frequency increases. For
example in a 25 MHz system clock with a 45:55 percent Duty Cycle requirement, tps cannot exceed a maximum of 4 ns (tPLH of
18 ns and tpLH of 22 ns) and still meet the Duty Cycle requirement. However for a 50 MHz system clock with a 45:55 percent
Duty Cycle requirement, tps cannot exceed a maximum of 2 ns (tpLH of 9 ns and tpHL of 11 ns) and still meet the Duty Cycle
requirement. This analysis assumes a perfect 50:50 percent Duty Cycle input signal.
Definition

Example

tps (Pin Skew or Transition Skew):
clock input
50% duty
cycle

tps = ItpHL -tpLHI
Both high-to-Iow and low-to-high propagation delays are
measured at each output pin across the given device.

output 1

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output 2

tpSl

= tpH~ = tplH1

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0

tpH~

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tplH2

tpHl2
TL/F/l0942-58

FIGURE 1-7. tps
Example: A 33 MHz, 50/50% duty cycle input signal would be degraded by 2.6% due to a tps = 0.8 ns. (See Table and
Illustration below.)
Note: Output symmetry degradation also depends on input duty cycle.

TABLE 1-111. Duty Cycle Degradation of 33 MHz
f
(MHz)
33

Input

Device

Output

DC Input

tiN
ens)

TIN
ens)

tps
(ns)

tOUT
(ns)

TOUT
(ns)

DC
Output

50%/50%
45%/55%

15.15/15.15
13.6/16.6

30.3
30.3

o.s

14.35/15.95
12.1/18.1

30.3
30.3

47.4%/52.6%
39.9%/60.1 %

50%
HIGH

1.5

rzzz.a

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...

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WORST CASE DEGRADATION,
TPS
0.8 nS.

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50%

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LOW LEVEL
(2.6% PULSE WIDTH INCREASE)

LOW LEVEL

TL/F/l0942-60

FIGURE 1-S. Pulse Width Degradation

1-6

% I:::.. DC
Input to Output

2.6%
5.1%

Definition of Parameters (Continued)
tOST (Opposite Edge Skew)
tOST defines the difference between the fastest and the slowest of both transitions within a given chip. Given a specific system
with two components, one being positive-edge triggered and one being negative-edge triggered, tOST helps to calculate the
required delay elements if synchronization of the positive- and negative-clock edges is required.
device
output

pin 1
pin 2

pin 8

................;..............
~tpLH

.•.;....,.....;....;....:....:........;....;

IIIIIlIIIIIIIII tpHL

;....:....:....;....:....:....: ..:.

I
time, ns
TL/F/l0942-64

FIGURE 1-9. tOST
Definition
tOST (Opposite Edge Skew):
tOST = ItPcpm-tPcpnl
where 

u,y- PHL 1,1 ~~ • • • • • • DEVICE 2 : OUTPUT 2 y""'--;--- . : : - tpLH2 -: tP4>x,; = t pLH2 ,2 • •• • :t;: TL/F/10942-67 FIGURE 1-13_ tpv TABLE 1-IV. Guaranteed Specifications Device tpv Conditions CGS74B2525 CGS74C2525 CGS74CT2525 CGS74C2526 CGS74CT2526 100115 1.75 ns 3.5 ps 3.5 ps 3.5 ps 3.5 ps Not Available 50 pF, 5000, O°C to + 70°C, Vee 4.5V to 5.5V 50 pF, 5000, O°C to + 85°C, Vee 4.5V to 5.5V 50 pF, 5000, O°C to + 85°C, Vee 4.5V to 5.5V 50 pF, 5000, O°C to + 85°C, Vee 4.5V to 5.5V 50 pF, 5000, O°C to + 85°C, Vee 4.5V to 5.5V 500, O°C to + 70°C, VEE -4.2V to -4.8V The skew specifications offered on National's CGS products were chosen based on system performance demands. The parameters tOSHL, tOSLH, tOST, tps, and tpv each relate to a specific system requirement which helps designers compensate for pin-to-pin skew, duty cycle degradation, and part-to-part variation. 1-8 Section 2 Performance Data Section 2 Contents Product Performance Specifications .................................................. Characterization Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Skew Performance Studies .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balanced Load Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unbalanced Load Performance ...................................................... Clock Modeling: Transmission Line Characteristics (TLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature vs. Vee Derating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Performance vs. Process Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-5 2-6 2-16 2-18 2-22 2-26 CGS products are available today in FACTTM (CMOS and TIL compatible CMOS, C2525/26, CT2525/26) and FASTTM lSI (B2525), and F1 OOK Series ECl (100115) technologies. Below is a summary of AC/DC and skew specifications for these CGS products. Q) Q) 'B2525 'C2525 'CT2525 100115 4.5-5.5 0°C-70°C 2.0-6.0 0°C-70°C 2.0-6.0 0°C-70°C -5.7, -4.2 0°C-85°C Typ Max Typ Max Typ Max 2.0 0.8 2.4 0.5 48 -64 -1.165 -1.810 -1.025 -1.620 -20.0 -6.0 2.75 2.75 5.49 0.01 3.85 1.65 4.86 0.36 24.0 -24.0 1.5 1.5 5.49 0.01 2.0 0.8 4.86 0.36 24.0 -24.0 Max Typ -1.165 -1.810 -1.025 -1.620 -20.0 -6.0 AC (DYNAMIC) CHARACTERISTICS TABLE 2-11. AC Characteristics of CGS Products tpLH (ns) tpHL (ns) trise (ns) tfall (n5) 'C2525 'B2525 100115 'CT2525 Min Typ Max Min Typ Max Min Typ Max 2.0 2.0 2.9 2.9 4.8 4.8 2.9 2.9 5.0 5.0 8.1 8.1 4.0 4.0 8.5 8.5 10.1 10.1 1.3 0.8 TBD TBD Min Typ 0.83 0.83 0.075 0.075 1.1 1.1 1.1 1.1 Max Refer to datasheets for actual conditions. SKEW PERFORMANCE CHARACTERISTICS TABLE 2-111. Skew Specification of CGS Products Skew Parameter tOSLH (n5) tOSHL (n5) tps (ns) tOST (ns) tpv (ns) n - Refer to datasheets for actual conditions. AC Parameter Q) :l C TABLE 2-1. DC Characteristics of CGS Products VIH(V) VIL(V) VOH(V) VOL (V) IOH(V) IOL(V) o CD DC (STATIC) CHARACTERISTICS Vee Range Oper. Temp. -3 "'tJ CD ... Product Performance Specifications 'C2525 'B2525 100115 'CT2525 Typ Max Min Max Typ Max Typ Max 0.15 0.15 0.6 0.7 1.0 1.0 1.5 1.5 1.75 0.2 0.2 0.7 0.7 0.2 0.2 0.7 0.7 0.075 0.075 0.4 1.0 3.5 0.4 1.0 3.5 0.2 Refer to datasheets for actual conditions. 2-3 - m ,-------------------------------------------------------------------------------------------, m C CI) o c m ...E o 't: CI) c.. Characterization Data Each design has unique characteristics across load and frequency. To help the system designers use National's CGS parts, several derating curves were collected. Data was collected across load and frequency to determine the CMOS and TTL skew performance. This data allows one to compensate for any variations due to loading and frequency on a given product. The setup used for the data collection included a 3-layer board, using separate layers for ground and Vee to reduce any crosstalk and noise. The signal paths on the PC board were all the same length to minimize any propagation delay differences due to trace lengths. Standard TTL and CMOS loads and inputs were used. Data was collected at room temperature (+ 25°C) and 5.0V Vee. Below is a simplified diagram of the test jig schematic. >--.....- .....-OUT IN soon TL/F/l0942-70 FIGURE 2-1. Test Jig Schematic EXAMPLE OF A TYPICAL DERATING CURVE Feature: Pin-to-Pin Output Skew Specification, tOSHL 0.5 0.4 0.3 MElli0.2 0.1 ns - 0.2 ns gj 0.1 0.2 ns - 0.3 ns ffif:i 250 pF 100 kHz !«.;.):~. 0.3 ns - 0.4 ns 50 MHz TL/F/l0942-16 FIGURE 2-2. Max tOSHL (ns) For example, for the CGS74C2525 1 to 8 Clock driver, tOSHL skew performance is observed over frequency (100 kHz to 50 MHz) and capacitive loading (0 pF to 250 pF): Output Skew: Contour Curve Reading: at 50 MHz and 30 pF ...... tOSHL is 0.1 ns to 0.2 ns (100 ps to 200 ps) 2-4 "tJ (1) ..... Skew Performance Studies The performance studies to be described are designed to help system designers use National's CGS devices by providing derating curves observing skew across load and frequency. Data was collected across load and frequency to determine the CMOS and TTL skew performance. This data allows one to compensate for any variations due to loading and frequency on a given CGS product. o 3OJ :::s (") (1) C OJ Study # 1: Skew performance for balanced (matched) loads from a pF to 250 pF over 100 kHz to 50 MHz. S" Other conditions: room temperature and 500n resistance loads. This study is intended to observe skew variation with matched capacitive loading across all outputs of the clock driver during multiple output switching at high frequencies. To ensure the integrity of the bench performance study, the data was taken over various sample lots to account for process variations. The data collected is the worst case (maximum skew) performance measured for each of the various skew specifications over balanced loads. '2525 '2525 TLlF/l0942-73 TL/F/l0942-72 FIGURE 2-3. Balanced Load 0 pF FIGURE 2-4. Balanced Load 250 pF Refer to the Balanced Load Performance graphs. Study #2: Skew performance for unbalanced (unmatched) loads from a pF to 50 pF over 100 kHz to 50 MHz. Other conditions: room temperature and 500n resistive loads. This study is indended to observe skew variation with unmatched capacitive loading across all outputs of the clock driver during multiple output switching at high frequencies. To ensure the integrity of the bench performance study, the data was taken over various sample lots to account for process variations. This data is useful to compensate for applications where achieving matched loads is not possible. The data collected is the worst case (maximum skew) performance measured for each of the various skew specifications over unbalanced loads. 12 11 '2525 10 TL/F/10942-74 FIGURE 2-5. Unbalanced Load 0 pF to 50 pF Refer to the Unbalanced Load Performance graphs. Study # 3: Skew performance for Distributive Loads (Transmission Lines) This study is intended to provide device information required to perform transmission line simulation of the CGS drivers. Many simulation tools are available today and each has a unique set of information required to perform simulation. In order to create a model for the driver one must know how the driver behaves as its medium changes. That is how parameters such as trise, tfall along with the output impedance change when board parameters such as length and/or the line's impedance change. 14 13 01 03 Zo = son = SOil Zo CKIN Vee GND 05 ~ ____________~Z~O_=~7~sn~____________________~NT 0., TL/F/10942-75 FIGURE 2-6. Distributive Loads Refer to the Transmission Line graphs. 2-5 gC'tJ Balanced Load Performance Q) u c:::: C'tJ E a- o a- Q) a.. D o ns 1 1 ns 4 t:::::::;t 2 R 2 ns - 3 ns U~1j11111j1j11J 3 ns - 4 ns 100 kHz 250 pF 100 pF II • 4 ns - 5 ns opF 5 ns - 6 ns 50 MHz TL/F/10942-1 FIGURE 2-7. CGS74B2525 Max trise (n5) II ons - 1 ns R 1 ns - 2 ns r;o;o;o;o;o;o;l ~:;:;:;:~:~:~:;: 2 ns - 3 ns 100 kHz o 250 pF 100 pF II 3 ns - 4 ns 50 MHz TL/F/10942-2 FIGURE 2-8. CGS74B2525 Max tfall (n5) 2-6 "'C CD Balanced Load Performance (Continued) =l. o 3 D) ::l (") CD C D) D) D ons - 1 ns [ill] 1 ns - 2 ns g 100 kHz 2 ns - 3 ns )~:l~~ll:t • 250 pF "ns - 5 ns TL/F/10942-7 FIGURE 2-9. CGS74CT2525 Max trise (n5) [£ill [ill] o ns - 1 ns 1 ns - 2 ns g 2 ns - 3 ns Ijlj~jljlj~j~ilil • 250 PF 3 ns - 4 ns 4 ns - 5 ns 50 MHz TL/F/10942-8 FIGURE 2-10. CGS74CT2525 Max tfall (n5) I Ell 2-7 cu ~ Balanced Load Performance (Continued) G) (.) C CU ... E o ... G) c.. • •• • o ns - 1 ns II R 1 ns - 2 ns 2 ns - 3 ns 100 kHz 250 pf 3 ns - 4 ns 4 ns - 5 ns 5 ns - 6 ns • • • ons - 50 MHz TL/F/10942-13 FIGURE 2-11. CGS74C2525 Max trise (n5) 1 ns II 1 ns - 2 ns R 100 kHz 2 ns - 3 ns 3 ns - 4 ns II 4 ns - 5 ns 5 ns - 6 ns TL/F/10942-14 FIGURE 2-12. CGS74C2525 Max t1all (n5) 2-8 "'tJ Balanced Load Performance (I) .... o .... (Continued) 3Q) ~ (') (I) C Q) S" • •• On5-0.32n5 mE] 0.32 n5 - 0.64 n5 0.64 ns - 0.96 n5 1.6 1.28 0.96 0.64 0.32 250 pF 0.96 ns - 1.28 n5 50 MHz TL/F/10942-3 FIGURE 2-13. CGS7482525 Max tOSLH (ns) • •• • On5-0.4n5 mE] 0.4 n5 - O.B ns 0.8 n5- 1.2 ns 2.0 1.6 1.2 O.B 0.4 250 pF 100 kHz 1.2 ns- 1.6 ns 1.6 ns- 2.0 ns 50 MHz TLlF/10942-4 FIGURE 2-14. CGS7482525 Max tOSHL (ns) 2-9 m ~ Balanced. Load Performance (Continued) Q) (,) C m E o ~ ~ Q) D.. 1.5 Will 1.2 • ons - 0.3 ns 0.9 0.6 0.3 ns - 0.6 ns 0.3 II 0.6 ns - 0.9 ns 100 kHz 250 pF 0.9 ns - 1.2 ns 50 t.lHz TLlF/10942-9 FIGURE 2-15. CGS74CT2525 Max tOSLH (ns) [I] • ons - 0.3 ns 1.5 1.2 0.9 0.3 ns - 0.6 ns 0.6 II 0.3 100 kHz 0.6 ns - 0.9 ns I~l~l~~lllil 250 pF 0.9 ns - 1.2 ns • 100pF 1.2 ns - 1.5 ns 50 t.lHz TL/F/10942-10 FIGURE 2-16. CGS74CT2525 Max tOSHL (ns) 2-10 "'C -3 .... (1) Balanced Load Performance (Continued) o Q) :::l (') (1) C Q) S" 0.5 [£J 0.4 Ons-O.l ns 0.3 [£J 0.1 ns - 0.2 ns 1m 0.2 ns - 0.3 ns ~ 0.2 0.1 o 250 pF' 0.3 ns - 0.4 ns 50 MHz TLlF/10942-15 FIGURE 2-17. CGS74C2525 Max tOSLH (n5) 0.5 0.4 Will] 0.1 ns - 0.2 ns 1m 0.3 0.2 0.1 0.2 ns - 0.3 ns ~ 250 pF' 100 kHz 0.3 ns - 0.4 ns 50 MHz TL/F/10942-16 FIGURE 2-18. CGS74C2525 Max tOSHL (n5) 2-11 co co C Balanced Load Performance (Continued) Q) (.) c co E I- o I- Q) D.. 4.0 L2B • • 3.4 1.0ns-1.6ns 2.8 2.2 1.6 ns - 2.2 ns 1m mil 2.2 ns - 2.8 ns 1.6 250 pF 2.8 ns - 3.4 ns 3.4 ns - 4.0 ns 50 MHz TLlF/10942-5 FIGURE 2-19. CGS74B2525 Max tOST (ns) L2B • • 1.0ns-1.6ns 1.6 ns - 2.2 ns 1m mil 4.0 3.2 2.4 2.2 100 kHz 1.6 2.2 ns - 2.4 ns 2.4 ns - 3.2 ns 1.0 250 pF 3.2 ns - 4.0 ns TLlF/10942-6 FIGURE 2-20. CGS74B2525 Max tps (ns) 2-12 -3 "'tJ ... (!) Balanced Load Performance (Continued) o Q) ::::J (') (!) C Q) 6) 6.0 5.2 4.4 EBJ • •• 2.0 ns - 2.8 ns 2.8 ns - 3.6 ns WI 3.6 2.8 2.0 250 pF 3.6 ns - 4.4 ns 4.4 ns - 5.2 ns 5.2 ns - 6.0 ns 50 MHz TLlF/10942-11 FIGURE 2-21. CGS74CT2525 Max tOST (ns) EBJ • •• 1 ns - 2 ns 100 kHz 2 ns - 3 ns WI 3 ns - 4 ns 4 ns - 5 ns • I 5 ns - 6 ns TL/F/10942-12 FIGURE 2-22. CGS74CT2525 Max tps (ns) 2-13 - ,-------------------------------------------------------------------------------------------, ~ ~ Balanced Load Performance (Continued) (1) CJ C ~ E .... o .... (1) c.. 1.0 Will o •• • ns - 0.2 ns 0.2 ns - 0.4 ns 0.8 0.6 0.4 0.2 100 kHz 0.4 ns - 0.6 ns Ii] 250 pF 0.6 ns - 0.8 ns 0.8 ns - 1.0 ns 50 MHz TL/F/l0942-17 FIGURE 2·23. CGS74C2525 Max tOST (ns) 1.0 Will •• • ons - 0.2 ns 0.2 ns - 0.4 ns 0.8 0.6 0.4 0.2 100 kHz 0.4 ns - 0.6 ns Ii] 250 pF 0.6 ns - 0.8 ns 0.8 ns - 1.0 ns 50 MHz TLlF/l0942-18 FIGURE 2·24. CGS74C2525 Max tps (ns) 2-14 "'tJ Balanced Load Performance ... CD (Continued) o 3 D) :::J (") CD C D) ii) 3.50 [£lJ 2.80 Ons-0.70n. 2.10 •• •• 1.40 0.70 ns - 1.40 ns 100 kHz 0.70 1.40 n. - 2.10 ns 2.10ns-2.80n. 2.80 ns - 3.50 ns 50 101Hz TL/F/l0942-19 FIGURE 2-25. CGS74B2525 Max tpv (n5) t±J •• m • 2 ns- 3 n. 3 ns- 4ns 4 ns - 5 ns 5 ns- 6 ns 6 ns - 7 ns TL/F/l0942-20 FIGURE 2-26. CGS74CT2525 Max tpv (n5) L±ll o •• • ns - 0.3 ns 0.3 ns - 0.6 ns 0.6 ns - 0.9 ns 1.5 1.2 0.9 0.6 0.3 250 pF 0.9 ns - 1.2 ns 50 IotHz TLlF/l0942-21 FIGURE 2-27. CGS74C2525 Max tpv (n5) 2-15 • I co co C Unbalanced Load Performance CD In many instances, no matter how much one tries to balance the loads across the outputs of the driver, there will be a slight imbalance. This imbalance will impact output rise/fall and propagation delay times which, in turn, impacts skew across the outputs. The graphs below show worst-case skew, given unbalanced loads of 0 pF to 50 pF across all eight outputs. This data was collected by placing the least amount of load on the fastest output (0 pF) and the heaviest load on the slowest output (50 pF). Data was collected at 5.0V supply voltage and at room temperature (+ 25°C). (.) C CO ...E -... o CD c.. Feature: Skew Performance Data over unbalanced (unmatched) loads. Example: Unbalanced Load Performance o pF to 50 pF unmatched loads placed on driver outputs, 5V, room temp, 3 process lots. 14 13 Note: The following example is for illustration only. It is not the actual load· ing configuration for worst case conditions. GND 12 '2525 11 10 TLlF/10942-82 FIGURE 2-28. Unbalanced Loads Unbalanced Skew 2.5 2.0 1.5 cg 1.0 0.5 0.0 0.1 10 20 30 40 50 MHz - . - MAX TOSLH -0- MAX TOSHL -¢- -+- MAX TRISE MAX TF ALL TL/F/10942-76 Unbalanced Skew 2.5 cg 1.5 0.5 10 0.1 20 30 40 50 MHz - . - MAX TPS -0- MAX TOST -+- TPV FIGURE 2-29. '82525 Unbalanced Load Skew Performance 2-16 TL/F/10942-77 "tJ Unbalanced Load Performance (1) ..... o ..... 3 Q) (Continued) Unbalanced Skew :l 1.5 (") (1) C Q) S" III " 0.5 0.1 10 20 30 40 50 MHz -+- MAX TOSLH -¢- MAX TOSHL -0- MAX HALL -.- MAX TRISE TL/F/l0942-78 Unbalanced Skew 4.5 -------. 3.5 VI 2.5 c::: 1.5 0.5 0.1 10 20 30 40 50 MHz -+- TPS -0- TOST -.- TPV TL/F/l0942-79 FIGURE 2-30. 'CT2525 Unbalanced Load Skew Performance Unbalanced Skew 1.5 1.0 VI c::: 0.5 0.0 0.1 10 20 30 40 50 I II MHz TOSLH -0- TOSHL -¢- TFALL -+- TRISE FIGURE 2-31. 'C2525 Unbalanced Load Skew Performance 2-17 TL/F/l0942-80 C'tI C'tI C Unbalanced Load Performance (Continued) cu c C'tI E (J Unbalanced Skew 2.0 ... ... cu o 1.5 c.. Vl c: 1.0 -.--.--.#:~.--+-.~: ---.'?' .-__.-__ 0.5 0.1 10 20 30 40 50 MHz - - TOST -0- TPS -+- TPV TLIF/10942-Bl FIGURE 2-31. 'C2525 Unbalanced Load Skew Performance (Continued) Clock Modeling: Transmission Line Characteristics (TLC) As the speed of the clock signals increase, system designers must account for transmission lines effects. As a general rule of thumb, if the rise or fall time of any signal is more than twice the propagation delay of the signal's path, the path (trace) behaves as a transmission line. Clocks today operate in the 50 MHz region with the rise and fall time approaching sub-nanosecond transition performance. Also the length of traces are not getting any shorter and the need to distribute the clock to many components at different locations has actually increased. This results in the need to evaluate and simulate the board for transmission line and cross-talk effects caused in high frequency. Many simulation tools are available today and each has a unique set of information required to perform simulation. Given a set of conditions and characteristics, most of these tools simulate the effects of transmission lines and crosstalk on any path. They usually require information such as the driver's and receiver'S input and output characteristics along with information from PC board manufactures regarding the board's layout and impedance characteristics. In order to create a model for the driver one must know how the driver behaves as its medium changes. That is how parameters such as trise, tfall along with the output impedance change when board parameters such as length and/or the line's impedance change. For this reason many simulators such as QUAD DESIGN's XNS/TLC require models of the drivers and receivers. These models can be obtained either from the manufacturers or can be measured. trise and tfall times can be measured from plots of the output driving purely resistive loads. I-V plots (Le., plots of VOH/IOH and VOL/iod can be extrapolated from the load lines and the effective impedance of the output. The output's pin capacitance is also needed since it adds to the total load. Below are the I-V plots for CGS74B2525, CGS74C2525 and CGS74CT2525 (Figures 2-32,2-33, 2-34). They reflect a typical output's (pin 14, Q8) performance. The load lines can be obtained by calculating the slopes of VOH and VOL. trise and tfall graphs (Figures 2-35, 2-36, 2-37) will provide the signal transition times needed for analysis of the transmission line. VI VI ( v) ( v) 5.600 c - - - - - , - - - - - - - - - - , 5.600 . . . . . - - - - - , - - - - - - - , > > l5 l5 I I .,; .,; -1.-400 -1.400 -100.0 -100.0 100.0 11 100.0 11 20.00/DIV (rnA) TLIF/10942-B7 20.00/DIV (rnA) TLIF/10942-BB FIGURE 2-32. I-V Plots for CGS7482525 2-18 -3 "tJ Clock Modeling: Transmission Line Characteristics (TLC) (1) .... (Continued) o D) ::l VI ( v) VI 5.600 5.600 (") (1) ( v) / C ~----r------" D) D) l - > c ....... g ~ o I / -1.400 -1.400 -200.0 0 11 -200.0 200.0 40.00jDIV (rnA) 0 11 200.0 40.00jDIV (rnA) TL/F/l0942-89 TL/F/l0942-90 FIGURE 2-33. I-V Plots for CGS74C2525 VI ( v) VI 5.600 5.600 , - - - - - - . , . . . . . - - - - - , ( V) / l - > c g o .... o I -1.400 -1.400 -200.0 -200.0 200.0 11 0 11 40.00jDIV (rnA) TLlF/l0942-91 200.0 40.00jDIV (rnA) TL/F/l0942-92 FIGURE 2-34. I-V Plots for CGS74C2525 2-19 C'tI ~ Clock Modeling: Transmission Line Characteristics (TLC) (Continued) (1) (.) r::: 400mY C'tI .,,- r--- E a... o - I (1) a.. ........-. r--- / 1/ a... > Ci ~ E o I/') / J / -100 mY 1 nS/OIY TL/F/10942-93 400mY '""""'\ \. > Ci \ ~ E o I/') " \.. -100 mY " ~ -' .--- 1 nS/OIY TL/F/10942-94 FIGURE 2-35. trise and tfall Plots for CGS7482525 750 mY /' / > ........ Ci ~ > E ) g - / -250 mY 1 nS/OIY TL/F110942-95 750 mY > Ci ........ > E , \. '\ o o ~ " ~ """"""- r-- -250 mY 1 nS/OIY FIGURE 2-36. trise and tfall Plots for CGS74CT2525 2-20 TL/F/10942-96 -3 "'tJ .... (t) Clock Modeling: Transmission Line Characteristics (TLC) (Continued) o Q) 750mV :::l o(t) V > i5 ........ / > E - r-.... C Q) / Q) ) o o / -250 mV 1 nS/OIV TLlF/l0942-98 750 mV > i5 ........ > E o o , \. '\ ""- - ~ """""- ~ -250 mV 1 nS/OIV TL/F/l0942-97 FIGURE 2-37. trise and tfall Plots for CGS74C2525 , fI 2-21 ctI ctI C Q) (,) c ctI ...E o ... - Temperature vs Vee Derating Curves The following graphs show the performance of the 82525 across Vee and temperature. The data was collected for 50 pF, 500n loads. tOSLH (n5) 0.5ns Q) 0.. 0.3ns ... .- tOSHL (n5) ...... _ ---- ---- -- 0.5ns ......... .....-::_- ~.-=--. -..: .. I-.--~ =-.---': ~ O.4ns .-.-'" ~--- O.4ns - --' _. 0.3ns 0.2ns 0.2ns 0.1 ns 0.1 ns ,tI" .... 1--- ... "'--""t .. ... ........ Ons -40°C 85°C 85°C TL/F/l0942-23 TLlF/10942-22 tps (n5) 1.2ns loOns 0.8ns 0.6ns O.4ns 0.2ns Ons tOST (n5) 1.20ns .... -..-.--- ----_. .:- - .."..' , .... -- -' ... .--~ .... :;:;....."" - -- --- - -- 1.00ns --- 0.80ns .-- 0.60ns 0.40ns 0.20ns ' "___... I-- '" ~ .... - ..... ....... -.IJ .", -'"' .",.,.-", -~ ...--...::;;i ~ ~ ~ Ons -40°C -40°C 85°C 85°C TL/F/l0942-25 TLlF/l0942-24 tpv (n5) 1.2ns loOns 0.8ns 0.6ns O.4ns • - - . 4.5 Vcr. Max - • - 4.5 Vcr. Mean -- .--. _. ----- --...-- -':. ...... ----.... .. --. .-.-~ -:;",~ -~ ~ --- 0.2ns Ons - - - 5.5 Vcr. Max -5.5Vcr.Mean -40°C TL/F/l0942-27 85°C TLlF/l0942-26 FIGURE 2-38. CGS7482525 Performance Data 2-22 ." Temperature vs Vee Derating Curves (Continued) The following graphs show the performance of the C2525 across Vee and temperature. The data was collected for 50 pF, 5000. loads. CD .... o .... 3 Q) ::s (') 0.25ns 0.25ns 0.20ns ~--- ----_ . --- ---__ ".-..: :.-: --. 0.15ns --- -.--------y----~---__r---_, 0.20ns ~- 0.15 ns -+-..... -- --- --- ....----_- _____ " "-=-=...:~----+_--=-----~ ~- __,_ ..._=-c.:::! -- I"'"- Ons Ons~----4----+_---~---~ -55°C -55°C 125°C 125°C TL/F/10942-30 TL/F/10942-31 tps (n5) tOST (n5) 0.8ns 0.6ns 0.8ns --.------ -_I1-_-- O.4ns ~ ~"''''- 1 ._---- -----_I . -. -----..1--:"-';-:.,-,: -- - 0.6ns ... .- ....---.: -:.,-,: ~. O.4ns 0.2ns 0.2ns -r-- --Ons -- Ons -55°C 125°C -55°C 125°C TL/F/10942-32 TLlF/10942-33 tpv (n5) 1,50ns -,----,.-----r-----.------, 1,OOns ~----4----+_---~---~ ----- ----_. ----_ . _........... -...... - . _---- 0.50ns - t - - - - - + - - - - - + - - - - - + - - - - - - - t ---- - - - - 4.5 Vo;; Max - - - 4.5 Vo;; Mean • • • 5.5 Vo;; Max -5.5Vo;;Mean -- Ons~----4----+_---~---~ -55°C TL/F/10942-27 125°C TLlF/10942-34 FIGURE 2-39. CGS74C2525 Performance Data 2-23 C Q) S" 0.10ns - t - - - - - + - - - - - + - - - - - + - - - - - - - t 0.10ns 0.05ns CD tOSHL (n5) tOSLH (n5) m m C Q) (.) c m E .... o .Q)... a. Vee Temperature vs Derating Curves (Continued) The following graphs show the performance of the CT2525 across Vee and temperature. The data was collected for 50 pF, soon loads. tOSLH (n5) tOSHL (n5) 0.25ns 0.20ns 0.15ns 0.30ns .. -. _. .---roo----- 1--~----- ----':-~~ .. --_. ~ 0.25ns !!"_- - _ •...... -.. ----~~ !.--_. -.. _-. 0.20ns -- --- - 0.15ns 0.10ns 0.10ns --- -- 0.05ns 0.05ns --~ Ons -- - - -----. Ons -55°C -40°C 25°C 85°C -55°C 125°C -40°C 25°C 85°C TL/F/10942-35 tps (n5) loOns 0.8ns _... , 0.6ns _ OAns 0.2ns ..•.. ._. _..- tOST (n5) __ I - ...... LOOns .... - 0.80ns - .--- -_ ..- 0.20ns ./ "- Y-~ ;~ ~~~ ...e.::':;'~ 0.40ns Ons -55°C ",. 0.60ns --- ----- ----- ----- 125°C TL/F/10942-36 ~- -- --- ----- ----- Ons -40°C 25°C 85°C -55°C 125°C -40°C 25°C 85°C 125°C TL/F/10942-3S TL/F/10942-37 tpv (n5) 2.50ns 2.00ns ---- ..-----~... --- -------It. 1.50ns -.. 1.00ns - - - - 4.5 Vee Max - - - 4.5 Vee Mean • - • 5.5 Vee Max - _ .. ... .---- -_. ~ 0.50ns Ons 5.5 Vee Mean -55°C TL/F/10942-27 -40°C 25°C 85°C 125°C TLlF/10942-39 FIGURE 2-40. CGS74CT2525 Performance Data 2-24 ""0 -3 .... (1) Temperature vs Vee Derating Curves (Continued) The following graphs show the performance of the 82525 and C2525 across Vee and temperature. The data was collected for 50 pF, 500n loads. o D) :l tfall (n5) 1.4ns 1.12ns 0.84ns - ...... - .. -1-..... ...... -- - -. ~ 0.56 ns trise (n5) 1.4ns - r - - - - - - , . - - - - . , . . . - - - - " " T " " - - - - - - , ----_. ----.. -1-.-."- ---.10_--- 1.12ns .. - ~- ---- 0.84 ns ......... - ... ~. ~ - ... - .. -~. - . -1-.-":'-..-:":'-.-":'-.-- - - - ... - - - • 0.56ns -+------+-----+-----+-----j 0.28ns + - - - - - + - - - - + - - - - _ + _ - - - - j 0.28 ns Ons~---_4----+_---_+_---_4 Ons -40°C -40°C 85°C 85°C TLlF/l0942-29 TL/F/l0942-28 FIGURE 2-41. CGS7482525 trise and tfall tfall (n5) 3.00ns - - . - - - - - - - - - . , . . . - - - - - - - - - - , 3.50ns -r---------.,...----------, 2.80ns -t----------+-------_=__~ 3.20ns -+---------+-----.,.-.,.~""---__I 2.60ns -+---------+-:=-0iiiI:'_----~""-"=~ 2.90ns +-------_--:=-oIo..L------=~...,,==i 2.40 ns -t------,.,..,....'-""--+--::-<''''''=o..--=''----__I 2.60 ns -+---==--'""-"--------:::::......"""'-=---==-...-""-------; 2.20 ns -\.-.......,::+-'-::::"'IO'!!:SlllitJllll'!'.=----+---------j 2.30ns -!:i.......- . , = - - - - - + - - - - - - - - - j 2.00ns + - - - - - - - - + - - - - - - - - _ 4 2.00ns -55°C trise (n5) .,.'" .,.'" -- ~--------+---------j -55°C 125°C -.,. TL/F/l0942-45 125°C TL/F/l0942-46 • - - .. 4.5 - .. - 4.5 • - • 5.5 5.5 Vcr; Vcr; Vcr; Vcr; Max Mean Max Mean TL/F/l0942-27 FIGURE 2-42. CGS74C2525 trise and tfall 2-25 (') (1) C D) 6) ca ca C Q) (.) c ca ...oE ... Q) D. Power Performance vs Process Technology For synchronous systems to operate, the clock must always be functioning. In the higher performance systems for which National's CGS products are targeted, the system clock is typically operating at very high frequencies, driving large loads, and is rarely if ever turned off (TRI-STATEO). Historically the process technology of choice to meet the low power constraints would be CMOS due to its low quiescent power consumption. However, as the frequency of the clock increases, the benefits of CMOS low quiescent power consumption disappear and dynamic Icc becomes a key concern. This is due to the fact that the P-channel and N-channel transistors do not have time to completely turn off (discharge) which results in a low resistive path from Vcc to ground. The graph below presents empirical data comparing CMOS, Bipolar, and ECl power consumption for the CGS devices with no load. Given a standard load, the cross-over frequency of TTL and CMOS moves to the right somewhat (increases to about 25 MHz). This is because, for the Bipolar device Icc increases more across frequency than for the CMOS device. As the internal impedance of the Bipolar device is more than CMOS, external loads added in parallel will reduce the total load (impedance). This affects Bipolar more than CMOS. This holds true until the load impedance becomes more than the internal impedance of the Bipolar device. 300 250 <~ -.- '82525 200 .,c: -0- 'C2525 :::J 150 '" 100 u ~ -+- 'CT2525 -¢- '100115 VI 50 0 1104Hz 10 104Hz 20 104Hz 30 104Hz 40 104Hz 50 104Hz 60 104Hz 70 104Hz 80 104Hz TLlF/l0942-83 FIGURE 2-43. Dynamic Power Comparison Note: This graph reflects dynamic conditions only, no loading. The power supply (Vee> for the '2525 devices is +5.0V; and for the 100115, VEE = -4.8V. The 100115 device, as with all Eel devices, demonstrates constant current over frequency. All these clocked devices' power supply current will increase proportionately as their outputs are connected to a load. . In conjunction with the dynamic Icc, the output loading will affect the fMAX (Maximum operating frequency). The graphs below show how maximum operating frequency of the device is limited by system airflow. These charts provide the recommended airflow to maintain + 150°C junction temperature. The maximum power consumed by the chip is calculated given the output load and frequency. Balanced loads are assumed across all outputs. 'CT2525 '82525 14-Pin PDIP 5.5V, +25 0 C 180 ~~~ 160 ~ 140 ... ::I: .3 )( ..!:'" .......... 90 80 ~~~ ......~ 100 ............. 80 100 . ..... 120 ~~ ~'r ~ 60 40 14-Pin PDIP 5.5V, +25 0 C --. Jrr.... ..................... .......:......... .... '-............-. 70 ... h. ___ ... ::I: 60 .3 50 .......... )( ..!:'" ""[ 30 20 20 .----- 40 -I - . .... ~ ~ .... ..........[J.. -.............. ........ .......... ------.....: 10 o o 25 50 25 100 50 100 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) TL/F/l0942-85 TL/F/l0942-84 • 500 IF"M 0 225 LF"M • a IF"M TL/F/l0942-86 FIGURE 2-44. Airflow vs Frequency a) '82525, b) 'CT2525 2-26 Section 3 Selection Criteria and Datasheets Section 3 Contents Selecting the Correct CGS Product for your High Speed Application. . . . . . . . . . . . . . . . . . . . . . . CGS Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection Criteria for CGS Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGS74B303/304/305 Octal Divide-by-2 Circuits/Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . CGS74B2525 1-to-8 Minimum Skew Clock Driver (Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGS74C2525/2526 1-to-8 Minimum Skew Clock Driver (CMOS)...... .......... ....... .. . CGS74CT2525/2526 1-to-8 Minimum Skew· Clock Driver (CMOS TTL Compatible) . . . . . . . . . . 100115 Low Skew Quad Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100310 Low Skew 2:8 Differential Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 100311 Low Skew 1:9 Differential Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100315 Low Skew Quad Differential Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-3 3-7 3-8 3-9 3-10 3-14 3-14 3-20 3-24 3-25 3-30 en CD Clock Generation and Support (CGSTM) CD (") O· ::l o... APPLICATIONS Selecting the Correct Clock-Generation-and-Support (CGSTM) Product for your High Speed Application INTRODUCTION ;:;: Clock generation and support is a key design area that enables today's CISC- and RISC-based systems to optimize maximum operating frequencies. The primary goal of the system clock is to deliver a clock signal to each component's input pins while meeting the system's requirements for skew, acceptable wave shape (rise and fall time, overshoot, undershoot, voltage swings), stability (cycle to cycle), and avoiding setup and hold time violations. The components of clock skew include intrinsic skew (pin to pin skew within a single chip) and extrinsic skew (clock skew generated from trace routing and loading). ... iii' CD This section presents input clock requirements for some of today's popular processors and defines each requirement. A typical memory caching scheme is presented and analyzed for the need of a minimum skew clock driver. A decision tree presents a guide for selecting from National Semiconductor's CGS products that are available on different process technologies. SUMMARY OF INPUT CLOCK REQUIREMENTS Each microprocessor has unique input clock requirements. These requirements are based on factors such as operating frequency (MHz) and the structure of the input clock (i.e., CMOS or Bipolar). This is true for the CPU, FPU, and/or any peripherals (controllers). Almost every device which requires a clock for its operation has common parameters shown in Table 3-1, which presents a summary of popular microprocessor's input clock requirements. Among these parameters the most common ones are trise, tfall, and the duration of the high and low pulses, namely pulse width high and low. trise and tfall parameters require that the driver make a transition from low to high state (trise) and vice versa (tfall) during a set amount of time. The actual specification has voltages as reference points such as 0.8V to 2.0V for bipolar and typically 20% to 80% of the Vee for CMOS devices. The trend in the microprocessor trise and tfall is toward faster edge rates, driven by the shorter period of the higher-frequency CPU's. The downside is that faster edge rates cause unwanted noise such as overshoot and undershoot which may cause glitches that can change the internal thresholds and cause erroneous triggering. TABLE 3-1. Input Clock Requirements of Some Popular Microprocessors Processor Intel 386DX Intel 387DX Intel i486 Mot 68040 NSC32532 AMD29000 lSI 64901 Intel i860 Intel1960ca Mot 88100 MIPR3001 InputCLK Frequency ClK2 ClK2 ClK PClK ClK ClK ClK ClK ClK ClK ClK2 (xsyS) *66 MHz *66 MHz 50 MHz *50 MHz *66 MHz *50 MHz 25MHz 50 MHz 40MHz 25MHz *66 MHz trise High Width tfall Low Width ns Max Volts a,b ns Max Volts c,d ns Min Volts b,c ns Min Volts a,d Swing Fig. 4.0 4.0 2.0 1.7 3.0 5.0 3.0 6.0 6.0 4.0 5.0 3.7,0.8 3.7,0.8 2.0,0.8 2.0,0.8 2.0,0.8 2.0,0.8 2.0,0.8 3.0,0.8 2.0,0.8 4.0,1.0 2.0,0.8 4.0 4.0 2.0 1.7 3.0 5.0 3.0 6.0 6.0 4.0 5.0 0.8,3.7 0.8,3.7 0.8,2.0 0.8,2.0 0.8,2.0 0.8,2.0 0.8,2.0 0.8,3.0 0.8,2.0 1.0,4.0 0.8,2.0 4.5 4.5 7.0 10.5 4.3 10.5 15.0 3.0 5.0 19.0 6.0 3.7,3.7 3.7,3.7 2.0,2.0 1.5,1.5 2.0,2.0 1.5,1.5 1.5,1.5 3.0,3.0 2.0,2.0 0.8,0.8 Vee 1.5,1.5 4.5 4.5 7.0 10.5 4.3 10.5 15.0 5.0 5.0 19.0 6.0 0.8,0.8 0.8,0.8 0.8,0.8 1.5,1.5 0.8,0.8 1.5,1.5 1.5,1.5 0.8,0.8 0.8,0.8 0.2,0.2 Vee 1.5,1.5 CMOS CMOS TTL TTL TTL TTL TTL CMOS TTL CMOS TTL 1 1 1 2 1 2 2 1 1 1 2 "Divide by two is done internally. EI 3-3 m 0': Q) 0': o CGS (Continued) t(period) = trise + tfall + High Width + Low Width C o ;:; (.) Q) Cii en HIGH 4 \ LOW ~- ~-~:~~-~ !-~:~~--V-- a- ---- - \-ise - I\d"---J- r-- ~all TLIF/10942-99 FIGURE 3·10 Input Clock Period The high and low pulse durations are required specifications of the input clocks. These parameters guarantee that there is enough time for the processor to recognize the transition. This may also be looked at as a hold-time equivalent of the input clock for any internal transitions. Again these parameters are specified at reference voltages and vary from processor to processor. The combination of trise and tlall along with pulse width high and low determine the operating frequency of the system. If the trise and tlall are equal and all of the reference points are the same (see Figure 3-1), frequency is the reciprocal of the clock period, and the clock period can be determined from the addition of the low and high pulse widths along with trise and tlall transitions. As the speed of the microprocessors increases, the input clock specifications become more stringent (see Table 3-1). As an example trise and tlall are required to be under 2 ns for Motorola's 68040 microprocessor running at 50 MHz. Pulse width durations are also required to be shorter since the total clock period is reduced. These requirements affect systems that are synchronized using various distribution methods. The rise and fall times along with the skew of the outputs become critical design considerations. The Minimum Skew Clock Design Problem Example: i386TM-33 MHz caching restriction. A typical cache scheme using an Intel's 386 microprocessor is shown in Figure 3-2. This example, described below, illustrates the need for a minimum skew clock driver providing the clock input to the CPU and the cache controller. The cache controller used is Intel's 80395TM. In Figure 3-2 the CPU's address bus is connected directly to the Tag memory (Tag RAM) which is an SRAM. Depending on the scheme used, all or some of the address bits (AOO thru A31) may be connected from the CPU to the cache tag (direct mapped system or associative set mapping). The function of the tag RAM is to indicate to the controller by means of its MATCH output signal whether the address requested by the processor exists within the cache RAM. Also connected from CPU directly to the cache memory is the data bus. Again all or some bits could be directly connected depending on the size of the data bus. The cache controller requires many inputs from the CPU as its control signals, among which are the W/R# and ADS#. The W/R# is a read/write signal generated by the CPU indicating if the current cycle is a read or a write operation. The ADS# status signal also generated from the CPU and it indicates if the address bus is valid or not. The cache controller also provides control signals of its own, some of which are inputs to the CPU and some are for controlling the status of the SRAMs. The Ready# signal supplied to the CPU indicates whether or not the contents of the SRAMs have been accessed (case of hit). WE # and OE are outputs from the controller to the memory arrays. WE # indicates if the current cycle is a read or write cycle, OE enables or disables the output of the cache RAM. Finally provided to both units are the CLK2 signals which are twice the operating frequency of the system (66 MHz), hence each unit performs the divide-by-two function internally to obtain the required duty cycle. Both of these clocks are supplied from an oscillator and are distributed by a driver. The function typically used as the driver was the '244 or '1004 with all inputs hard wired together. National's CGS products replace the '244, '1004 function, provide the benefits of tighter skew, and also minimize impedance mismatches in the '244, '1004 implementation due to the multiple inputs being tied together. 3-4 en CGS CD (i) -o· (Continued) (') LOCAL BUS SRAM ::::J o.... ;::;: CD .... LOCAL ADDRESS .... r CPU .... DATA .Ii ..... CACHE RAM iii" r LOCAL ADDRESS .... ..... ..... TAG RAM r MATCH CLK2 t!i CONTROL OE WE# READY W/R# OSC IN -. CLOCK DRIVER - ADS# CACHE CONTROLLER CLK2 TL/F/10942-A1 FIGURE 3-2. Cache Module for Intel's 386DXTM Figure 3-3 is the timing cycle for the Figure 3-2 cache controller. This timing diagram shows a cache memory hit cycle. During this cycle the CPU issues the read command by activating a low on W/R# status line. When this line is low it indicates that the following cycle is a read cycle from memory. Next, the Address output pins of the CPU become valid (Le., they correspond to a readable address). This time is indicated by the ADS# status signal transitioning from a high to a low, which is the Address Valid Delay time of the CPU. For the i386DX operating at 33 MHz this is 15 ns (T1). Notice that W IR # and ADS # are activated on a low transition of the ClK signal, which is the internal clock of the CPU and the controller, and is obtained by performing a divideby-two function of the ClK2. Also an assumption has been made by the controller that this cycle will be a read cycle. This assumption allows the controller to provide a high on the W IE # status input signal to the cache arrays. At this time the memory starts its address access cycle. This time with current cache technologies is no less than 20 ns (T2). The addition of these two times (address valid delay T1, plus memory access time T2) equals 35 ns which is longer than the period of the internal ClK (30 ns). The second assumption by the controller is now made, that is, there will be a cache hit. If the assumption is invalid and there is not a cache hit the CPU will have to wait for the data to be accessed from the main memory (normally DRAM arrays). However, this "HIT" assumption can be made since the amount of time for the controller to reverse this operation by activating the Ready# signal is 4 ns, and therefore less than the DE enable time (T3). The "HIT" assumption is actually made at the second negative transition of the ClK, where the controller enables the cache outputs by driving the DE signal low. Enabling the DE pin on the SRAMSs allows the data to be released to the local data bus. The amount of time for this operation is 15 ns (T3) for the 395 module operating at 33 MHz plus the SRAMs output enable time from TRI-STATE to active (T4) which is 10 ns. Another timing requirement is the CPU's data set-up time. This time is 5 ns and is the amount of time that the data has to be on the local bus before the next negative transition of the ClK (T5). The sum of these three timing requirements (T3 + T4 + T5) equals 30 ns which is coincident with the ClK's total period. This indicates the amount of tolerance between the two clocks supplied to the CPU and the cache controller can not exceed 0 ns! However, in reality this time can vary somewhat since the timing specifications are at absolute maximum. In this typical configuration it is assumed that the clocks to the CPU and controller are identical. In most applications the source of these clocks (ClK2) are supplied by an oscillator feeding into a clock driver. Ideally all outputs of the driver are identical, however, in reality there is a difference between the propagation delays of each output pin. This delay difference is known as skew. Therefore the ClK2 signals to the CPU and controller are not identical and the skew between them needs to be accounted in the timing diagram of Figure 3-3. National's CGS devices, with guaranteed skew specifications, enable designers to optimize system operating frequencies. 3-5 m ,----------------------------------------------------------------------------------------------, '':: ~ '':: (.) C o :;:; CGS (Continued) ClK2 I (.) Q) Cii CJ) ,I ClK \ ADDRESS \,-_~I _ ADDRESS VALID 1 i W/R#~ 1 ~'----J ADS# WE# READ It' / I J I 1 \~----~-------- READ :-----~,----------- READY# :. MATCH / i \ '------", 1 t4 )4 _~.L..__I_....JI .: -~'-:\ t3 14 • -; _ - 1 1 -----------i---__I---4~ DAT~ RI-STATE DOO-D31 1 1 10- " ; , , , -... -: t5 OUT ) ) . - - - - - - '- READ MISS FIGURE 3-3. Read Hit Cycle 3-6 TL/F/10942-A2 en CD CGS Selection Criteria CD (') The decision tree provides a summarized method for choosing the appropriate CGS technology based on system application requirements. The first decision must be made knowing the power supply and maximum clock frequency. Dynamic Icc graphs demonstrates that CMOS provides the best power/frequency performance below 20 MHz, TTL is the optimal choice between 20 MHz70 MHz, and ECl above 70 MHz. Propagation delay is a concern in applications such as clock trees where the maximum operating frequency is a reciprocal function of the sum of the propagation delays through the tree. trise and trail requirements are driven by CPU demands which require the transitions to be less than 2 ns between 0.8V and 2.0V. The Skew parameters are somewhat less flexible in terms of system designs. For most cases less than 1.0 ns of skew for tpLH and tpHL are required in order to preserve synchronization and less than 2.0 ns of tps (example at 50 MHz) to preserve the duty cycle. Part-to-part skew is critical when the system design incorporates clock trees as previously described. The amount of drive is mainly a function of system bus requirements and loading. Additional concerns are items such as symmetric outputs to optimize termination schemes and whether or not the CPU or ASIC requires CMOS rail-to-rail input swings. CRITERIA POWER SUPPLY 2-5.5V <20 MHz FREQUENCY AND POWER CONSUMPTION SPEED ~is9/~all TIMES PIN- TO-PIN SKEW >5 nS <2.0 nS <700 Ps <3.0 nS OUTPUT DUTY CYCLE PART-TO-PART SKEW <3.5 nS SYMMETRICAL (RAil TO RAil) CURRENT DRIVE 24 rna LOl/lOH 100115 SELECTION CMOS/TTL TTL FIGURE 3-4. CGS Driver Decision Tree 3-7 ECl TL/F/l0942-A3 C)" :l (") ..... ;:;: CD ..... iii" ca o 'i: Cl) ' i: Selection Criteria for CGS Drivers TABLE 3·11 C o ; Device Selection Co) Cl) Q) en Customer Decision Driver Skew (ns) Pin-to-Pin Skew, TOSH/LH (TSG-G in ECl) Significance Performance Comment Meets skew requirements of microprocessor clock designs by reducing timing guardbands. In most systems, 1 ns or less of output skew is acceptable. All CGS drivers meet this need. Part-to-Part skew is critical in mUlti-level tree and parallel driving applications. Best in ECl then Bipolar then CMOS. Meets duty cycle requirement of microprocessors (45/55%) Output signal symmetry is best in bipolar then CMOS. Many microprocessor specs (50 MHz-80 MHz) require 2 ns or less trise/fall times. All CGS drivers have 2 ns or less triselfall performance. Unbalanced load Skew Performance Helpful in designing skew devices for unmatched loads and PCB routing discontinuities. Overall CMOS/TTL part has better unmatched load skew performance than Bipolar. ECl data not available. Speed May be a limiting factor in high speed system designs. Technology performance shows ECl best then bipolar (FASTTMlSI) and then CMOS (FACTTM). Depends on applications, e.g., standard TIL or CMOS loads or backplane driving. Bipolar has highest drive. CMOS has symmetric drive. Dynamic Power Performance is significant in clock driving applications where drivers are continuously switching; and where TRI-STATE is not common. Bipolar has best dynamic performance from 20 MHz to 80 MHz. CMOS is good below 20 MHz due to simultaneous conduction (no load conditions). Part-to-Part Skew, T PV Pin Signal Skew, tps (Duty Cycle Degradation) trise/fall Time (ns) tpLH tpHL Current Drive IOL IOH Power Dynamic Icc (mA) Bipolar CGS74B2525 CMOS/TTL CGS74C2525 CGS74CT2525 ECl 100115 Values Values Values 1 ns 700 ps 75 ps 1.75ns 3.5 ns TBD 1.5 ns 3.0 ns TBD < 2 ns < 2 ns 0.75 ns See CGS Performance Feature 4.8 ns 12.4 ns 0.85 ns 64mA 48mA 24mA 24mA 20mA 6mA 50mA@ 50 MHz 160 mA@ 50 MHz 100 mA @ 50MHz References 1. NSC/lntel/Motorola/ AMD/lSI logic/MIPs microprocessors Datasheets for specifications on input clocks. 2. XNS/TlC technical manual. QUAD DESIGN, Camarillo, CA. 3.33 MHz 386 system design considerations. AP-442 Intel microprocessors volume 2 data book. 4. Rich Jolly, Clock Design in 50 MHz i486™ Systems. AP-453 Intel. 3-8 Not Evaluated (,.) o ~National U ADVANCE INFORMATION (,.) • • o (,.) o Semiconductor ~ (,.) CJ1 CGS7 48303/CGS7 48304/CGS7 48305 Octal Divide-by-2 Circuits/Clock Drivers General Description Features These minimum skew clock drivers are designed for Clock Generation & Support (CGS) applications. The devices guarantee minimum output skew across the outputs of a given device and also from device-to-device. Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems. These octal dividers contain eight flip-flops designed to have minimum skews between the outputs. The '303 is a minimum skew clock driver with six in-phase with ClK and two out-of-phase outputs. The '304 is a minimum skew clock driver with eight in-phase with ClK outputs. The '305 is a minimum skew clock driver with four in-phase with ClK and four out-of-phase outputs. • Functionality compatible to industry standard AS303, AS304 and AS305 • Maximum output skew of less than 1 ns to meet the tight skew budget required in hi-speed clocking schemes • Specifications for device-to-device variation of output skew to ensure tight skew over process variations • Specification for transition skew to meet near-50% output duty cycle requirements • Center pin Vee and GND configuration to minimize high speed switching noise • Capability of current sourcing 48 mA and current sinking of 64 mA • lowest dynamic power consumption at high frequencies Connection Diagrams Pin Assignment for DIP and '303 sOle '304 03 16 02 03 04 15 01 04 2 '305 16 02 03 16 02 15 01 04 15 01 14 ClR GND 14 ClR GND 14 ClR GND GND 13 Vee GND 13 Vee GND GND 12 Vee GND 12 Vee GND 05 11 ClK 05 11 ClK 05 06 10 PRE 06 10 PRE as 08 07 08 07 07 TL/F/10966-1 TL/F/10966-2 3-9 4 7 13 Vee 12 Vee 11 ClK 10 PRE Q8 TLlF/10966-3 ~ C'II r-------------------------------------------------------------------------------------, ~ ~National ~ Semiconductor CGS74B2525 1-to-8 Minimum Skew Clock Driver General Description Features This minimum skew clock driver is designed for Clock Generation and Support (CGS) applications operating well above 20 MHz (33 MHz, 50 MHz). The device guarantees minimum output skew across the outputs of a given device and also from device-to-device. Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems. The 'B2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications. • Clock Generation and Support (CGS) Device-Ideal for high frequency signal generation or clock distribution applications • CGS74B version features National's Advanced Bipolar FAST® LSI process • 1-to-8 low skew clock distribution • Sub 1 ns pin-to-pin output skew • Specifications for device-to-device variation of propagation delay • Specification for transition skew to meet duty cycle requirements • Center pin Vee and GND configuration to minimize high speed switching noise • Current sourcing 48 rnA and current sinking of 64 rnA • Low dynamic power consumption above 20 MHz • Guaranteed 4 kV ESD protection Ordering Code: See Section 4 Logic Symbol Connection Diagram Pin Assignment for DIP and sOle '82525 '82525 I CKIN I I I I I I I I TL/F/l0907-1 00- 1 14 ~01 02- 2 13 1-03 ~CKIN GND- 3 12 GND- 4 Ill-Vee vee - 10 5 ~GND 04- 6 91-°5 06- 7 8~~ TL/F/l0907-2 3-10 to Functional Description I\) Truth Table CJ'1 I\) CJ'1 On the multiplexed clock device, the SEL pin is used to determine which CKn input will have an active effect on the outputs of the circuit. When SEL = 1, the CK1 input is selected and when SEL = 0, the CKo input is selected. The non-selected CKn input will not have any effect on the logical output level of the circuit. The output pins act as a single entity and will follow the state of the CKIN or CK1 /CKo pins when the (,82525) clock distribution chip is selected. '82525 Inputs Outputs L H L H Pin Description Pin Names '82525 Description ~------~~~ Clock Input (,82525) Outputs Y>1 3-11 0 7 TL/F/10907-5 Absolute Maximum Ratings Recommended Operating Conditions (Note 1) If Military/Aerospace specified devices are required, please contact the National Semicond uctor Sales Office/Distributors for availability and specifications. Supply Voltage (Vee) 7.0V Input Voltage (VI) 7.0V Operating Free Air Temperature Storage Temperature Range 4.5Vto 5.5V Supply Voltage (Vee) O°C to + 70°C - 65°C to + 150°C Input Voltage-High (VIH) 2.0V Input Voltage-Low (Vld 0.8V High Level Output Current (IOH) -48mA Low Level Output Current (Iod +64mA Free Air Operating Temperature (TA) Typical BJA Plastic (N) Package °C/W 104 JEDEC SOIC (M) Package °C/W 120 Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. O°C to +70°C DC Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at Vce Symbol Conditions Parameter Min VIK Input Clamp Voltage Vee = 4.5V, II = -18 mA VOH High Level Output 10H = -3 mA, Vee = 4.5V 2.4 10H = -48 mA, Vee = 4.5V 2.0 Voltage Low Level Output VOL Vee = 4.5V, 10L = 64 mA Input Current @ Vee = 5.5V, VIH = 7V Typ Max Units -1.2 V V 0.35 Voltage II = 5V, T A = 25°C. Max Input Voltage 0.5 V 0.1 mA IIH High Level Input Current Vee = 5.5V, VIH = 2.7V 20 J.lA IlL Low Level Input Current Vee = 5.5V, VIH = O.4V -0.5 mA 10 Output Drive Current Vee = 5.5V, Vo = 2.25V Icc Supply Current Vee = 5.5V CIN Input Capacitance Vee = 5V -150 mA Outputs High -50 8 15 mA Outputs Low 32 42 mA 5 pF AC Electrical Characteristics CGS748 Symbol Vee Parameter = 4.5V to 5.5V Units RL = 500n, CL = 50 pF Min Typ Max tpLH Propagation Delay 2 4.8 tpHL CK to On (,2525) 2 2.9 3.0 3-12 4.8 ns m I\,) Extended AC Electrical Characteristics 01 I\,) 01 CGS74B Symbol Parameter Vcc· (V) RL 500n, CL TA Min tOSHL = = = 50 pF, Units O°C to 70°C Typ Max 5.0 0.15 1 ns 5.0 0.15 1 ns 5.0 0.7 1.5 ns 1.75 ns 1.5 ns Maximum Skew Common Edge Output-to-Output Variation (Note 1) tOSLH Maximum Skew Common Edge Output-to-Output Variation (Note 1) tOST Maximum Skew Opposite Edge Output-to-Output Variation (Note 1) tpv Maximum Skew Part-to-Part Variation Skew 5.0 (Note 2) tps Maximum Skew Pin (Signal) Transition Variation 5.0 0.6 (Note 1) trise, Maximum Rise/Fall Time 5.0 1.90 ns tlall (from 0.5/2.4V to 2.4/0.5V 5.0 1.15 ns at 33 MHz, T A = 25°C) 'Voltage Range 5.0 is 5.0V ± 0.5V Note 1: Output·to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHU or LOW to HIGH (tOSLH) or in opposite directions both HL and LH (loST). Parameters tOST and tps guaranteed by design. Note 2: Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is specified for a given set of conditions (Le., capacitive load, Vee, temperature, # of outputs switching, etc.). Parameter guaranteed by design. 3-13 U) r-----------------------------------------------------------------------------~ N LC) ~National •N U Semiconductor N I- o U) LC) N o •N CGS54C/74C2525. CGS54CT/74CT2525 LC) LC) N I- o • LC) N LC) N o CGS54C/74C2526. CGS54CT/74CT2526 1-to-8 Minimum Skew Clock Driver The CGS 'C/CT2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications. The '2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the tpLH and tpHL transitions. The '2526 is similar to the '2525 but contains a multiplexed clock input to allow for systems with dual clock speeds or systems where a separate test clock has been implemented. Features • These CGS devices implement National's FACTTM family • Ideal for signal generation and clock distribution • Guaranteed pin to pin and part to part skew • Multiplexed clock input (,2526) • Guaranteed 2000V minimum ESD protection • Symmetric output current drive of 24 rnA for IOL/IOH • 'CT has TTL-compatible inputs • These products identical to 7 4ACI ACT2525 and 2526 Ordering Code: See Ordering Information Logic Symbols Connection Diagrams Pin Assignment for DIP, Flatpak and sOle '2525 '2525 CKIN '2526 °0 1 14 0, °0 1 16 0, °2 NC 2 13 03 2 15 3 12 CKIN °2 NC 3 14 °3 CKO GND 4 11 GND 4 13 Vee 5 10 Vee GND 5 12 Vee GND °4 Os 6 9 Vee SEL 11 CKI 7 8 TL/F/10684-1 Os 07 °4 Os 6 10 8 Os °7 TL/F/10684-3 TLlF/10684-4 Pin Assignment '2526 for Lee SEL TL/F/10684-2 '2525 '2526 NC GND NC Voc NC NC GND NC Voc SEL l]J[Z]m,rnm [[J[Z][§J[Ilm 04 ill] moo 04 ill] moo °slill NC [j] m0 2 ITlNC °slill NC [j] m0 2 ITlNC °7 Ii] °slJ]] ~O, 1IID03 °7 Ii] °slJ]] [i]]°3 ~O, ~1j]1I§J[j])1I§J ~1j]1ffiI[j])1I§J NC GND NC Voc CKIN CKI GND NCVocCKO TLlF/10684-5 3-14 TL/F110684-6 Functional Description 00- 0 7 SEL o• '2525 -f Inputs Outputs CKIN 01- 0 7 L H L H oN• '2526 en N CJ1 N CJ1 CJ1 N Inputs Pin Description CKIN CKo, CK1 CJ1 N CJ1 On the multiplexed clock device, the SEL pin is used to determine which CKn input will have an active effect on the outputs of the circuit. When SEL = 1, the CK1 input is selected and when SEL = 0, the CKo input is selected. The non-selected CKn input will not have any effect on the logical output level of the circuit. The output pins act as a single entity and will follow the state of the CKIN or CK1/CKo pins when either the multiplexed (,2526) or the straight (,2525) clock distribution chip is selected. Pin Names oN Truth Tables o• Outputs -f N Description CKo CK1 SEL 01- 0 7 Clock Input (,2525) Clock Inputs (,2526) Outputs Clock Select (,2526) L H X X X X H L L H H L H L H L L = Low Voltage Level H = High Voltage Level X = Immaterial '2525 CJ1 N en '2526 CKo CK1N .If >-----t SEL-----..J TLIF/10684-7 TLIF/10684-8 3-15 (0 C\I I.t) C\I t- o Absolute Maximum Ratings C\I C\I Supply Voltage (Vee) • DC Input Diode Current (11K) VI = -0.5V VI = Vee +0.5V • (0 I.t) o I.t) C\I I.t) C\I t- DC Input Voltage (VI) • DC Output Diode Current (10K) VA = 0.5V Va = Vee +0.5V DC Output Voltage (Va) O I.t) C\I I.t) C\I o Recommended Operating Conditions (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (Vee) 'C 'CT -0.5V to + 7.0V -20mA +0.2 mA -20mA +20mA ±50mA OVto Vee Minimum Input Edge Rate 'CT Devices VIN from 0.8V to 2.0V Vee @ 4.5V, 5.5V ±50MA - 65°C to + 150°C Storage Temperature (TSTG) OVto Vee - 40°C to + 85°C - 55°C to + 125°C Minimum Input Edge Rate (~V I ~t) 'C Devices VIN from 30% to 70% of Vec Vee @ 3.3V, 4.5V, 5.5V -0.5V to Vee + 0.5V DC Vee or Ground Current per Output Pin (lee or IGNO) Input Voltage (VI) Output Voltage (Va) Operating Temperature (TA) CGS74C/CT CGS54C/CT -0.5V to Vee +0.5V DC Output Source or Sink Current (10) 2.0Vt06.0V 4.5Vto 5.5V 125 mV/ns (~V I ~t) 125 mV/ns Junction Temperature (TJ) CDIP PDIP Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of CGS circuits outside databook specifications. DC Electrical Characteristics for CGS54C/74C Family Devices Symbol Parameter Vee (V) CGS74C CGS54C CGS74C TA = +25°C TA = -55°C to + 125°C TA = -40°C to +85°C VIL VOH Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 , 3.15 3.85 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1V or Vee -0.1V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1V or Vee -0.1V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.4 3.7 4.7 2.46 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 0.36 0.36 0.36 0.40 0.50 0.50 0.44 0.44 0.44 3.0 4.5 5.5 VOL Conditions Guaranteed Limits Typ VIH Units Maximum Low Level Output Voltage 3.0 4.5 5.5 0.002 0.001 0.001 3.0 4.5 5.5 • All outputs loaded; thresholds on input associated with output under test. tMaximum test duration 2.0 ms, one output loaded at a time. 3-16 lOUT = -50/-LA *VIN = VIL or VIH -12mA -24mA 10H -24mA lOUT = 50 p.A V *VIN = VIL or VIH 12mA 24mA IOL 24mA o DC Electrical Characteristics for CGS54C/74C Family Devices I\,) U1 (Continued) I\,) U1 CGS74C Symbol Parameter Vee (V) TA = +25°C CGS54C CGS74C TA = -55°C to + 125°C TA = - 40°C to + 85°C Typ Maximum Input Leakage Current liN ",Minimum Dynamic Output Current IOLD IOHD Maximum Quiescent Supply Current Icc o• -i Units Conditions U1 Guaranteed Limits ±0.1 5.5 ±1.0 ±1.0 )J-A VI = Vcc. GND @ 5.5 50 75 rnA VOLD = 1.65V Max o• 5.5 -50 -75 rnA VOHD = 3.85V Min I\,) 8.0 5.5 80.0 3.0V are guaranteed to be less than or equal to the respective limit @ 80.0 )J-A 25'C is identical to CGS74C @ 5.5V Vcc. 25'C. @ CGS74CT CGS54CT CGS74CT TA = - 55°C to + 125°C TA = - 40°C to + 85°C Parameter Vee VIH Minimum High Level Input Voltage 4,5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 V VOUT = 0.1V orVcc -0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOUT = 0.1V orVcc -0.1V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 V 3.86 4.86 3.70 4.70 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.50 0.50 0.44 0.44 V ±0.1 ±1.0 ±1.0 )J-A 1.6 1.5 (V) TA = +25°C Typ Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 liN Maximum Input Leakage Current 5.5 ICCT Maximum Icc/Input 5.5 IOLD ",Minimum Dynamic Output Current 5.5 50 5.5 -50 IOHD lee Maximum Quiescent Supply Current 0.6 8.0 5.5 160.0 "All outputs loaded; thresholds on input associated with output under test. tMaximum test duration 2.0 ms, one output loaded at a time. Note: Icc for CGS54CT @ 25'C is identical to CGS74CT Conditions Guaranteed Limits 4.5 5.5 VOL Units @ 25'C. 3-17 V V lOUT = -50)J-A 'VIN = VIL or VIH -24 rnA -24mA lOUT = 50)J-A 'VIN = VIL or VIH 24 rnA 24 rnA IOH IOL VI = Vcc. GND rnA VI = Vce - 2.1V 75 rnA VOLD = 1.65V Max -75 rnA VOHD = 3.85V Min )J-A VIN = Vce orGND 80.0 -i U1 VIN = Vcc orGND DC Electrical Characteristics for CGS54CT17 4CT Family Devices Symbol U1 en tMaximum test duration 2.0 ms, one output loaded at a time. Icc for CGS54C o• I\,) I\,) "All outputs loaded; thresholds on input associated with output under test. Note: liN and Icc I\,) U1 I\,) I\,) en CD N ll) N t- AC Electrical Characteristics O CGS74C CGS54C CGS74C TA = +25°C CL = 50 pF TA = -55°C to + 125°C CL = 50pF TA = -40°C to + 85°C CL = 50pF • CD N ll) N o Symbol Vee' (V) Parameter • ll) N Units Min Typ Max Min Max Min 3.0 2.5 11.0 8.2 3.0 2.9 12.5 8.1 ns Typ Max ll) N t- O • N ll) ll) N o tpLHo tpHL Propagation Delay CK to On (,2525) 3.3 5.0 3.0 3.2 6.5 5.0 11.0 7.8 tpLH, tpHL Propagation Delay CK(n) to On (,2526) 3.3 5.0 3.0 3.6 7.0 5.5 13.0 7.8 3.0 3.3 14.0 8.6 ns tpLH, tpHL Propagation Delay SEL to On (,2526) 3.3 5.0 3.0 4.0 8.0 6.5 14.0 8.5 3.0 3.5 15.0 9.5 ns tOSHL Maximum Skew Common Edge Output-to-Output (Note 1) Variation 3.3 0.3 1.0 1.5 1.0 5.0 0.2 0.7 1.0 0.7 3.3 0.3 1.0 1.5 1.0 5.0 0.2 0.7 1.0 0.7 5.0 0.4 1.0 tOSLH tOST tpv ns Maximum Skew Common Edge Output-to-Output (Note 1) Variation ns Maximum Skew Opposite Edge Output-to-Output (Note 1) Variation Maximum Skew Part-to-Part Variation (Note 2) 1.5 1.0 ns 1.0 'C2525 'CT2525 'C2526 5.0 3.5 'CT2526 5.0 5.0 5.0 3.0 triS9' tlall Maximum Rise/Fall Time (20% to 80% Vee> triS9' tlall Maximum Rise/Fall Time (0.8V /2.0V and 2.0V /0.8V) 4.0 ns ns 3.75 4.0 0.9 1.1 ns ns ·Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Note 1: Output·to·Output Skew is defined as the absolute value of the difference between the elK to Q propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to lOW (tosHLl or lOW to HIGH (losLH) or in opPosite directions both Hl and lH (loST), Note 2: Part·to·part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is specified for a given set of conditions (Le., capacitive load, Vee, temperature, # of outputs switching, etc.). Parameter guaranteed by design. AC Electrical Characteristics Symbol Parameter tpLH, tpHL Propagation Delay CK to On (,2525) tpLH, tpHL Propagation Delay CK(n) to On (,2526) Vee' (V) CGS74CT CGS54CT CGS74CT TA = +25°C CL = 50 pF TA = -55°C to + 125°C CL = 50 pF TA = -40°C to + 85°C CL = 50 pF Min Typ Max 5.0 4.6 6.5 5.0 5.8 8.5 3-18 Min Max Units Min Max 9.0 4.0 10.1 ns 11.1 5.1 12.4 ns AC Electrical Characteristics o I\) CJ'I (Continued) I\) CJ'I Symbol Vcc' (V) Parameter CGS54CT CGS74CT TA = +25°C CL = 50 pF TA = -55°C to + 125°C CL = 50 pF TA = -40°C to +85°C CL = 50 pF Min Typ Max 5.1 8.5 12.4 Propagation Delay SEL to On (,2526) 5.0 tOSHL Maximum Skew Common Edge Output-to-Output (Note 1) Variation 5.0 0.2 Maximum Skew Common Edge Output-to-Output (Note 1) Variation 5.0 Maximum Skew Opposite Edge Output-to-Output (Note 1) Variation 5.0 tOST Maximum Skew Part-to-Part Variation (Note 2) tpv Min Max Min Typ -4 I\) Units oI\)• Max 14.1 ns 0.7 0.7 ns 0.2 0.7 0.7 ns 0.4 1.0 1.0 ns 4.4 5.0 3.5 ns 5.0 ns 5.0 3.0 Maximum Rise/Fall Time (0.8V 12.0V and 2.0V /0.8V) 3.75 1.1 0.9 ns ns 'Voltage Range 5.0 is 5.0V ± 0.5V Note 1: Output-to·Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (toSHU or LOW to HIGH (toSLH) or in opposite directions both HL and LH (tOST)' Note 2: Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is specified for a given set of conditions (Le .. capacitive load. Vee. temperature. # of outputs switching. etc.). Parameter guaranteed by design. Capacitance Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF Vee = 5.0V CPO Power Dissipation Capacitance (,2525) 820 pF-1.2 x 10- 18 (f)" pF Vee = 5.0V CPO Power Dissipation Capacitance (,2526) 820 pF-1.2 x 10- 18 (t)" pF Vee = 5.0V = frequency Recommended Maximum Power Dissipation (W) TA = 85°C TA = 25°C LFPM o• I\) 5.0 trise. tfall I\) 0') -4 ACT2526 Maximum Rise/Fall Time (20% to 80% Vee> 'f I\) CJ'I AC2525 ACT2525 AC2526 trise. tfall Symbol CJ'I CJ'I tpLH. tpHL tOSLH o• CGS74CT PDIP SOIC PDIP SOIC 0 1.105 0.858 0.528 0.41 225 1.493 1.055 0.714 0.504 500 1.71 1.210 0.820 0.578 3-19 CJ'I I\) 0') ~ ,.... o o ,----------------------------------------------------------------------------------, ~National U Semiconductor 100115 Low-Skew Quad Clock Driver General Description Features The 100115 contains four low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input. This device also has the capability to select a secondary single-ended clock source for use in lower frequency system level testing. • • • • Ordering Code: Low output to output skew (:s: 75 ps) Differential inputs and outputs Small outline package Ideal for applications which require the low skew distribution of a clock signal to multiple outputs • Secondary clock available for system level testing See Section 4 Logic Diagram Connection Diagram r.,--ClKl ClKIN ClKIN SOIC CLKl ......--CLK2 • .-,~- CLK2 CLKSEL r . , - - CLK3 • .-,r _ _ CLK3 TCLK ......--CLK4 • .-~- CLK4 TL/F/9842-2 ClKIN CLKIN VEE CLKl VEE CLK4 CLKl 4 CLK4 CLK2 CLK3 CLK2 ClK3 VeeA TCLK ClKSEl Vee TL/F/9842-1 Pin Names Description CLKIN, CLKIN CLK1_4, CLKl_4 TCLK CLKSEL Differential Clock Inputs Differential Clock Outputs Test Clock Inputt Clock Input Selectt tTCLK and CLKSEL are single·ended inputs, with internal 50 k!l pulldown resistors. Truth Table L CLKSEL CLKIN CLKIN TCLK CLKN CLKN L L H H L H H L X X X X X X L H L H L H H L H L = Low Voltage Level = High Voltage Level X = Don't Care H 3-20 ..... o o ..... ..... (1J Absolute Maximum Ratings Above which the useful life may be impaired (Note 1) Case Temperature under Bias (T c) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature Input Voltage (DC) - 65°C to + 150°C Maximum Junction Temperature (TJ) O°C to +85°C -7.0V to + 0.5V VEE Pin Potential to Ground Pin Vccto +0.5V Output Current (DC Output HIGH) +150°C Operating Range (Note 2) -50mA -5.7V to -4.2V DC Electrical Characteristics VEE = -4.5V, Vcc Symbol = VCCA = GND, Tc = O°C to + 85°C (Note 3) Parameter Min Typ Max VOH Output HIGH Voltage -1025 -955 -880 VOL Output LOW Voltage -1810 -1705 -1620 VOHC Output HIGH Voltage -1035 VOLC Output LOW Voltage VIH Single-Ended Input HIGH Voltage -1165 VIL Single-Ended Input LOW Voltage -1810 IlL Input LOW Current 0.50 Units Conditions (Note 4) mV VIN = VIH(Max) OrVIL(Min) Loading with 50n to -2.0V mV VIN = VIH(Min) OrVIL(Max) Loading with 50n to -2.0V -880 mV Guaranteed HIGH Signal for All Inputs -1475 mV Guaranteed LOW Signal for All Inputs fLA VIN -1610 = VIL(Min) DC Electrical Characteristics VEE = -4.2V, VCC Symbol = VCCA = GND, Tc = O°C to +85°C (Note 3) Parameter Min VOH Output HIGH Voltage -1020 Typ -870 VOL Output LOW Voltage -1810 -1605 VOHC Output HIGH Voltage -1030 VOLC Output LOW Voltage VIH Single-Ended Input HIGH Voltage -1150 VIL Single-Ended Input LOW Voltage -1810 IlL Input LOW Current 0.50 Max Conditions (Note 4) Units mV VIN = VIH(Max) OrVIL(Min) Loading with 50n to -2.0V mV VIN = VIH(Min) OrVIL(Max) Loading with 50n to -2.0V -870 mV Guaranteed HIGH Signal for All Inputs -1475 mV Guaranteed LOW Signal for All Inputs fLA VIN -1595 = VIL(Min) DC Electrical Characteristics VEE = -4.8V, VCC Symbol = VCCA = GND, Tc = O°C to +85°C (Note 3) Parameter Min VOH Output HIGH Voltage -1035 Typ -880 VOL Output LOW Voltage -1830 -1620 VOHC Output HIGH Voltage -1045 VOLC Output LOW Voltage VIH Single-Ended Input HIGH Voltage -1165 VIL Single-Ended Input LOW Voltage -1830 IlL Input LOW Current 0.50 Max Conditions (Note 4) Units mV VIN = VIH(Max) OrVIL(Min) Loading with 50n to -2.0V mV VIN = VIH(Min) orVIL(Max) Loading with 50n to -2.0V -880 mV Guaranteed HIGH Signal for All Inputs -1490 mV Guaranteed LOW Signal for All Inputs fLA VIN -1610 = VIL(Min) Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Parametric values specified at -4.2V to -4.BV. Note 3: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. 3-21 II) ,... ,... o o ,... DC Electrical Characteristics = -4.2V to -4.8V unless otherwise specified, Vee = VeeA = GND, Te Symbol Typ VEE Parameter Min VOIFF Input Voltage Differential 150 VeM Common Mode Voltage Vee - 2V IIH Input High Current ClKIN, ClKIN TClK ClKSEl = O°C to Max +85°C Units Conditions mV Required for Full Output Swing Vee - 0.5V V 107 300 260 fJ-A fJ-A fJ-A -30 fJ-A rnA VIN = VIH(Max) leBO Input leakage Current -10 lEE Power Supply Current -70 VIN = VEE AC Electrical Characteristics VEE = -4.2V to -4.8V, Vee = VeeA = GND Symbol Tc = QOC Tc = +25°C Tc = +85°C Min Max Min Max Min Max Parameter Units Conditions tpLH tpHL Propagation Delay ClKIN, ClKIN to ClK(1_4), ClK(1_4) 0.63 0.83 0.65 0.85 0.70 0.93 ns Figures 1,3 tpLH tpHl Propagation Delay, TClK to ClK(1_4), ClK(1-4) 0.50 1.20 0.50 1.20 0.50 1.20 ns Figures 1,2 tpLH tpHl Propagation Delay, ClKSEl to ClK(1_4), ClK(1_4) 0.60 1.40 0.60 1.40 0.60 1.40 ns Figures 1,2 75 ps 0.75 ns tSG-G Skew Gate to Gate (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.35 75 75 0.80 0.75 0.30 0.25 Figures 1, 4 Note 1: Maximum output skew for anyone device. +2V I SCOPE CHAN B : L1 Y O . O l l 1" I SCOPE CHAN A ~. r, "2- Vee 'l DIFFERENnAl PULSE GENERATOR " -L " -L ~ VeeA ClKl ClKIN ClK2 ClK2 ClK3 H'~ H'~ ClKSEl ClK3 TClK ClK4 ClK4 VEE -== -L Lfr-.Lfr-.Lfr-.- I SCOPE CHAN D I -L lj'~ Lfr-.Llr-.- -2.5V Note 1: Shown for testing ClKIN to ClK1 in the differential mode. = equal length 50n impedance lines. Note 3: All unused inputs and outputs are loaded with 50n in parallel with :s; 3 pF to GND. Note 4: Scope should have 50n input terminator internally. FIGURE 1. AC Test Circuit 3-22 : SCOPE CHAN C " YO.Oll 1" Note 2: L1, l2, l3 and l4 l4 " ClKl ClKIN - l3 -== TLlF/9842-3 ..... ..... ..... o o TClK, ClKSEl ClK(1-4) U1 ~~:~ ~~:: OUTPUTS (NOTE 1) ClK(1-4) TL/F/9842-4 FIGURE 2. Propagation Delay, TCLK, CLKSEL to Outputs ClKIN ClKIN ClK(1-4) ~:;:~ ~:;:~ ClK(1-4) 1.05V INPUTS O.31V TRUE OUTPUTS (NOTE 1) COMPLEMENT TL/F/9842-5 FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs ClK(I-4) - - - - - - " " \ . ClK(I-4) - - - - - - TL/F/9842-6 FIGURE 4. Transition Times Note 1: The output to output skew, which is defined as the difference in the propagation delays between each of the four outputs on anyone 100115 shall not exceed 75 ps. EI 3-23 o.... Cot) .... ~National ADVANCE INFORMATION o o U Semiconductor 100310 Low Skew 2:8 Differential Clock Driver General Description Features The 100310 is a low skew 8-bit differential clock driver which is designed to select between two separate differential clock inputs. The low output to output skew « 50 ps) is maintained for either clock input. A lOW on the select pin (SEl) selects ClKINA, ClKINA and a HIGH on the SEl pin selects the ClKINB, ClKINB inputs. The 100310 is ideal for those applications that need the ability to freely select between two clocks, or to maintain the ability to switch to an alternate or backup clock should a problem arise with the primary clock source. A VBB output is provided for single-ended operation. • • • • low output to output skew (:0;; 50 ps) Differential inputs and outputs A"ows multiplexing between two clock inputs Voltage compensated operating range: -4.2V to -5.7V Logic Symbol CLI(O Pin Names Description ClKIN n, ClKIN n SEl ClKo_7' ClKO_8 VBB NC Differential Clock Inputs Select Differential Clock Outputs VBB Output No Connect clKo ClK1 ClK1 ClK2 ClK2 ClK3 ClK3 ClKINA ClKINA Truth Table ClK. ClK. ClKINS ClKINB ClKINA ClKINA ClKINB ClKINB SEl ClK n ClK n X H l X l H l X X H H l l l H X X H l l H X X l H H l H ClKs ClKs SEL ClKs ClKs ClK7 ClK7 ~VeB TL/F/10943-1 Connection Diagram 28-Pin pcc ~ ClKs CLK7 VCCAeLK7 NC ClKINB ITII [Q] [2] 1:!][Il ~ []J [!] ClKINS ClKslj]] ClKs !]] I]]VBB ClK.!]] IlJ ClKINA VCCA 11m ClK. OJ Vec ClK31IZl Ill] SEl ClK3 [j] ~VEE rm ~ClKINA 11ill~~Illl§~~ Cl~ Cl~ ClK, VCCA CLK, CLKo Cl~ TL/F/10943-2 3-24 r----------------------------------------------------------------------------------, o ~National U -4 o W -4 -4 Semiconductor 100311 Low Skew 1:9 Differential Clock Driver General Description Features The 100311 contains nine low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input (ClKIN, ClKIN). If a single-ended input is desired, the Vss output pin may be used to drive the remaining input line. A HIGH on the enable pin (EN) will force a lOW on all of the ClK n outputs and a HIGH on all of the ClK n output pins. The 100311 is ideal for distributing a signal throughout a system without worrying about the original signal becoming too corrupted by undesirable delays and skew. The 100311 is pin-for-pin compatible with the Motorola 100E111. • • • • low output to output skew (::;; 50 ps) 2000V ESD protection 1:9 low skew clock driver Differential inputs and outputs Ordering Code: See Section 4 Logic Symbol --I"oo.~-CLKO ClKa .........-ro...-_ ClK 1 WI .........-ro...-_ CLK2 w2 .........-ro...-_ ClK3 W3 ClKIN ClKIN ---f......,..~H-..........,-- Pin Names Description ClKIN, elKIN EN ClKo_B' ClKO_B Vss NC Differential Clock Inputs Enable Differential Clock Outputs Vss Output No Connect ClK, W, EN Truth Table ClKs Ws ~-I"oo.'--ClK6 W6 .........-ro.._- ClK 7 W7 .............--CLKs Ws elKIN elKIN EN elK n elK n l H H l X X l l H l H l H l H -{:>---V88 TL/F/l0648-1 Connection Diagram 28·Pin pee eLKs a:Ks a.K7 Vr:r:.A CU<7 CLKs ClKa m[Q][[)[ID(I][§J1]] wslill [IjNC ClKs [j] W,~ [IJ Vaa [II ClKIN VCCAIi]] OJ Vee CLK,1ill ~ClKIN CLK3 11l1 IlllEN ClK3 [i]] ~V[[ Ell 112I~~~IDl~~ ~ ~ CU<1 Vr:r:.A a.K1ClKa a.Ko TLlF/l0648-2 3-25 ,.. ,.. M o o ,.. Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature (TSTG) Maximum Junction Temperture (TJ) Ceramic Plastic Pin Potential to Ground Pin (VEE) Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Case Temperature (Tc) Commercial Industrial - 65°C to + 150°C O°Cto +85°C - 40°C to + 85°C Supply Voltage (VEE) Commercial Industrial + 175°C +150°C -7.0Vto +0.5V -5.7V to -4.2V -5.7V to -4.2V VEE to +0.5V -50mA ~2000V Commercial Version-100311 DC Electrical Characteristics VEE = -4.2V to -5.7V, Vcc = VCCA = GND, Tc = O°C to + 85°C (Note 3) Symbol Min Typ Max Units VOH Output HIGH Voltage Parameter -1.025 -955 -870 mV VOL Output lOW Voltage -1830 -1705 -1620 mV VOHC Output HIGH Voltage -1035 VOLC Output lOW Voltage VBB Output Reference Voltage -1380 VOIFF Input Voltage Differential 150 VCM Common Mode Voltage VCC - 2.0 VCC - 0.5 V VIH Input High Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs VIL Input low Voltage -1830 -1475 mV Guaranteed lOW Signal for All Inputs IlL Input lOW Current p.A VIN = VIL (Min) IIH Input HIGH Current ClKIN, ClKIN EN mV -1610 -1320 -1260 0.50 mV Conditions VIN = VIH (Max) orVIL (Min) loading with 50n to -2.0V VIN = VIH orVIL (Max) loading with 50n to -2.0V mV IVBB = - 300 p.A mV Required for Full Output Swing VIN = VIH (Max) leBO Input leakage Current -10 lEE Power Supply Current -115 Vpp Minimum Input Swing 250 VCMR Common Mode Range -1.6 100 250 p.A p.A VIN = VEE -57 mA Inputs Open mV -0.4 V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL·STD·883, Method 3015. Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. 3·26 Commercial Version-100311 (Continued) AC Electrical Characteristics VEE = -4.2V to -5.7V, Symbol vcc = VCCA = GND Tc = O°C Parameter Min f max Max Toggle Frequency tpLH tpHL Propagation Delay, CLKIN to CLKN Differential Single-Ended Max 750 Tc = +25°C Min Tc = +85°C Max Min 750 Units MHz 750 Figures 1 and 2 0.750 0.650 0.950 1.050 0.775 0.675 0.975 1.175 0.840 0.740 1.040 1.240 ns 1.20 0.80 1.25 0.85 1.35 ns tpLH tpHL Propagation Delay Enable and Disable to Output 0.75 tA Release Time EN toCLKIN 0.30 0.30 tskew Gate to Gate Skew Setup Time SEL to CLKINN 250 250 300 ps th Hold Time SEL to CLKINN 0 0 0 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 275 750 50 275 50 750 Figures 1 and 2 ns 0.30 ts 50 Conditions Max 275 750 ps ps Figures 1 and 2 Note 1: Gate to gate skew is defined as the different in propagation delays between each of the outputs. Industrial Version-100311 DC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND (Note 3) Symbol Parameter Tc = -40°C Min Tc = O°C to +85°C Max Min Units Conditions Max VOH Output HIGH Voltage -1085 -870 -1025 -870 mV VOL Output LOW Voltage -1830 -1575 -1830 -1620 mV VOHC Output HIGH Voltage -1095 VOLC Output LOW Voltage -1610 mV VIN = VIH orVIL (Min) VBB Output Reference Voltage -1260 mV IVBB = - 300 p.A VDIFF Input Voltage Differential mV Required for Full Output Swing VCM Common Mode Voltage VIH Input High Voltage -1035 -1565 -1395 -1255 150 -1380 mV 150 VCC - 2.0 VCC - 0.5 VCC - 2.0 VCC - 0.5 -1170 -870 -1165 3-27 -870 VIN = VIH (Max) Loading with 500. to -2.0V orVIL (Min) Loading with 500. to -2.0V V mV Guaranteed HiGH Signal for All Inputs ,... ,... Cf) o o ,... Industrial Version-100311 (Continued) DC Electrical Characteristics (Continued) VEE = -4.2V to -5.7V, Symbol vcc = VCCA = GND (Note 3) Tc = -40°C Parameter VIL Input low Voltage IlL Input lOW Current IIH Input HIGH Current ClKIN, ClKIN EN Tc = O°C to +85°C Min Max Min Max -1830 -1480 -1830 -1475 0.50 Units 0.50 Conditions mV Guaranteed lOW Signal for All Inputs fJ-A VIN = VIL (Min) VIN = VIH (Max) 100 250 ICBO Input leakage Current -10 lEE Power Supply Current -115 VPP Minimum Input Swing 250 VCMR Common Mode Range -1.6 100 250 fJ-A fJ-A VIN = VEE -57 mA Inputs Open -10 -57 -115 250 -0.4 -1.6 mV -0.4 V Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. Note 1: AC Electrical Characteristics VEE = -4.2V to -5.7V, Symbol vcc = VCCA = GND Parameter Tc = -40°C Min fmax Max Toggle Frequency tpLH tpHL Propagation Delay, ClKIN to ClKN Differential Single-Ended Max 750 Tc = +25°C Min Max 750 Tc = +85°C Min Units MHz 750 Figures 1 and 2 0.725 0.625 0.925 1.025 0.80 0.70 1.00 1.20 1.05 0.90 1.25 1.40 ns 1.20 0.60 1.60 0.60 1.60 ns tpLH tpHL Propagation Delay Enable and Disable to Output 0.70 tR Release Time EN toClKIN 0.30 tskew Gate to Gate Skew ts Setup Time SEl to ClKINN 250 200 200 ps th Hold Time SEl to ClKINN 0 0 0 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.30 50 275 750 0.30 50 275 3-28 600 Figures 1 and 2 ns 50 275 Conditions Max 600 ps ps Figures 1 and 2 Test Circuit L1 I~\ Vee \ O.l/,F 1 I l RT -= -= TLlF/l0648-3 FIGURE 1. AC Test Circuit Switching Waveforms 0.7:0.1 n5--", l ~ ,-0.7:0.1 ns ~ I~ -M - . 1"I OUTPUT---t-PL-H-~---~ ~ l~PHL +1.05 V 80% INPUT 50% 20% tpHL - - . . tpLH + 0.31 V TRUE COMPLEMENT tTLH~1 lJ TLlF/10648-4 FIGURE 2. Propagation Delay and Transition Times 3-29 ,.... ll) Cf') o o,.... ~National Q Semiconductor 100315 Low-Skew Quad Clock Driver General Description Features The 100315 contains four low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input. This device also has the capability to select a secondary single-ended clock source for use in lower frequency system level testing. The 100315 is a 300 Series redesign of the 100115 clock driver. • • • • • • • Low output to output skew (~50 ps) Differential inputs and outputs Small outline package (SOIC) Secondary clock available for system level testing 2000V ESD protection Voltage compensated operating range: -4.2V to -5.7V Military and industrial grades available Ordering Code: See Section 4 Logic Diagram Connection Diagram ClK1 ClKIN ClKIN SOICand Flatpack ClK1 ClK2 ClK3 ClK3 TCLK ClK4 CLK4 TL/F/l0960-1 16 ClKIN ClK2 ClKSEL ClKIN VEE 2 15 VEE ClK1 3 14 ClK4 ClK1 4 13 ClK4 12 CLK3 ClK2 11 CLK3 VeeA 10 CLK2 TClK Vee ClKSEL TLlF/l0960-2 Pin Names Description CLKIN, CLKIN CLKl-4, CLKl_4 TCLK CLKSEL Differential Clock Inputs Differential Clock Outputs Test Clock Inputt Clock Input Selectt tTCLK and CLKSEL are single-ended inputs, with internal 50 kn pulldown resistors. Truth Table ClKSEl ClKIN ClKIN TClK ClKN ClKN L L H H L H X X H L X X X X L H L H L H H L H L = Low Voltage Level = High Voltage Level X = Don't Care L H 3-30 Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired (Note 1) If Military/ Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature Maximum Junction Temperature (TJ) Plastic Ceramic Case Temperature (Td Commercial Industrial Military - 65°C to + 150°C Supply Voltage (VEE) Commercial Industrial Military +150°C +175°C Case Temperature under Bias (Td O°Cto +85°C -7.0Vto +0.5V VEE Pin Potential to Ground Pin Input Voltage (DC) O°Cto + 85°C - 40°C to + 85°C - 55°C to + 125°C -5.7V to -4.2V -5.7V to -4.2V -5.7Vto -4.2V Vccto +0.5V -50mA Output Current (DC Output HIGH) Operating Range (Note 2) -5.7V to -4.2V ESD (Note 2) ::::2000V Commercial Version-100315 DC Electrical Characteristics VEE = -4.2V to -5.7V, Vcc Symbol = Parameter VCCA = GND, Tc = O°C to +85°C (Note 3) Min Typ Max VOH Output HIGH Voltage -1025 -955 -870 VOL Output LOW Voltage -1830 -1705 -1620 VOHC Output HIGH Voltage -1035 VOLC Output LOW Voltage VIH Single-Ended Input HIGH Voltage -1165 -870 mV VIL Single-Ended Input LOW Voltage -1830 -1475 mV IlL Input LOW Current 0.50 IIH Input High Current CLKIN, CLKIN TCLK CLKSEL Conditions (Note 4) Units mV VIN = VIH(Max) OrVIL(Min) Loading with 500. to -2.0V mV VIN = VIH(Min) or VIL(Max) Loading with 500. to -2.0V -1610 p,A Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL(Min) VIN = VIH(Max) 150 250 250 VOIFF Input Voltage Differential 150 VCM Common Mode Voltage VCC - 2V ICBO Input Leakage Current -10 lEE Power Supply Current -67 Vpp Minimum Input Swing 250 VCMR Common Mode Range -1.6 p,A p,A p,A mV VCC - 0.5V V -35 mA p,A Required for Full Output Swing VIN = VEE mV -0.4 V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 4: Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. EI 3-31 Il) ,.... ('t) o o ,.... Commercial Version-100315 AC Electrical Characteristics Symbol (Continued) VEE Tc Parameter Min = = -4.2V to -4.8V, O°C Max = Tc vcc = VCCA = Tc +25°C Max Min = GND +85°C Min fMAX Maximum Clock Frequency 750 tpLH tpHL Propagation Delay CLKIN, ClKIN to CLK(1_4), ClK(1_4) Differential Single-Ended 0.59 0.59 0.79 0.99 0.62 0.62 0.82 1.02 0.67 0.67 0.87 1.07 750 Units Conditions Max 750 MHz ns Figures 1, 3 tpLH tpHL Propagation Delay, TCLK to CLK(1_4), ClK(1_4) 0.50 1.20 0.50 1.20 0.50 1.20 ns Figures 1,2 tpLH tpHL Propagation Delay, ClKSEL to CLK(1_4), CLK(1_4) 0.80 1.60 0.80 1.60 0.80 1.60 ns Figures 1,2 50 ps 0.80 ns tSG-G Skew Gate to Gate (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 50 0.30 0.80 50 0.30 0.80 0.30 Figures 1,4 Note 1: Maximum output skew for anyone device. Industrial Version-100315 DC Electrical Characteristics VEE = Symbol Parameter Tc = -4.2Vto -5.7, VCC -40°C Tc = = VCCA = O°C to + 85°C GND Units Conditions Min Max Min Max -1085 -870 -1025 -870 mV VIN = VIH(Max) OrVIL(Min) -1830 -1575 -1830 -1620 mV VIN = VIH(Min) OrVIL(Max) mV VIN = VIH(Max) OrVIL(Min) -1610 mV VIN = VIH(Min) OrVIL(Max) VOH Output HIGH Voltage VOL Output lOW Voltage VOHC Output HIGH Voltage VOLC Output LOW Voltage VIH Single-Ended Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for All Inputs VIL Single-Ended Input LOW Voltage -1830 -1480 -1830 -1475 mV Guaranteed LOW Signal for All Inputs IlL Input LOW Current 0.50 p,A VIN = VIL(Min) IIH Input HIGH Current ClKIN, CLKIN TCLK CLKSEl p,A p,A p,A VIN = VIH (Max) -1095 -1035 -1565 0.50 107 300 260 VOIFF Input Voltage Differential VCM Common Mode Voltage ICBO Input leakage Current lEE Power Supply Current -70 107 300 260 150 150 VCC - 2V VCC - 0.5V V -10 -10 p,A VPP Minimum Input Swing 250 VCMA Common Mode Range -1.6 -30 -70 0.4 -1.6 mV -30 250 3-32 mA mV -0.4 V Required for Full Output Swing VIN = VEE Loading with 50nto -2.0V loading with 50nto -2.0V ....4 Industrial Version-100315 o o (Continued) W ....4 AC Electrical Characteristics Symbol Tc Parameter (J1 VEE = Min = -4.2Vto -5.7V, vcc -40°C Max Tc = Min = VCCA Max = GND +85°C Min Units fMAX Maximum Clock Frequency 750 Propagation Delay ClKIN, ClKIN to ClK(1_4), ClK(1_4) Differential Single-Ended 0.59 0.59 0.99 0.99 0.62 0.62 0.82 1.02 0.67 0.67 0.87 1.07 0.50 1.20 0.50 1.20 0.50 1.20 ns 50 ps 0.80 ns Propagation Delay, TClK to ClK(1_4), ClK(1_4) tSG-G Skew Gate to Gate (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 50 0.30 0.80 750 MHz 50 0.30 0.80 Conditions Max tpLH tpHL tpLH tpHL 750 = Tc +25°C 0.30 ns Figures 1, 3 Figures 1,2 Note 1: Maximum output skew for anyone device. Military Version-100315-Preliminary DC Electrical Characteristics VEE = -4.2Vto -5.7V, VCC = VCCA = GND (Note 3) Symbol Parameter VOH Output HIGH Voltage VOL Output lOW Voltage VOHC Output HIGH Voltage VOLC Output lOW Voltage VDIFF Input Voltage Differential VCM Common Mode Voltage VIH Min Typ Max Units Tc -1025 -870 mV O°Cto + 125°C -1085 -870 mV -55°C -1830 -1620 mV O°Cto + 125°C -1830 -1555 mV -55°C -1035 mV O°Cto + 125°C -1085 mV -55°C -1610 mV O°Cto + 125°C -1555 mV -55°C mV -55°C to + 125°C 150 Conditions Notes VIN = VIH(Max) OrVIL(Min) loading with 50n. to - 2.0V 1,2,3 VIN = VIH(Min) orVIL(Max) loading with 50n. to - 2.0V 1,2,3 Required for Full Output Swing 1,2,3 Vcc - 2.0 VCC - 0.5 V -55°C to + 125°C Single-Ended Input High Voltage -1165 -870 mV -55°C to + 125°C Guaranteed HIGH Signal for All Inputs 1,2,3,4 VIL Single-Ended Input low Voltage -1830 -1475 mV -55°C to + 125°C Guaranteed lOW Signal for All Inputs 1,2,3,4 IIH Input HIGH Current ClKIN, ClKIN 120 }LA -55°C to + 125°C TClK 350 }LA ClKSEl 300 }LA ICBO Input leakage Current lEE Power Supply Current, Normal -10 -90 }LA -30 mA -55°C to +125°C -55°C to + 125°C 1,2,3 VIN = VIH(Max) VIN = VEE 1,2,3 1,2,3 1,2,3 Note 1: FlOOK 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55'C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100 % on each device at - 55'C, + 25'C, and + 125'C, Subgroups 1, 2, 3, 7, and a. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at -55'C, + 25'C, and + 125'C, Subgroups Al, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing VOHIVOL. 3-33 Military Version-100315-Preliminary (Continued) AC Electrical Characteristics Symbol Parameter VEE = -4.2V to -5.7V, Vee = VeeA = GND Tc = -55°C Min Max Min Max Min Max Tc = +25°C Tc = + 125°C Units tpLH tpHL Propagation Delay ClKIN, ClKIN to ClK(1_4), ClK(1_4) 0.61 0.S1 0.61 0.S1 0.60 0.S3 ns tpLH tpHL Propagation Delay, TClK to ClK(1_4), ClK(1-4) 0.50 1.20 0.50 1.20 0.50 1.20 ns tSG-G Skew Gate to Gate (Note 5) 100 ps tTLH tTHL Transition Time 20% to SO%, SO% to 20% 0.75 ns 100 0.35 100 O.SO 0.30 0.25 0.75 Conditions Notes 1,2,3 Figures 1 and2 4 Note 1: FlOOK 300 Series cold temperature testing is performed by temperature soaking (to guarantee iunction temperature equals -55·C, then testing immedi· ately after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at + 25·C temperature only, Subgroup A9. + 25·C, Subgroup A9, and at + 125·C and Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at Al1. - 55·C temperatures, Subgroups A 10 and Note 4: Not tested at + 25·C, + 125·C and - 55·C temperature (design characterization data). Note 5: Maximum output skew for anyone device. +2V ..I. II I SCOPE CHAN B : I SCOPE CHAN A : -'J:::L - 'J:::L -,. DIFFERENTIAL PULSE GENERATOR -t: L3 r -_ _ _ I I Vee VeeA - l2 0.011 JlF SCOPE CHAN C I SCOPE CHAN D I L4 CLKl ClKIN ..L - - ,. ..L -- ClK2 CLKIN CLK3 & "'H-I\I'I'I\I,'I'~"''I''''''-4 CLKSEl CLK4 .H-JV'l'.v.~"""""..... TCLK & & CLK4 HI~M_""" II "."." ryO.OIl.' -2.SV Note 1: Shown for testing CLKIN to CLKl in the differential mode. Note 2: l1, L2, L3 and L4 = equal length 50n impedance lines. Note 3: All unused inputs and outputs are loaded with 50n in parallel with !S:3 pF to GND. Note 4: Scope should have 50n input terminator internally. FIGURE 1. AC Test Circuit 3-34 TLIF/10960-3 TClK, ClKSEL j >t ClK (1-4) _ _ _ _ >t tpLH PHL -.._t_ _ _ _ _ _ _.., tpLH ",,_tP_HL_ __ OUTPUTS (NOTE 1) ClK ( 1 - 4 ) - - - - ' TLIF/10960-4 FIGURE 2. Propagation Delay, TCLK, CLKSEL to Outputs ClKIN ClKIN ClK (1-4) ~~~~ ~ ClK (1-4) 1.05V INPUTS O. .31V tpLH tpHL TRUE OUTPUTS (NOTE 1) COMPLEMENT TLIF/10960-5 FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs ClK(1-4)------_ ClK(1-4)------TL/F/10960-6 FIGURE 4. Transition Times Note 1: The output to output skew, which is defined as the difference in the propagation delays between each of the four outputs on anyone 100115 shall not exceed 75 ps. 3-35 Section 4 Physical Dimensions Section 4 Contents Ordering Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bookshelf Distributors 4-2 4-3 4-4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows for Bipolar. CMOS and CMOS TTL compatible CGS parts: CGS T Clock Gene,."on and Suppa,' N 74 T L Operating Temperature Range - - - - - - - - - - - ' 54 = Military 74 = Commercial Package Code M = S.O.I.C (JEDEC Standard) N = Plastic DIP Technology - - - - - - - - - - - - - - - - - - - - ' B = Bipolar C = CMOS CT = CMOS TTL Compatible Device Type - - - - - - - - - - - - - - - - - - - - - - ' Temperature Information Temperature Range t Technology 74-Grade TTL/CMOS Bipolar 64-Grade O°Cto 70°C -40°C to + 85°C 54-Grade - 55°C to + 125°C CMOS -40°C to + 85°C N/A - 55°C to + 125°C CMOS/TTL Compatible - 40°C to + 85°C N/A - 55°C to + 125°C - 55°C to + 125°C BiCMOS O°Cto + 70°C - 40°C to + 85°C tTypically, 64- and 74-grade are commercial products; and 54-grade mayor may not be Mil/Aero product. The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows for ECl compatible CGS parts: 100115 Device Numbe, =r (basic) S TL J PackageCode-----------------~ S = Small Outline Package (SOIC) 4-3 C Temperature Range C = Commercial (O°C to + 85°C) rn c o 'iii c G> E ~National U Semiconductor All dimensions are in inches (millimeters) C (ij (.) '~ -&. 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 0.200 ±0.005 (5.080±0.127) 45 x 0 0.350±0.008 -------. (8.890 ± 0.203) I I o Top View JI _/ ;I (0.381)J~ +~~, 0.015 I~ 0.063-0.075 ~ TYiP - '" MINTYP 0.007-0.011 (0.178-0.279) R TYP I "00'-''',, 0.077-0.093 r j-- _+_ (1.959-2.362) 0.045-0.055 0.022 -0.028 (0.S59-0.711) TYP j- (1.143_2,397) ~~~~~ TYP 0.067 -0.083 / (1.702-2.108) TVP - - - .... LOETAILA Side View 45°x~ (1.016 ±0.254) 3 PLCS Bottom View ~ (0.076).. (~:~~~) 'MAX TYP MINTYP~ 0.022 • .l I.mll!f~ (0.152) MIN TYP MAX TYP Detail A 14 Lead Ceramic Dual-In-Line Package (D) NS Package Number J14A 0.785 1 - . - - - - (19.939) - - - - - 1__1 MAX t 0.025 (0.635) 0.220-0.310 (5.588-7.874) RAD ~r-T"!"T""~~-r.:"T""l~~ 0.018 ±0.003 (0.457 ±0.076) L 0.100 ±0.01 0 (2.540 ±0.2S4) --H- 0.12S-D200 (3.175-5.D80) 0.150 (3.81) MIN 4-4 0.015 ±O.OlD (0.381±0.254) J14AIREVGI 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J 16A 0.785~ (19.939) MAX 13 12 0.025 (0.635) 11 10 9 --r RAO 0.220-0.310 (5.588 - 7.874) ~~~~~ 0.005 - 0.020 (0.127 - 0.508) RAO TYP .-=i D.290-D.320 I 0.200 D.DD5--j ~~!(7'366_8'128) .!!:.!!!!. 95°+5° - (4.572) ".:' ~ ~~~J=~~J=~~j=tJ~~_.--r - - 0.008-0.012 (0.203-0.305) MAX J __-r__ ~ 0.080 I --l 0.310 _ 0.410 (7.874 -10.41) I (2.032) B~~~ I-- ENDS J16A fREV K) 14 Lead Small Outline Integrated Circuit (S) NS Package Number M 14A (~~~:=~:;~:)-I 114 13 12 11 10 9 8 ~~.........,. -1 ;w-I 0.228-0.244 (5.791-6.198) 30' ~yp (-, !~'0 LEAD NO.1 ____ )OENT J/ /\ _*____f:;:;::;:::;:::;:;:::::;::::;:::;::;:::;:;:::::;::::;J/ ~ ----t 1 J!J!.!Q.MAX (0.254) 0.150-0.157 (3.810 -3.988) - 0.010-0.020 45° (0.254 -0.508) x =1 r 80 MAX TYP r;----'\: H1c .l--JE 0.008~ (0.203-0.254) TYP ALL LEADS 0.004 (oTo2) t ALL LEADS + -----rlJ--.I It I 0.053 - 0.069 (1.346-1.753) SEATING PLANE 0.004 -0.010 ~ t *f 0.014 (0.356) 0.016-0.050 (0.406 -1.270) TYP ALL LEADS ~J (1.270) TYP I-Jl (0.'02~0.254) _ 1 1 : J - 0 . 0 2 0 TYP (0.356 - 0.508) ~TYP (0.203) M14AtAEV 1-11 ALL LEAD TIPS 4-5 C/) c::: "en c::: cv o 16 Lead Small Outline Integrated Circuit (5) NS Package Number M16A r, E i5 (ij (.) (~:;~:=~03~~) ""'i r~' "en >.s:: a.. I Q &1 0.228-0.244 (5.791-6.198) LEAD NO.1 IDENT (~:!~~=~:~:~) 1r;---....... )lh. L - t r--=r ::::::~~, I J L,::::::, 1 0.053-0.069 (1.346 -1. 753) 0.010 -0.020 , (0.254-0.508) x45 t + ad) ( TYP ALL LEADS ~ 8' MAX TYP ALL LEADS 0.004 t ot (0.356) TYP ALL LEADS 0.004 - 0.01 0 (0.102 -0.254) tU=-ro§~~ JL J LOJ-D.:~:P 0.D50Jl (1.270) (0.356 -0.508) ~TYP TYP iD.i'02i SEATING (0.203) ALL LEAD TIPS M16' IREV HI 14 Lead Plastic Dual-In-Line Package (P) NS Package Number N14A 41312 ~ p,,:~~tll~j m W li INDEX IDENT ~DIA ~MAX (2.337) (0.762) DEPTH OPTION 1 OPTION 02 0.135±0.OO5 (3.429iO.127) 0.3DO -0.320 ~:' T 90' ±4° TYP + 0.020 MIN 0.125-0.150 (0.508) I (3.175-3.810) -II 0.014-0.023 TYP- _ (0.356 -0.584) I --'1 ~ ~ ~~/;o -'~I ,t.-..m. TYP (0.203-0.406) I 0.075±0.015 -(1.905±0.381) _ __ 0.10D±0.01D TYP (2.540±0.254) 0.050±0.010 TYP -(1.270-0.254) I 0.280 _(7.112)~ MIN 1 of .. 0.325 ~~:~~~ +1.016) (8255 . -0.381 4-6 N14"tREVf) r------------------------------------------------------------------------------------, -c ::::T 16 Lead Plastic Dual-In-Line Package (P) NS Package Number N16E -j, '< en n" e!. ·r c 9 ~~~~~~~---r 0.250tO.Ol0 (6.350 t 0.254) PIN NO.1 IDENT 3" 0.090 (2.286) ~~~~~~~~ 4 OPTION 01 (1) ::l en 0" IAREA N D E X 15 :(S ,', ::l en PIN NO.1 IDENT 1 1 2 OPTION 02 0.300-0.320 r- (7.620-8.128)1 0.145 - 0.200 (3.683 - 5.080) o.o;o.J (0.508) r= L 0'15~ 0.125 (3.175- 3.810) 0.014 - 0.023 (0.356 - 0.584) I- 0.030 :to.015 (0.762:t0.381) I I-- 0.100:t0.Ol0 (2.540:t 0.254) TYP TYP ~ 95°:t5° 0.280 I- -l I,~,I (0.325~~:~tg (8.255 ~k~1~) 28 Lead Plastic Chip Carrier (Q) NS Package Number V28A VIEW A·A ~ ~_II~ (1.143) x45 D 0.165-0.180 (4.191-4.572) 0.032-0.040 (0.813 -1.016) t t t (0.127-0.381) t t + 0.104-0.118 (2.642-2.997) V2SAIAEVG) 4-7 0.065 (1.651) : 0.008-0.G16 (0.203-0.406) TYP N16E (REV F) In C o "Cii c(L) E 14 Lead Ceramic Flatpak (F) NS Package Number W14B - C "iii (.) "Cii >- .c 0.026-0.035 (0.660-0.889) TYP I'- 0.370-0.385._ 0.055-0.080 ( 1.397-2.032) (9.398-9.779) 11- (Q.127) 0.050:1: 0.005 (1.270 :1:0.127) TYP ... 0.005 MIN TYP i a.. 0.250-0.370 13~1~2 ~101o.l9~8"'i~9.398) l j o 1 1.... 4 .. 0.280 (7.112) G MAX.L ....1.... 1 ) 0.245-0.255 lLA_S_S.,rf-I-"I" "I I2~31" 1" 1'4 SEEI~/: 7'1"'!~6.m) .,.5'1""1"'1'6.. DETAIL A PIN #1 IDENT j L 0.015-0.019 (0.381-0.483) TYP j 0.008-0.012 (0.203-0.305) 0.250-0.370 (6.350-9.398) DETAIL A 0.004-0.006 (0.102-0.152) TYP ~j L L j ! e- 0.045 MAX TYP W14B (REV H) ( 1.143) 16 Lead Ceramic Flatpak '(F) NS Package Number W16A 0.050-0.080 (1.270 - 2.032) 1 0.004 - 0.006 TYP (0.102-0.152) ~ -tjl-oll- II r 1t 0.371 - 0.390 ~f9.423-9.906) I 0.007 -0.018 (0.178 -0.457)-" TYP 0.050 ±0.005 TYP (1.270±0.127) ~1"-0.000 MIN TYP 0.25010.370 (6.350 - 9.398) I ~~~~~~----,r .161514131211109 0.300 (7.620) MAX GLASS t 0.245 ~0.275 (6.223-6.985) ~ I --,2 3 4 5 6 7 8 -'~llij DETAIL A PIN NO.1 10ENT 0.026-0.040 (0.660 -1.016) TYP~ l , I t + 0.015-0.019 (0.381-0.482) TYP 4-8 0.008 - 0.012 ~.- (0.203-0.305) 0.250-0.370 (6.350-9.398) ~I~ 1]- W'6A (REV HI DETAIL A Bookshelf of Technical Support Information National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical literature. This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and section contents for each book. Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this bookshelf. We are interested in your comments on our technical literature and your suggestions for improvement. Please send them to: Technical Communications Dept. MIS 16-300 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 AlS/AS lOGIC DATABOOK-1990 Introduction to Advanced Bipolar logic • Advanced low Power Schottky • Advanced Schottky ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CEllS-1987 SSI/MSI Functions • Peripheral Functions • lSllVlSI Functions • Design Guidelines • Packaging CMOS lOGIC DATABOOK-1988 CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount DATA ACQUISITION liNEAR DEVICES-1989 Active Filters. Analog Switches/Multiplexers. Analog-to-Digital Converters. Digital-to-Analog Converters Sample and Hold • Temperature Sensors • Voltage Regulators • Surface Mount DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989 Selection Guide and Cross Reference Guides. Diodes • Bipolar NPN Transistors Bipolar PNP Transistors • JFET Transistors • Surface Mount Products. Pro-Electron Series Consumer Series • Power Components • Transistor Datasheets • Process Characteristics DRAM MANAGEMENT HANDBOOK-1991 Dynamic Memory Control. Error Detection and Correction • Microprocessor Applications for the DP8408A/09A117/18/19/28/29. Microprocessor Applications for the DP8420Al21A/22A Microprocessor Applications for the NS32CG821 EMBEDDED SYSTEM PROCESSOR DATABOOK-1989 Embedded System Processor Overview • Central Processing Units • Slave Processors • Peripherals Development Systems and Software Tools FDDI DATABOOK-1991 FOOl Overview. DP83200 FOOl Chip Set • Development Support • Application Notes and System Briefs F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1990 Family Overview. 300 Series (low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets ECl BiCMOS SRAM, ECl PAL, and ECl ASIC Datasheets • Design Guide • Circuit Basics • logic Design Transmission Line Concepts • System Considerations • Power Distribution and Thermal Considerations Testing Techniques • Quality Assurance and Reliability. Application Notes FACTTM ADVANCED CMOS LOGIC DATABOOK-1990 Description and Family Characteristics • Ratings, Specifications and Waveforms Design Considerations. 54AC174ACXXX. 54ACT174ACTXXX. Quiet Series: 54ACQ/74ACQXXX Quiet Series: 54ACTQ174ACTQXXX. 54FCT174FCTXXX. FCTA: 54FCTXXXA174FCTXXXA FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990 Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F174FXXX FAST® APPLICATIONS HANDBOOK-1990 Reprint of 1987 Fairchild FAST Applications Handbook Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders Operators· FIFOs· Counters. TTL Small Scale Integration. Line Driving and System Design FAST Characteristics and Testing • Packaging Characteristics GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989 Continuous Voltage Regulators • Switching Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators Instrumentation Amplifiers • Surface Mount GRAPHICS HANDBOOK-1989 Advanced Graphics Chipset • DP8500 Development Tools • Application Notes IBM DATA COMMUNICATIONS HANDBOOK-1992 IBM Data Communications. Application Notes INTERFACE DATABOOK-1990 Transmission Line Drivers/Receivers • Bus Transceivers • Peripheral Power Drivers. Display Drivers Memory Support • Microprocessor Support • level Translators and Buffers • Frequency Synthesis. Hi-Rei Interface LINEAR APPLICATIONS HANDBOOK-1991 The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit applications using both monolithic and hybrid circuits from National Semiconductor. Individual application notes are normally written to explain the operation and use of one particular device or to detail various methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index. LOCAL AREA NETWORK DATABOOK-1992 Integrated Ethernet Network Interface Controller Products • Ethernet Physical layer Transceivers Ethernet Repeater Interface Controller Products • Hardware and Software Support Products. FOOl Products • Glossary LS/S/TTL DATABOOK-1989 Contains former Fairchild Products Introduction to Bipolar logic • low Power Schottky • Schottky • TTL • TTL-low Power MASS STORAGE HANDBOOK-1989 Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers. Disk Drive Interface Circuits Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits • Disk Interface Design Guide MEMORY DATABOOK-1990 PROMs, EPROMs, EEPROMs • TTL I/O SRAMs • ECl I/O SRAMs MICROCONTROLLER DATABOOK-1989 COP400 Family. COP800 Family. COPS Applications. HPC Family • HPC Applications MICROWIRE and MICROWIRE/PLUS Peripherals· Microcontroller Development Tools MICROPROCESSOR DATABOOK-1989 Series 32000 Overview • Central Processing Units • Slave Processors • Peripherals Development Systems and Software Tools. Application Notes. NSC800 Family PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1990 Product Line Overview • Datasheets • Designing with PLDs • PLD Design Methodology. PLD Design Development Tools Fabrication of Programmable Logic • Application Examples REAL TIME CLOCK HANDBOOK-1991 Real Time Clocks and Timer Clock Peripherals • Application Notes RELIABILITY HANDBOOK-1986 Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510 The Specification Development Process. Reliability and the Hybrid Device· VLSIIVHSIC Devices Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device European Reliability Programs • Reliability and the Cost of Semiconductor Ownership Reliability Testing at National Semiconductor • The Total Militaryl Aerospace Standardization Program 883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products Radiation Hardened Technology • Wafer Fabrication • Semiconductor Assembly and Packaging Semiconductor Packages· Glossary of Terms· Key Government Agencies. ANI Numbers and Acronyms Bibliography. MIL-M-38510 and DESC Drawing Cross Listing SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989 Audio Circuits • Radio Circuits • Video Circuits • Motion Control Circuits • Special Function Circuits Surface Mount TELECOMMUNICATIONS-1992 COMBO and SLiC Devices • ISDN • Digital Loop Devices • Analog Telephone Components • Software Application Notes NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS ALABAMA Huntsville Arrow Electronics (205) 837-6955 Bell Industries (205) 837-1074 Hamilton! Avnet (205) 837-7210 Pioneer Technology (205) 837-9300 Time Electronics (205) 721-1133 ARIZONA Chandler Hamilton! Avnet (602) 961-1211 Phoenix Arrow Electronics (602) 437-0750 Tempe Anthem Electronics (602) 966-6600 Bell Industries (602) 966-7800 Time Electronics (602) 967-2000 CALIFORNIA Agora Hills Bell Industries (818) 706-2608 Time Electronics (818) 707-2890 Zeus Components (818) 889-3838 Burbank Elmo Semiconductor (818) 768-7400 Calabasas F!X Electronics (818) 592-0120 Chatsworth Anthem Electronics (818) 775-1333 Arrow Electronics (818) 701-7500 Time Electronics (818) 998-7200 Costa Mesa Hamilton Electro Sales (714) 641-4100 Cypress Bell Industries (714) 895-7801 Gardena Hamilton! Avnet (213) 516-8600 Irvine Anthem Electronics (714) 768-4444 Rocklin Anthem Electronics (916) 624-9744 Bell Industries (916) 652-0414 Roseville Hamilton! Avnet (916) 925-2216 San Diego Anthem Electronics (619) 453-9005 Arrow Electronics (619) 565-4800 Hamilton! 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Avnet (913) 888-8900 MARYLAND Columbia Anthem Electronics (301) 995-6840 Arrow Electronics (301) 596-7800 Time Electronics (301) 964-3090 Zeus Components (301) 997-1118 Gaithersburg Pioneer Technology (301) 921-0660 MASSACHUSETTS Andover Bell Industries (508) 474-8880 Beverly Sertech Laboratories (508) 927-5820 Lexington Pioneer Standard (617) 861-9200 Norwood Gerber Electronics (617) 769-6000 Peabody Hamilton! Avnet (508) 531-7430 Time Electronics (508) 532-9900 Tyngsboro Port Electronics (508) 649-4880 Wakefield Zeus Components (617) 246-8200 Wilmington Anthem Electronics (508) 657-5170 Arrow Electronics (508) 658-0900 MICHIGAN Grand Rapids Pioneer Standard (616) 698-1800 Grandville Hamilton! Avnet (616) 243-8805 Livonia Arrow Electronics (313) 462-2290 Pioneer Standard (313) 525-1800 Novi Hamilton! Avnet (313) 347-4720 Wyoming R. M. Electronics. Inc. (616) 531-9300 MINNESOTA Eden Prairie Anthem Electronics (612) 944-5454 Arrow Electronics (612) 828-7140 Pioneer Standard (612) 944-3355 Edina Arrow Electronics (612) 830-1800 Time Electronics (612) 943-2433 Minnetonka Hamilton! Avnet (612) 932-0600 NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued) MISSOURI Chesterfield Hamiltonl Avnet (314) 537-1600 SI. Louis Arrow Electronics (314) 567-6888 Time Electronics (314) 391-6444 NEW JERSEY Cherry Hill Hamiltonl Avnet (609) 424-0100 Fairfield Hamiltonl Avnet (201) 575-3390 Pioneer Standard (201) 575-3510 Marlton Arrow Electronics (609) 596-8000 Time Electronics (609) 596-6700 Pine Brook Anthem Electronics (201) 227-7960 Arrow Electronics (201) 227-7880 Wayne Time Electronics (201) 758-8250 NEW MEXICO Albuquerque Alliance Electronics Inc. (505) 292-3360 Bell Industries (505) 292-2700 Hamiltonl Avnet (505) 345-0001 NEW YORK Binghamton Pioneer (607) 722-9300 Buffalo Summit Electronics (716) 887-2800 Commack Anthem Electronics (516) 864-6600 Fairport Pioneer Standard (716) 381-7070 Hauppauge Arrow Electronics (516) 231-1000 Hamiltonl Avnet (516) 231-9444 Time Electronics (516) 273-0100 Port Chester Zeus Components (914) 937-7400 Rochester Arrow Electronics (716) 427-0300 Hamilton/Avnet (716) 292-0730 Summit Electronics (716)334-8110 Ronkonkoma Zeus Components (516) 737-4500 Syracuse Hamiiton/Avnet (315) 437-2641 Time Electronics (315) 432-0355 Westbury Hamilton/ Avnet Export Div. (516) 997-6868 Woodbury Pioneer Electronics (516) 921-8700 NORTH CAROLINA Charlotte Hamilton/ Avnet (704) 527-2485 Pioneer Technology (704) 527-8188 Durham Pioneer Technology (919) 544-5400 Raleigh Arrow Electronics (919) 876-3132 Hamilton/ Avnet (919) 878-0810 Time Electronics (919) 874-9650 OHIO Centerville Arrow Electronics (513) 435-5563 Cleveland Pioneer (216) 587-3600 Columbus Time Electronics (614) 794-3301 Dayton Bell Industries (513) 435-8660 Bell Industries-Military (513) 434-8231 Hamilton/ Avnet (513) 439-6700 Pioneer Standard (513) 236-9900 Zeus Components (513) 293-6162 Solon Arrow Electronics (216) 248-3990 Hamilton/ Avnet (216) 349-5100 Westerville Hamilton/ Avnet (614) 882-7004 OKLAHOMA Tulsa Arrow Electronics (918) 252-7537 Hamiltonl Avnet (918) 664-0444 Pioneer Standard (918) 665-7840 Radio Inc. (918) 587-9123 OREGON Beaverton Anthem Electronics (503) 643-1114 Arrow Electronics (503) 626-7667 Hamilton/ Avnet (503) 627-0201 Lake Oswego Bell Industries (503) 635-6500 Portland Time Electronics (503) 684-3780 PENNSYLVANIA Horsham Anthem Electronics (215) 443-5150 Pioneer Technology (215) 674-4000 Mars Hamilton/ Avnet (412)281-4150 Pittsburgh Pioneer (412) 782-2300 TEXAS Austin Arrow Electronics (512) 835-4180 Hamilton/ Avnet (512) 837-8911 Minco Technology Labs. (512) 834-2022 Pioneer Standard (512) 835-4000 Time Electronics (512) 346-7346 Carrollton Arrow Electronics (214) 380-6464 Dallas Hamilton/ Avnet (214) 308-8111 Pioneer Standard (214) 386-7300 Houston Arrow Electronics (713) 530-4700 Hamilton/ Avnet (713) 240-7733 Pioneer Standard (713) 495-4700 Richardson Anthem Electronics (214) 238-7100 Time Electronics (214) 644-4644 Zeus Components (214) 783-7010 UTAH Midvale Bell Industries (801) 255-9611 Salt Lake City Anthem Electronics (801) 973-8555 Arrow Electronics (801) 973-6913 Hamilton/ Avnet (801) 972-2800 West Valley Time Electronics (801) 973-8494 WASHINGTON Bellevue Arrow Electronics (206) 643-4800 Bothell Anthem Electronics (206) 483-1700 Kirkland Time Electronics (206) 820-1525 Redmond Bell Industries (206) 867-5410 Hamilton/ Avnet (206) 241-8555 WISCONSIN Brookfield Arrow Electronics (414) 792-0150 Pioneer Electronics (414) 784-3480 Mequon Taylor Electric (414) 241-4321 Waukesha Bell Industries (414) 547-8879 Hamilton/ Avnet (414) 784-8205 CANADA WESTERN PROVINCES Burnaby Hamilton/ Avnet (604) 420-4101 Semad Electronics (604) 420-9889 Calgary Electro Sonic Inc. (403) 255-9550 Semad Electronics (403) 252-5664 Zentronics (403) 295-8838 Edmonton Zentronics (403) 468-9306 Markham Semad Electronics Ltd. (416) 475-3922 Richmond Electro Sonic Inc. (604) 273-2911 Zentronics (604) 273-5575 Saskatoon Zentronics (306) 955-2207 Winnipeg Zentronics (204) 694-1957 EASTERN PROVINCES Mississauga Hamilton/ Avnet (416) 795-3825 Time Electronics (416) 672-5300 Zentronics (416) 564-9600 Nepean Hamilton/ Avnet (613) 226-1700 Zentronics (613) 226-8840 Ottawa Electro Sonic Inc. (613) 728-8333 Semad Electronics (613) 727-8325 Pointe Claire Semad Electronics (514) 694-0860 SI. Laurent Hamilton/ Avnet (514) 335-1000 Zentronics (514) 737-9700 Willowdale ElectroSonic Inc. (416) 494-1666 Winnipeg Electro Sonic Inc. (204) 783-3105 NOTES NOTES NOTES SALES OFFICES ALABAMA Huntsville (205) 721·9367 GEORGIA Atlanta (404) 551·1150 MISSOURI St. Louis (314) 569·9830 PENNSYLVANIA Horsham (215) 672·6767 ARIZONA Tempe (602) 966·4563 ILLINOIS Schaumburg (708) 397·8777 NEW JERSEY Paramus (201) 599·0955 PUERTO RICO Rio Piedras (809) 758·9211 CALIFORNIA Rocklin (916) 632:2750 San Diego (619) 587·0666 Sunnyvale (408) 721·8400 Tustin (714) 259·8880 Woodland Hills (818) 888·2602 INDIANA Carmel (317) 843·7160 Fort Wayne (219) 436·6844 NEW YORK Fairport (716) 223·7700 Wappinger Falls (914) 298·0680 QUEBEC Pointe Claire (514) 426·2992 IOWA Cedar Rapids (319) 395·0090 NORTH CAROLINA Raleigh (919) 832·0661 MARYLAND Hanover (410) 796·8900 OHIO Dayton (513) 435·6886 Independence (216) 524·5577 COLORADO Boulder (303) 440·3400 Englewood (303) 790·8090 FLORIDA Boca Raton (407) 997·9891 Maitland (407) 875·8800 MASSACHUSETTS Burlington (617) 221·4500 MICHIGAN Livonia (313) 464·0020 MINNESOTA Bloomington (612) 854·8200 ONTARIO Mississauga (416) 678·2920 Nepean (613) 596·0411 OREGON Portland (503) 639·5442 TEXAS Austin (512) 346·3990 Houston (713) 894·4888 Richardson (214) 234·3811 UTAH Murray (801) 268·1175 WASHINGTON Kirkland (206) 822·4004 WISCONSIN Brookfield (414) 782·1818 ~National D Semiconductor


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