1992_National_IBM_Data_Communications_Handbook 1992 National IBM Data Communications Handbook

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400029

~ N~tional

~ SemICOnductor

IBM DATA
COMMUNICATIONS
HANDBOOK
1992 Edition

IBM Data Communications
Application Notes
Physical Dimensions

..
•
III

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1. Life support devices or systems are devices or systems
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or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
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TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice, to change said circuitry or specifications.

S"
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~National

-...
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Semiconductor

:::J

Introduction to IBM Data Communications

iii
3C

D)
D)

IBM 3270/3299 PROTOCOL

NATIONAL'S SOLUTION

The IBM 3270/3299 serial communications protocol was
developed by IBM for the cluster controller-peripheral link in
370 class mainframe systems. Fortune 1000 corporations
that use these systems have large scale networking needs
and often support thousands of terminals and printers. Although PC-based networks have increased in popularity,
shipments of IBM 3270 peripherals have remained steady
over the last few years due to the huge investments made in
both hardware and software application development.

With over a decade of shipments into the IBM 3270 connectivity market, National is the leading standard product semiconductor supplier. The first generation DP8340/41 protocol translation chips were used in DCA's industry standard
IRMA cards which were the first 3270 terminal emulation
products available for IBM PC's. Although the DP8340/41
pair solved many design issues regarding IBM 3270 protocol, bit slice microcontrollers were still required to meet
the fast response times specified by IBM. To address this
issue National introduced the DP8344 Biphase Communications Processor in 1987. This product features a
3270/3299/5250 transceiver tightly coupled to a high
speed RISC. CPU. The BCP was the first single hardware
platform capable of supporting the 3270, 3299 and 5250
datastreams. This new product was well received by corporations such as Memorex Telex, IBM, DEC, Harris Adacom,
Tandberg Data, liS, Apple Computer, and many others.

The 3299 protocol is a variation of the 3270 protocol in that
an 8·bit address byte is asserted between the starting sequence and the first word for each out board transmission
from the controller. This was done to allow up to eight 3270
peripherals to be multiplexed and connected to the controller via a single coax cable, thus reducing cabling costs. The
multiplexing and de-multiplexing is done with a 3299 terminal multiplexer.

With a combination of experience in IBM connectivity protocols, mixed signal design capabilities, extensive laboratory
resources, and knowledge of IBM peripherals (terminals,
printers, terminal emulation cards), National will continue to
develop products that meet the semiconductor needs of our
customers. By working in conjunction with third parties, National can offer the complete hardware and software solution to IBM Data Communications.

IBM 5250 PROTOCOL
The 5250 serial communications protocol was developed by
IBM originally for the mid-range System 3x line of computers. IBM has updated the System 3x series to the AS/400.
The AS/400 line can vary from small office environment
processors to more powerful processors with greatly enhanced networking facilities that rival the smaller 370 class
mainframes. They are typically used in hotels, bank branch
offices and hospitals for a variety of tasks.

iii

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3
3
c

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n·
o·
::s

Table of Contents
Introduction ................................................................. .
Alphanumeric Index .......................................................... .

iii
v

Section 1 IBM Data Communications
DP8340 IBM 3270 Protocol Transmitter/Encoder .....' ..........•.....•............
DP8341 IBM 3270 Protocol Receiver/Decoder .................................. .
DP8342 High-Speed 8-Bit Serial Transmitter/Encoder ............................ .
DP8343 High-Speed 8-Bit Serial Receiver/pecoder .............................. .
DP8344B Biphase Communications ~rocessor-BCP ............................. .

1-3
1-12
1-23
1-33
1-44

Section 2 Application Notes,'
AN-641 MPA-II-A Multi-Protocol Terminal Emulation Adapter Using the DP8344 .....
AN-624 A Combined Coax~Twisted Pair 3270 Line Interface for the, DP8344 Biphase
Communications Processor ........ '......................................... .
AN-623 Interfacing Memory to the DP8344B ............................•........
AN-504 DP8344 BCP Stand-Alone Soft-Load System ............................. .
AN-499 "lnterrupts"~A Powerful Tool of the Biphase Communications Processor ... .
AN-625 JRMKSpeeds Command Decoding ........... '........ ; ..... ; .............
AN-627 DP8344 Remote processor Interfacing ...... '" ......... ~ ..... '.......... .
AN-626 DP8344 Timer Application ...................... " ... ~ ................. .
AN-516 Interfacing the DP8344 to Twinax ...................................... .
AN-688 The DP8344 BCP Inverse Assembler ............. ; ..................... .

Section 3

2-3
2':95
2-99
.2-101
2-112
2-117
2-121
2-135
2-152
2-172

Physical Dimensions

. Physical Dimensions ....................................................... ',' .
Bookshelf
Distributors'

3-3

Alpha-Numeric Index
AN-499 "Interrupts"-A Powerful Tool of the Biphase Communications Processor ............... 2-112
AN-504 DP8344 BCP Stand-Alone Soft-Load System ........................................ 2-101
AN-516 Interfacing the DP8344 to Twinax .................................................. 2-152
AN-623 Interfacing Memory to the DP8344B ................................................. 2-99
AN-624 A Combined Coax-Twisted Pair 3270 Line Interface for the DP8344 Biphase Communications
Processor ............................................................................. 2-95
AN-625 JRMK Speeds Command Decoding ................................................ 2-117
AN-626 DP8344 Timer Application ......................................................... 2-135
AN-627 DP8344 Remote Processor Interfacing .............................................. 2-121
AN-641 MPA-II-A Multi-Protocol Terminal Emulation Adapter Using the DP8344 ................ ;.2-3
AN-688 The DP8344 BCP Inverse Assembler ............................................... 2-172
DP8340 IBM 3270 Protocol Transmitter/Encoder ..... ; ........................................ 1-3
DP8341 IBM 3270 Protocol Receiver/Decoder ............................................... 1-12
DP8342 High-Speed 8-Bit Serial Transmitter/Encoder ................ ; ........................ 1-23
DP8343 High-Speed 8-Bit Serial Receiver/Decoder ........................................... 1-33
DP8344B Biphase Communications Processor-BCP .......................................... 1-44

~
~

~National

Semiconductor

:::s

Product Status Definitions

(/)

:::s

a..

Definition of Terms
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

Section 1
IBM Data
Communications

III

Section 1 Contents
DP8340 IBM 3270 Protocol Transmitter/Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8341 IBM 3270 Protocol Receiver/Decoder.........................................
DP8342 High-Speed 8-Bit Serial Transmitter/Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8343 High-Speed 8-Bit Serial Receiver/Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8344B Biphase Communications Processor-BCP ....................................

1-2

1-3
1-12
1-23
1-33
1-44

~National

Semiconductor

DP8340 IBM 3270 Protocol Transmitter/Encoder
General Description

Features

The DP8340 generates a complete encoding of parallel
data for high speed serial transmission which conforms to
the protocol as defined by the IBM 3270 information display
system standard. The DP8340 converts parallel input data
into a serial data stream. Although the IBM standard covers
biphase serial data transmission over a coax line, the
DP8340 also adapts to general high speed serial data transmission over other than coax lines, at frequencies either
higher or lower than the IBM standard.

•
•
•
•

Ten bits per data byte transmission
Single-byte or multi-byte transmission
Internal parity generation (even or odd)
Internal crystal controlled oscillator used for the generation of all required chip timing frequencies
• Clock output directly drives receiver (DP8341) clock input
• Input data holding register
• Automatic clear status response feature
• Line drivers at data outputs provide easy interface to
biphase coax line or general transmission lines
II < 2 ns driver output skew
• Bipolar technology provides TTL input/output compatibility
• Data outputs power up/down glitch free
II Internal power up clear and reset
• Single + 5V power supply

The DP8340 and its complementary chip, the DP8341 (receiver/decoder) have been designed to provide maximum
flexibility in system designs. The separation of the transmitter/receiver functions provides convenient addition of more
receivers at one end of a biphase line without the need of
unused transmitters. This is specifically advantageous in
control units where typical biphase data is multiplexed over
many biphase lines and the number of receivers generally
exceeds the number of transmitters.

Connection Diagram
Dual·ln·L1ne Package
01 11

Vee

01 10

REG LOAD

Dig

REG FULL

DiS

AUTO RESPONSE

Dl7

TRANSMITTER ACTIVE

016

PARITY CRT

01 5

EVEN/ODD

014

DATA OUT

013

DATA OUT

012

DATA DELAY

eLK OUT

GNO

X1
TLlF/5251-1

Top View
FIGURE 1
Order Number DP8340N
See NS Package Number N24A

1·3

Block Diagram
C~~~I~LI

CLOCK
OUTPUT

RESET

TRANSMITTER
ACTIVE

EVEN/O~~
PARITY

.....'\N\I-II-t~ X2
EXTERNAL
CRYSTAL
18.867 MHz

c::::J

I
I

-C----I-I

CRYSTAL
OSCILLATOR
Xl

CONTROL LOGIC

&....------1

~------~~------~

AUTO·
RESPONSE

~
~A T A

UI\'I\

}

SERIAL
OUTPUTS

DATA
DELAY

REGISTERS
FULL
TLlF/5251-2

FIGURE 2. DP8340 Serial BI-Phase Transmitter/Encoder Block Diagram

Functional Description
while still maintaining even or odd parity in the bit 12 position. This is the format of data word bytes and other commands in the 3270 Standard. The Parity Control input is the
pin which controls when this operation is in effect.

Figure 2 is a block diagram of the DP8340 biphase Transmitter/Encoder. The transmitter/encoder contains a crsytal
oscillator whose input is a crystal with a frequency eight (8)
times the data rate. A Clock Output is provided to drive the
DP8341 receiver/decoder Clock Input and other system
components at the oscillator frequency. Additionally, the oscillator drives the control logic and output shift register/format logic blocks.

Another feature of the transmitter/encoder is the internal
TI / AR (Transmission Turnaround/Auto Response) capability. After each Write type message from the control unit in
the 3270 Standard, the receiving unit must respond with
clean status (bits 2 through 11). With the transmitter/encoder, this function is accomplished simply by forcing the AutoResponse input to the Logic "0" state.

Data is parallel loaded from the sytem data bus to the transmitter/encoder's input holding register. This data is in turn
loaded by the transmitter/encoder to its output shift register
if this register was empty at the time of the load. During this
load, message formatting and parity are generated. The formatted message is then shifted out at the bit rate frequency
to the TIL to biphase block which generates the proper
data bit formatting. The three data outputs, DATA, DATA,
and DATA DELAY provide for flexible interface to the coax
line with a minimum of external components.

Operation of the transmitter/encoder is automatic. After the
first data byte is loaded, the Transmitter Active output is set
and the transmitte.r/encoder immediately formats the input
data and serially shifts it out its data outputs. If the message
is a multi-byte message, the internal format logic will modify
the message data format for multi byte as long as the next
byte is loaded to the input holding register before the last
data bit of the previous data byte is transferred out of the
internal output shift register. After all data is shifted out of
the transmitter/encoder the Transmitter Active output will
return to the inactive state.

The Control Logic block interfaces to all blocks to insure
proper chip operation and sequencing. It controls the type
of parity generation through the Even/Odd Parity input. An
additional feature provided by the transmitter/encoder is
generation of odd parity and placement in bit 10 position

1-4

Detailed Pin/Functional Description
Crystal Inputs X 1 and X2

is edge sensitive, the data present during the logic "0" state
of this input is loaded, and the input data must be valid
before the logic "0" to logic "1" transition. It is after this
transition that the transmitter/encoder begins formatting of
data for serial transmission.

The oscillator is controlled by an external, parallel resonant
crystal connected between the X1 and X2 pins. Normally, a
fundamental mode crystal is used to determine the operating frequency of the osicllator; however, overtone mode
crystals may be used.

Auto Response (IT/ AR)

This input provides for automatic clear data transmission (all
bits in logic "0") without the need of loading all zero's.
When a logic "0" is forced on this inpiut the transmitter/encoder immediately responds with transmission of "clean
status". This function is necessary after the completion of
each write type command and in other functions in the 3270
specification. In the logic "1" state the transmitter/encoder
transmits data entered on the Data Inputs.

Crystal Specifications (Parallel Resonant)

Type

AT-cut crystal

Tolerance

0.005% at 25°C
0.01 % from O°C to + 70°C
Fundamental (Parallel)

Stability
Resonance
Maximum Series Resistance

Dependent on Frequency
(For 18.867 MHz, 50n)

Load Capacitance
R

15 pF
C

TO PIN X2 ~L- VCC

..L

PIN (14)

TO PIN Xl
PIN (13)

___T....
_
....

CRYSTAL
SEE (FIG. 16)

FREQ

Even/Odd Parity

This input sets the internal logic of the DP8340 transmitter/
encoder to generate either even or odd parity for the data
byte in the bit 12 position. When this pin is in the logic "0"
state odd parity is generated. In the logic "1" state even
parity is generated. This feature is useful when the control
unit is performing a loop back check and at the same time
the controller wishes to verify proper data transmission with
its receiver/decoder.

10 MHzto 500n
30 pF
20 MHz ±10%
>20 MHz

120n
15 pF
±10%

TL/F/5251-3

Parity Control/Reset
Depending on the type of message transmitted, it is at times
necessary in the IBM 3270 specification to generate an additional parity bit in the bit 10 position. The bit generated is
odd parity on the previous eight (8) bits of data. When the
Parity Control input is in the logic "1" state the data entered
at the Data Bit 10 position is placed in the transmitted word.
With the Parity Control input in the logic "0" state the Data
Bit 10 input is ignored and odd parity on the previous data
bits is placed in the normal bit 10 position while overall word
parity (bit 12) is even or odd (controlled by Even/Odd Parity
input). This eliminates the need for external logic to generate the parity on the data bits.
Truth Table

FIGURE 3. Connection Diagram

If the DP8340 transmitter is clocked by a system (clock
crystal oscillator not used), pin 13 (X1 input) should be
clocked directly using a Schottky series (74S) circuit. Pin 14
(X2 input) may be left open. The clocking frequency must be
set at eight times the data bit rate. Maximum input frequency is 28 MHz. For the IBM 3270 Interface, this frequency is
18.867 MHz. At this frequency, the serial bit rate will be
2.358 Mbits/sec.
Clock Output

The Clock Output is a buffered output derived directly from
the crystal oscillator block and clocks at the oscillator frequency. It is designed to directly drvie the DP8341 receiver/
decoder Clock Input as well as other system components.
Registers Full

This output is used as a flag by the external operating system. A logic "1" (active state) on this output indicates that
both the internal output shift register and the input holding
register contain active data. No additional data should be
loaded until this output returns to the logic "0" state (inactive state).

Parity Control Input

Transmitted Data Bit 10

Logic "1"

Data entered on Data Input 10

Logic "0"

Odd Parity on 8-bit data byte

When this input is driven to a voltage that exceeds the power supply level (9V to 13V) the transmitter/ encoder is reset.
Serial Outputs-DATA, DATA, and DATA DELAY

These three output pins provide for convenient application
of data to the biphase Coax line (see Figure 15 for application). The Data outputs are a direct bit representation of the
biphase data while the DATA DELAY output provides the
necessary increment to clearly define the four (4) DC levels
of the pulse. The DATA and DATA outputs add flexibility to
the DP8340 transmitter/encoder for use in high speed differential line driving applications.

Transmitter Active

This output will be in the logic "1" state while the transmitter/encoder is about to transmit or in the process of transmitting data. Otherwise, it will assume the logic "0" state
indicating no data presently in either the input holding or
output shift registers.
Register Load

The Register Load input is used to load data from the Data
Inputs to the input holding register. The loading function

III
I

1-5

C)
~

~
D-

r---------------------------------------------------------------------------------------,
Functional Timing Waveforms-Message Format

Single Byte Transmission

TRANSMISSION
TERMINATION

TRANSMISSION
START

REG FULL

--I1____________

----(~,~

DATA _ _ _....

DATA

. DATA DELAY

111 11 11 1 1
\-STARTING

SEQUENCE-----~
TL/F/5251-4

FIGURE 4. Overall Timing Waveforms for Single Byte
Multi-Byte Transmission
SYNC BIT
BYTE 2

PARITY
BYTE X

((

TA-----1

DATA _ _ _....

I I

DATA

1 11 11 1

r-IJ.D~

DATA DELAY

1 ICODEVIOLATION

SY~CI B~T(? B1T IsY1cIB~T
BIT

BIT

B1T
12

-si~8~~~E

STARTING SEQUENCE

TL/F/5251-5

FIGURE 5. Overall Timing Waveforms for Multi-Byte

1·6

Absolute Maximum Ratings

(Note 1)
Maximum Power Dissipation @25°C·
Dual-In-Line Package
'Derate dual·in·line package 20 mWI'C above 25"C.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee

Input Voltage

Operating Conditions,

5.5V

Output Voltage

5.25V

Storage Temperature Range

Supply Voltage, (Vee)

- 65°C to + 150°C

lead Temperature (Soldering, 10 sec.)

2500mW

Min
4.75

Max
5.25

Units
V

+70

°C

Ambient Temperature, TA

300°C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

ConditIons

VIH

logic "1" Input Voltage
(All Inputs Except X1 and X2)

VIL

logic "a" Input Voltage
(All Inputs Except X1 and X2)

VeLAMP

Input Clamp Voltage
(All Inputs Except X1 and X2)

liN = -12 mA

IIH

logic "1" Input Current
Register load Input

Vee = 5.25V
VIN = 5.25V

IlL

logic "a" Input Current
Register load Input

VOH1

logic "1" All Outputs Except ClK OUT,
DATA, DATA, and DATA DELAY

Min

,Vee = 5.25V
VIN = 0.5V

All Inputs Except X1 and X2

VOH2
VOL1

logic "a" All Outputs Except ClK OUT,
DATA, OATA and DATA DELAY Outputs

Max

2.0

All Others Except X1 and X2

logic" 1" for CKl OUT, DATA,
OATA and DATA DELAY Outputs

Typ

V
0.8

-0.8

-1.2

0.3

120

,.,.A

0.1

,.,.A

-15

-300

,.,.A

-5

-100

,.,.A

3.2

3.9

10H = -1 mA

2.5

3.4

10H = -10 mA

2.6

3.0

'IOH = -100,.,.A

Units

.10L =

5 mA

0.35

0.5

0.4

0.6

logic "a" for ClK OUT, DATA,
DATA and DATA DELAY Outputs

IOL = 20 mA

Short Circuit Current for All Outputs
Except ClK OUT, DATA, DATA, and
DATA DELAY

VOUT = OV
(Note 4)

-10

-30

-100

IOS2

Short Circuit Current for DATA,
DATA, and DATA DELAY Outputs

VOUT = OV
(Note 4)

-50

-140

-350

IOS3

Short Circuit Current for ClK OUT

(Note 4)

-30

-90

-200

lee

Power Supply Current

Vee = 5.25V

170

250

VOL2
IOS1

Timing Characteristics Oscillator Frequency =

18.867 MHz (Notes 2 and 3)
Typ

Max

Units

tpd1

REG LOAD to Transmitter Active (TA)
Positive Edge

load Circuit 1
Figure 7

tpd2

REG lOAD to REG Full; Positive Edge

Load Circuit 1
Figure 7

tpd3

load Circuit 1
Figure 7

tpd4

Positive Edge of REG lOAD to
Positive Edge of DATA

load Circuits 1 & 2
Figure 9

Symbol

Parameter

Conditions

1-7

Min

III

Timing Characteristics Oscillator Frequency =

18.867 MHz (Notes 2 and 3) (Continued)
Typ

Max

Units

tpd5

REG LOAD to DATA; Positive Edge

Load Circuits 1 & 2
Figure 9, (Note 6)

380

475

tpd6

REG LOAD to DATA DELAY; Positive Edge

Load Circuits 1 & 2
Figure 9, (Note 6)

160

250

tpd7

Positive Edge of DATA to Negative Edge
of DATA DELAY

Figure 9, (Note 6)

100

115

Positive Edge of DATA DELAY to Negative
Edge of DATA

Figure 9, (Note 6)

110

125

110

4 X T -50

Symbol

tpd8

Parameter

Conditions

Load Circuit 2
Load Circuit 2

t pd9,
tpd10

Skew between OATA and DATA

tpd11

Negative Edge of Auto Response to
Positive Edge of TA

Figure 10

Maximum Time Delay to Load Second Byte
after Positive Edge of REG FULL

Figure 8, (Note 6)

tpd12
tpd13

Min

Load Circuit 2
Figure 9

X1 to CLK OUT; Positive Edge

Load Circuit 1
Load Circuit 1
Load Circuit 2
Figure 13

tpd14

X1 to CLK OUT; Negative Edge

Load Circuit 2
Figure 13

tpd15
tpd16
tpd17

Negative Edge of AR to Positive
Edge of REG FULL

Figure 10

Load Circuit 1

Skew between TA and REG FULL during
Auto Response

Figure 10

REG LOAD to REG FULL; Positive Edge
for Second Byte

Figure 14

Load Circuit 1
Load Circuit 1

tpw1

REG LOAD Pulse Width

Figure 12

tpw2

First REG FULL Pulse Width (Note 5)

Load Circuit 1
Figure 7, (Note 6)

tpw3

REG FULL Pulse Width prior to Ending
Sequence (Note 5)

A'gure 7, (Note 6)

tpw4

Pulse Width for Auto Response

Figure 10

Data Setup Time prior to REG LOAD
Positive Edge, Hold Time (tH) = 0 ns

Figure 12

tr1

Rise Time for DATA, OATA, and DATA
DELAY Output Waveform

Figure 11

Fall Time for DATA, DATA, and DATA
DELAY Output Waveform

Figure 11

tf1
tr2

Rise Time for TA and REG FULL

Load Circuit 2
Load Circuit 1
Figure 15

tf2

Fall Time for TA and REG FULL

8 x T

Load Circuit 1,

Load Circuit 2

Load Circuit 1
Figure 15

+ 60

8x T

+ 100

5XB

ns
ns

ns
15

(Note 7)
Data Rate Frequency
Mbits/s
DC
3.5
(Clock Input must be
this Frequency)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min.lmax. limits apply across the O·C to + 70·C temperature range and the 4.7SV to S.2SV power supply range. All typical
values are for TA = 2S·C and Vee = S.OV.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max. or min. are so classified on absolute basis.
Note 4: Only one output should be shorted at a time. Output should not be shorted for more than one second at a time.
Note 5: T = 1/(Oscillator Frequency), unit for T should be ns. 8 = 8T
Note 6: Oscillator Frequency Dependent.
Note 7: For the IBM 3270 Interface, the data rate frequency is 2.3S8 Mbits/s. 28 MHz clock frequency corresponds to 3.7S% jitter when referenced to Figure 10 of
DP8341 Datasheet.

fMAX

1-8

Timing Characteristics (Continued)

co
w

Load Circuit 1

Load Circuit 2

Vee

vee

TL/F/5251-6

TLlF/5251-7

FIGURE 6. Test Load Circuits

Timing Waveforms
~--------~~------------------3V

50%

II~

R~ru:: ------I------Jf.~ . r JVOH
50

%-VOL

-tPW2-! ~(--J !-tpw3TLlF/5251-B

FIGURE 7. Timing Waveforms for Single Byte Transfer

'It:

~~r.:~

--=it__t~Pd12

REG FULL

VOH

" .

VOL

_ _ _ _ _oJ.

WINDOW
TO LOAD MULTI-BYTE DATA 17'1zxB

.
TL/F/5251-9

FIGURE 8. Maximum Window to Load Multi-Byte Data

tpd4
\

DATA

'----------'

VOL

•

VOH
DATA DELAY
TL/F/5251-10

FIGURE 9. Timing Waveforms for Three Serial Outputs
1-9

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
C")

co
a.
C

Timing Waveforms

(Continued)
~,

__------~~-----------------------3Y
50%

REG FULL
TL/F/5251-11

FIGURE 10. Timing Waveforms for Auto-Response

10%
1'----YoL
TL/F/5251-12

FIGURE 11. Output Waveform for DATA, DATA, DATA DELAY (Load Circuit 2)

REG LOAO

--------,.ii

i llory----I-'s- 'V1-'H=on5 3Y
lPW1

50%

DATA OR PARITY -------~'V
CONTROL

11\...._______ OY

Ii\

TLlF/5251-13

FIGURE 12. Register Load Waveform Requirement

eLK OUT

VOL
TL/F/5251-14

FIGURE 13. Timing Waveforms for Clock Pulse

REG LOAD

y~"l
-I

,-----------------------------3Y
50%

OV
OH

~
50%

_lpd17

Ipd3

-lpd2

VOL

VoH

REG FULL

50%

VoL
TL/F/5251-15

FIGURE 14. Timing Waveforms for Two Byte Transfer

10%
1.....- - - - - - - VOL
TLlF/5251-16

FIGURE 15. Rise and Fall Time Measurement for TA and REG Full

1-10

Typical Applications
FIG.J

~VCC
'PARITY CONTROL

r--....&.;;;.;...---il..,,;..;;~.,

AUTO RESPONSE
DP8340
TRANSMITTERI
ENCODER
REG FULL

TRANSMITTER
ACTIVE

~I
~I

RECEIVER
DISABLE
DATA
AVAILABLE

~I+-----t

~ ...__
ER_R_O_R_-I

t;;
~

•

tiN

DP8341
RECEIVERI
DECODER

OUTPUT CONTROL
OUTPUT ENABLE

1:1:1 PULSE
TRANSFORMER
FIG. 17

BI·PHASE
INPUT
-IN

IRECEIVER ACTIVE
TL/F/5251-17

FIGURE 16. Typical Applications for IBM 3270 Interface

+5V

DATA
DELAY

__ 1'!..._
A

OS3487

Rl
150

~
~

DATA

z
c

90Q COAX
(RG62A/U)

....

...
e

R5
150

TRANSMITTER
ACTIVE

I2
I

+IN]

CONNECT TO
OPB341
RECEIVER

L __ ,*,s_--1

&
R6
120

-IN
6

GND
TL/F/5251-18

Note 1: Resistance values are in

•

n, ± 5%, 114 W

Note 2: Tl is a 1:1:1 pulse transformer, LMIN = 500 ",H for 18 MHz system clock. Pulse Engineering Part No. 5762/Surface Mount, 5762M/PE·85762. Technitrol
Part No. 11 LHA, Valor Electronics Part No. CT1501 or equivalent transformers.
Note 3: Crystal manufacturer's Midland Ross Corp. NEL Unit Part No. NE·18A (C2560N)
@ 18.867 MHz.

18.867 MHz and the Viking Group of San Jose, CA Part No. VXB46NS

FIGURE 17. Translation Logic
1-11

.,..
"II:t
Cf)

co
a..

~National

Semiconductor

DP8341 IBM 3270 Protocol Receiver/Decoder
General Description

Features

The DP8341 provides complete decoding of data for· high
speed serial data communications. In specific, the DP8341
recognizes serial data that conforms to the IBM 3270 Information Display System Standard and converts it into ten
(10) bits of parallel data. Although this standard covers biphase serial data transmission over a coax line, this device
easily adapts to generalized high speed serial. data transmission on other than coax lines atfrequencles either higher or lower than the IBM 3270 standard.

_ DP8341 receivers ten (10) bit data bytes and conforms
to the IBM 3270 Interface Display System Standard
_ Separate receiver and transmitter provide maximum
system design flexibility
iii Even parity detection
_ High sensitivity input on receiver easily interfaces to
coax line
II Standard TTL data input on receiver provides generalized transmission line interface and also provides
hysteresis
• Data holding register
• Multi-byte or single byte transfers
_0 TRI-STATE receiver data outputs provide flexibility for
common or separated transmit/receive data bus
operation
.
_ Data transmission error detection or receiver provides
for both error detection and error type definition
_ Bi-polar technology provides TTL input/output compatibility with excellent drive characteristics
_ Single + 5V power supply operation

The DP8341 receiver and· its complementary chip, the
DP8340 transmitter, are designed to provide maximum flexibility in system designs. The separation of transmitter and
receiver functions allows addition of more receivers at one
end of the biphase line without the necessity of adding unused transmitters. This is advantageous specifically in control units where typically biphase data is multiplexed over
many biphase lines and the number of receivers generally
outnumber the number of transmitters. Tile separation of
transmitter and receiver function provides an additional advantage in flexibility of data bus. organization. The data bus
outputs of the receiver are TRI-STATE®, thus enabling the
bus configuration to be organized as either a common transmit/receive (bi-directional) bus or as separate transmit and
receive busses for higher speed.

Connection Diagram
Dual-ln-L1ne Package
RECEIVER DISABLE

VCC

+AMPlIFIER INPUT

0011

-AMPLIFIER INPUT

0010

DATA (TTL)

DOg

DATA CONTROL

D08

CLOCK

007

RECEIVER ACTIVE

006

ERROR

DOS

D04

DATA AVAILABLE

003

OUTPUT CONTROL
GNO

002
12

OUTPUT ENABLE
TLlF/5238-2

Top View
Order Number DP8341N
See NS Package Number N24A
FIGURE 1

1-12

Block Diagram

1-------------. :mJ~EII

CLOCK - - - - - - - - - ,

CON~:J~ - - - - - - - ,

AMPLIFIER
(INPUT)
IIEOISTEII

mil

DATA
AVAILABLE

R~fll~t~ ------....--~I

OUTPUT
ENABLE

ERROR OUTPUT

PARALLEL OUTPUT DATA
TL/F/5238-3

FIGURE 2. DP8341 Serial BI-Phase Receiver/Decoder Block Diagram

Block Diagram Functional Description
Figure 2 is a block diagram of the DP8341. This chip is

register and the holding register are full a Data Overflow
Error will be detected, terminating the message. Data is
read from the holding register through the TRI-STATE Output Buffers. The Output Enable input is the TRI-STATE control for these outputs and the Register Read input signals
the receiver that the read has been completed.

essentially a serial in/parallel out shift register. However,
the serial input data must conform to a very specific format
(see Figures 3-5). The message will not be recognized unless the format of the starting sequence is. correct. Deviations from the format in the data, sync bit, parity or ending
sequence will cause an error to be detected, terminating the
message.
Data enters the receiver through the differential input amplifier or the TTL Data input. The differential amplifier is a high
sensitivity input which may be used by connecting it directly
to a transformer coupled coax line, or other transmission
medium. The TTL Data input provides 400 mV of hysteresis
and recognizes TTL logic levels. The data then enters the
demodulation block.

When the receiver detects an ending sequence the Receiver Active output will be reset to a logic "a" indicating the
message has been terminated. A message will also termi~
nate when an error is detected. The Receiver Active output
used in conjunction with the Error output allows quick response to the transmitting unit when an error free message
has been received.
The Error Detection and Identification block insures that valid data reaches the outputs of the receiver. Detection of an
error sets the Error output to a logic "1" and resets the
Receiver Active output to a logic "0" terminating the message. The error type may be read from the data bus outputs
by setting the Output Control input to logic "0" and enabling
the TRI-STATE outputs. The data bit outputs have assigned
error definitions (see error code definition table). The Error
output will return to a logic "a" when the next starting sequence is received, or when the error is read (Output Control to logiC "a" and a Register Read performed).

The data demodulation block samples the data at eight (8)
times the data rate and provides signals for detecting the
starting sequence, ending sequence, and errors. Detection
of the starting sequence sets the Receiver Active output
high and enables the input shift register.
As the ten bits of data are shifted into the shift register, the
receiver will verify that even parity is maintained on the data
bits and the sync bit. After one complete data byte is received, the contents of the input shift register is parallel
loaded to the holding register, assuming the holding register
is empty, and the Data Available output is set. If the holding
register is full, this load will be delayed until that register has
been read. If another data byte is received when the shift

The Receiver Disable input is used to disable both the amplifier and TTL Data receiver inputs. It will typically be connected directly to the Transmitter Active output of the
DP8340 transmitter circuit (see Figure 12).

1-13

Detailed Functional Pin Description
RECEIVER

DP8340 transmitter also operates at this frequency. The
Clock Output of the transmitter is designed to directly drive
the receiver's Clock Input. In addition, the receiver is designed to operate correctly to a data bit rate of 3.5 MHz.

~ISABlE

This input is used 'to disable the receiver's data inputs: The
Receiver Disable input will typically be connected to the
Transmitter Active output of the DP8340. However, at the
system controller it is necessary for both the transmitter and
receiver to be active at the same time in the loop-back
check condition. This variation· can be' accomplished with
the addition of minimal external ,logic.

,RECEIVER ACTIVE
l

Truth Table
Recelver'Disable

Logic

Data Inputs

~~O"

Active

Logic "1"

Disabled

The purpose of this output is to inform the external system
when the DP8341 is in the process of receiving a message.
This output will transition to a logic "1" state after the receipt of a valid starting sequence and transition to logic "0"
when a valid ending sequence is received or an error is
detected. This output combined with the Error output will
.info~m the operating system of the end of an error free data
transmission.
ERROR
The Error output transitions to a logic "1" when an error is
detected. Detection of an error causes the Receiver Active
and the Data Available outputs to transition to a logic "0".
The Error output returns to a logic "0" after the error register has been read or when the next starting sequence is
detected.

AMPLIFIER I~~UTS
The receiver i1asa differential input amplifier which may be
directly connected to the transformer coupled coax line. The
amplifier may also be connected, to, a differential type TTL
line. The ampUfier has 20 mV of hysteresis.

DATA INPUT'

This input can be used either as an alternate data input or
as a power-up check input. If the system designer prefers to
use his own amplifier, instead of the one provided on the'
receiver, then this TTL input may be used. Using this pin as
an alternate data input allows self-test of the peripheral system without disturbing the transmission line.

The Register Read input when driven to the logic "0" state
signals the receiver that data in the holding register is being
read by the external operating system. The data present in
the holding register will continue to remain valid until the
Register Read input returns to the logic "1" condition. At
this time, if an additional byte is present in the input shift
register it will be transferred to the holding register, otherwise the data will remain valid in the holding register. The
Data Available output will be in the logic "0" state for a
short interval while a new byte is transferred to the holding
register after a register read.
' ,

DATA CONTROL

This input is the control pin that selects which of 'the inputs
,are used f?r ,data: entry to th~ receiver.
'
, 'Truth Table
.

Data Control

Logic'~O"

L09ic"1"

DATA AVAILABLE

Oats input To

This output indicates the existence of a data byte within the
output holding register; It niay also indicate the presence of
a data byte in both the holding register and the input shift
register. This output will transition to the logic "1" state as
soon as data is available and return to the logic "0" state
after each data byte has been read. However, even after the
last data byte has been read and the Data Available output
has assumed the logic "0" state, the last data byte read
from the holding register will remain until new data has been
received.

Data Input
Amplifier Inputs

Note:This input is also used for testing, When the input voltage is raised to
7.5V the chip resets.

CLOCK INPUT
The input is the internal clock of the receiver. It must be set
at eight(8) times the line data bit rate. For the IBM 3270
Standard. this frequency is 18.87 MHz or a data bit rate of
2.358 MHz; The crystal-controlled oscillator provided in the

1-14

Detailed Functional Pin Description

(Continued)
fined in the table below. The Output Control input is the
multiplexer control for the Data/Error bits.

OUTPUT CONTROL
The Output Control input determines the type of information
appearing at the data outputs. In the logic "1" state data will
appear, in the logic "0" state error codes are present.

Error Code Definition
Error Type

Data Bit

Truth Table

Data Overflow (Byte not
removed from holding register
when it and the input shift
register are both full and new
data is received)

002

Output Control

Data Outputs

Logic "0"

Error Codes

Logic "1"

Data

OUTPUT ENABLE
The Output Enable input controls the state of the
TRI·STATE Data outputs.

003

Parity Error (Odd parity detected)

004

Transmit Check conditions
(existence of errors on any or all
of the following data bits: 003,
005, and 006

005

An invalid ending sequence

006

Loss of mid·bit transition
detected at other than normal
ending sequence time

007

New starting sequence detected
before data byte in holding
register has been read

008

Receiver disabled during
receiver active mode

Truth Table
Output Enable

TRI-STATE
Data Outputs

Logic "0"

Disabled

Logic "1"

Active

DATA OUTPUTS
The DP8341 has a ten (10) bit TRI·STATE data bus. Seven
bits are multiplexed with error bits. The error bits are de·

Message Format
Single Byte Transmission

TRANSMISSION
START

TRANSMISSION
TERMINATION

Multi-Byte Transmission
SYNC BIT
BYTE 2

PARITY
BYTE X

TL/F/5238-4

FIGURE 3. IBM 3270 Message Format

III
I

1·15

a..

r----------------------------------------------------------------------------------------------,
Message Format (Continued)

DATA

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _ _..1

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J
AVAILABLE

FIGURE 4a. Single Byte Message

DATA~~~~~
LINE QUIESCE

CODE
VIOLATION r - 1 S 1 BYTE

- I I- - 2nd BYTE -

•••

Ir---- LAST BYTE -

ENDING 1
SEQUENCE

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _--1

--InL.____. .r···
.

DATA _ _ _ _ _ _ _ _ _ _ _ _ _
AVAILABLE

•

-------------------U
TLlF/5238-6

FIGURE 4b. Multi-Byte Message

DATA

LINE QUIESCE

VIOCL~~~ON I-

LERROR DETECTED
CORRECT DATA BYTE - - -..... 1

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _---'

DATA _____________________________...J
AVAILABLE

ERROR

--------------------------------_....

OUTPUT
CONTROL
TLlF/5238-7

FIGURE 5. Message with Error

1-16

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee

Maximum Power Dissipation· at 25·C
Dual-In-Line Package

Input Voltage

Operating Conditions

+5.5V

Output Voltage

5.25V

Storage Temperature Range

Electrical Characteristics
Symbol

Supply Voltage, (Vee>

- 65°C to + 150·C

Lead Temperature (Soldering, 10 seconds)

.2237mW

·Derate Dual·ln·Une package 17.9 mW/,C above 2SoC.

Min

Max

4.75

5.25

+70

·c

Ambient Temperature, (TA)

300·C
(Notes 2,3, and 5)

Parameter

Conditions

Typ

Min

VIH

Input High Level

VIL

Input Low Level

VIH-VIL

Data Input Hysteresis (TTL, Pin 4)

VeLAMP

Input Clamp Voltage

liN = -12 rnA

IIH

Logic "1" Input Current

Vee = 5.25V, VIN = 5.25V

IlL

Logic "0" Input Current

Vee = 5.25V, VIN = 0.5V

VOH

Logic "1" Output Voltage

10H = -100}-LA

3.2

3.9

10H = -1 rnA

2.5

3.2

Max

Units

0.8

2.0

"a" Output Voltage

2.0

VOL

Logic

los

Output Short Circuit Current

Vee = 5V, Your = OV
(Note 4)

loz

TRI-STATE Output Current

AHYS

Amplifier Input Hysteresis

Icc

Power Supply Current

Units

0.4

-0.8

-1.2

}-LA

-20

-250

}-LA
V
V

0.35

0.5

-10

...,;20

-100

rnA

Vee = 5.25V, Vo = 2.5V

-40

+40

}-LA

Vee = 5.25V, Vo = 0.5V

-40

-5

+40

}-LA

10L = 5mA

160

250

rnA

5
Vee = 5.25V

Timing Characteristics (Notes 2,6,7, and 8)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

T01

Output Data to Data Available
Positive Edge

T02

T03

Error Positive Edge to Data Available
Negative Edge

30.

T04

Error Positive Edge to Receiver Active
Negative Edge

T05

T06

Delay from Output Control to Error Bits
from Data Bits

T07

Delay from Output Control to Data Bits .
from Error Bits

T08

First Sync Bit Positive Edge to Receiver
Active Positive Edge

3.5 x T
+70

1-17

Timing Characteristics
Symbol
T09

(Notes

2,6,7, and 8) (Continued)
Conditions

Parameter

Min

Max

Typ

Receiver Active Positive Edge to First Data

Units

92 x T

11.5 x T
+ 50

TpW2

TpW3

Data Available Logic

-5

Available Positive Edge
T010

Negative Edge of Ending Sequence to
Receiver Active Negative Edge

tOl1

Data Control Set-Up Multiplexer Time Prior
to Receiving Data through Selected Input

TpW1

"0" State between

Data Bytes
Ts

Output Control Set-Up Time Prior to
Register Read Negative Edge

Output Control Hold Time After the
Register Read Positive Edge

TZE

"1" or
"0" from High Impedance State

Load Circuit

Delay from Output Enable to High Imped-

Load Circuit

Delay from Output Enable to Logic
Logic

Tez

ance State from Logic
FMAX

"1" or Logic "0"

Data Bit Frequency (Clock Input must be

(Note

3.5

MBits/s

8 x the Data Bit Frequency)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min.lmax. limits apply across the O·C to +70·C temperature range and the 4.7SV to S.2SV power supply range. All typical
values are for TA = 2S·C and Vee = S.OV.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max. or min. are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Input characteristics do not apply to amplifier inputs (pins 2 and 3).
Note 6: Unless otherwise specified, all AC measurements are referenced to the 1.SV level of the input to the I.SV level of the output and load circuit 1 is used.
Note 7: AC tests are done with input pulses supplied by generators having the following characteristics:

ZOUT

son and Tr

S ns, Tf

S ns.

Note 8: T = I/(clock input frequency). units for "T" should be ns.
Note 9: 28 MHz clock frequency corresponds to 3.7S% iitter when referenced to Figure 10.

vee

Vee

.......

Rl=2k

---I""
-::- ---=
l'~~'

1"., :

1"""'11

-::-

~,.

-F-

R2=2k ~,

I ·

~,
V

Load Circuit

........

..:~ R1=1k

-I-

~~
~

TLlF/523B-B

Load Circuit 2
FIGURE

6. Test Load Circuits

1-18

Timing Waveforms

~'.5V

OUTPUT - - " ' , 5V
ENABLE
~

Og3T~8~~ ------<

TEl

(OUTPUT CONTROL HI)

DATA _ _ _ _ _ _ _
AVAILABLE

I- TOI
..J)(llr------"""\~~
1\

-----------------

jlPw11V

T02
r --------------------

------------------------------""'\'X

READ

TL/F/5238-9

FIGURE 7. Data Sequence Timing

DATA
AVAILABLE

I-TD3~

RECEIVER
ACTIVE

-TD4-1

ERROR

--I

~Tpw2-l-lH-1

OUTPUT
CONTROL

105

~TD6-1

'-TDT-I

DATA BITS

D02-DOS

ERROR BITS

DATA BITS
TL/F/5238-10

FIGURE 8. Error Sequence Timing

I I I I
1

VIJ&~~ON

I I
1

I I I I

DATA

MCV

~---r22~--J1J
-I

I-TDB

I-TD1D1

RECEIVER _ _ _ _ _ _ _ _ _ _ _ _ _....~~2--------.~_ _ __
ACTIVE
•
-

I-TD9--1
DATA
AVAILABLE

r-----------

----------------------------------i2~

TL/F/5238-11

FIGURE 9. Message Timing

1-19

.,..
~

~
D-

Timing Waveforms (Continued)

4T±(T-25nl)-

CLOCK

INPU~ FREQUENCY

-------lo3:t:rN. VIN+

-----,I-----Il----I-----I~----,f--- VIN-

_ _ _ _ -40 mV MIN. VIN+

-1.3V MAX.

TLlF/5238-12

FIGURE 10. Data Waveform Constraints: Amplifier Inputs

Note:

ITr - T,l :s:

CLOCK

INPU~ FREQUENCY

TLlF/5238-13

10 ns

. FIGURE 11. Data Waveform Constraints: Data Input (TTL)

1·20

Typical Applications

tARITY CONTROL

I
I
I

AUTO RESPONSE
OP834D
TRANSMITTER!
ENCOOER

REG LOAO

REG FULL

I
I
I

RECEIVER
DISABLE
DATA
AVAILABLE

ERROR

1:;

OUTPUT CONTROL

Ii;

G62AIU
COAX

1·

TRANSMITTER
ACTIVE

+IN
DP8341
RECEIVER!
DECODER

OUTPUT ENABLE

1:1:1 PULSE
TRANSFORMER
FIG.14

BI·PHASE
INPUT
-IN

REG READ

RECEIVER ACTIVE
TLlF/5238-14

Note 3: Crystal manufacturers: Midland Ross Corp.
NEl Unit Part No. NE18A (C2560N)

The Viking Group Part No. VXB-46NS

18.867 MHz
@

18,867 MHz. located in San Jose, CA.

FIGURE 12. Typical Application for IBM 3270 Interface
VCC-------o----~~----------o--

VIN+

VIN-

---------01---.....J
TL/F/5238-15

FIGURE 13. Equivalent Circuit for DP8341 Input Amplifier

..
1-21

Typical Applications

(Continued)

150
DATA
DELAY

TRANSMITIER
ACTIVE

2150 Cll":::J:·

- -

~ 8" - -1

~
R6
120

90Q COAX
(RG62A/U)

DP8341

mam
-IN 6

GND
TL/F/5238-16
Note 1: Resistance values are in

±5%,

Y.W

Note 2: T1 is a 1:1:1 pulse transformer, LMIN = 500 p.H for 16 MHz system clock
Pulse Engineering Part No. 5762/Surface Mount, 5762M/PE-65762
Valor Electronics Part No. CT1501
Technitrol Part No. 11 LHA or equivalent transformers

FIGURE 14. Translation Logic

IDEAL
WAVEFORM
AT TRANSMITTER
END OF CABLE

TL/F/5238-17
°To maintain loss at 95% of ideal signal, select transformer inductance
such that:
4MIN) = 10,000
fCLK

fCLK

Note 1: Less inductance will cause greater amplitude attenuation

System Clock
Frequency
(e.g., 16.67 MHz)

Note 2: Greater inductance may decrease signal
rise time slightly and increase ringing, but these
effects are generally negligible.

EXAMPLE:
L

= ~6
16.67 x 10

-+ L(MIN)

= 530p.H

FIGURE 15. Transformer Selection

1-22

~National

Semiconductor

DP8342 High-Speed 8-Bit Serial Transmitter/Encoder
General Description

Features

The DP8342 generates a complete encoding of parallel
data for high speed serial transmission. It generates a five
bit starting sequence, three bit code violation, followed by a
syn bit and eight bit per byte of data plus a parity bit. A
three-bit ending code signals the termination of the transmission. The DP8342 adapts to generalized high speed serial data transmission as well as the coax lines at a maximum
data rate of 3.5 MHz.

III Eight bits per data byte transmission

The DP8342 and its complementary chip, the DP8343 (receiver/decoder) have been designed to provide maximum
flexibility in system designs. The separation of the transmitter receiver functions provides convenient addition of more
receivers at one end of a biphase line without the need of
unused transmitters. This is specifically advantageous in
control units where typical biphase data is multiplexed over
many biphase lines and the number of receivers generally
exceeds the number of transmitters.

• Single-byte or multi-byte transmission
• Internal parity generation (even or odd)
• Internal crystal controlled oscillator used for the generation of all required chip timing frequencies
• Clock output directly drives receiver (DP8343) clock input
• Input data hold register
• Automatic clear status response feature
• Line drivers at data outputs provide easy interface to
bi-phase coax line or general transmission media

• <2 ns driver output skew
• Bipolar technology provides TTL input/output compatibility
• Data outputs power up/down glitch free
• Internal power up clear and reset
• Single + 5V power supply

Connection Diagram
Dual-In-Line Package
OUTPUT ENABLE

BYTE CLK

iiEiITiOOi

BIT 8

REG FULL

VCC

BIT7

AUTO RESPONSE

BITS

TRANSMITIER ACTIVE

BIT5

RESET

BIU

EVEN/ODD

BIT3

DATA OUT

BIT 2

DATA OUT

BIT 1

DATA DELAY

CLKOUT

GND

.,'

',.:

I:,

TL/F/5236-1

FIGURE 1
Order Number DP8342N
See NS Package Number N24A

•
1-23

Block Diagram
CLOCK
OUTPUT

TRANSMITIER
ACTIVE

CRYSTAL
OSCILLATOR

CONTROL LOGIC

EVEN/ImD
PARITY

...'\I\,..,.......... X2
EXTERNAL
CRYSTAL c::J

-C--4-X1
I

......-----'

BYTE CLOCK
DATA

DATA
DELAY

OUTPUT ENABLE

BITS
BIT 1 TO BIT B
DATA INPUTS

REGISTERS
FULL

TL/F/5236-2

FIGURE 2

Functional Description
Figure 2 is a block diagram of the OP8342 Biphase Trans-

the Reset and Output-TRI-STATE® capability. Another feature of the OP8342 is the Byte Clock output which keeps
track of the number of bytes transferred.
The transmitter/encoder is also capable of internal TI / AR
(Transmission Turnaround/ Auto Response). When the
Auto-Response (AR) input is forced to the logic "0" state,
the transmitter/encoder responds with clean status (all zeros on data bits).
Operation of the transmitter/encoder is automatic. After the
first data byte is loaded, the Transmitter Active output is set
and the transmitter/encoder immediately formats the input
data and serially shifts it out its data outputs. If the message
is a mutli-byte message, the internal format logic will modify
the message data format for multibyte as long as the next
byte is loaded to the input holding format logic will modify
the message data format for multibyte as long as the next
byte is loaded to the input holding register before the last
data bit of the previous data byte is transferred out of the
internal output shift register. After all data is shifted out of
the transmitter/encoder the Transmitter Active output will
return to the inactive state.

mitter/Encoder. The transmitter/encoder contains a crystal
oscillator whose input is a crystal with a frequency eight (8)
times the data rate. A Clock Output is provided to drive the
DPB342 receiver/decoder Clock Input and other system
components at the oscillator frequency. Additionally, the oscillator drives the control logic and output shift register/
format logic blocks.
Data is parallel loaded from the system data bus to the
transmitter/encoder's input holding register. This data is in
tum loaded by the transmitter/encoder to its output shift
register if this register was empty at the time of the load.
During this load, message formatting and parity are generated. The formatted message is then shifted out at the bit rate
frequency to the TIL to Biphase block which generates the
proper data bit formatting. The data outputs, OATA, OATA,
and OATA OELAY provide for flexible interface to the transmission medium with little or no external components.
The control Logic block interfaces to all blocks to insure
proper chip operation and sequencing. It controls the type
of parity generation through the Even/Odd Parity input. An
additional feature provided by the transmitter/encoder is

1-24

Detailed Pin/Functional Description
CRYSTAL INPUTS Xl AND X2

TRANSMITTER ACTIVE

The oscillator is controlled by an external, parallel resonant
crystal connected between the Xl and X2 pins. Normally, a
fundamental mode crystal is used to determine the operating frequency of the oscillator; however, over-tone mode
crystals may be used.

This output will be in the logic "1" state while the transmitter/encoder is about to transmit or is in the process of transmitting data. Otherwise, it will assume the logic "0" state
indicating no data presently in ,either the input holding or
, output shift registers.
.

CRYSTAL SPECIFICATIONS (PARALLEL RESONANn

Type

The Register Load input is used to load data from the Data
Inputs to the input holding register. The loading function is
level sensitive, the data present during the logic "0" state of
this input is loaded, and the input data must be valid before
the logic "0" to logic "1" transition. It is after this transition
that the transmitter/encoder begins formatting of data for
serial transmission.

<20 MHz AT-cut
or> 20 MHz BT-cut

Tolerance

0.005% at 25°C

Stability

0.01 % from O°C to

Resonance

+ 70°C

Fundamental (Parallel)

Maximum Series Resistance

Dependent on Frequency
(For 20 MHz, 50n) ,

Load Capacitance

AUTO RESPONSE (TT/AR)

15 pF

This input provides for automatic clear data transmission (all
bits in logic "0") without the need of loading all zero's.
When a logic "0" is forced on this input the transmitter/encoder immediately responds with' transmission ., of" ~'clean
status". When this input is in the logic "1" state the transmitter/encoder transmits data entered on the Data Inputs.

Connection Diagram
R
TOPIN
PIN(14)
22 --'""''''
y'n

I'L-..
C

Vcc

c:::=J CRYSTAL

EVEN/ODD PARITY

___.T... (FIG. 18)
TO PIN Xl ...
_
PIN (13)

This input sets the internal logic of the DP8342 transmitter/
encoder to generate either even or odd parity for the data
byte in the bit 10 position. When this pin is in the logic "0"
state odd paritY is generated. In the logic "1" state even
parity is generated. This feature is useful when the control
unit is performing a loop back check and at the same time
the controller wishes to verify proper data transmission with
its receiver/decoder.

TL/F/5236-3

Freq

10 MHz-20 MHz 500n 30pF
>20 MHz

120n 15 pF

SERIAL OUTPUTS-DATA, DATA, AND DATA DELAY

If the DP8342 transmitter is clocked by a system clock
(crystal oscillator not used), pin 13 (Xl input) should be
clock directly using a Schottky series (74S) circuit. Pin 14
(X2 input) may be left open. The clocking frequency must be
set at eight times the data bit rate. Maximum input frequency is 28 MHz.

These three output pins provide for convenient application
of data to the Bi-Phase transmission line. The Data outputs
are a direct bit representation of the Biphase data while the
Data Delay output provides the necessary increment to
clearly define the four (4) DC levels of the pulse. The DATA
and DATA outputs add flexibility to the DP8342 transmitter/
encoder for use in high speed differential line driving applications. The typical DATA to DATA skew is 2 ns.

CLOCK OUTPUT
The Clock Output is a buffered output derived directly from
the crystal oscillator block and clocks at the oscillator frequency. It is designed to directly drive the DP8343 receiver/
decoder Clock Input as well as other system components.

RESET
When a logic "0" is forced on this input, all outputs except
Clock Output are latched low.

REGISTERS FULL

, OUTPUT ENABLE

When a logic "0" is forced on this input the three serial data
outputs are in the high impedence state.
BYTE CLOCK

This pin registers p~lse at the end of each byte transmission. The number of pulses registered corresponds to the
number of bytes transmitted.

•
1-25

~
~

a.
C

r---------------------------------------------------------------------------------------~

Message Format
Single Byte Transmission

TRANSMISSION
TERMINATION

TRANSMISSION
START

Multi-Byte Transmission
SYNC BIT

PARITY

BYTE 2

BYTE X

TL/F/5236-4

FIGURE 3

Functional Timing Waveforms
IIEU"t1mI

--u
L

REG FULL

--I1---------------r
-:-I____________-..?,

BYTECLOCK _ _

Dm_~1
DATA

II
I I

DATA DELAY

~
'

I' I' I' I' Ic..".LAn~icl·,

BIT

""---_._--"1-.

STARTING SEQUENCE

TL/F/5236-5

FIGURE 4. Overall Timing Waveforms for Single Byte

~~
I I

DATA DELAY

I' I' 11 11 I

I I

II~~

DATA

CODE VIOLATION

mci Of ,lsi~Ji

ilD I J

BIT2?PARITY BlmPARITY
ENDING
~ ~ SEQUENCE

STARTING SEQUENCE

8 BIT + PARITY 8 BIT + PARITY
TLlF/5236-6

FIGURE 5. Overall Timing Waveforms for Multi-Byte

1-26

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Maximum Power Dissipation· at 25·C
Cavity Package
Dual·ln-Line package

Supply Voltage, Vee

°Derate cavity package 14.9 mWrC above 2SoC; derate dual in line package 20 mW rc above 2SoC.

Input Voltage

5.5V

Output Voltage

5.25V

Storage Temperature Range

Operating Conditions

- 65·C to + 150·C

lead Temperature (Soldering, 10 sec.)

2237mW
2500mW

300·C

Supply Voltage, (Vee>

Min
4.75

Max
5.25

+70

Ambient Temperature, T A

Units
V
·C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

VIH

logic "1" Input Voltage (A" Inputs Except X1 and X2)

VIL

logic "0" Input Voltage (A" Inputs Except X1 and X2)

Vee

VeLAMP

Input Clamp Voltage (A" Inputs Except X1 and X2)

liN

IIH

logic "1"
Input Current

A" Others Except X1 and X2

logic "0"
Input Current

A" Inputs Except X1 and X2

IlL

=
=

Vee

Typ

Min

Max

Units

2.0

V
0.8

-0.8

-1.2

Vee = 5.25V
VIN = 5.25V

0.3

120

p.A

0.1

p.A

Vee = 5.25V
VIN = 0.5V

-15

-300

p.A

-5

-100

p.A

-12 rnA

VOH1

logic "1" A" Outputs Except ClK OUT,
DATA, DATA, and DATA DELAY

10H = -100 p.A
Vee = 4.75V

VOH2

logic "1" forClK OUT, DATA,
DATA, and DATA DELAY Outputs

VOL1

logic "0" A" Outputs Except ClK OUT,
DATA, DATA, and DATA DELAY

= -1 rnA
Vee = 4.75V
10H = -10 rnA
Vee = 4.75V
10H

3.2

3.9

2.5

3.4

2.6

3.0

0.35

0.5

0.4

0.6

-10

-30

-100

rnA

10L = 5 rnA

VOL2

logic "0" for ClK OUT, DATA
DATA, and DATA DELAY Outputs

Vee = 4.75V
10L = 20 rnA

1051

Output Short Circuit Current for A" Except
ClK OUT, DATA, DATA, and DATA
DELAY Outputs

(Note 5)
VOUT = OV

1052

Output Short Circuit Current DATA,
DATA, and DATA DELAY Outputs

(Note 5)
VOUT = OV

-50

-140

-350

rnA

1053

Output Short Circuit Current for ClK OUT

(Note 5)
VOUT = OV

-30

-90

-200

rnA

Icc

Power Supply Current

Vee

170

250

rnA

Timing Characteristics Vee =
Symbol

5V ± 5%, T A

5.25V

O·C to 70·C, Oscillator Frequency

28 MHz (Notes 2 and 3)

Parameter

Conditions

Typ

Max

Units

tpd1

REG lOAD to Transmitter Active (TA)
Positive Edge

load Circuit 1
Figure 6

tpd2

REG lOAD to Register Fu";
Positive Edge

load Circuit 1
Figure 6

tpd3

T A to Register Fu";
Negative Edge

load Circuit 1
Figure 6

tpd4

Positive Edge of REG lOAD to
Positive Edge of DATA

load Circuit 2
Figure 9

tpd5

REG lOAD to DATA;
Positive Edge

load Circuit 2
Figure 9

280

380

tpd6

REG lOAD to DATA DELAY;
Positive Edge

load Circuit 2
Figure 9

150

240

1-27

Min

•

Timing Characteristics (Continued)
Vee

5V ± 5%, TA

O·C to 70·C, Oscillator Frequency

28 MHz (Notes 2 and 3)
Typ

Max

Units

tpd7

Positive Edge of DATA to Negative Edge
of DATA DELAY

load Circuit 2
Figure 9

tpd8

Positive Edge of DATA DELAY to Negative
Edge of DATA

load Circuit 2
Figure 9

tpd9.
t pd10

Skew between DATA and DATA

load Circuit 2
Figure 9

tpd11

Negative Edge of Auto Response (AR)
to Positive Edge of T A

load Circuit 1
Figure 10

100

tpd12

Maximum Time Delay to load Second Byte
after Positive Edge of REG FUll

load Circuit 1
Figure 8, (Note 7)

4xT-50

tpd13

X1 to ClK OUT; Positive Edge

load Circuit 2
Figure 11

tpd14

X1 to ClK OUT; Negative Edge

load Circuit 2
Figure 11

tpd15

Negative Edge of AR to Positive Edge of
REG FUll

load Circuit 1
Figure 10

tpd16

Skew betWeen TA and REG FUll during
Auto Response

load Circuit 1
Figure 10

tpd17

REG lOAD to REG FUll; P~sitive Edge
for Second Byte

load Circuit 1
Figure 7

tpd18

REG FULL to BYTE ClK; Negative Edge

load Circuit 1
Figure 7

t pd19 .

REG FUll to BYTE ClK; Positive Edge

load Circuit 1
Figure 7

145

180

tZH

Output Enable to DATA, DATA, or DATA
DELAY outputs: HiZ to High

Cl = 50pF
Figures 16, 17

tZL

Output Enable to DATA. DATA, or DATA
DELAY Outputs; HiZ to High

Cl = 50pF
Figures 16, 17

tHZ

Output Enable to DATA, DATA, or DATA
DELAY Outputs; High to HiZ

Cl = 15 pF
Figures 16, 17

100

tLZ

Output Enable to DATA. DATA, or DATA
DELAY Outputs; low to HiZ

Cl = 15 pF
Figures 16, 17

tpw1

REG lOAD Pulse Width

Figure 12

tpW2

First REG FUll Pulse Width (Note 6)

load Circuit 1
Figure 7, (Note 7)

tpw3

REG FUll Pulse Width Prior to Ending
. Sequence (Note 6)

Symbol

tpw4
tpu5
ts

Parameter

' Pulse Width for Auto Response
Pulse Width for BYTE ClK
Data Setup Time prior to REG lOAD
. Positive Edge; Hold Time = 0 ns

Conditions

Min

40
8 x T

load Circuit 1
Figure 7
Figure 10
Load Circuit 1
Figure 7, (Note 7)
'Figure 12

+ 60

8 x T

+ 100

5xB

ns
ns

ns
8 x T

+ 30

8 x T

+ 80

trl

Rise Time for DATA, DATA, and DATA
DELAY Output Waveform

Load Circuit 2
Figure 13

ttl

Fall Time for DATA, DATA, and DATA
DELAY Output Waveform

Load Circuit 2
Figure 13

tr2

Rise Time f6rTA and REG FUll

load Circuit 1
Figure 14

tt2

Fall Time for TA and REG FUll

load Circuit 1
Figure 14

1-28

...

Timing Characteristics (Continued)
Vee

= 5V ± 5%, T A = O·C to 70·C, Oscillator Frequency = 28 MHz (Notes 2 and 3)

Symbol

Parameter

Min

Conditions

Data Rate Frequency
(Clock Input must be 8 x this Frequency)

Typ

Input Capacitance-Any Input

(Note 4)

Max

Units

3.5

Mbits/s

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

+ 70'C temperature range

Note 2: Unless otherwise specified, minImax limits apply across the O'C to
values are for TA = 2S'C and Vee = S.OV.

and the 4.7SV to S.2SV power supply range. All typical

Note 3: All currents Into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute basis.
Note 4: Input capacitance Is guaranteed by periodic testing. fTEST

10 kHz at 300 mV, TA

= 2S'C.

Note 5: Only one output should be shorted at a time.
Note 6: T = 1/(Oscillator Frequency). Unit for T should be in ns. B = ST.
Note 7: Oscillator Frequency Dependent.

Timing Waveforms

(Continued)

4 --------------~:):~--------~~~::

RmDlD\

f'~'

-l
REG FULL

--50%

~
-~,
1l:$.= =~
tPd2

~tPd3~::
-

50%

VOL

tpw3

BYTE CLOCK

TL/F/5236-7

FIGURE 6. Single Byte Transfer

}

-I
REO FULL

P
_d1_ _~- -_I;. . -(?-~2·~2~~~~~~~~~~~::::~~~~~~~~~~~~~-~~~50~%--~ :

_ _t

. ~tpd2

______,
-

VOL

tpd17

lr(~

tpd3-

J,f-

-tpw2

_
tpd18-

~'f\

BYTE ClK

50%

Ipw3

-==

VoH
VoL

JEIPd111

-------------~2~JI.1
-,

50%

VoH
VoL

,--lpwS
TL/F/5236-8

FIGURE 7. Two-Byte Transfer

~1
REG FULL

\.If~

3V
I

----/}.:~~ ::
-

WINDOW
TO LOAD MUIll·BYTE DATA 1SVrxa

TL/F/5236-9

FIGURE 8. Maximum Window to Load Multi-Byte Data

1·29

Functional Timing Waveforms

(Continued)

3V
1.5V
OV

DATA

VOH
' - - _ _ _..J

VOL

: - - - - l p d 5 - - - - .1 r - -.....

VOL
VOH
DATA DELAY

VOL
TL/F/5236-10

FIGURE 9. Three Serial Outputs

,-----------~~----------------------3V

- - - - - - - - - - - - - - - - - 1.5Y

TA _ _

REG FULL

....;..--Jr'~"

__ l
__-1
...J

-",d,,15

I~'
50%

Xl~-=~~5V

';';=,,' ~I-=---:L~

YOH

-VOH
50%
VOL

elK O U T '
,

VOL

E-'Pd16 YoH

TLlF/5236-12

50%

FIGURE' 11. Clock Pulse

VOL
TL/F/5236-11

FIGURE 10. Auto-Response

10%

,
TL/F/5236-13

TL/F/5236-14

FIGURE 13. Output Waveform for DATA, DATA,
DATA DELAY (Load Circuit 2)

FIGURE 12. REG LOAD

Vee

Vee
RL=2k

RL=2k

10%

TLlF/5236-15

FIGURE 14. Rise and Fall Time Measurement
for TA and REG FULL

TL/F/5236-16

Load Circuit 1
Load Circuit 2
FIGURE 15. Test Load Circuits

1-30

Timing Waveforms (Continued)
VCC

4.7K

-=- 2.7K
TL/F/5236-17

FIGURE 16. Load Circuit for Output TRI-STATE Test

}. . ._____. .l~5-0-%-----:::

OUTPUT ENABLE

VOH
DATA OUTPUTS

I-1HZ
:.. VOH-O.5V
J VOL +O.5V

VOL

-I

I-Ill

-·1

HIGH Z

-I

-IZl
f-VOH-O.5V
r-VOl+O.5V

VOH
VOL

-IZH
TLiF/5236-1B

FIGURE 17. TRI-STATE Test

Typical Applications

I
I
I
I

RESET

II AUTO RESPONS~•
REG LOAD
REG FULL

OPTIONAL
INTERFACE
lOGIC
FIG. 19

DP8342

TRANSMITTERI
ENCODER

COAX LINE (FIG. 19)
TWISTED PAIR LINES
FIBER·DPTIC
MAGNETIC
INFRARED
RF
ULTRASONIC
AUDIO
CURRENT CARRYING

BYTE CLOCK
en
=>

TRANSMITTER
ACTIVE

....c..>

:::
~
~
~

RECEIVER
DISABLE

DATA
AVAILABLE
ERROR

I OUTPUT CONTROL
I OUTPUT ENABLE•
I

•
I REG READ
I
•
I RECEIVER ACTIVE

DP8343
RECEIVERI
DECODER

OPTIONAL
INTERFACE
LOGIC

DC TO 3.5MHz

I
I

I
TL/F/5236-19

FIGURE 18

1·31

Typical Applications

(Continued)

150
DATA
DELAY

90Q COAX
(RG62A/U)
3

~
R6

120

150

TRANSMITTER
ACTIVE

+IN

I2
I

J
•

CONNECT TO
OP8343
RECEIVER

L __ ,*S_.J

-IN

GNO
Note 1: Resistance values are In

±5%,

TLlF/5236-20

y..W.

Note 2: T1 Is a 1:1:1 pulse transformer, L = 500,...H for 18 MHz to 28 MHz system clock. Pulse Engineering Part No. 5762; Technitrol Part No. 11LHA, Valor
Electronics Part No. CT1501, or equivalent transformer.
Note 3: Crystal manufacturer Midland Ross Corp. NEL Unit Part No. NE-18A at 28 MHz.

FIGURE 19. Interface Logic for a Coax Transmission Line

r----....... (NOTE)
OATA

90QCOAX

DP8342
TRANSMITTERI
ENCODER
TA
OE
+IN

•

~
u:J
4

CONNECT TO
0P8343
RECEIVER
-IN

TL/F/5236-21

Note: Data rates up to 3.5 Mbits/s at 5000' stili apply.

FIGURE 20. Direct Interface for a Coax Transmission Line (Non-IBM Voltage Levels)

1-32

~National

Semiconductor

DP8343 High-Speed 8-Bit Serial Receiver/Decoder
General Description

Features

The DP8343 provides complete decoding of data for high
speed serial data communications. In specific, the DP8343
receiver recognizes biphase serial data sent from its complementary chip, the DP8342 transmitter, and converts it
into 8 bits of parallel data. These devices are easily adapted
to generalized high speed serial data transmission systems
that operate at bit rates up to 3.5 MHz.

The DP8343 receiver and the DP8342 transmitter are designed to provide maximum flexibility in system designs. The
separation of transmitter and receiver functions allows addition of more receivers at one end of the biphase line without
the necessity of adding unused transmitters. This is advantageous in control units where the data is typically multiplexed over many lines and the number of receivers generally exceeds the number of transmitters. The separation of
transmitter and receiver function provides an additional advantage in flexibility of data bus organization. The data bus
outputs of the receiver are TRI-STATE®, thus enabling the
bus configuration to be organized as either a common transmit/receive (bi-directional) bus or as separate transmit and
receive busses for higher speed.

III

•
•

a
II
III

•
II

DP8343 receives 8-bit data bytes
Separate receiver and transmitter provide maximum
system design flexibility
Even parity detection
High sensitivity input on receiver easily interfaces to
coax line
Standard TTL data input on receiver provides generalized transmission line interface and also provides
hysteresis
Data holding register
Multi-byte or single byte transfers
TRI-STATE receiver date outputs provide flexibility for
common or separated transmit/receive data bus
operation
Data transmission error detection on receiver provides
for both error detection and error type definition
Bipolar technology provides TTL input/output compatibility with excellent drive characteristics
Single + 5V power supply operation

Connection Diagram
Dual-In-Line Package
RECEIVER DISABLE

VCC

+AMPLIFIER INPUT

DATA CLOCK

-AMPLIFIER INPUT

SERIAL DATA

DATA (TTL)

BIT 8

DATA CONTROL

BIT7

CLOCK

BIT 6

RECEIVER ACTIVE

BIT5
BIT 4

ERROR

BIT 3

DATA AVAILABLE

BIT 2

BIT 1

OUTPUT ENABLE

OUTPUT CONTROL
GNO

TL/F/5237-1

FIGURE 1
Order Number DP8343N
See NS Package Number N24A

III
I

1-33

Block Diagram

1-------------- :mJ~ER

CLOCK - - - - - - - - - ,

CONf:~~ - - - - - -........
DATA (TTL)

SERIAL DATA

AMPLIFIER
INPUT

SERIAL DATA CLOCK

DATA
AVAILABLE

OUTPUT
CONTROL

ERROR OUTPUT

PARALLEL OUTPUT DATA
TLlF/5237-2

FIGURE 2. DP8343 Blphase Receiver

Functional Description
Figure 2 is a block diagram of the DP8343 receiver. This

been read or the start of another data byte is received, in
which case a Data Overflow Error will be detected, terminating the message. Data is read from the holding register
through the TRI-STATE Output Buffers. The Output Enable
input is the TRI-STATE control for these outputs and the
Register Read input signals the receiver that the read has
been completed.
When the receiver detects an ending sequence the Receiver Active output will be reset to a logic "0" indicating the
message has been terminated. A message will also terminate when an error is detected. The Receiver Active output
used in conjunction with the Error output allows quick response to the transmitting unit when an error free message
has been received.
The Error Detection and Identification block insures that valid data reaches the outputs of the receiver. Detection of an
error sets the Error output to a logic "1" and resets the
Receiver Active output to a logic "0" terminating the message. The error type may be read from the data bus outputs
by setting the Output Control input to logic "0" and enabling
the TRI-STATE outputs. The data bit outputs have assigned
error definitions (see error code definition table). The Error
output will return to a logic "0" when the next starting sequence is received, or when the error is read (Output Control to logic "0" and a Register Read performed).

chip is essentially a serial in/parallel out shift register. However, the serial input data must conform to a very specific
format (see Figures 3-6). The message will not be recognized unless the format of the starting sequence is correct.
Deviations from the format in the data, sync bit, parity or
ending sequence will cause an error to be detected, terminating the message.
Data enters the receiver through the differential input amplifier or the TTL Data input. The differential amplifier is a high
sensitivity input which may be used by connecting it directly
to a transformer coupled coax line, or other transmission
medium. The TTL Data input provides 400 mV of hysteresis
and recognizes TTL logic levels. The data then enters the
demodulation block.
The data demodulation block samples the data at eight (8)
times the data rate and provides signals for detecting the
starting sequence, ending sequence, and errors. Detection
of the starting sequence sets the Receiver Active output
high and enables the input shift register.
As the eight bits of data are shifted into the shift register, the
receiver will verify that even parity is maintained on the data
bits and the sync bit. Serial Data and Serial Data Clock, the
inputs to the shift register, are provided for use with external
error detecting schemes. After one complete data byte is
received, the contents of the input shift register is parallel
loaded to the holding register, assuming the holding register
is empty, and the Data Available output is set. If the holding
register is full, this load will be delayed until that register has

1-34

Detailed Functional Pin Description
RECEIVER DISABLE

ERROR

This input is used to disable the receiver's data inputs. The
Receiver Disable input will typically be connected to the
Transmitter Active output of the DP8342. However, at the
system controller it may be necessary for both the transmitter and receiver to be active at the same time. This variation
can be accomplished with the addition of minimal external
logic.
Truth Table

The Error output transitions to a logic "1" when an error is
detected. Detection of an error causes the Receiver Active
and the Data Available outputs to transition to a logic "0".
The Error output returns to a logic "0" after the error register has been read or when the next starting sequence is
detected.

Receiver Disable

REGISTER READ
The Register Read input when driven to the logic "0" state
signals the receiver that data in the holding register is being
read by the external operating system. The data present in
the holding register will continue to remain valid until the
Register Read input returns to the logic "1" condition. At
this time, if an additional byte is present in the input shift
register it will be transferred to the holding register, otherwise the data will remain valid in the holding register. The
Data Available output will be in the logic "0" state for a
short interval while a new byte is transferred to the holding
register after a register read.

Data Inputs

Logic "0"

Active

Logic "1"

Disabled

AMPLIFIER INPUTS
The receiver has a differential input amplifier which may be
directly connected to the transformer coupled coax line. The
amplifier may also be connected to a differential type TTL
line. The amplifier has 20 mV of hysteresis.
DATA INPUT

DATA AVAILABLE

This input can be used either as an alternate data input or
as a power-up check input. If the system designer prefers to
use his own amplifier, instead of the one provided on the
receiver, then this TTL input may be used. Using this pin as
an alternate data input allows self-test of the peripheral system without disturbing the transmission line.

This output indicates the existence of a data byte within the
output holding register. It may also indicate the presence of
a data byte in both the holding register and the input shift
register. This output will transition to the logic "1" state as
soon as data is available and return to the logic "0" state
after each data byte has been read. However, even after the
last data byte has been read and the Data Available output
has assumed the logic "0" state, the last data byte read
from the holding register will remain until new data has been
received.

DATA CONTROL
This input is the control pin that selects which of the inputs
are used for data entry to the receiver.
Truth Table
Data Control

Data Input To

Logic "0"

Data Input

Logic "1"

Amplifier Inputs

OUTPUT CONTROL
The Output Control input determines the type of information
appearing at the data outputs. In the logic "1" state data will
appear, in the logic "0" state error codes are present.
Truth Table

Note: This input is also used for testing. When the input voltage is raised to
7.5V the chip resets.

CLOCK INPUT
This input is the internal clock of the receiver. It must be set
at eight (8) times the line data bit rate. The crystal-controlled
oscillator provided in the DP8342 transmitter also operates
at this frequency. The Clock Output of the transmitter is
designed to directly drive the receiver's Clock Input. In addition, the receiver is designed to operate correctly to a data
bit rate of 3.5 MHz.

Output Control

Data Outputs

Logic "0"

Error Codes

Logic "1"

Data

OUTPUT ENABLE
The Output Enable input controls the state of the
TRI-STATE Data outputs.
Truth Table

RECEIVER ACTIVE
The purpose of this output is to inform the external system
when the DP8343 is in the process of receiving a message.
This output will transition to a logic "1" state after a receipt
of a valid starting sequence and transition to logic "0" when
a valid ending sequence is received or an error is detected.
This output combined with the Error output will inform the
operating system of the end of an error free data transmission.

Output Enable

TRI-STATE
Data Outputs

Logic "Oil

Disabled

Logic "1"

Active

DATA OUTPUTS
The DP8343 has an 8-bit TRI-STATE data bus. Seven bits
are multiplexed with error bits. The error bits are defined in
the following table. The Output Control input is the multiplexer control for the Data/Error bits.

1-35

•

(f)
~

Message Format

Si~gle

Byte Transmission
TRANSMISSION
START SEQUENCE

TRANSMISSION
TERMINATION

TRANSMISSION
START .'

Multi-Byte Transmission
SYNC BIT
BYTE 2

PARITY
BYTE X

TL/F/5237-3

FIGURE 3

DATA
LINE QUIESCE

BIT BIT BIT BIT BIT BIT BIT BIT
CODE
1 2 3 4 5 6 7
8
VIOLATION.
DATA
•

SYNC
RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _ _..1

ENDING

SEQUENCE

PARITY

DMA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-"'1~IL._ _ __
AVAILABLE

TL/F/5237-4

FIGURE 4a. Single Byte (8-Blt) Message

DATA~ U1.Jl.J1r rfl
LINE QUIESCE.

. I

CODE
ENDING
VIOLATION j---11t BYTE-j-2nd BYTE- ••• I-LAST BYTE- SEQUENCE

RECEIVER·
ACTIVE _ _ _ _ _ _ _ _ _--'

---InL_______r ···

DATA _ _ _ _ _ _ _ _ _ _ _ _
AVAILABLE

•

----------------U
TL/F/5237-5

FIGURE 4b. Multi-Byte Message

1-36

Message Format (Continued)
Error Code Definition
Data Bit
DP8343

Error Type
Data Overflow (Byte not removed from holding register when it and the input shift register are both full and new
data is received)

Bit 1
Bit2

Parity Error (Odd parity detected)

Bit3

Transmit Check conditions (existence of errors on any or all of the following data bits: Bit 2, Bit 4, and Bit 5)

Bit4

An invalid ending sequence

Bit5

Loss of mid-bit transition detected at other than normal ending sequence time

Bit6

New starting sequence detected before data byte in holding register has been read

Bit7

Receiver disabled during receiver active mode

SERIAL DATA

DATA CLOCK

The Serial Data output is the serial data coming into the
input shift register.

The Data Clock output is the clock to the input shift register.

DATA

LINE QUIESCE

ICODE~
VIOLATION

LERROR DETECTED

CORRECT DATA BYTE-

RECEIVER
ACTIVE

DATA
AVAILABLE

ERROR

OUTPUT
CONTROL
TL/F/5237-6

FIGURE 5. Message with Error

DATA

SERIAL
DATA

DATA
CLOCK
TLlF/5237-7

FIGURE 6. Data Clock and Serial Data

III
I

1-37

Absolute Maximum Ratings

(Note 1)
Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7.0V
Supply Voltage, (VeC>

Supply Voltage, (VeC>
Ambient Temperature, T A

5.25V

Output Voltage

300°C

Operating Conditions

5.5V

Input Voltage

- 65°C to + 150°C

Lead Temperature (Soldering, 10 sec.)

Min
4.75
0

Max
5.25
+70

Unlt$
V
°C

Max

Units

0.8

-1.2

Electrical Characteristics (Notes 2, 3 and 5)
Symbol

Parameter

VIH

Input High Level

Vil

Input Low Level

Conditions

Min

Typ

2.0

VIH"Vll

Data Input Hysteresis (TTL, Pin 4)

VeLAMP

Input Clamp Voltage

0.2

0.4
-0.8

liN = -12 mA

IIH

Logic "1" Input Current

Vee = 5.25V, VIN = 5.25V

/LA

III

Logic "0" Input Current

Vee = 5.25V, VIN = 0.5V

-20'

-250

/LA

VOH

Logic "1" Output Voltage

IOH = -100/LA

3.2

3.9

IOH = -1 mA

2.5

3.2

VOL

. Logic "0" Output Voltage

0.35

0.5

-20

-100

-40

+40

/LA

-40

-5

+40

/LA

160

250

IOl = 5 mA

los

Output Short Circuit Current

Vee = 5V, VOUT = OV
(Note 4)

-10

10Z

TRI-STATE Output Current

Vee = 5.25V, Vo = 2.5V
Vee = 5.25V, Vo = 0.5V

AHYS

Amplifier Input Hysteresis

Icc

Power Supply Current

Vee = 5.25V

Timing Characteristics (Notes 2,6,7, and 8)
Min

Typ

Max

Units

T01

Output Data to Data Available
Positive Edge

T02

T03

Error Positive Edge to
Data Available Negative Edge

T04

Error Positive Edge to
Receiver Active Negative Edge

T05

T06

Delay from Output Control to
Error Bits from Data Bits

TO?

Delay from Output Control to
Data Bits from Error Bits

T08

First Sync Bit Positive Edge to
Receiver Active Positive Edge

3.5 x T
+70

TOg

Receiver Active Positive Edge to
First Data Available Positive Edge

76 x T

T010

Negative Edge of Ending Sequence to
Receiver Active Negative Edge

11.5 x T
+50

T011

Data Control Set-up Multiplexer Time Prior
to Receiving Data through Selected Input

T012

Serial Data Set-Up Prior to
Data Clock Positive Edge

3xT

Symbol

Parameter

Conditions

1-38

C
co

Timing Characteristics (Notes 2,6, 7, and 8) (Continued)

Symbol

Parameter

Conditions

Typ

Min

Max

Units

TpW1

TpW2

TpW3

Data Available Logic
Data Bytes

Output Control Set-Up Time Prior to
Register Read Negative Edge

-5

Output Control Hold Time after the
Register Read Positive Edge

-5

TZE

"a" State between

Delay from Output Enable to Logic "1" or
Logic "a" from High Impedance State

Load Circuit 2

Delay from Output Enable to High Impedance State from Logic "1" or Logic "a"

Load Circuit 2

Data Bit Frequency (Clock Input must be

3.5

MBits/s

8 x the Data Bit Frequency)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min.lmax. limits apply across the O'C to -+- 70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA = 25'C and Vec = 5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max. or min. are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Input characteristics do not apply to amplifier inputs (pins 2 & 3).
Note 6: Unless otherwise specified, all AC measurements are referenced to the 1.5V level of the input to the 1.5V level of the output and load circuit 1 is used.
Note 7: AC tests are done with input pulses supplied by generators having the following characteristics: ZOUT
Note 8: T

= 50, Tr

5 ns, and Tr ~ 5 ns.

= 1/(clock input frequency). units for "T' should be ns.

Test Load Circuits
Vee

Vee

-1 . . .
-1

- l'~~'-'I --~,
I~

15PF

15PF.:

TlIF/5237-8

R2=2k~'

-=-

~~
~

TlIF/5237-9

Load Circuit 1

Load Circuit 2
FIGURE 7

II
1-39

~ r---------------------------------------------------------------------------------------~
~

Timing Waveforms

OUTPUT J - 1 SV
ENABLE
~

1"--·- -

--I

TEl
(VOH-O.5IV

og3j~U -r-_~(Z~+"':'O.~SIVo:_:__<
(OUTPUT CONTROL

=Hil

(Z - O.SIV

I-

T
Ol

PW1
REGISTER ---------------"'"\~
,'
REAO

t1-'--T-0-2-------

1V,..------------

"-----..Ii

TL/F/5237-10

FIGURE 8. Data Sequence Timing

DATA
AVAILABLE

IRECEIVER
ACTIVE

T
03-\

-T04-1

ERROR

r-lD5~

I-,..,-I-'H-l

Ts-I

Lro'-I

DATA BITS

BIT1·BIT7

;(

\
~'''I

OUTPUT
CONTROL

ERROR BITS

DATA BITS
TL/F/5237-11

FIGURE 9. Error Sequence Timing

1 1 1 1 I 1 I

VIOC&~~ON

I 1 I

I 0

DATA

I MCV I MCV I

~---{2l~--JlJ

-I

I..

I-TD8

T011

RECEIVER _ _ _ _ _ _ _ _ _ _ _ _ _ _...I~(;O---------..._ _ _ __
ACTIVE
!
.

I-TD9-1
O~A

AVAILABLE

~-----------

------------------f2~

TL/F/5237-12

FIGURE 10. Message Timing

1-40

Timing Waveforms

(Continued)

-'X'-_______-'X'-____

SERIAL DATA _ _ _ _

T012-1

_ ____1
1

DATA CLOCK

, . . - - - - - \_' - - - - _
. TLlF/5237-13

FIGURE 11. Data Clock and Serial Data Timing

. - BT±(T -25nl)-

CLOCK INPUT FREOUENCY

4T±(T-25ns)-

------~----~----~----~-----+------~N-

_ _ _ _ -40 mY MIN. VIN+
-1.3Y MAX.

TL/F/5237-14

FIGURE 12. Data Waveform Constraints: Amplifier Inputs

-BT±(T-25ns)T..

4T±(T-25ns)-

CLOCK

INPU~ FREOUENCY

1'--------

Note: ITr - T,I s: 10 ns
FIGURE 13. Data Waveform Constraints: Data Input (TTL)

TLlF/5237-15

VCC-----~----~----------~--

VIN+

VIN- ---------f-----~

TL/F/5237-16

FIGURE 14. Equivalent Circuit for DP8343 Input Amplifier

1-41

(f)
~

(f)

a..

Typical Applications

r-o VCC
RESET
I AUTO RESPONSE
REG LOAD

REG FULL

DPTIONAL
INTERFACE
LOGIC
(FIG. 16)

DPB342
TRANSMITTERI
ENCODER

COAX LINE (FIG. 16)

BYTE CLOCK

TWISTED PAIR LINES
FIBER·OPTIC

CI,I

::>

III

...w

...9
...

~
CI,I

CI,I

MAGNETIC

:00:

!....

TRANSMITTER
ACTIVE

INFRARED
RF
RECEIVER
DISABLE

DATA
AVAILABLE

ULTRASONIC
AUDIO
CURRENT CARRYING

ERROR
I OUTPUT CONTROL
I OUTPUT ENABLE

OPTIONAL
INTERFACE
LOGIC

DP8343
RECEIVERI
DECODER

DC TO 3.5MHz

I REG READ
I
I RECEIVER ACTIVE

TLlF/5237-17
Note 1: Crystal manufacturer Midland Ross Corp., NEL Unit Part No. NE·18A

28 MHz

FIGURE 15

1-42

Typical Applications

(Continued)

150
DATA
DELAY

90Q CDAX
(RG62A/U)

I2
TRANSMITTER
ACTIVE

dJ
R6
120

R5
150

50
+IN

CDNNECT TD
DP8341

RECEIVER

L--*8-~

-IN

GND
TUF/5237-18
Note 1: Resistance values are in

±5%,

V.w.

Note 2: T1 is a 1:1:1 pulse transformer, LMIN = 500 J.LH for 18 MHz system clock.
Pulse Engineering Part No. 5762,
Valor Electronics Part No. CT1501
Technitrol Part No. 11 LHA or equivalent transformers.

FIGURE lS.lnterface Logic for a Coax Transmission Line

IDEAL
WAVEFORM
AT TRANSMITIER
END OF CABLE

TUF/5237-19

TL/F/5237-20
Note 1: Less inductance will cause greater amplitude
attenuation.

°To maintain loss at 95% of ideal signal, select
transformer inductance such that:
10,000
L(MIN) =

fCLK

Note 2: Greater inductance may decrease signal rise
time slightly and Incease ringing, but these effects are
generally negligible.

fCLK = System Clock

Frequency
(e.g., 18.87 MHz)
Example:

L=~18.87 x 106

L(MIN) = 530 H
po

FIGURE 17. Transformer Selection

1·43

III

m
oqo

~ ~National
~

Semiconductor

DP8344B Biphase Commun\ications Processor-BCP®
General Description
The DP8344B BCP is a communications processor designed to efficiently process IBM® 3270, 3299 and 5250.
communications protocols. A general purpose 8-bit protocol
is also supported.
The BCP integrates a 20 MHZ 8-bit. Harvard architecture
RISC processor, and an intelligent, software-configurable
transceiver on the same low power microCMOS chip. The
transceiver is capable of operating without significant processor interaction, releasing processor power for other tasks.
Fast and flexible interrupt and subroutine' capabilities with
on-chip stacks make this power readily available.
The transceiver is mapped into the processor's register
space, communicating with the processor via,an asynchronous interface which enables both sections of the chip to
run from different clock sources. The transmitter and receiver run at the same basic clock frequency although the receiver extracts a clock from the incoming data stream to
ensure timing accuracy.
The BCP is designed to stand alone and is capable of implementing a complete communications interface, using .the
processor's spare power to control the complete system.
Alternatively, the BCP can be interfaced to another processor with an on-chip interface controller arbitrating access to
data memory. Access to program memory is also possible,
providing the ability to download BCP code.
A simple line intertace connects the Bep to the communications line. The receiver includes an on-chip analog comparator, suitable for use in a transformer-coupled environment,

although a TTL-level serial input is also provided for applications where an external comparator is preferred.
A typical system is shown below. Both coax and twinax line
interfaces are shown, as well as an example of the (optional) remote processor interface.

Features
Transceiver
• Software configurable for 3270, 3299, 5250 and general
8-bit protocols
II Fully registered status and control
• On-chip analog line receiver
Processor
• 20 MHz clock (50 ns T-states)
• Max. instruction cycle: 200 ns
• 33 instruction types (50 total opcodes)
• ALU and barrel shifter
• 64k x 8 data memory address range
• 64k x 16 program memory address range
(note: typical system requires <2k program memory)
• Programmable wait states
• Soft-Ioadable program memory
• Interrupt and subroutine capability
• Stand alone or host operation
• Flexible bus interface with on-chip arbitration logic
General
• Low power microCMOS; typo Icc = 25 rnA at 20 MHz
• 84-pin plastic leaded chip carrier (PLCC) package

Block Diagram
Typical BCP System
Program
.. emory

r,;:::::-;;;=-,c~~1ill:I

Coax
DP8344B

Line

Twin ..

----f..-:.It-+-...

Lint

FIGURE 1

1-44

TL/F/9336-S1

The DP8344B Is an enhanced version of the DP8344A, exhibiting Improved switching performance and additional
functionality. The device has been been characterized In a number of applications and found. to be. a compatible
replacement for the DP8344A. Differences between the DP8344A and DP8344B are noted by shading of the text on the
pages of this data sheel For more Information, refer to Section 6.6.
Note: In this document [XXX] denotes a control or status bit in a register, (YYyJ denotes a register.

Table of Contents
1.0 COMMUNICATIONS PROCESSOR OVERVIEW

3.0 TRANSCEIVER

1.1 Communications Protocols

3.1 Transceiver Architectural Description

1.2 Internal Architecture Overview

3.1.1 Protocols
3.1.1.1 IBM 3270
3.1.1.2 IBM 3299
3.1.1.3 IBM 5250
3.1.1.4 General Purpose 8-Bit

1.3 Timing Overview
1.4 Data Flow
1.5 Remote Interface Overview
2.0 CPU DESCRIPTION

3.2 Transceiver Functional Description

2.1 CPU Architectural Description

3.2.1
3.2.2
3.2.3
3.2.4
3.2.5

2.1.1 Register Set
2.1.1.1 Banked Registers
2.1.1.2 Timing Control Registers
2.1.1.3 Interrupt Control Registers
2.1.1.4 Timer Registers
2.1.1.5 Transceiver Registers
2.1.1.6 Condition Code/Remote Handshaking
Register
2.1.1.7 Index Registers
2.1.1.8 Stack Registers

Transmitter
Receiver
Transceiver Interrupts
Protocol Modes
Line Interface
3.2.5.1 3270 Line Interface
3.2.5.2 5250 Line Interface

4.0 REMOTE INTERFACE AND ARBITRATION SYSTEM
(RIAS)
4.1 RIAS Architectural Description
4.1.1
4.1.2
4.1.3
4.1.4

2.1.2 Timer
2.1.2.1 Timer Operation
2.1.3 Instruction Set
2.1.3.1 Harvard Architecture Implications
2.1.3.2 Addressing Modes
2.1.3.3 Instruction Set Overview

Remote Arbitration Phases
Access Types
Interface Modes
Execution Control

4.2 RIAS Functional Description
4.2.1 Buffered Read
·4.2.2 Latched Read

2.2 Functional Description
2.2.1 ALU
2.2.2 Timing
2.2.3 Interrupts

4.2.3 Slow Buffered Write
4.2.4 Fast Buffered Write
4.2.5 Latched Write

2.2.4 Oscillator

4.2.6 Remote Rest Time

•
1-45

,', Table of Contents (Continued)
5.0 DEVICE SPECIFICATIONS
5.1 Pin Description

6.3 Remote Interface Reference
6.4 Development Tools

5.1.1 Timing/Control Signals

6.4.1 Assembler System

5.1.2 Instruction Memory Interface
5.1.3 Data Memory Interface

6.4.2 Development Kit
6.4.3 Multi-Protocol Adapter Design/Evaluation Kit

5.1.4 Transceiver Interface
5.1.5 Remote Interface
5.1.6

Ext~rri~il~terru~ts

5.2 Absolute Maximum Ratings
5.3 Operating Conditions
5.4 Electrical Characteristics
5.5 Switching

Characte~istics,

6.4.4 Inverse Assembler
6.5 3rd Party Suppliers
6.5.1 Crystal
6.5.2 System Development Tools
6.6 DP8344A Compatibility Guide
6.6.1 CPU Timing Changes
6.6.2 Additional Functionality

5.5.1 Definitions,

6.6.2.1 4 T-state Read

5.5.2 Timing Tables and Figures

6.6.2.2 AI AD Reset State
6.6.2.3 RIC

6.0 REFERENCE SECTION
6.1 Instruction Set Reference
6.2 Register Set Reference
6.2.1 Bit Index
6.2.2 Register 'bespriPtion
6.2.3 Bit Definition Tables
,6.2:3~f Processor
6.2.3.2 Transceiver

6.6.2.4 Transceiver
6.7 Reported Bugs
6.7.1 History
6.7.2 LJMP, LCALL Address Decode
6.7.2.1 Suggested Work-around
6.8 Glossary
6.9 Physical Dimensions

List of Illustrations
Block Diagram of Typical BCP System .............................................................................. 1
Biphase Encoding ......................•....................................................•.•...............• 1-1
IBM 3270 Message Format ...................................................................................... 1-2
Simplified Block Diagram ...............................................•........................................ 1-3
Memory Configuration .......................................................................................... 1-4
Effect of Memory Wait States on Timing ......................•.................................................... 1-5
Register to Register Internal Data Flow ....................•...•....................................•............ 1-6a
Data Memory WRITE Data Flow ................................................................................ 1-6b
Data Memory READ Data Flow ..............................•................•................................. 1-6c
WRITE to Transmitter Data Flow ..........................................................•..................... 1-6d
READ from Receiver Data Flow ................................................................................. 1-6e
Load Immediate Data Data Flow ........................•...............................•.....•..•.....•......... 1-6f
Basic Remote Interface ......................................................................................... 1-7
Register Map ..................................................................................................2-1
Timer Block Diagram ..........................................................•...........................•....2-2
Timer Interrupt Diagram ..............................................................................•..........2-3
Index Register Map .........................•....................................•..............................2-4
Coding Examples of Equivalent Conditional Jump Instructions ....................................................... 2-5
JRMK Instruction Example ...............................•.......................•..............................2-6
Condition Code Register AlU Flags .............................•..........................•....•................ 2-7
Carry and Overflow Calculations •................................................................................ 2-8
Shifts' Effect on Carry .....................•.......................................•............•...............2-9
Rotates' Effect on Carry .......................................................................................2-1 0
Multi-Byte Arithmetic Instruction Sequences ......................................................................2-11
CPU-ClK Synchronization with X1 .............................................................•................2-12
Changing from OClK/2 to OClK ................................................................................ 2-13
Two T-state Instruction .........................................................................•..............2-14
Three T-state Instruction ........................................................................•.....•........2-15
Three T-state Data Memory Write Instruction ..................................................................... 2-16
Three T-state Data Memory Read Instruction ..........................•.......................................... 2-17
Four T-state Data Memory Read Instruction ...................................................................... 2-18
FourT-state Program Control Instruction ......................................................................... 2-19
Four T-state Two Word Instruction .............................................................................. 2-20
Data Memory Write with One Wait State ......................................................................... 2-21
Data Memory Read with One Wait State •............................•........................................... 2-22
Data Memory Read with Two Wait States .......................................•................................ 2-23
Two T-state Instruction with Two Wait States ..................................................................... 2-24
Four T-state Instruction with One Wait State ..................................•.......................•........... 2-25
Data Memory Access Wait Timing ............................................................................... 2-26
Two T-state Instruction WAIT Timing ................................................................•.........•. 2-27
Three T-state Program Control Instruction WAIT Timing ...............•............................................ 2-28
Four T-state Program Control Instruction WAIT Timing .......................................••.................... 2-29
lOCK Timing ....................•................................•...........................................2-30
lOCK Timing with One Wait State ..................................•......................•..................... 2-31
CPU Start-Up Timing ..........................................................................................2-32
Functional State Diagram of CPU Timing ..........................................................•.............. 2-33
Interrupt Timing ................•..............................................................................2-34
DP8344B Operation with Crystal .........................•......................................................2-35
DP8344B Operation with External Clock ........................................................•.•.............. 2-36

1-47

"'I:t'

List of Illustrations (Continued)

System Block Diagram, Showing Details of Line Interface ........................................................... 3·1

Biphase Encoding ..............................................................................................3·2
3270/3299 Protocol Framing Format ............................................................................. 3·3
5250 Protocol Framing Format ...................................................................................3·4
General Purpose 8·Bit Protocol Framing Format .................................................................... 3·5
Block Diagram of Transceiver, Showing CPU Interface .............................................................. 3·6
Transmitter Output .............................................................................................3·7
Timing of Receiver Flags Relative to Incoming Data ................................................................ 3·8
3270, 3299 Frame Assembly/Disassembly Description .............................................................. 3·9
5250 Frame Assembly/Disassembly Description .................................................................. 3·10
General Purpose 8·Bit Frame Assembly/Disassembly Description ................................................... 3·11
BCP Receiver Design .......................................................................................... 3·12
BCP Driver Design ............................................................................................3·13
BCP Coax/Twisted Pair Front End ...................................................................•.......... 3·14
5250 Line Interface Schematic .................................................................................. 3·15
Remote Interface Processor ..................................................................................... 4·1
Remote Interface Control Register ............................................................................... 4·2
Generic Remote Access ........................................................................................ 4·3
Generic RIC Access .................................................................................... ; ....... 4·4
Memory Select Bits in (RIC I ..................................................................................... 4·5
Generic DMEM Access .........................................................................................4·6
Generic PC Access .............................................................................................4·7
Generic IMEM Access ........................................•.................................................4·8
Read from Remote Processor ................................................................................... 4·9
Buffered Write from Remote Processor ............................ " ........................................... .4·10
Latched Write from Remote Processor ..........................................................•............... .4·11
Minimum BCP/Remote Processor Interface ...................................................................... 4·12
Interface Mode Bits ...........................................................................................4·13
Flow Chart of Buffered Read Mode ..............................................................................4·14
Buffered Read of Data Memory by Remote Processor ............................................................ .4·15
Flow Chart of Latched Read Mode .............................................................................. 4·16
Latched Read of Data Memory by Remote Processor ............................................................. .4·17
Flow Chart of Slow Buffered Write Mode ......................................................................... 4·18
Slow Buffered Write to Data Memory by Remote Processor ...........................................•............. 4·19
Flow Chart of Fast Buffered Write Mode .......................................................................... 4·20
Fast Buffered Write to Data Memory by Remote Processor ......................................................... 4·21
Flow Chart of Latched Write Mode .............................................................................. 4·22
Latched Write to Data Memory by Remote Processor .............................................................. 4·23
Mistaking Two Remote Accesses as Only One .................................................................... 4·24
Remote Rest Time for All Modes Except Latched Write ............................................................ 4·25
Rest Time for Latched Write Mode ............................................................................. .4·26
DP8344B Top View .............................................................................................5·1
Switching Characteristic Measurement Waveforms ................................................................. 5·2
Data Memory Read Timing ...................................................................................... 5·3
Data Memory Write Timing ......................................................................................5·4
Instruction Memory Timing ......................................................................................5·5
Clock Timing .................................................................................................. 5·6

1·48

List of Illustrations (Continued)
Transceiver Timing .............................................................................' ......... '....... 5-7
Analog and DATA-IN Timing .....................................................................................5-8
Interrupt Timing ........................................................................................... ; ..... 5-9
Control Pin Timing .....................................................................'. '..... ; ................ 5-10
Buffered Read of PC, RIC .................................................... _.................................. 5-1.1
Buffered Read of DMEM ....................................................................................' ..... 5-12
Buffered Read of IMEM ........................................................................................5-13
Latched Read of PC, RiC .................................................................• ; ................... 5-14
Latched Read of DMEM ....................................................................................... 5-15
Latched Read of IMEM ........................................................................ ; .. '............. 5-16
Slow Buffered Write of PC, RIC ................................................................................. 5-17
Slow Buffered Write of DMEM ..................................................................................5-18
Slow Buffered Write of IMEM ..........................................................•....•...................5-19
Fast Buffered Write of PC, RIC .................................................................................. 5-20
Fast Buffered Write of DMEM ..................................................................... ;.: ........ ; ... 5-21
Fast Buffered Write of IMEM ...................................................................................5-22
Latched Write of PC, RiC .... '...............................................,.........•...... , .................... 5-23
Latched Write of DMEM .......................................................................................5-24
Latched Write of IMEM .............•......................................................... ;' ................ 5-25
Remote Rest Times ..........................................................................,.. _.............. 5-26
Remote Interface WAIT Timing .................................................................. ~ ........ ; .. '... 5-27
WAIT Timing after Remote Access ...............................................................•...... ',' ....... 5-28
Instruction Memory Bus Timing for 2 T-state Instructions .................................•.......................... 6-1
Instruction Memory Bus Timing for 3 T-state Instructions ............................................................ 6-2
Instruction Memory Bus Timing for (2+2) T-state Instructions ........................................................ 6-3
Instruction Memory Bus Timing for 4 T-state Instructions .......................................... : .............•... 6-4
Instruction/Data Memory Bus Timing for Data Memory Read [4TR] = 0 ................................. , .•........... 6-5
Instruction/Data Memory Bus Timing for Data Memory Read [4TR] = 1 ................................................ 6-6
Instruction/Data Memory Bus Timing for Data Memory Write ......................................................... 6-7

List of Tables
Register Addressing Mode Notations ., .........................................................'.... : ............. 2-1
Immediate Addressing Mode Notations .......................................................... , .............. : .2-2
Index Register Addressing Mode Notations ..................................................... :.: ................ 2-3
Relative Index Register Mode Notations ...........................................................................2-4
Data Movement Notations .......................................................................................2-5
Integer Arithmetic Instruction ............................................................. ',' .: ....•............ ',' .2-6
Logic Instructions ....................................................,....................... ,' ... ; ... , ........ , .2-?
Shift and Rotate Instructions ........................................................... ',' .......... , ....... " ... , .2-8
Comparison Instructions ................................................,' ...... ,' ................ ; .. " . !

••••••• " •. 2-9

Unconditional Jump Instructions ................................ ,' ........................•........... , ... ,....... 2-10
Conditional Relative Jump Instructions .............................................................. , ............ 2-11
"f" Flags ............................................................................•.. : .. : ........ ', ......... 2~12
"cc" Conditions Tested ........................................................................................2-13
Conditional Absolute Jump Instructions ............................................ : .............. : •........... : .2-14
JRMK Instruction .............................................................................................2-15
Unconditional CaUlnstructions ................................................................................. ,2-16
Conditional Call Instructions .............................................................................. '...... 2-17
Unconditional Return Instruction ................................................................................ 2-18
Conditional Return Instruction .................................................................................. 2-19
TRAP Instruction ..............................................................................................2-20
EXX Instruction ...............................................................................................2-21

1-49

m
~

List of Tables

(Continued)

Unsigned Comparison Results ................•..........•...................................................... 2-22

Signed Comparison Results .................................................................................... 2-23
Data Memory Wait States .•...•.........•................•..................................................... 2-24
Instruction Memory Wait States ......•................................................................•......... 2-25
BIRQ Control Summary .........................................................................................2-26
IICR I Interrupt Mask Bits and Interrupt Priority ...•................................................................ 2-27
Interrupt Vector Generation ..•....................•............................................................ 2-28
Recommended Crystal Parameters .•...........•................................................................ 2-29
Protocol Mode Definitions ....•......•..•..........••............................................................ 3-1
Transceiver Interrupts ..•......•........••........•.•.........•........•........................................ 3-2
Receiver Interrupts ......................•......................................................................3-3
Decode of 3270 Coax Commands ..•.........................•................................................... 3-4
RIAS Inputs and Outputs ........•...........•.....•...•..........•............................... ~ .............. 4-1

Note: To match Timing table number with appropriate Timing illustration, Tables 5-1 and 5-2 are purposely omitted.
Data Memory Read Timing ..........•.....•................................................................•.... 5-3
Data Memory Write Timing .....•...........•....................................................................5-4
Instruction Memory Timing .......•.............................................................................. 5-5
Clock Timing ......•......................••................................................................... 5-6
Transceiver Timing .•..........••............................................................................... 5-7
Analog and DATA-IN Timing ....•...........•................•...............•........................... '........ 5-8
Interrupt Timing .......•..................•.........•........................................................... 5-9
Control Pin Timing ............................................................................................5·1 0
Buffered Read of PC, RIC ...................•.................................................................. 5·11
Buffered Read of DMEM ................................ : ...................................................... 5-12
Buffered Read of IMEM ....................•.........•......................................................... 5·13
Latched Read of PC, RiC ......•....... '................•....................................................... 5-14
Latched Read of DMEM .......••............•.........•....................................................... 5-15
Latched Read of IMEM .......................•................................................................5·16
Slow Buffered Write of PC, RiC •...•.•.................................................•........................ 5·17
Slow Buffered Write of DMEM ..•...•........•..........•....................................................... 5-18
Slow Buffered Write of IMEM ...........•.....•.................................•..............................•5-19
Fast Buffered Write of PC, RIC ......•...... '..•.................................................................. 5-20
Fast Buffered Write of DMEM .................•.........•.....................................................•. 5-21
Fast Buffered Write of IMEM ...........•.........................................•........ ; .................... 5-22
Latched Write of PC, RiC ............' ....•.................•.................................................... 5-23
Latched Write of DMEM ........................................................................................ 5-24
Latched Write of IMEM .........................................................................................5-25
Remote Rest Times ...................•.......•........................•.........•....•............'........... 5-26
Remote Interface WAIT Timing ....•....•.....•................................................................. 5-27
WAIT Timing after Remote Access •............•.••............................................................. 5-28
Notational Conventions for Instruction Set ......... '...................... '.......................................... 6-1
Instructions vs T-states, Affected Flags and Bus Timing ......................................................•...... 6-2
Instruction Opcodes ........ " ....................................................•.............................6-3
DP8344B Application Notes ............... ~ .......................................................................6-4

1-50

1.0 Communications Processor Introduction
codes the data value, other transitions lie on bit boundaries.
Bit boundaries are not always indicated by transitions, so
techniques employing start sequences and sync bits are
used with bi-phase transmissions to ensure proper frame
alignment and synchronization.

The increased demand for computer connectivity has driven
National Semiconductor to develop the next generation of
special purpose microprocessors. The DP8344B is the first
example of a "Communications Processor" for the IBM environment. It integrates a very fast, full function microprocessor with highly specialized transceiver circuitry. The combination of speed, power, and features allows the designer
to easily implement a state-of-the-art communications interface. Typical applications for a communications processor
are terminal emulation boards for PCs, stand-alone terminals, printer interfaces, and cluster controllers.

The software specification covers the use of start sequences and sync bits, as well as defining the. message
format. Parity bits may be used to ensure data integrity. The
message format is the "language" that is used to exchange
information across the connecting medium. It defines command and control words, response times, and expected responses.

The transceiver is designed to simplify the handling of specific communication protocols. This feature makes it possible to quickly develop interfaces and software with little concern for the "housekeeping" details of the protocol being
used.

The DP8344B Bi-phase Communications Processor supports both the IBM 3270 and 5250 communication protocols, as well as IBM 3299 and a general purpose 8-bit protocol. The specialized transceiver is combined with a microprocessor whose instruction set is optimized for use in a
communications environment. This makes the DP8344 a
powerful single-chip solution to a wide range of communication applications.

1.1 COMMUNICATIONS PROTOCOLS

A communication protocol is a set of rules which defines the
physical, electrical, and software specifications required to
successfully transfer data between two systems.

An example of an IBM 3270 message is shown in Figure
1-2. The transmission begins with a very specific start sequence and sync pulse for synchronization. This is followed
by the data, command, and parity bits. Finally, the end sequence defines the end of the transmission.

.The physical specification includes the network architecture, as well as the type of connecting medium, the connectors used, and the maximum distance between connections.
Networks may be configured in "loops," "stars," or "daisy
chains," and they often use standard coaxial or twisted-pair
cable.

The IBM 3270 and 5250 are two widely used protocols. The
3270 protocol was developed for the 370 class mainframe,
and it employs coaxial cable in a "star" configuration. The
5250 protocol was developed for the System/3x machines,
and it uses a "daisy-chain" of twin-ax cable. A good overview of both of these environments may be found in the
"Multi-Protocol Adapter System User Guide" from National
Semiconductor, and in the Transceiver section of this document.

The electrical specification includes the polarity and amplitude of the signal, the frequency (bit rate), and encoding
technique. One common method of encoding is called "biphase" or "Manchester II." This technique combines the
clock and data information into one transmission by encoding data as a "mid-bit" transition. Figure 1-1 shows how the
data transition is related to the bit boundary in a typical
transmission. The polarity of the "mid-bit" transition en-

BIT BOUNDARY
ENCODED
SIGNAL
DATA
VALUE

"0"

"1"

"0"
TlIF /9336- 87

FIGURE 1-1. Biphase Encoding
START
SEQUENCE

SYNC

COt.Ct.CAND
&

DATA

END
SEQUENCE

~PARITY-+1

1-]

1
,..------TlIF/9336-8B

FIGURE 1-2. IBM 3270 Message Format

II
1-51

m r-------------------------------------------------------------------~
~
1.0 Communications Processor Introduction (Continued)

"'I:t'

~
C

1.2 INTERNAL ARCHITECTURE INTRODUCTION'
The DP8344B Biphase Communications Processor (BCP) is
divided into three major functional blocks: the Transceiver,
the Central Processing Unit (CPU), and the Remote Interface and Arbitration System, RIAS. Figure 1-3 shows how
these blocks are related to each other and to other system
components.
The transceiver consists of an asynchronous transmitter
and re'ceiver which can communicate across' a serial data
path. The transmitter takes parallel data frornthe CPU and
appends to it the appropriate framing information. The resuiting message is shifted out and is available as a serial
data stream on two output ,pins. The receiver shifts in serial
messagesi'strips off the framing information, and makes the
data available in parallel form to the CPU. The framing infor~
mation supplied by'the BCP provides the proper message
format for several popular communication protocols. These
include IBM 3270,' 3299, and 5250, as well as a general
purpose 8-bit mode. .'
The transceiver clock may be derived from the' internal oscillator, either directly or through internal divide-down circuitry. There is also an' input for an external transceiverciock,
thus allowing complete flexibility in the choice of data rates.
The receiver input can come from three possible sources.
There is a built-in differential amplifier which is suitable for
most line interfaces; a single-ended digital input for use with
an external comparator, and an internal loopbackpath for
self testing. Refer to the Transceiver section for a detailed
description of all transmitter and receiver functions, and to
the application note on coax interfaces for the proper use of
the differential amplifier.
, CP U',Is a general purpose,
' ,a-bit
' microprocessor capaThe

(ALU) which performs addition, subtraction, Boolean operations, rotations and shifts. Separate instruction and data
memory systems are supported, each with 16-bit address
buses, for a total of 64k address space in each.
There are 44 internal registers accessible to the CPU.
These include special configuration and control registers for
the transceiver and processor, four 16-bit indices to data
memory,and 20 8-bit general purpose registers. There is
also a 16-bit timer and a 16-byte deep LIFO data stack
which are accessible in the' register address space. For
more detailed information, see the specific sections on the
Register set, the Timer, and the ALU.
The BCP can operate independently or with another processor as the host system. If such a system is required, communication with the BCP is possible by sharing data memory. The Remote Interface controls bus arbitration and access to data memory, as well as program up-loading and
execution. For example, it is possible for a host system to
load the BCP's instruction memory and begin program execution, then pass data back and forth through data memory
accesses. The section on the Remote Interface and Arbitration System provides all of the necessary timing and control
information to implement an interface between a BCP and a
remote system.
As shown in Figure 1-4, the BCP uses two entirely separate
memory systems, one for program storage and the other for
data storage. This type of memory arrangement is referred
to as Harvard architecture. Each system has 16 address
lines, for a maximum of 64k words in each, and its own set
of data lines. The instruction (program) memory is two bytes
(16 bits) wide, and the data memory' is one byte (8 bits)
wide.

ble of 20 MHz operation. It has a reduced instruction set
which is optimized for transceiver and data handling performance. It also has a full function arithmetic/logic unit

In order to reduce the number of pins required for these
Signals, the address and data lines for data memory are
multiplexed together. This requires an external latch and the
Address Latch Enable signal (ALE) for de-multiplexing.

CENTRAL PROCESSING
UNIT

1
~

~I ~
TRANSMISSION
INTERFACE'

..-

REMOTE
INTERFACE

TRANSCEIVER
I--

RAM/ROM
MEMORY

HOST COMPUTER
(OPTIONAL)

--y
.A

I
~

TL/F/9336-B9

FIGURE 1-3. Simplified Block Diagram

1-52

1.0 Communications Processor Introduction
Simultaneous access to both data and program memory,
and instruction pipelining greatly enhance the speed performance of the BCP, making it well suited for real-time processing. The pipeline allows the next instruction to be retrieved from program memory while the current instruction is
being executed.

(Continued)

rotates, and register moves, require only two T-states.
Branching instructions and data memory accesses require
three to four T-states.
Each memory system has a separate, programmable number of wait states to allow the use of slower memory devices. Instruction memory wait states are inserted into all instructions, as shown in Figure 1-5, thus they affect the
overall speed of program execution. Instruction memory
wait states can also apply when the Remote Interface is
loading a program into instruction memory. Data memory
wait states are only inserted into data memory access instructions, hence there is less degradation in overall program execution. Refer to the Timing section for detailed examples of all BCP instruction and data memory timing.

1.3 TIMING INTRODUCTION

The timing of all CPU operations, instruction execution and
memory access is related to the CPU clock. This clock is
usually generated by a crystal and the internal oscillator,
with optional divide by two circuitry. The period of the resulting CPU clock is referred to as a T-state; for example, a
20 MHz CPU clock yields a 50 ns T-state. Most CPU functions, such as arithmetic and logical operations, shifts and

ADDRESS

I\.
I'

DATA

A
~

R7W

INSTRUCTION
MEMORY
64k x 16

BCP
READ
WRITE
ADDRESS

roNmOl~

I\.
I'

DATA
MEMORY
64k x 8

LATCH

A
~

ADDRESS/DATA

TL/F/9336-C1

FIGURE 1-4. Memory Configuration

INSTRUCTION
BOUNDARY
CPU CLOCK
T-STATE
TWO T-STATE
INSTRUCTION
WITH NO WAIT STATES

INSTRUCTION
BOUNDARY
CPU CLOCK
T-STATE
TWO T-STATE
INSTRUCTION
WITH TWO WAIT STATES

FIGURE 1-5. Effect of Memory Wait States on Timing

1-53

TLlF/9336-C2

1.0 Communications Processor Introduction

(Continued)

The other key element in the data path is the ALU. This unit
does all of the arithmetic and data manipulation operations,
but it also has bus multiplexing capabilities. Both the Data
Memory bus and a portion of the Instruction Memory bus
are routed to this unit and serve as alternative sources of
data. Since the data flow is always through this unit, most
data moves may include arithmetic manipulations with no
penalty in execution time.

1.4 DATA FLOW

The CPU registers are all dual port, that is, they have separate input and output paths. This arrangement allows a single register to function as both a source and a destination
within the same instruction.
Figures 1-6a through 1-6f show the internal data flow path
for the BCP. The CPU registers are a central element to this
path. When a register functions as an output, its contents
are placed on the Source bus. When a register is an input,
data from the Destination bus is written into that register.

Figure 1-6a shows the data path for all arithmetic instructions and register to register moves. The source register
contents are placed on the Source bus, routed through the

FROM DATA
MEMORY

DATA
MEMORY
ADDRESS

DATA

I-....~~ MEMORY

ADDRESS

TLIF/9336-C5
TL/F/9336-C3

FIGURE 1·6a. Register to Register

TL/F/9336-C4

FIGURE 1·6b. Data Memory WRITE

FIGURE 1·6c. Data Memory READ

IMMEDIATE DATA
FROM
INSTRUCTION BUS

~. . ._ _ ~~~EIVER

TRANSMITTER
nFO

TLIF/9336-C6

FIGURE 1·6d. WRITE to Transmitter

TL/F/9336-C7

FIGURE 1·6e. READ from Receiver

1-54

TL/F /9336-C8

FIGURE 1·61. Load Immediate Data

1.0 Communications Processor Introduction

(Continued)

ALU/MUX, and then placed on the destination bus. This
data is then stored into the appropriate destination register.

1.5 REMOTE INTERFACE AND ARBITRATION SYSTEM
INTRODUCTION

Figures 1-6b and 1-6c show the data path for data memory
accesses. For a WRITE operation, the source register contents follow the same path through the ALU/MUX, but the
Destination bus is routed to output pins and on to data
memory. For ,a READ operation, incoming data is routed
onto the Destination bus by the ALU/MUX, and then stored
in a register. The address for all data memory accesses is
provided by one of four 16-bit index registers which can
operate in a variety of automatic increment and decrement
modes.

The BCP is designed to serve as a complete, standalone
communications interface. Alternately;ihari be interfaced
with another processor by means of 'the Remdtelnterface
and Arbitration System. Communication' between the BCP
and the remote processor is possible by,sharing data memory. Harvard architecture allows the remote system' to access any BCP data memory location while the BCP' contin~
ues to fetch and execute instructions, thereby' minimizing
performance'degradation.
Figure 1-7 shows a simplified remote processor interface.
This includes tri-state buffers on the address'and data buses of the BCP's Data MemorY, and all of the-control and
handshaking signals required tocomrilunicate' between the
BCP and the host system:

Transfer of the data byte between the CPU and the Transceiver is accomplished through a register location. This register, ! RTR J, appears as a normal CPU register, but writing
to it automatically transfers data' to the transmitter FIFO,
and reading from it retrieves data from the receiver FIFO.
These paths are illustrated in Figures 1-6d and 1-6e.

There is an 8-bit control register~ Rem'ote Interf~c'e Control
! RIC J, accessible only to the remote system, which is used
to control a variety of features, including the types'of memory accesses, interface speeds, single step program execu-'
tion, CPU start/stop, instruction memdry loads, and
forth.
Detailed information on all interface options is provided in
the section on Remote Interface' and,ArbitratiOn' System,
and in the related Reference section:

It is also possible to load immediate data into a CPU register. This data is supplied by the program and is usually a
constant such as a pointer or character. As shown in Figure
1-6f, a portion of the Instruction bus is routed through the
ALUlMUX for this purpose.

I:',

ADDRESS

DATA

INSTRUCTION
MEMORY

R1ii

64k x 16

BCP
READ
WRITE

ADDRESS

~
LATCH

64k x 8

A DATA
~

DATA
MEMORY

;:..

LCL

r--0

;I ·Il. I!

/j
~

.. 7-

BUS CONTROL

;:..

REMOTE
PROCESSOR

DATA

ADDRESS

TLIF/9336-C9

FIGURE 1-7. Basic Remote Interface

1-55

3
C")

a..
Q

2.0 CPU Description
The CPU Is a general purpose, 8-bit microprocessor capable of 20 MHz operation. It contains a large register set for
standard CPU operations and control of the transceiver.
The reduced InstructlQn set is optimized for the communications environment. The following sections are an architectural and functional description of the DP8344B CPU.

Alternate

IBR

-"ATR

rBR

2.1 CPU ARCHITECTURAL DESCRIPTION
2.1.1 Register Set
This section describes the BCP's internal CPU registers. It is
a general overview of the register structure and the functions mapped Into the CPU register space. It is not a detailed or exhaustive description of every bit. For such a description, please refer to Section 6.2, Register Set Reference. Also, the Remote Interface Configuration register,
(RIC), Is not accessible to the BCP (being accessible only
by the remote system) and is described in Section 6.3, Remote Interface Reference.
The register set of the BCP provides for a compliment of
both special function and general purpose registers. The
special function registers provide access to on-chip peripherals (transceiver, timer, Interrupt control, etc.) while the
general purpose registers maximize CPU throughput by minImlzlng accesses to external data memory. The CPU can
address a total of 44 8·bit registers, providing access to:

-TcR"
Tt.lR

-GP4'
GPS'
-GP6'

---GP7'

• 20 general purpose registers
• 8 configuration and control registers

Index Registers
(pointers)

• 4 transceiver access registers

CCR

Ncr

ICR

ACR

R3
I

-RTR
TSR
B:

t.laln
I

OCR

GPO

GPI

GP2

GP3

GP4 (accumulator)

GPS

GP6

RIO

GP7

Rll

W (low byte)

R12

W (high byte)

R13

x (low

R14

byte)

X (high byte)

R1S

Y (low byte)

R16

Y (high byte)

R17

• 2 8-bit accumulators
• 4 16-bit pointers
• 16·blt timer
• 16 byte data stack
• address and data stack pointers
The CPU addresses internal registers with a 5-bit field, addressing 32 locations generically named RO through R31.
The first twelve locations (RO-R11) are further organized by
function as two groups of banked registers (A and B) as
shown In Figure 2-1. Each group contains both a main and
an alternate bank. Only one bank is active for group A and
one for bank B and thus accessible during program execution. Switching between the banks is performed by the exchange Instruction EXX which selects whether Main A or
Alternate A occupies RO-R3 and whether Main B or Alternate B occupies R4-R11.

TIm"

Z (low byte)

RIB

Z (high byte)

RI9

GPB

R20

GP9

R21

GP10

R22

GPII

R23

GP12

R24

GP13

R2S

GP14

R26

GP1S

R27

I:~

sp
st"k. DS

R28
R29

1'30
R31

TL/F /9336-32

FIGURE 2·1. Register Map

1-56

2.0 CPU Description

(Continued)
not have to be switched in to poll the transceiver. Timer and
BIRQ tasks may also be run using polling techniques to
Main A bank.
In general, the registers have been f3,rranged within the
banks so as to minimize the need to switch banks. The power-up state is Alternate bank A, Alternate bank B' allowing
access to configuration registers. Again, the banks switch
by using theEXX instruction which explicitly specifies which
bank is active (Main or Alternate) for each register group (A
and B). The EXX instruction allows selecting any of four
possible bank settings with a single two T-state instruction.
This instruction also has the option of enabling or disabling
the maskable interrupts.
'

Registers in the RO-R11 address space are allocated in a
manner that minimizes the need to switch banks:
Main A:

CPU control and transceiver status

Alternate A:

CPU and transceiver configuration

Main B:
Alternate B:

8 general purpose
4 transceiver access, 4 general purpose

Most of the BCP's instructions with register operand(s) can
access all 32 register locations. Only instructions with an
immediate operand are limited to the first sixteen register
locations (RO-R15). These instructions, however, still have
access to all registers required for transceiver operation,
CPU status and control registers, 12 general purpose registers, and two of the index registers.

The cO!1tents of the special function registers can be divided into several groups for general discl1ssion-timing/control, interrupt control, the try
Note: & = logical AND

R7,A
R5,R7
R6,A
R4,R6

= one's complement

Signed Comparison Results
Comparison: x - y
xy

Boolean Condition

(N&V) I (N&V)

z I (N&V) I (N&V)
z

(N&V) I (N&Y)
(N&V&l) I (N&V&l)

Note: & = logical AND

= logical OR
= one's complement

2.2.2 Timing
Timing on the BCP is controlled by an internal oscillator and
circuitry that generates the internal timing signals. This circuitry in the CPU is referred to as Timing Control. The internal timing of the CPU is synchronized to an internal clock
called the CPU clock, CPU-ClK. A period of CPU-ClK is
referred to as a T-state. The clock for the BCP is provided
by a crystal connected between X1 and X2 or from a clock
source connected to X1. This clock will be referred to as the
oscillator clock, OClK. The frequency of OClK is divided in
half when the CPU clock select bit, [CCS] , in the Device
Control Register, (DCR I, is set to a one. Either OClK or
OClK/2 is used by Timing Control to generate CPU-ClK
and other synchronous signals used to control the CPU timing.
After the BCP is reset, [CCS] is high and CPU-ClK is generated from OClK/2. Since the output of the divider that creates OClK/2 can be high or low after reset, CPU-ClK can
also be in a high or low state. Therefore, the exact number
of clock cycles to the start of the first instruction cannot be
determined. Automatic test equipment can synchronize to
the BCP by asserting RESET as shown in Figure 2-12. The
falling edge of RESET generates a clear signal which causes CPU-ClK to fall. The next rising edge of X1 removes the
clear signal from CPU-ClK. The second rising edge of X1
will cause CPU-ClK to rise and the relationship between X1
and CPU-ClK can be determined from this point.
Writing a zero to [CCS] causes CPU-ClK to switch from
OClK/2 to OClK. The transition from OClK to OClK/2
occurs following the end of the instruction that writes to

;GET LSB OF Y
;Y(LSB)=X(LSB)+Y(LSB)
;GET MSB OF Y
;Y(MSB)=X(MSB)+Y(MSB)
+CARRY

To perform the assignment Y = X - Y:

MOVE
SUBA
MOVE
SBCA

= logical OR

TABLE 2-23

R7,A
R5,R7
R6,A
R4,R6

clz
z
C
C&l

x~y

Assume the 16-bit variable X is represented by the register pair R4(MSB), R5(lSB), and that the 16-bit variable
Y is represented by the register pair R6(MSB), R7(lSB).
To perform the assignment Y = X + Y:

MOVE
ADDA
MOVE
ADCA

Boolean Condition

x PHASE-9
SHIELD GND
DPDT
PHASE-A

PASS THRU

-----'

~---f---I

TERMINATE

5UD.
1%

54.9D.
1%

10k

820k

4.7k
11

33pF'

4.7k

D-.....-

....=> DATA-IN

75112
11

VeelA

lY
lZ

MINUS-12
820k

19
lC
D

27mA

2A
74ALS810
DATA-DLY O----~"

29
2C

2Y
2Z
TL/F/9336-G4

FIGURE 3·15. 5250 Line Interface Schematic

1-104

4.0 Remote Interface and Arbitration System (RIAS)
INTRODUCTION

bus control circuitry. The RP's address lines decode a chip
select for the BCP called Remote Access Enable (RAE).
Basically, the BCP's Data Memory has been memory
mapped into the RP's memory. A Remote Access of the
BCP occurs when REM-RD or REM-WR, along with RAE is
asserted low. REM-RD and REM-WR can be directly connected to the Remote Processor's read and write lines, or
for more complicated systems the REM-AD and REM-WR
signals may be controlled by a combination of address decode and the RP's read and write signals. To the RP, an
access of the BCP will appear as any other memory system
access. This configuration allows the RP to read and write
. Data Memory, read and write the BCP's Program Counter,
and read and write BCP Instruction Memory. These functions are selected by control bits in the Remote Interface
Configuration register! RIC I. This register can be accessed
only by the RP and not by the BCP CPU. If the Remote
Processor executes a remote access with the Command
input (CMD) high, !RICI is accessed ,through the BCp's AD
bus.

Communication with the BCP is based on the BCP's ability
to share its data memory. A microprocessor (or any intelligent device) can read and write to any BCP data location
while the BCP CPU is executing instructions. This capability
is part of the BCP's Remote Interface and Arbitration System (RIAS). Sharing data memory is possible because
RIAS's arbitration logic allocates use of the BCP's data and
address buses. RIAS has been designed so that accesses
of BCP data memory by another device minimally impact its
performance as well as the BCP's. In addition to data memory accesses, RIAS allows another device to control how
BCP programs are loaded, started and debugged.
4.1 RIAS ARCHITECTURAL DESCRIPTION
Interfacing to the BCP is accomplished with the control signals listed in Table 4-1. Figure 4-1 shows the BCP interfaced to Instruction Memory, Data Memory, and an intelligent device, termed the Remote Processor (RP). Instruction
and Data are separate memory systems with separate address buses and data paths. This arrangement allows continuous instruction fetches without interleaved data accesses. Instruction Memory (IMEM) is interfaced to the BCP
through the Instruction (I) and Instruction Address (IA) buses. IMEM is 16 bits wide and can address up to 64k memory. Data Memory (DMEM) is eight bits wide and can also
address up to 64k memory. The DMEM address is formed
by the 8-bit upper byte (A bus) and the a-bit lower byte (AD
bus). The AD bus must be externally latched because it also
serves as the path for data between the BCP and DMEM.
For further information on how AD bus is used, refer to Section 2.2.2 CPU Timing.

In Figure 4-1, the Remote Processor's address lines are
decoded to form the CMD input. When a remote access
takes place with CMD low, the memory system designated
in !RICI is accessed. Figure 4-2 shows the contents of
!RICI. The two least significant bits are the Memory Select
bits [MS1-0] which designate the type of reinote access: to
Data Memory, the Program Counter, or Instruction Memory.
This register also contains the BCP start bit [STRT], three
interface select bits [FBW, LR, LW], the Single-Step bit
[SS], and the Bi-directional Interrupt Status bit [BIS]. Refer
to the RIAS Reference Section for a more detailed description of the contents of this register and the function of each
bit.

The Remote Processor's address and data buses are connected to the BCP's address and data buses through the

--I

IAl========~~AD;D;R

INSTR
tc===============~DATA RAM
ViR

1--------.-,~IViR

J=======:::;;==:::;;::::~ADDR DATA
RAM

REMOTE
PROCESSOR

DATA t:;::::======:::J
ADDRI=======~
TLIF/9336-19

FIGURE 4·1. BCP/Remote Processor Interface
1-105

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

TABLE 4-1. RIAS Inputs and Outputs
In/Out

Reset
State

CoMmanD input. When high, remote accesses are directed to the
Remote Interface Configuration register, (RICI. When low, remote
accesses are directed to Data Memory, Instruction Memory or the
Program Counter as determined by (RIC [1,0] I.

Out

loCal. Normally low, goes high when the BCP relinquishes the data
and address bus to service a remote access.

'['(5CK

Asserting this input Low will lOCK out local (BCP) accesses to Data
Memory. Once the remote processor has been granted the bus,
lOCK gives it sole access to the bus and BCP accesses are
"waited".

'RAE

Remote Access Enable. Setting this input low allows host access of
BCP functions and memory.

REM-RD

REMote ReaD. When low along with RAE, a remote read cycle is
requested; serviced by the BCP when the data bus becomes
available.

REM-WR

REMote WRite. When low along with RAE, a remote write cycle is
requested; serviced by the BCP when the data bus becomes
available.

WR·PEND

Out

WRite PENDing. In a system configuration where remote write
cycles are latched, WR·PEND will go low, indicating that the latches
contain valid data which have yet to be serviced by the BCP.

XACK

Out

Transfer ACKnowledge. Normally high, goes low on REM-RD or
REM-WR going low (if RAE low) returning high when the transfer is
complete. Normally used as a "wait" signal to a remote processor.
(In the latched Write mode, XACK will only transition if a second
remote access begins before the first one completes.)

WAIT

Asserting this input low will add wait states to both remote accesses
and to the BCP instruction cycle. WAIT will extend a remote access
until it is set high.

Signal
CMD

Function

The two key handshake signals involved in the BCP/RP
interface are Transfer Acknowledge (XACK) and Local
(LCL). Internally, two more signals control the access tim·
ing: INT·READ and INT-WRITE. The timing for a generic
Remote Access is shown in Figure 4-3. A remote access is

IBIS ISS IFBW ILR ILW ISTRT IMS1 IMSO IRIC
BIS

-Bidirectional Interrupt Status

-Single-Step

FBW

-Fast Buffered Write mode

-Latched Read mode

-Latched Write mode

REHDM~

REt.I-WR

XACK

,
!,

STRT -BCP CPU start/ stop

[C[

MS1-0 -Memory Selection
FIGURE 4-2. Remote Interface Control Register

INT- READ or
INT-WRITE
Arbitration

The BCP CPU and RIAS share the internal CPU-ClK. This
clock is derived from the X1 crystal input. It can be divided
by two by setting [CCS] = 1 in (OCR I or run undivided by
setting [CCS] = O. The frequency at which the Remote
Processor is run need not bear any relationship to the CPUClK. A remote access is treated as an asynchronous event
and data is handshaked between the Remote Processor
and the SCPo

,
,

4.1.1 Remote Arbitration Phases

;

'/
I

Access

__ J

Termination

TLIF/9336-20

FIGURE 4-3. Generic Remote Access (RAE

= 0)

initiated by the RP asserting REM-RD or REM-WR with RAE
low. There is no set-up/hold time relationship between RAE
and REM-RD or REM-WR. These signals are internally gated together such that if RAE (REM-RD + REM-WR) is true,
a remote access will begin. A short delay later, XACK will
fall. This signal can be fed back to the RP's wait line to
extend its read or write cycle, if necessary. When the BCP's

1·106

4.0 Remote Interface and Arbitration System (RIAS)
arbitration logic determines that the BCP is not using data
memory, lCl rises, relinquishing control of the address and
data buses to the RP. The remote access can be delayed at
most one BCP instruction (providing [lOR] is not set high).
If the CPU is executing a string of data memory accesses,
RIAS has an opportunity to break in at the completion of
every instruction. The time period between REM-RD or
REM-WR being asserted (with RAE low) and [C[ rising is
called the Arbitration Phase. It is a minimum of one T-state,
but can be increased if the BCP CPU is accessing Data
Memory (local access) or if the BCP has set the lock Out
Remote bit [lOR].
The CMD pin is internally latched on the first falling edge of
the CPU-ClK after a remote access has been initiated by
asserting RAE low along with asserting REM-RD or
REM-WR low. If the remote interface is asynchronous, the
CMD signal must be valid simultaneously or before RAE is
asserted low along with REM-RD or REM-WR being asserted low. The value of CMD is only sampled once during each
remote access and will remain in effect for the duration of
the remote access.
After the Arbitration Phase has ended, the Access Phase
begins. Either Data Memory, Instruction Memory, the Program Counter, or (RIC! is read or written in this phase.
Either INT-READ or INT-WRITE will fall one T-state after
[C[ rises. These two signals provide the timing for the different types of accesses. INT-READ times the transitions on
the AD bus for Remote Reads and forms the external READ
line. INT-WRITE clocks data into the PC and (RIC! and
forms the IWR and WRITE lines. INT-READ and INT-WRITE
rise with XACK, or shortly after.
The duration of the Access Phase depends on the type of
memory being accessed. Data Memory and Instruction
Memory accesses are subject to any programmed wait
states and all remote accesses are waited by asserting
WAIT low. The minimum time in the Access Phase is 2
T-states.
The rising edge of XACK indicates the Access Phase has
ended and the Termination Phase has begun. If the RP was
doing a read operation, this edge indicates that valid data is
available to the RP. During the Termination Phase the BCP
is regaining control of the buses. [C[ falls one T-state after
XACK and since the RP is no longer being waited, it can
deassert REM-RD or REM-WR. The duration of this phase
is a minimum of one T-state, but can be extended depending on the interface mode chosen in (RIC!.

(Continued)

TRI-STATE during a Remote Write Figure 4-4(b) while [C[
is high. The byte being written to (RIC! is latched on the
rising edge of XACK and can be seen on AD after [C[ falls.
The Access Phase, in this case, is always two T-states (unless WAIT is low) because (RIC! is not subject to any programmed wait states.

Arbitration
REt.I-RD

Access

Termination

~'--_...I._ _ _ _.....a.._ _-J~

WllZ
,'---'----......,/

XACK

''---

..I/

LCL _ _ _ _
AD

RIC

TLIF/9336-BO

(a) Remote Read Timing (RAE = 0)
Arbitration

Acc.ss

Termination

R[t.I-WR~~_ _+-_______~____...I~
Ct.l D

7lZllI

XACK

,'--+-----~/
I

LCL
RIC

WllZ

)

''--(

New RIC

TLIF/9336-B1

(b) Remote Write Timing (RAE = 0)

4.1.2 Access Types
There are four types of accesses an RP can make of the
BCP:
-Remote Interface Control Register (RIC!
-Data Memory (DMEM)
-Program Counter (PC)
-Instruction Memory (IMEM)
An access of (RIC! is accomplished by asserting RAE and
REM-RD or REM-WR with the CMD pin asserted high. The
Remote Interface Configuration register is accessed
through the AD bus as shown in Figure 4-4(c). A read or
write of (RIC! can take place while the BCP CPU is executing instructions. Timing for this access is shown in Figures
4-4(a) and (b). Note that in the Remote Read Figure 4-4(a),
AD does not transition. This is because the contents of
( RIC! are active on the bus by default. The AD bus is in

TL/F/9336-B2

1-107

,~'r---------------------------------------------------------------------------~
~

('t)

D..

4.0 Remote Interface and

Arbitration System (RIAS).(Continued)

Remote Accesses other than ,to {RIC I are. accomplished
with the CMD pin low in conjunction with asserting RAE low
along with REM-WR or REM-RD being taken low. The type
of access performed is defin~d by the Memory Select bits in
{RICl, as shown in Figure 4-5.

Arbitration

RllZZ

~""'--......i-_~_ _.l..-_ _

:.CMD

76543210
I BIS

I,~s

I FBW I LRILW 1ST

Tennlnlltlon

Access

REM~RD~~__~__________~__~~

XACK

MS1! MSOJ

'"",,--

.LcL

. Memory Select Bits
00 - Data Memory
01 - Instru'ction M~mory
10 - PC low byte
11 - PC high byte'

READ

1
1

RIC

(

FIGURE 4~5:Merriory' Select Bits in {RIC I

RIC

TL/F/9336-63

(a) Remote Read Timing (RAE = 0)

Re~ds or ~rites of Data Memory (DMEM) are preceded by
setting the Memory Select bits in {RICI for a DMEM access: [MS1,O] = OO."After that, the· RP simply reads or
writes to BCP Data Memory as many times as it needs to. A
DMEM access, as well as a (RICI access, can be made
while the BCP CPLJ: i.s executing instructions. All other accesses must be executed with' the BCP CPU stopped.

Arbitration
REM-WR

, CMD

The timing for a Data Memory read and write are shown in
Figure 4-6. The access is initiated by asserting RAE and
REM-RD or REM-WR while CMD is low. The BCP responds
by bringing its address and data lines into TRI-STATE and
allowing the RP to control DMEM. READ is asserted in the
Acces~ Phase of a Remote Read Figure 4-6(a).lt will stay
low.for a minimum of one T-state, but can be extended by
adding programmable data waif states or by taking WAIT
low. WRITE is asserted in the Access Phase with a remote
write. It too is a minimum of one T-state and can be increased by adding programmable wait states or by taking
WAIT I.ow. \. .
" ,

Tennlnlltlon

Access

~,-'__~__________...;-__~r-,

lllllZ

~""'--......i---:""---';'_ _- I -_ _

XACK

"'.i-.------~i
1

LcL ________J~r--~---~~\~___
WRITE

AD·

i
1
1

RiC

'---~1

)

RIC

TL/F /9336-64

(b) Remote Write Timing (RAE = 0)

Figure 4-7(c) shows the data path from the Progra~ Counter to the AD bus. Both high and. low PC bytes can be written or read through AD. The RP has independent control of
the high. and low bytes' of the Program Counter....:the· byte
being ac~~ssed is specified in the Memory Select bits. The
high byte, of the. PC is accessed by setting [MS1-0] = 11.
Setting [MS1-0] = 10 allolNs access to the low byte of the
PC"After the Memory Select bits are set by a Remote Write
to {RIC I; the byte selected can be read or written by the RP
by executing a Remote Access with CMD low. Remote accesses t~ both the high and low bytes of the PC;as well as
the instruction memory access must be executed with the
BCP CPU· idle.' Four accesses by the RP are ,necessary to
read or write both the high and low bytes of the PC. Timing
for a PC access is shown in Figure 4-7(a) and (b). The PC
becomes valid on a Remote Read (a) one T-state after [C[
rises and one T-state befOre XACK rises. AD is in TRISTATE whil.e. LC?L ishigh for a Remote Write (b)., Time in the
Access Phase is two T-states if WAIT is not asserted.

FIGURE 4·6. Generic DMEM Access
Timing for an IMEM access is shown in Figure 4-8(a) and
(b). As before, the Memory Select bits are first set to instruction memory:. [MS1-0] = 01. It is only necessary to set
[MS1-0] once for repeated IMEM accesses. (Instruction
Memory is the powf,3r-up Memory Selection state.) A simple
state machine keeps track of which instruction byte is expected next-low or high byte.' The state machine powers
up looking for the low instruction byte and every IMEM access causes this state ,machine to switch to the alternate
byte. Accesses other than to IMEM will not cause the state
machine to switch to the alternate byte, but writing 01 to the
.Memory ?electbits in (,RIOUi.e. [MS1-0]'"", 01,pointingto
IMEM) Will always force the state machine tothe"low,byte
state". This way the Instruction word boundary can be resElt
without resetting the 80~; When the BOP is reset the state
machine will also be forced to the~'low bYte state:"
Figure 4-8(a) shows a Remote Read of Instruction memory.
Both the low byte, then the high byte can be seen on back
to back remote reads: An instruction byte becomes active
on the AD bus one T-state after [C[ rises and is valid when
XACK rises. This time period will be a minimum of one
T-state, but can be extended up to three more T-states by
instruction wait states.
'.

Instruction memory (IMEM) is accessed through another internal path: from .AD to the I bus, shown in Figure 4-8(c).
The memory is accessed first low byte, then high byte. Low
and high bytes of the 16-bit I bus are alternately accessed
for Remote Reads. An 8-bit holding register, ILAT, retains
the low byte until the high byte is written by the Remote
Processor for the, write to IMEM. The. BCPincrements the
PC after the high byte has been accessed.

1-108

4.0 Remote Interface and Arbitration System (RIAS) (Continued)
Arbitration

ACCI.,

REM-RD~~__~____________~_____

CMDD.,~_.:..-_ _ _ _....:.._ _

XACK

ffi _ _ _ _....J~
AD ___R_IC________-JX~

________

(a) Remote Read Timing (RAE = 0)
Arbitration

T.rmlnatlon

Acc"s

REM-WR~

IlllE

CMDD.,
1

XACK

ffi

(I
1

"
1

RIC

(

RIC
TLlF/9336-66

(b) Remote Write Timing (RAE = 0)

1-,..-..

~tlIA15- 8

.........-tl..... 1A7-0

TL/F/9336-67

1·109

•

m
"'11:1'

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

a..

Arbitration

Access

Termination

REIA-RD~

'i:,>-

Arbitration

I
. I

\
!(IiiJ}71iJA

I •.

t.,

CIAO"

Access

Termination

IlllE

XACK~

ill
IA

RIC

);

PC+1

It.tEIA 10

RIC

It.tEIA hi

X
TL/F19336-88

(a) Remote Read Timing (RAE ~ 0)
Arbitration

Termination

Access

REIA-WR~

I
I
. I

CIAO"

Arbitration

.\.

'{@J.i.ii~

Access

'.y,

IlllE
I

ill

(

XACK

Termination

I
I
I ..

XEl

I;,

I
I

iWR
AD

-'-I
I
I

RIC

(

RIC

'-'-----1

(

RIC

TL/F/9336-89

(b) Remote Wr~te Ti l1l lng (RAE = 0)

TL/F/9336-90

4.0 Remote Interface and Arbitration System (RIAS) (Continued)
In addition, WAIT can delay the rising edge of XACK indefinitely. One T-state after XACK rises, I RIC I will once again
be active on AD. Timing is similar for a Remote Write. AD is
in TRI-STATE while LCL is high. LCL is asserted for a minimum of three T-states, but can be extended by instruction
wait states and the WAIT pin. IWR clocks the instruction
into memory during the write of the high byte. The Instruction Address (PC) is incremented about one T -state after
LCL falls on a high byte access for both Remote Reads and
Writes.

es and one half T-state later LCL falls. The BCP can use the
buses one T-state after LCL falls. The minimum time (no
wait states, no arbitration delay) the BCP CPU could be prevented from using the bus is four T-states in the Latched
Read Mode.
A Buffered Read prevents the BCP CPU from using the bus
during the time RP is allocated the buses. This time period
begins when LCL rises and ends when REM-RD is removed. If the REM-RD is asserted longer than the minimum
Buffered Read execution time (four T-states), then the BCP
may be unnecessarily prevented from using the buses.
Therefore, if there are no overriding reasons to use the Buffered Read Mode, the Latched Read Mode is preferable.

Soft-loading Instruction Memory is accomplished by first
setting the BCP Program Counter to the starting address of
the program to be loaded. The Memory Select bits are then
set to IMEM. BCP instructions can then be moved from the
Remote Processor to the BCP-Iow byte, high byte-until
the entire program is loaded.

There are three Remote Write Modes-two require buffers
and one requires latches. The timing for the writes utilizing
buffers is shown in Figure 4-10. The Slow Buffered Write (a)
is handshaked in· the same manner as the Buffered Read
and thus has the same timing. The Fast Buffered Write has
similar timing to the Latched Read. This timing similarity exists because the BCP terminates the remote access without
waiting for the RP to deassert REM-WR.

4.1.3 Interface Modes
The Remote Interface and Arbitration System will support
TRI-STATE buffers or latches between the Remote Processor and the BCP. The choice between buffers and latches
depends on the type of system that is being interfaced to.
Latches will help prevent the faster system from slowing to
the speed of the slower system. Buffers can be used if the
Remote Processor (RP) requires that data be handshaked
between the systems.

In both cases, XACK falls a short delay after REM-WR falls
and LCL rises when the RP is given the buses. One T-state
after LCL rises, INT-WRITE falls. The termination in the
Slow Buffered Write mode keys off REM-WR rising, as
shown in Figure 4-10(a). INT-WRITE rises a prop-delay later
and LCL falls one T-state later. The Fast Buffered Write,
shown in Figure 4-10(b), begins the Termination Phase with
the rising edge of XACK. INT-WRITE rises at the same time
as XACK, and LCL falls one T-state later. The BCP can
begin a local access one T-state after LCL transitions.

Figure 4-9 shows the timing of Remote Reads via a buffer
(a) and a latch (b) (called a Buffered Read and Latched
Read). The main difference in these modes is in the Termination Phase. The Buffered Read handshakes the data
back to the RP. When the BCP deasserts XACK, data is
valid and the RP can deassert REM-RD. Only after REM-RD
goes high is LCL removed. In the Latched Read Figure
4-9(b) XACK rises at the same time, but the Termination
Phase completes without waiting. for the rising edge of
REM-RD. One half T-state after XACK rises, INT-READ ris-

A Fast Buffered Write is preferable to the Slow Buffered
Write if RP's write cycles are slow compared to the minimum Fast Buffered Write execution time. The Fast Buffered
Write assumes, though, that data is available to the BCP by
the time INT-WRITE rises.

~
XACK

ill

~------/-----

/
~'--l--

-----'

,'-----

'-------'
Arbitration

Access

Termination

Arbitration

TL/F/9336-91

''-__
--1
TermInation
Access
TL/F/9336-92

(a) Buffered Read

(b) Latched Read
FIGURE 4-9. Read from Remote Processor

III
1-111

4.0 Remote Interface and Arbitration System (RIAS) (Continued)

XACK

LCL

---Arbitration

Access

Termination

TL/F/9336-93

(a) Slow Buffered Write
REM - WR

XACK

I
I
I

LCL

INT- WRITE
Arbitration

Access

Termination

TL/F/9336-94

(b) Fast Buffered Write
FIGURE 4-10. Buffered Write from Remote Processor
in both Buffered Write Modes, XACK is asserted to wait the
RP. The Latched Write Mode makes it possible for the RP to
write to the BCP without getting waited. The timing for the
Latched Write Mode is shown in Figure 4-11. When the Remote Processor writes to the BCP, its address and data
buses are externally latched on the rising edge of REM-WR.
Even though REM-WR has been asserted XACK does not

switch. The BCP only begins remote access execution after
the trailing edge of REM-WR. Since the RP is not requesting
data back from the BCP, it can continue execution without
waiting for the BCP to complete the remote access. After
REM-WR is deasserted, WR-PEND is taken low to prevent
overwrite of the latches. A minimum of two T-states later
LCL switches and AD, A, and the external address latch go
into TRI-STATE, allowing the latches which contain the remote address and data to become active. If the RP attempts
to initiate another access before the current write is complete, XACK is taken low to wait the RP and the address
and the data are safe because WR-PEND prevents the
latches from opening. The Access Phase ends when
INT-WRITE rises and the data is written. One T-state later,
[C[ falls and one T-state after that WR-PEND rises. If another access is pending, it can begin in the next T-state.
This is indicated by XACK rising when WR-PEND rises.

XACK

ill

----1----.1

A minimum BCP/RP interface utilizes four TRI-STATE buffers or latches. A block diagram of this interface is shown in
Figure 4-12. The blocks A, B, C, and D indicate the location
of buffers or latches. Blocks A and B isolate 16 bits of the
RP's address bus from the BCP's Data Address bus. Two
more blocks, C and D, bidirectionally isolate 8 bits of the
RP's data bus from the BCP AD bus.

'----1,---I

Arbitration

Access Phase

: Termination
TL/F/9336-95

FIGURE 4-11. Latched Write from Remote Processor

1-112

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

~~----------------------------~I

Bep

It.4Et.4

At-r_~r--'"":>C""'""-----..,j
Dt.4Et.4
AD

ADDR ~______________- - I

REt.40TE
PROCESSOR

DATA I'\r-------."----------------J
TL/F/9336-96

FIGURE 4-12. Minimum BCP/Remote Processor Interface
The BCP Remote Arbitrator State Machine (RASM) must
know what hardware interfaces to the RP in order to time
the remote accesses correctly. To accomplish this, three
Interface Mode bits in (RIC} are used to define the hardware interface. These bits are the Latched Write bit [LWl,
the Latched Read bit [LR] and the Fast Buffered Write bit
[FBW]. See Figure 4-13.
765432

1 BIS 1SS I, FBW 1 LR 1 LW

and [FBW] = 1. designates a Fast Buffered Write. A
Latched Write is accomplished by using latches for blocks
A, B, and C and setting [LW] = 1.
4.1.4 Execution Control
The BCP can be started and stopped in two ways. If the
BCP is not interfaced to another processor, ilcan be started
by pulsing RESET low while both REM-RD and AEM-WA
are low. Execution then begins at location zero. If there is a
Aemote Processor interfaced to the BCP, a write to (AIC}
which sets the start bit [STAT] high will begin execution at
the current PC location. Writing a zero to [STAT] stops execution after the current instruction is completed. A SingleStep is accomplished by writing a one to the Single-Step bit
[SS] in (RIC}. This will execute the instruction at the current
PC, increment the PC, and then return to idle. [SS] returns
low after the single-stepped instruction has completed. [SS]
is a write only bit and will always appear low when (AIC} is
read.
Two pins (WAIT and IT5Ci<), and one register bit, [LOR],
can also affect the BCP CPU or RIASexecution. The WAIT
pin can be used to add wait states to a remote access.
When WAIT must be asserted low to add wait states is dependent on which remote access mode is being used. The
information needed to calculate when WAIT must be asserted to add wait states, is contained within the individual descriptions of the modes in the next section (4.2 RIAS Functional Description).

1 MS1 1 MSO I

Interface Mode Bits
- 0 - - Buffered Read
- 1 - - Latched Read
o - 0 - Slow Buffered Write
1 - 0 - Fast Buffered Write
X - 1 - Latched Write
FIGURE 4-13. Interface Mode Bits
All combinations of Remote Reads or Writes with buffers or
latches can be configured via the Interface Mode bits. A
Buffered Read is accomplished by using a buffer for block D
and setting [LR] ;; o. Conversely, using a latch for block D
and setting [LR] = 1 configures the RASM for Latched
Reads. Using buffers for blocks A, B, and C and setting
[LW] = 0 allows either a Slow or Fast Buffered Write. Setting [FBW] = 0 configures RASM for a Slow Buffered Write

1-113

4.0 Remote Interface and Arbitration System (RIAS)
Programmed wait states delay when WAIT must be asserted since programmed wait states are inserted before WAIT
is tested to see if any more wait states should be added.
LOCK prevents local accesses of Data Memory. If LOCK is
asserted a half T-state before T1 of a BCP instruction cycle,
further local accesses will be prevented by waiting the Timing Control Unit. The Timing Control Unit (TCU) is the BCP
CPU sub system responsible for timing each instruction. For
a more detailed description of the operation of LOCK, refer
to the CPU Timing section. [LOR] allows the BCP to prevent
remote accesses. Once [LOR], located in {ACR I, is set
high, further remote accesses are waited by XACK remaining low.

(Continued)

Also provided is a memory arbitration example in the form of
a timing diagram for each of the five modes. These examples show back to back local accesses punctuated by a
remote access. Both the state of RASM and the Timing
Control Unit are listed for every clock at the top of each
timing diagram. The RASM states listed correspond to the
flow charts. The Timing Control Unit states are described in
Section 2.2.2, Timing portion of the data sheet.
4.2.1 Buffered Read
The unique feature of this mode is the extension of the read
until REM-RD is deasserted high. The complete flow chart
for the Buffered Read mode is shown in Figure 4-14. Until a
Remote Read is initiated (RAE·REM-RD true), the state machine (RASM) loops in state RSA1. If a Remote Read is
initiated and [LOR] is set high, RASM will move to state
RSA2. Likewise, if a Remote Read is initiated while the buses have been granted locally (Le., Local Bus Request = 1),
RASM will move to state RSA2. The state machine will loop
in state RSA2 as long as [LOR] is set high or the buses are
granted locally. If the BCP CPU needs to access Data Memory while in either RSA state (and LOCK is high), it can still
do so. A local access is requested by the Timing Control
Unit asserting the Local Bus Request (lCl-BREQ) signal. A
local bus grant will be given by RASM if the buses are not
being used (as is the case in the RSA states).

Though the BCP CPU runs independently of RIAS there is
some interaction between the two systems. [LOR] is one
such interaction. In addition, two bits allow the BCP CPU to
keep track of remote accesses. These bits are the Remote
Write bit [RW] and the Remote Read bit [RR], and are located in {CCR[6-5]}. Each bit goes high when its respective remote access to DMEM reaches its Termination
Phase. Once one of these bits has been set, it will remain
high until a "1" is written to that bit to reset it low.
4.2 RIAS FUNCTIONAL DESCRIPTION
In this section, the operation of the Remote Arbitration State
Machine (RASM), is described in detail. Discussed, among
other things, are the sequence of events in a remote access, arbitration of the data buses, timing of external signals, when inputs are sampled, and when wait states are
added. Each of the five Interface Modes is described in
functional state machine form. Although each interface
mode is broken out in a separate flow chart, they are all part
of a single state machine (RASM). Thus the first state in
each flow chart is actually the same state.

XACK is taken low as soon as RAPREM-RD is true, regardless of an ongoing local access. If [lOR] is low, RASM
will move, into RSs on the next clock after RAE·REM-RD is
true and there is no local bus request. No further local bus
requests will be granted until the remote access is complete
and RASM returns to RSA. Half a T·stateafter entering RSs
the A· bus (and AD bus if the. access is to Data Memory)
goes into TRI-STATE.

The functional state machine form is similar to a flow chart,
except that transitions to a new state (states are denoted as
rectangular boxes) can only occur on the rising edge of the
internal CPU clock (CPU-CLK). CPU-CLK is high during the
first half of its cycle. A state box can specify several actions,
and each action is separated by a horizontal line. A signal
name listed in a state box indicates that that pin will be
asserted high when RASM has entered that state. Signals
not listed are assumed low.

On the next CPU-ClK, RASM enters RSc and LCL is taken
high while XACK remains low. The wait state counters, ilW
and lOW, are loaded in this state from {IW1-0] and [DW2~
01; respectively, in {DCRl-The Abus (and AD jf the access
Is to Data Memory) remains in TRI-STATE and the Access
Phase begins.
The state machine can move into one of several states,
depending on the state of CMD and [MS1-0], on the next
clock. XACK remains low and LCl remains high in all the
possible next states. If CMD is high, the access is to {RICI
and the next state will be RSD1. Since the default state of
AD is {RIC I, it will not transition in this state.

Note: This sometimes necessitates using the inversion of the external pin
name.

This same rule applies to the A and AD buses. By default,
these buses are active. The A bus will have the upper byte
of the last used data address. The AD bus will display
{RIC I. When one of these buses appears in a state box, the
condition specified will be in effect only during that state.
Decision blocks are shown as diamonds and their meaning
is the same as in a flow chart. The hexagon box is used to
denote a conditional state-not synchronous with the clock.
When the path following a decision block encounters a conditional state, the action specified inside the hexagon box is
executed immediately.

The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RS02 or RS03 and the low or high
bytes of the Program Counter, respectively, will be read.
[MS1-0] = 00 designates a Data Memory access and
moves RASM into RS04. READ will be asserted in this state
and A and AD continue to be in TRI-STATE. This allows the
Remote Processor to drive the Data Memory address for
the read. Since DMEM is subject to wait states, RS04 is
looped upon until all the wait states have been inserted.

1-114

4.0 Remote Interface and Arbitration System (RIAS)
~

1-115

(Continued)

DP8344B
RAS~

state

TCU state

RSA

RS A

RSA

RS 8

TWd

RS C

TWr

RS D

RS E

TWr

_ TWr .

TWr

RS E

TWr

RS E

RSE

_ TWr

TWr

RSr

TWr

RS A

RSA

TWr

RSA

RS A

TWd

(:)
~
(I)

CLK-OUT

3
o

...
...
...
(I)

REiHffi

::J

(I)

....
S»

LCL

(I)

S»
::J

XACK

...l>
::;
...S»

READ

...

ALE

o·::J

BCP BUS

........en

ADDR/DATA

(0-7)

IIIIIIXLOCALADDRX

...

RWOTE DATA

LOCAL DATA

(I)

ADDRESS

(0-15)

11111 IX

RE~OTE

LOCAL ADDRESS

-»
3

ADDRESS

-en

REt.lOTE BUS
RE~OTE

ADDRESS

oo
~

RE~OTE

DATA

s·

DATA

L - LOCAL ~E~ORY READ ~

L..-_ _ _ _ _ _ _ _ _ _

RE~OTE

READ _ _ _ _ _ _ _ _ _ _- - - l

LOCAL

~E~ORY READ ~
TUF/9336-27

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RIC} Contents: XXXOX100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-WR =1
LOCK
=1

FIGURE 4-15. Buffered Read of Data Memory by Remote Processor

4.0 Remote Interface and Arbitration System (RIAS)
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for an IMEM
access depend on if RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HI B).
If HIB is low, the next state is RS05 and the low instruction
byte is MUXed to the AD bus. If HIB is high, the high instruction byte is MUXed to AD and RS06 is entered. An IMEM
access, like a OM EM access, is subject to wait states and
these states will be looped on until all programmed instruction memory wait states have been inserted.

(Continued)

From RSE4, RASM enters RSF2 on the CPU-ClK after
RAE*REM-RD is deasserted. In RSF2, [C[ remains high
while both A and AD remain in TRI-STATE.
From RSF1, the next clock will return the state machine
back to state RSA1 where it will loop until another Remote
Access is initiated. If the access was to IMEM, then the last
action of the remote access before returning to RSA is to
switch HIB and increment the PC if the high byte was read.
From RSF2, the next CPU-ClK returns to state RSA3 where
low, but A and AD remain TRI-STATE for the
first half T-state of RSA3. If no Remote Access is initiated
the next state will be RSA 1 where it will loop until another
Remote Access is initiated.
The example in Figure 4-15 shows the BCP executing the
first of two consecutive Data Memory reads when REM-RD
goes low. In response, XACK goes low waiting the remote
processor. At the end of the first instruction, although the
BCP begins its second read by taking ALE high, the RASM
now takes control of the bus and takes lCl high at the end
of T1. A one T-state delay is built into this transfer to ensure
that READ has been deasserted before the data bus is
switched. The Timing Control Unit is now waited, inserting
remote access wait states, TWr, as RASM takes over.

ICC returns

Note: Resetting the SCP will reset HIS (i.e., HIS = 0). Writing 01 to the
Memory Select bits in IRICI (i.e., [MS1-0] = 01, pointing to IMEM)
will also force HIB to zero. This way the instruction word boundary
can be reset without resetting the SCPo

After all of the programmed wait states are inserted in the
RSo states, more wait states may be added by asserting
WAIT Iowa half T-state before the end of the last programmed wait state. If there are no programmed wait
states, WAIT must be asserted Iowa half T-state before the
end of RSo to add wait states. If WAIT remains low, the
remote access is extended indefinitely. All the RSo states
move to their corresponding RSE states on the CPU-ClK
after the programmed wait state conditions are met and
WAIT is high. The RSE states are looped upon until RAE*
REM-RD is deasserted. lCl remains high in all RSE states
and A remains in TRI-STATE. AD will also stay in TRISTATE if the access was to DMEM. XACK is taken back
high to indicate that data is now valid on the read. If XACK is
connected to a Remote Processor wait pin, it is no longer
waited and can now terminate its read cycle. This state begins the Termination Phase. The action specified in the conditional box is only executed while RAE*REM-RD is asserted-a clock edge is not necessary. In all RSE states except
RSE4 (OM EM) lCl will fall a propagation delay after
RAE*REM-RD is deasserted. In RSE4, lCl remains high
through the whole state.
On the CPU-ClK after RAE*REM-RD is deasserted. RASM,
enters RSF1 from every RSE state except RSE4 (OM EM). In
RSF1. ICC remains low and A remains in TRI-STATE while
CPU-ClK is high (Le., for the first half T-state of RSF1).

The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. The Remote Processor will respond by deasserting
REM-RD high to which the BCP in turn responds by deasserting READ high. Following READ being deasserted high,
the BCP waits till the end of the next T-state before taking
lCl low, again ensuring that the read cycle has concluded
before the· bus is switched. Control is then returned to the
Timing Control Unit and the local memory read continues.

4.2.2 Latched Read
This mode differs from the Buffered Read mode in the way
the access is terminated. A latched Read cycle ends after
the data being read is valid and the termination doesn't wait
for the trailing edge of REM-RD. Therefore the Arbitration
and Access Phases of the latched Read mode are the
same as for the Buffered Read mode. The complete flow
chart for the latched Read mode is shown in Figure 4-16.

1-117

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

[MS1-0] = 00 designates a Data Memory access and
moves RASM into RS04. READ will be asserted low in this
state and A and AD continue to be tri-stated. This allows the
Remote Processor to drive the Data Memory address for
the read. Since OM EM is subject to wait states, RS04 is
looped upon until all the wait states have been inserted.

Until a Remote Read is initiated (RAE*REM-RD true), the
state machine (RASM) loops in state RSA1. If a Remote
Read is initiated and [LOR] is set high, RASM will move to
state RSA2. Likewise, if a Remote Read is initiated while the
buses have been granted locally (Le., Local Bus Grant = 1),
RASM will move to state RSA2. The state machine will loop
in state RSA2, as long as [LOR] is set high or the buses are
granted locally. If the BCP CPU needs to access Data Memory while in either RSA state (and LOCK is high), it can still
do so. A local access is requested by the Timing Control
Unit asserting the Local Bus Request (LCL-BREQ) signal. A
local bus grant will be given by RASM if the buses are not
being used (as is the case in RSA).

The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for the IMEM
access depend on if RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB).
If HIB is low, the next state is RS05 and the low instruction
byte is MUXed to the AD bus. If HIB is high, the high instruction byte is MUXed to AD and RS06 is entered. An IMEM
access, like a DMEM access, is subject to wait states and
these states will be looped on until all programmed instruction memory wait states have been inserted.

XACK is taken low as soon as RAE*REM-RD is true, regardless of an ongoing local access. If [LOR] is low, RASM
will move into RSs on the next clock after RAE*REM-RD is
asserted and there is no local bus request. No further local
bus requests will be granted until RASM enters the Termination Phase. If the BCP CPU initiates a Data Memory access
after RSA, the Timing Control Unit will be waited and the
BCP CPU will remain in state T Wr until the remote access
reaches the Termination Phase. Haifa T-state after entering
RSs the A bus (and AD bus if the access is to Data Memory)
goes intoTRI-STATE.

Note: Resetting the ecp will reset HIS (i.e., HIS' "" 0). Writing 01 to the
Memory Select bits in (RICI [I,e" [MS1-0] "" 01, pointing to IMEM)
will also force HIS to zero. This way the instruction word boundary
can be reset without resetting the BCP.

After all of the programmed wait states are inserted in the
RSo states, more wait states may be added by asserting
WAIT low a half T -state before the end of the last programmed wait state. If there are no programmed wait states
WAIT must be asserted Iowa half T-state before the end of
RSo to add wait states. If WAIT remains low, the remote
access is extended indefinitely. All the RSo states move to
their corresponding RSE states on the CPU-CLK after the
programmed wait state conditions are met and WAIT is
high. LCL remains high in all RSE states and A remains in
TRI-STATE (and AD if the access is to Data Memory).
XACK returns high in this state, indicating that data is valid
so that it can be externally latched. The action specific to
each RSo state remains in effect during the first half of the
RSE cycle (Le. READ is asserted in the first half of RSE4).
This half T -state of hold time is provided to guarantee data
is latched when XACK goes high. This state begins the Termination Phase.

On the next clock, RASM enters RSc and LCL is taken high
while XACK remains low. The wait state counters, ilW and
iow, are loaded in this state from [lW1-0] and [DW2-0],
respectively, in {DCRl. The Abus (and AD if the access is
to Data Memory) now remains TRI-STATE and the Access
. .
Phase begins. .
The state machine can move into one of several states,
depending on the state of CMD and [MS1-01. on the next
clock. XACK remains low and i l l remains high in all the
possible next states. If CMD is high, the access is to (RIC}
and the next state will be RS01. Since the default state of
AD is (RIC l. it will not transition in this state. The five other
next states all have CMD low and depend on the Memory
Select bits. If [MS1-0] is 10 or 11 the state machine will
enter either RS02 or RS03 and the low or high bytes of the
Program Counter, respectively, will be read.

1-118

(1)

...3
...

(1)

::::s

(1)
'""I

-to

(1)

::::s

a.
l>
'""I
C"

::;:

...
o·
'""I

::::s

en
'<
en

...

(1)

3
'ij

l>
en

'o0
~

:i"

c::

.9:

t.-:....

FIGURE 4-.16. Flow Chart of ~tched Read Mode

TUF/9336-98

8tt&SdO

DP83448
HAS.. stat.
TCU stat.
ClK-ouT

RSA
Tl

RSA

RSB

RSA

RSc

RSD

RSo

RSE

RSr

RSo

RSA

TWr

TWd

I-. I-. I-. I-. I-. I-. I-. I-. I-. I-. I-. I-. I-.
TX

TWd

TWr

(:)

:II
CD

...

....

REhl-RD

LCl

....CD
D)

XACK

:::s

.
....

~
tr

READ

::;

ALE

......
......
I\J
0

o
:::s
en

ADDR/DATA

...

(0-7)

A(~~) 141UIIX

_ru
OATA

LOCAL ADDRESS

IXIIIIIX

REMOTE ADDRESS

rRafOTE BUS

R~ott ~

~zzzzzzzzzzzzz>zzzzzzzzzzzzzzzzzzzx
LOCAL MEMORY READ

REMOTE READ

::D

i>
en

~+
II

'o0

:r
c:
CD

.s
BCP INT. OP.
TVF/9336-30

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-(RIC) Contents: XXX1X100
-[LOR] = 0

Other BCP Control Signals:
=0
RAE
CMD
=0
REM-WR =1
=1
LOCK

FIGURE 4-17. Latched Read of Data Memory by Remote Processor

4.0 Remote Interface and Arbitration System (RIAS) ,(Cortinued).
On the next clock the state machine will enter RSF and LCL
will return low. The A bus (and AD bus if the access is to
data memory) remains in TRI-STATE for the first half
T-state of RSF. After the first half of RSF, the Remote Processor is no longer using the buses and the BCP
CPU will be granted the buses if LCL-BREQ is asserted. If a
local bus request is made, a local bus grant will be given to
the Timing Control Unit. If the preceding access was a read
of IMEM, then HIB is switched and if the access was to the
high byte of IMEM then the PC is incremented. If RAE*
REM-RD is deasserted at this point, the next clock will bring
RASM back to RSA where it will loop until another Remote
Access is initiated. RSG is entered if RAE*REM-RD is still
true. RASM will loop in RSG until RAE*REM-RD is no longer
active at which time the state machine will return to RSA·
In Figure 4-17, the BCP is executing the first of two Data
Memory reads when REM-RD goes low. In response, XACK
goes low, waiting the Remote Processor. At the end of the
first instruction, although the BCP begins its second write by
taking ALE high, the RASM now takes control of the bus
and deasserts [C[ high at the end of T1· A one T-state
delay is built into this transfer to ensure that READ has been
deasserted high before the data bus is switched. The Timing
Control Unit is now waited, inserting' remote access wait
states, TWr, as RASM takes over.
The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, T Wd later, having satisfied the memory access
time. READ returns high a half T-state later, ensuring sufficient hold time, followed by LCL being reasserted low after
an additional half T-state, transferring bus control back to
the BCP. The Remote Processor responds to XACK returning high by deasserting REM-RD high, although by this time
the BCP is well into its own memory read.

and iow, are loaded in this state from [IW1-0] and [DW20], respectively, in IOCR I. The A and AD buses now remain
in TRI-STATE and the Access Phase begins. If the Remote
Access is to IMEM and the high instru9tion byte flag is set
(Le., HIB = 1), then IWR is asserted low in RSc. The state
machine can move into one of several states, depending on
the state of CMDand [MS1-01. on the next clock. XACK
remains low and, LCL remains high in' all the possible next
states. If CMD is high, the access is to IRICI and the next
state will be RS01' The path from AD to IRICI opens in this
state. Any remote access mode changes made by this write
will not take effect until one T-state after the completion of
the present write.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11, the state
machine will enter either RS02 or RS03 and the,low or high
bytes of the Program Counter, respectively. will be written.
[MS1-0] equal to 00 designates a Data~ Memo~ access
and moves RASM into RS04. WRITE will be asserted in this
state and A and AD continue to be tri-stated. This allows the
Remote Processor to drive the Data Memory address and
data buses for the write. Since DMEM is subject to wait
states, RS04 is looped upon until all the programmed data
memory wait states have been inserted.

4.2.3 Slow Buffered Write
The timing for this mode ,is the same as the Buffered Read
mode. The complete flow chart for the Slow Buffered Write
mode is shown in Figure 4-18. Until a Remote Write is initiated (RAE*REM-WR true), the state machine (RASM) loops
in state RSA1. If a Remote Write is initiated and [LOR] is set
high, RASM will move to state RSA2. Likewise, if a Remote
Write is initiated while the buses have been granted locally
(Le., Local Bus Grant = 1), RASM will move to state RSA2.
The state machine will loop in state RSA2 as long as [LOR]
is set high or the buses are granted locally. If the BCP CPU
needs to access Data Memory while in either RSA state
(and LOCK is high), it can still do so. A local access is requested by the Timing Control Unit asserting the Local Bus
Request (LCL-BREQ) signal. A local bus grant will be given
by RASM if the buses are not being used (as is the case in
the RSA state).
XACK is taken low as soon as RAE*REM-WR is true, regardless of an ongoing local access. RASM will move into
RSs on the next clock after RAE*REM-WR is asserted and
there is no local" bus request and [LOR] = O. No further
local bus requests will be granted until the remote access is
complete and RASM returns to RSA' If the BCP CPU initiates a Data Memory access after RSA, the Timing Control
Unit will be waited and the BCP CPU will remain in state T Wr
until completion of the remote access. Haifa T-state after
entering RSs the A and AD buses go into TRI-STATE.
'

The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on whether RASM is expecting the low byte or high
byte. Instruction words, are accessed low byte, then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB).
IfHIB.is low, the next state is RS05 and the low instruction
byte is written into the holding register, ILAT. If HIB is high,
the high instruction byte is moved to 115-8 and the value in
ILAT is moved to 17-0. At the same time, IWR is asserted
" low, beginning the write to instruction memory. An IMEM
access, like a OM EM access, is' subject to wait states and
these states will be looped on until all programmed Instruction Memory wait states have been inserted.
Note: Resetting the SCP will reset HIS (i.e .• HIS = 0). Writing 01 to.the

On the next CPU-CLK, RASM enters RSc and LCL is taken
high while XACK remains low. The wait state counters, ilW

1-121

Memory Select bits in (RIC) v.e.; [MS1-0] = 01. pointing to IMEM)
will also, force HIS to zero; This way the instruction word boundary
can be reset with~ui resetting the SCPo

After all of the programmed wait states are inserted in the
RSo states, more wait states may be added by asserting
WAIT Iowa half T-state before the end of the last programmed wait state. If there are no programmed wait
states, WAIT must be asserted Iowa half T-state before the
end of RSo to add wait states. If WAIT remains low, the
remote access is extended indefinitely. All the RSo states
move to their corresponding RSE states on the CPU-ClK
after the programmed wait state conditions are met and
WAIT is high. The RSE states are looped upon until RAE*
REM-WR is deasserted. LCL remains high in all RSE states,
but XACK is taken back high to indicate that the remote
access can be terminated. If XACK 'is connected to a Remote Processor wait pin, it can now terminate its write cycle.
This state begins the Termination Phase. The action specified in the conditional box is only executed while RAE*REMWR is asserted-a clock edge is not necessary.
On the CPU-CLK afte~ RAE*REM-WR i$ deasserted, RASM
enters RSF. where LCL remains high and the BCP A and AD
buses are still in TRI-STATE. The next CPU-CLK causes
RASM to move to RSA3' If the access was to 1M EM, then

DP8344B
~

b
:rJ

'RS,u

...o
...

iCl

TRI-STAfE AtAD'RSot

TRt-STAJE At AD I

::J

RSo2

::::.

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...m

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CD

TL/F /9336-99

fIGUFtE'ft~~· FJ§W··~taiil't§f.~IC)W.~~ff~fed Wr!te'Mode

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

is set high, RASM will move to state RSA2. Likewise, if a
Remote Write is initiated while the buses have been granted
locally (I.e., local Bus Grant = 1), RASM will move to state
RSA2. The state machine will loop in state RSA2 as long as
[lOR] is set high or the buses are granted locally. If the
BCP CPU needs to access Data Memory while in either RSA
state (and LOCK is high), it can still do so. A local access is
requested by the Timing Control Unit asserting the Local
Bus Request (lCl-BREQ) signal. A local bus grant will be
given by RASM if the buses are not being used (as is the
case in the RSA states).
XACK is taken low as soon as RAE*REM-WR is true, regardless of an ongoing local access. If [lOR] is low, RASM
will move into RSs on the next clock after RAE*REM-WR is
asserted and there is no local bus request. No further local
bus requests will be granted until the BCP enters the Termination Phase. If the BCP CPU initiates a Data Memory access after RSA, the Timing Control Unit will be waited and
the BCP CPU will remain in state TWr until the remote access reaches the Termination Phase. Half a T-state after.
entering RSs the A and AD buses go into TRI-STATE.

the last action of the remote access before moving to RSA3
is to switch HIB and increment the PC if the high byte was
written. In RSA3, LCL goes low while A and AD remain in
TRI-STATE for the first half of RSA3. If no new Remote
access is initiated the next clock brings the state machine
back to RSA1 where it will loop until a Remote Access is
initiated.
In Figure 4-19, the BCP is executing the first of two consecutive Slow Buffered Writes to Data Memory when REM-WR
goes low. In response, XACK goes low, waiting the Remote
Processor. At the end of the first instruction, although the
BCP begins its second write by taking ALE high, RASM now
Takes control of the bus and deasserts LCL high at the end
of T 1. A one T-state delay is built into this transfer to ensure
that WRITE has been deasserted high before the data bus
is switched. The Timing Control Unit is now waited, inserting
remote access wait states, TWr, as RASM takes over.
The remote address is permitted one T-state to settle on the
BCP address bus before WRITE goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. The Remote Processor will respond by deasserting
REM-WR high to which the BCP in turn responds by deasserting WRITE high. Following WRITE being deasserted
high, the BCP waits till the end of the next T-state before
asserting LCL low, again ensuring that the write cycle has
concluded before the bus is switched. Control is then returned to the Timing Control Unit and the local memory write
continues.

On the next CPU-ClK, RASM enters RSc and ill is taken
high while XACK remains low. The wait state counters, ilW
and iow, are loaded in this state from IIW1-0] and [DW2~<
0], respectively, in !DCRL The A and AD buses remain in
TRI-STATE and the Access Phase begins. If the Remote
Access is to IMEM and the high instruction byte flag is set
(I.e., HIB =. 1), then IWR is asserted low in RSc.
The state machine can move into one of several states depending on the state of CMD and [MS1-0] on the next
clock. XACK and lCL in all the possible next states. If CMD
is high, the access is to {RIC J and the next state will be
RS01. The path from AD to {RIC J opens in this state. Any
remote access mode changes made by this write will not
take effect until one T-state after the completion of the present write.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RS02 or RS03 and the low or high
bytes of the Program Counter, respectively, will be written.

4.2.4 Fast Buffered Write
The timing for the Fast Buffered Write mode is very similar
to the timing of the Latched Read. The major difference is
the additional half clock that AD is active in the Latched
Read mode that is not present in the Fast Buffered Write
mode. The Fast Buffered Write cycle ends after the data is
written and the termination doesn't wait for the trailing edge
of REM-WR. Therefore the Arbitration and Access Phases
of the Fast Buffered Write mode are the same as for the
Latched Read mode.
The complete flow chart for the Fast Buffered Write mode is
shown in Figure 4-20. Until a Remote Write is initiated
(RAE*REM-WR true), the state machine (RASM) loops in
state RSA1' If a Remote Write is initiated and [lOR]

[MS1-0] = 00 designates a Data Memory access and
moves RASM into RS04. WRITE will be asserted in this

1-123

DP83448
~

RASM state
TCU state

RS A

RSA

RS A

TWd

TWr

IRSO
TWr

RS O

RS[

TWr

RS[

RS[
. TWr

- - - - - - - - - -

I
CLK-OUT

RS
Tl

RS c

TWr
I

RS[

RS r

RS A

RSA

RS A

TWr

TWd

:IJ
(I)

...
......

(I)

REM-WR

::::J

(I)

....

LCL

Q)
(')

(I)
Q)

XACK

::::J
Co

...l>tT

WRITE

...o·...

::;:

ALE

AD DR/DATA I A I I I I XLOCAL ADDRX
(O-7)

'~~~

(fllX

LOCAL DATA I

X I I I I I I I I I I I I I I I I I I I I I I I I I I X

REMOTE DATA

::::J

...

'<
LOCAL ADDRESS

t t

'OOR~ ~

til

REMOTE ADDRESS

(I)

REMOTE BUS

:IJ

R~OITADM~S

OATA;JJ/JJ/JJ/JJJJ/=/JJ>/JJJJJJJJJJJJJJJJ/JJ/~",TE

OAlA

'00
~

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LOCAL MEMORY WRITE

L......_ _ _ _ _ _ _ _ _ _

(l)

REMOTE WRITE _ _ _ _ _ _ _ _ _ _--l

.e,
TLlF/9336-28

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-(RIC} Contents: XXOX0100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-RD =1
LOCK
=1

FIGURE 4·19. Slow Buffered Write to Data Memory by Remote Processor

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)
On the next clock the state machine will enter RSF and
will return low. The A and AD buses remain in TRI-STATE
for the first half T-state of RSF' After the first half of RSF,
the Remote Processor is no longer using the buses and the
SCP CPU can make an access to Data Memory by asserting
lCl-SREQ. If a local bus request is made, a local bus grant
will be given to the Timing Control Unit. If the preceding
access was a write of IMEM, then HIS is switched and if the
access was to the high byte of IMEM then the PC is incremented. If RAEoREM-WR is deasserted at this point, the
next clock will bring RASM back to RSA where it will loop
until another remote access is initiated. RSG is entered if
RAE"REM-WR is still true. RASM will loop in RSG until
RAE*REM-WR is no longer active at which time the state
machine will return to RSA·
In Figure 4-21, the SCP is executing the first of two Data
Memory writes when REM-WR goes low. In response,
XACK goes low, waiting the Remote Processor. At the end
of the first instruction, although the SCP begins its second
write by taking ALE high, RASM now takes control of the
bus and de asserts lCl high at the end of T1. A one T-state
delay is built into this transfer to ensure that WRITE has
been deasserted high before the data bus is switched. The
Timing Control Unit is now waited, inserting remote access
wait states, TWr, as RASM takes over.
The remote access is permitted one T-state to settle on the
SCP address bus before WRITE goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. WRITE returns high at the same time, and one T-state
later LCl returns low, transferring bus control back to the
SCPo The remote processor responds to XACK returning
high by deasserting REM-WR high, although by this time the
SCP is well into its own memory write.

state and A and AD continue to be tri-stated. This allows the
Remote Processor to drive the Data Memory address and
data buses for the write. Since OM EM is subject to wait
states, RS04 is looped upon until all the programmed Data
Memory wait states have been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on whether RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Syte flag (HIS).
If HIS is low, the next state is RS05 and the low instruction
byte is written into the holding register, ILAT. If HIS is high,
the high instruction byte is moved to 115-8 and ILAT is
moved to 17-0. At the same time IWR is asserted low, beginning the write to instruction memory. An IMEM access,
like a OM EM access, is subject to wait states and these
states will be looped on until all programmed instruction
memory wait states have been inserted.
Note: Resetting tM SC? will reset HIS (I.e., HIS" 0). Writing 01 to the
Memory Select bits in (RICI O.e.• [MS1-0] .. 01. pointing to IMEM)
wUl also force HIS to zero. This way the instruction word boundary
can be reset without resetting the SCPo
After all of the programmed wait states are inserted into
RSo states, more wait states may be added by asserting
WAIT Iowa half T-state before the end of the last programmed wait state. If there are no programmed wait states
WAIT must be asserted Iowa half T-state before the end of
RSo to add wait states. If WAIT remains low, the remote
access is extended indefinitely. All the RSo states converge
to state RSE on the next CPU-ClK after the programmed
wait state conditions are met and WAIT is high. i l l remains
high in all RSE states and A and AD remain in TRI-STATE
as well. XACK returns high in this state, indicating that the
data is written and the cycle can be terminated by the RP.
This state begins the Termination Phase.

II
1-125

DP8344B
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TUF/9336-AO

FtG9RE.f2Q~ •.~oW.·.~~art ott=ast . f)Uff~red:Wrlt~.·Mode

RASt.l state
TCU state

RSA

RS e

RS C

RS O

RS E

RS r

RS G

RS H

RSA

TWd

TWr

TWx

TWd

(:)
lJ
(I)

CLK-OUT

...
.......

(I)
REt.l-WR

(I)

....

LCL

(I)

XACK

:t>
....

WRITE

;::;:

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ADDR/DATA

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LOCAL DATA

(0-7)

(I)

ADDRESS

(0-15)

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REMOTE BUS
ADDRESS

-en

REt.lOTE ADDRESS

()

DATA

o
35·

REt.lOTE DATA

S
L..-_ _ _

LOCAL t.l[t.lORY WRITE - - - - '

L..-_ _ _ _

REt.lOTE WRITE

L - LOCAL IAEt.lORY WRITE ~ L

BCP INT. OP.

--1
TUF/9336-29

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RIC} Contents: XX1X0100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-RD =1
LOCK
=1

FIGURE 4-21. Fast Buffered Write to Data Memory by Remote Processor

8l7l7eSdC

4.0 Remote Interface and Arbitration System (RIAS)
4.2.5 Latched Write

(Continued)

The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on if RASM is expecting the low byte or high byte.
Instruction words are accessed low byte then high byte and
RASM powers up expecting the low Instruction byte. The
internal flag that keeps track of the next expected Instruction byte is called the High Instruction Byte flag (HI B). If HIB
is low, the next state is RSF5 and the low instruction byte is
written into the holding register, ILAT. If HIB is high, the high
instruction byte is moved to 115-8 and the value in ILAT is
moved to 17-0. At the same time, IWR is asserted low and
the write to Instruction Memory is begun. An IMEM access,
like a OM EM access, is subject to wait states and these
states will be looped on until all programmed instruction
memory wait states have been inserted.

This mode executes a write without waiting the Remote
Processor-XACK isn't normally taken low. The complete
flow chart for the Latched Write mode is shown in Figure
4-22. Until a Remote Write is initiated (RAE*REM-WR true),
the state machine (RASM) loops in state RSA. If the BCP
CPU needs to access Data Memory at this time (and LOCK
is high), it can still do so. A local access is requested by the
Timing Control Unit asserting the Local Bus Request
(LCL-BREQ) signal. A local bus grant will be given by RASM
if the buses are not being used (as is the case in RSA).
RASM will move into RSs on the next clock after
RAE*REM-WR is asserted. XACK is not taken low
and therefore the RP is not waited. The state machine will
loop in RSs until the RP terminates its write cycle-until
RAE*REM-WR is no longer true. The external address and
data latches are typically latched on the trailing edge of
REM-WR. A local bus request will still be serviced in this
state.

Note: Resetting the SCP will reset HIS (I.e.• HIS .;. 0). Writing 01 to the
Memory Select bits In (RIC) O.e., [MS1-01 "" 01. pointing to IMEM)
will also force HIS to zero. This way the instruction word boundary
can be reset without resetting the BCP.

All the RSF states converge to a single decision box that
tests WAIT. If WAIT is low then the state machine loops
back to RSF, otherwise RASM will move on to RSG. i l l
remains high and WR-PEND remains low in this state but
the actions specific to the RSF states have ended (I.e.
WRITE will no longer be asserted low).

Next, RASM enters RSc and WR-PEND is asserted to prevent overwrite of the external latches. Since the RP has
completed its write cycle, another write or read can happen
at any time. Any Remote Read cycle (RAE*REM-RD) or
Remote Write cycle (RAE*REM-WR) occurring after the
state machine enters RSc will take XACK low. A local access initiated before or during this state must be completed
before RASM can move to RSo. Once RSo is entered,
though, no further local bus requests will be granted until
RASM enters the Termination Phase. If the BCP CPU initiates a Data Memory access after RSc, the Timing Control
~ni~ will be waited and the BCP CPU will remain in state T Wr
until the RASM.· enters RSH. Half aT-state after entering
RSelhe A and AD buses gointo.TRI-STATE.

The next CPU-ClK moves RASM into RSH, the last state in
the state. machine. i l l returns .Iow .butWR-PEND is still
low. The A and AD buses remain in TRI-STATE for the first
be. taken low if a Remote Access
half of RSH' XACK
is initiated. If the just completed access was to IMEM, HIB
will be switched. Also, the PC will be incremented if the high
byte was written. A local access will be granted if LCLBREQ is asserted in this state.

will

If another Remote Write is pending, the state machine takes
the path to RSs where that write will be processed. A pending Remote Read will return to the RSA in either the Buffered or Latched Read sections (not shown in Figure 4-22)
of the state machine. And if no Remote Access is pending,
the machine will loop in RSA until the next access is initiated.

On the next clock, the state machine enters RSE and ill is
taken high. WR-PEND continues to be asserted low in this
stat~ and the data and instruction wait state counters, iow
andllW. are loaded from [DW27'O] and [lW1-0]. respective~
ly,inlDCRI. The A and AD buses remain in TRI·STATE
and the Access Phase begins. Any remote accesses now
occurring will take XACK low and wait the Remote Processor. If the Remote Access is to IMEM and the high instruc~
tion byteflag is set (i.e:, HI8 =1), then TWR is asserted loW
in RSE.

In Figure 4-23, the BCP is executing the first of two Data
Memory writes when REM-WR goes low. The BCP takes no
action until REM-WR goes back high, latching the data and
making a remote access request. The SCP responds to this
by taking WR-PEND low. At the end of the first instruction
although the BCP begins its second write by taking ALE
high, RASM now takes control of the bus and deasserts
LCL high at the end of T 1. A one T -state delay is built into
this transfer to ensure that WRITE has been deasserted
high before the data bus is switched. Timing Control Unit is
now waited, inserting remote access wait states, T Wr, as
RASM takes over.

The state machine will move into one of several states on
the next clock, depending on the state of CMD and
[MS1-0]. WR-PEND remains low and LCL remains high in
all the possible next states. If CMD is high, the access is to
(RIC} and the next state will be RSF1. The path from AD to
(RIC} opens in this state. Any remote access mode changes made by this write will not take effect until one T-state
after the completion of the present write.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RSF2 or RSF3 and the low or high
bytes of the Program Counter, respectively, will be loaded.

The remote address is permitted one T -state to settle on the
BCP address bus before WRITE goes low. WRITE then returns high one T-state plus the programmed Data Memory
wait state, T Wd later, having satisfied the memory access
time, and one T-state later LCL is reasserted low, transferring bus control back to the SCPo

[MS1-0] = 00 designates a Data Memory access and
moves RASM into RSF4. WRITE will be aStlerted low in this
state and A and AD continue to be tri-stated. This allows the
Remote Processor to drive the Data Memory address and
data for the write. Since OM EM is subject to wait states
RSF4 is looped upon until all the programmed Data Memo~
wait states have been inserted.

In this example, REM-WR goes low again during the remote
write cycle which, since WR-PEND is still low, causes XACK
to go low to wait the Remote Processor. Then LCL goes
low, allowing the second data byte to be latched on the next
trailing edge of REM-WR. One T-state later. XACK and
WR-PEND go back high at the same time.
1-128

Jl
(D

...
.....,
0

::::J

....

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D)

::::J

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...ci"
::::J

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TUF/9336-Al

FIGURE 4-22. Flow Chart of Latched Write Mode

8~~&8da

DP8344B
~

(:)

RASII state
TCU state

RSA

RS B

RS C

RS O

RS E

RS r

TWd

TWr

~I~I~I~I
~
~
~
~

RS C

RS D

RSE

RS G

RS H

RSA

ClK-OUT

:D
(I)

..
.....
3
o
(I)

ROI-WR

:::l

(I)

......
n

WR-PEND

m -+__________________-+____J

(I)

:::l
XACK

WRITE

...l>C"
D)

ALE

.....
(.oJ

S·

BCP BUS

ADDR~~~~~ /~

XZllX

LOCAL DATA

REIIOTE DATA

LOCAL ADDRESS X

LOCAL DATA

A(~~~~) m///X~---L-OC-AL-A-DD-RE-S-S--.....;.,.X

:::l

XlllX

REMOTE ADDRESS

LOCAL ADDRESS

I
X

REMOTE ADDRESS

X///////a

( REMOTE DATA)

(

'<
t/)

(I)

Xr-----R-EM-OTE-A-D-DR-ES-S------------~X7///////////////0///0//0/

REMOTE ADDRESS

I
DATA

X/OVZWl

REMOTE DATA

I
REMOTE BUS

ADDRESS

.....
en
..
;:;

REMOTE DATA)

::!.

5·

L - - LOCAL MEMORY WRITE ~ I

REMOTE WRITE HOST

L - - LOCAL MEMORY WRITE ~ L

BCP INT. OP.--'

BCP INT. OP.-.-...J
TL/F/9336-31

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-(RIC} Contents: XXXX1100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-RD =1
LOCK
=1

FIGURE 4-23. Latched Write to Data Memory by Remote Processor

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

(Reference Figure 4-24 for the timing diagrams which demonstrate how two remote accesses can be mistaken as
one.)

The BCP is now shown executing a local memory write, with
remote data still pending in the latch. At the end of this
instruction, the BCP begins executing a series of internal
operations which do not require the bus. RASM therefore
takes over and, without waiting the Timing Control Unit, executes the Remote Write.

The second source of remote rest time is due to the manner
in which the BCP samples the CMD signal. CMD is sampled
once at the beginning of each remote access. Due to the
manner in which CMD is sampled, CMD will not be sampled
again if a second remote access begins within 1.5 T-states
plus a hold time, after the BCP recognizes the end of the
first remote access. If this happens, the BCP will use the
value of CMD from the previous remote access during the
second remote access. If the value of CMD is the same for
both accesses, the second access will proceed as intended.
However, if the value of CMD is different for the two remote
accesses, the second remote access will read/write the
wrong location.

4.2.6 Remote Rest Time
For the BCP to operate properly, remote accesses to the
BCP must be separated by a minimal amount of time. This
minimal amount of time has been termed "rest time".
There are two causes for remote rest time. The first cause is
implied in the functional state machine forms for remote accesses and can be explained as follows: At the beginning of
every T-state the validity of a remote access is sampled for
that T-state. To guarantee that the BCP recognizes the end
of a remote cycle, the time between remote accesses must
be a minimum of one T-state plus set up and hold times.

The reader should note that the timing of the second source
of rest time begins at the same time that the BCP first samples the end of the previous remote access. Thus when the
first source of rest time ends, the second source of rest time
begins. (Reference Figure 4-25 for timing diagrams for rest
time in all modes except Latched Write mode).

In the case of Latched Read and Fast Buffered Write, the
validity of a remote access is not sampled on the first rising
edge of the CPU-CLK following XACK rising. However, on
all subsequent rising edges of the CPU-CLK the validity of
the remote access is sampled. As a result, if the remote
processor can terminate its remote access quickly after
XACK rises (within a T-state), up to a T-state may be added
to the above equation for Latched Read and Fast Buffered
Write modes (Le., a second remote access should not begin
for two T-states plus set up and hold times after XACK rises
in Latched Read and Fast Buffered Write modes). On the
other hand, if the remote processor does not terminate its
remote access within a T-state of XACK rising, the above
equation (one T-state plus set up and hold times between
remote accesses) remains valid for Latched Read and Fast
Buffered Write modes.

Latched Write Mode
Latched Write mode is a special case of rest time and
needs to be discussed separately from the other modes.
The first cause of rest time affects every mode including
Latched Write. In regards to the second source of rest time,
Latched Write mode was designed to allow a second remote access to start while a write is still pending (Le.,
WR-PEND = 0). Thus, when WR-PEND rises (signaling the
end of the previous write) the value of CMD is sampled for
the second remote access. This allows Latched Write to
avoid the second cause of rest time discussed above.

If these specifications are not adhered to, the BCP may
sample the very end of one valid remote access and one
T-state later sample the very beginning of a second remote
access. Thus, the BCP will treat the second access as a
continuation of the first remote access and will not perform
the second read/write. The second access will be ignored.

However, if a remote access begins within one half a
T-state after WR-PEND rises, CMD will not be sampled
again. For this case, if the value of CMD changes just after
WR-PEND rose and at the same time the remote access
begins, the BCP will read/write the wrong location. (Reference Figure 4-26 for timing diagrams of rest time for latched
write mode.)

II
I

1-131

4.0 Remote Interface and Arbitration System (RIAS)
I'

1 T-state

(Continued)

c:::: _---,_._---+~-.....)_:_~:'+-~""'--~-.
______
TL/F/9336-G5

(a) This timing diagram shows two remote accesses within one T-state. The first set of arrows
. shows the BCP s'ampllng a valid remote read. The next time the BCP samples the validity of the
remote access Is shown by the second set of arrows (1 T-state later). In this case, It will sample
the second remote access and mistake It as a continuation of the first remote access.

TLIF/9336-G6

(b) This timing diagram shows the timing necessary for the BCP to recognize both accesses as
separate accesses. The first set of arrows shows the BCP sampling a valid remote read. One T-state
later at the second set of arrows the BCP will sample the end of the first remote access. Another T-state
later at the third set of arrows the BCP will sample the beginning of the second remote access.
FIGURE 4·24. Mistaking Two Remote Accesses as Only One

1-132

4.0 Remote Interface and Arbitration System (RIAS)

(Continued)

CPU-ClK

CMD

1st Remote Access's
CMD Value

fWA0Wff?>uCi< low till no more local accesses is (MAX(now. nlw-1)+3)T.
Note 4: The formula(s) apply to a 2. T·state instruction. For a 3 T-state Instruction. add one T.state; for a 4 T·state Instruction. add two T·states.

1-149

In
~

C')

5.0 Device Specifications (Continued)

leLK

TL/F19336-62

(a) Reset Timing

WAIT

ALE
READ

WRITE

------.1
---"'I
--------TLlF/9336-63

lelK

--------'1

ALE _ _ _ _ _ _ _ _ _ _ _ _J

Aw;1llfflffpijllh7Plffffhr)X____________
Tl/F/9336-64

~:~ =,---~~~ ~_I_ _'--~@d

TLlF/9336-AB

(d) Instruction WAIT Timing
FIGUFl~s-:10.CoritrotPlriTlrillrig'

1-150

5.0 Device Specifications (Continued)
TABLE 5-11. Buffered Read of PC, RIC (Note 1)

10#

Symbol

Parameter

tSU-RRR-CO

RAE, REM-RD Falling before CLK-OUT Rising

tH-RRR-X

RAE, REM-RD Rising after XACK Rising (Note 2)

,Max'

Min

Formula

ns
-34

2T+
tSU-CMD-RRR

CMD Valid before RAE, REM-RD Falling

tH-CMD-RRR

CMD Invalid after RAE, REM-RD Falling

T+

RAE, REM-RD Falling to XACK Falling

tpD-X-LCL

XACK Falling to ill Rising

(nLw+1)T+

-5

tPD-LCL-X

LCL Rising to XACK Rising

2T+

-10

tPD-RRR-LCL

RAE, REM-RD Rising to LCL Falling

tAZ-A-LCL

A Disabled before LCL Rising

-18,

tZA-LCL-A

A Enabled after LCL Falling

TH+

15'

tpD-LCL-PC

LCL Rising to AD (PC) Valid

T+ .

tpD_PC-X

AD (PC, RIC) Valid before XACK Rising

T+

tpD-PC-RRR

' RAE, REM-RD Rising to AD (PC) Invalid'

tpD-RRR-X

tw-PC

Units

ns
26

' : ns'

AD (PC, RIC) Valid Time

' ns
ns

22
-24

T+'

: ns
ns'

.. -

-2

' 'ns'

All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to' create' a new timing
specification may lead to invalid results.
Note 2: The maximum value for this parameter is the latest RAE', REM-RD can be removed without adding a T-state to the remote access.
Note 1:

ClK-OUT - - - I

RAE

G2:1

CMD~

REM-RD

- CD

- kD

--,~

.
e

lJ~

LCl
READ
A

)V//// / // / // ///// // ///// ////////////////////~

~l-

I'-

3,.-

-0

- 01-

..:0

['"

-=-10

--®---1

I-

1\"

®-

~
AD

~
XACK

RIC

RIC, PC

~
J

RIC

'1?

III

TlIF/9336-65
I

FIGURE 5-11. Buffered Read of PC, RIC

1-151

m
~
~

Cf)

5.0 Device Specifications (Continued)
TABLES';12; Buffered Read of DMEM(Nofe 1)'
Symbol

10#

Parameter

tSU-RRR-CO

tH-RRR-X

R'Al:, REM-RD Falling before ClK-OUT Rising
R'Al:, REM-RD Rising after XACK RiSing (Note 2)

Formula

Min

Max

Units

ns
-32

T+

tSU-CMO-RRR

CMD Valid before RAE, REM-RD Falling

tH-CMO-RRR

CMD Invalid after RAE, REM-RD Falling

tpO-RRR-X

'RAE, REM-RD Falling to XACK Falling

tpO-X-LCL

XACK Falling to [C[ Rising

(nLW+1)T+

-5

tpO-LCL-X

[C'[ Rising to XACK Rising

(nOW+2)T+

-10

tpO-RRR-LCL

RAE, REM-RD Rising to ill Falling

T+

tPO-LCL-RO

[C[ Rising to READ Falling

T+

-5

tpO-RO-X

READ Falling to XACK Rising

(now+1)T+

-15

tpO-RRR-RO

tAZ-AAO-LCL

'RAE, REM-RD Rising to READ Rising
A, AD Disabled before ill Rising

TL+

-20

tZA-LCL-AAO

A, AD Enabled after [C[ Falling

TH+

-10

tW-RO

Read low

(nOW+1)T+

-4

0
26

T+

ns
26

ns
ns

Note 1: All parameters are Individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to Invalid results.
Note 2: The maximum value for this parameter is the latest tiAE:. ~ can be removed without adding a T-state to the remote access.

ClK-OUT --.-:;

, - k0

RAE

- CD ,l-,._ _ _ _ _ _ _ _ __

jf"

~~I~~~~~~~

CNO

~?j

H/I//////////////1///////////////////////1/////////////////////////I//.
f"

-0XACK

~If.

l ...

lCl ________________

A,AO

_ _ _ _ _01

,8./

r---cv

-@-)~

~
j

r-®-

II1

TL/F/9336-66

1-152

5.0 Device Specifications (Continued)
TABLE 5-13. Buffered Read of IMEM (Note 1)

10#

Symbol

Parameter

Min

Formula

Max

Units

tSU-RRR-CO

RAE, REM-RD Falling before ClK-OUT Rising

tH-RRR-X

RAE, REM-RD Rising after XACK Rising (Note 2)

tSU-CMD-RRR

CMD Valid before RAE, REM-RD Falling

tH-CMD-RRR

CMD Invalid after RAE, REM-RD Falling

tpD-RRR-X

RAE, REM-RD Falling to XACK Falling

tPD-X-LCL

XACK Falling to [C[ Rising

tpD-LCL-X

lCl Rising to XACK Rising

tpD-RRR-LCL

RAE, REM-RD Rising to [C[ Falling

tAZ-LCL-A

A Disabled after [C[ Rising

tZA-A-LCL

A Enabled before [C[ Falling

tpD-IMEM-X

AD (IMEM) Valid before XACK Rising

tpD-RRR-IMEM

AD (IMEM) Invalid after RAE, REM-RD Rising

tPD-LCL-IMEM

[C[ Rising to AD (IMEM) Valid

tW-IMEM

(IMEM) Valid

tPD-LCL-IA

[C[ Falling to Next IA Valid (Note 3)

-32

T+
0

T+

ns
26

T+

-5

(nIW+2)T+

-10
3

-18

TH+

(nlw+1)T+

-25

ns
22

T+
(nlw+1)T+

TH+

ns
ns
ns

T+TH+

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.
Note 2: The maximum value for this parameter is the latest RM:, ~ can be removed without adding a T-state to the remote access.
Note 3: Two remote reads from instruction memory are necessary to read a 16-bit instruction word from IMEM-Iow byte followed by high byte. The timing for the
two reads are the same except that IA is incremented after the high instruction memory byte is read.

CLK-OUT

-.,
RAE

- 0-

~
cw~
-

k'/////////////////////////////////////////////////~

REt.f-RD~
XACK

1-0

- r-0

LCL
READ

j-0A

·~~I

III

--@

r---®--14

It.fEt.f

RIC

~
X

TlIF/9336-67

FIGURE 5~13; Buffered Read of IMEM
1-153

5.0 Device Specifications (Continued)
TABL.E S':;14;L.atcheC:f Reacfof PC, RIC (Note 1)
Formula

Min

Max

Units

10#

Parameter

tSU-RRR-CO

RAE, REM-RD Falling before CLK-OUT Rising

tH-RRR-X

RAE, REM-RD Rising after XACK Rising

tSU-CMD-RRR

CMD Valid before RAE, REM-RD Falling

tH-CMD-RRR

CMD Invalid after RAE, REM-RD Falling

T+

Symbol

tpD-RRR-X

RAE, REM-RD Falling to XACK Falling

tPD-Xf-LCLr

XACK Falling to LCL Rising

(nLW+1)T+

-5

tPD-LCL-X

LCL Rising to XACK Rising

2T+

-10

tPD-Xr-LCLf

XACK Rising to LCL Falling

T+

-11

tAZ-A-LCL

A Disabled before LCL Rising

TL+

-18

tZA-LCL-A

A Enabled after LCL Falling

TH+

-12

tpC-LCL-PC

LCL Rising to AD (PC) Valid

T+

tpD-PC-X

AD (PC) Valid before XACK Rising

T+

-22

tpD-X-PC

XACK Rising to AD (PC) Invalid

TH+

tw-PC

AD (PC, RIC) Valid

T+TH+

-12

ns
ns
20

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

ClK-OUT

---l

- kD

-CD*-

RAE - - \

0.:j ~

~///////////////////////J7'/7/777///////////~

Ct.lD~

REt.I-RD

-l-

~
XACK

'3k-

lCl

READ
A

-0--

-=10

- @r:

\I'

0j,
AD

RIC

-@- @fRIC, PC
'(

RIC

'14'
TL/F/9336-68

FIGURE 5-14. Latched Read of PC, RIC

1-154

5.0 Device Specifications (Continued)
TABLE 5·15. Latched Read of OMEM (Note 1)

Min

Max

Units

10#

Parameter

tSU-RRR-CO

tH-RRR-X

RAE. REM-RD Falling before ClK-OUT Rising
RAE. REM·RD Rising after XACK Rising

tSU-CMD-RRR

CMD Valid before RAE. REM·RD Falling

Symbol

Formula

tH-CMD-RRR

CMD Invalid after RAE. REM·RD Falling

tpD-RRR-X

RAE:. REM·RD Falling to XACK Falling

tPD-Xf-LCLr

XACK Falling to [C[ Rising

(nLW+1)T+

-5

tpD-LCL-X

(nDW+2)T+

-10

T+

-11

T+

-5

(nDW+1)T+

-15
12

T+

ns
ns

tPD-Xr-LCLf

tpC-LCL-RD

ill Rising to XACK Rising
XACK Rising to i l l Falling
ill Rising to READ Falling

tpD-RD-X

READ Falling before XACK Rising

tpD-X-RD

XACK Rising to READ Rising

TH+

-7

tAZ-AAO-LCL

A. AD Disabled before [C[ Rising

-20

tZA-LCL-AAD

A. AD Enabled after [C[ Falling

TH+

-10

tW-RD

READ low

(now+1)T+TH+

-12

All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 1:

CLK-OUT

--,

RAE
3

Ct.lD

REJ.t-RD

- 0f-

1
~

~///////////////////////////////////////////~~

kDXACK

LCL

Il-

~t\

-®-

~
-

READ

1\
~

-j@1A. AD

@f-

~
1\

TLIF/9336-69

FIGURE 5-15. Latched Read of OMEM

..
I

1-155

5.0 Device Specifications (Continued)
TABLE 5";1S.LatcheClReaCl of IMEM'(Nole1}'
10#

Symbol

Parameter

Formula

Min

Max

. Units

tSU-RRR-CO

tH-RRR-X

RAE, REM-RD Rising after XACK Rising

tSU-CMD-RRR

CMD Valid before RAE, REM-RD Falling

tH-CMD-RRR

CMD Invalid after RAE, REM-RD Falling

T+

tpD-RRR-X

RAE, REM-RD Falling to XACK Falling

tpD-Xf-LCLr

XACK Falling to LCL RiSing

T+

-5

tpD-LCL-X

LCL Rising to XACK Rising

(nIW+2)T+

-10

-11

RAE, REM-RD Falling before CLK-OUT Rising

ns
ns

, 26

tPD-Xr-LCLf

XACK Rising to LCL Falling

T+

tAZ-A-LCL

A Disabled before LCL Rising

tZA-LCL-A

A Enabled after LCL Falling

TH+

tPD-LCL-IMEM:

LCL Rising to AD (IMEM) Valid

tpD-IMEM-X

AD (IMEM) Valid to XACK Rising

tpD-X-IMEM

XACK Rising to AD (IMEM) Invalid

tpD~LCL-IA

LCL Falling to Next IA Valid (Note 2)

tW-IMEM

IMEMValid

ns,
ns
ns
ns

-18

-12

ns
22

T+
(nlw+1)T+

-23

TH+

T+TH+

-19

(nlW + 1)T + T H+

-9

ns
ns
ns

ns
ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote reads from instruction memory are necessary to ~ead a 16-bit instruction word from IMEM-low byte followed by high byte. The timing for the
two reads are the same except that IA is incremented after the high instruction memory byte is read.

ClK-OUT

-0f-

' -l-

RAE - - - ' \

;"~
-~

REt.4-RD

-0--1

1I11111111111111111111111111111i ,/llllllllllllllllllllllllllllllt
f

1\
~'

XACK

t7'
\.:.J

-0

lCL

}
,

READ
A

r-&I

f--®

e- @)

RIC

It.4Et.4

"*-

~
RIC

J.;'\

IA
TL/F /9336-70

FIGURE 5-16. Latched Read of IMEM

1-156

5.0 Device Specifications

(Continued)

TABLE 5·17. Slow Buffered Write of PC, RIC (Note 1)

10#

Symbol

Parameter

Min

Formula

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising (Note 2)

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

-37
0

ns
ns

T+

Units
ns

0
T+

tSU-CMD-RRW

Max

tSU-RRW-CO

ns
26

tpD-X-LCL

XACK Falling to [C[ Rising

(nLW+1)T+

-5

tpD-LCL-X

[C[ Rising to XACK Rising

2T+

-10

tPD-RRW-LCL

RAE, REM-WR Rising to [C[ Falling

T+

tAZ-MD-LCL

A, AD Disabled before lCl Rising

-20

tZA-LCL-MD

A, AD Enabled after lCl Falling

TH+

-10

tSU-RDAT-RRW

AD (Data) Valid before RAE, REM-WR Rising

tH-RDAT-RRW

AD (Data) Invalid after RAE, REM-WR Rising

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: The maximum value for this parameter is the latest RAE:, ~ can be removed without adding a T-state to the remote access.

CLK-OUT
RAE

----,

- CD -

0.,j ~
'fl)(

XlIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII/- ifill/- IfIIIIIIIIIIIIII11//IIIIIIIIIII

CUD

REU-WR

~t"

It-

-0XACK

1<-

-0
\:../

LCL
-WRITE

lit
--

r-0A,AD

\I'

H9-tTL/F/9336-71

FIGURE 5-17. Slow Buffered Write of PC, RIC

II
I

1-157

5.0 Device Specifications (Continued)

r ABLE 5·18. Slow Buffered Write of OMEM (Note 1)
Min

Max

Units

Symbol

10#

tSU-RRW-CO

RAE, REM-WR Falling before CLK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising (Note 2)

Parameter

Formula

-34

T+
tSU-CMO-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMO-RRW

CMD Invalid after RAE, REM-WR Falling

tpO-RRW-X

RAE, REM-WR Falling to XACK Falling

tpO-X-LCL

XACK Falling to LCL Rising

tpO-LCL-X

LCL Rising to XACK Rising

tpO-RRW-LCL

RAE, REM-WR to LCL Falling

T+

(nLW+1)T+

-5

(now+2)T+

-10

T+

-5

(now+1)T+

-17

ns
8

tpO-LCL-WR

LCL Rising to WRITE Falling

tpO-WR-X

WRITE Falling to XACK Rising

tpO-RRW-WR

RAE, REM-WR Rising to WRITE Rising

tAZ-AAO-LCL

A, AD Disabled before LCL Rising

TL+

-20

tAZ-LCL-AAO

A, AD Enabled after LCL Falling

TH+

-10

tW-WR

WRITE Low

(now+1)T+

-3

ns
28

All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: The maximum value for this parameter is the latest RAE:. RE'fiif-WR can be removed without adding a T-state to the remot~ access.

Note 1:

ClK-OUT

-----l

- r-G

-0 .,

RAE~~
3

HIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!J7J77l7llllllll111//////if/f////L

CMD

REM-WR

Hi>XACK

lCl

\.8.1
~r

-@--

~
-WRITE

HiD-

14'

r@+
A,AD

~
TL/F/9336-72

FIGURE 5·18. Slow Buffered Write of DMEM

1-.158

5.0 Device Specifications

(Continued)

TABLE 5-19. Slow Buffered Write of IMEM (Notes 1,2)
Symbol

Parameter

10#

Formula

Min

Max

Units

tSU-RRW-CO

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising (Note 3)

ns
-34

T+
0

tSU-CMD-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

tPD-X-LCL

XACK Falling to lCL Rising

T+

-5

tpD-LCL-X

lCL Rising to XACK Rising

(nlw+2)T+

-10

tPD-RRW-LCL

RAE, REM-WR to LCL Falling

T+

tAZ-AAD-LCL

A, AD Disabled before LCL Rising

-20

tZA-LCL-AAD

A, AD Enabled after LCL Falling

TH+

-10

tpD-RDAT-1

AD (Data) Valid to I Valid

tH-RDAT-RRW

AD (Data) Invalid after RAE, REM-WR Rising

tpD-LCL-IA

LCL Falling to next IA Valid

tPD-LCL-IWR

LCL Rising to IWR Falling

tpD-IWR-X

IWR Falling before XACK Rising

tpD-RRW-IWR

RAE, REM-WR Rising to IWR Rising

tZA-IWR-1

IWR Falling to I Enabled

tAZ-IWR-1

IWR Rising to I Disabled

tpD-I-IWR

I Valid before IWR Rising

(nIW+ 1)T+

-10

tW-IWR

IWR Low

(nIW+2)T+

-2

tPD-I-IA

I Disabled to IA Invalid

2T+TH+

-64

T+

ns
26

ns
ns

ns
30

T+TH+

-20
-3

(nlw+2)T+

-19

T+

-2
22

ns
52

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEM-Iow by1e followed by high by1e. The timing for the 2nd
write is shown in the following diagram. The timing of the first write is the same as a write of the PC or RIC.
Note 3: The maximum value for this parameter is the latest RAl:, REM-WR can be removed without adding a T-state to the remote access.

II
I

1-159

DP8344B
U1

a"
CD
en

"a
CD

n
:::;;

a"
Q)

0"
::J
en

ao
a.

:r
c:
CD

.s
....
en

(20)

01
TUF/9336-73

FIGURE 5~19.SJow Buffered WriteofiMEM

5.0 Device Specifications (Continued)
TABLE 5-20. Fast Buffered Write of RIC, PC (Note 1)

10#

Parameter

tSU-RRW-CO

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising

tSU-CMD-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

tPD-X-LCL

XACK Falling to lCL Rising

(nLW+1)T+

-5

tpD-lCl-X

[C[ Rising to XACK Rising

2T+

-10

,ns

tPD-Xr-lCLf

XACK Rising to lCl Falling

T+

-11

tAZ-AAD-LCL

A, AD Disabled before lCl Rising

-20

tZA-LCl-AAD

A, AD Enabled after lCl Falling

TH+

-10

tSU-RDAT-X

AD (Data) Valid before XACK Rising

Symbol

tH-RDAT-X

Formula

Min

Max

' Units

T+

ns
26

AD (Data) Invalid after XACK Rising

ns
ns

,ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

ClK-OUT

RAE

Ct.lD

-REt.4-WR

--=10 ~

1f!lX

'¥I//////////////////////////////////////////////////////h

...

~
XACK

- 0-

f
.-

17'.
\:J

-0
LCl

-WRITE

A,AD

-0-~@~
11
"'"

r-0-

'Ill.

~
TlIF/9336-74

FIGURE 5-20. Fast Buffered Write of RIC, PC

II
I

1-161

5.0 Device Specifications (Continued)
TABLE 5';21: Fast Buffered Write of OMEM (Note 1)
Symbol

10#

Parameter

tSU-RRW-CO

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising

tSU-CMD-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

tPD-Xf-LCLr

XACK Falling to [C[ Rising

tpD-LCL-X
tPD-Xr-LCLf

Formula

Min

Max

Units

T+

(nLw+1)T+

-5

[C[ Rising to XACK Rising

(nDW+2)T+

-10

XACK Rising to [C[ Falling

T+

-11

tpD-LCL-WR

lCl Rising to WRITE Falling

T+

-5

tpD-WR-X

WRITE Falling to XACK Rising

(nDW+1)T+

-16

tpD-X-WR

XACK Rising to WRITE Rising

ns
ns

-4

tAZ-AAD-LCL

A, AD Disabled before lCl Rising

TL+

-20

tZA-LCL-AAD

A, AD Enabled after lCl Falling

TH+

-10

tW-WR

WRITE low

(nDW+1)T+

-10

All parameters are Individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 1:

eLK-OUT

RAE

3
CMD

-REM-WR

- G)f-

..,~

HIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII '/1111'IIIIIIIIIIII/IIIII!J

8D-XACK

l..-

J'f..

-0
-

t.:j'\

-@--

--0

WRITE

t-@A,AD

0--

\:..J

LCL

r-®

~
TL/F/9336-75

FIGURE 5-21. Fast Buffered Write of OM EM

1-162

5.0 Device Specifications (Continued)
TABLE 5-22. Fast Buffered Write of IMEM (Notes 1, 2)
Formula

10#

Parameter

tSU-RRW-CO

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-X

RAE, REM-WR Rising after XACK Rising

tSU-CMD-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

tPD-Xf-LCLr

XACK Falling to i l l Rising

Symbol

Min

Max

Units

T+

-5
8

ns
ns

tpD-LCL-X

lCl Rising to XACK Rising

(nlw+2)T+

-10

tPD-Xr-LCLf

XACK Rising to [C[ Falling

T+

-11

tAZ-AAD-LCL

A, AD Disabled before [C[ Rising

-20

tZA-LCL-AAD

A, AD Enabled after lCl Falling

TH+

-10

tPD-RDAT-1

AD (Data) Valid to I Valid

tH-RDAT-X

AD (Data) Invalid after XACK Rising

tpD-IWR-X

IWR Falling before XACK Rising

tpD-LCL-IA

lCl Falling to next IA Valid

tpD-LCL-IWR

lCl Rising to IWR Falling

-3

XACK Rising to IWR Rising

-2

tpD-X-IWR

30
3
(nlw+2)T+

-19

T+TH+

-19

ns
ns
ns

-2

tZA-IWR-1

IWR Falling to I Enabled

tAZ-IWR-1

IWR Rising to I Disabled

tPD-I-IWR

I Valid before IWR Rising

(nlw+1)T+

-18

tW-IWR

IWR low Time

(nlw+2)T+

-10

2T+TH+

-70

tpD-I-IA

T+

I Disabled to IA Invalid

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEM-Iow byte followed by high byte. The timing of the 2nd
write is shown in the following diagram. The timing of the first write is the same as a write of the PC or RIC as shown in Figure 5-20.

..
I

1-163

m
"'11:1'

5.0 Device Specifications (Continued)

C
ClK-OUT

RAE

CMD

XACK

lCl

A,AD

----------"1

......------'1

IA _ _ _ _ _ _ _ _ _ _~----~~----~-------------'I~

TL/F 19336-76

FIGURE 5-22. Fast Buffered Write of IMEM

1-164

5.0 Device Specifications (Continued)
TABLE 5·23. Latched Write of PC, RIC (Note 1)

10#

Symbol

Parameter

Formula

tSU-RRW-CO

RAE, REM-WR Falling before ClK-OUT Rising

tH-RRW-CO

RAE, REM-WR Rising after ClK-OUT Rising (Note 2)

Min

TH+

Max

Units

ns
-20

T+

tH-RRW-X

RAE, REM-WR Rising after XACK Rising

tSU-CMD-RRW

CMD Valid before RAE, REM-WR Falling

tH-CMD-RRW

CMD Invalid after RAE, REM-WR Falling

tpD-RRW-X

RAE, REM-WR Falling to XACK Falling

tSU-RDAT-LCL

AD (Data) Valid after lCl Rising

2T+

tH-RDAT-LCL

AD (Data) Invalid after ICC Rising

2T+

tAZ-AAD-LCL

A, AD Disabled before lCl Rising

-20

tZA-LCL-AAD

A, AD Enabled after [C[ Falling

TH+

-10

tpD-RRW-WPND

RAE, REM-WR Rising to WR-PEND Falling

tSU-CMD-WPND

CMD Valid before WR-PEND Rising

tH-CMD-WPND

CMD Invalid after WR-PEND Rising

tSU-RRWr-CO

RAE, REM-WR Rising before ClK-OUT Rising

tpD-X-WPND

XACK Rising to WR-PEND Rising

T+

ns
26

-30

ns
ns

T+

ns
ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: The maximum value for this parameter is the latest~, ~ can be removed without delaying the remote access by one T-state.

RAE

~~
"'
1l'""""""'\

CMD

///~

CLK-OUT
-

REM-WR

-®----1
V/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / .
~

:+0 f+-

-0
~

XACK

LCL
-WRITE

-jeD
A. AD

--WR-PEND

V/~

:--.
AD

A
TL/F/9336-IO

f I 9UR i; 5.2~.V'laltTIn1JIl9AfterRer1'l~~eAc:cess:

•
1-173

6.0 Reference Section
6.1 INSTRUCTION SET REFERENCE

Instruction Format

The Instruction Set Reference section contains detailed information on the syntax and operation of each BCP instruction. The instructions are arranged in alphabetical order by
mnemonic for easy access. Although this section is primarily
intended as a reference for the assembly language programmer, previous assembly language experience is not a
prerequisite. The intent of this instruction set reference is to
include all1he pertinent information regarding each instruction on the page(s) describing that instruction. The only exceptions to this rule concern the instruction. addressing ,
modes and the bus timing diagrams. The discussion of the
instruction addressing modes occurs at the beginning of the
BCP Instruction Set Overview section and, therefore, will
not be repeated here. The figures for the' bus timing diagrams are located at the end of this introduction rather than
constantly repeating them under each instruction. The information that is contained under each instruction is divided
into eight categories titled: Syntax, Affected Flags, Description, Exampie, Instruction Format, T-states, Bus timing, and
Operation. The following paragraphs explain what information each category' conveys and any special nomenclature
that a category may use.,

This category illustrates the formation of an instruction's
machine code for each operand variation. Assembly or disassembly of any instruction can be accomplished using
thes~ figures.
T-states
The T-state category lists the number of CPU clock cycles
required for 'each' instruction, including operand variations
and conditional considerations. Using this information, actual execution times may be calculated. For example, if the
conditional relative jump instruction's condition is not met,
the CPU's clock cycle is 18.867 MHz aCCS] = 0), and no
instruction wait states are requested ([IW1 - 0] = 00), then
Jcc's execution time is calculated as shown below:
texecution

= 1/(CPU clock frequency)

x T-states

= 1/(18.867 X 106 Hz) X 2
=

(53 X 10- 9s) x 2

= 106 ns
See the section BCP Timing for more information on calculating instruction execution times.
Bus Timing
This category refers the user to the Bus Timing Figures 6-1
to 6-6 on the following pages. These figures illustrate the
relationship between software instruction execution and
some of the BCP's hardware signals.

Syntax
This category illustrates the assembler syntax for each instruction. Multiple lines are used when a given instruction
supports more than one type of addressing mode, or if it has
an optional mnemonic. All capital letters, commas (,), math
are entered into the assymbols (+, -), and brackets
sembler exactly as shown. Braces (I I) surround an instruction's optional operands and their associated, syntax. The
text between the braces may either be entered in with or
omitted from the instruction. The braces themselves should
not be entered into the assembler because they are not part
of the assembler syntax. Lower c'ase characters and operands that begin with the capital R represent symbols. These
must be replaced with actual register names, numbers, or
equated registers and numbers. Table 6-1 lists all the symbols and their associated meanings.

Operation

a))

The operation category illustrates each instruction's operation in a symbolic coding format. Most of the operand
names used in this format come directly from each instruction's syntax. The exceptions to this rule deal with implied
operands. Instructions that imply the use of the accumulator$ use the name "accumulator" as an operand. Instructions that manipulate the Program Counter use the symbol
"PC". Instructions that "push" onto or "pop" off of the internal Address Stack specify "Address Stack" as an operand.
Instructions that save or restore the ALU flags and the register bank selections use those terms as operands. Two
specialized operator symbols are used in the symbolic coding format, the arrow " ~ " and the concatenation operator
"&". The arrow indicates the movement of data from one
operand to another. For instance, after the operation
"Rs ~ Rd" is performed the content of Rd has been replaced with the content of Rs. The concatenation operator
"&" simply indicates that the operands surrounding an "&"
are attached together forming one new operand. For example, "PC & [GIE] & ALU flags & register bank
selections ~ Address Stack" means that the Program
Counter, the Global Interrupt Enable bit, the ALU flags and
the register bank selections are combined into one operand
and pushed onto the internal Address Stack. Three conditional structures are utilized in the symbolic coding format:
the "Two Line If" structure, the "Blocked If" structure, and
the "Blocked Case" structure. In the "Two Line If" structure, if the condition is met then the operation is performed,
otherwise the operation is not performed.

Affected Flags
If an instruction sets or clears any of the ALU flags, (Le.,
Negative [N], Zero [Z], Carry [C], and/or Overflow [V)),
then those flags affected are listed under this category.
Description
The Description category contains a verbal discussion
about the operation of an instruction, the operands it allows,
and any notes highlighting special considerations the prorammer should keep in mind when using the instruction.
Example
Each instruction has one or more coding examples designed to show its typical usage(s). For clarity, register
name abbreviations are often used instead of the register
numbers, (Le., RTR is used in place of R4). Each example
assumes that the" .EQU" assembler directive has been previously executed to establish these relationships. Information relating register abbreviations to register names, numbers, and purpose is located in the CPU Registers section.

"Two Line If" structure:
If condition
then operation

1-174

6.0 Reference Section

(Continued)

In the "Blocked If" structure, if the condition is met then all
the operations between the "If" statement and the "End if"
statement are performed.

"Blocked Case" structure:
Case operand of
0: operation
1: operation
2: etc ...

"Blocked If" structure:
If condition then
operation
operation
etc ...

End case
Two reference tables have been added to the back of the
Instruction Set Reference section. The first table, Table 6-2,
lists all the instructions with their associated T-states, Affected Flags, and Bus Timing figure numbers in a compact
format. The second table, Table 6-3, lists all the instructions
in opcode order to facilitate disassembly.

End if
In the "Blocked Case" structure, the operation preceded by
the equivalent numeric value of the operand is executed.
For example, if the operand's value is equal to "1" then the
operation preceded by "1:" is executed.

TABLE 6-1. Notational Conventions for Instruction Set
Symbol
n

Meaning

Represents

o to 255
+ 127 to -128

8 Bits
16 Bits

o to 65535

Unsigned Number

RO-R31

Source Register

RO-R31

Destination Register

Rsd

RO-R31

Combination Source/Destination Register

RO-R15

Limited Source Register

RO-R15

Limited Destination Register

rsd

RO-R15

Limited Combination Source/Destination Register

IW,IX,IY,IZ

Index Register

IrIr
Ir+
+Ir

Index Register in One of the Following Address Modes:
Post Decrement
No Change
Post Increment
Pre-Increment

mlr

Length

Unsigned Number
Signed Number

0-7

Shift Field

3 Bits

0-7

Mask Field

3 Bits

0-7

Position Field

3 Bits

0-1

State Field

1 Bit

0-7

Flag Reference Field

3 Bits

Condition Code Instruction Extensions

cc
v

0-63

Vector Field

6 Bits

0-3

Global Interrupt Enable Flag [GIE] Status Control

2 Bits

0-1

Global Interrupt Enable Flag [GIE] Limited Status Control

1 Bit

0-1

1 Bit

0-1

1 Bit

0-1

1 Bit

1-175

6.0 Reference Section

(Continued)

CPU-ClK

IClK

PC+1

TLIF/9336-21

FIGURE 6-1. Instruction-Memory Bus Timing for 2 T-state Instructions
(No Instruction Walt States [lW1-0] = 00, CPU Running at Full Speed [CCS]

CPU-ClK

IClK

IA
TL/F/9336-22

FIGURE 6-2. Instruction-Memory Bus Timing for 3 T-state Instructions
(No Instruction Walt States [lW1-0] = 00, CPU Running at Full Speed [CCS]

1-176

6.0 Reference Section

(Continued)

I-Tl

'I'

T2--j

CPU-ClK

IClK

PC +1

nn
TL/F/9336-23

FIGURE 6-3. Instruction-Memory Bus Timing for (2 + 2) T-state Instructions
(No Instruction Walt States [lW1-0] = 00, CPU Running at Full Speed [CCS] = 0)

I -T1---*I'"-- Tx--'*I'"-- Tx--·-tl·'-- T2--j
CPU-ClK

IClK

IA
TL/F/9336-24

FIGURE 6-4. Instruction-Memory Bus Timing for 4 T -state Instructions
(No Instruction Walt States [lW1-0] = 00, CPU Running at Full Speed [CCS] = 0)

1·177

6.0 Reference Section (Continued)

I-Tl
CPU-ClK

IClK

----+-'

ALE

READ
TLlF/9336-25

F.lG(JRlni~S;lristructtori/OataMeirioryBusTlmirigfor Data Memory Read

(~§J!'1~t~~c::!Ic)~c)II)Cl!Cl ...enlOI)' VIIalt.~tClt~s, 9PUFlu~n(ngat. Fu USpeed

[9CS).= . 0, [4TFll··';' .•. 0)

CPU-ClK

IClK

ALE

----+-...
~~--~~.'-------------~

READ
TL/F/9336-ll

fFIGOR~~+6:tristructtorl!OataMetnory Bus Tlrillrig for Data Memory Reaa

[(~~]~!~~!I§~C)!J:)Cl~M~tn~ry·Vlltllt~~tetJ;.9P~Runrilrlgatfull.~pe~d.[99~1 . .·"",. ··9),J4""R)""'I~)

1-178

6.0 Reference Section

(Continued)

I - T1-

t.-I·- TX--'·It-·-T2----j

...
•

CPU-ClK

IClK

ALE

---...........

WRITE
TLIF/9336-26

FIGURE 6-7.lnstruction/Data Memory Bus Timing for Data Memory Write
(No Instruction or Data Memory Walt States, CPU Running at Full Speed [CCS] = 0)

ADCA

Add with Carry and Accumulator

Instruction Format
ADCA Rs, Rd

Syntax
ADCA
ADCA

Rs, Rd
Rs, [mlr]

-register, register
-register, indexed

Affected Flags
N,Z,C,V

1
.

I0 I

Rs, [mlr]
1

I0 0
Opcode

I0 I

00
01
10
11

I
. m
8

Example

ADCA

Description
Adds the source register Rs, the active accumulator, and
the carry flag together, placing the result into the destination
specified. The destination may be either a register, Rd, or
data memory via an index register mode, [mlr]. Note that
register bank selection determines which accumulator is active.
Add the constant 109
bits wide).
SUBA A, A
ADD
109, R12
ADCA R13, R13

111111010111
Opcode
.

post-decrement
no change
post Increment
pre-Increment

00 -IW
01 - IX
10 - IY
11 - IZ

to the index register IW, (which is 16

TL/F/9336-5

;Clear the accumulator
;Add 109 to low byte of IW
;Add carry to high byte of IW

1-179

T-states
ADCA Rs, Rd
ADCA Rs, [mlr]

-3

Bus Timing
ADCA Rs, Rd
ADCA Rs, [mlr]

-Figure 6-1
-Figure 6-6

-2

Operation
ADCA Rs, Rd
Rs + accumulator

+ carry bit - . Rd

ADCA Rs, [mlr]
Rs + accumulator

+ carry bit - . data memory

6.0 Reference Section
ADD

(Continued)
Instruction Format
ADDA Rs, Rd

Add Immediate

Syntax
ADD n, rsd
-immediate, limited register
Affected Flags
N,Z,C,V
Description
Adds the immediate value n to the register rsd and places
the result back into the register rsd. Note that only the active registers RO-R15 may be specified for rsd. The value of
n is limited to 8 bits; (unsigned range: 0 to 255, signed
range: + 127 to -128).
Example
Add the constant -3 to register 10.
ADD
-3, R10
;R10 + (-3) -+ R10
Instruction Format
0 10 10 10 I
Opcode .
15
11
T-States
2
Bus Timing
Figure 6-1
Operation
rsd + n -+ rsd

ADDA

I
Rd
15
ADDA

Rs, [mlr]

00
01
10
11

post-decrement
no change
post Increment
pre-Increment

OO-IW
01 - IX
10 - IY
11 - IZ
TL/F/9336-6

T-states
ADDA Rs, Rd
-2
ADDA Rs, [mlr]
-3
Bus Timing
ADDA Rs, Rd
-Figure 6-1
ADDA Rs, [mlr]
-Figure 6-6
Operation
ADDA Rs, Rd
Rs + accumulator -+: Rd
ADDA Rs, [mlr]
Rs + accumulator -+ data memory

rsd

110111010101°1
.
Opcode
.
1
IS

Add with Accumulator

AND

Syntax
ADDA Rs, Rd
-register, register
ADDA Rs, [mlr]
-register, indexed
Affected Flags
N,Z,C,V
Description
Adds the source register Rs to the active accumulator and
places the result into the destination specified. The de~tina
tion may be either a register, Rd, or data. memory via an
index register mode, [mlr]. Note that register bank selection
determines which accumulator is active.
Example
In the first example, the value 4 is placed into the currently
active accumulator, that accumulator is added to the contents of register 20, and then the result is placed into register 21.
MOVE 4, A
;Place constant into accum
;R20 -+ accum -+ R21
ADDA R20, R21
In the second example, the alternate accumulator of register bank B is selected and then added to register 20. The
result is placed into the data memory pointed to by the index
register IZ and then the value of IZ is incremented by one.
EXX
0, 1
;Select alt accumulator
ADDA R20, [IZ +] ;R20 + accum -+ datamem
;and increment data pointer

And Immediate

Syntax
AND n, rsd
-immediate, limited register
Affected Flags
N,Z
Description
Logically ANDs the immediate value n to the register rsd
and places the result back into the register rsd. Note that
only the active registers RO-R15 may be specified for rsd.
The value of n is 8 bits wide.
Example
Unmask both the Transmitter and Receiver interrupts via
the Interrupt Control Register (ICR}, R2. Leave the other
interrupts unaffected.
EXX 0,0
;select main register banks
AND 11111100B,R2 ;unmask transmitter and
; receiver interrupts
Instruction Format

I
n
15

T-states

2
Bus Timing
Figure 6-1
Operation
rsd AND n -+ rsd

1-180

rsd
3

6.0 Reference Section
ANDA

(Continued)

And with Accumulator

BIT

Syntax
ANDA As, Ad
-register, register
ANDA As, [mlr]
-register, indexed
Affected Flags
N,Z
Description
Logically ANDs the source register As to the active accumu·
lator and places the result into the destination specified.
The destination may be either a register, Ad, or data memo·
ry via an index register mode, [mlr]. Note that register bank
selection determines which accumulator is active.
Example
This example demonstrates a way to quickly unload all 11
bits of the three words in the Aeceiver FIFO when the FIFO
is full. The example assumes that the index register IZ
points to the location in data memory where the information
should be stored.
EXX
1,1
;select alternate banks
MOVE 00000111 B, A ;place the ITSA} mask
; into the accumulator
Pop the first word from the receiver FIFO
ANDA TSA, [IZ+]
;read bits 8,9, & 10
MOVE ATA, [IZ + ]
;pop bits 0-7
Pop the second word from the receiver FIFO
ANDA TSA, [IZ + ]
MOVE ATA, [IZ + ]
Pop the third word from the receiver FIFO
ANDA TSA, [IZ + ]
MOVE ATA, [IZ+]
Instruction Format
ANDA As, Ad

15
ANDA
1
/.
15

I0 I

AS,[mlr]
1

I 0 11
Opcode
~

00
01
10
11

I0 I0

I
. m
8

post-decrement
no change
post Increment
pre-Increment

t
00 - IW

01 - IX
10 - IY
11 - IZ

TLIF/9336-7

T-states
ANDA As, Ad
ANDA As, [mlr]

n
15
T-states
2
Bus Timing
Figure 6·1
Operation
rs AND n

I
Ad

Bit Test

Syntax
BIT rs, n
-limited register, immediate
Affected Flags
N,Z
Description
Performs a bit level test by logically ANDing the source reg·
ister rs to the immediate value n. The affected flags are
updated, but the result is not saved. Note that only the ac·
tive registers AO-A15 may be specified for rs. The value n
is 8 bits wide.
Example
Poll the Transmitter FIFO Empty flag [TFE] in the Network
Command Flag register I NCF}, A1, waiting for the Trans·
mitter to send the current FIFO data.
EXX 0,1
;select main A, alt B
Poll:
BIT NCF,1 OOOOOOOB ;AII data sent yet?
JZ
Poll
; No, poll TFE
; Yes, send next byte(s)
Instruction Format

-2
-3

Bus Timing
-Figure 6·1
ANDA As, Ad
ANDA As, [mlr]
-Figure 6·1
Operation
ANDA As, Ad
As AND accumulator - . Ad
ANDA As, [mlr]
As AND accumulator - . data memory

1·181

6.0 Reference Section
CALL

(Continued)

CMP

Unconditional Relative Call

Syntax

CALL

Compare

Syntax

-immediate

CMP

-limited register, immediate

rs, n

Affected Flags

None

N,Z,C,V

Description

Description
Compares the immediate value n with the source register rs
by subtracting n from rs. The affected flags are updated, but
the result is not saved. Note that only the active registers
RO-R15 may be specified for rs. The value of n is limited to
8 bits; (unsigned range: 0 to 255, signed range: + 127 to
-128).

Pushes the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIE], and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the memory address
calculated by adding the contents of the Program Counter
to the immediate value n, (sign extended to 16 bits). Since
the immediate value n is an 8-bit two's complement displacement, the unconditional relative caWs range is from
+ 127 to -128 relative to the Program Counter. Note that
the Program Counter initially contains the memory address
of the next instruction following tha call.

Example
Compare the data byte in register 11 to the ASCII character

"A".
CMP

JC
JEO

Example

Transfer control to the subroutine "Send.it". Note that
"Send. it" must be within + 127/ -128 words relative to the
PC.
CALL

R11,"A"
Less_thanJ
Equal_toJ

;If:
data<"A"
data="A"
;else data> "A"

Compare the contents of register 8 to the value 25.
CMP
BIT
JZ

Send.it

Instruction Format

R8,25
CCR,00000011 B
Greater_than

;if:
data> 25
Goto Greater_than

n
15
T-states
3
Bus Timing

Comparing of Unsigned Values

Flag{s) to Test

Comparison

«)
LT
LEO «=)
(=)
EO
GEO (>=)
(»
GT

Figure 6-2
Operation

PC & [GIE] & ALU flags & register bank selections
~ Address Stack
PC + n(sign extended) ~ PC

clz
Z
C
C&Z

Note: & = logical AND
= logical OR

Instruction Format

0
1.

I 0 I 1 11

Opcode
15

T-states
2
Bus Timing

Figure 6-1
Operation

rs - n

1-182

I
_

n
11

6.0 Reference Section
CPL

(Continued)

Complement

EXX

Syntax
CPL Rsd
-register
Affected Flags
N,Z
Description
Logically complements the contents of the register Rsd,
placing the result back into that register.
Example
Load the fiJI-bit count passed from the host into the Transmitter's Fill-Bit Register (FBR I, R3, and then perform the
required one's complement of the fill-bit count. In this example, register 20 contains the fill-bit count.
EXX
1,1
;select alternate banks
MOVE
R20, FBR ;Ioad (FBR 1
CPL
FBR
;complement fill-bit count
Instruction Format
110111011111110101010\
Opcode
.
15
4
T-states
2
Bus Timing
Figure 6-1
Operation

Exchange Register Banks

Syntax
EXX ba, bb (,gl
Affected Flags
None
Description
Selects which CPU register banks are active by exchanging
between the main and alternate register sets for each bank.
Bank A controls RO-R3 and Bank B controls R4~R11. The
table below shows the four possible register bank configurations. Note that deactivated registers retain their curren~ vClI~
ues. The Global interrupt Enable bit [GIE] can be set or
.
cleared, if desired.
Register Bank Configurations

I I
Rsd

Active Register Banks.

0
0
1
1

0
1
0
1

Main AMain B
Main A, Alternate: B
Alternate A, Main B
Alternate A, AlternateB .

Example
Activate the main register set of Bank A, the alternate register set of Bank B, and leave the Global interrupt Enable bit
[GIE] unchanged.
EXX
0,1
;select main A, alt B reg banks
Instruction Format

Rsd~Rsd

11 1 0 1 1 1
15

, ., ,

~~~o~~ 1 1 1 0 11 I ~

ba 1 bb

0 10 10 1

6!4
3.2
0
OO-'-GIE not affected
01-reserved
10-SetGIE
11-Clear GIE

T-states
2
Bus Timing
Figure 6-1
Operation
Case ba of
0: activate main Bank A
1: activate alternate Bank A
End case
Case bb of
0: activate main Bank B
1: activate alternate Bank B
End case
Case g of
0: leave [GIE] unaffected, (default)
1: (reserved)
2: set [GIE]
3: clear [GIE]
End case

1-183

6.0 Reference Section (Continued)
JMP Conditional Relative Jump

Instruction Format

Jcc
Syntax
JMP f, s, n
Jcc n

-immediate
-immediate (optional syntax)

T-states
2 if condition is not met
3 if condition is met

Affected Flags
None
Description

Bus Timing

Conditionally transfers control to the instruction at the memory address calculated by adding the contents of the Program Counter to the immediate value n, (sign extended to
16 bits), if the state of the flag referenced by f is equal to the
state of the bit s; or, optionally, if the condition cc is met.
See the tables below for the flags that f can reference and
the conditions that cc may specify. Since the immediate value n is an 8-bit two's complement displacement, the conditional relative jump's range is from + 127 to -128 relative
to the Program Counter. Note that the Program Counter initia"y contains the memory address of the next instruction
following the jump.

Figure 6-1 if condition is not met
Figure 6-2 if condition is met

Operation
JMP f, s, n
If flag f is in state s
then PC + n(sign extended) -+ PC
Jcc n
If cc condition is true
then PC + n(sign extended) -+ PC
Flag Reference Table for "f"

Example
This example demonstrates both syntaxes of the conditional relative jump instruction testing for a non-zero result from
a previous instruction; (Le., [Z] = 0). If the condition is
met then control transfers to the instruction labeled
"LOop. back"; else the next instruction following the jump is
executed.
JMP
JNZ

OOOB,O,Loop.back

;jump on not zero

Loop.back

;jump on not zero

Meaning
Zero
Not Zero
Equal
Not Equal
Carry
No Carry
Overflow
No Overflow
Negative
Positive
Receiver Active
Not Receiver Active
Receiver Error
No Receiver Error
Data Available
No Data Available
Transmitter FIFO Fu"
Transmitter FIFO Not Fu"

(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

4
5
6*
7

Flag Reference
[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

in {CCRI
in {CCRI
in {CCRI
in {CCRI
in {TSRI
in {TSRI
in {TSRI
in {TSRI

°Note: The value of f for [DAV] differs from the numeric
value for the position of [DAV] in {TSRI.

Condition Tested for
[Z]
[Z]
[Z]
[Z]
[C]
[C]
[V]
[V]
[N]
[N]
[RA]
[RA]
[RE]
[RE]
[DAV]
[DAV]
[TFF]
[TFF]

(binary)

Condition SpeCification Table for "cc"

Z
NZ
EO
NEO
C
NC
V
NV
N
P
RA
NRA
RE
NRE
DA
NDA
TFF
NTFF

0
1
2

= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0

1-184

6.0 Reference Section
JMP

(Continued)

Unconditional Relative Jump

Syntax
JMP n
-immediate
JMP Rs
-register
Affected Flags
None
Description
Unconditionally transfers control to the instruction at the
memory address calculated by adding the contents of the
Program Counter to either the immediate value n or the con·
tents of the source register Rs, (both sign extended to 16
bits). Since the immediate value n and the contents of Rs
are 8·bit two's complement displacements, the uncondition·
al relative jump's range is from + 127 to -128 relative to
the Program Counter. Note that the Program Counter initial·
Iy contains the memory address of the next instruction fol·
lowing the jump.
Example
Transfer control to the instruction labeled "I niLXmit",
which is within + 127/ -128 words relative to the PC.
JMP IniLXmit
;go initialize Transmitter
Instruction Format
JMP n

n
JMP

15
Rs

11111010111110111110101
Opcode
15

Rs
4

T-states

JMP n
-3
-4
JMP Rs
Bus Timing
-Figure 6-2
JMP n
JMP Rs
-Figure 6-4
Operation
JMP n
PC + n(sign extended) ----+ PC
JMP Rs
PC + Rs(sign extended) ----+ PC

III
1-185

6.0 Reference Section (Continued)
JRMK Relative Jump with Rotate and
Mask on Register
Syntax
JRMK Rs, b, m

-register
Affected Flags
None
Description
Transfers control to the instruction at the memory address
calculated by adding the contents of the Program Counter
to a specially formed displacement. The displacement is
formed by rotating a copy of the source register Rs the value of b bits to the right, masking (setting to zero) the most
significant m bits, masking the least significant bit, and then
sign extending the result to 16 bits. Typically, the JRMK
instruction transfers control into a jump table. The LSB of
the displacement is always set to zero so that the jump table
may contain two word instructions, (e.g., LJMP). The range
of JRMK is from + 126 to -128 relative to the Program
Counter. Note that the Program Counter initially contains
the memory address of the next instruction following JRMK.
The source register Rs may specify any active CPU register.
The rotate value b may be from 0 to 7, where 0 causes no
bit rotation to occur. The mask value m may be from 0 to 7;
where m = 0 causes only the LSB of the displacement to be
masked, m = 1 causes the MSB and the LSB to be masked,
m = 2 causes bits 7-6 and the LSB to be masked, etc ...
Example
This example demonstrates the decoding of the address
frame of the 3299 Terminal Multiplexer protocol. In the address frame, only the bits 4-2 contain the address of the
Logical Unit.
EXX
0,1
;select main A, alt B
;decode device address
JRMK
RTR,1,4
;jump to device handler #0
LJMP
AD OR.O
ADDR.1
;jump to device handler # 1
LJMP
LJMP
ADDR.2
;jump to device handler # 2
LJMP
ADDR.7
Instruction Format

;jump to device handler #7

I I
b

15
T-states
4
Bus Timing

Figure 6-4

Operation
Copy Rs to a temporary register:
Rs ~ register
Rotate the register b bits to the right:

reglstor

TL/F/9336-8

Mask the most significant m bits and the LSB:

A
register AND 0 ... 0 1 ... 1 0 ~ register
Modify the Program Counter:
PC + register(sign extended)

PC
1-186

~----------------------------------------------------------------~c

6.0 Reference Section

"'C
Q)

(Continued)

LCALL Conditional Long Call

LCALL

Syntax

LCALL

Rs, p, s, nn

-register, absolute

LCALL

Affected Flags

~
~

Unconditional Long Call

-absolute

Affected Flags

None

Description

If the bit in position p of register Rs is equal to the bit s, then
push the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIE], and the current register bank selections onto the internal Address Stack. Following the push,
transfer control to the instruction at the absolute memory
address nn. The operand Rs may specify any active CPU
register. The value of p may be from 0 to 7, where 0 corresponds to the LSB of Rs and 7 corresponds to the MSB of
Rs. The absolute value nn is 16 bits long, (range: 0 to 64k),
therefore, all of instruction memory can be addressed.

Pushes the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIE], and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the absolute memory
address nn. The value of nn is 16 bits long, (range: a to
64k), therefore, all of instruction memory can be addressed.

Example
Transfer control to the subroutine "Send.it.all", which could
be located anywhere in instruction memory.
LCALL

Example
Call the "Load.Xmit" subroutine when the Transmitter FIFO
Empty flag, [TFE], of the Network Command Flag register
(NCF} is "1".
EXX
0,0
LCALL NCF,7,1, Load.Xmit

111110101111111011101010101010101
Opcode

;select main A, alt B
;If [TFE] = 1 call

Instruction Format

nn
1

p
15

15
T-states
(2

Send.it.all

Instruction Format

15
T-states

Bus Timing

Figure 6-3

Operation
PC & [GIE] & ALU flags & register bank selections
~ Address Stack

nn~PC

Bus Timing
Figure 6-3

Operation
If Rs[p] = s then
PC & [GIE] & ALU flags & register bank selections
~ Address Stack
nn~PC

End if

•
1-187

6.0 Reference Section (Continued)
LJMP

Conditional Long Jump

LJMP

Syntax
LJMP Rs, p, s, nn
-register, absolute
Affected Flags
None
Description
Conditionally transfers control to the instruction at the absolute memory address nn if the bit in position p of register Rs
is equal to the state of the bit s. The operand Rs may specify any active CPU register. The value of p may be from 0 to
7, where o corresponds to the LSB of Rs and 7 corresponds
to the MSB of Rs. The absolute value nn is 16 bits long,
(range: 0 to 64k), therefore, all of instruction memory can be
addressed.
Example
Long Jump to one of the receiver error ,handling routines
based on the contents of the Error Code Register {ECR I.
EXX
0,1,3
;select main A, alt B
; and clear [GIE]
;set [SEC] in {TSR}
. DR
01000000B,TSR
MOVE ECR, R11
;read {ECRI
,; Determine error condition
, LJMP R11, 0, 1, Software_error
LJMP R11, 1, 1, Loss_of_Midbit
LJMP R11, 2,1, Invalid_Ending_Seq
LJMP R11, 3,1, Parity_error
LJMP R11, 4,1, Software_error
Instruction Format
1

15
T-states
(2

.
1

1 1 1 101011 1 1 1 1 1010101,010101010101
Opcode
.
15
0

15
LJMP

Rs
4

Unconditional Long Jump

Syntax
LJMP nn
-absolute
LJMP [lr]
-indexed
Affected Flags
None
Description
Unconditionally transfers control to the instruction at the
memory address specified by the operand. The operand
may either specify an absolute instruction address nn, (16
bits long), or an index register Ir, which contains an instruction address. Long Jump's addressing range is from 0 to
64k; (Le., all of instruction memory can be addressed).
Example
Transfer control to the instruction labeled "Reset.System",
which may be located anywhere in instruction memory.
LJMP
Reset.System
;go reset the system
Instruction Format
LJMP nn

[lr]

I 1 I 0 I ~~~o~~ I 0 I 1 1 0

I ir I

0 10 10

6 J..

OO-IW
01-IX
10-IY
11-12

o
T-states
LJMP nn
LJMP [lr]
Bus Timing
LJMP nn
LJMP [lr]
Operation
LJMP nn

Bus Timing
Figure 6-3
Operation
If Rs[p] = s
then nn~ PC

nn~PC

LJMP

[lr]

Ir~PC

1-188

-(2+ 2)

-2
-Figure 6-3
-Figure 6-1

I0 I0 1
0

6.0 Reference Section
MOVE

(Continued)
Instruction Format
MOVE [mid, Rd

Move Data Memory

Syntax
MOVE [mlr], Rd
-indexed, register
MOVE [lr+ AJ. Rd -register-relative, register
MOVE [lZ + n], rd -immediate-relative, limited register
Affected Flags
None
DescrIptIon
Moves a data memory byte into the destination register
specified. The data memory source operand may specify
anyone of the index register modes; [mlr], [lr+A], [lZ+n].
The index register-relative mode, [lr+ A], forms its data
memory address by adding the contents of the index register Ir to the unsigned 8-bit value contained in the currently
active accumulator. The immediate-relative mode, [lZ+n],
forms its data memory address by adding the contents of
the index register IZ to the unsigned 8-bit immediate value
n. The destination register operand Rd may specify any active CPU register; where as, the destination register operand
rd is limited to the active registers RO-R15.
Example
The first example loads the current accumulator by "popping" an external data stack, which is pointed to by the
index register IX.
MOVE
[ + IX], A
;pop accum from ext. stack
The second example demonstrates the random access of a
data byte within a logical record contained in memory. The
index register IY contains the base address of the logical
record.
R9, A
;calculate offset into record
ADDA
[lY + A], R20 ;get data byte from record
MOVE
In the final example, the 4th element of an Error Count table
is transmitted to a host. The index register IZ points to the
1st entry of the table.
EXX
0,1
;select main A. alt B
MOVE
[lZ + 3], RTR ;transmit 4th element

Rd
15

00 - post-decrement
01 - no change
10 - post Increment
11 - pre-Increment

00
01
10
11

IX
IY

TL/F/9336-9

MOVE
11

[lr+A], Rd

I 1 I 0 I ~~~o~~ I 0 I 0 I 0 I

MOVE

1
.1

Ilr

I I
Rd

644
OO-IW
01-IX
10-IY
11-IZ
[lZ+n], rd

I 0 I 0 11

Opcode .
15
11
T·states
3 [4TR] = 0
4 [4TR] 1
Bus TIming

Figure 6-5 (4TRJ = 0
Figure. 6·6 {4TRJ ...==1
OperatIon
MOVE [mid, Rd
data memory ..... Rd
MOVE [lr+A], Rd
data memory ..... Rd
MOVE [IZ + n], rd
data memory ..... rd

III
I

1-189

In
~

::;
~
c

6.0 Reference Section
MOVE

(Continued)

Move Immediate

Syntax
MOVE

n, rd

-immediate, limited register

MOVE

n, [lr]

-immediate, indexed

Affected Flags
None

Description
Moves the immediate value n into the destination specified.
The destination may be either a register, rd, (limited to the
active registers RO-R15), or data memory via an index register, Ir. The value n is 8 bits wide.

Example
Load the current accumulator with the value of 4.
MOVE

;Load accumulator

4, A

Instruction Format

n, rd

MOVE

1I 0 I 1 I 1 1
.
1

Opcode

MOVE

n, [lr]

I I

Ir
15

6 J-

n[4-0]

OO-IW
01-IX
10-IY
11-IZ

T-states
MOVE
MOVE

n, rd
n, [lr]

-2
-3

Bus Timing
MOVE
MOVE

n, rd
n, [lr]

-Figure 6-1
-Figure 6-7

Operation
MOVE

n, rd

n-+ rd
MOVE n, [lr]
n -+ data memory

1-190

6.0 Reference Section
MOVE

C
"tJ
co

(Continued)

MOVE

Syntax
MOVE

Rs, Rd

-register, register

MOVE
MOVE

Rs, [mlrJ
Rs, [Ir+ AJ

-register, indexed
-register, register-relative

MOVE

rs, [lZ + nJ

-limited register, immediate-relative

Rs
15
MOVE
1 11

I0I0

I0 I 0 I

Opcode

00
01
10
11

post-decrement
no change
post Increment
pre-Increment

00
01
10
11

IW
IX
IY
IZ

TlIF/9336-10

MOVE
.1

Rs, [Jr+AJ

111101010111010111
Opcode
.

1 1
Rs

6 J,

OO-IW
01-IX
10-IY
11-IZ
MOVE

rs, [Z + nJ

0 1 0 1 0 11 1
1
.1 Opcode .
11
15
T-states
MOVE Rs, Rd
MOVE Rs, [mlrJ
MOVE Rs, [Jr+ AJ
MOVE rs, [JZ + nJ

;select main A, alt B
;Load the Transmitter FIFO

The second example "pushes" the current accumulator's
contents onto an external data stack, which is pointed to by
the index register IX.
A, [IX -J

Rs, [mlrl

Example
The first example loads the Transmitter FIFO with a data
byte in register 20.

MOVE

Description
Moves the contents of the source register into the destination specified. The source register operand Rs may specify
any active CPU register; where as the source register operand rs is limited to the active registers RO-R15. The destination operand may specify either any active CPU register,
Rd, or data memory via one of the index register modes;
[mlrl, [lr+AJ, [IZ+n]. The index register-relative mode,
[lr+ Al. forms its data memory address by adding the contents of the index register Ir to the unsigned 8-bit value contained in the currently active accumulator. The. immediaterelative mode, [lZ + nJ, forms its data memory address by
adding the contents of the index register IZ to the unsigned
8-bit immediate value n.

0,1
R20, RTR

Rs, Rd
1

Affected Flags
None

EXX
MOVE

0l:Io
0l:Io

Instruction Format

Move Register

;push accum to ext. stack

The third example demonstrates the random access of a
data byte within a logical record contained in memory. The
index register IY contains the base address of the logical
record.
ADDA R9, A
;calculate offset into record
MOVE R20, [lY + AJ
;update data byte in record

n
3

-2
-3
-3
-3

Bus Timing
MOVE Rs, Rd
MOVE Rs, [mlrJ
MOVE Rs, [Jr+AJ
MOVE rs, [JZ + nJ

In the final example, the 4th element of an Error Count table
is updated with a new value contained in the current accumulator. The index register IZ points to the 1st entry of the
table.
MOVE A, [IZ + 3J
;update 4th element of table

-Figure 6-1
-Figure 6-6
-Figure 6-6
-Figure 6-6

Operation
MOVE Rs, Rd
MOVE Rs, [mlrJ
MOVE Rs, [Jr+AJ
MOVE rs, [JZ + nJ

-Rs-+ Rd
-Rs -+ data memory
-Rs -+ data memory
-rs -+ data memory

II
I

1-191

6.0 Reference Section
OR

(Continued)

ORA

OR Immediate

OR with Accumulator

Syntax

Syntax
-imm~diate,

Affected Flags

ORA
ORA

N,Z

Affected Flags

Description

N,Z

Logically ORs the immediate value n to the register rsd and
places the result back into the register rsd. Note that only
the active registers RO-R15 may be specified for rsd. The
value of n is 8 bits wide.

Description

n, rsd

limited register

-register, register
-register, indexed

Rs, Rd
Rs, [mlr)

Logically ORs the source register Rs to the active accumulator and places the result into the destination specified.
The destination may be either a register, Rd, or data memory via an index register mode, [mlr). Note that register bank
selection determines which accumulator is active.

Example
Mask both the Transmitter and Receiver interrupts via the
Interrupt Control Register (lCR}, R2. Leave the other interrupts unaffected.
EXX 0,0
;select main reg banks
OR 000000118, ICR ;mask transmitter and
; receiver interrupts

Example
Write an 11-bit word to the Transmitter's FIFO. This example assumes that the index register IZ points to the location
of the data in memory.
TCR.settings: .EQU 001010008

Instruction Format

0
.1

11 10 11

Opcode
15

.
11

EXX
1,1
MOVE TCR.settings,A
MOVE [lZ+],R20
ORA
R20,TCR
MOVE [lZ+),RTR
Instruction Format
ORA Rs, Rd

rsd
3

T-states
2
Bus Timing
Figure 6-1
Operation
rsd

;select main A, alt 8
;Ioad accumulator w/mask
;Ioad bits 8, 9, & 10
;write bits 8,9, 10 to {TCR}
;push 11-bit word to FIFO

1 1
Rs

n ~ rsd

15
ORA

9
Rs, [mlr)

11 I 0 I 1 I 0 11 I 0 I
Opcode

00
01
10
11

post-decrement
no change
post Increment
pre-Increment

00 - IW
01 - IX
10 - IY

11 - IZ

TL/F/9336-11

T-states
ORA
ORA

Rs, Rd
Rs, [mlr)

-2
-3

Bus Timing
ORA
ORA

Rs, Rd
Rs, [mlr)

-Figure 6-1
-Figure 6-7

Operation
ORA Rs, Rd
Rs OR accumulator ~ Rd
ORA Rs, [mlr)
Rs OR accumulator ~ data memory

1-192

6.0 Reference Section
RETF

Condition Specification Table for "CC"

(Continued)

Conditional Return

Rcc
Syntax
RETF f, s(,(g} (,rf})
Rcc (g(,rf})
-(optional syntax)
Affected Flags
If rf = 1 then N, Z, C, and V
Description
Conditionally returns control to the last instruction address
pushed onto the internal Address Stack by popping that address into the Program Counter, if the state of the flag referenced by f is equal to the state of the bit s; or, optionally, if
the condition cc is met. See the tables on the following page
for the flags that f can reference and the conditions that cc
may specify. The conditional return instruction also has two
optional operands, g and rf. The value of g determines if the
Global Interrupt Enable bit [GIE] is left unchanged (g=O),
restored from the Address Stack (g = 1), set (g = 2), or
cleared (g = 3). If the g operand is omitted then g = 0 is assumed. The second optional operand, rf, determines if the
ALU flags and register bank selections are left unchanged
(rf = 0), or restored from the Address Stack (rf = 1). If the rf
operand is omitted then rf=O is assumed.

001 B, 1

(binary)

0
1

(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111 )

2
3
4

; If [C] = 1 then return

6*
RC

[Z]
[Z]
[Z]
[Z]
[C]
[C]
[V]
[V]
[N]
[N]
[RA]
[RA] .
[RE]
[RE]
[DAV]
[DAV]
[TFF]
[TFF]

= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
.= 1
=0
= l'
=0
=1
=0
= 1
=0

Flag Referenced
[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

in (CCR)
in (CCA)
in (CCA)
in (CCA)
in (TSA)
in (TSA)
in (TSA)
in (TSA)

"Note: The value of f for [DAV) differs from the numeric
value for the position of [DAV) in I TSR l.

Instruction Format

Condition Tested for

Flag Reference Table for lit"

Example
This example demonstrates both syntaxes of the conditional return instruction testing for a carry result from a previous
instruction; (Le., [C] = 1). If the condition is met then the
return occurs, else the next instruction following the return
is executed. The current environment is left unchanged.
RETF

cc
Z
NZ
EO
NEO
C
NC
V
NV
N
P
RA
NRA
RE
NRE
DA
NDA
TFF
NTFF

6 J,

OO-GIE not affected
01-Restore GIE
10-SetGIE
11-Clear GIE
T-states

2 if condition is not met
3 if condition is met
Bus Timing
Figure 6-1 if condition is not met
Figure 6-2 if condition is met
Operation

If flag f is in state s then
Case g of
0: leave [GIE] unaffected, (default)
1: restore [GIE] from Address Stack
2: set [GIE]
3: clear [GIE]
End case
If rf= 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack
End if
Address Stack - . PC
End if

II
I

1-193

r---------------------------------------------------------------------~

~
~
Cf)

6.0 Reference Section

RET Unconditional Return

ROT

Syntax

co
C

RET

(Continued)

ROT

Ig I,rfll

Rotate
Rsd, b

-register

Affected Flags
N,Z,C

Affected Flags
If rf= 1 then N, Z, C, and V
Description

Description

Unconditionally returns control to the last instruction address pushed onto the internal Address Stack by popping
that address into the Program Counter. The unconditional
return instruction also has two optional operands, g and rf.
The value of g determines if the Global Interrupt Enable bit
[GIE] is left unchanged (g = 0), restored from the Address
Stack (g = 1), set (g = 2), or cleared (g = 3). If the g operand
is omitted then g = 0 is assumed. The second optional operand, rf, determines if the ALU flags and register bank selections are left unchanged (rf = 0), or restored from the Address Stack (rf = 1). If the rf operand is omitted then rf = 0 is
assumed.

Rotates the contents of the register Rsd b bits to the right
and places the result back into that register. The bits that
are shifted out of the LSB are shifted back into the MSB,
(and copied into the Carry flag). The value b may specify
from 0 to 7 bit rotates.
Example
Add 3 to the Address Stack Pointer contained in the Internal
Stack Pointer register liSP}, R30.
MOVE
ROT

ADD
ROT
MOVE

Example
Return from an interrupt.
RET

1,1

ISP, RB
RB, 4
3, RB
RB, 4
RB,ISP

;get IISPI
;shift [ASP] to low order nibble
;add 3 to [ASP]
;shift [ASP] to high order nibble
;store new liSP}

Instruction Format

;Restore environment & return

I I

Instruction Format

Rsd

T-states

Bus Timing
Figure 6-1

OO-GIE not affected
01-Restore GIE
10-SetGIE
11-ClearGIE

Operation

T-states
2
Bus Timing

Rsd

Figure 6-1

TLlF9336-12

Operation
Case g of
0: leave [GIE] unaffected, (default)
1: restore [GIE] from Address Stack
2: set [GIE]
3: clear [GIE]
End case
If rf= 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack
End if
Address Stack ----+ PC

1-194

6.0 Reference Section
SBCA

(Continued)

Subtract with Carry and
Accumulator

SHL

Syntax
SBCA Rs, Rd
-register, register
SBCA Rs, [mlr]
-register, indexed
Affected Flags
N,Z,C,V
Description
Subtracts the active accumulator and the carry flag from the
source register Rs, placing the result into the destination
specified. The destination may be either a register, Rd, or
data memory via an index register mode, [mlr]. Negative
results are represented using the two's complement format.
Note that register bank selection determines which accumulator is active.
Example
Subtract the constant 109 from the index register IW, (which
is 16 bits wide).
SUBA A, A
;Clear the accumulator
SUB
109, R12
;Iow byte of IW-109
SBCA R13, R13
;high byte of IW-borrow
Instruction Format
SBCA Rs, Rd

I
15

Rsd

15
T-states
2
Bus Timing
Figure 6-1
Operation

SBCA Rs, [mlr]
1

I0 I

I0 I 1 I 1 I

Opcode

t
00 -

post-decrement
01 - no change
10 - post Increment
11 - pre-increment

~~_ _ _ _ _ _ _ _~~O

Shift Left

Syntax
SHL Rsd, b
-register
Affected Flags
N,Z,C
Description
Shifts the contents of the register Rsd b bits to the left and
places the result back into that register. Zeros are shifted in
from the right, (Le., from the LSB). The value b may specify
from 0 to 7 bit shifts. The Carry flag contains the last bit
shifted out.
Example
Place a new internal Address Stack Pointer into the Internal
Stack Pointer register (ISP}, R30. Assume that the new
[ASP] is located in register 20.
MOVE ISP,RB
;read liSP} for [DSP]
AND
00001111 B,RB ;save [DSP] only
SHL
R20,4
;Ieft justify [ASP]
ORA
R20,ISP
;combine [ASP] + [DSP],
; then place into liSP}
Instruction Format

l
00 -IW

Rsd
TL/F19336-14

01 - IX
10 - IY
11 - IZ
TL/F9336-13

T-states
SBCA Rs, Rd
-2
SBCA Rs, [mlr]
-3
Bus Timing
SBCA Rs, Rd
-Figure 6-1
SBCA Rs, [mlr]
-Figure 6-7
Operation
SBCA Rs, Rd
Rs - accumulator - carry bit ~ Rd
SBCA Rs, [mlr]
Rs - accumulator - carry bit ~ data memory

1-195

6.0 Reference Section
SHR

(Continued)

Shift Right

SUB

Syntax

SHR

Rsd, b

Subtract Immediate

Syntax

SUB n, rsd

-register

-immediate, limited register

Affected Flags

N,Z,C,V

N,Z,C

Description

Subtracts the immediate value n from the register rsd and
places the result back into the register rsd. Note that only
the active registers RO-R15 may be specified for rsd. The
value of n is limited to 8 bits; (signed range: + 127 to
-128). Negative numbers are represented using the two's
complement format.

Shifts the contents of the register Rsd b bits to the right and
places the result back into that register. Zeros are shifted.in
from the left, (Le., from the MSB). The value b may specify
from 0 t07 bit shifts. The Carry .flag contains the last bit
shifted out.
Example

Example

Right justify the Address .Stack Pointer from the Internal
Stack Pointer register {ISP}, R30.
MOVE ISP, R20
;Load [ASP] from liSP}
SHR
R20,4
;right justify [ASP]

Subtract the constant 3 from register 10.
SUB 3, R10
; R10 - 3 --+ R10
Instruction Format

Instruction Format

11 11 10 ~~101~ 01 0 10 1
15

Rsd

Opcode
15

T-states

Bus Timing
Figure 6-1

2
Bus Timing
Figure 6-1

Operation

rsd - n --+ rsd

Operation

o~~________~ __~
Rsd
TLlF/9336-15

1-196

T-states

0 10 11 10 I

rsd

6.0 Reference Section
SUBA

(Continued)

TRAP

Subtract with Accumulator

Syntax
SUBA
AS,Ad
As, [mlr]
SUBA
Affected Flags
N,Z,C,V

-register, register
-register, indexed

Affected Flags
None
Description
Pushes the Program Counter, the Global Interrupt Enable bit
[GIE), the ALU flags, and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the memory address
created by concatenating the contents of the Interrupt Base
Aegister IIBA} to the value of v extended with zeros to 8
bits. If the value of g' is equal to "1" then the Global Interrupt Enable bit [GIE) will be cleared. If the g' operand is
omitted, then g' = 0 is assumed. The vector number v
points to one of 64 Interrupt Table entries; (range: 0 to 63).
Since some of the Interrupt Table entries are used by the
hardware interrupts, the TAAP instruction can simulate
hardware interrupts. The following table lists the hardware
interrupts and their associated vector numbers:

Description
Subtracts the active accumulator from the source register
As and places the result into the destination specified. The
destination may be either a register, Ad, or data memory via
an index register mode, [mlr]. Negative numbers are represented using the two's complement format. Note that register bank selection determines which accumulator is active.
Example
In the first example, the value 4 is placed into the currently
active accumulator, that accumulator is subtracted from the
contents of register 20, and then the result is placed into
register 21.
MOVE
SUBA

4, A
;Place constant into accum
A20, A21
;A20 - accum ~ A21
In the second example, the alternate accumulator of register bank B is selected and then subtracted from register 20.
The result is placed into the data memory pointed to by the
index register IZ and then the value of IZ is incremented by
one.
EXX
0, 1
;Select alt accumulator
SUBA A20, liZ +) ;A20 - accum ~ data mem
;and increment data pointer
Instruction Format
SUBA As, Ad

Hardware Interrupt Vector Table

TAAP

I I0I I I0

(Binary)

28
4
8
12
16
20

(011100)
(000100)
(001000)
(001100)
(010000)
(010100)

8, 1

;TFE interrupt simulation

Instruction Format

SUBA As, [mlr]

Interrupt
NMI
AFF/OAlAA
TFE
LTA
BIAQ
TO

Example
Simulate the Transmitter FIFO Empty interrupt.

I
Ad

Software Interrupt

Syntax
TAAP v I,g'}

I0 I
+

00 - post-decrement
01 - no change
10 - post Increment
II - pre-Increment

o
15
6 5
T-states
2
Bus Timing
Figure 6-1
Operation
PC & [GIE) & ALU flags & register bank selections
~ Address Stack
if g' = 1
then clear [GIE)
Create PC address by concatonating the IIBA} register to
the vector number v as shown below:

Opcode

t
00 - IW
01 - IX

10 - IY

II - IZ

TlIF/9336-16

T-states
SUBA As, Ad
SUBA As, [mlr)

-2
-3

Bus Timing
SUBA As, Ad
SUBA As, [mlr)

-Figure 6-1
-Figure 6-7

Operation
SUBA Rs, Ad
As - accumulator ~ Ad

I I I
{IBR}

I0 I 0 I

!Lpc

LI-5------~~------~7--~~5----------~0

SUBA As, [mlr]
As - accumulator ~ data memory

TL/F/9336-17

1-197

6.0 Reference Section
XOR

(Continued)

Exclusive OR Immediate

XORA

Syntax
XOA n, rsd

-immediate, limited register

XOAA
XOAA

Affected Flags
N,Z
Description

Encode/decode a data byte in register 15.
XOA code_pattern, A15
;encode/decode

Example
Decode the data byte just received and place it into data
memory. This example assumes that the accumulator contains the "key" and that the index register IY points to the
location where the information should be stored.
EXX
1,1
;select alternate banks
XOAA .. ATA, [lY + ] ;decode received byte and
; save it

Instruction Format
Opcode

15
T-states

-register, register
-register, indexed

Logically exclusive OAs the source register As to the active
accumulator and places the result into the destination specified. The destination may be either a register, Ad, or data
memory via an index register mode, [mlr]. Note that register
bank selection determines which accumulator is active.

Example

0 11 1 1 1 0 I

As, Ad
As, [mlr]

Affected Flags
N,Z
Description

Logically exclusive OAs the immediate value n to the register rsd and places the result back into the register rsd. Note
that only the active registers AO-A15 may be specified for
rsd. The value of n is 8 bits wide.

Exclusive OR with Accumulator

Syntax

Instruction Format

Bus Timing
Figure 6-1
Operation
rsd XOA n -+ rsd

XOAA As, Ad
1

XORA Rs, [mlr]

I0I

I 0 11
Opcode

I
.

00
01
10
11

post-decrement
no change
post Increment
pre-increment

00 - IW .
01 - IX
10 - IY
11 - IZ
TL/F 19336-1 B

T-states
XORA Rs, Rd
XORA Rs, [mlr]

-2
-3

Bus Timing
XORA Rs, Rd
XORA Rs, [mlr]

-Figure 6-1
-Figure 6-7 .

Operation
XORA Rs, Rd
Rs XOR accumulator -+ Rd
XORA Rs, [mlr]
Rs XOR accumulator -+ data memory

1-198

6.0 Reference Section

(Continued)

TABLE 6-2. Instructions Versus T-states, Affected Flags, and Bus Timing

Instruction

T-states

Affected
Flags

Timing
Figure

Instruction

T-states

Affected
Flags

Timing
Figure

ADCA

Rs, Rd

N,Z,C,V

6·1

MOVE

Rs, [mlr]

6-7

ADCA

Rs, [mlr]

N,Z,C,V

6-7

MOVE

Rs, [lr + A]

6-7

ADD

n, rsd

N,Z,C,V

6-1

MOVE

rs, [lZ + n]

6-7

MOVE

[mlr],Rd

3 [4TR] = 0
4 [4TR] =' 1

6-5
6-6

MOVE

[lr + A], Rd

3 [4TR] - 0
4 [4TR] = 1

6-5
6-6

MOVE

[lZ+ n], rd

3 [4TR] = 0
4 [4TR]='1

6-5
6-6

ADDA

Rs, Rd

N,Z,C,V

6-1

ADDA

Rs, [mlr]

N,Z,C,V

6-7

AND

n, rsd

N,Z

6-1

ANDA

Rs, Rd

N,Z

6-1

ANDA

Rs, [mlr]

N,Z

6-7

BIT

rs, n

CALL

CMP

rs, n

CPL

Rsd

EXX

ba, bb (,g)

6-1

Jee

2 false
3 true

6-1
6-2

N,Z

6-1

n, rsd

6-2

ORA

Rs, Rd

N;Z,C,V

6-1

ORA

Rs, [mlr]

N,Z

6-1

Ree

(g (,rf))

--"-

N,Z

6-1

N,Z

6-7

N,Z

6-7

2 false
3 true

N,Z,C,V·

6-1
6-2

RET

(g(,rf))

N,Z,C,V*.

6-1

RETF

f, s (,(g) (,rf))

2 false
3 true

N,Z,C,V*

6-1
6-2

N,Z,C

6-1

JMP

f, s, n

2 false
3 true

6-1
6-2

ROT

Rsd,b

JMP

6-2

SBCA

RS,Rd

N,Z,C,V

6-1

JMP

6-4

SBCA

Rs, [mlr]

N,Z,C,V

6-7

JRMK

RS,b,m

6-4

SHL

Rsd,b

N,Z,C

6-1

LCALL

(2+2)

6-3

SHR

Rsd,b

N,Z,C

6-1

LCALL

Rs, p, s, nn

(2+2)

6-3

SUB

n, rsd

N,Z,C,V

6-1

LJMP

(2+2)

6-3

SUBA

Rs, Rd

N,Z,C,V

6-1

LJMP

[lr]

6-1

SUBA

Rs, [mlr]

N,Z,C,V

6-7

LJMP

Rs,p,s,nn

(2+2)

6-3

TRAP

v (,g')

MOVE

n, rd

6-1

XOR

n, rsd

N,Z

6-1

MOVE

n, [lr]

6-7

XORA

Rs, Rd

N,Z

6-1

MOVE

Rs, Rd

6-1

XORA

Rs, [mlr]

N,Z

6-7

6-1

·Note: If rf = 1 then N. Z. C. and V are affected,

III

1-199

m
~

6.0 Reference Section

CO
Q.

(Continued)

TABLE 6-3. Instruction Opcodes

OOOO-OFFF

101010101
Opcode

1 0 1 0 10 11
Opcode

1 0 1 0 11 10
Opcode

2000-2FFF

1000-1 FFF

n
11

KEY

Instruction

Opcode

Hex

1 1
rsd

1
rs

1 1
rsd

I
0

ADD

n, rsd

I
0

MOVE

rs, [lZ + n]

I
0

SUB

n, rsd

rnlr
IrIr
Ir+
+Ir

00
01
10
11
Ir
00
01
10
11

IW
IX
IY
IZ

9
3000-3FFF

IOpcode
0 11 I 1 I

1 0 11 I 0 11
Opcode

1 0 11 11 I 0
Opcode

BOOO-B7FF

I I I

1
n

I I I

1
n

I I I

11
1
rn

11101010101
Opcode
15

I I I

I0 IOpcode
1I1I1I
15

1
n

7000-7FFF

I I I

6000-6FFF

I I I

011
10101
Opcode
15

5000-5FFF

1
n

4000-4FFF

I I I

1
b

I I I
rs

I I

rsd

I I I
rsd

1 1
rsd

I I I
rs

1 1
Rs

1-200

I
0

CMP

rs, n

I
0

AND

n, rsd

I
0

n, rsd

I
0

XOR

n, rsd

I
0

BIT

rs, n

I
0

JRMK

RS,b,rn

NCHG
RI
EI
01

00
01
10
11

9'
0
1
1

NCHG
01
ba/bb

000
001
010
011
100
101
110
111

[Z]
[C]
[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

6.0 Reference Section

.."

(Continued)

~
~

TABLE 6-3. Instruction Opcodes (Continued)

BBOO-BBFF

11 1010101 1 10
Opcode
15

1
n[7-5] .

I I I

B
1

I I I

n[4-0]

I I I

MOVE

n, [lr]

LJMP

Rs, p, s, nn

1
0

I I

1
nn

I I I

BCOO-BOFF .1110101011111011
s
Opcode

OOOO-FFFF

KEY

Instruction

Opcode

Hex

I
0

mlr
IrIr
Ir+
+Ir

00
01
10
11
Ir
00
01
10
11

I I I

IW
IX
IY
IZ

9
BEOO-BFFF

111010101111111
.
Opcode
s
B

15
OOOO-FFFF

I I I

I Ip I

I I I

1
nn

I I I

1
4

I I I

AOOO-A1FF

I I I

1
m

I
6

I I I

MOVE

[lZ+n1. rd

AOOA

Rs, [mlr]

6
1
m

I I I

AOCA

Rs, [mlr]

0
1

ba/bb

6
1
m

111011101011101
Opcode

111011101010111
Opcode

~
1

I I I II I I
rd
I
3

111011101010101
Opcode

A400-A5FF

A200-A3FF

1
n

NCHG
RI
EI
01

I I I

IOpcode
0 I0 I1 I

LCALL Rs, p, s, nn

9000-9FFF

00
01
10
11

I I I
Rs

1
4

SUBA

Rs, [mlr]

000
001
010
011
100
101
110
111

[Z]
[C]
[V]

[t-:J]
[RA]
[RE]
[OAV]
[TFF]

III
I

1-201

m
~

6.0 Reference Section

(Continued)

D..
C

TABLE 6-3. Instruction Opcodes (Continued)

Hex

Opcode

ASOO-A7FF

1 1 1 1
1
111011101011111 1
Opcode
Rs
m 1 Ir 1
1
15
B
S
4
0

SBCA Rs, [mlr]

ABOO-A9FF

111011101110101
Opeode

1
1
1 1 1 1
m 1 Ir 1
Rs
1
B
S
4
0

ANOA Rs, [mlr]

1
1
1 1 1 1
m 1 Ir 1
Rs
1
B
S
4
0

ORA

AAOO-ABFF

111011101110111
Opeode
15

KEY

Instruction

Rs, [mlr]

mlr
IrIr
Ir+
+Ir

00
01
10
11
Ir
00
01
10
11

IW
IX
IY
IZ

9
ACOO-AOFF

1
1 1 1 1
111011101111101 1
Opeode
m 1 Ir 1
Rs
1
15
B
S
4
0

XORA Rs, [mlr]

AEOO-AE1F

11101110111111101010101 1 1 1 1
Opeode
Rs
1
15
4
0

CPL

1
9 1 ba 1 bb 1 0 1 0 1 0 1
S
4
3
2
0

EXX

ba, bb I.g1

1
1 1
f
9 1 rl 1 s 1
1
4 3 2
S
0

RETF
Ree

f,sl.lgll,rlll
Igl,rlll

1 IrllOIOIOlol
9
6
4 3
0

RET

AEBO-AEFB

1110111011111110111
Opeode
15

AFOO-AF7F

1110111011111111101
Opeode
15

AFBO-AFFO

1110111011111111111
Opeode
15

BOOO-BFFF

11 1 0 1 1 1 1 1 1 1 1 1 1
Opeode
n
15
11

1
1
3

1-202

1 1
rd
0

NCHG
RI
EI
01
g'

Rsd
0
1
1

Igl.rlll

MOVE n, rd
1

00
01
10
11

NCHG 1
01
ba/bb

000
001
010
011
100
101
110
111

[Z]
[C)
[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

6.0 Reference Section

"tJ

(Continued)

~
~

TABLE 6-3. Instruction Opcodes (Continued)

Opcode

COOO-C1FF

1 1 1 1
1
111110101010101 1
Rd
Opcode
m 1 Ir 1
1
15
6
4
a
0

MOVE

[mlr], Rd

C200-C3FF

1
1 1 1 1
111110101010111 1
Rs
m 1 Ir 1
Opcode
1
15
a
6
4
0

MOVE

Rs, [mlr]

C400-C47F

1
Ir 1

1111101010111010101
Opcode
15

KEY

Instruction

Hex

1 1 1 1
Rd
4

MOVE

[lr+A1. Rd

mlr
IrIr
Ir+
+Ir

00
01
10
11
Ir
00
01
10
11

IW
IX
IY
IZ

9
C4aO-C4FF

caOO-CaFF

CAOO-CAFF

SHL

Rsd,b

ROT

Rsd,b

1
0

1 1 1 1 1
n

JMP

CALL

1
0

7
1

11111010111110101
Opcode

g'
0
1
1

NCHG 1

ba/bb

4
1

1 1 1 1
Rsd

1 1
b
1

NCHG
RI
EI

Rsd,b

SHR
1

1 1 1 1
Rsd

1 1
(a-b) 1

Rs, [lr+A]

MOVE
1

1 1 1 1
Rsd

11111010111011111
Opcode
15

CCOO-CCFF

11111010111011101
Opcode
15

CBOO-CBFF

1 1

11111010111010111
Opcode
15

1 1 1 1
Rs
4

11111010111010101
Opcode
15

C900-C9FF

1
Ir 1

1111101010111010111
Opcode

00
01
10
11

1 1 1 1 1

n
7

000
001
010
011
100
101
110
111

[Z]
[C)
[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

1
0

III
1-203

m
~

6.0 Reference Section

(Continued)

TABLE 6-3. Instruction Opcodes (Continued)

COOO-C060

KEY

Opcode

Hex
11

Instruction

I 11 0 I 0 11 I 1 10 I 1 I 01 I
Opcode

10101010101

[lr]

LJMP

mlr
IrIr
Ir+
+Ir

00
01
10
11
Ir

C080-C09F

CEOO
OOOO~FFFF

11111010111110111110101
Opcode

I I I
Rs

JMP

LJMP

00
01
10
11

11 11 10 10 11 11 11 10 0 10 10 10 10 10 10 10
.
Opcode
15

9
00
01
10
11

II I I

I I I

0
1

CE80
OOOO-FFFF

11 11

I 0 10 11

11 11 10 11"10 10 10 10 10
Opcode

I 0 10 I

I
I

I I I

11111010111111111111
Opcode
g'

IOpcode
1 I 0 I 1-1

NCHG
01
ba/bb

I I I
I
0

OOOO-OFFF

LCALL

0
1

CF80-CFFF

NCHG
RI
EI
01

_ 15

IW
IX
IY
IZ

I
10

I I
f

I I I
v

I I I

TRAP

v{,g'}

JMP
Jcc

f, S, n
n

I I I

I
0

1-204

000
001
010
011
100
101
110
111

[Z]
[C)
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

6.0 Reference Section

""C
co

(Continued)

W
0I:loo
0I:loo

TABLE 6-3. Instruction Opcodes (Continued)
Opcode

Hex
EOOO-E3FF

E400-E7FF

EBOO-EBFF

1111111010101
Opcode
15
9

1 1 1 1
Rd

1 1 1 1
Rs

1 1 1
Rd
1

0
1 1 1 1
Rs

1 1 1 1
Rd

1111111011101
Opcode

Instruction

1111111010111 1
Opcode
15
9

KEY

Rs, Rd

AOCA

RS,Rd

AOOA

mlr

SUBA

Rs, Rd

IrIr
Ir+
+Ir

00
01
10
11
Ir

1 1 1 1
Rs

00
01
10
11

IW
IX
IY
IZ

9
ECOO-EFFF

1 1 1 1
1111111011111 1 1 1 1
Opcode
Rd
Rs
1
1
15
9
0
4

FOOO-F3FF

1111111110101
Opcode
15

F400-F7FF

FCOO-FFFF

1 1 1 1
Rs

1 1 1
Rd
1

1 1 1 1
Rd

[]EJ
ORA

RS,Rd

XORA

Rs, Rd

ba/bb

1
0

1 1 1 1
Rs

1 1 1 1
Rd
1

Rs, Rd

NCHG
RI
EI
01

1 1 1 1
1111111111101 1 1 1 1
Opcode
Rd
Rs
1
1
15
9
0
4
1111111111111
Opcode

ANOA
1

1 1 1 1
Rs

Rs, Rd

1111111110111
Opcode
15

FBOO-FBFF

SBCA

00
01
10
11

MOVE
1
0

Rs, Rd

000
001
010
011
100
101
110
111

[Z]
[C)
[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

•
1-205

6.0 Reference Section

(Continued)

6.2 REGISTER SET REFERENCE
The register set reference contains detailed information on the bit definitions of all special function registers that are addressable in the CPU. This reference section presents the information in three forms: a bit index, a register description and bit
definition tables. The bit index is an alphabetical listing of all status/control bits in the CPU-addressable function registers, with a
brief summary of the function. The register description is a list of all CPU-addressable special function registers in alphabetical
order.' The 'bit definition tables describe the location and function of all control and status bits in the various CPU-addressable
special function registers. These tables are arranged by function.
6.2.1 Bit Index
An alphabetical listing of all status/control bits in the CPU-addressable special function registers, with a brief summary of
function. Detailed definitions are provided in Section 6.2.3, Bit Definition Tables.
Location

Bit

Name

i}.4IB.·· •. ·•. ·•.:·.·.• . . • ·.

FourT.Stat~ Bead •..•
poll/ ACKnowledge
Address Stack Pointer
Auxilliary Transceiver control
Advance Transmitter Active
Bi-directionallnterrupt Control
Bi-directionallnterrupt ReQuest
Carry
CPU Clock Select
Clock Out Disable
Data AVailable
Data Error or Message End
Data Stack
Data Stack Pointer
Data memory Wait-state select
Fill Bits
Global Interrupt Enable
Invalid Ending Sequence
Interrupt Mask select
Interrupt Vector
Instruction memory Wait-state select
Line Active
Loss of Mid Bit Transition
Lock Out Remote
internal LOOP-back
Line Turn Around
Negative
receiver OVerFlow
Odd Word Parity
PARity error
POLL
Protocol Select
Receiver Active
Received Auto-Response
Receiver DISabled while active
Receiver Error
Receive FIFO
Receive FIFO Full
Receiver INvert
Receiver Interrupt Select
Receive Line Quiesce
RePeat ENable
Remote Read
Receive/Transmit FIFO
Remote Write
Select Error Codes
Select Line Receiver
Transmitter Active
Transceiver Clock Select
Transmit FIFO

ASP3-0
AT7-0
ATA
BIC
BIRO
C
CCS
COD
DAV
DEME
DS7-0
DSP3-0
DW2-0
FB7-0
GIE
, IES
IM4-0
IV15-8
IW1,0

LA
LMBT
LOR
, LOOP
LTA

N
OVF
OWP
PAR'
POLL
PS2-0
RA
RAR
RDIS
RE
RF10-8
RFF
RIN
RIS1,0
RLO
RPEN
RR
RTF7-0
RW
SEC
SLR
TA
TCS1,0
TF10-8

· · ·. .• · · ••.. . ····i····· . •. •

1·206

. .AC8\
NCF
ISP
ATR
TCR
ACR
CCR
CCR
OCR
ACR
TSR
NCF
OS
ISP
OCR
FBR
ACR
ECR
ICR
IBR
OCR
NCF
ECR
ACR
TMR
NCF
CCR
ECR
TCR
ECR
NCF
TMR
TSR
NCF
ECR
TSR
TSR
NCF
TMR
ICR
TCR
TMR
CCR
RTR
CCR
TCR
TCR
TSR
OCR
TCR

(3)
[1]
[7-4]
[7-0]
[4]
[4]
[4]
[1]
[7]
[2]
[3]
[3]
[7-0]
[3-0]
[2-0]
[7-0]
[0]
[2]
[4-0]
[7-0]
[4,3]
[5]
[1]
[1]
[6]
[4]
[3]
[4]
[3]
[3]
[0]
[2-0]
[4]
[2]
[0]
[5]
[2-0]
[6]
[4]
[7,6]
[7]
[5]
[6]
[7-0]
[5]
[6]
[5]
[6]
[6,5]
[2-0]

Function

... I imirl999titr()!

,"oW,,"_

Receiver Status
Stacks
Receiver Control
Transmitter Control
Interrupt Control
Interrupt Control
Arithmetic Flag
Timing Control
Timing Control
Receiver Status
Receiver Status
Stacks
Stacks
Timing Control
Transmitter Control
Interrupt Control
Receiver Error Code
Interrupt Control
Interrupt Control
Timing Control
Receiver Status
Receiver Error Code
Remote Interface
Transceiver Control
Receiver Status
Arithmetic Flag
Receiver Error Code
Transmitter Control
Receiver Error Code
Receiver Status
Transceiver Control
Receiver Status
Receiver Status
Receiver Error Code
Receiver Status
Receiver Control
Receiver Status
Receiver Control
Interrupt Control
Receiver Control
Receiver Control
Remote Interface
Transceiver Control
Remote Interface
Receiver Control
Receiver Control
Transmitter Status
Transceiver Control
Transmitter Control

6.0 Reference Section

(Continued)

6.2.1 Bit Index (Continued)
An alphabetical listing of all status/control bits in the CPU·addressable special function registers, with a brief summary of
function. Detailed definitions are provided in Section 6.2.3, Bit Definition Tables.
Bit

Name

TFE
TFF
TIN
TLD
TM7-0
TM15-8
TMC
TO
TRES
TST

Transmit FIFO Empty
Transmit FIFO Full
Transmitter INvert
Timer LoaD
TiMer
TiMer
TiMer Clock select
Time Out flag
Transceiver RESet
Timer StarT
oVerflow
Zero

V
Z

Function

Location
NCF
TSR
TMR
ACR
TRL
TRH
ACR
CCR
TMR
ACR
CCR
CCR

6.2.2 Register Description

[7]
[7]
[3]
[6]
[7-0]
[7-0]
[5]
[7]
[7]
[7] .
[2]
[0]

Transmitter Status
Transmitter Status
Transmitter Control
Timer
Timer
Timer
Timer
Timer
Transceiver Control
Timer
Arithmetic Flag
Arithmetic Flag

ACR AUXILIARY CONTROL REGISTER
[Main R3; read/write]

A list of all CPU-addressable special function registers, in
alphabetical order.

I TST I TlD I TMC I BIC

The Remote Interface Configuration register (RICI, which is
addressable only by the remote system, is not included. See
Section 6.3, Remote Interface Reference for details of the
function of this register.

321
rsv

I COD I LOR I GIE

rsv ... state is undefined at all times.

TST

Each register is listed together with its address, the type of
access available, and a functional description of each bit.
Further details on each bit can be found in Section 6.2.3, Bit
Definition Tables.

- Timer StarT ... When high, the timer is enabled
and will count down from it's current value.
When low, timer is disabled. Timer is stopped by
writing a 0 to [TST].

TlD

- Timer LoaD ... When high, generates timer load
pulse. Cleared when load complete.

TMC

TIMer Clock select ... Selects timer clock frequency. Should not be written when [TST] is
high. Can be written at same time as [TST] and
[TlD).
TMC

Timer Clock

BIC

(CPU-ClK)/16
1
(CPU-ClK)/2
BI-directlonal Interrupt Control ... Controls direction of BIRQ.
BIC

BIRQ

1-207

Input
Output
Clock Out Disable ... When high, ClK-OUT output is at TRI-STATE.

COD

lOR

Lock Out Remote ... When high, a remote system is prevented from accessing the BCP.

GIE

Global Interrupt Enable ... When low, disables
all maskable interrupts. When high, works with
[lM4-0] to enable maskableinterrupts.

4TR

4 T-state Read .•• When high, RE'AI5 strobe timing is changed to allow more time between the
TRI-STATE of the AD lines by the BCP and the
falling of the RE:AD strobe. All data memory reads
take four T-states when this bit is set. See Section.2.2.2 for more information.

6.0 Reference Section

(Continued)
CCR CONDITION CODE REGISTER
[Main RO; bits 0-3, 5-7 read/write, bit 4 read only]
76543210

ATR AUXILIARY TRANSCEIVER REGISTER
[Alternate R2; read/write]
7

543

I AT7 I AT6 I AT5 I AT4 I AT3

2
AT2

AT1

I ATO I

TX-ACT Hold Time (p.s)
(if TCLK = 8 MHz)

00000
00001
00010
00011

0
0.5
1.0
1.5

11111

15.5

- Time Out flag ... Set high when timer counts to
zero. Cleared by writing a 1 to this location or by
stopping timer (by writing a 0 to [TST».
RR
- Remote Read ... Set on the trailing edge of a
REM-RD pulse, if RAE is asserted and {RIC} is
pointing to Data Memory. Cleared by writing a 1
to this location.
RW
- Remote Write ... Set on the trailing edge of a
REM-WR pulse, if RAE is asserted and {RIC} is
pointing to Data Memory. Cleared by writing a 1
to this location.
BIRO - BI-directional Interrupt ReQuest ... [Read
only). Reflects the logic level of the Bi-directional
interrupt pin, BIRO. Updated at the beginning of
each instruction cycle.
N
- Negative .. . A high level indicates a negative
result generated by an arithmetic, logical or shift
instruction.

AT7 -0 - Auxiliary Transceiver ... In 5250 protocol
modes, bits 2-0 define the receive station address, and bits 7-3 control the amount of time
TX-ACT stays asserted after the last fill bit.
In 8-bit protocol modes, bits 7-0 define the receive station address.
For further information, see Section 3.0 Transceiver.
ATR 7-3

I TO I RR I RW I BIRO I

V
C

1-208

oVerflow ... A high level indicates an overflow
condition generated by an arithmetic instruction.
- Carry ... A high level indicates a carry or borrow
generated by an arithmetic instruction. During a
shift/rotate operation the state of the last bit shifted out appears in this location.
- Zero ... A high level indicates a zero result generated by an arithmetic, logical or shift instruction.
Further information: Section 2.2.1 ALU, Section
2.2.3 Interrupts.

6.0 Reference Section

(Continued)

DCR DEVICE CONTROL REGISTER
[Alternate RO; read/write]

DS DATA STACK
[Main R31; read/write]

76543210

ICCS ! TCS1! TCSO !IW1
CCS

!IWO ! OW2! OW1 ! OWO

543

OCLK
OCLK/2

TCS1,O - Transceiver Clock Select ... Selects transceiver clock, TCLK, frequency.
OCLK represents the frequency of the on-chip
oscillator, or the externally applied clock on input X1. X-TCLK is the external transceiver
clock input.
TCS1,O
TCLK
00
OCLK
01
OCLK/2
10
OCLK/4
11
X-TCLK
IW1,O
- Instruction memory Walt-state select ...
Selects from 0 to 3 wait states for accessing
instruction memory.
OW2-0 - Data memory Walt-state select ... Selects
from 0 to 7 wait states for accessing data memory.

1-209

OS1

I OSO I

- Data Stack ... Data stack input/output port.
Stack is 16 bytes deep. Further information:
Section 2.1.1.8 Stack Registers.

rsv ... state is undefined at all times.

CPUCLK

I OS7 \ OS6 \ OS5 I OS4 ! OS3 ! OS2\
OS7-0

- CPU Clock Select . .. Selects CPU clock frequency. OCLK represents the frequency of the
on-chip oscillator, or the externally applied clock
on input X1.
CCS

6.0 Reference Section (Continued)
ECR ERROR CODE REGISTER
[Alternate R4 with [SEC] high; read only]
7

654

FBR FILL-BIT REGISTER
[Alternate R3; read/write]
1

543

I rsv I rsv Irsv I OVF I PAR liES ILMBT I RDIS I

I FB7 I FB6 I FB5 I FB4 I FB3 I FB2 I FB1 I FBO I

OVF

- Receiver oVerFlow ... Set when the receiver
has processed 3 words and another complete
frame is received before the FIFO is read by the
CPU. Cleared by reading (ECR) or by asserting
[TRES].

FB7 -0 - Fill Bits ... 5250 fill-bit control. Further information: Section 3.0 Transceiver.

PAR

- PARity error ... Set when bad (odd) overall
word parity is detected in any receive frame.
Cleared by reading (ECR) or by asserting
[TRES].

IES

- Invalid Ending Sequence ... Set when the
"mini-code violation" is not correct during a 3270,
3299, or 8-bit ending sequence. Cleared by reading (ECR) or by asserting [TRES].
LMBT - Loss of Mid-Bit Transition ... Set when the expected Manchester Code mid-bit transition does
not occur within the allowed window. Cleared by
reading (ECR) or by asserting [TRES].
RDIS - Receiver DISabled while active ... Set when
transmitter is activated while receiver is active,
without RPEN being asserted. Cleared by reading
(ECR) or by asserting [TRES]. Further information: Section 3.2 Transceiver Functional Description.

1-210

6.0 Reference Section

"'0
CD

(Continued)

(,)

IBR INTERRUPT BASE REGISTER
[Alternate R1; read/write]
7654321

IIV151IV14!IV13!IV12!IV11 !IV10! IV9

I IV8 I

011100
000100
001000
001100
010000
010100

543

I RISO I rsv I IM4 11M3 11M2 I IM1 I IMO I
RIS1,O Interrupt Source
00
01
10
11

15
8
5
o
The interrupt vector is obtained by concatenating IIBR J
with the vector address:
NMI
Receiver
Transmitter
Line Turn Around
Bi-directional
Timer

I RIS1

RIS1,O - Receiver Interrupt Select ... Defines the
source of the Receiver Interrupt.

I I I IBIR I I I 10
10 I. Ivector
I address
I I I
.

Vector Address

rsv •.. state is undefined at all times

IV15-8- Interrupt Vector ... High byte of interrupt and
trap vectors. Further information: Section 2.2.3,
Interrupts.
Interrupt Vector

Interrupt

0l:Io
0l:Io

ICR INTERRUPT CONTROL REGISTER
[Main R2; read/write]

RFF + RE
DAV + RE
(unused)
RA

" +" indicates logical "or"

Priority

Further information: Section 3.2.3 Transceiver Interrupts.

1 high
2 i
3
4 !
5 low

IM4-0 - Interrupt Masks ... Each bit, when set high,
masks an interrupt. 1M3 functions as an interrupt
mask only if BIRO is defined as an input. When
BIRO is defined as an output, 1M3 controls the
state of BIRO.
IM4-0

Interrupt

o0 0 0 0 No Mask
X X X X 1 Receiver
X X X 1 X Transmitter
X X 1 X X Line Turn-Around
X 1 X X X Bi-Directional
1 XXXX Timer
Further information: Section 2.2.3 Interrupts.

1-211

6.0 Reference Section

(Continued)

ISP INTERNAL STACK POINTER
[Main R30; read/write]
7654321

NCF NETWORK COMMAND FLAG REGISTER
[Main R1; read only]
0

76543

210

ITFE / RFF I LA I LTA I DEME I RAR lACK / POLL I

IASP3/ASP2/ASP1/ASPO/DSP3/DSP2/DSP1/DSpol
ASP3-0 - Address Stack Pointer ... Input/output port
of the address stack pointer. Further information: Section 2.1.1.8 Stack Registers.
DSP3-0- Data Stack Pointer ... Input/output port of the
data stack pointer. Further information: Section
2.1.1.8 Stack Registers.

TFE
RFF

1-212

- Transmit FIFO Empty ... Set high when the
FIFO is empty. Cleared by writing to {RTR I.
- Receive FIFO Full ... Set high when the Receive FIFO contains 3 received words.
Cleared by reading to {RTR I.
- Line Active ... Indicates activity on the receiver input. Set high on any transition;
cleared after detecting no input transitions for
16 TCLK periods.

LTA

Line Turn Around ... Set high when end of
message is received. Cleared by writing to
{RTR l. writing a "1" to this location, or by
asserting [TRES].

DEME

Data Error or Message End ... In 3270 &
3299 modes, asserted when abyte parity error is detected. In 5250 modes, asserted when
the [111] station address is decoded and
[DAV] is asserted. Cleared by reading {RTR I.
Undefined in 8-bit modes and in the first frame
of 3299 modes.

RAR

ACK

POLL

Received Auto-Response ... Set high when
a 3270 Auto-Response message is decoded
and [DAV] is asserted. Cleared by reading
{RTR I. Undefined in 5250 and 8-bit modes
and in the first frame of 3299 modes.
Poill ACKnowledge ... Set high when a 3270
poll/ack command is decoded and [DAV] is
asserted. Cleared by reading {RTR I. Undefined in 5250 and 8-bit modes and in the first
frame of 3299 modes.
POLL ... Set high when a 3270 poll command
is decoded and [DAV] is asserted. Cleared by
reading {RTR I. Undefined in 5250 and 8-bit
modes and in the first frame of 3299 modes.
Further information: Section 3.0 Transceiver.

6.0 Reference Section

(Continued)

RTR RECEIVE/TRANSMIT REGISTER
[Alternate R4; read/write]
7

TCR TRANSCEIVER COMMAND REGISTER
[Alternate RS; read/write]
7

543210

IRTF7' RTFS\ RTF5\ RTF4' RTF3\ RTF2\ RTF1 \ RTFO \

I RLQ \ SEC \ SLR \ ATA \ OWP \ TF10 , TF9\

RTF7-0 -

RLQ

Receive Transmit FIFO's ... Input/output
port to the least significant eight bits of receive
and transmit FIFO's. [OWP], [TF10-8] and
[RTF7-0] are pushed onto the transmit FIFO
on moves into (RTRI. [RF10-8] and [RTF70] are popped from receiver FIFO on moves
out of (RTR I. Further information: Section 3.0
Transceiver.

- Receive Line Qulesce ... Selects number of
line quiesce bits the receiver looks for.
RLQ

SEC
SLR

TF8\

Number of
Qulesces

- Select Error Codes ... When high (ECRI is
switched into (RTR I location.
- Select Line Receiver ... Selects the receiver
input source.
SLR

Source

ATA

OWP

DATA-IN
On-chip analog
line receiver
- Advance Transmitter Active ... When high,
TX-ACT is advanced one half bit time so that
the transmitter can generate 5.5 line quiesce
pulses.
- Odd Word Parity .,. Controls transmitter
word parity.
OWP

o
TF10-8

1-213

Word Parity
Even
Odd

- Transmit FIFO ... [OWPl, [TF10-8] and
[RTF7 -0] are pushed onto transmit FIFO on
moves into (RTR I.
Further information: Section 3.0 Transceiver.

6.0 Reference Section (Continued)
TMR TRANSCEIVER MODE REGISTER
[Alternate R7; read/write]
7

543210

I TRES 1 LOOP 1 RPEN 1 RIN
TRES

LOOP

RPEN

RIN
TIN
PS2-0

TRH TIMER REGISTER - HIGH
[Main R29; read/write]
76543210

I· TIN 1 PS2 1 PS1 1 PSO I

ITM151TM141TM131TM121TM111TM10lTM91TMSI
TM15-S- TiMer ... Input/output port of high byte of timer.
Further information: Section 2.1.1.4 Timer Reg.
isters.

- Transceiver RESet .... Resets transceiver
when high. Transceiver can also be reset by
RESET, without affecting [TRES].
- Internal LOOP-back ... When high, TX-ACT
is disabled (held at 0) and transmitter serial
data is internally directed to the receiver serial
data input.
- RePeat ENable ... When high, the receiver
can be active at the same time as the transmitter.
- Receiver INvert ... When high, the receiver
serial data is inverted.
- Transmitter INvert ... When high the transmitter serial data outputs are inverted.
- Protocol Select ... Selects protocol for both
transmitter and receiver.
PS2-0 Protocol
000 3270
001 3299 multiplexer
010 3299 controller
01 1 3299 repeater
100 5250
1 01
5250 promiscuous
110 S-bit
1 1 1 S-bit promiscuous
Further information: Section 3.0 Transceiver.

1-214

6.0 Reference Section

(Continued)

TRL TIMER REGISTER-LOW
[Main R2S; read/write]
7

I TM71

TSR TRANSCEIVER STATUS REGISTER.
[Alternate R5; read only]
2

76543

TM61 TM5\ TM4\ TM3\ TM2\ TM1 \ TMO

TM7-0- TIMer ... Input/output port of low byte of timer.
Further information: Section 2.1.1.4 Timer Registers.

I TFF

\ TA \ RE \ RA \ DAV \ RF10 \ RF9

0
RFS

TFF

- Transmit FIFO Fu" ... Set high when the transmit FIFO is full. I RTR 1 must not be written to
when [TFF] is high.
.

- Transmitter Active ... Reflects the state of. TXACT, indicating that data is being transmitted.
Unlike TX-ACT, however, [TA] is not disabled by
[LOOP].
- Receiver Error ... Set high when a receiver error is detected. Cleared by reading I ECR 1 or by
asserting [TRES).

- Receiver Active ... Set high when a valid starting sequence is received. Cleared wh~m either
an end of message or an error is detected. In
5250 modes; [RA] is cleared at the same time
as [LA].
DAV
- Data AVailable ... Set high when valid data is
available in IRTR 1and I TSR I. Cleared by reading I RTR I, or when an error is detected.
RF10-S- Receive FIFO.; ; [RF10-S] and [Frr:F7-0] reflect the state of the top word of the. receive
FIFO.
Further information: Section 3.0 Transceiver.
I

1-215

6.0 Reference Section

(Continued)

6.2.3 Bit Definition Tables
The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers. The Remote Interface Configuration register, (RIC I, which is addressable only by a remote processor is not
included.
6.2.3.1 Processor
Bit
Timing/
Control

CCS

Name
CPU Clock Select

Location
OCR [7]

Function

Reset State
1

Selects CPU clock frequency.
CCS
0
1

CPUCLK
OClK
OClK/2

Where OClK is the frequency of the on-chip oscillator, or
the externally applied clock on input X1.
DW2-0

Data memory
Wait-state select

OCR [2-0]

111

Selects from 0 to 7 wait states for accessing data memory.

IW1,O

Instruction memory
Wait-state select

OCR [4,3]

Selects from 0 to 3 wait states for acceSSing instruction
memory.

Clock Out Disable

ACR [2]

When high, ClK·OUT is at TRI·STATE.

'4T';'sfiittfFlead'"

'ACR[3]

()

When high; data memoryreaastakefolJrT~states;

lORt

Lock Out Remote

ACR [1]

When high, a remote processor is prevented from accessing
the BCP or its memory.

RRt

Remote Read

CCR [6]

Set on the trailing edge of a REM·RD pulse, if RAE is
asserted and (RIC I is pointing to Data Memory. Cleared by
writing a 1 to [RR].

RW·

Remote Write

CCR [5]

Set on the trailing edge of a REM-WR pulse, if RAE is
asserted and (RIC I is pointing to Data Memory. Cleared by
writing a 1 to [RW).

BIC

Bi·directional
Interrupt Control

ACR [4]

Controls the direction of BIRO.

COD
.··.~IB<

Remote
Interface

Interrupt
Control

BIC

BIRQ

0
1

Input
Output

BIRO

Bi·directional
Interrupt ReQuest

CCR [4]

[Read Only]. Reflects the logic level of the BIRO input.
Updated at the beginning of each instruction cycle.

GIE

Global Interrupt
Enable

ACR [0]

When low, disables all maskable interrupts. When high,
works with [lM4-0] to enable maskable interrupts.

IM4-0

Interrupt Mask
select

ICR [4-0]

11111

Each bit, when set high, masks an interrupt.
IM4-0

Interrupt

00000

No Mask
Receiver
Transmitter
Line Turn-Around
Bi·Directional
Timer

XXXX1
XXX1X
XX1XX
X1XXX
1XXXX

Priority

1
2
3
4
5

High

t
.J,
low

1M3 functions as an interrupt mask only when BIRO is
defined as an input. When BIRO is defined as an output,IM3
controls the state of BIRO.
·These bits represent the only visibility and control that the processor has Into the operation of the remote interface controller. The Remote Interface Configuration
register, (RICI, accessible only by a remote processor, provides further control functions. See Remote Interface section for more Information.

1-216

6.0 Reference Section

(Continued)

6.2.3 Bit Definition Tables (Continued)
The following tables describe the location and function of all control and status bits in the various SCP addressable special
function registers. The Remote Interface Configuration register, (RIC l. which is addressable only by a remote processor is not
included.
6.2.3.1 Processor (Continued)
Bit
Interrupt
IV15-8
Control
(Continued)

Name
Interrupt Vector

Location

Reset State

Function

ISR [7-0]

00000000

High byte of interrupt and trap vectors.
The interrupt vector is obtained by concatenating (ISR) with
the vector address:
Interrupt

Vector Address

NMI
Receiver
Transmitter
Line Turn Around
Bi-Directional
Timer

011100
000100
001000
00'1100
010000
010100

Interrupt Vector

10 "0

15
RIS1,O

Receiver Interrupt ICR [7,6]
Select

ASP3-0

Address Stack
Pointer

DSP3-0 Data Stack
Pointer

Arithmetic
Flags

vector address
5

Defines the source of the receiver interrupt.
RIS1,O Interrupt Source
00
01
10
11

Address
and
Data
Stacks

ISR

RFF + RE
DAV + RE
(unused)
RA

ISP [7-4]

0000

Address stack pointer. Writing to this location changes the
value of the pointer.

ISP [3-0]

0000

Data stack pointer. Writing to this location changes the value
of the pointer.

XXXXXXXX Data Stack Input/Output port. Stack is 16 bytes deep.

DS7-0

Data Stack

OS [7-0]

Carry

CCR [1]

A high level indicates a carry or borrow, generated by an
arithmetic instruction. During a shift/rotate operation the
state of the last bit shifted out appears in this location.

Negative

CCR [3]

A high level indicates a negative result generated by an
arithmetic, logical, or shift instruction.

oVerflow

CCR [2]

Zero

CCR [0]

1-217

A high level indicates an overflow condition, generated by an
arithmetic instruction.
A high level indicates a zero result generated by an
arithmetic, logical, or shift instruction.

6.0 Reference Section

(Continued)

6.2.3. Bit Definition Tables (Continued)
The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers. The Remote Interface Configuration register, I RIC l. which is addressable only by a remote processor is not
included.
6.2.3.1 Processor (Continued)
Bit
Timer

Name

TLD

Timer LoaD

Location
ACR [6]

Function

Reset State

Set high to load timer. Cleared automatically when load
complete.

TM15-8

TiMer

TRH [7-0]

XXXXXXXX

TM7-0

TiMer

TRL [7-0]

XXXXXXXX

TMC

Timer Clock
select

ACR [5]

Input/output port of high byte of timer.
Input/output port of low byte of timer.
Selects timer clock frequency. Must not be written when
[TST] high. Can be written at same time as [TST] and
[TLD].
TMC Timer Clock
0
1

CPU-CLK/16
CPU-CLK/2

Time Out flag

CCR [7]

Set high when timer counts down to zero. Cleared by writing
a 1 to [TO] or by stopping the timer (by writing a 0 to [TST]).

TST

Timer StarT

ACR[7]

When high, timer is enabled and will count down from its
current value. Timer is stopped by writing a 0 to this location.

6.2.3.2 Transceiver
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
of data frames. For further information see the Transceiver section.
Bit

Name

Transceiver LOOP
Control

internal
LOOP-back

TMR [6]

Protocol Select

TMR [2-0]

PS2-0

Location

RTF7-0 Receive/Transmit RTR [7-0]
FIFOs

Reset State
0

Function
When high, TX-ACT is disabled (held at 0) and transmitter
serial data is internally directed to the receiver serial data
input.

000

Selects protocol for both transmitter and receiver.
PS2-0

Protocol

000
001
010
011
100
1 01
110
111

3270
3299 Multiplexer
3299 Controller
3299 Repeater
5250
5250 Promiscuous
8-bit
8-bit Promiscuous

XXXXXXXX Input/output port of the least significant 8 bits of receive and
transmit FIFOs. [OWP], [TF10-8] and [RTF7-0] are pushed
onto the transmit FIFO on moves to I RTR}. [RF10-8] and
[RTF7 -0] are popped from receive FIFO on moves from
IRTR}.

1-218

6.0 Reference Section

(Continued)

6.2.3 Bit Definition Tables (Continued)
6.2.3.2 Transceiver (Continued)
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver section.
Bit

Name

Transceiver TCS1,O Transceiver Clock
Select
Control

Location Reset State
OCR [6,5]

Function
Selects transceiver clock, TCLK, source.
TCS1,O

(Continued)

TRES
Transmitter ATA
Control
AT7-3

TMR [7]

Resets transceiver when high. Transceiver can also be reset
by RESET, without affecting [TRES).

Advance Transmitter TCR [4]
Active

When high, TX-ACT is advanced one half bit time so that the
transmitter can generate 5.5 line quiesce pulses.

Transceiver RESet

Auxiliary
Transceiver control

ATR [7-3]

XXXXX

In 5250 modes. Controls the time TX-ACT is held after the last
fill bit.
AT7-3

TX-ACT Hold Time (fA-s)
(If TCLK = 8 MHz)

00000
00001
00010

0
0.5
1

11111

15.5

FB7-0

Fill Bit select

FBR [7-0] XXXXXXXX The value in this register contains the 1's complement of the
number of additional 5250 fill bits selected.

OWP

Odd Word Parity

TCR [3]

Controls transmitter word parity.
OWP
0
1

Receiver
Control

TCLK

00
OCLK
01
OCLK/2
10
OCLK/4
X-TCLK
11
OCLK is the frequency of the on-chip oscillator, or the
externally applied clock on input X1. X-TCLK is the external
transceiver clock input.

Word Parity
Even
Odd

TF10-B Transmit FIFO

TCR [2-0]

TIN

Transmitter INvert

TMR[3]

AT7-0

Auxiliary
Transceiver control

ATR [7-0] XXXXXXXX In 5250 modes, [AT2-0] contains the station address. In B-bit
modes, [AT7 -0] contains the station address.

RF10-B Receive FIFO

TSR [2-0]

000
0

XXX

[OWP], [TF10-B] and [RTF7 -0] are pushed onto the
transmit FIFO on moves to (RTR J.
When high, the transmitter serial data outputs are inverted.

Reflects the state of the most significant 3 bits in the top
location of the receive FIFO.

RIN

Receiver INvert

TMR[4]

When high, the receiver serial data is inverted.

RLQ

Receive Line
Quiesce

TCR [7]

Selects number of line quiesce bits the receiver requires
before it will indicate receipt of a valid start sequence.
RLQ Number of Line Qulesce Pulses
0
1

2
3

RPEN

RePeat ENable

TMR [5]

When high, the receiver can be active at the same time as the
transmitter.

SEC

Select Error Codes

TCR [6]

When high, (ECR J is switched into (RTR J location.

1-219

6.0 Reference Section

(Continued)

SLR

Name
Select Line
Receiver

Location Reset State
TCR [5]

(Continued)

Transmitter
Status

Receiver
Status

Function
Selects the receiver input source.
SLR

Source

0
1

DATA-IN
On-Chip Analog
Line Receiver

Transmitter Active TSR [6]

Reflects the state of TX-ACT, indicating that data is being
transmitted. Is not disabled by [LOOP].

TFE

Transmit FIFO
Empty

NCF[7]

Set high when the FIFO is empty. Cleared by writing to
IRTR).

TFF

Transmit FIFO
Full

TSR [7]

Set high when the FIFO is full. IRTRI must not be written
when [TFF] is high.

polll

NCF [1]

Set high when a 3270 poll lack command is decoded and
[DAV] is asserted. Cleared by reading I RTR I. Undefined in
5250 and a-bit modes and in the first frame of 3299 modes.

ACK

ACKnowledge
DAV

Data AVailable

TSR [3]

Set high when valid data is available in I RTR I and I TSR I.
Cleared by reading I RTR I , or when an error is detected.

DEME

Data Error or
Message End

NCF [3]

In 3270 or 3299 modes, asserted when a byte parity error is
detected. In 5250 modes, asserted when the [111] station
address is decoded and [DAV] is asserted. Undefined in a-bit
modes and first frame of 3299 modes.

Line Active

NCF[5]

Indicates activity on the receiver input. Set high on any
transition; cleared after no input transitions are detected for
16 TCLK periods.

LTA

Line Turn Around

NCF[4]

Set high when an end of message is detected. Cleared by
writing to I RTR I. writing a "1" to [LT A] or by asserting
[TRES].

POLL

NCF[O]

Set high when a 3270 Poll command is decoded and [DAV] is
asserted. Cleared by reading I RTR I. Undefined in 5250 and
a-bit modes and in the first frame of 3299 modes.

Receiver Active

TSR [4]

Set high when a valid start sequence is received. Cleared
when either an end of message or an error is detected.

RAR

Received
Auto-Response

NCF[2]

Set high when a 3270 Auto-Response message is decoded
and [DAV] is asserted. Cleared by reading I RTR I. Undefined
in 5250 and a-bit modes and in the first frame of 3299 modes.

Receiver Error

TSR [5]

Set high when an error is detected. Cleared by reading I ECR I
or by asserting [TRES].

RFF

Receive FIFO·
Full

NCF [6]

Set high when the receive FIFO contains 3 received words.
Cleared by reading I RTR I.

1-220

6.0 Reference Section (Continued)
6.2.3 Bit Definition Tables (Continued)
6.2.3.2 Transceiver (Continued)
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver section.
Bit

Name

Location Reset State

Function

Invalid Ending
Sequence

ECR [2]

Set when the first mini-code violation is not correct during a
3270, 3299 or a-bit ending sequence. Cleared by reading
(ECR I or asserting [TRES].

LMBT

Loss of Mid-Bit
Transition

ECR [1]

Set when the expected Manchester Code mid-bit transition
does not occur within the allowed window. Cleared by reading
(ECRI or by asserting [TRES].

OVF

receiver OVerFlow ECR [4]

Set when the receiver has processed 3 words and another
complete frame is received before the FIFO is read by the
CPU. Cleared by reading (ECR I or asserting [TRES].

PAR

PARity error

ECR [3]

Set when bad (odd) overall word parity is detected in any
receive frame. Cleared by reading (ECR I or asserting
[TRES].

RDIS

Receiver DISabled ECR [0]
while active

Set when transmitter is activated by writing to (RTR I while
receiver is still active, without [RPEN] first being asserted.
Cleared by reading (ECR I or asserting [TRES].

Receiver
IES
Error Codes

6_3 REMOTE INTERFACE CONFIGURATION REGISTER

low (BCP stopped). When set, the BCP begins executing at the current Program Counter address.
When cleared, the BCP finishes executing the current instruction, then halts to an idle mode.

This register can be accessed only by the remote system.
To do this, CMD and RAE must be asserted and the [LOR]
bit in the (ACRI register must be low.

In some applications, where there is no remote
system, or the remote system is not an intelligent
device, it may be desirable to have the BCP powerup/reset running rather than stopped at address
OOOOH. This can be accomplished by asserting
REM-RD, REM-WR and RESET, with RAE de-asserted. (Refer to Electrical Specification Section
for the timing information needed to start the BCP
in stand alone mode.)

76543210

IBIS I SS I FW I LR I LW I STRT I MS1 I MSO I RIC
BIS

Bidirectional Interrupt Status ... Mirrors the state
of 1M3 (( ICR I bit 3), enabling the remote system to
poll and determine the status of the BIRQ I/O.
When BIRO is an output, the remote system can
change the state of this output by writing a one to
BIS. This can be used as an interrupt acknowledge, whenever BIRO is used as a remote interrupt. For complete information on the relationship
between BIS, 1M3 and BIRQ, refer to Section 2.2.3
Interrupts.

MS1,O

Single-Step ... Writing a 1 with STRT low, the BCP
will single-step by executing the current instruction
and advancing the PC. On power up/reset this bit
is low.
Fast Write ... When high, with LW low, selects fast
write mode for the buffered interface. When low
selects slow write mode. On power up/reset this
bit is low (LW will also be low, so buffered write
mode is selected).

Latched Read ... When high selects latched read
mode, when low selects buffered read mode. On
power up/reset this bit is low. (Buffered read mode
is selected.)

Latched Write ... When high selects latched write
mode, when low selects buffered write mode. On
power up/reset this bit is low (FW will also be low,
so slow buffered write mode is selected).

STRT

STaRT ... The remote system can start and stop
the BCP using this bit. On power-up/reset this bit is

Memory Select 1,0 ... These two bits determine
what the remote system is accessing in the BCP
system, according to the following table:
MS1

MSO

Selected Function

a
a

1
1

Data Memory
Instruction Memory
Program Counter (Low Byte)
Program Counter (High Byte)

1
1

The BCP must be idle for the remote system to
read/write Instruction memory or the Program
Counter.
All remote accesses are treated the same (independent of where the access is directed using MSO
and MS1), as defined by the configuration bits LW,
LR, FW.

•

If the remote system and the BCP request data
memory access simultaneously, the BCP will win
first access. If the locks ([LOR], meR) are not set,
the remote system and BCP will alternate access
cycles thereafter.
On power-up/reset, MS1,O points to instruction
memory.
Power-up/Reset state of (RIC[7-0] I is 1000 0001.
1-221

6.0 Reference Section

(Continued)

6.4 DEVELOPMENT TOOLS
National Semiconductor provides tools specifically created
for the development of products that use the DP8344.
These tools consist of the DP8344 BCP Assembler System,
the DP8344 BCP Demonstration/Development Kit, and the
DP8344 BCP Multi-Protocol Adapter (MPA) Design/Evaluation Kit.

many of these products, we do not provide techni.cal support, or in any way guarantee the functionality of these products.
6.5.1 Crystal Supplier
The recommended crystal parameters for operation with the
DP8344 are given in Section 2.2.4. Any crystal meeting
these specifications will work correctly with the DP8344.
NEL Frequency Controls, Inc., Burlington, Wisconsin, has
developed crystals, the NEL C2570N and NEL C2571 N,
specifically for the DP8344 which meet these specifications.
The C2570N and C2571 N are both 18.8696 MHz fundamental mode AT cut quartz crystals. The C2571N has a
hold down pin for case ground and a third mechanical tie
down. NEL Frequency Controls, Inc. is located at:

6.4.1 Assembler System
The Assembler System· is an MS-DOS compatible program
used to translate the DP8344's instruction set into a directly
executable machine language. The system contains a macro cross assembler,. link editor and librarian. The macro
cross assembler provides nested macro definitions and expansions, to automate common instruction sequences,· and
source file inclusion nested conditional assembly, which allows the assembler to make intelligent decisions concerning
instruction sequence based on user directives. The linker
allows relocatable object sections to be combined in any
desired order. It can also generate a load map which details
each section's contribution to the linked module. The librarian allows for the creation of libraries from frequently accessed object modules, which the linker can automatically
include to resolve references.

NEL Frequency Controls, Inc.
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
6.5.2 System Development Tools
The DP8344, with its higher level of integration and processing power, has opened the IBM mainframe connectivity market to a wider range of product manufacturers, who until
now found the initial cost and time to market prohibitive.
This wider base of manufacturers created the opportunity
fora more extensive line of development tools that dealt not
only with the use of the DP8344 but also with the implementation of the 3270 and 5250 protocols: While National Semiconductor is dedicated to providing the Customer with the
proper tools in both areas, we also have aided and encouraged a number of third party suppliers to offer additional
development tools. This has further provided an avenue for
faster and more reliable product development in this product area. The development tools discussed in this section
are controller emulators and line monitors for the IBM 3270/
3299 and 5250 protocols.

6.4.2 Demonstration/Development Kit
The Demonstration/Development kit is a cost effective development tool that performs functions similar to an in-circuit emulator. The kit, developed by Capstone Technology,
Inc., Fremont, California, consists of a DP8344 based development board, a monitor/debugger software package, National Semiconductor's DP8344 video training tapes, and all
required documentation. The development board is a full
size PC card that contains a 22 square inch area for logic
prototype wiring. The monitor/debugger program displays
internal register contents and status information. It also provides functions such as execution break points and single
stepping.

A controller emulator is a device that emulates an IBM 3x74
cluster controller or a System 3x controller. With the
DP8344 both of these controllers can be emulated with the
same piece of hardware. The controller emulator allows the
designer to issue individual commands or sequences of
commands to a peripheral. This is very useful in characterizing existing equipment and testing of products under development. Capstone Technology offers such a product. Their
Extended Interactive Controller, part #CT-109, is a single
PC expansion card that can emulate both 3270 and 5250
control devices (the 3x74 and System 3X, respectively).
Newleaf Technologies, Ltd., Cobham, Surrey, England, and
Azure Technology, Inc., Franklin, Mass., also supply products in this area. Newleaf Technology offers the COLT52, a
twinax controller emulator, and Azure Technology offers a
controller made with their CoaxScope· and TwinaxScope
line monitors.
A line monitor is a device that monitors all the activity on the
coax or twinax cable. The activity includes both the commands from the controller and the responses from the peripheral. These devices typically decode the commands and
present them in an easy to read format. The individual transmissions are time stamped to provide the designer with responsetime information. The line monitors are very useful in
characterizing communications traffic and in determining
the source of problems during development or in the field.
Azure Technology offers both a 3270/3299 (Coax) and
5250 (Twinax) line monitor. Their Coax Scope and Twinax

6.4.3 Multi-Protocol Adapter (MPA)
Design/Evaluation Kit
The Multi-Protocol Adapter (MPA) is a PC expansion card
that emulates a 3270 or 5250 display terminal and supports
industry standard PC emulation software. The MPA comes
in a design/evaluation kit that includes the hardware, schematics and PAL equations, and software. including all the
DP8344 source code. This kit was produced to provide a
blueprint for PC emulation products and a cornerstone for
all 3270 and 5250 product development using the DP8344.
The code was developed in a modular fashion so it can be
adapted to any 3270 or 5250 application.
6.4.4 DP8344 BCP Inverse Assembler
The DP8344 BCP Inverse Assembler is a software package
for use in an HP 1650A or HP1651A Logic Analyzer, or in an
HP16500A Logic Analysis System with an HP 16510A
State/Timing Card installed. The inverse Assembler was developed by National Semiconductor to allow disassembly of
the DP8344 op-code mnemonics. This allows one to determine the actual execution flow that occurs in the system
being developed with the DP8344.
6.5 THIRD PARTY SUPPLIERS
The following section is intended to make. the DP8344 Customer aware of products, supplied by companies other than
National Semiconductor, that are available for use in developing DP8344 systems. While National Semiconductor has
supported these ventures and has become familiar with
1-222

6.0 Reference Section

(Continued)
The DP8344A exhibits a small amount of contention between certain bus signals as detailed in the Device Specifications section of this data sheet. The DP8344B interface
timing improvements are designed to reduce and/or eliminate this bus contention.

Scope are single PC expansion cards that can record, decode and display activity on the 3270 coax and 5250 twinax
line respectively. These devices also allow the play back of
the recorded controller information. Capstone Technology
also supplies a line monitor. The CT1 01 C, Network Analysis
Monitor (NAM), is a coax line monitor.

- 70 ns Data Memory
At a 20 MHz CPU clock rate, the DP8344B can support 70
ns static RAM for data memory with no wait states. The
DP8344A was limited to 55 ns static RAM for data memory with no wait states. (See Section 5.0 Device Specifications.)

These companies can be contacted at the following locations:
Azure Technology, Inc.
38 Pond Street
Franklin, Massachusettes 02038
(508) 520-3800

• READ
The timing of the READ strobe has been improved to reduce bus contention during a data memory access. There
is now more time between AD disabled and READ falling
as well as one~half T-state between READ rising and AD
enabled. In addition, a new 4 T-state read option has been
provided to eliminate bus contention. (See Section 5.0 Device Specifications for timing changes, and 4 T-state
Read later in this document for more information on the 4
T-state Read option.)

Capstone Technology
853 Brown Rd., Suite 207
Fremont, California 94539
(415) 438-3500
New Leaf Technology, Ltd.
24A High Street
Cobham
Surrey
KT113EB
ENGLAND
(0932) 66466

The user can therefore choose between a fast read mode
(3 T-states) with a small amount of contention and a slower read mode (4 T-states) with no contention.

For technical assistance in using the DP8344B, contact the
BCP Hot Line (817) 468-6676.

• AI AD Bus Timing
The timing of the A and AD buses has been changed to
eliminate bus contention during remote accesses of data
memory. There is now a one-half T-state TRI-STATE zone
during the bus transfer from local to remote control and
vice versa. (See Section 5.0 Device Specifications.)

TABLE 6-4. DP8344 Application Notes
App
Note No.
AN-623
AN-624

AN-516
AN-504
AN-499
AN-625
AN-627
AN-626
AN-641
AN-688

Title
Interfacing Memory to the DP8344B
A Combined Coax-Twisted Pair 3270 Line
Interface for the DP8344 Biphase
Communications Processor
Interfacing the DP8344 to Twinax
DP8344 BCP Stand-Alone Soft-Load
System
"Interrupts"-A Powerful Tool of the Biphase
Communications Processor
JRMK Speeds Command Decoding
DP8344 Remote Processor Interfacing
DP8344 Timer Application
MPA - A Multi-Protocol Terminal Emulation
Adapter Using the DP8344
The DP8344 BCP Inverse Assembler

-IWR
The timing of IWR has been changed such that IWR now
falls one T-state earlier. This eliminates bus contention
during the start of soft loads. (See Section 5.0 Device
Specifications.)
• IA Bus Softload Timing
The auto-increment of the IA bus address during soft
loads of instruction memory now occurs one T-state later
to maintain in-phase data and thereby eliminate bus contention. (See Seection 5.0 Device Specifications.)
• LCL
LCL is now removed when REM-RD is taken high on buffered reads of (RIC}, the program counter, and instruction
memory, to eliminate bus contention in this mode. (See
Section 5.0 Device Specifications.)

6.6 DP8344A AND DP8344B COMPATIBILITY GUIDE

- RIC
The hold time on slow buffered writes to (RIC} and the
program counter has been improved. (See Section 5.0 Device Specifications.)

The DP8344B is an enhanced version of the DP8344A, exhibiting improved switching performance and additional
functionality. The device has been characterized in a number of applications and found to be a compatible replacement for the DP8344A. Differences between the DP8344A
and DP8344B are dstailed in this section.

- "Kick-start"
The h.old time on REM-WR and REM-RD to RESET to
"kick-start" the CPU has been improved. (See Section 5.0
Device Specifications.)

6.6.1 Timing Changes to the CPU
Relative to the DP8344A, the DP8344B incorporates a number of timing changes designed to improve the system interface. These timing changes are improvements in the timing
specifications and therefore should allow the DP8344B to
drop into existing DP8344A designs without any hardware
modifications.

6.6.2 Additional Functionality of the DP8344B
6.6.2.1 4 T-state Read
To eliminate bus contention during memory accesses, a
new optional read mode has been created, controlled by

1-223

III
I

6.0 Reference Section

(Continued)
This can be accomplished by creating a section of "filler"
code that will occupy the instruction address range AFOOh
to AF7Fh. As an example, the "filler" section of code could
be as follows:

[4TR] in (ACR}. When a one is written to this bit, all subsequent data memory read operations expand to 4 T-states
with an extra one-half T-state between the falling edge of
ALE and the falling edge of READ. This eliminates bus contention on data memory read operations. After a BCP reset,
or when a zero is written to this bit, the DP8344B data memory read operations operate in 3 T-states, as in the
DP8344A, in which this bit was unused. (See Section 2.2.2
for more information.)

FILLER: • SECT x
: Start of ··filler" code section
.REPEAT 128 ; Repeat the following
instruction 128 times
JMP $
; Jump to self
.ENDR
; End of repeat block
.END

6.6.2.2 AI AD Reset State

The JMP $ instruction causes an infinite loop at that instruction. Thus one would be able to determine if the program
inadvertently entered the "filler" section of code. The repeat 128 instruction causes the section to occupy 128 bytes
of instruction memory which is the size of the affected address range.
Next, by using the Linker in the DP8344 BCP Assembler
System, one can specify that this "filler" section of code
must occupy instruction memory starting at address AFOOh
by using the -L option. For example, the following commands can be entered at the DOS command line to invoke
the Assembler and Linker (this assumes that the "filler"
section is located in the file FILLER.BCP):

After a BCP reset, the index registers and the A and AD
buses will be zero. In the DP8344A, their states were undefined after a reset.
6.6.2.3 RIC
Each time instruction memory is selected via (RIC[1,01l
(Le., (RIC} is set to XXXX XX01 binary), the next read (or
write) of instruction memory by a remote processor will always return (or update) the low order 8 bits of the 16 bit
instruction location pointed to by the program counter. In
the DP8344A, setting (RIC I had no affect on which instruction memory byte would next be fetched and an algorithm
had to be developed to determine this. (See Section 4.1.2
for more information.)

NBCPASM FILLER.BCP
NLINK -LFILLER=AFOO FILLR.BCO

6.6.2.4 Transceiver
When the Transceiver is reset, DATA-OUT now goes into a
state equal to [TIN] e [ATA], which eliminates coincident
transitions on DATA-OUT and DATA-DLY with TX-ACT.
(See Section 3.2 for more information.

This will prevent any other section of code from occupying
the range which the "filler" section of code is located in.
Hence, one would not have to be concerned about using
labels to specify the address in LJMP and LCALL instruction.

6.7 REPORT BUGS

6.8 GLOSSARY
3270-An IBM communication protocol originally developed for the 370 class mainframe that implements a star
topology using a single coax cable per slave device. In this
master-slave protocol, all communication is initiated by the
controller (master) and responses are returned by the terminal or other attached device (slave). The data is transmitted using blphase encoding at a bit rate of 2.3587 MHz.
3299-A communications protocol that is the 3270 protocol with an eight bit address frame added to the beginning
of each controller transmission between the start sequence and the first coax word. Currently, IBM only uses
three bits of the address field which allows up to eight devices to communicate with the controller through a multiplexer.
5250-An IBM communications protocol originally developed for the Series 3 that became widely used on the System 34/36/38 family of minicomputers and currently the
AS/400. It uses a multidrop bus topology on twin-ax cable.
This protocol is a master-slave type. The data is transmitted
using bl-phase encoding at a bit rate of 1 MHz.
accumulator-The implied source register of one operand
for some arithmetic operations. In the BCP, R8 in the currently enabled bank acts as the accumulator.
ALU-The Arithmetic Logic Unit, a component of the CPU
that performs all arithmetic (addition and subtraction), logical (AND, OR, XOR, compare, bit test, and complement),
rotational, and shifting operations.
ALU flags-Bits that indicate the result of certain ALU functions.

6.7.1 History
The DP8344 Data Sheet Reference, first published
10/29/87 (rev. 3.6), listed a total of 13 bugs. All these bugs
were corrected in the DP8344A, released to production April
1989. Subsequent to this date, an additional bug has been
reported. This bug is present in all versions of the BCP:
DP8344, DP8344A and DP8344B.
For additional information regarding differences in functionality between the DP8344B and DP8344A, see Section 6.6.
6.7.2 LJMP, LCALL Address Decode
The LJMP and LCALL instructions to the address range
AfOOh through AF7Fh do not function correctly. Both conditional and unconditional LCALL or LJMP instructions to this
address range will not decode as LCALL or LJMP instructions. Instead the address field will be incorrectly decoded
as the instruction. Thus a LJMP or LCALL to an instruction
in the address range AFOOh through AF7Fh will be decoded
as a RETF instruction.
Example: the instruction
LJMP AFOO
will be decoded as
AFOO
which is
RETF 000. 00
Note that LJMP and LCALL to all other addresses work correctly.
The LJMP or LCALL instruction should therefore not be
used to transfer program control to an instruction in the
range AFOOh to AF7Fh.
6.7.2.1 Suggested Work-around
The simplest work-around is not to place any code necessary for system operation in the affected address range.

1-224

6.0 Reference Section (Continued)
banked registers-Two or more sets of CPU registers that
occupy the same register space, but only one of which is
accessible at a time.
barrel shifter-Dedicated hardware for shifting and rotating.
BCP-An abbreviation for Biphase Communications Processor, the National Semiconductor DP8344.
blphase-In this communications signal encoding technique, the data is divided into discrete bit time intervals denoted by a transition in the center of the bit time. This technique combines the clock and data information into one
transmission. In 3270 and 3299 protocols, a mid-bit transition from low to high represents a bi-phase 1, and a mldbit transition from high to low represents a bi-phase O. For
the 5250 protocol, the definition of biphase logic levels is
reversed. Biphase encoding is also called Manchester II
encoding.
BIRQ-The Bidirectional Interrupt ReOuest. Without any
other notation, BIRO will refer to the BIRO interrupt itself.
BIRO with a bar on top of it (BIRO) is used where the pin is
referenced. BIRO in brackets ([BIRO]) is bit 4 in the
(CCR} register.
coax-(1) RG-62A1U 930 coaxial cable that is used in
3270 protocol systems. (2) Sometimes, this term is used to
refer to the 3270 protocol itself.
code vlolatlon-A violation of the bl-phase encoding format that is part of the start sequence. In 3270, 3299, and
the general purpose 8-blt mode, the code violation is 1%
bit times low and then 1% bit times high. In the 5250 protocol, the signal levels are reversed.
communications protocol-A set of rules which defines
the physical, electrical, control, and formatting specifications required to successfully transfer data between two
systems.
context swltch-Switching between two theoretically independent functions that should not affect each other except
under specified circumstances.
controller-The master device that initiates all communication to the slave device and controls the manner in which
the slave presents the information. It acts as the interface,
both physically and logically, between the slave terminals
and printers and a host processor.
CPU-CLK-The clock that the operation of the BCP's CPU
is synchronized to. The period of this clock which defines
T-state boundaries is either that of OCLK or one-half of
OCLK depending on the configuration of the BCP. The timer clock is also derived from CPU-ClK.
CUT-Control Unit Terminal. A mode of the controller
where attached devices have limited intelligence and are
perceived to be hardware extensions of the controller. The
controller directs all printer, screen, and keyboard activity.
OFT-Distributed Function Terminal. A controller mode
that supports multiple logical terminals in the same device.
The controller communicates in higher level commands via
data placed in the buffer. The slave device has a greater
amount of intelligence than the CUT mode device and is
responsible for the terminal operation.
direct coupled-The connection of the transceiver to the
transmission cable in a manner that does not isolate it from
DC voltages. Contrast this with transformer coupled.

dual port memory-A memory architecture that allows two
different processors to access the same memory range. alternately.
ending sequence-A defined sequence· of bits signifying
the end of a transmission. In 3270 and 3299, it consists of a
bl-phase a followed by a low to high transition on the bit
time boundary and two mini-code violations.
FIFO-A section of memory or, as in the case of the BCP
transceiver, a set of registers that are accessed in a First-In
First-Out method. In other words, the first data placed in the
FIFO by a write will be the first data removed by a read.
fill bits-Fill bits are bl-phase O's used only in the .5250
protocol. A minimum of three fill bits are required between
each frame of a multi-frame message. This number may
be increased by the controller to approximately 243 per the
SetMode command. There are always only three fill bits after the last frame of the transmission.
general purpose 8-blt mod~A generic communications
mode similar to 3270 and 5250 frame formatting using 8-bit
serial data and bl-phase signal encoding. The BCP supports both promiscuous and non-promiscuous modes.
Harvard architecture-A computer architecture where the
instruction and data memory are organized into two independent memory banks, each with their own address and
data buses.
hold time-The amount of time the line is driven at the end
of 5250 transmissions to suppress noise on the cabling system.
'
ICLK-The clock that identifies the start of each instruction
when it rises and indicates when the next instruction address is valid when it falls.
Immediate addressing, mode-An addressing method
where one operand, the data for Move instructions and the
address for Jump instructions, is contained in the instruction
itself.
.
"
Immediate-relative addressing mode-An addressing
method that adds an unsigned 8-bit immediate number' to
the index register IZ to form the data memory address of an
operand.
,
Indexed addressing mode-An addressing method that
uses the contents of an index register as the data memory
address for one of the operands in an instruction. ,
Interrupt latency-The time from when, an interrupt first
occurs until it begins executing at its interrupt vector.: .
jitter-Timing variations for signals of different harmonic
content that move the edges of a transmitted signal in time
causing uncertainty in their decoding.
jitter tolerance-The total amount of time an edge of a
transmitted bit may move and still have its data bit decoded
correctly.
LlFO-A sequence of registers or memory locations that
are accessed in a last-In First-Out method; in other words,
the last data written into the LIFO will be the first to be
removed by a read. Also known as ,a stack.
limited register set-In the BCP, the first 16 register address locations (RO-R11 in both banks and R12-R15) that
can be used in all instructions.

1-225

•

6.0 Reference Section

(Continued)
line hold-The act of driving the transmission line during
5250 transmissions at the end of a message to allow the
receivers to unsync. This insures that the receivers will not
see line noise as the start of another frame when the line
floats.
line Interface-All the circuity between the BCP and the
communications cable medium.
line reflection-Energy from a transmission that is not absorbed by a load impedance and can cause interference in
that signal.
Manchester II encodlng-See bl-phase encoding.
mask-(1) A mechanism that allows the program to specify
whether interrupts will be accepted by the CPU. (2) To disable the accepting of an interrupt by the CPU.
mld-blt-In bl-phase encoding, the transition in the center
of a bit time.
mini-code vlolatlon-A violation of the bl-phase encoding
format that is part of the ending sequence in 3270, 3299,
and the general purpose S-blt mode. The mini-code violation has no mid-bit transition being high for the entire bit
time. There is no mini-code violation in 5250.
multldrop-A communication method where all the slave
devices are attached to the same cable and respond to
controller commands and data only when their own address frame precedes the transmitted frame.
multi-frame message-Several bytes of data together in
the same uninterrupted message that have only one start
sequence and one ending sequence.
multlplexer-A device that receives 3299 protocol transmissions from a controller, strips off the address field, and
determines over which of eight ports to transmit the message in 3270 format. The device then directs the response
from the terminal back to the controller.
non-promlscuous-A receiver mode that only enables a
data available interrupt when the address frame of the message matches that previously specified. The 5250 and general purpose S-blt modes of the BCP support both promiscuous and non-promiscuous modes.
NRZ-Non Return to Zero. A data format that uses a high
level to represent a data 1 and a ·Iow level to represent a
data O. The signal level does not return to a zero level in
each bit time. See also NRZI.
NRZI-Non Return to Zero Inverted. A data format similar
to NRZ but with the signal levels reversed.
OCLK-The external Oscillator CLocK connected to the
BCP. This frequency, from a crystal or a clock, cannot be
changed by the BCP itself. CPU-CLK is derived from OCLK;
in addition, the transceiver can be configured so that TCLK
is derived from OCLK.
parlty-A one bit code, usually following data, that makes
the total number of 1's in a data word odd or even, including
the parity bit itself. It is included as an error checking mechanism.
POLL-A command issued by a controller to determine
changes in terminal status, such as keyboard activity or keylock.
POLLI ACK (PACK)-A command issued by a controller
to indicate to the terminal that the controller has recognized
the non-zero status response of the terminal to its POLL,
hence its full name poll/acknowledge.

pop-To remove data from a stack.
predistortion-The initial voltage step in a Manchester
encoded bit used to change frequency components of the
signal to limit introducing jitter.
promiscuous-A receiver mode that enables a data available interrupt regardless of the contents of the transmission
address frame. The 5250 and general purpose S-blt
modes of the BCP support both promiscuous and non-promiscuous modes.
push-To place data onto a stack.
qulesce pulse-A bl-phase 1 bit that is placed at the beginning of a transmission to charge the cable in preparation
for the transmission of data. In addition, the quiesce pulses
are used as part of the identifying start sequence. Typically, five quiesce pulses are placed there.
register addressing mode-An addressing method that
uses only operands contained in registers.
register-relative addressing mode-An instruction addressing mode that adds the unsigned 8-bit value in the
current accumulator to anyone of the index registers forming a data memory address for one of the instruction's operands.
remote access-An access to dual port memory by a
device other than the BCP.
repeater-A device used to extend the communication distance between a controller and a slave device by receiving
the message and re-transmitting it.
RIAS--The Remote Interface and Arbitration System that
allows a remote processor and the BCP to share the same
memory with arbitration of any conflict while the BCP is running. A remote processor may also stop and start the BCP
as well as read and write the Program Counter.
soft-Ioadable-A feature of a processor system that allows
another processor to provide it with instructions and data.
stack-See LIFO.
start sequence-A unique arrangement of bits that begin
each transmission to ensure proper frame alignment and
synchronization. Each transmission begins with five blphase encoded 1's quiesce pulses, a code violation, and
the sync bit of the first frame.
station address-The identification number of a 5250 terminal or other slave device that will specify which device on
a multidrop line a message is sent to.
sync bit-A bl-phase 1 that is placed as the first bit of a
frame.
T-state-The period of CPU-CLK.
TCLK-The Transceiver CLocK that runs both the transmitter and receiver at a frequency equal to eight times the required serial data rate. The clock can be obtained from a
scaled OCLK or from X-TCLK.
tlme-out-An interrupt that occurs when the timer reaches
a count of zero.
transceiver-The TRANSmitter used for sending messages and the reCEIVER used for reading messages.
transformer coupled-The isolation of the transceiver
from the transmission cable through the use of a transformer. Contrast this with direct coupled.
trar>--A BCP instruction that forces a software interrupt.

1-226

6.0 Reference Section (Continued)
TTl AR-Transmission Turn-around I Auto Response. An
acknowledgement by the terminal or other slave device that
a write command has successfully been received or that a
POLL command status response is all zero.
twin-ax-(1) The shielded pair cable that is used in a 5250
communications systems. (2) Sometimes used to refer to
the IBM 5250 communications protocol itself.

unmask-Enable the accepting of an interrupt by the CPU.
wait state-Additional T-states that may be added to a
memory access to increase the time from address generation to the beginning of either a memory read or write. The
BCP may add as many as seven data wait states and three
instruction wait states.
X-TCLK-The eXternal Transceiver CLocK. An independent clock source that the BCP transceiver operation may
synchronize to rather than from OCLK.

1-227

Section 2
Application Notes

Section 2 Contents
AN-641 MPA-II-A Multi-Protocol Terminal Emulation Adapter Using the DP8344 .......... .
AN-624 A Combined Coax-Twisted Pair 3270 Line Interface for the DP8344 Biphase
Communications Processor ....................................................... .
AN-623 Interfacing Memory to the DP8344B .......................................... .
AN-504 DP8344 BCP Stand-Alone Soft-Load System .................................. .
AN-499 "Interrupts"-A Powerful Tool of the Biphase Communications Processor ......... .
AN-625 JRMK Speeds Command Decoding .......................................... .
AN-627 DP8344 Remote Processor Interfacing ........................................ .
AN-626 DP8344 Timer Application ... '.' .............................................. .
AN-516 Interfacing the DP8344 to Twinax .: .......................................... .
AN-688 The DP8344 BCP Inverse Assembler ......................................... .

2-2

2-3
2-95
2-99,
2-101
2-112
2-117
2-121
2-135
2-152
2-172

r------------------------------------------------------------------.>
National Semiconductor
Application Note 641
Thomas Norcross
Paul J. Patchen
Thomas J. Quigley
Tim Short
Debra Worsley
Laura Johnson

MPA-II-A Multi-Protocol
Terminal Emulation
Adapter Using the DP8344

Table of Contents

APPENDIX A HARDWARE REFERENCE
MPA-II Schematic
MPA-II Layout
MPA-II Assembly Drawing
PAL Equations

1.0 INTRODUCTION
About This System User Guide
Contents of the MPA-II Design/Evaluation Kit
MPA-II Description
DP8344B BCP

APPENDIX B TIMING ANALYSIS

2.0 OPERATION

APPENDIX C FILTER EQUATIONS

System Requirements
Requirements for Design Development
Useful Tools
MPA-II Installation
Running Emulation: A Quick Start

APPENDIX D REFERENCES

1.0 INTRODUCTION
About This System User Guide
The purpose of this document is to provide a complete description of the Multi-Protocol Adapter II (MPA®-II), a hardware and software design solution for emulating basic 3270
and 5250 terminal emulation products in an IBM® PC environment. This document discusses the system support
hardware and complete link level firmware required to
achieve 3270/3299 CUT, DFT, and 5250 emulation with the
National Semiconductor Biphase Communications Processor, BCP®. The document is divided into the following chapters and appendices:

3.0 DEVELOPMENT ENVIRONMENT
4.0 SOFTWARE OVERVIEW
IBM 3270 and 5250 Environments
3270 Data Stream Architecture·
5250 Data Stream Architecture
Terminal Emulation
DCA
IBM
Screen Presentation
MPA-II

1.0 Introduction: provides a summary of each chapter and
each appendix along with a checklist of items included in
the MPA-II Design/Evaluation Kit. This chapter provides an
MPA-II product description including a list of the new features in the MPA-II that were not present in the original MPA
Evaluation Kit. Finally, a description of the DP8344 Biphase
Communications Processor, and National Semiconductor's
VLSI Products, is provided.

5.0 HARDWARE ARCHITECTURE
Architectural Overview
BCP Minimum System Core
PC Interface
Front End Interfaces
Miscellaneous Support

6.0 SOFTWARE ARCHITECTURE
Kernel
System Initialization
Coax Task
Coax Interrupt Handlers
IRMA Interface
IBM Interface
Twinax Task
Twinax Interrupt Handlers
Smart Alec Interface
7.0 LOADER AND MPA-II DIAGNOSTICS
Soft-Loading Instruction Memory
Configuring the MPA-II
MPA-II Diagnostics

2.0 Operation: describes the system requirements, installation instructions, and steps for using the MPA-II to achieve
3270/3299 and 5250 emulation.
3.0 Development Environment: describes the environment under which the MPA-II has been developed, the tools
used by the design team to characterize the products evaluated, and the tools used to test the MPA·II.

4.0 System Overview: describes the 3270/3299 environment, 5250 environment, and terminal emulation. This chapter also describes the DCA® and IBM emulator system architectures and discusses the MPA-II system organization.

fII
I

2-3

5.0 Hardware Architecture: discusses the MPA-II hardware architecture including a description of the BCP core,
PC interface, Front-end interface, and miscellaneous support circuitry.

ALEC emulation card interface modes, including SIMPC
MASTERTM by SIMWARE, RELAY Gold® by RELAY Communications, and CrossTalkTM MK.4 by Digital Communications Associates, can be used with the MPA-II.

6.0 Software Architecture: discusses the Kernel, coax
task, twinax task, and interrupt structure.

DP8344BBCP
The DP8344B BCP is a communications processor designed to efficiently process IBM 3270, 3299 and 5250 communications protocols. A general purpose 8-bit protocol is
also supported.

Included in this chapter is an in depth discussion of the
IRMATM, IBM and Smart Alec™ interfaces.

7.0 Loader and MPA·IJ Diagnostics: discusses soft-loading the BCP, configuring the MPA-II interface mode, and the
diagnostics provided for testing the MPA-II hardware.

The BCP integrates a 20 MHz, 8-bit, Harvard architecture,
RISC processor and an intelligent, software-configurable
transceiver on the same low power microCMOS chip. The
transceiver is capable of operating without significant processor interaction, releasing processor power for other tasks.
Fast, flexible interrupt and subroutine capabilities with onchip stacks make the power readily available.

Appendix A. Hardware Reference: provides the complete
MPA-II schematic, assembly drawing, board layout and PAL
equations.
Appendix B. Timing Analysis: discusses the timing of the
MPA-II system.

The transceiver is mapped into the processor's register
space, communicating with the processor via an asynchronous interface which enables both sections of the chip to
run from different clock sources. The transmitter and receiver run at the same basic clock frequency although the receiver extracts a clock from the incoming data stream to
ensure timing accuracy.

Appendix C. Filter Equations for the Combined Coaxl
Twisted Pair Interface: provides the derivation of the filter
equations for the combined coax/twisted pair interface.
Appendix D. References: is a list of reference materials
and company contacts.
MPA·IJ Description
The Multi-Protocol Adapter II (MPA-II) is a complete design
solution for IBM 3270, 3299, and 5250 connectivity products. The MPA-II system is intended to be a design example
for customers to use in developing their own products using
the Biphase Communications Processor, BCP. The BCP is a
"system on a chip" designed by National Semiconductor to
specifically address the IBM connectivity market place. Built
on the tradition of the DP8340/41 3270 receiver/transmitter
pair, the BCP takes the state of the art in IBM communications a step further. The MPA-II provides the system support
hardware and complete link level firmware to achieve 3270/
3299 CUT, DFT, and 5250 emulation with the BCP and an
appropriate PC emulator. The MPA-II Design/Evaluation Kit
does not include the PC emulation software. Thus, the end
user must purchase the PC emulation software to bring up a
live terminal emulation session using the MPA-II. PC emulation software such as DCA's E78 for MPA-II IRMA mode,
one of IBM's PC 3270 emulation programs for MPA-II IBM
mode, DCA's EMU for MPA-II ALEC mode, or any of the
third party vendors which support either the IRMA, IBM or

The BCP is designed to stand alone and is capable of implementing a complete communications interface, using the
processor's spare power to control the complete system.
Alternatively, the BCP can be interfaced to another processor with an on-chip interface controller arbitrating access to
data memory. Access to program memory is also possible,
providing the ability to softload BCP code. The MPA-II implements these features.
A simple line interface connects the BCP to the communications line. The receiver includes an on-chip analog comparator suitable for use in a transformer-coupled environment,
although a TTL-level serial input is also provided for applications where an external comparator is preferred.
A typical system is shown in Figure 1-1. Both coax and twinax line interfaces are shown, as well as an example of the
(optional) remote processor interface.
For a detailed discussion on the BCP refer to the DP8344B
Biphase Communications Processor data sheet.

2-4

rPROGRAIA - - - - - - - - -16 - ~
: IAEIAORY
,
,
:

,.r--------------AOOR~S~,

ADDRESS

RAIA OR
PROIA
64K X 16
(IAAX)

1/".......,'--'----..,.
,
~----------------.
,,

...

C~~~ -!L.--ft3~
:
COAX
, INTERfACE

. _ - - - - - - - - - - - - ____ 4

r-----------------~3

,,
,
TWINAX -i-'.....,~--+..
LINE -,--\::r-'"
,,

~--~--------------!

NOTE: A TYPICAL SYSTEIA WILL
REQUIRE < 2K PROGRAIA IAEIAORY

OPTIONAL REIAOTE
PROCESSOR INTERFACE
TLlF/l0488-1

FIGURE 1-1. Block Diagram of Typical BCP System
To support the IBM interface mode, the MPA-II utilizes an Bk
block of dual-port RAM. This. RAM must be located somewhere in the PC's memory space. The default location in PC
memory is CEOOO. This location can be relocated by writing
the upper Bk byte boundary to I/O location 2D7h or by using
the MPA-II Loader program (LD).

2.0 OPERATION
System Requirements
THE MPA-II system implements both 3270 and 5250 terminal emulation using the DCA and IBM industry standard interfaces. Note that the MPA-II system emulates the hardware and link-level firmware portion of the DCA and IBM
interfaces. This allows the MPA-II system to run with a variety of emulators. For example, the DCA emulator system for
the 3270 environment is called IRMA. IRMA consists of a
full sized PC board along with its link-level firmware, and the
PC emulator software "E7B.EXE". The MPA-II system replaces the IRMA PC board and its link-level firmware.
Therefore, the MPA-II system, when configured correctly,
appears in every way to the emulator, E7B, to be the actual
IRMA hardware/link-level firmware portion of the DCA emulator system for the 3270 environment. Thus to operate the
MPA-II system in a live communication system, a PC emulation program is required; for example DCA's E7B.EXE. In
DCA interface modes the emulators are: "E7B", for the
3270 IRMA system; and "EMU", for the 5250 Smart Alec
system. In the IBM interface mode the emulators are
"PC3270" for the 3270/3299 CUT environment and
"PSCPG" for the 3270/3299 OFT environment. Any emulator compatible with one of the emulators listed above can
be used to achieve terminal emulation using the MPA-II system.

The I/O space requirements, for any interface mode, are
the total of the I/O space requirements for the MPA-II.
This means that the I/O locations 220h-22Fh and 2DOh2DFh are required for the MPA-II.
For execution space, the LD requirements are minimal (less
than 64k). The amount of free RAM available for a PC emulator depends on the particular emulation package (i.e., E7B,
EMU, or IBM PC 3270, etc ... ). The MPA-II system does
not use any resident software of its own accord.
In summary, the Multi-Protocol Adapter II Design/Evaluation
Kit contains the hardware, software and the MPA-II System
User Guide and Technical Reference to aid designers in
development of peripheral devices and network interfaces
based on the DPB344. The following items are not included
in the MPA-II system and therefore MUST be provided by
the user to use the MPA-II in a live terminal emulation session:

The system requirements for using the MPA-II are dependent upon which interface the MPA-II is emulating. In DCA
interface modes, a PC interrupt is not used. However, in the
IBM interface mode, a PC interrupt is required. The PC interrupt level is selected as follows: IRQ2 is selected with jumper JP6; IRQ3 by jumper JP4; and IRQ4 by jumper JP5. The
factory configuration selects the PC interrupt levellRQ2.

2-5

IBM PC XT/AT or compatible

PC-DOS version 3.0 or higher

PC emulation software such as DCA's E7B for MPA-II
IRMA interface mode, one of IBM's PC 3270 emulation
programs for MPA-II IBM interface mode, DCA's EMU
for MPA-II ALEC interface mode, or any of the third party
vendors which support either the IRMA, IBM or ALEC
emulation card interface modes, including SIMPC MASTER by SIMWARE, RELAY Gold by RELAY Communications, and CrossTalk MK.4 by DCA.

•

"III:t'

Z
c(

r-------------------------------------------------------------------------------------------,
-

Link to an IBM 370 class mainframe (for example,
through the IBM 3174/3274 controllers) for 3270/3299
connectivity; or a link to a System 3X, or AS/400 for
5250 connectivity.

• If the MPA-II will be used for Twinax operation, determine
if the MPA-II will operate in pass-through or terminate
mode. If it is NOT the terminator, remove jumpers JP2
and JP3. The factory default is terminate .

Requirements for Design Development

• Install the MPA-II in an open PC bus slot.

To create the software design environment for leveraging
off the MPA-II source code, the following software must be
purchased:

• Replace the screw from the end plate previously removed to hold the MPA-II firmly in place. A good electrical connection here is important as it provides shield
ground for the cables.

National Semiconductor's DP8344 Assembler System,
DP8344ASM1.2

Microsoft's C 5.1 Optimizing Compiler for the IBM PC

• Close the system unit and replace all screws, etc ...
according to the manufacturers instructions.
• For 3270/3299 operation, install any 3270 coax type "A"
port cable to the rear BNC/Twisted Pair connector.

- Microsoft's Macro Assembler 5.1 for the IBM PC
The minimum hardware requirements to set up a hardware
evaluation and design environment for creating virtually any
end product (terminal, printer, protocol converter, multiplexer, gateway, etc.) are an IBM PC/XT, IBM PC/AT or compatible and the MPA-II PC board.

• For 3270/3299 twisted pair. operation, solder any 24
AWG unshielded twisted pair cable to the ADC Twisted
Pair Plug provided with the MPA-II kit. Then, connect the
Twisted Pair plug to the rear BNC/Twisted Pair connector on the MPA-II board. Make sure that the other end of
the 24 AWG unshielded twisted pair cable is properly
attached to the controller as a twisted pair cable.

Useful Tools
The tools listed in this section will greatly assist in the design process:

• For twinax operation, install the Twinax Adapter cable to
the MPA-II by inserting the 9 Pin D-Sub-miniature connector onto the mating connector on the rear panel, and
connect the twinax cable(s) to the Tee connector.

Azure Technologies Coax Scope (or Twinax Scope) for
monitoring and analyzing data transmitted on 3270 Coax
Type "A" media (or on IBM System 3X or AS400 Twinax
media).
Capstone Technology CT-104 BCP Demonstration/Development Kit. This kit includes a development board
with a 22 square inch logic prototype area and a· 3
square inch line interface prototype area. Additionally,
the kit supplies a Monitor/Debugger which features a
simple operator interface, single step program execution
and software break-points.
CT-106 Enhanced Interactive Coax-A Controller, EICC,
(or the CT-103 Interactive Twinax Controller, ITC) by
Capstone Technology allows issuing specific 3270 (or
5250) instructions to a Device Under Test in place of the
traditional mainframe and 3X74 controller operations (or
the System 3X or AS400 controller operations).
Logic Analyzer (National Semiconductor has an Inverse
Assembler for the BCP which requires one of the following Hewlett Packard Logic Analyzer Models: HP1650A,
HP1651A or an HP16500A with an HP16510 State/Timing Card).

Running Emulation-A Quick Start

To use the MPA-II immediately, follow these instructions.
First, select a PC/XT, PC/AT, or compatible and make sure
that the following I/O addresses, IRO interrupt, and Memory
addresses are unused in that PC:
I/O: 0220-022F and 02DO-02DF
IROs: IR02
Memory: Segment CEOO
Next, install the MPA-II hardware into the PC. Then, change
the default DOS drive to A:, insert the distribution disk labeled DISK 1 into drive A:, and type at the DOS prompt:

SETUP

where c: is the target hard disk drive. This will install the
MPA-II software onto the PC's hard disk. Next, change the
default DOS drive to the hard disk and change the default
DOS directory to \MPA. Execute the following program at
the'DOS command prompt to verify correct operation of the
MPA-II hardware within the PC:

LD -LS

See Section 3.0, Development Environment for a description of how these tools were used in developing the MPA-II
system.

If the self test passed then the MPA-II board is operational
within this PC. If it fails, check again for I/O, IRO, or Memory
address conflicts as each MPA-II is tested before it is
shipped.
Now, install onto the hard disk the PC emulation software of
your choice, such as DCA's E78 for MPA-IIIRMA mode, one
of IBM's PC 3270 emulation programs for MPA-IIIBM mode,
DCA's EMU for MPA-II ALEC mode, or any of the third party
vendors which support either the IRMA, IBM or ALEC emulation card interface modes, such as SIMPC MASTER by
SIMWARE, RELAY Gold by RELAY Communications, and
CrossTalk MK.4 by DCA. Note that the PC emulation software must be supplied by the end user, it is not included as
part of the MPA-II Evaluation Kit.

MPA-liinstallation

The first step in using the MPA-II is installing the MPA-II
circuit board in an IBM PC/XT, PC/AT or compatible. The
MPA-II installs in the usual way: please be sure that the
power is OFF, that the system unit is unplugged, and that
proper grounding techniques are used.
• Remove the cover by following the directions supplied by
the manufacturer.
• Remove the end plate from the system unit in the slot
desired for the MPA-II.
• Remove the MPA-II from its anti-static bag, and hold it by
the edges.

2-6

l>
Finally, load the MPA-II emulation card with the DP8344AV
microcode using the Loader and then start the PC emulation
program. To use the listed emulator, or equivalent, type at
the DOS prompt when in the \MPA directory:

LD MPA2 -M

= IRMA

; to use the DCA IRMA
emulator ·E78 n or
equivalent

LD MPA2 -M

= IBM

; to use the IBM emulator
"PC3270· or equivalent

LD MPA2 -M

= ALEC

; to use the DCA Smart
Alec emulator "EMU" or
equivalent

A majority of the logic for the DCA and IBM interfaces is
implemented in Programmable Array Logic. We used the
abel program from DATA I/O to prepare the JEDEC files for
programming the devices.

Your emulator should now be operational.

Software development was done on IBM PCs with the National Semiconductor DP8344 Assembler. The assembler
allows relocatable code, equate files, macros, and many
other "large CPU" features that make using it a pleasure.
The modularity of the software design allowed us to use
multiple coders and a single "system integrator" who linked
the modules and handled system debugging. The assembler adapts well to large projects like this because of its
relocation capability. The Microsoft MAKE utility was used
to provide the system integrator with a automated way of
keeping up with source modules' dependencies and changes. The BRIEFTM text editor from UnderWare™ was used
for editing. This editor allowed us to invoke the National
Semiconductor DP8344 Assembler from within the editor
and to locate and correct bugs quickly. Finally, an ethernet
LAN allowed the software development team to share files
and update each other quickly and efficiently. These tools
are not all necessary, but are common enough to be useful
in illustrating a typical environment.

Invoking the Loader program with no arguments will produce a short help screen. A detailed help for the Loader can
be accessed using the -h option. Therefore, at the DOS
command line enter:

The BCP's sophistication and advanced development tools
made the MPA-II development project proceed at a much
greater rate than is possible with other comparable solutions.

Then, change to the PC emulation program directory of the
separately purchased and installed PC emulation software
(see installation instructions of that PC emulation software
for the name of that directory. In this example assume the
directory name is \EMULATOR, and then type the name of
the PC emulator program:

CD \EMULATOR
E78

LD -H

z
I

en
~

.....

Characterization of IBM 3270 and 5250 products was performed by using Capstone's EICCIITC to drive the coax/
twinax line and the Azure scopes to monitor the results. In
this way we could stimulate the IBM terminal under controlled conditions, testing most every situation, and then
stimulate the MPA-II under the same conditions to verify
correct functionality.

For more information on the Loader program, refer to the
Loader documentation in Section 7.0.

3.0 DEVELOPMENT ENVIRONMENT
The environment used for development of the MPA-II consists of a few readily available, relatively inexpensive tools.
The hardware was first prototyped with the Capstone Technology CT-104 BCP Demonstration/Development card. The
software was developed with the National Semiconductor
BCP Assembler. It was tested with Capstone's EICC (Enhanced Integrated Coax Controller), Capstone's ITC (Integral Twinax Controller), and Azure Technologies' Coax and
Twinax scope products. Debugging was accomplished with
BSID, Capstone's debugger/monitor which we modified for
use with the MPA-II software model and the MPADB.EXE
debugger included with the MPA-II (see Chapter 6). For particularly difficult interrupt problems a Hewlett Packard model
16500A Logic Analysis System with a State/Timing card installed was used to monitor instruction execution and PC
accesses.
The CT-104 board was modified through the wire-wrap area
to approximate the hardware design. This wire-wrap card
allowed us to get a working version of the hardware design
very quickly, since most of the circuitry was already there. In
some development projects, it is often faster to go directly
to pcbs as a prototype run. This process has advantages in
speed when the device is large and complex, but often debugging is quite messy with multi-layer pcbs, not to mention
expensive. Since the CT-104 has the major functional
blocks already and the wire wrap area is large, the wirewrap time was minimal, thus allowed us to easily debug the
hardware.

The debuggers allow a developer to load and run code on
the target system, set breakpoints, examine and modify instruction or data memory. Early configurations were accomplished using the standard DOS DEBUG tool, but once the
MPA-II Loader program (LD) was operational, configuration
and loading was accomplished through it.
The HP logic analyzer was attached to the target system to
monitor the instruction accesses and data bus activity on
the target card. This information is helpful in finding interrupt
problems that the debugger cannot. Using ICLK from the
BCP to sample the BCP instruction address and data busses allows one to monitor instruction execution. Symbolic
disassembly can be done with the DP8344 BCP Inverse Assembler, which is a software package for use in an
HP1650A or HP1651A Logic Analyzer, or in an HP 16500A
Logic Analysis System with an HP 16510A State/Timing
Card installed. The inverse assembler was developed by
National Semiconductor to allow disassembly of the
DP8344 op-code mnemonics. The inverse assembler provides the real time sequence of events by displaying on the
HP Logic Analyzer's screen the actual execution flow that
occurred in the system being developed with the DP8344.

4.0 SYSTEM OVERVIEW
The MPA-II addresses a systems market that is driven by
the large installed base of IBM systems throughout the

fI
2-7

....

world. The IBM plug compatible peripheral and terminal emulation markets are growing along with the success of IBM
in the overall computer market place. The originally proprietary architecture of the IBM peripherals and the subsequent
vague and confusing ProductAttachme,ntinformation Manuals (PAis) have kept the 'attachment technology ~Iusive.
The IBM communications system in generalis not well understood. The desire of customers and systems vendors to
achieve more attachment options, however, is significant,

modular and combines the best features of the System/36
and System/38 to produce IBM's most popular mid-range
system to date. In addition, the AS/400 continues to expand
the role and importance of the 5250 data stream, adding it
to the definition of IBM's SAA. The 370 class and AS/400
machines have grown closer together through the advent of
SNA (Systems Network Architecture). SNA allows both systems to function together in an integrated network.
The 3270 and 5250 communications systems evolved at a
time when hardware design constraints were very different
than today. Microprocessors and 1 Mb DRAMs were not
available. Memory in general was very expensive. Telecommunications channel sharing between multiple peripherals
was imperative. Even so, fast screen updates and keystroke
handling were necessary. The 3270 and 5250 data stream
architectures were developed to address specific design
goals within IBM's overall network communications system.
The controller sub-system where they were implemented
has proved adaptable to new directions in SNA and the migration of processor power out into workstations.
The 3270 and 5250 controller sub-systems split the peripheral support tasks into two sections: screen with keyboard,
and host communications interface. Figure 4-1 shows the
3270 Communications System, 5250 is similar. The controller architectures can be thought of as having integral screen
buffers and keyboards for each of their associated terminals
with the caveat that screens and keyboards must be accessed through a secondary, high speed serial link. Since
the controller views the terminal's screen buffer as its own,
the controller does not maintain a copy of the information
on that screen. The processing capability of some terminals
is severely limited; the early terminals were state machines
designed to handle the specific data stream. With the advent of SNA and APPC, (Advanced Peer to Peer Communications) the intelligence in some peripherals has become
significant. The data streams have essentially remained the
same, with hierarchically structured protocols built upon
them. SNA and these higher protocols will be discussed
later.

IBM 3270 and 5250 Environments
The study of IBM communications fills many volum'es. The
intent of this discussion is not to describe ,it fully, but to
highlight the areas of)BM communications that the BCP
and MPA-II address. Specifically, these areas'are the controller/peripheral'links that use the 3270/3299 and 5250
data streams. These links are found in 370 class mainframe
networks and the smaller, mid-range "systems such as the
AS/400 and System/3x lines.
'
The" 3270 commu~ications' sub-system, was developed for
370 class mainframes as demand for terminal support began to outstrip batch job entry modes. These systems had
large scale networking needs, and ofte,:" needed to support
thousands of terminals and printers. The original systems
were linked together through dedicated telephony lines using' Binary Synchronous Communications (BSC) serial protocol. The 5250 communications system was developed
originally for the Series 3 and became widely used on the
System/34. The System/34 wa.'sa small,office environment
processor with limited networking and terminal support capabilities.' Typical System/34 installations supported up to
16 terminals and printers. The System/36 replaced the System/34 in 1984. Next, IBM introduced the System/38, a
mid-range processor tMt could rival the 4300 series (small
370 class) mainframes in processing power. The System/36
and 38 machines now have greatly enhanced networking
facilities, and can support up to 256 local terminals. In 1988
IBM released a new, mid-range system line called the Advanced System 400, or AS/400, to replace the aging System/3x line. The Advanced ,System 400 series is highly

CURSOR

CONTROL
SEC. CONTROL
STATUS

I ,KEYSTROKE I
(

DDDDDDDDDDDDD )
oOOOOOOOODOOO

DOOOOOOocoooc
OOC::==::=:=:=:::OD

LIGHT PEN

STRIPE

, TL/F/l0488-2

FIGURE 4-1.3270 Communications System

2-8

Separating the screen buffer and keyboard from the intelligence to handle the terminal addressed several design
goals. Since the terminal needs screen memory to regenerate its CRT, the "regen" buffer logically resides in the terminal. The controller need not duplicate expensive memory by
maintaining another screen copy. The data stream architectures implemented with high speed serial links between the
controller and terminal allow fast keystroke echoing. It also
allows fast, single screen updates, giving the appearnace of
good system performance. The terminal screen maintenance philosophy developed with these architectures lends
itself well to the batch processing mode that traditionally
was IBM's strong suit. The terminal system is optimized for
single screen presentation with highly structured field oriented screens. Data entry applications common in business
computing are well suited to this. Essentially, the architecture places field attributes and rudimentary error checking in
the controller, so that most keystrokes can pass from the
terminal to the controller and back to the screen very quick·
Iy without host CPU intervention. Only when particular keystrokes are sent (AID keys) does the controller read the
contents of the screen fields and present the host with the
screen data.

Controllers typically support multiple terminals and essentially concentrate the terminal traffic onto the host communications channel. The controller has a secondary communcations system that implements the 3270 data stream protocol over coaxial cable at 2.3587 Mb/s. Each peripheral connected to the controller has its own coax port. The coax
lengths may be up to 5000 feet. The protocol is controller
initiated, poll/response type.
The serial protocol organizes data into discrete groups of 12
bits, called a frame. Biphase (Manchester II) encoding is
used to impress the data frames onto the transmission medium. Biphase data have embedded clock information denoted as mid-bit transitions. Frames may be concatenated
to form packets of commands and/or data. All transmissions begin with a line quiesce sequence of five biphase
one bits followed by a three bit time line violation. The first
bit of all frames is called the sync bit and is always a logic
one. The sync bit follows the line violation and precedes all
successive frames. Each frame includes a parity bit that establishes even parity over the 12-bit frame. Each transmission from the controller elicits a response of data or status
from the device. The response time requirements are such
that a device must begin its response within 5.5 ms after
reception of the controller transmission. Simple reception of
a correct packet is acknowledged by the device with a
transmission of "DAR", or transmission turn around/auto
response. The controller initiated, poll/response format protocol addresses multiple logical devices inside the peripheral through a three or four bit command modifier. The different logical devices decode the remaining bits as their command sets. Commands to the base or keyboard are decoded as shown in Table 4-1.

3270 Data Stream Architecture
The 3270 communications system, as discussed above, is a
single logical function separated into two physical pieces of
hardware connected by a protocol implemented on a high
speed serial link. The terminal hardware has the screen
buffers and keyboard, magnetic slot reader, light pen, etc.,
(Le., all the user interface mechanisms). The controller has
a communications link to the host CPU or network and the
processing power to administrate the terminal functions.

TABLE 4-1. 3270 Data Stream Command Set
Command
READ TYPE:

WRITE TYPE··:

Value

Description

TO BASE-Device Address 0 or 1
POLL
POLLIACK
READ STATUS
READ TERMINAL ID
READ EXTENDED ID
READ ADDRESS COUNTER HI
READADDRESSCOUNTERLO
READ DATA
READ MULTIPLE

01h
11 h
ODh
09h
07h
05h
15h
03h
OBh

Respond with Status
Special Status Acknowledgement Poll
Respond with Special Status
Respond with Terminal Type
Respond with 4 Byte ID (Optional)
Respond with Address Counter High Byte
Respond with Address Counter Low Byte
Respond with Data at Address Counter
Respond with Up to 4 or 32 Bytes

TO BASE-Device Address 0 or 1
RESET
LOAD CONTROL REGISTER
LOAD SECONDARY CONTROL
LOAD MASK
LOAD ADDRESS COUNTER HI
LOAD ADDRESS COUNTER LO
WRITE DATA
CLEAR
SEARCH FORWARD
SEARCH BACKWARD
INSERT BYTE
START OPERATION
DIAGNOSTIC RESET

02h
OAh
1Ah
16h
04h
14h
OCh
06H
10h
12h
OEh
08h
1Ch

POR Device
Load Control Byte
Load Additional Control Byte
Load Mask Used in Searches, CLEAR
Load Address Counter High Byte
Load Address Counter Low Byte
Load Regen Buffer with Data
Clear Regen Buffer to Nulls
Search Forward in Buffer until Match
Search Back in Buffer until Match
Insert Byte at Address Counter
Begin Execution of Higher Level Command
Special DFD Reset

!II

"Denotes foreground task

"All WRITE type commands elicit TTAR upon clean reception.

2-9

attributes is limited by the size of the displayable character
set. The EAB provides a method to enhance screen control,
with color for instance, without losing character space. The
EAB contains both character attributes, that correspond to
characters in the regen buffer, and field attributes that correspond to attributes in the regen.

The 3299 variant on the 3270 data stream uses an additional eight bit address field to address up to 8 more 3270 devices with the same coax cable. Since coax installations are
point-to-point between controller and peripheral, cabling
costs motivated the introduction of 3299 multiplexer/demultiplexers. Using the extended address field, eight devices
can be connected via one coax cable between the controller and the multiplexer. (The 3299 protocol can support up
to 32 devices per line if IBM so chooses.)

Status developed in the terminal, such as keystrokes or errors, are reported in the poll/response mechanism. A POLL
command to the base device with keyboard status pending
elicits a keystroke response in 5.5 J-Ls. The controller then
sends a POLL! ACK command to acknowledge the keyboard status and thus clear it. The terminal then responds
with "clean" status, i.e., TTAR. Controllers poll frequently to
assure that status updates are quick. Outstanding status is
reported in the poll response and in some cases is handled
directly by command modifiers in the POLL command. Keystrokes are the most command status and hence are acknowledged by the POLL! ACK command. Status reported
in the status register can be read and acknowledged independently of the polling mechanism, if desired.

Basic 3270 terminals have a structure as shown in
Figure 4-2. The EAB (Extended Attribute Buffer) is a shadow
of the regen buffer; each location in the regen has a corresponding location in the EAB. The EAB is a separately addressable device with an address modifier of 7h. The EAB
bytes are used to provide extra screen control information.
In the 3270 world, the screen and field attributes that the
controller uses to format and restrict access to fields on the
screen.take up space in the screen. The attribute characters
appear as blanks and cannot be used for displayable characters at the same time. Since the number of permutations
of the a-bit character byte is limited to 256, the number of
ADDRESS COUNTER
(CURSOR HI:)

EAB
REGEN

~--------------------~

(CURSOR LO:) ~____________________~

KEYSTROKE BUrfER: 1
...____________________......

CONTROL:

3564

(MOD 5)

'----~--~~~~-'-~~~

CONT _BLINK ~ BLINK CURSOR
CONLREV ~ REVERSE IMAGE CURSOR
' - - - - - CONT _'NHCURSOR

TURN Off CURSOR

' - - - - - - - CONLBLANK ~ BLANK SCREEN
L -_ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _

7
SECCiNDARY CONTROL:

CONLINHSTEP ~ PREVENT I/O STEP
CONLMOD

SCREEN MODEL

1rsv 1-1-1-1-1-1-1 B~
SCONLSIG ~ READ BIG MODE

TERMINAL 10: 1
...____..,....____......__..,...__......_0~I
' - - - - - ID_MOD ~ MODEL
ID_KEYBD ~ KEYBOARD TYPE

L -_ _ _ _ _ _ _ _

STALMONO ~ MONO CASE ON
STALRSVI
'-----

STALAVAIL~NOT

BUSY

' - - - - - - - STALKEY - SECURITY KEY ON
L -_ _ _ _ _ _ STALRSV2
L -_ _ _ _ _ _ _ _

'-----------

STAT _fERROR

' - - - - - - - - - - - - - STALBLANK
MASK: I~

fEATURE ERROR

STALOPCOMP~OP
N

COMPLETE

SCREEN BLANKED BY KEY

_______________......

EAS MASK: 1
...____________________......

TLlF/l0466-3

FIGURE 4·2. 3270 Internal Terminal Architecture

2-10

The SEARCH, INSERT and CLEAR commands require the
terminal to process the command in the foreground while
responding with "BUSY" status to the controller. (The foreground refers to non-interrupt driven routines. Foreground
routines may be interrupted at any time.) Processing these
commands requires substantially more time than the others,
and hence are allowed to proceed without real-time response restrictions.

parts; a bit synchronization pattern, a frame synchronization
pattern, and one or more command or data frames. The bit
sync pattern is typically five one bit cells. This pattern
serves to charge the distributed capacitance of the transmission line in preparation for data transmission and to synchronize receivers on the line to the bit stream. Following
the bit sync or line quiesce pattern is the frame sync or line
violation. This is a violation of the biphase, NRZI data midbit transition rule. A positive going half bit, 1.5 times normal
duration, followed by a negative going signal, again 1.5
times normal width, allows the receiving circuitry to establish frame sync.

An interesting feature found in terminals and printers is the
START OP command. Originally, this command was used
only by controllers and printers to begin print jobs. Printers
have specific areas within their buffers that are reserved for
higher level commands from the controller. These higher
level protocols started as formatting commands and extra
printer feature control. With the advent of SNA and Distributed Function Devices, this concept is now used in terminals to pass SNA command blocks to multiple NAUs (Network Addressable Units) within the terminal. These NAUs
are complete terminals, or peers, not just simple user interface devices.
As large mainframe systems proliferated, 50 did the need to
off-load terminal support from the emerging 370 class mainframe. The need to "network" both remotely and locally
was becoming apparent. In addition, the need to separate
display and printer interface tasks from applications was
sorely felt. The system developed by IBM eventually became Systems Network Architecture (SNA). The 370 class
machines use secondary processors, or "front-ends" to
handle the networking aspect of large scale systems and
these "front ends" in turn use terminal and printer controlers to interface locally with the user interface devices. The
controllers handle the device specific tasks associated with
interfacing to different printers and displays. The front-ends
handle connecting the routes from terminals or printers to
applications on the mainframe. A session is a logical entity
split into two halves; the application half and the terminal
half, and connected by a virtual circuit. Virtual circuits can
be set up and torn down by the system between applications and terminals easily, and the location of the specific
terminal or printer is not important. NAUs are merely devices that can be addressed directly within the global network.
Setting up multiple NAUs within a terminal allows all sorts of
gateway opportunities, multi-display workstations, combination terminal/printers, and other things.

Frames are 16 bits in length and begin with a sync or start
bit that is always a 1. The next 8 bits comprise the command or data frame, followed by the station address field of
three bits, a parity bit establishing even parity over the start,
data and address fields, and ending with a minimum of three
fill bits (fill bits are always zero). A message consists of a bit
sync, frame sync, and any number of frames. A variable
amount of inter-frame fill bits may be used to control the
pacing of the data flow. The SET MODE command from the
host controller sets the number of bytes of zero fill sent by
attached devices between data frames.
Message routing is accomplished through the use of the
three bit address field and some basic protocol rules. There
is a maximum of eight devices on a given twinax line. One
device is designated the controller or host, the remaining
seven are slave devices. All communication on the twinax
line is host initiated and half duplex. Each of the seven devices is assigned a unique station address from zero to six;
address seven is used for an End Of Message delimiter, or
EOM. The first or only frame of a message from controller to
device must contain the address of the device. Succeeding
frames do not have to contain the same address for the
original device to remain selected. The last frame must contain the EOM delimiter. For responses from the device to
the controller, the responding device places its own address
in the address field in all frames but the last one. It places
the EOM delimiter in the address field of the last frame.
However, if the response to the controller is only one frame,
the EOM delimiter is used. The controller assumes that the
responding device was the one addressed in the initiating
command.
Responses to the host must begin within 60 ± 20 J.Ls of receiving the transmission, although some specifications state
a 45 ± 15 J.Ls response time. In practice, controllers do not
change their time out values per device type so that anywhere from 30 J.Ls to 80 J.Ls response times are appropriate.

DFD devices can support up to five separate NAUs using a
basic 3270 port. Using 3299 addressing allows eight sessions for each DFD device, or 40 possible NAUs per coax.
By layering protocols over the basic 3270/3299 data
stream, the controller can distribute more of the SNA processing to intelligent devices that replace terminals. APPC
will allow more and more functions to be shared by NAUs
that act as "peers" in the network.

The 5250 terminal organization is set up such that there are
multiple logical devices within the terminal as in 3270.
These devices are addressed through a command modifier
field in the command frame. The command set for the base
logical devices is shown in Table 4.2. Note that except for
POLLs and ACTIVATE commands, all commands are executed in the foreground by the terminals, unlike the 3270
commands. In addition, 5250 terminals only respond after a
POLL or ACTIVATE READ command. The remaining commands are loaded on a queue for passing to the foreground
while the terminal responds with "busy" status to the host
when Polled until all the commands on the queue have
been processed. See Figure 4-3 for the 5251 terminal architecture.

5250 Data Stream Architecture

The 5250 data stream architecture has many similarities to
3270, although they are different in important ways. The
primary difference is the multi-drop nature of 5250. Up to
seven devices may be "daisy chained" together on the
same twinax cable. Twinax is a very bulky, shielded, twisted
pair as opposed to the RG/62U coax used in 3270.
The 5250 Bit stream used between the host control units
and stations on the twinax line consists of three separate

2-11

.,...
'O::t'

TABLE 4·2. 5250 Command Set

(,0
I

Queueable Commands
Reads

Writes

Read Data (Note 1)
Read Device 10 (Note 1)
Read Immediate (Note 1)
Read Limits (Note 1)
Read Registers (Note 1)
Read Line (Notes 1, 2)

Write Control Data
Write Data and
Load Cursor
Write Immediate (Note 1)
Write Data (Note 1)

Control

Operators

Eoa

Clear
Insert Char.
Move Data
Search

Load ADDR Counter
Load Cursor Reg.
Load Ref. Counter
Reset
Set Mode

Non·Queueable Commands
Responders

Acceptors

Poll
Activate Read

Activate Write

Note 1: Must be last command loaded onto queue. (EOQ may follow). When Terminal responds to POLL as not busy, then the appropriate ACTIVATE command
must be sent.
Note 2: Not a documented command in the IBM PAl. (See MPA·" code for response.)

I-.J

80 bytes

--I
16 bits

LINE 1

ADDRESS COUNTER

16 bits

I REFERENCE COUNTER I
16 bits

SCREEN BUFFER

CURSOR REGISTER

8 bits

IINDICATOR I
8 bits

I CONTROL I
8 bits

5251 MODEL II

KEYSTROKE
QUEUE

TL/F/10488-4

2·12

I.IPA

DCA
E78

REGEN
SCREEN
BUFFER
0

1
3RD
PARTY
APPS

IBI.I
3278/79
CUT,DFT
3287
DCA
Smart
Alec
5250

NSC
SOFTLOADER

I+-

I+4

CHAI.IELEON
INTERFACE
IBI.I
IRI.IA
Smart Alec

l........+

LOAD/
CONFIGURE

I
I
I
I
I
I
I
I
I

EAB 0

~ 3270 - .
..- 3299 - .

TWINAX
PROCESS

~ 5250 - .

EAB 1

REGEN
SCREEN
BUFFER
I-1

COAX
PROCESS

••
•

EABn

REGEN
SCREEN
BUrFER
n

PC CHANNEL
TL/F/l0488-5

FIGURE 4-4. MPA-II System Architecture

Terminal Emulation

The terminal emulation market opened with Technical Analysis Corporation's IRMA product in 1982. The 3278179 terminal emulator quickly became the industry standard, even
as IBM and many others entered the market place. Technical Analysis Corporation merged with Digital Communications Associates in 1983. The 3270 emulation market is now
dominated by DCA and IBM. IBM· produced the first 5250
terminal emulator in 1984, although it was a severely limited
product. The market opened up in 1985 with the release of
products by AST Research, IDE Associates, and DCA.
DCA's Smart Alec was the first product to provide seven
session support, address bidding, and a documented open
architecture for third party interfacing. DCA's IRMA was released with a technical reference detailing their Decision
Support Interface. This document along with the source
code to E78 (their PC emulator software) allowed many
companies to design micro to mainframe products using the
DSI as the mainframe interface. IBM provides a technical
reference for their 3278 Entry Level' Emulator as well, (see
Appendix C for a complete list of references).

Personal computers are often used to emulate 3270 and
5250 terminals, and in fact, have hastened the arrival of
APPC functions in both the 3270 and 5250 arenas. Basic
CUT (Control Unit Terminal) emulation is often accomplished by splitting the terminal functions into real-time
chores and presentation services. The presentation services, such as video refresh and keyboard functions, are handled by the PC, and real-time response generation, etc., by
an adapter card (see Figure 4-4). This is a somewhat expensive alternative to a "dumb" terminal. However, since
PCs are becoming more and more powerful, their use as
peers in SNA networks, as multiple NAUs, or multiple display sessions in 5250 is very promising. Although primitive
in many ways, the 3270 and 5250 communications system's
fast response times, unique serial protocols and processing
overhead requirements have traditionally limited the confidence of third party developers in designing attachments. In
addition, the high cost of many early solutions discouraged
many would-be developers.

The proliferation of the IBM and DCA interfaces coupled
with the availability of detailed technical information about
them made these interfaces good choices for the MPA-II.
The MPA-II system was designed to do two major functions:
one is emulation of the DCA and IBM emulation products;
the second is to provide a powerful, multi-protocol interface
that will afford greater utilization of the DP8344A. Specifically, the MPA-II emulates the hardwarelfirmware resident in
PC add-in boards for 3270 and 5250 emulation products
from DCA and IBM. To do this, we have constructed hardware and firmware that mimics the corresponding system
components of the other emulators. The MPA-II system appears in every sense to be the board it is emulating, once it
has been loaded and configured.

National Semiconductor opened the 3270 attachment market place to many third parties in 1980 with the release of
the DP8340/41 protocol translation chip set. The chip set
removed one of the major stumbling blocks to attachment
designs, although formidable design challenges remained.
Bit-slice or esoteric microcontrollers were still required to
meet the fast response times specified by IBM. The difficulties and costs in designing interface circuitry for these solutions remained a problem. So in 1987 National Semiconductor introduced the DP8344 Biphase Communications Processor, BCP. By tightly coupling a sophisticated
3270/3299/5250 transceiver to a high speed RISC based
CPU, National eliminated the last major stumbling block to
IBM connectivity. National also made available for the first
time a single hardware platform capable of supporting the
3270, 3299 and 5250 data streams.

2-13

fII

,...

IRMA maintains a screen image in PC memory that is used
in conjunction with a complex algorithm to determine which
lines of the screen to update. Smart Alec maintains a 16
entry FIFO queue that contains screen modification information encoded in start/end addresses. This information is
processed to decide which screen locations should be updated.

The DCA and IBM system organizations are similar. Each
system is divided into two major functional groups: presentation services, and terminal emulation. The terminal emulation function resides entirely on the adapter hardware and
maintains the screen buffers that belong to the host control
unit. The terminal emulation function includes all real time
responses and status generation necessary to appear as a
true 5250 or 3270 device to the host controller. Presentation services carried out by the PC processor through the
emulator software include fetching screen data from the
adapter, translating it into displayable form, and providing
the data to the PC's display adapter. In addition, the PC side
presentation services collect keystrokes from the keyboard
and present them to the adapter. The communication between the PC presentation handler and adapter emulation
function consists mainly of status updates, keystrokes, and
screen data.

IBM
The IBM system organization, in general, is very similar to
the DCA systems. The major differences lie in the interface
implementations. The IBM system utilizes RAM dual-ported
between the PC processor and the adapter board processor
to transfer screen data from the adapter. In addition, IBM
does not use an interpreted command/response I/O interface. The IBM interface uses 121/0 locations with individual
bits defined in each register for direct status availability. The
status bits consumed by the PC presentation services are
cleared through a "write under mask" mechanism. Consumable bits are read by the PC and, when written to, corresponding status bits are cleared by one bits in the value
written. Reading a register of consumable bits and writing
that value back out clears the bits set in that register. The
interface can operate in a polled manner, although it typically is operated via interrupts. One register in the interface is
dedicated to interrupt status (ISR-Interrupt Status Register, 2DOh) and when the PC is interrupted, the particular
status change event is indicated in that register. Buffer modifications are indicated through a status change in the I/O
interface which also provides an indication of the block
modified. The actual screen data is in 8k of dual-port RAM
and may be read by the PC when the "Buffer-Being-Modified" flag is cleared. This type of interface affords the IBM
products great speed advantages, although limits compatibility with other add in PC boards.

DCA
The DCA products use an I/O mapped 4 byte mailbox to
pass information between the PC's processor and the processor on the emulation card. The information is encoded in
a
,
[],
[],
[] and , [response], [response],
[response] format. Information flow is controlled through a
Command/ Attention semaphore implemented in hardware.
Both the Smart Alec (5250) and IRMA (3270) interfaces
have command sets that include reading and writing the
screen buffers maintained on the adapter boards, sending
keystrokes, and passing display information such as cursor
position and general screen modes. The interfaces are both
used in a polled manner, although both are capable of generating interrupts to the PC processor.
Both Smart Alec and IRMA have Signetics 8X305 processors that run the terminal emulation functions and interface
to the PC presentation services. The PC function initiates
commands and status requests by writing the appropriate
value into the mailbox and setting the Command semaphore. The semaphore is then polled by the PC for a change
in state that signals completion of the command and signals
that valid response data is in the mailbox. The PC will poll
for a specific amount of time before assuming a hardware
malfunction has occurred. The 8X305 processors have no
interrupt capabilities and handle all terminal emulation subtasks in a polled manner. The PC interface tasks are the
lowest priority of all. The 8X305 may initiate information
transfer to the PC by posting the Attention semaphore,
and/or setting a PC interrupt, although this is not generally
done. Both the Smart Alec andlRMA interfaces are implemented with 74LS670 dual-ported register files so that
reads and writes from each processor are directed into separate register files.

Screen Presentation
Both the IBM and DCA systems present EBCDIC data to the
PC presentation services for display. The presentation software must translate the EBCDIC codes into ASCII for PC
display adapters. In addition, the screen attribute schemes
for PCs and mainframe terminals differ greatly. The presentation services must provide the necessary display interface
to emulate the "look" of the terminal that is being emUlated.
The PC keyboard scan codes are incompatible with mainframe scan codes, and must be translated for the keyboard
type of the terminal being emulated. Both systems provide
advanced PC functions such as residency, keyboard remapping, and multiple display support.
MPA-II
The MPA-II implements emulation of both the DCA and IBM
interfaces. Therefore, an overall architecture similar to the
DCA and IBM systems is employed (see Figure 4-5). The
logical split in functionality between the PC and the adapter
board processors is roughly analogous; the PC provides
presentations services and the adapter hardware/firmware
handles the host terminal emUlation tasks (see Figure 4-6,
4-7 and 4-8). The BCP on the adapter board is soft-loaded
by the PC and configured to operate in one of the protocols
and interface modes. The adapter board then assumes the
hardware emulation tasks of the physical interfaces of the
DCA or IBM products. At this time the DCA, IBM (or a
DCAlIBM compatible) emulation program is executed on
the PC. To this program the MPA-II appears to be a DCA or
IBM emulation card.

DCA interfaces were designed for compatibility at the expense of interface through-put. The small I/O requirements
and the fact that interrupts to the PC are not necessary
allow the interfaces to install easily in most environments.
The IRMA Decision Support Interface (DSI) utilizes eight I/O
locations at 220h-227h. Smart Alec resides in I/O locations
228h-22Fh. All screen data and status information must
pass through these mailboxes with the semaphore mechanism. This makes repainting the entire screen very slow.
Both IRMA and Smart Alec utilize different schemes to reduce the necessity of reading entire screen buffers often.

2-14

accesses by the PC and BCP do not occur. The location of
the dual-port RAM in the PC memory map is determined by
a value written into the 2D7h I/O location. This "Segment"
register is the upper 7 bits of the PC address field and is
compared with the address presented during PC memory
cycles for decoding. Writing different values to this register
moves the decoded memory block anywhere within the PC
memory space to avoid conflicts. The pacing of dual-port
accesses is handled by provisions in the emulated interface
definition.

The MPA-II hardware consists of a DP8344A running at
18.89 MHz with 8k x 16 bits zero wait state instruction
memory, 32k x 8 bits one wait state data RAM, a
coax/twisted pair 3270/3299 front end, a 5250 twinax front
end, and a BCP software controlled PC interface that enables the MPA-II to appear as a variety of industry standards interfaces. The BCP Remote Interface Configuration
register (RIC) is located in PC I/O space at 2DFh (see Figure 4-9). This register facilitates downloading of instructions
and data memory from the PC, starting and stopping the
processor, and configuring the low level interface mode.
The MPA-II utilizes the low level fast buffered write/latched
read interface mode.

»z

0)
~

.....

The PC I/O map for the MPA-II adapter board is as follows:
TABLE 4-3. MPA-II PC I/O Map

220h221h222h223h224h225h226h-

The MPA-II Configuration register (see Figure 4-10) is located at I/O location 2DCh and controls which type of high
level interface the MPA-II board is operating in (Le., IRMA,
Smart Alec, IBM, coax, etc.). Changing the value of this register while the MPA-II is operating will cause the MPA-II to
change mode, resetting the emulation session in progress.
In addition, a simple MPA-II command set can be issued
through the MPA-II Configuration register and the MPA-II
Parm/Response register (I/O location 2DBh) for use as a
passive debugging aid.

227h228h229h22Ah22Bh22Ch22Dh22Eh-

When either of the DCA modes are enabled, the I/O block
220h-22Fh is decoded, split into read and write banks, and
mapped into the BCP's data memory. For the IBM mode,
the I/O block from 2DOh-2DAh is decoded and the WriteUnder-Mask function is enabled. In addition, the 8k of dualport RAM is defined according to the IBM interface mode.
For CUT emulation, only the lower 4k of the dual-port RAM
is used. For OFT mode, the entire 8k block may be utilized.
Neither DCA mode utilizes dual-port memory, but it is still
available to the PC so the MPA-II firmware maps screen
information there. Note that the MPA-II hardware always decodes I/O addresses 220h-22Fh and 2DOh-2DFh regardless of the PC interface selected.

22Fh2DOh2D1h2D2h2D3h2D4h2D5h2D6h2D7h-

The MPA-II interface mimics the DCA and IBM interfaces by
interrupting the BCP when write accesses occur to the I/O
space of interest (220h-22Fh, 2DOh-2D6h and 2D8h2DEh) while holding off any other PC accesses to the
MPA-II board, thus "locking out" the PC. The BCP monitors
these I/O accesses through the use of the "MPA-II Access"
register contained in a PAL. This register captures the location of the last PC I/O access. The BCP's I/O access interrupt routines then get control and emUlate in software
DCA's or IBM's I/O hardware functions (such as IBM's write
under mask function). At the end of interrupt processing, the
software "unlocks" the PC, allowing access once again to
the MPA-ll's memory and I/O registers by the PC. The extreme speed of interrupt processing by the BCP makes this
feasible. Accesses of the dual-port RAM by the PC are regulated by the interface only in assuring that simultaneous

IRMA Command/Status Register
IRMA Argument/Response
IRMA Argument/Response
IRMA Argument/Response
Decoded, Unused
Decoded, Unused
IRMA Command/Attention
Semaphore Control
IRMA Command/Attention Semaphore
Smart Alec Command/Status Register
Smart Alec Argument/Response Register
Smart Alec Argument/Response Register
Smart Alec Argument/Response Register
Decoded,Unused
Smart Alec Control Register
Smart Alec Control Register,
Command/ Attention Semaphore
Smart Alec Strobe

2D8h2D9h2DAh-

IBM Interrupt Status Register
IBM Visual/Sound
IBM Cursor Address Low
IBM Cursor Address High
IBM Connection Control
IBM Scan Code
IBM Terminal 10
IBM/MPA-II Dual-Port Segment
Location Register
IBM Page Change Low
IBM Page Change High
IBM 87E Status

2DBh2DCh2DDh2DEh2DFh-

MPA-II Parm/Response Register
MPA-II Configuration/Command Register
Decoded, Unused
Decoded,Unused
MPA-II RIC Register

•
2-15

.,...
~

z•

EMULATION CARD
(MPA-II)

INTERRUPT
HANDLERS

RECEIVER
TRANSMITTER
TIMER
BIRQ (INTERrACE)

IBM

3278/79

DUAL PORT
t.tEt.tORY

CUT, Drr

8k -

6~k

IRt.tA
(DCA)

3278/79
THIRD PARTY
APPLICATIONS
ALEC
(DCA)

5250

THIRD PARTY

' - - - - f i l l APPLICATIONS
SIt.CPC
RELAY GOLD
CROSS TALK
TL/F/l04BB-15

FIGURE 4-5. PC Terminal Emulation Architecture

IBM

PC SOFTWARE

3278/79
CUT, Drr

- REFORMATS AND TRANSLATES REGEN
BUFFER TO ASCII FOR PC SCREEN'
IRt.tA
(DCA)

3278/79

-ACCEPTS KEY STROKES FROM USER

- PERFORMS FILE AND DATA TRANSFER

THIRD PARTY
APPLICATIONS

ALEC
(DCA)

5250

THIRD PARTY
APPLICATIONS
SIt.lPC

- THIS COULD BE DONE IN THE BCP MICROCODE

RELAY GOLD

CROSS TALK
TLlF/l04BB-9

FIGURE 4-6. PC Software

2-16

PC INTERFACE

DUAL PORT
1.4Et.lORY

• ALLOWS PC TO COMMUNICATE
WITH THE TERMINAL EMULATOR
CARD.

6k - 64k

• IBM
-STATUS QUERY METHOD
• IRMA/ALEC
-COMMAND/RESPONSE
METHOD

TLlF/10488-10

FIGURE 4-7. PC Interface

EMULATION CARD
(MPA-II)

EMULATION CARD
• PROVIDES PHYSICAL AND ELECTRICAL
CONNECTION
• PROCESSES ALL DATA LINK COMMANDS
• ISSUES ALL DATA LINK RESPONSES
• OPERATES INDEPENDENT OF PC CPU
-REBOOTING PC HAS NO EFFECT ON
ACTIVE SESSIONS
IBM
HOST SYSTEM
OR
CONTROLLER
TLlF/l0466-11

FIGURE 4-8. Emulation Card

FII
2-17

I I

MSO: MEMORY SELECT: DATA, INSTRUCTION
MS1: MEMORY SELECT: DATA, INSTRUCTION
STRT: BCP START/STOP
LW: LATCHED WRITE INTERrACE MODE
LR: LATCHED READ MODE
RW: r AST WRITE MODE
SS: SINGLE STEP THE BCP
BIS: BIRO STATUS

TL/F/l04BB-B

FIGURE 4-9. BCP Remote Interface Configuration Register

[

I J I I I I I I

POR INTERrACE (0 INDICATES THAT POR IS COMPLETE)
RESERVED
3299 MODE
COAX EAB INSTALLED
MPA COMMAND (0 INDICATES COMMAND EXECUTION COMPLETE)
IBM INTERrACE MODE
DCA INTERrACE MODE
5250/3270

TLlF/l04BB-7

FIGURE 4-10. MPA-II Configuration Register

yields an average instruction cycle time of 160 ns, a maximum instruction cycle time of 212 ns and a maximum interrupt latency of 237 ns (excluding wait states due to PC accesses). Although such performance may seem excessive,
remember that the 3270 protocol requires a 5.5 JLs response time and that the newer controllers sometimes send
commands less than 10 JLs apart. These commands must
be executed in real-time, so for short periods of time, extremely high performance is required. In the MPA-II, the
BCP also has other real-time demands on it. For example,
the MPA-II requires the BCP to perform DCA or IBM 110
hardware emulation real-time in firmware. Furthermore, both
the controller and the PC are asychronous events which
can (and do) occur at the same time.

MPA-II Firmware Organization

The BCP firmware provides true 5250, 3270, and 3299 emulation support, as well as providing the intelligence behind
the PC interface. To do this, a software architecture radically different than the DCA or IBM systems was developed.
The real power of the BCP lies in its rich instruction set and
full featured CPU. Taking advantage of that power, the BCP
firmware is interrupt driven and task oriented. It is not truly
multi-tasking, although the firmware logically handles mUltiple tasks at once. The firmware basically consists of a round
robin task scheduler (called the Kernel) with real-time interrupt handlers to drive the system. Events that happen in
real-time, such as accesses by the PC or host commands,
schedule tasks to complete background processing. Realtime status and responses are developed and presented in
real-time.

Using Hewlet Packard's 16500A Logic Analyzer and
10390A System Performance Analysis Software, the
MPA-lI's worse case performance scenario was analyzed.
This scenario consisted of the MPA-II running 3270 with
EAB installed while performing IRMA file transfers using
DCA's FTCMS software. A special NO-OP routine was added to the MPA-II software in order to achieve 100% utilization of the BCP. The breakdown of relative activity is shown
in Table 4-4.

The BCP firmware uses a number of memory constructs
known as templates to handle its data structures. The primary construct is the D~P, or Device Control Page. The
DCP is a 256 byte block that contains all global system
variables. The DCP contains a map of which SCPs, or Session Control Pages are active. Each SCP is 256 bytes and
contains all variable storage for a particular session; 3270,
5250, or 3299. Each SCP has a corresponding screen buffer, and optionally an EAB buffer (there is no EAB in 5250
terminals).

TABLE 4-4. MPA-II Performance

MPA-II Performance

The BCP is running at 18.8696 MHz with no instruction
memory wait states and one data memory wait state. This

Coax Related Activity
IRMA Related Activity

9%
10%

Total Activity

19%

As is shown in Table 4-4, the BCP still has over 81 % of its
bandwidth free to do additional tasks.

2-18

Advanced Product Possibilities

mabie logic devices, this level of functionality was provided
on a single half-height PC XT / AT card. In an effort to convey the reasons behind specific decisions made in the hardware design, the design methodology is presented from a
"top-down" perspective.

With over 81 % of the BCP's bandwidth unutilized, possibilities for advanced 3270/3299 and 5250 devices with exceptional overall system performance, advanced features, and
compactness become both realizable and practical. For example, if a more efficient PC to MPA-II (BCP) interface was
developed which eliminated the need for the BCP firmware
to emulate I/O hardware, and additional tasks were off loaded to the BCP, such as Regen/EAB buffer to PC Screen
buffer translation, then the overall system performance of a
full featured MPA-II CUT mode terminal could rival that of
the most advanced IBM CUT mode terminals. Yet, the PC
memory requirements of such an emulator would be less
than that of the simplest PC emulator on the market today
because the PC software would only need to process keystrokes and copy the BCP's translated PC screen buffer
directly into the PC's screen buffer memory. Furthermore,
advanced features such as 3299 support could be included
without additional hardware costs. All this is possible using
the current MPA-II board without hardware modification because the MPA-Il emulates DCA and IBM interface hardware using BCP software. Adding this new interface into the
.
product requires only software changes.

Architectural Overview
The MPA-II hardware should be viewed as three conceptual
modules (see Figure 5-1 ), including:

1. BCP minimum system core, consisting of the BCP, instruction memory, data memory, clock, and reset logic.
2. PC interface including the PC and BCP memory decode
and interrupts.
3. Coax/twisted pair and twinax front-end logic and connectors.
These module divisions are denoted by the dotted lines
seen in Figure 5-1. The minimum system core is required,
with some modifications, for any design using the BCP. The
type of bus (PC, PS/2™ Micro Channel™, VME, etc.) and
transfer rate requirements dictate the interface logic, which,
for the MPA-II design, is optimized for the PC XT/AT I/O
channel. The front-end logic meets the physical-layer requirements of the 3270 and 5250 protocols.
Since much of the logic external to the BCP is implemented
in programmable logic devices (PALs), these conceptual
partitions overlap at the device level. Although the design
can be implemented in discrete logic, we chose to use programmable logic devices to shorten development time, decrease board real-estate requirements, and maintain maximum future adaptability. The schematic and the listings describing the logic embodied in the PALs are in the Hardware
Reference in Appendix A.

5.0 HARDWARE ARCHITECTURE
This chapter focuses on the hardware employed to satisfy
the goals of the MPA-II project. Designed to support both
the coax (3270/3299) and twinax (5250) protocols, the
hardware also allows emulation of the PC interfaces outlined in Chapter 2. By taking advantage of the BCP's power
and integrating the extra logic requirements into program-

FRONT END

BCP CORE

I
I
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INSTRUCTION
RAt.I
Bk x 16

COAX/
TWISTED
PAIR
FRONT
END

TWINAX
FRONT
END

I+i-

32k x B DATA RAt.I
0

t t

BCP
DPB344

18.86" .",

PC INTERFACE
I
I
I
I

DUAL PORT
MEMORY

DCA READ
REGISTERS
DCA WRITE·
REGISTERS

B MHz

Inb

MPA-II REGISTERS
PC ACCESS REGISTER
(MPA_ACCESS)

AUXILIARY CONTROL
REGISTER (t.4PA DATA)

INTERFACE
UNIT:

I
I

IBt.I REGISTERS
32K

....

I
I
I
I
I

DUAL
""RY
I/O PORT
REGISTERS
PC IRQ INTERRUPT

~
~

IRMA
MAILBOX

I/o

220-227h

SMART ALEC
MAILBOX

I/o

22B-22Fh

IBt.I
REGISTERS,
DUAL PORT
. MEt.lORY

I/o 2DO-2DFh
t.lEt.lORY BKi
MOVEABLE
DEFAULT:
CEOO: 0000

MPA-II
COMMAND
INTERFACE

I/o

20B-2DCh
2DFh

I
I
I

64K

TLlF/l04BB-B

FIGURE 5·1. MPA·II Hardware Architecture

2-19

•

BCP Minimum System Core

The 18.8696 MHz clock is provided by the BCP's on-chip
clock circuitry and an external oscillator. This circuit, in conjunction with external series load capacitors, forms a
"Pierce" parallel resonance crystal oscillator design. The
oscillator is physically located as close as possible to the X1
and X2 pins of the BCP to minimize the effects of trace
inductances. The traces (0.05") are wider than normal. NEL
Industries makes a crystal specifically cut for the
18.8696 MHz frequency and is the recommended source for
these devices. This crystal requires a 20 pF load capacitance which can be implemented as 40 pF on each lead to
ground minus the BCP/socket capacitance and the trace
capacitance. A typical value for the BCP/socket combination capacitance is 12 pF. The wide short traces contribute
very little additional capacitance. We therefore chose a
standard value of 27 pF for the discrete ceramic capacitors
C24 and C25, placing them as close as possible to the crystal. The 5.60 pull up resistor tied to X1 is designed to improve oscillator start up under unusual power supply ramp
conditions. This is normally not a problem for PC power supplies so that the resistor could be omitted. The twinax clock
is provided by a standard 8 MHz TIL monolithic clock oscillator attached to the BCP's external clock input, XTCLK.

The BCP offers a high level of integration and many functions are provided on-chip; there is, however, a minimal
amount of external logic required. This core is comprised of
the BCP and the external logic require to support the clock
requirements, reset control, Harvard memory architecture,
and multiplexed AD bus (see Figure 5-2).
Clock Source
The coax and twinax protocols operate at substantially different clock frequencies (2.3587 MHz and 1 MHz, respectively), therefore two clock sources are required. The BCP
has the software-programmable flexibility to drive both the
CPU and transceiver in the following ways: the clock independently divided down to either or both sections, or by two
separate asynchronous clocks (utilizing the external transceiver clock input, XTCLK). To provide sufficient waveform
resolution, the transceiver must be clocked at a frequency
equal to eight times the required serial bit rate. This means
that an 18.8696 MHz (8 x 2.3587 MHz) clock source is required when operating in the 3270 coax environment and an
8 MHz clock (8 x 1 MHz) is needed for the 5250 twinax
environment. An 18.8696 MHz clock is also a good choice
for the BCP's CPU section.

The MPA-II runs the BCP at full speed, 18.8696 MHz
((DCR[CCSll = 0), with zero instruction (nIW) and one
data (now) wait states, resulting in a T-state of 53 ns. For a
system running the BCP at half speed, 9.45 MHz
((DCR[CCSll = 1), with zero instruction (nIW) and zero
data (now) wait states, the T-state would be 106 ns. The Tstate can be calculated using the following equation:

Therefore, in the coax mode, the transceiver and the BCP's
CPU share the same clock source. To maximize the available CPU bandwidth in the twinax mode, the 18.8696 MHz
clock source drives the CPU while a TIL clock is used to
drive the BCP's external transceiver clock input. Therefore,
in the twinax mode, the BCP's CPU and transceiver sections
operate completely asynchronously.

T-state = 1/(CPU Clock Frequency)
ADDRESS

CI"!"RY

R7W

....

/16

RESET

INSTRUCTION
MEMORY

(2) 8k x 8
6264

READ

BCP

WRITE

ADDRESS

ALE

CONTROL

X-TCLK

....

'16

osc.

, 16

/
'I

IWR

TL7705A

8 !.1Hz

....

DATA

..1
RESET

~
'I' 8

b.~:;i

LATCH
74ALS573

5[
ADDRESS/DATA

DATA
MEMORY

32k x 8

1\
r'

62256

!.1Hz

TL/F/10488-16

FIGURE 5·2. BCP Core

2-20

Reset Control

Instruction Memory

Power-up reset for the BCP consists of providing the debounced, active low, minimum pulse width specification of
ten T-states. Since the BCP powers upin the slowest configuration, a T-state is the period of the oscillator divided by
two, or 106 ns. The external logic must therefore provide a
minimum 1.06 JJ.s reset pulse to the BCP. The MPA-II design
incorporated two reset sources in addition to power-up including: the PC I/O channel reset· control signal (active
high), and an automatic reset if the digital supply voltage
drops by more than 10%.

A design goal for the MPA-II project dictated our choice of
static RAM for instruction memory, since the ability to softload code from the PC was necessary. Furthermore, to maximize CPU bandwidth we chose zero wait-state instruction
memory operation. When the hardware was designed, instruction memory requirements were estimated at 4k to 8k
words, therefore two 8k x 8-bit static RAMs were employed.
Instruction memory access ti~e requirements can be calculated using Parameter 1, the Instruction Memory Read Time,
Table 5-5, Instruction Memory Read Timing, of the Device
Specifications section of the DP8344B Data Book.

We chose the Texas Instruments TL7705A supply voltage
supervisor to monitor Vee and provide the minimum pulse
width requirement. This device will reset the system if the
digital 5V supply drops by more than 0.5V, and keep the
reset asserted until the voltage returns to an acceptable
level. The TL7705A will also assure that the minimum time
delay is met. The time delay is set by an external capacitor
and an internal current source. Since this time delay is not
guaranteed in the data sheet, we chose a 0.1 JJ.F ceramic
capacitor resulting in a typical 1.3 ms reset pulse width. A
0.1 JJ.F ceramic capacitor is connected to the REF input of
the chip to reduce the influence of fast transients in the
supply voltage. The active high PC reset signal is inverted in
the MPA-ILAC (MPA-II Auxiliary Control) PAL. The active
low output of the bipolar TL7705A is the MPA-II system reset and is pulled up by a 10k resistor for greater noise immunity.

(nlW

+ 1.5) T + C-19) ns

Where: nlW is the number 'Of instruction wait-states, and
T = 53 ns. Therefore the maximum access time is (0 + 1.5)
53 - 19 = 60.5 ns. For the MPA-II system running the BCP
at half speed (T-state = 106 ns), the maximumaccess time
is (0 + 1.5) 106 - 19 = 140 ns. Comparing both the half
and full speed maximum instruction memory access tim~
requirements, it is apparent that 55 ns RAMs are appropri:
ate. A complete instruction memory timing analysis is pro~
vid~d in Appendix B.
.
Reads of instruction memory by the remote system occur
through the BCP and look identical in timing to the local
(BCP) reads on the instruction bus.

Soft-Load Operation
The BCP. cannot modify instruction memory itself. Memory
is only written through the BCP (while the BCP is stopped)
from the remote system (PC), and is referred to as "softload" operation. Since the BCP has an 8-bit data path and a
16-bit instruction bus, instructions are read or written by the
PC in two access cycles; the first cycle accessing the low
byte of the instruction, the second cycle accessing the high
byte of the instruction and automatically incrementing the
Program Counter after the instruction has been accessed.
See the Remote Interface section of the DP8344B Data
Book for a complete description of instruction memory accesses.

Memory Architecture
The BCP utilizes separate instruction and data memory sections to overcome the single bus bandwidth bottleneck often associated with more conventional architectures. Instruction memory is owned exclusively by the BCP (remote
processor accesses to this memory occur through the BCP,
and only when the BCP is stopped); therefore, the entire
instruction memory/bus bandwidth is available to the BCP.
This architecture allows the BCP to simultaneously fetch
instructions and access data memory, thus load/store operations can be very quick. It is important to note, however,
that the instruction bus bandwidth does have some dependency on data bus activity. If a remote processor, for instance, is currently the data bus master, execution of an
instruction accessing data memory will be waited, degrading
BCP CPU performance.

The critical parameter for instruction writes is the minimum
write strobe pulse width of the RAM, which is about 40 ns
for most 8k x 8 55 ns static RAMs (55 ns RAM specifications are compared to the BCP minimum requirements since
it represents the worst case). The IWR (BCP Instruction
WRite output, active low) minimum pulse width is calculated
from Parameter 20 (IWR Low Time) in Table 5-22, Fast Buffered Write of IMEM, of the Device Specifications section of
the DP8344B Data Book:

The speed of both instruction and data memory accesses is
limited by memory access time. Since the BCP features programmable memory wait states, the designer has the flexibility of choosing memories strictly on a cost/performance
trade-off. No ex1ernal hardware is required to slow the BCP
memory access down (unless the maximum number of programmable wait states is insufficient, in which case the'
WAIT input of the BCP can be utilized). Instruction memory
access time has the biggest impact on system performance'
since every instruction executed involves an access of this
memory. Each added instruction wait state degrades zerowait state performance by approximately 40%. Load/store
operations occur less frequently in normal code execution,
therefore relatively slower data memory can often be utilized. Each additional data memory wait state degrades the
performance of a zero-wait state data access by about
33%.

(nlW

1)T -10ns

For soft-loads thafoccur after reset, the CPU clock is in the
POR half-speed state and the number of instruction and
data memory wait states is a maximum; therefore aT-state
is 106 ns and nlW equals 3; thus, IWR minimum pulse width
is (3 + 1) 106 - 10 '= 414 ns. Soft-loads that occur after
the BCP Device Control Register has been initialized to full
speed operation with no instruction wait states represent
the worst case timing of (0 + 1) 53 -.,. .10 = 43 ns, which is
still greater than the 55 ns RAM requirement of 40 ns.

2-21

Again, the numbers reveal the validity of the hardware design for local (BCP) accesses of data memory. Please see
the PC interface section for timing related to the remote
access. Also, an MPA-II timing analysis of both 106 ns and
53 ns T-states is provided in Appendix B.

Other parameters that must be considered are data setup
and hold times for the RAM. The BCP must provide valid
data on the Instruction bus before the minimum setup time
of the RAM and hold the valid data on the bus at least as
long as the minimum hold time. For the RAMs we considered, these times were 25 ns and 0 ns, respectively. Again,
looking at Table 5-22 (Parameter 19, I valid before IWR rising), we see that if valid data for the high byte of the instruction is present on the AD bus in time, the BCP is guaranteed
to present valid data on the Instruction bus a minimum of

Multiplexed AD Bus
The BCP's 8-bit data bus is multiplexed with the lower 8-bits
of the data memory address bus to lower pin count requirements. This necessitates de-multiplexing the Address/Data
bus externally. The timing of the ALE (Address Latch Enable) control signal relative to the AD bus is optimized for
use with a standard octal latch, therefore a 74ALS573 is
employed to provide separate Address and Data buses for
the system. The TRI-STATE buffers of the latch are enabled
by the BCP output LCL (active low) such that if a remote
access occurs this device will TRI-STATE.

(nlW + 1) T - 18 ns
before the rising edge of IWR. The BCP will hold that data
on the bus for a minimum of 22 ns afterward (see Parameter
18, IWR rising to I Disabled). To see that the minimum set
up time is met for both the half speed POR state and the full
speed operation, note that both (3 + 1) 106 - 18 ns =
406 ns (half speed) and (nlW + 1) 53 - 18 ns = 35 ns (full
speed) are greater than the minimum set up time of the
RAM which was 25 ns. Furthermore, the minimum hold time
of 22 ns, for both half speed and full speed, is greater than
the 0 ns required. Thus, successful operation is assured.
See the MPA-II timing analysis in Appendix B and the PC
interface section in this chapter for a discussion of AD bus
timing.

PC Interface
As mentioned earlier, the MPA-II supports the industry-standard interfaces associated with coax and twinax terminal
emulation. These include:
COAX:
IBM 3270 Emulation Adapter Interface
DCA Decision Support Interface (IRMA)
TWINAX:
DCA Smart Alec Interface
These interfaces share some common elements, but have
many differences as well. The IBM adapter employs an interrupt-driven interface, IRMA's PC interface is a polled implementation, and Smart Alec, while operating in a polled
environment, has the capability of interrupting the PC as
well. The IBM Emulation Adapter's control registers are
mapped into the PC's I/O space; the screen buffer is
mapped into the PC's memory space and is relocatable
(see Table 5-2). The two DCA interface occupy a contiguous block of PC I/O space only; there screen buffer(s) are
not directly visible to the PC. These architectures are explored in much greater detail in Chapter 6 of this manual.
Note than the MPA-II utilizes some of the IBM reserved registers for MPA-II usage. These MPA-II registers may be easily relocated by changing the MPA-II PAL equations.

Data Memory
A considerable amount of data memory was required for the
MPA-II design since the system supports multiple sessions
(see Chapter Six, MPA-II Software Architecture, for more
information). For this reason we specified 32K of 8-bit data
memory).
Data Memory Timing
Data RAM can be accessed by both the BCP and the remote system, part of the RAM appears to the remote system as dual-ported RAM via the Remote Interface logic of
the BCP. This memory can be both read from and written to
during BCP code execution. Designing in the data RAM is
therefore a more complicated procedure than selecting instruction memory. Using 53 ns for the MPA-II T-state and
one for now (number of data wait-states) as defined earlier,
we can verify the critical memory parameters by comparing
the results of the calculations against the RAM requirements. The 32K x 8, 100 ns static CMOS RAM minimum
requirements for the critical parameters are compared
against the BCP's minimum specifications and are listed in
Table 5-1. For a complete description of the BCP minimum
specifications, see Appendix B.

TABLE 5-2. PC Mapping of the MPA-II Board

I/O
IBM Interface:
Remote Interface
Control (RIC)
Decoded and Unused
MPA-II Configuration
Register
MPA-II Parm/Response
Register
IBM Control Registers

TABLE 5-1. Data Memory Timing
Parameter

RAM

BCp·

Address Setup
Chip Select to Write End
Access Time
Write Strobe Width
Data Setup
Data Hold

0
90
100
60
40
0

47.5
122.5
108.5
96
86
31.5

Address

Description

02DF*
02DD* - 02DE*
02DC*
2DB*
02DO-02DA
CEOOO
(Relocatable)

IBM Screen Buffer

-All units are In nanoseconds.

DCA DSllnterface:
IRMA
Smart Alec

'53 ns T-state with one data wait state.

'Reserved IBM register spaces.

2-22

Memory

0220-0227
0228-022F

decoded for several functions (see Table 5-3). The decoding sections feed into a control section that makes the final
decision on whether (or not) the current PC bus cycle is an
access of one of the emulated systems. It should be noted
that the type of emulation is not selectable; the MPA-II
board will respond to accesses of all of the PC addresses
detailed in Table 5-2. The MPA-II will not run concurrently
with any of the boards it emulates, or any other board that
overlaps with these same addresses.
The BCP's RIC (Remote Interface Control) register is
mapped into the PC's 1/0 space. The PC can always find
this register by reading 1/0 hex address 02DFh. The DCA
interfaces (IRMA and Smart Alex) occupy PC 1/0 addresses
220-22Fh. The IBM interface occupies PC 1/0 addresses
2DO-2DFh for register space, and a relocatable 8k block of
memory for the screen buffer(s).

The MPA-II design had to encompass all of these implementations. This was accomplished by taking advantage of
the underlying similarity of the interfaces as well as the
speed and flexibility of the BCP. We minimized chip count
and board space requirements through judicious partitioning
of the PC address decode while emulating in BCP software
the interface registers in data RAM. Refer to Figure 5-3 for
an overview of the hardware architecture employed in implementing the BCP/PC interface.
The PC address decoding is partitioned into sections that
first check for accesses to the relocatable memory block
and accesses to the 1/0 register addresses of the different
interfaces. These addresses are then translated into the
proper area of the BCP data memory. The BCP data memory map is divided in half, the lower 32k is contained in the
single 32k x 8 RAM described earlier, and the upper 32k is

TABLE 5·3. BCP Data Memory Map
Description

BCP Address (A15-0)

Auxiliary Control Register (mp~data)
PC Access Register (mp~access)
'IBM API Registers
DCA API (IRMA and Smart Alec)
PC Writes:
PC Reads:
BCP-Owned Memory Area
'Screen Buffer Area

AOOO-BFFF
8000-9FFF
7FDO-7FDF
7F20-7F2F
7E20-7E2F
2000-7E1F
0OOO-1FFF

°Dual-Ported RAM (Visible to Both BCP and PC)

2-23

PC 1/0 Address

2DO-2DF
220-22F

Relocatable

»
z

en
~
~

r---------------------------------------------------------------------------------------~

'OI:t
CD

cs:
-

READ

ViR

WRITE

....
ADDR

~
ALE

BCP

LATCH
74ALS573

~'}.

...t.

AD
-

...t.

DATA
RAM
32k ,x '8

-1\
-V

DATA

62256

LCL

XACK
WR-PEND
REM-RD REM-WR

CMD RAE

4Y .
.... ;r

PC I/o AND MEMORY
ADDRESS DECODE

BUS
CONTROL
..tt.

...t.

lOW

lOR

MEMR

MEMW

10CHRDY
DATA

~
'4

ADDR

TL/F/10488-19

FIGURE 5·3. BCP/PC Interfaces

the MPA-II System, the base address of the memory segment must be loaded into the segment register (PC 1/0 address 2D7h) before the PC can access the IBM screen buffer area in dual-port RAM. This Segment Register is not accessible by the BCP. It is only accessed by a PC write to 1/0
location 2D7h. A PC read of the 1/0 address 2D7h accesses a corresponding RAM location which is written in the
same manner as all writes to the IBM 1/0 locations 2002DAh, as described next.

PC 1/0 and Memory Address Decode

The BCP CPU and Remote Interface units operate autonomously. Since the 1/0 registers are mapped into the BCP's
data RAM and the CPU has to know which register was
written to by the PC, external logic is provided that latches
the low six bits of the address bus during remote accesses.
The BCP can read this external register to identify which
emulated register has been modified and take the appropriate action.

Accesses to the 1/0 locations used by the IBM Interface
(200h-2DFh) and the DCA DSI Interfaces (220-22Fh) are
decoded as follows: PC address lines A 12-A4 are brought
into the MPA-II_PD (PC Address Decode) PAL-U9 for decode. PC address lines A 14-A16 and A 17 -A 19 are first
decoded with three input NOR gates, U5B and U5C, which
are in a 74ALS27. The outputs of both of these NOR gates
are then brought into the MPA-II_PD PAL for further decode. Note that PC address lines A 13 and AO-A3 are not
decoded at this point. A preliminary decision is made by the
MPA-II_PD Pal to indicate if the IBM or DCA interfaces are
being accessed. The outputs DCA-REG and IBM_REG

The relocatable memory segment location where the
screen buffer of the IBM interface is located is decoded in
discrete hardware consisting of the following components:
U15, a 74ALS521 magnitude comparator that compares the
PC memory address accessed against the stored value of
the relocatable memory segment address and asserts the
signal MMATCH (active low) when a match occurs; the Segment Register U16, a 74ALS574 containing the stored
memory address used to identify the memory segment of
the screen buffer block. The relocatable block of data memory defaults to base address CEOOO on the IBM adapter. In

2-24

indicate which, if any, emulated interface is being accessed.
These signals are used in conjunction with MMATCH, the
PC address lines A 13 and AO-A4, and the read and write
strobes of the PC in U7, the MPA-II_RD (MPA-II Register
Decode) PAL to make the final determination on the validity
of the access. If it is an emulated interface I/O register access, IOJCCESS will be asserted back to the MPA-II_PD
PAL. This PAL will in turn translate the access to the top of
the BCP data RAM where the I/O register page is located
(see Table 5-3). Note the differentiation in Table 5-3 between PC reads and writes for the DCA translation. This is
required to emulate the dual-ported register files used on
the DCA boards.

operates autonomously. This unis is very flexible and offers
a number of configurations for different external interfaces
(see the Remote Interface and Arbitration System chapter
of the BCP data book). We chose to use the Fast Buffered
Write/Latched Read interface configuration to maximize the
possible data transfer rate and minimize the BCP performance degradation by the slower PC bus cycles. Data is buffered between the PC and BCP data buses with U18, a
74ALS646, giving us a monolithic, bidirectional transceiver
with latches for PC reads and buffering for PC writes.
Rest Time Circuit
To support the newer high performance PC AT compatibles
entering the market, a rest time circuit is implemented on
the MPA-II. The purpose of this circuit is to prevent two
remote accesses made by a high performance PC from being mistaken as one remote access. (For a detailed descrip~
tion of BCP remote rest time, refer to the Remote Interface
and Arbitration System section of the DP8344A data sheet).

If the PC access is to the IBM screen buffer, IOJCCESS
will not be asserted out of the MPA-II_PD PAL. The MPA"_PD PAL will, when [C[ goes high on the remote access,
force A15 low and pass the buffered address lines A12-8
onto the data RAM. Address lines A 14 and A 13 are implemented through U8, MPA-II_CT (MPA-II Control Timing)
PAL. PC address lines A7-0 are buffered by U14, a
74ALS541 and passed onto the BCP data memory address
lines AD7 -0 when LCL switches high for the remote access. The data memory RAM's chip select, DMEM_CS, is
asserted on any remote access. If the BCP's LCL output
goes high, DMEM_CS will be asserted low; on,a local access, this signal will be asserted if the BCP's A 15 signal is
low (RAM occupies the lower half of the BCP's memory
map).

The rest time circuit is implemented in one PAL16RA8,
MPA-II_RI, U4. This rest time circuit implements all modes
except Latched Write and does not take advantage of the
increase in speed possible when CMD does not change
from one access to the next.
First, how the REM_ENABLE Signal controls remote accesses will be discussed. Then, a description of the operation of the rest time state machine in the PAL16RA8 will be
given.

This scenario for remote accesses works because RAM is
the only element external to the BCP that is visible to the
PC. If the PC is accessing the BCP (RIC, the Program Counter, or Instruction Memory), the BCP's READ/WRITE
strobes will not be asserted to the data RAM. On a PC access of the BCP's RIC register, for example, data RAM will
be selected and the CMD (CoMmanD) output of the MPA"_RD PAL will be asserted to the BCP, selecting the BCP's
RIC. No bus collision will occur on a read or data inadvertently destroyed on a write because the BCP will not assert
the external strobes on an internal register access.

The REM_ENABLE signal is produced in the rest time
PALRA8 and is low during rest time. After rest time is over
the REM_ENABLE signal goes high until the end of the
next access, when it once again goes low during rest time.
The signal REM_ENABLE is fed back into MPA-II_RD,
U7.
Through the rest time circuit, both REMRD and REMWR are
held high when REM_ENABLE = o. This prevents all remote accesses during rest time. When rest time is over
REM_ENABLE = 1 and then decodes of MEMW, MEMR,
lOW, and lOR control REMRD and REMWR respectively.

The MPA-II_RD PAL also combines the memory and I/O
read/write strobes to form the REMRD/REMWR strobes to
the rest of the MPA-II system. Since PC bus cycles can only
be validated by the assertion of one of these strobes, this
PAL makes the final decision on the validity of the bus cycle.
If the PC cycle is a valid access of the BCP system, this PAL
will assert RAE (Remote Access Enable), the BCP's chip
select. RIC, the output CMD, and the BCP's READ/WRITE
strobes will determine which part of the system receives or
provides data.

STATE: IDLE
This state is entered when a system reset occurs. In this
state REM_ENABLE = 1, and XACK controls the state of
PC_RDY.
The state machine will stay in this state until a valid remote
access starts (Le. RAE = 0). Then the state machine
moves to CYCLLSTART.

The PC IRQ interrupt for the IBM interface is set and
cleared by the BCP through U3, the MPA-IIJC (Auxiliary
Control) PAL. The interrupt is set from the BCP by pointing
data memory to an address in the range AOOO-BFFF (see
Table 5-3), and writing to this location with AD7 set high; it is
likewise cleared by writing with AD7 low, to this location. The
interrupt powers up low (deasserted) and can be assigned
to PC interrupts IRQ2, 3, or 4 by setting the appropriate
jumper (JP4-6).

NOTE: The Signal ~ is a full decode of a valid access by MPA-U_RD, U7.
If I1Al: is only an address decode, it alone would not indicate that a
valid access has started.

STATE:CYCLE--START
In this state, REM_ENABLE = 1 and XACK controls the
state of PC_RDY. The state machine will stay in this state
until the remote access ends, indicated by RAE = 1. Then
the state machine moves to WAIT1.

Remote accesses of the BCP are arbitrated and handled by
the Remote Interface and Arbitration System (RIAS) control
logic. The arbiter sequential state machine internal to the
BCP shares the same clock with the CPU, but otherwise

2-25

,...
~

STATE: WAIT1

L.stat
-Emulation Mode
mp3.-mainstat
-Main Interface Control Bits, such as
Clicker and Alarm Status

2-37

•

~ r---------------------------------------------------------------------------~
~

ca:

mp<-pack, respectively. The basic functions of the cz-poll
routine are to decide if TT / AR or special status should be
returned to the coax controller and to handle the POLL
modifiers in the upper bits of the POLL command. These
modifiers include the terminal alarm and key click control.
The determination of which status to send is made after
checking mp~control for the MPA-STAT_PEND bit. If
MPA-STAT_PEND is asserted, the poll response variables have new status to send. If no status is pending,
TT / AR is sent. Next, the POLL command modifiers are applied
to the alarm and clicker status bits in mpLmainstat.
The POLL! ACK routine always responds with TT / AR. Next,
mp~control is checked to see if the pending status has
been polled by the coax controller..If not, the POLL! ACK
routine exits. Otherwise the pending status is cleared and
both mp~control and mp~auxcontrol are updated. Then
the poll response bytes, poliresp_lo and pollresp_hi, are
cleared.
Update_poll in the C~TASK.BCP module handles updating mp~control and mp~auxcontrol to reflect new status
conditions. This routine' updates the poliresp_lo and hi
bytes based on the priority of the status in mp~control
and mp~auxcontrol. POR is the highest priority condition
and outstanding status from EAB is the lowest.

2-40

Read Commands
All read type commands to the base are found in the
CLBASRD.BCP module. Each read type command is decoded by the receiver interrupt handler and vectored to the
appropriate cx-routine. The most basic read type command is cx-readata. This is invoked upon decoding the
READ DATA data stream command. The character pointed
to by the address counter is sent immediately. The addrcounter variable is incremented after the character is
sent.

through the routine and cumulative interrupt latency effects
may become significant. To address this, the dv_write routine always empties the receiver FIFO.
Other write type commands found in the CW_BASWR.BCP
module include the initial stubs for the foreground commands; SEARCH FORWARD, SEARCH BACKWARD, INSERT, and CLEAR. All these commands are initially decoded and vectored here in real-time. When their associated
parameters are received, the foreground commands are
scheduled through the sub-task communcation mailbox. All
the foreground commands cause the terminal to set
NOTJVAIL status (busy) in the status register. All four
respond with TT / AR to acknowledge reception of the command and parameters cleanly.
All the other write commands load variables on the SCP
corresponding to registers in the emulated terminal, or
cause some controlling action in the terminal. These include
the low and high bytes of the address counter, the mask
value for CLEAR and INSERT, the control registers and resetting the terminal. Cx-reset calls the hosLreset routine
that re-initializes the SCP variables to the POR state. The
screen buffers are not cleared. The START OPERATION
command causes a vector to the cx-start routine and returns TT / AR.

The cx-readmul routine is also found in the
CLBASRD.BCP module and is vectored to when a READ
MULTIPLE command is decoded. READ MULTIPLE expects multiple bytes of screen data to be sent within 5.5 p,s.
The response is initiated inside cx-rdmul. The routine has
two modes: 4 byte and 32 byte. The default mode is 4 byte
and is determined by the state of the LSB in the secondary
control register. Both modes use the variable addrcounter
on the SCP to determine both where to find the data to send
and how many bytes to send, up to the 4 or 32 byte limit. In
other words, 4 and 32 bytes are the maximum that will be
sent to the coax controller. The addrcounter is incremented
after sending each byte and terminates the response when
the two or five low order bits roll to zero. The transmit FIFO
on the BCP will hold up to three bytes. The Transmitter
FIFO Full flag, TFF, indicates when the transmitter's FIFO
has been loaded with those three bytes. Using this flag, the
read multiple routine begins by loading the transmitters
FIFO. Once TFF is true, the read multiple routine then alternates between checking the TFF flag and checking for PC
activity via the BIRO flag. If PC activity is detected, then the
appropriate fast BIRO routine is called to handle the PC
access. When. all the requested bytes have been sent, the
read multiple routine passes control to the receiver interrupt
handler exit routine. The remaining read type commands
are all handled similarly. Cx-rach and cx-racl respond
with the high and low bytes of the addrcounter variable,
respectively. Cx-rdid responds with the terminal ID byte.
Cx-rxid responds with TT / AR since it is not implemented.
Cx-rdstat responds with the staLreg variable. All these
commands check for LTA prior to responding. If LTA has
not occurred, then a protocol error is posted since read type
commands are required to be the last frame in a message
from a coax controller. The cx-rdid routine does additional
processing, however. The status conditions OPERATION
COMPLETE and FEATURE ERROR are cleared by reception of the READ ID command.

Foreground Commands
The foreground routines are all executed by cx-task when
the sub-task communication mailbox is filled with the appropriate value. These are tLinsert, tLclear, tLsforward
and tLsback. The routines are found in the
CLCOM.BCP module along with other local support routines.
EAB Commands
The EAB commands are found in the CLEAB.BCP module. Read and write type commands addressed to the EAB
feature are included here. The number of commands for the
EAB feature are small enough that they are logically
grouped together in one module, as opposed to the base
commands. Some of the more complex commands from a
performance standpoint are addressed to the EAB feature.
WRITE ALTERNATE, WRITE UNDER MASK, and READ
MULTIPLE EAB require the most real-time bandwidth of any
coax function.
The READ MULTIPLE EAB command is the same as its
base counterpart except for two features: it functions with
the EAB exclusively and, if the Inhibit Feature I/O step bit in
the Control register is set, then this command is ignored.
WRITE ALTERNATE receives a variable length stream of
data that is written with screen and EAB data alternately.
The WRITE UNDER MASK command uses data associated
with the command, the EAB byte pointed to by the cursor
register, and the EAB mask to modify the contents of the
EAB. The algorithm is quite strange and is best described by
the code. Please refer to eab_wum and dv_wum for specifics on the command implementation.

Write Commands
All write type commands to the base are found in the
CLBASWR.BCP module. Commands are decoded by the
receiver interrupt handler and vectored to this module at the
cx-addresses. Each write command has an associated
dv_stub for handling incoming data. The routines load the
DATA-VECTOR with the appropriate stub before exiting.
Cx-write and its data vector stub dv_write are responsible
for writing data into the screen buffer, setting the MPA-ll's
Buffer Being Modified semaphore and indicating the screen
buffer update in the MPA page change word. When the next
command is decoded, write mode will be terminated, the
Buffer Being Modified bit will be cleared, and the Buffer
Modified bit will be set. The dv_write stub is very critical in
that very large blocks of data may be sent to the device

IRMA Interface Overview
IRMA is a member of a family of micro-to-mainframe links
produced by Digital Communications Associates. It provides
the IBM PC, PC XT, or PC AT with a direct link to IBM 3270
networks via a coaxial cable connection to an IBM3174,
3274, or integral terminal controllers with type "A" adapters.

2-41

.....
~

<-read_line vector is set up for the
transmitter interrupt. The transmitter will in turn respond to
the System Unit with the contents of the regen buffer line.
The tw_read_dev_id_cmd command routine first decodes the device/feature address by comparing the field to
all defined logical devices and feature addresses. If there is
a match, it will jump to the appropriate command routine to
set up routines to respond with the device or feature ID.
Otherwise it will jump to the twJead_fid~oLinstall routine which will direct the transmitter to respond with zero
data.
There are three different flavors of the READ DATA command. The READ DATA command addressed to the Magnetic Strip Reader is documented in the 5250 PAl. Since the
MSR is not installed, the tw_read_dat~cmd command
routine sets up the t><-read_data routine address for the
transmitter interrupt and them jumps back to tw_cmd_ret.
The transmitter will in turn respond to the System Unit with
sixteen bytes of zero data, per the 5250 PAl. The other two
flavors of the READ DATA command are undocumented,
but supported by the IBM 5250 terminal emulation card. The
READ DATA command 08h directed to the Base device
simply returns the regen buffer byte that the address counter currently points to. An invalid register exception is posted if the address counter value lies outside the regen buffer
area. Then the t><-dat~vector is set to the t><-rd_dat~
base 08 routine address for the transmitter interrupt by the
tw_rd_dat~base08_cmd command routine. The READ
DATA command 18h is the other undocumented read command. It is very similar to the read immediate command
discussed below except that the address counter points to
the start of the response, the address counter is set to the
last byte of the response plus one, and that if no attribute is
found when the end of the regen buffer is reached, then an
attribute exception is posted. The tw_rd_dat~base18_
cmd sets up the t><-rd_dat~base18 routine address for
the transmitter interrupt, as well as the starting address for
the response. Note that the tw_rd_dat~base18_cmd
command routine actually determines the ending address
and then simply passes a count to the transmitter interrupt
as to how many bytes of the regen buffer to return. This
keeps the transmitter interrupt very simple.
The tw_read_limits_cmd transfers a display field of data
to the controller. The area of transfer is delimited by the
address counter and reference counter; therefore, tw_
read_limits_cmd first checks whether they lie within the
regen buffer and whether the reference counter is greater
than or equal to the address counter. If anyone of these
tests fail, the program will post an invalid register value exception and return to the session task. Otherwise, it will
pass the address counter and the byte count (reference minus address) to the transmitter interrrupt through four memory storage locations: tw_acLbeginlo, tw_acLbeginhi,
tw_acLendlo and tw_acLendhi, and then set up the
READ LIMITS routino. The transmitter will then fetch the
data from the regen buffer and send it to the System Unit.

WRITE Commands
All write type commands are grouped in the TW_
WRITE.BCP module. The entry names of the command routines are shown in Table 6-6. The PREACTIVATE WRITE
command routines, tw_write_imm_cmd and tw_write_
dat~cmd, are relatively simple. They just set the beginning
address of the operation to tw_acLbeginhi and tw_acL
beginlo. When the receiver interrupt gets an ACTIVATE
WRITE command, the receiver interrupt will put the data
into the regen buffer and determine the end of operation.
Processing of other write commands is done completely in
the foreground. We shall discuss each command in more
detail.
TABLE 6-6. Entry Names of Module tw_write
Command Name
WRITE CONTROL DATA
WRITE DATA and
LOAD CURSOR-base
WRITE DATA and
LOAD CURSOR-indicate
WRITE IMMEDIATE DATA
WRITE DATA

Command Routine
Entry Name
tw_write_cntl_cmd
tw_write_datCL.ld_cur_cmd
tw_write_datCL.lo_ind_cmd
tw_write_imm_cmd
tw_write_datCL.c.:md

The tw_write_cntl_cmd command pops the data byte following the command from the queue and puts it into the
control register location (tw_ctrI1) in the SCPo It also
checks the Reset Exception Status bit (bit 12) of the data
word. If the bit is set; the tw_clear_exception subroutine is
called. On the 3180-2 model terminal, the command may
have a second data byte. This routine checks bit 8 of the
first data byte, if it is set, one more byte will be popped out
and saved into tw_ctrl2 in the SCPo
The tw_write_dat~ld_cur_cmd command may also
have one or more data bytes associated with it. This routine
checks the first data byte to determine if it is in the range of
01 to OEh. If the data byte is not in this range, it is the only
data byte associated with the command and the routine just
writes it to the location pointed to by the address counter. If
the data byte is in this range, the routine will take the first
byte as the byte count and will pop that number of data
bytes from the queue and write them into the regen buffer.
During the write operation, the address counter will be incremented and checked for overflow. Storage exception status
will be posted if an overflow occurs. At the end of the operation, the program updates the cursor register to the value of
the address counter and loads up the action stack by calling
the tw_acLldr routine.
The tw_write_dat~to_ind.~_cmd command routine handles the WRITE DATA AND LOAD CURSOR command ad-

2-62

dressed to the indicators. It simply pops out the data byte
following the command and saves it in the memory location
tw_idctr_data in the appropriate SCPo It also notes the
transition direction of certain indicators and saves this information in the memory location tw_s~trans_ident for
Smart Alec.
The tw_write_imm_cmd routine first pops the starting address from the queue, then checks to see if it is valid. If it is
valid, it will be converted into absolute form and passed to
the receiver interrupt. The starting address entry of the action stack is also set up. The receiver will then pick up the
rest of the operation when the ACTIVATE WRITE command
is received.
The tw_write_dat, for information on the commands supported by MPADB. All the source code for
MPADB is included, see MPADB.C under the directory
DEBUG.

LD [Confi9-options ... ] [Options ... ]
where the following notation applies:

The read and write data commands use an internal MPA-II
register called the MPA-II address counter, AC. This address counter works much like the Coax and Twinax address counters. The read command returns the byte pointed
to by the MPA-II address counter. The write command
places its data at the location pointed to by the MPA-II address counter. Whether or not the MPA-II address counter
auto-increments depends on the contents of the MPA-II
control register, see Figure 6-21. If the LSB is a one (1) then
the MPA-II address counter auto-increments, otherwise it
does not change.

Items enclosed in square brackets are optional.

< >

Items enclosed in triangular brackets are required.

ALL CAPS Items in all capital letters must be entered exactly as shown.
lower case Items in lower case letters indicate that desired
values should be substituted.
The Loader Options that apply to the "soft-loading" of instruction memory will be discussed in the section titled
"Soft-Loading
Instruction
Memory".
The
Loader
Confi9-options will be discussed in the section titled "Configuring the MPA-II". The Loader options that apply to the
selftest facility will be discussed in the section titled "MPA-II
Diagnostics". Examples demonstrating the Loader options
as well as the Loader defaults will also be provided in this
chapter.

If 1 THEN POST INCREMENT AC

The Loader is primarily written in Microsoft "C"5.1. The portion of the Loader code which performs the MPA-II Diagnostics has been written using National Semiconductor's
DP8344 BCP Assembler System as well as Microsoft's
Macro Assembler 5.1. All of the source code required for
the Loader is included on the distribution disks and is well
documented. For complete details of the implementation of
the Loader functions described in this section, refer to the
source code.

L..-L_.l...-.......L_.L.........L_ _ _ RESERVED
TL/F/10488-65

FIGURE 6-21. MPA-II Control Register
The Load Address Counter High, Load Address Counter
Low, Read Address Counter High, and Read Address Counter Low commands simply provide access to the 16-bit
MPA-II address counter. The Load Control Register allows
one to write to the 8-bit MPA-II control register.

The Loader provides two levels of help. The first level of
help is provided in a brief, single screen and is accessed by
typing LD with no options at the DOS system prompt. A
multi-screened, comprehensive help, is accessed by specifying the -h option of tlie Loader as shown below:
LD -h

The receiver error counter commands provide an easy, reli·
able way to read the MPA-II receiver error counters located
in the MPA-II Device Control Page, DCP. PC software that
uses these commands does not have to be updated if the
receiver errors are relocated in BCP data memory because
the BCP assembler will automatically update all references
to those error counters when the MPA-II microcode is re-assembled.

The Loader provides the following return values which are
useful when using the Loader in a batch file:

Finally, the Revision Number command allows the PC to
determine a) if the MPA-II running and b) what version of the
MPA-II microcode is the MPA-II running. This MPA-II command is used by the Loader when the Loader performs an
autoload (·a option). For the PC to read the revision number,
the REV command must be executed three (3) times. Each
returned byte's bits are defined as "xxcc dddd", where:

PASSED: Loader ran to completion as requested by the
user.

WARNING: Loader ran to completion, but not exactly as
requested by the user.

16 FATAL ERROR: Loader was unable to run to completion due to a fatal error.
Before the Loader implements any of its primary functions, the Loader will verify that the MPA-II printed circuit
board is present in the PC. This is done in two different
stages (see the Loader flow chart, Figure 7-1). First, the
Loader performs a non-intrusive test. This test entails
reading RIC a number of times while checking that the
value of RIC does not change and that the single step bit
of RIC is not set. The second test is intrusive, meaning
that it will affect the current state of operation of the
MPA-II, if the MPA-II is "alive" (more on this later). This
test checks for the presence of the MPA·II by writing various patterns to RIC, then reading RIC back to check that it
contains the correct value. For example, when the pattern
written to RIC has the single-step bit set and the start bit
cleared, the Loader expects to read back RIC with the
single-step bit cleared. If either of the instrusive or non-in-

dddd = a revision digit coded in Binary Coded Decimal,
BCD
cc
= a count showing the position of the revision digit
xx

[]

= reserved

For example, if calling REV three times returned (in hex) 20,
34, and 13, then the revision number is 3.04.
Last notes, unused commands and invalid parms are ig·
nored. In addition, commands with values less than 3F(hex)
are reserved for National Semiconductor. Feel free to define
commands with values greater than this if compatibility with
future MPA-II releases is desired.
7.0 LOADER AND MPA-II DIAGNOSTICS
The Loader is a PC program designed to load the MPA-II
with BCP microcode, start the BCP, and configure the
2-71

•

,...

Filename: The file specified by the Filename contains the
BCP microcode to be soft-loaded into the MPA-II system.
The file format must be either BCX or FMT as described
earlier in this section. The - Band - F options can be
used to specify the file format as BCX or FMT, respectively. The file format can also be specified implicitly with
a file extension of .BCX for BCX format files or .FMT for
FMT format files. The Loader defaults to BCX format,
and, if no file extension is entered, the Loader will append
the appropriate file extension (i.e., either .BCX or .FMT).
A file with no extension can be loader by ending the file
name with a".".

Once the program counter has been initialized, the first instruction to be loaded into instruction memory is fetched
from the BCX or FMT format file specified by the user. The
instruction is then split into high and low bytes. This is necessary because the instructions are 16 bits wide, but they
must be latched into instruction memory through the BCP's
a-bit Data bus. The instructions are then loaded into the
MPA-ll's instruction memory by pointing RIC to instruction
memory and writing the low byte of the instruction followed
by the high byte of the instruction to dual port memory. The
program counter then auto-increments allowing the next instruction to be loaded. At any time, the program counter
may be modified, followed by instruction loads, to allow areas of instruction memory to be skipped. The remaining instructions are loaded in the same manner. When all the
instructions have been loaded, the system is started and
configured as requested by the user.

Options:

- 8- Specifies that the format of the file to be loaded is
binary or "BCX" format. This option provides the user
with the flexibility to load a file with an extension other
than .BCX as a BCX format file.
- F- Specifies that the format of the file to be loaded is
ASCII PROM or "FMT" format. This option provides the
user with the flexibility to load a file with an extension
other than .FMT as a FMT format file.
-N[ =] [I_addr]- Soft-loads the file into instruction memory beginning at the hex address, I_addr, but does not
start the MPA-II after the load. This feature can be useful
for debugging code using tools such as Capstone's monitor debugger, BSID. The load address, I_addr, defaults
to the hex address 0000.
- R[ =] [addr] [,r_addr]- Soft-loads the file into instruction memory beginning at the hex address I_addr, then
sets the program counter to r_addr and starts the BCP.

Interrupts can occur prior to the execution of the first instruction loaded into instruction memory if a BCP program
has been previously running in the MPA-II system with interrupts enabled. This is because the BCP uses a "dummy"
instruction to fetch the first instruction in instruction memory
and this "dummy" instruction does not disable interrupts.
The following is a scenario that describes this: the MPA-II is
running with a BCP program that has receiver interrupts enabled. The BCP is then stopped by clearing [STRT] in

2-73

The instruction address where the BCP begins running,
r_addr, defaults to the value of I_addr if r_addr is not
specified. I_addr defaults to the hex address 0000.

is possible for the BCP, but not for the DCA or IBM interfaces.) The terminal emulation interface which the MPA-II emulates is implemented by the MPA-II as described in Chapter
6. The Loader Configuration Options available to the user
will be discussed later in this section.

- U [ = ] [seg_id]- Enables dual port RAM in the PC memory map to the PC memory segment seg_id, where
seg_id is the upper byte of the PC memory segment.
This allows the MPA-II system to avoid PC memory conflicts. The Loader defaults to seg_id = CEo The value for
the seg_id must be on an even 8K boundary. Therefore,
seg_id = CD is invalid.

The Loader configures the MPA-II interface mode by writing
the configuration to the MPA-ll's Configuration Register.
Figure 7-2 shows the bit definitions for the MPA-II Configuration Register. The Loader writes to the configuration register immediately after starting the BCP's CPU. The MPA-II
configuration register is located at the PC I/O location
2DCh. Writing to this register will set the BIRO interrupt, and
thus, could lock out the PC if this feature has been activated
by previous BCP microcode. If the BCP's CPU is stopped
when the configuration register is written, then the next access of the BCP's memory (both dual port and I/O) made by
the PC could be held off indefinitely since the BIRO interrupt
can not be cleared by the BCP's microcode. Therefore,
when the Loader Option - N, as described in the previous
section, is selected, the Loader will not set the configuration
requested. (The Loader notifies the user that the configuration has not been set.) See Chapter 5 for further information
regarding BIRO and the PC lock out feature.

Examples using the file, MPA2.BCX, provided in the MPA-II
Design/Evaluation Kit are shown below. This file is a BCX
formatted file. The following examples all load the file
MPA2.BCX in the same format and demonstrate the - B
and - F options:
LD MPA2

Loader defaults to BCX
format and applies the .BCX
file extension.

LD MPA2.BCX

Loader determines that
format is BCX from the file
extension.

LD MPA2.BCX -B Loader determines that the
file format is BCX from
the -B option.
The following example demonstrates options which affect
how the file is soft-loaded:

The Loader uses the following handshaking protocol with
the BCP microcode to verify that the configuration has been
recognized by the MPA-II system. The Loader sets [PaR] in
the MPA-II Configuration register when it writes a configuration to the MPA-II Configuration Register. The Loader then
polls the MPS-II Configuration Register looking for [PaR] to
be cleared by the BCP microcode. This indicates that the
BCP microcode has processed the requested configuration.
The value in the MPA-II Configuration Register now contains the actual MPA-II interface configuration implemented
by the BCP microcode. If [PaR] is not cleared within a predefined time period, then the Loader reports a failure. If
[PaR] is cleared within the predefined time limit, the Loader
then compares the configuration implemented with the configuration requested by the user. If they are not the same,
the Loader reports the differences. This feature allows the
BCP microcode to determine valid configurations.
The Loader Configuration Options are discussed here.
Where applicable, these options can be combined to create
a customized configuration for the interface mode. Once
again, for convenience the ,Loader notation is repeated:

LD MPA2 -R=OOOO, 0126 -U=CC
In this example, the Loader soft-loads code through dual
port memory mapped at the PC memory address CCOOO,
from the BCX format file MPA2.BCX, starting at instruction
memory OOOOh. The Loader then sets the program counter
to 0126h and starts the BCP.
Configuring The MPA~II
The Loader configures the MPA-II terminal emulation interface mode as requested by the user through the Configuration Options. Configuring the MPA-II interface mode enables
the MPA-II to emulate the standard PC terminal emulation
interfaces including DCA's IRMA and Smart Alec interface
modes; and IBM's 3270 CUT and OFT interface modes. In
addition, the MPA-II extends the DCA and IBM 3270 modes
to support single session 3299. (Multi-session 3299 support

LD[Config_options ••• ] [Options ••• ]

I I I I I I I I I'

POR SYSTEM (0 INDICATES THAT THE POR IS COMPLETE)
RESERVED
3299 MODE
COAX EAB INSTALLED
MPA COMMAND (0 INDICATES COMMAND EXECUTION COMPLETE)
IBM INTERFACE MODE
DCA INTERFACE MODE
5250/3270
TL/F/10488-46

FIGURE 7-2. MPA-II Configuration Register

2-74

Conflg_options:

the correct version of microcode), the Loader will automatically load the BCP microcode and configure the MPA-II as
requested.

-C-The Loader clears the 5250/3270 bit of the MPA-II
Configuration Register. This selects a 3270 Coax-Twisted
Pair terminal emulation interface mode for the MPA-II interface.

The autoload function is useful when the Loader is used in a
batch file such as the AUTOEXEC.BAT file. If the PC is rebooted then the Loader will not destroy an ongoing terminal
emulation session. In addition, the error levels returned by
the Loader may be used to skip loading of the PC terminal
emulator if the MPA-II board is not present. The following is
an example of how to use the autoload function to implement the IRMA interface mode in a batch file:

-0-The Loader sets the DCA Interface Mode bit of the
MPA-II Configuration Register. This selects a DCA terminal
emulation interface mode for the MPA-II interface. The
5250/3270 bit of the MPA-II Configuration Register is used
to determine which DCA Interface mode, IRMA or Alec, is
actually set.

LD MPA2.BCX -M=IRMA -A
IF ERRORLEVEL 8 GOTO SKIPIRMA
E78 /R
:SKIPIRMA

-E-The Loader sets the EAB bit of the MPA-II Configuration Register. This selects the Coax Extended Attribute Buffer.
-I-The Loader sets the IBM Interface Mode bit of the
MPA-II Configuration Register. This selects the IBM 3270
terminal emulation interface mode for the MPA-II interface.

MPA-II Diagnostics
The Loader can run diagnostics to test the functionality of
the MPA-II hardware. These diagnostics are implemented
with the Loader and the BCP microcode; MPADIAG.BCX,
provided in MPA-II Design/Evaluation Kit. Note, the Loader
expects the file MPADIAG.BCX to be located in the same
directory as the file LD.EXE.

-T-The Loader set the 5250/3270 bit of the MPA-II Configuration Register. This selects a 5250 Twinax terminal emulation interface mode for the MPA-II interface.

-Xl =] -The Loader sets the 3299,

mux, bit of the
MPA-II Configuration Register. This selects 3299 coax
mode for the MPA-II interface. A decimal muX address is
required, and is passed to the MPA-II through the MPA-II
parm/response register, 2DBh, which is written prior to the
configuration being set, but after the BCP's CPU is started.

Figure 7-3, The MPA-II DiagnostiCS Flow Chart, provides a
good overview of the extent of testing performed by the
MPA-II diagnostics. For the actual implementation of these
tests, refer to the source code, which is well documented.
The first four diagnostic tests do not require BCP microcode. These diagnostics include testing RIC, the BCP's Program Counter, dual port memory, and instruction memory. In
all of these diagnostics, the Loader writes patterns to the
device under test, and expects to read the pattern back
from the device under test.

-Z-The Loader does not set the MPA-II Configuration Register. This option provides the flexibility to use the Loader to
load microcode other than the MPA-II microcode.
-M[ =] -This option allows for automatic configuration of the standard terminal emulation modes, i.e.,: DCA's
IRMA, DCA's Smart Alec and IBM's interface modes. Valid
MODE options are IRMA, IBM, and ALEC. These modes set
the MPA-II Configuration Register as follows: When the
mode is ALEC, the Loader sets the 5250/3270 bit and the
DCA Interface Mode bit in the MPA-II Configuration Register. For IBM mode, the Loader clears the 5250/3270 bit and
sets the IBM Interface Mode bit. For IRMA mode, the Loader clears the 5250/3270 bit, sets the DCA Interface bit and
the Coax EAB bit. This option also allows a hex value to be
entered directly into the MPA-II Configuration Register with
the < MODE> = CONFIG [ = ] < config > , where config is the
hex byte value to be loaded into the MPA-II Configuration
Register. The Loader defaults to configure the MPA-II interface mode for IRMA.

If all these initial tests pass, then the BCP microcode,
MPA-DIAG.BCX is soft-loaded into instruction memory and
the BCP is started. The Loader maintains ultimate control
over the diagnostics. This is accomplished through a handshaking protocol in which dual port memory is used to pass
codes to and from the Loader program and the BCP microcode program, MPADIAG.BCX. The Loader passes a start
code through dual port memory. The BCP microcode polls
dual port memory until it receives the start code. Once the
BCP microcode recognizes the start code, it executes the
next test in sequence. Each diagnostic test that the BCP
microcode executes writes codes into dual port memory to
indicate both the completion of the test and if the test
passed or failed. When appropriate, the BCP microcode
also indicates the failure mechanism. The BCP microcode
then polls dual port memory for the start code of the next
test. After the Loader writes a start code to dual port memory, it polls dual port memory for the code from the BCP
microcode indicating completion of the test. If the completion code is not received within a predefined time limit, the
Loader indicates a failure. If the completion code is received, the Loader then checks dual port memory to determine if the test passed or failed.

As an example of how to use the configuration options, lets
assume that the IRMA interface mode is required along with
coax 3299 support using the 3299 station address 3. The
following command lines all perform this task using the Configuration Options discussed above:

LD MPA2.BCX -M=IRMA -X=3
LD MPA2.BCX -C -D -E -X=3
For further flexibility, the Loader also provides an autoload
option, -a, to configure the MPA-II on the fly. The autoload
function is actually a "smart hotswitch", allowing the user to
change the MPA-lI's configuration without necessarily reloading BCP microcode. The autoload is "smart" in that the
Loader verifies that the MPA-II is "alive" before it changes
configurations. If the MPA-II is not alive (i.e., running with

Either of the two Loader Options, -s or -I, cause the Loader
to implement the MPA-II diagnostics. For convenience the
Loader notation is repeated and the options which apply to
the MPA-II diagnostics are discussed here:

LD[Config_options ••• ] [Options ••• ]

2-75

•

Options:
-S[=][count[,lrq#]]- Selftest option of the Loader. Cycles through the MPA-II Diagnostics count (default
count= 1) times. The irq# refers to the PC IRQ interrupt
level to be tested. irq#=2 (default) tests the PC IRQ2
interrupt (Le., jumper JP6 connected). irq#3 tests the PC
. IRQ3 interrupt (Le., jumper JP4 connected). irq# =4 tests
the PC IRQ4 interrupt (Le., jumper JP5 connected).
-L-In addition to the selftest, the BCP's transceiver is tested by implementing an external Loopback feature. In
loopback, the BCP's receiver and transmitter are allowed
to be active at the same time. This allows the BCP to test
the external transmitter and receiver logic on the

MPA-II board. This test should not be performed when
the MPA-II is connected to a controller as it may cause
the controller to detect line errors.
The following examples demonstrate using the Loader options to implement the MPA-II diagnostics:
LD -S=3, 4 Cycles through the MPA-II diagnostics three
times (the external loopback test is not performed), the PC IRQ interrupt level 4 is tested.
LD-L-S
Cycles through the MPA-II diagnostics one
time, the loopback test is performed, and PC
IRQ interrupt level 2 is tested.

TLlF/10488-47

FIGURE 7·3. MPA·II Diagnostics Flow Chart
2-76

APPENDIX A

0')
~

.....

HARDWARE REFERENCE

MPAII_AC - U3·
V3.02
auxillary control register

Provides line interface logic, including the coax and
twinax TX_ACT signals as well as the ex-or of /DATA_OUT and
DATA_DLY for the twinax logic.
AD6 -> COAX
(if AD6 10, COAX enabled)
IRQ output to pc is registered output of AD7 in this pal.
If
the BCP puts a 1 to AD7 during a write to this register, the
PC interrupt will be asserted.
The interrupt is cleared by
a BCP write with AD7 = O.

history:VO.1
VO.2
VO.3
VO.4
Vl.O
V3.00
V3.01

rosa
msa
rosa
msa
msa
wvm
wvm

12/13/87
12/16/87
12/31/87
02/27/88
04/07/88
08/10/88
09/07/89

V3.02

wvm

09/11/89

create
Abel version
added IRQ
u9 -> u4
u4 -> aux_ctl
eliminated manual reset
make signal names match
schematic and add test vectors
add BIRQ_EN function

INC. 1987,1988,1989,1990

module mpaii_aux_ctl
title 'data register'
"declarations
TX_ACT
DATA_DLY
DATA_OUT
ADS
BCP_RSTPC_RST
AD6
AD7

COAX_ACT
TWX_ACT
act_swtch
not_used1
BIRQ_EN
IRQ
INTENSE
IRSTH,L,C,Z,X
outputs
r_outputs

mpaii_ac
pin
9;
pin
8;
pin
7;
pin
6;
pin
5;
pin
4;
pin
3;
pin
2;
pin
pin

11;
1;

pin
pin
pin
pin
pin
pin
pin
pin

19;
18;
17;
16;
15;
14;
13;
12;

device 'P16R4';

1,0, .C., .Z., .X.;
(COAX_ACT,TWX_ACT,INTENSE,IRST-);
(act_swtch,not_used1,BIRQ_EN,IRQ);

TL/F/l0488-48

2-77

,...
~

CD
I

u9a
u9a -> ctl_tim
fixed DATA_G- bus contention
(REMRD- -> REMWR-)
made revisions for MFAII:
1) eliminated unused chip
selects
2) removed bcp_rst, it was an
unused signal input
3) moved the pc_rdy signal to
MFA II_R I
4) added PRE_BIRO decode
5) added A13 and A14 decodes
for remote accesses
make signal names match
schematic and add test vectors
change name of DATA_CBA to
DATA_CAB and corrected equation
to use XACK instead of BCP_RD.
replace IODO with IBM_REG-,
simplified PRE_BIRO, and modified
out_A13 and out_A14 to include
IBM_REG-

module mpaii_ctl_tim
title 'PC iface - data control'
"declarations
device 'P20L10'j

mpaii_ct
XACK
REMRDREMWRIBM_REGRAE-

IO_ACCESSBCP RDBCP _WRLCLAlS,A14,A13

pin
pin
pin
pin
pin
pin
pin
pin
pin
pin

1;
2;
3;
4;

5;
7;
10;
11;
13;
9,6,8;
TL/F/l0488-50

2-79

•

~
~

r-----------------------------------------------------------------------------------------------,

Z
<

pin
pin
pin
pin
pin
pin
pin
pin
pin
pin

DMEM_CSAREG_OCAREG_CLKout_A13
DATA_DIRDATA_CABDATA_Gout.;..A14
DREG_CLKPRE_BIRQ
H,L,Z,X
a_dec
outputs

oS:

14:
23:

15;
16;
17;
18;
19;

20:
21;
22;

1,0, .Z., .X.:
[A15 .. A13);
[DMEM_CS-,AREG..;..OC-,AREG_CLK-:-,DREG_CLK-,
DATA_DIR-,DATA_CAB-,DATA_G-,PRE_BIRQ);
[out_A14,out_A13);

equations
!DMEM_CS- .. LCL- t (!A15 & !LCL-);
lAREG_CLK- ... lIO_ACCESS-& LCL- & !BCP_WR-:
!AREG_CLK!LCL- & !BCP_WR- & (a_dec
~blOO);
!AREG_OC- c: !BCP_RD- &,lLCL- & (a_dec c: .. ~blOO);
out_A13
out_A14

.. lIO_ACCESS- t lIBM_REG-;
a
lIO_ACCESS- t !IBM_REG-;

lDATA_GlDATA_CAB":'
DATA_DIRenable outputs
enable bcp_oc

" pc access to set
" bcp access to clear

(! REMWR- & oLCL-) t

(l RAE- & 1REMRD-) :

... ! REMRD- & ,! XACK & LCL-;

"Abus -> Bbus if rem_read cycle

lREMRD- & lRAE-:

~blllllll11;

LCL-:

TL/F/10488-51

2-80

V3.03
Upper PC address buffer and I/O decode

..
..
..
..
..
..

This PAL decodes the PC address lines A12-A4,PC_A19_16 ,PC_A16_14 and
IOACCESS-, REMRD- to provide the BCP A1S, A12-8 outputs and the
two partial decodes IBM, DCA indicating which system (IBM, or DCA)
is being accessed. Note that this scheme will not allow the MFAII board
to co-exist w/ any board using these PC I/O addresses. A1S, A12-8
are enabled by LCL- going high, indicating a remote access cycle .

..
..
"
"

If IOACCESS- and LCL- are as~erted, A12-8 are driven high to translate
the PC I/O access to the top page of the BCP's data RAM (7FFX - unless
it is a read of IRMA space, which is translated to 7FEX,) required to
emulate the dual-ported registers used on this board .

.. If the PC accesses the BCP's data memory, LCL- will be asserted but not
\\ IOACCESS-, in which case no translation will occur, and A12-8 will only
\\ be buffered onto the BCP's address lines.
IBM_REG- DCA_REG1
1
0
1
1
0
0
0

-type of decodenot an MFAII 10 decode
DCA 10 access (addresses 0022x)
IBM 10 access (addresses 002dx)
not an MFAII 10 decode

wvrn

12/13/87
12/16/87 Abel
12/17/87
02/27/88
03/03/88
03/12/88
04/07/88
08/10/89

V3.01

wvrn

09/07/89

V3.02
V3.03

wvrn
tas

09/11/89
10/25/89

history:VO.1
VO.2
VO.3·
VO.4
VO.5
VO.6
VI. 0
V3.00

msa
rosa

tjq
msa
rosa
rosa
rosa

create
version
simulate
u3 -> u23
corrected address pin nums
edits for TN's irma code
u23 -> pad_ dec
made revisions for MFAII:
1) moved REMOTE decode to an
inverter
2) moved A13 and A14 decodes
for remote accesses to
MFAII_CT
3) include decode of PC_A14
through PC_A19 in 1000
and 1001
make signal names match
schematic and add test vectors
rearrange pins
renamed 1000 and 1001 to DCA_REGand IBM_REG-,respectively. Swapped
1000/1 pins. Added IBM_REG- to
A12-A8.

INC. 1987,1988,1989,1990

module mpaii-pad_dec
title 'PC iface - i/o decode'
TlIF/10488-52

2-81

0III::t
CD

r-----------------------------------------------------------------------------------------------.
"declarations
mpaii-pddevice 'P20L10';
PC_A12,PC_A11,PC A10
PC_A9,PC_AS,PC_A7
PC_A6, PC_AS, PC_A4
PC_A14 16
PC_A17 19

pin
pin
pin
pin
pin

1,3,4;
S, 6, S;
9,10,11;
lS;
16 ;

REMRDIO_ACCESSLCL-

pin
pin
pin

2;
7;
13;

A1S
A12, All
A10, A9, AS

pin
pin
pin

14;
17,lS;
19,20,23;

IBM_REG-,DCA_REG-

21,22;

H, L, X, Z '"

low
pc a
pc_abuf
bcp_oc
bcp_a
io_dec

1,0, .X., .Z.;
"bll;
[PC_A12 .. PC_M];
[PC_A12 .. PC_AS];
[A12 .. AS];
[A12 .. AS];
[IBM_REG-,DCA_REG-];

equations
!IBM_REG!DCA_REG-

"h02d) & PC_A14_16 & PC_A17_19;
"h022) & PC_A14_16 & PC_A17_19;

A15

A12
All
AIO
AS

PC_A12
PC_All
PC_AI 0
PC_A9
PC_AS

enable iO_dec
enable bcp_oc
enable A1S

low;
LCL-;
LCL-;

f
f
f
f
f

!IO_ACCESS- f
!IO_ACCESS- f
!IO_ACCESS- f
!IO_ACCESS- f
(! IO_ACCESS-

!IBM_REG-;
!IBM_REG-;
! IBM_REG-;
!IBM_REG-;
& REMRD-)

! IBM_REG-;

TLlF/l0488-53

2-82

z
I

0')

.....

MPAII_RD - U7
V3. 04
PC I/O register decode

Decodes the low 4 bits of the PC address
data memory, RIC, and SREG.
All four PC
strobes as well as the IBM_REG-/DCA_REG-,
signals are inputs. /RAE, CM /MEM_CS and
and /SREG_EN are outputs.
history:VO.1
VO.2
VO.3
VO.4
VO.5
VO.6
VO.7
V1.0
V3.00

msa
msa

msa
msa
wvrn

12/13/87
12/16/87
12/17/87
12/17/87
12/31/87
02/27/88
03/12/88
04/07/88
08/10/89

V3.01

wvrn

09/7/89

v3.02
v3.03

wvrn
tas

09/11/89
10/19/89

V3.04

tas

10/25/89

rosa

msa
msa
rosa

lines to
read and
PC_A13,
/REM_RD,

determine enables for
write
PC_AEN, REM_enable and /MMATCH
/REM_WR, /IOACCESS

create
Abel version
added pc_clk edit
to 2018
added bcp reset input
u4 -> u8
edited for tn's irma
u8 -> reg_dec
revisions made to MPAII:
1) eliminate PC_HI_OC and
PC_LO_OC
2) remove IO_MAYBE and replace
it with PC_AEN
3) input PC_A13 for address
decodes
4) input REM_enable to control
accesses during rest-time
5) Make RAE- a full decode of
every access
make signal names match
schematic and add test vectors
rearrange pin assignments
aaded PC_AEN to SREG_EN to
eliminate accidental clock of SREG.
Rename 1000, 1001 to DCA REG-,
IBM_REG-, repectively.' Swap 1000, 1001 pins. Changed
la_ACCESS to avoid SREG.

INC. 1987,1988,1989,1990

module mpaii_reg_dec
title 'PC iface - i/o decode'
"declarations
mpaii_ rd
BCP RSTDCA REGPC_AEN
IBM REGPC A3,PC A2
PC A1,PC AD
PC_MEMRPC_MEMWPC IOR-

pin
pin
pin
pin
pin
pin
pin
pin
pin

device 'P20LB';

1;
2;
3;
4;
5,6;
7, B;

9;
10;
11;
TL/F/10466-54

2-83

•

.....
~

Z•

PC_IOWBCP_WRPC_A 13
REM_enable
MMATCH-

pin
pin
pin
pin
pin

13;
14;
16;
17;
23;

RAE-

CMD
IO_ACCESSSREG_EN-

pin
pin
pin
pin
pin
pin

22;
21;
20;
19;
18;
15;

CMD

ISTYPE

'feedyin' ;

REMRDREMWR-

H,L,X,Z

pc a
pc_hi
pc_lo
iO_dec
no_acc
dca_acc =
ibm_acc =
strobes =
outputs c

equations
lRAE-

1,0, .X., .Z.;
[PC_A3 .. PC_AD];
(pc_a -- "blllO);
(pc_a -- "bl101);
[IBM_REG-,DCA_REG-];
(io_dec -- "b11):
(io_dec c = "b10);
(io_dec == "b01);
[PC_MEMR-,PC_IOR-,PC_MEMW-,PC_IOW-];
[CMD, RAE- , REMWR- , REMRD- ,
IO_ACCESS-,SREG_EN-];

«lPC_IOR- f lPC_IOW-) & lno_acc& lPC_AEN& lPC_A13)
f (!MMATCH- & lPC_AEN & (!PC_MEMW- t !PC_MEMR-));

CMD
!REMRD-

!PC_IOR- & REM enable
t !PC_MEMR- & REM_enable:

!REMWR- =

!PC_IOW- & REM_enable
f !PC_MEMW- & REM_enable;
(!PC_IOW-) & (pc_a c = "b0111)&(ibm_acc)&(!PC_A13)&!BCP_WR~
&!PC_AEN f !BCP_RST-;

!IO_ACCESS-= lDCA_REG- & lCMD & lPC_A13 & lPC_AEN & (lPC_IOW- • !PC_IOR~)
• !IBM_REG- & !CMD & !PC_A13 & !PC_AEN & !PC_IOR• !IBM_REG- & !CMD & !PC_A13 & lPC_AEN & !PC_IOW- &
(!PC_AOf !PC_Al • !PC_A2):
" IO_ACCESS- is active if:
1) it's an IRMA register read or write
2) it's an IBM register read
3) it's an IBM register write except to xxx7 or xxxF.
xxx7 = Segment Register (U16)
xxxF
the BCP's RIC register
enable outputs =

"bll1l11 :

TL/F/l0488-55

2-84

V3.02
birq register and rest-time circuit

This PAL sends the BIRO interrupt to the BCP whenever a
IBM, IRMA or SMART_ALEC I/O access is made. The BIRO
interrupt is cleared when the BIRO register is read by
the BCP.
This PAL also contains all of the rest-time 'state machine
needed to pevent missed or inproper accesses.
The signal
REM_enable is fed back to MPAII_RD and prevents remote accesses
during rest-time.
The PC_RDY signal to the PC bus is also
controlled by XACK from the BCP and the rest-time state
machine.
history:V3.00
V3.01

wvm
wvm

08/10/89
09/07/89

V3.02
V3.02

wvm

tas

09/11/89
01/03/90

create
make signal names match
schematic
change BIRO decode
corrected some test vectors

module remote_interface-pal
title 'REST-TIME Compliance State Machine':
MPAII RI device

'P16RA8':

"inputs
PLXACK
CLK_OUT
BCP rst-

RAE-

unused_ 1
BIRO_EN
AREG_CLKPRE_BIRO
OE-

pin
pin
pin
pin
pin
pin
pin
pin
pin
pin

11:

pin
pin
pin
pin
pin
pin
pin
pin

19:
18:
17:
16:
15:
14:
13:
12:

1:
2:

3:
4:
5:
6;
7;
8;
9:

"outputs
PC_RDY-

qO
q1
q2
q3
wait_start
REM_enable
BIRO

"definitions
x,z,L,H

.x., . z., 0, 1:
TL/F/l0488-56

2-85

•

,..
'III:t

equations
enable PC_RDY-

'" (!RAE-);

PC_RDY- .RE
PC_RDY-.PR

., 1;
., 1;
:= (!XACK
I qO & !RAEI !q2 & !RAEI q3 & !RAE-);

REM_enable.RE
REM_enable .PR

= 1;

., 1;

:- wait_start
!q3 & q2 & q1 ,

I RAE- ,

q3.PR
q3.C
!q3

'" !BCP_rst-;
.. CLK_OUT;
: .. (! qO &

I
I
f

q2.RE
q2.C

! q2
!qO & !ql ,
!qO , !q3 ,
!qO , !ql &

, ! q3
!RAE!RAE- & !wait_start
q2);

- !BCP_rst-;
.. CLK_OUT;

!q2

:- (!qO , !ql & !q2 & !q3
I !ql , q3 & !RAEI ql & !q2 , q3
I qO & !ql , q3);

ql.PR
q1.C

"" !BCP_rst-;

!ql

!qO;

.. CLK_OUT;

:.. (! qO

! ql

I !qO & !q2 & q3
I qO & q2 & q3
I !qO & !ql & q2 , RAE-);

qO .PR
qO.C

.. !BCP_rst-i

!qO

:= (!qO & !ql
f !qO & !q2

., CLK_OUT;

TL/F/10488-S7

2-86

I BIRQ & ql & !q2 & q3
I !qO & !q3);

wait_start.PR
wait_start.C

q3 & !q2 & !ql & !qO;
RAE- & BCP_rst-;
!q3 & q2 & !ql & !qO;

BIRQ.RE
BIRQ.C

!BCP_rst-;
'"' AREG_CLK-;

!BIRQ

end rernote_interface-pal
TL/F/l0468-56

2-87

APPENDIX B

er than 60.5 ns (See Table B-1). Note that 55 ns Static
Rams will work for both full speed and half speed operation
of the MPA-II.

Timing Analysis
This section will first discuss the timing analysis used in seleting appropriate data memory and instruction memory for
use in the MPA-II system. Following this is a description of
the timing involved in interfacing the MPA-II system with the.

PC-XT/AT.
As discussed in Chapter 5-Hardware Architecture, the
BCP utilizes a Harvard Architecture, where the data memory
and instruction memory are organized into two independent
memory banks, each with their own address and data buses. The data memory is dual ported enabling both the BCP
and the remote processor to have access. The instruction
memory, on the other hand, is exclusively owned by the
BCP. Any remote processor accesses to this memory occur
through the BCP, and only when the BCP is idle.

TL/F/10488-59

FIGURE B-1. Instruction Memory Read Timing
TABLE B-1. Instruction Read Times, tl (ns)

The MPA-II system runs with the BCP operating at full'
speed, 18.8696 MHz ({ OCR [CCS] I = 0), with zero instruction (nIW) and one data (now) wait state resulting in a
T-state of 53 ns. For a system running the BCP at half
speed, 9.45 MHz ({ OCR [CCS] I = 1), with zero instruction
and zero data wait states, the T-state is 106 ns. The T-state
is calculated as shown:

Interfacing Memory to the DP8344B
As with most other aspects of a design, choosing memory is
a cost vs. performance trade off. Maximum performance is
achieved running no wait-states with fast, expensive memory. Slower, less expensive memory can be used, but waitstates must be added, slowing down the BCP. Therefore
one needs to choose the slowest memory possible while
still meeting design specifications. While this appendix assumes RAM is used for instruction and data memory, the
information is relevant to memory devices in general.

9.43
18.86
20.00

140
60.5
56

246
115.5
106

352,
166.5
156

458
219.5
206

Walt States nlw

tos = (nlW

+ 1)T -

18 ns

and the write pulse width tlW (parameter 20) is:

Instruction Memory Timing

tlW = (nlW

The BCP needs separate data and instruction RAM, each
with their own requirements. Instruction read time is the major constraint when choosing instruction RAM. Instruction
read time tl, as shown in Figure B-1, is measured from when
the instruction address becomes valid to when the next instruction is latched into the BCP. Instruction read time for
various clock frequencies and wait states are given in Table
B-1. Clock frequency and wait state combinations other
than those given in the table can be calculated using parameter 1 in Table 5-5, Instruction Memory Read Timing, of the
OP8344B data sheet:

However, instruction read time is not the only timing consideration when choosing instruction RAM. If the BCP is used
in an application which requires full speed softloading of
instruction RAM, there are two other timing relationships
which require evaluation. These are data setup time and
write pulse width (see Figure B-2). The relevant BCP timing
parameters are I valid before IWR rising, tos, and IWR low
time, tiW. The value of these timing parameters depends on
the Remote Interface mode of operation, which is Fast Buffered Write for the MPA-II system. Using Table 5-22, Fast
Buffered Write of IMEM, of the OP8344B datasheet, the
data setup time (parameter 19) is:

T-state = 1I(CPU Clock Frequency)

tl = (1.5

CPU
Clock Freq.
(MHz)

+ 1)T -

10 ns

Table B-2a and B-2b give various data setup times and write
pulse widths. Once again, the RAM chosen must have a
faster RAM data setup time and quicker RAM write strobe
width than the corresponding desired data setup time and
write pulse width. Thus, for the MPA-II system, the selected
Instruction RAM data setup time must be less than 35 ns
(Table B-2a), and the RAM Write Strobe Width must be less
than 43 ns (Table B-2b). In a typical application of the BCP,
softloading occurs after reset with the BCP operating with
CLK/2 and full wait states. Under these conditions the instruction read time value is the critical parameter for choosing the instruction RAM. In the MPA-II system, softloading
can also occur under the full speed conditions. First, softloading occurs upon a first load of instruction memory into
the MPA-II on power up. The MPA-II system can then be
reloaded without powering down. In this situation, the
MPA-II system is set to full speed. Therefore, the RAM selected must meet all the parameters listed thus far.

nlW) T - 19 ns

where tl is the instruction read time (ns), nlW is the number
of instruction memory wait states, and T is the 7-state time
(ns). The RAM chosen needs to have a faster access time
than the read time for the desired combination of clock frequency and wait states. Since the MPA-II system runs at full
speed (18.8696 MHz) with nlW = 0, the RAM chosen for
instruction memory must have an access time which is fast-

2-88

________________________________--JI
v///~/I////li///////////////i///4

__________________________________-JI

~----------------------------~I
I

\'----------

)

}

_______________________________________c:=:

IWR

TL/F/10466-60

FIGURE B-2. Data Setup Time and Write Pulse Width for Fast Buffered Write of IMEM
signal (IWR) from the BCP. Table B-3 compares the selected instruction memory RAM parameters with required parameters for the DP8344B.

TABLE B-2a. Data Setup Times,
tos (ns) for Fast Buffered
Write of Instruction Memory
CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

88
35
32

194
88
82

300
141
132

406
194
182

Data Memory Timing

Walt States nlw

The MPA-/I system uses a 100 ns 32K x 8 CMOS Static
RAM to implement the system data memory.
The selection of data memory RAM requires the evaluation
of several important timing parameters. The RAM access
time, strobe width, and data setup times are three of the
most critical timing parameters and must all be matched to
equivalent BCP timing parameters. The RAM access time
should be compared to the data read time of the BCP.

TABLE B-2b. Write Pulse Width,
tlW (ns) for Fast Buffered
Write of Instruction Memory
CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

96
43
40

202
96
90

308
149
140

414
202
190

Data read time, to, (Figure 8-3) is measured from when the
data address is valid to when data from the RAM is latched
into the BCP. Table B-4 gives data read times. The equation
for calculating data read time is similar to the one given for
instruction read time, and is taken from Table 5-3 (Parameter 14) of the DP8344B data sheet:

Walt States nlw

to = (2.5 + MAX (now, nlW - 1»T - 40
where to is the data read time (ns), now is the number of
data memory wait states, nlw is the number of instruction
memory wait states, and T is the T-state time (ns). Since the
lower address byte (AD) is externally latched, the latch
propagation delay needs to be subtracted from the available
read time when determining the required RAM access time.

The MPA-/I uses two 55 ns 8K x 8 CMOS Static RAMs for
instruction memory. The output enable is tied low and the
chip select enables are both enabled. Therefore, the RAMs
are always selected. The write enable is the instruction write

•
2-89

T-

r-----------------------------------------------------------------------------------------~

TABLE B-3. Instruction Memory Read and Write Parameters

DP8344B BCP (Minimum)
Fujitsu RAM
(Minimum)
(55 ns)

Parameter

Read

55
40
25

Access Time (tl)
Write Pulse Width (tw)
Data Setup (tos)

Write

Full
Speed

Half
Speed

POR

60.5

140

458

Full
Speed

Half
Speed

POR

43
35

96
88

414
406

Measurements are in ns.
Full Speed is 53 ns T-state with nlw = 0 and now = 1.
Half Speed is 106 ns T-state with nlW

POR is 106 ns T-state with nlW

0 and now

3 and now

relationships for a data memory access are shown in Figure
8-3 for a read and in Figure 8-4 for a write. Table 8-5 contains READ and WRITE pulse width values for various clock
frequencies and wait state combinations. The equation for
calculating READ and WRITE pulse widths are taken from
parameter 8 of Table 5-4 and parameter 12 of Table 5-3 in
the DP83448 data sheet:

CLK-OUT~
I

===WWd/////~

:=:::x

x:::

ALE~
AD

ij/////////,

ADDR

tR = tw = (1 + MAX (now, nlW - 1»T - 10
where tw (= tR) is the pulse width (ns), now is the number
of data memory wait states and nlW is the number of instruction memory wait states. The RAM chosen should require shorter strobe widths than the pulse width listed in
Table 8-5 for the desired combination of clock frequency
and wait states. Thus, for the MPA-II system, the RAM
strobe width must be shorter than 96 ns.

)--~

A /'//////// / /.

READ

The last important consideration when choosing the data
memory RAM is setup times into the 8CP on a read and into
the RAM on a write. In a typical application, READ is connected to the output enable pin on the RAM. When reading
from the RAM, the data becomes valid when READ falls
and activates the RAM outputs. The data must become valid fast enough to meet the setup time required by the 8CP.
This setup time tSR, as shown in Figure 8-3, is listed in
Table 8-6 for various combinations of clock frequencies and
wait states. Using Table 5-3 (parameter 7) of the DP83448
datasheet, tSR can be calculated as follows:

TL/F/104BB-61

FIGURE B-3. Data Memory Read Timing
TABLE B-4. Data Read Time, to (n5)
Wait States
Max (now, nlW - 1)

CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

225
92.5
85

331
145.5
135

437
198.5
185

tSR = (1 + MAX(now, nlW - 1»T - 22
where tSR is the maximum time allowed for the data to become valid (ns), now is the number of data memory wait
states and nlW is the number of instruction memory wait
states. The data memory RAM used needs to have a faster
output enable time than the time listed in Table 8-6 for the
desired combination of clock frequency and wait states.

An octal latch (74ALS573) is used in the MPA-II system to
demultiplex and latch the address. There is a delay associated with latching of the address and it is dependant on the
latch considered. The latch' enable is the ALE signal from
the 8CP. While ALE is high, the outputs follow the inputs.
When ALE falls the address is latched on the outputs. The
latch has a propagation delay of 20 ns which corresponds to
the time it takes for the data on the inputs to reach the
outputs.

When writing to data memory, the data must be valid in time
to meet the setup time requirement of the RAM. In a typical
application, this time is measured from the data becoming
valid out of the 8CP to WRITE going high. Figure 8-4 shows
this timing relationship, tow, and Table 8-7 contains times
for various combinations of clock frequencies and wait
states. The equation for calculating this time is from Table
5-4 (parameter 4) of the DP83448 datasheet.

Therefore, for the MPA-II system the RAM access time is:
tacc = to - 20 ns
Using Table 8-4, the required RAM access time can be cal.
culated to be:

tow = (1 + MAX(now, nlW - 1»T - 20
where tow is the minimum data valid time before WRITE
rising (ns), now is the number of data memory wait states
and nlW is the number of instruction memory wait states.
This time should be at least as long as the data setup time
of the RAM.

tacc = 145.5 - 20 = 125.5 ns
for full speed operation with one wait state.
Another important timing parameter is the RAM strobe
width. The 8CP READ and WRITE outputs will typically be
used to strobe data out of and into the RAM. The signal

2-90

TABLE B·S. READ and WRITE Pulse Width, tR = tw (ns)

Table B-8 compares the BCP data memory requirements
with the selected data RAM.

Walt States
Max (now, nlW - 1)

CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

96
43
40

202
96
90

308
149
140

PC System
The MPA-II expansion board is an 8-bit board, which runs in
a PC-XT, PC-AT or compatible system. The timings of the
two systems have many differences, but the 8 MHz PC-AT
bus specifications are more stringent than those of the
4.77 MHz PC-XT bus. So, this evaluation will cover the
8 MHz PC-AT.

TABLE B·6. Data Read Setup Time, tSR (ns)

The critical timing in this system will be the amount of time
the MPA-II will have before it must deassert 10-CHRDY low
in order to extend the access cycle by adding wait states.
By deasserting 10CHRDY the MPA-II can extend a read or
write cycle until the correct data is available or written, respectively.

Wait States
Max (now, nlw - 1)

CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

84
31
28

190
84
78

296
137
128

As stated before, the MPA-II is an 8-bit board so both the
1/0 and memory cycles will have 8-bit access cycles. In the
PC-AT, 8-bit 1/0 and memory cycles have the exact same
timing. There is always one command delay (0.5 T-states)
from the time ALE falls until the command strobe (lOR,
lOW, MEMR or MEMW) goes active low. Four programmed
wait states are inserted, forcing the command strobe to stay
active low for a minimum of 4.5 T-states. Figure 8-5 shows
the relationship between ALE, the command strobes and
the bus cycles T-states.

TABLE B·7. Data Write Valid Time, tow (ns)
Wait States
Max (now, nlw - 1)

CPU
Clock Freq.
(MHz)

9.43
18.86
20.00

86
33
30

192
86
80

278
139
130

For the following calculations the original IBM PC-AT schematic has been used. This schematic can be found in IBM
Technical Reference Personal Computer AT.

Instruction RAM has the greatest affect on execution speed.
Each added instruction memory wait state slows the BCP by
about 40% as compared to running with no instruction
memory wait states. Each added data memory wait state
slows a data access by 33% as compared to running with
no data memory wait states. RAM costs are coming down,
but higher speed RAM still carries a price premium. So there
is the trade-off.

In the PC-AT, both ALE and all of the command strobes are
controlled by an 82288 bus controller. The command
strobes will go active a short delay time after the 82288
inserts the command delay. (The delay time for an 8 MHz
82288 is T (delay 82288) = 25 ns.) After leaving the 82288,
MEMR and MEMW pass through a 74ALS244 before reaching the expansion bus.

TABLE B·8. Data Memory Read and Write Parameters
Hitachi
HM62256
RAM
(Minimum)

Parameter

100
60
40

Access Time (tace>
Write Pulse Width (tw)
Data Setup (tDW)
Output Enable (tSA)

DP8344B BCP (Minimum)
Read

Write

Full
Speed

Half
Speed

125.5

205

Full
Speed

Half
Speed

96
86

Measurements are in ns.
Full Speed is 53 ns T·state with nlw

= 0 and nDW = 1.

Half Speed is 106 ns T-state with nlw = 0 and nDW

IALE

FIRST
SECOND
THIRD
FOURTH
STATUS
COMMAND
PROGRAMMED
PROGRAMMED
PROGRAMMED
PROGRAMMED
STATE ---I- STATE - I - WAIT --I- WAIT --I--- WAIT --I- WAIT-STATE
STATE
STATE
STATE

~~~--~~--+-~--~

CMD

TLlF/l04BB-63

FIGURE B·S. Relationship of ALE, CMD, and Bus Timing

2-91

So, T(delay 82288) + T(delay 74ALS244) is equal to the
maximum amount of time from the end of the command
delay until the command strobe reach the MPA-II.
T(strobes valid) = T(delay 82288)
= 25 ns + 10 ns
= 35 ns

As a final note, the reader should be aware that most faster
PC-AT's still run their expansion buses at 8 MHz to remain
compatible. This means that the timing on these expansion
buses should remain the same as those on any other PC-AT
no matter how fast the CPU runs. Thus, the MPA-II will run
in all PC-AT's with 8 MHz expansion buses that follow the
original 8 MHz PC-AT's expansion bus design. In fact, as
can be seen above, the MPA-II will run with bus speeds
faster than 8 MHz.

T(delay 74ALS244)

In order to add wait states any expansion board must deassert 10CHRDY low in time for it to propagate through a
74ALS32, then through a 74F74 (from preset to output), and
then setup to the 82284 by the end of the third programmed
wait state (which is also the beginning of the fourth wait
state). If the 10CHRDY signal also meets the 82284's hold
requirement, then a fifth wait state will be added. Then
again, at the end of the fourth wait state if 10CHRDY is still
deasserted low a sixth wait state will be added. This will
continue until 10CHRDY is asserted high. On the other
hand, if 10CHRDY is deasserted too late (Le. after the end
of the third programmed wait state), then the cycle will end
without adding any additional wait states.

APPENDlXC
Filter Equations
Derivation of Filter
Equations for the Combined
Coax/Twisted Pair Interface

The basic operation of the filter can be understood by studying the figure below. The actual circuit includes the effects
of the terminating resistors, DC isolation capacitors, and the
transformer; furthermore, a thorough investigation of bandwidth and gain characteristics should employ the use of a
circuit simulator such as SPICE.

The following is a calculation of the minimum amount of
time before the end of the third wait state that 10CHRDY
must be deasserted to add wait states:
T(add wait) = T(delay 74ALS32 H-L)
T(setup 82284)
= 12 ns

25 ns

T(74F74 P-Q)

0 ns

37 ns
The maximum amount of time an expansion board has before it must deassert 10CHRDY (to add wait states) from the
command strobe being valid is:

TL/F/10488-64

T(Max 10CHRDY) = 3.5T - T(st'robes) - T(add wait)

Simple loop analysis yields the following transfer function
for the filter:

where, T = 125 ns in a 8 MHz expansion bus. Therefore,
T(MAX 10CHRDY = 3.5 (125 ns) - 35 ns - 37 ns
= 365.5 ns

2_R.!:.2C....!2:.....(S_)_~----

Vo = _ _-=-____
Vs
s2 +s [ R1C1 + C2 (4R2 + 2R1)] + - -1- 2R1R2C1C2
R1 R2C1C2
If it is assumed R1 > > R2 and C1 > > C2, we can then
simplify the equation and solve for the poles to obtain the
following form:

This means that the MPA-II has 365.5 ns to deassert
10CHRDY (if wait states are needed) from the time it receives a valid remote access command strobe.
On the MPA-II, the command strobes are buffered by a
20L8B PAL tothe BCP's REM-RD and REM-WR inputs. The
BCP will respond to a valid remote access by deasserting
XACK a delay time after receiving a valid remote access
REM-RD or REM-WR strobe. XACK controls 10CHRDY via
a 16RA8 PAL.

III

41T

The maximum delay from receiving a valid remote access
command strobe to deasserting 10CHRDY follows:
T(MPA-IIIOCHRDY) = T(delay 20L8B) + T(XACK) 1 +
T(delay 16RA8)
= 15 ns

26 ns

~ ~ ± ~~ -4 (R,R;C,C,)

After splitting the above equation to solve each pole and
using a binomial expansion to simplify each pole's equation,
we get:

35 ns

1
fl::::: --::::: 20kHz
1TR1C1
(vs. 30 kHz from simulation and testing)

= 76 ns

The MPA-II will deassert 10CHRDY a maximum of 76 ns
after it receives a valid remote access command strobe.
One should notice 76 ns is much less than the maximum
allowable time of 365.5 ns.

fh::::: ---::::: 40 MHz
41TR2C2
(vs. 30 MHz from simulation and testing)

2-92

Microsystem Components Handbook-Volume I (230843·
002), Intel Corporation, Literature Department, 3065.Bowers
Avenue, Santa Clara, CA 95051.

APPENDIX D

References
DP8344B Biphase Communcations Processor Data Sheet,
National Semiconductor, 2900 Semiconductor Drive, P.O.
Box 58090, M/S 16·197, Santa Clara, CA 95052·8090, Ver·
sion 4.2.
DP8344 Biphase Communcations Processor Assembler
User Manual (DP8344BSM·M5) National Semiconductor,
2900 Semiconductor Drive, P.O. Box 58090, Santa Clara,
CA 95052·8090, February 1988.
DP8344 Biphase Communications Processor Application
Notes, National Semiconductor, 2900 Semiconductor Drive,
P.O. Box 58090, Santa Clara, CA. 95052·8090.
IBM PC 3270 Emulation Program Entry Level Version 1.10
(84X0280), International Business Machines Corporation,
Department 52Q, Neighborhood Read, Kingston, NY 12401,
1981.
IRMATM User's Manual (40·97910·001), Digital Communica·
tions Associates, Inc., 1000 Alderman Drive, Alpharetta, GA,
30201.
Smart Alec™ User's Guide (40·98100·007), Digital Com·
muncations Associates, Inc., 1000 Alderman Drive, Alphar·
etta, GA 30201.
Guide to Operations Personal Computer AT (1502241), In·
ternational Business Machines Corporation, P.O. Box
1328·C, Boca Raton, FL 33432, 1984.
Guide to Operations Personal Computer XT (6936810), In·
ternational Business Machines Corporation, P.O. Box
1328·C, Boca Raton, FL 33432, 1983.
IBM 3270 Connection Technical Reference (GA23·0339·
02), Information Development, Department 802, P.O. Box
12195, Research Triangle Park, NC 27709, 1988.
IBM 3174/3274 Control Unit to Device Product Attachment
Information, International Business Machines Corporation,
Armonk, NY 10504, October 1986.
IBM 3274 Control Unit to Distributed Function Device Prod·
uct Attachment Information, International Business Ma·
chines Corporation, Armonk, NY 10504, June 1985.
5250 Information Display System to System/36, System/
38, and Applications System/400, System Units Pr~duct At·
tachment Information, International Business Machines Cor·
poration, Armonk, NY 10504, October 1988.
Technical Reference Personal Computer A T (502243), In·
ternational Business Machines Corporation, P.O. Box
1328·C, Boca Raton, FL 33432, 1984.
Technical Reference Personal Computer XT (6936808), In·
ternational Business Machines Corporation, P.O. Box
1328·C, Boca Raton, FL 33432, 1983.
abe/TM(880004), Data I/O Corporation, 10525 Willows Road
NE, P.O. Box 97046, Redmond, WA 93073·9746,1988.
BRIEFTM User's Guide, Underware, Inc., 84 Gainborough
St., Suite 103W, Boston, MA 02115, June 1987.
BSID, Capstone Technology, 47354 Fremont Blvd., Fre·
mont, CA 94538.
DP8344 BCP Demonstration/Development Kit, Capstone
Technology, 47354 Fremont Blvd., Fremont, CA 94538.

8088 Microprocessor Data Sheet
8288 Bus Controller Data Sheet
80286 Microprocessor Data Sheet
82288 Bus Controller Data Sheet
8284 Clock Generator and Driver Data ,Sheet

iAPX 86/88, 186/188 User's Manual Hardware Reference
1985 (210912·001), Intel Corporation, Literatur~ Distribu·
tion, Mail Stop SC6·714, 3065 Bowers Avenue, Santa Clara,
CA 95051.
iAPX286 Hardware Reference Manual 1983 (210760·001),
Intel Corporation, Literature Department, 3065 Bowers Ave·
nue, Santa Clara, CA 95051.
S/LS/TTI Logic Data Book (1985-400050), National Semi·
conductor, 2900 Semiconductor Drive, Santa Clara, CA
95051.

Contacts
For further information on the MPA·II or the DP8344 BCP
contact:
BCP Product Marketing
National Semiconductor
2900 Semiconductor Drive
Mail Stop: D3800
Santa Clara, CA 95052·8090
Phone: (408) 721·5000
For Technical Information on the MPA·II or the DP8344 BCP
contact:
DATACOM Applications Support
National Semiconductor
1111 W. Bardin Road
Mail Stop: A2190
Arlington, TX 76017
Phone: (817) 468·6676
Fax: (817) 468·1468
For requesting IBM Product Attachment Information manu·
als (PAl's) contact:
Industry Relations Dept.
IBM
2000 Purchase Street
Purchase, New York 10577
Phone: (914) 697·7227
For ordering IBM manuals other than PAl's contact your
local IBM Sales Office.
For ordering products from Azure Technologies contact:
Azure Technologies, Inc.
38 Pond Street
Franklin Massachusetts 02038
Phone: (508) 520·3800
Fax: (508) 528·4518
For ordering products from Capstone Technology contact:
Richard L. Drolet
Capstone Technology
47354 Fremont Blvd.
Fremont, CA 94538
Phone: (510) 438·3500

II
I

2·93

r-------------------------------------------------------------------------------------~

For ordering products from Hewlett Packard contact your
local Hewlett Packard Sales Office:

For ordering products from Relay Communications, such as
Relay Gold, contact:
Relay Communications, Inc.
41 Kenosia Avenue
Danbury, CT 06810
Phone: (800) 222-8672

For ordering products from DCA contact:
Digital Communications Associates, Inc.
1000 Alderman Drive
Alpharetta, Georgia 30201
Phone: (404) 740-0300
For ordering products from Simware, such as SimPC Master, contact:

For ordering products from Fischer International Systems,
such as Xeus, contact:

Simware, Inc.
20 Colonnade Road
Ottawa, Ontario
Canada K2E 7M6
Phone: (613) 727-1779
Fax: (613) 727-9409

2-94

Fischer International Systems Corp.
P.O. Box 9107
4073 Merchantile Avenue
Naples, Florida 33942
Phone: (813) 643-1500

A Combined Coax-Twisted
Pair 3270 Line Interface for
the DP8344 Biphase
Communications Processor

National Semiconductor
Application Note 624
Tim Davis and David Weinman

This paper will discuss the design of an improved 3270
transceiver interface for the National Semiconductor
DP8344 combining increased error-free performance and
the ability to communicate over both coax and twisted pair
transmission lines. At this date, the largest installed base of
terminals is the 3270 protocol terminal which primarily utilizes coax cabling. Because of phone wire's easy accessibility and lower cost, twisted pair cabling has become popular
among end users for new terminal installations. In the past,
baluns have been used to augment existing coax interfaces,
but their poor performance and cost considerations leave
designers seeking new solutions. In addition, the integration
of coax and twisted pair on the same board has become a
market requirement, but this is a considerable design challenge. A brief summary of the interface concepts, a discussion of the proposed design, and a description of the results
are included in this application note.

An effective receiver design must address each of the
above concerns. To counteract the effects of line filtering
and noise, there must be a large amount of jitter tolerance.
Some filtering is needed to reduce the effects of environmental noise caused by terminals, computers, and other
proximate circuitry. At the same time, such filtering must not
introduce transients that the receiver comparator translates
into data jitter.

CONCEPTS

Coax cable is normally driven on the center conductor with
the shield grounded. Conversely, unshielded twisted pair cable is driven on both lines. Because of the way that each is
driven, coax operation is often called unbalanced and twisted pair operation balanced.
Transmission line characteristics of coax and twisted pair
cables can be envisioned as essentially those of a low-pass
filter with a length-dependent bandwidth.1 In 3270 systems,
different data combinations generate dissimilar transmission
frequencies because of the Manchester format. 2 These two
factors combine to produce data pulse widths that vary according to the data transmitted and the length and type of
cable used. This pulse-width variation is often described as
"data jitter." 3
In addition to line filtering, noise can cause jitter. Coax cable
employs a shield to isolate the signal from external noise.
Electromagnetically balanced lines minimize differential
noise in unshielded twisted pair cable. In other words, the
twisted pair wires are theoretically equidistant from any
noise source, and all noise superimposed on the signal
should be the common-mode type. Although these methods
diminish most noise, they are not totally effective, and environmental interference from other nearby wiring and circuitry may still cause problems.
Besides the effects of jitter, reflections can produce undesirable Signal characteristics that introduce errors. These reflections may be caused by cable discontinuities, connectors, or improper driver and receiver matching. Signal edge
rates may aggravate reflection problems since faster edges
tend to produce reflections that may dramatically distort the
signal. 3 Most reflection difficulties occur over short cable
(less than 150 ft.) because at these distances reflections
suffer little attenuation and can significantly distort the signal. Since the timing of the reflections is a function of cable
length, it may be possible to operate at some short distance
and not at some greater length.

Like the receiver design, a successful driver design should
compensate for the filtering effects of the cable. As cable
length is increased, higher data frequencies become attenuated more than lower frequency signals, yielding greater disparity in the amplitudes of these signals. 4 This effect generates greater jitter at the receiver. The 3270 signal format
allows for a high voltage (predistorted) magnitude followed
by a low voltage (nondistorted) magnitude within each data
half-bit time. 2 Increasing the predistorted-to-nondistorted
Signal level ratio counteracts the filtering phenomenon because the lower frequency signals contain less predistortion
than do higher frequency signals. Thus, the amplitude of the
higher frequency components are greater than the lower
frequency components at the transmitter. Implementation of
this compensation technique is limited because nondistorted signal levels are more susceptible to reflection-induced
errors at short cable lengths. Consequently, proper impedance matching and slower edge rates must be utilized to
eliminate as much reflection as possible at these lengths.
Besides improved performance, both unbalanced and balanced operation must be adequately supported. Electromagnetic isolation for coaxial cabling can be provided by a
properly grounded shield. Electrically and geometrically
symmetric lines must be maintained for twisted pair operation. For both cable types, proper termination should be employed, although terminations slightly greater than the characteristic impedance of the line may actually provide a larger received signal with insignificant reflection. 3 In the board
layout, the comparator traces should be as short as possible. Lines should be placed close together along their entire
path to avoid the introduction of differential noise. These
traces should not pass near high frequency lines and should
be isolated by a ground plane.
BCP LINE INTERFACE DESIGN

An extensive characterization of the BCP comparator was
done to facilitate this interface design. The proposed design
enhances some of the BCP transceiver's characteristics
and incorporates the aforementioned suggestions.
The interface design takes into account the common comparator attributes of power supply rejection, variable switching offset, finite voltage sensitivity, and fast edge rate sensitivity. Vee noise can affect the comparator output when the
inputs are biased to the same voltage. This particular type of
biasing may render portions of the comparator susceptible
to supply noise. Variable switching offset and finite voltage
sensitivity cause the receiver decoding circuitry to see a

II
I

2-95

-.:r

~
Z

substantial amount of data jitter when signal amplitudes approach the sensitivity limits of the comparator. At these signal magnitudes, considerable variation in the output of the
. comparator is observed. Finally, edge sensitivity may allow
a fast edge to introduce errors as charge is coupled through
the inputs during a rapid predistorted-to-nondistorted level
transition, especially as the nondistorted level is reduced in
magnitude.

Like many present 3270 circuits, the driver design (Figure 2)
utilizes a National Semiconductor DS3487 and a resistor
network to generate the proper signal levels. The predistorted-to-nondistorted ratio was chosen to be about 3 to 1. This
ratio was observed to offer good noise immunity at short
cable lengths (less than 150 feet) and error-free transmission to an IBM 3174 controller at long cable lengths (greater
than 5000 feet).

The receiver interface design (Figure 1) addresses each of
the BCP comparator's characteristics. A small offset (about
17 ·.mV) separates the inputs to eliminate Vee-coupled
noise. This offet is relatively large compared to possible fab. rication variations;' resulting in a more consistent, deviceindependent operation. The offset has the added benefit of
making the comparator more immune to ambient noise that
may be present on the circuit board. A 2:1:1 transformer
(arranged as a 3:1) restores any voltage sensitivity lost by
introducing the offset. A bandpass filter is employed to re. duce the edge rate of the signal at the comparator and to
eliminate environmental noise. The bandwidth (30 kHz to
30 MHz) was chosen to provide sufficient noise attenuation
while producing minimum data jitter. Refer to Appendix 2 for
a derivation of the filter equations.

To allow for two interfaces in the same circuit design, the
coax/twisted pair front end (Figure 3) includes an ADC Telecommunications brand TPC connector to switch between
coax and twisted pair cable. This connector allows different
male connectors for coax and twisted pair cable to switch in
different interfaces for the particular cable type. The coax
interface has only the shield capacitively coupled to ground.
The 510n resistor and the filter loading produce a termination of about 95n. The twisted pair interface balances both
lines and possesses an input impedance of about 1DOn .
This termination is somewhat higher than the characteristic
impedance (about 96!1) of twisted pair. Terminations of this
type produce reflections that do not tend to generate mid-bit
. errors, as well as having the benefit of creating a larger
voltage at the receiver over longer cable lengths.

DP8344

+5V
PE 5769

,-=+.;..........o4J......--II--+--JWIr---4~--I +AlG-IN

''--+----4......- - - I I - -....-'V'V'\t--...- - - I -AlG-IN

Legend

To coax/twisted pair front end

lID

To line driver circuitry
TLlF/l044B-l

*Includes board capacitance

FIGURE 1. BCP Receiver Filter Design

1/2 DS3487

DP8344

45.3n 1%
38
1--+-__ -1 DATA-OUT

+
37
1--+---1 DATA-DlY
loon 1%
. Legend,

lID

To 2:1:1 Transformer _

TLlF/l044B-2

FIGURE 2. BCP Driver Design

2-96

ADC Connector

0.1 J.lF

Center - - - - - - -..2;;....--(i~-----Ia-[[r
Twisted Pair
Shleld_

:: 510n

..L O.IJ.1F
"> 510n~

....-../.

I77T

GND
Legend

(A) To 2:1:1 Transformer

I~-

IIl..!..J
0.1 J.lF

Il'·'PF

TL/F/l044B-3

·Connector closes switch for coax and opens switch for twisted pair.

FIGURE 3. BCP Coax/Twisted Pair Front End
RESULTS AND COMPARISONS

ances (higher turn ratios may demand circuits with very low
tolerance percentages).

The evaluation involved producing multiple data transfers
between an IBM 3174-81 R and the device under test during
a live 3270 session. The preferred method of testing would
be to transfer extremely large files to the host. Since terminals and muxes cannot transfer files and all devices being
tested needed to be evaluated under similar conditions, a
screen-oriented approach was taken for testing. The
screen-oriented approach involved using common methods
for forcing the controller to send an entire screen of characters to the device. Procedural specifics are included in Appendix 1.

There are also economical advantages in using the BCP
comparator. The number of active and passive components
required to build the line interface is small compared to
competing solutions. The proposed design is extremely cost
competitive with current media solutions.
CONCLUSION
An effective and economical 3270 interface solution has
been demonstrated using only passive components and a
line driver. Guidelines have also been suggested to facilitate
the design and layout of such an interface. Criteria concerning board layout and noise suppression must be considered
to be at least as important as the components themselves;
for example, adjustments should be made for variations in
board capacitances and inductances. With only slight modification of the components given for this design, it is thus
likely that optimum performance can be obtained for a specific layout. Implementation of these design principles
should prove advantageous for the development of an efficient and competitive 3270 line interface.

Performance of the BCP interface typically extended over
7000 feet of RG62A/U coax and 1700 feet of AT&T DIW
4 pair/24 AWG unshielded twisted pair. This operation met
or exceeded many of the current 3270 solutions. The performance of other 3270 products was obtained from production stock of competitors' equipment and should be taken as typical operation. Although these long distances are
possible, it is recommended that companies specify their
products to IBM's PAI2 specifications of 5000 feet of coax
cable. The extra long distance capability of the new interface will assure the designer a comfortable guardband of
performance. Similarly, a 50% margin on the unshielded
twisted pair capability will give approximately a 900 foot
specification.

REFERENCES
1. H.P. Neff, Jr., Basic Electromagnetic Fields, New York:
Harper and Row, 1981, Chapter 13.
2. IBM 311413214 Control Unit to Device Product Attachment Information, Communication Products Information Development, International Business Machines Corporation,
Research Triangle Park, NC, October 1986.

It should be noted that the BCP receiver detects errors before the controller does. This is because of comparator
skew, a mechanism that occurs when the amplitude of the
signal approaches the sensitivity of the comparator. At
these small levels, propagation symmetry for high-to-Iow
and low-to-high transitions is lost. The failure mechanisms
of competitors include insufficient receiver jitter tolerance,
filter tranSients, and comparator skew. Operational distance
may be extended by the utilization of transformers with higher turn ratios as long as considerations are taken for impedance matching, driver loading, and component quality toler-

3. K.M. True, The Interface Handbook: Line Drivers and Receivers, Semiconductor Components Group, Fairchild Camera and Instrument Corporation, Mountain View, CA, 1975.
Chapters 3 and 4.
4. N.S. Nahman, "A Discussion on the Transient Analysis of
Coaxial Cables Considering High Frequency Losses," IRE
Trans. Circuit Theory, vol. CT-9, pp. 144-152, June 1962.

EI
I

2-97

~
Z

> R2 and C1 > > C2, we can then
simplify the equation and solve for the poles to obtain the
following form:

III

~ ~ ± ~~ - 4 (AI A2' e, e2)
41T

After splitting the above equation to solve each pole and
using a binomial expansion to simplify each pole's equation,
we get:

1
f, :::: 'lTR1 C1 :::: 20 kHz
(vs. 30 kHz from simulation and testing)
1
fh :::: 4'IT R2 C2 :::: 40 MHz

(vs. 30 MHz from simulation and testing)

2-98

Interfacing Memory to the
DP83448

National Semiconductor
Application Note 623
Bill Fisher,
Mark Koether

As with most other aspects of a design, choosing memory is
a cost vs. performance trade off. Maximum performance is
achieved running no wait-states with fast, expensive memory. Slower, less expensive memory can be used, but waitstates must be added, slowing down the BCP. Therefore
one needs to choose the slowest memory possible while
still meeting design specifications. While this article assumes RAM is used for instruction and data memory, the
information is relevant to memory devices in general.
The BCP needs separate data and instruction RAM, each
with their own requirements. Instruction read time is the major constraint when choosing instruction RAM. Instruction
read time, tl, as shown in Figure 1, is measured from when
the instruction address becomes valid to when the next instruction is latched into the BCP. Instruction read time for
various clock frequencies and wait states are given in Table
I. Clock frequency and wait state combinations other than
those given in the table can be calculated by the following
equation:

The selection of data memory RAM requires the evaluation
of several important timing parameters. The RAM access
time, strobe width, and data setup times are three of the
most critical timing parameters and must all be matched to
equivalent BCP timing parameters. The RAM access time
should be compared to the data read time of the BCP. The
following discussion assumes 3 T-state data memory read
timing ([4TR] = 0). However, the basic approach is applicable to the less critical 4 T-state data memory read timing.
Detailed information on this mode can be found in the CPU
Description and the Device Specifications sections of the
BCP data manual.
Data read time, to, (Figure 2) is measured from when the
data address is valid to when data from the RAM is latched
into the SCPo Table II gives data read times. The equation
for calculating data read time is similar to the one given for
instruction read time:

tl = 103 (1

h +
+T

nlw)/fcPU - 19

where tl is the instruction read time (ns), nlW is the number
of instruction memory wait states, T L is the CPU clock low
pulse width (ns), T is the CPU clock period (ns), and fcpu is
the clock frequency (MHz) at which the CPU is running. The
RAM chosen needs to have a faster access time than the
read time for the desired combination of clock frequency
and wait states. However, instruction read time is not the
only timing consideration when choosing instruction RAM. If
the BCP is used in an application which requires full speed
softloading of instruction RAM, there are two other timing
relationships which require evaluation. These are data setup
time and write pulse width. The relevant BCP timing parameters are I valid before IWR rising, tpo-I-IWR, and IWR ·Iow
time, tW-IWR. The value of these timing parameters depends
on the Remote Interface mode of operation. More detailed
information can be found in the Device Specifications and
the Remote Interface and Arbitration System sections of the
BCP data manual. Note that in a typical application of the
BCP, softloading occurs after reset with the BCP operating
with CLK/2 and full wait states. Under these conditions the
instruction read time value is the critical parameter for
choosing the instruction RAM.
T1

tp = 103 (2

TABLE II. Data Read Time, to (ns)
CPU
Clock Freq.
(MHz)
(TL/T = 0.5)

FIGURE 1. Instruction Read Time

9.43

140

246

352

18.86

113

166

20.00

106

156

TL/F/10447-2

TL/F/10447-1

::::::::XZVAV?1W~

FIGURE 2. Data Memory Read Timing

ALE~

~"~

IA:::::::X

lAO-IS

Wait States

CLK-OUT~

TABLE I. Instruction Read Times, tl (ns)

MAX (now, nlW - 1»/fCpu - 40

where to is the data read time (ns), now is the number of
data memory wait states, nlW is the number of instruction
memory wait states, T L is the CPU clock low pulse width
(ns), T is the CPU clock period (ns), and fcpu is the clock
frequency (MHz) at which the CPU is running. Since the
lower address byte (AD) is externally latched, the latch
propagation delay needs to be subtracted from the available
read time when determining the required RAM access time.

CLK-OUT~

CPU
Clock Freq.
(MHz)
(TL/T = 0.5)

h +
+T

Wait States
MAX(now, nlw - 1)

9.43

225

331

437

18.86

145

198

20.00

135

185

Another important timing parameter is the RAM strobe
width. The BCP READ and WRITE outputs will typically be
used to strobe data out of and into the RAM. The signal
relationships for a data memory access are shown in Figure
2 for a read and in Figure 3 for a write. Table III contains
READ and WRITE pulse width values for various clock frequencies and wait state combinations. The equation for calculating READ and WRITE pulse width is:
tw = 10 3(1 + MAX(now, nlW - 1)/fcpu - 10

2-99

•

,---------------------------------------------------------------------------------------,
where tw is the pulse width (ns), now is the number of data
memory wait states, nlW is the number of instruction memory wait states, and fcpu is the clock frequency (MHz) at
which the CPU is running. The RAM chosen should require
shorter strobe widths than the pulse width listed in Table III
for the desired combination of clock frequency and wait
states.

and fcpu is the clock frequency (MHz) at which the CPU is
running. The data memory RAM used needs to have a faster output enable time than the time listed in Table IV for the
desired combination of clock frequency and wait states.
TABLE IV. Data Read Setup Time, tSR (ns)
CPU
Clock Freq.
(MHz)

elK-OUT

____________c:

9.43

ALE

l(Z

DATA

TLIF/10447-3

FIGURE 3. Data Memory Write Timing

Walt States
MAX(now, nlw - 1)

190

296

18.86

137

20.00

128

When writing to data memory, the data must be valid in time
to meet the setup time requirement of the RAM. In a typical
application, this time is measured from the data becoming
valid out of the BCP to WRITE going high. Figure 3 shows
this timing relationship, tow, and Table V contains times for
various combinations of clock frequencies and wait states.
The equation for calculating this time is:

9.43

202

308

tow = 103 (1 + MAX(noW,nIW - 1»/fcpu - 20
where tow is the minimum data valid time before WRITE
rising (ns), now is the number of data memory wait states,
nlW is the number of instruction memory wait states, and
fcpu is the clock frequency (MHz) at which the CPU is running. This time should be at least as long as the data setup
time of the RAM.

18.86

149

TABLE V. Data Write Valid Time, tow (ns)

20.00

140

TABLE III. READ and WRITE Pulse Width, tw (ns)
CPU
Clock Freq.
(MHz)

Walt States
MAX (now, nlW - 1)
0

The last important consideration when choosing the data
memory RAM is setup times into the BCP on a read and into
the RAM on a write. In a typical application, READ is connected to the output enable pin on the RAM. When reading
from the RAM, the data becomes valid when READ falls
and activates the RAM outputs. The data must become valid fast enough to meet the setup time required by the BCP.
This setup time tSR, as shown in Figure 2, is listed in Table
IV for various combinations of clock frequencies and wait
states. It can be calculated from the following equation:
tSR = 103 (1 + MAX(now, nlW - 1)/fcpu - 22
where tSR is the maximum time allowed for the data to become valid (ns), now is the number of data memory wait
states, nlW is the number of instruction memory wait states,

CPU
Clock Freq.
(MHz)
9.43

Walt States
MAX (now, nlW - 1)
0

200

306

18.86

147

20.00

130

Instruction RAM has the greatest effect on execution speed.
Each added instruction memory wait state slows the BCP by
about 40% as compared to running with no instruction
memory wait states. Each added data memory wait state
slows a data access by 33% as compared to running with
no data memory wait states. RAM costs are coming down,
but higher speed RAM still carries a price premium. So there
is the trade-off.

2-100

l>
ZI

National Semiconductor
Application Note 504
Jim Margeson

DP8344 BCP Stand-Alone
Soft-Load System
INTRODUCTION
The DP8344 Biphase Communications Processor (BCP) is a
20 MHz Harvard architecture microprocessor with an onchip transmitter and receiver. The BCP can be used to implement several biphase communication protocols:
IBM 3270, IBM 3299, IBM 5250, and National's general purpose 8-bit protocol. This application note shows how

DP8344 software can be loaded from EPROM into instruction RAM. It is particularly valuable in stand-alone systems
where the BCP is not interfaced to a host processor. Possible applications include: protocol converters, multiplexers,
high-speed remote data acquisition systems and remote
process control systems.

INSTRUCTION ADDRESS
16

LINE
INTERFACE

INSTRUCTION
MEMORY

INSTRUCTION
16
DATA ADDRESS

BCP

DATA
MEMORY
8

MULTIPLEXED
ADDRESS/DATA

HOST
PROCESSOR
TL/F/9403-1

FIGURE 1. BCP System with Host Processor
INSTRUcnON ADDRESS

'16
1

LINE
INTERFACE

A
"I

INSTRUCTION
RAM 45n5

INSTRUcnON
'16

DATA ADDRESS

BCP

'$~6

DATA
MEMORY

LATCH

Jr"

INTERFACE
CONTROL
LINES

PAL
16R6B

' 8

IoIULTlPLEXED
ADDRESS/DATA

CONTROL
i - . LINES

16K X 8
EPROM
3~O

PERIPHERALS:
DIGITAL I/o
ANALOG I/o
AND/OR
UARTS

FIGURE 2. BCP Stand-Alone System with EPROM Soft Load Circuit

2-101

TlIF/9403-2

IWR
INSTRUCTION AOORESS

ClK-OUT A.

XTAll

1J118.8696

N.C.
-

ICU<

It!

CLK-OUT

citr'
~ It :~TClK
~

MHZ

39p'

WAiT

iiiiI

10K

ffi-IN
BIRQ

~O:IS)

BCP

INSTRUCTION BUS
REAo-

OP8344V
A(8:1S)
t.(O:7

AO(O:7

LINE
INTERFACE

_ _ _ _...I

~
10 10

DATA-OEL
DATA-OUT
TX-ACT
IN-PLUS
IN-MINUS

20
30
40
SO
60
70
80
C

20
30
4Q
SO
SO
70
SO

tAc

~i=
~~
r

I--<

tt:::::

----i

CH.~

r~e

A~ ~K ~ I:.i. ....lC.l_'-I-...Jr,---ti-!F=j]t::=================
.

ill

lu. iKt.lW

f jJ.mt. .

~~u 4,..!ill- :~ ~g~!I..l.!~LillQ.~~:t:=:----t-l
6
4~
V
RAE.' _ _ _+-__...1
74ALS14

:MCK

.11W1

EPAO

TLIF/9403-3

FIGURE 3. Schematic

2-102

»
z
I

en
o
~

iA(O:IS) INSTRUCTION AOORESS

INSTRUCTION WEWORY
T28

vee

3 1.12
All
1A9
4 1.10
lAB
5 1.9
AS
~ 1.7 RAW
1.6 8KX8
1A5
AS 45nS
1A4
6
1.4
A3
A2
AI
lAO I
1.0 GIlD
11.11

Eli
P.P
~ ~~ ~

INSTRUCTION BUS

WE
Or

ffi

T28

hI
I:: :a

CS2
,
07
D6
05
16 11
04
03 ~
02 ~
01 ~
DO

1.12
1A10
1 All
AID
lAB 2 Ai
1.8
1.7
RAW
~
1.6 8KX8
AS 45nS
1.4
1.3
~
IA2
8
1.2
AI
!
AD GIlD

~
~

r---#.--4
i ~~ ~

rU--L-

I~~ 1~

WB81 C78A-45
PKG FT-28PW02

vee

}i4

~0:15)

WE
Or
CSi

CS2

hT
22
2
6

07 19 17
D6
05
04 ~
03
3 I
02
1
11
01
DO

i:~

m!=

rll--L-

WB81 C78A-45
PKG FT-28PW02

READ
WRITE
ADDRESS (HIGH)

1.(8:15)
1.0:7

ADDRESS LOW

A 0:7

DATA WULTIPLEXED

DATA WEWORY

! ~~~ 2~

~
t-#-¥.
~
1.7
3

"b!

NWC27CP128

1 VPP
VCC

iUl'

A6
AS
1.4
1.3
A
AI
AO

20 EE

AI4~,

1.13
OE
1.12
EPROW All
16KX8 Ai~
350nS 1.8
07
1.7
06
1.6
05
AS
04
1.4
03
A3
02
A2
01
AI
00 GNO AD

5
6
7
8
9
10

I
~8

VCe....
1.12
WE
All
Or
AID
ffi
Ai
CS2
1.8
1.7 RAW 07
1.6 8KX8 D6
AS 45nS 05
1.4
04
1.3
03
A2
02
AI
01
1.0
DO
GIlD

~
Ii
18
17
16
15
13
1
11

1.07
1.06
ADS
AD4
AD3
AD
ADI
ADO

PERIPHERALS
(UARTS.
DIGITAl I/O.
AND/OR
ANAlOG I/O)

WB81 C78A-45
PKG FT-28PW02

IAU

TL/F/9403-4

FIGURE 3. Schematic (Continued)

2-103

Ll)
I

«,

WHY EPROM 50FT-LOAD?

In a stand-alone application, the BCP instruction code must
be kept in non-volatile memory. Instruction memory with
45 ns access time is required to run the BCP at full speed.
EPROM at this speed can be quite expensive, much more
than 45 ns RAM or 350 ns EPROM. RAM with 45 ns access
time can be used for instruction memory if a scheme is employed to load the BCP code into the RAM from slow
(350 ns), inexpensive EPROM, upon power-up.
In non-stand-alone applications, a host processor would
communicate with the BCP through the BCP's built-in remote interface (Figure 1). In such a system, BCP code
would be loaded from the host into the BCP's instruction
RAM using the remote interface. In a stand-alone system,
however, the BCP is not interfaced to a host; the program is
loaded from EPROM through the remote interface. As
shown in Figure 2 a PAL ® sequencer controls the loading of
the program, generating handshaking, signals similar to
those of a typical host processor. When the load is complete, the sequencer tells the BCP to begin execution of the
program.
HOW THE 50FT-LOAD CIRCUIT WORKS
The BCP, as configured in this system,.comes up halted'
after reset (Figure 3). The program counter is set to zero,
and the remote interface is configured to receive '16-bit instructions in 8-bit pieces and write them into instruction
memory. The BCP has the feature that it can be configured

to come up stopped or to begin program execution after a
reset has occurred. If the following conditions are true when
reset is de-asserted then the processor will begin running:
RAE - (Remote Access Enable, active low) = High,
REMWR - (Remote Write, active low) = low, REMRD(Remote Read, active low) = low. Otherwise, it will come up
halted.
The PAL sequencer begins the software load by writing the
low byte of the first instruction to the remote interface. A
simplified flowchart of the sequence operation is shown in
Figure 4.
This byte comes from address OOOOH of the EPROM. The
corresponding locations of EPROM and RAM are shown in
Figure 5. The I,east significant address line of the EPROM is
controlled by the seque~cer; the other address lines are
driven by the instruction address bus of the BCP. The instruction address bus reflects the contents of the BCP's
program counter (PC), which contains the destination of the
instruction currently being loaded. After the low byte of the
first instruction' is' written to the remote interface, the sequencer brings the least significant address line of the
EPROM high. Now location 0001 H of the EPROM is addressed, and the high byte of the first instruction is written to
the remote interface. At this point the BCP writes both bytes
into address OOOOH of instruction RAM, and increments its
, program counter.

TL/F/9403-5

FIGURE 4. Sequencer Operation

2-104

EPROM
Address

0
1

2
3
4
5

•
•
•
•
16382
16383

address bus. Location 0002H of the EPROM is addressed,
and the low byte of the second instruction is written to the
remote interface. The sequencer then brings the least significant address line of the EPROM high (to address location 0003H) and the high byte of the second instruction is
transferred. The BCP writes the second 16·bit instruction to
location 0001 H of instruction RAM. This process is repeated
until the last instruction is transferred.

Instruction
Memory Address

0
0
1
1
2

(Low Byte)
(High Byte)
(Low Byte)
(High Byte)
(Low Byte)
(High Byte)

•
•
•

8190
8191

The sequencer senses that the load is complete when instruction address line 13 comes high. This occurs when the
program counter is incremented to a value of 4000H, indicating that 8K instruction words have been transferred. At
this point the BCP must be started. To achieve this, the
sequencer resets the BCP again, while holding RAE - high,
REMRD- low, and REMWR- low. A reset during these
conditions brings the processor up running, and also clears
the program counter. The BCP begins execution at instruction address OOOOH and the sequencer and EPROM go into
an inactive state, transparent to the software being executed. A detailed version of the sequencer flowchart is shown
in Figure 6. A hardware compiler/minimizer was used to obtain the equations shown in Figure 7. These equations were
used to program a National PAL16R6B. Typical timing
waveforms of the soft-load are shown in Figure 8.

(Low Byte)
(High Byte)

FIGURE 5. EPROM to RAM Address Mapping

The first 16-bit instruction has been transferred; the second
is done in a similar manner. The sequencer brings the least
significant address line of the EPROM low again. The PC
now contains 0001 H, which is output on the instruction

2-105

-.:to

oLt)

XXXXXX
I I I I I
I I I I

REt.4RD
STI
ST2
CS
EPAO
REt.4WR

--I I II
---- I I I
I I
-----I

WRITE LOW BYTE
INSTRUCTION

TLIF/9403-8

FIGURE 6. Sequencer Flowchart

2-106

increment through the memory locations, thus an external
13-bit counter would be needed. TRI-ST ATE® buffers would
isolate the RAM and EPROM from the instruction data and
instruction address busses during soft-load. These buffers
would add propagation delays to memory accesses demanding that faster RAM be used. Soft-loading through the
remote interface requires fewer I.Co's and does not degrade
the performance of the processor.

There are several advantages to using the remote interface
to load the BCP software. If a scheme like the one in Figure
9 was used to load the program directly from EPROM to
instruction RAM, much more hardware would be required
and the access time of the RAM would need to be shorter.
Two EPROMs would have to be used instead of one because the transfer would be 16 bits wide instead of 8 bits. In
this case the BCP's program counter could not be used to

DMPAL16R6B;
SOFTLOAD
CK LCL XACK IA13 RESET NC6 NC7 NC8 IWR GND
10E IBRESET IREMWR IEPAO ICS IST2 ISTl IREMRD ILCLINV VCC
IREMRD .- RESET*
IREMRD*
CS*/EPAO*/REMWR
+ RESET*
IREMRD*
ST2* CS*
IREMWR
+ RESET*
IREMRD* ST1*
CS*
IREMWR
+ RESET*IA13* REMRD*/ST1*/ST2*/CS*/EPAO* REMWR
._ RESET*
REMRD*/ST1* ST2*/CS
ISTl
+ RESET*
REMRD* ST1*/ST2*/CS
+ RESET*
IREMRD* ST1*/ST2* CS*
IREMWR
+ RESET*
IREMRD*/ST1* ST2* CS*
IREMWR
IREMWR
+ RESET*/XACK*REMRD*
IST2*/CS*
._ RESET*
REMRD*
ST2*/CS
IST2
IREMWR
+ RESET*/XACK*REMRD*/ST1*
ICS*
+ RESET*
IREMRD*
ST2* CS*
IREMWR
+ RESET*
CS* EPAO*/REMWR
IREMRD*/STl*
+ RESET*
REMRD* ST1*/ST2* CS* EPAO* REMWR
._ RESET*
REMRD*
IREMWR
ICS
ICS*
+ RESET*
REMRD* ST1*
ICS
+ RESET*
REMRD*
ICS* EPAO
+ RESET*
REMRD*
ST2*/CS
+ RESET*
REMRD* ST1* ST2*
EPAO* REMWR
+ RESET*/IA13*REMRD*
ICS
*/EPAO := RESET*
REMRD*
ST2*/CS*/EPAO
+ RESET*/XACK*REMRD*
ICS*/EPAO
+ RESET*
REMRD*
ICS*/EPAO* REMWR
+ RESET*
REMRD* ST1*
ICS*/EPAO
+ RESET*
IREMRD* ST1*
CS*/EPAO*/REMWR
+ RESET*
ST2* CS*/EPAO*/REMWR
IREMRD*
+ RESET*XACK* REMRD*/ST1*/ST2*/CS*EPAO*/REMWR
+ RESET*
REMRD* ST1* ST2* CS*EPAO* REMWR
IREMWR .- RESET*
IREMRD*
ST2*/CS*
IREMWR
+ RESET*
REMRD* ST1*
ICS*
IREMWR
+ RESET*
IREMRD*
CS*/EPAO*/REMWR
+ RESET*
IREMRD*
ST2* CS*
IREMWR
+ RESET*
REMRD*/ST1*/ST2*/CS*
REMWR
+ RESET*
IREMRD* ST1*
CS*
IREMWR
+ RESET*/XACK*REMRD*
ICS*
IREMWR
IBRESET
IRE SET +
IREMRD*/ST1*
CS *IEPAO *IREMWR
ILCLINV
LCL

=
=

FIGURE 7

2-107

»
z

It)

:riming at Beginning of Instruction Load

RESET

BRESET

RAE ~.

REMRD

REMWR

XACK

LCL

.~r

__~fl~·__~·t.l~__~fl~·__~·~

__~'[l~'__~'[l~'_'__~I.l~'____'~

.u......

____~.I. ...... ~ .

.r'--.. . .I.

IWR

U . .L
.,-I'---ilL.

ICLK
TLIF/9403-6

Timing at End of Instruction Load

BRESET-------------------------------,.LJ.

RAE _._ _ _ _ _ _ _ _ _ _ _

REMWR
XACK

.1·--1·1.
..
.................... .
la-.:__. . . .n. ·. _______n. .·_. ·.1. . .................... .
la-:__. ·n
. . ___.·1.. .

.u.

.~r

_________________________

.f____1
n. . . --......I·n.....· _.fLJ. --......If

ICLK _______________________........

1-..1

TL/F/9403-9

FIGURE 8. Example of Timing Waveforms

2·108

PAL

--I

I
INSTRUCTION
ADDRESS
I

-,..

'16

LINE
INTERFACE

A
~

INSTRUCTION

r-B

'16

r
r

E
R
'-

DATA ADDRESS

BCP

LATCH

T
13 - BIT
COUNTER

INSTRUCTION
RAM
<45ns

,
'16

,
'II

ROM
300ns

DATA
MEMORY'

MULTIPLEXED
ADDRESS/DATA

PERIPHERALS:
DIGITAL I/O
. ANALOG I/o
AND/OR
UARTS
TL/F/9403-7

FIGURE 9. Another Method of Soft-Loading (A Non-Ideal Solution)
tional I.C.'s into the breadboard area. A diagram of the
CT-l04 board with the additional components is shown in
Figure 11. Note that most of the prototyping area remains
available, enabling the addition of other circuitry specific to
the application being developed. A parts list is shown in
Figure 12. The PAL16R6 is programmed with the equations
shown in Figure 7. U22 and U23 must be removed from the
CT-l04 board and be replaced with specially wired 20-pin
headers. The wiring on these headers, shown in Figure 13,
provides access to the RESET - signal and disables the
unused interface circuitry on the board. Pin 11 of the header
that replaces U23 must be wired to pin 13 of the 74LS14. A
wiring list is shown in Figure 14. Power supply connections
must be added because the board can no longer reside in
the PC. Development of a stand-alone soft·load application
can be done easily and quickly by using the CT-l04 board
because minimal circuit construction is required.

MODIFYING THE SOFT-LOAD SYSTEM
FOR LARGER MEMORY
The soft-load system as documented loads 8K x 16 bits of
instruction memory. Large programs may require more
memory; smaller, lower cost systems may use less. The
soft-load system can easily be altered to load larger or
smaller instruction memory by changing one connection.
Connecting a different instruction address line to pin 4 of
the PAL changes how much instruction memory is loaded:
These connections are shown in Figure 10
Instruction Memory Size:

Connect Pin 4 of PAL to:

32kx 16
16k x 16
8kx 16
4kx 16
2kx 16

IA15
IA14
IA13
IA12
IAll

SUMMARY

FIGURE 10. Connections for Altering
Instruction Memory Size

The soft-load circuit uses the BCP's remote interface to
load BCP code from slow EPROM to fast RAM, with a minimum of extra hardware. This method is useful in systems
where there is no host processor directly interfaced to the
BCP and the full processing speed of the BCP is needed.

USING THE CAPSTONE CT-104 DEVELOPMENT BOARD
TO EVALUATE THE SOFT-LOAD APPLICATION
A DP8344 biphase Communications Process development
board is available from Capstone Technology Inc., of Fremont, California. The board is designed to reside in an IBM®
PC. A breadboard area is provided on the board so that
custom circuitry can be added. It can be converted into a
stand-alone soft-load system by wire-wrapping three addi-

The circuit can easily be modified to load different sizes of
memory. The Capstone Technology, Inc. CT-l04 development board can easily be converted to a stand-alone softload system for evaluation of the application.

2-109

•

11
11

~22 ns

REt.lRD

minimum

'"'

1
mi~~~~m -.f

'1
1

REt.lWR
TLlF/l04S1-2

(b) This timing diagram shows the timing necessary for the BCP to recognize both accesses as separate accesses. The first set of arrows
shows the BCP sampling a valid remote r~ad. One T-state later at the second set of arrows, the BCP will sample the erid of the first
remote access. Another T-state later at the third set of arrows,the BCP will sample the beginning of the second remote access~
FIGURE 1. Mistaking Two Remote Accesses as Only One

1.5 T - s t a t e s - - - - - - - i

BCP's CPU CLK

RAE

REt.lRD

REt.lWR

Ct.lD

2nd Remole Access's

1st Remota Access's
CIAO Value

CIAO Value

TL/F/l04S1-3

(a) This timing diagram shows the second remote access violating rest time. The first set of arrows shows the BCP sampling a valid
remote write. The second set of arrows (1 T-state later), shows the BCP sampling the end of the first remote access. If a second
remote access starts before the position of the third set of arrows (another 1.5 T-states later), the value of CMD will not be sampled.
The value of CMD has changed from the first remote access, so the BCP will write to the wrong location during the second access.

I\:)

1------- 1.5 T-stat•• - - - - - - . j
BCP's CPU CLK

RAE

-+..!.-....

+ - 1_ _ _ _ _ _

REt.lRD

REt.lWR

+-1_ _ _ _ _ _ _

CMD I 1st Remote Access'.
CIAO Value

......I~....

2nd Remote Access's
CWO Value

TL/F/l04S1-4

(b) This timing diagram shows the second remote access violating rest time. The first set of arrows shows the BCP sampling a valid remote write.
The second set of arrows (1 T-state later), shows the BCP sampling the end of the first remote access. If a second remote access starts
before the position of the third set of arrows (another 1.5 T-states later), the value of CMD will not be sampled. The value of CMD
does not change from the first remote access, so the BCP will write to the intended location during the second remote access.
FIGURE 2. Remote Rest Time for All Modes except Latched Write

L~9·N\f

III

AN-627
1+------- 1.5 r-.tat•• - - - - - - . j
BCP's CPU CLK

r--l

RAE

......,

I -22 minlmum- f..

~ IOns

minimumj..-

REt.lRD

I
j . - - 22 minimum-

REt.lWR

Ct.lD

lst Remote Acce.s's
CWD Value

I" "" "

""1/11

I
.... IOns minimumj..-

'II

'"''''

U U U

,.. .. ...... ,'"'''''''''''''''''''''''''''''' I

2nd Remote Acces.'s
CWD Value

TUF/l0451-5

(C) This timing diagram shows the timing needed to avoid rest time for all modes except latched write. The first set of arrows shows the BCP sampling the end
of the first remote access. The second set of arrows (1.5 T-states later), shows the BCP recognizing no remote access has started and the value of CMD will
be sampled for the next remote access. The third set of arrows shows the BCP sampling the correct value of CMD for the second remote access.

FIGURE 2. Remote Rest Time for All Modes except Latched Write (Continued)

I\)
~

BCP's CPU CLK

!
!

-l
4>

D.5 r-ltatll-1

11
RAE
REt.lRO

REt.lWR

WR-PENO

8n.-I

8ns

r1
'1
H

Ct.lO

2nd Remot. Acc ...••
CWD Value

TLlF/l0451-13

(d) This timing diagram shows a remote access starting after a half T-state plus a hold time since WR-PEND rose. The first set of arrows
shows the BCP sampling the value of CMD when WR-PEND rises. The second set of arrows shows the BCP recognizing that no remote
access has started and the value of CMD will be sampled for the next remote access. The third set of arrows shows the BCP sampling
the correct value of CMD for the second remote access. The BCP will carry out the second remote access as it was intended.
FIGURE 3. Rest Time for Latched Write Mode (Continued)

I\)

1-1

r-stat.--l

CPU CLOCK

ClK-OUT
TLlF/l0451-9

(a) BCP Running at Full Speed

CPU ClOCK

I----- ,.-.....

ClK-OU'
TLlF/l0451-10

(b) BCP Running at Half Speed
FIGURE 4. Relationship between the BCP's CPU-Clock and ClK-OUT

cle. As a result, at full speed one T -state equals one
ClK-OUT cycle, but at half speed one T-state equals two
ClK-OUT cycles. (Reference Figure 4 to see the relationship between the BCP's CPU-ClK and ClK-OUT at full
speed and half speed.) The specifications in Table 26 are all
measured with the BCP running at full speed. All of the rest
time specifications are dependent on the CPU-ClK and not
on ClK-OUT. At full speed, the CPU-ClK and ClK-OUT are
the same, and this fact allows specifications to ClK-OUT in
place of the CPU-ClK. On the other hand, at half speed the
specifications to ClK-OUT are no longer valid because one
cannot tell if a rising edge of ClK-OUT is a rising or falling
edge of the CPU-ClK.
Earlier the worst case rest time for the BCP mistaking two
fast back to back accesses as only one was given as:

For latched write mode the remote rest time starts when
WR-PEND rises. The rest time for this case can be calculated as follows:
rest time = 0.5T
(CMD changes)

The real time worst case for rest time in latched write mode
is with the BCP running at half speed. The following is a
calculation of this rest time with the BCP running at half
speed and OClK = 18.8196 MHz.
rest time = 1(ClK-OUT cycle)
(CMD changes)

DESIRABLE FEATURES OF A REST TIME CIRCUIT

The real time worst case for the BCP mistaking two accesses as one, happens when the BCP runs at half speed. So for
the BCP running at half speed and OClK = 18.8696 MHz,
the worst case rest time for mistaking two accesses as one
is:

In regards to designing with the rest time specifications, the
first suggestion is to determine if rest time is an issue in
one's design(s). If one's present or future design(s) is for
systems which can never violate the rest time specification,
the whole issue of rest time is a moot point.

+ th

On the other hand, designs such as terminal emulation
boards, which may be placed in faster and faster PC buses,
must address rest time. In slower PCs one's product may
never violate rest time, but in faster PCs rest time may become an issue.

rest time = 2(53 ns) + 22 ns + 10 ns
(mistaking two accesses as one)
rest time = 135 ns
(mistaking two accesses as one)

All remote accesses are susceptible to having two fast back
to back accesses recognized as only one. The worst case
rest time for this was determined earlier as:

Up to a full T-state (or two ClK-OUT cycles) may be added
to the above equation if one is using latched Read or Fast
Buffered Write modes. As explained in the CAUSES of Remote Rest Time section, this extra T-state is only added if
the remote processor can terminate the remote access
quickly after XACK rises (within a T-state). Otherwise, the
above equation remains valid as written. The reader should
note that this extra T-state is not mentioned or included in
the following calculations because it takes place coincidentally with that cause of rest time.
As mentioned previously, the absolute worst case rest time
for all modes, except latched write mode, may be calculated
by adding the above case of rest time to the second source
of rest time caused by fast back to back accesses with different values for CMD. This rest time can be calculated as
follows:
rest time = first source
(CMD changes)

rest time = 135 ns
(mistaking two accesses as one)
(where OClK = 18.8696 MHz and the BCP runs at half
speed, [CCS] = 1)
All designs with the BCP must guarantee this minimum
amount of time between every access.
The second issue of remote rest time involves fast back to
back accesses that have different values for CMD. The
worst case for this was also calculated earlier as:
rest time = 297 ns
(CMD changes)
(where OClK = 18.8696 MHz and [CCS] = 1)
Two ways to handle this rest time issue are:

+ second source

1. Prevent all remote accesses to the BCP for at least
297 ns after the end of every remote access.

resttime
= [H + t (setup time) + t (hold time)]
(CMD changes)
+ [1.5T + t (hold time)]

2. Hold off remote accesses that change the value of CMD
for a minimum of 297 ns after the last remote access.
However, allow remote accesses that do not change the
value of CMD to occur a minimum of 135 ns after the last
access. (When the value of CMD does not change from
one access to the next, this will allow accesses up to
162 ns sooner than option 1).

Note: The first hold time is during the second source's 1.5 T-states, so in
the following formula it disappears.

rest time = 2.5T
(CMD changes)

+ t (setup time) + t (hold time)

For the BCP running at half speed and OClK
18.8696 MHz, the absolute worst case rest time is:
rest time = 5(ClK-OUT cycles)
(CMD changes)
rest time = 5(53 ns)
(CMD changes)

+ 22 ns +

+ t (hold time)

rest time = 53 ns + 7 ns = 60 ns
(CMD changes)
Please refer to the latest datasheet for more information
and the most current specifications.

rest time = H + t (setup time) + t (hold time)
(mistaking two accesses as one)

rest time = 2(ClK-OUT cycles) + tsu
(mistaking two accesses as one)

+ t (hold time)

When designing with rest time one must decide if the increase in speed of option 2) is worth the extra logic. However, as is demonstrated by the design example for the
CT-104 (Next section), the increase in logic between option
1) and option 2) may be minimal.

+ tsu + th
10 ns

rest time = 297 ns
(CMD changes)

2-127

......
~

::2:

On the original CT-104, the REMRD and REMWR outputs of
U22 were buffered signals of MEMR and MEMW respectively. With the new rest time circuit both REMRD and
REMWR are held high when REM_enable = O. This prevents all remote accesses during rest time. When rest time
is over REM_enable = 1 and once again, MEMR and
MEMW control REMRD and REMWR respectively.

Again, latched write mode is addressed separately. Unlike
the other modes, latched write's rest time starts when
WR-PEND rises. Two possible design options are:
1. Hold off all remote accesses for at least 60 ns (If
OClK = 18.8696 MHz) after WR-PEND rises. However,
doing ,this will result in slowing every remote access to
the BCP. Furthermore, it should be noted that WR-PEND
Will, not rise until a minimum of three T-states after the
previous access has ended. If no accesses are allowed
until after WR-PEND rises, then the second access will
never be mistaken as a continuation of the previous access.

One of the D flip-flops in the 74AlS74 stores the value of
the previous access's CMD (LCMD). This value (LCMD)
was'latched at the beginning of the previous valid remote
access. With this value stored in a flip-flop, the rest time
state machine can determine if the present value of CMD
has changed since the last remote access.

2. Similar to the previous options, allow accesses after 136
ns if CMD has not changed between accesses. Then hold
off access for at least 60 ns after WR-PEND rises when
CMD changes between accesses.

The other D flip-flop acts as a part of the rest time circuit's
state machine. When RAE rises (signaling the end of that
access) a one (1) is latched into this flip"flop. This signal
(WAIT_START) forces the state machine to move through
the next three states in sequence. If this latch is not used,
the rest time state machine may also miss the ending of an
access if back to back accesses occur within one ClK-OUT
cycle plus the setup time for a PAL 16R4B's register input. If
OClK = 18.8696 MHz this time will be:

The last design issue that must be addressed is how to wait
the host processor while preventing remote accesses to the
,BCP. Normally the wait signal of a remote processor is driven by the XACK signal out of the BCP. (Please note that the
XACK signal can be active low, only when a remote access
to the BCP is in progress.) During rest time, the rest time
circuit prevents remote accesses to the BCP, so the XACK
signal will not wait the remote processor. PC buses specify
the maximum amount of time before the bus must be waited
(i~ it is going to be waited). It is possible that not allowing
remote accesses to the BCP (during rest time) may delay
the XACK signal long enough to violate this bus specification. To prevent this, designs which wait a PC bus, must use
logic to waitthe bus whenever a remote access begins during rest time. Furthermore, the logic that starts waiting the
bus before remote access is allowed to the BCP, must continue to wait the bus until XACK takes over waiting the bus.

time = 1 (ClK-OUT cycle)
time = 53 ns

+ t (setup time for PAL 16R4B)

+ 20 ns

= 73 ns

This in effect, trades a rest time of 136 ns for one of 73 ns.
However, while the output of this latch (WAIT_START, Figure 5) equals one, REM_enable will be low and the state
machine will be forced to' start the rest time states. In the
third rest time state the WAIT_START latch is, cleared by
the ClR_ST ART (Figure 5) signal going low.
ClR_START is produced in the rest time PAL 16R4B and
ClR_START equals zero (0) only when in the third rest
time state. In this way the WAIT_START signal guarantees
the minimal rest time of 136 ns by keeping REM_enable
equal to zero through at least three ClK-OUT cycles (Le.,
3[53 ns] = ,159 ns if OClK = 18.8696 MHz).

DESIGN EXAMPLE FOR THE CT-104
The four major goals in designing a rest time circuit for the
CT-104 were:
1. Keep the component count to a minimum.

To describe the operation of the state machine, a state by
state description follows. When reading through the states
one should remember that the state machine can only
change states on the rising edge of ClK-OUT. A flow chart
of this state machine is provided as Figure 6. Figure 7 is a
PAL program (written in the ABEL program language) for
the PAL 16R4, rest time PAL. Figure 8 shows the reduced
equations that result for the PAL program given in Figure 7.

2. Keep the impact to the original CT-104 design to a minimum.
3. Allow the CT-104 to operate in every mode.
4. Take advantage of the faster accesses allowed when
CMD does not change from one access to the next.
The rest time circuit is implemented on one PAL 16R4B and
one 74AlS74. Only a single signal (REM_enable) is fed
back into the original CT-104 design. In addition, the XACK
signal from the BCP is now fed into the rest time PAL 16R4B
and the IO_CHRDY signal to the PC bus is controlled by
this PAl®. This rest time circuit implements all modes and
takes advantage of the increase in speed possible when
CMD does not change from one access to the next.

STATE: IDLE
This state is entered when a system reset occurs. In this
state REM_enable = 1, CMD_clk = 0, and XACK controls the state of IO_CHRDY.
The state machine will stay in this state until a valid remote
access starts (Le., RAE = 0). Then the state machine
moves to CYCLE_START.

First, how the REM_enable signal controls remote accesses will be discussed. Then, the functions implemented by
the two positive-edge-triggered D flip-flops in the 74AlS74
will be discussed. Finally, a description of the operation of
the rest time state machine, in the PAL 16R4B, will be given.
Figure 5 is the schematic for the CT-104's rest time circuit.

Note: On the CT-104, the Signal RAE is a full decode of a valid access. This
means that it decodes a valid address and a valid MEMR or MEMW. If
RAE is only an address decode, it alone would not indicate that a
valid access had started.

STATE:CYCLE--START

The REM_enable (Figure 5) signal is produced in the rest
time PAL 16R4B and is low during rest time. After rest time is
over the REM_enable signal goes high until the end of the
next access, when it once again goes low during rest time.

In this state REM_enable = 1, CMD_clk = 1 as long as
RAE = 0, ClR_ST ART = 1, and XACK controls the state
of IO_CHRDY. Note, when CMD_clkrises it latches in the
present value of CMD. The state machine will stay in this
state until the remote access ends, indicated by either
RAE = 1 or WAIT_START = 1. Then the state machine
moves to WAIT1.

The signal REM_enable is fed back into U22 (a PAL16l8)
on the CT-104. (Note that this PAL had one unused pin so
the design of this PAL was only slightly altered.)

2-128

SYS_RESET

......II ~

CL10,LU22
PAL16L8

UODE
UODE

'C..ADDR

PC_CTL

L
~

3 18

B7 13 SYS RESET

A17

4 17

B6 14 REURD

A16

5 16

B5 15 HST PD PCH

A15

6 15

B4 16 HST PO PCL

7 14

B3 17 RAE

AEN

8 13

B2 18 REJ.I ENABLE

UEUR

9 12

01 19 CUD

UEUW 11 11

I
I

......-.

---C-H

HS~P

---

---CL

---

HS~P

~
.....~
......-.

RESLPAL
PAL16R4
CLILOUT

SYS RESET

RAE

WAfT START

CK
00 19

.....-

......-.

A19

....
.....

CULSTART

08 12 REUWR

0 ???? START

I:I..ILOUT

1 110
2 19

74lS74

~CK
I\)

REJ.IWR

A19

WR PEND

XACK

LCUD

CUD

10
11
12

10 CHRDY

01 18 CUD_CLK

---

IO~D

02 13 CLR_START
03 12 REU ENABLE

13
14
15
16
17

00 17 00
01 16 01
02 15 02
03 14 03

74lS74

~ D PR 0 LCUD
CU~CK

0
CLR

....
......

-=-

TLlF/l0451-11

FIGURES

L~9·N"

yes

REt.4_enable = 0
Ct.4D_clk =0
CLR_START = 1

REt.4_enable = 0
Ct.4D_clk = 0
CLR_START = 0
REt.4_enable = 0
Ct.4D_clk =0
CLR_START = 1

REt.4_enable = 0
Ct.4D_CLK=O
CLR_START = 1

REt.4_enable = 0
Ct.4D_clk =0
= 1

REt.4_enable = 1
Ct.4D_CLK= 1
CLR_START = 1

REt.4_enable = 1
Ct.4D_clk = 1
CLR_START = 1

TL/F/10451-12

FIGURE 6. State Diagram of Rest Time Circuit
RAE = 0. Again WAIT_START = 1 and after another
ClK-OUT cycle the state machine moves to WAIT3.

STATE: WAin
In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 1, and if a remote access starts, IO_CHRDY is
driven low whenever RAE = 0. While in this state WAIT_
START remains equal to one because it has not been
cleared yet. Thus, after one ClK-OUT cycle the state machine moves to WAIT2.

STATE: WAIT3
In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 0 which clears WAIT_START, and IO_CHRDY
is driven low whenever RAE = 0. Since WAIT_START is
cleared, on the next rising edge of ClK-OUT the state machine will make a decision:

STATE: WAIT2
In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 1, and IO_CHRDY is driven low whenever
2-130

IF LCMD equals CMD (indicating no change in the value
of CMD between cycles) and a valid remote access has
started (Le., RAE = 0), then the state machine will move to
the RESUME state. (The RESUME state is covered after
the WAITS state.) However, if those conditions are not met
then the state machine moves to WAIT4.

»
z

module rescpal
flag '-r3'
title 'REST-TIME Compliance State Machine';

'p16r4';
"inputs:
c1ock,enab
!sys_reset
!rae
waicstart
!wr_pend
xack

STATE: WAIT4
In this state REM_enable = 0, CMD_clk
0, ClR_
START = 1, and IO_CHRDY is driven low whenever
RAE = O. If LCMD equals CMD and RAE = 0, then on
the next rising edge of ClK-OUT the state machine will
move to the RESUME state. Otherwise the state machine
moves to state WAIT5.

L cmd

cmd

STATE: WAITS

pin I,ll;
pin 2;
pin 3;
pin 4;
pin 6;
pin 7;
pin 8;
pin 9;

"outputs:
rem_enable pin 12;
pin 13;
c1cstart
q3,q2,ql,qO pin 14,15,16,17;
pin 18;
cmd_clk
pin 19;
I03hrdy

In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 1, and IO_CHRDY is driven low whenever
RAE = O. IF LCMD equals CMD and RAE = 0 then the
next state will be RESUME.
As long as the above condition is not met and WR-PEND =
0, the state machine will remain in this state. WR-PEND = 0
indicates that the previous access was a write with the BCP
in latched write mode. Holding the state machine at WAIT5
prevents remote accesses, that changes the value of CMD,
for the required latched write rest time.

=[q3,q2,ql,qO];
=rem_enable;

sreg'
outputs
"definitions:
ck,x,z,L,H
access
st

If both of the above conditions are false then the next state
will be WAIT6.

= .C., .X., .Z.,O,l;
= rae;

=[q3,q2,ql,qO];

"State Values ...

STATE: WAITS

idle
start
waitl
wait2
wait3
wait4
wait5
wait6
wait7
wait8
resume
hold
notusedl
notused2
notused3
notused4

In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 1, and IO_CHRDY is driven low whenever
RAE = O. If LCMD equals CMD and RAE = 0, then on
the next rising edge of ClK-OUT the state machine will
move to the RESUME state. Otherwise the state machine
moves to state WAIT7.
STATE: WAIT7
In this state REM_enable = 0, CMD_clk = 0, ClR_
START = 1, and IO_CHRDY is driven low whenever
RAE = O. Any remote access that has changed the value of
CMD will be prevented until the end of this state. That would
be a minimum of seven ClK-OUT cycles between accesses
or 371 ns if OClK = 1S.S696 MHz.
Also, all remote accesses which follow a latched write and
change the value of CMD have been prevented at least two
ClK-OUT cycles or 106 ns, if OClK = 1S.S696 MHz. Thus
after one ClK-OUT cycle, if RAE = 0 the next state will be
RESUME. Otherwise," it will be WAITS.

="bOlOO;
="bOllO;
="blllO;
="bll 11;
="bllOl;
="blool;
="blOll;
="blOlO;
="bl000;
="blloo;
="bOOOO;
="boolO;
="bOll 1;
="booll;
="bOlOl;
="bOOOl;

" 4h
" 6h
"Eh
"Fh
"Dh
" 9h
" Bh
" Ah
" 8h
"Ch
"Oh
" 2h
"7h
" 3h
" 5h
" lh
TLlF/l0451-14 .

FIGURE 7. PAL Program File
(Written In the ABEL Program Language)

STATE: WAITS
In this state REM_enable = 1, (allows accesses), CMD_ "
clk = 0, CLEAR_START = 1, and IO_CHRDY is driven low

2-131

N
CD

Z
<

r---------------------------------------------------------------------------------~

equations
enable outputs =1;
enable IO_chrdy =access;
!I03hrdy =( q3 * access) # (!q2 * access) # ( qO * access)
# (!xack) # (waicstart * access );
!clcstart = «q3) * (q2)
# (sys_reset);

* (!q1) * (qO»

cmd3lk =(access * !q3 * !q2 * !qO * !waicstart)
#(access * !q3 * q1 * !qO * !waicstart)
# (access * cmd_clk * !waicstart);
!rem_enable

=(!q2 * q3) # qO # (q 1 * q3) # waiutart;

state_diagram sreg;
State idle:
" Remain in idle while sys_reset is active.
IF (sys_reset) TIffiN idle;
ELSE IF (access) TIffiN start;
ELSE idle;
State start:
" Begin normal access.
IF (sys_reset) TIffiN idle;
ELSE IF (!access # waicstart) TIlEN wait1;
ELSE start;
State wait1:
"First wait cycle.
IF (sys_reset) TIffiN idle;
ELSE IF (access & L3md & cmd & !waiutart) TIffiN resume;
ELSE IF (access & !L3md & !cmd & !waiUtart) TIlEN resume;
ELSE wait2; .
State wait2:
IF (sys_reset) TIffiN idle;
ELSE IF (access & L_cmd & cmd & !waicstart) TIIEN resume;
ELSE IF (access & !L_cmd & !cmd & !waiUtart) TIlEN resume;
ELSE wait3;
State wait3:
IF (sys_reset) TIffiN idle;
ELSE IF (access & L_cmd & cmd & !waicstart) TIffiN resume;
ELSE IF (access & !L_cmd & !cmd & !waiUtart) TIffiN resume;
ELSEwait4;
TL/F/10451-15

FIGURE 7. PAL Program File (Written In the ABEL Program Language) (Continued)
whenever RAE = O. This state was included in the state
machine to reduce the state machine's logic. Otherwise it
would have been logical to return to the IDLE state from
WAIT? if RAE = 1 (no access in progress). If RAE = 0,
then the next state will be RESUME. Otherwise the state
machine returns to IDLE.
STATE: RESUME
In this state REM_enable = 1, CMD_clk = 1 (rising edge
of CMD_clk latches in the present value of CMD), CLR_
START = 1, and 10_CHRDY is driven low while RAE = O.
When the state machine moves to this state, it means that a
remote access took place quickly after the previous access.
The state machine has allowed the remote access to proceed. However, the state machine must have waited the
PC-bus for some period of time before entering this

state. As a result, the PC-bus should be waited until the
XACK signal can take over control of driving 10_CHRDY.
For the design of the CT-104, it was determined that once
REM_enable = 1, the XACK signal would take over control within two ClK-OUT cycles. So the state machine will
wait the PC-bus through this state and the next. On the next
rising edge of ClK-OUT the state machine will move to the
HOLD state.
STATE: HOLD
In this state REM_enable = 1, CMD_clk = 1, CLR_
START = 1, and 10_CHRDY is driven low while RAE = O.
Again, this state is provided to wait the PC-bus for a second
ClK-OUT cycle while still allowing remote access. The next
state is CYClLSTART. In CYCLE_START, XACK will
take over control of 10_CHRDY.

2-132

State wait4:
IF (sys_reset) TIffiN idle;'
ELSE IF (access & L_cmd & cmd & !waiutart) THEN resume;
ELSE IF (access & !L_cmd & !cmd & !waicstart) TIffiN resume;
ELSE waitS;
State waitS:
IF (sys_reset) TIffiN idle;
ELSE IF (access & L_cmd & cmd & !waicstart) THEN resume;
ELSE IF (access & !L_cmd & !cmd & !waicstart) THEN resume;
ELSE IF (wcpend) THEN waitS;
ELSE wait6;
State wait6:
IF (sys_reset) TIffiN idle;
ELSE IF (access & L_cmd & cmd & !waicstart) TIffiN resume;
ELSE IF (access & !L_cmd & !cmd & !waicstart) THEN resume;
ELSE wait7;
State wait7:
IF (sys_reset) TIffiN idle;
ELSE IF (access) TIffiN resume;
ELSE wait8;
State wait8:
IF (sys_reset) TIffiN idle;
ELSE IF (access) TIffiN resume;
ELSE idle;
State resume:
IF (sys_reset) TIffiN idle;
ELSE hold;
State hold:
IF (sys_reset) TIffiN idle;
ELSE start;
State notusedl:
IF (sys_reset) THEN idle;
ELSE wait2;
State notused2:
IF (sys_reset) TIffiN idle;
ELSEwait2;
State notused3:
IF (sys_reset) THEN idle;
ELSE wait2;
State notused4:
IF (sys_reset) THEN idle;
ELSE wait2;
end
TL/F/10451-16

FIGURE 7. PAL Program File (Written in the ABEL Program Language) (Continued)

•
I

2·133

REST-TIME Compliance State Machine
Equations for Module rescpal

Device REST_PAL

Device REST_PAL
!qO := (!qO & !ql
# !qO& !q2
# q 1 & !q2 & q3 & -wr_pend
# !L3md & !cmd & q3 & I-rae & !waiUtart
# L_cmd & cmd & q3 & !-rae & !waiUtart
# !-sys_reset
# !qO& !q3);

Reduced Equations:
enable rem_enable = (l);
enable IO_chrdy = (!-rae);
!I03hrdy = (!-rae & waiutart
# !xack
#qO& I-rae
# !q2 & I-rae
# q3 & I-rae);

TL/F/10451-18

!elcstart = (!-sysJeset # qO & !q 1 & q2 & (3);
!cmd_clk =(waicstart
# !cmd_elk & qO
# !cmd_elk & !q 1 & q2
# !cmd_elk & q3
#-rae);
!rem_enable = (waiUtart # q 1 & q3 # qO # !q2 & (3);
!q3 := (!qO & !q2 & !q3
# !qO& !ql & I-rae
# !L_cmd & !cmd & q3 & I-rae & !waiutart
#L_cmd &cmd&q3 & I-me & !waiutart
# !qO & !q3 & I-rae & !wait_start
# !-sys_reset
# !qO & !ql & q2);
!q2:= (!qO & !ql & !q2 & !q3 & -sys_rcset
# !ql & q3 & I-rae & -sys_reset
# q 1 & !q2 & q3 & -sys_reset
# qO & !q 1 & q3 & -sys_reset
# !L_cmd & !cmd & q3 & I-rae & -sysJeset & !wait_start
# L_cmd & cmd & q3 & I-rae & -sys_reset & !waicstart);
!ql := (!qO & Iql & q3
# !qO& !q2 &q3
#qO&q2&q3
# !L_cmd & !cmd & q3 & I-rae & !wait_start
# L_cmd & cmd & q3 & I-rae & !wait_start
# !qO & !q 1 & q2 & -rae
# !-sys_reset);

TLlF/10451-17

FIGURE 8. Reduced Equations for Rest Time State Machine PAL

2-134

»
z

National Semiconductor
Application Note 626
William V. Miller

DP8344 Timer Application

0)
I\)
0)

INTRODUCTION

The DP8344 is a communications processor which handles
IBM 3270, 3299 and 5250 protocols along with NSC general
8-bit protocol. In order to reduce the impact on the
DP8344's CPU the timer was designed to stand-alone and
count independently of the CPU.
The timer's circuitry includes a unique holding register. This
holding register can be loaded with a sixteen-bit countdownvalue, which will remain unchanged until a new value is
loaded or the DP8344 is reset.
When the timer counts to zero it takes two actions: 1) it sets
both the timer interrupt and the Time Out flag [TO], and 2)
the timer reloads the sixteen-bit countdown-value stored in
the holding register and continues the countdown cycle.
This demonstrates a significant advantage of the DP8344's
timer; the timer continues keeping accurate time while notifying the CPU that the timer has completed a cycle. The
timer does not wait for the CPU to service it, instead the
timer notifies the CPU of the completion of a cycle and allows the CPU to take the desired action when it has the
time.
With the use of the holding register, a multiple number of
timer cycles of the exact same duration can be performed
consecutively. The other major advantage of the holding
register is that it allows the interleaving of any number of
countdown-values. Loading the holding register with a new
countdown-value does not affect the countdown-value presently in the timer's countdown circuitry. In this way a countdown-value (call it A) can be counting down and the holding
register can be loaded with a new countdown-value (call it
B). When the value A reaches zero, both the timer interrupt
and Time Out flag [TO] are set, and the value B is loaded
into the countdown circuitry and starts its countdown. Then
the value A can be loaded back into the holding register
when the CPU has the time. This demonstrates how countdown-values with different durations can be interleaved and
once again how the timer does not have to wait to be serviced by the CPU, making both the timer and CPU more efficient.
The CPU can load the upper and lower bytes of the holding
register by writing the desired value to the CPU registers
{TAHI and {TALI respectively.
Control of the timer's countdown circuitry is maintained via
three bits in the Auxiliary Control Aegister {ACA I.
Timer STart [TST] (bit 7 of (ACAI) is the start/stop control
bit for the timer. Writing a one to [TST] starts the timer
counting down from the present value in the countdown circuitry. When [TST] is zero the timer stops and the timer
interrupt is cleared.
The second control bit is Timer LoaD [TLD] (bit 6 of
(AAC I). This bit allows the CPU to immediately load the
timer's countdown circuitry with the value in the timer's
holding register. This capability is required after the DP8344
is reset; the value in the timer's countdown circuitry will be
the reset value and not the desired value. CPU controlled
loading can also be used to load higher priority countdownvalues before a lower priority countdown is completed. The
5250 Protocol application implements the timer in this manner.

Writing a one to [TLD] will load the timers countdown circuitry with the value in the timer's holding register and initializes the timer clock in preparation to start counting down.
Upon completing the load operation [TLD) is cleared by internal hardware.
When the timer is loaded by writing a one to [TLD], the
timer is re-initialized to prevent the timer's circuitry from decrementing the newly loaded countdown-value prematurely.
By initializing the countdown circuitry after a CPU load, the
newly loaded countdown-value's duration will be accurately
measured. The reader should note that there is no way to
precisely measure the total elapse time of two or more
countdown-values if the CPU loads them (using [TLD)) into
the countdown circuitry. However, the error due to CPU
loading will be a maximum of one period of the timer for
each CPU load and can often be ignored if the countdown
values are large.
EXAMPLE:

countdown-value
= 1000
maximum count error = 1
maximum error

= 0.1 %

The last control bit is TiMer Clock select (bit 5 of (ACAI).
This bit determines the rate at which the countdown-value
will be decremented. When [TMC] is low, the timer decrements the countdown-value at one-sixteenth the CPU's
clock frequency. When [TMC] is high the rate is one-half the
CPU's clock frequency. The reader should note that the timer's decrement rate is based on the CPU's clock frequency,
which is controlled by CPU Clock Select [CCS] (bit 7 of
(DCA I). When [CCS] is low the CPU's clock frequency
equals the oscillator's clock frequency, and when [CCS] is
high the CPU's clock frequency equals one-half the oscillator's clock frequency.
The last portion of the timer's circuitry is a sixteen-bit output
register. This output register is loaded with the present value of the countdown-value in the countdown circuitry, at the
end of every execution cycle. This register is loaded even if
the timer is stopped.
The CPU can read the upper and lower bytes of this output
register by reading the CPU registers {TAHI and {TALI
respectively.
The reader should note that when the CPU reads and writes
to the registers {TAHI and {TALI the timer's circuitry accesses different registers. All writes will load the timer's
holding register and all reads will read the timer's output
register.
The count status of the timer can be monitored by reading
{TAL I and/or {TAH I. When the registers are read, the value in the timer's output register is presented to the CPU and
not the value in the input holding register. To read back
what was written to {TALI and {TAHI, the timer must be
loaded first, followed by a one instruction delay before reading {TALI and {TAHI to allow the output register to be
updated after the load operation. Figure 1 is a block diagram
of the Timer-CPU interface.

2-135

Ell
I

r-------~-------------------------------------------------------------------

CPU

:2:

0,
I\)
0')

lW_TIMER.BCP:

.SECf X

exx
MA,AB
; switch reg bank
PUSHP IZ
; save IZ
or
CCR_TO,CCR
; clear time out of timer
UMPBP RSTATE,lW_ TIMER_RESP,NS,tm_relti_c1k
;jump to real time clock counter
timer poll/activate read response timeout and offline response
timing
and -ACR_TST,ACR
move
TM_2IMS_HI,ACC

stop timer
prepare timer input
upper byte
move
ACC,lRH
; move, to TRH
move
TM_2IMS_LO,ACC
; prepare timer input
lower byte
m0 ve
ACC,1RL
; move to TRL
or
ACR_TST,ACR
; start timer
UMPBP
RSTATE,RX_RESPONSE_WAIT,S,tm_skip_tfe
; if offline response
timeout, skip tfe call
and
; unmask Tx interrupt
since interrupt expects
to be unmasked
; go handle response
via TFE interrupt
tm_skip_tfe:
UMPBP
RSTATE,lW_TO_PEND,S,tm_relti_c1k_1
; jump to real time clock
if interrupt pending
and -(lW_TIMER_RESPIRX_RESPONSE_WAIT),RSTA TE;
; reset poll response flag
; go check birq, do birq
if needed [V0.51
; real timer e10ck counter
tm_relli_clk_l:
and -(lW_ TlMER_RESPIRX_RESPONSE_W Am
lW_ TO]END),RSTATE
reset poll response, response
wait, and int pending FLAGS
tm_relli_e1k:
move DCPHI,IZHI
; setup IZHI
move
LOW(tw_sysa_por_cntO-I),ACC
; setup IZLO
move
ACc,mn
move
I,ACC
; set a 'I' for
later use
move [+IZ1,GP7
; get counter
cmp
GP7,TM_5SEC
; equal to 5.4sec?
jz
tm_nexCI
; yes, goto next session
without counter + I
adda GP7,[IZ]
; increment counter

.,
I

TL/F/104S0-S

FIGURE 3 (Continued)

2-141

tm_nexc1 :

move [+IZ),GP7
GP7,TM_5SEC
cmp
jz
tm_nexc2
adda

GP7,[IZ)

; get counter
; equal to 5.4sec?
; yes, goto next session
without counter + 1
; increment counter

tm_next_2:
move [+IZ),GP7
cmp
GP7,TM_5SEC
jz
tm_nexC3
adda

GP7,[IZ)

; get counter
; equal to 5.4sec?
; yes, goto next session
without counter + 1
; increment counter

tm_next_3:
move [+IZ),GP7
cmp
GP7,TM_5SEC
tm_next_4
jz
adda

GP7,[IZ)

; get counter
; equal to 5.4sec?
; yes, go to next session
without counter +1
; increment counter

tm_next_4:
move [+IZ),GP7
GP7,TM_5SEC
cmp
jz
tm_nexc5
adda

GP7,[IZ)

; get counter
; equal to 5.4sec?
; yes, goto next session
without counter + 1
; increment counter

tm_nexc5:
move [+IZ),GP7
GP7,TM_5SEC
cmp
tm_next_6
jz
adda

GP7,[IZ)

; get counter
; equal to 5.4sec?
; yes, goto next session
without counter + 1
; increment counter

tm_nexc6:
move [+IZ),GP7
GP7,TM_5SEC
cmp
tm_next_end
jz
adda

GP7,[IZ)

tm_nex t_end:
tm_check_birq:
Ijmp CCR,BIRQ,S,tm_no_birq
IcaH dca_fasCbirq
tm_no_birq:
POPP
IZ

UNl1XX
ret
RI,RFB

; get counter
; equal to 5.4sec?
; yes, goto next session
without counter + I
; increment counter

; following codes added
in [VO.5)
; check pending
birq
; yes, go do it
; restore Z

; unlock remote
; return with OlE, ALU flags
and reg bank restored

.end
TL/F/l0450-6

FIGURE 3 (Continued)

from a serial keyboard. The timer in this application is used
to read the serial keystroke dataword at the proper baud
rate. (Refer to Figure 4 for the actual BCP code used for this
application.)

DP8344 AS A SERIAL INPUT FROM A KEYBOARD
Introduction

To keep the cost of terminals low, the 3270 protocol was
designed to place all of the intelligence of the system in the
cluster controller while all of the memory remained in the
terminal. In this protocol the terminal is responsible for recording all keystrokes until the cluster controller can poll the
terminal and process the keystroke data.

Description

The specifications for the serial dataword produced by the
serial keyboard and read by the DP8344 are as follows: it is
1) asynchronous, 2) ten bits long (1 startbit, 8 databit with
the most significant bit first, and 1 stopbit), and 3) transmitted at 1200 baud. When no serial data is being transmitted

With that in mind this application uses the timer along with
the BIRO interrupt pin as a serial port to read in keystrokes

2-142

the serial data line will be held high. The start bit will be a
zero to indicate the beginning of the serial bit string.

Once the value of the keystroke dataword has been calculated it is transferred to data memory and the temporary
register is cleared so that the next keystroke value may be
calculated there. The following is a more detailed description of this process, starting in the middle of the start bit.

As mentioned in the introduction, the serial data line from
the keyboard is connected to the BIRO interrupt pin (Pin 53
on the OP8344). The BIRO interrupt pin acts as the serial
port through which the serial keystroke dataword is read
into the OP8344.

After eight more timer interrupts the middle of the first and
most significant data bit is present at the BIRO pin. So the
software unmasks the BIRO interrupt. If a zero is present at
the BIRO pin, the software calls the BIRO interrupt service
routine. The BIRO interrupt is masked off and nothing is
added to the value in the temporary register. After masking
off the BIRO interrupt the software returns to perform other
operations. On the other hand, if the value at the BIRO pin
is a one, the BIRO interrupt is masked off and the value 80
(Hex) (Most Significant Bit) is added to the value (initially 00
(Hex)) in the temporary register.

First, BCP software programs the timer to determine the
baud rate at which the OP8344 will read the serial dataword
presented at the BIRO pin. The timer is pre-configured to
divide the CPU clock by two (Le., [TMC] = 1) with the CPU
clock set equal to the oscillator clock at 18.8696 MHz (Le.,
[CCS] = 0). The time out value of 0307 (Hex) is loaded into
the timer's holding register via (TRLI and (TRH I. The time
out value of 0307 (Hex) corresponds to 0.104188748 ms or
approximately one eighth of 0.833333 ... ms, which is the
period of one bit at 1200 baud. After the holding register is
loaded, the timer is loaded but not started. Both the timer
and BIRO interrupts are unmasked and enabled. Now the
OP8344 is ready to read an asynchronous, ten bit long serial
keystroke dataword at 1200 baud via its BIRO interrupt pin.
After the timer is configured the OP8344's software can perform other operations until a zero on the serial data line
activates the BIRO interrupt (Note: the BIRO interrupt is active low). The software then jumps to a BIRO interrupt service routine. The service routine will mask off the BIRO interrupt and start the timer and then return to perform other
operations. After four consecutive timer interrupts the middle of the startbit should be present at the BIRO pin. To
ensure that a glitch or noise did not produce a zero momentarily and that the zero is actually a startbit, the BIRO interrupt is unmasked. If the value at the BIRO pin is a one
instead of a startbit zero, the timer is stopped and reloaded
with the countdown-value 0307 (Hex). The BIRO interrupt
will remain unmasked waiting for the next zero. However, if
the value at the BIRO pin is a zero (indicating a valid startbit), the software jumps to the BIRO interrupt service routine. The BIRO interrupt is masked off and the timer continues to run and the software returns to perform other operations.

Likewise, after eight more timer interrupts the middle of the
second serial databit is present at the BIRO pin. So the
BIRO interrupt is unmasked and goes through the same
procedure as above to decide if 40 (Hex) should be added
to the value in the temporary register. Similarly this method
will continue for the next six data bits. After the least significant bit has been evaluated, the value in the temporary register is moved to data memory. The reader should realize
that this value can also be stored in another register if desired. Then the temporary register is cleared so that the
next keystroke value can be recorded there.
The software continues to mask off the BIRO interrupt until
the end of the stopbit. At the end of the stopbit the timer is
stopped and the time out value 0307 (Hex) is loaded into
the timer. The BIRO interrupt is unmasked to wait for the
next start bit zero.
This application has demonstrated how the timer and the
BIRO input/output pin can be used as a serial input. However there should be a note of warning that a production program should sample the serial input signal more than once
every bit-time to guarantee valid data at a given baud rate.
Furthermore, the software for the OP8344 must guarantee
that the timer and/or BIRO interrupts are not masked off by
higher priority interrupts for too great a time; this could delay
the sampling of the serial input signal for more than a bittime, resulting in invalid data being read.

For the case of a true startbit the OP8344 needs to read in
the value of the serial keystroke dataword. The value of
each data bit must be read one at a time. After each value is
read, it is added to a temporary value stored in a register.

2-143

~------------------------------------------------------------------~

C\I

;-----------------------------------------------------------------------

This program will receive serial data using the BIRQ pin as
a serial. input pin.
The timer will be used to detennine when the middle of a bit
is present at the BIRQ pin. Then the value of the bit is sampled
with the use of the BIRQ interrupt along with software to decide
if the bit is a one or a zero. Then the software takes the
appropriate action for each case.
In this program all keystoke values are stored in consecutive
memory locations.

****** National Semiconductor Copyrightl988 *****
,----------------------------------------------------------------------stdequ.hdr"
.input
II

.sect x

CODE:
initialization:
exx
move
move
exx
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move

AA,AB,DI
SFh,DCR
02h,IBR
MA,MB,DI
OE7h,ICR
lO,IWLO
OO,IWHI
O,IX
O,GPO
O,GPl
O,GP2
O,GP3
O,GP4
O,GPS
GPS,IZLO
l,GP6
GP5,IZHI
80h,GP7
GP7,[IZ+2]
40h,GP7
GP7,[lZ+3]
20h,GP7
GP7,[IZ+4]
lOh,GP7
GP7,[IZ+S]
08h,GP7
GP7,[IZ+6]
04h,GP7
GP7,[IZ+7]
02h,GP7
GP7,[IZ+8]
Olh,GP7
GP7,[IZ+9]
OD7h,GP7
GP7,TRL
03h,GP7

;set CPU-CLK equal to OCLK
;set up interrupts
;unmask timer and BIR interrupts
;clearIW
;clearIX
;clear temporary registers

;load IZ with
;base address in data memory
;for bit constant values
;storing constants for
; the most significant bit
; bit6
; bit S
; bit4
; bit 3
; bit 2
; bit 1
; the least significant bit
;load timer's holding register
;with count down value
TL/F/10450-7

FIGURE 4

2-144

z
a,

move GP7,TRH
;load timer
move 61h,ACR
;END of initialization

back:
cmp
jz
cmp
jz
cmp
jnz
move
jmp

GPO,O
back
GPO,O
back
GPl,O
nexcl
O,GP2
nexc2

move
move
move
adda
cmp
jnz
move
move
move

OEFh,ICR
GPl,GP4
[IZ+AJ,GP4
GP5,GP5
GPl,9
next 2

;waiting for BIRQ interrupt
;protection
;Is this a true start bit?
;NO, then clear GP2

nexcl:
;mask off the BIRQ interrupt
;load value of present bit
;add value of present bit
;Is this bit O?

GP5~[IW+J

;YES, store byte of imfonnation
;clear temporary registers

O,GP5
O,GP6

nexc2:
move O,GPO
Ijmp back
;Timer Interrupt Service Routine

,.*******************************
tm:

or
cmp
jnz
add
cmp
jnz
move
move
move
move
move
move

80h,CCR
GP6,O
nexclO
l,GP3
GP3,14h
nexcll
60h,ACR
O,GPI
O,GP2
O,GP3
l,GP6
OE7h,ICR

ret

cmp
jnz
add
cmp
jnz
move
move
move

GPl,O
nexc12
l,GP3
GP3,4
nexc13
l,GPO
O,GP3
OE7h,ICR

ret

;clear [TO] flag
;Is GP6 = O?
;loop until the stop
; bit has passed
;stop and load timer
;clearGPl
;clearGP2
;clearGP3
;set GP6 = 1
;unmask the BIRQ interrupt

nexcll:
nexcl0:
;Is this the start bit?
;YES, add one to GP3
;Is it the middle of the
;start bit?
;YES, set GPO = 1
;clearGP3
;unmask BIRQ interrupt

nexc13:
TL/F/10450-8

FIGURE 4 (Continued)

2-145

z
jmp

loop

;Timer interrupt selVice routine

,.*******************************

dest:

nexcl:

nexC2:

nexc3:

CODE:

or
add
cmp
rnz
move
move
add
cmp
jnz
move
move
rnz
move
add
cmp
jnz
move
move
move
rnz
move
add
cmp
jnz
move
move
move
rnz
move
add
move
move
ret

80h,CCR
1,IWLO
IWLO,32h
RI
O,IWLO
[IZ+40h] ,IXLO
1,IXLO
IXLO,3Ch
nexcl
O,IXLO
IXLO,[lZ+40h]
RI
[IZ+30h],IXLO
1,IXLO
IXLO,3Ch
nexc2
O,IXLO
IXLO,[IZ+30h]
O,IXLO
RI
[IZ+20h],IXLO
1,IXLO
IXLO,18h
nexc3
O,IXLO
IXLO,[lZ+20h]
O,IXLO
RI
[IZ+ 1Oh],IXLO
1,IXLO
IXLO,[IZ+ 10h]
O,IXLO
RI

;c1ear [TO] flag
;increment IW
;does IW =50 decimal
;NO, then return with interrupt on
;c1earIW
;YES, then increment IX
;does seconds =60
;YES, then clear seconds
;move seconds to data memory
;increment minutes
;does minutes =60
;YES, then clear minutes
;move minutes to data memory

;increment hours
;does hours =24
;YES, then clear hours
;move hours to data memory

;increment days

.sect ax
.org 114h
Ijmp dest
.END
TL/F/10450-13

FIGURE 7 (Continued)

II
I

2·151

U)
,....

Lt)

PHASE-A
.--------+......------c:::::::>PHASE-B
~-~~~~---~~~~

SHIELD eND

~-ACT

-0.

, PWR-COOD

TERMINATE

5Ull

1:;

54.911

1:;

10K

820K

33pF

10"-9

L> NRZI-DAT

" 1 '. . . . . . .

TLIF/9635-5

FIGURE 5_ Schematic

2-154

nominally 29 mV ± 20%. This value allows the steady state,
worst case signal level of 100 mV 66% of its amplitude
before transitioning.

The current mode drive method used by native twinax devices has both distinct advantages and disadvantages. Current
mode drivers require less power to drive properly terminated, low-impedance lines than voltage mode drivers. Large
output current surges associated with voltage mode drivers
during pulse transition are also avoided. Unwanted current
surges can contribute to both crosstalk and radiated emission problems. When data rate is increased, the surge time
(representing the energy required to charge the distributed
capacitance of the transmission line) represents a larger
percentage of the driver's duty cycle and results in increased total power dissipation and performance degradation.

To achieve this, a differential comparator with complementary outputs can be applied, such as the National LM361.
The complementary outputs are useful in setting the hysteresis or switching threshold to the appropriate levels. The
LM361 also provides excellent common mode noise rejection and a low input offset voltage. Low input leakage current allows the design of an extremely sensitive receiver,
without loading the transmission line excessively.
In addition to good analog design techniques, a low pass
filter with a roll-off of approximately 1 MHz should be applied to both the A and B phases. This filter essentially conducts high frequency noise to the opposite phase, effectively making the noise common mode and easily rejectable.

A disadvantage of current mode drive is that DC coupling is
required. This implies that system grounds are tied together
from station to station. Ground potential differences result in
ground currents that can be significant. AC coupling removes the DC component and allows stations to float with
respect to the host ground potential. AC coupling can also
be more expensive to implement.

Layout considerations for the LM361 include proper bypassing of the ± 12V supplies at the chip itself, with as short as
possible traces from the pins to 0.1 J.LF ceramic capacitors.
USing surface mount chip capacitors reduces lead inductance and is therefore preferable in this case. Keeping the
input traces as short and even in length is also important.
The intent is to minimize inductance effects as well as standardize those effects on both inputs. The LM361 should
have as much ground plane under and around it as possible. Trace widths for the input Signals especially should be
as wide as possible; 0.1 inch is usually sufficient. Finally,
keep all associated discrete components nearby with short
routing and good ground/supply connections.
'

Drivers for the 5250 environment may not place any signals
on the transmission system when not activated. The poweron and off conditions of drivers must be prevented from
causing noise on the system since other devices may be in
operation. Figure 5 shows a "DC power good" signal enabling the driver circuit. This Signal will lock out conduction
in the drivers if the supply voltage is out of tolerance.
Twinax signals can be viewed as consisting of two distinct
phases, phase A and phase B, each with three levels, off,
high and low. The off level corresponds with 0 mA current
being driven, the high level is nominally 62.5 mA,
+20%-30%, and the low level is nominally 12.5 mA,
+20%-30%. When these currents are applied to a properly terminated transmission line the resultant voltages impressed at the driver are: off level is OV, low level is 0.32V
± 20%, high level is 1.6V ± 20%. The interface must provide for switching of the A and B phases and the three
levels. A bi-modal constant current source for each phase
can be built that has a TTL level interface for the BCP.
An integrated solution can be constructed with a few current
mode driver parts available from National and Texas Instruments; The 7511 OA and 75112 can be combined to provide
both the A and B phases and the bi-modal current drive
required as in Figure 5. The external logic used adapts the
coax oriented BCP outputs to the twinax interface circuit,
and prevents spurious transmissions during power-up or
down. The serial NRZ data is inverted prior to being output
by the BCP by setting TIN, {TMR[3] J.

Design equations for the LM361 in a 5250 application are
shown here for example. The hysteresis voltage, Vh, can be
expressed the following way:
Vh = Vrio + ((Rin/(Rin + RI) x Vol)
- (Rin/(Rin + RI) x Vol))
where
Vh -

Hysteresis Voltages, Volts

Rin - Series Input Resistance, Ohms
RI -

Feedback Resistance, Ohms

Cin -

Input Capacitance, Farads

Vrio- Receiver Input Offset Voltage, Volts
Voh- Output Voltage High, Volts
Vol - Output Voltage Low, Volts
The input filter values can be found through this relationship:
Vcin = Vin1 - Vin2/1 + jwCin (Rin1
where Rin1 = Rin2 = Rin:
Fro = W/21T

RECEIVER CIRCUITS

The pseudo-differential mode of the twinax signals make
receiver design requirements somewhat different than the
coax 3270 world. Hence, the analog receiver on the BCP is
not well suited to receiving twinax data. The BCP provides
both analog inputs to an on-board comparator circuit as well
as a TTL level serial data input, TTL-IN. The sense of this
serial data can be inverted by the BCP by asserting RIN,
{TMR[4]J.

+ Rin2)

Fro = 1/(21T X Rin X Cin)
Cin = 1/(21T X Rin X Fro)
where
Vin1, Vin2- Phase A and B signal voltages, Volts
Vcin

Voltage across Cjn, or the output of the filter,
Volts

Rin1, Rin2- lnput resistor values, Rin1 = Rin2, Ohms
Fro
- Roll-Off Frequency, Hz
W
- Frequency, Radians

The external receiver circuit must be designed with care to
ensure reliable decoding of the bit-stream in the worst environments. Signals as small as 100 mV must be detected. In
order to receive the worst case signals, the input level
switching threshold or hysteresis for the receiver should be

2-155

»
z
I

U1
-"

CD
orLI)

:2:

.....

CD
'9'-

Lt)

z•

setup. This vectors to code that refills the FIFO and re-enabies that interrupt again, if needed. This operation must be
carried out before the transmitter is finished the last frame in
the FIFO or the message will end prematurely.

RECEIVER INTERRUPT

The receiver interrupt algorithm handles any or all seven
addresses possible on the twinax line. The same code is
used for each address by utilizing a page oriented memory
scheme. Session specific variables are stored in memory
pages of 256 bytes each. All session control pages, or
SCPs are on 256-byte even boundaries. By setting the high
order byte of a BCP index register to point to a particular
page or SCP, the low order byte then references an offset
within that page. Setting up data memory in such a way that
the first SCP begins at an address of B # xxxx xOOO 0000
0000 further enhances the usefulness of this construct. In
this scheme, the high byte of the SCP base pointer can be
used to set the particular SCP merely by summing the received or selected address into the lower three bits of the
.
base register.

The last frame transmitted must contain the EOM delimiter.
It can be loaded into !TCRI and data into !RTRI while the
transmitter is running without affecting the current frame. In
other words, the transmit FIFO is 12 bits wide, including
address and parity with data; the address field is clocked
along with the data field. In this way, multi-byte response
may be made in efficient manner.
ERROR HANDLING

In 5250 environments, the time immediately after the end of
message is most susceptible to transmission errors. The
BCP's receiver does not detect an error after the end of a
message unless transitions on the line continue for a complete frame time or resemble a valid sync bit of a multiframe transmission. If the twinax line is still active at the end
of what could be an error frame, the receiver posts the
LMBT error. For example, if noise on the twinax line continues for up to 11 p,s after the three required fill bits, the
receiver will reset without flagging an error. If noise resembles a start bit, the receiver now expects a new frame and
will post an error if a loss of synchronization occurs. If the
noisy environment is such that transitions on the receiver's
input continue for 11 p,s, or the receiver really has lost sync
on a real frame, the error is posted.
Basically, the receiver samples [LA] in addition to the loss
of synchronization indication to determine when to reset or
to post an error. After a loss of synchronization in the fill bit
portion of a frame, if the [LA] flag's time-out of 2 p,s is
reached prior to the end of what could be the next frame,
the receiver will reset. If the transitions prevent [LA] from
timing out for an entire 11 p,s frame time, a LMBT error is
posted. This method for resetting the receiver is superior in
that not only are the spurious loss of mid bit errors eliminated, the receiver performs better in noisy environments than
other designs.

NORMAL OPERATION

In normal operation, the configuration described thus far is
used in the following manner: After initializing the registers,
data structures .are initialized, and interrupt routines should
be activated. This application utilizes the receiver, transmitter, timer, and bi-directiorial interrupts. Since (lBRlis set to
H#1F, the interrupt table is located at H#1FOO. A LJMP to
the receiver interrupt routine should be installed at location
H # 1F1 04, the transmitter interrupt vector at H # 1FOS, the
BIRO interrupt vector at H#1F10, and the Timer interrupt
vector at H # 1F14. Un-masking the receiver interrupt and
BIRO at start up allows the device to come on-line.
When interrupt by the receiver, the receiver interrupt service
routine first checks the [ERR] flag in ! TSR [B5] I. If no errors have been flagged, the received_EOM flag is either
set or cleared. This is accomplished by comparing ! TSR
[BO-2]1 with the B # 111 EOM delimiter. A test of the selected flag, ! GP5' [B7] I determines if any of the active addresses are selected. Assuming that the system is just coming on line, none of the devices would be selected. ·U the
frame is addressed to an active device, the SCP for that
device is set, and the command is parsed. Parsing the command sets the appropriate state flags, so that upon exiting,
the interrupt routine will be prepared for the next frame.
Once parsed, the command can be further decoded and
handled. If the command is queue-able, the command is
pushed on the internal command queue, and the receiver
interrupt routine exits. If the command requires an immediate response, then the response is formulated, the timer
interrupt is setup, and the routine is exited.
The timer interrupt is used in responding to the host by waiting an appropriate time to invoke the transmit routine. The
typical response delay is 45 ± 15 p,s after the last valid fill
bit received in the command frame. Some printers and terminals are allowed a full 60 ± 20 p,s to respond. In either
case, simply looping is very inefficient. The immediate response routine simply sets the timer for the appropriate delay and unmasks the timer.

SUMMARY
The IBM 5250 twinax environment is less understood and in
some ways more complex than the 3270 environment to
many developers. This application note has attempted to
explain some basics about twinax as a transmission medium, the hardware necessary to interface the DPS344 to that
medium, and some of the features of the BCP that make
that task easier. Schematics are included in this document
to illustrate possible designs. Details of the twinax waveforms were discussed and figures included to illustrate
some of the more relevant features. Also, some different
software approaches to handling the transceiver interface
were discussed.
REFERENCES

5250 Information Display to Systeml36. and Systeml38
System Units Product Attachment Information, IBM, November 19S6.
Transmission Line Characteristics, Bill Fowler, National
Semiconductor Application Note AN-10S.
Basic Electromagnetic Theory, D.T. Paris, F.K. Hurd
McGraw-Hili Inc., 1969.

In the transmit routine, the data to be sent is referenced by
a pointer and an associated count. The routine loads the
appropriate address in the three LSBs of !TCRI. and writes
the data to be sent into! RTR I. This starts the transmitter. If
the data count is greater than the transmit FIFO depth
(three bytes), the Transmit FIFO Empty interrupt [TFE] is

2-160

»
z

APPENDIX A: EXAMPLE CODE

The following code was assembled with the HILEVEL assembler. Table II shows the correlation between HILEVEL mnemonics
and the mnemonics used in National data sheets for the DP8344V.

U1
~

TABLE II

HILEVEL

National Semiconductor

MOVE
LD
ST
LDAX
STAX
LDNZ
STNZ
LDl
STl

t10VE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

Rs,Rd
F't r , Rd { , Md e}
Rs,F'tr{,Mde}
F'tr,Rd
Rs,F'tr
n,Rd
Rs,n
n,Rd
n,F'tr

Rs,Rd
EmIr J , Rd
Rs, EmIr J
Elr + AJ ,Rd
Rs,Elr + AJ
EIZ + nJ ,rd
rs,EIZ + nJ
n,rd
n,ElrJ

ADD Rs,Rd
ADDRI Rs,F'tr{,Mde}
ADDl n,Rsd

ADDA Rs,Rd
ADD A Rs, EmIr J
ADD n,rsd

ADC Rs,Rd
ADCRI Rs,F'tr(,Mde}

ADCA Rs,Rd
ADCA Rs, EmIr]

SUBT Rs,Rd
SUBRI Rs, F'tr (, Mde}
SUBl n,Rsd

SUBA Rs,Rd
SUBA Rs,EmIrJ
SUB n ,r-sd

SBC Rs,Rd
SBCRI Rs,F'tr{,Mde}

SBCA Rs,Rd
SBCA Rs, EmIr]

AND Rs,Rd
ANDRI Rs,F'tr(,Mde}
ANDI n,Rsd

ANDA Rs,Rd
ANDA Rs, EmIr]
AND n,rsd

Rs,Rd
OR
ORRI Rs,Ptr{,Mde}
ORI n,Rsd

ORA
ORA
OR

XOR Rs,Rd
XORRI Rs,F'tr(,Mde}
XORI n,Rsd

XORA Rs,Rd
XORA Rs, emIr J
XOR n,rsd

Rs,Rd
Rs, EmIr]
n,rsd

CMF'

Rs,n

CMF'

rs,n

CPL

Rsd

CF'L

Rsd

BIT

Rs,n

BIT

rs,n

SRL
SLA
ROT

Rsd,n
Rsd,n
Rsd,n

SHR
SHL
ROT

Rsd,b
Rsd,b
Rsd,b
TLIF/9635-9

II
2-161

U) r------------------------------------------------------------------------------------.
....
a.n

JMP
LJMP
JMPR
JMPI
JRMK
Jt1PB
JMPF

JMP
LJMP
JMP
LJMP
JRM.<
LJMP
JMP
Jcc

n
n
Rs
Ptr
Rs,n,m
Rs,s,p,n
s,f,n

nn
F~s

UrJ
Rs,b,m
Rs,p,s,nn
f,s,n
n
- opt. syntax for JMP f-

CALL n
LCALL n
CALLB Rs,s,p,n

CALL r,
LCALL
LCALL

RET {g{,rf}}
RETF s,f{,g{,rf}}

{g {,rf}}
RETF f,s,{,{g}
{g o[,rf}}
Rcc

EXX

Rs,p,s,nn

F~ET

EXX

a,b{,g}

{,r-f}}

-: opt. !.;ynta:·: -

ba,bb,{,g}

TRAP n {,gU}

TRAP no[, g}

Tab l~:l 2.
Addr

Line
1

2
3
4
5
6
7
9
9
10
11
12
13
14
15
16
17
19
19
20
21
22
23
24
25
26

.REL
TAB
B
WIDTH 132
LIST
S,F
TITLE RXlNT
;----------------- ---------------------------------------------------RUNT· 9/21/87
pseudo tode
;
;boal
jbyte
jbyte
jbaol

selected;
seladdrj
luItitount;
activated;

station is selected
1* address af selected station
'*nulber af frales in this luI ti
It tOlland has been activated

data;
rx.eolll;
Ita;

1* data star age
It recei ved EDI!
If line turn araund flag

;rxinto
jbyte
;baol
jbaal
j{

if (errarl

if (lagerrar () == true I return;

1* recei ver errors

)

else {
if (TSR == ED"I rx.eal = true;
else rx.eoll = false;

It set received EO" flag

if (!selectedl {
TLIF/9635-10

2·162

if (!rx_eoll
seladdr : !TSR f EO~);
I l = (SCPBASE + seladdrl; /f set SCP to appropriate session -/
data: rtr;
else {
proto_error (); I' should not get here
reset_xcvr (I;
return II;

33
34
35
36
37

)

39
40

else {
reset_xcvr II;
return II;

41
42

if (lIuHifralle) (
If adivate llrite, etc ...
lulticount = parseldata)j /f set nUlber of frales 1/
seleded = truej
/f ani y lIay to select f/
queue Idata) ;

49
49

else {

44
45
46

)

50
51

52
53
54
55
Addr

/f not of interest

}

--43

/ f not luI ti
, if ((var = single_decodeldata)) == queable)
queue (datal;
else if (var == illedl illediate Idatal j

else {
1Z = (SCPBASE + seladdr I;

selected

Li ne RUNT

data = rtr

57
5B
59

60
61
62
63
64
65
66
67
6B

69
70
71
72

73
74
75
76
77
78

»z

if Cacti vel {

29
30
31

,. in the liddle of translission

if (acti vatedl {

act_data(datal;
if (rx_eol) {
selected = false;
activated = false;

end of lessage

}

return () ;
}

if Clulticount > 0)
queue(data) ;
if (luI ticount-= 0)
if (n_eol) selected = fal se;
)

else {
if (luHifrue) (

luHicount = parse Idata);
queue (data);
)

else {
if ((var = singleJecodeldatall == queablel
queue(datal;
TL/F/9635-11

2-163

U1
-I.

~
.....
Lt')

r---------------------------------------------------------------------------------else if ('/ar == i.led) imllediateldata);
if Irx_eolll) selected = false;

:2:

BO
Bl

c:r::

B2
83
84
B5
86
B7

return I);

; logerror ()

89
90

91
T2
93
94

95
96
97
9B
99
100
101
102
103
104
105
lOb
107
lOB
109
110

Addr

}

; boal resul tj
s"itch lerror _typel
case RDIS:
result = errJdisl)j
break;
case 1MBT:
result = err )Ibt II;
break;
case PARR:
result = err _parr II ;
break;
case OVF:
result = err _ovf () j
break;
defaul t:
result = err _unknolln ();
break;

'If receiver diabled while active

/f loss of midbi terror

/f pari ty error

/f recei ver FIFO overrun

/* strange error handler

return Iresul t) j

Line RUNT
111
112
113
114
115
116
117

11B
119
120
121
122
123
124
125
126
127
12B

jerr )lbtO
j{

if I!DA &Ie !selected
else {
log ();
return (true) j

1I~

!delayllAIl returnlfalselj /* delay of 6 usee
1* bump error counters
/f adlli t defeat

; --------------------------------------------------------------------nale:
RXlNi
recei ver interrupt handler
descri ption:
recei ved datu. is sent to other routines thru gp7'
SCP is set appropriately in lZ
SP5P - active addresses: bits 0-6
. selected flag: bit 7
6P6P - lultieount:
bit 7-6
unused:
bi t 5
TlIF/9635-12

2-164

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
00000
00000
00001
00002
00003
00004
00004

IC:"'I
.N

AEE8
D500
CCOO
D900
D900
B078

00005 FI6S
00006 307B
00007 DODO

bi t 4
bi t 3
bi ts 2-0

Oil interrupt, GP5', GP6'
ACC' ,SP7' ARE DESTROYED
tjq 9/16/87 create

entry:
exit:
hi story:

--------------------------------------------------------------------PUBLIC RCVRINT

5ELERR:
RXEDI'I:
EOI'I:
MULTI:
SELECT:
LTA:
CFLAS:

EXTRN
EHRN
EXTRN

PARSE, QUEUE, I ~~EDECODE, RESXCVR
I'll DERRL, I'll DERRH, OVFERRL, OVFERRH, PARERRL, PARERRH
RXERRL ,RXERRH ,R5PCTL ,RSPCTH ,8flSE5CP, IESERRL, IESERRH

EQU
EQU
EQU
EQU
EQU
EQU
EQU

8101000000
BI0000I000
BIOOOOOlll
8111000000
8110000000
ell01
8100000010

; sel ect the error regi ster
j rxeoll flag
i EOM deliileter
; multi count
; selected flag

EXX

/'\A,AB,DI

; 5ET APPROPRIATE BANK

JI'IPF
CALL
JI'IPF

NS, RERR, NOERROR
RXERROR
; ERROR IN FRAME
5, C, EXIT
; ABORT

LDI
AND

EOH,ACC
TSR,SP7

; LOAD MASK
; FORM ADDRESS

CMP

GP7, EO 1'1

; TEST

JI'IPF

NS,Z,CIRXINT

i IF NOT EQUAL, JUMP

ORI
JHP

RIEOI'I, GP6
C2RXINT

; ELSE SET EOI'I FLAG

ANDI

RXEOM* ,6Pb

; CLEAR IT

; CARRY FLAG

RCVRINT:

NOERROR:

Line RXINT

Addr
00008
00009
OOOOA
OOOOA

154
154
155
156
157
158
159
160
160
161
161
162

acti vated:
rx_eoll flag:
seladdr:
6P7P - received data

50BA
cavo
C800
4F7A

OOOOB
00008 8DE9
OOOOC 0000

163
164
165
101:
167
168
169
170
171
171
171
172
173

CIRXINT:

;
; DECIDE IF WE'RE ALREADY SElECTED

;
C2RXINT:
JI'IPB

6P5,S,B7,DEVSELECT ; IF ALREADY SELECTED

;
; NOT SELECTED ... DECIDE IF ADDRESS IS ACTIVE, IE; VALID FOR US
TLIF/9635-13

2-165

....CD

it)

Z
U1
.....

Line RUNT

OOOSE BCOB
0005F 0000
00060 CEeJ
00061 ~OOO
00062 CEBO
00063 0000
00064 CBOO

00065
00065 CEBO
00066 0000
00067
0006B
00069
0006A

BC6A
0000
47F9
47F9

0006A
0006B
0006C
0006C

CEBO
0000
0000
AFBO

0006D
0006D 5406
0006E FD64
0006F 4BF 6
00070 BD2D
00071 0000
00072 BD6D
00073 0000

265
265
265
266
266
266
267
267
267
26B
269
270
271
272
273
273
273
274
274
274
275
276
277
277
277
27B
279
290
2Bl
2B2
2B3
2B4
2B5
2B6
2B7
2BB
2B9
290
291
292
293
294
294
295
296
296
296
297
297
297
299

JIIPB

SP7,NS,BO,SINGLE; IF NEW COIIIIAND IS NOT IIULTI,

LCALL

PARSE

; IS IIUL TI, SET COUNT

LCALL

QUEUE

; PUSH ON QUEUE

; QUIT, TIL NEXT FRAIIE
JIIP
EXIT
;
; NEil COIIIIAND IS SINGLE ANDIOR NEEDS IIIIIEDIATE RESPONSE

;
SINGLE:
; SINGLE ••• SO DO IT

LCALL

IIIIIEDECODE

JIIPB

6P6,NS,B3,EXIT ; IF NOT EOII •••

ANDI

SELECT f ,6PS

; CLEAR SELECTED BIT

LCALL

RESXCYR

RET

RI,RF

; RETURN GRACEFULLY

RSTRX:
RESET, CLEAR DATA OUT

EXIT:

;--------------------------------------------------------------------RXERROR
nne:
description:
recei ver ERROR handl er
entry:
exi t:
hi story:

;

DA + ERR interrupt, SPS', GP6'
ACC' ,GP7' ARE DESTROYED
tjq 9/16/B7 create

---------------------------------------------------------------------

j RECEIVER ERROR HANDLER
;
RXERROR:
SELERR, TeR
ORI
RTR,SP7
110YE

; SET ECR BIT
j SET ERROR TYPE

ANDI
JIIPD

SELERRt, TCR
; RESET TCR
GP7,S, 81 ,LIIBTERRj LOSS OF IIID8IT

JI1PB

GP7,S,B3,PARERR; PARITY

JI1PB

SP7, S, 84, OYFERR ; OYER FLOW
TLIF/9635-17

•
I

2-169

CD
,....
I.t)

Z
c(

00074
00075
00076
00076

BDBB
0000
0000
BOOB

Addr

00079 BDE9
0007A 0000
0007B ceoo
BCAI
0000
0000
BOOB
CBOO
CBOO.
BOOB
CBOO
CBOO
B008
B008

000B3 E212
000B4 BOIB
00085 COCA
000B6 A04A
000B7 0100
OOOBB COCA
000B9
OOOBA
OOOBB
OOOBD
oooac
OOOBC
OOOaD

ILLEGAL:
LDI

ILLEGAL, ACC

; WHAT ERROR IS THIS?

JI!P

BUI!PERR

; SHOULD NOT GET HERE!!

JI!PF
JI!PB

; if DA, THEN NO ERROR
S,DA,CLEARC
GP5,S,B7,LOSIT ; IF SELECTED, POST

CALL
JI1PB

; DELAY FOR 6 USEe
SOLY
NCF,NS,B5,CLEARC; IF NOT ACTIVE - DISCARD, ELSE POST

LDI
JI1P

I!IOERRL,ACC
BUI1PERR

; LOSS OF I!IDBIT
i INCREMENT CoUtlTER

LDI
JI!P

PARERRL ,ACC
BUI1PERR

LDI

OVFERRL, ACC

; OVERFLOW ... VERY BAD!

ADD

ZLO, YLO

; FORI! NEW POINTER

LDI
LD

HIOl,ACC
PTRY,GP6

ADORI

GP6,PTRY,POSTD i ilRITE OUT NEil

JI!PF
LD

NS,C,RXEIIT
PTRY,GP6

ADDRI

6P6,PTRY

ORl

CFLA6,CCR

Line RUNT

00077 CBOO
0007B CBOO
00078 DEOO

0007C
00070
oo07E
0007E
0007F
OOOBO
OOOBO
OOOBI
00082
000B2
00083

29B
29B
299
300

AOCA
5020
5020
AFBO
AFBO
4FDO
CBOO

301
302
303
304
304
304
305
306
306
306
307
30B
309
310
311
312
313
314
315
316
316
317
31B
31B
319
319
320
321
321
322
322
323
324
325
326
327
32B
329
330
331
332
333
334
335
336
337

LI!BTERR:

LOGIT:

PARERR:
PARITY

OVFERR:
BUI1PERR:

INCREIIENT
; FETCH OLD COUNT

; 6ET OUT
; FETCH UPPER BYTE

i SET CARRY

RIEXIT:
; DO NOT restore flags

RET
CLEARC:
ANDl
JI1P

CFLAGf,CCR
RXEXIT

; CLEAR CARRY

; --------------------------------------------------------------------SDLY
nale:
delay routine, I!ULTIPLES OF 4.Busec,
description:
1.4 usee OVERHEAD, IIAI OF 410usec
delay count on stack
entry:
acc destroyed
exi t:
DDNT CALL THIS WITH COUNT = O!
WARNING:
tjq 9/16/B7 create
history:
-------------------------------------------------------------------TL/F /9635-18

2·170

:r>
338
339
SDLV:
OOOBE
340
OC08E AESO 340
341
0008F FD1F 341
342
00090 FFEB 342
343
Addr
Line RUNT
00091 FFEA
00092
00093
00093
00094
00094
00095
00096
00097

FD6S
FD6S
S03A
B03A
201A
0000
201B
0000

00098 FD5F
00099 FD7F
0009A AFBO

343
344
344
345
346
347
348
349
350
351
352
352
353
353
354
355
356
357

en
.....

EXX

IIA,IIB,NAI

BANK, ALLOW INTERRUPTS

1I0VE

DS,Ace

SET COUNT

!lOVE

SP7,DS

PUSH 6P7 RESISTERS USED

IIOVE

SP6,DS

1I0VE

ACC,6P7

; USE 6P7 FOR COUNT ALSO

LOI

HI03,6P6

SUBI
JIIPF
SUBI
JIIPF
!'lOVE

j DECREIIENT COUNT
HI01,6P6
NS, Z,SDLYLP2 ; CONTINUE UNTIL EXHAUSTED
; DECREMENT OUTER COUNT
HI01,6P7
NS, Z,SDLVLPI j CONTINUE IF NOT ZERO
j POP RE6
DS,6P6

!lOVE

DS,6P7

RET

RI,RF

SDLVLPI :
LOAD FOR 4.8usec COUNTS

SDLVLP2:

RETURN, RESTORE FLASS

END

Asselbl y Phase co.plete.
o error (51 detected.
TLlF/9635-19

II
I

2-171

00
00
CD

r-------------------------------------------------------------------------------------~

National Semiconductor
Application Note 688
Laura Johnson

:Z The DP8344 BCp® Inverse
cc

Assembler
OVERVIEW
The DP8344 BCP Inverse Assembler is a software package
for use in a Hewlett Packard Logic Analyzer. It was developed by National Semiconductor's Arlington Design Center
to allow disassembly of the DP8344 op-code mnemonics.
When developing systems using a RISC processor such as
the DP8344, the need often arises to know the sequence of
events that occurred in real time in the system. The actual
execution flow that occurred in the system can be determined by monitoring the states on the Instruction memory
Address bus and the Instruction memory bus of the DP8344
with a Hewlett Packard Logic Analyzer. The DP8344 BCP
Inverse Assembler enhances this development tool by displaying the BCP instruction op-code mnemonics on the logic analyzer's screen. This Application Note lists the equipment needed as well as the necessary information to set up,
use, and obtain the DP8344 BCP Inverse Assembler. Additionally, the source code flow chart for the DP8344 BCP
Inverse Assembler is provided in Appendix A of this Application Note.
EQUIPMENT REQUIRED

Design/Evaluation Kit includes both the hardware and software that allows the MPA to emulate a 3270 or 5250 display
terminal and to support industry standard PC emulation software. The MPA Design/evaluation Kit is available from National Semiconductor (Part No. D88344MPA-EB). All the examples in this document were generated using an MPA
board and it's associated software for the target system.
Additional equipment which one may find useful includes an
extender card and an 84-pin PLCC Adapter. The extender
card brings a PC board out of the PC chasis, allowing easier
access to the BCP. An 84-pin PLCC Adapter allows one to
directly connect the channels of the logic analyzer to the
pins on the BCP. Emulation Technology, Inc., makes an
84-pin PLCC Adapter which it calls a BUG KATCHER. (It is
Part No. BC-4-084-PCC5-00000).
The sample target system described above includes the following equipment:
1. IBM® Personal Computer or compatible
2. MPA Development Kit
3. Extender Card (optional)

The following equipment is required to use the DP8344 BCP
Inverse Assembler:
1. DP8344 BCP Inverse Assembler; Available from National
Semiconductor.
2. HP1650A or HP1651A Logic Analyzer, or HP16500A Logic Analysis System with an HP16510A State/Timing Card
installed.
3. DP8344 Biphase Communications Processor in a System.
It is assumed that the reader is familiar with the operation of
the HP Logic Analyzer. For further information refer to the
Operation Reference Manual provided with the HP1650A or
1651 A Logic Analyzers, or with the HP1651 OA Logic Analyzer Module. Information pertaining to the operation of the
logic analyzer in a state mode will be useful.
SYSTEM SETUP
A block diagram of the setup of the system for using the
DP8344 BCP Inverse Assembler is shown in Figure 1. The
target system refers to a system containing a BCP which is
running. The DP8344 BCP Inverse Assembler is software
which has been loaded into the HP Logic Analyzer. The
target system is interfaced to the DP8344 BCP Inverse Assembler through the HP Logic Analyzer's channels.
An example of a target system is a Multi-Protocol Adapter
(MPATM) installed in a personal computer. The MPA

Target
System

I
I

4. 84-Pin PLCC Adapter
The DP8344 BCP Inverse Assembler requires information
from both the Instruction memory Address bus and the Instruction memory data bus of the BCP in the target system.
Thus, these pins must be connected to the logic analyzer.
The 84-pin PLCC Adapter allows one to directly connect the
logic analyzer channels to the BCP. Figure 2 provides a
detailed view of the pin connections from the DP8344 to the
logic analyzer. The pins can be connected to any of the
pods as long as the channel and label definitions are defined accordingly in the FORMAT Menu as described later
in this Application Note.
STARTING THE DP8344 BCP INVERSE ASSEMBLER
Once the system hardware has been set up, the DP8344
BCP Inverse Assembler software needs to be installed in
the HP Logic Analyzer. The 3% inch diskette provided in the
DP8344 BCP Inverse Assembler Package contains the software for the HP Logic Analyzer. Load the DP8344 BCP Inverse Assembler Software into the HP Logic Analyzer by
selecting either LOAD ALL from file BCP, or LOAD State/
Timing E, from File BCP.E as in Figure 3. This automatically
loads the DP8344 BCP Inverse Assembler as well as the
stored State/Timing configuration into the HP Logic Analyzer.

Channels from the HP Logic
Analyzer to the BCP

J
I

IHP Logic
Analyzer

I
TL/F/10B14-1

FIGURE 1. Block Diagram of the System Set Up

)
2-172

CONFIGURING THE HP LOGIC ANALYZER

logic analyzer's configuration must follow the setup described here. Figures 4-6 show the configuration provided
on the DP8344 BCP Inverse Assemblerdiskette. One may
create their own configuration by adding more labels and
connecting more channels to the target system than shown
in the examples in this document. This will allow one to
monitor the system activity according to their needs. However, the logic analyzers system configuration must include
the following:

The DP8344 Inverse Assembler software contains a Statel
Timing configuration which one may use without any changes. The designer can change this default configuration, or
define an entirely new configuration to meet their own systems needs. However, certain parameters must exist in the
configuration for the DP8344 Inverse Assembler to work.
These parameters will be described using the default configuration as an example.

»
z
m
CD
CD

In the Configuration Menu, as in Figure 4, one must:

Internal communication variables are set as the logic analyzer collects data from the target system. Therefore, the

1. Define the Analyzer Type to be a State Analyzer.
2. Assign at least two pods to the State Analyzer.

Label DATA:
Channels 8-15

Label DATA:
Channels 0-7

,,'
Label DATA:

~eIO ...

{~------~~'------~

Label ADDR:
Channels 1-7

AD7
18
AD6
19
ADS
20

DP8344A

AD4

Vee
Label STAT
Channel 0

BCP

GND
23

84-pin PLCC

(top viow)

AD3

Label ADDR:
Channels 8-15

25
26

Connect to clock channel
of any Pod and define
this as the clock in the
Format Menu
TLIF/10814-2

FIGURE 2. Pins Connected to Logic Analyzer Pods

fII
I

2-173

'-_";"-_ _"')

(

Front Disc)

)

from file

All

BCP
(

Execute
TL/F/l0614-3

File Type

File Description

inverse_assem
16530A-config
16510A-config
16500A-config

DP8344 BCP
DP8344 BCP
DP8344 BCP
DP8344 BCP

INVERSE ASSEMBLER
INVERSE ASSEMBLER
INVERSE ASSEMBLER
INVERSE ASSEMBLER

(a)

'-_";"-_ _"')

(

( Cancel

Front DISC)

'-____...J)

)

State/TImlng E

from file

(

BCP_E

)

Execute

)
TL/F/l0814-4

Filename

File Type

File Description

BCP
BCP_D
BCP_E
BCP_

inverse_assem
16530A-config
16510A-config
16500A-config

DP8344
DP8344
DP8344
DP8344

BCP INVERSE ASSEMBLER
BCP INVERSE ASSEMBLER
BCP INVERSE ASSEMBLER
BCP INVERSE ASSEMBLER

(b)

FIGURE 3. Two Methods to Load DP8344 BCP Inverse
Assembler Software from the Front Disk Menu

(

state/TImlng E

)(

Configuration

Analyzer 1
Name:
Type:

(

)

cancel

) (

Run

)

Analyzer 2

MACHINE 1
State

Type:

Off
Unassigned Pods

I
. __________ ---- _:- __ ---'J
Pod 1

Pod 2

Pod 5

11--.-----------------------------__-_-1

( ---------~~~~--------- )

----. ___-----___________ J
Pod 3
_____________________
. II
TL/F/l0814-5

FIGURE 4. Configuration Menu on Logic Analyzer

2-174

In the Format Menu, see Figure 5, define the labels and
assign the channels in the following manner:
1. Create labels ADDR, DATA, and STAT.

iii. For the label STAT it is not necessary to actually connect any of the defined channels to the BCP. However,
it is recommended that one does connect all defined
channels to a pin such as ground. This is because the
BCP does not use a STATUS bus. The STAT label
must be defined in the Format Menu. In the example
shown in Figure 5, the channel assigned to the STAT
label corresponds to a ground pin on the BCP connected to channel 0 of Pod E3.

2. Assign the channels connected to the labels as follows:
i. label ADDR refers the channels connected to the Instruction memory Address Bus on the DP8344. From
Figure 2, these are pins 75 through 68, and pins 65
through 58. To use the default configuration the pins
from the Instruction memory Address bus must be
connected to channel 0 through 15 of Pod E1.

) (

Format 1

Cancel

)

Clock

I~I

~~~:

)(

Run

Pod E3

Pod E2

Pod E1

Clock

II
-1-5-~~-.--87-~~-~:-O

Pol

( SymbolS)

,-~~__ (~~Jt~______- J

•
en
Q)

3. Define the Clock to be the channel which corresponds to
the connection from the pod clock connection to pin 51,
IClK, on the DP8344. In the example shown in Figure 5,
the J clock means that IClK is connected to the clock
channel of pod E1. Set the clock to trigger on the rising
edge of IClK.

ii. The DATA label refers to the channels connected to
the Instruction memory data bus on the DP8344. From
Figure 2, these are pins 9-2, and pins 83-76. To use
the default configuration the pins from the Instruction
memory Data bus must be connected to channels 0
through 15 of Pod E2.

State/TIming E

II1-5-~~-.--87-

Clock

15 ••• 87 .... 0

•• -: :-0

~+~.:::::::::: ~~~ ......."..,,: ~~~ . """""".

STAT

+ . . . . . . . . . .•

...........

. ......... .

••••••••••

. .•...••.••

DATA

......•.. "

Off
Off
Off
Off
TL/F/l0814-6

FIGURE 5. Format Menu on Logic Analyzer

)(

Stae
t /TIImlng
.

Run

race

)

Sequence Levels
While storing "any state"
TRIGGER on "a"

1 times

Store "any state"

Label>

( AD DR

) (DATA

) (STAT

) (DATA

Base>

(

Hex

)(

(

0000

)

)(
)(

(

XXX X

)

(
(

XXXX

)

)(
(
(
(

XXXX

)

(

Invasm

Hex

XXXX

)(

XXX X

)(
)(

XXXX

(

Branches
Off

)

(

Count
TIm.

)

(

Prestor.
Off

)

)
)
)
)
)
)
TL/F/l0814-7

FIGURE 6. Trace Menu on Logic Analyzer
2-175

•

00
00
CD

:Z
<

r----------------------------------------------------------------------------------------------Third, verify that the three labels: ADDR, DATA and STAT
exist in the Format Menu. Fourth, in the State Listing Display, shown in Figure 7, select the base field below the label
DATA. This will generate seven pop-outs. Select the "Invasm" pop-out to allow the mnemonics to be displayed. Finally, store the new configuration to the DP8344 BCP Inverse Assembler using one of the two methods shown in
Figure 8. Whenever this configuration file' is loaded, the inverse assembler will automatically load. Note that storing
the configuration to the Inverse Assembler will write over
any previously stored configurations. Therefore, it is recommended that one back up all of the stored configurations by
copying them to a backup diskette.

The trigger may be defined in. the Trace Menu according to
the ,information desired. For example, in Figure 6, the trace
is set to, trigger, when the BCP executes the program, Le.,
the Instruction ,memory Address bus is 0 hex.
Once the system configuration has been developed,'it must
be linked with,'the inverse assembler software. First; load
the DP8344 BCP Inverse Assembler Software by either
method showhin Figure 3; Second, create a configuration
by either:
.
Lmodifying'theconfiguration file which was loaded into the
HPLogic AnalyZerwith the DP8344' BCP Inverse Assembler, or'
iL by loading another State/Timing Configuration 'which has
been stored "on diskette.

State/TImlng E

) (

Listing 1

~====:II

DATA
Hex

L..-"':':':::;""'..,JII

The system is now set to capture the BCPop-codes from
your system and display them as mnemonics.

(

)

Invasm

)

(

Run

I~I====DP=8=34=4=B=C=P=~=NE=M=O=NI=C==~1 ~I===n=m=e=~

1 1-1__R~e:::la:::;tI~ve~---I

Hex

TL/F/l0S14-S

FIGURE 7~ State LIsting Display

The Data Label with base Hex
DATA to be "Invasm".

will display the op-codes in Hex Format. The DP8344 BCP MNEMONIC Label is generated by selecting the base type for the Label
..

(

System

(

, Store'

) (

)

Front Disc

1'," (
(

file description:

All

to file

(

DP8344 BCP INVERSE ASSEMBLER

BCP
)

(

)

Execute

)
TL/F/l0S14-9

Filename

File Type

File Description

BCP
BCP_D
BCP_E
BCP_

inverse_assem
16530A...:..ccinfig
16510A...:..config
16500A...:..config

DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER

(a)

(
(.

System'

"" ' : Stofe '

) (

Front Disc' )

) (

file description:

(

State/TImlng E

)

to file

(

DP8344 BCP INVERSE ASSEMBLER

BCP_E
)

(

Execute

)
)
TL/F/l0S14-10

" Filliname
BCP
BCP_D
BCP_E
BCP_

File Description

File Type

DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER
DP8344 BCP INVERSE ASSEMBLER

inverse_assem
16530A...:..config
16510A...:..config
, J6500A...:..config

(b)
FIGURE 8. Two Methods to Store Configurations to the
DP8344 BCP Inverse Assembler Software

2-176

DP8344 BCP INVERSE ASSEMBLER OPERATION

the display. Then select the "Invasm" pop-up on the top line
of the State Listing Display. This causes the inverse assembler to disassemble the code from the first line on the display. For an example, refer to Figures 9 through 12. The
inverse assembler was set to trigger when the Instruction
Address Bus was 80 hex, as in Figures 9 and 10. The two
byte instructions captured prior to the trigger were not correctly disassembled. Referring to Figure 11, one observes
that line -10 is disassembled as an ADD Instruction rather
than as the second byte of the LJMP instruction from line
-11. To correct this, one must select "Invasm" from the
top line of the State Listing Menu. The inverse assembler
immediately disassembles the code from the first line on the
screen. The correctly disassembled code is shown in Figure
12.

An inverse assembler converts instructions captured by the
logic analyzer in binary form into mnemonics. Thus it makes
it much easier to follow the program's execution flow. Furthermore, one can still use the logic analyzer to view other
useful information by specifying the trace conditions, labels
and channel connections in the logic analyzer's configuration file.
One needs to be aware of how the captured information is
actually diassembled. The inverse assembler begins disassembling at the event which was triggered upon. Hence, any
information captured prior to the trigger may not be correctly
disassembled. To ensure valid disassembly of states captured prior to the trigger, one must scroll the display so the
first instruction one wants disassembled is the first line on

State/TIming E

) (

Trace 1

Run

Sequence Levels
While storing "anystate"

1 times

TRIGGER on "a"
Store "anystate"

Label>
Base>

( ADDR

) (DATA

) ( STAT

(
(

)(
)
)
)
)

) ( Hex )
~=~
( X )
X
)
(~=~
~=::::
X
)
(
~=~
X _)
("""---_

(
(
(

Hex

0080

XXXX
XXXX
XXXX

Invasm

Branches

(
(

Count
TIme

)

Prestore

)

Off

) (DATA)

~=~

(

Hex)

(

XXX X

)

(

XXXX

)

(

XXXX

)

(

XXXX

)
TL/F/l0B14-11

FIGURE 9. Triggering Event

State/TIming E

) [

Listing 1

[]QQ[J~I

Invasm

DP8344 BCP I.tNEI.tONIC

~~I
-7

(

Hex

0001
0501
CF40
CFOO
4FE2
C50B
CC1C

JMP AE, S, 005EH
JMP AE, NS, 005FH
ILLEGAL OPCOOE
ILLEGAL OPCOOE
ANO FEH, ICA/ATA
ILLEGAL OPCOOE
CALL0080H

Run

II
II

TIme
Relative
TLlF/l0B14-12

-6
-5
-4
-3
-2
-1

005C
0050
005F
0060
0061
0062
0063

120 ns
80 ns
160 ns
120 ns
120 ns
80 ns
120 ns

0080

AE80

EXX MA, MS, NCHG

160 ns

0081
0082
0083
0084
0085
0104
0085
0086

C343
AE90
AEC8
C343
AEEO
AFFO
AEEO
C343

MOVE ACA/FSA, [IV + 1
EXX AA, MS, NCHG
EXX MA, AS, EI
MOVE ACA/FSA, [IV + 1
EXX MA, BM, 01
AETOI, AFB
EXX MA, MB, 01
MOVE ACA/FBA, [IV + 1

80 ns
160 ns
120 ns
120 ns
160 ns
80 ns
120 ns
120 ns

FIGURE 10. Triggered Event as Shown In the State Listing
2-177

Ell

co
co

(

)[

StateL!!mln~ E
t.4arkers

Off

Invasm

~ [

Hex

II
II

DATA
Hex

II
II

DP8344 BCP t.4NEt.40NIC
Hex

II
II

)

Time
Relative
TLlF/l0814-13

-16
-15
-14
-13

0050
0051
0052
0053
0054
0055
0056

0051
4009
C340
C089
8000
857C
COOO

ADD 05H, NCF/18R
AND OOH, GP5/GP5'
MOVE CCR/OCR, [IV + ]
JMP GP5/GP5'
MOVE OOH, IWHI
MOVE 57H, IWLO
LJMP [lW]

-12

0057

8009

JRMK GP5/GP5', OH, OH

80ns

-11
-10
-9
-8
-7
-6
-5
-4

0058
0059
005A
0058
005C
0050
005F
0060

8009
0058
8C09
005C
0001
0501
CF40
CFOO

LJMP GP5/GP5', OH, S, 0058H
ADD 05H, GP4/GP4'
LJMP GP5/GP5', OH, NS, 005CH
ADD 05H, IWLO
JMP RE, S, 005EH
JMP RE, NS, 005FH
ILLEGAL OPCOOE
ILLEGAL OPCOOE

200ns
120ns
120ns
80 ns
120 ns
120 ns
160 ns
80 ns

-17

Run

)
ADDR

-19
-18

)

Listing 1

120ns
80ns
120 ns
160 ns
200 ns
120 ns
120 ns

FIGURE 11. Incorrectly Disassembled Instructions Prior to Triggered Event

(

StateL!!mln~ E
t.4arkers

Off

Invasm

Listing 1

Run

)
ADDR
Hex

-19
-18

)[

II
II

DATA
Hex

II
II

DP8344 BCP t.4NEt.40NIC
Hex

II
II

Time
Relative
TLlF/l0814-14

-16
-15
-14
-13

0050
0051
0052
0053
0054
0055
0056

0051
4009
C340
C089
8000
857C
COOO

ADD 05H, NCFII8R
AND OOH, GP5/GP5'
MOVE CCR/OCR, [IV + ]
JMP GP5/GP5'
MOVE OOH, IWHI
MOVE 57H, IWLO
LJMP [lW]

120 ns
80 ns
120 ns
160 ns
200 ns
120 ns
120 ns

-12

0057

8009

JRMK GP5/GP5', OH, OH

80ns

-11
-10
-9
-8
-7
-6
-5
-4

0058
0059
005A
0058
005C
0050
005F
0060

8009
0058
8C09
005C
OD01
0501
CF40
CFOO

LJMP GP5/GP5', OH, S, 0058H

200ns
120ns
120ns
80ns
120 ns
120 ns
160 ns
80ns

-17

LJMP GP5/GP5', OH, NS, 005CH
JMP RE, S, 005EH
JMP RE, NS, 005FH
ILLEGAL OPCOOE
ILLEGAL OPCOOE

FIGURE 12. Instructions Prior to Triggered Event, Correctly Disassembled after Choosing the "Invasm" Pop-Out

2-178

This same technique must be applied if one jumps ahead in
the display and then scrolls backwards to view a certain
state; in other words, you do not scroll forward through every line to reach the desired state. For example, if one manually selected the line number -12 in Figure 12 and
entered line 226, the screen would display lines 219 through
234. Now if one rolls the screen backwards to display lines
199 through 214 as in Figure 13, the two byte instruction,
LJMP, is once again not correctly disassembled. Therefore,
select the "Invasm" pop-out and the display is'correctly disassembled as shown in Figure 14.

To view the op-code in both mnemonic form and hex form,
as in Figure 16, define the, DATA label twice in the Format
Menu, as in Figure 4. Then, select the base label to be
"Hex" for one and "Invasm" for the other in the State listing.
OBTAINING THE DP8344 BCP INVERSE ASSEMBLER

The DP8344 BCP Inverse Assembler package for use in a
Hewlett Packard Logic Analyzer can be obtained from National Semiconductor. Included in the Inverse Assembler
Package is the DP8344 BCP Inverse Assembler software,
including configuration files as described in this application
note. These will be on a 3%" diskette formatted for use in
the HP Logic Analyzer. Additionally, a 5%" diskette formatted for use on an IBM personal computer or compatible,
containing the DP8344 Inverse Assembler source code can
be obtained upon a request from National Semiconductor.

One of the features of the BCP is that it uses register banks.
However, there is no external indication of the bank's state.
The name of a register therefore depends upon which bank
one is in, as in Figure 15. Due to the manner in which the
inverse assembler disassembles the captured data, keeping
track of the correct register name meant that one would
constantly have to scroll the screen back to the last EXX
statement and hit the "Invasm" pop-out to ensure that the
displayed register names are correct. Hence, to avoid this
inconvenience, the register names for both banks are displayed at all times. Refer to line 45 of Figure 16 for an
example. The op-code decodes to MOVE where the source
register is RO. Therefore, the register names for RO in both
banks: Main Bank A -: CCR, and Alternate Bank A - DCR,
are displayed.

(

State/T!mlng E

ADDR
Hex

199
200
201
202
203
204
205

006A
0068
006C
006A
0068
006C
006A

) (

II
II

If one owns the HP 10391A Inverse Assembler Development Package, the source code can be modified to make
any improvements one wishes to make to the DP8344 BCP
Inverse Assembler. Note that it is not necessary to have the
HP 10391A Inverse Assembler Development Package to
use the DP8344 BCP Inverse Assembler.,

Listing 1

DATA
Hex

FD08
CEOa
006A
FD08
CEOO
006A
FD08

(

Invasm

DP8344 BCP t.lNEt.40NIC

Hex

MOVE GP4/GP4', GP4/GP4'
LJMPOa6AH
ADD 06H, GP6/GP6'
MOVE GP4/GP4', GP4/GP4'
LJMP006AH
ADD 06H, GP6/GP6'
MOVE GP4/GP4', GP4/GP4'

(

TIme

Relative
TL/F/10814-15

120 ns
80 ns
120ns
120ns
80ns
120 ns
80 ns

206

0068

CEOO

LJMP006AH

120 ns

207
208
209
210
211
212
213
214

006C
006A
0068
006C
006A
0068
006C
006A

006A
FD08
CEOO
006A
FD08
CEOO
006A
FD08

ADD a6H, GP6/GP6'
MOVE GP4/GP4', GP4/GP4'
LJMP006AH
ADD 06H, GP6/GP6'
MOVE GP4/GP4', GP4/GP4'
LJMP006AH
ADD 06H, GP6/GP6'
MOVE GP4/GP4', GP4/GP4'

120ns
80ns
120 ns
120 ns
80 ns
120ns
120ns
80ns

FIGURE 13. Incorrectly Disassembled Instructions Produced
by Jumping Ahead In Display

2-179

Run

co
co

r---------------------------------------------------------------------------------------,

(

State/TImlng E

) (

LIsting 1

G;D (

Invasm

(

StateL!!mln2 E
t.4arkers

Off

)

Listing 1

(

Invasm

)

~ (

Run

)

Q)
Q)

)
ADDR

Hex
45
46
47
48
49
50
51

)(

002B
002C
0020
002E
002F
0030
0031

II
II

DATA

Hex
C340
E96S
C340
A52B
C340
207B
C340

II
II

DP8344 BCP t.4NEt.40NIC

Hex
MOVE CCR/DCR, [IV + )
SUBA GP4/GP4', GP7/GP7'
MOVE CCR/DCR, [IV + )
SUBA GP7 /GP7', [IX + )
MOVE CCR/DCR, [IX + )
SUB 07H, GP7/GP7'
MOVE CCR/DCR [IV + )

II
II

TIme
Relative
TLIF/10814-17
160ns
160 ns
120 ns'
160 ns
160ns
160 ns
80 ns

0032

ED6B

SBCA GP7/GP7', GP7/GP7'

160 ns~

53
54
55
56
57
58
59
60

0033
0034
0035
0036
0037
0038
0039
003A

C340
A72B
C340
A92B
C340
F573
C340
AB2B

MOVE CCR/DCR [IV + )
SBCA GP7/GP7' [IX + )
MOVE CCR/DCR [IV + )
ANDA GP7/GP7', [lX+)
MOVE CCR/DCR, [IV + )
ORA IZHI, GP7/GP7'
MOVE CCR/DCR, [IV + )
ORA GP7IGP7', [lX+)

120ns
160 ns
160 ns
160 ns
160ns
160 ns,
80 ns
160 ns

FIGURE 16. listing of Inverse Assembler on Logic Analyzer
Demonstrating the Display of Both Register Bank Names

EI
I

2-181

co
co
to

:Z
<

APPENDIX A

Flow Chart of DP8344 Inverse Assembler Source Code

TL/F/10814-18

2·182

Section 3
Physical Dimensions

Ell

Section 3 Contents
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

3-2

3-3

"::r

~National

(;'

Semiconductor

All dimensions are in inches (millimeters)

e.
c

3'
(I)

:s
tn

24 Lead Molded Dual-In-Line Package (N)
NS Package Number N24A

0'
:s
en

1.243-1.270
1--------(31.57_32.261--------1

0.062
(1.5751
RAO
PIN NO. llDENT

z
oonEO OUTLINES
REFLECT ALTERNATE
~~
MOLDED BODY CONFIGURATION
114.731
0.030
MIN
-(0.-76-21
0.075
0.600-0.620
MAX
11.9051

0.16010.005

Ll"I""r----+-+------;..;.;...-H---,n--J:-----------L

[r,115.24-15.7481

95°±5°

0.625

~:~~~

r-- (15875
+11.635) ---l
.
-(1.381

0.10010.010
(2.54010.2541

t t

TYP
0.015
0.018±0.0.
(0381'
- - - - 0.125-0.140 • I
(0.457 ±0.0761 (3.175-3.5561 MIN
.

N2'AIREVEl

84 Lead Plastic Chip Carrier (V)
NS Package Number V84A

1{j

::~:1
NDM

1.12010.010

UAIINO.IID£HT
0.080

(1.IUI
DIA

.!!!!.':!:ill..

32L

DDH-D.OS31

(1:m-l.3461-'
REf

VIEW A-A

20 SPACES AT
0.005-0,015

(~:~:~=~::l---~~
sa

til

3·3

NOTES

~National

~ Semiconductor

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. MIS 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090

AlS/AS lOGIC DATABOOK-1990
Introduction to Advanced Bipolar logic • Advanced low Power Schottky. Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CEllS-1987
SSIIMSI Functions • Peripheral Functions • lSllVlSI Functions • Design Guidelines • Packaging

CMOS lOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes • MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

DATA ACQUISITION liNEAR DEVICES-1989
Active Filters • Analog Switches/Multiplexers • Analog-to-Digital Converters • Digital-to-Analog Converters
Sample and Hold • Temperature Sensors • Voltage Regulators • Surface Mount

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors • JFET Transistors • Surface Mount Products • Pro-Electron Series
Consumer Series • Power Components • Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1991
Dynamic Memory Control • Error Detection and Correction • Microprocessor Applications for the
DP8408A109A117/18/19/28/29· Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821

EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview • Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools

FDDI DATABOOK-1991
FOOl Overview. DP83200 FOOl Chip Set • Development Support. Application Notes and System Briefs

F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1990
Family Overview • 300 Series (low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
ECl BiCMOS SRAM, ECl PAL, and ECl ASIC Datasheets. Design Guide. Circuit Basics. logic Design
Transmission Line Concepts • System Considerations • Power Distribution and Thermal Considerations
Testing Techniques • Quality Assurance and Reliability. Application Notes

FACTTM ADVANCED CMOS LOGIC DATABOOK-1990
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • 54AC174ACXXX • 54ACT174ACTXXX • Quiet Series: 54ACQ17 4ACQXXX
Quiet Series: 54ACTQ17 4ACTQXXX • 54FCT174 FCTXXX • FCTA: 54FCTXXXA17 4FCTXXXA

FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F174FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction • Multiplexers • Decoders. Encoders
Operators. FIFOs. Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics

GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators. Switching Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators
Instrumentation Amplifiers • Surface Mount

GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset • DP8500 Development Tools • Application Notes

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications. Application Notes

INTERFACE DATABOOK-1990
Transmission Line Drivers/Receivers • Bus Transceivers • Peripheral Power Drivers • Display Drivers
Memory Support • Microprocessor Support • level Translators and Buffers • Frequency Synthesis • Hi-Rei Interface

LINEAR APPLICATIONS HANDBOOK-1991
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this haridbook takes advantage of this innate coherence by
keeping each application
note
intact, arranging them in numerical order,
and providing a detailed Subject Index.
,
.
,

LOCAL AREA NETWORK DATABOOK-1992
Integrated Ethernet Network Interface Controller Products. Ethernet Physical layer Transceivers
Ethernet Repeater Interface Controller Products. Hardware and Software Support Products. FOOl Products. Glossary

LS/S/TTL

DATABOO~-1989

Contains former Fairchild Products
Introduction to Bipolar logic • low Power Schottky • Schottky • TTL • TTL-low Power

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller • SCSI Bus Interface Circuits • Floppy Disk Controllers • Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide

MEMORY DATABOOK-199Q
PROMs, EPROMs, EEPROMs • TTL I/O SRAMs • ECl I/O'SRAMs

MICROCONTROLLER DATABOOK-1989
COP400 Family. COP800 Family • COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PlUS Peripherals. Microcontroller Development Tools

MICROPROCESSOR DATABOOK-1989
Series 32000 Overview. Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools. Application Notes. NSC800 Family

PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1990
Product Line Overview. Datasheets • Designing with PLDs • PLD Design Methodology. PLD Design Development Tools
Fabrication of Programmable Logic • Application Examples

REAL TIME CLOCK HANDBOOK-1991
Real Time Clocks and Timer Clock Peripherals • Application Notes

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process • Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge. Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology • Wafer Fabrication • Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits • Radio Circuits • Video Circuits • Motion Control Circuits • Special Function Circuits
Surface Mount

TELECOMMUNICATIONS-1990
Line Card Components • Integrated Services Digital Network Components • Analog Telephone Components
Application Notes

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~ National

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TL3564

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1992_National_IBM_Data_Communications_Handbook 1992 National IBM Data Communications Handbook

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