1992_National_Memory_Databook 1992 National Memory Databook

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Semiconductor

MEMORY
DATABOOK
1992 Edition

CMOS EPROMs
CMOS EEPROMs
PROMs
Application Notes
Quality and Reliability
Physical Dimensions

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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National resen"
without notice, to change said circuitry or specifications.

~National

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New Products for 1992
EPROMs

EEPROMs

68040 Compatible EPROM

16K MICROWIRETM EEPROM

Brief Description: This device can interface directly with
Motorola's 68040 Microprocessor to allow for speed maximization while reducing the number of glue logic devices,
thus reducing system cost.

Brief Description: The NM93C86A can be configured either x8 or x16 and offers 16K of NV memory. This device
will be offered in an 8-pin small-outline (SO) package for
minimal space usage.

Low Voltage EPROMs

16K MICROWIRE EEPROM

Brief Description: These devices operate at 3V for low
power consumption, and have JEOEC standard pinouts.
These devices are ideal for handheld applications.

Brief Description: The NM59C16 can be configured either
x8 or x16, can be monitored for programming status by
monitoring the ROY/BUSY pin and offers 16K of NV memory. This device will be offered in an 8-pin small-outline (SO)
package for minimal space usage.

2 Megabyte EPROM
Brief Description: This device is a high performance device that possesses two megabytes of NV memory, and has
JEOEC standard pinout.

2K/4K Extended Low Voltage 12C EEPROM
Brief Description: These devices operate on an 12C 2-wire
bus and operate in an extended voltage range of 2.5V to
5.5V.
4K SPITM EEPROM
Brief Description: These devices are designed for data
storage in applications requiring both non-volatile memory
and in-system data updates.
Note: For device status and availability, contact your local sales office.

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Memory Databook
Introduction

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National Semiconductor's Memory Databook is a comprehensive collection of information on advanced memory products intended to meet the needs of virtually every electronic
system. We are committed to designing and providing stateof-the-art non-volatile EPROM and EEPROM solutions. National's EPROM families-Standard Products, Processor Oriented ePROMs, 5V Low Current and Low Voltage (3V), along
with our EEPROM families-MICROWIRETM and 12C, are designed to do just that.
National Semiconductor's EPROM families are suited to
meet a variety of customer needs. The Standard Product
EPROMs are industry compliant JEDEC parts. Yet, a standard EPROM does not meet the needs of every electronic
system. To meet these needs, National provides other families such as the Low Current 5V family which has low Icc for
power sensitive applications, Low Voltage EPROMs for newly emerging portable hand-held markets, and Processor Oriented ePROMs (POPTM) which are designed to fully utilize
microprocessor features which increase data throughput.
National Semiconductor's EEPROM families are also suited
to provide any solution in serial EEPROM. Different microcontrollers provide various serial interfaces. National, the in. dustry leader, is setting the standard again! The MICROWIRE interface is the industry standard. We have expanded
our offering to also include the 12C interface for consumer
electronics, and SPITM for automotive and telecommunication.
National Semiconductor is committed to excellence in design, manufacturing, reliability, and service to our customers
through the continuing development of new products and
technologies. As new information and devices become available, individual new datasheets will be issued. For the most
current information, please contact your local National Semiconductor sales office or distributor.
Look to National for long term support for your memory
needs!

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~National

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Semiconductor

Product Status Definitions

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Definition of Terms
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Data Sheet Identification

Product StatuI

Advancelnformatlon

Formative or
In Design

This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.

First
Production

This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.

Full
Production

This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.

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Identification:
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Definition

National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

Table of Contents
Alphanumeric Index ................................................'. . . . . . . . . . .
CMOS EPROMS

viii

Section 1

STANDARD PRODUCT EPROMS
CMOS EPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMC27C16B 16,384-Bit (2048 x 8) CMOS EPROM ...............................
NMC27C32B 32,768-Bit(4096 x 8) CMOS EPROM...............................
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM.................................
NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM ................
NM27C256 262, 144-Bit (32K x 8) High Performance CMOS EPROM ................
N M27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM ................
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM .............
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM .............
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM .............
PROCESSOR ORIENTED EPROMS
Processor Oriented EPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM ...............
NM27P210 1,048,576-Bit (64K x 16) Processor Oriented CMOS EPROM ............
NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM............
NMC87C257 262,144-Bit (32K x 8) CMOS EPROM with On-Chip Address Latches....
5V LOW CURRENT EPROMS
NM27LC256 262,144-Bit (32K x 8) Low Current CMOS EPROM....................
NM27LC512 524,288-Bit (64K x 8) Low Current CMOS EPROM ....................
LOW VOLTAGE EPROMS
NM27LV512 524,288-Bit (64K x 8) Low Voltage EPROM................... ........
NM27LV010 1,048,576-Bit (128K x 8) Low Voltage EPROM. . . . . . . . . . . . . . . . . . . . . . . .
NM27LV210 1,048,576-Bit(64Kx 16) Low Voltage EPROM........................
Section 2 CMOS EEPROMS
12C CMOS EEPROM Selection Guide ...........................................
MICROWIRE CMOS EEPROM Selection Guide ..................................
Specialty Products CMOS EEPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12C SYNCHRONOUS 2·WIRE BUS
NM24C02/C04/C08/C16 2K-/ 4K-/8K-/16K-Bit Serial EEPROM (12C Synchronous
2-Wire Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM24C03/C05/C09/C17 2K-/4K-/8K-/16K-Bit Serial EEPROM with Write Protect
(12C Synchronous 2-Wire Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM24C02L1C04L 2K-/4K-Bit Serial EEPROM with Extended Voltage (12C
Synchronous 2-Wire Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM24C03L1C05L 2K-/4K-Bit Serial EEPROM with Write Protect and Extended
Voltage (12C Synchronous 2-Wire Bus) ........................................
MICROWIRE SERIAL EEPROMS
NM59C11 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable with
Programming Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM93C06/C46/C56/C66 256-/1024-/2048-/4096-Bit Serial EEPROM
(MICROWIRE) .............................................................
NM93CS06/CS46/CS56/CS66 256-/1024-/2048-/4096-Bit Serial EEPROM with Data
Protect and Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM93C06L/C46L1C56L/C66L 2S6-/1024-/2048-/4096-Bit Serial EEPROM with
Extended Voltage (2.0V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
NM93CS06L1CS46L1CS56L1CS66L 256-/1024-/2048-/ 4096-Bit Serial EEPROM with
Extended Voltage (2.0V to 5.5V) and Data Protect .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM93C46A 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable .........

1-3
1-4
1-13
1-22
1-31
1-41
1-51
1-61
1-69
1-78
1-88
1-89
1-99
1-108
1-117
1-127
1-136
1-146
1-147
1-155
2-3
2-4
2-5

2-6
2-17
2-27
2-39

2-51
2-58
2-66
2-77
2-87
2-100

Table of Contents (Continued)
Section 2 CMOS EEPROMS (Continued)
NM93C46AL 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable . . . . . . . .
APPLICATION SPECIFIC EEPROM
NM95C12 1K-Bit CMOS EEPROM with Programmable Switches............ .... ....
Section 3 PROMS
Bipolar PROM Selection Guide. . . .. . . . . . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . .. .
NON-REGISTERED BIPOLAR PROMS
DM74S188 (32 x 8) 256-Bit TTL PROM. .........................................
DM74S288 (32 x 8) 256-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S287 (256 x 4) 1024-Bit TTL PROM........................................
DM74S387 (256 x 4) 1024-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74LS471 (256 x 8) 2048-Bit TTL PROM......................................
DM7 4S4 72 (512 x 8) 4096-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7 4S4 73 (512 x 8) 4096-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S570 (512 x 4) 2048-Bit TTL PROM.................... ....................
DM74S571 (512 x 4) 2048-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S572 (1024 x 4) 4096-Bit TTL PROM......................................
DM74S573 (1024 x 4) 4096-Bit TTL PROM.................. ................... .
APPLICATIONS INFORMATION
Bipolar PROM Devices in Plastic Leaded Chip Carriers ............................
Non-Registered PROM Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Approved Programmers/Quality Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 4 Application Notes
AB-15 Protecting Data in Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-18 Electronic Compass Calibration Made Easy with EEPROMs . . . . . . . . . . . . . . . . . .
AN-338 Designing with the NM93C06 A Versatile Simple to Use EEPROM ...........
AN-423 The NM93C46-An Amazing Device.....................................
AN-507 Using the NM93CSXX Family of Electrically Erasable Programmable Memory.
AN-716 Using the NM93CS EEPROM Family Features....................... .....
AN-731 Using National's NMC87C257 256K EPROM with On-Chip Latches..........
AN-735 Understanding National's NM95C12 EEPROM with Programmable Switches..
AN-755 NM95C12 Flexibility in Industrial Control Applications ., . . . . . . . . . . . . . . . . . . . .
AN-756 Using the NM95C12 to Solve Common Manufacturing Problems............ .
AN-758 Using National's MICROWIRE EEPROM. . . . .. . . . . . .. .. . . .. .. . .. . . . . ... . .
AN-765 Using the NM95C12 CMOS EEPROM with Programmable Switches for Analog
Applications ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-766 Using the NM95C12 in a Stand Alone Metering Device................ .....
AN-767 NM95C12 Memory Mapping Solution for PC® Applications.................
AN-789 Integrated Manufacturing Control-NM95C12.............................
AN-790 NM95C12 EEPROM Controls Amplifier Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-791 Stand Alone Control of MICROWIRE Peripherals Using the NMC87C257 .....
AN-792 NM95C12 Applications in a PC-AT Ethernet Adapter. . . . . . . . . . . . . . . . . . . . . . .
AN-794 Using an EEPROM-12C Interface NM24C02/03/04/05/08/09/16/17 ........
Section 5 Quality and Reliability
EPROM and EEPROM Reliability Information.. . . . . . . .. . . .. . . .. . . .. . . .. . . .. .. . .. ..
Section 6 Physical Dimensions
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
vii

2-108
2-118
3-3
3-4
3-8
3-12
3-16
3-20
3-24
3-28
3-32
3-36
3-40
3-44
3-48
3-51
3-52
3-53
3-53
4-3
4-5
4-6
4-12
4-15
4-29
4-31
4-33
4-39
4-50
4-62
4-73
4-80
4-89
4-93
4-96
4-102
4-123
4-127
5-3
6-3

Alpha-Numeric Index
AB-15 Protecting Data in Serial EEPROMs .................................................... 4-3
AB-18 Electronic Compass Calibration Made Easy with EEPROMs ............................... 4-5
AN-338 Designing with the NM93C06 A Versatile Simple to Use EEPROM ........................ 4-6
AN-423 The NM93C46-An Amazing Device ................................................. 4-12
AN-507 Using the NM93CSXX Family of Electrically Erasable Programmable Memory ............. 4-15
AN-716 Using the NM93CS EEPROM Family Features ........................................ 4-29
AN-731 Using National's NMC87C257 256K EPROM with On-Chip Latches ...................... 4-31
AN-735 Understanding National's NM95C12 EEPROM with Programmable Switches .............. 4-33
AN-755 NM95C12 Flexibility in Industrial Control Applications .................................. 4-39
AN-756 Using the NM95C12 to Solve Common Manufacturing Problems ........................ 4-50
AN-758 Using National's MICROWIRE EEPROM ............................................. 4-62
AN-765 Using the NM95C12 CMOS EEPROM with Programmable Switches for Analog
Applications ........................................................................... 4-73
AN-766 Using the NM95C12 in a Stand Alone Metering Device ................................. 4-80
AN-767 NM95C12 Memory Mapping Solution for PC® Applications ............................. 4-89
AN-789 Integrated Manufacturing Control-NM95C12 ......................................... 4-93
AN-790 NM95C12 EEPROM Controls Amplifier Gain .......................................... 4-96
AN-791 Stand Alone Control of MICROWIRE Peripherals Using the NMC87C257 ................ 4-102
AN-792 NM95C12 Applications in a PC-AT Ethernet Adapter .................................. 4-123
AN-794 Using an EEPROM-12C Interface NM24C02/03/04/05/08/09/16/17 ................... 4-127
DM74LS471 (256 x 8) 2048-Bit TTL PROM .................................................. 3-20
DM7 4S 188 (32 x 8) 256-Bit TTL PROM ....................................................... 3-4
DM74S287 (256 x 4) 1024-Bit TTL PROM ................................................... 3-12
DM74S288 (32 x 8) 256-Bit TTL PROM ....................................................... 3-8
DM74S387 (256 x 4) 1024-Bit TTL PROM ................................................... 3-16
DM74S472 (512 x 8) 4096-Bit TTL PROM ................................................... 3-24
DM74S473 (512 x 8) 4096-Bit TTL PROM ................................................... 3-28
DM74S570 (512 x 4) 2048-Bit TTL PROM ................................................... 3-32
DM74S571 (512 x 4) 2048-Bit TTL PROM ................................................... 3-36
DM74S572 (1024 x 4) 4096-Bit TTL PROM .................................................. 3-40
DM74S573 (1024 x 4) 4096-Bit TTL PROM .................................................. 3-44
NM24C02 2K-Bit Serial EEPROM (12C Synchronous 2-Wire Bus) ................................. 2-6
NM24C02L 2K-Bit Serial EEPROM with Extended Voltage (12C Synchronous 2-Wire Bus) .......... 2-27
NM24C03 2K-Bit Serial EEPROM with Write Protect (12C Synchronous 2-Wire Bus) ............... 2-17
NM24C03L 2K-Bit Serial EEPROM with Write Protect and Extended Voltage (12C Synchronous
2-Wire Bus) ............................................................................ 2-39
NM24C04 4K-Bit Serial EEPROM (12C Synchronous 2-Wire Bus) ................................. 2-6
NM24C04L 4K-Bit Serial EEPROM with Extended Voltage (12C Synchronous 2-Wire Bus) .......... 2-27
NM24C05 4K-Bit Serial EEPROM with Write Protect (12C Synchronous 2-Wire Bus) ............... 2-17
NM24C05L 4K-Bit Serial EEPROM with Write Protect and Extended Voltage (12C Synchronous
2-Wire Bus) ............................................................................ 2-39
NM24C08 8K-Bit Serial EEPROM (12C Synchronous 2-Wire Bus) ................................. 2-6
NM24C09 8K-Bit Serial EEPROM with Write Protect (12C Synchronous 2-Wire Bus) ............... 2-17
NM24C16 16K-Bit Serial EEPROM (12C Synchronous 2-Wire Bus) ................................ 2-6
NM24C17 16K-Bit Serial EEPROM with Write Protect (12C Synchronous 2-Wire Bus) .............. 2-17
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM ......................... 1-61
NM27C040 4, 194,304-Bit (512K x 8) High Performance CMOS EPROM ......................... 1-78
NM27C128 131 ,072-Bit (16K x 8) High Performance CMOS EPROM ............................ 1-31
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM ......................... 1-69
NM27C256 262, 144-Bit (32K x 8) High Performance CMOS EPROM ............................ 1-41
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM ............................ 1-51

viii

Alpha-Numeric

Index(continUed)

NM27LC256 262, 144-Bit (32K x 8) Low Current CMOS EPROM ............................... 1-127
NM27LC512 524,288-Bit (64K x 8) Low Current CMOS EPROM ............................... 1-136
NM27LV010 1,048,576-Bit(128K x 8) Low Voltage EPROM ................................... 1-147
NM27LV210 1,048,576-Bit(64K x 16) Low Voltage EPROM ................................... 1-155
NM27LV512 524,288-Bit (64K x 8) Low Voltage EPROM ..................................... 1-146
NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM ....................... 1-108
NM27P210 1,048,576-Bit (64K x 16) Processor Oriented CMOS EPROM ........................ 1-99
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM ........................... 1-89
NM59C11 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable with Programming
Status ................................................................................ 2-51
NM93C06 256-Bit Serial EEPROM (MICROWIRE) ............................................ 2-58
NM93C06L 256-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) ........................ 2-77
NM93C46 1024-Bit Serial EEPROM (MICROWIRE) ........................................... 2-58
NM93C46A 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable .................... 2-100
NM93C46AL 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable ................... 2-108
NM93C46L 1024-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) ...................... 2-77
NM93C56 2048-Bit Serial EEPROM (MICROWIRE) ........................................... 2-58
NM93C56L 2048-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) ...................... 2-77
NM93C66 4096-Bit Serial EEPROM (MICROWIRE) ........................................... 2-58
NM93C66L 4096-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) ...................... 2-77
NM93CS06 256-Bit Serial EEPROM with Data Protect and Sequential Read ...................... 2-66
NM93CS06L 256-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) and Data Protect ....... 2-87
NM93CS46 1024-Bit Serial EEPROM with Data Protect and Sequential Read ..................... 2-66
NM93CS46L 1024-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) and Data Protect ...... 2-87
NM93CS56 2048-Bit Serial EEPROM with Data Protect and Sequential Read ..................... 2-66
NM93CS56L 2048-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) and Data Protect ...... 2-87
. NM93CS66 4096-Bit Serial EEPROM with Data Protect and Sequential Read ..................... 2-66
NM93CS66L 4096-Bit Serial EEPROM with Extended Voltage (2.0V to 5.5V) and Data Protect ...... 2-87
NM95C12 1 K-Bit CMOS EEPROM with Programmable Switches ............................... 2-118
NMC27C16B 16,384-Bit (2048 x 8) CMOS EPROM ............................................ 1-4
NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM ........................................... 1-13
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM ............................................. 1-22
NMC87C257 262, 144-Bit (32K x 8) CMOS EPROM with On-Chip Address Latches ............... 1-117

Section 1
CMOS EPROMs

•

Section 1 Contents
STANDARD PRODUCT EPROMS
CMOS EPROM Selection Guide......................................................
NMC27C16B 16,384-Bit (2048 x 8) CMOS EPROM .....................................
NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM.. . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . .
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM27C128 131 ,072-Bit (16K x 8) High Performance CMOS EPROM. . . . . . . . . .. . . . . . . .. .. .
NM27C256 262, 144-Bit (32K x 8) High Performance CMOS EPROM ......................
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM ................. . . . . .
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM ...................
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM ...................
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM...................

1-3
1-4
1-13
1-22
1-31
1-41
1-51
1-61
1-69
1-78

PROCESSOR ORIENTED EPROMS
Processor Oriented EPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM .. . . . . . . . . . . . . . . . . . . .
NM27P210 1,048,576-Bit (64K x 16) Processor Oriented CMOS EPROM ..................
NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM..................
NMC87C257 262, 144-Bit (32K x 8) CMOS EPROM with On-Chip Address Latches. . . . . . . . . .

1-88
1-89
1-99
1-108
1-117

5V LOW CURRENT EPROMS
NM27LC256 262, 144-Bit (32K x 8) Low Current CMOS EPROM ..........................
NM27LC512 524,288-Bit (64K x 8) Low Current CMOS EPROM..........................

1-127
1-136

LOW VOLTAGE EPROMS
NM27LV512 524,288-Bit (64K x 8) Low Voltage EPROM ................................
NM27LV010 1,048,576-Bit (128K x 8) Low Voltage EPROM..............................
NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2

1-146
1-147
1-155

~---------------------------------------------------------------------'n

oU)

~National

1ft

Semiconductor

"'0

CMOS EPROM Selection Guide
Standard Products

-o·
CD

::J
G)
C

a.:
CD

General Description

Features

National Semiconductor's family of high performance
CMOS EPROMs offer the following shared features: pin
compatibility with byte-wide JEDEC EPROMs; "Don't Care"
feature during read operations; high speed operation with
high performance CPUs such as the 80186, 68020, 80386;
single chip solutions for the code storage requirements of
100% firmware based equipment.

• High performance CMOS
- 100 ns access time
• Fast programming
• EPI processing
- Latch-up immunity to 200 rnA
- ESD protection exceeds 2000V
• Compatible with JEDEC EPROM configurations
• Simplified upgrade path
- Vpp and PGM are "Don't Care" during normal read
operation
• Single 5V power supply

A feature not shared by all family members is found in the
NMC87C257-address latches for direct interfacing with
address/ data multiplexed microprocessors. Other differences are memory size, speed, packaging and operating temperature range.

Available Product
NMC27C16B
NMC27C32B
NMC27C64
NM27C128
NM27C256
NM27C512
NM27C010
NM27C210
NM27C040

Packages
Q
Q
Q,N

Temperature Ranges
C,E
C,E
C,E,M*

Q,N
Q,V,N
Q,V,N
Q,V,N
Q,V
Q

C,E
C,E
C,E
C,E
C,E
C,E

Spud
150 ns, 200 ns
200ns
150 ns, 200 ns
200 ns, 250 ns
100 ns, 120 ns, 150 ns, 200 ns
120 ns, 150 ns, 200 ns
120 ns, 150 ns, 200 ns
120 ns, 150 ns, 200 ns
150 ns, 170 ns, 200 ns

ON package available only in commercial temperature range (O'C to +70·C).
Note: All products will operate at speeds slower than those listed.

Ordering Information

....JT

National Memory _ _ _ _ _ _
EPROM

1LA_ _" ,
E

120

120 = 120n$

Operatint , ....,..,..,.......

CMOS .....------------~

No Entry = O·C to + 70·C
E ;: -40·C to + 85°C

' - - - - - - Package.

Ceramic DIP
N = OTPDIP
V = PLCC

' - - - - - - - - Size

512 = 512k

1-3

III
CD

~ ~National

(.) U
::e

Semiconductor

NMC27C16B 16,384-Bit (2048 X 8) CMOS EPROM
General Description

Features

The NMC27C168 is a high performance 16K UV erasable
and electrically reprogrammable CMOS EPROM, ideally
suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.

• Low CMOS power consumption
Active power: 55 mW max
Standby power: 0.55 mW max (99% savings)
• Optimal EPROM for total CMOS systems
• Extended temperature range available,
-40°C to +85°C
• Fast and reliable programming (100 p,s for most bytes)
• TTL compatible inputs/outputs
• TRI-STATE® output
• Manufacturer's identification code for automatic programming equipment
• High current CMOS level output drivers
• Upgrade for NMOS 2716

The NMC27C168 is packaged in a 24-pin dual-in-line package with a quartz window. The quartz window allows the
user to expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written into the device by
following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power consumption and excellent reliability.

Block Diagram
Vee 0--+
GND 0--+

DATA OUTPUTS 00 - 07

Vpp 0--+

OUTPUT ENABLE; CHIP ENABLE
AND PROG LOGIC

OUTPUT
BUrFIRS

Pin Names
AO-A10

AOA10
ADDRESS
INPUTS

--+
--+
--+
--+
--+
--+
--+
--+
--+
--+
--+

y
DECODER

x
DECODER

y
GATING

•
•
•
•
•

16,384- BIT
CELL MATRIX

TL/D/91BO-l

1-4

Addresses

Chip Enable

Output Enable

00- 0 7

Outputs

PGM

Program

No Connect

Connection Diagram
27C256
27256

27C128
27128

27C64
2764

27C32
2732

Vpp
A12
A7
A6
A5

A3
A2
A1
AO

A7
A6
A5
A4
A3
A2
A1
AO

NMC27C16B
Dual-ln-L1ne Package
A7- 1

\..J

A6- 2

24 -Vee
23 -A8

A5- 3

22 -A9

A4- 4

~Vpp

A3- 5

-OE

27C32
2732

27C64
2764

27C128
27128

27C256
27256

Vee
AS
A9
A11
OElVpp
A10
CE

Vee
PGM
NC
AS
A9
A11
OE
A10
CE

Vee
PGM
A13
AS
A9
A11
OE
A10
CE

Vee
A14
A13
AS
A9
A11
OE
A10

A2- 6

19 -Al0

Al- 7

18 .... cr/PGt.I

AO- 8

17 -07

00- 9

04
03

06
05
04
03

02- 11

16 ~06
15 -0s
14 -04

GND

GND- 12

13 -03

O,- IO

TL/D/9160-2

Top View
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C168 pins.

Order Number NMC27C16BQ
See NS Package Number J24AQ
Commercial Temp. Range WC to 70°C) Vee
Parameter/Order Number

Access Time (ns)

NMC27C16B0150

150

NMC27C16B0200

200

Extended Temp. Range (-40°C to
Parameter/Order Number

± 10%

+ 85°C) Vee =

± 10%

Access Time (ns)

NMC27C16BOE150

150

NMC27C16BOE200

200

1-5

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,

All Output Voltages with
Respect to Ground (Note 10)

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
Commercial Parts
Extended Temp. Parts

-10°C to + 80°C
- 40°C to + 85°C

Storage Temperature

- 65°C to + 150°C

Vec Supply with
Respect to Ground

+7.0Vto -0.6V

All Input Voltages except A9 with
Respect to Ground (Note 10)

+6.5Vto -0.6V

Vee + 1.0Vto GND-0.6V

Vpp Supply and A9 Voltage
with Respect to Ground

+ 14.0V to -0.6V
1.0W

Power Dissipation
Lead Temp. (Soldering, 10 sec.)

300°C

Operating Conditions (Note 8)
Temperature Range
NMC27C16B0150, 200
NMC27C16BOE150, 200

O°C to + 70°C
- 40°C to + 85°C
+5V ±10%

Vee Power Supply

READ OPERATION
DC Electrical Characteristics
Symbol

Typ
(Note 11)

Max

Units

VIN = Vec or GND

0.1

p,A

Parameter

Conditions

Min

III

Input Load Current

iLO

Output Leakage Current

VOUT = Vcc or GND, CE = VIH

0.1

p,A

lecl
(Note 3)

Vcc Current (Active)
TTL Inputs

CE = VIL, f = 5 MHz
Inputs = VIH or VIL
110 = 0 mA

ICC2
(Note 3)

Vee Current (Active)
CMOS Inputs

CE = GND, f = 5 MHz
Inputs = Vcc or GND,
110 = 0 mA

leeSBl

Vcc Current (Standby)
TTL Inputs

CE = VIH

0.1

leeSB2

Vee Current (Standby)
CMOS Inputs

CE = Vec

0.5

100

p,A

Ipp

Vpp Load Current

Vpp = 5.5V

p,A

VIL

Input Low Voltage

-0.2

VIH

Input High Voltage

2.0

VOL1

Output Low Voltage

IOL = 2.1 mA

VOHl

Output High Voltage

IOH = -400 mA

VOL2

Output Low Voltage

IOL = 10 /LA

VOH2

Output High Voltage

IOH = -10 /-LA

0.8

Vee + 1

0.45
2.4

V
V

0.1

V
V

Vee -0.1

AC Electrical Characteristics
NMC27C16BQ
Symbol.

Parameter

Conditions

Q150,QE150

Q200,QE200

Min

Max

Units

Max

tAec

Address to Output Delay

CE = OE = VIL

150

200

tCE

CE to Output Delay

OE = VIL

150

200

tOE

OE to Output Delay

CE = VIL

tOF

OE High to Output Float

CE = VIL

teF

CE High to Output Float

OE = VIL

tOH

Output Hold from Addresses,
CE or OE, Whichever Occurred First

OE = OE = VIL

1-6

Capacitance T A = + 25°C. f
Symbol
CIN
COUT

oN
.....

= 1 MHz (Note 4)

Parameter

Conditions

Typ

Max

Units

Input Capacitance
Output Capacitance

VIN = OV
VOUT = OV

12
12

pF
pF

o
......

tEl

AC Test Conditions
Output Load (Note 12)

1 TIL Gate and CL = 100 pF
~

Input Rise and Fall Times
Input Pulse Levels

Timing Measurement Reference Level
Inputs
Outputs

5 ns

0.45V to 2.4V

AC Waveforms

(Notes 2 & 9)

ADDRESSES

OUTPUT

0.8Vand 2V
0.8Vand 2V

ADDRESSES VALID

O.8V

2V
O.8V

VALID OUTPUT

a.sv

t AcC
(NOTE

5)
TL/D/91BO-3

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
Note 3: Vpp may be connected to Vce except during programming. Icel ,;; the sum of the lec active and Ipp read currents.
Note 4: This parameter is only sampled and is not 100% tested.
Note 5: DE may be delayed up to tAce - tOE after the falling edge of ljE without impact on tAce.
Note 6: The tOF and tCF compare level is determined as follows:
High to TRI·STATE, the measured VOHl (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 7: TRI-STATE may be attained using OE or ljE.
Note 8: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.1 IJ-F ceramic capacitor be used on every
device between Vec and GND.
Note 9: The outputs must be restricted to Vee

+ 1.0V to avoid latch-up and device damage.

Note 10: Inputs and outputs can undershoot to - 2.0V for 20 ns maximum.
Note 11: Typical values are for T A

25°C and nominal supply voltages.

Note 12: 1 TIL Gate: IOL = 1.6 mA, 10H = 400 IJ-A.
CL: 100 pF inlcudes fixture capacitance.

1-7

Programming Characteristics (Notes 1,2,3 & 4)
Symbol

Parameter

tAS

Address Setup Time

tOES

OE Setup Time

tos

Data Setup Time

tyes

Vee Setup Time

Conditions

tyPS

Vpp Setup Time

tAH

Address Hold Time

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

Min

Typ

Max

100

105

ILs

150

Units

o
CE/PGM = VIL

o
95

CE/PGM = VIL

tOE

Data Valid from OE

Ipp

Vpp Supply Current During
Programming Pulse

Ice

Vee Supply Current

Temperature Ambient

Vce

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

3.0

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

V
ns

0.0

0.45

V
V

4.0

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed Simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum speCification. At least a 0.1 /-IF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings. The Min and Max limit
Parameters are Design parameters, not Tested or guaranteed.

Programming Waveforms
! . - - - - PROGRAM

ADDRESSES

~O.~8V~----

-J~1-

'AS

DATA

ADDRESS STABLE
__________________
-r____________

I-J

~lr-T

_________

,1 l"AH
HIGH Z

o.~~------ 2000V

ESD Protection
All Output Voltages with
Respect to Ground

Vee + 1.0VtoGND -0.6V

Read Operation
DC Electrical Characteristics Over Operating Range with Vpp

= Vee
Min

Max

Units

VIL

Input Low Level

-0.5

0.8

VIH

Input High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL

= 2.1 mA

0.4

VOH

Output High Voltage

IOH

= -2.5 mA

leeSB1

Vee Standby Current
(CMOS)

CE
VIL

= Vee ±0.3V
= GND ± 0.3V, VIH = Vee ±0.3V

leeSB2

Vee Standby Current (T2L)

= VIH

lee1

Vee Active Current, T2L Inputs

CE = OE = VIL, f
1/0 = 0 mA

lee2

Vee Active Current
CMOS Inputs

CE = GND, f = 5 MHz
Inputs = Vee or GND, 1/0
C,I Temp. Range

Vpp Supply Current

Vpp

Symbol

Ipp

Parameter

Test Conditions

= 5 MHz

= 0 mA

= Vee

Vpp

Vpp Read Voltage

III

Input Load Current

VIN

ILO

Output Leakage Current

VOUT

= 5.5V or GND

120

Parameter
Min

Min

p.A

p.A
V

-1

p.A

-10

p.A

= Vee
200

150
Max

100

. Vee

Vee - 0.7

= 5.5V or GND

AC Electrical Characteristics Over Operating Range with Vpp
Symbol

3.5

Max

Min

Units
Max

tAee

Address to Output Delay

120

150

200

teE

CE to Output Delay

120

150

200

tOE

OE to Output Delay

teF
(Note 2)

CE High to Output Float

tDF
(Note 2)

OE High to Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE orOE,
Whichever Occurred First

1·33

II
I

'9"'"

......

Capacitance T A = + 25°C, f =

1 MHz (Note 2)

Symbol

Typ

Max

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

:!::

Parameter

Conditions

Units

AC Test Conditions
Output Load

1 TIL Gate and
CL = 100 pF (Note 8)

::;; 5 ns

Input Rise and Fall Times

AC Waveforms

(Notes 6,7 and 9)
ADDRESSES VALID

2.0V
O.BV

Hi-Z

2.0V

OUTPUT

I--~E-

2.0V
O.BV

(Note 10)
0.8V and 2.0V
0.8V and 2.0V

~
O.BV

ADDRESSES

0.45 to 2.4V

Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs

O.BV

.rr

tOE
(NOTE 3)

,"""",

VALID OUTPUT

..I

'-~F(NOTES",5)
toF

(NOTES., 5)

i'HI-Z

JJ
JJ

tACC
i4-(NOTE 3) -

. . . toHITL/D/11329-4

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3:

OE may be delayed up to tACC

- toE after the falling edge of CE without impacting tACC'

Note 4: The tOF and tCF compare level is determined as follows:
High to TRI-STATEiI!>, the measured VOHl (DC) - 0.10V;
Low to TRI-STATE, the measured VOLl (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between VCC and GND.
Note 7: The outputs must be restricted to Vcc

1.0V to avoid latch-up and device damage.

Note 8: TTL Gate: IOL = 1.6 mA, IOH = - 400 /LA.
CL = 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vcc except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

1-34

Programming Characteristics
Symbol

(Notes 1, 2, 3, 4 and 5)

Parameter

Conditions

Min

Typ

Max

Units

tAS

Address Setup Time

IJ-s

tOES

OE Setup Time

IJ-s

teEs

CE Setup Time

IJ-S

tvps

Vpp Setup Time

IJ-s

tves

Vee Setup Time

IJ-s

tos

Data Setup Time

IJ-s

tAH

Address Hold Time

IJ-s

tOH

Data Hold Time

IJ-S

tOF

Output Enable to Output
Float Delay

tpw

Program Pulse Width

tOE

Data Valid from

Ipp

Vpp Supply Current
during Programming Pulse

<:5E = VIH

CE =

VIL

CE =
CE =

VIL

0
95

<:5E

100

VIL

105

IJ-s

100

rnA

lee

Vee Supply Current

rnA

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

V
ns

0.0

Programming Waveforms
ADDRESSES

5
0.45

4.0

V
V

(Note 3)

DATA~

pe~~~rAylA_

i--PROGRAIA

~
'"-

ADDRESS N

HI-Z

DATA IN STABLE
ADDN

tAH

-. DATA OUT VALID
ADD N

If--

f-.IoF

6.25V
Vee

tyes

Vl~
pp
CE

O.8Y

I§
--PGI.t

2V
O.8Y

Ipw

I-Io£s1 1-10£ ....

OE O~~v

-u

TLlD/11329-5

Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 JLF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the Fast Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the ~ pin must be brought high (~ VIH) either coincident with or before power is applied to Vpp.

1-35

o......
N

r-------------------------------------------------------------------------------------~

Fast Programming Algorithm Flow Chart

(Note 4)

INCREMENT ADDR

TLIO/11329-6

FIGURE 1

1·36

Interactive Programming Algorithm Flow Chart (Note 4)

INCREMENT ADDR

TL/D/11329-7

FIGURE 2

1-37

Functional Description
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TIL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vcc power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.

Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's"'will be programmed, both "1's" and "O's"can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.

The EPROM is in the programming mode when the Vpp
power supply is at 12.75V, CE is A7 VIL, and OE is at VIH. It
is required that at least a 0.1 ILF capacitor be placed across
Vpp, Vcc to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TIL.
When the address and data are stable, an active low, TIL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 ILs pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 ILs pulse.

Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 220 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.
Output Disable

The EPROM must not be programmed with a DC signal applied to the PGM input.

The EPROM is placed in output disable by applying a TIL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirments. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TIL pulse applied
to the PGM input programs the paralleled EPROM.

Output OR·Typing
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:

Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (shown in Figure 2).

a) the lowest possible memory power dissipation, and

Program Inhibit

b) complete assurance that output bus contention will not
occur.

Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE) of the parallel EPROMs may be common. A TIL low level program pulse applied to an EPROM's
CE input with Vpp at 12.75V will program that EPROM. A
TIL high level CE input inhibits the other EPROMs from
being programmed.

1-38

Functional Description

(Continued)
length of 2537 A. The integrated dose (i.e., UV intenSity x
exposure time) for erasure should be a minimum of
15W-sec/cm2.

Program Verify

A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee, except during programming and program verify.

The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum EPROM erasure time for various light
intensities.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.

MANUFACTURER'S IDENTIFICATION CODE

SYSTEM CONSIDERATION

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacture and device type. The
code for NM27C12S is "SF83", where "SF" designates that
it is made by National Semiconductor, and "S3" designates
a 128K part.

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 jJ-F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 jJ-F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A1-AS, A 1O-A 13, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C to ± 5°C.
ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wave-

1-39

N
......

o
.....
N

(X)

C\I
......

o......
C\I

Mode Selection
The modes of operation of NM27C128 listed in Table I. A single 5V power supply is required in the read mode. All inputs are TIL
levels except for Vpp and A9 for device signature.
TABLE J. Modes Selection
Pins

PGM

Vpp

Vee

VIL

VIH

Vee

5.0V

DOUT

VIH

Vee

5.0V

High-Z

VIH

Vee

5.0V

High-Z

6.25V

DIN

Mode
Read
Output Disable
Standby

Outputs

Programming

VIL

VIH

VIL

12.75V

Program Verify

VIL

VIH

12.75V

6.25V

DOUT

Program Inhibit

VIH

12.75V

6.25V

High-Z

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code
Pins

AD
(10)

A9
(24)

07
(19)

06
(18)

05
(17)

04
(16)

03
(15)

02
(13)

01
(12)

00
(11)

Hex
Data

Manufacturer Code

VIL

12V

Device Code

VIH

12V

1-40

~
N

~National

-.....

o
N

~ Semiconductor

NM27C256
262, 144-Bit (32K

(J1
0)

8) High Performance CMOS EPROM

General Description
The NM27C256 is a 256K Electrically Programmable Read
Only Memory. It is manufactured in National's latest CMOS
split gate EPROM technology which enables it to operate at
speeds as fast as 120 ns access time over the full operating
range.
The NM27C256 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software. Its 120 ns access time
provides high speed operation with high-performance CPUs.
The NM27C256 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment.
Frequently-used software routines are quickly executed
from EPROM storage, greatly enhancing system utility.
The NM27C256, is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.

The NM27C256 is one member of a high density EPROM
Family which range in densities up to 4 Mb.

Features
• High performance CMOS
- 100 ns access time
• High reliability with EPI processing
- Latch-up immunity to 200 mA
- ESD protection exceeds 2000V
• JEDEC standard pin configuration
- 28-pin DIP package
- 32-pin chip carrier
• Drop-in replacement for 27C256 or 27256
• Manufacturer's identification code

Block Diagram
Vcc~
GND~

DATA OUTPUTS 00 -0 7

Vpp~

OUTPUT ENABLE
AND CHIP
ENABLE LOGIC

OUTPUT
BUFFERS

Y
DECODER

Y GATING

AO-AI4
ADDRESS
INPUTS

•
•
•
•

X
DECODER

•

262,144 - BIT
CELL MATRIX

•
TL/D/l0833-1

1-41

U)
11)

r---------------------------------------------------------------------------------------,
Connection Diagrams

I'N

27C512 27C010 27C020 27C040 27C080

27C080 27C040 27C020 27C010 27C512
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02

DIP
NM27C256

xX/Vpp xX/Vpp xX/Vpp

GND

Vee

XX/PGM XX/iSG'Ki

A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02

A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02

- vpp
-A12
-A7
-A6
-A5
-A4
--A3
-A2
-AI
-AD
-00
-01
-02

GND

-GHD

Vee

A18
A17
A14
A13
A8
A9
A11

Vee

A"--

A14
A13
A8
A9
A11

O'E--

DE/Vpp

(5i;

(5i;/Vpp

Al0--

A10

crjPGI.t -

~/PC3M

07-06-05-04-03--

07
06
05
04
03

vee --AI4-AI3-A8-A9--

A17
A14
A13
A8
A9
A11

CE/P'GM CE/~
07
06
05
04
03

07
06
05
04
03

TLlO/l0833-2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins.

Commercial Temp. Range {O°C to
VCC = 5V ±10%

+ 70°C}

Extended Temp. Range (- 40°C to
VCC = 5V ±10%

+ 85°C)

Parameter/Order Number

Access Time {ns}

Parameter/Order Number

NM27C256 Q, N, V 120

120

NM27C256 QE, NE, VE 120

120

NM27C256 Q, N, V 150

150

NM27C256 QE, NE, VE 150

150

NM27C256 Q, N, V 200

200

NM27C256 QE, NE, VE 200

200

Military Temp. Range { - 55°C to
VCC = 5V ±10%

Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.

+ 125°C}

Parameter/Order Number

Access Time {ns}

NM27C256 QM 150

150

NM27C256 QM 250

250

Access Time (ns)

Package Types: NM27C256 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic OTP DIP
V = Surface-Mount PLCC
• All packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower
speeds.
PLCC

Pin Names
Symbol

Description

AO-A14

Addresses

Chip Enable

Output Enable

A3
A2

00-07

Outputs

PGM

Program

Don't Care (during Read)

Top

1-42

TL/O/l0833-3

> 2000V

ESD Protection
All Output Voltages with
Respect to Ground

Vcc + 1.0V to GND -0.6V

- 65°C to + 150°C

All Input Voltages except A9 with
Respect to Ground

Operating Range
-0.6Vto +7V

Vpp and A9 with Respect
to Ground

-0.7Vto +14V

Vee Supply Voltage with
Respect to Ground

- 0.6Vto +7V

Range

Temperature

Vee

Comm'l

O°Cto +70°C

+5V ±10%

- 40°C to + 85°C

+5V±10%

- 55°C to + 125°C

+5V ±10%

Industrial
Military

Read Operation
DC Electrical Characteristics Over Operating Range with Vpp = Vec
Symbol

Parameter

Max

Units

VIL

Input Low Level

Test Conditions

-0.5

Min

0.8

VIH

Input High Level

2.0

Vec + 1

VOL

Output Low Voltage

0.4

VOH

IOL

= 2.1 mA

Output High Voltage

IOH

= -400,..,A

15B1
(Note 11)

Vee Standby Current
(CMOS)

CE = Vee ±0.3V

15B2

Vee Standby Current

ICC1

Vee Active Current
TTL Inputs

CE = OE = VIL, f = 5 MHz
Inputs = VIH or VIL

lec2

Vee Active Current
CMOS Inputs

CE = GND, f = 5 MHz,
Inputs = Vee or GND, I/O
C,I Temperature Ranges
Vpp

3.5

= VIH

= 0 mA

= Vcc

Ipp

Vpp Supply Current

Vpp

Vpp Read Voltage

III

Input Load Current

VIN

ILO

Output Leakage Current

VOUT

= 5.5V or GND
= 5.5V or GND

AC Electrical Characteristics Over Operating Range with Vpp
Symbol

100

Parameter
Min

Min

/-LA

Vee - 0.7

Vec

-1

/-LA

-10

/-LA

200

150
Max

/-LA

= Vce

120
Max

100

Min

Max

Min

Units
Max

tAee

Address to Output Delay

100

120

150

200

tCE

CE to Output Delay

100

120

150

200

tOE

OE to Output Delay

tOF
(Note 2)

Output Disable to
Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE orOE,
Whichever Occurred First

1-43

III
ns

CD
U')

3......

Capacitance TA = + 25°,C, f =

Symbol

CIN

Input Capacitance

COUT

Output Capacitance

:i:

Parameter

1 MHz (Note 2)

Conditions

Typ

Max

Units

VIN = OV

VOUT = OV

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note 8)
~

Input Rise and Fall Times

AC Waveforms

Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs

5 ns

0.45 to 2.4V
(Note 10)
0.8V and 2.0V
0.8V and 2.0V

(Notes 6, 7 and 9)

2.0V

ADDRESSES

o BV

2.0V
O.BV

OUTPUT

ADDRESSES VALID

2.0V

VALID OUTPUT

O.BV

t ACC
(NOTE3)
TLlO/l0833-4
Note 1: Stresses above those listed under "Absolute Maximum Aatings" may cause permanent damage to the device. This is stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for ex1ended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of

cr without impacting tACC.

Note 4: The tOF and tcF compare level is determined as follows:
High to TAI-STATE@, the measured VOHl (DC) - 0.10V;
Low to TAl-STATE, the measured Vou (DC) + 0.10V.
Note 5: TAl-STATE may be attained using

OE or CE.

Note 6: The power switching characteristics of EPAOMs require careful device decoupling. It is recommended that at least a 0.1 ,...F ceramic capacitor be used on
every device between Vcc and GND.
Note 7: The outputs must be restricted to VCC

1.0V to avoid latch-up and device damage.

Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400,...A.
CL = 100 pF includes fix1ure capacitance.
Note 9: Vpp may be connected to Vcc except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns MaJ:<.
Note 11: CMOS inputs: VIL = GND ±O.3V, VIH = VCC iO.3V.

1-44

Programming Characteristics
Symbol

(Notes

1,2,3,4 and 5)
Conditions

Parameter

Min

Typ

Max

Units

tAS

Address Setup Time

J-ts

tOES

OE Setup Time

J-ts

tvps

Vpp Setup Time

IJ-s

tves

Vee Setup Time

J-ts

tos

Data Setup Time

IJ-s

tAH

Address Hold Time

J-ts

tOH

Data Hold Time

J-ts

tOF

Output Enable to Output
Float Delay

tpw

Program Pulse Width

tOE
Ipp

VIL

Data Valid from OE

VIL

Vpp Supply Current
during Programming Pulse

=
=

VIL

0
95

100

105

J-ts

100

rnA

lee

Vee Supply Current

rnA

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

tOUT

Output Timing Reference Voltage

5
0.0

Programming Waveforms

(Note

Vpp

2.0

0.8

2.0

P~~~I~M_

Hi-Z

DATA IN STABLE
ADD N

- J

K:
tAH I -

DATA OUT YALID
ADD N

I--

I - tOF

~
"

5.75Y

tyCS

2Y
O.SV
tpw

IOE

0.8

-JJ

~
Vee

ADDRESS N

ADDRESSES O.SY

DATA

0.45

4.0

3)
PROGRAM

V
ns

t oEs

2Y
0.8V

I - tOE -

)
TL/D/10833-5

Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 J.LF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the PGM pin must be brought high (2 VIH) either coincident with or before power is applied to Vpp.

1-45

CD
Ln

r-..

Fast Programming Algorithm Flow Chart

(Same as NMC27C256B)

C'i

INCRE~ENT

ADDR

TL/D/l0833-6

FIGURE 1

1-46

E:
N
.......

Interactive Programming Algorithm Flow Chart (Note 4)

(")

INCREMENT ADDR

TL/D/l0833-9

FIGURE 2

1-47

LI)

Functional Description

N
~

DEVICE OPERATION

o.......
Z

READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vcc power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.

Programming

CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1 's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.

Read Mode

The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACe) is equal to the delay
from CE to output (tCE)' Data is available at the outputs tOE
after the falling edge of OE, assuming that CE/PGM has
been low and addresses have been stable for at least tACCtOE,

The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 fJ-F capacitor be placed across Vpp, VCC
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TIL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 fJ-s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 JLs pulse.

Standby Mode

The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 385 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.

The EPROM must not be programmed with a DC signal applied to the CE/PGM input.

Output Disable

The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirments. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.

Output OR-Typing

Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:

Note: Some programmer manufacturers, due to equipment limitation, may
offer interactive program Algorithm (shown in Figure 2),

Program Inhibit

Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel EPROMs may be
common. A TTL low level program pulse applied to an EPROM's CE/PGM input with Vpp at 12.75V will program that
EPROM. A TIL high level CE/PGM input inhibits the other
EPROMs from being programmed.

1-48

z
Functional Description

s::
N

(Continued)
length of 2537 A. The integrated dose (Le., UV intensity x
exposure time) for erasure should be a minimum of
15W-sec/ cm 2.

Program Verify

A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vcc, except during programming and program verify.

""N
o
U1

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

MANUFACTURER'S IDENTIFICATION CODE

SYSTEM CONSIDERATION

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27C256 is "SF04", where "SF" designates that
it is made by National Semiconductor, and "04" designates
a 256K part.

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vcc transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 J.lF ceramic
capacitor be used on every device between Vcc and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 J.lF bulk electrolytic
capacitor should be used between Vce and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 0 0 -07. Proper code
access is only guaranteed at 25°C to ± 5°C.
ERASURE CHARACTERISTICS

III

1-49

Mode Selection
Themodes of operation of NM27C256 listed in Table I. A single 5V power supply is required in the read mode. All inputs are TTL
levels except for Vpp and A9 for device signature.
TABLE I. Modes Selection
Pins
Mode
Read
Output Disable
Standby
Programming

CE/PGM

Vpp

Vee

Outputs

VIL

Vee

5.0V

Dour

X
(Note 1)

VIH

Vee

5.0V

High-Z

VIH

Vee

5.0V

High-Z

VIL

VIHX

12.75V

6.25V

DiN

12.75V

Dour

6.25V

High-Z

Program Verify

VIL

12.75V

Program Inhibit

VIH

12.75V

Note 1: X can be VrL or VrH.

TABLE II. Manufacturer's Identification Code
AO
(10)

A9
(24)

Manufacturer Code

VIL

Device Code

VIH

Pins

03
(15)

02
(13)

07
(19)

06
(18)

05
(17)

04
(16)

12V

1-50

01
(12)

00
(11)

Hex
Data

~National

oCJ1

~ Semiconductor

.....
N

NM27C512
524,288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The NM27C512 is a high performance 512K UV Erasable
Electrically Programmable Read Only Memory. It is manufactured in National's latest CMOS split gate EPROM technology, which enables it to operate at speeds as fast as
120 ns access time over the full operating range.
The NM27C512 provides microprocessor-based systems
storage capacity for portions of operating system and application software. Its 120 ns access time provides nowait-state operation with high-performance CPUs. The
N M27C512 offers a single chip solution for the code storage
requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from
EPROM storage, greatly enhancing system utility.
The NM27C512 is configured in the standard JEDEC
EPROM pinout which provides an easy upgrade path for
systems which are currently using standard EPROMs.

The NM27C512 is one member of a high density EPROM
Family which range in densities up to 4 Megabit.

Features
• High performance CMOS
- 120 ns access time
• Fast turn-off for microprocessor compatibility
• High reliability with EPI processing
- Latch-Up immunity to 200 mA
- ESD protection exceeds 2000V
• JEDEC standard pin configuration
- 2S-pin DIP package
- 32-pin chip carrier
• Manufacturers identification code

Block Diagram
DATA OUTPUTS 0.-07
Vee 0---+

GND 0---+

OUTPUT
BUffERS

Y GATING

AD-AI5
ADDRESS
INPUTS

52u....rr

CEll MATRIX

TLlD/10834-1

1-51

C\I
,...
I.t)

o
.....

Connection Diagrams

27C080 27C040 27C020 27C010 27C256

C\I

-A 1S C 1

'-"

A12 C 2
- A7 C 3

pVcc-

25 p A s - -

-AsC 5

24 PA9 - -

- A4 C 6

23PA l1 -

- A2 C 8
- A 1C 9
-AcC 10

22 P

OE/Vpp-

21PA 10 20 P cr/PGij19P 07 - -

-OoC 11

18P 0 6 - - ,

-OIC 12

17 P O s - -

-02C 13

16PO,,-'-

-GNDC I"

15P Ol - -

27C020

27C080

27C040

Vee
Vee
Vee
Vee
XX/PGM XX/PGM
A1S
A1S
XX
Au
Au
Au
Vee
A14
A14
A14
A14
A14
A13
A13
A13
A13
A13
As
As
As
As
As
Ag
Ag
Ag
Ag
Ag
. An
An
A11
A11
A11
OE.
OE
OE
OE
OE/vpp
A10
A10
A10
A10
A10
CE/PGM CE/PGM
CE/PGM
CE
CE
07
07
07
07
07
06
06
06
06
06
Os
Os
Os
Os
Os
04
04
04
04
04
03
03
03
03
03

27PA1. 26 PA1l -

- A6 C"

-AlC 7

27C010

27C256

DIP
NM27C512

A19 XX/Vpp XX/Vpp XX/Vpp
A16
A16
A16
A16
Vpp
A1S
A1S
A1S
A1S
A12
A12
A12
A12
A12
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
As
As
As
As
As
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
Ao
Ao
Ao
Ao
Ao
00
00
00
00
00
01
01
01
01
01
02
02
02
02
02
GND
GND
GND
GND
GND

TL/O/l0834-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27CS12 pins.

Commercial Temp Range (O°C to

+ 70°C)

Extended Temp Range (- 40°C to

+ 85°C)

Access Time (ns)*

Parameter/Order Number

Access Time (ns)*

NM27C512 Q, N, V 120

120

NM27C512 QE, NE, VE 120

120

NM27C512 Q, N, V 150

150

NM27C512 QE, NE, VE 150

150

NM27C512 Q, N, V 200

200

NM27C512 QE, NE, VE 200

200

Parameter/Order Number

Military Temp Range (- 55°C to
Parameter/Order Number

+ 125°C)

Note: Surtace mount PLCC package available for commercial and extended
temperature ranges only.
• All versions are guaranteed to function for slower speeds.

Access Time (ns)*

NM27C512 QM 200

200

Package Types: NM27C512 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP Package
N = Plastic OTP DIP Package
V = PLCC Package
• All packages conform to the JEDEC standard.
PLCC

Pin Names
AO-A15

Addresses

Chip Enable

Output Enable

rff¥ ,t3ff
As-

1 32 31 30
29 -As

As- 6

28 - Ag

A. -

27 -~1
26 -NC

00-07

Outputs

A3 -

PGM

Program

A2 ~ -

25 -

Don't Care (During Read)

OE/Vpp

-~o

Ao-

24
23

NC -

22 r-~

00 -

r- RtpGt;i
I- 06

14 15 16 17 18 19 20
I

I", ~ ~

I", I... ~

OOt§ZOO

TLlO/l 0834-3

1-52

Absolute Maximum Ratings

(Note 1)

If MilitaryI Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbuto,rs for availability and specifications.
Storage Temperature

Vee Supply Voltage with
Respect to Ground

Vpp and A9 with Respect to Ground

-0.6Vto +7V

All Output Voltages with
Respect to Ground

-0.6Vto +7V

>2000V

Vee + 1.0VtoGND -0.6V

-0.7V to + 14V

Operating Range
Range

Temperature

Vee

Tolerance

Comm'l

O°Cto +70°C

+5V

±10%

- 40°C to + 85°C

+5V

±10%

- 55°C to + 125°C

+5V

±10%

Industrial
Military

Read Operation
DC Electrical Characteristics
Symbol

Parameter

Test Conditions

Min

Max

VIL

Input Low Level

-0.5

VIH

Input High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL = 2.1 mA

0.4

VOH

Output High Voltage

IOH = -400,..,A

1581

Vee Standby Current (CMOS)

CE = Vee ±0.3V

100

,..,A

1582

Vee Standby Current

CE = VIH

rnA

lee1

Vee Active Current

CE = OE = VIL

f = 5 MHz

rnA

lee2

Vee Active Current
CMOS Inputs

CE = GND, f = 5 MHz
Inputs = Vee or GND, I/O = 0 rnA
C, I Temp Ranges

rnA

Vpp = Vee

,..,A

Ipp

Vpp Supply Current

Vpp

Vpp Read Voltage

III

Input Load Current

ILO

Output Leakage Current

3.5

Units

Ve - 0.7

Vee

VIN = 5.5V or GND

-1

IJ-A

VOUT = 5.5V or GND

-10

IJ-A

AC Electrical Characteristics
Symbol

120

Parameter
Min

150
Max

Min

200
Max

Min

Units
Max

tAee

Address to Output
Delay

120

150

200

teE

CE to Output Delay

120

150

200

tOE

OE to Output Delay

tDF

Output Disable to
Output Float

tOH

Output Hold from
Addresses, CE or OE,
Whichever Occurred First

1-53

..o
CJ'1

ESD Protection
(MIL Std. 883, Method 3015.2)

- 65°C to + 150°C

All Input Voltages Except A9 with
Respect to Ground

N
......

C"II
,...
lI)

r-:lE

Capacitance TA = + 25°C, f =

C"II

Symbol

1 MHz (Note 2)
Parameter

Conditions

Typ

Max

Units

= OV

CIN1

Input Capacitance
except OElVpp

VIN

COUT

Output Capacitance

VOUT

CIN2

OElVpp Input
Capacitance

VIN

= OV

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note B)

Timing Measurement Reference Level (Note 9)
Inputs
O.BV and 2V
Outputs
O.BV and 2V

=:;;5 ns

Input Rise and Fall Times
Input Pulse Levels

0.45V to 2.4V

AC Waveforms

(Notes 6,7)

ADDRESSES

OE/V pp

OUTPUT

-- )
~:g~

ADDRESSES VALID

2.0V
O.BV

I-- tcE _

2.0V
O.BV

Hi-Z

-.tcr -

(NOT£4.5)

tOE
(NOTE 3) I--

,""""","',","'

2.0V
O.BV

.."

VALID OUTPUT

t ACC
-(NOTE3)-

"
"rr

- '\-"",,:
tor

(NOT£4.5)

I-Hi-Z

1-111,

-toHI-TL/D/l0834-4

OE may be delayed

up to tACC - toE after the falling edge of CE without impacting tACC.

Note 4: The tOF and tcF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vcc

1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400/LA.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

1-54

Programming Characteristics (Notes 1 and 2)

Units

(")
U1

tAS

Address Setup Time

JJ.s

tOES

OE Setup Time

JJ.s

Symbol

Parameter

Conditions

Min

Typ

Max

tos

Data Setup Time

JJ.s

tvcs

Vcc Setup Time

JJ.s

tAH

Address Hold Time

JJ.s

tOH

Data Hold Time

tCF

Chip Enable to Output Float Delay

tpw

Program Pulse Width

tOEH

OE Hold Time

tov

Data Valid from CE

tpRT

OE Pulse Rise Time

JJ.s

OE = VIL

100

105

JJ.s

250

OE = VIL

during Programming
tVR

Vpp Recovery Time

Ipp

Vpp Supply Current during

JJ.s

CE = VIL
OE = Vpp

Programming Pulse

.....

Icc

Vcc Supply Current

rnA

Temperature Ambient

°C

Vcc

Power Supply Voltage

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

0.45

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

O.B

tOUT

Output Timing Reference Voltage

O.B

Programming Waveforms
PROGRAt.4_
VERIFY(c..

PROGRAt.I
ADDRESSES

O.SV
~

ADDRESS N

~
DATA

2V
O.BV

~
OE/Vpp

'~~O
tpRT

CE,

"
~

DATA IN STABLE
ADON

Hi-Z

2V x

DATA OUT

O.BV~

.I-

vALi>'

ADO N

~
~

tOEH

2V
O.SV

III

"
CtvR1

Ftvcs-

Vee 6.25V
TL/D/l0834-5

Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vce.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 JLF capacitor is required across Vec to GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings.

1-55

Fast Programming Algorithm Flow Chart (Same as NMC27C512A)

INCREMENT ADDR

TL/D/10634-6

FIGURE 1

1-56

Interactive Programming Algorithm Flow Chart

......

...I.

INCREMENT ADDR

TL/D/l0B34-B

FIGURE 2

1-57

Functional Description
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are active only when data is desired from a particular memory device.

DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vee and
OElVpp. The OElVpp power supply must be at 12.75V during the three programming modes, and must be at 5V in the
other three modes. The Vee power supply must be at 6.25V
during the three programming modes, and at 5V in the other
three modes.

Programming
CAUTION: Exceeding 14V on pin 22 (OElVpp) will damage
the EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1 's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.

Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OElVpp) is the
output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tAee) is equal to
the delay from CE to output (teE)' Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tAce-tOE'

The EPROM is in the programming mode when the OElVpp
is at 12.75V. It is required that at least a 0.1 J-LF capacitor be
placed across Vee to ground to suppress spurious voltage
transients which may damage the device. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed.
The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is programmed
with a series of 100 J-Ls pulses until it verifies good, up to a
maximum of 25 pulses. Most memory cells will program with
a single 100 J-Ls pulse.
The EPROM must not be programmed with a DC signal applied to the CE/PGM input.

Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 385 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.

Output OR-Typing
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and

Note: Some programmer manufacturers, due to equipment limitation, may
offer interactive program Algorithm (shown in Figure 2).

Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OElVpp) of the parallel EPROMs may
be common. A TTL low level program pulse applied to an
EPROM's CE/PGM input with OElVpp at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits
the other EPROMs from being programmed.

1-58

Functional Description

(Continued)

length of 2537 A. The integrated dose (Le., UV intensity X
exposure time) for erasure should be minimum of
15W-sec/ cm 2 .

Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. Data
should be verified T DV after the falling edge of CEo

"'"

o
U'1
-.
N

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.

MANUFACTURER'S IDENTIFICATION CODE

The EPROM has a manufacturer's identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27C512 is "SFS5", where "SF" designates that
it is made by National Semiconductor, and "S5" designates
a 512K part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C ± 5°C.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 J1-F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 J1-F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

ERASURE CHARACTERISTICS

III

1-59

Mode Selection
The modes of operation of the NM27C512 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels excepts for Vpp and A9 for device signature.
TABLE I. Mode Selection
Pins
Mode

Outputs!

CE/PGM

OE/Vpp

Vee

VIL

5.0V

DOUT

X
(Note 1)

VIH

5.0V

HighZ
HighZ

Read
Output Disable
Standby

VIH

5.0V

Programming

VIL

Vpp(2)

6.25V

DIN

Program Verify

VIL

6.25V

DOUT

Program Inhibit

VIH

Vpp(2)

6.25V

HighZ

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code
AO
(10)

A9
(24)

07
(19)

Manufacturer Code

VIL

12V

Device Code

VIH

12V

Pins

06
(18)

05
(17)

1-60

04
(16)

03
(15)

02
(13)

01
(12)

00
(11)

Hex
Data

~National

Semiconductor

NM27C010
1,048,576-Bit (128K x 8) High Performance CMOS EPROM
General Description
The NM27C01 0 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is
organized as 128K-words of 8 bits each. Its pin-compatibility
with byte-wide JEDEC EPROMs enables upgrades through
8 Mbit EPROMs. The "Don't Care" feature during read operations allows memory expansions from 1M to 8M bits with
no printed circuit board changes.
The NM27C010 can directly replace lower density 28-pin
EPROMs by adding an A16 address line and Vee jumper.
During the normal read operation PGM and Vpp are in a
"Don't Care" state which allows higher order addresses,
such as A17, A18, and A19 to be connected without affecting the normal read operation. This allows memory upgrades to 8M bits without hardware changes. The
NM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
The NM27C010 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software. Its 100 ns access time
provides no-wait-state operation with high-performance
CPUs. The NM27C010 offers a Single chip solution for the
code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The NM27C010 is manufactured using National's advanced
CMOS SVG EPROM technology.
The NM27C010 is one member of a high density EPROM
Family which range in densities up to 4 Megabit.

Features
• High performance CMOS
- 100 ns access time
• Fast turn-off for microprocessor compatibility
• High reliability with EPI processing
- Latch-up immunity
- ESD protection
• Simplified upgrade path
- Vpp and PGM are "Don't Care" during normal read
operation
• Compatible with 27010 and 27C010 EPROMs
• JEDEC standard pin configurations
- 32-pin DIP package
- 32-pin chip carrier
• Manufacturers identification code
• Fast programming

Block Diagram
DATA OUTPUTS 00-07

Vec 0--+
GNDo--+

OUTPUT
BUFFERS

Y GATING

AD-A16
ADDRESS
INPUTS

1.1I4I.516-BIT
CEll MATRIX

TL/D/10798-1

1·61

0
~

Connection Diagrams

I'N

Z
==

DIP PIN CONFIGURATIONS

DIP
NM27C010

27C080 27C040 27C020 27C512 27C256
A19
A16
A15
A12
A7
A6
A5

XX/Vpp- 1
A16- 2

XXlVpp XXlVpp
A16
A16
A15
A15
A12
A12
A7
A7
A6
A6
A5
A5

'-..I

27C256 27C512 27C020 27C040 27C080

32 ~Vcc
31 f-XX/i'GM

A15
A12
A7
A6
A5

Vpp
A12
A7
A6
A5

A15- 3

30 f-XX

A12- 4

29 i-A14

A7- 5

28 i-A13

A6- 6

27 f-A8

A5- 7

26 f-A9

M- 8

A3
A2
A1
AD
00
01
02
GND

A3
A2
A1
AO
00
01
02
GND

A3- 9
A2- 10

Al- 11

Vee

XX/PGM

25 f-All
24 f-OE
23 f-Al0
22 f-CE
211-0 7

AO- 12

00 - 13

20 f-0s
19 f-0 s
18 f-O.
17 f-0 3

01- 14
02- 15
GNO- 16

A17
A14
A13
A8
A9
A11

Vee
Vee
A14
A14
A13
A13
A8
A8
A9
A9
A11
A11
OE
OElVpp
A10
A10
CE/PGM CE/PGM
07
07
06
06
05
05
04
04
03
03

DE
A10
CE·
07
06
05
04
03

Vee
Vee
A18
A18
Al7
A17
A14
A14
A13
A13
A8
A8
A9
A9
A11
A11
OE
OElVpp
A10
A10
CE/PGM CE/PGM
07
07
06
06
05
05
04
04
03
03

TLlD/10798-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C01 0 pins.
Commercial Temperature Range COOC to
VCC = 5V ±10%
Parameter/Order Number

+ 70·C)

I
I

Access Time (ns)

NM27C010 Q, V, N 100

100

NM27C010 Q, V, N 120

120

NM27C010 Q, V, N 150

150

NM27C010 Q, V, N 200

200

Extended Temperature Range (- 40·C to
VCC = 5V ±10%

Access Time (ns)

NM27C010 QE, VE, NE 120

120

NM27C010 QE, VE, NE 150

150

NM27C010 QE, VE, NE 200

200

Parameter/Order Number

Access Time (ns)

NM27C010 QM 200.

200

Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.

Package Types: NM27C010 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package

+ 85·C)

Parameter/Order Number

+ 125·C)

Military Temperature Range (- 55·C to
VCC = 5V ±10%

• All packages conform to JEDEC standard.
• All versions are guaranteed to function at slower speeds.

Pin Names

PLCC Pin Configuration

AO-A 16

Addresses

Chip Enable

Output Enable

00-07

Outputs

A6- 6

29 -~.
28 ~~3

PGM

Program

As- 7

27 -As

Don't Care (During Read)

>'t.
N

U')

co . . . . . .

fff~r~~

~ 4

A7 -

1 32 31 30

A. -

26 f-Ag

A3 -

A2 -

25 -~1
24 f-OE

~- 11
12

23 f-~o
22 i-CE

Ao-

°0- 13 14

21 i-~
15 16 17 18 19 20

TL/D/10798-3

Top View

1-62

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

- 65°C to + 150°C

All Input Voltages Except Ag with
Respect to Ground (Note 10)
Vpp and Ag with Respect to Ground

:s:
N

Operating Range

(Note 1)

......

Range

Temperature

Vee

Tolerance

Commercial
Industrial
Military

O°Cto + 70°C
- 40°C to + 85°C
- 55°C to + 125°C

+5V
+5V
+5V

±10%
±10%
±10%

o
.....
o

-0.6Vto +7V
-0.6Vto +14V

Vee Supply Voltage with
Respect to Ground

-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground (Note 10) Vee + 1.0V to GND - 0.6V

DC Read Characteristics Over Operating Range with Vpp =
Symbol
VIL

Parameter

Vee

Test Conditions

Input Low Level

Min

Max

Units

.-0.5

0.8

2.0

Vee + 1

0.4

VIH

Input High Level

VOL

Output Low Voltage

IOL = 2.1 mA

VOH

Output High Voltage

IOH = - 400 IlA

1581

Vee Standby Current.
(CMOS)

CE = Vee ±0.3V

1582

Vee Standby Current

CE = VIH

lee

Vee Active Current

CE = OE = VIL

Ipp

Vpp Supply Current

Vpp

Vpp Read Voltage

Vee - 0.7

Vee

III

Input Load Current

VIN = 5.5 or GND

-1

Il A

ILO

Output Leakage Current

Your

-10

IlA

3.5

f = 5 MHz

Vpp = Vee

= 5.5Vor GND

AC Read Characteristics Over Operating Range with Vpp =
Symbol

Min

Max

Min

Il A

IlA

Vee

120

100

Parameter

100

200

150
Max

Min

Max

Min

Units
Max

tAee

Address to Output Delay

100

120

150

200

teE

CE to Output Delay

100

120

150

200

tOE

OE to Output Delay

tDF
(Note 2)

Output Disable to Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, Whichever
Occurred First

1-63

o'P"
o

o.....
N

Capacitance T A = +25°C, f = 1 MHz (Note 2)
Symbol

Parameter

Conditions

Typ

Max

Units

= OV
Your = OV

VIN

CIN

Input Capacitance

COUT

Output Capacitance

AC Test Conditions
Output Load

1 TIL Gate and

Timing Measurement Reference Level

CL = 100 pF (Note 8)

AC Waveforms

(NotesS,

7, & 9)

ADDRESSES VALID

ADDRESSES

or
OUTPUT

0.8Vand 2V
0.8Vand 2V

0.45V to 2.4V

Input Pulse Levels

Inputs
Outputs

~5 ns

Input Rise and Fall Times

2.0V
O.BV

~2.~Ov~-+-_HI_-_Z-+4:-H:-H+f-H

VALID OUTPUT

HI-Z

'-I.~~~+-------~'t-----+-+""'~~

O.BV

1+-_ _ _ tAcc - - - - I

(NOTE 3)
TlID/l0798-4

rn: may be delayed up to tACC -

toE after the falling edge of ~ without impacting tACC.

Note 4: The tOF and teF compare level is determined as follows:
High to TRI·STATEIft>, the measured VOHl (DC) - 0.10V;
Low to TRI·STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI·STATE may be attained using

rn: or cr.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between Vec and GNO.
Note 7: The outputs must be restricted to Vec

1.0V to avoid latch·up and device damage.

Note 8: 1 TIL Gate: IOL = 1.6 mA, IOH = -400/LA.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vec except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

1-S4

Programming Characteristics (Notes 1, 2, 3, 4, & 5)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

JLs

Data Setup Time

JLs

tvps

Vpp Setup Time

JLs

tves

Vee Setup Time

JLs

tAH

Address Hold Time

JLs

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

tAS

Address Setup Time

tOES

OE Setup Time

teEs

CE Setup Time

tos

OE = VIH

tOE

Data Valid from OE

CE = VIL

Ipp

Vpp Supply Current during
Programming Pulse

CE = VIL
PGM = VIL

100

105

JLs

100

lee

Vee Supply Current

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

0.0

0.45

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

Programming Waveforms

(Note

a sv
~

HI-Z

DATA IN STABLE
ADDN

V
V

K:
tAH I-

DATA OUT VALID
ADON

~
Vee

4.0

P~~~~F~IoI_

ADDRESS N

DATA~

-PROGRAIoI
ADDRESSES

l-'oF

6.2SV

tves

pp
v~

CE a.sv
!-Icrs_
PGM

a.sv

\Pw
r-

-'"

JLs

CE = VIL

N
.....
oo

lors

~~sv

-'or-

r-TL/D/10798-5

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 /kF capacitor is required across VpP. Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the PGM pin must be brought high (~VIH) either coincident with or before power is applied to Vpp.

1-65

C)
.....

8.....

.-----------------------------------------------------------------------------------~

Fast Programming Algorithm Flow Chart (Same as NMC27C010)

INCREt.4ENT AD DR

TLlD/l0798-6

FIGURE 1

1-66

~
N

Functional Description

......

DEVICE OPERATION

The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 ,....F capacitor be placed across Vpp, Vcc
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied S bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

o
o

When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 ,....S pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 ,....S pulse.

Read Mode

The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins,
independent of device selection. Assuming that the addresses are stable, address access time (tACe) is equal to
the delay from CE to output (tCE)' Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tAcC-tOE'

The EPROM must not be programmed with a DC signal applied to the PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the PGM input programs the paralleled EPROM.

Standby Mode

The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 275 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.

Program InhIbit

Programming niultiple EPROM's in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel EPROM may be
common. A TTL low level program pulse applied to an
EPROM's PGM input with CE at VIL and Vpp at 12.75V will
program that EPROM. A TTL high level CE input inhibits the
other EPROM's from being programmed.

Output Disable

The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Program Verify

A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vce, except during programming and program verify.

Output OR-Tying

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.

MANUFACTURER'S IDENTIFICATION CODE

To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

The EPROM has a manufacturer's indentification code to
aid in programming. When the device is inserted in an
EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algorithm for the part. This automatic programming
control is only possible with programmers which have the
capability of reading the code.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code tor the NM27C010 is "SFS6", where "SF" designates
that it is made by National Semiconductor, and "S6" designates a 1 Megabit (12SK x S) part.

Programming

The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A1-AS, A10-A16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH tor the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C ± 5°C.

1-67

o
,...
o

o
r--

Functional Description

(Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wave·
lengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.

symptoms that can be misleading. Programmers, components and even system designs have been erroneously suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, IcC,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a O~ 1 p,F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 p,F bulk electrolytic
capacitor should beused between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces. .

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (Le., UV intensity X
exposure time) for erasure should be a minimum of 15W~
sec/cm2.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the distance from the lamp. (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause

MODE SELECTION
The modes of operation of the NM27C21 0 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TIL levels except for Vpp and A9 for device signature.
TABLE I. Modes Selection
Pins

Vpp

Vee

Outputs

5.0V

DOUT

5.0V

HighZ

5.0V

HighZ

VIL

VIH

VIL

12.75V

6.25V

DIN

Program Verify

VIL

VIH

12.75V

6.25V

DOUT

Program Inhibit

VIH

12.75V

6.25V

HighZ

VIL

VIH

Standby

VIH

Programming

PGM

Mode
Read
Output Disable

X
(Note 1)

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code

AO
(12)

A9
(26)

Manufacturer Code

VIL

12V

Device Code

VIH

12V

Pins

(21) (20)

Os
(19)

1-68

00
(13)

Hex
Data

(18) (17) (15) (14)

~National

Semiconductor

NM27C210
1,048,576-Sit (64K x 16) High Performance CMOS EPROM
General Description

Features

The NM27C210 is a high performance Electrically Programmable UV erasable ROM (EPROM). It contains 1,048,576
bits configured as 64K x 16 bit. It is offered in both erasable
versions for prototyping and early production applications
as well as non-erasable, plastic packaged versions that are
ideal for high volume and automated assembly applications.

• High performance CMOS
- 120 ns access time
• Fast turn-off for microprocessor compatibility
• High reliability with EPI processing
- Latch-up immunity
- ESD protection exceeds 2000V
• Simplified upgrade path
- Vpp and PGM are "Don't Care" during normal read
operation
• Compatible with 27210 and 27C210 EPROMs
• JEDEC standard pin configuration
- 40-pin DIP package
- 44-pin PLCC package
• Manufacturer's identification code
• Fast programming

The NM27C210 operates from a single 5 volt ± 10% supply
in the read mode.
The NM27C210 is offered in both DIP and surface mount
packages. The DIP package is a 40-pin dual-in-line ceramic
with a quartz window to allow erasing. The surface mount
package is a 44-pin PLCC that is offered in OTP.
This EPROM is manufactured using National's proprietary
1.2 micron CMOS SVG EPROM technology for an excellent
combination of speed and economy while providing excellent reliability.

Block Diagram
DATA OUTPUTS 00 - 0 15

Vee 0 - - .
GND 0 - - .
Vpp 0 - - .

OUTPUT ENABLE,
CHIP ENABLE, AND
PROGRAt.I LOGIC

OUTPUT
BUFFERS

y
Y GATING

DECODER

Ao - A15
ADDRESS
INPUTS

I,048,576-BIT
CELL MATRIX

X
DECODER

TL/0/11093-1

1-69

0
'9'-

Connection Diagrams

DIP PIN CONFIGURATIONS

r--

27C280

27C240

27C220

Ala
CE/PGM
015
014
013
012
011
010
09
Oa
GND
07
Os
05
04
03
O2
01
_00
OElVpp

XXlVpp
CE/PGM
015
014
0 13
0 12
0 11
010
09
Oa
GND
07
Os
05
04
03
02
01

XXlVpp
CE
0 15
0 14
0 13
012
0 11
0 10
09
Os
GND
07
Os
05
04
03
02
01
00
OE

QQ.
OE

DIP
NM27C210
-XX/Vppl: 1
-cr1:2
- 0 ,S I: 3

\...../

39pxx/PGIi38pNC37PA , s -

-°141:4
-OuI: S

3&PA 4 '
3Sp AU
34PA ,2 33PA 11 -

- ° ,2 1:&
-0,,1:7
-°'01: 8
-Ogl:

4OP Vcc-

~O O~~

-Oal:
-GNOI: 11
- ° 7 1 : 12
- o s l : 13
- o s l : 14

30
29
28
27

PA ,0 PAgPGNOpAa-

P A7 pAs2&P As -

- 0 4 1 : IS

2SP A4 24PA3 -

-°31:16
-°21:17
-o,1:18

23P A2 22~A,-

-°01:19
-0[1:20

21PAo-

27C220

27C240

27C280

Vee

XX/PGM
A1S
A15
A14
A13
A12
All
AlO
A9
GND
Aa
A7
As
A5
A4
A3
A2
Al
Ao

A17
A1S
A15
A14
A13
A12
All
Al0
A9
GND
As
A7
As
A5
A4
A3
A2
Al
Ao

A17
A1S
A15
A14
A13
A12
All
AlO
A9
GND
Aa
A7
As
A5
A4
A3
A2
Al
Ao

TLlD/ll093-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C21 0 pins.

Commercial Temperature Range (O°C to
VCC = 5V ±10%
Parameter/Order Number

+ 70°C)

Extended Temperature Range ( - 40°C to
VCC = 5V ±10%

+ 85°C)

Access Time (ns)

Parameter/Order Number

Access Time (ns)

NM27C210 N, Q, V 120

120

NM27C210 NE, QE, VE 120

120

NM27C210 N, Q, V 150

150

NM27C210 NE, QE, VE 150

150

NM27C210 N, Q, V 200

200

NM27C210 NE, QE, VE 200

200

Military Temperature Range (- 55°C to
VCC = 5V ±10%
Parameter/Order Number
NM27C210 QM 200

Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.

+ 125°C)

Package Types: NM27C210 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package

Access Time (ns)
200

• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.

Pin Names
AO-A 15

Addresses

CE
OE

Chip Enable

00-015

Outputs

PGM

Program
Don't Care (During Read)

JcrJltj~~ >H~~ 11

Output Enable

XX
NC

PLCC Pin Configuration

012

::/ti:1~!:i lW ;; ~i~; ;u~

0" .::8

38::

010 .::9

37::
3&::

09 ::,0
0a

::11

GND
NC

::,2
::,3

07
06
Os

No Connect

°4

35::

34::

33::

::14
::,5

Au
A'2
A11
AID
Ag
GND
NC

32:: Aa
31 ::. A7
30 ::- As

::16

1~:~nH~ [~:2;?N~

fm ?m:i9

TLlD/ll093-3

Top View

1-70

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

Commercial
Industrial
Military

Vpp and A9 with Respect to Ground

N
.....

Temperature

Range

- 65°C to + 150°C

All Input Voltages except A9 with
Respect to Ground (Note 10)

Operating Range

(Note 1)

O°Cto +70°C
- 40°C to + 85°C
- 55°C to + 125°C

Vee

Tolerance

+5V
+5V
+5V

±10%
±10%
±10%

o
N

..&.

-0.6Vto +7V
-0.6V to + 14V

Vee Supply Voltage with
Respect to Ground

-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground (Note 10)
Vee + 1.0V to GND - 0.6V

DC Read Characteristics Over Operating Range with Vpp =
Symbol

Parameter

Vee

Test Conditions

Min

Max

Units

VIL

Input Low Level

-0.5

0.8

VIH

Input High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL

VOH

Output High Voltage

IOH

= 2.1 mA
= - 400 p,A

1881

Vee Standby Current
(CMOS)

= Vee ±0.3V

1882

Vee Standby Current

CE = VIH
CE = OE = VIL
Vpp = Vee
VIN = 5.5 or GND
Your = 5.5V or GND

lee

Vee Active Current

Ipp

Vpp Supply Current

III

Input Load Current

ILO

Output Leakage Current

0.4

AC Read Characteristics Over Operating Range with Vpp =
Symbol

Min

100

p,A

-1

p,A

-10

p,A

= 5 MHz

Vee

120

Parameter

200

150
Max

Min

Max

Min

Units
Max

tAee

Address to Output Delay

120

150

200

teE

CE to Output Delay

120

150

200

tOE

OE to Output Delay

tDF
(Note 2)

Output Disable to Output Float

tOH
(Note 2)

Output Hold from Addresses.
CE or OE. Whichever
Occurred First

1-71

V
V

3.5

o
....
~
r-..

Capacitance

TA =

+ 25°C, f

C'\I

Symbol

CIN

Input Capacitance

COUT

Output Capacitance

Parameter

= 1 MHz (Note 2)

Conditions

Typ

Max

Units

VIN = OV

VOUT = OV

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note 8)
~5

Input Rise and Fall Times
Input Pulse Levels

Timing Measurement Reference Level
Inputs
Outputs

0.8Vand 2V
0.8Vand 2V

0.45V to 2.4V

AC Waveforms

(Notes 6,7, & 9)

ADDRESSES YALID

ADDRESSES

2.0Y
O.BY

2.0Y
C.BY

HI-Z

2.0Y
OUTPUT O.BY

YALID OUTPUT

tACC
(NOTE 3)
TLID/ll093-4
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: DE may be delayed up to tAee - tOE after the falling edge of CE without impacting tAee.
Note 4: The tOF and !cF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured Vou (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

at or CE.

Note 6: The power switching characteristics of EPRDMs require careful device decoupling. It is recommended that at least a 0.1 p.F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee

1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 p.A.
CL: 100 pF includes fixture capaCitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

1-72

s:
N

Programming Characteristics (Notes 1, 2, 3, 4 & 5)
Symbol

Parameter

.......

Conditions

Min

Typ

Max

Units

tAS

Address Setup Time

,...s

tOES

OE Setup Time

,...s

tCES

CE Setup Time

,...s

tos

Data Setup Time

,...s

tvps

Vpp Setup Time

,...s

tvcs

Vee Setup Time

,...s

tAH

Address Hold Time

,...s

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

toE

Data Valid from OE

Ipp

Vpp Supply Current during
Programming Pulse

= VIH

105

,...s

CE = VIL

100

CE = VIL
PGM = VIL

100

Ice

V cc Supply Current

Temperature Ambient

·C

Vcc

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

(Note

0.45

4.0

V
V

pe~~,~M-..
rr

ADDRESS N

2V
DATA ~

ItAH
HI-Z

DATA IN STABLE
ADD N

~
Vee

-PROGRAM
ADDRESSES

0.0

Programming Waveforms

.....

,...s

CE = VIL

o
N

DATA OUT VAUO
ADD N
rr

:.-

........ tor

6.25V
tves

Vl~t
pp
~

/--teEs

O.SV
-+

r<-

PGM

2V
O.SV
tpw

I-

toEs

OE a~SV

1
"'

- tOE -

,,-

r--TL/D/ll093-5

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 fLF capacitor is required across Vpp, Vec to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verity are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the PmJ pin must be brought high (:2:V,H) either coincident with or before power is applied to Vpp.

1·73

Fast Programming Algorithm Flow Chart

INCREMENT AD DR

TLlD/11093-6

FIGURE 1

1-74

Functional Description

DEVICE OPERATION

.......

o
N

.....

Programming

Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (GE) is the power control and should be used
for device selection. Output Enable (DE) is the output control and should be used to gate data to the output pins,
independent of device selection. Assuming that the addresses are stable, address access time (tACe) is equal to
the delay from CE to output (tCE)' Data is available at the
outputs toE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tACC-tOE·

CAUTION: Exceeding 14V on the Vpp or A9 pin will damage
the EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the" 1's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"D's" will be programmed, both "1's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 p.F capaCitor be placed across Vpp, Vcc
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 16 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 275 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the OE input.

When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 P.s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 p.s pulse.

Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the DE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

The EPROM must not be programmed with a DC signal applied to the PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the PGM input programs the paralleled EPROM.

Output OR-Tying
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.

1-75

o.....
N

Functional Description

Program Inhibit

ERASURE CHARACTERISTICS

Programming multiple EPROM's in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel EPROM may be
common. A TIL low level program pulse applied to an EPROM's PGM input with CE at V,L and Vpp at 12.75V will
program that EPROM. A TIL high level CE input inhibits the
other EPROM's from being programmed.

......

:!:

(Continued)

The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER'S IDENTIFICATION CODE
The EPROM has a manufacturer's identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.

SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ,..,F ceramic
capacitor be used on every device between Vee and GNO.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,..,F bulk electrolytic
capacitor should be used between Vee and GNO for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for the NM27C210 is "SF06", where "SF" designates
that it is made by National Semiconductor, and "06" designates a 1 Megabit (64K x 16) part.
The code is accessed by applying 12V ± 0.5V to address
pin Ag. Addresses A1-Aa, A10-A15, and all control pins are
held at V,L. Address pin AO is held at V,L for the manufacturer's code, and held at V,H for the device code. The code is
read on the lower eight data pins, 00-07. Proper code access is only guaranteed at 25°C ± 5°C.

1-76

MODE SELECTION
The modes of operation of the NM27C210 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels except for Vpp and A9 for device signature.
TABLE I. Modes Selection
Pins

VIL

PGM

Vpp

Vee

Outputs

5.0V

DOUT

Mode
Read

X
(Note 1)

VIH

5.0V

HighZ

Standby

VIH

5.0V

HighZ

Programming

VIL

VIH

VIL

12.75V

6.25V

DIN

Program Verify

VIL

VIH

12.75V

6.25V

DOUT

Program Inhibit

VIH

12.75V

6.25V

HighZ

Output Disable

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code
Pins

AO
(21)

A9
07 06 05 04
(31) (12) (13) (14) (15)

(16) (17) (18) (19)

Hex
Data

Manufacturer Code

VIL

12V

Device Code

VIH

12V

1-77

~ ~National
~ U Semiconductor
z
NM27C040
4,194,304-Bit (512K x 8) High Performance CMOS EPROM
General Description
The NM27C040 is a high performance, 4, 194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is
organized as 512K words of 8 bits each. Its pin-compatibility
with byte-wide JEDEC EPROMs enables upgrades through
8 Mbit EPROMs. The "Don't Care" feature on Vpp during
read operations allows memory expansions from 1M to
8 Mbits with no printed circuit board changes.
The NM27C040 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software. Its 150 ns access time
provides high speed operation with high-performance CPUs.
The NM27C040 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment.
Frequently used software routines are quickly executed
from EPROM storage, greatly enhancing system utility.

The NM27C040 is manufactured using National's advanced
CMOS SVG EPROM technology.

Features
• High performance CMOS
- 150 ns access time
• High reliability with EPI processing
- Latch-up immunity to 200 mA
- ESD protection exceeds 2000V
• Simplified upgrade path
- Vpp is a "Don't Care" during normal read operation
• JEDEC standard pin configuration
- 32-pin DIP package
• Manufacturer's identification code

Block and Connection Diagrams
DATA OUTPUTS 00 - 07

Ycc~
GND~

Ypp~

OUTPUT ENABLE,
CHIP ENABLE, AND
PROGRAIA LOGIC

I---W

OUTPUT
BUFFERS

•
•

Y GATING

y
DECODER

AO-AIB
ADDRESS
INPUTS

•
•
•
•
•

DECODER

4,194,304-BIT
CELL IAATRIX

TL/O/l0836-1

1-78

:!:

Block and Connection Diagrams (Continued)
27COSO
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

27C020
XXlVpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

N
.....
oo

DIP
NM27C040

27C010
XXlVpp
A16
A15
A12
A7
A6
A5

-XX/VppC 1
-

'-.-/

A16C 2

31pm 30 p m 29p ... , 4 -

A15C 3
-AI2C 4
-A7C5

28 p m -

-A6C 6

27pA8-

-A5C7

-A4C 8

A3
A2
A1
AO
00
01
02
GND

32 pVcc-

-A3C9
-

A2C 10

PO(--

23p""022 pcr/PGij-

-A1Cll
-

26pA9-25pAll-

AOC 12

21::J°7--

-OoC 13

20POs--

-O,CI4
- 0 2 C 15

19::J°s - 18PO.--

17::J°3 - -

GNDC 16

27C010

27C020

27COSO

Vee
XX/PGM
XX
A14
A13
A8
A9
A11
OE
A10
CE
07
06
as
04
03

Vee
XX/PGM
A17
A14
A13
A8
A9
A11
OE
A10
CE
07
06
Os
04
03

Vee
A18
A17
A14
A13
AS
A9
A11
OElVpp
A10
CE/PGM
07
06
as
04
03

0l:Io

TLlD/l0836-2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.

Extended Temperature Range (-40°C to +S5°C)
Vee = 5V ±10%

Commercial Temperature Range WC to + 70°C)
Vee = 5V ±10%
Parameter/Order Number

Access Time (ns)

Parameter/Order Number

Access Time (ns)

NM27C040 Q 150

150

NM27C040 QE 150

150

NM27C040 Q 170

170

NM27C040 QE 170

170

NM27C040 Q 200

200

NM27C040 QE 200

200

Military Temperature Range ( - 55°C to + 125°C)
Vee = 5V ±10%
Parameter/Order Number

Package Types: NM27C040 Q,VXXX
Q = Quartz-Windowed Ceramic DIP
• All packages conform to the JEDEC standard.

Access Time (ns)

NM27C040 QM 200

• All versions are guaranteed to function for slower
speeds.

200

Pin Names
AO-A16

Addresses

Chip Enable

Output Enable

00-07

Outputs

PGM

Program

Don't Care (During Read)

III

1-79

Absolute Maximum Ratings

Operating Range

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

- 65°C to + 150°C

All Input Voltages except A9 with
Respect to Ground
Vpp and A9 with Respect to Ground

Range

Temperature

Vee

Tolerance

Commercial
Industrial
Military

O°Cto +70°C
- 40°C to + 85°C
-55°C to +125°C

+5V
±5V
±5V

±10%
±10%
±10%

-0.6Vto +7V
-0.6V to + 14V

Vee Supply Voltage with
Respect to Ground

-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground

Vee +10VtoGND -0.6V

Read Operation
DC. Electrical Characteristics
Symbol

Over operating range with Vpp = Vee

Parameter

Test Conditions

Min

Max

Units

VIL

Input Low Level

-0.5

0.8

VIH

I nput High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL = 2.1 mA

VOH

Output High Voltage

IOH = -400/J-A

1581

Vee Standby Current (CMOS)

CE = Vee ± 0.3V

1882

Vee Standby Current

CE = VIH

0.4

Icc

Vee Active Current

CE = OE = VIL

Ipp

Vpp Supply Current

Vpp = Vee

Vpp

Vpp Read Voltage

3.5

V
V

f = 5 MHz

Vee - 0.4

100

/J- A

Vee

III

Input Load Current

VIN = 5.5V or GND

-1

/J-A

ILO

Output Leakage Current

VOUT = 5.5V or GND

-10

/J-A

AC Electrical Characteristics Over operating range with Vpp =
Symbol

150

Parameter
Min

Vee

170
Max

Min

200
Max

Min

Units
Max

tAee

Address to Output Delay

150

170

200

teE

CE to Output Delay

150

170

200

tOE

OE to Output Delay

tOF
(Note 2)

Output Disable to
Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, Whichever
Occurred First

1-80

Capacitance TA = + 25°C, f =
Symbol

Parameter

:!:

1 MHz (Note 2)
Typ

Max

Units

Conditions

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

.......

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note 8)
~5

Input Rise and Fall Times
Input Pulse Levels

Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2V
Outputs
0.8V and 2V

0.45V to 2.4V

AC Waveforms

(Notes 6, 7, and 9)
rr

2V)
~

ADDRESSES

ADDRESSES VALID

}

O.BV

I---t C E -

NOTE5.4,S)

O.BV
2.0V

Hi-Z

OUTPUT
O.BV

tOE
(NOTE3)

I--tCf"-

,"""",

tOf"
..... NOTES
".5)

VALID OUTPUT ;;

"',"'"

-+-

t ACC
-4-(NOTE3)-

-+-

Hi-Z

#."",

..... tOHITL/O/l0836-4

OE may be delayed up to tAec - toE after the falling edge of CE without impacting tAce.

Note 4: The tOF and tCF compare level is determined as follows:
High to TRI-STATE@. the measured VOHl (DC) - 0.10V;
Low to TRI·STATE. the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 !-IF ceramic capaCitor be used on
every device between Vce and GND.
Note 7: The outputs must be restricted to Vec

+ 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 !-IA.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to - 2.0V for 20 ns Max.

1-81

"'I::t
C)

ol"'-

r-------------------------------------------------------------------------------------------,
Programming Waveform

(Note 3)

ADDRESSES

DATA

O£ ~~8V
TLlD/10836-5

1-82

Programming Characteristics (Notes 1, 2, 3 & 4)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

tAS

Address Setup Time

J.Ls

tOES

DE Setup Time

J.Ls

tos

Data Setup Time

J.Ls

tvps

Vpp Setup Time

J.Ls

tves

Vee Setup Time

J.Ls

tAH

Address Hold Time

J.Ls

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

tOE

Data Valid from DE

Ipp

Vpp Supply Current during
Programming Pulse

CE/PGM = X

J.Ls

0
95

100

CE/PGM = X
CE/PGM = VIL

105

J.Ls

100

lee

Vee Supply Current

Temperature Ambient

·C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

0.45

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

-0.1

0.0

VIH

Input High Voltage

2.4

4.0

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

V
V

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 IlF capacitor is required across Vpp, Vee to GNO to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Progam Algorithm, at typical power supply voltages and timings.
Note 5: Ouring power up the JSroJ pin must be brought high (~VIH) either coincident with or before power is applied to Vpp.

1-83

-.:to

8
......

r-----------------------------------------------------------------------------------~

Fast Programming Algorithm Flow Chart

:e
z

INCREMENT ADDR

TL/D/l0836-6

FIGURE 1

1·84

Functional Description
To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary
device selecting function, while OE be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TIL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vcc power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.

3:
N
......
o
o
~
o

Programming

CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.

Read Mode

The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs tOE
after the falling edge of OE, assuming that CE/PGM has
been low and addresses have been stable for at least tACCtOE,

Initially, and after each erasure, all bits of the EPROM are in
the "1 's" state. Data is introduced by selectively programming "a's" into the desired bit locations. Although only
"a's" will be programmed, both "1 's" and "a's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 f..1F capacitor be placed across Vpp, VCC
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TIL.

Standby Mode

The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from of 385 mW to
0.55 mW. The EPROM is placed in the standby mode by
applying a CMOS high signal to the CE/PGM input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.

When the address and data are stable, an active low, TIL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 f..1s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 f..1s pulse.

Output Disable

The EPROM is placed in output disable by applying a TIL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in· a high impedance state (TRI-STATE).

The EPROM must not be programmed with a DC signal applied to the CE/PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TIL pulse applied
to the CE/PGM input programs the paralleled EPROM.

Output OR-Typing

Note: Some programmer manufacturers, due to equipment limitation, may
offer interactive program Algorithm (shown in Figure 2).

b) complete assurance that output bus contention will not
occur.

•
1-85

C) r-------------------------------------------------------------------------------------~

0lI:l"

Functional Description

C\I

Program Inhibit

Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OE) of the parallel EPROMs may be
common. A TTL low level program pulse applied to an
EPROM's CE/PGM input with Vpp at 12.75V will program
that EPROM. A TTL high level CE/PGM input inhibits the
other EPROMs from being programmed.

o
r....

::!:

(Continued)
lengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (Le., UV intensity X
exposure time) for erasure should be minimum of
15W-sec/cm 2 .
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.

Program Verify

An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time
increases by factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.

AFTER PROGRAMMING

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 flF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 flF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27C040 is "SFOS", where "SF" designates that
it is made by National Semiconductor, and "OS" designates
a 4 Megabit (512K x S) part.
The code is accessed by applying 12V ±0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07' Proper code
access is only guaranteed at 25°C ± 5°C.
ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wave-

1-S6

Mode Selection
The modes of operation of the NM27C040 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels except for Vpp and A9 for device signature.

III

1-87

~National
" D
Semiconductor
c
o

:;::;
Co)
Q)

t/)

:!5

Processor Oriented EPROM Selection Guide

oa:
D..

General Description

cQ)

National Semiconductor's family of Processor Oriented
EPROMs are devices with features or functions to enhance
their operation with various microprocessors and microcontrollers. There are 3 devices with specification improvements to help eliminate wait states and glue logic. These

"i:

o...
o

UJ
UJ

are the NM27P512, NM27P210, and NM27P040. There is
one device that has address latches to facilitate multiplexed
data/address busses without the use of external address
latches, the NMC87C257.

Q)
Co)

D..

Available Product
NM27P512
NM27P210
NM27P040
NMC87C257

Packages
Q,N,V
Q,N,V
Q,N,V
Q,V

Temperature Ranges·
C,E,M
C,E,M
C,E,M
C,E,M

Improved tOF/tOH

Latches

Y
Y

y
y

·Contact your National Semiconductor sales representative for military operating temperature range devices.

Ordering Information

:::~n:I_M_e_m_O_r_y_____________j-_M__

~:r r lr 1
J
Q

120

Lspeed

Processor Oriented - - - - - - - - - - - - - ' Memory Configuration
257 = 32k x 8 w/Latches
512 = 64kx8
210 = 64kx 16
040 = 512k x 8

Operating Temperature Range
No Entry = O°C to + 70°C
E = -40°C to + 85°C
M = - 55°C to + 125°C

' - - - - - - Package
Q = Quartz Window Ceramic
N = Plastic DIP (OTP)
V = PLCC (OTP)

1-88

~National

Semiconductor

NM27P512
524,288-Bit (64K x 8) Processor Oriented
CMOS EPROM
General Description

Features

The NM27P512 is a 512K Processor Oriented EPROM configured as 64k x 8. It's designed to simplify microprocessor
interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the speCification improvements are taken advantage
of in the system design. The NM27P512 is implemented in
National's advanced CMOS EPROM process to provide a
reliable solution and access times as fast as 120 ns.

• Fast output turn off to eliminate wait states
• Extended data hold time for microprocessor
compatibility
• High performance CMOS
- 120 ns access time
• High reliability with EPI processing
- Latch-up immunity to 200 mA
- ESD protection exceeds 2000V
• JEDEC standard pin configuration
• Manufacturer's identification code

The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P512 remains compatible with industry standard
JEDEC pinout EPROMs. The time from CE or OE being negated until the outputs are guaranteed to be in the high impedance state has been reduced to eliminate the need for
wait states at the termination of the memory cycle and the
data-out hold time has been extended to eliminate the need
to provide data hold time for the microprocessor by delaying
control signals or latching and holding the data in external
latches.

Block Diagram
DATA OUTPUTS De-07

OUTPUT
BUFFERS

Y GATING

AD-A15
ADDRESS

INPUTS

524.288-8IT
CELL MATRIX

TL/D/11365-1

1-89

N
.....
lI)
a.
.....

Connection Diagrams

::E

27C08o27C040 27C020 27C010 27C25S

A19
A1S
A15
A12
A7
As
A5
A4
A3
A2
A1
Ao
00
01
02
GND

A1S
A15
A12
A7
As
A5
A4
A3
A2
A1
Ao
00
01
02

GND

27C256

DIP
NM27P512

XX/Vpp XX/Vpp XX/Vpp
Vpp

-A,sC 1

A12
A7
As
A5
A4
A3
A2
A1
Ao
00
01
02

- A, 2 C 2
- A7 C 3

-AgC 4

2SPAa24PAg--

-A.C 6

23PA,,-

- A2 C

-A,C 9

-AcC 10

A14
A13
As
Ag
A11

21PA,020

A10

pcrfPGt,l-

19P<7 - 18POs--

-o,c

CEiPGM

16PO.--

-GNDC 14

15P 03 - -

07
Os
05
04
03

bos - -

- 0 2 C 13

27C040

27C080

Vee

A1S
A17
A14
A13
As
Ag
A11
OE
A10

A1S
A17
A14
A13
As
Ag
A11

A14
A13
As
Ag
A11

22 POE/Vpp -

-<>oC 11
12

27C020

Vee
Vee
XX/PGM XX/PGM
XX
A17

Vee

2SPA,3 -

-AsC 5
- A3 C 7

GND

28pVcc 27PA,. -

27C010

A10

CE/j5GM CE/j5GM

07
Os
05
04
03

OE/vpp

07
Os
05
04
03

07
Os
Os
04
03

TLlD/11365-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27PS12 pins.
Commercial Temp Range (O°C to
Parameter/Order Number

+ 70°C)

Extended Temp Range ( - 40°C to

+ 85°C)

Access Time (ns)*

Parameter/Order Number

NM27P512 0, N, V 120

120

NM27P5120E, NE, VE 120

120

NM27P512 0, N, V 150

150

NM27P5120E, NE, VE 150

150

Military Temp Range (- 55°C to
Parameter/Order Number

Note: Surface mount PLee package available for commercial and extended
temperature ranges only.

+ 125°C)

Access Time (ns)*

NM27P512 OM 200

Access Time (ns)*

• All versions are guaranteed to function for slower speeds.

200
Package Types: NM27P512 0, N, V XXX
Quartz-Windowed Ceramic DIP Package
N = Plastic OTP DIP Package
V = PLCC Package

• All packages conform to the JEDEC standard.
Pin Names
AO-A15

Addresses

Chip Enable

Output Enable

00-07

Outputs

PGM
XX

PLCC

fff¥fff

1 32 31 30

f- A8

Ag -

AS -

28 r- Ag

A. -

27 f- A"

A3 -

Program

A2 -

25 r- OE/Vpp

Don't Care (During Read)

Ac -

23 f-

NC -

22 f- <7

00 -

A,- 10

f- NC

24 r-A,o

21 f-06
14 15 16 17 18 19 20

!-IN~~I",I
..
o
zOO
~

TLlD/11365-3

1-90

Absolute Maximum Ratings

(Note 1)

If Military/ Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

Vee Supply Voltage with
Respect to Ground

- 65°C to + 150°C

All Input Voltages Except A9 with
Respect to Ground
Vpp and A9 with Respect to Ground

-0.6Vto +7V

ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground

-0.6Vto +7V

>2000V

Vee + 1.0VtoGND -0.6V

-0.7V to + 14V

Operating Range
Range

Temperature

Vee

Tolerance

Comm'l

O°Cto + 70°C

+5V

±10%

Industrial

-40°C to + 85°C

+5V

±10%

Military

- 55°C to + 125°C

+5V

±10%

Read Operation
DC Electrical Characteristics
Symbol

Test Conditions

Parameter

Min

Max

Units

VIL

Input Low Level

-0.5

VIH

Input High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL = 2.1 mA

VOH

Output High Voltage

IOH = -400,....A

1581(10)

Vee Standby Current (CMOS)

CE = Vee ±0.3V

1582

Vee Standby Current

CE = VIH

0.4
3.5

V
V

f = 5 MHz

100

,....A

lee

Vee Active Current

CE = OE = VIL

Ipp

Vpp Supply Current

Vpp = Vee

Vpp

Vpp Read Voltage

Ve - 0.7

Vee

III

Input Load Current

VIN = 5.5V or GND

-1

,....A

ILO

Output Leakage Current

VOUT = 5.5VorGND

-10

,....A

AC Electrical Characteristics
Symbol

120

Parameter
Min

150
Max

Min

200
Max

Min

Units
Max

tAee

Address to Output Delay

120

150

200
200

teE

CE to Output Delay

120

150

tOE

OE to Output Delay

tOF(2)

Output Disable to Output Float

tOH(2)

Output Hold from Addresses, CE
or OE, Whichever Occurred First

1-91

III

N
'9"'"

......
N
:E

Capacitance T A = + 25°C, f =
Symbol

1 MHz (Note 2)

Parameter

Conditions

Input Capacitance
except OE/vpp

VIN = OV

COUT

Output Capacitance

VOUT = OV

CIN2

OE/vpp Input
Capacitance

VIN = OV

CIN1

Typ

Max

Units

AC Test Conditions
Output Load

Timing Measurement Reference Level (Note 9)
Inputs
0.8V and 2V
Outputs
0.8V and 2V

1 TIL Gate and
CL = 100 pF (Note 8)
~5

Input Rise and Fall Times
Input Pulse Levels

0.45V to 2.4V

AC Waveforms

(Notes 6,7)

ADDRESSES

2.0V
O.BV

DE/Vpp

2.0V
O.BV

OUTPUT

ADDRESSES VALID

2.0V

VALID OUTPUT

O.BV

tACC
(NOTE 3)

TLID/11365-4

DE may be

delayed up to tACC - toE after the falling edge of CE without impacting tACC'

Note 4: The tOF and tCF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOlt (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

DE or CE.

1.0V to avoid latch-up and device damage.

Note 8: 1 TIL Gate: IOL = 1.6 mA, IOH = - 400 /LA.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 10: CMOS inputs; VIL

= GND ±0.3V, VIH = VCC ±0.3V.

1-92

s:
N

Programming Characteristics (Notes 1 and 2)
Symbol

Parameter

Conditions

Typ

Min

Max

Units

.,.,.......
U1
...6

tAS

Address Setup Time

/-,-S

tOES

OE Setup Time

/-,-S

tos

Data Setup Time

/-,-S

tvcs

Vcc Setup Time

/-,-S

tAH

Address Hold Time

/-,-S

tOH

Data Hold Time

tCF

Chip Enable to Output Float Delay

tpw

Program Pulse Width

tOEH

OE Hold Time

tov

Data Valid from CE

tpRT

DE Pulse Rise Time

DE =

/-,-S

VIL

100

105

/-,-S

250

OE = VIL

during Programming
tVR

Vpp Recovery Time

Ipp

Vpp Supply Current during
Programming Pulse

/-,-S

= VIL
OE = Vpp

rnA

Icc

Vcc Supply Current

rnA

Temperature Ambient

·C

Vcc

Power Supply Voltage

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

tFR

Input Rise, Fall Time

V
ns

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

tOUT

Output Timing Reference Voltage

0.8

0.45

V
V

Programming Waveforms
P~~~~AyM_

PROGRAM
ADDRESSES

C.SV
~

.,-

ADDRESS N

~
DATA

2V
a.BV

DATA IN STABLE
ADDN

~
OE/Vpp

'~~o
\PRT

Hi-Z

2V x
a.BVlI.

DATA OUT VALID ADD N

~~
IoEH

2V
C.SV

Ftves-

t VR

1
"

•

~
~

.,1
"

Vee 6.2SV
TL/D/11365-5

Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 ",F capacitor is required across Vee to GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings.

1-93

N
..-

......

Fast Programming Algorithm Flow Chart

INCREMENT ADDR

TlI0/11365-6

FIGURE 1

1-94

Interactive Programming Algorithm Flow Chart

INCREMENT ADDR

II
TLIO/11365-7

FIGURE 2

1-95

....
~
:E.....
N

r---------------------------------------------------------------------~

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TIL levels. The power supplies required are Vee and
OElVpp. The OElVpp power supply must be at 12.75V during the three programming modes, and must be at 5V in the
other three modes. The Vee power supply must be at 6.25V
during the three programming modes, and at 5V in the other
three modes.

Programming

CAUTION: Exceeding 14V on pin 22 (OElVpp) will damage
the EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1 's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "D's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.

Read Mode

The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OElVpp) is the
output control and should be used to gate data to the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tAee) is equal to
the delay from CE to output (teE)' Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tAce-tOE'

The EPROM is in the programming mode when the OElVpp
is at 12.75V. It is required that at least a 0.1 fLF capacitor be
placed across Vee to ground to suppress spurious voltage
transients which may damage the device. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TIL.
When the address and data are stable, an active low, TIL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed.

Standby Mode

The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is programmed
with a series of 100 fLs pulses until it verifies good, up to a
maximum of 25 pulses. Most memory cells will program with
a single 100 fLs pulse.
The EPROM must not be programmed with a DC signal applied to the CE/PGM input.

Output Disable
The EPROM is placed in output disable by applying a TIL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TIL pulse applied
to the CE/PGM input programs the paralleled EPROM.

Output OR-Typing

Note: Some programmer manufacturers, due to equipment limitation, may
offer interactive program Algorithm (shown in Figure 2),

Program Inhibit

a) the lowest possible memory power dissipation, and

Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OElVpp) of the parallel EPROMs may
be common. A TIL low level program pulse applied to an
EPROM's CE/PGM input with OElVpp at 12.75V will program that EPROM. A TIL high level CE/PGM input inhibits
the other EPROMs from being programmed.

b) complete assurance that output bus contention will not
OC~~

To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary
device selecting function, while OElVpp be made a common connection to all devices in the array and connected to
the READ line from the system control bus.

1-96

Functional Description

s::
N

(Continued)

.......

length of 2537 A. The integrated dose (Le., UV intensity x
exposure time) for erasure should be minimum of
15W-sec/cm2.

Program Verify

A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. Data
should be verified T DV after the falling edge of CEo

-a
CJ1

......

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

MANUFACTURER'S IDENTIFICATION CODE

The EPROM has a manufacturer's identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P512 is "SFS5", where "SF" designates that
it is made by National Semiconductor, and "S5" designates
a 512K part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C ± 5°C.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 J.LF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 J.LF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

ERASURE CHARACTERISTICS

1-97

Mode Selection
The modes of operation of the NM27P512 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TTL levels excepts for Vpp and A9 for device signature.
TABLE I. Mode Selection
Pins

CE/PGM

OE/Vpp

Vee

Outputs

VIL

5.0V

Dour

VIH

5.0V

HighZ

VIH

5.0V

HighZ

Programming

VIL

Vpp(2)

6.25V

DIN

Program Verify

VIL

6.25V

Dour

Program Inhibit

VIH

Vpp(2)

6.25V

HighZ

Mode
Read

Output Disable

(Note 1)
Standby

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code
AO
(10)

A9
(24)

07
(19)

Manufacturer Code

VIL

12V

Device Code

VIH

12V

Pins

06
(18)

05
(17)

04
(16)

1·98

03
(15)

02
(13)

01
(12)

00
(11)

Hex
Data

~National

Semiconductor

NM27P210
1,048,576-Bit (64K
CMOS EPROM

16) Processor Oriented

General Description
The NM27P210 is a 1024K Processor Oriented EPROM
configured as 64K x 16. It's designed to simplify microprocessor interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the specification improvements are taken advantage
of in the system design. The NM27P210 is implemented in
National's advanced CMOS EPROM process to provide a
reliable solution and access times as fast as 120 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P210 remains compatible with industry standard
JEDEC pinout EPROMs. The time from CE or OE being negated until the outputs are guaranteed to be in the high impedance state has been reduced to eliminate the need for
wait states at the termination of the memory cycle and the

data-out hold time has been extended to eliminate the need
to provide data hold time for the microprocessor by delaying
control signals or latching and holding the data in external
latches.

Features
• Fast output turn-off to eliminate wait states
• Extended data hold time for microprocessor
compatibility
• High performance CMOS
- 120 ns access time
• High reliability with EPI processing
- LatCh-up immunity to 200 mA
- ESD protection exceeds 2000V
• JEDEC standard pin configuration
• Manufacturer's identification code

Block Diagram
DATA OUTPUTS 00 - 015

Vee 0--+

GND 0--+
vpp

0--+

OUTPUT
BUffERS

Y GATING

Ao -

A15

ADDRESS
INPUTS
I,O~B,576-BIT

CELL I.IATRIX

TLlD/11366-1

1-99

C) ~----------------------------------------------------------------------------------------~
'P"'

Connection Diagrams

DIP PIN CONFIGURATIONS

.......

::::E

27C280

27C240

27C220

A1S

XX~

XXlVpp
CE
01S
014
013
012
0 11
010
09
Os
GND
07
Os
Os
04
03
02
01
00
OE

cr/P'GM
01S
014
0 13
012
011
010
09
Oa
GND
07
Os
Os
04
03
02
01
_00
OElVpp

cr/P M
01S
014
013
0 12
0 11
010
09
Os
GND
07
Os
Os
04
03
02
01
00

DIP
NM27P210

-cr
-0,5

1.,0AgGND-

ASA7 -

A,;-

As-

A.A3 A2 -

27C220

27C240

27C280

Vee

XX/PGM
A1S
A1S
A14
A13
A12
All
AlO
A9
GND
As
A7
As
As
A4
A3
A2
Al
Ao

A17
A1S
A1S
A14
A13
A12
All
AlO
A9
GND
As
A7
As
As
A4
A3
A2
Al
Ao

A17
A1S
A1S
A14
A13
A12
All
Al0
A9
GND
Aa
A7
As
As
A4
A3
A2
Al
Ao

TL/D/113S6-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P21 0 pins.

Commercial Temperature Range WC to
VCC = 5V ±10%
Parameter/Order Number

+ 70°C)

Extended Temperature Range (- 40°C to
VCC = 5V ±10%

Access Time (ns)

Parameter/Order Number

+ 85°C)

Access Time (ns)

NM27P210 0, V 120

120

NM27P210 OE, VE 120

120

NM27P210 0, V 150

150

NM27P210 OE, VE 150

150

Military Temperature Range (-55°C to
VCC = 5V ± 10%
Parameter/Order Number
NM27P210 OM 200

Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.

+ 125°C)

Package Types: NM27P210 0, V XXX
= Ouartz-Windowed Ceramic DIP package
V = PLCC package

Access Time (ns)
150

• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applications.

Pin Names
AO-A15

Addresses

Chip Enable

Output Enable

00-015

Outputs

PGM

Program

Don't Care (During Read)

No Connect

PLCC Pin Configuration
>'t

cr crcrltt -a- ~

ti !2! til;;;;i ~~ ;~:3:9

0,2 _7::ts! ts! t4!

>8~ ~ ; ;

_::s
_::9

::11

35::

GND

::12

34::

GND

::13

33::

::14

32::

3B::

A,3
1.,2
1."
1.,0
Ag

0'0

37::

::10

36::

~: ~;::
o.

~~ ;~- ~

1:i~~gr~rj1tlr2i3f~r~~~f?~~:i9
0"" ONO

oOI~ ~

-P.c

...:{"'<>'1 "",.

TL/D/11366-3

Top View

1-100

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

- 65'C to + 150'C

All Input Voltages except A9 with
Respect to Ground (Note 10)
Vpp and A9 with Respect to Ground

Operating Range

(Note 1)

-......

Range

Temperature

Vee

Tolerance

Commercial
Industrial
Military

O'Cto +70'C
- 40'C to + 85'C
- 55'C to + 125'C

+5V
+5V
+5V

±10%
±10%
±10%

-a

N
.....

-0.6Vto +7V
-0.6V to + 14V

Vcc Supply Voltage with
Respect to Ground

-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground (Note 10)
Vee + 1.0V to GND - 0.6V

DC Read Characteristics Over Operating Range with Vpp =

Vee

Min

Max

Units

Vil

Input Low Level

-0.5

0.8

VIH

Input High Level

2.0

Vec + 1

0.4

Symbol

Parameter

Test Conditions

VOL

Output Low Voltage

IOl = 2.1 mA

VOH

Output High Voltage

IOH = -400 J-tA

1581

(Note 11)

VCC Standby Current
(CMOS)

3.5

Vcc ±0.3V

1582

Vec Standby Current

Icc

Vec Active Current

Ipp

Vpp Supply Current

III

Input Load Current

= VIH
= OE = Vil
Vpp = Vcc
VIN = 5.5 or GND

IlO

Output Leakage Current

VOUT = 5.5V or GND

f = 5 MHz

100

J-tA

-1

J-tA

-10

J-tA

AC Read Characteristics Over Operating Range with Vpp = Vce
Symbol

150

120

Parameter
Min

Max

Min

Units
Max

tACC

Address to Output Delay

120

150

tCE

CE to Output Delay

120

150

tOE

OE to Output Delay

tOF/tCF
(Note 2)

Output Disable to Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, Whichever
Occurred First

1-101

o
,...
,....

~
N

:!:

Capacitance T A = + 25°C, f
Symbol

= 1 MHz (Note 2)

Typ

Max

Units

CIN

Input Capacitance

Parameter

VIN = OV

COUT

Output Capacitance

VOUT = OV

Conditions

AC Test Conditions
Output Load

1 TIL Gate and

Timing Measurement Reference Level

CL = 100 pF (Note 8)

::;:5 ns

Input Rise and Fall Times
Input Pulse Levels

0.8V and 2V
0.8V and 2V

0.45V to 2.4V

AC Waveforms

(Notes

6, 7,&9)

ADDRESSES VALID

ADDRESSES

2.0V
O.BV

OUTPUT

Inputs
Outputs

~2-=.O~V:---+-_Hi_-_Z_+H-+++++i-<
VALID OUTPUT
O.BV
~~~~~_ _ _ _ _ _ _ _--'. r,...-----+---......."

Hi-Z

~_ _ _ tACC _ _ _~

(NOTE 3)
TL/D/11366-4

cr without impacting tAee.

Note 4: The tOF and tcF compare level is determined as follows:
High to TRI·STATEIB>, the measured VOH1 (DC) - 0.10V;
Low to TRI·STATE, the measured VOLl (DC) + 0.10V.
Note 5: TRI·STATE may be attained using DE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee

1.0V to avoid latch·up and device damage.

Note 8: 1 TIL Gate: IOL = 1.6 mA, IOH = -400/LA.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS inputs; VIL

GND ±O.3V, VIH

Vee ±O.3V.

1·102

Programming Characteristics (Notes 1, 2, 3, 4 & 5)
Symbol

Parameter

Conditions

Typ

Min

Max

Units

tAS

Address Setup Time

J-Ls

tOES

OE Setup Time

J-Ls

tCES

CE Setup Time

J-Ls

tos

Data Setup Time

J-Ls

tvps

Vpp Setup Time

J-Ls

tvcs

Vcc Setup Time

J-Ls

tAH

Address Hold Time

J-Ls

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

tOE

Data Valid from OE

Ipp

Vpp Supply Current during
Programming Pulse

VIH

J-Ls

VIL

CE
CE

100

VIL

= VIL
PGM = VIL

105

J-Ls

100

Ice

Vcc Supply Current

Temperature Ambient

·C

Vce

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

5
0.0

Programming Waveforms

V
V

P~~~~FAyt.l_

' - " - - - PROGRAM

ADDRESS N

DATA~

ilAH

Hi-Z

DATA INSTABLE
ADD N

.. DATA OUT VALID
ADD N

~
I-

I--Ior

6.2SV

tves

Vl~
pp

0.45

4.0

(Note 3)

ADDRESSES O.8V

Vee

V
ns

•

O.8V

!-IcES_
2V
PGIot O.8V

ipw

I-

IoEs

2V
OE O.8V

~IoE-

Tl/D/11366-5

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 /LF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the

PGM pin must be brought high

(~VIH) either coincident with or before power is applied to Vpp.

1-103

o
.....

......

Fast Programming Algorithm Flow Chart

C\I

Z
==

INCRE~ENT

ADDR

TL/D/11366-6

FIGURE 1

1·104

Functional Description
DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vccand
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vcc power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.

Programming

Read Mode

CAUTION: Exceeding 14V on the Vpp or A9 pin will damage
the EPROM.

The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins,
independent of device selection. Assuming that the addresses are stable, address access time (tACe) is equal to
the delay from CE to output (tCE). Data is available at the
outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least
tACC-tOE·

Initially, and after each erasure, all bits of the EPROM are in
the "1 's" state. Data is introduced by selectively programming "D's" into the desired bit locations. Although only
"D's" will be programmed, both "1 's" and "D's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 flF capacitor be placed across Vpp, Vcc
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 16 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 fls pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 fls pulse.
The EPROM must not be programmed with a DC Signal applied to the PGM input.

Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simpliCity of the
programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the PGM input programs the paralleled EPROM.

III
I

1-105

C) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

.....

Functional Description

C\I

Program Inhibit

Programming multiple EPROM's in parallel with different
data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel EPROM may be
common. A TIL low level program pulse applied to an EPROM's PGM input with CE at VIL and Vpp at 12.75V will
program that EPROM. A TIL high level CE input inhibits the
other EPROM's from being programmed.

C\I

r-..

:IE

(Continued)
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 30ooA-400oA range.

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (Le., UV intensity x
exposure time) for erasure should be a minimum of 15Wsec/cm 2 .
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.

Program Verify

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 J-tF ceramic
capacitor be used on every device between Vee and GNO.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 J-tF bulk electrolytic
capacitor should be used between Vee and GNO for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for the NM27P210 is "8FOS", where "8F" designates
that it is made by National Semiconductor, and "OS" designates a 1 Megabit (S4K x 1S) part.
The code is accessed by applying 12V ±0.5V to address
pin Ag. Addresses A1-Aa, A1O-A15, and all control pins are
held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The code is
read on the lower eight data pins, 00-07. Proper code access is only guaranteed at 25°C ± 5°C.

1-10S

s:
N

MODE SELECTION
The modes of operation of the NM27P210 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TIL levels except for Vpp and A9 for device signature.

1·107

......

"'D

N
......
o

~National

~ Semiconductor

NM27P040
4,194,304-Bit (512K x 8) Processor Oriented
CMOS EPROM
General Description
The NM27P040 is a 4096K Processor Oriented EPROM
configured as 512K x 8. It's designed to simplify microprocessor interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the specification improvements are taken advantage
of in the system design. The NM27P040 is implemented in
National's advanced CMOS EPROM process to provide a
reliable solution and access times as fast as 150 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P040 remains compatible with industry standard
JEDEC pinout EPROMs. The time from CE or OE being
negated until the outputs are guaranteed to be in the high
impedance state has been reduced to eliminate the need
for wait states at the termination of the memory cycle and

the data-out hold time has been extended to eliminate the
need to provide data hold time for the microprocessor by
delaying control signals or latching and holding the data in
external latches.

Features
• Fast output turn off to eliminate wait states
• Extended data hold time for microprocessor
compatibility
• High performance CMOS
- 150 ns access time
• High reliability with EPI processing
- Latch-up immunity to 200 mA
- ESD protection exceeds 2000V
• JEDEC standard pin configuration
• Manufacturer's identification code

Block Diagram
DATA OUTPUTS 00 - 07

Vcc~

______

~A,

______

GND~

vpp~

OE
PGM

OUTPUT ENABLE,
CHIP ENABLE, AND
PROGRAM LOGIC

y
DECODER

AO-A 18
ADDRESS
INPUTS
X
DECODER

1--""

OUTPUT
BUFFERS

•
•

Y GATING

•
•
•
•
•

4,194,304-BIT
CELL MATRIX

TLlD/11367-1

1-108

Connection Diagrams
27C080

27C020

.......

27C010

A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO

XXlVpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO

XXlVpp
A16
A15
A12
A7
A6
A5

00
01
02

GND

"'tJ

DIP
NM27P040
- XX/VppC 1

-AI6C 2

32pVcc 31 : ' A I 8 -

30 P A I 7 -

AISC 3

-AI2C 4

29t:!AI4-

-A7CS

28pA13-

-A6C6

27 : ' A 8 - -

-ASC7

26;=1A9--

-A4C 8

A3
A2
A1
AO

\..J

-A3C9

2SPAll24;=10£--

- A 2 C 10

23fJA10-

-A1Cll

22 P

-AOC 12

21P~-

-OoCI3
-O,C14

20bos - 19;=105 - -

- 0 2 C IS

18bo, - -

17;=1°3--

CNOC 16

CI!PGii -

27C010

27C020

27C080

Vee
XX/PGM
XX
A14
A13
AS
A9
A11
OE
A10
CE

XX/PGM
A17
A14
A13
AS
A9
A11
OE
A10
CE

Vee
A1S
A17
A14
A13
AS
A9
A11
OElVpp
A10
CE/PGM

07
06

04
03

oI:lo

TLlD/11367-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P040 pin.

Commercial Temperature Range WC to
Vee = 5V ±10%
Parameter/Order Number

+ 70·C)

Extended Temperature Range ( - 40·C to
Vee = 5V ±10%

Access Time (ns)

Parameter/Order Number

+ 85·C)

Access Time (ns)

NM27P040 Q 150

150

NM27P040 QE 150

150

NM27P040 Q 170

170

NM27P040 QE 170

170

Military Temperature Range (- 55·C to
Vee = 5V ±10%
Parameter/Order Number

+ 125·C)

Package Types: NM27P040 QXXX
Q = Quartz-Windowed Ceramic DIP
• All packages conform to the JEDEC standard.

Access Time (ns)

NM27P040 QM 200

• All versions are guaranteed to function for slower
speeds.

250

Pin Names
AO-A16

Addresses

Chip Enable

Output Enable

00-07

Outputs

PGM

Program

Don't Care (During Read)

III

1-109

Absolute Maximum Ratings

Operating Range

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65°C to + 150°C
All Input Voltages except A9 with
Respect to Ground
Vpp and A9 with Respect to Ground
Vee Supply Voltage with
Respect to Ground

Range

Temperature

Vee

Tolerance

Commercial
industrial
Military

O°Cto +70°C
- 40°C to + 85°C
- 55°C to + 125°C

+5V
±5V
±5V

±10%
±10%
±10%

-0.6Vto +7V
-0.6V to + 14V
-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground

Vee + 10V to GND-0.6V

Read Operation
DC Electrical Characteristics Over operating range with Vpp =
Symbol
VIL

Parameter
Input Low Level

VIH

Input High Levei

VOL

Output Low Voltage

iOL = 2.1 rnA

VOH

Output High Voltage

IOH = -400 IlA

1581

Vee Standby Current (CMOS)
(Note 11)

Min

Max

Units

-0.5

0.8

2.0

Vee + 1

0.4

Vee Standby Current

CE = VIH

Ice

Vee Active Current

CE =

Ipp

, Vpp Supply Current

Vpp

Vpp Read Voltage

ill

Input Load Current

ILO

Output Leakage Current

3.5

= Vee ± 0.3V

1582

OE = VIL, f = 5 MHz

Vpp = Vee

100

' IlA

rnA

Il A

Vee - 0.4

Vee

VIN = 5.5V or GND

-1

Il A

Your

-10

Il A

= 5.5V or GND

AC Electrical Characteristics Over operating range with Vpp =
Symbol

Vee

Test Conditions

Vee

150

Parameter
Min

250

170
Max

Min

Max

Min

Units
Max

tAce

Address to Output Delay

150

170

250

teE

CE to Output Delay

150

170

250

tOE

OE to Output Delay

tOF/teF
(Note 2)

Output Disable to
Output Float

tOH
(Note 2)

Output Hold from Addresses, CE or DE,
Whichever Occurred First

1-110

Capacitance TA = + 25°C, f =
Symbol

1 MHz (Note 2)

Parameter

Conditions

Typ

Max

UnIts

= OV

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

= OV

AC Test Conditions
Output Load

Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2V
Outputs
0.8V and 2V

1 TIL Gate and
CL = 100 pF (Note 8)

:::::5 ns

Input Rise and Fall Times
Input Pulse Levels

0.45V to 2.4V

AC Waveforms (Notes 6, 7, and 9)
2V

ADDRESSES

ADDRESSES VALID

O.sv

O.BV

2.0V

OUTPUT
O.BV

--~-----+H+~~I

VALID OUTPUT

t ACC
(NOTE 3)

TLlD/11367-3

DE may be delayed up to tACC

- toE after the falling edge of

CE without impacting tAce.

Note 4: The tDF and teF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI·STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

DE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee

1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: 10L = 1.6 mA, IOH = - 400 /LA.
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.

•

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS input: VIL

= GND ±0.3V, VIH = Vee ±0.3V.

1-111

o
~
o

a.
......

Programming Waveform

(Note 3)

PROGRAM
....- - - PROGRAM ----J~--- VERIFY --~

::!i!E

ADDRESSES

Hi-Z

DATA

toH

toES

2V
O.SV
TL/D/11367-4

1·112

Programming Characteristics (Notes 1,2,3 & 4)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

tAS

Address Setup Time

tOES

OE Setup Time

,..,S

tos

Data Setup Time

,..,s

tvps

Vpp Setup Time

,..,s

tves

Vee Setup Time

,..,s

tAH

Address Hold Time

,..,s

tOH

Data Hold Time

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

tOE

Data Valid from OE

Ipp

Vpp Supply Current during
Programming Pulse

CE/PGM = X

,..,s

,..,S

105

,..,s

CE/PGM = X

100

CE/PGM = VIL

100

lee

Vee Supply Current

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

V
ns

-0.1

0.0
4.0

0.45

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

National's standard product warranty applies only to devices programmed to specifications described herein.
Nole 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Nole 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. eare must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 /.IF capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Nole 4: Programming and program verify are tested with the fast Progam Algorithm, at typical power supply voltages and timings.
Nole 5: During power up the PGM pin must be brought high (;:>: VIH) either coincident with or before power is applied to Vpp.
Nole 1:

III

1-113

r-..
N
:!:

Fast Programming Algorithm Flow Chart

INCREMENT ADDR

TL/D/11367-5

FIGURE 1

1-114

Functional Description
sented in the data word. The only way to change a "a .. to a
"1" is by ultraviolet light erasure.

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The Vce power supply must be at 6.25V during the three programming modes, and at 5V in the other
three modes.

The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 p.F capacitor be placed across Vpp, VCC
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 P.s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 P.s pulse.
The EPROM must not be programmed with a DC signal applied to the CE/PGM input.

Read Mode

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.

Standby Mode

Note: Some programmer manufacturers, due to equipment limitation,
may offer interactive program Algorithm (shown in Figure 2).

Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OE) of the parallel EPROMs may be
common. A TTL low level program pulse applied to an
EPROM's CE/PGM input with Vpp at 12.75V will program
that EPROM. A TTL high level CE/PGM input inhibits the
other EPROMs from being programmed.

b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary
device selecting function, while OE be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

AFTER PROGRAMMING

Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P040 is "8F08", where "SF" designates that

1-115

N
........

"tJ

o
0l:Io.
o

Functional Description

(Continued)
tain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.

it is made by National Semiconductor, and "OS" designates
a 4 Megabit (512K x S) part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C ± 5°C.

SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ,.,.F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,.,.F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (Le., UV intensity X
exposure time) for erasure should be minimum of
15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time
increases by factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make cer-

Mode Selection
The modes of operation of the NM27P040 are listed in Table I. A single 5V power supply is required in the read mode.
All inputs are TTL levels except for Vpp and A9 for device
signature.

TABLE I. Modes Selection
Pins

CE/PGM

Vpp

Vee

Outputs

VIL

X
(Note 1)

5.0V

DOUT

VIH

5.0V

HighZ
HighZ

Mode
Read
Output Disable
Standby

VIH

5.0V

Programming

VIL

VIH

12.75V

6.25V

DIN

Program Verify

VIL

12.75V

6.25V

DOUT

Program Inhibit

VIH

12.75V

6.25V

HighZ

Note 1: X can be VIL or VH

TABLE II. Manufacturer's Identification Code
Pins

AO
(12)

A9
(26)

07
(21)

06
(20)

05
(19)

04
(18)

03
(17)

02
(15)

01
(14)

00
(13)

Hex
Data

Manufacturer Code

VIL

12V

Device Code

VIH

12V

1-116

~National
Q Semiconductor
NMC87C257
262, 144-Bit (32K x 8) CMOS EPROM
with On-Chip Address Latches
General Description

Features

The NMC87C257 is a CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.

• Address latches for direct interfacing with address/data
multiplexed microprocessors
• Low CMOS power consumption:
- Active power: 110 mW max
- Standby power: 0.55 mW max
• Pin compatible with standard 256K EPROM
• Fast and reliable programming
• TTL, CMOS compatible inputs/outputs
• TRI-STATE® output
• Manufacturer's identification code for automatic programming control use NMC27C2568 PGM Algorithm
• High current CMOS level output drivers

The NMC87C257 has latched addresses for direct interfacing with address/data multiplexed microprocessors and microcontrollers. The AO-A7 pins can be tied to the respective 00-07 pins and then bused to the microprocessor or
microcontroller directly. No latch device is needed for interfacing.
The part is designed to operate with a single
supply with ± 10% tolerance.

+ 5V

power

The part is packaged in a 28-pin dual-in-line package with a
quartz window or PLCC. The quartz window allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure. The PLCC is not
erasable.
This EPROM is fabricated with National's proprietary CMOS
double-poly silicon gate technology.

Block Diagram
DATA OUTPUTS OO-Cl7

Vee 0----+GND 0----+

OUTPUT ENABLE
AND CHIP ENABLE LOGIC

y
DECODER

AO-A14
ADDRESS
INPUTS

X
DECODER

262,144-BIT
CELL t.lATRIX

TLID/11012-1

1-117

.....
Ln

.....

Connection Diagram

NMC87C257Q

27C256

Vpp/ALE- 1
A12- 2

Vpp
A12
A7
A6
A5

'-'

A7- 3

27C256

28 -Vee
27 ~A14

Vee
A14
A13
A8
A9
A11
OE
A10
CE/PGM
07
06
05
04
03

26 -A13

A6- 4

A5- 5

24 I-A9

A4- 6

23 -All

A3
A2
A1
AO
00
01
02
GND

A3- 7

22 ~OE

~A8

A2- 8

Al- 9

20 ~CE7PGM

~Al0

AO- 10

00- 11

18 1-06

~07

01- 12

171-05

02- 13

~04

GND- 14

~03

TLlD/ll012-2
Note: Socket compatible 27C256 EPROM pin configuration is shown in the block adjacent to the NMC87C257 pins.

Pin Names
Symbol

PLCC Pin Configuration

Description

AO-A14

Addresses

Chip Enable

Output Enable

A6- 5

29 -A8

00-07

Outputs

A5- 6

28 -A9

PGM

Program

A4- 7

27 -All

A3- 8

26 -NC

~ 4

ALE

Address Latch Enable

Vpp

Programming Supply

Vee

1 32 31 30

A2- 9

-0£

Al- 10

~Al0

Power Supply

AO- 11

23 ~CE/PGM

GND

Ground

NC- 12

No Connection

~07

211- 06

Commercial Temperature Range WC to
Vee = 5V ± 10%

Note: Leadless or
Leaded, Plastic or
Ceramic Package

+ 70·C)

TL/D/ll012-8

ParameterIOrder
Number

Access
Time (ns)

NMC87C2570150, V150
NMC87C2570200, V200

150
200

Extended Temperature Range (- 40·C to
Vee = 5V ± 10%

Top

+ 85·C)

ParameterIOrder
Number

Access
Time (ns)

NMC87C2570E150
NMC87C2570E200

150
200

1-118

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Vpp Supply Voltage and A9
with Respect to Ground

Temperature under Bias

- 65°C to + 150°C

Storage Temperature

- 65°C to + 150°C

Lead Temperature
(Soldering, 10 Seconds)

300°C

ESD Rating
(Mil Spec 883C, Method 3015.2)

1700V

Vee Supply Voltages
with Respect to Ground

+ 7.0V to -0.6V

All Input Voltages except A9
with Respect to Ground (Note 2)

+6.5Vto -0.6V

+ 14.0V to - 0.6V
1.0W

Power Dissipation

Operating Conditions (Note 3)
5V ±10%

Vee Power Supply

All Output Voltages with Respect
to Ground (Note 2)
Vee + 1.0V to GND -0.6V

Temperature Range
Commercial
Extended

O°Cto +70°C
-40°C to +85°C

READ OPERATION
DC Electrical Characteristics
Symbol

Typ

Max

Units

Input Load Current

VIN = Vee or GND

0.Q1

1.0

,..,A

Parameter

III

Conditions

Min

ILO

Output Leakage Current

VOUT = Vee or GND, CE = VIH

0.01

1.0

,..,A

lee1
(Note 4)

Vee Current (Active)
TTL Inputs

ALE = VIH, f = 5 MHz
All Inputs = VIH or VIL, I/O = 0 mA

lee2
(Note 4)

Vee Current (Active)
CMOS Inputs

ALE = Vee, f = 5 MHz
All Inputs = Vee or GND, I/O = 0 mA

leeSB1

Vee Current (Standby)
TTL Inputs

CE = VIH, ALE = VIH

Stable

CE = VIH. ALE = VIL

0.3

leeSB2

Vee Current (Standby)
CMOS Inputs

Switching

CE = Vee, ALE = Vee

0.5

100

,..,A

-0.2

0.8

2.0

Vee + 1

0.40

Ipp

Vpp Load Current

VIL

Input Low Voltage

Switching

Stable

CE = Vee, ALE = GND
Vpp = Vee

VIH

Input High Voltage

VOL1

Output Low Voltage

IOL = 2.1 mA

VOH1

Output High Voltage

IOH = -2.5 mA

VOL2

Output Low Voltage

IOL = 10,..,A

VOH2

Output High Voltage

IOH = -10,..,A

3.5
0.1
Vee - 0.1

V
V

-2.0V for 20 ns Max.

Note 3: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 fLF ceramic capacitor be used on
every device between Vec and GND.
Note 4:

Vpp

may be connected to

Vee except during programming.

1-119

AC Electrical Characteristics
NMC87C257
Symbol

Parameter

Conditions

150
Min

200
Max

Min

Units
Max

tACC

Address Access Time

CE = OE = VIL

150

200

tCE

Chip Enable Access Time

OE = VIL

150

200

tLL

Chip Deselect Width

tAL

Address to ALE Latch Set-Up

tLA

Address Hold from ALE Latch

tOE

Output Enable to Output Valid

tLOE

ALE to Output Enable

tCF
(Note 1)

Chip Disable to Output
in High Z

OE = VIL

tOF
(Note 1)

Output Disable to
Output in High Z

CE = VIL

tOH

Output Hold from Addresses,
CE or OE, whichever
occurred first

CE = VIL
20

1-120

ns
ns

Note 1: This parameter is only sampled and is not 100% tested.

75
30

Capacitance
Symbol

TA =

+ 25°C, f

z
o
(X)

= 1 MHz (Note 1)

Parameter

Conditions

Typ

Max

......

Units

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

U1
......

AC Test Conditions
Output Load

Timing Measurement Reference Level
Inputs
Outputs

1 TTL Gate and
CL = 100 pF (Note 7)
~5

Input Rise and Fall Times

AC Waveforms

(Notes 5, 6 and 8)

V ----_
IH

0.8V and 2V
0.8Vand 2V

0,45V to 2,4V

Input Pulse Levels

ADDRESSES

VIH

_ _ _ _"'"

1,---------~""'IIl"""'IIl"

_________"'"

"'_t-!'II-'JIr_1 _ - - -

ADDRESS IN STABLE

-r~

________

~"'-Jj~~....K...K...K....K.o¥...K..~ Y."'-Jj~o.../II_I

----

---t---t LA

-----ft---.........,.

~---------tCE--------~

VIL

t - - - - t LoE ---~>---

VIH
VIL
VIH

OUTPUT

VIL

------+------------f 4 - - - - - - - - - tAcc

--------------~

HIGH Z

-----------------------<1
TL/D/11012-3

Note 1: This parameter is only sampled and is not 100% tested.
Note 2:

OE may be

delayed up to tACC - teE after the falling edge of

CE without impacting tACC.

Note 3: The tDF and tCF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOLl (DC) + 0.10V.
Note 4: TRI-STATE may be attained using OE or CE.
Note 5: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 /LF ceramic capacitor be used on
every device between Vcc and GND.
Note 6: The outputs must be restricted to Vcc

1.0V to avoid latch-up and device damage.

Note 7: 1 TTL Gate: IOL = 1.6 mA, IOH = -400/LA.
CL: 100 pF includes fixture capacitance.
Note 8: Vpp may be connected to VCC except during programming.

1-121

......
LI)
N

o......
CD
o
:::E
z

Programming Characteristics (Notes 1, 2, 3 and 4)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

tAS

Address Setup Time

,...s

tOES

DE Setup Time

,...s

tos

Data Setup Time

,...s

tvps

Vpp Setup Time

,...s

tves

Vee Setup Time

,...s

tAH

Address Hold Time

,...s

tOH

Data Hold Time

,...s

tOF

Output Enable to Output Float Delay

tpw

Program Pulse Width

100

105

,...s

tOE

Data Valid from DE

DE = VIL

100

Ipp

Vpp Supply Current
during Programming Pulse

= VIL
DE = VIH

lee

Vee Supply Current

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

V
ns

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

4.0

tiN

Input Timing Reference Voltage

0.8

1.5

2.0

tOUT

Output Timing Reference Voltage

0.8

1.5

2.0

0.0

0.45

V
V

Programming Waveforms
P~~~I~~M_

PROGRAM
ADDRESSES

DATA~

.0'

ADDRESS N

HI-Z

DATA IN STABLE

DATA OUT VALID

ADD N

Vpp

Ives
.-

=:.J ~

2V
O.BV
Ipw

I-

ADD N

..-.IOF

6.0V
Vee

11AH

I OES

2V
O.BV

I--IOE -

J
TL/D/11012-4

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute ailowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 Jl.F capacitor is required across Vpp, Vee to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.

1-122

s::

Fast Programming Algorithm Flow Chart (Note 1) (Same as NMC27C256B)

oCD
.......

N
U1

.......

INCREIotENT ADDR

TLlD/11012-5

FIGURE 1
Note 1: Programming and program verify are tested with the fast Program Algorithm. at typical power supply voltages and timings.

1-123

LI)

o
'"
~
co

o
:e
z

r---------------------------------------------------------------------------------------Functional Description
DEVICE OPERATION

Standby Mode

The seven modes of operation of the NMC87C257 are listed in Table I. It should be noted that all inputs for the seven
modes are at TIL levels. The power supplies required are
Vee and Vpp. The Vpp power supply must be at 12.75V
during the three programming modes, and must be at 5V in
the other modes. The Vee power supply must be at 6.25V
during the three programming modes, and at 5V in the other
modes.

The NMC87C257 has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC87C257 is placed in the standby mode
by applying a CMOS high signal to the CE input and a
CMOS low signal to the ALE input. When in standby mode,
the outputs are in a high impedance state, independent of
the DE input.

Read Mode

Because NMC87C257s are usually used in larger memory
arrays, National has provided a 3-line control function that
accommodates this use of multiple memory connections.
The 3-line control function allows for:

Output OR·Tying

The NMC87C257 has a chip enable (CE) and an output
enable (DE), both of which must be logically active in order
to obtain data at the outputs. Chip Enable (CE) is the power
control and should be used for device selection. Output Enable (DE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access time
(tAee) , is equal to the delay from CE to output (teE)' Data is
available at the outputs tOE after the falling edge of DE,
assuming that CE has been low and addresses have been
stable for at least tAee - tOE,

a. the lowest possible memory power dissipation, and
b. complete assurance that output bus contention will not
occur.
To most efficiently use these control lines, it is recommended that CE and ALE be decoded and used as the primary
device selecting functions while DE be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.

Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC87C257.

Address Latch Operation
The NMC87C257 has an Address Latch Enable (ALE) pin
which latches the address inputs on a negative transition.
Addresses must be stable for the address setup time (tAL>
before the ALE transition, and they must hold for the address hold time (tLA) after the transition. After the hold time
has transpired the address drive can be removed from the
address input pins and the bus can be used for other signals. The ALE pin is a feed-through latch and the part will
operate as a normal unlatched device when the ALE pin is
held high.

Initially, and after each erasure, all bits of the NMC87C257
are in the "1" state. Data is introduced by selectively programmings "as" into the desired bit locations. Although only
"as" will be programmed, both "1s" and "as" can be present in the data word. The only way to change a "a" to a "1"
is by untraviolet light erasure.
The NMC87C257 is in the programming mode when the Vpp
power supply is at 12.75V and DE is at V,H. It is required
that at least a 0.1 I-'-F capacitor be placed across Vpp, Vee
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

An important application for the NMC87C257 is memory in
an address/data multiplexed microprocessor system. In an
8 bit system the low order memory address pins, AO-A7,
can be tied to the respective memory output pins, 00-07
and run on an 8-bit bus to the ADO-AD7 pins of the microprocessor. This reduces the bus width and it can be done
without adding an address latch interface device. In this application the Output Enable (DE) pin should be held high
until after the address hold time (tLA) has transpired, to
avoid bus contention.

When the address and data are stable, an active low, TIL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed. The NMC87C257 is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 I-'-s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 I-'-s pulse. The NMC87C257 must
not be programmed with a DC signal applied to the CE input.

1-124

Functional Description

0==

(Continued)

......

TABLE I. Mode Selection
Mode

CE
(20)

OE
(22)

Vpp/ALE
(1)

Vee
(28)

Outputs
(11-13,15-19)

Read

VIL

VIH

DOUT

Pins

Latched

VIL

DOUT

Standby

VIH

Don't Care

VIL

Hi-Z

Don't Care

VIH

Hi-Z

Program

VIL

VIH

12.75V

6.25V

DIN

Program Verify

VIH

VIL

12.75V

6.25V

Program Inhibit

VIH

12.75V

6.25V

DOUT
Hi-Z

Output Disable

0
N
c.n

......

(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range. After programming, opaque labels should be placed
over the NMC87C257 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

Programming multiple NMC87C257s in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paralleled NMC87C257 may be connected together when they
are programmed with the same data. A low level TTL
pulse applied to the CE input programs the paralleled
NMC87C257.

The recommended erasure procedure for the NMC87C257
is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a minimum
of 15 W-sec/cm 2 .

Program Inhibit
Programming multiple NMC87C257s in parallel with different data is also easily accomplished. Except CE, all like
inputs (including OE) of the parallel NMC87C257s may be
common. A TTL low level program pulse applied to an
NMC87C257 CE input with Vpp at 12.75V will program that
NMC87C257. A TTL high level CE input inhibits the other
NMC87C257 from being programmed.

The NMC87C257 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC87C257 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when incomplete erasure was the problem.

Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 12.75V. Vpp must be at
Vee except during programming and program verify.
Manufacturer's Identification Code
The NMC87C257 has a manufacturer's identification code
to aid in programming. When the device is inserted in an
EPROM programmer socket, the programmer reads the
code and then automatically calls up the specific programming algorithm for the part. This automatic programming
control is only possible with programmers which have the
capability of reading the code.
The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and the device type.
The code for NMC87C257 is "8F04", where "8F" designates that it is made by National Semiconductor, and "04"
designates a 256K part.
The code is accessed by applying 12.0V ± 0.5V to address
pin A9. Addresses A 1-A8, A 1O-A 14, and all control pins
are held at VIL and Vpp/ ALE is held at VIH. Address pin AO
is held at VIL for the manufacturer's code, and held at VIH
for the device code. The code is read on the eight data pins,
00-07. Proper code access is only guaranteed at 25°C ±
5°C.

SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 jJ.F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 jJ.F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

ERASURE CHARACTERISTICS
The erasure characteristics of the NMC87C257 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms

1-125

......
it)
('II

o
......

Functional Description

(Continued)

TABLE II. Manufacturer's Identification Code

:e
z

Pins

AO
(10)

07
(19)

OS
(18)

05
(17)

04
(1S)

03
(15)

02
(13)

01
(12)

00
(11)

Hex
Data

Manufacturer Code

VIL

Device Code

VIH

TABLE III. Minimum NMC87C257 Erasure Time
Light Intensity
(Micro-Watts/cm 2)

Erasure Time
(Minutes)

15,000

10,000

5,000

1-126

~National

~ Semiconductor

NM27LC256
262, 144-Bit (32k X 8) Low Current CMOS EPROM
General Description

Features

The NM27LC256 is a 32k x 8 EPROM manufactured on a
proven, manufacturable CMOS process, consuming extremely low current in both the active and standby modes.
The NM27LC256 consumes a mere 17.5 mW, (typical) making it ideal for battery powered portable and hand held systems, and for systems using "in-line" power.

• Low power consumption
- 5V operation
- 4.5 mA (max) active
- 100 fJ-A (max) standby

The NM27LC256 is one among a family of Power Miser
products from National Semiconductor catering to the increasing low current demands of the market.

•
•
•
•
•

170 ns access time
Latch-up immunity to 200 mA
ESD protection exceeds 2000V
JEDEC standard pinout
Manufacturer's identification code

Offered in the JEDEC Pinout, the NM27LC256 offers a viable alternative to the user as a replacement for existing high
power devices, while also providing an upgrade path to
higher densities.

Block Diagram

Vee 0--+
GND 0--+
Vpp

OAT A OUTPUTS 00 -

0.,

0--+

OUTPUT ENABLE
AND CHIP
ENABLE LOGIC

Pin Names

OUTPUT
BUFFERS

AO-A14

y
Y GATING

DECODER

AO-A 14
ADDRESS
INPUTS

X
DECODER

•
•
•
•
•

Chip Enable

Output Enable

00- 0 7

Outputs

PGM

Program

XX
262,144 - BIT
CELL MATRIX

TLlD/11405-1

1-127

Addresses

Don't Care
(During Read)

II)

Connection Diagrams

..J

.....
N

:E
Z

27LC010

27LC512

XX/Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

27LC64

Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

27LC64

DIP
NM27LC256
- Vpp -

\....../

28I-V ee - -

A12- 2

27 r-AIo4-

-A7- 3

26 r - A I 3 -

-A6- 4

-A5- 5

24 r - A 9 - -

Vee
PGM
NC
A8
A9
A11
OE
A10
CE
07
06
05
04
03

~A8--

-Ao4- 6

23 r-A11-

-A3- 7

22 I-OE--

-A2- 8

21 I - A l 0 -

-Al- 9

20 r-CE--

-AO- 10

19 r - 0 7 - -

-00-11

18 r - 0 6 - -

- 0 1 - 12

17 r - 0 5 - -

- 0 2 - 13

16 r-004--

-GND- 14

15 r - 0 3 - -

27LC512

27LC010
Vee
XX/PGM
XX
A14
A13
A8
A9
A11
OE
A10
CE
07
06
05
04
03

Vee
A14
A13
A8
A9
A11
~/Vpp

A10
CE
07
06
05
04
03

TL/D/11405-2

Note: Compatible EPROM plan configurations are shown in the blocks adjacent to the NM27LC256 plan

Commercial Temperature Range
(O°C to + 70°C)
Vee = 5V ± 10%
Parameter/Order Number

Extended Temperature Range
( - 40°C to + 85°C)
Vee = 5V ±100/0

Access Time (ns)

Parameter/Order Number

Access Time (ns)

NM27LC256 Q, N, 170

170

NM27LC256 QE, NE, 170

170

NM27LC256 Q, N, 200

200

NM27LC256 QE, NE, 200

200

NM27LC256 Q, N, 250

250

NM27LC256 QE, NE, 250

250

Ordering Information
LC

National_M_e_m_O_ry_ _ _ _ _ _ _ _ _T_M_-.lJ
EPROM

g5,§

1L
E

170

Low Current - - - - - - - - - - - - - - - - '

Access TIme

170 = 170 ns
200 = 200 ns
250 = 250 ns

Operating Temperature Range
E = Extended Temperature
L -_ _ _ _

L -_ _ _ _ _ _

Blank-Commercial Temperature
Q = Ceramic DIP
N = Plastic DIP, OTP
Package Size
64 = 64k
256 = 256k
512 = 512k

1-128

Absolute Maximum Ratings
Storage Temperature

(Note 1)

ESD Protection

- 65°C to + 150°C

All Input Voltages Except A9 with
Respect to Ground
Vpp and A9 with
Respect to Ground

All Output Voltages with
Respect to Ground

-0.6Vto +7V

Vee + 1.0V to GND - 0.6V

.......

o
N

U1
0)

Operating Range

-0.6V to + 14V

Vee Supply Voltage with
Respect to Ground

>2000V

Range

Temperature

Vee

Commercial

O°Cto +70°C

5V ±10%

-40°C to +85°C

5V ±10%

-0.6Vto +7V

Industrial

Read Operation
DC Electrical Characteristics Over Operating Range with Vpp =
Symbol

Parameter

Vee

Conditions

Min

Typ

Max

Units
V

VIL

Input Low Level

-0.1

0.8

VIH

Input High Level

2.0

Vee + 1

VOL

Output Low Voltage

IOL = 2.1 rnA

0.4

VOH

Output High Voltage

IOH = -400/-LA

2.4

1581

Vee Standby Current (CMOS)

CE = Vee ±0.3V

0.5

100

/-LA

1582

Vee Standby Current

CE = VIH

0.1

1.0

rnA

lee1

Vee Active Current
TTL Inputs

CE = OE VIL, F = 3 MHz
Inputs VIH or VIL

Com'l

7.0

9.0

Ind'i

7.0

10.0

Vee Active Current
CMOS Inputs

CE = GND, F = 3 MHz
Inputs = Vee or GND,
I/O = OmA
(See Figures 1, 2)

Com'l

3.5

4.5

3.5

5.0

lee2

Ipp

Vpp Supply Current

Vpp

Vpp Read Voltage

rnA
Ind'i

Vpp = Vee
Vee- 0.7

Vee + 0.7

III

Input Load Current

VIN = 5.5V or GND

-1

ILO

Output Leakage Current

VOUT = 5.5V or GND

-10

AC Electrical Characteristics Over Operating Range with Vpp =
Symbol

170

Parameter
Min

rnA

Vee

200
Max

Min

250
Max

Min

Units
Max

tAee

Address to Output Delay

170

200

250

teE

CE to Output Delay

170

200

250

tOE

OE to Output Delay

100

tDF
(Note 2)

Output Disable to
Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, whichever
Occurred First

1-129

III ___

....

:::E«(

~ ~

4+---~---1----~--~---+--~~--~

«(

o
.9

O~TT.rrn~"TT~rn""O+rrMrl~,,+TT

-50

-30

-10

TEMPERATURE (C)

FIGURE 1. lec-ACTIVLCMOS vs Temperature Vee

TL/D/11405-3

= Vp = 5.0V, Frequency 1 MHz

o
o

FREQUENCY (MHz)

FIGURE 2. lec-ACTIVLCMOS vs Temperature vs Frequency Vee

1-130

5
TLlD/11405-4

= Vpp = 5.0V, Temperature = 25°C

Capacitance TA = + 25°C, 1 =

1 MHz (Note 2)

Parameter

Symbol

3:
N

Conditions

Typ

Max

Units

Input Capacitance
Output Capacitance

COUT

VOUT = OV

AC Test Conditions
Output Load

1 TIL Gate and
CL = 100 pF (Note 8)
::;: 5 ns

Input Pulse Levels

AC Waveforms

0.45V to 2.4V

Input Pulse Level
Timing Measurement Level (Note 10)

(Note 10)

Inputs

0.8Vto 2V

Outputs

0.8Vto 2V

(Notes 6,7, and 9)

ADDRESSES

2.0V~

ADDRESS VALID

~:g~

\..,...-----------oI;~p-.---'I-teFI- teE -

(NOTES 4,5)

~.......j--",

2.0V
O.8V

-"""",.

toE

(NOTE 3)

2.0V
OUTPUT

Hi-Z

0.8V

..
r

VALID OUTPUT

t AcC

~(NOTE3)-

)
-

(NOT~:4' 5) I"''''i\'\.' Hi-Z

#0"",

TL/D/11405-5

rn:: may be delayed up to tACC -

teE after the falling edge of ~ without Impacting tACC.

Note 4: The T DF and T CF compare level is determined as follows:
High to TRI·STATE!!), the measure VCHl (DC) - 0.10V;
Low to TRI·STATE, the measure VOL1 (DC) + 0.10V.
Note 5: TRI·STATE may be attained using

OE or~.

Note 6: The power switching characteristics of EPROMs require careful device decoupiing. It is recommended that at last a 0.2 /LF ceramic capacitor be used on
every device between VCC and GND.
Note 7: The outputs must be restricted to Vcc

1.0V to avoid latch·up and device damage.

Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = - 400 /LA, CL: 100 pF inCludes fixture capacitance.
Note 9: Vpp may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS inputs VIL

GND ±0.3V, VIH

= VCC

± 0.3V.

1-131

Programming Characteristics
Symbol

1,2,3,4 and 5)

(Notes

Parameter

Typ

Min

Conditions

Max

Units

tAS

Address Setup Time

fLs

tOES

OE Setup Time

tos

Data Setup Time

2
2

fLs
fLs
fLs
fLs
fLs
fLs

tvps

Vpp Setup Time

tves

Vee Setup Time

tAH

Address Hold Time

a
2

tOH

Data Hold Time

tOF

Output Enable to Output
Float Delay

CE/PGM = VIL

0
0.45

tpw

Program Pulse Width

toE

Data Valid from OE

CE/PGM = VIL

Ipp

Vpp Supply Current
during Programming Pulse

CE/PGM = VIL

0.5

130

0.55

150

Ice

Vee Supply Current

Temperature Ambient

Vee

Power Supply Voltage

5.75

6.0

6.25

Vpp

Programming Supply Voltage

12.2

13.0

13.3

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

(Note

D
2Y

DATA~

4.0

V
V

3)
PROGRAM
VERIFY

PROGRAM
ADDRESSES O.SY

0.45

0.0

Programming Waveforms

V
ns

ADDRESS N

llAH
Hi-Z

DATA IN STABLE
ADD N

DATA OUT VALID
ADD N

I-tor

S.7SY
Vee

Vpp

Iyes

:::::.....J ~

CE O.SY

tpw

I-

toEs

2Y
O.BY

~toE-

j
JJ

TL/D/1140S-6

Note 4: Programming and program verify are tested with the Interactive Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the PGJJ pin must be brought high (;;' VIH) either coincident with or before power is applied to Vpp.

1·132

Interactive Programming Algorithm Flow Chart

.......

o
N

INCREMENT ADDR

TLlD/11405-7

FIGURE 3

1-133

~
II)

,...,
N
:s
....I

r-------------------------------------------------------------------------------~

Functional Description
To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The Vee power supply must be at 6.0V during
the three programming modes, and at 5V in the other three
modes.

Programming; Interactive Algorithm
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1's" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.
The EPROM is in the programming mode when the Vpp
power supply is at 13.0V and OE is at VIH. It is required that
at least a 0.1 p,F capacitor be placed across Vpp, Vee to
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied
8 bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Interactive
Programming Algorithm shown in Figure 3. Each Address is
programmed with a series of 500 p,s pulses until it verifies
good, up to a maximum of 20 pulses. Most memory cells will
program with a single 500 p,s pulse.

Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAee) is equal to the delay
from CE to output (teE). Data is available at the outputs tOE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tAee-tOE'
The sense amps are clocked for fast access time. Vee
should therefore be maintained at operating voltage during
read and verify. If Vee temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 97%, from 24.75 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE input. When in standby mode,
the outputs are in a high impedance state, independent of
the DE input.

The EPROM must not be programmed with a DC signal applied to the CE input.

Output Disable

Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE input programs the paralleled EPROM.

The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and

Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE, all like inputs (including OE) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROMs
CE input with Vpp at 13.0V will program that EPROM. A TTL
high level CE/PGM input inhibits the other EPROM from
being programmed.

b) complete assurance that output bus contention will not
occur.

TABLE I. Modes Selection
Pins

CE/PGM

Vpp

VIL

Vee

5.0V

Dour

Vee

5.0V

HighZ
HighZ

Vee

Outputs

Mode
Read
Output Disable
Standby

X
(Note 1)

VIH

Vee

5.0V

12.75V

6.25V

DIN

VIL

Program Verify

VIL

12.75V

Dour

Program Inhibit

VIH

12.75V

6.25V

HighZ

Programming

Note 1: X can be VIL or VIH.

1-134

Functional Description

(Continued)
The recommended erasure procedure for the EPROM is ex·
posure to short wave ultraviolet light which has a wave·
length of 2537 A. The integrated dose (Le., UV intensity x
exposure time) for erasure should be a minimum of
15W·sec/ cm 2 .
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.

Program Verify

A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vee, except during programming and program verify.
AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the genera·
tion of photo currents.

An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the dis·
tance from the lamp. (If distance is doubled the erasure time
increases by factor of 4.) Lamps lose intensity as they age.
When a lamp has aged, the system should be checked to
make certain full erasure is occurring. Incomplete erasure
will cause symptoms that can be misleading. Programmers,
components, and even system designs have been errone·
ously suspected when incomplete erasure was the problem.

MANUFACTURER'S IDENTIFICATION CODE

SYSTEM CONSIDERATION
The power switching characteristic of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system de·
signer: the standby current level, the active current level,
and the transient current peaks that are produced by volt·
age transitions on input pins. The magnitude of these tran·
sient current peaks is dependent of the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 JLF ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 fLF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The pur·
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27LC256 is "BFC4", where "BF" designates
that it is made by National Semiconductor, and "C4" desig·
nates a 256k (32kB) part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AB, A 1O-A 16, and all control pins
are held at VIH. Address pin AO is held at VIL for the manu·
facturer's code, and held at VIH for the device code. The
code is read on the eight data pins, 00-07. Proper code
access is only guaranteed at 25°C to ± 5°C.
ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era·
sure begins to occur when exposed to light with wave·
lengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluores·
cent lamps have wavelengths in the 3000A-4000A range.

TABLE II. Manufacturer's Identification Code
Pins

AO
(10)

A9
(24)

Manufacturer Code

VIL

12V

VIH

12V

Device Code

07
(19)

06
(18)

(17)

03
(15)

02
(13)

04
(16)

01
(12)

00
(11)

Hex
Data

1-135

,...

~ ~National

PRELIMINARY

~ ~ Semiconductor
z

NM27LC512
524,288-Bit (64k X 8) Low Current CMOS EPROM
General Description

Features

The NM27LC512 is a 64k x 8 EPROM manufactured on a
proven, manufacturable CMOS process, consuming extremely low current in both the active and standby modes.
The NM27LC512 consumes a mere 30 mW, making it ideal
for portable and hand held computers, data acquisition and
medical equipment, and for systems using in-line power.

• Low CMOS power consumption
- 5V operation
- 8.0 mA (Max) active
- 100 J.tA (Max) standby
• 150 ns access time
• Latch-up immunity to 200 mA
• ESD protection exceeds 2000V
• JEDEC standard pinout
• Manufacturer's identification code

The NM27LC512 is one among a family of Power Miser
products from National Semiconductor catering to the increasing low current demands of the market.
Offered in a JEDEC Standard Pinout, the NM27LC512 offers a viable alternative to the user as a replacement for
existing high power devices, while also providing an upgrade path from lower densities.

Block Diagram

Vee 0--+
GND 0--+
vpp

DATA OUTPUTS 00 -

0--+

OUTPUT ENABLE
AND CHIP
ENABLE LOGIC

y
DECODER

AO-AI5
ADDRESS
INPUTS

X
DECODER

Pin Names

OUTPUT
BUffERS

Y GATING

•
•
•
•
•

524,288 - BIT
CELL MATRIX

TLlD/11406-1

1-136

AO-A15

Addresses

Chip Enable

OElVpp

Output Enable

00-0 7

Outputs

PGM

Program

Don't Care
(During Read)

Connection Diagram

27LC010

27LC256

DIP

Vpp
A12
A7
A6
A5

A3
A2
A1

A3
A2
A1
AO
00
01
02
GND

-A3- 7

22 r- DE/Vpp -

-A2- 8

21 r-Al0--

-Al- 9

20 r - C E - -

AO
00
01
02
GND

27LC256

27LC010

Vee
A14
A13
AS
A9
A11
OE
A10
CE
07
06
05
04
03

Vee
XX/PGM
XX
A14
A13
AS
A9
A11
OE
A10
CE
07
06
05
04
03

NM27LC512

XXlVpp
A16
A15
A12
A7
A6
A5

\...J

-AI5-1
-

A12 -

28 r- Vee-27r-AI4-

-A7- 3

26r-A13-

-A6- 4

25 r- A 8 - -

-A5- 5

24 r - A 9 - -

-A4- 6

23r-All--

- A O - 10

19 r - 0 7 - -

-00-11

18 r - 0 6 - -

- 0 1 - 12

17 r - 0 5 - -

- 0 2 - 13

16 r - 0 4 - -

-GND- 14

15 r - 0 3 - -

U'I
.....

TLlD/11406-2
Note: Compatible EPROM plan configurations are shown in the blocks adjacent to the NM27LC256 plan.

Commercial Temperature Range
(O'C to + 70'C)
Vee = 5V ±10%
Parameter/Order Number

Extended Temperature Range
(- 40'C to + 85'C)
Vee = 5V ± 10%

Access Time (ns)

Parameter/Order Number

Access Time (ns)

NM27LC256 Q, N 150

150

NM27LC256 QE, NE 150

150

NM27LC256 Q, N 200

200

NM27LC256 QE, NE 200

200

NM27LC256 Q, N 250

250

NM27LC256 QE, NE 250

250

Ordering Information
LC

National_M_e_m_O_ry_ _ _ _ _ _ _ _ _T_M_---'T
EPROM

9..11

1L
E

200

Access Time
200 = 200 ns
Operating Temperature Range
No Entry = O'C to + 70'C
E = -40'C to +S5'C

Low C u r r e n t - - - - - - - - - - - - - - - - '

L-.._ _ _ _

Package
Q = Ceramic DIP

L-.._ _ _ _ _ _

Density in kbits
512 = 512 kbits

1-137

N
.....
Lt)

....o.....
N

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,

ESD Protection

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

All Output Voltages with
Respect to Ground

Storage Temperature

>2000V
Vee + 1.0V to GND - 0.6V

- 65'C to + 150'C

All Input Voltages Except A9 with
Respect to Ground
Vpp and A9 with
Respect to Ground

Operating Range
-0.6Vto +7V
-0.7Vto +14V

Vee Supply Voltage with
Respect to Ground

Range

Temperature

Vee

Commercial

O'Cto +70'C

5V ± 10%

- 40'C to + 85'C

5V ± 10%

Industrial

-0.6Vto +7V

Read Operation
DC Electrical Characteristics Over Operating Range ~ith Vpp = Vee
Symbol
VIL

Parameter

Conditions

Min

Input Low Level

VIH

Input High Level

VOL

Output Low Voltage

VOH

Output High Voltage

1581

Vee Standby Current
CMOS Inputs

1582

Vee Standby Current
TIL Inputs

leC1

Vee Active Current
TIL Inputs

CE = OE = VIL, f = 3 MHz
Inputs = VIH or VIL

leC2

Vee Active Current
CMOS Inputs

CE = GND, f = 3 MHz
Inputs = Vee or GND, I/O
(Refer to Figures 1, 2)

= 2.1 mA
IOH = -2.5mA
CE = Vee ± 0.3V

Max

Units

-0.2

Typ

0.8

2.0

Vee + 1

0.4

IOL

3.5

= VIH

= 0 mA

Vpp Supply Current

Vpp

Input Load Current

VIN

ILO

Output Leakage Current

0.5

100

IJ-A

0.1

1.0

16.0

12.5

6.0

8.0

5.0

= Vee
= 5.5V or GND
VOUT = 5.5V or GND

Ipp
III

V
V

IJ-A

-1

ILA

-10

ILA

AC Electrical Characteristics Over Operating Range with Vpp = Vee
Symbol

200

150

Parameter
Min

Max

Min

250
Max

Min

Units
Max

tAce

Address to Output Delay

150

200

250

teE

CE to Output Delay

150

200

250

tOE

OE to Output Delay

100

tDF
(Note 2)

Output Disable to
Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, whichever
Occurred First

1-138

N
......
ro

14
12

'<
.5

U1
.....

(I)

0-,

:::E<
(.)(.)
.... ii:

(.)

<
u
_u

w'"

FREQUENCY (MHz)
TLlD/11406-3

FIGURE 1. lee-ACTIVE_CMOS vs Frequency
Vee = Vp = 5.0V, Temperature = 25°C

14,----.----r---,----.----.---,----.-,
12;----+----r---~---+----r---~---+~
10;----+----~--~---+----~--;----+~

-50

-30

-10

TEMPERATURE (C)
TL/D/11406-4

FIGURE 2. lee-ACTIVE_CMOS vs Temperature
Vee = Vpp = 5.0V, Frequency = 1 MHz

1-139

N
'I"'"

Capacitance T A = + 25°C, 1 =

1 MHz (Note 2)

..J

Symbol

Parameter

Conditions

Typ

Max

Units

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note 8)
::;: 5 ns

Input Rise and Fall Times

AC Waveforms

Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs

0.45V to 2.4V
(Note 9)
0.8Vto2V
0.8Vto2V

(Notes 6, 7, and 9)
2.0V
O.BV

ADDRESSES

2.0V
O.BV

OE/Vpp

2.0V
O.BV

ADDRESSES VALID

2.0V

OUTPUT

VALID OUTPUT

O.BV

TL/0/11406-5

DE may be delayed up to tACC

- teE after the falling edge of CE without impacting tACC'

Note 4: The T OF and TCF compare level is determined as follows:
High to TRI-STATE®, the measure VCHl (DC) - 0.10V;
Low to TRI-STATE, the measure Vou (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

DE or GE.

Nole 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 poF ceramic capacitor be used on
every device between Vcc and GND.
Note 7: The outputs must be restricted to Vcc
Nole 8: 1 TTL Gate: IOL

1.6 mA, IOH

1.0V to avoid latch-up and device damage.

400 poA.

CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 10: CMOS inputs VIL

= GND ±0.3V, VIH = VCC ± 0.3V.

1-140

Programming Characteristics
Symbol

(Notes 1, 2, 3 and 4)

Parameter

Conditions

Typ

Min

Max

Units

tAs

Address Setup Time

p.s

tOES

OE Setup Time

p.s

tos

Data Setup Time

p's

tves

Vee Setup Time

p's

tAH

Address Hold Time

p.s

p's

tOH

Data Hold Time

tel

Chip Enable to Output
Float Delay

tpw

Program Pulse Width

tOEH

OE Hold Time

tov

Data Valid from CE

tpAT

OE Pulse Rise Time
During Programming

tVA
Ipp

Vpp Recovery Time

OE = VIL

60
100

OE = VIL

Vpp Supply Current
During Programming Pulse

P.s

250

P.s
ns

p.s

lee

Vee Supply Current

Temperature Ambient

°C

Vee
Vpp

Power Supply Voltage

6.25

6.5

12.5

12.75

0.45

Programming Supply Voltage

...a.
N

105

CE = VIL
OE = Vpp

N
.....
roU1

tFA

Input Rise, Fall Time

VIL

Input Low Voltage

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

1.5

tOUT

Output Timing Reference Voltage

0.8

1.5

1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee,
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V, Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification, At least 0,1 fLF capacitor is required across Vee to GND to suppress spurious
Note

voltage transients which may damage the device,
Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings,

Programming Waveforms
PROGRAM_
VERlfY:~

PROGRAM
ADDRESSES

lh:)

ADDRESS N

O.SV

'r
JJ

~
DATA

O.SV

"'-

DATA IN STABLE
ADD N

DE/Vpp

1~'
tpRT

Hi-Z

2V
O.SV

toEH

;~
~

C~R1
'\

III

DATA OUT VALID ADO N

tAH

'r\

'r
JJ

r
J

F~CSVee

O.SV

toES

~
~

6.2SV
TLlD/11406-6

1-141

C\I
.....

C3
..J
,....

Interactive Programming Algorithm Flow Chart

C\I

:::E

INCREt.4ENT ADDR

TUD/11406-8

FIGURE 3

1-142

Fast Programming Algorithm Flow Chart

INCREMENT ADDR

•
TL/D/11406-7

FIGURE 4

1-143

N
.....
Lt)
o
.....

.....
N

DEVICE OPERATION
The six modes of operation of the NM27LC512 are listed in
Table I. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp during
programming. In the program mode the OElVpp input is
pulsed from a TTL low level to 12.75V.

Programming
CAUTION: Exceeding 14V on pin 22 (OElVpp) will damage
the NM27LC512.

Read Mode

Initially, and after each erasure, all bits of the NM27LC512
are in the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be presented in the data word. The only way to change a "0" to a
"1" is by ultraviolet light erasure.

The NM27LC512 has two control functions, both of which
must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs after
the falling edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC-tOE.
The sense amps are clocked for fast access time. Vce
should therefore be maintained at operating voltage during
read and verify. If Vec temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.

The NM27LC512 is in the programming mode when the
OElVpp is at 12.75V. It is required that at least a 0.1 J-LF
capacitor be placed across Vcc and ground to suppress
spurious voltage transients which may damage the device.
The data to be programmed is applied 8 bits in parallel to
the data output pins. The levels required for the address
and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE input. A program pulse
must be applied at each address location to be programmed.

Standby Mode
The NM27LC512 has a standby mode which reduces the
active power dissipation by over 99%, from 44 mW to
0.55 mW. The NM27LC512 is placed in the standby mode
by applying a CMOS high signal to the CE input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.

The NM27LC512 is programmed with the Fast Programming Algorithm shown in Figure 4. Each Address is programmed with a series of 100 J-Ls pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 J-Ls pulse.
The NM27LC512 must not be programmed with a DC signal
applied to the CE input.

Output OR·Typing
Because the NM27LC512 is usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:

Programming multiple NM27LC512 in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the paralleled
NM27LC512 may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE input programs the paralleled NM27LC512.

a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.

Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (Shown in Figure 3).

To most efficiently use these two control lines, it is recommended that CE (pin 20) be decoded and used as the primary device selecting function, while OElVpp (pin 22) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.

Mode Selection
The modes of operation of the NM27LC512 are listed in
Table I. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and A9 for
device signature.

TABLE I. Modes Selection
Pins

CE/PGM

Vpp

Vee

VIL

Vcc

5.0V

DOUT

Vcc

5.0V

HighZ
HighZ

Mode
Read

Outputs

X
(Note 1)

VIH

Standby

VIH

Vcc

5.0V

Programming

VIL

12.75V

6.25V

DIN

Program Verify

VIL

12.75V

DOUT

Program Inhibit

VIH

12.75V

6.25V

HighZ

Output Disable

Note 1: X can be VIL or VIH.

1-144

Functional Description

s:
N

(Continued)
After programming opaque labels should be placed over the
NM27LC512 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

Program Inhibit
Programming multiple NM27LC512 in parallel with different
data is also easily accomplished. Except for CE, all like inputs (including OE) of the parallel NM27LC512 may be common. A TTL low level program pulse applied to an
NM27LC512's CE input with OElVpp at 12.75V will program
that NM27LC512. A TTL high level CE input inhibits the other NM27LC512 from being programmed.

-...J

r-.

(')
U1

The recommended erasure procedure for the NM27LC512
is exposure to short wave ultraviolet light which has a wavelength of 2537 A. The integrated dose (i.e., UV intensity x
exposure time) for erasure should be a minimum of
15W-sec/cm2 .

Program Verify

The NM27LC512 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NM27LC512 erasure time for various
light intensities.

An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the system should be checked to make certain full
erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components,
and even system designs have been erroneously suspected
when incomplete erasure was the problem.

Manufacturer's Identification Code
The NM27LC512 has a manufacturer's identification code
to aid in programming. The code, shown in Table ii, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NM27LC512 is , "SF S5", where "SF" designates
that it is made by National Semiconductor, and "S5" designates a 512k part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-AS, A 1O-A 15, CE, and OE are held
at VIL. Address AO is held at VIL for the manufacturer's
code, and at VIH for the device code. The code is read on
the S data pins. Proper code access is only guaranteed at
25°C ±5°C.

SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer-the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 JJ-F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 JlF bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capaCitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic programming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NM27LC512 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.

TABLE II. Manufacturer's Identification Code

Pins

AO
(10)

A9
(24)

Manufacturer Code

VIL

12V

VIH

12V

Device Code

(19)

06
(18)

OS
(17)

03
(1S)

02
(13)

04
(16)

TABLE III. Minimum NM27LCS12 Erasure Time
Light Intensity
(Micro-Watts/cm 2)

Erasure Time
(Minutes)

15,000

10,000

5,000

1-145

01
(12)

00
(11)

Hex
Data

III

N
..-

~ ~National
~

ADVANCE INFORMATION

Semiconductor

NM27LV512
524,288-Bit (64k X 8) Low Voltage EPROM
General Description
The NM27LV512 is a high performance Low Voltage
Electrical Programmable Read Only Memory. It is manufactured using National's latest 1.2p, CMOS split gate SVG EPROM technology. This technology allows the part to operate
at speeds as fast as 200 ns over commercial temperature
(O°C to 70°C), and 250 ns over industrial temperatures
(-40°C to + 85°C).

dowed LCC for prototyping and software development,
PLCC for production runs, and TSOP for PC board sensitive
users.
The NM27LV512 is one member of National's growing Low
Voltage product family.

This Low Voltage and Low Power EPROM is designed with
power sensitive handheld and portable battery products in
mind. This allows for code storage of firmware for
applications like notebook computers, palm top computers,
cellular phones, and HOD.

• 3.0V to 5.5V operation
• 200 ns access time
• Low current operation
- 12 rnA Icc Active Current @ 5 MHz
- 20 p,A Icc Standby Current @ 5 MHz
• Ultra Low Power operation
- 50 p,W Standby Power @ 3.3V
- 50 mW Active Power @ 3.3V
• High reliability EPI processing
- Latch up immunity up to 200 rnA
- 2000V ESD protection
• Surface mount package options
- 28-pin CERPACK
- 28-pin PLCC
- 28-pin TSOP

National still maintains its' commitment to high quality and
reliability with EPI processing on the NM27LV512. Latch-up
immunity is guaranteed for stresses up to 200 rnA on address and data pins from -1V to Vee + 0.3V. ESD
protection is guaranteed 2000V.
Small outline packages are just as critical to portable applications as Low Voltage and Low Power. National
Semiconductor has forseen this need and provides win-

Features

Block Diagram
DATA OUTPUTS

Ot-D7

OUTPUT
BUFFERS

Y GATING

AO-A15
ADDRESS

INPUTS

524.288-81T
CELL MATRIX

TLlD111375-1

1-146

~National

PRELIMINARY

~
N

.......

r<
o
-I.
o

~ semiconductor

NM27LV010
1,048,576-Bit (128k x 8) Low Voltage EPROM
General Description
The NM27LV01 0 is a high performance Low Voltage Electrically Programmable Read Only Memory. It is manufactured
using National's latest 1.2,.,. CMOS split gate SVG EPROM
technology. This technology allows the part to operate at
speeds as fast as 200 ns over Industrial temperatures
( - 40·C to + 85·C).
This Low Voltage and Low Power EPROM is designed with
power sensitive hand held and portable battery products in
mind. This allows for code storage of firmware for applications like notebook computers, palm top computers, cellular
phones, and HOD.
National still maintains its commitment to high quality and
reliability with EPI processing on the NM27LV010. Latch-up
immunity is guaranteed for stresses up to 200 mA on address and data pins from -1V to Vee + O.3V. ESD protection is guaranteed for 2000V.
Small outline packages are just as critical to portable applications as Low Voltage and Low Power. National Semiconductor has foreseen this need and provides windowed LCC
for prototyping and software development, PLCC for production runs, and TSOP for PC board sensitive applications.

The NM27C010 is one member of National's growing Low
Voltage product Family.

Features
• 3.0V to 5.5V operation
• 200 ns access time
• Low current operation
- 15 mA Icc active current @ 5 MHz
- 20 ,.,.A Icc standby current @ 5 MHz
• Ultra low power operation
- 33 ,.,.W standby power @ 3.3V
- 50 mW active power @ 3.3V
• High reliability EPI processing
- Latch-up immunity up to 200 mA
- 2000V ESD protection
• Surface mount package options
- TSOP package
- 32-pin PLCC

Block Diagram
DATA OUTPUTS 00-01

<>--+
GND <>--+
Vce

OUTPUT
BUFFERS

Y GATING

AD-A1B
ADDRESS
INPUTS

1.048.57&-8IT
CfiLMATRIX

TL/D/11377-1

1-147

Connection Diagram
PLCC and CLCC Pin Configuration

Pin Names
AO-A16

Addresses

Chip Enable

Output Enable

00-07

Outputs

PGM

Program

A,4
A13

Don't Care (During Read)

Vpp

Programming Voltage

All

DE
Extended Temperature Range ( - 40°C to
Vee = 3.3 ± 0.3

Al0

Parameter/Order Number

200
250

NM27LV010 L, V, T 300

300

• All packages conform to the JEDEC standard.

Access Time (ns)

NM27LV010 L, V, T 200

250

NM27LV010 LE, VE, TE

Package Types: NM27LV010 L, V, T
L = Quartz-Windowed LCC Package
T = TSOP
V = PLCC

+ 70°C)

NM27LV010 L, V, T 250

Access Time (ns)

NM27LV010 LE, VE, TE

Note: Surface mount PLCC available for commercial and extended temperature ranges only.

TLlD/11377-6

Top View

Commercial Temperature Range (O°C to
Vee = 3.3 ± 0.3

+ 85°C)

• All versions are guaranteed to function for slower speeds.

TSOP Pin Configuration

All

Al0

A13

A14

PGM

8x20MM
TSOP

Vee

Vss

A15

A12

Vpp

A16

TL/D/11377-2

Top View

1-148

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

- 65°C to + 150°C

All Input Voltages except A9 with
Respect to Ground (Note 10)
Vpp and A9 with Respect to Ground

Operating Range

(Note 1)

II.)

Range

Temperature

Vee

Tolerance

Commercial
Industrial

O°Cto + 70°C
- 40°C to + 85°C

3.3V
3.3V

±0.3
±0.3

......
r-

<
Q
.....
Q

-0.6Vto +7V
-0.6Vto +14V

Vee Supply Voltage with
Respect to Ground

-0.6Vto +7V

ESD Protection

>2000V

All Output Voltages with
Respect to Ground (Note 10)

Vee + 1.0V
to GND - 0.6V

DC Electrical Characteristics Over Operating Range with Vpp =
Symbol

Parameter

Vee

Test Conditions

Min

Max

Units

VIL

Input Low Level

-0.3

0.8

VIH

Input High Level

2.0

Vee + 0.3

VOL1

Output Low Voltage (TTL)

IOL = 2.0 mA

0.4

VOH1

Output High Voltage (TTL)

IOH = -2.0 mA

VOL2

Output Low Voltage

IOL = 100,...,A

0.2

,...,A

2.4

VOH2

Output High Voltage (CMOS)

IOH = -100,...,A

1581

Vee Standby Current
(CMOS)

CE = Vee ±0.3V

1582

Vee Standby Current(TTL)

CE = VIH

lee

Vee Active Current

CE + OE = VIL

Ipp

Vpp Supply Current

Vpp = Vee

Vpp

Vpp Read Voltage

III

Input Load Current

ILO

. Output Leakage Current

Vee - 0.3

f = 5 MHz

Vee - 0.7
VIN = 3.OV or GND
-1

VOUT = 3.0V or GND

AC Electrical Characteristics Over Operating Range with Vpp =
Symbol

Min

Max

Min

,...,A

Vee

,...,A

300
Max

Min

Units
Max
150

tAee

Address to Output Delay

200

120

teE

CE to Output Delay

200

120

tOE

OE to Output Delay

tOF
(Note 2)

Output Disable to Output Float

tOH
(Note 2)

Output Hold from Addresses,
CE or OE, Whichever
Occurred First

1-149

,...,A

Vee

250

200

Parameter

100

150

Capacitance TA = + 25°C, 1 =
Symbol

Parameter

1 MHz (Note 2)

Conditions

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

Typ

Max

Units

AC Test Conditions
Output Load

1 TTL Gate and
CL = 100 pF (Note 8)
~5

Input Rise and Fall Times
Input Pulse Levels

Timing Measurement Reference Level
Inputs
Outputs

O.BV and 2V
O.BV and 2V

0.45V to 2.4 V

AC Waveforms

(Notes 6, 7, and 9)

ADDRESS

ADDRESS VALID

2.0V

O.BV

2.0V

O.BV

2.0V

OUTPUT

-..:..:;:.:..+---~~~~(

VALID OUTPUT

HI-Z

O.BV

1----tACC---~

(NOTE 3)
TLlD/11377-3

CE without impacting tAee.

Note 4: The tOF and teF compare level is determined as follows:
High to TRI-STATEIB>, the measured VOHl (DC) - 0.10V;
Low to TRI-STATE, the measured VOll (DC) + 0.10V.
Note 5: TRI-STATE may be attained using

rno or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2 JJ.F ceramic capacitor be used on
every device between Vee and GND.
Note 7: The outputs must be restricted to Vee

1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOl = 1.6 mA, IOH = -400 ",A.
Cl: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vee except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

1·150

Programming Characteristics
Symbol

:5:

(Notes 1, 2, 3, 4 and 5)

Parameter

Conditions

Min

Typ

Max

Units

N
......
r-

o
......

tAS

Address Setup Time

}J-s

tOES

OE Setup Time

}J-s

tos

Data Setup Time

}J-s

tvps

Vpp Setup Time

}J-s

tves

Vee Setup Time

}J-s

tAH

Address Hold Time

}J-s

tOH

Data Hold Time

}J-s

tOF

Output Enable to Output
Float Delay

CE/PGM = VIL

tpw

Program Pulse Width

tOE

Data Valid from OE

CE/PGM = VIL

Ipp

Vpp Supply Current
during Programming Pulse

CE/PGM = VIL

0
95

100

105

}J-s

100

Icc

Vee Supply Current

Temperature Ambient

°C

Vee

Power Supply Voltage

6.0

6.25

6.5

Vpp

Programming Supply Voltage

12.5

12.75

13.0

tFR

Input Rise, Fall Time

VIL

Input Low Voltage

0.0

0.45

VIH

Input High Voltage

2.4

tiN

Input Timing Reference Voltage

0.8

2.0

tOUT

Output Timing Reference Voltage

0.8

2.0

Programming Waveform

V
V

P~~~f/Yt.4_
.~

Hi-Z

DATA IN STABLE
ADD N

vPP

4.0

ADDRESS N

DATA~

vee

o.sv

(Note 3)
PROGRAt.4

ADDRESSES

tAH I-

DATA OUT VALID
ADD N

I--

-lor

S.7SV

tyes

:::...J~

CE O.sv
Ipw

I-

IoEs

2Y
OE o.sv

1
"'

~IoE-

I
TL/OI 11377-4

Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vee.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 J-LF capacitor is required across Vpp, Vee to GNO to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
Note 5: During power up the PillJ pin must be brought high (;;, VIH) either coincident with or before power is applied to Vpp.
1-151

....

C) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

Fast Programming Algorithm Flow Chart

r--

INCREMENT ADDR
~- ... ~

TLlD/11377-5

FIGURE 1

1-152

Functional Description
DEVICE OPERATION

The EPROM is in the programming mode when the Vpp
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 p,F capacitor be placed across Vpp and
Vee to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are Vee and
Vpp. The Vpp power supply must be at 12.75V during the
three programming modes, and must be at 3.3V in the other
three modes. The Vee power supply must be at 6.25V during the three programming modes, and at 3.3V in the other
three modes.

3:
N
......

o.....
o

When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 p,s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 p,s pulse.

Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (GE) is the power control and should be used
for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAee) is equal to the delay
from GE to output (teE)' Data is available at the outputs tOE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least tAee-tOE'

Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 50 mW to 33 p,W. The
EPROM is placed in the standby mode by applying a CMOS
high signal to the CE input. When in standby mode, the
outputs are in a high impedance state, independent of the
OE input.

Program Inhibit
Programming multiple EPROM's in parallel with different
data is also easily accomplished. Except for CE, all like inputs (including OE and PGM) of the parallel
EPROM may be common. A TTL low level program pulse
applied to an EPROM's PGM input with CE at VIL and Vpp
at 12.75V will program that EPROM. A TTL high level GE
input inhibits the other EPROM's from being programmed.

AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.

a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.

MANUFACTURER'S IDENTIFICATION CODE
The EPROM has a manufacturer's identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.

Programming

The Manufacturer's Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for the NM27LV01 a is "8F86", where "8F" designates
that it is made by National Semiconductor, and "86" designates a 1 Megabit (128k x 8) part.
The code is accessed by applying 12V ± 0.5V to address
pin A9. Addresses A 1-A8, A 1a-A 16, and all control pins
are held at VIL. Address pin AO is held at VIL for the manufacturer's code, and held at VIH for the device code. The
code is read on the lower eight data pins, 00-07. Proper
code access is only guaranteed at 25°C ± 5°C.

CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the "1's" state. Data is introduced by selectively programming "a's" into the desired bit locations. Although only
"a's" will be programmed, both "1's" and "a's" can be presented in the data word. The only way to change a "a" to a
"1" is by ultraviolet light erasure.

1-~53

II
I

...o
~.....
N

::e
Z

Functional Description

(Continued)
mers, components, and even system designs have been
erroneously suspected when incomplete erasure was the
problem.

SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, Icc,
has three segments that are of interest to the system designer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated Vee transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 ,...F ceramic
capacitor be used on every device between Vee and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,...F bulk electrolytic
capacitor should be used between Vee and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e., UV intensity x
exposure time) for erasure should be a minimum of 15Wsec/cm 2.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp has aged, the system should be checked to
make certain full erasure is occurring. Incomplete erasure
will cause symptoms that can be misleading. Program-

Mode Selection
The modes of operation of the NM27LV010 are listed in Table I. A single 5V power supply is required in the read mode. All inputs
are TIL levels except for Vpp and A9 for device signature.
TABLE I. Modes Selection
Pins

CE/J5mi

Vpp

Vee

VIL

Vee

3.3V

Dour

VIH

Vee

3.3V

HighZ

Standby

VIH

Vee

3.3V

HighZ

Programming

Outputs

Mode
Read
Output Disable

VIL

VIH

12.75V

6.25V

DIN

Program Verify

VIL

12.75V

Dour

Program Inhibit

VIH

12.75V

6.25V

HighZ

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer's Identification Code
Pins
Manufacturer Code
Device Code

00 Hex
AD A9 07 06 05 04 03 02 01
(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
VIL

12V

VIH

12V

1-154

~National

ADVANCE INFORMATION

~ Semiconductor

NM27LV210
1,048,576-Bit (64K

16) Low Voltage EPROM

General Description
The NM27LV210 is a high performance Low Voltage Electrical Programmable read only memory. It is manufactured using National's latest 1.2J.L CMOS split gate SVG EPROM
technology. This technology allows the part to operate at
speeds as fast as 200 ns over commercial temperature
(O°C to + 70°C) and 250 ns over industrial temperatures
(-40°C to + 85°C).
This Low Voltage and Low Power EPROM is designed with
power sensitive hand held and portable battery products in
mind. This allows for code storage of firmware for applications like notebook computers, palm top computers, cellular
phones, and HDD.
National still maintains its commitment to High Quality and
Reliability with EPI processing on the NM27LV21 O. Latch up
immunity is guaranteed for stresses up to 200 mA on address and data pins from -1V to Vee + 0.3V. ESD protection is also guaranteed up to 2000V.
Small outline packages are just as critical to portable applications as Low Voltage and Low Power. National Semiconductor has foreseen this need and provides windowed LCC

for prototyping and software development, PLCC for production runs, and TSOP for PC board sensitive users.
The NM27LV010 is one member of National's growing Low
Voltage product family.

Features
• 3.0V to 5.5V operation
• 200 ns maximum access time
• Low current operation
- 15 mA Icc active current @ 5 MHz
- 20 J.LA Icc standby current @ 5 MHz
• Ultra low power operation
- 60 J.LA standby power @ 3.3V
- 50 mW active power @ 3.3V
a High reliability EPI processing
- Latch up immunity up to 200 mA
- 2000V ESD protection
• Surface mount package options
- TSOP package
- 44-Pin PLCC

Block Diagram
DATA OUTPUTS 00 -

Vee 0----+

GND 0----+
vpp

0----+

OUTPUT
BUFFERS

•

Y GATING

Ao -

A'5

ADDRESS
INPUTS
I,048,576-BIT
CELL MATRIX

TL/D/11376-1

1-155

Section 2
CMOS EEPROMs

Section 2 Contents
12C CMOS EEPROM Selection Guide ................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MICROWIRE CMOS EEPROM Selection Guide ........................................
Specialty Products CMOS EEPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12C SYNCHRONOUS 2·WIRE BUS
NM24C02/C04/C08/C16 2K-/4K-/8K-/16K-Bit Serial EEPROM (12C Synchronous 2-Wire
Bus) .............................. .................... ............. .............
NM24C03/C05/C09/C17 2K-/ 4K-/8K-/16K-Bit Serial EEPROM with Write Protect
(12C Synchronous 2-Wire Bus) .....................................................
NM24C02L1C04L 2K-/4K-Bit Serial EEPROM with Extended Voltage (12C Synchronous
2-Wire Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM24C03L1C05L 2K-/4K-Bit Serial EEPROM with Write Protect and Extended Voltage
(12C Synchronous 2-Wire Bus) .....................................................
MICROWIRE SERIAL EEPROMS
NM59C11 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable with Programming
Status ..........................................................................
NM93C06/C46/C56/C66 256-/1024-/2048-/4096-Bit Serial EEPROM (MICROWIRE) ......
NM93CS06/CS46/CS56/CS66 256-/1024-/2048-/4096-Bit Serial EEPROM with Data
Protect and Sequential Read ......................................................
NM93C06L1C46L1C56L1C66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended
Voltage (2.0V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM93CS06L/CS46L/CS56L1CS66L 256-/1024-/2048-/4096-Bit Serial EEPROM with
Extended Voltage (2.0V to 5.5V) and Data Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NM93C46A 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable . . . . . . . . . . . . . ..
NM93C46AL 1024-Bit Serial EEPROM 64 x 16-Bit or 128 x 8-Bit Configurable ..............
APPLICATION SPECIFIC EEPROM
NM95C12 1K-Bit CMOS EEPROM with Programmable Switches. . . . . . . . . . . . . . . . . . . . . . . . . .

2-2

2-3
2-4
2-5

2-6
2-17
2-27
2-39

2-51
2-58
2-66
2-77
2-87
2-100
2-108
2-118

o
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~National

~ Semiconductor

o
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m
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12C CMOS EEPROM Selection Guide

o
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CD

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CD

General Description

Features

National Semiconductor's family of 12C CMOS EEPROMs
share the following features: A serial interface and software
protocol allowing operation on a two wire bus. Also, programming of the upper half of the memory can be disabled
by connecting the WP pin to Vee on certain members of the
family.

• Low power CMOS
- 2 mA active current typical
- 60 ,..,A standby current typical
• Hardwire write protect for upper half of memory
• 2 wire serial interface
• Bidirectional data transfer protocol
• Sixteen byte page write mode
- Minimizes total write time per byte
• Self timed write cycle
- Typical write cycle time of 5 ms
• Data retention greater than 40 years
• 8-pin mini-DIP, 8-pin SO or 14-pin SO package

National Semiconductor EEPROMs offer 100,000 write cycles guaranteed-500,000 typical with data retention greater than 40 years. The 12C CMOS EEPROMs are all available
in DIP and SO packaging.

Available Product
NM24C02
NM24C03
NM24C04
NM24C05
NM24C08
NM24C09
NM24C16
NM24C17

Packages
N,M,M8
N,M,M8
N,M,M8
N,M,M8
N,M
N,M
N,M
N,M

Temperature Ranges
C,E,M
C,E,M
C,E,M
C,E,M
C,E,M
C,E,M
C,E,M
C,E,M

---IT

12C Interface

J08

CMOS
Memory Size - - - - - - - - - - - - - - - - - - '
02 = 2Kbit
03 = 2K bitw/write protect
04 = 4K bit
05 = 4K bit w/write protect
08 = 8K bit
09 = 8K bit w/write protect
16 = 16K bit
17 = 16K bitw/write protect

2-3

2.SV-S.SV

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y

a:
CD

Security

Y
Y
Y
Y

LEN

C
National Mem_ory_ _ _ _ _
T_M

4.SV-S.SV

::::s

PaCkage
N = Plastic DIP
M = 14 lead SO
M8 = 8 lead SO
Operating Temperature Range
No Entry = O°C to + 70°C
E = -40°C to + 85°C
M = -55°C to + 125°C

' - - - - - Operating Voltage Range
No Entry = 4.5V to 5.5V
L = 2.5V to 5.5V

·s

c::

r-----------------------------------------------------------------------------------------~

a~National
Semiconductor

Co)
~

Ci)

MICROWIRETM CMOS EEPROM Selection Guide

oa:::

General Description

Features

National Semiconductor offers a family of CMOS EEPROMs
which share the following features: MICROWIRE Serial Interface, floating gate M2CMOSTM technology, 5V only operation, 100,000 cycle operation, Directwrite t , and self-timed
programming cycle with programming status on the data out
pin. All of these devices are offered in compatible packages
and pinouts.
There are also several features not shared by all family
members, which separate the family into three groups.
These features are operating voltage range, write protection, and sequential register read. Other differences
are memory size, packaging, and operating temperature
range. Although, for the purpose of this selection guide, the
family will not be separated by these differences, as each
individual device is available with all of these variants.

•
•
•
•
•
•
•
•
•
•
•

o
:E
o
w

a:::

3:
o
a:::
o
3i

40 year data retention
Extended voltage operation
Endurance: 106 data changes
Reliable CMOS floating gate technology
Single voltage operation in all modes
MICROWIRE compatible serial interface
Directwrite t , no erase cycles required
Self-timed programming cycle
Device status signal during programming mode
Sequential Register Read*
User configurable write protection*

'Features available on NM93CS only.

Available Product
NM93CS06
NM93CS46
NM93CS56
NM93CS66
NM93C06
NM93C46
NM93C56
NM93C66

Packages
N,M8
N,M8
N,M8
N,M

Temperature Ranges
C,E,M
C,E,M
C,E,M
C,E,M

4.SV-S.SV

2.0V-S.SV*

y
Y
Y
Y

N,M8
N,M8
N,M8
N,M8

C,E,M
C,E,M
C,E,M
C,E,M

Y
Y
Y
Y

'Extended Voltage (2.0-S.S) operation is not available on the M Temperature Range (-SSOC to

+ 12S0C)

NOTE: For 14·Pin SO availability, contact local sales office.

National Memory _ _ _ _ _ _ _.....J1

Microwire Interface _________________. . .J_
CMOS--------------~

Features-------------------------------~

No Entry = Standard
S = User programmable write protection and sequential
read
Memory Size _______________________________----1
06
46
56
66

=
=
=
=

L
LpaCkage
N = Plastic DIP
J = Ceramic DIP
M = 14 Lead SO
M8 = 8 Lead SO

Operating Temperature Range
No Entry = O°C to + 70°C
E = -40°C to + 85°C
M = -55°C to + 125°C

1------ Operating Voltage Range

256 bit
1024 bit
2048 bit
4096 bit

L = 2.0V to 5.5V
No Entry = 4.5V to 5.5V

tDirectwrite allows directly writing over existing data. without erasing.

2-4

"'C
(1)

~National

n
iii'

Semiconductor

...o-a

Specialty Products CMOS EEPROM Selection Guide

General Description

Features

National Semiconductor offers a full line of CMOS
EEPROMs. Some share the MICROWIRETM Serial Interface
such as the NM93C06 and the NM93CS06; others share
the 12C (2 wire) Interface such as the NM24C02 and the
NM24C08. In addition to the above EEPROMs, we also offer some specialty EEPROMs.

•
•
•
•
•
•
•

These include the NM95C12,
NM59C11 EEPROMs.

NM93C46A

and

the

oen

m
m
-a

No erase necessary
MICROWIRE compatible interface
Self-timed programming cycle
40 years data retention
Endurance: 106 data changes
Compatible with COPSTM Microcontroller
Reliable CMOS floating gate technology

::D

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(1)
CD

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(1)

The NM95C12 is a 976-bit CMOS EEPROM with 8 programmable outputs that can be used as DIP switches. The
976 bits of memory are divided into 61 registers of 16 bits
each with each register individually accessible. Registers
61-63 are dedicated for DIP switch functions. The
NM95C12 contains 8 individually programmable outputs
which can be used as switches.

The NM93C46A and the NMS9C11 are both 1024 bits of
CMOS EEPROM which can be organized as either 64 16-bit
registers or as 128 8-bit registers. The NM93C46A and the
NM59C11 share the MICROWIRE Interface and the x8 and
x16 configuration. The differentiating feature is in the pin
configuration: The NM93C46A's Program/Erase status is
output on the Data-Out (DO) pin; the NM59C11 's on a separate ROY/BUSY pin. Both devices use a low to high transition on the clock (SK) to clock all data into or out of the
device, except device programming status which is independent of the clock.

Available Product
NM95C12
NM93C46A
NM59C11

Packages

Temperature Ranges

4.SV-S.SV

2.0V-S.SV

N,M
N,M8
N,M8

C,E,M
C,E,M
C,E,M

Y
Y
Y

2-5

.....

o
......
co
o

o
......

.-------------------------------------------------------------------------------------~

~National

~ Semiconductor

o
o......
N
o

o
~
N

Z
==

NM24C02/C04/COS/C 16
2K-/4K-/SK-/16K-Bit Serial EEPROM
(12C Synchronous 2-Wire Bus)
General Description

Features

The NM24C02/C04/C08/C16 devices are 2048/40961
8192/16,384 bits, respectively, of CMOS non-volatile electrically erasable memory. These devices conform to all
specifications in the 12C 2-wire protocol and are designed to
minimize device pin count and simplify PC board layout requirements.

• Low Power CMOS
- 2 mA active current typical
- 60 p.A standby current typical

This communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the
master (for example a microprocessor) and the slave
EEPROM device(s). In addition, this bus structure allows for
a maximum of 16K of EEPROM memory. This is supported
by the NSC family in 2K, 4K, 8K and 16K devices, allowing
the user to configure the memory as the application requires
with any combination of EEPROMs (not to exceed 16K).

• 2-wire 12C serial interface
- Provides bidirectional data transfer protocol
• Sixteen byte page write mode
- Minimizes total write time per byte
• Self timed write cycle
- Typical write cycle time of 5 ms
• Endurance: 106 data changes
• Data retention greater than 40 years
• Packages available: 8 pin mini-DIP or 14 pin SO
package

National EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power
consumption.

Functional Diagram
Vcc

VSS -

H.V. GENERATION
TIt.4ING
&: CONTROL

START CYCLE
SDA--....~...

E2 PROt.l
16x16x8
32 x 16 x 8
64 x 16 x 8
128 x 16 x 8

SCL-"'-f--I
A2-f--'"
A l - f - - -....

AO-+----...

10 _ _ _ _ _ _ _ _ _ _ _

DEVICE ADDRESS BITS
CK

DATA REGISTER

TLl0/11099-1

2-6

Connection Diagrams

N
0l:Io
(')
Q

Dual-In-Llne Package (N)

SO Package (M8)

AO- 1 ' - ' B -Vce

AO- 1 ' - ' 8 -Vee

Al- 2 Nt.lHe02 7 -NC
A2 -

Vss -

Nt.l24e04
3 Nt.l24e08 6 Nt.l24C16

A2 -

5 I- SDA

Vss -

N
.....
(')

'-'

0l:Io
.....
(')

INPUTS NC- 1

Al- 2

SCL

SO Package (M)

14 i-NC

7 -NC
Nt.l24C02
3 Nt.l24C04 6 - SCL

AO- 2

13 ~VCC

Al- 3

12 i-NC

5 -SDA

NC- 4

lll-NC

A2- 5

10 i-SCL

VSS - 6
NC- 7

9 i-SDA

TL/0/11099-2

TL/0/11099-21

Top View

See NS Package Number N08E (N)

See NS Package Number M08A (M8)

.....
(')
Q)

.....
en

B i-NC
TL/0/11099-3

Top View
See NS Package Number M14B (M)
Pin Names
AO, A 1, A2

Device Address Inputs

Vss

Ground

SOA

Data 1/0

SCl

Clock Input

No Connection

Vee

+5V

Ordering Information
Commercial Temperature Range (O"C to

+ 70·C)

Order Number
NM24C02NINM24C04NI NM24COSNINM24C16N
NM24C02M/NM24C04M/NM24COSM/NM24C16M
NM24C02MS/NM24C04MS
Extended Temperature Range ( - 40"C to

+ 85·C)

Order Number
NM24C02EN/NM24C04ENI NM24COSEN/NM24C16EN
NM24C02EM/NM24C04EM/NM24COSEM/NM24C16EM
NM24C02EMS/NM24C04EMS
Military Temperature Range (- 55·C to

+ 125·C)

Order Number
NM24C02MN/NM24C04MN/NM24COSMN/NM24C16MN
NM24C02MM/NM24C04MM/NM24COSMM/NM24C16MM
NM24C02MMS/NM24C04MMS

2-7

....
CD

o
.......

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Ambient Operating Temperature

co
o

.......
~

o
.......

Ambient Storage Temperature

All Input or Output Voltages
with Respect to Ground

Lead Temperature
(Soldering, 10 seconds)

o
~
:E

- 65°C to

NM24C02/C04/C08/C16

+ 70°C

+ 85°C

NM24C02M/C04M/C08M/C16M

+ 150°C

+ 6.5V to

O°C to
- 40°C to

NM24C02E/C04E/C08E/C16E
(Mil. Temperature)

- 55°C to

Positive Power Supply (Vee>

- 0.3V

+ 125°C

4.5Vto 5.5V

+ 300°C

ESDRating

2000V min

DC and AC Electrical Characteristics Vee,=

5V ± 10% unless otherwise specified
Limits

Symbol

Parameter

Test Conditions
Min

Units

Typ
(Note 1)

Max

leCA

Active Power Supply Current

fSCL = 100 kHz

2.0

3.0

IS8

Standby Current

VIN = GND or Vce

100

fLA

III

Input Leakage Current

VIN = GND to Vee

0.1

fLA

VOUT = GND to Vee

0.1

fLA

ILO

Output Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

Capacitance TA =

-0.3
Vee

x 0.7

VCC X 0.3

+ 0.5

Vee

0.4

IOL = 3 mA

25°C, f = 1.0 MHz, VCC = 5V

Symbol

Test

Conditions

Max

Units

CliO (Note 2)

Input/Output Capacitance (SDA)

VI/a = OV

CIN (Note 2)

Input Capacitance (AO, A 1, A2, SCL)

VIN = OV

AC Conditions of Test
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
Output Load
Note 1: Typical values are for TA

Vee

x 0.1

to Vce

x 0.9

10 ns
Vee

x 0.5

1 TTL Gate and
CL = 100 pF
= 25°C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

2·8

:!:

Read and Write Cycle Limits
Symbol

0l:Io

Parameter

Min

Max

Units

fSCL

SCl Clock Frequency

100

kHz

Noise Suppression Time
Constant at SCl, SDA Inputs

100

0l:Io
......

tAA

SCl low to SDA Data Out Valid

0.3

3.5

J.Ls

tsuF

Time the Bus Must Be Free
before a New Transmission
Can Start

4.7

(X)
......
o
.....

J.Ls

tHD:STA

Start Condition Hold Time

4.0

J.Ls

tLOW

Clock low Period

4.7

J.Ls

tHIGH

Clock High Period

4.0

J.Ls

tSU:STA

Start Condition Setup Time
(for a Repeated Start Condition)

4.7

tHD:DAT

Data in Hold Time

tSU:DAT

Data in Setup Time

250

SDA and SCl Rise Time

SDA and SCl Fall Time

tSU:STO

Stop Condition Setup Time

4.7

tDH

Data Out Hold Time

300

tWA (Note 3)

Write Cycle Time

N
......
o
o

J.Ls
J.Ls
ns
1

J.Ls

300

ns
J.Ls
ns

Note 3: The write cycle time (tWA) is the time from a valid stop condition of a write sequence to the end ot the internal erase/program cycle. During the write cycle,
the NM24Cxx bus interface circuits are disabled, SOA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address.

Bus Timing
tr
--+

SCL

~
tSU:STA

SDA

~.
--I-

~r-

f-_
I+- tLOW -

t-tHIGHl

tHD:STA

--+

I-- t LOW -

"t-

I /
I---jtAA

.,t

tHD:DAT f-- f-- tSU:DAT
..l

"] k-

f---jtOH

tsu~~
•

tBUf

~~~=
TL/D/11099-4

fI
I

2-9

~
o.....

«;

S
o
~

:!:
Z

r-------------------------------------------------------------------------------~

BACKGROUND INFORMATION (12C Bus)

DEFINITIONS

As mentioned, the 12C bus allows synchronous bidirectional
communication between transmitter/Receiver using the
SCL (clock) and SDA (Data I/O) lines. All communication
must be started with a valid START condition, concluded
with a STOP condition and acknowledged by the Receiver
with an ACKNOWLEDGE condition.

WORD
PAGE

In addition, since the 12C bus is designed to support other
devices such as RAM, EPROM, etc., the device type identifier string must follow the START condition. For EEPROMs,
this 4-bit string is 1010.

PAGE BLOCK

As shown below, the EEPROMS on the 12C bus may be
configured in any manner required, providing the total memory addressed does not exceed 16K (16,834 bits). EEPROM
memory addressing is controlled by two methods:

MASTER

SLAVE

• Hardware configuring the AO, A 1 and A2 pins (Device
Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (Tied to Vss).

TRANSMITIER

• Software addressing the required PAGE BLOCK within
the device memory array (as sent in the Slave Address
string).

RECEIVER

8 bits (byte) of data.
16 sequential addresses (one byte
each) that may be programmed
during a "Page Write" programming
cycle.
2,048 (2K) bits organized into 16
pages of addressable memory.
(8 bits) x (16 bytes) x (16 pages) =
2,048 bits
Any 12C device CONTROLLING the
transfer of data (such as a
microprocessor).
Device being controlled (EEPROMs
are always considered Slaves).
Device currently SENDING data on
the bus (may be either a Master OR
Slave).
Device currently receiving data on
the bus (Master or Slave).

Addressing an EEPROM memory location involves sending
a command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK
ADDRESS]-[BYTE ADDRESS]

Example of 16K (Maximum Size) of Memory on 2-Wire Bus
Vee

SDA---------------T----------------,....--------------~--------------~~~

SCL----~----~r_~------------r__r------------r_~------------~_+--~

NM24C02

NM24C04

NM24e02

TO Vee OR Vss

Vss

TO Vee OR Vss

NM24C08

TO Vee OR Vss
TLID/ll099-20

Note: The SDA pull·up resistor is required due to the open·drain/open·collector output of 12C bus devices.
Note: The SCL pull-up resistor is recommended because of the normal SCL line inactive "high" state.
Note: It is recommended that the total line capacitance be less than 400 pF.
Note: Specific timing and addreSSing considerations are described in greater detail in the following sections.

Address Pins

Device

Memory Size

Number of
Page Blocks

NM24C02

2048 Bits

NM24C04

Vss

4096 Bits

NM24C08

Vss

8192 Bits

NM24C16

Vss

16,384 Bits

DA: Device Address

2-10

~
N

Pin Descriptions

Device Operation

SERIAL CLOCK (SCl)

The NM24Cxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device that is controlled is the slave. The master will
always initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the NM24Cxx
will be considered a slave in all applications.

CLOCK AND DATA CONVENTIONS

The SCL input is used to clock all data into and out of the
device.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs.
Device address pins AO, A1 and A2 are connected to Vee
or Vss to configure the EEPROM address. The following
table (Table A) shows the active pins across the NM24Cxx
device family.
TABLE A
Device

8
4
2
1

........

ClO

........

o
......

START CONDITION
All commands are preceded by the start condition, which is
a HIGH to LOW transition of SDA when SCL is HIGH. The
NM24Cxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command
until this condition has been met.

Effects of Addresses

=
=
=
=

........

Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figures 1 and
2.

DEVICE ADDRESS INPUTS (AO, A1, A2)

NM24C02 ADR ADR ADR 23
X ADR ADR 22
NM24C04
X
X ADR 21
NM24C08
X
X 20
NM24C16
X

(8) x (2K) = 16K
(4) x (4K) = 16K
(2) x (8K) = 16K
(1) x (16K) = 16K

STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used by the NM24Cxx to
place the device in the standby power mode.

ADR: Denotes an active pin used for device addressing
X: Not used for addressing (Must be tied to GroundlVssl

Write Cycle Timing
SCL

SDA

START
CONDITION

STOP
CONDITION

Nt.l2-4C02/C0-4/COB
ADDRESS
TL/D/ll099-5

!xi
LV

SDA

SCL

---~V
DATA STABLE

I
I

~"";-----

DATA
CHANGE

TLlD/ll099-6

FIGURE 1. Data Validity

EI
I

LJJ

SDA

' ___ I\.J;

SCL

STOP BIT

START BIT

FIGURE 2. Definition of Start and Stop
2-11

TL/D/ll099-7

CD
'9"'"

o
.......
co
o

SCL FROt.4
t.4ASTER

o
.......
~

o
.......
C\I
o

DATA
OUTPUT
FROt.4
TRANSt.4ITTER

C\I

:IE

~
I

DATA
OUTPUT
FROt.4
RECEIVER

I
I

7
I
I

\
I
I
I

START

r
I
I
I

ACKNOWLEDGE

TLlO/ll099-B

FIGURE 3. Acknowledge Response from Receiver
ACKNOWLEDGE

selected, the NM24Cxx will respond with an acknowledge
after the receipt of each subsequent eight bit word.

Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA
line LOW to acknowledge that it received the eight bits of
data. Refer to Figure 3.

In the read mode the NM24Cxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and await the
stop condition to return to the standby power mode.

The NM24Cxx device will always respond with an acknowl·
edge after recognition of a start condition and its slave address. If both the device and a write operation have been

2-12

Device Addressing
Following a start condition the master must output the address of the slave it is accessing. The most significant four
bits of the slave address are those of the device type identifier (see Figure 4). This is fixed as 1010 for all four devices:
NM24C02, NM24C04, NM24C08 and NM24C16.
DEVICE TYPE
IDENTIFIER

NM24C021

R!W! (LSB)

DEVICE
ADDRESS

0l:Io

Page Blocks

TL/D/ll099-9

NM24C04

(4K)

P
NM24C16 P

P
P

(SK)

(16K)

.......

(NONE)

.......

000 001 010 011

...

111

A simple review: After the NM24C02/C04/C08/C16 recognizes the start condition, the devices interfaced to the 12C
bus wait for a slave address to be transmitted over the SDA
line. If the transmitted slave address matches an address of
one of the devices, the designated slave pulls the line LOW
with an acknowledge signal and awaits further transmissions.

DEVICE
ADDRESS

------~-----\~

: A2: Al : AO :R/W! (LSB)
~

PAGE
BLOCK ADDRESS
TL/D/ll099-16

DEVICE TYPE
IDENTIFIER

NM24C161

PAGE
BLOCK ADDRESS
TL/D/ll099-19

FIGURE 4. Slave Addresses

2-13

0l:Io

(2K)

.......
Page Block Addresses

The last bit of the slave address defines whether a write or
read condition is requested by the master. A "1" indicates
that a read operation is to be executed, and a "a" initiates
the write mode.

PAGE
BLOCK ADDRESS

Number of

All 12C EEPROMs use an internal protocol that defines a
PAGE BLOCK size of 2K bits (for Word addresses 0000
through 1111). Therefore, address bits AO, A 1 or A2 (if designated "P") are used to access a PAGE BLOCK in conjunction with the Word address used to access any individual data byte (Word).

NM24COOI

AO A1 A2

A: Refers to a hardware configured Device Address pin
P: Refers to an internal PAGE BLOCK memory segment

: A2 : A 1 : AO :R/W! (LSB)

DEVICE TYPE
IDENTIFIER

NM24C02

NM24COS

------~-----\~
NM24C041

oo
N

TL/D/ll099-17

DEVICE TYPE
IDENTIFIER

:5:

Refer to the following table for Slave Addresss string details:
Device

DEVICE
ADDRESS

: A2 : A1 : AD :

DEVICE ADDRESSING

o-"
en

~
.....
o

co
'"
o

'"
o
~

o
.......
C'I

o
~

C'I

::E

r---------------------------------------------------------------------~

After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is
accepted. If the master should transmit more than sixteen
words prior to generating the stop condition, the address
counter will "roll over" and the previously written data will
be overwritten. As with the byte write operation, all inputs
are disabled until completion of the internal write cycle. Re~
fer to Figure 6 for the address, acknowledge and data transfer sequence.

Write Operations
BYTE WRITE
For a write operation a second address field is required
which is a word address that is comprised of eight bits and
provides access to anyone of the 256 words in the selected
page of memory. Upon receipt of the word address the
NM24Cxx responds with an acknowledge and waits for the
next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24Cxx begins the
internal write cycle to the nonvolatile memory. While the
internal write cycle is in progress the NM24Cxx inputs are
disabled, and the device will not respond to any requests
from the master. Refer to Figure Sfor the address, acknowledge and data transfer sequence.

ACKNOWLEDGE POLLING
Once the stop condition is issued to indicate the end of the
host's write operation the NM24Cxx initiates the internal
write cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the NM24Cxx is still busy
with the write operation no ACK will be returned. If the
NM24Cxx has completed the write operation an ACK will be
returned and the host can then proceed with the next read
or write operation.

PAGE WRITE
The NM24Cxx is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the
first data word is tranferred, the master can transmit up to
fifteen more words. After the receipt of each word, the
NM24Cxx will respond with an acknowledge.
S

T
BUS ACTIVITY:
MASTER

A
R

ADDRESS

SDA LINE

S
T
0

W~D

SLAVE
ADDRESS

DATA

EJ1Jl D
A
C

BUS ACTIVITY:
NM24CXX

-,:-:::-::-:II::::::: IEr
•

•

A
C

KKK

TLlD/ll099-10

FIGURE 5. Byte Write

BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
NM24CXX

S
T
A
R
T.

SLAVE
ADDRESS

WORD ADDRESS (n)

DATA n + 1

DATA n

S
T
0
p

DATA n + 15

EI1Jl Cl , I : : : : : : : II : : : : : : : II : : : : : :.: I en: ::::I R
•

••

A
C

•

A
C

•

A
C

KKK

••

A
C

K
TL/D/ll099-11

FIGURE 6. Page Write

2-14

dress it is to read. After the word address acknowledge, the
master immediately reissues the start condition and the
slave address with the R/W bit set to one. This will be followed by an acknowledge from the NM24Cxx and then by
the eight bit word. The master will not acknowledge the
transfer but does generate the stop condition, and therefore
the NM24Cxx discontinues transmission. Refer to Figure 8
for the address, acknowledge and data transfer sequence.

Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations: current address read, random read and sequential
read.
CURRENT ADDRESS READ
Internally the NM24Cxx contains an address counter that
maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read
or write) was to address n, the next read operation would
access data from address n + 1. Upon receipt of the slave
address with R/W set to one, the NM24Cxx issues an acknowledge and transmits the eight bit word. The master will
not acknowledge the transfer but does generate a stop condition, and therefore the NM24Cxx discontinues tranmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.

The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for
read operations increments all word address bits, allowing
the entire memory contents to be serially read during one
operation. After the entire memory has been read, the counter "rolls over" and the NM24Cxx continues to output data
for each acknowledge received. Refer to Figure 9 for the
address, acknowledge and data transfer sequence.

s
T
A
R

BUS ACTIVITY:
MASTER

SLAVE
ADDRESS

T
0

lru1.Dl J:::::::! EJ
T • •

SDA LINE

BUS ACTIVITY:
NM24CXX

DATA

TLlD/11099-12

FIGURE 7. Current Address Read

BUS ACTIVITY:
MASTER
SDA LINE

S
T
A
R
T

SLAVE
ADDRESS
~.- - - " - - - - ,

S
T
A
R

WORD
ADDRESS n

•

S
T
0

SLAVE
ADDRESS

T..

1:::::::I0l.JLCJlI:::::::IEJ

ErLJl 0

A
C

BUS ACTIVITY:
NM24CXX

A
C

A'
C

DATA n

K K K
TLlD/11099-13

FIGURE 8. Random Read

BUS ACTIVITY:
MASTER
SDA LINE

511: ::::::II: : : : : : : II : : : : : : : I CAD: ::::::lEI
A''-_ _-".._ _--''

BUS ACTIVITY:
Nt.l24CXX

S
T
0
P

A
A
A
C
C
C
K K K

SLAVE
ADDRESS

C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x
TL/D/11099-14

FIGURE 9. Sequential Read

2-15

N
.......

.;..

.......

ClQ

Sequential reads can be initiated as either a current address
read or random access read. The first word is transmitted in
the same manner as the other read modes; however, the
master now responds with an acknowledge, indicating it requires additional data. The NM24Cxx continues to output
data for each acknowledge received. The read operation is
terminated by the master not responding with an acknowledge or by generating a stop condition.

Random read operations allow the master to access any
memory location in a random manner. Prior to issuing the
slave address with the R/W bit set to one, the master must
first perform a "dummy" write operation. The master issues
the start condition, slave address and then the word ad-

.;..

.......

SEQUENTIAL READ

RANDOM READ

s:
N

o
......

U) ,-------------------------------------------------------------------------------------------,
"P-

o
.......
co
o

Read Operations (Continued)

o
.......

Vee

"=:t

o
.......
C\I

s~------~~--------._--------~--------~~--------._~

o
"=:t

SCL-1~--~~--._----+_--~----_r--_1~--~----._----+_--~

C\I

TLID/ll099-15

Note:

FIGURE 10. Typical System Configuration
Due to open drain configuration of SOA, a bus-level pull-up resistor is called for, (typical value = 4.7 k!l)

2·16

~
N

~National

0l:Io

Semiconductor

.......
oo

NM24C03/C05/C09/C 17

.......

2K-/4K-/8K-/16K-Bit Serial EEPROM
with Write Protect (I2C Synchronous 2-Wire Bus)

CD
.......

....&.

.......

General Description

Features

The NM24C03/COS/C09/C17 devices are 2048/40961
8192/16,834 bits, respectively, of CMOS non-volatile electrically erasable memory. These devices conform to all
specifications in the 12C 2-wire protocol, and are designed
to minimize device pin count and simplify PC board layout
requirements.

• Hardwire write protect for upper block
• Low Power CMOS
- 2 mA active current typical
- 60 ,.,.A standby current typical
• 2-wire 12C serial interface
- Provides bidirectional data transfer protocol
• Sixteen byte page write mode
- Minimizes total write time per byte
• Self timed write cycle
- Typical write cycle time of S ms
• Endurance: 106 data changes
• Data retention greater than 40 years
• Packages available: 8 pin mini-DIP or 14 pin SO
package

The upper half of the memory can be disabled (Write Protected) by connecting the WP pin to Vee. This section of
memory then becomes ROM.
This communication protocol uses CLOCK (SCL) and DATA
1/0 (SDA) lines to synchronously clock data between the
master (for example a microprocessor) and the slave EEPROM device(s). In addition, this bus structure allows for a
maximum of 16K of EEPROM memory. This is supported by
the NSC family in 2K, 4K, 8K and 16K devices, allowing the
user to configure the memory as the application requires
with any combination of EEPROMs (not to exceed 16K).
National EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption.

Functional Diagram
vcc vss -

wp--------------------------~

START CYCLE

SDA - - - -..........

E2 PROt.l

SCL -

16x16x8
32 x 16 x 8
64 x 16 x 8
128 x 16 x 8

....-t---I

A2 --it--.......

Al--il---.......
AO

--1-------

TLIO/lll00-1

2-17

t-,....

.....
0)

Connection Diagrams

0
.....
Lt)

Dual-In-Llne Package (N)

.....
~

==
Z

AO- 1

\...../

SO Package (M)

Pin Names
AO, A1, A2

Device Address Inputs

Vss

Ground

SDA

8 I- Vee

Al- 2 24C03 7 ~WP
A2- 3 24C05 6 I- SCL
24C09
VSS - 4 24C17 51-SDA
TL/D/lll00-2

INPUTS NC- 1

'-"

~NC

AO- 2

13 !-VCC

Data liD

Al- 3

SCL

Clock Input

NC- 4

ll-NC

Vee

+5V

A2- 5

10 -SCL

Vss - 6
NC- 7

8 -NC

Top View

See NS Package Number N08E

Write Protect

-wp

9 -SDA

No Connection
TL/D/lll00-3

Top View
See NS Package Number M14B

Ordering Information
Commercial Temperature Range WC to + 70°C)
Order Number
NM24C03N/NM24C05NINM24C09N/NM24C17N
NM24C03M/NM24C05M/NM24C09M/NM24C17M
Extended Temperature Range (- 40°C to + 85°C)
Order Number
NM24C03EN/NM24C05EN/NM24C09EN/NM24C17EN
NM24C03EM/NM24C05EM/NM24C09EM/NM24C17EM
Military Temperature Range ( - 55°C to + 125°C)
Order Number
NM24C03MN/NM24C05MN/NM24C09MN/NM24C17MN
NM24C03MM/NM24C05MM/NM24C09MM/NM24C17MM

2-18

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Ambient Operating Temperature
NM24C03/C05/C09/C17
NM24C03E/C05E/C09E/C17E
NM24C03M/C05M/C09M/C17M
(Mil. Temp.)

Ambient Storage Temperature

- 65°C to + 150°C

Ail Input or Output Voltages
with Respect to Ground

+ 6.5V to

:!1:
N

(')

O°C to + 70°C
-40°C to +85°C
- 55°C to + 125°C
4.5Vto 5.5V

Positive Power Supply (Vce)

-0.3V

(')

o
U1
.......
(')

CD
.......

lead Temperature
(Soldering, 10 sec.)

(')

.....
......

+300°C

ESD Rating

2000V

DC and AC Electrical Characteristics Vcc =

5V ± 10% (unless otherwise specified)
Limits

Symbol

o
CN
.......

Parameter

Test Conditions
Min

Units

Typ.
(Note 1)

Max

ICCA

Active Power Supply Current

fseL = 100 kHz

2.0

3.0

IS8

Standby Current

VIN = GND or Vee

100

p.A

III

Input leakage Current

VIN = GND to Vee

0.1

p.A

VOUT = GND to Vee

p.A

ILO

Output leakage Current

VIL

Input low Voltage

-0.3

Vee x 0.3

VIH

Input High Voltage

Vee x 0.7

Vce + 0.5

VOL

Output low Voltage

0.4

Capacitance TA =

0.1

IOL = 3 mA

25°C, f = 1.0 MHz, Vee = 5V

Symbol

Test

Conditions

Max

Units

CliO (Note 2)

Input/Output Capacitance (SDA)

VI/O = OV

CIN (Note 2)

Input Capacitance (Ao, Al, A2, SCl, WP)

VIN = OV

A.C. Conditions of Test
Input Pulse levels

Vee x 0.1 to Vee x 0.9

Input Rise and
Fail Times

10 ns

Input and Output
Timing levels
Output load
Note 1: Typical values are for TA

Vee x 0.5
1 TIL Gate and
CL = 100 pF
= 25°e and

nominal supply voltage

(5V).

Note 2: This parameter is periodically sampled and not 100% tested.

2-19

I"'-

""'"
o......

Read and Write Cycle Limits

(7)

o
o
......
Lt)
o

Symbol

Min

Parameter

Max

Units

100

kHz

100

3.5

J.Ls

fSCL

SCl Clock Frequency

o
......
C"')

Noise Suppression Time
Constant at SCl, SDA Inputs

o
"'I::t'

tAA

SCl low to SDA Data Out Valid

0.3

tSUF

Time the Bus Must Be Free
before a New Transmission
Can Start

4.7

J.Ls

tHD:STA

Start Condition Hold Time

4.0

J.Ls

tLOW

Clock low Period

4.7

J.Ls

tHIGH

Clock High Period

4.0

J.Ls

tSU:STA

Start Condition Setup Time
(for a Repeated Start Condition)

4.7

tHD:OAT

Data in Hold Time

tSU:OAT

Data in Setup Time

250

SDA and SCl Rise Time

SDA and SCl Fall Time

tSU:STO

Stop Condition Setup Time

4.7

tOH

Data Out Hold Time

300

tWA (Note 3)

Write Cycle Time

COlI

:!E

J.Ls

ns
1

J.Ls

300

ns
J.Ls

ns
10

Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end ot the internal erase/program cycle. During the write cycle,
the NM24Cxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address.

Bus Timing
tr
rtHIGHl

I- tLOW -

SCL

tSU:STA

SDA

"'t

- - I - tHD:STA

~.-

-tLOW -

~.tHD:DAT

I !

I--

-- r-.

--'

, .tAA

--I tDH

~~~ XXXXXXXXXXXX):

tSU:DAT

tsu:1o•

tBur

j(
TLIO/lll00-4

2-20

z
BACKGROUND INFORMATION (12C Bus)

As mentioned, the 12C bus allows synchronous bidirectional
communication between Transmitter/Receiver using the
SCl (clock) and SDA (Data I/O) lines. All communication
must be started with a valid START condition, concluded
with a STOP condition and acknowledged by the Receiver
with an ACKNOWLEDGE condition.

WORD
PAGE

In additon, since the 12C bus is designed to support other
devices such as RAM, EPROM, etc., the device type identifier string must follow the START condition. For EEPROMs,
this 4-bit string is 1010.

PAGE BLOCK

As shown below, the EEPROMs on the 12C bus may be
configured in any manner required, providing the total memory addressed does not exceed 16K (16,834 bits). EEPROM
memory addressing is controlled by two methods:

MASTER

DEFINITIONS

• Hardware configuring the AO, A 1 and A2 pins (Device
Address pins) with pull-up or pull-down resistors. All
UNUSED PINS MUST BE GROUNDED (tied to Vss).

TRANSMITIER

• Software addressing the required PAGE BLOCK within
the device memory array (as sent in the Slave Address
string)

RECEIVER

SLAVE

Addressing an EEPROM memory location involves sending
a command string with the following information:

[DEVICE TYPEJ-[DEVICE ADDRESSJ-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]
Example of 16k (MaXimum Size) of Memory on 2·Wlre Bus
Vee

-,r-..............................
+-.........................-r.....r-..........-.-..........-.-4~..........~..........,--t.....~

SDA--..............................~...................................r-..............................

"""T~

SCL--....................~.....

NM24C03
AO

NM24C03
vss

TO Vee OR Vss

NM24C09

NM24C05
vss

TO Vee OR Vss

Vss

TO Vee OR Vss

Vss

TO Vec OR Vss
TLID/11100-20

Note:
The SDA pull-up resistor is required due to the open-drain/open-collector output of 12C bus devices.
The SCl pull·up resistor is recommended because of the normal SCl line inactive "'high" state.
It is recommended that the total line capacitance be less than 400 pF.
Specific timing and addressing considerations are described in greater detail in the following sections.

Address Pins

Device
AD
NM24C03
NM24C05

Memory Size
A2

Number of
Page Blocks

2048 Bits

4096 Bits

Vss

NM24C09

Vss

8192 Bits

NM24C17

Vss

16,384 Bits

DA: Device Address

2-21

w
......

U1
......

co
......

o.....
........

,...
o......
~

r-------------------------------------------------------------------------------------------,
Pin Descriptions

en
o

SERIAL CLOCK (SCl)

The SCl input is used to clock all data into and out of the
device.

o
......
Lt)
o
......
Cf')
o

o"'1:2'
N

::2:

If tied to Vss, normal memory operation is enabled, READI
WRITE over the entire memory is possible.
This feature allows the user to assign the upper half of the
memory as ROM which can be protected against accidental
programming. When write is disabled, slave address and
word address will be acknowledged but data will not be acknowledged.

SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs.

Device Operation

DEVICE ADDRESS INPUTS (AO, A1, A2)

The NM24C03/C05/C09/C17 supports a bidirectional bus
oriented protocol. The protocol defines any device that
sends data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the transfer is
the master and the device that is controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore,
the NM24Cxx is considered a slave in all applications.

Device address pins AO, A1 and A2 are connected to Vee
or Vss to configure the EEPROM address. The following
table (Table A) shows the active pins across the NM24Cxx
device family.
TABLE A
Device

Effects of Addresses

NM24C02 ADR ADR ADR 23
NM24C04 X ADR ADR 22
NM24C08 X
X ADR 21
NM24C16 X
X
X 20

=
=
=
=

8 (8)
4 (4)
2 (2)
1 (1)

x ( 2K)
x ( 4K)
x ( 8K)
x (16K)

=
=
=
=

CLOCK AND DATA CONVENTIONS

16K
16K
16K
16K

Data states on the SDA line can change only during SCl
lOW. SDA state changes during SCl HIGH are reserved for
indicating start and stop conditions. Refer to Figures 1 and

ADR: Denotes an active pin used for device addressing

START CONDITION

X: Not used for addressing (must be tied to GroundlVssl

All commands are preceded by the start condition, which is
a HIGH to lOW transition of SDA when SCl is HIGH. The
NM24Cxx continuously monitors the SDA and SCl lines for
the start condition and will not respond to any command
until this condition has been met.

WP WRITE PROTECTION
If tied to Vee, PROGRAM operations onto the upper half of
the memory will not be executed. READ operations are possible.

Write Cycle Timing
SCL

SDA

STOP
CONDITION

SDA

START
CONDITION

!x!

L!,

I
I
I

I
I

Nt.l24C03/C05/C09/C 17
ADDRESS

I
I

SCL

DATA STABLE

DATA
CHANGE

TL/O/lll00-6

FIGURE 1. Data Validity
SDA

SCL

START BIT

STOP BIT

FIGURE 2. Definition of Start and Stop

2-22

TL/O/lll00-7

TLlO/lll00-5

3:
SCL FROM
MASTER

~
I

I
I

,J:Io.

o
o

........

o
o

DATA
OUTPUT
FROM
TRANSMITTER

........

DATA
OUTPUT
FROM
RECEIVER

........

START

-.....

ACKNOWLEDGE

TL/0/11100-8

FIGURE 3. Acknowledge Response from Receiver
STOP CONDITION
DEVICE TYPE
IDENTIFIER

All communications are terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used by the NM24Cxx to
place the device in the standby power mode.

NM24C031

DEVICE
ADDRESS

: 0 : 1 : 0 > < A1 >

- 65°C to + 150°C

All Input or Output Voltages
with Respect to Ground

N
0l:Io

(')

o
r......
c,.)

O°C to +70°C
-40°C to + 85°C
2.5Vto 5.5V

(')

+ 6.5V to - 0.3V

Lead Temperature
(Soldering, 10 seconds)

+ 300°C

ESD Rating

2000V min

DC and AC Electrical Characteristics Vee =

4.5V to 5.5V (unless otherwise specified)
Limits

Symbol

Parameter

Test Conditions
Min

Units

Typ
(Note 1)

Max

2.0

3.0

leeA

Active Power Supply Current

fseL

Iss

Standby Current

VIN

GND orVee

100

p.A

III

Input Leakage Current

VIN

GND to Vee

0.1

p.A

ILO

Output Leakage Current

VOUT

0.1

p.A

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

100 kHz

GND to Vee
-0.3
Vee

IOL

x 0.3

Vee + 0.5

0.4

Vee

x 0.7

3 mA

Note 1: Typical values are for TA = 25'C and nominal supply voltage (5V).

Capacitance T A =

25°C, f

1.0 MHz, Vee = 5V

Symbol

Test

Conditions

Max

Units

CliO (Note 2)

Input/Output Capacitance (SDA)

Vila

CIN (Note 2)

Input Capacitance (AO, A 1, A2, SCL)

VIN

OV
OV

Note 2: This parameter is periodically sampled and not 100% tested.

AC Conditions of Test
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
Output Load

Vee

x 0.1

to vee

x 0.9

10 ns

Vee

x 0.5

1 TTL Gate and
CL = 100 pF

2-43

..J

an
o

STANDARD VOLTAGE (4.5V

(.)

Vee

5.5V) SPECIFICATIONS

.......

..J
C")

Read and Write Cycle Limits

(.)
"II:t'
N

Max

Units

fSCl

SCl Clock Frequency

100

kHz

Noise Suppression Time
Constant at SCl, SDA Inputs

100

3.5

Il s

Symbol

Min

Parameter

tAA

SCl low to SDA Data Out Valid

0.3

tSUF

Time the Bus Must Be Free
before a New Transmission
Can Start

4.7

Il s

tHD:STA

Start Condition Hold Time

4.0

Il s

tlOW

Clock low Period

4.7

Il s

tHIGH

Clock High Period

4.0

Il s

tSU:STA

Start Condition Setup Time
(for a Repeated Start Condition)

4.7

Il s

tHD:DAT

Data in Hold Time

Il s

tSU:DAT

Data in Setup Time

250

SDA and SCl Rise Time

Il s

SDA and SCl Fall Time

300

tSU:STO

Stop Condition Setup Time

4.7

Il s

tDH

Data Out Hold Time

300

tWA (Note 3)

Write Cycle Time

Note 3: The write cycle time (tWA) is the time from a valid stop condition of a write sequence to the end ot the internal erase/program cycle. During the write cycle,
the NM24Cxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address.

Bus Timing

SCL

SDA

~U'ST~~.
1t-

+*- tow -

...

r~'GHl

.,1"

~D:STA

*- tow -

~ ...
tHD:DAT

I----

-,
tAA

-....

...

r--

~~~=~

.,t

toH

tSU:DAT

~u,:~
•

t BUF

-:
TL/D/11400-4

2-44

~
N

BACKGROUND INFORMATION (12C Bus)

As mentioned, the 12C bus allows synchronous bidirectional
communication between Transmitter/Receiver using the
SCL (clock) and SDA (Data I/O) lines. All communication
must be started with a valid START condition, concluded
with a STOP condition and acknowledged by the Receiver
with an ACKNOWLEDGE condition.

WORD
PAGE

In additon, since the 12C bus is designed to support other
devices such as RAM, EPROM, etc., the device type identifier string must follow the START condition. For EEPROMs,
this 4-bit string is 1010.

PAGE BLOCK

MASTER

DEFINITIONS

• Hardware configuring the AO, A 1 and A2 pins (Device
Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to Vss).

TRANSMITTER

• Software addressing the required PAGE BLOCK within
the device memory array (as sent in the Slave Address
string)

RECEIVER

SLAVE

Addressing an EEPROM memory location involves sending
a command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]

Example of 8k (% Maximum Size) of Memory on 2·Wire Bus

SDA--------------~--------------_.----------------r_~

SCL-----------r--~----------~--+_----~----_.--t_--~

NM24C03

A1 A2

TO Vcc OR Vss

NM24C05

A2 Vss

TO Vcc OR Vss

A1 A2 Vss

TO Vee OR Vss
TL/D/11400-05

Notes:
The SDA pull-up resistor is required due to the open-drain/open-collector output of 12C bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive "high" state.
It is recommended that the total line capacitance be less than 400 pF.
Specific timing and addressing considerations are described in greater detail in the following sections.

Address Pins

Device
AD

Memory Size
A2

Number of
Page Blocks

NM24C03L

2048 Bits

NM24C05L

Vss

4096 Bits

DA: Device Address

2-45

r
.......
o
o
U1
r

...J

I.t)

Pin Descriptions

...J

SERIAL CLOCK (SCL)

The SCL input is used to clock all data into and out of the
device.

o
......
C"')

o
~
C\I

:!:

If tied to Vss, normal memory operation is enabled, READ/
WRITE over the entire memory is possible.
This feature allows the user to assign the upper half of the
memory as ROM which can be protected against accidental
programming. When write is disabled, slave address and
word address will be acknowledged but data will not be acknowledged.

SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs.

Device Operation

DEVICE ADDRESS INPUTS (AO, A 1, A2)

The NM24C03L1C05L supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master
will always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
NM24Cxx is considered a slave in all applications.

Device address pins AO, A1 and A2 are connected to Vee
or Vss to configure the EEPROM address. The following
table (Table A) shows the active pins across the NM24Cxx
device family.
TABLE A
Device

Effects of Addresses

NM24C03L ADR ADR ADR 23 = 8
NM24C05L X ADR ADR 22 = 4

(8)
(4)

x (2K)
x (4K)

= 16K

CLOCK AND DATA CONVENTIONS

= 16K

Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figures 1 and

ADR: Denotes an active pin used for device addreSSing
X: Not used for addreSSing {must be tied to GroundlVss>

WP WRITE PROTECTION

START CONDITION

If tied to Vee, PROGRAM operations onto the upper half of
the memory will not be executed. READ operations are possible.

All commands are preceded by the start condition, which is
a HIGH to LOW transition of SDA when SCL is HIGH. The
NM24Cxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command
until this condition has been met.

Write Cycle Timing
SCL

SDA

STOP
CONDITION

SDA

START
CONDITION

Nt.lHC03L/COSL
ADDRESS

1X!

I
I

:r-------~

r------~

SCL

DATA STABLE

DATA
CHANGE

TLl0/11400-7

FIGURE 1. Data Validity
SDA

SCL

STOP BIT

START BIT

FIGURE 2. Definition of Start and Stop

2-46

TL/0/11400-B

TL/0/11400-6

'
---r--LF\J

SCL FROM:
MASTER
1

1
1

DATA

OU;~~~

--X I

TRANSMITTER:

C!=J

DATA
OUTPUT
FROM
RECEIVER

:5:

1
1

.I:loo

o
o

ro
o

.......
CJ1

nl----~\

I~--"I
1

START

ACKNOWLEDGE

TlID/11400-9

FIGURE 3. Acknowledge Response from Receiver
STOP CONDITION

Device Addressing

Following a start condition the master must output the address of the slave it is accessing. The most significant four
bits of the slave address are those of the device type identifier, (see Figure 4). This is fixed as 1010 for both devices:
NM24C03L and NM24C05L.

ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA
line LOW to acknowledge that it received the eight bits of
data. Refer to Figure 3.

DEVICE TYPE
IDENTIFIER

NM24C03LI

: a :

DEVICE
ADDRESS

1 : 0 > < Al >0"'-------

TL/D/10750-S

"The NM93CS56 and NM93CS66 require a minimum of 11 clocks cycles. The NM93CS06 and NM93CS46 require a minimum of 9 clock cycles.

WDS:
PRE = 0, PE = X, DO = TRI-STATE

SK'

,:>0\------

TLlD/107S0-6

"The NM93CS56 and NM93CS66 require a minimum of 11 clocks cycles. The NM93CS06 and NM93CS46 require a minimum of 9 clock cycles.

WRITE:
PRE = 0

L
~

SK_

oo--~b~t
=!

REAOY

t wp

"Address bit A7 becomes a "don't care" for NM93CS56.
"Address bits A5 and A4 become "don't cares" for NM93CS06.

TL/D/107S0-7

2-73

CD
CD

o
......
CD
an

Timing Diagrams

(Continued)

WRALLt:
PRE = 0

o
......

"'lIt'
U)

o
......
CD
o
U)

o
M

en
:!E

..~~~------------

------------------------------------'Zll~----------~~----~----~

·Don't care

TL/D/10750-8

tProtect Register MUST be cleared.

PRE

PRREAD:
PE = X

J
J

Ol~

1~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

OO------------------------------~
• Address bits A5 and A4 become "don't cares" for NM93CS06.
·Address bit A7 becomes "don't care" for NM93CS56.

TL/D/10750-9

2-74

z
Timing Diagrams

(Continued)

en
o

PRE

PREN*:
DO = TRI-STATE

.......

o
en
U1
0)

.......

0)
0)

CSJ
SK

DI
'A WEN cycle must precede a PREN cycle.

PRE

TL/D/10750-10

PRCLEAR*:

J
2

SK~

1\____

DI~
DO

----------~21f_2-------_;_L~\ t
~
BUSY

• A PREN cycle must Immediately precede a PRCLEAR cycle.

2-75

READY

Ell
\...
TL/D/10750-11

CD
CD
(J)

o
........

Timing Diagrams

(Continued)

PRWRITEt:

Lt)

(J)

o
........
CD

-.::t

PRE

(J)

o........
CD

(J)

o
C")

:iE

\'-----

_flJlJlJ1JlJ

-+L_·_\

DO _ _ _ _ _ _ _ _ _ _ _ _

'Address bit A7 becomes a "don't care" for NM93CS56.
'Address bits AS and A4 become "don't cares" for NM93CS06.

BUSY.Jl

READY

,"--_ _ _ __

TL/D/10750-12

tProtect Register MUST be cleared before a PRWRITE cycle. A PREN cycle must Immediately precede a PRWRITE cycle.

PROS":

PRE

r;\ 0 0 0 •••
o
o
~l~--------------------------------

----' '

------------~ul"-----------+b--8 R~

'ONE TIME ONLY instruction. A PREN cycle must Immediately precede a PROS cycle.

2-76

\...
TL/D/10750-13

s::
CD

~National

Semiconductor

ro
~

........

NM93C06L/C46L/C56L/C66L
256-/1024-/2048-/4096-Bit Serial EEPROM
with Extended Voltage (2.0V to 5.5V)

The NM93CxxL Family interfaces to microprocessors and
microcontrollers via a single 4-wire MICROWIRETM bus
which possesses the following parameters: SK (Serial
Clock), CS (Chip Select), 01 (Data Input) and DO (Data-Output). 01 includes: instruction, address and data to be written.
DO offers data read and programming status information.
Serial interfacing allows 8-pin DIP or 8-pin SO packaging to
minimize board space. The following seven instructions (op
codes) control device operation: EWEN (Erase/Write Enable), EWDS (Erase/Write Disable), READ (Read), ERAL

ro
U1

........

(Erase all registers), ERASE (Erase a register/address),
WRAL (Write all registers with 16 bits of data) and WRITE
(Write a register/address).

General Description
The
NM93C06L1C46L1C56L/C66L
devices
are
256/1024/2048/4096 bits, respectively, of non-volatile
electrically erasable memory divided into 16/64/128/256 x
16-bit registers (addresses). The NM93CxxL Family functions in an extended voltage operating range, requires only
a single power supply and is fabricated using National Semiconductor's floating gate CMOS technology for high reliability, high endurance and low power consumption. These devices are available in an SO package for small space considerations.

........

Features
• 2.0V to 5.5V operation in read mode
• 2.5V to 5.5V operation in all other modes
• Typical active current of 400 /-LA; Typical standby
current of 25 /-LA
•
•
•
•
•
•
•
•

Direct write
Reliable CMOS floating gate technology
MICROWIRE compatible serial I/O
Self-timed programming cycle
Device status during programming mode
40 years data retention
Endurance: 106 data changes
Packages available: 8-pin SO, 8-pin DIP

Block Diagram
CS------------------------~

SK----;~==:;_---~
DI

INSTRUCTION
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS.

Vpp

+-Vcc

HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER

EEPROM ARRAY
2048/4096 BITS
(128/256 x 16)

DO.---------------------~

TLlD/1004S-1

2-77

oen

..J
CD
CD

o
........

..J

LI)

Connection Diagrams
Dual·ln·L1ne Package (N)
and S·Pln SO (MS)

Pin Names
CS

Chip Select

8 -Vec

Serial Data Clock

SK- 2

7 -NC

Serial Data Input

..J

01- 3

6 -NC

Serial Data Output

00- 4

5 -GNO

........
..J
CD
-.::t'

o
........
CD

CS-l

'-/

('t)
Q)

GND

Ground

Vee

Power Supply

TL/D/1004S-2

Top View
See NS Package Number NOSE or MOSA

Ordering Information
Commercial Temp. Range (O"C to

+ 70·C)

Order Number
NM93C06LN/NM93C46LN
NM93C56LN/NM93C66LN
NM93C06LM8/NM93C46LM8
NM93C56LM8/NM93C66LM8

Extended Temp. Range (- 40·C to

+ S5·C)

Order Number
NM93C06LEN/NM93C46LEN
NM93C56LEN/NM93C66LEN
NM93C06LEM8/NM93C46LEM8
NM93C56LEM8/NM93C66LEM8

Alternate (Turned) SO Pinout
Order Number
NM93C46TLM8/NM93C46TLEM8

Alternate SO Pinout (TMS)

NCDs NC

vee

GNO

01
TL/D/1004S-12

See NS Package Number MOSA

2-78

LOW VOLTAGE ( < 4.5V) SPECIFICATIONS
Absolute Maximum Ratings

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Storage Temperature
- 65·C to + 150·C
All Input or Output Voltages
+ 6.5V to - 0.3V
with Respect to Ground
Lead Temp. (Soldering, 10 sec.)
+300·C
ESD Rating
2000V

Ambient Operating Temperature
NM93C06L-NM93C66L
N M93C06LE - NM93C66LE

O·Cto +70·C
-40·C to + 85·C

Power Supply (Vcd Range
Read Mode
All Other Modes

2.0Vto 5.5V
2.5V to 5.5V

DC and AC Electrical Characteristics
Symbol

Parameter

Part Number

Max

Units

lee1

Operating Current
CMOS Input Levels

NM93C06L-NM93C66L
NM93C06LE·NM93C66LE

250 kHz

2
2

lee2

Operating Current
TTL Input Levels

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

CS = VIH. SK = 250 kHz
4.5V :5: Vee :5: 5.5V

3
3

lee3

Standby Current

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

50
50

fLA

IlL

Input Leakage

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

VIN

OV to Vee

-2.5
-10

2.5
10

fLA

IOL

Output Leakage

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

VIN

OV to Vee

-2.5
-10

2.5
10

fLA

VIL1
VIH1

Input Low Voltage
Input High Voltage

4.5V :5: Vee :5: 5.5V

VIL2
VIH2

Input Low Voltage
Input High Voltage

2V :5: Vee :5: 4.5V

VOL1
VOH1

Output Low Voltage
Output High Voltage

4.5V :5: Vee :5: 5.5V
IOL = 2.1 mA
IOH = - 400 fLA

VOL2
VOH2

Output Low Voltage
Output High Voltage

2V :5: Vee :5: 4.5V
IOL = 10 fLA
IOH = -10 fLA

fSK

SK Clock Frequency

NM93C06L·NM93C66L
NM93C06LE-NM93C66LE

tSKH

SKHighTime

NM93C06L·NM93C66L
NM93C06LE-NM93C66LE

(Note 2)

1
1

fLs

tSKL

SKLowTime

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

(Note 2)

1
1

fLs

tSKS

SK Setup Time

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

Relative to CS

50
50
100

1
1

fLs

Conditions

VIH, SK

Min

0.8
2
-0.1
0.8 Vee

0.15 Vee
Vee + 1

0.4

V
V

0.1 Vee

V
V

2.4

0.9 Vee
0
0

250
250

kHz

tes

MinimumCS
Low Time

NM93C06L·NM93C66L
NM93C06LE-NM93C66LE

(Note 3)

tess

CS Setup Time

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

Relative to SK

0.2
0.2

fLs

tOH

DO Hold Time

Relative to SK

2·79

..J
CD
CD

LOW VOLTAGE « 4.5V) SPECIFICATIONS

o......
..J
CD

Lt)

DC and AC Electrical Characteristics

o
......

Symbol

to IS

01 Setup Time

tesH

CSHoldTime

oC")

tOIH

01 Hold Time

tp01

Output Delay to "1"

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

2
2

tpoo

Output Delay to "0"

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

..J

-.:::t

o......

..J

z==

Max

Units

Part Number

Conditions

Min

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

Relative to SK

0.4
0.4

p,s

Relative to SK

p,s

Relative to SK

0.4

Parameter

p,s

tsv

CS to Status Valid

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

tOF

CSto DO in
TRI-STATE®

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest
CS = VIL

twp

Write Cycle Time

p,s
p,s

1
1

p,s

0.4
0.4

p,s

Capacitance (Note 4)
TA = 25°C f = 1 MHz
Units

Test

Max

COUT

Output Capacitance

CIN

Input Capacitance

Symbol

AC Test Conditions
Output Load: 1 TTL Gate and CL = 100 pF
Vee Range

4.5V

< Vee < 5.5V

AC Test Conditions
Input Pulse Levels
Timing Measurement Level
(VI LiVl H)
Timing Measurement Level

O.BV and 2.0V
0.9V and 1.9V

O.BV and 2.0V
(VOLiVOH)
(TTL Load Conditions:
IOL = 2.1 mA, IOH = - 0.4 mA)

2.0V

< Vee < 4.5V

Input Pulse Levels
Timing Measurement Level
(VILiVIH)
Timing Measurement Level
(VOLiVOH)
(CMOS Load Conditions:
IOL = 10 p,A, IOH = -10 p,A)

0.3V and 1.BV
O.4V and 1.6V
O.BVand 1.6V

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The above SK frequency specifies a minimum SK clock period of 4 JLs; therefore, in an SK clock cycle, tSKH + tSKL must be greater than or equal to 4 JLs.
For example, if tSKL = 1 P.s, then the minimum tSKH = 3 p.s in order to meet the SK frequency specification.
Note 3: es must be brought low for a minimum of 1 JLs (lcs) between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.

2-BO

:!i:
co

STANDARD VOLTAGE (4.5V ::;: Vee::;: 5.5V) SPECIFICATIONS

Co)

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Ambient Operating Temperature
NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

........

Ambient Storage Temperature

Power Supply (Vce)

All Input or Output Voltages
with Respect to Ground
Lead Temp. (Soldering. 10 sec.)
ESD Rating

- 65°C to + 150°C

O°Cto + 70°C
-40°C to +85°C

4.5Vto 5.5V

........

+6.5Vto -0.3V

oen

+ 300°C

........

2000V

ro
en

DC and AC Electrical Characteristics Vcc =
Symbol

5.0V ± 10% unless otherwise specified

Parameter

Part Number

Conditions

ICC1

Operating Current
CMOS Input Levels

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ICC2

Operating Current
TIL Input Levels

ICC3

Min

Max

Units

CS = VIH. SK = 1 MHz
SK = 1 MHz

2
2

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

CS = VIH. SK = 1 MHz
SK = 1 MHz

3
3

Standby Current

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

CS = OV

50
50

).LA

IlL

Input Leakage

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

VIN = OV to Vcc

-2.5
-10

2.5
10

).LA

IOL

Output Leakage

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

VIN = OV to Vcc

-2.5
-10

2.5
10

).LA

VIL
VIH

Input Low Voltage
Input High Voltage

-0.1
2

Vcc + 1

VOL1

Output Low Voltage

VOH1

Output High Voltage

VOL2

0.8

0.4
0.4

0.2

1
1

MHz

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

IOL = 2.1 mA
IOL = 2.1 mA

Output Low Voltage

NM93C06LE-NM93C66LE

IOL=10).LA

fSK

SK Clock Frequency

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

tSKH

SKHighTime

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

(Note 2)
(Note 3)

250
300

tSKL

SK Low Time

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

(Note 2)
(Note 3)

250
250

tcs

MinimumCS
Low Time

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

(Note 4)
(Note 5)

250
250

tcss

CS Setup Time

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

Relative to SK

50
50

tOH

DO Hold Time

Relative to SK

IOH = -400).LA

2-81

2.4

0
0

-oJ

(Q
(Q

STANDARD VOLTAGE (4.5V

o
........

-J

(Q
Lt)

o
........

-J
(Q

"11:2'

o........

-J
(Q

o
(f)
0)

:!!:

Vee

DC and AC Electrical Characteristics Vee
Symbol

Parameter

= 5.0V

5.5V) SPECIFICATIONS
± 10% unless otherwise specified (Continued)

Part Number

Conditions

Min

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

Relcltive to SK

100
200

ns
ns

Max

Units

tOIS

01 Setup Time

tesH

CSHoldTime

Relative to SK

tOIH

01 Hold Time

Relative to SK

tp01

Output Delay to "1"

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

500
500

tpoo

Output Delay to "0"

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

500
500

tsv

CS to Status Valid

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest

500
500

tOF

CSto OOin
TRI-STATE

NM93C06L-NM93C66L
NM93C06LE-NM93C66LE

ACTest
CS = VIL

100
100

twp

Write Cycle Time

Note: Throughout this table "M" refers to temperature range (- 55'C to

+ 125'C), not package.

Capacitance (Note 6)
TA = 25°C, f = 1 MHz
Symbol

Test

Typ

Max

Units

COUT

Output Capacitance

CIN

Input Capacitance

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial and Extended temperature range parts specifies a minimum SK clock period of 1 ,""s; therefore, in an SK
clock cycle, tSKH + tSKL must be greater than or equal to 1 ,""s. For example, if tSKL = 250 ns then the minimum tSKH = 750 ns in order to meet the SK frequency
specification.
Note 3: The SK frequency specification for Military Temperature parts specifies a minimum SK clock period of 2 ,""s; therefore, in an SK clock cycle, tSKH + tSKL
must be greater than or equal to 2 ,""s. For example, if the tSKL = 500 ns, then the minimum tSKH = 1.5 '""S in order to meet the SK frequency specification.
Note 4: For Commercial and Extended temperature range parts, CS must be brought low for a minimum of 250 ns (tes) between consecutive instruction cycles.
Note 5: For Military Temperature parts CS must be brought low for a minimum of 500 ns (lcs) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.

2-82

s::

Functional Description

The NM93CxxL Family has seven instruction sets as described below. Note that each instruction set is broken
down into the Start Bit (SB), Op code, Address (if applicable) and Data (if applicable). As shown in the timing diagrams and INSTRUCTION SET tables, address bits will
have 6 bits for the NM93C06 and NM93C46 and 8 bits for
the NM93CS6 and NM93C66 devices. All instruction bits are
entered into the device on the SK low-to-high transitions.

Read (READ):
The READ instruction outputs the specified address data on
the DO pin. After the READ instruction is received, the instruction and address are decoded and data is transferred
from the address to a 16-bit shift register output buffer. A
dummy bit (logical 0) precedes all 16-bit data out strings.
The READ instruction may be executed from either the enabled or disabled state.

Programming is enabled by bringing CS to a Logical 0 state
for the required tes period. After this tes period the selftimed operation may be monitored by bringing CS to a logical 1 and observing the DO status: Logical 1 = READY
(Ready for the next instruction) and Logical 0 = BUSY (Programming in progress).

Write All (WRAL):
This instruction, when followed by 16 bits of data, programs
all registers/addresses in the memory array with the specified data pattern, (Bulk write).

Instruction Set for the NM93C06L and NM93C46L
Instruction

OpCode

Address

READ

AS-AO

Reads data stored in memory at specified address.

EWEN

11XXXX

Write enable must precede all programming modes.

ERASE

AS-AO

WRITE

AS-AO

ERAL

10XXXX

WRAL

01XXXX

EWDS

OOXXXX

Data

Comments

Erase register ASA4A3A2A1AO.
D1S-DO

Writes register.

D1S-DO

Writes all registers.

Erases all registers.

Disables all programming instructions.

Instruction Set for the NM93C56L and NM93C66L
Instruction

Op Code

Address

Data

Comments

READ

A7-AO

Reads data stored in memory at specified address.

EWEN

11XXXXXX

Write enable must precede all programming modes.

ERASE

A7-AO

WRITE

A7-AO

ERAL

10XXXXXX

WRAL

01XXXXXX

EWDS

OOXXXXXX

Erase register A7A6ASA4A3A2A1AO.
D1S-DO

Writes register.
Erases all registers.

D1S-DO

Writes all registers.
Disables all programming instructions.

2-83

U1
(7)

Write (WRITE):

Erase/Write Disable (EWDS):

(7)

r.......

This instruction, when followed by an address location, programs all bits in the selected register/address to a 1 state
(Register erase).

This instruction, when followed by an address location and
16 bits of data, programs the selected register/address.

To protect against accidental data disturbance, the Erase/
Write Disable instruction disables all programming modes
and should follow the end of all programming cycles.

r.......

This instruction programs all registers/addresses in the
memory array to a 1 state, (Bulk erase).

When Vee is applied to the device, it powers up in the programming Erase/Write disabled state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once this instruction is executed,
programming remains enabled until the Erase/Write Disable
(EWDS) instruction is executed or until Vee is removed from
the part.

(7)

Erase (ERASE):

Erase All (ERAL):

Erase/Write Enable (EWEN):

(7)
(7)

..J

CD
CD

o
......

Timing Diagrams

..J

Synchronous Data Timing

ll)

o
......

tess

..J
CD

o
......

1+------- 1)J.s

t--~:....,f+--- tSKH

I•

----t

..J
CD

CW')

en
:E

VOH ---t----t------,,/

DO (READ) VOL
VOH

DO (PROGRAM) VOL

----0(' -______________________________________
STATUS VALID

TL/D/l004S-13

'This is the minimum SK period (Note 2).
ttSKS is not needed if DI

VIL when CS is going active (HIGH).

READ:

csJ

OO---------------~~.
TL/D/l004S-S

'Address bits As and A4 become "don't care" for NM93C06L.
'Address bit A7 becomes a "don't care" for NM93C56L.

EWEN:

csJ
01
TL/DI1 0045-6

'The NM93C56L and NM93C66L require a minimum of 11 clock cycles. The NM93C06L and NM93C46L require a minimum of 9 clock cycles.

2-84

==
co
w

Timing Diagrams (Continued)

EWDS:

csJ

en
r.......

r.......
o
(J1

en
r.......
oen
en

.:>0\-----

TL/D/l004S-7

·The NM93C56L and NM93C66L require a minimum of 11 clock cycles. The NM93C06L and NM93C46L require a minimum of 9 clock cycles.

WRITE:

csJ
JUUUUlIlJU1J
II

TL/D/l004S-8

·Address bit As and A4 become "don't care" for NM93C06L.
·Address bit A7 becomes a "don't care" for NM93C56L.

WRAL:

csJ

lJU1JlJU1J1JL

SK*

..~~--------------

OO--....................------------.....--.....--.....--~ll~2--.....--...............1~--.....~.....~

TLlD/l004S-9

·The NM93CS6L and NM93C66L require a minimum of 11 clock cycles. The NM93C06L and NM93C46L require a minimum of 9 clock cycles.

2-85

Ell

-J
CD
CD

o
.......

Timing Diagrams

-J

(Continued)

ERASE:

o
.......

-J
CD
"II:t

o.......

csJ

-J

oC")

:!:

·~~--I---(~---I--to-F--

1_--

TRI-STATE

OO--~~~~--------------------~S51~----~~----~__~~-'1

TRI-STATE

TL/D/l0045-10

ERAL:
SK

-.-f1\_O_0..JJ1\ ° 1////7llIIII\,

OO __

~T~RI~-S~T~AT~E~

________________________________

~~~

I--"'Il"'-I

TL/D/l0045-11

2·86

~National

~ Semiconductor

en
o

NM93CS06L/CS46L/CS56L/CS66L
256-/1024-/2048-/4096-Bit Serial EEPROM
with Extended Voltage (2.0V to 5.5V) and Data Protect
General Description

Features

The NM93CS06L1CS46L1CS56L1CS66L devices are
256/1024/2048/4096 bits, respectively, of non-volatile
electrically erasable memory divided into 16164/128/256 x
16-bit registers (addresses). The NM93CSxxL Family functions in an extended voltage operating range and is fabricated using National Semiconductor's floating gate CMOS
technology for high reliability, high endurance and low power consumption. N registers (N s: 16, N s: 64, N s: 128,
N s: 256) can be protected against data modification by programming the Protect Register with the address of the first
register to be protected against data modification. Additionally, this address can be "locked" into the device, making all
future attempts to change data impossible.

•
•
•
•
•
•
•
•
•
•
•
•
•

These devices are available in an SO package for small
space considerations.

en
r
......

en
~

r
......

oen
(J1

Sequential register read
Write protection in a user defined section of memory
2.0V to 5.5V operating range in read mode
2.5V to 5.5V operating range in other modes
Typical active current of 400 /LA; typical standby
current of 25 /LA
Direct Write
Reliable CMOS floating gate technology
MICROWIRE compatible serial 1/0
Self timed write cycle
Device status during programming mode
40 year data retention
Endurance: 106 data changes
Packages Available: 8~pin SO, 8-pin DIP

r
......

en
en
r

The serial interface that control these EEPROMs is
MICROWIRETM compatible, providing simple interfacing to
standard microcontrollers and microprocessors. There are a
total of 10 instructions, 5 which operate on the EEPROM
memory and 5 which operate on the Proted Register. The
memory instructions are READ, WRITE, WRITE ALL,
WRITE ENABLE, and WRITE DISABLE. The Protect register instructions are PRREAD, PRWRITE, PREN, PRCLEAR,
and PROS.

Block Diagram

CS------------------------H
SK----~=====I--------~

INSTRUCTION
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS.

'-Vcc

1+------------ PRE
1+---------4-- PE

ADDRESS COt.lPARE
AND
WRITE ENABLE
10-_ _ _ _""

HIGH VOLTAGE
GENERATOR
AND
PROGRAt.4
Tlt.4ER

•

DO.-------------------~

TL/D/l0044-1

2-87

...I
CD
CD

Connection Diagrams

...I
CD

Dual-In-Llne Package (N)
and S-Pln SO Package (MS)

0
......

Pin Names

LI)

en
0

......

~Ov~

PIN OUT:
SO Package (M)

Chip Select

Serial Data Clock

NC- 1

\....,/
14 -NC

-I
CD

PRE

Serial Data Input

CS-2

13 -Vee

Serial Data Output

SK- 3

12 -PRE

GNO

0
......

...I
CD
0

GND

TL/D/10044-2

Top View

See NS Package Number NOSE (N)
See NS Package Number MOSA (MS)

0C")

:iE

Ground

NC- 4

ll-NC

01- 5

10 -PE

Program Enable

00- 6

9 -GNO

PRE

Protect Register Enable

NC- 7

8 -NC

Vee

Power Supply

TLlD/10044-3

Top View
See NS Package Number M14A (M)

Ordering Information
Commercial Temp. Range WC to

+ 70°C)

Order Number
NM93CS06LN/NM93CS46LN/NM93CS56LN/NM93CS66LN
NM93CS06LM8/NM93CS46LM8/NM93CS56LM8/NM93CS66LM*

Extended Temp. Range ( - 40°C to

+ S5°C)

Order Number
NM93CS06LEN/NM93CS46LEN/NM93CS56LEN/NM93CS66LEN
NM93CS06LEM8/NM93CS46LEM8/NM93CS56LEM8/NM93CS66LEM*
"The NM93CS66 is available in a-pin DIP and 14-pin SO only.
Note: 14-pin SO availability on the 93CS06, CS46 and CS56, contact your local
National Semiconductor Sales Office.

2-88

LOW VOLTAGE «4.5) SPECIFICATIONS
Absolute Maximum Ratings

CD
W

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Ambient Operating Temperature
NM93CSxxL
NM93CSxxLE

Ambient Storage Temperature

Power Supply (Vce) Range
Read Mode
All Other Modes

-65°C to + 150°C

All Input or Output Voltages
with Respect to Ground

+ 6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)
ESD rating

Operating Conditions

(Note 1)

(J)

oQ)

O°Cto +70°C
- 40°C to + 85°C

+300°C

r.......

o
(J)
U1

2000V

Parameter

(J)
~

2.0Vto 5.5V
2.5V to 5.5V

.......

o(J)

DC and AC Electrical Characteristics
Symbol

r.......

Q)
Q)

Part Number

Conditions

Min

Max

Units

0.1 Vcc

VRPP

Power Supply Ripple

ICC1

Operating Current
CMOS Input Levels

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

= VIH, SK = 250 kHz

2
2

ICC2

Operating Current
TTL Input Levels

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CSS66LE

CS = VIH, SK = 250 kHz
4.5V:S;:Vcc:S;:5.5V

3
3

ICC3

Standby Current

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

= OV

50
50

p,A

IlL

Input Leakage

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

VIN

= OV to Vcc

-2.5
-10

2.5
10

p,A

IOL

Output Leakage

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CSS66LE

Your = OV to Vcc

-2.5
-10

2.5
10

p,A

VIL1
VIH1

Input Low Voltage
Input High Voltage

4.5V:S;:Vcc:S;:5.5V

VIL2
VIH2

Input Low Voltage
Input High Voltage

2V:S;:Vcc:S;:4.5V

Vou
VOH1

Output Low Voltage
Output High Voltage

4.5V:S;: Vcc:S;: 5.5V
IOL = 2.1 mA
IOH = -400 p,A

VOL2
VOH2

Output Low Voltage
Output High Voltage

2V:S;:Vcc:S;:4.5V
IOL = 10 p,A
IOH = -10 p,A

fSK

SK Clock Frequency

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

tSKH

SK High Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 2)

1
1

p,s

tSKL

SK Low Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 2)

1
1

p,s

tSKS

SK Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to CS

50
50
100

1
1

p,s

Peak-to-Peak
(Note 5)

0.8
2
-0.1
0.8 Vcc

0.15 Vcc
Vcc + 1

0.4

0.1 Vcc

250
250

kHz

2.4

0.9 Vcc
0
0

tcs

MinimumCS
Low Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 3)

tcss

CS Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

0.2
0.2

p,s

tpRES

PRE Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

0.2
0.2

p,s

2-89

..J
CD
CD

LOW VOLTAGE «4.5) SPECIFICATIONS

o......
..J
CD
LC)

DC and AC Electrical

(Continued)

Characterist~cs (Continued)
Max

Units

Part Number

Conditions

Min

tpES

PE Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE- NM93CS66LE

Relative to SK

0.2
0.2

J-I-s

o......

tOIS

01 Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

0.4
0.4

J-I-s

tOH

DO Hold Time

Relative to SK

tesH

CS Hold Time

Relative to SK

J-I-s

tpEH

PE Hold Time

Relative to CS
Relative to CS

0.4
0.4

J-I-s

tPREH

PRE Hold Time

Relative to SK

J-I-s

tOIH

01 Hold Time

Relative to SK

0.4

tp01

Output Delay to "1"

o......
..J
CD

Symbol

Parameter

..J
CD

('t)
0')

::E

Output Delay to "0"

tpoo

CS to Status Valid

tsv
tOF

CSto OOin
TRI-STATE®

twp

Write Cycle Time

Capacitance
TA

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

J-I-s

ACTest

2
2

J-I-s

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest

2
2

J-I-s

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest

1
1

J-I-s

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

CS = VIL
ACTest

0.4
0.4

J-I-s

(Note 4)

= 25°C, f = 1MHz
Test

Max

COUT

Symbol

Output Capacitance

Units

CIN

Input Capacitance

AC Test Conditions
Output Load: 1 TTL Gate and CL = 100 pF
AC Test Conditions

Vee Range

4.5V

2.0V

< Vee < 5.5V

< Vee < 4.5V

Input Pulse Levels
Timing Measurement Level (VILIVIN):
Timing Measurement Level (VOLIVOH):
(TIL Load Conditions: IOL = 2.1 mA; IOH

= -

Input Pulse Levels:
Timing Measurement Level (VILIVIH):
Timing Measurement Level (VOLIVOH):
(CMOS Load Conditions: IOL = 10 J-I-A; IOH

O.BV and 2.0V
0.9Vand 1.9V
O.BV and 2.0V
0.4 mA)

= -

0.3V and 1.BV
0.4Vand 1.6V
O.BV and 1.6V
10 J-I-A)

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The above SK frequency specifies a minimum SK clock period of 4 J-Ls; therefore, in an SK clock cycle, tSKH + tSKL must be greater than or equal to 4 J-Ls.
For example, if tSKL = 1 J-Ls, then the minimum tSKH = 3 J-Ls in order to meet the SK frequency specification.
Note 3: CS must be brought low for a minimum of 1 J-Ls (lcs) between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
Note 5: Rate of voltage change must be less than 0.5 V/ms.

2-90

STANDARD VOLTAGE (4.5
Absolute Maximum Ratings

Lead Temp. (Soldering, 10 second)
ESD Rating

5.5) SPECIFICATIONS

(")

en
o

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Storage Temperature
- 65°C to + 150°C
All Input or Output Voltages
with Respect to Ground

Ambient Operating Temperature
NM93CSxxL
NM93CSxxLE

O°Cto + 70°C
- 40°C to + 85°C
4.5V to 5.5V

Power Supply (Vce)

r......

(")

en
~

+6.5Vto -0.3V

r......

+ 300°C

2000V

r......

(")

en
en

DC and AC Electrical Characteristics Vcc =

4.5V to 5.5V unless otherwise specified
Throughout this table "MOl refers to temperature range (- 55°C to + 125°C) not package.

Symbol

Parameter

Part Number

Conditions

ICC1

Operating Current
CMOS Input Levels

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ICC2

Operating Current
TTL Input Levels

ICC3

Max

Units

CS = VIH, SK = 1.0 MHz
SK = 1.0 MHz

2
2

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

CS = VIH, SK = 1.0 MHz
SK = 1.0 MHz

3
3

rnA

Standby Current

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

CS = OV

50
50

,...,A

IlL

Input Leakage

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

VIN = OV to Vcc

-2.5
-10

2.5
10

,...,A

IOL

Output Leakage

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Your

-2.5
-10

2.5
10

,...,A

VIL
VIH

Input Low Voltage
Input High Voltage

-0.1
2

Vec+ 1

VOL1

Output Low Voltage

VOL2
VOH2

Output Low Voltage
Output High Voltage

fSK

SK Clock Frequency

N M93CS06L-N M93CS66L
NM93CS06LE-NM93CS66LE

tSKH

SK High Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 2)
(Note 2)

250
300

tSKL

SK Low Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 2)
(Note 2)

250
250

tes

MinimumCS
Low Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

(Note 4)
(Note 4)

250
250

tcss

CS Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

50
50

tpRES

PRE Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

50
50

tDH

DO Hold Time

Relative to SK

NM93CS06LE-NM93CS66LE
NM93CS06LE-NM93CS66LE

= OV to Vcc

0.8
0.4
0.4

IOL = 2.1 mA
IOL = 2.1 mA
IOL = 10 JlA
IOL = -10,...,A

2-91

Min

0.2
Vcc- 0.2
0
0

1
1

V
V
V
MHz

..J
CD

STANDARD VOLTAGE (4.5 ~ V ~ 5.5) SPECIFICATIONS

(f)

o........

..J

(Continued)

DC and AC Electrical Characteristics Vee = 4.5V to 5.5V unless otherwise specified
Throughout this table "M" refers to temperature range (- 55°C to + 125°C) not package. (Continued)

(f)

o
........

Symbol

Part Number

Conditions

Min

tpES

PE Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

50
50

tOIS

01 Setup Time

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

Relative to SK

100
100

tesH

CS Hold Time

Relative to SK

tpEH

PE Hold Time

Relative to CS
Relative to CS

250
250

tpREH

PRE Hold Time

Relative to SK

tOIH

01 Hold Time

Relative to SK

tp01

Output Delay to "1"

..J
~

Parameter

(f)

o
........

..J
CD

C
(f)

o
C")

en
:ill

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest

Max

500
500

Units

tpoo

Output Delay to "0"

N M93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest

500
500

tsv

CS to Status Valid

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest

500
500

tOF

CSto DO in
TRI-STATE®

NM93CS06L-NM93CS66L
NM93CS06LE-NM93CS66LE

ACTest
CS = VIL

100
100

twp

Write Cycle Time

Capacitance (Note 6)
TA

25°C f

1 MHz

Test

Max

Units

COUT

Output Capacitance

CIN

Input Capacitance

Symbol

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial and Extended parts specifies a minimum SK clock period of 1 microsecond; therefore. in an SK clock cycle,
tSKH + tSKL must be greater than or equal to 1 microsecond. For example, if tSKL = 250 ns, then the minimum tSKH = 750 ns in order to meet the SK frequency
specification.
Note 3: The SK frequency specification for Military Temperature parts specifies a minimum SK clock period of 2 microseconds; therefore, in an SK clock cycle,
tSKH + tSKL must be greater than or equal to 2 microseconds. For example, if tSKL = 500 ns, then the minimum tSKH = 1.5 microseconds in order to meet the SK
frequency specification.
Note 4: For Commercial and Extended parts, CS must be brought low for a minimum of 250 ns (leS) between consecutive instruction cycles.
Note 5: For Military Temperature parts, CS must be brought low for a minimum of 500 ns (les) between consecutive instruction cycles.
Note 6.: This parameter is periodically sampled and not 100% tested.

2-92

::
CD

Functional Description

The extended voltage EEPROMs of the NM93CSxxL Family
have 10 instructions as described below. Note that there is
a difference in the length of the instruction for the
NM93CS06L and NM93CS46L vs. the NM93CS56L and
NM93CS66L since the two larger devices require 2 additional address bits which are not required for the smaller devices. Within the two groups of devices the number of address
bits remain constant even though in some cases the most
significant bites) are not used. In every instruction, the first
bit is always a "1" and is viewed as a start bit. The next 8 or
10 bits, depending on device size, carry the op code and
address. The address is either 6 or 8 bits, depending on the
device size.

Write Disable (WDS):

(')

To protect against accidental data disturb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.

Protect Register Read (PRREAD):
The Protect Register Read (PRREAD) instruction outputs
the address stored in the Protect Register on the DO pin.
The PRE pin MUST be held high while loading the in~truc
tion. Following the PRREAD instruction the 6- or 8-blt address stored in the memory protect register is transferred to
the serial out shift register. As in the READ mode, a dummy
bit (logical 0) precedes the 6- or 8-bit address string.

Read and Sequential Register Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock. In the Sequential Read mode of
operation, the memory automatically cycles to the next register after each 16 data bits are clocked out. The dummy-bit
is suppressed in this mode and a continuous string of data is
obtained.

Protect Register Enable (PREN):
The Protect Register Enable (PREN) instruction is used to
enable the PRCLEAR, PRWRITE, and PROS modes. Before
the PREN mode can be entered, the part must be in the
Write Enable (WEN) mode. Both the PRE and PE pins
MUST be held high while loading the instruction.
Note that a PREN instruction must immediately precede a
PRCLEAR, PRWRITE, or PROS instruction.
Protect Register Clear (PRCLEAR):
The Protect Register Clear (PRCLEAR) instruction clears
the address stored in the Protect Register and therefore
enables all registers for the WRITE and WRALL instruction.
The PRE and PE pins must be held high while loading the
instruction; however, after loading the PRCLEAR instruction, the PRE and PE pins become "don't care". Note that a
PREN instruction must immediately precede a PRCLEAR
instruction. The Protect Register will be read as Os after it is
cleared.

Write Enable (WEN):
When Vee is applied to the part, it "powers up" in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
executed or Vee is removed from the part.
Write (WRITE):
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address. After the last bit of
data is allocated to the data-in (01) pin, CS must be brought
low before the next rising edge of the SK clock. This falling
edge of the CS initiates the self-timed programming cycle.
The PE pin MUST be held high while loading the WRITE
instruction; however, after loading the WRITE instruction,
the PE pin becomes a "don't care". The DO pin indicates
the READY IBUSY status of the chip if CS is brought high
after a minimum of 250 ns (tcs). DO = logical 0 indicates
that programming is still in progress. DO = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in
the instruction and that the part is ready for another instruction.

Protect Register Write (PRWRITE):
The Protect Register Write (PRWRITE) instruction is used to
write into the Protect Register which is the address of the
first register to be protected. After the PRWRITE instruction
is executed, all memory registers whose addresses are
greater than or equal to the address specified in the Protect
Register are protected from the WRITE operation. Note t~at
before executing a PRWRITE instruction, the Protect Register must first be cleared by executing a PRCLEAR operation
and the PRE and PE pins must be held high while loading
the instruction; however, after loading the PRWRITE instruction, the PRE and PE pins become "don't care". Note
that a PREN instruction must immediately precede a
PRWRITE instruction.
Protect Register Disable (PROS):
The Protect Register Disable (PROS) instruction is a one
time only instruction which renders the Protect Register unalterable in the future. Therefore, the specified registers become PERMANENTLY protected against data changes. As
in the PRWRITE instruction the PRE and PE pins must be
held high while loading the instruction, and after loading the
PROS instruction the PRE and PE pins become "don't
care".

Write All (WRALL):
The Write All (WRALL) instruction is valid only when the
Protect Register has been cleared by executing a
PRCLEAR instruction. The WRALL instruction will simultaneously program all registers with the data pattern specified
in the instruction. Like the WRITE instruction, the PE pin
MUST be held high while loading the WRALL instruction;
however, after loading the WRITE instruction, the PE p~n
becomes a "don't care". As in the WRITE mode, the DO pin
indicates the READY IBUSY status of the chip if CS is
brought high after a minimum of 250 ns (tcs).

Note that a PREN instruction must immediately precede a
PROS instruction.

2-93

en
o

(')
""
en
~

(')
""
en
U1

""
en
(')

en
en

..J
CD
CD

Instruction Set for the NM93CS06L and NM93CS46L

.......

Instruction

OpCode

Address

CD
Ln

READ

A5-AO

o
.......

WEN

11XXXX

WRITE

A5-AO

015-00

WRALL

01XXXX

015-00

..J

..J
~

o
.......
..J

Data

PRE

Comments

Reads data stored in memory, starting at specified address.

Write enable must precede all programming modes.

Writes register if address is unprotected.

Writes all registers. Valid only when Protect Register is
cleared .

WOS

OOXXXX

Disables all programming instructions.

o
Cf)

PRREAO

XXXXXX

Reads address stored in Protect Register.

PREN

11XXXX

Must immediately precede PRCLEAR, PRWRITE, and
PROS instructions.

PRCLEAR

111111

Clears the Protect Register so that no registers are
protected from WRITE. Cleared state is read as O's.

PRWRITE

A5-AO

Programs address into Protect Register. Thereafter,
memory addresses ~ the address in Protect Register are
protected from WRITE.

PROS

000000

One time only instruction after which the address in the
Protect Register cannot be altered.

:!E

Instruction Set for the NM93CS56L and NM93CS66L
Instruction

PRE

Comments

Reads data stored in memory, starting at specified address.

Write enable must precede all programming modes.

Writes register if address is unprotected.

Writes all registers. Valid only when Protect Register is
cleared.

OOXXXXXX

Disables all programming instructions.

XXXXXXXX

Reads address stored in Protect Register.

11XXXXXX

Must immediately precede PRCLEAR, PRWRITE, and
PROS instructions.

11111111

Clears the "protect register" so that no registers are
protected from WRITE. Cleared state is read as O's.

A7-AO

Programs address into Protect Register. Thereafter,
memory addresses ~ the address in Protect Register are
protected from WRITE.

00000000

One time only instruction after which the address in the
Protect Register cannot be altered.

OpCode

Address

READ

A7-AO

Data

WEN

11XXXXXX

WRITE

A7-AO

015-00

WRALL

01XXXXXX

015-00

WDS

PRREAO

PREN

PRCLEAR

PRWRITE

PROS

2·94

3:
CO
w

Timing Diagrams

Synchronous Data Timing

en
C)

en
.-

.......

o
en
~

en
.-

.......

o
en
U1

en
.-

.......
VOH

en
en

---+----+--~

DO (READ) VOL

en
.-

VOH

DO (PROGRAM) V - - - - " \ ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OL
TL/D/10044-15

·This is the minimum SK period (Note 2).
ttSKS is not needed if DI = VIL when CS is going active (HIGH).

READ:
PRE = 0, PE = X

csJ
SK

JlJlJU1JUlfLJ1JlJ1MJUlfm

·Address bit A7 becomes "don't care" for NM93CS56L.
·Address bits A5 and A4 become "don't cares" for NM93CS06L.

TL/D/10044-5

tThe memory automatically cycles to the next register.

2-95

..J
CD
CD

o
........

Timing Diagrams

(Continued)
WEN:
PRE = 0, DO = TRI-STATE

..J
CD
Ln

o
........

K\\\\\\\\\\

..J
CD
~

o
........
..J

csJ

CD
C

en
oCf)

SKO

:!E

.~"",----

TL/D/l0044-6
'The NM93CS56L and NM93CS66L require a minimum of 11 clock cycles. The NM93CS06L and NM93CS46L require a minimum of 9 clock cycles.

WDS:
PRE = 0, PE = X, DO = TRI-STATE
CS

SKO

.]0\----

TL/D/l0044-7
'The NM93CS56L and NM93CS66L require a minimum of 11 clock cycles. The NM93CS06L and NM93CS46L require a minimum of 9 clock cycles.

WRITE:
PRE = 0

K\\\\\\\\\\
CS

Oo--~6~t
=!

READY

t wp

TLlD/10044-8
• Address bit A7 becomes a "don't care" for NM93CS56L.
• Address bits A5 and A4 become "don't cares" for NM93CS06L.

2-96

Timing Diagrams

E:
CD
w

(Continued)

WRALL:
PRE = 0

0')

.......

K\\\\\\

csJ

en
~

0')

r
.......
o
en
U1

0')

r
.......

0')
0')

oo------------~L-\~~~~
~tw~
'Don't care

TL/D/10044-9

tProtect Register MUST be cleared.

PRREAD:
PE = X
PRE

J
J

01~1

1~_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

oo------------------------------~
TL/D/10044-10

-Address bits AS and A4 become "don't cares" for NM93CS06L.
-Address bit A7 becomes "don't care" for NM93CS56L.

2-97

..J
CD
CD

t/)

Timing Diagrams

(Continued)

.......

..J

CD
Ln

t/)

o
.......

..J

PRE

CD
~

PREN*:
TRI-STATE

t/)

o
.......
..J
CD
Q

t/)

o
C")

:::lE

--.A. O.__O..,/ 1
TLlD/10044-11

°A WEN cycle must precede a PREN cycle.

PRCLEAR*:

PRE

J
J

1\_____

OJ~l

oo---+--L
~

BUSY.Jl READY

°A PREN cycle must Immediately precede a PRCLEAR cycle.

2-98

'TL/D/10044-12

Timing Diagrams

(Continued)

en
o

PRWRITEt:
PRE

en
r-

"'-

o
en
~

en
r-

"'-

oen
(J1

en
r-

"'-

en
en
r-

oo----+--L
'U~ t
~

REAOY

\'-----TL/D/l0044-13

"Address bit A7 becomes a "don't care" for NM93CSS6L.
• Address bits AS and A4 become "don't cares" for NM93CS06L.
tProtect Register MUST be cleared before a PRWRITE cycle. A PREN cycle must Immediately precede a PRWRITE cycle.

PROS·:
PRE

CSJ

OI~~O_____O____O_________________O____O________________________

OO--------------------+b--s! ,~m 'TLlD/l0044-14

"ONE TIME ONLY instruction. A PREN cycle must Immediately precede a PRDS cycle.

2-99

«
CD

~ ~National
~

Semiconductor

NM93C46A
1024-Bit Serial EEPROM
64 x 16-Bit or 128 x 8-Bit Configurable
General Description

Features

The NM93C46A is 1024 bits of CMOS non-volatile electrically erasable memory organized as either 64 16-bit registers or 128 8-bit registers. The organization is determined by
the status of the ORG input. The memory device is fabricated using National Semiconductor's floating gate CMOS process for high reliability, high endurance and low power consumption. The NM93C46A is available in an SO package for
space considerations.

• Device status during programming mode
• Typical active current of 400 /LA; typical standby
current of 25 /LA

The interface that controls the EEPROM is MICROWIRETM
compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. There are 7 instructions
that operate the NM93C46A: Read, Erase/Write Enable,
Erase, Write, Erase/Write Disable, Write All, and Erase All.

•
•
•
•
•
•
•

Direct write
Reliable CMOS floating gate technology
MICROWIRE compatible interface
Self-timed programming cycle
40 years data retention
Endurance: 106 data changes
Packages available: 8-pin SO, 8-pin DIP

The NM93C46A is compatible with National Semiconductor's NM93C46 if the ORG pin (Pin 6) is left floating, as it is
internally pulled up to Vee to default to the 64 x 16 configuration.

Block Diagram

ORG---~~------+I
CS---~~------+I
SK---~~------+I

INSTRUCTION
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS

+-Vcc

HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER

DO.---------~

TL/D/11042-1

2-100

Connection Diagrams

Dual-In-Line Package (N)
and S-Pln SO (MS)

Pin Names
CS

Chip Select

8 -Vee

Serial Data Clock

7 -NC

Serial Data Input

01- 3

6 -ORG

Serial Data Output

DQ-4

5 -GNO

GND

Ground

CS- 1

\.J

SK- 2

TLlD/ll042-2

Top View

Vee

Power Supply

ORG

Organization

See NS Package Number
NOSE and MOSA

Ordering Information
Commercial Temp. Range (O°C to

+ 70°C)

Order Number
NM93C46AN
NM93C46AM8

Extended Temp. Range (- 40°C to

+ S5°C)

Order Number
NM93C46AEN
NM93C46AEM8

Military Temp. Range ( - 55°C to
Order Number
NM93C46AMN
NM93C46AMM8

2-101

+ 125°C)

0l:Io

0')

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Storage Temperature
Ail Input or Output Voltages
with Respect to Ground

Ambient Operating Temperature
NM93C46A
NM93C46AE
NM93C46AM

- 65·C to + 150·C

O·Cto +70·C
- 40·C to + 85·C
- 55·C to + 125·C
4.5Vto 5.5V

Power Supply (Vce)
+6.5Vto -0.3V

Lead Temperature
(Soldering, 10 Seconds)

+300·C

EDS Rating

2000V

DC and AC Electrical Characteristics Vcc =
Note: Throughout this table, "M" refers to temperature range (- 55°C to

5.0V ±10% Unless Otherwise Specified

+ 125°C), not package.

Parameter

Part Number

Max

Units

Operating Current
CMOS Input Levels

NM93C46A
NM93C46AE
NM93C46AM

CS = VIH, SK = 1 MHz
SK = 1 MHz
SK = 0.5 MHz

2
2
2

Operating Current
TTL Input Levels

NM93C46A
NM93C46AE
NM93C46AM

CS = VIH, SK = 1 MHz
SK = 1 MHz
SK = 0.5 MHz

3
3
4

ICC3

Standby Current

NM93C46A
NM93C46AE
NM93C46AM

CS = OV

III

Input Leakage

NM93C46A
NM93C46AE
NM93C46AM

VIN = OVtoVcc

NM93C46A
NM93C46AE.
NM93C46AM

VIN = OVtoVcc

Symbol
ICC1

ICC2

IOL

Output Leakage

Conditions

Min

50
100
100

p..A

-2.5
-10
-10

2.5
10
10

p..A

-2.5
-10
-10

2.5
10
10

p..A

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

Vcc+ 1

VOL1

Output Low Voltage

0.4
0.4
0.4

VOH1

Output High Voltage

VOL2

Output Low Voltage

VOH2

Output High Voltage

fSK

SK Clock Frequency

tSKH

tSKL

tSKS

tcs

NM93C46A
NM93C46AE
NM93C46AM

SK High Time

SK Low Time

SK Setup Time

MinimumCS
Low Time

IOL = 2.1 mA
IOl = 2.1 mA
IOL = 1.8mA
IOH = -400 p..A

0.2

IOL = 10 p..A
IOH = -10 p..A
NM93C46A
NM93C46AE
NM93C46AM

2.4

Vcc - 0.2
0
0
0

1
1
0.5

MHz

NM93C46A
NM93C46AE
NM93C46AM

(Note 2)
(Note 2)
(Note 3)

250
300
500

NM93C46A
NM93C46AE
NM93C46AM

(Note 2)
(Note 2)
(Note 3)

250
250
500

NM93C46A
NM93C46AE
NM93C46AM

Relative to CS

50
50
100

NM93C46A
NM93C46AE
NM93C46AM

(Note 4)
(Note 4)
(Note 5)

250
250
500

2-102

DC and AC Electrical Characteristics Vee = 5.0V ± 10% Unless Otherwised Specified (Continued)
Parameter

Part Number

Conditions

Min

CS Setup Time

NM93C46A
NM93C46AE
NM93C46AM

Relative to SK

50
50
100

NM93C46A
NM93C46AE
NM93C46AM

Relative to SK

100
100
200

ns
ns

Symbol
tess

DI Setup Time

tOIS

tesH

CSHoldTime

Relative to SK

tOIH

01 Hold Time

Relative to SK

tp01

Output Delay to "1"

Output Delay to "0"

tpoo

CS to Status Valid

tsv

CSto DO in
TRI·STATE®

tOF

twp

Write Cycle Time

tOH

DO Hold Time

Capacitance
TA

= + 25'C, f =

NM93C46A
NM93C46AE
NM93C46AM

ACTest

NM93C46A
NM93C46AE
NM93C46AM

ACTest

NM93C46A
NM93C46AE
NM93C46AM

ACTest

NM93C46A
NM93C46AE
NM93C46AM

ACTest
CS = VIL

Relative to SK

Units

ns
500
500
1000

500
500
1000

100
100
200

ms
ns

AC Test Conditions

(Note 6)

Output Load

1 MHz

Symbol

Test

Max

Units

COUT

Output Capacitance

Input Capacitance

CIH

Max

1 TTL Gate and CL

= 100 pF

Input Pulse Levels

O.4V to 2.4V

Timing Measurement Reference Level
Input
Output

1V and 2V
0.8Vand 2V

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial and Extended temperature range parts specifies a minimum SK clock period of 1 /Ls; therefore, in an SK
clock cycle, tSKH + tSKL must be greater than or equal to 1 /Ls. For example, if tSKL = 2S0 ns, then the minimum tSKH = 7S0 ns in order to meet the SK frequency
specification.
Note 3: The SK frequency specification for Military Temperature parts specifies a minimum SK clock period of 2 /Ls; therefore, in an SK clock cycle, tSKH + tSKL
must be greater than or equal to 2 /Ls. For example, if the tSKL = SOO ns, then the minimum tSKH = 1.S /Ls in order to meet the SK frequency specification.
Note 4: For Commercial parts, CS must be brought low for a minimum of 2S0 ns

(tcs) between consecutive instruction cycles.
(tcs) between consecutive instruction cycles.

Note 5: For Military Temperature parts, CS must be brought low for a minimum of SOO ns
Note 6: This parameter is periodically sampled and not 100% tested.

2·103

Functional Description
Write (WRITE)

The NM93C46A has 7 instructions as described below.
Note that the MSB of any instruction is a "1" and is viewed
as a start bit in the interface sequence. The next 8/9 bits
carry the op code and the 617-bit address for register selection.

The Write (WRITE) instruction is followed by 8 or 16 bits of
data to be written into the specified address. After the last
bit of data is put on the data-in (01) pin, CS must be brought
low before the next rising edge of the SK clock. This falling
edge of CS initiates the self-timed programming cycle. The
DO pin indicates the READY/BUSY status of the chip if CS
is brought high after a minimum of 2S0 ns (tes). DO =
logical 0 indicates that programming is still in progress. DO
= logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern
specified in the instruction and the part is ready for another
instruction.

Read (READ)
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded, followed by data transfer from the
selected memory register into an 8- or 16-bit serial-out shift
register. A dummy bit (logical 0) precedes the 8- or 16-bit
data output string. Output data changes are initiated by a
low to high transition of the SK clock.

Erase All (ERAL)

Erase/Write Enable (EWEN)

The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical '1'
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 2S0 ns (tes). The
ERASE ALL instruction is not required, see note below.

When Vee is applied to the part, it powers up in the
Erase/Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or Vee
is removed from the part.

Write All (WRAL)

Erase (ERASE)

The (WRAL) instruction will simultaneously program all registers with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
2S0 ns (tes).

The ERASE instruction will program all bits in the specified
register to the logical '1' state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 2S0 ns (tes). DO =
logical '0' indicates that programming is still in progress. DO
= logical '1' indicates that the register, at the address specified in the instruction, has been erased, and the part is
ready for another instruction.

Erase/Write Disable (EWDS)
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.

Note: The NM93C46A device does not require an 'ERASE' or 'ERASE ALL' prior to the 'WRITE' and 'WRITE ALL' instructions. The 'ERASE' and 'ERASE ALL'
instructions are included to maintain compatibility with the NMOS NMC9346.

Instruction Set
Instruction

Start Bit

Opcode

Address*
128x8

64x 16

Data
128x 8

Comments
64 X 16
Read Address AN-AO

READ

A6-AO

AS-AO

ERASE

A6-AO

AS-AO

WRITE

A6-AO

AS-AO

EWEN

11XXXXX

11XXXX

Program Enable

EWDS

OOXXXXX

OOXXXX

Program Disable

ERAL

10XXXXX

10XXXX

WRAL

01XXXXX

01XXXX

·It is necessary to clock in the "Don't Care" Address Bits.

2-104

Erase Address AN-AO
D7-DO

D1S-DO

Write Address AN-AO

Erase All Addresses
D7-DO

D1S-DO

Program All Addresses

Timing Diagrams
Synchronous Data Timing

tess

1------- 1 J.'s
tSKH
-I'

----.j

VOH

DO (PROGRAM)

VOL

-----(
STATUS VALID
'---------------------________________________1
TL/O/ll042-3

"This is the minimum SK period (Note 2).
ttsKS is not needed if 01 = VIL when CS is going active (HIGH).

READ

csJ

..~l2
~~---~~----------------------------------------

DO - - - - - - - - - - - - - - - - - 0

•••

TLlO/ll042-4

EWENt
DO

=TRI-STATE

CSJ

FJ
SK

..:>0\----

TL/O/ll042-5

tFor the EWEN, EWOS, WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x 8 configuration a minimum of 5 additional clock cycles are required.

2-105

Timing Diagrams

(Continued)

EWDst

csJ

=TRI-STATE
U

.00\
TLlO/11042-6

WRITE

CSJ

r;\

r;v;;;v::.

---1ILJI~

oo---------------------------nll------------~Z'~l----~--~

READY

\..
TLlO/11042-7

WRALt

csJ
SK

":B---

OO------------------------------------~Zll~----------~~----~----,

TL/O/11042-8
tFor the EWEN, EWDS, WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x 8 configuration a minimum of 5 additional clock cycles are required.

2-106

Timing Diagrams

(Continued)

0')

ERASE
SK

VUSK\\SSS\\\S\SSSSS'

- -.....

CSJ

"~~--~~~~------~-~-r---
______
__

DO ___

__________________________

T_R~I-_ST_A_TE

~5~S

~~~

,---,'- TRI-STATE

TL/D/11042-9

ERALt
SK

-_.....

CSJ
/1\

01 - - . J 1 \ _ O_ _

TRI-STATE

DO----~--------------------------------------~P-+---~~~'--'I

TLlD/l1042-10

tFor the EWEN. EWDS. WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x 8 configuration a minimum of 5 additional clock cycles are required.

Synchronous Data Timing

tess ~------ 1 j.Ls· - - - . - j
~--'-;""'~-- tsKH --·~lfooI.'---

VOH

DO (READ) VOL

DO (PROGRAM)

VOH
VOL

-----+----+---,,1
~

-----(

_______________________________J
STATUS VALID
TL/D/11042-11

·This is the minimum SK period (Note 2).
ttSKS is not needed if DI

= VIL when CS is going active (HIGH).

2-107

..J
c(

~ ~National
~

:ill

Semiconductor

NM93C46AL
1024-Bit Serial EEPROM
64 x 16-Bit or 128 x 8-Bit Configurable
General Description

Features

The NM93C46AL is 1024 bits of CMOS non-volatile electrically erasable memory organized as either 64 16-bit registers or 128 8-bit registers. The organization is determined by
the status of the ORG input. The memory device is fabricated using National Semiconductor's floating gate CMOS process for high reliability, low power consumption and a wide
operating voltage range.

• 2.0V to 5.5V operation in read mode
• 2.5V to 5.5V operation in all other modes
• Typical active current of 400 p,A; typical standby current of 25 p,A

The interface is MICROWIRETM compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. There are 7 instructions that operate the
NM93C46AL: Read, Erase/Write Enable, Erase, Write,
Erase/Write Disable, Write All, and Erase All.

•
•
•
•
•
•
•

The NM93C46AL is compatible with National Semiconductor's NM93C46L if the ORG pin (Pin 6) is left floating, as it is
internally pulled up to Vee to default to the 64 x 16 configuration.

Block Diagram
ORG
INSTRUCTION
DECODER,
CONTROL LOGIC,
AND CLOCK
GENERATORS

CS
SK

+-Vcc

Vpp

HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER

DO~--------------------~

TL/D/11330-1

2-108

Connection Diagrams
Dual-In-Line Package (N)
and S-Pln SO (MS)

'-.-/

Pin Names
CS

Chip Select

8 f-Vcc

Serial Data Clock

SK- 2

7 f-NC

Serial Data Input

01- :3

6 f-ORG

00- 4

5 f-GNO

CS- 1

TL/D/11330-2

Top View
See NS Package Number
NOSE and MOSA

Serial Data Output

GND

Ground

Vee

Power Supply

ORG

Organization

Ordering Information
Commercial Temp. Range (O·C to

+ 70·C)

Order Number
NM93C46ALN
NM93C46ALMB
Extended Temp. Range (- 40·C to
Order Number
NM93C46ALEN
NM93C46ALEMB

2-109

+ S5·C)

LOW VOLTAGE «4.5V) SPECIFICATIONS
Operating Conditions

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-65·C to + 150·C
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
Lead Temperature
(Soldering, 10 Seconds)
+300·C
ESD Rating
2000V

Ambient Operating Temperature
NM93C46AL
NM93C46ALE

O·Cto +70·C
- 40·C to + 85·C

Power Supply Range
Read Mode
All Other Modes

2.0V to 5.5V
2.5Vto 5.5V

DC and AC Electrical Characteristics
Parameter

Part Number

Max

Units

ICC1

Operating Current
CMOS Input Levels

NM93C46AL
NM93C46ALE

CS = V,H. SK = 250 kHz

2
2

ICC2

Operating Current
TIL Input Levels

NM93C46AL
NM93C46ALE

CS = V'H, SK = 250 kHz
4.5V :::; Vee:::; 5.5V

3
3

ICC3

Standby Current

NM93C46AL
NM93C46ALE

CS = OV

50
100

/LA

I,L

Input Leakage

NM93C46AL
NM93C46ALE

Y,N = OV to Vee

Symbol

Conditions

Pin6
NM93C46AL
NM93C46ALE

Min

-2.5
-10

2.5
10

-10

-2.5
-10

2.5
10

/LA

IOL

Output Leakage

V,L1
V,H1

Input Low Voltage
Input High Voltage

4.5V :::; Vee:::; 5.5V

V,L2
V,H2

Input Low Voltage
Input High Voltage

2V :::; Vce:::; 4.5V

Vou

Output Low Voltage

VOH1

Output High Voltage

VOL2

Output Low Voltage

VOH2

Output High Voltage

fSK

SK Clock Frequency

NM93C46AL
NM93C46ALE

tSKH

SKHighTime

NM93C46AL
NM93C46ALE

(Note 2)

1
1

/Ls

tSKL

SKLowTime

NM93C46AL
NM93C46ALE

(Note 2)

1
1

/Ls

tes

MinimumCS
Low Time

NM93C46AL
NM93C46ALE

(Note 3)

1
1

/Ls

Y,N = OVtoVee

0.8
2

NM93C46AL
NM93C46ALE

4.5V :::; Vee:::; 5.5V
IOL = 2.1 mA
IOH = - 400 /LA

-0.1
0.8 Vee

0.2 Vee
Vce + 1

0.4

0.1 Vec

V
V

0.9 Vee
0
0

2·110

2.4

2V :::; Vee:::; 4.5V
IOL=10/LA
IOH = -10 /LA

/LA

250
250

kHz

LOW VOLTAGE ( < 4.5V) SPECIFICATIONS
DC and AC Electrical Characteristics (Continued)
Max

Units

Part Number

Conditions

Min

tess

CS Setup Time

NM93C46AL
NM93C46ALE

Relative to SK

0.2
0.2

p.s

tOIS

01 Setup Time

NM93C46AL
NM93C46ALE

Relative to SK

0.4
0.4

p.s

tesH

CS Hold Time

Relative to SK

p.s

tOIH

DI Hold Time

Relative to SK

0.4

tp01

Output Delay to "1"

NM93C46AL
NM93C46ALE

ACTest

2
2

p.s

tpoo

Output Delay to "0"

NM93C46AL
NM93C46ALE

ACTest

2
2

p.s

tsv

CS to Status Valid

NM93C46AL
NM93C46ALE

ACTest

1
1

p.s

tOF

CStoDOin
TRI·STATE®

NM93C46AL
NM93C46ALE

ACTest
CS = VIL

0.4
0.4

p.s

twp

Write Cycle Time

tOH

DO Hold Time

Symbol

Parameter

Capacitance
TA =

+ 25°C, f

Relative to SK

AC Test Conditions (>4.5V)

(Note 4)

Output Load

= 1 MHz

Units

Symbol

Test

Max

COUT

Output Capacitance

Input Capacitance

CIH

p.s

1 TTL Gate and CL = 100 pF

Input Pulse Levels

O.4V to 2.4V

Timing Measurement Reference Level
Input
Output

1V and 2V
0.8Vand 2V

2·111

STANDARD VOLTAGE (4.5 s;: VS;: 5.5)
Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground

Ambient Operating Temperature
NM93C46AL
NM93C46ALE

-6S·C to + 1S0·C

O·Cto +70·C
- 40·C to + 8S·C

Positive Power Supply (Vce)

4.SVto S.SV

+6.SVto -0.3V

Lead Temperature
(Soldering. 10 Seconds)

+300·C

ESD Rating

2000V

DC and AC Electrical Characteristics
Symbol

Parameter

Part Number

Max

Units

ICC1

Operating Current
CMOS Input Levels

NM93C46AL
NM93C46ALE

CS = VIH. SK = 1 MHZ
SK = O.S MHz

2
2

rnA

ICC2

Operating Current
TTL Input Levels

NM93C46AL
NM93C46ALE

CS = VIH. SK = 1 MHz
SK = O.S MHz

3
3

rnA

ICC3

Standby Current

NM93C46AL
NM93C46ALE

CS = OV

SO
100

IJ-A

IlL

Input Leakage

NM93C46AL
NM93C46ALE

VIN = OV to Vcc

-2.S
-10

2.S
10

IJ-A

IOL

Output Leakage

NM93C46AL
NM93C46ALE

VIN = OVtoVcc

-2.S
-10

2.S
10

IJ-A

Conditions

Min

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

Vcc+ 1

VOL1

Output Low Voltage

0.4
0.4

0.2

NM93C46AL
NM93C46ALE

IOL = 2.1 rnA
IOL = 2.1 rnA

VOH1

Output High Voltage

IOH = -400 IJ-A

VOL2

Output Low Voltage

IOL = 10 IJ-A

2.4

VOH2

Output High Voltage

IOH = -10 IJ-A

fSK

SK Clock Frequency

NM93C46AL
NM93C46ALE

tSKH

SK High Time

NM93C46AL
NM93C46ALE

(Note 2)
(Note 3)

2S0
SOO

tSKL

SK Low Time

NM93C46AL
NM93C46ALE

(Note 2)
(Note 3)

2S0
SOO

tcs

MinimumCS
Low Time

NM93C46AL
NM93C46ALE

(Note 4)
(NoteS)

2S0
SOD

Vcc - 0.2
0
0

2-112

1
O.S

MHz

STANDARD VOLTAGE
DC and AC Electrical Characteristics
Symbol

Parameter
CS Setup Time

tess

(4.5~V~5.5)

(Continued)

Part Number

Conditions

Min

NM93C46AL

Relative to SK

01 Setup Time

NM93C46AL

Relative to SK

CS Hold Time

tOIH

01 Hold Time

NM93C46AL

Relative to SK

100

NM93C46ALE
Output Delay to "1"

tp01

NM93C46AL

100

Relative to SK

ns
ns
ns

200
500

ACTest

1000

NM93C46ALE
Output Delay to "0"

tpoo

NM93C46AL

500

ACTest

1000

NM93C46ALE
CS to Status Valid

tsv

NM93C46AL

500

ACTest

1000

NM93C46ALE
tOF

CStoDOin

NM93C46AL

ACTest

100

TRI-STATE

NM93C46ALE

CS = VIL

200

Capacitance
TA =

Write Cycle Time

twp

+ 25°C, f

Symbol

AC Test Conditions

(Note 6)

= 1 MHz

Test

Output Load

Max

ns
ms

(>4.5V)

1 TTL Gate and CL = 100 pF

Input Pulse Levels

Units

Units
ns

200

NM93C46ALE
tesH

Max

100

NM93C46ALE
tOIS

(Continued)

O.4V to 2.4V

Timing Measurement Reference Level
COUT
CIH

Output Capacitance

Input Capacitance

Input
Output

1V and 2V
O.8Vand 2V

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 fLs; therefore, in an SK clock cycle, tSKH + tSKL must be
greater than or equal to 1 fLs. For example, if tSKL = 250 ns, then the minimum tSKH = 750 ns in order to meet the SK frequency specification.
Note 3: The SK frequency specification for Extended Temperature parts specifies a minimum SK clock period of 2 fLs; therefore, in an SK clock cycle, tSKH + tSKL
must be greater than or equal to 2 fLs. For example, if the tSKL = 500 ns, then the minimum tSKH = 1.5 fLs in order to meet the SK frequency specification.
Note 4: For Commercial parts, CS must be brought low for a minimum of 250 ns (tcs) between consecutive instruction cycles.
Note 5: For Extended Temperature parts, CS must be brought low for a minimum of 500 ns (les) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.

EI
I

2-113

..J

<
CD
~

o
CW)

en
:E

Functional Description
The NM93C46AL has seven instruction sets as described
below. Note that each instruction set is broken down into
the Start Bit (SB), Op code, Address (if applicable) and Data
(if applicable). As shown in the timing diagrams and INSTRUCTION SET tables, address bits will have 6/7 bits and
8/16 bits for the data. All instruction bits are entered into the
device on the SK low-to-high transitions.

Read (READ):

The Read instruction outputs the specified address data on
the DO pin. After the READ instruction is received, the instruction and address are decoded and data is transferred
from the address to an 8-/ 16-bit shift register output buffer.
A dummy bit (logical 0) precedes all 8-/16-bit data out
strings. The READ instruction may be executed from either
the enabled or disabled state.

Erase (ERASE):

This instruction, when followed by an address location, programs all bits in the selected register/address to a 1 state
(Register erase).

Erase/Write Enable (EWEN):

Erase All (ERAL):

When Vee is applied to the device, it powers up in the programming Erase/Write disabled state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once this instruction is executed,
programming remains enabled until the Erase/Write Disable
(EWOS) instruction is executed or until Vee is removed from
the part.

This instruction programs all registers/addresses in the
memory array to a 1 state (Bulk erase).

Erase/Write Disable (EWDS):

This instruction, when followed by 8/16 bits of data, programs all registers/addresses in the memory array with the
specified data pattern (Bulk write).

Write (WRITE):

This instruction, when followed by an address location and
8/16 bits of data, programs the selected register/address.
Write All (WRAL):

To protect against accidental data disturbance, the Erase/
Write Disable instruction disables all programming modes
and should follow the end of all programming cycles.

Note: The NM93C46AL device does not require an 'ERASE' or 'ERASE ALL' prior to the 'WRITE' and 'WRITE ALL' instructions. The 'ERASE' and 'ERASE ALL'
instructions are included to maintain compatibility with the NMOS NMC9346.

Instruction Set
Instruction

Start Bit

Opcode

Address·

128x8

64x 16

Data

128 x8

Comments

64 x 16

READ

A6-AO

A5-AO

ERASE

A6-AO

A5-AO

WRITE

A6-AO

A5-AO

EWEN

11XXXXX

11XXXX

Program Enable

EWDS

OOXXXXX

OOXXXX

Program Disable

ERAL

10XXXXX

10XXXX

WRAL

01XXXXX

01XXXX

·It is necessary to clock in the "Don't Care" Address Bits.

2-114

Read Address AN-AO
Erase Address AN-AO
07-00

015-00

Write Address AN-AO

Erase All Addresses
07-00

015-00

Program All Addresses

Timing Diagrams
Synchronous Data Timing

DO (PROGRAM)

VOH
VOL

1 - - - - - - - 1 J.'S

tess

'I'

f-o-==--o....--tSKH

----0(

----1

' -______________________________________________J

STATUS VALID

TL/D/11330-3

-This is the minimum SK period (Note 2).
ttSKS is not needed if DI = VIL when CS is going active (HIGH).

READ

CSJ

uuu

..~ZZ
~~--~~--------------------------~

DO --------------------------------

•••

TL/D/11330-4

EWENt
DO

= TRI-STATE

CSJ

.00\'-------

TL/D/11330-5

tFor the EWEN, EWDS, WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x B configuration a minimum of 5 additional clock cycles are required.

2-115

Timing Diagrams

(Continued)

EWDst

DO = TRI-STATE

csJ

.C)0\----

TL/0/11330-6

WRITE

CSJ

.~~--------------------

0 r;v:;JV:..
----11,\L.J
~
I

00----------------------------~2,l~----------~I~----~--~

TLl0/11330-7

WRALt

CSJ

..~~------------

OO--------------------------------------~l'~l------------~'~-----+----~

TL/0/11330-B

tFor the EWEN, EWDS, WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x 8 configuration a minimum of 5 additional clock cycles are required.

2-116

Timing Diagrams

(Continued)

ERASE

u-v =
S

~~----------------------------~;S~----~.~I

OO __

.
~T~RI~-~ST~A~TE~

·~H---+--"ilj-----+---to-F-

______________________~;S~

______

~~~

____

I,-....- I L

TRI-STATE

1Io-_~_'I

TL/D/11330-9

ERALt
SK

-_......

J
TRI-STATE

OO--------------------------~~~--~

-ft;.....,(~_1

TLlD/11330-10
tFor the EWEN. EWDS. WRAL and ERAL it is necessary to provide a minimum number of clock cycles after the last bit of opcode is clocked in. In the 64x16
configuration a minimum of 4 additional clock cycles are required. In the 128 x 8 configuration a minimum of 5 additional clock cycles are required.

2-117

C\I
,..

o
Ln

en
~

~National

Semiconductor

NM95C12 1K-Bit CMOS EEPROM
with Programmable Switches
General Description

Features

The NM95C12 is a 976-bit, CMOS EEPROM with 8 non-volatile programmable outputs that can be used as DIP
switches. The 976 bits of memory are divided into 61 registers of 16 bits each and each register can be individually
accessed. Registers 61-63 are dedicated to storing the
switch settings.

• 8 DIP switch positions or 4 SPST switch positions
• 976 bits of CMOS EEPROM memory available
• 4 mA (max) operating current, 50 p.A (max) standby
current
• Software write protection
• Serial I/O interface fully MICROWIRE compatible
• Single + 5V ± 10% operation
• 14-pin DIP or SO package availability
• 100,000 write cycles guaranteed, 500,000 typical
• 40 year data retention
• Reliable floating gate technology
• Sequential register read
• Self-timed write cycle
• Erase cycles not necessary
• Compatible with COPSTM microcontrollers

In addition to the 976 bits of EEPROM memory, the
NM95C12 contains eight individually programmable outputs
which can be used as switches and two additional registers
used in conjunction with the switch logic which are volatile.
Each switch output may be programmed to provide either a
High or Low level. These outputs may also be programmed
to form four individual pairs of SPST switches.
The switch configuration information is obtained from a non
volatile register whenever power is first applied to the device. This ensures the switches will always have a user determined state upon power-up.

Block Diagram
Address.
PROGRAMMING
&

POWER UP
CIRCUITS

,....-----.9
E2 PROM
61 WORDS x16 BITS

6'0

A2
B2

A3
B3
01
DO

S K - - -.......

CS-----..I

B4
TL/D/9632-1

FIGURE 1. Block Diagram

2-118

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vcc

Ambient Operating Temperature
NM95C12
NM95C12E
NM95C12M*

6.5V

Voltage at Any Pin

-65°C to +150°C

Maximum Power Dissipation @25°C

o
O°Cto +70°C
- 40°C to + 85°C
- 55°C to + 125°C
4.5Vto 5.5V

500mW

Lead Temperature
(Soldering, 10 seconds)

300°C

ESD Rating

2000V

DC Electrical Characteristics Vcc =
Symbol

<0
U1

Power Supply Voltage (Vce)
·Contact factory for availability

-0.3 to +6.5V

Storage Temperature Range

Operating Conditions

(Note 1)

5V ± 10%

Parameter

Max

Units

1 MHz

Min

1 MHz

/LA

800

/LA

Conditions
VIH. SK

=
=
=

Standby Current
TTL Input Levels on Switches

liL

Input Leakage

VIN

loL

Output Leakage

VOUT

VIL

ICC1

Operating Current CMOS Input Levels

ICC2

Operating Current TTL Input Levels

ICC3

Standby Current
CMOS Input Levels on Switches

ICC4

VIH. SK

=
=

OV to Vcc

-2.5

+2.5

/LA

-2.5

2.5

/LA

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

2.0

Vcc + 1

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

RON

Switch On Resistance

ROFF

Switch Off Resistance

= 2.1 mA
IOH = - 400 /LA

IOL

Maximum Voltage Allowed on any Switch Terminal
Max Current Allowed through Switch Terminals

AC Electrical Characteristics Vcc =

tSKH

tSKL

Parameter
SK Clock Frequency

SK High Time

SK Low Time

fSK

2.4
200

Symbol

OV to Vcc

!l
M!l

Vcc + 1

5V ± 10% unless otherwise specified

Part Number

Conditions

NM95C12
NM95C12E
NM95C12M

Min

Max

Units

0
0
0

1
1
0.5

MHz

NM95C12
NM95C12E
NM95C12M

(Note 2)
(Note 2)
(Note 3)

250
300
500

NM95C12
NM95C12E
NM95C12M

(Note 2)
(Note 2)
(Note 3)

250
250
500

50
50
100

ns
ns
ns

tSKS

SKSetup

NM95C12
NM95C12E
NM95C12M

tcs

MinimumCS
Low Time

NM95C12
NM95C12E
NM95C12M

(Note 4)
(Note 4)
(Note 5)

250
250
500

CS Setup Time

NM95C12
NM95C12E
NM95C12M

Relative to SK

50
50
100

tcss

2-119

-10.

N
,....
o
II)

:e
z

AC Electrical Characteristics Vee =
Symbol

Parameter

tpUSR

Power Up Slew Rate

to IS

01 Setup Time

5V ± 10% unless otherwise specified (Continued)

Part Number

NM95C12
NM95C12E
NM95C12M

Conditions

Relative to SK

Min

ms
ns
ns

CS Hold Time

Relative to SK

tOIH

01 Hold Time

Relative to SK

tp01

Output Delay to "1"

tpOD

tsv

tOF

tlSWD

tSWPOD

tSWP01

tsws

tSWH

Output Delay to "0"

CS to Status Valid

ACTest

500
500
1000

NM95C12
NM95C12E
NM95C12M

ACTest

500
500
1000

NM95C12
NM95C12E
NM95C12M

ACTest

500
500
1000

CStoDOin
TRI-STATE®

NM95C12
NM95C12E
NM95C12M

CS = VIL
ACTest

100
100
200

Switch Delay
from Switch Input

NM95C12
NM95C12E
NM95C12M

ACTest

250
250
500

Switch Delay
to 0 from
Config. Change

NM95C12
NM95C12E
NM95C12M

ACTest

500
500
1000

Switch Delay
to 1 from
Config. Change

NM95C12
NM95C12E
NM95C12M

ACTest

500
500
1000

A1-A4, B1-B4
Setup Time for
SRR Read

NM95C12
NM95C12E
NM95C12M

100
100
200

A1-A4, B1-B4
Hold Time for
SRR Read

NM95C12
NM95C12E
NM95C12M

100
100
200

twp

Write Cycle Time

tOH

DO Hold Time

10
Relative to SK

Capacitance (Note 6)
T A = 25°C, f = 1 MHz
Symbol

Units

100
100
200

tesH

NM95C12
NM95C12E
NM95C12M

Max

Test

ms
ns

AC Test Conditions
Output Load
Max

Units

COUT

Output Capacitance

CIN

Input Capacitance

1 TIL Gate and CL = 100 pF

Input Pulse Levels

O.4V to 2.4V

Timing Measurement Reference Level
Input
Output

1Vand 2V
0.8Vand 2V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range",
the device should not be operated at these limits. The table of "Electrical Characteristics" provides actual operating limits.
Note 2: The SK frequency specification for Commercial and Extended temperature range parts specifies a minimum SK clock period of 1 JLs; therefore, in an SK
clock cycle, tSKH + tSKL must be greater than or equal to 1 JLs. For example, if tSKL = 2S0 ns, then the minimum tSKH = 7S0 ns in order to meet the SK frequency
specification.
Note 3: The SK frequency specification for Military parts specifies a minimum SK clock period of 2 JLs; therefore, in an SK clock cycle tSKH + tSKL must be greater
than or equal to 2 JLs. For example, if tSKL = SOO ns, then the minimum tSKH = 1.S JLs in order to meet the SK frequency specification.
Note 4: For Commercial and Extended temperature range parts, CS must be brought low for a minimum of 2S0 ns (tes) between consecutive instruction cycles.
Note 5: For Military parts, CS must be brought low for a minimum of SOO ns (leS) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested.
Note 7: Power dissipation temperature derating-plastic "N" package: -12 mW I'C from + 6S'C to + 8S'C.

2-120

Connection Diagrams

....&.

SO Package

Dual-In-Llne Package

Pin Names

CS- 1

'-'

14 -Vee

CS- 1

SK- 2

13 -A4

SK- 2

13 -A4

01- 3

12 -84

01- 3

12 -84

00- 4

11 -A3

00- 4

11 -A3

81- 5

10 -83

81- 5

10 -83

~Vee

Al- 6

9 -A2

Al- 6

9 -A2

GNO- 7

8 -82

GNO- 7

8 -82

TL/D/9632-3

Top View
Order Number NM95C12M,
NM95C12EM and NM95C12MM
See NS Package M 14A

CS
SK
bl
DO
A1-A4
81-84

Chip Select
Serial Clock
Serial Data In
Serial Data Out
Switch Terminals
Switch Terminals

TL/D/9632-2

Top View
Order Number NM95C12N,
NM95C12EN and NM95C12MN
See NS Package N14A

Pin Descriptions
Pin
Name

Description

Chip Select, Input-This input must be high while communicating with the NM95C12. When this
input is LOW, the chip is powered down into the standby mode. It should be noted that the CS
does not control the A 1 through A4 and 81 through 84 outputs and hence has no effect on them.
The CS input must be made LOW after completing an instruction to prepare the control logic to
accept the next instruction. If the CS input becomes LOW prematureiy, the operation in progress
is aborted. If programming the E2 memory is in progress and the CS goes LOW, the programming
is not aborted but will proceed to its normal completion.

Serial Clock, Input-This input is used for clocking the serial 110. The CS input must be high for
clocking to have any effect. Information presented on the 01 input will be shifted into the device
on the LOW to HIGH transition of the clock. Information from the device will be available on the
DO output serially, in response to the LOW to HIGH transition of the clock.

Serial Data In, Input-All information needed for the operation of the device is entered serially
from this input. HIGH represents logic '1' and LOW represents logic '0'. The entry order is most
significant bit first and least significant bit last.

Serial Data Out, Output, 3-state-When data is read, data from the addressed location will be
available on this output serially, in sync with the LOW to HiGH transitions on the SK input.
Normally the DO pin is in high impedance state. During a read instruction, when the last bit of the
address is shifted in, the DO will go LOW indicating that data will follow. The data will follow in
response to the clock transitions. The data will come out most significant bit first and least
significant bit last. During E2 programming operations, this output is also used as the status
indicator. During programming operations, LOW indicates 8usy (programming in progress) and
HIGH indicates Ready. The DO output will be in the high impedance state if the CS input is LOW
unconditionally.

A1-A4
81-84

Switch Terminals-These pins provide the simulated DIP switch features and hence are called
terminals. The behavior of these pins is determined by the settings in the Switch Configuration
Register and are independent of the CS input.

Vee

+ 5V Power Supply.

GND

Ground.

2-121

Functional Description
address 61 is used in the NM95C12 to provide the initial
switch configuration information automatically on power-up.

Figure 1 is a block diagram of the NM95C12. It consists of a
62-word X 16-bit E2PROM array, a 16-bit Switch Configuration Register (SCR), a 16-bit Switch Readback Register
(SRR), four identical blocks of switch logic, programming
and power-up circuits and the necessary control logic. It
may be noted that only eight bit positions of the SRR are
used in the NM95C12.

The SCR is located at address 62. The SCR is not an E2
location and hence is volatile. It does not have endurance
limits or programming time requirements associated with it,
allowing the switches to be reconfigured an unlimited number of times.
The SCR is automatically loaded from address 61 on powerup. The SCR controls the switch logic and hence the behavior of the terminals A1 through A4 and B1 through B4.

ADDRESS SPACE

Registers 0-60 of the E2PROM are available to the user as
general purpose non-volatile memory. Data may be read or
programmed into this memory using the appropriate instructions. Address location 61 is an E2 location which also can
be read or programmed like any other E2 location. However,

Located at address 63 is the Switch Readback Register
(SRR). This is a read only register.

TABLE I. Switch Configurations
MODE·

SWITCH CONfiGURATION

~A~B

A=I,B=O

~A ~B

A = 1 , B= 1

COMMENTS

A=O, B=O

A=O,B=1

A = 0 , B= TRI-STATE

A=B

t>c>-::

A=i.i

~A
OB

0
0

A = 1 , B = TRI-STATE

A = TRI-STATE , B = 0

B=A

I ~:

B=A

A~ rco'

+o-fo
-=

"Modes 0 thru 11 are logic level functions. Modes 12 and 13 are Analog switch functions.

2-122

A = TRI-STATE , B= 1

Analog Switch
Open

Analog Switch
Closed

':"

TLlD/9632-6

Functional Description

(Continued)

SWITCH CONFIGURATIONS

The bit assignments and conceptual function of the SRR is
shown in Figure 3. As shown, only bits 15 thru 8 are used,
and bits 7 thru 0 are always read as logical O. The SRR is a
Read·Only register and if it is written, the device will not
perform a write or generate a Ready/8usy status. The SRR
is not implemented in EEPROM, allowing an infinite number
of cycles in the register.

The 16·bit SCR format is shown in Figure 2. It consists of
four 4·bit fields. Each field controls its corresponding switch
control logic. The individual bits in each field are labelled W,
X, Y, and Z. Table I shows the relationship between these
bit values and the resulting behavior of the terminals. It
should be remembered that the CS input has no effect on
the behavior of the terminals.

The NM95C12 instruction set contains five instructions, and
each instruction is ten bits long. The first 2 bits of the in·
struction are the start bits (S8) and are always a logical
"01", followed by the op code (2 bits) and the address field
(6 bits). The WRITE and WRALL instructions are followed
by sixteen bits of data (015-00) which is written into the
memory. Table II is a list of the instructions and their format.

The SRR allows the current logic level present at the switch
terminals to be read back via the Microwire bus. The SRR is
loaded by the rising edge of SK immediately after the last
instruction bit is clocked in (The same clock edge that loads
AO). The SRR is loaded on this clock edge only when regis·
ter 63 (Switch Readback Register) is being read. In the case
of switch mode 13 (Analog switch mode), the SRR will not
report the actual levels present at the terminals due to this
mode being analog levels. In mode 13, bits 15-8 of the
SRR will be all O's to indicate a closed analog switch. This is
done to avoid ambiguous logic levels which could exist
when the device is used in the analog switch mode.
11

.....

INSTRUCTION SET

SWITCH READBACK REGISTER

15 14 13 12

U1
(")

Izlvlxlwlzlvlxlwlzlvlxlwlzlvlxlwl
SWITCH 4

SWITCH 3

SWITCH 2

SWITCH 1

Tl/D/9632-4

FIGURE 2. Switch Configuration Register (SCR)

ENABLE 1

Tl/D/9632-5

FIGURE 3. Switch Readback Register (SRR)
TABLE II. NM95C12 Instructions
Instruction

Op Code

Address

READ

A5-AO

Reads data stored in memory, starting at specified address.

WEN

11XXXX

Write enable must precede all programming modes.

WRITE

A5-AO

015-00

Writes register.

WRALL

01XXXX

015·00

Writes all registers.

WOS

OOXXXX

Data

Comments

Disables all programming instructions.

2·123

C\I
,...

oit)

Functional Description

WDS (Write Disable): When this instruction is issued, all
subsequent writing into the NM95C12 is locked out. Any
attempt to write into a locked device is ignored. The
NM95C12 powers up in the locked state. The WEN is the
only instruction that unlocks the device. The write disable
operation has no effect on read operations. Thus reading
will occur normally even from a locked device.

(Continued)
the address. The data will come out serially on the DO output on the rising edge of the clock. A logical '0' precedes
the 16-bit data (dummy bit).
The NM95C12 has a convenient feature called sequential
register read. Normally, the CS input is made LOW after the
last data bit is shifted out. However; if the CS input is left
HIGH and clocking continues, data from the next address
location will be delivered on the DO pin. This sequential read
can continue indefinitely whereby the address is automatically incremented after delivering 16 bits of data. It should
be noted that in the sequential register read mode, address
wrap-around will occur.
During a sequential register read there will be a dummy bit
preceding the first word read, after which, the bit stream will
be continuous without any dummy bits separating the data
words.

WRALL (Write All): When this instruction is executed, the
NM95C12 bulk-programs the same 16-bit data pattern into
all of its E2 memory locations (address 0 through 61). The
SCR is unaffected since it is not an E2 location. The data
pattern must follow immediately after the last bit of this instruction. The chip enters into the self-timed program mode
after CS is brought low, before the next rising edge of SK.
WEN (Write Enable): This instruction is used to unlock the
write circuits. The circuits will remain unlocked until the
WDS instruction locks them. The NM95C12 powers up in
the locked state and hence WEN must be executed prior to
any programming instructions.

ReadyIBusy Indication
Programming an E2 memory takes several milliseconds. Unlike some devices which reCluire the user to keep track of
the elapsed time to ensure completion of the programming
cycle, the NM95C12 contains an on-chip timer. The timer
starts when the CS input goes LOW after the last data bit is
entered. After entering a programming cycle (CS forced
LOW), the timer status may be observed by forcing the CS
input back HIGH. The timer status is available on the DO pin
if the CS input is forced HIGH within one ms of starting the
programming cycle. LOW on the DO pin indicates that the
programming is still in progress while HIGH indicates the
device is READY for the next instruction. It should be noted
that if the CS input is made HIGH for status observation, it
must be made LOW when READY is indicated before loading the next instruction.

WRITE (Write/Program): This instruction writes a 16-bit
data word into the address location specified by the Ao-As
bits of the instruction. The 16 data bits must follow the last
bit of the instruction. After loading the WRITE instruction
and the 16-bit data, the chip enters into the self-timed program mode when CS is brought low before the next rising
edge of the SK clock. If the addressed location is the SCR,
then the chip does not enter into the self-timed E2 programming mode (the SCR is not an E2 location) but loads the
switch configuration data into the SCR. The WRITE instruction can only be aborted by deselecting the chip (CS LOW)
before entering all the instruction bits. The NM95C12 does
not require erasing prior to writing.
READ (Read): This instruction reads the data from the addressed location. As before, the instruction also contains

Timing Diagrams
Synchronous Data Timing

OO(REAO)

----'

---....p.---r

00 (PROGRAM)

*=~tsws

____________

Ai,Bi _ _ _ _ _ _ _ _ _ _ _ _ _

_ltSWPD~t:

'I tSWPDX-",:::::::

Bi,Ai

TL/D/9632-7

2-124

Timing Diagrams

(Continued)

......

Instruction Sequence

READ:

cSJ
SK

Ol---!J 1

1 \

GX::JG)GO"\

HI-Z

TL/D/9632-B

SRR READ:

csJ
SK

Ol---!J 1

GX::JG)GO"\\

HI- Z

X
X
~""t,,"~

Ai,8i

TL/D/9632-14

WEN:

\~-----------------------

CSJ
SK

oJ/

01 ----2...17\..;;0_ _.;..0

xXXXXXXXXXXXXA'-______________
TL/D/9632-9

WDS:
CSJ

\~-------------------------

TL/D/9632-10

"The memory automatically cycles to the next register.

2-125

Timing Diagrams

(Continued)

Instruction Sequence (Continued)

WRITE:
CS

DI _ _~

OO~H~I-Z~_ _ _----~---------------------r-------~__~B~U~SY~~Y-~R~EA~D~Y--'------i-----Iwp-----+l
TL/D/9632-11

WRITE SCR:
CS - - '

\~----------------

01~1
DO

1 \

______________________

HI-Z
TL/D/9632-12

01 ___..;.."

~HI~-Z~--------------------------------------------------r-------'-~B~US~Y~
1-4---lwp--TL/D/9632-13

2-126

Section 3
PROMs

Section 3 Contents
Bipolar PROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3

NON-REGISTERED BIPOLAR PROMS

DM74S188 (32 x 8) 256-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S288 (32 x 8) 256-Bit TTL PROM....... ....................... ..................
DM74S287 (256 x 4) 1024-Bit TTL PROM .............................................
DM74S387 (256 x 4) 1024-Bit TTL PROM .............................................
DM74LS471 (256 x 8) 2048-Bit TTL PROM.... ........................................
DM74S472 (512 x 8) 4096-Bit TTL PROM................ .............................
DM74S473 (512 x 8) 4096-Bit TTL PROM.............................................
DM74S570 (512 x 4) 2048-Bit TTL PROM....... .............................. ........
DM74S571 (512 x 4) 2048-Bit TTL PROM....... ......................................
DM74S572 (1024 x 4) 4096-Bit TTL PROM ............................................
DM74S573 (1024 x 4) 4096-Bit TTL PROM ............................................
APPLICATIONS INFORMATION
Bipolar PROM Devices in Plastic Leaded Chip Carriers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Registered PROM Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Approved Programmers/Quality Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

3-4
3-8
3-12
3-16
3-20
3-24
3-28
3-32
3-36
3-40
3-44
3-48
3-51
3-52
3-53
3-53

Bipolar PROM Selection Guide

Non-Registered PROMs
Size
(Bits)

Organization

Pins
(DIP)

Part
Number

tAA
(Max) In ns

tEA
(Max) In ns

Icc
(Max) In rnA

Temperature
Celsius

256

32 x 8
32 x8
32 x 8
32 x8

DC
TS
DC
TS

16
16
16
16

DM74S188
DM74S288
DM74S188A
DM74S288A

35
35
25
25

20
20
20
20

110
110
110
110

O°Cte
O°Cte
O°Cte
O°Cte

+ 70°C
+ 70°C
+ 70°C
+70°C

1024

256x4
256 x4
256x4
256x4

DC
TS
DC
TS

16
16
16
16

DM74S387
DM74S287
DM74S387A
DM74S287A

50
50
30
30

25
25
20
20

130
130
130
130

O°Cte
O°Cte
O°Cte
O°Cte

+ 70°C
+70°C
+ 70°C
+70°C

2048

512x4
512x4
512x4
512x4
512x4
256x8

DC
TS
DC
TS
TS
TS

16
16
16
16
16
20

DM74S570
DM74S571
DM74S570A
DM74S571A
DM74S5718
DM74LS471

55
55
45
45
35
60

30
30
25
25
25
30

130
130
130
130
130
100

O°Cte
O°Cte
O°Cte
O°Cte
O°Cte
O°Cte

+ 70°C
+70°C
+ 70°C
+ 70°C
+70°C
+70°C

4096

512x8
512x8
512x 8
512x8
512x 8
512x 8
1024x4
1024 x 4
1024 x4
1024 x 4
1024 x 4

DC
TS
DC
TS
TS
DC
DC
TS
DC
TS
TS

20
20
20
20
20
24
18
18
18
18
18

DM74S473
DM74S472
DM74S473A
DM74S472A
DM74S4728
DM74S475
DM74S572
DM74S573
DM74S572A
DM74S573A
DM74S5738

60
60
45
45
35
65
60
60
45
45
35

30
30
30
30
25
35
35
35
25
25
25

155
155
155
155
155
170
140
140
140
140
140

O°Cte
O°Cte
O°Cte
O°C te
O°Cte
O°Cte
O°C te
O°Cte
O°Cte
O°Cte
O°Cte

+70°C
+ 70°C
+ 70°C
+ 70°C
+70°c
+ 70°C
+70°C
+ 70°C
+ 70°C
+70°C
+ 70°C

3-3

a~National
Semiconductor
DM74S188
(32 X 8) 256-Bit TTL PROM
General Description

Features

This Schottky memory is organized in the popular 32 words
by 8 bits configuration. A memory enable input is provided
to control the output states. When the device is enabled, the
outputs represent the contents of the selected word. When
disabled, the 8 outputs go to the "OFF" or high impedance
state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-25 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
Pin Names

A4
A3

256-BIT ARRAY
32 x 8
MEMORY MATRIX

A2
Al
AO

00
TLfD/9187-1

3-4

AO-A4

Addresses

Output Enable

GND

Ground

00-07

Outputs

Vee

Power Supply

~---------------------------------------------------------------------.

Connection Diagrams

Dual-In-Llne Package

'-J

en
......

Plastic Leaded Chip Carrier (PLCC)
-

(X)
(X)

~Ic.:>

~ I
1 20 19

161-Vcc

'I 'I i

01- 2

lSI-a

02- 3

141-A4

02 -

181- A4

03- 4

131-A3

03- 5

17 I- A3

04- 5

121-A2

NC- 6

16 I- NC

05- 6

111-Al

04- 7

15 I- A2

06- 7

10l-AO

05- 8

GND- 8

91-07

00- 1

0
~
.....

141- AI

9 10 11 12 13
TL/D/9187-2

Top View

TLlD/9187-3

Top View

Order Number DM74S188J, 188AJ,
DM74S188N or 188AN
See NS Package Number J16A or N16A

Order Number DM74S188V or 188AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number

+ 70°C)

Max Access Time (ns)

DM74S188N

DM74S188J

DM74S188V

DM7 4S 188AN

DM74S188AJ

DM74S188AV

3-5

co
.,...

U)
~

.......

::E

Operating Conditions
Min

Max

Units

Supply Voltage (Vee>
Commercial

4.75

5.25

Ambient Temperature (TN
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage

0
0
2.0

+70
0.8
5.5

°C
V
V

(Note 3)

Parameter

DM74S188

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee = Max, VIN = 0.45V

IIH

Input Leakage Current

Vee = Max, VIN = 2.7V

/LA

Vee = Max, VIN = 5.5V

1.0

VOL

Low Level Output Voltage

VIL (Note 4)

Low Level Input Voltage

Vee = Min, 10L = 16 mA

0.35

/LA

0.45

0.80

/LA

100

/LA

-1.2

VIH (Note 4)

High Level Input Voltage

loz

Output Leakage Current
(Open-Collector Only)

Input Clamp Voltage

Vee = Min, liN = -18 mA

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Vo = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

2.0

Vee = Max, VeEx = 2.4V
Vee = Max, VeEx = 5.5V
-0.8

Vee = Max, Input Grounded
70
110
mA
All Outputs Open
Note 1: Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated
at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25'C.
Note 4: These are absolute voltages with respect to pin 8 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
Icc

Power Supply Current

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O°C to

+ 70°C)

JEDEC
Symbol

Parameter

TAA

TAVQV

TEA

TEVQV

TER

Symbol

DM74S188
Min

DM74S188A
Min

Max

Address Access Time

Enable Access Time

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

3-6

Typ

Units

Typ

Max

Functional Description
TEST ABILITY

TITANIUM·TUNGSTEN FUSES

The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-Chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.

3-7

co
co

~ ~National

:i
Q

Semiconductor

DM74S288 (32 X 8)
256-Bit TTL PROM
General Description

Features

PAOMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A4
A3

256-8tT ARRAY
32 x 8
MEMORY MATRIX

AZ
At
AO

00
TLlD/8360-1

Pin Names
AO-A4

Addresses

Enable

GND

Ground

00-07

Outputs

Vee

Power Supply

3-8

Connection Diagrams
Dual·ln·Llne Package

00- 1

Plastic Leaded Chip Carrier (PLCC)

yr 1

16 I-Vcc
151-(;

01- 2

rl(i

1 20 19
~A4

02- 3

141-A4

02- 4

03- 4

~A3

03- 5

171-A3

04- 5

~A2

NC- 6

lSi-NC

05- 6

lll-Al

Q4- 7

15i-A2

06- 7

10l-AO

05- 8

GND- 8

91-07

14i-Al
9 10 11 12 13

TL/D/8360-2

Top View

TL/D/8360-7

Top View

Order Number DM74S288J, 288AJ or
DM74S288N,288AN
See NS Package Number J16A or N16A

Order Number DM74S288V or 288AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O·C to
Parameter/Order Number

+ 70·C)

Max Access Time (ns)

DM74S288N

DM74S288J

DM74S288V

DM74S288AN

DM74S288AJ

DM74S288AV

II
I

3·9

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee)
Commercial

-0.5V to + 7.0V

Supply Voltage (Note 2)

Min

Max

Units

4.75

5.25

V
°C

Input Voltage (Note 2)

-1.2Vto +5.5V

Ambient Temperature (TA)
Commercial

+70

Output Voltage (Note 2)

-0.5Vto +5.5V

Logical "0" Input Voltage

0.8

- 65°C to + 150°C

Logical "1" Input Voltage

2.0

5.5

Storage Temperature
Lead Temperature (Soldering, 10 sec.)

300°C

ESD rating to be determined

DC Electrical Characteristics
Symbol

Parameter

(Note 3)
DM74S288

Conditions
Min

IlL

Input Load Current

IIH

Input Leakage Current

VOL

Low Level Output Voltage

VIL (Note 4)

Low Level Input Voltage

VIH (Note 4)

High Level Input Voltage

Vee = Max, VIN = 0.45V

Units

Typ

Max

-80

-250

p,A

Vee = Max, VIN = 2.7V

p,A

Vee = Max, VIN = 5.5V

1.0

0.45

0.35

Vee = Min, 10L = 16 mA

0.80
2.0

V
V

-0.8

-1.2

Input Clamp Voltage

Vee = Min, liN = -18 mA

Input Capacitance

Vee = 5.0, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Vo = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

Icc

Power Supply Current

los

Short Circuit
Output Current

Vee = Max, Input Grounded
All Outputs Open
Vo = OV, Vee = Max
(Note 5)

102

Output Leakage
(TRI-STATE)

Vee = Max, Vo = OA5V to 2AV
Chip Disabled

VOH

Output Voltage High

10H = -2.0mA

70
-20

110

-70

+50

p,A

-50

p,A
V

V
2.4
3.2
10H = -6.5 mA
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25'C.
Note 4: These are absolute voltages with respect to pin 8 on the device and include all overshoots due to system and/ or tester noise. Do not attempt to test these
values without suitable equipment.
Note 5: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

3-10

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMPERATURE RANGE (O°C to
Symbol

Parameter

......

.&:10
(J)

+ 70°C)

JEDEC
Symbol

DM74S288
Min

N
CD
CD

DM74S288A

Typ

Max

Min

Units

Typ

Max

TAA

Address Access Time

TAVQV

TEA

Enable Access Time

TEVQV

TER

Enable Recovery Time

TEXQX

TZX

Output Enable Time

TEVQX

TXZ

Output Disable Time

TEXQZ

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metalization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

3-11

"co

~ ~National

::e
~ Semiconductor
c

DM74S287
(256 X 4) 1024·Bit TTL PROM
General Description

Features

This Schottky memory is organized in the popular 256
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 30 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• > 2000V input protection for electrostatic discharge
• TRI-STATE® outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A7
A6
A5
A4
A3

1024-8IT ARRAY
32

Pin Names

x 32

MEMORY MATRIX

A2----f
AI -----I
AD - - - - - I

00
TL/D/B359-1

3-12

AO-A7

Addresses

G1,G2

Output Enables

GND

Ground

00-03

Outputs

Vee

Power Supply

Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)

Dual-In-Llne-Package

A6.!..~.!!VCC
AS

~ TIl

A41

.!!iIT

A3!
AD
AI

~
~
~

AZ 1
GND.!

00
01

02
03

l:3 r-.
<
I I

:z: >

1 20 19

(.)

M-4

18 -G2

A3- 5

17 -Gi

AO- 6

16 -ao

Al- 7

15 -NC

A2- 8

14 -al
9 10 11 12 13

TLlD/B359-2

Top View

(.)

I
0

(.)

..,

:z: (!)
:z: :z: 0

Order Number DM74S287J, 287AJ,
287N or 287 AN
See NS Package Number J16A or N16A

TLlD/B359- 7

Top View
Order Number DM74S287Vor 287AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number
DM74S2B7AJ

+ 70°C)

Max Access Time (ns)
30

DM74S2B7J

DM74S2B7AN

DM74S2B7N

DM74S2B7AV

DM74S2B7V

3-13

Operating Conditions
Supply Voltage (Vee)
Commercial
Ambient Temperature (TA)
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage

Min

Max

Units

4.75

5.25

70
0.8
5.5

°C
V
V

0
2.0

DC Electrical Characteristics (Note 3)
Symbol

Parameter

DM74S287

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee=Max, VIN=0.45V

IIH

Input Leakage Current

Vee = Max, VIN=2.7V

/-LA

Vee = Max, VIN=5.5V

1.0

VOL

Low Level Output Voltage

VIL (Note 4)

Low Level Input Voltage

0.35

Vee = Min, 10L = 16 mA

/-LA

0.45

0.80

-1.2

2.0

VIH (Note 4)

High Level Input Voltage

Input Clamp Voltage

Vee= Min, liN = -18 mA

Input Capacitance

Vee=5.0V, VIN=2.0V
TA =25°C, 1 MHz

4.0

Output Capacitance

Vee=5.0V, Vo=2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

Icc

Power Supply Current

Vee = Max, Inputs Grounded
All Outputs Open

los

Short Circui,t
Output Current

Vo=OV, Vee = Max
(Note 5)

loz

Output Leakage
(TAl-STATE)

Vee = Max, Vo=0.45Vt02.4V
Chip Disabled

Output Voltage High

10H= -2.0 mA

VOH

-0.8

-20

130

-70

+50

/-LA

-50

/-LA
V

2.4
3.2
V
10H= -6.5 mA
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = + 25'C.
Note 4: These are absolute voltages with respect to pin 8 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
Note 5: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

3-14

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O°C to

+ 70°C)
DM74S287A

DM74S287

Units

JEDEC Symbol

Parameter

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

ns
ns

Symbol

Min

Typ

Max

Min

Typ

Max

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

Functional Description
TESTABILITY

TITANIUM·TUNGSTEN FUSES

National's Programmable Read-Only Memories. (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY
As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.

3-15

a~National
Semiconductor
DM74S387
(256 X 4) 1024-Bit TTL PROM
General Description

Features

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 30 ns max
Enable access-20 ns max
Enable recovery-20 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A7

1024-81T ARRAY
32x32
MEMORY MATRIX

AS
A4

A3
A2----f
AI

AO---...,

Pin Names
AO-A7

Addresses

G1-G2

Output Enables

GND

Ground

00-03

Outputs

Vee

Power Supply

3-16

TL/O/91BB-l

Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)

Dual·ln·Llne Package
A6- 1

'-'

-Vee

III

~ '<"

1 20 19

A5- 2

15 -A7

M- 3

-Gi

M-4

A3- 4

-01

A3- 5

17 -

AO- 5

12 -00

AO- 6

16 -00

Al- 6

11-01

Al- 7

A2- 7

10 -02

A2- 8

14 -01

GHD- 8

-GZ

-He

9 10 11 12 13

~03

(,) c
Z

TLID/9188-2

(,) ", N

zoo

Top View

TLID/918B-3

Top View

Order Number DM74S387J, 387AJ,
DM74S387N,387AN
See NS Package Number J16A or N16A

Order Number DM74S387V, 387AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number
DM74S387AJ

+ 70°C)

Max Access Time (ns)
30

DM74S387J

DM74S387AN

DM74S387N

DM74S387AV

DM74S387V

3·17

Absolute Maximum Ratings

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required,

Min

Max

Units

4.75

5.25

0.8

°C
V

5.5

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee)
Commercial

Supply Voltage (Note 2)

Ambient Temperature (TA)
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage

2.0

-0.5Vto + 7.0V
-1.2Vto +5.5V

Input Voltage (Note 2)
Output Voltage (Note 2)

-0.5Vto +5.5V

Storage Temperature

- 65°C to + 150°C

Lead Temp. (Soldering, 10 seconds)
ESD

300°C
>2000V

DC Electrical Characteristics (Note 3)
Symbol

Parameter

DM74S387

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee

= Max, VIN = 0.45V

IIH

Input Leakage Current

Vee

= Max, VIN = 2.7V

J-tA

Vee

= Max, VIN = 5.5V

1.0

Vee

= Min, 10L = 16 mA

VOL

Low Level Output Voltage

VIL (Note 4)

Low Level Input Voltage

0.35

J-tA

0.45

0.80

J-tA

100

J-tA

-1.2

VIH (Note 4)

High Level Input Voltage

loz

Output Leakage Current
(Open-Collector Only)

Vee

= Max, VeEx = 2.4V

Vee

= Max, VeEx = 5.5V

Input Clamp Voltage

Vee

= Min, liN = -18 mA

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Va = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

2.0

-0.8

Vee = Max, Inputs Grounded
80
130
mA
All Outputs Open
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = + 25°C.
Note 4: These are absolute voltages with respect to pin B on the device and include all overshoots due to system and/ or tester noise. Do not attempt to test these
values without suitable equipment.
Ice

Power Supply Current

3-18

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O°C to
Symbol

Parameter

+ 70°C)
DM74S387

JEDEC Symbol
Min

TAA

DM74S387A

Typ

Max

Min

Units

Typ

Max

Address Access Time

TAVQV

TEA

Enable Access Time

TEVQV

TER

Enable Recovery Time

TEXQX

TZX

Output Enable Time

TEVQX

TXZ

Output Disable Time

TEXQZ

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

•
3-19

,...... r----------------------------------------------------------------------------------,

~ ~National
~

Semiconductor

DM74LS471
(256 X 8) 2048-Bit TTL PROM
General Description

Features

These Schottky memories are organized in the popular 256
words by 8 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-60 ns max
Enable access-30 ns max
Enable recovery-30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A7
A6
A5
AD
Al

2Q48.BIT ARRAY
32 x 64
MEMORY MATRIX

A2
A3
A4

TL/D/9190-1

Pin Names
AO-A?

Addresses

G1-G2

Output Enables

GND

Ground

OO-O?

Outputs

Vee

Power Supply

3-20

Connection Diagrams
Dual-In-Llne Package

AO- 1

\.J

Plastic Leaded Chip Carrier (PLCC)

r--

I i i I" i

-Vee

Al- 2

19 -A7

A2- 3

18 -A6

A3- 4

18 -A6

A3- 4

17 -AS

A4- 5

17 -AS

A4- 5

-cz

00- 6

-Gi

01- 7

15 -

01- 7

14 -07

02- 8

14 -07

02- 8

13 -06

03- 9

GND- 10

1 20 19

-cz
Gi

9 10 11 12 13

~05

11-04
TLlD/9190-3

Top View

TLlD/9190-2

Top View

Order Number DM74LS471V
See NS Package Number V20A

Order Number DM74LS471J or DM74LS471N
See NS Package Number J20A or N20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number

+ 70°C)

Max Access Time (ns)

DM74LS471N

DM74LS471J

DM74LS471V

•
3-21

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)
-0.5Vto +7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
-65°C to + 150°C
Storage Temperature
Lead Temp. (Soldering, 10 seconds)
300°C
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming ratings, refer to the
programming instructions.

DC Electrical Characteristics
Symbol

Parameter

Supply Voltage (Vee)
Commercial
Ambient Temperature (TA)
Commercial
Logical "0" Input Voltage
Logical "1 " Input Voltage

Min

Max

Units

4.75

5.25

0
0
2.0

+70
0.8
5.5

°C
V
V

(Note 1)
DM74LS471

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee = Max, VIN = 0.45V

IIH

Input Leakage Current

Vee = Max, VIN = 2.7V

fJ-A

Vee = Max, VIN = 5.5V

1.0

0.45

0.80

0.35

fJ-A

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

Input Clamp Voltage

Vee = Min, liN = -18 mA

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Va = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

lee

Power Supply Current

Vee = Max, Inputs Grounded
All Outputs Open

los

Short Circuit
Output Current

Va = OV, Vee = Max
(Note 2)

102

Output Leakage
(TRI-STATE)

Vee = Max, Va = 0.45V to 2.4V
Chip Disabled

Output Voltage High

10H = -2.0mA

VOH

Vee = Min, 10L = 16 mA

2.0
-0.8

-1.2

-20

100

-70

+50

fJ-A

-50

fJ-A
V

3.2
2.4
10H = - 6.5mA
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0v and TA =
Note 2: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

V
25'C.

AC Electrical Characteristics with Standard Load and Operating Conditions
Symbol

JEDEC Symbol

DM74LS471

Parameter
Min

Typ

Units
Max

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

3-22

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

•
3-23

~National

~ Semiconductor

DM74S472
(512 X 8) 4096-Bit TTL PROM
General Description

Features

This Schottky memory is organized in the popular 512
words by 8 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
AS
A7
A6
A5

409&BIT ARRAY
64x64
MEMORY MATRIX

AO
Al

Pin Names

DECODER

AZ----t
A3----t
A4----I

00
TLIO/9191-1

3-24

AO-A8

Addresses

Output Enable

GND

Ground

00-07

Outputs

Vee

Power Supply

Connection Diagrams
Dual-In-Llne Package

Plastic Leaded Chip Carrier (PLCC)

'-'

~:c~>8~

AO- 1
A1- 2

20 ~Vcc
19 ~A8

1 20 19

A2- 3

~A7

A3- 4

18 -A7

A3- 4

~A6

A4- 5

17 -A6

A4- 5

~A5

00- 6

16 -A5

QO- 6

15 ~G

01- 7

Q1- 7

~Q7

02- 8

14 -07

Q2- 8

~06

Q3- 9

~Q5

GND- 10

~04

-G

9 10 11 12 13
I I I I I
0
. . It') 10
a zt:) a a a

,.,

TLID/9191-3

Top View

TLID/9191-2

Top View

Order Number DM74S472V, 472AV, 472BV
See NS Package Number V20A

Order Number DM74S472J, 472AJ, 472BJ
DM74S472N, 472AN, 472BN
See NS Package Number J20A or N20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number
DM74S472AN

+ 70°C)

Max Access Time (ns)
45

DM74S472BN

DM74S472N

DM74S472AJ

DM74S472BJ

DM74S472J

DM74S472AV

DM74S472BV

DM74S472V

3-25

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Note 2)

-0.5V to + 7.0V

Input Voltage (Note 2)

-1.2Vto +5.5V
- 0.5V to + 5.5V

Output Voltage (Note 2)
Storage Temperature

Supply Voltage (Vee)
Commercial

-65°C to + 150°C

Lead Temp. (Soldering, 10 seconds)

Min

Max

Units

4.75

5.25

Ambient Temperature (TA)
Commercial

+70

°C

Logical "0" Input Voltage

0.8

Logical "1" Input Voltage

2.0

5.5

300°C

ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.

DC Electrical Characteristics
Symbol

Parameter

(Note 1)
DM74S472

Conditions
Min

Units

Typ

Max

-80

-250

/J-A

IlL

Input Load Current

Vee = Max, VIN = 0.45V

IIH

Input Leakage Current

Vee = Max, VIN = 2.7V

VOL

Low Level Output Voltage

Vee = Min,lOL = 16 mA

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

Input Clamp Voltage

Vee = Min, liN = -18 mA

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Vo = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

lee

Power Supply Current

Vee = Max, Input Grounded
All Outputs Open

110

los

Short Circuit
Output Current

Vo = OV, Vee = Max
(Note 2)

loz

Output Leakage
(TRI-STATE)

Vee = Max, Vo = 0.45V to 2.4V
Chip Disabled

Output Voltage High

10H = -2.0 rnA

10H = - 6.5 rnA
2.4
3.2
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25'C.
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

Vee = Max, VIN = 5.5V

VOH

0.35

1.0

0.45

0.80

2.0

3-26

V
-0.8

-20

-1.2

155

rnA

-70

rnA

+50

/J-A

-50

/J-A

3:
......

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O°C to

en
~

+ 70°C)

......
N

Symbol

JEDEC
Symbol

Parameter

Typ

Max

Typ

Max

Typ

Max

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

DM74S472
Min

DM74S472A
Min

DM74S472B
Min

Units

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard·ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally desig,ned to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

3-27

C")

I'-

;

~National

!:ic ~ Semiconductor
DM74S473
(512 X 8) 4096-Bit TTL PROM
General Description

Features

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-45 ns max
Enable access-30 ns max
Enable recovery-30 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open-collector outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A8
A7
A6
A5

409&81T ARRAY

64x64
MEMORY MATR1X

AD
A1
A2----I
A3----I
A4"'-------I

00
TLlD/9715-1

Pin Names

AO-A8

Addresses

Output Enable

GND

Ground

00-07

Outputs

Vee

Power Supply

3-28

Connection Diagrams
Dual-In-Llne Package
AO- 1

\.J

Plastic Leaded Chip Carrier (PLCC)

Al- 2

20 ~Vcc
19 p-A8

A2- 3

A3- 4

17 -A6

A3- 4

A4- 5

16 -A5

A4-5

17 I- A6

00- 6

16 I- A5

01- 7

14 1-07

01- 7

15 I- G

13 -06

02- 8

~A7

I-G

03- 9

12 -05

GND- 10

11 -04

1 20 19
~A7

~07

9 10 11 12 13

lz o! o! !
(!)

TLlD/9715-3

TL/D/9715-2

Top View

Order Number DM74S473J, 473AJ,
DM74S473N or 473AN
See NS Package Number J20A or N20A

Order Number DM74S473Vor473AV
See NS Package Number V20A

Ordering Ir:"formatiori
Commercial Temp. Range (DOC to
Parameter/Order Number

+ 70·C)

Max Access Time (ns)

DM74S473AN
DM74S473N

DM74S473AJ

DM74S473J

DM74S473AV

DM74S473V

•
3-29

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)

-0.5V to + 7.0V

Input Voltage (Note 2)

-1.2Vto +5.5V

Output Voltage (Note 2)

- 0.5V to + 5.5V

Storage Temperature

Supply Voltage (Ved
Commercial

-65·C to + 150·C

Min

Max

Units

4.75

5.25

Ambient Temperature (TA)
Commercial

+70

·C

Logical "0" Input Voltage
Logical "1" Input Voltage

0
2.0

0.8
5.5

V
V

300·C

Lead Temp. (Soldering, 10 seconds)
ESD to be determined

Note 1: Absolute maximum ratings are those values beyond which the de·
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.

DC Electrical Characteristics (Note 1)
Symbol

Parameter

DM74S473

Conditions
Min

IlL

Input Load Current

Vee

= Max, VIN = 0.45V

IIH

Input Leakage Current

Vee

=
=
=

Vee

Max, VIN
Max, VIN

= 2.7V
= 5.5V
= 16 rnA

Units

Typ

Max

-80

-250

p,A

1.0

0.45

0.80

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

loz

Output Leakage Current
(Open-Collector Only)

Vee

= Max, VeEx = 2.4V

p,A

Vee

100

p,A

Input Clamp Voltage

Vee

=
=

-1.2

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Vo = 2.0V
TA = 25·C, 1 MHz, Outputs Off

6.0

lee

Power Supply Current

Vee = Max, Input Grounded
All Outputs Open

110

Vee

Min,lOL

0.35

2.0

Max, VeEX
Min,IIN

5.5V

= -18 rnA

Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for

3-30

-0.8

Vce = 5.0V and TA = 25°C.

155

c
AC Electrical Characteristics
COMMERCIAL TEMP. RANGE (O°C to

.......

with Standard Load and Operating Conditions

0l:Io

en
0l:Io

+ 70°C)

.......
DM74S473

Symbol

JEDEC
Symbol

Parameter

Typ

Max

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

Min

DM74S473A
Min

Typ

Units
Max

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also per·
manently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column·select circuits and functionality of input and enable gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and parametric testing at every stage of the test flow.

National's Programmable Read-Only Memories (PROMs)
feature titanuim-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERIP (Jpackage). Device performance in all package configurations
is excellent.

3-31

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

r--

~ ~National
~

Semiconductor

DM74S570
(512 X 4) 2048-Bit TTL PROM
General Descriptio:n

Features

This Schottky memory is organized in the popular 512
words by 4 bits configuration. A memory enable input Is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access down to-45 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETMprogramming
• Open-collector outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
AS
A7
A6
A5
A4
A3

204&81T ARRAY

Pin Names

84x3Z

MEMORY MATRIX

AO-AS

Enable

GND

Ground

00-03

Outputs

Vee

Power Supply

A2 _ _--I
Al----I

-----LI!IIII!_}-iIIllU_~

00
TL/D/9189-1

3-32

Addresses

Connection Diagrams
Plastic Leaded Chip Carrier (PLCC)

Dual-In-Llne Package

It)

r--

i i i I" i

16 ~VCC

A6- 1
A5- 2

~A7

A4- 3

~A8

A3- 4

13 ~G

AO- 5

~OO

AO- 6

Al- 6

11~01

Al- 7

15 -NC

A2- 7

~02

A2- 8

GND- 8

~03

1 20 19

A4-4

18 -A8

A3- 5

17 ~G
~OO

14 ... 01
9 10 11 12 13

TL/D/91B9-2

Top View

TLlD/91B9-3

Top View

Order Number DM74S570J, 570AJ
DM74S570N,570AN
See NS Package Number J16A or N16A

Order Number DM74S570V, 570AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O°C to
Parameter/Order Number

+ 70°C)

Max Access Time (ns)

OM? 4S5?OAN

OM? 4S5?ON

OM? 4S5?OAJ

OM? 4S5?OJ

OM? 4S5?OAV

OM74S5?OV

3-33

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Min

Max

Units

4.75

5.25

-1.2Vto +5.5V

Ambient Temperature (TA)
Commercial

+70

·C

- 0.5V to + 5.5V

Logical "0" Input Voltage

0.8

- 65·C to + 150·C

Logical "1" Input Voltage

2.0

5.5

Supply Voltage (Note 2)

-0.5V to + 7.0V

Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature

Supply Voltage (Vee>
Commercial

Lead Temp. (Soldering, 10 seconds)

300·C

ESD to be determined
Note 1: Absolute Maximum Ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings. refer to the programming instructions.

DC Electrical Characteristics (Note 1)
Symbol

Parameter

DM74S570

Conditions
Min

IlL

Input Load Current

IIH

Input Leakage Current

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

loz

Output Leakage Current
(Open-Collector Only)

Input Clamp Voltage

Input Capacitance

Output Capacitance

lee

Power Supply Current

=
=
Vee =
Vee =

= 0.45V
= 2.7V
Max, VIN = 5.5V
Min, 10L = 16 rnA

Vee

Max, VIN

Vee

Max, VIN

Units

Typ

Max

-80

-250

0.35

p.A

1.0

rnA

0.45

0.80

p.A

100

p.A

-1.2

2.0

= Max, VeEx = 2.4V
Vee = Max, VeEx = 5.5V
Vee = Min, liN = -18 rnA
Vee = 5.0V, VIN = 2.0V
TA = 25·C, 1 MHz
Vee = 5.0V, Vo = 2.0V
TA = 25·C, 1 MHz, Outputs Off
Vee = Max, Input Grounded
Vee

-0.8
4.0

6.0

pF
130

All Outputs Open
Note 1: These limits apply over the entire operating range unless otherwise noted. All typical values are for Vee

p.A

rnA

= 5.0V and TA = 25°C.

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O·C to + 70·C)
Symbol

JEDEC Symbol

DM74S570

Parameter
Min

Typ

DM74S570A
Max

Min

Typ

Units
Max

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

3-34

Functional Description
TESTABILITY

TITANIUM·TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy 8
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.

•
3-35

.....
......

~ ~National

Semiconductor

DM74S571
(512 X 4) 2048-Bit TTL PROM
General Description

Features

This Schottky memory is organized in the popular 512
words by 4 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

• Low voltage TRI-SAFETM programming
• TRI-STATE® outputs

Block Diagram
Pin Names

A8
A7
2048-81T ARRAY
64 x 32
MEMORY MATRIX

A6
A5
A4
A3

AO-AS

Address

Output Enable

GND

Ground

A2 _ _ _-/

00-03

Outputs

AI----f
AO----t

Vee

Power Supply

00
TlID/9713-1

3-36

~------------------------------------------------------------------------.

c
3:

Connection Diagrams

.......
~

Dual-ln-L1ne Package

.......

Plastic Leaded Chip Carrier (PLCC)

A6- 1

'--'

16 ~Vcc

A5- 2

15 '.-A7

M- 3

14 ~A8

A4- 4

A3- 4

13 ~G

A3-5

17~G

AO- 5

12~QO

AO- 6

16 ~QO

Al- 6

II~Ql

Al- 7

15 ~NC

A2- 7

10 '.-Q2

A2-8

141-Ql

GND- 8

9 '.-Q3

1 20 19
18 ~A8

9 10 11 12 13
TLID/9713-2

Top View

TLIO/9713-3

Top View

Order Number
DM74S571J, 571AJ, 571BJ
DM74S571N, 571AN, 571BN
See NS Package Number J16A or N16A

Order Number
DM74S571V, 571AV, 571BV
See NS Package Number V20A

Ordering Information
Commercial Temperature Range (O·C to
Parameter/Order Number

+ 70·C)

Max Access Time (ns)

DM74S571AN

DM74S571BN

DM74S571N

DM74S571AJ

DM74S571BJ

DM74S571J

DM74S571AV

DM74S571BV

DM74S571V

3-37

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,

Operating Conditions

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage {Vee>
Commercial

Supply Voltage (Note 2)
-0.5V to + 7.0V
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
- 0.5V to + 5.5V
Storage Temperature
- 65°C to + 150°C
Lead Temp. (Soldering 10 sec.)
300°C
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.

Ambient Temperature (TAl
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage

Min

Max

Units

4.75

5.25

+70
0.8
5.5

°C
V
V

0
2.0

DC Electrical Characteristics (Note 1)
Symbol

Parameter

DM74S571

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee

= Max, VIN = 0.45V

IIH

Input Leakage Current

Vee

= Max, VIN = 2.7V

fJ-A

Vee

= Max, VIN = 5.5V

1.0

rnA

Vee

= Min,lOL = 16 rnA

0.45

0.80

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

0.35

fJ-A

VIH

High Level Input Voltage

Input Clamp Voltage

Vee

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Va = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

Icc

Power Supply Current

Vee = Max, Input Grounded
All Outputs Open

los

Short Circuit
Output Current

Va = OV, Vee
(Note 2)

loz

Output Leakage
(TAl-STATE)

Vee = Max, Va
Chip Disabled

Output Voltage High

IOH

VOH

2.0

= Min, liN = -18 rnA

= Max

-0.8

-1.2

-20

= 0.45V to 2.4V

= -2.0 rnA

2.4
3.2
IOH = -6.5 rnA
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA =
Note 2: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

3-38

130

rnA

-70

rnA

+50

fJ-A

-50

fJ-A
V
V

25'C.

AC Electrical Characteristics
COMMERCIAL TEMP RANGE (O°C to

.......
,&:10

DM74S571A

JEDEC
Symbol

Parameter

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

Symbol

en
U1
.......
.....

+ 70°C)
DM74S571
Min

Typ

Max

Min

Typ

DM74S571B

Max

Min

Unit

Typ

Max

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program effiCiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is deSigned to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The. Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

3-39

C\I
I""-

~ ~National

55
~ Semiconductor
c
DM74S572
(1024 x 4) 4096-Bit TTL PROM
General Description

Features

This Schottky memory is organized in the popular 1024
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-45 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• Open collector outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram
A9
AS
A7
AS
A5
A4

4006-BIT ARRAY

64x64

MEMORY MATRIX

Pin Names

A3------~~~~~~r_-,~--,

A2----I
AI-----I
AO------~~~~~r-~~~~~

AO-A9

Addresses

m,IT2

Output Enables

GND

Ground

00-03

Outputs'

Vee
03

00
TLlD/9712-1

3-40

Power Supply

Connection Diagrams
Dual-In-Llne-Package

A6- 1

Plastic Leaded Chip Carrier (PLCC)
~

'-"

I i

8,....

A5- 2

lB -Vee
17 I-A7

A4- 3

16 I-AB

A4- 4

lB I-AB

A3- 4

15 I-A9

A3- 5

171-A9
16 -00

I
3 2

1 20 19

AO- 5

14 1-00

AO- 6

Al- 6

131-01

Al- 7

15 -Ne

A2- 7

12 1-02

A2- B

14 !-"01

Gi- B

111-03
101-(;2

GND- 9

9 10 11 12 13

TL/D/9712-2

TL/D/9712-3

Top View

Order Number DM74S572J, 572AJ,
DM74S572N,572AN
See NS Package Number J 18A or N 18A

Order Number DM74S572V, 572AV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (OOC to
Parameter/Order Number
OM74S572AJ

+ 70·C)

Max Access Time (n8)
45

. OM74S572J

OM74S572AN

OM74S572N

OM74S572AV

OM74S572V

3-41

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Note 2)

-0.5 to + 7.0V
-1.2Vto +5.5V

Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature

Min
4.75
0
0
2.0

Supply Voltage (Ved
Ambient Temperature (TA)
Logical "0" Input Voltage
Logic "1" Input Voltage

Max
5.25
+70
0.8
5.5

Units
V
°C
V
V

- 0.5V to + 5.5V
-65°C to + 150°C

Lead Temp. (Soldering, 10 sec.)

300°C

ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.

DC Electrical Characteristics (Note 1)
Symbol

Parameter

DM74S572

Conditions
Min

Units

Typ

Max

-80

-250

IlL

Input Load Current

Vee

Max, VIN

0.45V-250

IIH

Input Leakage Current

Vee

Max, VIN

2.7V

fJ-A

Vee

Max, VIN

5.5V

1.0

Vee

Min, 10L

0.45

0.80

fJ-A

VOL

Low Level Output Voltage

0.35

16 mA

fJ-A

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

102

Output Leakage Current

Vee

Max, VeEX

(Open-Collector Only)

Vee

=
=

Max, VeEX == 5.5V

100

fJ-A

-1.2

2.0

2.4V

Input Clamp Voltage

Vee

Input Capacitance

Vee = 5.0V, VIN = 2.0V
TA = 25°C, 1 MHz

4.0

Output Capacitance

Vee = 5.0V, Va = 2.0V·
T A = 25°C, 1 MHz, Outputs Off

6.0

Ice

Power Supply Current

Vee = Max, Input Grounded
All Outputs Open

100

Min, liN

-18 mA

Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for

3-42

-0.8

140

Vce = 5.0V and TA = + 25°C.

AC Electrical Characteristics

(With Standard Load and Operating Conditions)
DM74S572A

Symbol

JEDEC Symbol

Parameter

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

Min

Typ

Max

Units

Functional Description
TESTABILITY

TITANIUM-TUNGSTEN FUSES

National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to program efficiently with only 10.5V applied. The high performance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titaniumtungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire operating ranges of Vee and temperature.

RELIABILITY

As with all National products, the Ti-W PROMs are subjected to an on-going reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples. in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configurations is excellent.

3-43

~ .---------------------------------------------------------------------------------~

to-

~ ~National
D Semiconductor
c

DM74S573
(1024 X 4) 4096-Bit TTL PROM
General Description

Features

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-down to 35 ns max
Enable access-25 ns max
Enable recovery-25 ns max
• PNP inputs for reduced input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
• TRI-STA TE® Outputs

PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location
by following the programming instructions.

Block Diagram

A9
A8
A7
A6
A5
A4

4m6-81T ARRAY
64x64
MEMORY MATRIX

Pin Names

A3-------r~~~--~r_~~--,

A2----f
Al----~

AO-------L~J-~~~~~~~

00
TLlD/9193-1

3-44

AO-A9

Addresses

G1-G2

Output Enables

GND

Ground

00-03

Outputs

Vee

Power Supply

s:
......

Connection Diagrams

.1:10

CJ)

Plastic Leaded Chip Carrier (PLCC)

Dual-In-Llne Package
A6- 1

18 f-Vcc

A5- 2

17 f-A7

A4- 3

16 f-A8

A4 -

A3- 4

15 f-A9

A3 -

17 - A9

AO- 5

14 f-OO

AO -

16 - 00

A1- 6

131-01

Al -

15 - He

A2- 7

121-02

A2- 8

14 -01

......
(,,)

G1- 8

111-03

GHD- 9

101-(;2

1 20 19

10 11 12 13

TTl
Ie>

t- A8

~ I~

I
~
TLID/9193-3

TLID/9193-2

Top View

Order Number
DM74S573J, 573AJ, 573BJ
DM74S573N, 573AN, 573BN
See NS Package Number J18A or N18A

Order Number
DM74S573V, 573AV, 573BV
See NS Package Number V20A

Ordering Information
Commercial Temp Range (O·C to
Parameter/Order Number

+ 70·C)

Max Access Time (ns)

DM74S573AJ

DM74S573BJ

DM74S573J

DM74S573AN

DM74S573BN

DM74S573N

DM74S573AV

DM74S573BV

DM74S573V

3-45

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Note 2)
Input Voltage (Note 2)
-1.2Vto +5.5V
Output Voltage (Note 2)
-0.5Vto +5.5V
Storage Temperature
- 65°C to + 150°C
Lead Temp. (Soldering, 10 seconds)
300°C
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics
Symbol

Operating Conditions
Supply Voltage (Vee>
Commercial
Ambient Temperature (TA)
Commercial
Logical "0" Input Voltage
Logical "1" Input Voltage

I'H

Input Leakage Current

Units

4.75

5.25

0
0
2.0

+70
0.8
5.5

°C
V
V

DM74S573

Conditions
Min

Input Load Current

Max

(Note 1)

Parameter

I,L

Min

= Max, Y,N = 0.45V
Vee = Max, Y,N = 2.7V

Vee

= Max, Y,N = 5.5V
Vee = Min, 10L = 16 mA

Units

Typ

Max

-80

-250

Vee

VOL

Low Level Output Voltage

V,L

Low Level Input Voltage

V,H

High Level Input Voltage

Input Clamp Voltage

Input Capacitance

Output Capacitance

Icc

0.35

p.A

1.0

0.45

0.80

V
V

2.0

= Min, liN = -18 mA
Vee = 5.0V, Y,N = 2.0V
TA = 25°C, 1 MHz

-1.2

-0.8

Vee

p.A

4.0

Vee = 5.0V, Vo = 2.0V
TA = 25°C, 1 MHz, Outputs Off

6.0

Power Supply Current

Vee = Max, Input Grounded
All Outputs Open

100

los

Short Circuit
Output Current

Vo = OV, Vee
(Note 2)

loz

Output Leakage
(TRI-STATE)

Vee = Max, Vo
Chip Disabled

Output Voltage High

10H

VOH

= Max

-20

= 0.45Vt02.4V

= -2.0mA

2.4
3.2
10H = - 6.5mA
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA =
Note 2: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

3-46

140

-70

+50

p.A

-50

IJ-A
V
V

25°C.

AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (O°C to
Symbol

+ 70°C)

JEDEC
Symbol

Parameter

DM74S573
Min

Typ

DM74S573A
Max

Min

DM74S573B

Typ

Max

Min

Units

Typ

Max

TAA

TAVQV

Address Access Time

TEA

TEVQV

Enable Access Time

TER

TEXQX

Enable Recovery Time

TZX

TEVQX

Output Enable Time

TXZ

TEXQZ

Output Disable Time

Functional Description
TESTABILITY

TITANIUM·TUNGSTEN FUSES

3-47

0o
..J

e:. ~National
fCD

...m

Semiconductor

"i:

Bipolar PROM Devices in Plastic
:c Leaded Chip Carriers (PLCC)
o

"C
CD

m
CD

..J
(.)

~
m

.E
o
CD

(.)

"S:
CD

c
:::E
o
a:

...

Introduction of Surface Mount
Technology
Recent years have seen rapid advances in microcircuit
technology. The integrated circuits of the 1980's are more
complex than the circuit boards of the 1960's. It is evident
that the next decade will bring demands for packages with
higher lead counts and closer lead spacing, both to support
the greater system density sought by designers.
National Semiconductor Corporation is committed to surface mount devices, for they provide the most practical solution to these needs. Geared to development of high-complexity semiconductor chips National has placed great emphasis on package development and introducing plastiC
leaded chip carriers with various number of leads as surface
mounted components.

'0
Features of Surface Mount Devices
Q.

Products in PLCC
National Semiconductor has a broad Family of high performance PROMs. All the PAL® and PROM products presently offered in DIP packages will now be available in the
PLCC (plastic leaded chip carrier) package including the
15 ns industries fastest PAL.

Advantages of PLCC
1. Permits automated assembly.
2. Lower manufacturing costs.
3. Smaller PLCC size, reduces board density and weight.
4. Lower noise and improved frequency response resulting
from shorter circuit paths. Automated assembly ensures
accurate component placement which improves reliability and provides more consistent product quality.

Additional Information

Surface mount devices have additional features compared
to molded Dual-In-Line Packages (DIP):

National Semiconductor offers a variety of technical briefs
covering surface mount topics. These include:

1. Compact design that saves space during assembly.

STARTM Tape-and-Reel Shipping System
Order Number 113635
Getting Started in Surface Mount (Equipment Suppliers)
Order Number 570435

2. Mounting on both sides of the substrate.
3. Easier handling and excellent reliability.
4. Automation of the assembly process.
5. Lower board manufacturing costs.
6. Improved operating speed.
7. Increased board density and reduced weight.

Applications
Surface mount devices can be used where substrate size,
as well as weight and thickness are limited. The surface
mount device can also be used in areas where conventional
packages cannot be used. Areas of application include; portable video cassette recorders, video cameras, hand-held
computers, personal computers, electronic toys, car electronics, cameras, telephones, and various telecommunication equipment.

A Basic Guide to Surface Mounting of Electronic
Components
Order Number 113615
Reliability Report: Small Outline Packages
Order Number 570430
Reliability Report: Plastic Chip Carrier
Order Number 980040
Plastic Chip Carrier Technology
Order Number 113295

3-48

PROM
Serles-20 Selection Chart

Device

Size
(Bits)

T AA (max) In ns
Configuration

ICC
max
InmA

DIP
pins

STD

A-Series

DM74S1880C
DM74S288TS

256

110

DM74S287TS
DM74S3870C

256

130

DM74S5700C
DM74S571 TS

512

55
55

45
45

130

DM74LS471 TS

256

100

60
60

45
45

140
140

18
18

60
55

45
45

155
155

20
20

DIP
pins

DM74S5720C
DM74S573TS

1,024

DM74S472TS
DM74S4730C

512

B-Serles

35
35

PLCC
pins

512X8 74S472,HS473

Serles-24 Selection Chart

Device

DM74S474 TS
DM74S4750C

Size
(Bits)

STD

A-Series

B-Series

ICC
max
InmA

170

T AA (max) In ns

Configuration

512

PLCC
pins

II
I

3-49

0'
o....I

Plastic Leaded Chip Carrier

D..

...
ca

512X8

745474,745475

/~~ ~ llJ~ ~v~ ~ ~'_~Jo.~
~~-'r--,\
"

/ / / ( lTI

:c
o

......-1---4 A"

t-..--f----I

CD
....I

:;::
tn

IiJ 111

~: G1 A, 0

m
Aorn

[]B G3
[ill G4

28 PIN PKG

I---+---f-C=
t-+--t

A10

~: G2 G1 G1

A2W
Al

(,)

G2 A, 1
G3

NC J--+-.-J

c::

......-1---4 NC

......-1---4 00

(,)

~~~~~~~!!n~~/
~D'
~

'S:

~. ~ ~-I--J

[3 Os I---+--'
D,GNDNe

D. D5

oc::

...ca

D..

TL/D/9261-6

'0
c.

Bipolar PROM Pinout

Programming Support

Programming Equipment

PROM devices may be programmed with hardware and
software readily available in the market. Most programmer
manufacturers will offer a PLCC adapter which will fit in existing equipment. For the availability of PLCC adapter
please check with your programmer manufacturer.

1.
2.
3.
4.
5.
6.
7.

3-50

Data 1/0
Structured Design
Stag
Dig Elec
Kontron
Prolog
Citel

Non-Registered PROM Programming Procedure

z
o

::J

:i:J
CD

cc
iii'

-...
CD
CD
Co

National Schottky PROMs are shipped from the factory with
all fuses intact. As a result, the outputs will be low (logical
"0") for all addresses. To generate high (logical "1 ") levels
at the outputs, the device must be programmed. Information
regarding commercially available programming equipment
may be obtained from National. If it is desired to build your
own programmer, the following conditions must be observed:

d) Enable the device by taking the chip enable(s) to a low
level. This is done with a pulse of 10 p,s. The 10 p,s
duration refers to the time that the circuit (device) is
enabled. Normal input levels are used and rise and fall
times are not critical.
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then
reducing Vee to 4.0V (±0.2V) for one verification and
to 6.0V (± 0.2V) for a second verification. Verification
at Vee levels of 4.0V and 6.0V will guarantee proper
output states over the Vee and temperature range of
the programmed part. The device must be Enabled to
sense the state of the outputs. During verification, the
loading of the output must be within specified IOL and
IOH limits. Steps b, c, and d must be repeated up to 10
times or until verification that the bit has been programmed.
f) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected bit.

1. Programming should be attempted only at ambient temperatures between 15°C and 30°C.
2. Address and Enable inputs must be driven with TTL logic
levels during programming and verification.
3. Programming will occur at the selected address when
Vee is at 10.5V, and at the selected bit location when the
output pin, representing that bit, is at 10.5V, and the device is subsequently enabled. To achieve these conditions in the appropriate sequence, the following procedure must be followed:
a) Select the desired word by applying high or low levels
to the appropriate address inputs. Disable the device
by applying a high level to one or more "active low"
chip enable inputs.

g) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed
on an automatic programmer, the duty cycle of Vee at
the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device
junction temperatures. After all selected bits are programmed, the entire contents of the memory should be
verified.

b) Increase Vee from nominal to 10.5V (±0.5V) with a
slew rate between 1.0 and 10.0 V / p,s. Since Vee is the
source of the current required to program the fuse as
well as the lee for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0V.
c) Select the output where a logical high is desired by
raising that output voltage to 10.5V (± 0.5V). Limit the
slew rate from 1.0 to 10.0 V / p,s. This voltage change
may occur simultaneously with the increase in Vee, but
must not precede it. It is critical that only one output at
a time be programmed since the internal circuits can
only supply programming current to one bit at a time.
Outputs not being programmed must be left open or
connected to a high impedance source of 20 kO minimum. (Remember that the outputs of the device are
disabled at this time).

Note: Since only an enabled device is programmed, it is possible to program
these parts at the board level if all programming parameters are com·
plied with.

3-51

"tJ

::D

a
..."tJ==
o

...

cc
D)

3
5"

...

"tJ

o
n

CD
Co
C
CD

...

CI)
~

:::J

'C
CI)

Programming Parameters Do not test or you may program the device

c..

c:n

Symbol

Parameters

Conditions

Min

Recommended
Value

Max

10.0

10.5

11.0

750

rnA

11.0

rnA

10.0

V/p,s

p,s

Units

Vccp

Required Vcc for Programming

Iccp

Icc during Programming

Vop

Required Output Voltage
for Programming

lop

Output Current while
Programming

IRR

Rate of Voltage Change of
Vcc or Output

1.0

PWE

Programming Pulse Width
(Enabled)

"c;,

VCCVH

Required High Vcc for Verification

5.8

6.0

6.2

a:
C

VCCVL

Required Low VCC for Verification

3.8

4.0

4.2

MDC

Maximum Duty Cycle for

"eE
ra

c:n
0~

c..
:!l
0

a:
c..

CI)

Vcc = 11V
10.5

10.0
Vour=11V

VccatVccp

Programming Waveforms

Non-Registered PROM

Tl = 100 ns Min.
T2

"'S Min. T2 may be > a if
Vccp rises at the same rate or
faster than (Vop)

= 5

IH
V
VIL

ADDRESS
INPUTS

Ts = 100 ns Min.
PWE is repeated for 5 additional
pulses after verification of VOH indicates a bit has been programmed.

SELECTED ADDRESS STABLE

T1r-

x::

Veep--~----.,

T3 = 100 ns Min.
T4 = 100 ns Min.

Vee S.DV
Veev

'""""'l
-I

~OH ;lliWW~~ ~::I?:ZZZZZZZ<

PROGRA~~ED

OUTPUT

OL
V
IH 1////
VIL '-'-"

ENABLE

-..j

I- I

PWE-l

I- T4

OUTPUT
VERIFY

I-

WAVEFOR~ FOR AN ACTIVE LOW ENABLE.
SO~E PRO~S HAVE ~ORE THAN ONE CHIP ENABLE.

NOTE: ENABLE

HOLD ALL OTHER ENABLE(S) TO ACTIVE STATE(S).
TLIOO/2S06-1

Standard Test Loads
Non-Registered PROMs
Vec

....

OUTPUT 0_-........4j~- TO- TEST POINT
R2:

..L

·~=30PF

__-GRD
TLIOO/2S06-3

3-52

Switching Time Waveforms
3.0V

ADDRESS

7777V
LLLU\

"Device input waveform characteristics are;
Repetition rate = 1 MHz
Source impedance = son
Rise and Fall times = 2.5 ns max.
(1.0 to 2.0 volt levels)

VALID

1== =1
TAA

fJ7777'V----~}_

OUTPUT

ENABLE

TZX iJ~
TEA-J

"TAA is measured with stable enable inputs.

t::TXZ::::J
TER-l

"TEA and TER are measured from the 1.5 volt level on inputs and outputs
with all address and enable inputs stable at applicable levels.

30V---'"\ .. - - - - - - - - - .. ~--...;...-

·ov _____ _ ..X

X.. _______ .

"For IOL = 16 rnA, Rl
"for IOL = 12 rnA, Rl

TL/00/2506-4

= 3000. and R2 = 6000.
= 4000. and R2 = BOOn.

""C" includes scope and jig capaCitance.

Approved Programmers for NSC PROMs
Manufacturer
DATA lID
PRO-LOG
KONTRON
STAG
AIM
DIGELEC
STARPLEXTM

System #

5/17/19/29A
M910,M980
MPP80S
PPX
RP400
UP803

Quality Enhancement Programs For Bipolar Memory
A+ PROGRAM*
Test
D.C Parametric
and Functionality

B+ PROGRAM

Condition

Guaranteed
LOTAQL5

25°C

0.05

Each
Temperature
Extreme

D.C Parametric
and Functionality

0.05

25°C

0.4

Mechanical

Critical

0.01

Major

0.28

Seal Tests
Hermetic

Fine Leak
(5 x 10- 8)

0.4

Gross

0.4

A.C. Parametric

Test

A.C Parametric

"Includes 160 hours of burn-in at 125'C.

3-53

Condition

Guaranteed
LOTAQL5

25°C

0.05

Each
Temperature
Extreme

0.05

25°C

0.4

Mechanical

Critical

0.01

Major

0.28

Seal Tests
Hermetic

Fine Leak
(5x 10- 8 )

0.4

Gross

0.4

Section 4
Application Notes

III

Section 4 Contents
AB-15 Protecting Data in Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-18 Electronic Compass Calibration Made Easy with EEPROMs . . . . . . . . . . . . . . . . . . . . . . . .
AN-338 Designing with the NM93C06 A Versatile Simple to Use EEPROM ... . . . . . . . . . . . . . .
AN-423 The NM93C46-An Amazing Device...........................................
AN-507 Using the NM93CSXX Family of Electrically Erasable Programmable Memory. . . . . . .
AN-716 Using the NM93CS EEPROM Family Features.......................... ........
AN-731 Using National's NMC87C257 256K EPROM with On-Chip Latches........ ........
AN-735 Understanding National's NM95C12 EEPROM with Programmable Switches........
AN-755 NM95C12 Flexibility in Industrial Control Applications. . . . . . . . . .. . . . . . . . . . . . . . . . . .
AN-756 Using the NM95C12 to Solve Common Manufacturing Problems..................
AN-758 Using National's MICROWIRE EEPROM.......................................
AN-765 Using the NM95C12 CMOS EEPROM with Programmable Switches for Analog
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-766 Using the NM95C12 in a Stand Alone Metering Device...........................
AN-767 NM95C12 Memory Mapping Solution for PC® Applications .......................
AN-789 Integrated Manufacturing Control-NM95C12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-790 NM95C12 EEPROM Controls Amplifier Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-791 Stand Alone Control of MICROWIRE Peripherals Using the NMC87C257 ...........
AN-792 NM95C12 Applications in a PC-AT Ethernet Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-794 Using an EEPROM-12C Interface NM24C02/03/04/05/08/09/16/17 ..............

4-2

4-3
4-5
4-6
4-12
4-15
4-29
4-31
4-33
4-39
4-50
4-62
4-73
4-80
4-89
4-93
4-96
4-102
4-123
4-127

>
m
.....

Protecting Data in Serial
EEPROMs

National Semiconductor
Application Brief 15
Paul Lubeck

National offers a broad line of serial interface EEPROMs
which share a common set of features:

ing or Writing it is necessary to place the device in the Program Enable Modet. Following placing the device in the
Program Enable Mode, Erase and Write will remain enabled
until either executing the Disable instruction or removing
Vee. Having Vee unexpectedly removed often results in
uncontrolled interface signals which could result in the
EEPROM interpreting a programming instruction causing
data to be destroyed.

• Low cost
• Single supply in all modes (+5V ± 10%)
• TTL compatible interface
• MICROWIRETM compatible interface
• Read-Only mode or read-write mode
This Application Brief will address protecting data in any of
National's Serial Interface EEPROMs by using read-only
mode.

Upon power up the EEPROM will automatically enter the
Program Disable Mode. Subsequently the design should incorporate the following to achieve protection of stored data.
1) The device powers up in the read-only mode. However,
as a backup, the EWDS instruction should be executed
as soon as possible after Vee to the EEPROM is powered up to ensure that it is in the read-only mode.

Whereas EEPROM is non-volatile and does not require Vee
to retain data, the problem exists that stored data can be
destroyed during power transitions. This is due to either uncontrolled interface signals during power transitions or noise
on the power supply lines. There are various hardware design considerations which can help eliminate the problem
although the simplest most effective method may be the
following programming method.

2) Immediately preceding a programming instruction
(ERASE, WRITE, ERAL or WRAL), the EWEN instruction
should be executed to enable the device for programming; the EWDS instruction should be executed immediately following the programming instruction to return

All National Serial EEPROMs, when initially powered up are
in the Program Disable Mode·. In this mode, the EEPROM
will abort any requested Erase or Write cycles. Prior to Eras-

·EWDS or WDS, depending on exact device.
tEWEN or WEN, depending on exact device.

~~___S_~_N_D~BY______

EWEN
EWDS

01---'\ 0 C'fl!!I!II/IIA
o

ENABLE = 11
DISABLE=OO

TLlD17085-1

FIGURE 1. EWEN, EWDS Instruction Timing

MAIN POWER SUPPLY

4.5V'5. 5V

Vee

r
r

1....._____

5.5V, Vee ,'.5V

MAINTAINED ON CAPACITOR

-jL

INSTRUCTIONJOOSl.....~~
(ERASE, WRITE,
ERAL OR WRAL)
TLlD17085-2
·EWDS must be executed before Vcc drops below 4.5V to prevent accidental data loss during subsequent power down and/or power up transients.

FIGURE 2. Typical Instruction Flow for Maximum Data Protection

4-3

the device to the read-only mode and protect the stored
data from accidental disturb during subsequent power
transients or noise.

must be large enough to maintain Vee between 4.5 and
5.5 volts for the total duration of the store operation, INCLUDING the execution of the EWDS instruction immediately following the last programming instruction. FAILURE TO EXECUTE THE LAST EWDS INSTRUCTION
BEFORE Vee DROPS BELOW 4.5 VOLTS MAY CAUSE
INADVERTENT DATA DISTURB DURINGSUBSEQUENT POWER DOWN AND/OR POWER UP TRANSIENTS.

3) Special care must be taken in designs in which programming instructions are initiated to store data in the EEPROM after the main power supply has gone down. This is
usually accomplished by maintaining Vee for the EEPROM and its controller on a capacitor for a sufficient
amount of time (approximately 50 ms, depending on the
clock rate) to complete these operations. This capacitor

4-4

Electronic Compass
Calibration Made Easy with
EEPROMs

National Semiconductor
Application Brief 18
Doug Zrebski

When a compass is first installed in a vehicle, or when new
equipment, such as car speakers, are added to a vehicle
with a compass, the compass must be compensated for
stray magnetic fields. With a magnetic compass, it must be
pointed towards magnetic north and then adjusted. This
procedure is repeated at all four main points of the compass
until the compass is calibrated. This procedure is lengthy
and also requires another calibrated compass to point the
vehicle in the correct direction.

once again over the microwire interface. To compensate the
compass in a new environment the procedure is very simple. Start by pointing the car in any direction and push the
switch. The CPU at this time will measure the voltage at the
sense amplifiers and store this information in the E2 memory over the microwire interface. Now the vehicle is turned
180°, and the button is pushed again. The same procedure
will be followed internally. The compensation procedures
are now complete. During operation the CPU will compensate for stray fields by adding an analog voltage back into
the sense amplifiers. This value is stored in E2 memory and
not lost when the power is turned off, but is readjustable if
its environment is modified.

The block diagram illustrates an electronic compass that,
with the aide of an E2 memory, makes adjusting a compass
as easy as pushing a button, and also eliminates the need
for another compass. In addition it gives you the ability to
adjust for variation between magnetic and true north. This is
a major advantage because it is something that even the
most expensive magnetic compass cannot do.

.....
0)

Compass variation is the difference between true and magnetic north. This variation differs all over the world and is
something that must be taken into consideration when navigating by compass. With the E2 memory device, a variance
can be programmed in for any given location. In California
this is approximately 17°, in Michigan approximately 1°.
Once again, this cannot be accomplished by a magnetic
compass, and would have been impossible to accomplish
without an E2 memory device.

The brain of the electronic compass is the COP421 microcontroller. There are two sense coils, one for north/south
and one for east/west. The output of each of the sense
amplifiers is an analog voltage which is fed into the A to D
converter. These voltages are read by the COP421 over the
microwire interface. From these voltages, the microcontroller determines the direction and displays the results

Electronic Compass Block Diagram

FLUX GATE
TOROID
DRIVER

NORTH/SOUTH
SENSE
COIL

NORTH/SOUTH
SENSE AI.lPLIFIER
LI.l324

EAST/WEST
SENSE
COIL

EAST/WEST
SENSE AI.lPLIFIER
LI.l324

A/D
CONVERTER
COP434

I.lICROWIRET~

E2 I.lEI.lORY
NI.l93C06

INTERFACE

COP421

TL/D/8613-1

4-5

•

~
C")
C")

1'-:-1

MAX

191

MIN------------------D-U-M-M-y-BI""TJ

~Jl.-J
r--5 s-, . ~
1
OL!..J0L-

0
.....D-I-5-D-l-J,... 013

DATA OUT
TL/D/8611-5

FIGURE 5

4-14

>
Z

National Semiconductor
Application Note 507

Using the NM93CSxx Family

.......

INTRODUCTION
TABLE I. NM93CSxx Family

This application note is intended for system designers interested in using the NM93CSxx family of CMOS serial
EEPROM devices. These devices are well-suited for applications that call for non-volatile, writeable memory. The
NM93CSxx devices offer the additional benefit of selective
write-protection by use of an on-chip protect register. This
allows the device to perform both read-only memory (ROM)
and EEPROM functions on the same chip.
EEPROMs are useful in a wide variety of applications because of their non-volatile, writeable characteristics. The
devices can be used for applications that store configuration values, such as feature telephones, station presets on
radios, and PC boards with configuration DIP switches and
jumpers. Adaptive, closed-loop systems, such as environment controllers and motor controllers, can use EEPROMs
to store loop control variables. Data logging is another of
the many application areas of EEPROMS.

16 x 16
32x 16
64x 16
128 x 16
256 x 16

NM93CSxx FAMILY DESCRIPTION

A set of 10 instructions are provided to control device operation. The general format of the instructions is a start bit
(logic 1) followed by opcode, register address and data
fields. The register address for the NM93CS06/26/46 is 6
bits, while the register address for the NM93CS56/66 is 8
bits. Data is shifted into the device on the 01 pin, and out on
the DO pin following a low to high transition of SK. CS must
be high to access the device (see Table 2).

The NM93CSxx family devices exhibit extremely low power
consumption due to the low drive requirements of their serial interface and the use of CMOS technology. The serial
interface also provides the designer with a flexible interface
mechanism allowing the devices to be easily designed into
microcontroller and microprocessor systems. In microcontroller systems, or those with a serial bus, the devices can
be connected with little or no support logic. The serial interface allows the device to fit in a smaller package, resulting
in minimal board space requirements.

CS_

Memory Size

The NM93CSxx family is a set of 5 CMOS serial EEPROM
devices with on-chip write-protection logic. The members of
the family are differentiated by their memory array size,
which ranges from 256 to 4096 bits organized 16 bits wide
(see Table I). Because the devices use a serial interface,
the pinout for each family member is identical. The devices
conform to the MICROWIRE interface and are backwards
compatible with previous National serial EEPROM devices
(see Figure 1).

The NM93CSxx family can support a new set of applications
because of their additional capability to perform selective
ROM functions. ROM is a requirement when the integrity of
data stored in a device must be guaranteed. Applications
can make use of this feature while at the same time allocating other locations in the device to operate as
EEPROM.

DIP

Device
NM93CS06
NM93CS26
NM93CS46
NM93CS56
NM93CS66

A read operation is performed by issuing the start bit, the
appropriate opcode (10), and the desired register address.
The device responds by shifting out a dummy bit (logic 0)
followed by the data in the selected register. The device will
continue to shift data from subsequent registers as long as
SK is active (non-volatile shift register mode). Write operations are performed by issuing the start bit, opcode (01),
register address, and 16 bits of data. CS must be brought
low to initiate the self-timed programming cycle, which includes an automatic erase cycle. CS can then be brought
high to monitor DO (low to high transition) for completion of
the cycle.
SO

t-Vee

NS_

Pin Names
I -NC

SK_

~PRE

CS_

-Vee

0100_

~PE

SK-

_PRE

I - GND

NC_

~NC

01_

r- PE

00-

r- GND

NC_

I - NC

TL/D/9417-1

TL/D/9417-2

FIGURE 1. NMC93CSxx Device Pinout

4-15

CS
SK
01
DO
GND
PE
PRE

Vee

Chip Select
Serial Clock
Serial In
Serial Out
Ground
Program Enable
Protect Register
Enable
Power Supply

.....

oII)

z•
cc

TABLE II. NM93CSxx Instruction Set
Instruction

OpCode

Address

READ

Ax-Ao

WEN

11XXXX

Data

PRE

Comments

Reads data stored in memory, starting at specified address.

Write enable must precede all programming modes.

Write register if address is unprotected.

Write all register. Valid only when "protect register"
is cleared.

WRITE

Ax-Ao

015-00

WRALL

01XXXX

015-00

WOS

OOXXXX

Disables all programming instructions.

PRREAO

XXXXXX

Reads address stored in "protect register".

PREN

11XXXX

Must immediately precede PRCLEAR, PRWRITE,
and PROS instructions.

PRCLEAR

111111

Clears the "protect register" so that no registers
are protected from WRITE.

PRWRITE

Ax-Ao

Programs address into "protect register". Thereafter,
memory address < the address in "protect register"
are protected from WRITE.

PROS

000000

One time only instruction after which the address in the
"protect register" cannot be altered.

The protect register is used to write protect a segment of
registers. The value contained in the protect register designates the first address of the protected segment. All subsequent register locations are write-protected.

93CSXX
MICRO

USING THE PROTECT REGISTER
The incorporation of the protect register in NM93CSxx devices sets the family apart from other CMOS serial
EEPROMs. Including a protect register allows the devices to
function as EEPROM and ROM simultaneously. The distribution of EEPROM and ROM in a device is determined by
the value in the protect register. The distribution of
EEPROM and· ROM can be changed in the system by
changing the protect register value.

---1

PRE

TLlD/9417 -3

FIGURE 2a. Protect Register Disabled

ROM applications typically require that data storage be nonvolatile so that no changes will occur when power is turned
off and read-only so that changes won't occur under any
other circumstances. EEPROMs are non-volatile, but aren't
read-only. An EEPROM will function as a ROM if write operations are never attempted or if any attempted write fails.

93CSXX
MICRO

The protect register is valuable when an application requires
a mix of EEPROM and ROM. A NM93CSxx device can be·
made less susceptible to write problems without using the
protect register. The entire device may be made read-only
by grounding PE. System software can be implemented to
avoid writing to read-only locations and limit when write instructions may be performed by making use of the write
enable (WEN) and disable (WOS) instructions. The device
would only be susceptible to a write problem if a system
failure caused an illegal write or some external source with
access to the device abused its write privileges. Use of the
protect register under system control would be somewhat
safer, but the device would still be subject to the abovementioned problems. Write access to the protect register
must be inhibited for the protected locations to be truly
read-only.

PRE

TL/D/9417-4

FIGURE 2b. Protect Register Enabled with Pulldown
93CSXX
MICRO

PRE

---1

TLlD/9417-5

FIGURE 2c. Protect Register Enabled

4-16

l>
data as it is read in. In addition, the protect register then
serves the dual purpose of being a pointer to the last location written, simplifying software and saving a variable location (see Figure 2c).

ROM devices are most often programmed with data before
insertion into a PC board. This approach is applicable to
NM93CSxx devices. In a microcontroller system, program
code or data could be off-loaded from the internal ROM of
the microcontroller into a ROM section in an NM93CSxx
device. An EEPROM section could be allocated for any
writeable data, such as configuration data values. ROM is
desirable in this application because any spurious writes
that could corrupt the program will be prevented, a smaller
internal microcontroller ROM is possible and if ROM code or
data needed alteration, it would be much easier and cheaper to reprogram a NM93CSxx device than the internal ROM
of the microcontroller. In manufacturing, the ROM data and
the protect register value would be programmed into the
device, and the protect register enabled before PC board
insertion. The PRE pin would be tied low on the board to
prevent write access to the protect register (see Figure 2a).

INTERFACING TO THE NM93CSxx FAMILY
COP800 Interface
The COP800 family is a set of 8-bit CMOS microcontrollers.
The family members differ by program and data memory,
on-chip peripherals, and package size. Some members
have on-chip EEPROM for program or data memory. The
devices with EEPROM for program memory are only intended for development purposes. All members of the family
have an on-chip MICROWIRETM interface.
93CSXX
CDP800

Another application for these devices is in systems that support automated production. Production information, such as
date codes and status, would be programmed into the
NM93CSxx on a board as it progressed through each step
of the production process. Board identification (serial number) and fixed configuration information could also be programmed into the device as a last step. The PRE pin would
be pulled low with a resistor to allow production test equipment to drive it high to write data into the device and set the
protect register, but prevent any writes to the protected locations during normal operations. The EEPROM section
could be used to allow the application to support automated
system configuration. Once all boards are placed in the system, any system configuration dependent variables could be
programmed (see Figure 2b).

CS1

PRE

TLlD/9417-6

FIGURE 3. MICROWIRE Interface
The COP800 family provides three options when interfacing
to a NM93CSxx device. The interface could be designed by
using the COP800 device parallel port pins under software
control, on-chip UART if available, or the MICROWIRE interface port. The most attractive option for the interface is the
MICROWIRE because NM93CSxx devices connect directly
to it.

In data logging applications, the protect register is programmed as the data is gathered to reduce the likelihood of
modification. When the protect register is accessed regularly by the software, PRE must be accorded an interface line,
usually a port pin that is controlled by software. The protect
register disable (PROS) instruction must be used upon completion of logging to fully protect the data. PROS will prevent
any further writing to the protect register, even if the device
is removed from the board. Extreme care should be exercised when considering use of PROS. Oata should be written into the device from high locations to low to protect the

The MICROWIRE port provides a serial clock (SK), serial
input (SI), and serial output (SO). These lines are directly
connected to SK, 00 and 01 of the EEPROM. COP800 parallel port pins can be used for providing CS, PE and PRE. If
PE or PRE are static in the application, they can be tied low
or high. No other hardware is required for the interface (see
Figure 3). In a system with multiple devices on the MICROWIRE, additional logic may be required to perform chip selection. If available, parallel port pins could be used for additional chip selects. Otherwise, a PAL device could be designed so that chip selects are set serially preceding any
serial device operations.

4-17

eno

.....

oLI)

z•

;RDEEPROM-READ DATA FROM E.EPROM

;THIS ROUTINE WILL READ A SPECIFIED NUMBER OF BYTES FROM
;THE EEPROM USING THE MICROWIRE. THE CODE ASSUMES THAT THE
;SHIFT CLOCK IS PROGRAMMED AT 1/2 THE INSTRUCTION CLOCK RATE.
;THE ARGUMENTS PASSED TO THIS ROUTINE ARE A BYTE COUNT, OPCODE,
;AND REGISTER ADDRESS, POINTED TO BY B.
;THE BYTE COUNT AND DATA READ ARE POINTED AT BY B ON RETURN.
RDEEPROM:

A,x'FE
A,x'F1
LD
A, [B+l
X
A,x'FO
SBIT 1,x'D4
SBIT 7,x'E9
SBIT 2,x'EF
RBIT 2,x'EF
A,[B]
LD
X
A,x'E9
SBIT 2,x'EF
IFBIT 2,x'EF
JMP
TSTl
SBIT 2,x'EF
RBIT 2,x'EF
CLRA
SBIT 2,x'EF
IFBIT 2,x'EF
JMP
TST2
X
A,x'E9
X
A, [B+l
DRSZ x'FO
JMP RLOOP
LD
A,x'F1
A,x'FE
X
RBIT 1,x'D4
RET

;SAVE POINTER

TSTl:

RLOOP:
TST2:

;COPY BYTE COUNT
;CHIP SELECT
;SEND START BIT

;SEND INSTRUCTION

;BUSY?
;GET DUMMY BIT?
;GET DATA BYTES
;BUSY?

;DONE GETTING?
;RESTORE POINTER
;DROP CHIP SELECT
FIGURE 5. COP800 MICROWIRE Read Routine

Inside a COP800 device the MICROWIRE hardware consists of an 8-bit shift register (SIO), a control bit (BUSY) in
the program status word (PSW) , and a control register
(CNTRl), BUSY is set by the control program to initiate a
shift operation and is automatically reset when eight bits
have been shifted. BUSY can be reset by the program for
shift operations of less than eight bits. CNTRl is used to set
the MICROWIRE mode and rate of SK. SK can be set to a
divide by 2, 4, or 8 of the instruction clock rate. The MSEl
bit of CNTRl sets the MICROWIRE to Master mode or
Slave mode. In Master mode, a device will generate SK and
in Slave mode it will receive SK. Master mode is used to
interface to an NM93CSxx device.

In addition to initializing the interface, software rountines are
required to control data transfers to and from the EEPROM
through the MICROWIRE port. The same routines used to
read and write to the EEPROM can be used to execute the
NM93CSxx instructions, including accessing the protect
register. The only extra step required to access the protect
register is that PRE must be set high.
A routine must access SIO to perform an NM93CSxx instruction. Since the MICROWIRE shift register is only eight
bits wide, multiple accesses are required to complete an
instruction. In addition, instructions aren't byte-aligned; routines must align the operation. Instructions can be bytealigned by sending a single start bit followed by a byte of
opcode and address. A start bit can be sent by using the set

4-19

.....

oLI)

~--------------------------------------------------------------------------------------.

bit (SBIT) instruction to set BUSY, followed by the rest bit
(RBIT) instruction when SK is being divided by two, or by
sending a byte with seven leading zeros as dummy bits and
a single one for the start bit. The NMC83CS56/66 devices
require two more bits to be sent for alignment because of
their larger address space. In this case it is easier to send
the byte with leading zeros.

the EEPROM and the number of bytes of data specified by
the byte-count. The dummy bit is read in exactly the same
way as a start bit is sent (see Figure 5).
HPC Interface
The HPC family is a set of high performance 16-bit microcontrollers. Like the COPS microcontrollers, the HPC devices are MICROWIRE compatible, providing an excellent
means of interfacing to NM93CSxx devices. Though, a software controlled interface using parallel port pins could be
used, as well as an on-chip UART.

The write routine, WREEPROM, sets CS to select the device, then writes a single start bit, followed by a byte of
opcode and address, and two bytes of data. The bytes sent
are stored as a string preceeded by a byte-count. The byte
count must, obviously, be three for a write. This routine can
be used to perform the other write-only NM93CSxx instructions by setting the byte-count and data string appropriately.
CS is brought low to initiate the automatic erase/write cycle.
The routine doesn't bring CS back high to check for completion of the cycle. This allows the routine to be used to perform the other NM93CSxx instructions and the control program to perform other tasks during the cycle. If the program
is unsure of cycle completion, DO should be checked before
initiating another instruction (see Figure 4).

93CSXX
8051

P2.0

The read routine, RDEEPROM, sets CS and sends the start
bit, opcode and address in the same manner as the write
routine. The routine then reads a dummy bit (logic 0) from

P2.1

P2.2

P2.3

PRE

TLID/9417-7

FIGURE 7. 8051 Interface

4-20

#define
#define
#define
#define
#define
#define
#define
#define

SELCS
*_iporta!=Ox40
/*
DROP_CS *_iporta &: = OxFB/*
SIO
OxD6
/*
PORTA
OxCS
/*
IRPD
OxD2
/*
NOT_DONE I(*_Irpd &: OX04) /*
BFUN
OxF4
/*
SK
\
*_bfun &: = OxBF
*_bfun ! = Ox40;

#define

WR_EE (bytes. data)
int i;

set chip select*,
lower chip select-,
SIO register location*,
PORT A location-,
IRPD register location-,
DONE flag set if true*'
BFUN register*,

SK;
for(I=O; I < bytes; 1+ +) \
\

(

*_sio = *dat.a++;
while (NOT_DONE) ;
*_irpd &: = OxFB;

I
'* Global Definitions-,
char
-_sio = SIO;
char
-_iporta = PORTA;
char
-_irpd = IRPD;
char
-_bufn = BFUN;
wr_eeprom(bytes.data)
int
bytes;
,- byte count-,
char
*data;
/* data buffer*,
SET_CS;
WR_EE;
DROP_CS;
rd_eeprom(bytes. data)
int
bytes;
,- byte count*'
char
*data;
'* buffer pointer·,
SET_CS;
WR_EE (1. data) ;
SK;
for (i = 0; i < bytes;
*data ++ = *_sio;
while (NOLDONE) ;
*_irpd & = OxFB;

/* get dummy bit *'
++){

DROP_CS;
FIGURE 6. HPC C Language Interface Routine

4-21

>
Z

CJ'I

....
Q

~ r---------------------------------------------------------------------------~

oa.n

;SNDBYT - SHIFTS 8 BITS OF DATA TO EEPROM
;THIS ROUTINE SHIFTS A BYTE POINTED AT BY RO
;ASSUMES CHIP SELECT ALREADY ACTIVE (HIGH)
SNDBYT
S_LOOP:

MOV
MOV
RLC
MOV
CLR
SETB
DJNZ
RET

B,#8
;LOAD SHIFT' COUNT
A,@RO
;GET BYTE
A
;SHIFT
P2.0,C ;SEND BIT
P2.2
;SK
P2.2
B,S_LOOP;DONE?

;WREEPROM - WRITE DATA TO EEPROM
;THIS ROUTINE WRITES A SPECIFIED NUMBER OF BYTES TO THE
;EEPROM USING SNDBYT UTILITY ROUTINE. THE DATA IS POINTED AT
;BY THE RO REGISTER AND CONSISTS OF BYTE COUNT, OPCODE/REG ADDR
;AND DATA BYTES. DO IS SET HIGH TO AVOID CONTENTION.
WREEPROM: MOV
INC
SETB
CLR
SETB
WR_LOOP: LCALL
INC
DJNZ
SETB
CLR
RET

R2,@RO
;COPY BYTE COUNT
RO
P2.1
;CHIP SELECT
P2.2
;START BIT
P2.2
SNDBYT
;WRITE DATA BYTES
RO
R2,WR_LOOP;
P2.0
;DEFAULT DO HIGH
P.21
;DESELECT/PROGRAM
FIGURE 8. 8051 Parallel Port Pin Interface-Write Routines
Unlike the COP800 microcontrollers, the HPC does not use
a 8USY bit to control shifting. The DONE flag in the IRPD
register is polled to determine completion of a shift operation. A single bit can be transferred by changing the mode of
the SK pin back to a general purpose port pin (8.6). This is
accomplished by clearing bit six of the port 8 function register (8FUN). If port 8 bit six is high, the pin will go high immediately clocking the EEPROM.

The MICROWIRE interface provides signals for SK, SI and
SO. CS, PE and PRE signals can be provided by using parallel port pins. Port A on the HPC is allocated for general
use and is ideal for this function. When used in Master
mode, the clock rate for the MICROWIRE is set by programming the appropriate value into the DIV8Y register. The
8-bit SIO register is used as a buffer for serial operations.

4-22

»
z

;RCVBYT - READ A BYTE OF SERIAL DATA

;THIS ROUTINE WILL SERIALLY READ 8 BITS OF DATA FROM THE PORT PIN
;AND STORE THE DATA IN THE LOCATION POINTED AT BY RO
RCVBYT:
R_LOOP:

MOV
CLR
SETB
MOV
RLC
DJNZ
MOV
RET
:RDEEPROM - READ

B,#8
P2.2
P2.2
C,P2.0
A
B,R_LOOP
@RO,A

;LOAD SHIFT COUNT
;SK
;GET BIT
:SHIFT
:DONE?
:STORE DATA

DATA FROM EEPROM

:THIS ROUTINE WILL READ A SPECIFIED NUMBER OF BYTES FROM
;THE EEPROM USING THE RCVBYT ROUTINE. INPUT ARGUMENT STRING IS
;A BYTE COUNT, AND OPCODE/REGISTER ADDRESS. ON RETURN, RO POINTS
;TO A STRING CONTAINING THE BYTE COUNT FOLLOWED BY DATA BYTES
RDEEPROM:

MOV
PUSH
INC
SETB
CLR
SETB
LCALL
SETB
CLR
SETB
LCALL
INC
DJNZ
POP
CLR
RET

R2,@RO
:COPY BYTE COUNT
RO
:SAVE POINTER
RO
P2.1
;CHIP SELECT
P2.2
;START BIT
P2.2
SNDBYT
;SEND INSTRUCTION
P2.0
;DEFAULT DO HIGH
P2.2
:DUMMY BIT
P2.2
RCVBYT
;GET DATA BYTES
RO
R2,RD_LOOP:DONE?
RO
;RESTORE POINTER
P2.1
;DESELECT
FIGURE 9. 8051 Parallel Port Pin Interface Read Routines

The HPC supports program development in the C language.
The software routines to support an HPC interface are similar to those for the COP80a, except that they are written in
C (see Figure 6). The main difference is how the start bit
and dummy read bit are handled. Since the HPC supports
the C language, core routines are written utilizing macros,
eliminating the overhead of an extra level of subroutine
calls.
8051 Interface
The 8051 offers two interface alternatives for the
NM93CSxx family; the first uses parallel port pins under
software control and the second is based on using the onchip serial port. Both interfaces require a minimum number
of device pins and no support logic. The main differences
are that the serial port is faster and requires less software.
The first choice for discussion is the use of the port pins.
The 8051 has four 8-bit bidirectional 1/0 ports. The ports

are accessed through a special function register. The port
registers are bit addressable which facilitates their use in
this application. The minimum interface requires the use of
only three port pins. A pin for CS, SK, and one connected to
both 01 and DO (see A"gure 7). A two wire interface is possible by tying CS active, but this leaves the device in the
active (high power) state and prevents the device programming cycle from being executed.
It is not necessary to have separate lines for 01 and DO
because DO is placed in a high-Z condition during write operations. During a read operation the 01 pin is driven to send
the instruction to the EEPROM and DO outputs the dummy
bit (0) and data. To prevent contention 01 has to stop driving
a high before DO can output the dummy bit. The 8051
doesn't drive a high, it uses internal pull-ups to obtain a
high, so there is no contention problem. This may be a con-

4-23

o.......

cern in other designs. The DO pin is driven when CS is
brought high following a write operation to time completion
of programming Contention will occur on the operation following a write if programming completion isn't checked. A
dummy check can be used.

the 8051 is an 8-bit machine, two utility routines, SNDBYT
and RCVBYT, are used to shift a byte of data to and from
the NM93CSxx.
The write routine, WREEPROM, raises CS to access the
device, shifts out a start bit, then calls SNDBYT to shift out
the opcode/register address byte, and other data bytes, as
specified by the byte-count (see Figure 8).

When using the port pins, one must consider that some of
the port pins have alternate functi9,ns. For example, Port 3
pins 0 and 1 are also allocated for the serial port. Similarly, if
the program being executed on the 80?1 resides in external
memory, then Ports 0 and 2' will serVe as the system bus
during external memory access.

The read routine, RDEEPROM, starts out by raising CS,
sending a start bit, and using SNDBYT for the opcode/register address byte. The dummy bit is then shifted from the
device and RCVBYT is called to shift in the number of bytes
of data specified by the byte-count (see Figure 9).

The software support routines are primarily concerned with
controlling the flow of data to/from th,~ EEPROM. Because

4-24

;RDEEPROM - READS DATA FROM NMC93CSXX DEVICE
;THE ROUTINE READS A SPECIFIED NUMBER OF BYTES FROM
;THE EEPROM USING THE SERIAL PORT. RO POINTS TO AN ARGUMENT STRING
;CONTAINING THE BYTE COUNT AND THE OPCODE/REGISTER BYTE
;A STRING IS RETURNED CONTAINING THE BYTE COUNT FOLLOWED BY DATA.
RDEEPROM:

RLOOP;

PUSH
MOV
INC
SETB
CLR
SETB
MOV
JBC
CLR
CLR
SETB
SETB
JBC
CLR
MOV
INC
DJNZ
CLR
CLR
POP
RET

RO
R2,@RO
RO
P2.1
P3.1
P3.1
SBUF
TI$
TI
P3.1
P3.1
REN
RI,$
RI
@RO,SBUF
RO
R2,RLOOP
REN
P2.1
RO

;SAVE POINTER
;COPY BYTE COUNT
;CHIP SELECT
;SEND START BIT
;SEND INSTRUCTION
;DONE?
;GET DUMMY BIT
;GET DATA BYTES
;DONE?

;DESELECT
;RESTORE POINTER

;WREEPROM - WRITE DATA TO EEPROM
;THE ROUTINE WRITES A SPECIFIED NUMBER OF BYTES TO EEPROM
;POINTED AT BY RO. ARGUMENTS INCLUDE BYTE COUNT AND OPCODE/ADDRESS
WREEPROM:

SLOOP:

MOV
INC
SETB
SETB
CLR
SETB
MOV
INC
JBC
DJNZ
CLR
RET

R2,@RO
RO
P2.1
P3.0
P3.1
P3.1
SBUF ,@RO
RO
TI,$
R2,SLOOP
P2.1

;COPY BYTE COUNT
;CHIP SELECT
;START BIT

;SEND DATA BYTES
;DONE?
;DESELECT

FIGURE 10.8051 Serial Port Read and Write Routines

4·25

,-------------------------------------------------------------------------------------------,

8051 INTERFACE-SERIAL PORT

c:c

The 8051 serial port operates in one of four modes: 8-bit
shift register, 8-bit UART and two different 9 bit UART
modes. The 8-bit shift register mode (Mode 0) is preferred
because it operates with no protocol, as opposed to the
UART modes which send and receive packeted data. When
in Mode 0, the 8051 RxO pin is used as a serial in/out pin
and the shift clock is provided on the TxO pin. The TxO pin
would be connected to SK and RxO would be connected to
01 and DO on the NM93CSxx device. CS, PE and PRE
would be connected the same way as in the port pin interface.

When implementing the parallel port pin interface, the
choice of the port pins used is more critical because more of
these pins have alternate functions. If the 8096 must perform external memory accesses, the use of Ports 3 and 4
becomes a problem because these two 8-bit ports make up
the address/data bus. Port 0 pins are used for the analog
input channels. Port 2 pins have alternate functions such as
the serial port. Port 1 pins do not have alternate functions
and may be preferred for use.
The 8096 provides an on-chip serial port which may be used
for interfacing the NM93CSxx devices. The serial port has 4
modes of operation. The mode of interest for this application is the shift register mode (Mode 0). The 8096 shift register mode serial clock rate is not a fixed rate. It is therefore
the responsibility of the support software to program the
baud rate appropriately.

When using the serial port in Mode 0, the serial port control
register (SCaN) must be programmed by setting the SMO
and SM1 bits (bits 7 and 6) to O. The serial clock runs at a
fixed rate of 1112 of the oscillator frequency. The maximum
frequency for the serial clock on NM93CSxx devices is
1 MHz. This means the 8051 can run with an oscillator frequency up to 12 MHz. After every eighth bit is received. or
transmitted the 8051 hardware will set either the receive
interrupt (RI) or transmit interrupt (TI) bit in SCaN. These
bits may be polled, or used to generate interrupts.

INTERFACING NM93CSxx WITH HIGH PERFORMANCE
MICROPROCESSORS
High performance microprocessors like the NS32000,
iAPX386 and the MC680xO are usually implemented as central processor in computers and aren't directly involved with
peripheral devices. Rather, these machines communicate
over a backplane bus. These processors are designed for
high speed, parallel data transfers. The NM93CSxx devices
could be used with these processors if a serial bus is implemented as part of the backplane bus. Typically, a serial bus
would be used for system configuration or diagnostic purposes. Both the VME bus and Multibus II supply serial communication signals that may be used to interface NM93CSxx
devices to a high performance processor.

The software routines for the serial port interface are virtually the same as those for the previous example. The only
differences are that the 8051 serial port performs the same
functions as the SNOBYT and RCVBYT routines. Instead of
calling these routines, the REN bit is enabled to initiate reception and the data is read from the serial buffer (SBUF).
For writing, the data is written into SBUF to perform the
transfer. The routines poll the RI or TI bits. Because data
transactions are synchronous, interrupts are not applicable
(see Figure 10).

SUMMARY
The NM93CSxx family can be used in a wide variety of applications. The devices provide a non-volatile, writeable
memory that requires the least amount of board space, support logic and power. The protect register allows for a flexible mix of RAM and ROM. The previous examples illustrate
that the NM93CSxx family easily interfaces to microcontrollers and systems with a serial bus.

8096 INTERFACE
The 8096 is a 16-bit microcontroller. Like other microcontrollers, it interfaces easily to the NM93CSxx devices. The
use of parallel port pins or the on-chip serial port provide
two interface options.

4-26

;RCYBYT - READ UTILITY ROUTINE
;THIS ROUTINE WILL READ 8 BITS OF DATA FROM THE SERIAL PORT
;THE DATA IS STORED IN THE LOCATION POINTED AT BY THE DX REGISTER.
RCVBYT:
BOP_SK:

BIT_l:
R_SHIFT:

LDB
ANDB
ORB
JBS
ANDB
SJMP
ORB
SHLB
DECB
JNE
LDB
RET

AH,#8
P2,#FBH
P2,#04H
P2,3,BIT_l
AL,#FEH
R_SHIFT
AL,#OlH
AL,l
AH
BOP_SK
(DX),AL

;LOAD SHIFT COUNT
;STROBE SK
;READ BIT

;DONE?
;SAVE DATA

;RDEEPROM - READ DATA FROM EEPROM

;SI, SK, CS, SO
P2[3 ••• 0]
;THIS ROUTINE WILL READ A SPECIFIED NUMBER OF BYTES FROM THE
;EEPROM AND STORE THE DATA. ARGUMENTS SUPPLIED TO THIS ROUTINE
;ARE A BYTE COUNT, OPCODE/REGISTER ADDRESS, AND ADDRESS FOR
;STORING THE DATA.
RDEEPROM:

RD_LOOP:

PUSH
LDB
ANDB
ORB
ORB
LCALL
ANDB
ORB
LCALL
INC
DECB
JNE
ANDB
POP
RET

DX
BL, (DX)+
P2,#FOH
P2.#03
P2,#04
SNDBYT
P2,#FBH
P2, #04H
RCVBYT
DX
BL
RD_LOOP
P2,#FDH
DX

;SAVE POINTER
;COPY BYTE COUNT
;CHIP SELECT,START BIT

;SEND INSTRUCTION
;GET DUMMY BIT
;GET DATA BYTES
;DONE?
;DESELECT
;RESTORE POINTER

FIGURE 11.8096 Port Pin Interface Read Routines

4-27

.....
o
in

Using National's
NMC87C257
256K EPROM with On-Chip
Latches

National Semiconductor
Application Note 731
Sean Pitonak

INTRODUCTION

parent and the Address Latch Enable (ALE) is on a shared
pin with Vpp. By tying Vpp to Vee, the NMCB7C257 behaves
exactly like the 27C256. The NMCB7C257 is available in
both quartz-windowed Ceramic DIP and Plastic LCC packages as is the 27C256.

The standard EPROM available from most manufacturers
limits the on-chip circuitry to just the minimum needed to
operate the EPROM and the minimum of user interface handles. Users of standard EPROMs are forced to include
latches in their design to interface with most microcontrollers and microprocessors.

SUMMARY

NATIONAL'S NMC87C257 SOLUTION
The NMCB7C257 is pin-compatible with the standard
27C256 (1 Megabit EPROM, organized as 12BK x B bits),
shown in Figure 1. In fact, the NMCB7C257 can be directly
substituted into the many existing 27C256 sockets when
used in the unlatched mode. The internal latches are trans-

Vpp
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

Vpp/ALE- 1

....

National's latched EPROM is useful because the same ALE
used for the 74F373 latch can be tied to the ALE of the
NMCB7C257, eliminating the need for the 74F373 latch. As
shown in Figure 2, it is as simple as removing the two octal
latches and routing the appropriate bus and control line to
the EPROM.

Probably one of the most desirable user-interface features
is the ability to directly interface the EPROM to a host device that has a multiplexed address and data port. This type
of interface is present on many microcontrollers and microprocessors such as the HPC, BOC51 and many of the Intel
and Motorola microcontrollers. National is now manufacturing an EPROM that can directly interface with a host device-the NMCB7C257.

27C256

'-I
CN

The NMCB7C257 allows the user the combination of familiar
functionality, pinout and programmability (due to its compatibility with existing 27C256 EPROMs) and the advantages of
saved board space, cost of the octal latches and their insertion and system power consumption. The NMCB7C257
gives the system designer the needed flexibility of interfacing directly with microcontrollers and microprocessors that
have multiplexed address and data ports.

'-'

A12- 2

27C256
28 f-Vcc
27 rA14

A7- 3

26 rA13

A6- 4

25 f-A8

A5- 5

241-A9

A4- 6

231-All

A3- 7

22 rOE

A2- 8

21 t-Al0

Al- 9

20 f-CE/PGt.l

AO- 10

19 r07

00- 11

18 r06

01- 12

17 r05

02- 13

16 f-04

GND- 14

15 -03

Vee
A14
A13
AB
A9
A11
OE
A10
CE, PGM
07
06
05
04
03

TLIO/ll089-1

FIGURE 1. Socket Compatible 27C256 EPROM Pin Configuration
is Shown In the Block Adjacent to the NMC87C257 Pins.

II
4-31

--......
Cf')

Z•

HPC

NM27C256

HPC

Understanding National's
NM95C12 EEPROM with
Programmable Switches

National Semiconductor
Application Note 735
Sean Pitonak

INTRODUCTION

Address 62 is the location of the SCR, which controls the
switch logic of the output terminals. This address contains a
volatile memory and therefore does not have endurance or
programming time limits associated with it, allowing the outputs to be reconfigured an unlimited number of times.

National's NM95C12 is a 1024-bit Serial EEPROM with 8
programmable switches. These outputs can provide logic
and analog switch inputs and outputs on a parallel bus, allowing this device to perform functions such as polling via
the serial bus, interrupts via the serial bus and converting
parallel data onto the serial bus.
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the NM95C12. It consists of a
61-word x 16-bit EEPROM array, a 16-bit Initial Switch Register (ISR), a 16-bit Switch Configuration Register (SCR), a
16-bit Switch Readback Register (SRRl, four identical
blocks of switch logic, programming and power-up circuits
and control logic.

Addresses 0-60 of the EEPROM are available to the user
as general purpose non-volatile memory. Data may be read
or programmed into this memory using the appropriate instructions.
Address 61 is also an EEPROM location, but it is used as
the ISR to provide the initial switch configuration information
automatically on power-up.

.......
W

Address 63 contains the SRR. This is a read-only register
that reads back the logic levels present on the switch terminals. Only 8-bits of the SRR are used.
The NM95C12 also includes a Sequential Register Read
function that allows the user to obtain an endless loop of
data by entering the read mode and leaving the CS high.
SWITCH CONFIGURATIONS
The 16-bit SCR format is shown in Figure 2. It consists of
four 4-bit fields. Each field controls its corresponding switch
control logic. The individual bits in each field are labelled W,
X, Y and Z. Table I shows the relationship between these bit
values and the resulting behavior of the terminals.
Each switch pair can be individually configured to 1 of 14
modes. Therefore both logic and analog switches can be
implemented simultaneously.
The logic switch configurations are at standard TTL levels.

Address.

,....----..,9

PROGRAt.At.AING

E2 PROt.A
61 WORDS x16 81TS

POWER UP
CIRCUITS

6'0

A2
82

16
0::

C
C

A3
83

01
DO

S K - - -.....

CS------'

84
TL/D/ll097-1

FIGURE 1. NM95C12 Block Diagram

4-33

C")

r------------------------------------------------------------------------------------------,

......

z•

15 14 13 12 11 10

Izlvlxlwlzlvlxlwlzlvlxlwlzlvlxlwl
SWITCH 4

SWITCH 3

SWITCH 2

SWITCH 1

TlID/11 097-2

FIGURE 2. Switch Configuration Register (SCR)

TABLE I. Switch Configurations
t.lODE·

SWITCH CONFIGURATION

COt.lt.lENTS

~A~B

A=1 ,B=O

~A ~B

A=1 ,B=1

~A
0

A=O,B=O

A=O,B=1

A = 0 , B = Tristate

t> ~:

A=B

e>o--::

A=B

~A
OB

0
0

A= 1·, B=Trlstate

A=Trlstate , B=O

t> ~:

B=A

I ~:

B=A

.o-p. {reo.
~
--

"Modes 0 thru 11 are logic level functions. Modes 12 and 13 are Analog switch functions.

4-34

A=Trlstate , B= 1

Analog Switch
Open

Analog Switch
Closed
TL/D/11097-3

For example, in Mode 1, Terminal A would be driving VOL
and Terminal 8 would be driving VOH. In Mode 5, where an
input and output structure exists, Terminal A would be driving VIL or VIH. The switches also include a TRI-STATE@
mode to represent an open terminal.

POWER-UP MODE

»
z

When the NM95C12 is powered-up:

......

1. The data previously stored in the ISR is automatically
transferred to the SCA.

2. The SCR controls the switch logic, producing the switch
configuration of the terminals A1 through A4 and 81
through 84.

Each switch pair can also function as input/output terminals
in Modes 5, 6, 9, 10 and 13. Modes 4, 7, 8, 11 and 12
represent the same input/output functions, but with the
switch in the "open" configuration.

The switch configuration is valid 1 ms after the device power
supply reaches 4.5V or greater.

Address.
PROGRAMMING

E2 PROt.l
61 WORDS x16 BITS

POWER UP
CIRCUITS

9
6'0

r-I
I
I
I

VII

~I ~I

g: C31
<:~: t~40i~!'
I

I 16}

.. - -

"'1".- - - 8

~~-----~ft~ICI']i~~-]

A3
B3

CS--------"'

SK- - - - -"'

TL/D/11097-4

FIGURE 3. Power-Up Mode

•
4-35

~ r---------------------------------------------------------------------~

C")

......

UPDATE MODE

To update the information that is contained in the SCR and
therefore on the output terminals:

INPUT MODE
The SRR allows the current logic level present at the switch
terminals to be read back on the MICROWIRETM bus:
1. The states of the output terminals are loaded into the
SRR by reading address 63.
2. The control logic allows the a-bit parallel input to be converted to serial output on the DO pin.
The bit assignments and the conceptual function of the
SRR are shown in Figure 7. Only bits 15 through a are used;
Bits 7 through 0 are always read as logical O.
The SRR Read Timing diagram is shown in Figure 8. Note
that it is valid to terminate any read cycle early, allowing the

user to avoid reading Bits 7 through 0 if that is desired. It is
also valid to include leading zeros after the CS has gone
high and before. sending the start bit. Combining leading
zeros and terminating the read cycle early may help simplify
device control and speed read cycles.

-.oJ
W
U1

Mode 12, Analog switch open, is valid for SRR input mode.
For switch mode 1~ (Analog switch closed), the SRR will not
report the actual levels present at the terminals due to the
analog levels. As a default, bits 15 through a of the SRR will
be all O's to indicate a closed analog switch. This is done to
avoid ambiguous logic levels which could exist when the
device is used in the Analog switch mode.

AI
81

DO
SK- - - - -

I
I

CS--------~

TL/D/ll097-7

FIGURE 6. Input Mode

TL/D/ll097-B

FIGURE 7. Bit Assignments and Conceptual Function of the Switch Readback Register
CHIP SELECT

-.Jr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , ' - .

SERIAL CLOCK

•

SERIAL DATA IN

SERIAL DATA OUT
TERt.4INAL INPUTS

(A4...AI, 84 ... 81)
TLlD/ll097-9

FIGURE 8. SRR Read (Input Mode) Timing Diagram
4-37

SEQUENTIAL REGISTER READ FUNCTION
In a read mode, normally the CS input is made LOW after
the last data bit is shifted out. However, if the CS input is left
HIGH and clocking continues,· data from the next address
location will be delivered on the DO pin. This sequential
read can continue indefinitely whereby the address is automatically incremented after delivering 16 bits of data. In this
mode the address count will continue through the ISR, SCR
and SRR and then wrap around to Address O.
During a sequential register read there will be a dummy bit
preceding the first word read, after which, the bit stream will
be continuous without any dummy bit separating the data
words.
WRITE CYCLE CONSIDERATIONS
After loading the WRITE instruction and the 16-bit data, the
chip enters into a self-timed programming cycle when CS is
forced LOW before the next rising edge of the SK clock
(refer to Figure 9). The timer status is available on the DO
pin if the CS input is forced HIGH within 1 ms of starting the
programming cycle. LOW on the DO pin indicates that programming is still in progress (BUSY), while HIGH indicates
that the device is READY for the next instruction.

If the CS input is made HIGH for status observation, it must
be made LOW when READY is indicated before loading the
next instruction.
CONCLUSION
National's NM95C12 offers users the standard functionality
of a 1024-bit EEPROM and includes 8 programmable terminals that can be used to implement both logic and Analog
switch functions simultaneously. These switches can be
used, for example, to replace mechanical DIP and SPST
switches, as well as allow interrupt polling via the serial bus.
When the device is powered-up, the switch configuration is
automatically transferred to the output terminals. The terminals can be updated easily by executing a write cycle. In the
input mode, the current logic level at the output terminals is
read into the device and output onto the serial bus.
The NM95C12 combines unique and useable features with
the simplicity of standard EEPROM functionality.

01 _ _ _1

DO ~~---------------------t----'-_lB~US~Y~--A'1_~~iY-'---R~OY
HI-Z

1------twP-----l
TLlD/11097-10

FIGURE 9. WRITE Timing Diagram

4-38

»
z

NM95C12 Flexibility in
Industrial Control
Applications

National Semiconductor
Application Note 755
Sean Long

INTRODUCTION

play (LCD, LED, etc.), I/O interfaces, and power driver/control circuits. The NM95C12 forms the basis of this design
performing the non-volatile parameter storage, a low cost
ADC, an I/O expander, and providing a simple control interface.
Figure 1 shows the basic block diagram with the shaded
parts representing the functions performed by the
NM95C12.

This application note describes a general purpose industrial
controller and details how a NM95C12 can be used to integrate a number of different functions typically found in such
a design.
General purpose application examples of the use of the
NM95C12 are presented rather than a specific design. Each
design idea and software can be incorporated into the designer's required application.

U1
U1

This application note will describe the theory of operation
behind the design and give detailed software examples to
show how to interface a popular microcontroller to the
NM95C12.

The basic building blocks of an industrial controller (for example, heating, process control, etc.) are a microcontroller,
an Analogue to Digital Converter (ADC), an EEPROM, a dis-

SENSOR

......

SWITCH
CONDITIONING

THESE FUNCTIONS CAN
BE INTEGRATED INTO
A NM95C12

KEYBOARD,
SWITCHES,

SOLENOID,
VALVE,

ETC.

ETC.
TL/D/11160-1

FIGURE 1. Typical Industrial Controller Block Diagram

4-39

It)
It)

......

z•
c(

+W~~------------'--------------1-----------------'----~~'-------------------------------

COP820C

r-------I CKI

OUTPUT 10 mV I Ok

"'---1--+

1II335:

CKO (G7)

VIN

10k
Rz

G5 G4 G6
(5K) (SO) (51)

5W11 SW21

I I
ov

TL/0/11160-2

COP820INM95C12 Industrial Controller

4-40

l>
THE NM95C121024-BIT CMOS EEPROM WITH DIP
SWITCHES

THEORY OF OPERATION
The relationship for charge of a capacitor is as follows:

The NM95C12 features 1K-bit EEPROM memory with a
switch logic terminals. These switch logic terminals are individually programmable outputs which may be used as DIP
switch positions or as SPST switch positions.

Charge (Q) = Voltage (V) x Capacitance (C)
= Current ( I ) x Time (T)
Therefore the voltage across the capacitor, VCAP
VCAP = (I x T)/C
Assuming that the current I is a constant source, and the
capacitance value C does not vary gives:

The NM5C12 uses the MICROWIRETM serial 110 interface
which is fully compatible with COPSTM microcontrollers via
4 simple control lines:
SK -

VCAP is proportional to T.

Serial Clock

CS -

Chip Select

Mode of Operation

DI-

Data In

DO- Data Out

initially switch S1 is closed to short out VCAP to measure
input voltage VIN

To Measure VIN:
- microcontroller opens S1 and starts internal timer at T1

The EPROM array (addresses 0 to 60) is addressed via five
instructions:
READ -

Read Data from register

VCAP is proportional to time T

WEN -

Write enable

WRITE -

Writes data to register

when VCAP
high

WRALL -

Writes to all registers

microcontroller stops internal timer at T2

WDS -

Disables all programming instructions

VIN is proportional to time T = T2 - T1

microcontroller closes S1 ready for next measurement

This area of memory is used for the normal EEPROM applications such as the storage of user changeable, non-volatile parameters such as time on/off, temperature on/off limits, etc.

This is based on a LM932 which has an Operational Amplifier and a Voltage Comparator in the same a-pin package.
This device operates from a single + 5V supply.

Address locations 61 to 63 control the switch operation.
Name

ISS

SCR

SRR

VIN then comparator output VCOMP goes

CURRENTSOURCE/VOLTAGECOMPARATOR
FORADC

CONTROLLING THE SWITCH LOGIC

Address

Refer to the National Semiconductor General Purpose linear Databook for further details of the LM392.

Description
Provides the initial switch
configuration automatically on
power-up. Controlled via a WRITE
operation.

INPUT SENSOR
For this example assume temperature needs to be controlled.
LM335: This is a precision, low-cost, easily calibrated two
terminal temperature sensor that behaves like a zener diode
with a voltage of + 10 mV / degree Kelvin. The initial accuracy is ± 10 and can be externally trimmed with a potentiometer connected to the ADJ pin.

The SCR is not an E2 location and
hence is volatile. The SCR is loaded
automatically from address 61 on
power-up. The SCR controls the
switch terminals A 1-A4 and
81-84.

Refer to the National Semicohductor Linear Databook 2 for
further details of the LM335 Temperature Sensors.
NM95C12 SWITCH LOGIC APPLICATIONSI
CONFIGURATIONS

The SRR allows the current logic
levels of the switch terminals to be
read back via the MICROWIRE bus.

A 1• B1-Control the Charge/Discharge of Capacitor for
ADC
Switch Configuration:
Analog Switch Open: Mode 12, ZYXW = 110?
(? = don't care)
Analog Switch Closed: Mode 13, ZYXW = 111?
To change the state of the switch terminals A1, 81, follow
the flowchart in Figure 3.

4-41

......

U1
U1

~ .---------------------------------------------------------------------~

VCAP

VIN
TL/D/11160-3

FIGURE 2. Single Slope Analogue to Digital Converter

READ CONFIGURATION
OF OTHER TERMINALS.
A2- 4• B2- 4

MASK OUT BITS 4-15
SO AS NOT TO
CHANGE A2- 4• B2- 4

UPDATE NEW
CONFIGURATION FOR
A, • B,

Read SCR

Logical "And" SCR Contents with:
FFFC-to OPEN switch
FFFE-to CLOSE switch

Write new value to SCR
TL/D/11160-4

FIGURE 3. Controlling Switch Terminals A 1, B 1

4·42

Address 62

The advantage of this design is that it saves input pins on
the micro controller and means that the software does not
have to perform periodic polling of the inputs to determine
the mechanical switch status since the circuit is interrupt
driven.

A2, B2 and A3, B3 - Switch Debouncing
The switch logic configuration is shown in Figure 4. When
either of the mechanical switches SW1 or SW2 are pressed,
this causes the interrupt line (INn to be pulled low signalling
to the microcontroller that a switch has been pressed. As
part of the interrupt service routine the microcontroller can
generate a delay to allow time for mechanical switch debouncing, before reading the NM95C12 SRR to determine
which mechanical switch was pressed.

Switch Configuration: both A2,B2 and A3,B3 will be configured in mode 5; ZYXW = 0101.
To change the state of the switch terminals A2,B2 and A3,B3
follow the flowchart in Figure 5.

+5V

INTERRUPT SERVICE
ROUTINE

1NT 10.0

--t'"---r----....--------

....-~-- 13.0V
VOUT1

r-~f--.;..--1-----

< 14.0

O.IOOA

+ COUT1
1330J.l.F
+5 ....- " " ' - -

......-"jIIIt---t-----e---- VOUT2

-13.0V
0.100A

COUT2

1330J.l.t

CIN2
1.00J.l.F

''I

+5
Lt.42577-ADJ
Ul

~IOJ.l.F

no!.80k

14.3k

17.5k

22.4k

81 Vec
82
Nt.495C12

83
GND

Al
A2
A3
CS
2.00k

(10V)

2.00k

(12V)

(15V)

Edge Connector
TL/D/11161-2

FIGURE 2

4-52

>
z

(,J1

THIS PROGRAMMING EXAMPLE IS A SAMPLE
THAT COULD BE USED TO PROGRAM THE NM95C12

IT IS WRITTEN IN ZSO ASSEMBLY LANGUAGE FOR THE NSCSOO

EQUATES:
READ
WEN
WRITE
WRALL
WDS
:
MODEO
MODEl
MODE2
MODE3
MODE4
MODE5
MODE6
MODE7
MODES
MODE9
MODE1O
MODEll
MODE12
MODE13

EQU
EQU
EQU
EQU
EQU

SOH
OOH+30H
40H
OOH+10H
OOH

:READ COMMAND
:WRITE ENABLE COMMAND
:WRITE COMMAND
:WRITE ENTIRE MEMORY
;WRITE DISABLE

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

OH
lH
2H
3H
4H
5H
6H
7H
SH
9H
OAH
OBH
OCH
ODH

:A=O,B=O
:A=O,B=l
iA=l,B=O
;A=l,B=l
;A=O,B=TS
;A=B
;A=B '
;A=l,B=TS
;A=TS,B=O
;B=A
iB=A'
;A=TS,B=l
;ANALOG SWITCH OPEN
;ANALOG SWITCH CLOSED

EQU
EQU

MODE12
MODE13

;

OPEN
CLOSED

MASKS USED TO OPEN AND CLOSE SWITCHES
AB1CLO
AB2CLO
AB3CLO
AB4CLO
AB10PN
AB20PN
AB30PN
AB40PN
AB1MSK
AB2MSK
AB3MSK
AB4MSK

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

OOOOFH
OOOFOH
OOFOOH
OFOOOH
OOOOCH
OOOCOH
OOCOOH
OCOOOH
OFFFOH
OFFOFH
OFOFFH
OOFFFH

; SWITCH
iSWITCH
iSWITCH
; SWITCH
; SWITCH
iSWITCH
iSWITCH
; SWITCH
iMASK

1
2
3
4
1
2
3
4

CLOSED
CLOSED
CLOSED
CLOSED
OPEN
OPEN
OPEN
OPEN

EEPROM MEMORY LOCATIONS
ENABLE

EQU

SN
DATE
PUSCR
SCR
SRR

EQU
EQU
EQU
EQU
EQU

1
32
61
62
63

:LOC O,BIT 0=1 IF WR ENABLE
=0 IF WR DISABLED
:
;SERIAL NUMBER STORAGE
;DATE STORED (DPS570 FORMAT)
;SCR LOADED FROM HERE ON POWER UP
;SWITCH CONFIGURATION REGISTER
;SWITCH READ BACK REGISTER (READ ONLY)
TL/D/11161-3

4-53

&t)
,.....

Z•

EEPORT: EQU
EE:
EQU

OOH
EEPORT

;I/O ADDRESS OF PARALLEL PORT
; SHORTHAND

THE PARALLEL PORT IS CONFIGURED AS:
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

0
1

2
3
4
5
6
7

DATA OUT
CLOCK
CHIP SELECT
N/U
N/U
N/U
N/U
DATA IN

OUTPUT
OUTPUT
OUTPUT

INPUT

FOR THIS PROGRAMMING EXAMPLE:
H
L
DE
B
C

EEPROM OPCODE
EEPROM ADDRESS
16 BIT DATA
SHIFT COUNTER
PORT DATA STORAGE

ORG

lOOOH

MAIN PROGRAM
THIS SAMPLE PROGRAM SETS SWITCH 1 CLOSED, ALL OTHERS OPEN
MAIN:
LD
CALL
LD

LD
LD
CALL
LD
LD
CALL
LD
CALL
HALT

H,WEN
;ENABLE CODE FOR NM95C12
WRCMD
;SEND COMMAND
DE,ABICLO+AB20PN+AB30PN+AB40PN
;SWITCH 1 CLOSED
;SWITCH 2 OPEN
;SWITCH 3 OPEN
;SWITCH 4 OPEN
H,WRITE
;EEPROM OPCODE
L,SCR
;ADDRESS TO WRITE TO
WRDATA
;WR TO SWITCH CONFIGURATION REGISTER
H,WRITE
;OPCODE
L,PUSCR
; ADDRESS
WRDATA
WR TO POWER UP SCR
H,WDS
WRITE DISABLE
WRCMD
DISABLE FURTHER WRITING
END OF THIS EXAMPLE
TLlD/11161-4

4-54

l>
ZI

......

WRITE COMMAND SUBROUTINE

USE FOR "WEN" AND "WDS" COMMANDS
WRITES COMMAND TO EEPROM
EXPECTS COMMAND TO BE IN H REG
EXPECTS ADDRESS TO BE IN L REG
WRCMD:
CALL
CALL
CALL
RET

PRECK
SHIFTS
CSLOW

;SET CS, CHECK FOR BUSY
;SEND COMMAND
;SET CS INACTIVE
iDONE

WRITE DATA SUBROUTINE
USE FOR "WRITE" AND "WRALL" COMMANDS
WRITES COMMAND AND DATA TO EEPROM
EXPECTS COMMAND TO BE IN H REG
EXPECTS ADDRESS TO BE IN L REG
EXPECTS DATA
TO BE IN D&E REG
ASSUMES EEPROM IS WRITE ENABLED

,
WRDATA:
CALL
CALL
CALL
CALL
RET

PRECK
SHIFTS
SHIFT16
CSLOW

;PRELIMINARY CKS
;SEND COMMAND
;SEND DATA
;SET CS INACTIVE

THIS ROUTINE DOES A PRECHECK OF THE EEPROM STATUS
IT SETS CS ACTIVE
WAITS AT LEAST 500 NS
LOOPS TILL NOT BUSY
LEAVES CS ACTIVE, DATA OUT LOW
IT EXPECTS PORT DATA IN C REG
PRECK:
PUSH
LD
AND
OR
LD
OUT

AF
A,C
OFDH

IN
AND
JP
POP
RET

A, (EE)
SOH
Z,PRECKl
AF

C,A
(EE) ,A

; SAVE
;GET PORT DATA
;MASK CLK & DATA LOW
iSET CS ACTIVE
iSAVE
;WRITE TO PORT

PRECK1:
;READ PORT
;ACC = 0 IF BUSY
;LOOP UNTILL NOT BUSY
; RESTORE
;ELSE DONE
TL/D/11161-5

4·55

THIS ROUTINE SHIFTS OUT 8 BITS OF COMMAND (+ START BIT)
IT WRITES TO A PARALLEL PORT WHOSE OUTPUTS ARE CONFIGURED AS:
BIT 0
BIT 1
BIT 2

DATA
CLOCK
CHIP SELECT (ACTIVE HI)

IT ASSUMES CS IS ACTIVE
IT SENDS A START BIT (LOW TO HI TRANSITION)
THEN IT SENDS DATA MSB FIRST
IT EXPECTS PORT DATA IN C REG
IT DESTROYS H,L,B
~

SHIFT8:
PUSH
CALL
LD
LD
OR
LD

AF
STRTBT
B,7
A,L
H
L,A

; SAVE
; SEND START BIT
;LOOP COUNTER
; ADDRESS
;COMBINE WITHOPCODE
~SAVE IN L

LD
AND
LD
RLC
JP
OR

A,C
OFDH
C,A
L
NC,SH8LP

;GET PORT CONTENTS
;MASK CLK AND DATA LOW
; SAVE
~CK MSB OF DATA
;IF 0, DO NOTHING
;ELSE SET DATA BIT HI

SNDBIT:

SH8LP:
OUT
OR
OUT
AND
OUT
DEC
JP

(EE) ,A
2

(EE) ,A
OFDH
(EE) ,A
B
NZ,SNDBIT

;SEND DATA WITH CLK=O
;CLK=l
;SEND IT
;CLK=O
;SEND IT
;LOOP ONE FEWER TIMES
;LOOP UNTILL DONE

ELSE, WE HAVE SENT 8 BITS
POP
RET

; RESTORE
TL/0/11161-6

4-56

»
z

-.....
(J1

THIS ROUTINE SHIFTS OUT 16 BITS OF DATA

0')

IT WRITES TO A PARALLEL PORT WHOSE OUTPUTS ARE CONFIGURED AS:
BIT 0
BIT 1
BIT 2

DATA
CLOCK
CHIP SELECT (ACTIVE HI)

IT ASSUMES CS IS ACTIVE
HOLDS DATA TO BE SENT (MSB FIRST)
i

SHIFT16:
PUSH
PUSH
LD

AF
DE
B,7

iLOOP COUNTER

LD
AND
LD
RLC
JP
OR

A,C
OFDH
C,A
D
NC,SH16LP
1

iGET PORT CONTENTS
iMASK CLK AND DATA LOW
iSAVE
iCK MSB OF FIRST BYTE OF DATA
;IF 0, DO NOTHING
iELSE SET DATA BIT HI

(EE) ,A

iSEND DATA WITH CLK=O
;CLK=l
iSEND IT
;CLK=O
;SEND IT
;LOOP ONE FEWER TIMES
iLOOP UNTILL DONE

SNDBT:

SH16LP:
OUT
OR
OUT
AND
OUT
DEC
JP

(EE) ,A
OFDH
(EE) ,A
B
NZ,SNDBT

ELSE, WE HAVE SENT FIRST 8 BITS
LD

B,7

iLOOP COUNTER

LD
AND
LD
RLC
JP
OR

A,C
OFDH
C,A
E
NC,SH16LPl

iGET PORT CONTENTS
iMASK CLK AND DATA LOW
iSAVE
iCK MSB OF SECOND BYTE OF DATA
iIF 0, DO NOTHING
iELSE SET DATA BIT HI

SNDBT1:

SH16LP1:
OUT
OR
OUT
AND
OUT
DEC
JP

(EE) ,A
2

(EE) ,A
OFDH
(EE) ,A
B
NZ,SNDBTl

iSEND DATA WITH CLK=O
;CLK=l
iSEND IT
;CLK=O
;SEND IT
;LOOP ONE FEWER TIMES
iLOOP UNTILL DONE

ELSE, WE HAVE SENT ALL 16 BITS
POP
POP
RET

DE
AF

RESTORE
TL/D/11161-7

4-57

CD
&n

r-Z•

SEND A START BIT
;

STRTBT:
PUSH
LD
AND
OUT
OR
OUT
OR
OUT
AND
OUT
LD
POP
RET

AF
A,C
OFCH
(EE) ,A
1

(EE) ,A
2

(EE) ,A
OFDH
(EE) ,A
C,A
AF

;SAVE ACC
iGET PORT CONTENTS
;MASK CLK « DATA LOW
;SEND IT
iDATA = 1
;SET UP DATA
iCLK = 1
; SEND
;CLK = 0
; SEND
iSAVE NEW CONTENTS IN C
;RESTORE ACC

SET CS LOW (INACTIVE)
ALTERS C REG
CSLOW:
PUSH
LD
AND
LD
OUT
POP
RET

AF
A,C
OF8H
C,A
(EE) ,A
AF

; SAVE
iGET PORT DATA
:SET CS LOW (AND DATA AND CLK)
; SAVE
:WRITE TO PORT
; RESTORE
; DONE

END
TLl0/11161-6

4·58

»
z

Main Loop

......

Set "DATA" SWI Closed
SW2. 3. 4 Open
Set "OPCODE" Write
Set "Addr" = SCR

TL/D/11161-9

Write Command to NM95C12

4-59

TL/D/11161-10

1.1)

1"0-

Z•

TLlD/11161-12

TL/D/11161-11

·Pre-check of NM95C12 sets CS active. Returns
when NM95C12 not busy.

Write Data (16 Bits) to NM95C12

$
$

CSActlve
Wait Till Not Busy
Send OPCODE

Send Data

CSlnactive

TL/D/11161-13

Send Start Bit to NM95C12

TL/D/11161-14

4-60

ADDRESS

Shifts 8 Bits Into the NM95C12 via the Data IN Pin

»
z

Shift 16 Bits of Data to NM95C12

......

U1
0)

Combine Port Data with
Data to be Sent
Rotate Data 1 Bit
SH16lP:
Combine Port Data with
Data to be Sent
Rotate Data 1 Bit

Send Data
Set ClK ..r-L
Dec loop Counter

SHelP:
Send Data
Set ClK ..r-L
Dec loop Counter

TLlD/11161-16

TL/D/11161-15

4-61

r---------------------------------------------------------------------~

Lt)

.....
Z•

to the NM93CS instruction set table (Table II) for definitions
of these instructions. As with the NM93C family, there is a
basic difference in instruction length depending on memory
size.

To further increase data security in these EEPROMs there
are also two additional input signals defined, Program Enable (PE) and Protect Register Enable (PRE). These signals
are on pins that are unused on the NM93C family providing
upward compatibility to the NM93CS devices.

TABLE I. NM93C Family Instruction Set Table
Instruction

Op Code

Address

A7/A5-AO

EWEN

11XXXX

Write enable must precede all programming modes.

ERASE

A5-AO

Erase register A5A4A3A2A1AO.

READ

WRITE

A5-AO

ERAL

10XXXX

WRAL

01XXXX

EWOS

OOXXXX

OpCode

Address

READ

A5-AO

Data

Comments
Reads data stored in memory.

015-00

Writes register.

015-00

Writes all registers.

Erase all registers.

Disables all programming instructions.

TABLE II. NM93CS Family Instruction Set Table
Instruction

Data

PRE

Comments
Reads data stored in memory, starting at specified address.

WEN

11XXXX

Write enable must precede all programming modes.

WRITE

A5-AO

015-00

Writes register if address is unprotected.

WRALL

01XXXX

015-00

Writes all registers. Valid only when Protect Register is
cleared.

WOS

OOXXXX

Disables all programming instructions.

PRREAO

XXXXXX

Reads address stored in Protect Register.

PREN

11XXXX

Must immediately precede PRCLEAR, PRWRITE, and PROS
instructions.

PRCLEAR

111111

Clears the Protect Register so that no registers are protected
from WRITE.

PRWRITE

A5-AO

Program address into Protect Register. Thereafter, memory
addresses ~ the address in Protect Register are protected
from WRITE.

PROS

000000

One time only instruction after which the address in the
Protect Register cannot be altered.

4-63

......

U1
ClO

1.1.3 Variations

During the course of clocking in the start bit, op-code address and data-in or data-out, chip select must be held high
continuously, otherwise the internal circuits will be reset and
the cycle will have to be started again with a new start bit.

There are two variations on the standard implementation of
the Microwire bus. Both variations can be viewed as enhancements. The first enhancement is a Organization
(ORG) input that allows the user to select the internal configuration of the memory as either 8 bits wide or 16 bits
wide. When the input is high or unconnected, the device is
configured as 16 bits wide, when the ORG input is at a low
level, the memory is configured as 8 bits wide, but twice as
deep. The feature is present on both the NM93C46A and
the NM59C11.

During programming cycles chip select initiates the internal
programming cycle. The falling edge of chip select will start
the internal programming cycle when a programming opcode has been entered (Erase, Write, Erase All, Write All)
and then, in conjunction with Data-Out (DO), will indicate if
programming is complete (except the NMOS NMC9306). If
programming is complete, Data-Out will drive high, if incomplete it will drive low. In the case of the NMC9306, the user
must provide the programming time and in this case chip
select must be held low for a minimum of 10 ms, then
brought high and clocked to end the programming cycle.

The second variation is the STATUS output. This is the
Busy/Ready polling to indicate programming status. All other devices have this feature on the Data-Out (DO) output,
the NM59C11 alone has status available as a separate output and not on the Data-Out output. This can simplify interfacing to a bidirectional data bus.

Several additional notes in regard to chip select:
If a programming cycle is partially clocked in and then chip
select dropped, the EEPROM may enter into a programming
mode. This is determined by how many bits have been
clocked in when chip select is dropped. If the start bit, opcode, and all of the address has been clocked in, a programming cycle will be initiated with no or partial data. If less
than a complete address has been clocked in, the programming cycle will not be initiated. Refer to Figure 2, reference
line 1.

2.0 Hardware Connection
2.1 INTERFACE PIN DESCRIPTIONS
In this section, each possible input or output will be described followed by the most popular variations of bus connections. Not all devices have all of the described 1I0s. The
1I0s are available according to Table III, 110 Functionality.

In the case of the NM59C11, a programming cycle will not
be entered unless a full data field has been clocked in. A full
data field may be either 8 or 16 bits depending on the logic
level present at the ORG input. A programming cycle will be
entered at reference line 2 in Figure 2 for the NM59C11.

2.1.1 CHIP SELECT (CS)
Chip Select is used to differentiate between various devices
on the same Microwire bus. In the case of EEPROM it cannot be tied high even if it is the only device on the bus as it
performs several additional functions. As it applies to any of
the Microwire EEPROMs, the rising edge resets the internal
circuitry of the device, a function necessary prior to initiating
any new cycle. As shown in the functional block diagram
(Figure 1) chip select also gates the data input and clock
input, thus disabling these functions.

Chip select hold time at the end of a cycle is referenced to
the last rising edge of clock (SK). The hold time from the
rising edge is the same as the minimum SK high time for the
particular device. This is stated in the datasheets as 0 ns
hold time from the falling edge of SK which assumes that
SK high time is always minimum. In this case SK can be left
in the high state or taken low at a later time. Internally chip
select gates SK, therefore SK is not critical.

TABLE 111.1/0 Functionality by Device
CS

x
x

NM93CS Family

x
x

NM93C46A

NM59C11

x
x
x
x

NM93C Family

x
x
x

4-64

PRE

ORG

STAT

x
x

>
Z

......

Vpp
GENERATOR

f+-VCC

!VPP

r--+

.-.

+
DECODER
1/16

E2PROM

256 BITS
(16x 16)

ADDRESS
LATCHES

R/WAMPS

I
4

l6
~

DATA
REGISTER
(17 BITS) CLK

.-L-

'",>-

rLJ

INSTRUenON
REGISTER CLK
(9 BITS)

J;
---CS
SK

INSTRUCTION
DECODE.
CONTROL
AND
CLOCK
GENERATORS

I---

"\.
TL/0/11169-1

FIGURE 1. Block Diagram

cs.J

TL/0/11169-2

FIGURE 2. Programming Cycle Point of No Return

4-65

II)

......

:2:
<

2.1.2 SERIAL CLOCK (SK)

2.1.4 OATA·OUT (~O)

The clock input is used to clock all data, address, op-code,
and start bits into or out of the EEPROMs. SK clocks both
input and output on the rising edge only, the falling edge has
no effect on the devices. The only function it is not necessary for is the Busy/Ready Polling which is an asynchronous function.

The Data-Out (DO) output sends read data onto the microwire bus and is clocked out on the rising edge of SK. It also
carries the programming status after a programming cycle
which is an asynchronous function that does not require the
clock. At all other times the Data-Out is in the high impedance state. During a Read cycle, the Data-Out output begins
to drive actively after the last address bit (AD) is clocked in.
During the Busy/Ready polling it begins to drive active after
chip select is raised to a high level.

Since SK is gated by ship select, it is a "Don't Care" any
time chip select is low. It is also don't care prior to a start bit
being clocked in and during Busy/Ready Polling. During
these conditions Data-In (DI) must be held at a low level,
otherwise a start bit will be interpreted.

During the Busy/Ready Polling, the Data-Out output drives
low while the device is still in the internal programming cycle. After the EEPROM has completed the internal programming cycle, the Data-Out pin will drive high when chip select
is high. Subsequently, if chip select is brought high again,
Data·Out will again drive high indicating it has completed
the programming cycle. To clear the Busy/Ready Polling it
is necessary to raise chip select and clock in a start bit.
Once the start bit is clocked in, Data-Out will return to the
high impedance state. It is not necessary to continue with a
cycle after this start bit has been clocked in, although it is
permissible to start a new cycle with this start bit. This clearing of the Busy/Ready status may be necessary if a bidirectional data bus is used (Data-In tied to Data-Out) as the
Data·Out output will interfere with the new data being presented on the Data-In input.

If it is desirable to insert additional clock cycles during a
instruction sequence for the purpose of byte aligning the
data, there are several places in the data stream they may
be inserted as described below:
-

On any instruction, zeros can be clocked into the DI input before the start bit. Any number of clock cycles may
be added if Data·ln (DI) is held at zero. The first 1
clocked in will be interpreted as the start bit. This requires special precautions if a bidirectional data bus is
used (Data-In tied to Data-Out) as the Busy/Ready Polling will interfere with the Data-In if it is not cleared out at
the end of each programming cycle. See Section 2.3,
THREE WIRE BUS, for more information.

During a Read instruction, it is allowable to continue to
clock the device after the 16 bits of data has been
clocked out. In the case of the NM93CS family this will
cause the memory to increment to the next register and
present its contents on the Data-Out pin. In the case of
all other devices, whatever was present on the Data-In
pin will become present on the Data-Out pin (Fall thru).
Refer to Figure 1, Block Diagram.

2.1.5 PROGRAM ENABLE (PE)
The program enable (PE) input will enable all programming
cycles when it is held at a high level during the duration of a
programming cycle. Conversely, it will disable all programming, including programming of the protect register, while it
is held low. This input has no affect on any other cycle, so it
may be permanently tied high or low, or may be used in an
active mode. This input is available on the NM93CS family
only.

During a Write or Write·AII, additional clock cycles may
be added after address AD and before the valid data.
The EEPROM will write into the memory the most recent
16 bits, or in the case of the NM93C46A, the most recent a bits or 16 bits depending on the status of the
ORG input. Adding additional clocks after the valid data
will cause the data to be misaligned. In the case of the
NM59C11, the device counts the data bits clocked in
and automatically enters the programming mode when it
receives a full data field, therefore bits cannot be inserted between AD and valid data.

2.1.6 PROTECT REGISTER ENABLE (PRE)
The protect register enable (PRE) input is used to switch
between memory operations and protect register operations
since the same op-codes are used for both. With the PRE
input high, the op-codes define operations in the protect
register, with the PRE input low, the op-codes define operations in the memory. This pin may be tied high or low, or
used in the active mode. This input is available on the
NM93CS family only.

During the EWEN, Erase, Erase All, EWDS, WEN, WDS
cycles, it is not necessary to clock in a data field, although it is mandatory to clock in a complete address
field, even if the addresses are "Don't Care". Additional
clocks can be added after the address field.

2.1.7 ORGANIZATION (ORG)
The Organization input (ORG) is used to control the internal
organization of the memory. The two selectable organizations are 16·bit words and a-bit words. Simply by holding the
ORG pin at a high level, 16-bit words are selected, by holding the input at a low level a-bit words are selected. When in
the a-bit mode, one additional address bit is required in the
instruction sequence since the depth of the memory is doubled. This input is available only on certain device types,
refer to the individual datasheets.

2.1.3 OATA·IN (01)
The Data-In input receives the Start-Bit, Address, and input
data in a serial stream, each bit clocked in on the rising
edge of SK. DI is gated by the chip select to provide a high
degree of noise immunity. As shown in the block diagram,
Data-In is routed to both the instruction shift register and the
data shift register. When the start bit is clocked into the last
bit of the instruction register, the clock is switched to the
data register to receive input data and clock data out simultaneous. The Data-Out remains in high impedance unless a
read cycle or Busy/Ready status is being done. The safest
state is to keep the Data-In pin in a low level as a start bit is
a high level.

2.1.8 STATUS (ROY/BUSY)
The status output indicates the programming cycle status
after a programming cycle. When the device is in the programming mode and therefore cannot accept any other cycles, this pin will be low. After completion of the cycle the
STATUS pin will be driven high. When this function is present, the Busy/Ready Polling is not available on the Data-Out

4-66

»z
•

----------~------~l~l-----------JII
II

II
I

: - ANY CYCLE - :
TLlD/11169-3
I

~n.rwu~
'cs

CS
WRITE

I
I

~-J~-J~-J~~~~~__~____~~____

TRI-STATE

i
I

I
I

i
I

t - - WRITE CYCLE - t
ONLY
TL/D/11169-4

CS
READ

~----------------~I~~----------~~----~~

~__~__J ' __-"~-J'~~~__________~~________~~I~

_ _ _ _ _ _ _ ____

--------------------------------~l~~(J~x:~je~~---------TRI-STATE

READ CYCLE ONLY
TLlD/11169-5

FIGURE 3. Possible Locations for Additional SK Cycles

4·67

II)

r--

Z•

ca:

.---------------------------------------------------------------------------------------------~

output. In some systems, particularly those using a bi-directional data bus, this can simplify interfacing by eliminating
the possible contention between the Ready indication and
the incoming data from the host device. This output is available only on certain device types, refer to the individual
datasheets.

and the dummy bit. This only occurs during a READ
cycle. This is not harmful to the device and the internal
circuitry of the EEPROM guarantees that the device will
function properly under this condition. To decrease the
noise created by the condition, a resistor may be
placed in the locations indicated in Figure 6. The timing
diagram in Figure 7 shows the bus conflict.

2.2 FOUR WIRE BUS

The 4 wire bus is the simplest interconnection between the
EEPROM and the host device. In most cases the only signals necessary to provide are clock, chip select, Data-In and
Data-Out as shown in Figure 5. The PRE, PE, ORG, and
STATUS pins are not shown as they are variations on this
and the 3 wire bus connection. Multiple devices can be connected to the microwire bus, the only limitations being loading and available chip select means. In some systems it is
necessary to have a bi-directional data line as described
below in 3 wire bus.

The second possible area of conflict occurs when the
Busy/Ready status is on the Data-Out output. Since the
device will continue to indicate a Ready status indefinitely after a programming cycle (until a start-bit is clocked
in), this can conflict with the beginning of the next cycle
if leading zeros are clocked in (See Figure 7). The solution is to either use a separate cycle to clear the Ready
bit or to eliminate any leading zeros from the instruction
sequence. If the Busy/Ready Polling is not used in the
application, the easiest solution is to use the NM59C11
that does not have the polling on Data-Out but has it on
a separate output.

93CXX
MICRO

MICRO

TLl0/11169-7

DO
5K

FIGURE 5. Four Wire Connection

2.3 THREE WIRE BUS
The 3 wire bus operates in the same mode as the 4 wire bus
with the exception that the Data-In and Data-Out pins on the
EEPROM are tied together. When using this connection,
there are two precautions that need to be observed.
-

TL/0/11169-8

FIGURE 6. Three Wire Connection Showing
Optional Resistor

When Data-In is tied to Data-Out, there is a possible
conflict between address AO in the instruction sequence

SK
1

II:

CS )

1
1

READ

1
DO

~~~-J~-J'~-'~~~---,------~l/~--------~11~1-------------1

r:-:

-----..I

CS
CONFLICT
WHEN 01 = 0

~_--....;.H...I-_Z____________~I~~

START BIT

HI-Z

READY BIT FROM PREVIOUS
PROGRAMMING CYCLE

HI-Z

015

DO
~

CONFLICT
WHEN AO=1

r--

TL/0/11169-9

FIGURE 7. Three Wire Connection Bus Conflict Areas

4-68

3.0 Timing Considerations

......

The following information describing the Microwire bus timing must be used in conjunction with the datasheet as it is
an expansion and clarification of the datasheet. First, the
basic timings with respect to the clock (SK) will be described, followed by instruction sequence timing, and finally,
specific information in each instruction sequence.

The only active edge of the clock is the rising edge.

The only time the clock is necessary is when clocking
data into or out of the EEPROM. It is not necessary during Busy/Ready Polling.

3.1. BUS TIMING

The synchronous data timing shown in Figure 8 is similar to
that shown in the various datasheets. There is one significant modification to the timing specification though, the chip
select (CS) hold time is referenced to the rising edge of the
clock rather than the falling edge. With this modification, the
hold time specification must be changed to be the same as

The clock may be left in either the high state or low state
between cycles. It is safer to leave the clock in the low
state.

When chip select (CS) is high, clock (SK) is a critical
signal. With the exceptions noted in Section 2.1.2 tilted
SERIAL CLOCK (SK), no additional clock cycles or noise
that crosses the VIH or VIL thresholds can be tolerated.

the minimum clock (SK) high time. Other significant points
are:

DO
TL/0/11169-11

FIGURE 8. Synchronous Timing

4-69

c.n

co
La
.......

3.2 INSTRUCTION SEQUENCE DESCRIPTIONS

c:(

3.2.1 READ CYCLE

z•

word is proceeded by a dummy bit as in a standard READ,
although the dummy bit is supressed in all subsequent data
words as shown in Figure 9.

The READ cycle requires the host to raise chip select (CS)
and then clock in thru the Data·ln (01) pin a start-bit, opcode, and address. Following clocking in the last address
bit, the Data-Out (DO) output comes out of the high impedance state and drives a low level on the output. This is
referred to as the dummy bit and is a good indication that a
READ mode has been successfully entered if difficulty is
encountered during initial debug of a system. The dummy bit
is clocked out of the EEPROM on the same rising edge of
SK that clocks in the last address bit, AO. This is shown in
Figure 9.

3.2.3 ERASE AND ERASE ALL
The ERASE cycles return the contents of the EEPROM to a
clear state which is read as 1'so It is not necessary for any of
the CMOS EEPROM described in this article, and is included in the NM93C family, NM93C46A, and NM59C11 only for
compatibility with older devices that require erasing. It is
recommended that the erase cycles be eliminated from the
instructions to simplify the code, speed up writing and to
improve the endurance obtained in the application. These
modes are entered by clocking in a start-bit, op-code, and
address. It is not necessary to clock in the data field as it is
assumed to be all 1'So It is necessary to clock in the address, even in the case of ERASE-ALL where it is "don't
care" in all except the first two bits of the address field
which is used as additional op-code bits. After the full address field has been clocked in, chip select must be returned to a low level in initiate the erase cycle. In all devices,
except the NMC9306, programming completion can be determined by Polling as shown in Figure 4, or a simple 10 ms
timeout will guarantee programming is complete if polling is
not used.

3.2.2 SEQUENTIAL READ
Sequential read is a read mode available only on the
NM93CS family. It is entered by entering a READ cycle and
clocking out the first 16-bit word. After reading the first
16-bit word if chip select (CS) is kept high, address A + 1
may be clocked out followed by address A + 2 and so on.
When the maximum address is reached, the memory continues in the sequential read mode at address O. In this manner, the host may operate the memory in a continuous loop
read. When initiating a SEQUENTIAL READ, the first data

csJ

l\.t_r
~l

~------~lll----------~I~Z--------~I~

TL/D/11169-12

FIGURE 9. Sequential Read Sequence

1DO

DI
TLlD/11169-6

FIGURE 4. Busy/Ready Polling Sequence

4-70

3.2.4 WRITE AND WRITE ALL

code and an address field of all O's while both the PRE and
PE inputs are at a high level. This instruction must be immediately proceeded by a PREN instruction.

The Write and Write All cycles will write a specified data
word into the specified address, or in the case of Write All,
the same data pattern will be written into all locations. In all
devices a new data pattern may be directly written over an
existing data pattern without erasing the first data pattern.
The write mode is entered by clocking in a start-bit, opcode, address, and data. The full address field must be
clocked in for the Write All even though it is don't care in all
but the first 2 bits. It is also necessary to clock in a full data
field to assure correct alignment of data. The write cycle will
be initiated after 8- or 16-bit have been clocked into the
device in some of the devices and in other devices after
chip select is brought low regardless of how many data bits
have been clocked in. Refer to the specific datasheets to
determine which method is used.

3.2.9 PROTECT REGISTER CLEAR
The protect register clear instruction will clear the contents
of the Protect Register making the entire contents of the
EEPROM alterable only if the PROS instruction has not previously been executed. This is done by clocking in a startbit, op-code, and address field of all ones. This instruction
must be immediately proceeded by PREN instruction and
requires that both PRE and PE inputs be held at a high level.

3.2.10 PROTECT REGISTER WRITE
The Protect Register write command (PRWRITE) allows the
host to write the protect register with the address where the
memory is to be segmented into ROM and EEPROM. The
defined address is the first ROM address and the ROM field
then continues to the top of memory. To execute this command a start-bit, op-code, and address must be clocked in,
the address field containing the memory address that defines the ROM/EEPROM boundary. The PRE and PE inputs
must be held at a high level.

3.2.5 PROGRAM ENABLE AND PROGRAM DISABLE
Program enable and program disable are the instructions
that enable or disable writing and, where included, erasing.
The instruction name varies depending on the specific device but includes EWEN, EWDS, WEN, and WDS. These
instructions enable or disable the entire memory array with a
single instruction. All devices power up in the disable mode
and once placed in the enabled mode remain enabled until
a disable instruction is performed or Vee is cycled. These
instructions provide the most basic level of data protection.
Although since most lost data is the result of the host device
becoming uncontrolled and performing the "Program Subroutine" it may be helpful to structure the software such that
the enable command is not included in the "Program Subroutine" but is in a separate subroutine. If a greater degree
of data security is needed, a NM93CS family device is recommended, or other more elaborate schemes involving redundant data storage and polling.

3.3 INTERFACING SOLUTIONS
When interfacing serial microwire EEPROMs to microcontrollers there is an apparent conflict that occurs when selecting clock polarity and phase. This can be easily overcome in most situations, although when using some microcontrollers that do not allow selection of either clock polarity
or clock phase, the only solution may be to resort to bit set
and bit reset instructions to interface to the EEPROM rather
than use of the serial interface provided on the microcontroller.
In the instance where there is a dedicated serial interface
provided, the conflict typically occurs as follows. Figure 10
demonstrates an EEPROM READ as this involves data being transferred from the micro to the EEPROM (Start bit, opcode, and address) and data transferred from the EEPROM
to the micro (address contents). The conflict occurs in this
example when the micros clock sets data up on the falling
edge of SK and expects the EEPROM to accept it on the
rising edge, but then expects the EEPROM to do the same
when it sends data back to the micro.

3.2.6 PROTECT REGISTER READ
The protect register read (PRREAD) command is the same
as a word read command except the input PRE must be
held at a high level and the address is don't care. In spite of
the address being don't care, the entire address field must
be clocked in. On the Data-Out pin the contents of the protect register will be clocked out MSB first descending to
LSB.

1. The micro sets up a data bit. A propagation delay after
the falling edge the data bit is valid at the EEPROM 01
pin.

3.2.7 PROTECT REGISTER ENABLE
Similar to the programming enable instructions described
above, the PREN instruction is necessary to perform any
programming instruction the affects the Protect Register.
Unlike the enable instructions described above, a PREN
must immediately proceed each programming instruction
that involves the protect register. The Protect Register programming instructions are PRCLEAR, PRWRITE, and
PROS.

2. The EEPROM uses the rising edge of SK to clock the
data bit into its internal register.
3. When the data direction changes the EEPROM sets the
data up starting at the rising edge of SK.
4. The micro attempts to clock the data bit in that was set
up on clock edge 3.
This example will work if the micro requires 20 ns or less
data hold time after edge 4. If greater than 20 ns is required,
an alternate strategy is needed.

3.2.8 PROTECT REGISTER DISABLE
The protect register disable instruction permanently disables any further programming instructions to the protect
register. Therefore it can only be performed once in the
lifetime of a NM93CS device. The purpose of it is to permanently configure a portion of the EEPROM as true ROM and
a portion as Read/Write EEPROM. Great caution should be
exercised prior to executing this instruction as there is no
second chance. It is performed by sending a start-bit, op-

1a. The micro sets up the data bit on the rising edge and a
propagation delay later it is valid at the EEPROM.
2a. The EEPROM clocks the data into its internal register.
The EEPROM requires only 10 ns data hold time, which
can normally be guaranteed.

4-71

co
,-------------------------------------------------------------------------------------------,
&I)

,...,

z•
c(

3a. The EEPROM sets the Data-Out up on the rising edge.

recognize this as a rising edge of SK. To accommodate this
in a design, it is allowable to clock in any number of logic
zeros prior to the start bit.

4a. The micro clocks the data into it's internal registers on
the falling edge of the clock and a minimum data setup
and hold time is guaranteed for the micro based on the
minimum high and low time of the SK clock used in the
application.

4.0 Conclusion
The serial EEPROM offered by National all share a common
structure. Separating them are various features that give
benefit to various applications such as the need for a bi-directional data bus or need for one byte word width. There
are a number of "tricks" that may simplify interfacing to
these which can easily be understood with the help of a
functional block diagram. Given this information the overall
job of using a serial interface EEPROM will be Simpler.

It should be noted that in the second example, CS (chip
select) is asserted when SK is low. If this cannot be done,
the DI input should be low when CS is asserted. If both DI
and SK are high when CS is asserted the EEPROM will

---1
CD

DO
TLIO/11169-13

DO
TLIO/11169-14

FIGURE 10

4-72

Using the NM95C12 CMOS
EEPROM with
Programmable Switches for
Analog Applications

National Semiconductor
Application Note 765
Alfred P. Neves

INTRODUCTION
National's NM95C12 EEPROM programmable switch occu·
pies a unique niche in the switch marketplace. Consisting of
a 1024-bit serial input EEPROM with 8 programmable
switches, the output can provide either an analog switch or
TIL compatible logic functions.
The combination of switch performance and the flexibility
offered in the ability to software reconfigure the switching
function makes the NM95C12 an excellent device for ana·
log systems requiring switching or multiplexing. Often cali·
bration sequences or multiplexing functions have either reo
quired using several IC's or manually shorting and opening
printed circuit board connections, until the availability of the
NM95C12.
However, the limited analog range of the NM95C12 makes
it difficult to use for general analog functions. In order to
capitalize on the full capabilities of programmable switches,
it is important to understand the appropriate design tech·
niques in level shifting, increasing the output drive capabili·
ty, and increasing the output signal range. The focus of this
application note is to summarize general circuits that per·
form this function, and thereafter provide a practical trans·
ducer measurement system example. The discussion will be
solely devoted to extending the use of the NM95C12's
switches function, and not on the actual software program·
ming or operation of the IC.

logic switch configurations are at standard TIL levels. Also,
the analog switch configurations can be looked at as stan·
dard MUX switches. Since this note specifically focuses on
extending the operating voltage range of the analog
switches, the emphasis will be on the analog switches. Fig·
ure 1 summarizes the salient operating features of the
switch pairs.
Logic Function
A

0--(>---0

o--{>o---o

B
TLlD/lllBB-l

Input Leakage ± 2.5 p.A max
TTL Level Input/Output

Switch Functions

-:-

,Ht.

GENERAL DESCRIPTION

-:-

A detailed description of the overall operation of the
NM95C12 can be found in AN-735, "Understanding Nation·
ai's NM95C12 EEPROM with Programmable Switches", or
the NM95C12 data sheet. However, for the sake of com·
pleteness, the NM95C12 consists of a 61-word x 16-bit
EEPROM array, a 16-bit Initial Switch Register, a 16-bit
Switch Configuration Register, a 16-bit Switch Readback
Register, four identical blocks of switch logic, programming
and power·up circuits and control logic. Essentially, the
NM95C12 programmable switch can be easily configured,
and reconfigured, for applications including both analog and
digital switching functions. 60 internal addresses are avail·
able to reconfigure the switch settings on the fly. Upon pow·
er·up the Initial Switch Register, address 61, provides a de·
fined set·up state. This operational feature is extremely val·
uable since it provides an established initial condition for the
system.
SWITCH DETAILS
Each switch pair can be configured for either logic functions,
or as an analog switch. Functional block details relating
control of the switches to the input control logic can be
found in Table I of the NM95C12 data sheet. Basically, the

,H.

OPEN OR
CLOSED

-:-

.. ~

TL/D/lllBB-2
RON 2000 max
ROFF 10 MO min

(+0.7) :?: VOUT:?: (Vee - 0.7V)

FIGURE 1. The NM95C12 can be Programmed to
Configure either Logic Function or an Analog Switch
LEVEL SHIFTING AND EXTENDING
THE SWITCHES RANGE
In considering level switching and enhancement of the volt·
age range for the NM95C12, it is logical to examine some
simple level translations that can be solved with commer·
cially available IC's. Examples of simple translation circuits
includes the DS1630B Hex CMOS Compatible Buffer shown
in Figure 2. Where simple translation of TIL output signals
to higher levels of output voltage is required (such as CMOS
compatible signals), used at the output of logic configured
NM95C12 switch, the DS1630B represents a simple solu·
tion.

4-73

+5V

.....

TTL INOO_......--I[>~_

TTL OR CMOS

_OOUT

TL/D/11188-3

1/6 DS3630B

Vee

OUTPUTS SWING TO
EITHER V3 OR Y2

OS8800

V2
TL/D/11188-5

OUT

10 kll

25
20
15

-5

-10

TL/D/11188-4

-15

Equivalent Circuit
FIGURE 2. The DS1630B/DS3630B Is a Hex CMOS
Buffer Amplifier. It Features Low Power Consumption,
and an Output Voltage that can go to 16V (Vee).

-20
-25
TL/D/11188-6

An example of a voltage translation is the 058800 Dual
Voltage Level Translator which can be found in Figure 3.
Custom control of output swing can be established over a
31V range by setting V3, and V2 to the appropriate values.
Additional information can be found in the 058800 data
sheet.

FIGURE 3. The DS8800 Is a Dual Voltage Translator
that Is useful for Programming MOS Type Memory,
Establishing Bias Voltages, and Driving Transducers.
Output Swing Is Limited to 31V.
Figures 4 through 10 illustrate some useful translation circuits that use discrete components to achieve higher output
drive than typical monolithic IC's. The circuit in Figure 4 is
similar in functionality to the 058800. However, wider output
swings (limited to BVCeo of the output transistor), and larger
sink/source current ability is achieved.
10 pF

...c:-1

~--o

OUTPUT,
+Y OR -Y

Nt.l95C12 LOGIC INPUT

-Y
TL/D/11188-7

FIGURE 4. - V to

+ V Voltage Translation, from TTL Input 51gnal

4-74

+V
2k

TL/D/11188-8

FIGURE 5. A Simple 0 -+ + V (+ V Typically Is 3V -+ + 18V) Level Translation Stage. ISOURCE > ISINK

-----o

I....iie-...

500n

OUT

Nt.495C12 LOGIC INPUT

ISINK

> ISOURCE

TLlD/11188-9

FIGURE 6. High Output Current Sink Level Translation Stage-Excellent for Transducer Bridge Drive

+V----e----------.---12k

TTL
A

Nt.495C12 LOGIC INPUT
TLlD/11188-10

FIGURE 7. A Simple OV -+

+ V Switch, from TTL Input
+V «100V)

TTL
Nt.495C 12 LOGIC INPUT

+5V

--'\jYv~"""'----f

f\.OAD

TL/D/11188-11

FIGURE 8. OV to High Voltage Translation Circuit, from TTL Input

4-75

&n
CD

to-

Your

VIN

c:c

tOOk

A
2N2907
Nt.495Ct2 LOGIC INPUT

82M

+5V

IO.t~F

-V
TLlD/lllBB-12

FIGURE 9. Control of FET Switch
+V

+t5V

LOAD

3300

Nt.495Ct2 LOGIC INPUT

TL/D/lllBB-13

FIGURE 10. TIL Control of Power FET
set voltage, and strobe the LF398 sample/hold. Complete
control of the transducer measurement system can now be
controlled by the reconfigurable memory contents of the
NM95C12.
A stable LM185-2.5 reference is used to generate an accurate 2.5V voltage. The 1K, 0.001 fLF, 20K circuit provides a
soft-start to the transducer bridge. This prevents potential
damage to metal-foil type 350 bridge transducers. SW1
must be programmed to either enable or disable the bridge
drive. A single-supply, low-power dual op-amp is used to
drive Q1 which provides the appropriate bridge drive. Reliability is enhanced by including a 100 mA short circuit current limit.
The circuit is compatible with positive supply voltages extending from + 5V to + 15V. SW2 can be enabled to alter
the output voltage range of the bridge drive. SW3 and SW4,
in combination with the LF11333 can be programmed to
provide a short to the instrumentation amplifier to null the
amplifiers offset.
Since the output range of the NM95C12 switch is limited to
a diode drop from the + 5V supply line, a LF13333 multiplexer is used to provide switching the bridge output voltage, which will probably exceed this limited voltage range.

TWO PRACTICAL EXAMPLES
Bridge circuits playa dominant role in many measurement
applications. Typically, providing a trimmed, calibrated output response is usually the goal of a bridge transducer signal processing system. Often this requires calibration,
switching for it's operation, and adjustments for operating
conditions related to available supply voltage. The
NM95C12 provides a software reconfigurable analog system, where manual shorting and opening circuit board
traces is not required for either altering the operation of the
.
system, or performing calibration.

Figure 9 shows how the NM95C12 can be used to control a
transducer measurement system. By shifting through the
61-word sequence of the NM95C12 operation of the
bridge-pulsing or exciting the bridge, sampling with the
LF398, and strobing the A/D converter can be performed
with the switches, which are configured in the TTL output
mode.
Figure 10 illustrates the inherent flexibility in using the
NM95C12 for controlling analog applications. One
NM95C12 is used as a switch to directly control both the
excitation voltage output level and enable to the bridge, provide TTL control signals for nulling the bridge-amplifier off-

4-76

.....•

+12V

3.3k

350n
STRAIN GAUGE

A
10k

TO AID

+12V
511k

-= 1FlU.!
OFFSET
ADJUST

s/H

0.068 }Jr
NM95C 12 LOGIC INPUT

TO AID
CONVERTER

TL/D/11188-14

FIGURE 11. Using the NM95C12In the TTL Output Switch Mode to Control Transducer Bridge Operation

III
4·77

AN-765

7n
BRIDGE
ENABLE
/
~

SW2

CURRENT LIMIT TO
-........... 100mA

STRAIN GAUGE
350n

1/4 Lr13333 .
11

~
ex>

N.C.

14
N.C.

1/4
Lr13333

SW4

SW3

TLlD/11188-15

SWX are Internal Switches to the NM95C12

FIGURE 12. Transducer Measurement System

l>
Z

......
0)
U1

:>----0

DC OUT TO A/D

SAt.!PLE/HOLD

SAt.!PLE/HOLD ENABLE EITHER
PROGRAt.!t.!ED EXTERNALLY OR
INTERNAL PULSE GENERATED
FROt.! Nt.! 95C12

FIGURE 12. Transducer Measurement System (Continued)

4-79

TL/D/111BB-16

~ r---------------------------------------------------------------------~
~

l"I

Z
C

Using the NM95C12 in a
Stand Alone Metering
Device

National Semiconductor
Application Note 766
ChrisSiegl

ABSTRACT

Enter the NM95C12 serial E2PROM with eight programmable outputs which are set to their stored values on power up.
This device is not only non-volatile, but is small, inexpensive, simple to use and does not require a microcontroller in
the key device.

This application gives a detailed description of the use of
the NM95C12 in electronic metering key applications where
it is desirable to have a status display without having the key
connected to any device. By using the NM95C12 such functionality can be obtained without using a microcontroller in
the key. This can have significant cost, size and power impact.
INTRODUCTION

Metering keys are becoming quite common now for use on
copying machines in large corporations for departmental accounting purposes as well as in the flood of neighborhood
copy centers and resource facilities shared by a number of
businesses. The simplest implementation of such a device
is a simple mechanical counter with an advance solenoidas each copy is made a pulse advances the counter. This
approach suffers a number of drawbacks including low reliability, easy to tamper with, bulky and unable to itemize between different uses or equipment. These types of devices
are no longer just used for copying machines-fax machine
usage, word processor usage, plotters, and laser printers
are now becoming part of the shared resources of a corporation or among a number of businesses as well as such
services being incorporated into the neighborhood copy
center. While the mechanical counter could still be used in
such applications where the device under use could increment the counter at different rates depending on the type of
usage, a different counter could be used for each service;
generating an itemized receipt for the user becomes very
cumbersome.
By using a non-volatile memory in the key device an itemized list can be kept of the services used. The value of the
servicE1s used could also be tracked and the key terminated
when a certain limit is reached. The key device could function like a debit card where the user gets a certain amount
of credit stored in his card-when it is all used up he must
go back for more at which point a cash register or other
device with a printer and a receptacle for the key device
would print an itemized list of usage and optionally erase the
memory and store a new credit amount. The disadvantage
of this approach when compared to the mechanical counter
is the lack of an indication of the remaining credit or usage
to the user. One way to solve this problem is to include a
display on the device being used to display the current credit information. This has the disadvantage that the user must
have the key device plugged into a service device to find his
credit status. Another approach is to include a microcontroller in the key device along with a display, a battery and a
switch to activate the display. If the battery fails, information
in the key is lost. By using serial E2PROM memory devices
such as the NM9306, NM93Cxx or NM93CSxx families
solves the information retention problem when the battery
fails, but we still need the microcontroller if the key device is
to have an active display without connection to another device.

THE NM95C12

The NM95C12 is a 1024-bit, CMOS E2PROM with 8 programmable outputs. The 1024 bits of memory are divided
into 60 registers of 16 bits each and each register can be
individually accessed. Registers 61-63 are dedicated to
storing the programmable output settings. Each output may
be programmed to provide either a HIGH or a LOW output
level or these outputs may also be programmed to form four
individual pairs of SPST switches. In this application we will
only be programming these pins as HIGH or LOW outputs
but there are many other applications where a SPST switch
or switches would be useful.
Other features of the NM95C12 include a very low operating
current (less than 4 mA), software write protection, self
timed write cycle (erase cycles not necessary) with an endurance of over 40,000 writes per register and at least 10
year data retention.
Interfacing to the NM95C12 is done through the on-board
MICROWIRETM port; this port consists of four signal lines: a
serial clock (SK), serial data input (SI), serial data output
(SO), and chip select (CS). MICROWIRE is supported in
hardware in the COP400, COP800 and HPCTM microcontroller families. MICROWIRE can also be easily implemented on most microncontrollers and microprocessors in software. The TP3064 and TP3065 implement a MICROWIRE
hardware interface to various standard microprocessors.
DISPLAY INTERFACE

NM95C1~ has 8 programmable outputs. The switch
configuration register (SCR) controls these outputs in pairs,
four bits per pair. Table I shows the different switch configurations possible for each pair. In this application we are only
interested in modes 0,1,2 and 3. Because the NM95C12
has a much greater current sinking capability than sourcing
we will configure our LED displays with their cathodes to the
output port. A LOW output results in a lit LED. Figure 1
shows a bar graph display being driven by the NM95C12. A
single resistor SIP can be used to limit the current to the
LEOs. The configuration register looks like Figure 2 with a,
b, c ... h representing the LED segments. To light a particular segment the appropriate bit in the SCR register must be
set to o. This register is set to the contents of the word
stored in the E2PROM's location 61 at power-up. The SCR
register itself is located at address 62 and can be written to
directly without affecting the E2PROM location 61 and the
new contents of the SCR register will be lost on powerdown. At the next power-up the contents of location 61 will
again be stored in the SCA.

iThe

4-80

•

0')
0')

V+ ~

vee

(HP)
HLCP-J 100
14

Vee

DATA OUT ~

M
9
5
C

Vee

1
2

ClK ~

CS
3k
11

GND

TLlD/lllB9-1

FIGURE 1
Switch Configuration Register (SCR)
15

z
)

10
y

6
y

Switch 3

)\.

Switch 4

Switch 2

)
Switch 1

FIGURE 2. SCR Configured to Drive Bar Graph
(a 0 In a, b ..• h turns on appropriate segment)
the battery voltage under 8V to 9V otherwise the LEOs
which should be off will get turned on through the protection
diodes (see modes 12 and 13 of Table I) not to mention the
increase in current discharging the battery. Another approach would be to power the LEOs from the regulated
+ 5V. Now the thing to watch out for is the current limit of
the LM2936; exceeding 65 mA could force the regulator to
go into current limit.

The circuit in Figure 1 uses some tricks to maximize the
battery life. The LM2936 (low dropout; ultra-low quiescent
current 5V regulator) was used to regulate the battery voltage down to 5V for the NM95C12. By bypassing the regulator for the + V connection to the resistor SIP the current
through the regulator only feeds the NM95C12 which in its
quiescent state (with all inputs at CMOS logic levels) is
<50 p.A the dropout voltage of the LM2936 is <0.1V. To
have the LEOs operate correctly it is important to keep

4-81

z•
<

TABLE I. Switch Configurations
t.lODE*

SWITCH CONFIGURATION

~A~B

A=I,B=O

~A ~B

A= 1 , B= 1

COt.ft.lENTS
A=O,B=O

A=O,B=1

A = 0 , B TRI-STATE

I I> ~:

A=B

I ~:

A=B

~A
OB

A = 1 , B TRI-STATE

0
0

I I> ~:

A = TRI-STATE , B = 0

B=A

r;:::

B=A

A = TRI-STATE , B = 1

A~+'
AO

f~~ f~

Anlliog Switch
Open

Anlliog Switch
Closed
TL/D/11189-9

'Modes 0 thru 11 are logic level functions. Modes 12 and 13 are Analog switch functions.

4-82

All the circuits in this application note use very low current
Hewlett Packard displays (they are specified for operation at
1 mA per segment) to maximize battery life. Other displays
at higher currents can be used but care must be exercised
not to exceed the current capabilities of the LM2936 as well
as the power dissipation capabilities of the NM95C12 especially if the surface mount package is used at higher temperatures. Another side effect of higher currents in the LEOs is
the VOL specification is O.4V at an IOL of 2.1 mA but will rise
with higher IOLS (typically stays well under 1V at 10 mA).

charge-the contents of the E2PROM are not lost. The rechargeable battery could be replaced with a 9V transistor
battery (typical voltage on these is 7V to 8V) which will give
operating life of multiple months if checked only intermittently. No data would be lost during battery changes. Figure
3 shows how the key would be configured using the transistor battery. Table II shows the bit combinations for the SCR
register to generate the digits 0 to 9. Notice with the 7 segment display we no longer can use a resistor SIP because
segment LEOs are all tied to a common cathode. Resistors
in this configuration are available in DIPs as well as SOIC.

Instead of using a bar graph individual LEOs could be used
in much the same manner. The length of bar graph lit or
number of LEOs lit would show the amount of credit remaining. Another approach would be to use a 7 segment display.
Figure 3 shows such a circuit. The button is pressed when
the user wishes to see the display. There is a diode bypass
of the push button switch so the display is active while the
key is plugged into the device under use. The user can monitor his remaining credit while operating the device. The battery is being charged whenever the key is plugged into a
device. If the battery should ever go too low to operate, the
user just plugs the key into a device for a while to re-

Applications desiring two digits (credit can now be displayed
as percent remaining) can be implemented with two
MM74HC4511 display decoder/drivers as shown in Figure
4. The MM74HC4511s have a quiescent current of <80 p.A
maximizing battery life and are available both in DIP as well
as SOIC packages. The MM74HC4511 has a maximum supply voltage of 6V so it should be operated from + 5V regulated supply as shown in Figure 5. Table III shows how the
BCD (binary coded decimal) data is configured in the SCR
register to display the two digits.

TABLE II
15

0 abO 0 c d 0 0 e f 0 0 9 dpl

10 o

o 0

000

o 0

000

o 0

000 000

000

o 0

o 000

o 0

I I

o 0

000

o 0

000

o
1o o

o 0

I
I

000 0 0 0 0 0 0
0

000 0 0 0 0 0 0

o 0 0 0

4-83

o 0
o 0

o o
o q

TLlD/11189-3

......

en
en

,...CDCD
Z

TLlD/11262-2

FIGURE 2. JTAG Test Access Port

4-94

Let's consider a typical high density PCB assembly (Figure
3). This assembly requires boundary scan testing, uses ISP

port for an ISP PLD loop and an E2PROM with security for
manufacturing control. The combined test, manufacturing
data and PLD programming requires only 5 access pins.

GALS and implements a serial E2PROM for manufacturing
control data.

Because JTAG test access often requires high speed, this
system has been broken down as two JTAG loops (hence
two TMS pins), one high speed dedicted to the test loop and
a slower speed loop dedicated to E2PROM and PLD access
through the COP 822. The speed of this JTAG loop is limited by COP processing speed in translation to MICROWIRE.

All 3 functions require a serial access scheme. If each is
considered independently, a considerable number of pins
would have to be dedicated to these functions (at least 12
connection points). One common bus and a common protocol to access management information, provide test access,
and perform incircuit PLD programming would be ideal.

This approach represents a solution for common access
using devices available today. As standards take hold (like
JTAG) then non-volatile memories and ISP PLD's may appear supporting a standard serial protocol and further reducing the overheads in a common access scheme.

AN EXAMPLE COMMON ACCESS SYSTEM
The circuit of Figure 3 uses a COP 822 microcontroller to
create a JTAG to MICROWIRE converter with added sup-

93CS46
Tt.lSO
Tt.lS1
TOO
TOI
TCLK

CS
01

PRE

G1
COP
822
L7

OCLK

SOl

t.lOOE

SOO

......-- DCLK

SOl

t.lOOE

SOO

DCLK

SOl

t.lOOE

SOO

TOI
TCLK

Tt.lS

TOO
ASIC

TOI

Tt.lS

TOO

I
I

ISP
GAL

TOI
TCLK

Tt.lS

TOO
I
I
I

18JXXX

ISP
GAL

ASIC

---

J
'"---

TCLK

ISP
GAL

I
I

TO OTHER JTAG
TESTABLE OEVICES
TL/D/11262-3

FIGURE 3. Common JTAG Access for Test, ISP, and Manufacturing Control

4-95

National Semiconductor
Application Note 790
Harry W. Lewis

NM95C12 EEPROM
Controls Amplifier Gain
BACKGROUND

converter is rated 0 -+ 5V, a gain of 25 in front of the AID
will give the full resolution over the reduced range. Additionally, the input range can be offset from zero. While many
AIDs have range and offset options, there are limits if the
accuracy is to be kept. A circuit to use both scaling and
offset is Figure 2. The gain and offset are mostly determined
by the reference and the resistor ratios.

Electrically Erasable PROM or EEPROM finds wide application in analog data acquisition. When using sensors, some
possibilities include storing calibration constants (gain, nonlinearities, temperature effects and offset), the engineering
units of measurements, and even keeping serial numbers. In
Figure 1 for example, after an AID converter converts the
analog sensor output, the processor can use correction factors from the EEPROM to get a final value. By keeping
these corrections with the sensor assembly, one can effectively get a more accurate sensor.

V(AlD) = VIN (1 + R3 • (R1 + R2)/(R1 * R2»
- VREF * R3/R1
Common metal film resistors are widely sourced and have
good temperature coefficients. Type RN55 T-2 are rated at
± 50 ppml"C. The difficulty comes with their resistance
specification of ± 1%. Since most gain stages require at
least 2 resistors to determine gain, the system accuracy is
already reduced to, at best, 2%. Multiple stages and other
error sources compound the problem. Some 10-bit serial
AIDs have 0.1 % accuracy! Even the lowly 8-bit converter
can be %%. For the circuit in Figure 2, EEPROM is a very
handy way to store the calibration of the low cost resistors
to get more of the full accuracy capability of the AID. Even
when not using a sensor, EEPROM can be useful for calibrating a scaling and offset circuit. This is especially true
now that low cost AID converters have gotten so accurate.

There are several ways to achieve a wide input range when
required. One way is to use an AID with more bits than
needed and then use the extra bits for ranging. In other
words, if 8 bits are needed for the output by using a 10-bit
converter a full scale resolution of 8 bits is still provided
even if the input range is only % of the converter range.
This can get expensive quickly since the price of accurate
AIDs goes up substantially with the number of bits! Even so,
with advances in audio parts of 16 to 18 bits, this could be
viable in some instances.
A more common way to cover wide range inputs is to scale
the incoming levels to close to the maximum rated input
range of the AID. If the input range is 0 -+ 0.2V and the

LM34
TEMP
SENSOR

I---

SENSOR OUT PUT

INSTRUMENT
PRESSURE
SENSOR

~
~

/CS
"---

2 CHANNEL
SERIAL
A/D

DATA OUT
DATA IN
CLOCK

CONDITIONING

EEPROM
CS

TL/D/11263-1

Full Scale (5V) = 4720 PSI
Zero (OV) = -83 PSI
Temp Coefficient = +0.2 PSII"F
Serial # = 184625
Last Rev = F

FIGURE 1. Sensor with Digital Output and Correction Factors

4-96

VIN

=0.2 -- 0.6V

>---------f

VOUT

=V AID =0 -- 5V

.......

VA D

R4
10k

VREF
Lt.l385BXZ-2.5

105k

TL/D/11263-2

VOUT

= V AID = VIN

( 1

R3(RI + R2))
(Rl· R2)

R3
Rl

-VREF

= 12.5· VIN - 2.5V

FIGURE 2. Scaling and Offset Circuit

general input and output, to set gain controls, and to drive
analog multiplexers. In Figure 5, the port of U4 selects the
input channel of the AID via the multiplexer U3. Input channel7 has a selectable gain preamplifier (U1) whose gain is
controlled by U2 selecting the proper feedback tap. The
resistor values for R1, R2, R3 and R4 are standard 1 %
values. Ideally the values would be 48K, 12K, 3K and 1K.
Although they are not quite correct for the gains desired,
calibration values stored in the EEPROM can correct for this
while fixing the other errors. One thing to keep in mind when
selecting the standard values, make sure the AID stays in
its active range during the whole range of expected signal
input. If the A/D needed to exceed the maximum count, the
error generated is not correctable. This implies making the
gains on the low side.

DON'T BE A DIP

For storing data, EEPROM can generally beat DIP switches.
However, there were some other things that DIP switches
could do better. One case was having external access to
logic levels without needing an additional port chip. Another
area was switching analog voltages. To replace an analog
DIP switch, a designer often had to add an output port and a
separate CMOS or other switch to do the actual switching.
The NMC95C12 1024-bit CMOS EEPROM with DIP
switches attacks both these areas. When first glancing at
the data sheet, the title "EEPROM with DIP switches" can
conjure up visions of the data being stored in 1024 tiny
levers on top of the package! Of course that is not the case,
see Figure 3 for the real block diagram. Actually the part has
61 words of 16 bits of EEPROM for general use. That totals
976 bits. The DIP switches referenced in the title are 8 pins
with switch logic to allow several different modes of operation as controlled by the switch configuration register. There
is a nonvolatile Initial Switch Setting Register of 16 bits.
And, finally, a Switch Readback Register allows the pins to
be used as a digital input port. Processor interface is by a
serial MICROWIRETM port.

MODES 12 AND 13?

Mode 12 is an open (10+ MO) between pins A and B.
Mode 13 is an ANALOG short (2000 or less) between the
same pins. In Figure 6, analog switches give variable gains
and do analog multiplexing. Switches 1 and 2 select the
input to the AID. Switches 3 and 4 control gain. Although
the pins used for a closed analog switch can not be read as
an input, the input function of the Switch Readback Register
will still work for the other pins, so mixed analog and digital
operation is possible. Of course, errors in the amplifier gains
will be corrected by storing calibration constants in the
EEPROM section of the part.

THE BIG SWITCH

Switches are the main difference between the NM95C12
and other EEPROMs. They can be thought of as four independent switches each having two pins, A and B. Each
switch has four control bits labeled W, X, Y and Z to set it to
one of its 14 modes. Table I shows all the modes. The
Switch Configuration Register (SCR Figure 4) is 16 bits long
to hold all four bits of each of the four switches. It is not
made from EEPROM cells so it can be written faster and
there is no wearout mechanism. Being volatile, the SCR is
reloaded at each powerup from the EEPROM Initial Switch
Setting Register.

FINALLYI
The NM95C12 can accomplish what a DIP switch used to
do without the extra parts. You have external access to logic levels and you can even switch analog voltages. All without needing additional port or multiplexer chips.

WHERE DID THE PARALLEL PORT COME FROM?

Switch modes 0-3 allow the 2 pins to be digital outputs.
When bits Y and Z are set to 0, A = X and B = W. Other
modes allow A and/or B to be TRI-STATE® for use as digital inputs or I/O. Figure 5 shows the switches being used for

4-97

o
en

......I
Z

Table I. Switch Configurations

--oB

A=O,B=l

Et>---oA

A=l,B=O

Et>---oA

Er>--oB

A= 1 , B= 1

~A
0

COt.4t.fENTS

A = 0 , B TRI-STATE

I [>

A=B

I [>0 ~:

A=B

Er>--oA
OB
0
0
OA

A = 1 , B= TRI-STATE

A = TRI-STATE , B= 0

I [>. ~:

B=A

I ~:

B=A

A = TRI-STATE , B= 1

Ao-p~,
AO

!'~~

Anlliog Switch
Open

Anlliog Switch
Closed
TL/D/11263-3

• Modes 0 thru 11 are logic level functions. Modes 12 and 13 are Analog switch functions.

4-98

l>
Z

•
.....
CD

Address,

PROGRAI.HAING
&:
POWER UP
CIRCUITS

E2 PROI.4
61 WORDS x16 BITS

6'0

A2
B2

0::

C
C

83
01
DO
S K - - -......

C S - - - - -....

B4
TL/D/11263-4

FIGURE 3. Block Diagram

I z I y I x I W I z I y I x I W I z I vi x I W I z I y I x I W I
SWITCH 4

SWdCH 3

SWITCH 2

swiTCH 1

TL/D/11263-5

FIGURE 4. Switch Configuration Register (SCR)

•
4-99

U3
~----------------~---------------------4XO
~--------------------------------------~Xl

~---------------------------------------4X2
~------------------------------------~X3

PULSE WIDTH

AID

~----------------------------------------~X4

~---------------------------------------4X5

CONVERTER

OUT

~----------------------------------------~X6
......- - - - - - - -...... X7
,..-----1INH
A
8
C
4051
t.fICROWIRE
INTERFACE

U4
Rl
47.5k

XO
XI
X2
X3
YO
Yl
Y2
Y3
INH
A
8

AV= 1
AV=4
AV= 16
AV= 64

81
Al
EXTRA I

R2
12.1k

82
A2
83
A3

R3
3.01k

EXTRA I
EXTRA I

a
a

R4
lk

DI
CS
SK
DO

84
A4
Nt.t95C12

4052
TL/D/11263-6

FIGURE 5. Using NM95C12 Switches as Digital 1/0

4-100

l>
Z

.....
CD

RANGE = 0 -- 2.5V

t.lICROWIRE
INTERFACE

TLlD/11263-7

FIGURE 6. Using NM95C12 Switches as Analog Switches

4·101

Stand Alone Control of
MICROWIRETM Peripherals
Using the NMC87C257

National Semiconductor
Application Note 791
Charlie Mitchell

INTENT

fresh next state logical determination takes place. One way
of implementing this state sequencer is by utilizing a register
or latch as the memory element and a Read Only Memory
to supply the logic function for the next state. Because a
ROM is a "rectangular" or complete logic array (Le., for every input combination there exists a unique output), this next
state logic is a lookup table.

This note describes the implementation and use of a standard memory element in the realization of state machine
control for the purpose of generating serial data. The applications shown here employ serial data streams to control
and program peripheral devices which would otherwise require CPU support for use.
The benefit to the user of the demonstrated techniques is
the low cost, low effort, implementation of tasks normally
allocated to more sophisticated and more engineering intensive methods. These solutions expand the range of systems
and applications in which a variety of National Semiconductor's MICROWIRE devices may be used.
MICROWIRE

The MICROWIRE standard is an interface technique first
developed at National in the 1970's in an effort to reduce
the component pin count (and hence package size and
cost) required for the interfacing of microcontrollers to peripheral components. Over the ensuing years a wide variety
of devices employing this interface technique have been introduced to the market. They include display drivers, analog
to digital converters, phase lock loop frequency synthesizers, memories and complex analog devices. A full list of all
but the most recent devices using the MICROWIRE interface can be found in the Master Selection Guide.
A MICROWIRE connection is a straight forward serial hookup consisting of data and clock. Generally, input and output
data are presented on separate lines. The clock to data
relationship resembles that of a TTL or CMOS 7400 series
shift register with the positive edge of the clock performing
the active transfer of data into and out of the device. Care
must be taken to examine the data sheet for a device under
consideration as there may be deviations from this general
description. A more complete description of this interface
method is available in National Semiconductor Application
Note 452 by Abdul Aleaf.
STATE SEQUENCERS

State machines or sequencers in their simplest form consist
of a current state memory element and a next state determination network. Upon a clock edge the next state information is converted and held as a new current state while a

THE NMC87C257 UV ERASABLE CMOS PROM
WITH LATCHES

The NMC87C257 is a device first conceived to reduce the
chip count in microprocessor systems which had a multiplexed address/data bus. As such, the latches required to
capture the address while return data occupied the bus
were put on board the device. Intended for this microprocessor application, the NMC87C257 does not have the
speed of some of the bipolar "logic" PROMs (nor the power
dissipation), but it's large memory array would be exceedingly expensive in a bipolar device. The 32k x 8 memory
means that in a state machine application fifteen inputs can
define over 32,000 states, represented in eight output pins.
GENERATING A SERIAL OUTPUT WORD FROM THE
NMC87C257 BASED STATE MACHINE

Figure 1 depicts a state machine capable of generating 128
different 128-bit serial data streams. DIP switches 0-7 select the specific data stream program. Seven bits of output
data are fed back to inputs to define the next state in the
serial data sequence. Bit 08 is the serial data output. A
CMOS oscillator generates the clock. It is important to note
that the clock drives both the ALE (Address Latch Enable)
and OE (Output Enable) inputs. ALE is the signal which activates the "open" state of the input latch, as such, unlike an
edge triggered register, the outputs follow the inputs until its
(ALE's) fall. To avoid a high speed feedback phenomenon
while the latches are open it is necessary to break the feedback loop and "freeze" the data at the desired output/input
state. This is accomplished by disabling the TRI-STATE®
outputs. As long as the outputs are loaded only by the high
impedance inputs of the CMOS device, the next state information will be transferred into the latches. Resistive or bipolar logic loads should not be attached to lines operating in
this manner.

4-102

»
z

"'CD"
.....

~89~~AU-02:---------00~~

01~

6 A3
s A<4
L....._ _ _ _~. AA 5
6
•

r-------------------------------------~2~A7
r -__________________________

A8
A9

~----------------------~2~~~
A12

Nt.tC87C257

Q
20k

18
19

serial output

~ ~22
CE

r-----,---.J--~:.r~ ~~!
Vee

I-M-

p.12-,

1
ALE

..>~

TLlD/11274-1

Note: Refer to AN 140 for R & C values.

FIGURE 1. State Machine for Serial Word Generation
TABLE I. PROM Addresses and Data
Address

Data
(7 Bits)

Serial
Output

nn7F

nnOO
nn 01

01
02
84
03

1
1
0
1

nn02

nn 84

•
•
•
•
nn 7E

Comments
Startup Address Generates
1st Word

Loop to Self - Stop

APPLICATIONS FOR A SERIAL WORD GENERATOR
USING THE NMC87C257

Table I shows an example of the PROM code which generates the serial output. The address includes a leading byte
"nn" which will determine which of the bit streams will be
selected. Notice that the 7-bit data is in fact the next state
information reflected in the next address.

A Power Supply Sequencer
The ADC0854 is a comparator circuit with a MICROWIRE
controlled four input multiplexer and a settable 8-bit reference divider which drives the second compare input. A
block diagram is depicted in Figure 2.

4-103

AN-791

~1
ClK11- -

DI..!!
NOTE 1

Vee

: I. It ~

Nm,l:: :t:~ ~ t
CH3 5 I

• I , I I

0
EOC.

!o
"""

•

JL
PARAllEL
XFRTO
LATCH

. •.

ANALOG
MUX
(MUX CODE 0, D, 0)

~R~"Jr~~Al

7V ZENER

INPUT

':'

TO
INTERNAL
CIRCUITS

"'Nt.
LADDER AND DECODER

,
':' AGND

BV~30V

7
DGND ] . ,

VREF 9

INPUT PRDTECTION-AlllOGIC INPUTS
TU0111274-2

Note 1: For ADC0852; 01 is input directly to the 0 input of ODD/SIGN, select is forced to a "1", ~ND and COM are internally tied to DGND, only Vee is brought out, VREF is internally tied to Vee, only CH2 and CH3 are brought out.

FIGURE 2. ADC0854 Detailed Block Diagram

Many voltage regulators feature an on-off input. Couple
these linear components along with the serial word generator and a sophisticated power supply sequencer can be
built.

parator from the voltage sources, in this case Simple
Switcher™ Regulators are used.
The serial word is presented to the ADC0854 is generated
from the sequence shown in Figure 5A. The Chip Select
input which acts to latch the data word into the comparator
is generated by a diode AND gate from the four output/input
lines controlling the count. All diodes depicted in the schematic are in a single FSA2619P 16-pin dual-in-line package.
An MM74C14 hex Schmitt trigger circuit provides the necessary clock wave form and an MM74C244 contributes buffering for the diode gates.

The ADC0854 requires a 12-bit serial word to provide setup
information. A start bit is required, which is followed by one
bit to select four single ended or two differential inputs. A
two bit channel selection and the eight bit reference data
byte complete the serial word. It is depicted in Figure 3.
Referencing the simplified schematic in A'gure 4, analog input signals are presented to the multiple inputs of the com-

»
z

......

CD
.....

CLK

AOC0854 {Ol

r-~-PR:OGRj\M MIUX--+------PRO~~RAMI

THRESHCILO V T H - - - - - - + - l

_.... DO ENAI!LEO BUT INVALID

. ~·t ----~----.:....--~~!....-----------~~~~c:D~:§~::)
11

Note: Valid Output can change only on Falling Edge of elK.

TL/0/11274-3

FIGURE 3. ADC0854 Clock, Control Data and Output Data Relationships

II
4-105

AN·791

20kll
2

!
2

.-4

74C14

74C241

I
1

I
U2
AO
9 AI
8 A2
7 A3
6 u
AS
A6
A7
A8
2
A9
2
Al0
2
All
A12
A13
A14
I

20kll
ON/orr

~
!o

I...L
I .....
I .....
I .....

<»

-J

Vee

00
01402
13
03
15
04
16
OS
17
06
18
07
19

~
I.....
I .....

,i,'0 p r

~1I74C14

ALE

(2)

CHI 3

CH2 4

10 DO

CH3 5

COli

..L-

13 V.

ACNO

,!-

OGNO
IAOC0854

VREr 9
2

-:L
-

(1)

:..

14 Vee

NIIC87C257

74C2U
(2)

CHO 2

~ Cs

"-f

~~
CE~

IU2
12 01

(1)

-: r- adj

LII385

3
(2)

(1)

""I

-==

ON/orr
vout:

• Yin
Simple Switcher

Unregulated _
Input L...-.,.;l
Power

• ON/Orr
Vout

I Yin

Simple Switcher

_IL
• ON/Orr
Vout

I Yin
Simple Switcher

I
1

Vout B

Vout A

Vout C

T
TUD/11274-4

Note: Refer to AN 140 for R & C values.
Note: As resistive and capacitive values in this circuit will vary with application, consult the datasheets of the associated devices for component selection.

FIGURE 4. Partial Schematic of Power Supply Sequencer

Each regulator output is sequentially selected by the PROM
generated MICROWIRE and tested for compliance to a voltage level also set via the MICROWIRE. When Voltage A
reaches its terminal value, the sequencer delays for a defined period while voltage settles as determined here by the
RC network at the comparator input and then raises the
control voltage to the regulator B ON/OFF input and, after
monitoring that regulator's voltage rise, continues to regulator C. A stable and fixed reference is supplied for the comparisons by an LM385.

three supply voltages. A drop from the proper sum will commence the controlled shutdown. These procedures are delineated by the state diagram in Figure 5b. In order to differentiate the state defining the condition of the voltages when
powering up and the state produced when shutting down a
"history circuit" consisting of four diodes and a capacitor
records the "all supplies on" condition. The ON/OFF switch
must be recycled for the system to power up once again.
A Zener diode regulated output is provided from the
ADC0854 permitting the PROM and the Schmitt Trigger oscillator to be powered from the primary source.

A similar control procedure allows an orderly shutdown.
During operation the controller monitors the sum of the

SI.lo Number Ooflnilion
Bill 0 - 2 =Oulpul Vol log .. 1 - 3
Bill 3 - 5 = Input Conlrol Signolo 1 - 3
:::

~:g~/g~;~~~t~h'~~~~IPUI~

=r=======-.J

L,b IrL
bbbbbbb

.h =hlslory bll

h= 1

01111111
Swllch Off

Figure 4A

TL/D/11274-5

FIGURE 5. State Diagram for Power Supply Sequencer

4-107

~ r---------------------------------------------------------------------------------------~

en
.....
z•
--

1
PR

_22

Q6
74HC74

9
74HC02

clock

slrobe

XI
Vee
TL/D/11274-7

FIGURE 7. Logic Diagram for Equalizer Controller
4-110

:J>
Z

•
......

clock input

..10

clock

rl.-

prestrobe

r
Lr

data
strobe

J
r
strobe

IIIIIIIIIIIIIIIIIIIIIIIIIIIII
w

data
10
Data
Prestrobe
Address --"'\
00
01
02
03
04
05
06
07
OB
09
OA
OB
OC
00
OE
OF'
10
11

12
13
14
15
16
17
18
19
lA
lB
lC
10
IE
IF'
20
21
22
23

\ \
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
0
1

b
b
b
b

R
R
X
H
0
9

9
9

9
9
9
B
L
0
b
b
b
b

R
R
X
H
a

24
25
26
27
28
29
2A
2B
2C
20
2E
2F'
30
31
32
33
34
35
36
37
3B
39
3A
3B
3C
3D
3E
3F'
40
41
42
43

44
45
46
47

1
1
1
I
1
1
1
0
I
1
I
1
1
1
1
1
0
1

1
1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
0
1

b
b
b
b

R
R
X
H
0

9
9
9
9
9
9
B
L
0
b
b
b
b
R

R
X
H
0

4B
49
4A
4B
4C
40
4E
4F'
50
51
52
53
54
55
56
57
5B
59
5A
5B
5C
50
5E
5F'
60
61
62
63
64
65
66
67
6B
69
6A
6B

b
b
b
b

R
R
X
H
a

9
9

9
9
9
9
B
L
0
b
b
b
b
R
R
X
H
0

6C
60
6E
6F'
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F'
80
81
82
83
84
85
B6
87
BB
89
8A
8B
8C
BO
8E
8F

b
b
b
b
R
R
X
H
a

9
9
9
9

9
9

B
L
0
b
b
b
b
R
R
X
H
0
9
9
9

9
9
9
B
L
0

90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9[
9F'
AO
Al
A2
A3
A4
A5
A6
A7
AB
A9

AA
AB
AC
AD
AE
AF'
BO
Bl
B2
B3

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
I
1
I
1
0
1
1
1
1
1
1
1
1

0
1

B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF'
CO
Cl
C2
C3
C4
C5
C6
C7
CB
C9
CA
CB
CC
CD
CE
CF'
DO
01
02
03
04
05
06
07

DB
09
OA
DB
DC
DO
DE
OF'
EO
El
E2
E3
E4
E5
[6
E7
E8
E9
EA
EB
EC
ED
EE
EF'
Fa
F'1
F2
F'3
F'4
F'5
F'6
F'7
F'8
F9
FA
FB

!} "".,

"I""" bib

R _ _ range, Ch, B
R _ _ range, Ch, A
X _ _ don't care
~--OATA I

g," "I""" bib

B _ _ boost/cut
L _ _ DATA II
a
b
b
b
b
R
R
X
H
0

NEXT AOOR = 00
TL/D/11274-8

FIGURE 8. Template for PROM Program for Filter Controller

4-111

SUMMARY
The use of the NMC87C257 CMOS PROM with latches has
been shown to be an effective element in the implementation of several MICROWIRE interfaces. This use allows the
designer to implement systems with devices necessitating a
MICROWIRE interface without the use of a microcontroller
or microprocessor.

In constructing or adapting any of the circuits described in
this note the reader is advised to obtain copies of the National Semiconductor data sheets for the components included and to review their operation for applicability to their
system requirements.

12.000 r--

r--

9.6000 r-

9.6000

7.2000

4.8000

2.4000

rrrr-

'" I,

7.2000 r4.8000 r-

2.4000 r-

0.0 r-2.400
-4.800
-7.200

-2.400
-4.BOO

-7.200

)

-9.600 t-12.00

0.0

-12.00
100

rr-

-9.600 t-

'--

Jif

10k

'--

SDk

100

10k

SOk

TLID/11274-9

TLIO/11274-10

FIGURE A 1. A Ramp Transfer Characteristic.
Refer to Table A 1 for program Inputs.

FIGURE A2. Vocal Presence Filter.
Refer to Table A2 for program Inputs.

TABLE A1. Program Inputs for
Ramp Transfer Characteristic

TABLE A2. Program Inputs
for Vocal Presence Filter

Frequency (Hz)

Level (dB)

Frequency (Hz)

40
63
100
160
250
400
630
1k
1.6k
2.5k
4k
6.3k
10k
16k

-7
-6
-5
-4
-3
-2
-1
0
+1
+2
+3
+4
+5
+6

40
63
100
160
250
400
630
1k
1.6k
2.5k
4k
6.3k
10k
16k

Level (dB)

o Subsonic Filter
0
0
0
0
+3
+3
+3
+3
+3
+3
o Supersonic Filter
0
0

Figures A 1 and A2 are gain vs. frequency plots of specimen filters realized using the logiC of Figure 7 and PROM code
generated with SM835.c.

4-112

/***************************************************************

*
*
*
*
*

*
File: SM835.C
Author: Bob Moses, Rane Corporation, Mukilteo, WA
Revision: 18 June 1991
Compiler: Borland TurboC

*
*

* Description: Generates Intel Hex file for NMC87C257 based
LMC835 state machine loader.

* File Input: void
* File Output: SML835.HEX

*
*
*

***************************************************************/

#include ·stdio.h·
/*------------*/
1* Data Types */

/*------------*/
struct LMC835_RECORD
{

int
int
int
int

chAbands [7] ;
chArng;
chBbands[7] ;
chBrng;

/*
/*
/*
/*

gains for chan A bands */
chan A range */
gains for chan B bands */
chan B range */

/*--------------------*/
/* Function Prototypes*/

/*--------------------*/
void
void
void
void
void

say_howdy(void) ;
get_parameters(struct LMC835_RECORD *eq) ;
compile_state_mach(struct LMC835_RECORD *eq, unsigned int states[]) ;
output_data(unsigned int states[]);
wr_ihex_data_rec(FILE *outfile, unsigned int addr, unsigned char recsize,
unsigned char data[]) ;

/*--------------*/
/* Main Program */

/*--------------*/
main()
{

/* declare one LMC835 equalizer */
struct LMC835_RECORD eql;

4·113

.,..
~

/* 14 bands * 2 blocks/band * 9 states/block + tinal state
unsigned int states[253];

:i•

= 253

states */

say_howdy () ;
get_parameters (&eql) ;
compile_state_mach (&eql, states) ;
output_data(states) ;

/*------------*/
/* Functions */
/*------------*/
void say_howdy (void)
{

clrscr() ;
tprintt(stdout,"\nSM835 - NMC87C257 LM835 State Machine Loader.") ;
tprintt(stdout,"\n\nThis Program accepts parameters tor an LMC835-based") ;
fprintt(stdout, "\nequalizer and generates an Intel Hex tile ( SML835.HEX )");
fprintt(stdout,"\nfor the NMC87C257 State Machine Loader. This tile can be");
fprintt(stdout,"\nloaded into most EPROM programmers and split-programmed") ;
fprintf(stdout,"\n(even and odd bytes) into two EPROMs.");
tprintf(stdout,"\n\nThe LMC835 graphic equalizer consists of two channels") ;
fprintf(stdout,"\n(chan A & chan B), each channel has 7 bands. The range ot");
fprintf(stdout,"\neach band is selectable tor ± 12 dB in 1 dB steps, or"):
fprintt(stdout,"\n± 6 dB in 1/2 dB steps.\n") ;

void get_parameters(struct LMC835_RECORD *eq)
{

unsigned int i,currng;
int tempint;
char chan;
tloat tempfloat;
/* get range for chan A */
tprintf(stdout,"\nPlease enter range ot chan A (0
fscanf(stdin,"%d·,&tempint) ;
tempint&Ox0001;
eq->chArng

= ±12dB, 1 = ±6dB):

.);

/* get range for chan B */
tprintf(stdout,"Please enter range of chan B (0
tscant(stdin, "%d",&tempint) ;
eq->chBrng
tempint&Ox0001;

4·114

= ±12dB, 1 = ±6dB):

");

/* get EQ bands */
for(i
O.chan
'A'.currng

= 12-6* (eq->chArng) ;i

< 14;)

/* if start of chan B. modify chan flag and chan range variables */
if(i
7)

(

chan
'B';
currng
12-6* (eq->chBrng) ;

/* get a band value */
fprintf(stdout.nGain of chan %c band #%d? ·.chan.(i%7)+1);
fscanf(stdin.n%gn.&tempfloat) ;
/* scale for range */
if(currng
6) tempint
(int) (tempfloat*2.0) ;
else tempint
(int)tempfloat;

/* check limits */
H«tempint > 12)

(tempint < -12))

(

fprintf(stderr.· ••• err! value must be between -%d and +%d\n·.currng.currng);
continue;
/* save band */
H(chan
'A') eq->chAbands[i]
tempint;
else eq->chBbands[i-7]
tempint;
1++; /* band counter */

void comp11e_state_mach(struct LMC835_RECORD *eq. unsigned int states[])
(
LMC835 CONTROL CODES
last bit

1st bit sent

DATA I - - - - - - - - - - - - DATA \I
bit:

*
0

5
rB

o
x

5
g4

be
TL/D/11274-11

4-115

.....
.....

chBrng)&Ox0001) «14) ;
I rA */
(eq-> chArng) &Ox0001) < <14) ;

I don't care */
I 1 */
Ox4000;

4-117

»
z

....,•

....

case 8: /* rest for strobe */
break;
case 9: /* DATA II gO */
stateimg += ((LMC835GainCodeTab1e[eq->chAbands[band]+12]&:Ox0001) < <14) ;
break;
case 10: /* DATA II g1 */
stateimg += ((LMC835GainCodeTab1e [eq-> chAbands [band] +12] &:Ox0002) < < 13) ;
break;
case 11: /* DATA II gO */
stateimg += ((LMC835GainCodeTable [eq-> chAbands [band] +12] &:Ox0004) < <12) ;
break;
case 12: /* DATA II g3 */
stateimg += ((LMC835GainCodeTable[eq->chAbands[band]+12]&:Ox0008) < <11) ;
break ;
case 13: /* DATA II g4 */
stateimg += ((LMC835GainCodeTable [eq-> chAbands [band]+12] &:OxOOl0) < <10) ;
break;
case 14: /* DATA II g5 */
stateimg += ((LMC835GainCodeTable [eq-> chAbands [band] +12] &:Ox0020) < <9) ;
break;
case 15: /* DATA II bc ( 0 = cut. 1 = boost) */
if(eq->chAbands[band] < 0) stateimg &:= OxBFFF;
else stateimg += Ox4000;
break;
case 16: /* DATA II 0 */
stateimg &:= OxBFFF;
break;
case 17: /* rest for strobe */
break;
1* switch... */
/* write this state to states array */
states[curstate++] = stateimg;
/* for(substate ••• */
/* for(band ••• */

/*--------*/
/* chan B */
/*--------*/
for(band = 7;band < 14;band++)
(

for(substate = O;substate < 18;substate++)
(

/* next state = current state +1 */
stateimg = (curstate+l)&:OxlFFF;
/* CLK Enable */
stateimg &:= OxDFFF;

4·118

1* Prestrobe

i f ( (substate -- 7)

II (substate

-- 16)) stateimg += Ox8000;

/* Data */
switch (substate)
(
case 0: /* DATA I bO */
stateimg += (( (band+1) &Ox0001) < <14) ;
break;
case 1: /* DATA I b1 */
stateimg += (( (band+1) &Ox0002) < <13) ;
break;
case 2: /* DATA I b2 */
stateimg += (( (band+1) &Ox0004) < <12) ;
break;
case 3: /* DATA I b3 */
stateimg += (( (band+1) &Ox0008) < <11) ;
break;
case 4: /* DATA I rB */
stateimg += (( (eq->chBrng)&Ox0001) «14) ;
break;
case 5: /* DATA I rA */
stateimg += (( (eq->chArng)&Ox0001) «14) ;
break;
case 6: /* DATA
don't care */
break;
case 7: /* DATA I 1 */
stateimg += Ox4000;
break;
case 8: /* rest for strobe */
break;
case 9: /* DATA II gO */
stateimg += ((LMC835GainCodeTab1e [eq-> chBbands [band-7] +12] &Ox0001)
break;
case 10: /* DATA II g1 */
stateimg += ((LMC835GainCodeTab1e [eq-> chBbands [band-7] +12] &Ox0002)
break;
case 11: /* DATA II g2 */
stateimg += ((LMC835GainCodeTab1e [eq-> chBbands [band-7] +12] &Ox0004)
break;
case 12: /* DATA II g3 */
stateimg += ((LMC835GainCodeTab1e [eq-> chBbands [band-7] +12] &Ox0008)
break;
case 13: /* DATA II g4 */
stateimg += (( LMC835GainCodeTab1e [eq-> chBbands [band-7] +12] &Ox0010)
break;

4-119

< <14) ;

< <13) ;

< <12) ;

< <11) ;

< < 10) ;

....
G)

.....•
z

case 14: /* DATA II g5 */
stateimg +=( (LMC835GainCodeTable [eq-> chBbands [band-7]+12] &:Ox0020) < <9) ;
break;
case 15: /* DATA II bc ( 0 = cut, 1 = boost) */
if(eq->chBbands[band-7] < 0) stateimg &:= OxBFFF;
else stateimg += Ox4000;
break;
case 16: /* DATA II 0 */
stateimg &:= OxBFFF;
break;
case 17: /* rest for strobe */
break;
1* switch... */
/* write this state to states array */
states[curstate++] = stateimg;
/* for(substate ••• */
/* for(band ••• */
/* final state: "jump 0" with clock disabled */
states[252] = 252+0x2000;

void output_data(unsigned int states[])
unsigned int i,addr,bitmask;
unsigned char csum,data[16] ;
FILE *outfile;
/* open output file */
if((outfile = fopen("sm1835.hex","w"»

== NULL)

(

fprintf(stderr, "can't open file SML835.HEX") ;
exit (0) ;

/* write states to stdout */
/*------------------------*/
for(i = O;i < 253 ;i++)
if(i == 252) fprintf(stdout,"\n\nFinal state ••• ");
else if (!(i&:18» fprintf(stdout, "\n\nBand %d ••• ",(i/18)+1);
fprintf (stdout, "\nState %d: ", i) ;
/* write each state as a binary image */
for(bitmask = O;bitmask < 16;bitmask++)
{
i f ( (states [i] < >8) &OxOOFF) ;
wr_ihex_data_rec (outfile ,252*2,2,data) ;
/* EOF record */
fprintf(outfile,"\n:00000001FF") ;
/* close file */
fclose (out file) ;

void wr_ihex_data_rec(FILE *outfile, unsigned int addr, unsigned char recsize, unsigned char
data[] )
(

unsigned int i;
unsigned char csum;
/* record mark, record length, record address, and record type fields */
fprintf(outfile;"\n:%2.2X%4.4XOO",recsize,addr) ;
csum = recsize + (char))addr&OxOOFF) + (char) ((addr»8)&OxOOFF);
/* data field */
for(i = O;i < recsize;i++)
{

fprintf (outfile, "%2. 2X", data[i]) ;
csum += data[i] ;

/* checksum field */
csum &= OxOOFF;
csum *= -1;
fprintf (outfile, "%2.2X", csum) ;

II
4·121

,..
0)

.....•
Z

National Semiconductor
Application Note 792
Sean Long

NM95C12 Applications in a
PC-AT® Ethernet® Adapter

CD
N

INTRODUCTION

SYSTEM DESCRIPTION

This application describes a typical Ethernet adapter card
designed to be plugged into a PC-AT expansion slot. The
board is designed around the National Semiconductor
DP83932 SONICTM Network Controller device. This application note will detail the system design and focus on the
functions performed by the NM95C12 EEPROM.

The network controller card has been designed to meet the
following specifications:

This application note assumes that the reader is familiar
with the PC-AT architecture, the DP83932 device, the
NM95C12 EEPROM and designing with GAL~ Programmable Logic Devices (PLDs).

• Designed around high performance 32-bit DP83932
Ethernet Controller
• 16-Bit bus master operation to give higher performance
• Fully software configurable (no jumpers or mechanical
DIP switches)
• Extensive test and configuration capabilities
• Supports different media interfaces
• Bootrom option
The system block diagram is shown in Figure 1.

DATA BUS 0(15:0)
DATA BUFFER

ADDRESS BUS A( 11:0)

OUTPUT PORT
3 BITS

BD(15:0)

p
C

NWI~C12

EEPROW

SA(1I:0)

A
T
S
L
0
T

NSBHE
NWERO
NWEWR

IRQ

','.10,11,12
DACK

',5,',7
DRQ
WULTIPLEXER

ORO
4,5,',7

0(7:0)

CONTROL BUS

TLlD/11265-1

·Denotes an active low signal.

FIGURE 1. System Block Diagram

4-123

en
....

oCt

r------------------------------------------------------------------------------------,
nals from the NM95C12. The outputs from the GAL20V8 are
the various chip select signals for the memory and I/O
ports. The system address bus transmits the current address value and the MI -10 signal determines if a memory
or I/O cycle is in progress.

FUNCTIONAL DESCRIPTION OF THE BOARD
The system contains the following logical functions:
1. Network controller (DP83932)
2. Cable interfaces
3. Busmaster interface logic, including data and address
buffers

Address lines AO-A19 allow up to 1 Meg (O-FFFFF) of
memory to be addressed, while address lines AO-A 15 allow
up to 64K (O-FFFF) of I/O ports to be addressed. If the
control signal MI -10 is logical "1 " (high) then the processor is performing a memory cycle and if the MI - 10 signal is
logical "0" then an I/O cycle is in operation.

4. EPROM option for remote boot loader
This system uses both the EEPROM locations and the
switch logic terminals of the NM95C12 to perform various
functions within the system as detailed below.

For a PC-AT various memory and liD locations are reserved for standard functions such as system memory and
liD (refer to PC-AT documentation to determine which
memory and I/O locations are free for add-in boards).

FUNCTIONAL DESCRIPTION OF NM95C12 EEPROM
Use of the Switches:
The switch terminals of the NM95C12 EEPROM are used as
part of the memory map address decoding and the liD map
decoding circuitry, feeding as inputs to a GAL20V8 which
performs the address decoding logic from the system address inputs.

The switch outputs from the NM95C12 are connected as
inputs to the GAL address decode logic and are used to
determine the base memory and liD locations for the add-in
card. Figure 2 shows the typical use of a GAL for address
decoding.

The NM95C12 switches control:
1. The base liD address of the network controller board.
2. The base memory address of the bootrom EPROM option

The advantage of using a PLD for the address decoding is
that it is an easy way to implement different address decode
functions by logic equations. The logic equations can be
implemented with a standard PLD design compiler such as
OPALTM from National Semiconductor or a third party software package such as ABELTM from Data liD. The PLD
compiler will take the logic equations and convert them into
the GAL fuse map which can be used for programming on a
wide range of device programmers. A typical set of logic
equations using National Semiconductors OPAL software
package is shown in Figure 3.

on the board.
ADDRESS DECODING
The address decoding is controlled by a GAL20V8 PLD (refer to the 1990 National Semiconductor PLD Databook and
Design Guide for further information) as shown in Figure 2.
The inputs to the GAL20V8 are the system address lines,
the memory and liD control signals, and the switch termi-

GAL20V8
SO
S1
SWITCH
INPUTS
FROt.!
Nt.!95C12

CHIP SELECT OUTPUTS

S3
S4

BOOTROM

PORTPAGE

ADDRES; BUS
I

M/NIO

TLID/11265-2

FIGURE 2_ Address Decoding

4-124

BEGIN HEADER
TITLE
Address decoding for PC AT Ethernet adapter card
PATTERN Addr_Dec
REVISION Rev 0
AUTHOR
Dave Engineer
COMPANY National Semiconductor
DATE
June 1991
Everything in the header command is copied directly into the JEDEC map as a comment field for
easy documentation
END HEADER
BEGIN DEFINITIONS
device G20V8:
inputs sO, sl, s2, s3, s4, s5:
inputs m_-io, aO, al, a2, a3, a4, a5;
outputs (com) bootroom, portpage;
{ OPAL will perform automatic pin assignment
set ioselect=[s2,sl,sO], memselect=[s5,s4,s3];
set address=[a5,a4,a3,a2,al,aO];
END DEFINITIONS

specify the device used
define the inputs }
{define the outputs}
{ define the switch sets

BEGIN EQUATIONS
{
ft
/
ft = logical NOT function
(i.e. logical 0)
ft
&.ft = logical AND function
a + n = logical OR function }
if m_-io is logical 0, then decode switch set s2, sl, sO and address lines for the various
base I/O locations.
Refer to PC-AT system I/O address map before selecting free I/O ports, the decodes shown are
for example only - change for specific applications as required. }
bootrom = /m_-io &
(ioselect __ 0) & (address __ jhOO)
+ (ioselect __ 1) & (address __ jhOl)
+ (ioselect __ 2) & (address __ jh02)
+ (ioselect __ 3) & (address
jh03)
+ (ioselect __ 4) & (address __ jh04)
+ (ioselect __ 5) & (address __ jh05)
+ (ioselect __ 6) & (address -- jh06));
{ if m_-io is logical 1, then decode switch set s5, s4, s3 and address line for the various
base memory locations.
Refer to PC-AT system I/O address map before selecting free Memory locations, the decodes
shown are for example purposes only - change for specific applications as required. }
portpage = m_ - io &
(memselect __ 0) & (address __ jh18)
+ (memselect __ 1) & (address __ jh20)
+ (memselect __ 2) & (address __ jh28)
+ (memselect __ 3) &: (address __ jh30)
+ (memselect __ 4) & (address __ jh38);
END EQUATIONS
FIGURE 3. GAL® Logic Equations
USE OF THE NM95C12 EEPROM LOCATIONS

4. Two locations are used to store information about the
production flow of the board e.g.; the version number of
the out-going inspection, and serialization program which
stores a unique ethernet address in the EEPROM.

1. Three locations are used to store the ethernet address of
the card.
2. One location is used to store the interrupt number and
the DMA channel of the board.

5. There are also some EEPROM locations used to enable
some special features in the network driver such as protocol, DMA priority, etc.

3. One location is used to store the busmaster speed setting
of the card.

4-125

:t>
z

•
.......

CD
N

(\II

Z
THAT 40

.FCRV1
DO WRITE TO EE-PROM

••••

; (2 BYTE SUCCESSIVE WRITE)
SBIT 0,
LD B,
RBIT 2 [B],
JSRSTACON
JSRWAIT

TLlD/11268-8

•
4-131

....en
I

4USEC
; SWITCH ALSO SDA LOW

t\QJ
t\QJ

RBIT 3,
RBIT 2,
.FORM
LD A, [B]
RRCA,

X A, [B]
DRSZBITCO
JP LOPA1,
LD A, [B+J,
IFBIT 1,
JMP,

RAG
GETDAT

JSRACK,
IFBIT 0,
JPCEC1,
IFBNE
JMP LOPA,
RET

#04

CEC1:
IFBNE,
JMP LOPA,

#06

RAG

; ROTATE BYTE ONE
; BIT POS. RIGHT
; AND SAVE
; CHECK IF 8 BITS
; SHIFTED
; DECREMENT 8
; CHECK IF READ
; 3RD BYTE IS NEXT?
; IF SO, THEN READ.
; GET ACKNOWLEDGED
; WHEN 8 BITS ARE
; SHIFTED.
; CHECK IF READ
; OR WRITE OPERATION.
; ON READ (HERE)
; IF NOT 2 BYTES YET
; AFTER EE·ADDRESS AND
; WORD ADDRESS ARE SHFT.
; 1ST AND 2ND DATA·
; BYTE (3RD + 4TH)
Tl/O/11268-9

4-132

....

; NSEC TO PROPERLY
; ERASE WRITE.
LD
LD
LD
LD
LD
LD

B,
[B-],
[B-],
[B-],
[B],
B,

#EEDAT2
#078
#056
#OEO
#025
PORTLD

; INIT RAMS
; ANOTHER 2 BYTES
; OF FIXED DATA
; MIRROR OF #07
; MIRROR OF "AS"
; POINT LPORT OAT REG.

; TO MODIFY "SDA, SCL"
RBIT 2, [B],
JSRSTACON,
JSR WAIT,

; PREPARE FOR START
; CONDITION.
; AFTER WRITE TO EE.
; WAIT FOR> THAN 40
; MSEC TO PROPERLY
; ERASE WRITE .

•FORM
· ••••••••••• ** •••••••••••••••••

; • • •• DO READ FROM EE-PROM ••••
*.

·, ... *.* .. ** ..... *.* .... *.* ....... * •••

(READ 4 SUCCESSIVE BYTES)
RBIT 0
LD B,
LD [B-],
LD [B],

RAG
#EEWRD
#OAO
#025

,·

; INDICATE READ
; INIT RAMS
; MIRROR OF #05
; MIRROR OF "AS"

*** •••••• **.** ••••••••••••••••

; •• FIRST 2 BYTES SAME AS IF WRITE ••
· ••••••••••• * •••• *** •••••••••••

LD B,
RBIT 2 [B]
JSRSTACON,

(IN TERMS OF TRNSMIT)
#PRTLD

SBIT 2,
NOP,
NOP,
SBIT 3,
SBIT 1,

PORTLD
RAG

LD B,
LD [B-],
LD [B],

#EEWRD
#OAO
#OAS

RBIT 2, [B],
JSRSTACON
RBIT 1,
JMP INIT
•FORM

PORTLD

; PREPARE
; FOR
; START COND.
; AND SHIFT 1ST
;2 BYTES.
; PREPARE FOR
; ANOTHER START; CONDITION,
; SDA HIGH FIRST.
; INDICATE THAT
; 3RD BYTE IS NEXT
;INIT RAMS
; MIRROR OF #05
; MIRROR OF "AS"
; PERFORM ANOTHER
; START

RAG
; CLOSE THE LOOP WHEN
;FINISHED
TLlD/11268-14

4-133

~ r---------------------------------------------------------------------------~
Q)

1'0

:2:

oct

STP:
SBIT 3,
NOP,
SBIT 2,
RET,
•FORM

;* *

PORTLD

; ESTABUSH STOP; CONDITION

PORTLD

GET 8BIT OF DATA FROM EE-PROM * *

.- * •• _ •• '* ••••

*.- ... _.... - '*.- '*.*

GETDAT:
JSRACK,
LD B,
JP

#EEREAD
GETDT1

GETDAT:
JSRACK,

; GET ACKNOWLEDGMENT
; POINT FIRST READ RAM
;ANDREADIN
; ACKNOWLEDGMENT TO EE; PROM WHEN 8 BITS
; ARE SHIFTED IN.

GETDAT1:
LDBITCO,
RBIT 2,
RBIT 2,

#008

PORTLC
PORTLD

LOPB:
SBIT 3,
RBIT 7, [B]
IFBIT 2,
SBIT 7, [B]
RBIT 3,
DRSZBITCO,
JPSHFT
LD A, [B+],
IFBNE
JMPGETDT,
SBIT 2,
JMPSTP

PORTLD
PORTLD
PORTLD

#06

PORTLC

; INIT BIT COUNTER
; BEFORE READING, PUT
; 'SDA' INTO HIGH-Z.
; DO CLOCK HIGH
; READ IN EEDATA
; IN SETS OF 8 BITS
; DO CLOCK LOW
; CHECK IF 8 BITS
; ARE SHIFTED
; INCREMENT B
; CHECK IF 4 BYTES
; ARE SHIFTED IN?
; PUT L2=0
; WHEN TRUE, DO STOP
; CONDITION AND
; RETURN

•FORM
SHFT:
LD A, [B],
RRC A
X A, [B]
JP LOPB

; ROTATE BITS ONE
; POSITION RIGHT

; * * SIMPLE ROUTING TO DO 40 MSEC DELAY * *
*- *- ••••••• - ••• - ._. _._._.- •••• - •• _.
TUD/11268-12

4-134

»
z

......

WAIT:
LD OF1

#0.20

; SIMPLE WAIT LOOP

#OFF

; TO PRODUCE>40MSEC
; TIMEOUT

CD
0l:Io

LOPD:
LD OF2,
LOPC:
; TO PROPERLY PROGRAM
; EEPROM. TIME REQUIRED
; TO ERASElWRITE
;THE EEPART.

DRSZ OF2,
JP LOPC,
DRSZOF1,
JP LOPD
REf
ACK1:
SBIT 2,
JPACLK,

PORTLC

; INDICATE TO EE-PROM
; (PUT DATA LINE LOW)

PORTLC

; PUT DATA-LINE HI-Z

SBIT 3,
f\al
f\al
f\al
RBIT 3,

PORTLD

; AND GET ACKNOWLEDGE
; 8 BITS ARE SHIFTED,
; DO A DUMMY CLOCK

PORTLD

; (FOR ACKNOWLEDGE)

SBIT 2,
REf
.END

PORTLC

ACK:
RBIT 2,
ACLK:

TLID/11268-13

4-135

Section 5
Quality and Reliability

Section 5 Contents
EPROM and EEPROM Reliability Information ..........................................

5-2

5-3

.."

~National

::0

Semiconductor

D)
~

EPROM and EEPROM
Reliability Information

rn
rn

.."

::0

!!.
iii"

Reliability testing of National Semiconductor's EPROMs and
EEPROMs has been on the basis of accept on zero, reject
on one. Sampling has typically been on the basis of 77
units. Since the qualification for hermetic and plastic devices is somewhat different, they are separated into two sections below.

1. The Operating Life is identical to that of the hermetic testing described above, I.e., 1S0·C for EPROMs and 1000
hours at 12S·C for EEPROMs.
2. Static Bake does not exceed 1S0·C for both EPROMs
and EEPROMs since the plastic molding compounds
cannot withstand higher temperatures for an extended
period of time. To partially compensate for this, the stress
is extended to 1,000 hours at or below 1S0·C. Again, the
pattern is usually checkerboard.

HERMETIC DEVICES (EPROMs)
Typical packages for EPROMs are the Cer-DIP and Ceramic
Leadless Chip Carrier, CLCC. Both meet industry standard
hermeticity tests and are monitored as part of the assembly
process. The following 3 principal tests are used for qualification of a new device or revision of an existing qualified
device:

~
S'

....o
3

0"
::s

3. The Temperature Cycling is identical to that of the hermetic testing (-6S·C to +1S0·C for 1,000 cycles).
4. Temperature Humidity Bias testing is done at 8S·C and
8S% relative humidity. The part is programmed and biased in a non-functioning mode with only DC power applied, at S.SV. The power application is chosen to minimize power consumption to avoid heating the part and to
maximize internal fields. The stress is continued for 1,000
hours. Any shift beyond datasheet limits is considered a
failure. Any electrical failure prevents qualification.

1. The Operating Life test is at 1S0·C with Vee at specification maximum-which in most cases is S.SV. Release is
given after 3 lots have completed SOO hours.
Note: The 3 lots are from 3 distinct wafer fabrication and assembly lots. This
helps verify the reliability and reproducibility of the device. The stress
is continued for at least 1,000 hours to insure the long term performance of NSC EPROMs. The devices are typically programmed to a
checkerboard type pattern.

S. Autoclave is also done on patterned devices. Any shift in
electrical characteristics beyond datasheet limits is considered a failure. 168 hours for EPROMs and SOO hours
for EEPROMs are minimum duration times. This stress is
normally continued beyond 168 hours for both EPROMs
and EEPROMs to determine device margins.

2. The Static Bake test is at 2S0·C with no power applied.
The purpose of this test is to insure the pattern remains
correct for many years in customer applications. Acceptance of the pattern is done after 168 hours with no sample failure on 3 separate wafer and assembly lots. The
most common pattern utilized is checkerboard, although
variations are used depending on the final test flow. Our
goal is to verify that no loss of pattern or pattern sensitivity has occurred. The testing is continued beyond 168
hours to determine performance margin and initial durability. The devices are tested for total electrical performance with emphasis on any charge change characteristic.

EPROM AND EEPROM RELIABILITY AUDITS
Quarterly audits are conducted to make certain there are no
changes in the reliability of the product going to customers.
The accept criteria is zero for these audits.
Graphs of the 168 and 1000 hour test data are forwarded to
corporate management each month to verify that the
EPROMs and EEPROMs meet expected standards.

3. The Temperature Cycling test is done from -6S·C to
+ 1S0·C for 1,000 cycles. The devices are checked for
electrical performance. Any degradation is considered a
defect. Again, 3 wafer lots are sampled.

WAFER LEVEL RELIABILITY
In addition to the classic reliability described above, National Semiconductor has a program in place that monitors performance of the dielectrics, metal and poly layers. This program is termed WLR (Wafer Level Reliability), and its purpose is to insure that the layers are processed correctly and
perform at their designed values. Examples of dielectric relability are Qbd (charge to break down), step coverage, and
pinhole testing. Examples of metal testing include step coverage, thickness, and hillock control.

PLASTIC DEVICES (EPROMs and EEPROMs)
In addition to the Operating Life, Storage Life, and Temperature Cycling tests mentioned above, Autoclave and Temperature Humidity Bias testing (8S:8S) are also done.

III
S-3

.....
c

CIS

EPROM Qualification/Audit Criteria

.2
.E

:a
.!!!
Ci)

QUALIFICATION CRITERIA
Test
Operating Life
Temperature/Humidity Bias

oa:

Temperature Cycle

Autoclave (Unbiased)

W
'C

Conditions

Duration

Vee:
Temperature:

5.5V
+ 125°C

1,000 Hours

Vee: .
Temperature:
Humidity:

5.5V
+ 85°C
85%RH

1,000 Hours

1,000 Cycles

168 Hours

-65°C

+ 150°C
121°C
15 PSIG

Temperature:
Pressure:

C
ftI

High Temperature Storage Life

Plastic Temperature:

150°C

1,000 Hours

High Temperature Storage Life

Ceramic Temperature:

250°C

168 Hours

Electrostatic Discharge (ESD)

Voltage:

±2000V

oa:
w

EPROM PERIODIC AUDIT CRITERIA
Test

Duration

Operating Life

Vee:
Temperature:

5.5V
+ 125°C

1,000 Hours

Temperature/Humidity Bias

Vee:
Temperature:
Humidity:

5.5V
+ 85°C
85%RH

1,000 Hours

1,000 Cycles

168 Hours

Temperature Cycle (Unbiased)
Autoclave (Unbiased)

Conditions

-65°C

Temperature:
Pressure:

+150°C
+ 121°C
15 PSIG

5-4

"'U

EEPROM Qualificationl Audit Criteria

:tJ

QUALIFICATION CRITERIA

Test

Conditions

Operating Life
Dynamic Burn-In

Vee:
Temperature:

5.5V
+ 125°C

Temperature/Humidity Bias

Vee:
Temperature:
Humidity:

5.5V
+85°C
85% RH

Temperature Cycle (Unbiased)

-65°C +---+ +150°C

Autoclave (Unbiased)

Temperature:
Pressure:

121°C
15 PSIG

High Temperature Storage Life

Temperature:

150°C

Electrostatic Discharge (ESD)

Voltage:

±2000V

Duration

1,000 Hours

:J
Co

"'U

:tJ

1,000 Hours

1,000 Cycles

500 Hours

1,000 Hours

o
==
:tJ

!!!.
iii·

~
S'

-..a
o

o·

::l

EEPROM PERIODIC AUDIT CRITERIA
Test

Duration

Operating Life
(Dynamic Burn-In)

Vee:
Temperature:

6.0V
+125°C

1,000 Hours

Temperature/Humidity Bias

Vee:
Temperature:
Humidity:

5.5V
+85°C
85%RH

1,000 Hours

Conditions

Temperature Cycle (Unbiased)

-40°C +---+ +150°C

1,000 Cycles

Temperature Cycle (Unbiased)

-65°C +---+ + 150°C

1,000 Cycles

500 Hours

Autoclave (Unbiased)

+121°C
15 PSIG

Temperature:
Pressure:

Note: Except for MIL·AERO parts, all EEPROMs are shipped in plastic packages.

5-5

Section 6
Physical Dimensions

Section 6 Contents
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

6-2

6-3

"en

~National

(;'

~ Semiconductor

All dimensions are in inches (millimeters)

e!.
C

:::s

en
0'
:::s
en

16 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J 16A

0.025
(0.635)
RAD

0.005 - 0.020
(0.127 - 0.508)
RAD TYP

,--::( 0.'''-0.320

0.200

~'p!\!-(7'366_B'12B)

0.180

95 0 +5 0
-

(~~)

--1

~ bF~~J=~~~=r~=t~:.~~__-+__~
0.008-0.012
(0.203-0.305)

0.310 - 0.410
(7.874 -10.41)

"M~~I

0.00'--1

(2~~;
BOTH

ENDS
J16AIREVKI

18 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J18A
~RADMAX
(0.508)

0.310
(7.874) MAX

~-::-r-r:;"T'"T"7'T'r::"T""T";:-r-r:;"T-r::"T"T:~U
~MIN-
(0.127)

0.180

0.290-0.320
(7.366-8.128)

H~
j
l

(~~)

950±;-

0.310-0.410

0.055±0.005
(1.397 ±0.127)

0.200
(5.080) MAX
0.020-0.060
(0.508-1.524)
0.125-0.200
5 080
H _-+__-.1.-(3_.1_7_5-t--,.r-)

n------++-----+t-I.-t

GLASS SEALA

NT..........
. 0.008-0.012

(0.203-0.305)

86;y~40

(7.874 -10.41)

J,SAIREVLI

•
I

6-3

o
C

·iii
c
CD

.-----~--------------------------------------------------------------------------------,

20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A

E
C

0.985
~--------(25.019)

1!.~

MAX

----------.t

.c
a.

0.055±0.1I05
(1.397±0.127)

0.180
(4.572)

GLASS SEALANT

MAX

0.200
(5.080)

MAX
0.125-0.200

0.008 - 0.012
(0.203 - 0.305)

(3.175 - 5.080)

I.- 0.310-0.410

0.018±0.003 ~IL
(0.457:0.076)

(7.874-10.41)

•

0.100±0.010
(2.540±0.254)
J20AIREVM)

24 Lead EPROM Ceramic Dual-In-Line Package (JQ) (Small Window)
NS Package Number J24AQ

1----------- 1.260 WAX ------------1

R0.025

0.270-0.290

U.V. WINDOW

0.590-0.620
0.560 WAX
GLASS

I - .0 685 -0.060---l
+0.025
I
1

0.090-0.110
TYP

JHAQ(REV. G)

0.060-0.100
TYP

6-4

28 Lead EPROM Ceramic Dual-In-Line Package (JQ) (Small Window)
NS Package Number J28AQ
. -_ _ _ _ _ _ _ _ 1.490 _ _ _ _ _ _ _ _-1.....1
(37.85)

MAX

0.030-0.055
(0.762-1.397)
RAD TYP

0.590-0.620
(14.99-15.75)

-I

GLASS
SEALANT \

0.020 - 0.070
(0.508-1.778)

- -

0.125

i3.11si
MIN

0.060-0.100 _
(1.524 - 2.540)
TYP

0.055±0.~:· 94° TYP
•

'.'OG±D.01'

(2.540 ± 0.254)

(1.397±0.127)
TYP
0.018±0.003

(0.457 ±D.D76)

TYP

J2BA.Q IAEV 0)

28 Lead EPROM Ceramic Dual-In-Line Package (JQ) (Medium Window)
NS Package Number J28CQ .
~------- 1.465 \.tAX

------+1

R0.025

R 0.030-0.055/
TYP

I
0 685 +0.025
I
1--.
-0.060 ---i
0.0 15-0.060
TYP

mea (REV.

6-5

(I)

c
"iii
c

32 Lead EPROM Ceramic Dual-In-Line Package (JQ)
NS Package Number J32AQ

1+----------

1.660 MAX

"~
.c

--------.-JI
17

RO.025

UV WINDOW SIZ[ AND CONFIGURATION
DETERMINED BY DEVICE SIZE.

I
0 685 +0.025
I
1--.
-0.060--.j
J32AQ(R£V.D}

40 Lead EPROM Ceramic Dual-In-Line Package (JQ)
NS Package Number J40AQ
f-------------(~;~:~)--------------I
MAX

~RAD
(0.635)

0.030-11.055
(0.762-1.391)
RAD TYP

0280±0.D04
(7.112±0.102)

~
0.020-0.070

~~~

i-t------t'--------------------..,--t---t

0.125-0.200

(iiH-5.OiOi

USO
(3.810) ~
MIN (1.397±O.121)
TYP

J40AQ (REV A)

6-6

40 Lead EPROM Ceramic Dual-In-Line Package (JQ)
NS Package Number J40BQ
0.610 IAAX GLASS
[15.49]

UV WINODW SIZE AND CONfiGURATION DETERIAINED BY DEVICE SIZE.
0.010 IAAX
[0.25]
0.050-0.060
0.020-0.070
[1.27-1.52] TYP
[0.51-1.78]
GLASS SEALANT

'590_0'620

[14.99-15.75]

0.180 IAAX
[4.57]
1~0.008-0.012 TYP
[0.20-0.30]

900-1000

1-=-/

I
r
I0.625-0.710 -l
[15.88-18.03]

HOBQ (REV. B)

8 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M08A

~X450J (r~:!~=~:~)
(0.254-0.008)

0.008-0.010

TYP ALL LEADS

80 MAX TYP

0.053 - 0.069
(1.348-1.753)

-:r

0.004 -0.010
(0.102-0.254)

J j
-lY

0.014
(0.356) ~
(1.270)
TYP

0.016-0.050

~:~~L ~~DO~

6-7

tt- -t

SEATING

PlANE
0.014-0.020TYP
(0.356-0.508)

f-t-

.!!!!!!.TYP
(0.203)

•

.t.1OOA (REV H)

o ,------------------------------------------------------------------------------------------,
C
o
14 Lead (0.150" Wide) Molded Small Outline Package (M)
"iii
c
NS
Package Number M 14A
m
E

m
o
"iii
>.c

-(~;~:=~:;~:)-I
14

c..

ioI-'-l

0.228 -0.244
(5791,6.198)
LEAD NO. 1

-1

.....................

30·

J~~::::;:;;:::;:::;=;:;::~:::;:;=;::;j/.
/\
~

IOENT----.

----1

7---r

..QJ!!!!.MAX
(0.254)

0.150-0.157

r
1

~45·
(0.254 -0.50a) x

r~---""\'

~Jj~
o.ooar.:(0.203-0.254)
TYP ALL LEADS

0.053 -0.069
(1.346 -1.753)

a. MAX TYP

~J
I --.:

ALL LEADS

SEATING
PLANE

t
0.014
(0.356)

0.016-0.050
(0.406-1.270)
TYP ALL LEADS

0.004
(0.102)
ALL LEAD TIPS

(1.270)
TYP

I
-

0.004-0.010
(0.102-0.254)

_11:J-o.020 TYP
(0.356-0.508)
TV P
(0.203)

..!.QQ!

M14A(AEVHI

14 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M 148

0.346-0.362

---~
14 13 12 11 10

-I
9

0.394 - 0.419

(~:~:: =~:~::) ---.~

0.009 -0.013
(0.229-0.330)

~ x45·

t
t.

(0.432)

8. MAX TYP

TV"~~S~

(0.102)
ALL LEAD
TIPS

0.093-0.104
(2.362 - 2.642)

(0.940-1.118)
~

~J JL~

.:d

tJiliJJJLiilt10il
L JI

0.050
(1.270)
TYP

(0.762-1.270)
TYP ALL LEADS

0.004-0.012
(0.102-0.305)

t
t

SEATING
PLANE

_~TVP
(0.356 -0.483)
M14B (REV 0)

6-8

32 Lead TSOP, EtAJ Type I (M)
NS Package Number MBH32A

1-001'---------

20.0 iO.2

----------1'1

(0.43)1

-.l

t0.5 TYP
16~~

r1.01:l:0.05

8.0 iO.l

______________________________________- r -

-.ll.,
..., 1 - - - - - - - - - 1 8 . 4

0.150 iO.008
(LEADFRAME THICKNESS)

:l:O.l--------"-,,.-Il.,,\

~~==========================~!,~~~ ~
"' ••

--~

SEE DETAIL A

DETAIL A
TYPICAL

WBH32A (REVA)

8 Lead Molded Dual-tn-Line Package (N)
NS Package Number N08E
.

--~DlA

(2.337)
PIN NO.

(~:!~!=~o~~~)]
7

--,

~0" ,

lIDENT~

+
0.250 ± 0.005
(6.35±0.127)
--.-.l

_._)
2

OPTION 1
1

-..!!:!!!!!!..
(2.286)

0.032+0.005
(0.813±0.127)
RAD
PIN NO.1 IDENT~
1

0.040
I
(1.016) TYP-.J -

OPTION 2

0.130 ± 0.005
(3.30210.127)

I I
0.009-0.015 j"~
~~:i~12:5)
(0.229-0.381)
DIA

0.125-0.140
(3.175-3.556)

95°±5° )

0.325

+0.040
-0.015

00±40

TYP

0.018 ±0.003
(0.457±0.076)
0.100±0.010

NOM

+1.016)
(8255
.
-0.381
0.045±0.015
(1.143±0.381)

0.020
(0.508)
MIN

-~(2'540 ±0.254)

I..-

0.060
(1.524)
NOBE (REV FI

6-9

o ,-------------------------------------------------------------------------------------------,

14 Lead Molded Dual-In-Line Package (N)
NS Package Number N 14A

(ij
Co)

.c
a..

~OIA ~MAX
(2.337)

(0.762) OEI'TH
OPTION 1

OPTION 02

0.135±0.005
(3.429 iO.127)

0.300 -0.320

4° TYP
OPTIONAL

(~:~~~)
MIN

0.125-0.150
(3.17~-3.810)

0.014-0.023
(0.356 -0.584)

T
90 ±4° TYP

-II

.....1

TYP~

~~TYP

0.075 to.015

~(l.905±O.38l)
O.100±0.010 TYP
(2.540 ± 0.254)

0.325~~::

(1.270-0.254)

+1.016)
(8255
. -0.381

NtUIREVFI

16 Lead Molded Dual-In-Line Package (N)
NS Package Number N 16A

(~:~~~) ~

MIN
0.lOO-0.l20

O.OlO
(0.762)
MAX

(7 .620-8.128)

". . V~--l-."',_.'.J.81I. "'J J
I·

0.l25

~~:~~

-I

+1016)
( 8.255 -0:381

0.075 ±0.015
(1.905 ±0.l81/

I
r-

0.100 ±0.010
(2.540 ±0.254)

Nt6AIREV E)

6-10

18 Lead Molded Dual-In-Line Package (N)
NS Package Number N18A
0.B43-o.B7o ~
(21.41-22.10)

0.092
0.030
- x(0.762)
-(2.336)

NOM
MAX
OEEP (2 PLCS)

0.250 ±0.005
(6.350 ±0.1271

I~;-:'-:'::
0.2Bo
(7.112)

~;:;:::r.::;::=;;;:;;=T;:r::::;:;;=r;;:::;:::~~

MIN

0.300-0.320

j£?\
I·

0325 +0.040
.
-0.015

·1

0.025 ±O.O 15

(..".OJ8I1,.,,,!.:,

f8.255 +1.016)
-0.3Bl

(2.540 ±0.254)

TYP
NI8A(REVE)

20 Lead Molded Dual-In-Line Package (N)
NS Package Number N20A
1.013-1.040
(25.73-26.42)

0.092 X D.03D
(2.337 X0.762)

=::1

~=========1=1==16===15==1=4~IJ~=12~=11~

MAX DP

D.032±0'005~O
19

-r

0.260 ±0.005
(6.604 to.127)

(0.813 ±0.127)
RAD

PIN NO.1IDENT~

~r.n~~~~~~~

OPTIDN 2

D.06S
(1.651)

~h-~~~~~~~~~

0.009-D.D1
(0.229-0.381)
TYP

0.325

~~:~~

0.02D
(D.50B)

0.06D to.ODS
(t.524tO.127)

MIN

18.255 +1.016)
~
-D.381
N20AIREVGI

[II
I

6·11

'iii
c

.---------------------------------------------------------------------------------------------~

28 Lead Molded Dual-In-Line Package (N)
NS Package Number N28B

is
CO

u
'~
.c
D.

PIN NO. llDENT

t.-------------- 1.393-1.420 _ _ _ _ _ _ _

--I~

(35.38-36.07)

0.1211-0.145
(3.1711-3.683)
N28B(REVEj

40 Lead Molded Dual-In-Line Package (N)
NS Package Number N40A

0.062
(1.&751

0.55010.005

RAD

PIN NO. llDENT

~~~~~=r.~~7r~~=ffirr.~~~~=arT.~~~~~~::J[.""

0.07510.015

N40A(AEVIE)

6·12

20 Lead Plastic Chip Carrier (V)
NS Package Number V20A
4 SPACES AT
0.050
(1.270)

i't"i43i
0·04if5
xes'

0.080

rz:om

'~~~r--"f--..L..

:f.

DIANOM
PEOESTAl

15'

VIEW A·A

14~

4 SPACES AT
0.050
~

\1_3
91
. ....
~
0.228
~--~r (5.740)
NOM
SQUARE

0.310 -0.330

i7.i7i=i.3i2i

(CONTACT DIMENSION)

0.020

(Q.5Oii
0.005-0.015

t-===F==m?(fffiffirffl~~~~

MIN
0.032-0.040
(0.813-1.016)

V20AIREVJ)

28 Lead Plastic Chip Carrier (V)
NS Package Number V28A

VIEW A·A

~-'I(1.143)
xU'

0.165-0.180
(4.181-4.572)

0.032-0.040

ii:iii=iiiii

!
_01 t-oIr'-'--(::::::~~)
TVP

f~
(2.642-2.997)
V28AtREVG)

6-13

'Ci)

cCI)

44 Lead Plastic Chip Carrier (V)
NS Package Number V44A

E
is

0.526
(13.36)
NOM

(ij
(.)

.c
D.

0.050
(1.270)
REF

t
t

0.04~

VIEW A-A

('L~

DI
~

~(1.143)

~ 0.050
(1.270)
REF

0.032-0.040
(0.813-1.016)

0.020

(D.5Os)

(0.127 -0.381)
MAX

j
L ---.J

0.026 - 0.032
(0.660 - 0.813)

0.104 - 0.118
12.642 - 2.997)

TYP

0.650
(16.51)

REF SQ

0.685-0.695
(17.40-17.65)

Y•• AIREY HI

SQUARE

6-14

32 Lead Plastic Chip Carrier (V)
NS Package Number VA32A

-H-

BASE
PLANE

0.541-0.545
[13.74-13.84]
0.585-0.595
[14.86-15.11]

0.013-0.021 TYP
[0.33-0.53]
SEE DETAIL A

1+ 10.007[0.18]

@Icl 0-[, F-G ® 1

0.078-0.095
[1.98-2.41]

0.118-0.129
[3.00-3.28]

1+ 1<1>0.010[0.25] 01 1 10-[, F-G ® I
B A

0.045
[1.14]

45 0 X 0.042-0.048
[1.07-1.22]

R 0.030-0.040
[0.76-1.02]

DETAIL A
TYPICAL
ROTATED 90°

--II-

0.031-0.037
[0.79-0.94]
0.026-0.032 TYP
[0.66-0.81]

1+1 0.007[0.IS]

®jHI O-[,F-G ®I
SECTION B-B
TYPICAL

6-15

VA32A (REV A)

NOTES

~National

~ Semiconductor

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
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ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic • Advanced Low Power Schottky. Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions • Peripheral Functions. LSIIVLSI Functions • Design Guidelines. Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC SWitching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCTIMM74HCT. CD4XXX • MM54CXXX/MM74CXXX. Surface Mount

DATA ACQUISITION LINEAR DEVICES-1989
Active Filters. Analog Switches/Multiplexers • Analog-to-Digital Converters • Digital-to-Analog Converters
Sample and Hold • Temperature Sensors • Voltage Regulators • Surface Mount

DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Linear Devices Databook.

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors. Surface Mount Products. Pro-Electron Series
Consumer Series • Power Components • Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1991
Dynamic Memory Control • Error Detection and Correction • Microprocessor Applications for the
DP8408A109A117/18/19/28/29. Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821

EMBEDDED CONTROLLERS DATABOOK-1992
COP400 Family • COP800 Family • COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals • Microcontroller Development Tools

EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview • Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools

FOOl DATABOOK-1991
FDDI Overview. DP83200 FDDI Chip Set • Development Support • Application Notes and System Briefs

F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1990
Family Overview • 300 Series (low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
ECl BiCMOS SRAM, ECl PAL, and ECl ASIC Datasheets • Design Guide • Circuit Basics • Logic Design
Transmission Line Concepts. System Considerations. Power Distribution and Thermal Considerations
Testing Techniques. Quality Assurance and Reliability. Application Notes

FACTTM ADVANCED CMOS lOGIC DATABOOK-1990
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • 54AC/7 4ACXXX • 54ACT /7 4ACTXXX • Quiet Series: 54ACQ/7 4ACQXXX
Quiet Series: 54ACTQ/7 4ACTQXXX • 54FCT /7 4FCTXXX • FCTA: 54FCTXXXA/7 4 FCTXXXA

FAST® ADVANCED SCHOTTKY TTL lOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F/74FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators • FIFOs • Counters • TIL Small Scale Integration • Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics

GENERAL PURPOSE liNEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators • Switching Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators
Instrumentation Amplifiers • Surface Mount

GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications • Application Notes

INTERFACE: liNE DRIVERS AND RECEIVERS DATABOOK-1992
EIA-232. EIA-422/423. EIA-485. Line Drivers. Receivers. Repeaters. Transceivers. Application Notes

liNEAR APPLICATIONS HANDBOOK-1991
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LOCAL AREA NETWORK DATABOOK-1992
Integrated Ethernet Network Interface Controller Products • Ethernet Physical layer Transceivers
Ethernet Repeater Interface Controller Products • Hardware and Software Support Products • FDDI Products. Glossary

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller • SCSI Bus Interface Circuits • Floppy Disk Controllers • Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits • Disk Interface Design Guide

MEMORY DATABOOK-1992
CMOS EPROMs • CMOS EEPROMs • PROMs • Application Notes

MICROPROCESSOR DATABOOK-1989
Series 32000 Overview • Central ProceSSing Units • Slave Processors • Peripherals
Development Systems and Software Tools. Application Notes. NSC800 Family

REAL TIME CLOCK HANDBOOK-1991
Real Time Clocks and Timer Clock Peripherals • Application Notes

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process • Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge • Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography· MIL-M-38510 and DESC Drawing Cross Listing

SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits • Radio Circuits • Video Circuits • Motion Control Circuits • Special Function Circuits
Surface Mount

TELECOMMUNICATIONS-1992
COMBO and SLiC Devices. ISDN. Digital Loop Devices. Analog Telephone Components. Software
Application Notes

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
ALABAMA
Huntsville
Arrow Electronics

(205) 837·6955

San Jose
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(408) 453·1200
Arrow Electronics

Bell Industries

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(205) 837·1074

Pioneer Technology

Hamilton! Avnet

(408) 954·9100

(205) 837·7210

Zeus Components

Pioneer Technology

(408) 629·4789

(205) 837·9300
Time Electronics

Sunnyvale
Bell Industries

Lake Mary
Arrow Electronics

(407) 333·9300
Orlando
Chip Supply

(301) 596·7800

Time Electronics

(407) 841·6565
St. Petersburg
Hamilton! Avnet

(813) 572·4329

(408) 734·8570

ARIZONA
Chandler
Hamilton! Avnet

Hamilton! Avnet

Winter Park
Hamilton! Avnet

(408) 743·3300

(407) 657·3300

(602) 961·1211
(602) 437·0750
Tempe
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Bell Industries

(602) 966·7800
Time Electronics

(602) 967·2000
CALIFORNIA
Agora Hills
Bell Industries

(818) 706-2608
Time Electronics

(818) 707·2890
Zeus Components

(818) 889·3838
Burbank
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Calabasas
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Chatsworth
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Arrow Electronics

(818) 701·7500
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Costa Mesa
Hamilton Electro Sales

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Cypress
Bell Industries

(714) 895·7801
Gardena
Hamilton! Avnet

(213) 516·8600
Irvine
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(714) 768·4444
Rocklin
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Bell Industries

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Roseville
Hamilton! Avnet

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San Diego
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Arrow Electronics

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Hamilton! Avnet

(619) 571·1900
Time Electronics

(619) 586-0129

Time Electronics

(408) 734·9888
Torrance
Time Electronics

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Tustin
Arrow Electronics

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Time Electronics

(714) 669·0100
Woodland Hills
Hamilton! Avnet

(818) 594·0404
Yorba Linda
Zeus Components

(714) 921·9000
COLORADO
Aurora
Arrow Electronics

(303) 373·5616
Denver
Bell Industries

(303) 691·9010
Englewood
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(303) 790·4500
Hamilton! Avnet

(303) 799·7800
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CONNECTICUT
Danbury
Hamilton! Avnet

(203) 743·6077
Shelton
Pioneer Standard

(203) 929·5600
Wallingford
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(203) 265·7741
Waterbury
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FLORIDA
Altamonte Springs
Bell Industries

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Pioneer Technology

(407) 834·9090
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Deerfield Beach
Arrow Electronics

(305) 429·8200
Bell Industries

(305) 421·1997
Pioneer Technology

(305) 428·8877
Fort Lauderdale
Hamilton! Avnet

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(301) 995·6840
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(205) 721·1133

Phoenix
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MARYLAND
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GEORGIA
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ILLINOIS
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(708) 495·9680
Bensenville
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(708) 860·7700
Elk Grove Village
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Itasca
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INDIANA
Carmel
Hamilton! Avnet

(317) 844·9333
Fort Wayne
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(219) 423·3422
Indianapolis
Advent Electronics Inc.

(317) 872·4910
Arrow Electronics

(317) 299·2071
Bell Industries

(317) 875·8200
Pioneer Standard

(317) 573·0880
IOWA
Cedar Rapids
Advent Electronics

(319) 363·0221
Arrow Electronics

(319) 395·7230
Hamilton! Avnet

(319) 362·4757
KANSAS
Lenexa
Arrow Electronics

(913) 541·9542
Hamilton! Avnet

(913) 888·8900

(301) 964·3090
Zeus Components

(301) 997·1118
Gaithersburg
Pioneer Technology

(301) 921·0660
MASSACHUSETTS
Andover
Bell Industries

(508) 474·8880
Beverly
Sertech Laboratories

(508) 927·5820
Lexington
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(617) 861·9200
Norwood
Gerber Electronics

(617) 769·6000
Peabody
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(508) 531·7430
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Tyngsboro
Port Electronics

(508) 649·4880
Wakefield
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Wilmington
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MICHIGAN
Grand Rapids
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(616) 698·1800
Grandville
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(313) 525·1800
Novi
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Wyoming
R. M. Electronics, Inc.

(616) 531·9300
MINNESOTA
Eden Prairie
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(612) 944·5454
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Minnetonka
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NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
MISSOURI
Chesterfield
Hamilton/ Avnet
(314) 537-1600
St. Louis
Arrow Electronics
(314) 567-6888
Time Electronics
(314) 391-6444
NEW JERSEY
Cherry Hill
Hamilton/ Avnet
(609) 424-0100
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Hamilton/ Avnet
(201) 575-3390
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(609) 596-8000
Time Electronics
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Arrow Electronics
(201) 227-7880
Wayne
Time Electronics
(201) 758-8250
NEW MEXICO
Albuquerque
Alliance Electronics Inc.
(505) 292-3360
Bell Industries
(505) 292-2700
Hamilton/ Avnet
(505) 345-0001

NEW YORK
Binghamton
Pioneer
(607) 722-9300
Buffalo
Summit Electronics
(716) 887-2800
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Fairport
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(716) 381-7070
Hauppauge
Arrow Electronics
(516) 231-1000
Hamilton/ Avnet
(516) 231-9444
Time Electronics
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Port Chester
Zeus Components
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Rochester
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Hamilton/ Avnet
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Time Electronics
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Westbury
Hamilton/ Avnet Export Div.
(516) 997-6868
Woodbury
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(516) 921-8700
NORTH CAROLINA
Charlotte
Hamilton/ Avnet
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Pioneer Technology
(704) 527-8188
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Pioneer Technology
(919) 544-5400
Raleigh
Arrow Electronics
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Hamilton/ Avnet
(919) 878-0810
Time Electronics
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OHIO
Centerville
Arrow Electronics
(513) 435-5563
Cleveland
Pioneer
(216) 587-3600
Columbus
Time Electronics
(614) 794-3301
Dayton
Bell Industries
(513) 435-8660
Bell Industries-Military
(513) 434-8231
Hamilton/ Avnet
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Pioneer Standard
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(513) 293-6162
Solon
Arrow Electronics
(216) 248-3990
Hamilton/ Avnet
(216) 349-5100
Westerville
Hamilton/ Avnet
(614) 882-7004
OKLAHOMA
Tulsa
Arrow Electronics
(918) 252-7537
Hamilton/ Avnet
(918) 664-0444
Pioneer Standard
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Radio Inc.
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OREGON
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Hamilton/ Avnet
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Lake Oswego
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(503) 635-6500
Portland
Time Electronics
(503) 684-3780

PENNSYLVANIA
Horsham
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(215) 443-5150
Pioneer Technology
(215) 674-4000
Mars
Hamilton/ Avnet
(412)281-4150
Pittsburgh
Pioneer
(412) 782-2300
TEXAS
Austin
Arrow Electronics
(512) 835-4180
Hamilton/ Avnet
(512) 837-8911
Minco Technology Labs.
(512) 834-2022
Pioneer Standard
(512) 835-4000
Time Electronics
(512) 346-7346
Carrollton
Arrow Electronics
(214) 380-6464
Dallas
Hamilton/ Avnet
(214) 308-8111
Pioneer Standard
(214) 386-7300
Houston
Arrow Electronics
(713) 530-4700
Hamilton/ Avnet
(713) 240-7733
Pioneer Standard
(713) 495-4700
Richardson
Anthem Electronics
(214) 238-7100
Time Electronics
(214) 644-4644
Zeus Components
(214) 783-7010
UTAH
Midvale
Bell Industries
(801) 255-9611
Salt Lake City
Anthem Electronics
(801) 973-8555
Arrow Electronics
(801) 973-6913
Hamilton/ Avnet
(801) 972-2800
West Valley
Time Electronics
(801) 973-8494
WASHINGTON
Bellevue
Arrow Electronics
(206) 643-4800
Bothell
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(206) 483-1700
Kirkland
Time Electronics
(206) 820-1525
Redmond
Bell Industries
(206) 867-5410
Hamilton! Avnet
(206) 241-8555

(Continued)

WISCONSIN
Brookfield
Arrow Electronics
(414) 792-0150
Pioneer Electronics
(414) 784-3480
Mequon
Taylor Electric
(414) 241-4321
Waukesha
Bell Industries
(414) 547-8879
Hamilton/ Avnet
(414) 784-8205
CANADA
WESTERN PROVINCES
Burnaby
Hamilton/ Avnet
(604) 420-4101
Semad Electronics
(604) 420-9889
Calgary
Electro Sonic Inc.
(403) 255-9550
Semad Electronics
(403) 252-5664
Zentronics
(403) 295-8838
Edmonton
Zentronics
(403) 468-9306
Markham
Semad Electronics Ltd.
(416) 475-3922
Richmond
Electro Sonic Inc.
(604) 273-2911
Zentronics
(604) 273-5575
Saskatoon
Zentronics
(306) 955-2207
Winnipeg
Zentronics
(204) 694-1957
EASTERN PROVINCES
Mississauga
Hamilton/ Avnet
(416) 795-3825
Time Electronics
(416) 672-5300
Zentronics
(416) 564-9600
Nepean
Hamilton/ Avnet
(613) 226-1700
Zentronics
(613) 226-8840
Ottawa
Electro Sonic Inc.
(613) 728-8333
Semad Electronics
(613) 727-8325
Pointe Claire
Semad Electronics
(514) 694-0860
St. Laurent
Hamilton/ Avnet
(514) 335-1000
Zentronics
(514) 737-9700
Willowdale
ElectroSonic Inc.
(416) 494-1666
Winnipeg
Electro Sonic Inc.
(204) 783-3105

~ National

Semiconductor

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1992_National_Memory_Databook 1992 National Memory Databook

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