1992_SGS_Designers_Guide_to_Power_Products_Application_Manual_2_Ed 1992 SGS Designers Guide To Power Products Application Manual 2 Ed
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DESIGNERS' GUIDE TO
POWER PRODUCTS
APPLICATION MAN UAl
2 nd EDITION
PRINTED ON RECYCLED PAPER
JUNE 1993
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON PRODUCTS ARE NOT AUl'HORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As
used herein:
1. Life support devices or systems are those which (a) are
intended for surgical implant into the body, or (b) supPort
or sustain life, and whose failure to perform, when
properly used in accordance with instructions for use
provided with the product, can be reasonably expected
to result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can reasonably be expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
TABLE OF CONTENTS
INTRODUCTION
GENERAL INDEX
Page
4
7
APPLICATION NOTES
TECHNOLOGY AND BASIC. . . . . . . . . . . . . . . . . . ..
11
SMART POWER DEVELOPMENT SYSTEM . . . . . . . . . ..
87
STEPPER MOTORS . . . . . . . . . . . . . . . . . . . . . . .
99
DC AND BRUSH LESS MOTORS . . . . . . . . . . . . . . . .. 205
DRIVERS AND INTELLIGENT POWER SWITCHES . . . . . .. 333
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . .. 393
POWER MOS AND IGBTs . . . . . . . . . . . . . . .. . . . .. 713
SCRs AND TRIACS . . . . . . . . . . . . . . . . . . . . . . .. 863
MONITOR AND TV CIRCUITS . . . . . . . . . . . . . . . . . . 993
THERMAL MANAGEMENT . . . . . . . . . . . . . . . . . . . . 1213
INTRODUCTION
THE BRIGHTER POWER
This book has been written for those interested in taking advantage of the most recent
advances in power integrated circuits. Smart power integrated circuits together with
power discrete devices form the heart of modern power electronics.
SGS-THOMSON is well established in the field of power electronics, both for power
discretes and power integrated circuits. In particular, the company is a world leader in
power integrated circuits. Ever since rankings were published for the fast-growing
power IC and smart power IC markets SGS-THOMSON has been number one.
Moreover, the company has a share almost twice that df the nearest competitor in both
power IC markets.
Our long term experience in bipolar discretes has led to reliable rugged devices using
state-of-the-art bipolar structures and both single and double implanted planar edge
termination techniques that meet today's demand for very high switching speeds and
high breakdown voltages.
These techniques are not confined to bipolar transistor fabrication. High voltage Power
MOS using high efficiency edge structures and platinum ion implanted IGBTs use
flexible processes that produce a range of rugged high voltage devices ideal for
switch mode applications.
SGS-THOMSON's leadership in power IC technology has its roots in its pioneering
work at the end of the '60s, when the first ICs combining power circuits a.nd control
circuits were first created. Initially this technology was used in applications such as
audio amplifiers, voltage regulators and TV deflection circuits. Later it was extended
to applications such as motor and solenoid driving.
Thanks to an advanced 2nd generation BCD smart power process, SGS-THOMSON integrates highly
complex power subsystems on a single chip. This Ie, designed for a hard disk drive, controls and drives
both the spindle motor and the head positioner. It includes more than 10,000 transistors.
-----------------------4
~~~@~~lal
------------------------
INTRODUCTION
In the early eighties another major step forward was taken when SGS-THOMSON
introduced a new power IC technology that combined bipolar CMOS and DMOS power
transistors on the same chip.
Unlike other "smart power" technologies, this allowedthe integration of isolated DMOS
transistors so any number could be placed on one chip and interconnected in any way.
Recently a shrink version of this technology has been introduced. Thanks to 2.51lm
geometries this version makes it possible to integrate very complex LSI power circuits
on one chip.
One example of the new generation is a single chip that controls and drives three
motors in a fax machine. Another circuit drives the head positioning and spindle motor
actuators of a 2.5" hard disk drive. This power IC, made with the 2nd generation BCD
process, integrates highly complex power subsystems on a single chip. It includes
more than 10,000 transistors.
In addition to the BCD technology, VIPower ICs have been developed. These unique
monolithic power ICs are based on discrete transistors with current flowing vertically
through the silicon and have integrated control circuits constructed on-chip. Three
sub-families of power ICs have been derived from this technology. Included in these
sub-families are bipolar output ignition drivers rated at 450V, 8.5A and Power MOSFET
output high-side drivers with an RDS(on) as low as 30mQ and V(BR)DSS of 60V and
low-side drivers rated at 450V, 0.75Q.
Because most SGS-THOMSON power ICs are innovative the company places great
emphasis on application support. For many products there are sophisticated application development tools - hardware and software - for use with the lab PC. The company
also regularly publishes application documentation. This volume is a follow-on from
the Smart Power Application Manual, reflecting the broader scope of power electronics.
It includes application notes and other useful material about SGS-THOMSON power
ICs, power technologies and power discretes.
SGS-THOMSON's innovative smart power processes are made to fit the needs of
today. By providing complex functions in small, rugged and easy to use packages the
task of system design is made easier and the system reliability is improved.
A variety of high voltage Power MOS in power packages to suit today's environments.
-----------------------
~~~@lH~l9~
------------------
5
GENERAL INDEX
TECHNOLOGY AND BASICS
Page
AN446 - Smart Power Processes for LSI Circuits ........................................
AN447 - Smart Power Technology Evolves to Higher Levels of Complexity ....................
13
19
AN449 - New Levels of Integration in Automotive Electronics ...............................
25
AN471 - Smart Power Technologies for Powertrain & Body Electronics .......................
35
AN451 - High-Current Motor Driver ICs Bring Automotive Multiplex Closer
....................
47
AN483 - Mixed Wire Bonding Technology for Automotive Smart Power ICs ....................
53
AN474 - How Design Rules Influence High-Frequency Switching Behaviour of Power Mosfets .....
57
AN475 - Gate Charge Characteristics Lead to Easy Drive Design for Power MOSFet Circuits
.....
67
AN370 - Analysis and Optimisation of High Frequency Power Rectification .................... ,
75
SMART POWER DEVELOPMENT SYSTEM
AN450 - PC Based Development System Cuts Design Time of Smart Power IC Applications. . . . . ..
89
STEPPER MOTORS
AN460 - Stepper Motor Drive Consideration, Common Problems & Solution
101
AN379 - Using the L6204,a Bipolar Stepper and DC Motors Driver in BCD Technology ........... 113
AN266 - Bipolar Stepper Motor Control ................................................ 121
AN279 - Short Circuit Protection on L6203
............................................. 133
AN280 - Controlling Voltage Transients in Full Bridge Drivers Applications ..................... 137
AN234 - A High Efficiency, Mixed-Technology Motor Driver ................................. 145
AN235 - Stepper Motor Driving
...................................................... 151
AN468 - Constant-Current Chopper Drive Ups Stepper-Motor Perfomance .................... 167
AN469 - Using the L6506 for Current Control of Stepper Motors ............................ 173
AN238 - High Power, Dual Bridge ICs Ease Stepper Motor Driver Design ..................... 179
AN470 - The L297 Stepper Motor Controller ............................................ 187
DC AND BRUSH LESS MOTORS
AN457 - Twin-Loop Control Chip Cuts Cost of DC Motor Positioning ......................... 207
AN380 - How to Drive DC Motors with Smart Power ICs
.................................. 215
AN452 - A Load Current Sensing in Switch-Mode Bridge Motor Driving Circuits ................. 231
AN454 - A Solid State Blinker for Automotive Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 237
AN455 - Rear Mirrors Multiplexing Using L9946 .......................................... 241
AN456 - 6A Door Lock Motor Driver for Automotive .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 249
AN281 - Driving DC Motors ......................................................... 255
AN240 - Applications of Monolithic Bridge Drivers ........................................ 263
AN241 - Speed Control of DC Motors with the L292 Switch-Mode Driver ...................... 273
AN242 - The L290-L291-L292 DC Speed/Position Control ................................. 281
AN282 - An Economic Motor Drive With Very few Components .............................. 305
AN424 - Versatile and Cost Effective Induction Motor Drive with Digital Three Phase Generation ... 309
AN481 - Motor Control Design using Vertical Smart Power ICs .............................. 323
7
GENERAL INDEX
DRIVERS AND INTELLIGENT POWER SWITCHES
Page
AN453 - How the TDE1897/98 Behave in Extreme Overload Conditions ........... "...... " ..... 335
AN243 - Switch-Mode Drivers for Solenoid Driving .... " .. " ... " .. " ..... " .. " ..... " ..... " ... 341
AN292 - Fully Protected High Voltage Interface For Electronic Ignition .. " ..................... 353
AN813 - Transistorized Power Switches with Improved Efficency ............................ 359
AN482 - Electronic Ignition with VB020 and L497 ........................................ 365
AN268 - Intelligent Autoprotected Drivers ........................................ ',' ..... 369
AN270 - Interfaces Dedicated to Processes Control ................. " ............ " ....... 379
AN271 - High-Side Monolithic Switch in Multipower-BCD Technology ......................... 385
POWER SUPPLY
AN458 - Designing with the L4963 Discontinuous Mode Power Switching Regulator ............. 395
AN487 - Introduction to a 10A Monolithic Switching Regulator in Multipower-BCD Technology ...... 413
AN364 - Switch-Mode Base Driver Circuit with the L4974 Smart Power IC ..................... 425
AN433 - Ultra Fast Nica Battery Charging using ST621 0 Microcontroller .................. ".... 429
AN244 - Designing with the L296 Power Switching Regulator .............................. 435
AN245 - Designing Multiple-Output Power Supplies with the L296 and L4960 .................. 477
AN246 - UC3842 Provides Low-Cost Current-Mode Control ................................ 487
AN247 - A 25W Off-Line Flyback Switching Regulator . " ................................... 503
AN362 - Flexible Low Cost High Efficiency 130W SMPS using SGSD00055 and TEA2018A ....... 509
AN250 - A Second-Generation IC Switch Mode Controller Optimized for High Frequency
PowerMOS Drive .......................................................... 515
AN352 - 200kHz 15W Push-Pull DC/DC Converter ....................................... 527
AN357 - High-Voltage Transistors with PowerMOS Emitter Switching ......................... 533
AN361 - A Transistor for a 100kHz Converter: ETD ....................................... 539
AN366 - An Innovative High Frequency High Current Transistor Chopper ...................... 547
AN367 - A Power Stage for a 20kHz, 10 KW Switched Mode Power Supply for the Industrial
380/440V Mains .............. " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 555
AN368 - Power Semiconductors for High Frequency AD/DC Converters Supplied on the
380/440V Mains ......................................................... "
565
AN369 - Optimized Power Stages for High Frequency 380/440V Medium Power Switch
Mode Supplies ............................................................. 571
AN376 - TEA2260/61 High Performance Driver Circuits for SMPS " .......................... 579
AN406 - TEA20'18A/19 Flyback Switch-Mode Power Supply Implementation .......... , ........ 613
AN389 - An Automatic Line Voltage Switching Circuit , .. , .. , ............................... 651
AN390 - How to Use the AVS Kit ..................................................... 657
AN253 - Power Suppy Design Basics .................................................. 661
AN290 - Very
L~w-Drop
Regulators Enhance Supply Performance .......................... 667
AN255 - A Designers Guide to the L200 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .. 677
AN256 - Dual Regulators Simplify Micro System Suppy Design ... ; .......... , .............. 697
AN254 - Low-Drop Voltage Regulators for Automotive Electronics , .......................... 705
8
GENERAL INDEX
POWER MOS AND IGBTs
Page
AN476 - Safe Behavior of IGBTs Subjected to dV/dt ...................................... 715
AN477 - Static and Dynamic Behavior of Parallel IGBTs .............. , .................... 725
AN478 - How Short Circuit Capabilities Govern the Desired Characteristics of IGBTs ............. 739
AN479 - Switching with IGBTs: How to Obtain Better Performance ........................... 749
AN480 - Series Connection of MOSFET, Bipolar and IGBT Devices .......................... 759
AN351 - Novel Protection and Gate Drives for MOSFETs used in Dridge-Leg Configuration ....... 771
AN356 - Use of the Internal MOSFET Diode in Bridge-Legs for High Frequency Applications ...... 777
AN358 - Environment Design Rules of MOSFET in Medium Power Application ................. 787
AN359 - Compact High Performance Brush DC Motor Servo Drives using MOSFETs ............ 797
AN463 - Switching with MOSFETs and IGBTs: from 50Hz to 200kHz ......................... 807
AN464 - Insulated Gate Bipolar Transistors in HF Resonant Converters ....................... 825
AN465 - Bipolar Junction Transistors Power MOSFETs or IGBTs in Resonant Converters ......... 837
AN466 - Analysis of Losses in IGBTs .................................................. 849
AN461 - A New Isolated Gate Drive for Power MOSFETs and IGBTs ......................... 857
SCRs AND TRIACs
AN301 - The TRIAC ............................................................... 865
AN302 - Thyristors and Triacs, An Important Parameter: The Holding Current .................. 887
AN303 - Thyristors and Triacs, An Important Parameter: Latching Current ..................... 893
AN306 - Design of a Static Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 903
AN307 - Use of a Triacs on Inductive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 907
AN308 - Control by a Triac for an Inductive Load: How to Select a Suitable.Circuit ............... 913
AN328 - Protect your Triacs ............................ : ............................ 925
AN392 - Power Control with ST621 0 MCU and Triac ...................................... 929
AN436 - Triac Control by Pulse Transformer ............................................ 939
AN437 - New Triacs : is the Snubber Circuit Necessary? ................................... 945
AN438 - Triacs + Microcontroller Safety Precautions for Development Tool ..................... 953
AN439 - Inprovement in the Triac Commutation .......................................... 957
AN440 - Triac Drive Circuit for Operation in Quadrants I and III .............................. 967
AN441 - Triacs for Microwave Oven ................................................... 973
AN442 -.Triacs and Microcontrollers: The Easy Connection ................................. 981
AN443 - Series Operation of Fast Rectifiers ...................... '....................... 983
AN444 - Transistor Protection by Transil: Dissipation Power and Surge Current Duration .......... 991
9
GENERAL INDEX
MONITOR AND TV CIRCUITS
AN373 - Vertical Deflection Circuits for TV & Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
Page
995
AN374 - TDA81 02A HorizontallVertical Processor for TIL - VDU ........................... 1019
AN377 - TEA5101A - RGB High Voltage Video Amplifier Basic Operation and Applications ....... 1035
AN393 - TV EIW Correction Circuits .................................................. 1059
AN407 - TEA2028fTEA2029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1095
AN408 - TEA5170 Secondary Controller for Master - Slave Structure . . . . . . . . . . . . . . . . . . . . . . .. 1151
AN409 - TEA2164 Master-Slave SMPS for TV Video Applications. . . . . . . . . . . . . . . . . . . . . . . . . .. 1165
AN410 - TEA2037 Horizontal & Vertical Deflection Circuit .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1195
THERMAL MANAGEMENT
AN467 - The Powerdip ( 16+2+2, 12+3+3) Packages .................................... 1215
AN261 - Designing with Thermal Impedance . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 1229
AN262 - Thermal Management in Surface Mounting ..................................... 1243
AN257 - Thermal Characteristics of the Multiwatt Package ................................ 1257
AN258 - Thermal Characteristics of the Pentawatt-Heptawatt Packages . . . . . . . . . . . . . . . . . . . . .. 1265
AN264 - Resistance to Soldering Heat and Thermal Characteristics of Plastic SMDS . . . . . . . . . . .. 1273
AN260 - Handling and Mounting ICs in Plastic Power Packages ............................ 1283
AN314 - T0220AB-T03-TOPLESS: Thermal Resistance and Mechanical Assembly ............ 1287
10
TECHNOLOGY AND BASICS
11
APPLICATION NOTE
SMART POWER PROCESSES
FOR LSI CIRCUITS
by Carlo Cini
Over the years smart power technology has advanced to ever-increasing power and voltage levels. At the same time, almost unnoticed there has been a remarkable increase in the smartness
of circuits -- the amount of complexity that can be integrated practically on one chip.
Today, for example, it is possible to integrate circuits like the one shown in figure 1, which contains two 1A motor drives, a 3A solenoid driver, a
1A switch mode power supply and a micro interface (this chip will be described in more detail
later). Clearly the possibility of integrating so
much of a system has a dramatic effect on the
way system engineers approach partitioning;
complexity is no longer limited by technology, but
by economic factors.
The technologies that allow such circuits to be
made are generally known as "BCD" technologies
because they combine bipolar, CMOS and DMOS
process structures. First introduced by SGS in
1986, they allow IC designers to use bipolar components when high precision is needed (in references etc), CMOS for high density digital and
analog, and power DMOS for low dissipation output stages.
Low dissipation is, in fact, one of the key advan-
tages of BCD technology. A DMOS powertransistor in switchmode operation dissipates very little
power so it is possible to deliver high power to the
load without expensive power packaging and
cooling systems (the power that can be dissipated
inside an IC is determined by the package).
Equally important is the fact that low dissipation
power stages make it feasible to place several
power stages on the same chip. This, together
with the high density CMOS, makes high complexity circuits feasible.
BCD TECHNOLOGY
The first commercial process to combine bipolar,
CMOS and power DMOS was the MultipowerBCD process introduced by SGS-THOMSON in
1986. A 60V technology, this was created by
merging vertical DMOS technology with a conventional junction-isolated bipolar IC process (figure 2).
Figure 1: A High Complexity Smart Power IC Containing Multiple Drivers.
AN446/0392
1/6
13
APPLICATION NOTE
Figure 2: Cross Section of the Multipower-BCD Process.
5 GO
~--_~I
HV P-CH
o
5 GO
SGD DGS
P-CH
N-CH
VDMOS
HV [RP
[-MOS
~
NPN
LPNP
This parameter appears to improve by a factor of
two every four years. In the signal section the
most common parameter is the number of ~ransis
tors per square millimeter. Here ,Progress IS ~o~e
marked than in the power section because It IS
possible to exploit the knowhow existing in VLSI
technology where the microlithography is the
dominating factor and not the current.
A high voltage (>600V) version is also close to introduction. The 60V and 100V versions cover the
majority of applications today, in industrial, computer peripheral, automotive and consumer products. At present the main applications for 250V
technology are in lamp ballasts and power s~p
plies, though it is expected that when new high
pressure gas discharqe I~ml?s ar.e adopted by th,e
automotive industry CirCUits In thiS technology Will
be appropriate, The expected uses of 50~V technology are mainly in offline power supplies and
home automation,
EXAMPLE PRODUCTS
We will now examine some typical BCD IC exemplify the remarkable versatility of the technology.
Figure 3 shows the block diagram ?f a Chip int.roduced in 1988 for a portable typewriter application
-- the chip shown in figure 1.
This circuit integrates 15 power DMOS transistors
and about 4000 other transistors. On this chip are
all of the power subsystems needE!d in the ~vpew
riter: a 1A motor drive for the carnage posltlon,er,
a 1A motor drive for paper feed, a 1A motor drive
for the daisy wheel, a 3A solenoid driver for the
hammer and a 1A/5V switch mode supply that
power the micro .. In <;tddition the ch,ip includes all
of the interface CirCUits, control logiC and protection circuits. One interesting characteristic of this
circuit is that most of the functions are programmed by loading internal registers .. It is ~ven
possible to program output stage configurations,
-------------- ""1' S[iS-THOMSON
~u©lmm~~©1fIm@OllU©~
14
BeE
LI_ _ _ _-'1 l---.JI,--_ _ _ _ _-'1 ~I_ _~I LI_ _ _ _- '
An important characteristic of this technology is
that it provided all of the contacts on the top surface of the die and completely isolated the pow~r
DMOS transistors. This was important because It
allowed the integration of any kind of power
stage: high side, low side, half bridge or bri~ge.
Moreover, multiple power stages could be Integrated on one chip.
Having bipolar, CMOS and DMOS structures
available gives the designer freedom to choo~e
the most appropriate for each P?rt o.f th~ CI.rCUIt.
Bipolar structures are used primarily In linear
functions where high precision is needed: low o~f
sets low drift and so on; it can also be useful In
predriving stages. CMOS is useful both for hi~h
density logic and high density analog Circuits
where high precision is not needed.
DMOS power stages have several important ?dvantages over their bipolar equivalents. Most Important is the low dissipatio~", which is be.cause
DMOS devices need no driVing current In DC
conditions and operate very efficiently in highspeed switching applications. Other advantages
include the freedom from second breakdown and
the presence of an intrinsic freewheeling diode,
which is useful with inductive loads.
Since the original 60V process was introduced
several other process variations have been introduced: a 1OOV version, a 250V version and a n~w
family of shrink processes called BCD-II, which
use a 2.5u geometry. The evolution of these can
be continuous and to give an idea of the improvement made and forecasted there are two values
(Ron x area and number of transistors per square
millimieter which express clearly the strength of a
technology. For the power components there is
the Ron x Area parameter which indicates for a
given area the reduction in ON re.sistan?~, and
hence the improvement in the electrical effiCiency,
or rather, the reduction of the power dissipated.
2/6
BE C
_ _ _ _ _ _ _ _ _ _ __
APPLICATION NOTE
Figure 3: Block Diagram of the Chip Shown in Figure 1.
..dl----.--~f-----r-l
PLQ08
Us
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Vss
SMPS
11
12
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HS02
LS01A
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LS02A
LS02B
Rsens1
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A8
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02
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26
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33
32
31
38
24
23
Ul
a:
MICRO
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w
:>
DUAL a:
0
OAC
35
37
34
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HS01
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LS01A
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Rsens2
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~u 43
a:
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Rsens3
f191L528B-B3A
an interesting concept that makes the device
more flexible than one would expect from such a
complex and highly-specific solution.
With the introduction of the shrink version, BCDII, circuits of this complexity have become smaller
and less expensive. Figure 4 shows a recent
example of a custom circuit in BCD-II technology
for a computer peripheral application that includes
a servo positioning system, motor controller and
various other functions that were not integrated
on other ICs on the board.
Figure 4: Complex Smart Power Chip Realized with Shrunk BCD-II Process.
---------------------------~~~~~~~~::~
3/6
--------------------------15
APPLICATION NOTE
Though most BCD circuits use switchmode
DMOS power stages it is also possible to use the
technology in linear applications, as illustrated in
fig4re 5, which shows a quad linear regulator
chip. Designed for a car radio, this circuit contains
four regulators (10V/60mA, 8V/50mA, 5V/300mA,
5V/600mA) with bipolar PNP pass transistors.
BCD technology was chosen in this case for several reasons: low cur-rent drain, compact die size
and the possibility of having an uninterrupted
positive output even in the presence of a negative
dump transient.
The circuit shown in figure 6 is an example of a
multiple power chip. for the automotive market.
This chip is used in rearview mirror units .and
drives the three motors (mirror adjust up/down,
adjust left/right and fold) plus the defroster heating element. Mixed bonding is employed in this
circuit.
Figure 7 shows a practical high voltage ICfabricated in BCD250 technology for a compact fluorescent lamp ballast application. A DMOS bridge
output stage is clearly visible.
Figure 6: Multiple Smart Power Chip for Car Mirror Control.
-----------------------------
4/6
16
~~~~~~~:oo~~
-----------------------------
APPLICATION NOTE
FAST DEVELOPMENT
The design of a BCD smart powerlC, even. a
complex one, is surprisingly s~ort. From th~ onginal idea to having a part working perfectly In the
application takes typically six to ten months.
These parts may not meet the original spec
100% or SGS-THOMSON's yield standards, but
they are good enough to use in production. Very
complex ICs can be developed in roughly the
same time because it is possible to divide the
work between several designers. Unlike digital
chips, in fact, a smart power IC is often designed
by a single ?esign engineer. T~is f.ast development is possible because such CIrCUitS almost always use just well known and p~edictable. elements -- mainly library cells -- which are simply
interconnected. And unlike linear power ICs, the
DMOS power stages usually operate in switchniode, which makes their behavior more predictable. The low power dissipation of power DMOS
also helps because it minimizes unwanted thermal interaction~.
In some cases the designer may also opt to use
automatic layout techniques. This method is fast,
Figure 8: Example of Layout Generated Using Automatic Software Tools.
17
APPLICATION NOTE
though it is not used where die size has to be reduced using manual layout. The circuit shown in
figure 8 is an example of a BCD circuit laid out
using automatic design tools.
Further time is saved by the application of 100%
layout verification using CAD. This practically
eliminates the risk of the first silicon not working
because of a layout error.
PACKAGES
In power ICs, where dissipation is a fundamental
limit, packaging very often determines both the
performance and the cost of ICs. Fortunately for
users of automatic assembly equipment in this
area radically new packaging concepts are not
expected in the near future.· All of the ICs described here are, in fact, housed either in DIP,
chip carrier or power packages like the Multiwatt
15-lead power tab package.
For high complexity types, where the pin count is
generally high, plastic-leaded chip carrier PLCC
packages are very popular. By modifying the lead
frame, replacing all of the leads on one side bya
triangular head spreader, it is possible to dissipate as much as 2.5W in a 44-lead PLCC. This is
the package used for the chip in figure 1.
Where the highest output power is needed packages like the Multiwatt are used. To cope with the
high currents involved in some circuits a mixed
bonding technique has been developed for this
package, using thick aluminum wires for the high
current connections and thin gold wires for the
others. An example of this is shown in figure 9, a
10A switching regulator IC. Thick aluminum could
not be used for all connections because the large
bonding pads required would waste too much silicon area; the use of multiple gold wires for power
connections would compromise reliability.
BCD technology is often described as "mixed",
primarily because it mixes bipolar, CMOS and
digital. But it can also be described as mixed because it mixes analog and digital, because it
mixes signal and power, because it mixes thick
and thin metallization, and because of the mixed
bonding technique.
Figure 9: An example of a power IC using mixed wire bonding.
----------------------------~~~~~~~~:~~A ----------------------------18
6/6
t=-=
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APPLICATION NOTE
SMART POWER TECHNOLOGY EVOLVES
TO HIGHER LEVELS OF COMPLEXITY
by Bruno Murari
Smart power devices are the shooting stars in power semiconductors, because it's possible to integrate digital and analog functions together with multiple power stages on the same silicon chip.
The trend towards higher density will continue.
Since it was first introduced in 1986, mixed bipolar/CMOS/DMOS 'smart power technology has
evolved rapidly, extending voltage capability and
integrating highly complex subsystems on single
chips containing thousands of transistors.
Integrated circuit fabrication technologies that
combine bipolar, CMOS and power DMOS structures on the same chip have had a significant impact on "smart power" integrated circuit design.
Since the dissipation of power DMOS stages in
sWltchmode operation is very low it is possible to
produce ICs capable of delivering substantial
power to the load without the usual heatsinks,
cooling fans and so on. Moreover, because it permits the integration of high-density CMOS and
multiple DMOS power stages the traditional constraints on complexity are removed and circuits
containing complete subsystems have been produced. An example of this is shown in figure 1 a custom IC that integrates a motor control system, servo positioning system, a step up converter, microprocessor interface and other circuits.
Figure 1: An example of the complexity now possible in smart power ICs. This custom LSI device
developed by SGS-THOMSON for a computer peripheral application that integrates a servo
positioning system, DC motor controller/driver and various other "glue" functions" not
ihtegrated in the other ICs on the board.
AN447/0291
1/5
19
APPLICATION NOTE
BCD TECHNOLOGY
A power IC technology combining bipolar, CMOS
and power DMOS was first introduced by SGSTHOMSON in 1986. Called Multipower-BCD, this
was a 60V process created by merging a conventional junction-isolated bipolar IC process with
vertical DMOS technology. The result is a process requiring 12 masks in the standard version
- no more complex than modern bipolar technologies.
Where this process departed significantly from
previous smart power processes is that it employs
isolated DMOS power devices. The significance
of this is that designers are not limited to a single
power DMOS transistor per chip, but can have
any number (hence "Multipower") and connect
them in any way. Thus it is possible to integrate
any power stage configuration (low side, high
side, half bridge or bridge), or even to have several complete power stages on the same chip.
Clearly the combined BCD process gives circuit
designers the possibility of choosing the optimal
technology for each circuit function: bipolar is the
first choice for linear functions where high precision and low offsets are required; CMOS is best
for complex analog and digital signal functions
because of its high density; and power DMOS is
ideal for power stages.
It is the possibility of integrating power DMOS
stages that gives BCD technology its greatest advantage: low dissipation. Unlike bipolar ,power
transistors, power DMOS devices need no driving
current in DC conditions and operate very efficie'ntly in fast switching operations.
This low dissipation can be exploited to' increase
the amount of useful power that can be achieved
with a given package. For example, both SGSTHOMSON's L296 bipolar power switching regulator and the functionally similar L4970 BCD type
are assembled in the Multiwatt package, but the
bipolar version delivers up to 160W while its BCD
counterpart delivers up to 400W.
An alternative way to profil'from low dissipation is
to use less costly low power packages in place of
high power packages. Very often a bipolar power
IC in a power packag'e can be replaced by a BCD
part in a DIP, or even PLCC or SO, package. This
can bring substantial savings not only because
power packages are more costly, but also because they'are more costly to mount on the board
and are not well suited to automatic assembly.
For example, a 4A bipolar switching regulator IC
in the Multiwatt package can be replaced by a
BCD switching regulator in a DIP package (figure
2) which delivers almost the same current.
·Figure 2:The low dissipation of power DMOS
can be exploited to make power ICs in
low power packages, which are less
expensive and easier to mount. This
DIP-packaged switching regulator
delivers 3.5A, replacing a Multiwatt
packaged bipolar IC.
Recently SGS~THOMSON has introduced a
"shrink" version of the original BCD proCess called BCD-II - which greatly increases the circuit and current density that can be achieved (figure 3).
The original Multipower-BCD process family used
4 micron lithography.
In the BCD-II versions this is reduced to 2.5
microns.
Consequently the current density and component
density are approximately doubled, In the case of
the 60V version, the shrink increases signal compone~ density from 650 transistors/mm to 1500
tr/mm ; at the sam~ time the RON.Ar~a is reduced
from 0.9 ohms/mm to 0.5 ohms/mm..
~
-------------Iiii ~~~~m~~~:U!~©$N -----~--------
20
APPLICATION NOTE
Figure 3: A shrink version of the Multipower-BCD technology has now been introduced. Called BCD-II, this
version doubles the component density, making high complexity devices much less expensive.
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STANDARD BCD PRODUCTS
The first BCD chips to be marketed were the
L6202 and L6203 DMOS bridge driver ICs - actually the same die assembled in DIP (L6202) and
Multiwatt (L6203) packages. Both of these devices have an ON resistance of 0.3 ohms, which
gives a maximum continuous current of about
1.SA (DIP version) and 3A (Multiwatt version).
These were followed by a variety of power ICs for
computer peripheral, industrial and automotive
applications. Typical examples include switching
regulator ICs, lamp drivers for automotive applications and motor drivers of various types.
All of the early chips and many introduced more
recently are standard devices in the sense that
they are normally used in various end products,
like standard Iinears or standard logic. In the late
eighties, however, designers began to apply BCD
technology to make power ICs with a complexity
that can truly be called LSI.
LSI COMPLEXITY IN POWER ICs
We have seen that BCD technology allows an arbitrary number of complete power stages on one
chip and the dissipation of each is low enough to
ensure that the cumulative dissipation of these
power stages is within the limit of practical packages. Moreover, high density CMOS allows signal
level circuits of LSI complexity to be added on the
same chip.
An interesting consequence of these factors is
that BCD technology allows the IC designer to
build complex systems on a single chip. Moreover, the technological limit on complexity is beyond the complexity of a wide range of end products.
The first example of a circuit that exploits the
[-MOS
NPN
BC E
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LPNP
possibilities of LSI smart power is the L6280, a
device introduced in 1989 for a portable typewriter application (figure 4). This IC integrates two
1A motor drivers, a 3A solenoid driver, a SV/1 A
SMPS and microprocessor interfacing circuitry all of the power subsystems of the typewriter. The
L6280 behaves like a microprocessor peripheral,
latching commands from the bus. All of the functions can be controlled by software - even the
output stage configurations.
Surprisingly, perhaps, the overall dissipation of
this complex IC is so low - less than 1.SW - a
power package was not needed. In fact the
L6280 is assembled in a PLCC 44 chip carrier,
though the 11 pins on one side are all connected
together and used to conduct heat to the PCB
tracks.
Since then the same approach has been applied
to other applications of comparable or greater
complexity. One example is a custom chip designed for a computer peripheral application (figure 1) that integrates a motor control circuit, a
servo positioning system, a step up converter, a
microprocessor interface and various other glue
circuits needed on the board. There are 12 power
transistors and roughly 4000 other transistors in
this IC. Such a solution is extremely effective because of the increasing trend towards very compact solutions.
BCD technology can also be applied in areas
where the emphaSis is more on "smart". than on
power. An example of this is the telephone set.
Using Multipower-BCD technology it has been
possible to realize a single-chip telephone that includes a pulse/tone dialler, voice circuit, ringer
and monitor amplifier. Modest power capability is
needed for the ringing transducer and the monitor
loudspeaker, but half of the chip is occupied by
the complex CMOS logic. A total of 16,000 transistors are integrated in this circuit.
---------------- ~~~~~~&~:~~~ ---------------3/5
21
APPLICATION NOTE
Figure 4: Designed for a portable typewriter application, the L6280 integrates two motor drivers, a
solenoid driver, a power supply and complex control logic .
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The introduction of the shrunk BCD-II technology
both increases the amount of logic that can be integrated at a reasonable cost. This improvement
in microlithography also allows an improvement in
current density of the power DMOS transistors an interesting advantage over bipolar technology
where current density depends on emitter area
and cannot be improved in this way.
It is also interesting to compare the potential complexity increases for various technologies (figure
5). Clearly there has been a much greater .increase in the complexity of pure digital circuits
(about eight decades) than in analog circuits (four
decades). In fact pure analog ICs containing thousands of components are extremely rare. A consequence of these curves is that there is a tendency to use digital techniques whenever possible
because it allows a greater reduction in area. The
possibility of having dense digital circuits on a
BCD chip allows designers power IC designers to
take advantage of this trend.
At present the capabilities of the technology in
terms of complexity generally exceed the demands of system designers, few of which have
learned to exploit fully the level of integration now
possible. Another important consideration is that
LSI smart power devices will· invariably be full
custom and developed for a specific end use with
4/5
IC designers and system designers working
together; at this level of complexity standard products are unlikely.
To create a complex smart power IC the system
designer has to understand the capabilities and
limits of IC technology and consider a highly-integrated solution from the outset. With today's level
of certainty in power IC design this is not a risky
choice.
Given the need to embody system knowhow in
silicon it is evident that some system designers
would prefer to do their own design, using a cell
library approach. SGS cTHOMSON uses such a
design technique in house but we believe that it is
too early to offer this on the market because the
deSign of power ICs is not as mechanical as low
power ICs and the silicon design experience of a
skilled designer is very important. The main difficulty lies in avoiding unwanted interaction between power sections and signal sections where a power IC designer really earns his salary. Another non-trivial complication is that there
is a difference between designing a circuit which
works and designing one that can be produced
and tested in large volumes. Often, in fact, the development of testing hardware and software can
be more troublesome than the design of the IC itself.
--------------------------- ~~~~~~~:9~ --------------------------22
APPLICATION NOTE
Figure 5: BCD technology allows power IC designers to take advantage of the much greater level of
integration achieved in digital technology. Analog functions are replaced by digital equivalents
in complex circuits.
Complexity (Nr.of tr.)
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________________________5_/5
23
APPLICATION NOTE
NEW LEVELS OF INTEGRATION
IN AUTOMOTIVE ELECTRONICS
by Riccardo Ferrari, Marco Morelli
One of the fastest growth areas today in electronics is in the automotive field. In this note the
authors describe the particular needs of this field and some typical dedicated ICs developed by
SGS- THOMSON.
INTRODUCTION
Since the early seventies, more and more functions have been added to our cars not only with
the purpose of guaranteeing a better comfort to
drivers and passengers, but also to reduce operating costs and finally to ensure compliance with
new regulations concerning noise and pollution
are concerned. Because of all these needs, cars
have to house more and more modules designed
to perform more or less complex operations (Fig. 1).
This growth makes more and more evident the
need to reduce the room taken by each module,
with the double target of minimizing the cost of
the particular function and increasing the number
of functions in a specific car; in parallel, by increasing the number of modules, it becomes
mandatory to increase the reliability of each of
them, otherwise the reliability of the total car
would be badly affected.
All these issues recently pushed the manufacturers of automotive systems to refer very often to
producers of integrated circuits asking for the de-
velopment of monolithic devices capable of replacing effectively a number of discrete components, passive parts included; anyway the trend
to a total integration is not over by just designing
onto a simple piece of silicon a complete function,
but it carries on implementing in the same device
a number of auxiliary services, that would add a
substantial cost if achieved by discrete components, that can easily find place on a few extra
square millimeters of silicon.
To that purpose the example given by the alternator regulator, subject of a specific description in
the following pages, is particularly enlightening.
Figure 2 shows briefly the evolution of the alternator regulator paralleled with the evolution of the
silicon technology; it is evident that the key issue
to pursue the monolithic design of very complex
functions in the automotive environment is the
availability of process capable to host on the
same chip high density signal circuitry, together
with power stages managing currents of several
amperes; a process with these characteristics is
usually called "smart power" process.
Figure 1: Electronics in present and future automobiles.
SAFETY &
CONVENIENCE
BODY CONTROL
POWER TRAIN
DRIVER INFORMATION
Rear Window Defoooer
Cruise Control
lanition
Climate Control
Intermittent Wipar
Spark Timino
DiQital Gauaes
DiQital Clock
Kevless Entrv
Antitheft Devices
Voltaae Reaulator
Multitons Alarms
Automatic Door Lock
Electr. Suspension
Alternator
EnQine DiaQn. Results
light Drimmer
Electr. Steering
Idle Speed control
Service Reminders
Traction Control
Multiplex Wiring
Turbo Control
Miles to Empty
Antiskid Braking
Module to Module
Emission System
Shift Indicator
Window Control
Communications
Transmiss. Control
Head-up Display
Memory Seat
Load Sensit. BrakinQ
Diagnostics
CRT DisjJlay
Heasted Windshield
Hard/Soft Ride Control
Audio Annunciator
Voice Controlled Trunk
Airbag Restraints
AN449/0392
1/9
25
APPLICATION NOTE
Figure 2: Alternator regulator evolution.
SEMICONDUCTOR
TECHNOLOGY
EVOLUTION
ALTERNATOR REGULATOR
EVOLUTION
TRANSISTORS,
DIODES
MONOFUNCnON
DISCRETE COMPONENTS
INSERTION TECHNIQUE
I
..1
I
ANALOG IC's
I
MULTIFUNCTION
DISCRETE COMPONENTS
INTEGRATED CIRCUITS ON
CERAMIC LAYER
SINGLE PACKAGE
L
I
TECHNOLOGY OVERVIEW
Ov~r
the years S~S-THOMSONhas developed
various technologies that allow the realization of
smart power circuits. The simplest way to classify
the.se technologies is to refer to the process type,
whlc:h can be purely bipolar or mixed, that is, including on a single piece of silicon both MOS
structures (of control and power) and bipolar
---,
MULTIFUNCTION
DISCRETE COMPONENTS
INTEGRATED CIRCUITS
ON PCB
MONOFUNCTION
MONOLITHIC
SMART POWER
IC's
I
~
MULTIFUNCTION
MONOLITHIC
I
structures.
Another method (figure 3) is to examine the way
i~ which !he curren! flows through the power seclion;. hOrizontal, with the current entering and
leaVing through the upper surface, or vertical,
where the current enters through the upper surface and leaves through the lower surface' for
this lower connection, instead of wire, the tie' bar
Figure 3: Integrated DMOS structures.
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1 OR MORE HV LDMOS DEVICES
WITH COMMON SOURCE
: s.
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I
MANY POWER VDMOS DEVICES
ANY CONFIGURATION
1 OR MORE HC VDMOS DEVICES WITH
COMMON DRAIN
2/9
----------------------------- ~~~~;~~~:~~ --------~-------------------
26
APPLICATION NOTE
MULTIPOWER BCD/60
VS.
BCD6011
Junction isolation
Field oxide
BCD20/60
BCD6011
down
up and down
Tapered oxide
Locos + field implant
VDMOS R on* Area (Q*mm2)
0.9
0.5
LDMOS R on* Area (Q*mm2)
0.6
0.25
CMOS tr. density (mm- 2)
650
1500
CMOS thres. voltage (V)
1.3
1
min. NPN area (miI2)
11
4
min. PNP area (miI2)
Number of masks
of the package is used.
The choice of one technology rather than another
depends o~ various ~Iements. By simplifying as
far as possible the criteria, we can say that vertical techn<;>logies can guarantee, for a given area,
lower resistances but they have the limitation of
b~inQ able to include just one power device per
circuit (or more than one, but always with the collectors or drains short-circuited). Horizontal technologies instead make it possible to have power
structures that are completely independent. It is
therefore evident that a vertical technology will
giv.e excell~nt results in the design of a light
sWitch, while a hOrizontal technology will be
equally well suited to the design of a multiple actuator.
Finally we have to underline that the continuous
evolution of the silicon technologies has already
made available, for the design activity, second
generation processes, offering to the user both
15
5
12/14
13/15
higher component density in the signal section
and higher current density in the power area, so
that in some cases the limit to achieve very low
values of resistance does not come from the silicon, but from the bonding wires. An example of
comparison between a first generation smart
power technology - today in full industrial production - and a second generation one - today available for new designs - is given in Table 1: the
way is open to processes -that will allow the design - on the same chip-actuators - of several amperes together with microcontroller of not negligible power.
It is important at this point to underline that a
smart power circuit does not consist of just silicon
technology, but relies heavily on package technology. In fact it is well known that a signal device
is bonded using gold wires with a diameter of 25
microns; however, gold wires can be used effectively up to diameters of 50 microns, which allows
Figure 4: Mixed bonding technology.
- - - - - - - - - - - - Gil
SGS~1lI0MSON
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3/9
~a©~@~~~i:1lIiil@Liila©@
27
APPLICATION NOTE
Figure 5: Power packages.
reliable operations with currents up to 2A, provided that the wire is surrounded by resin (the
current capacity drops by 50% for wires in free air
- that is, in the case of hermetic packages).
When, however, one has to deal with very high
currents (more than 5A in single-point injection
actuators, and more than 10A for window lift motors) gold wires are no longer suitable for obvious
cost reasons so it is necessary to turn to alu'
minum wires with a diameter from 180 microns to
375 microns; clearly in this case it will be necessary to have adequately dimensioned bonding
pads on the die, with a significant waste of silicon
area.
Optimization is obtained with a mixed bonding
technology where signal pads are bonded with
thin gold wires and power pads with thick aluminum wires (figure 4). A further optimization is
obtained by orienting the pads in the pad-tobond-post direction.
Finally, another key area for a real industrial implementation of a smart power device is packaging; SGS-Thomson has a reputation of unparalleled excellence in the development and in the
production of packaging techniques to meet
power dissipation even in the presence of high
pin count, and several innovative SGS-Thomson
packages have been adopted as worldwide industry standards; in Figure 5 several types are
displayed, including hermetic metal can, particularly suitable for components, such as the alternator regulators, that have to operate at a rather
high temperature, with junction temperature that
may exceed 150°C, in an extremely severe envi4/9
ronment, since the regulator is usually exposed to
any kind of dangerous element, such as grease,
sand, dust, salt water and so on. A quite original
power package for surface mounting, combining
a low Rth j·case (less than 3°C) with a small geometry, is under development in our laboratory.
THREE EXAMPLES
THE ALTERNATOR REGULATOR.
We have already briefly mentioned the evolution
of the alternator regulator, but it is worth covering
with some more details the history of this function.
Since the simple realization of so-called monofunction regulators by means of discrete components - diodes, transistors and resistors - the progress of the technology allowed the design of a
monolithic component, still monofunction: in parallel, to provide the driver with more information
about the status of the charging function, multifunction regulators were designed, but the power.
remained external, on a separate component.
A further improvement came with the assembly
technology on a ceramic substrate, housed in a
single package, but still several chips of silicon
were needed.
Now SGS-Thomson has reached the maximum
level of integration by designing a monolithic
multifunction regulator and offering to the customer a device that minimizes the assembly operations and maximizes the reliability because of
the single piece of silicon and the minimum number of connections between the silicon itself and
----------------------------- ~~~~~~~:~~
28
-----------------------------
APPLICATION NOTE
Figure 6: Block diagram of alternator regulator.
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the rest of the system: nevertheless the accuracy
of the regulation and the number of possible malfunctions monitored by the circuit are well above
what offered so far by the market.
The main characteristics of the device are summarized in Table 2 and the block diagram of the
circuit is displayed in Figure 6_
The choice of the technology required a particular
care and was driven by the following factors:
1)A circuit for the regulation of the alternator
voltage, even if equipped with a complex diagnostic, is however a circuit where the
power section, including the field drive in low
side configuration and the free wheeling
diode plus a big active zener diode, takes a
significant share - qbout one third of the total,
(see Figure7); therefore a bipolar process has
been selected.
2)On the other side, about 600 small signal devices had to be integrated, and because of
that a technology with a good intensity was
mandatory, otherwise the total economy of
the program would have been affected.
3)Finally an alternator regulator must be able to
withstand very severe voltage transients, as
fixed by ISO 7637/1, with voltages up to 270V
and energy up to 50 joule, that arise on the
car electrical network, for instance, if a sudden misconnection of the alternator occurs_
Table 2: MONOLITHIC ALTERNATOR
REGULATOR
" Low side configuration
D
No external component
D Accuracy on regulated voltage better than
1%
D
..
D
•
"
"
..
II
Precise temperature coefficient
Self-oscillating analog regulation loop
Minimized field current at alternator stopped
(500 mA max)
Maximum field current trimmed at 5A, with
1.5V saturation voltage
Full Diagnostic: alternator stopped
Broken belt
Extravo Itage
Broken wire alternator-battery
Protected against short circuit (current limitation and thermal shutdown)
Protected against short circuit of fault lamp
driver
Protected against extravoltages according to
ISO 7637/1
------------------------------ ~~~~~~~~~:~~~
5/9
------------------------------
29
APPLICATION NOTE
Figure 7
THE PEAK & HOLD INJECTOR DRIVER
Let us now consider the U140, another component designed by SGS-Thomson to make available to the user a complex function on a simple
chip; it is an actuator to drive in low side configuration the fuel injector in "single point" injection
system.
As it is well known, quite essential for a good efficiency of the injection system is the capability to
fix in the best way the time while the injector is
opened, since that time is directly proportional to
Considering all of the above, SGS-Thomson has
selected a high voltage process, internally named
BSOII, fully bipolar, horizontal, with lithography of
3Jlm, and more than 100V of breakdown voltage
in the VCBO condition.
The device is encapsulated in an hermetic package, TO-3 multi leads, with bonding wires of 5
mils, able to carry continuous current up to 7 amperes (see again Figure 6).
Figure 8: Injector driver.
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DIAGNOSTICS
SHORT CIRCUIT TO GROUND
SHORT CIRCUIT TO BATTERY
OPEN LOAD
THERMAL WARNING
..
PEAK AND HOLD
SWITCHED
MODE
REGULATION
DRIVERS
VBAT
--- -------
I---~
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:
INPUT
OUTPUT
SLOW/FAST
FREEWHEEL
CONTROL
LOGIC
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6_1_9___________________________
30
~~~~~g~:~~
_____________________________
APPLICATION NOTE
the quantity of fuel transferred to the intake manifold.
Particularly important to fix the fuel volume are
the opening and the closing time of the nozzle,
since both must be extremely fast; now, a single
point injector needs a consistent current in the
apening phase - up to. 5A at the "PEAK" - but
ance opened, less current is enough to maintain
the status - "HOLD" -. At the end af the cycle, finally the driving current must be switched aff in a
time as short as passible. The U140 meets all the
abave mentianed requirements: in addition, in the
"HOLD" phase a further reduction af the current is
achieved by switching an and aff the driver stage
(Figure 8), so. reducing the pawer cansumption
and, as a consequence, the junctian temperature.
A special mentian shall be paid to the transition
from "HOLD" to. the "OFF" condition; as already
said, it is quite important to reduce as much as
possible this time; in the U140 that is achieved by
discharging the inductor through an active zener
set at a quite high voltage (about 70V), and that
guarantees the closing of the injector in less than
50 sec. The same diode is set at 3V .in the HOLD
time. No external component is required by this
circuit, that interfaces directly the microcontroller
of the engine management system; by the way,
the microntroller has just to fix the start and the
end of the injection time, since the U140 is totally
autonomous in fixing the current levels in the different phases, as well as the sampling of the
holding current. (Figure 9).
The device incorporates a very sophisticated diagnostic (see again Figure 8), and transfers to
the microcontroller all the relevant information on
the status af the load.
The advantages of this monolithic devices are
quite evident, if compared with existing salutions
which need not less than 15 components including at least one IC and two discrete transist?rs,
but are nat limited to cost and room reduction,
and to a consistent increase of the reliability: as a
matter of fact the monolithic design allows to get,
practically at zero cost, a very accurate value of
the voltage af the recirculation diode, improving
the accuracy an the ON time of the injector, and,
last but not least, a diagnostic covering all the
possible failure modes of the load.
The circuit is realized with SGS-Thamson's BCD
technalagy, a mixed process including Bipolar,
CMOS, and DMOS structures an the same chip;
the input section is therefore able to. i.nterfa.ce d.irectly a microcontroller, and the low Side driver IS
designed with a DMOS having an ROSON of less
than 0.5 ohm. As already explained the recirculatian diode is set at 70 valt in the transition from
HOLD to OFF; because af that we selected the
~ St:iS.11fOMSON _ _ _ _ _ _ _ _ _ _ _ _7_/9
- - - - - - - - - - - - - - ""11
iltll©rnl@~IbIl©1rWO@~II!:$
31
APPLICATION NOTE
Table 3: MONOLITHIC PEAK AND HOLD INJECTOR DRIVER
•
•
•
•
•
•
Low side configuration
Peak current function of battery voltage to provide a constant charging time
Fast recirculation voltage independent from battery voltage
Slow recirculation at max 3V
Off time and peak current in hold condition internally fixed
Full diagnostic: - open load
- short circuit to ground and battery
- thermal warning .
BCD100, an option with a minimum breakdown
Drain,Source voltage of 1OOV.
All the main features of this innovative device are
listed in Table 3.
REARVIEW MIRROR DRIVING
While we are on the subject of higher levels of integration it is useful to mention the development
of circuits for the multiplex wiring system, which
replaces conventional cabling with a common bus
and "intelligent" switches.
The intelligent switch circuits are key components
for the multiplex system, and one of these is a
multiple driver IC,the L9946, developed by SGSTHOMSON for rearview mirror driving applications.
This IC integrates all of the control functions and
power circuits needed in the electronic external
rear-view mirror unit now being adopted for high
end cars and is the first chip to integrate these
functions. (see Figure 10).
An important feature is that the IC is controlled. directly by a microprocessor -- all of the 'posslbl~
drive conditions· are controlled by loading 4-blt
commands and the L9946 generates the appropriate motor control signals.
No external power circuits are needed because
the L9946 drives directly the two motors used for
mirror orientation (Ilp/down and left/right), the
motor that "folds" the mirror for. maneuvering and
the demister heating element. In a typical application the chip is used in multiplex door wiring system where the door is connected to the body by
three wires and all door functions controlled remotely using smart chips.
Inside the chip are four DMOS half bridge power
stages which drive the three bidirectional DC motors, plus a DMOS high side driver that drives the
demister element. Control logic integrated on the
chip decides how these transistors are to be
Figure 10
EN
DRQ
I1!JBL!J!J46-B2
8/9
~
....,I
32
SIiS·THOMSON _ _ _ _ _ _ _ _ _ _ _ __
il\loa:UiI@rn~rna:~UiI@~oa:$
APPLICATION NOTE
Table 4: MULTIPLE HALF-BRIDGE DRIVER
•
•
•
•
•
4.75A TOTAL OUTPUT CURRENT
VERY LOW CONSUMPTION IN OFF STATE
OVERLOAD DIAGNOSTIC
OPEN LOAD DIAGNOSTIC
GROUNDED CASE
switched to achieve the desired motion -- including rapid braking. Two of the half bridges are
rated at 1A output current; the other two half
bridges and the high side driver are capable of
delivering up to 4.75A.
In common with many other dedicated automotive
ICs the L9946 incorporates diagnostic functions.
Conditions such as overload and open load are
signalled to the control micro so that appropriate
action can be taken. In addition there is a standby
pin that allows the micro to put the L9946 into a
dormant state when it is not needed.
CONCLUSIONS
We think we have demonstrated that the industrial availability of processes capable to match, on
the same silicon, high power and complex control
functions is the key element to the integration of
completed functions on a single chip of silicon.
The examples described demonstrate that SGS-
Thomson has developed a technology portfolio
that can offer different answers for different applications, always optimizing the trade-off among
the various needs.
On the other side, all the above considerations
would have a merely academic interest if they
were not associated with a convenient cost. It is
clear that the monolithic integration of complex
functions implies the use of not negligible areas
of silicon, and that even in presence of high density processes.
It is therefore important to devote adequate resources to the diffusion technique, to increase the
yield of each process.
Today's chips, up to 30mm 2 (and all the thee
examples are below that limit) can be produced at
prices competitive with an equivalent discrete solution, and in the second half of the 90'S2the target
will be expanded up to areas of 40mm , giving a
green light to the monolithic design of complete
modules.
9/9
----------------------------- ~~~~;~g~:~~ ----------------------------33
APPLICATION NOTE
SMART POWER TECHNOLOGIES FOR
POWERTRAIN & BODY ELECTRONICS
by R. Ferrari
Smart power ICs are becoming increasing by common in automotive powertrain and body electronics. This note provides a general introduction to the subject.
As is well known, electronics is slowly but progressively invading every part of the automotive
environment (figure 1); entering first in the car
radio, it has extended progressively and is now
present in all of the subsystems of an automobile.
For those people who prefer a "historical" approach, the evolution of auto electronics has been
divided into three main sections, each subdivided
into various phases, correlated with the state of
the art in general electronics at that time. Today,
at the beginning of the 90's we are in the SMART
POWER phase, and it is precisely that which we
intend to discuss briefly here (see fig. 2).
We will look at, first of all, some definitions: smart
power or intelligent power indicates those families
of integrated circuits which include both logic control circuits and components capable of delivering
a significant amount of power to a generic load. In
numbers, a circuit can be considered smart power
if it is able to deliver more than 0.5A to the load,
or of withstanding more than 50V, or able to supply a power of at least 1W to the load.
Over the years SGS-THOMSON has developed
various technologies that allow the realization of
smart power circuits (figure 3). The simplest way
to classify these technologies is to refer to the
process type, which can be purely bipolar or
mixed, that is, including on a single piece of silicon both MOS structures (of control and power)
and bipolar structures. Another method (figure 4)
is to examine the way in which the current flows
through the power section; horizontal, with the
current entering and leaving through the upper
surface, or vertical, where the current enters
through the upper surface and leaves through the
lower surface; for this lower connection instead of
wire the tie bar of the package is used.
The choice of one technology rather than another
depends on various elements (figure 5) but simplifying as far as possible the criteria, we can say
that vertical technologies can guarantee, for a
given area, lower resistances but they have the
limitation of being able to include just one power
device per circuit (or more than one, but always
with the collectors or drains short-circuited); while
Figure 1: Electronics in present and future automobiles.
SAFETY &
CONVENIENCE
BODY CONTROL
POWER TRAIN
DRIVER INFORMATION
Rear Window Defogger
Cruise Control
Ignition
Climate Control
Intermittent Wipar
Spark Timing
Digital Gauges
Digital Clock
Keyless Entry
Antitheft Devices
Voltage Regulator
Multitons Alarms
Automatic Door Lock
Electr. Suspension
Alternator
Engine Diagn. Results
Light Drimmer
Electr. Steering
Idle Speed control
Service Reminders
Traction Control
Multiplex Wiring
Turbo Control
Miles to Empty
Antiskid Braking
Module to Module
Emission System
Shift Indicator
Window Control
Communications
Transmiss. Control
Head-up Display
Memory Seat
Load Sensit. Braking
Diagnostics
Heasted Windshield
Hard/Soft Ride Control
CRT Display
Audio Annunciator
Voice Controlled Trunk
Airbag Restraints
AN471/0392
1/11
35
APPLICATION NOTE
Figure 2.
PROGRESS OF ELECTRONICS TECHNOLOGIES
Source· Mitsubishi Motors Corp
Third Generation (System-Wide Control)
·Powertrain/traction system control
""8rake, suspension and steering system control
*Digital Audio
." Multiplexing and Two-power-source system
Second Generation
• Self-diagnostic device
• Electronic ongino control
~ Automobile communication, navigation
." Instrum.panel & TripComputer
." Electron.controlled suspension
." Anti-lock brake
." Audio System
I
I LARGE EEpROM
I SMART SENSOR
First Goneratlon ( Introduction period )
." Solid state radio
." Speed control
• Electric ignition
• Digital clock
." Alternator
SMART POWER
16 BIT MICRO
4/8 BIT MICRO
DIGITALICs
ANALOG ICs
r
TRANSISTORS
DIODES
60
70
80
90
2000
Figure 3: Smart Power Technologies Matrix.
WITH REFERENCE TO:
c
U
R
R
E
N
PROCESS
BIPOLAR
MIXED
BHP
BCD60 (I,ll)
B5011
B100
M1
MO, M2
HORIZONTAL
T
F
L
0
VERTICAL
W
2/11
----------------------------- ~~~~~~~~:~~~ ----------------------------36
APPLICATION NOTE
Figure 4: Integrated DMOS structures.
N-
I
1132t1URAR/
at
10R MORE HV LDMOS DEVICES WITH COMMON SOURCE
G
tf9211URAR [-B2
MANY POWER VDMOS DEVICES ANY CONFIGURATION
1..
1 OR MORE HC VDMOS DEVICES WITH COMMON DRAIN
'='= SCiS·lHOMSON
3/11
- - - - - - - - - - - - - - . .. , / liilH©Il@IIDl.~©'ITI1J@IIlD©$ - - - - - - - - - - - - - -
37
APPLICATION NOTE
Figure 5: Smart Power Technology Matrix selection criteria.
Figure 6.
------------------------- ~~~~~~g~:~~ -------------------------
4/11
38
APPLICATION NOTE
Figure 7: Bonding wire features.
WIRE
DIAMETER
(micron)
RESISTANCE
(mOhm/mm)
D.C. CAPABILITY
(Ampere)
in plastic
package
GOLD
GOLD
25
51
45
11
1.25
2.50
ALUMINIUM
ALUMINIUM
ALUMINIUM
178
254
381
1
0.5
0.2
15
28
43
horizontal technologies make it possible to have
power structures that are completely independent
(figure 6). It is therefore evident that a vertical
technology will give excellent results in the design
of a light switch, while a horizontal technology will
be equally well suited to the design of a multiple
actuator.
It is important at this point to underline that a
smart power circuit does not consist of just silicon
technology, but relies heavily on package technology. In fact it is well known that a signal device is
bonded using gold wires with a diameter of 25
microns; however, gold wire can be used effectively up to diameters of 50 microns, which allows
reliable operation with currents up to 2A, provided
that the wire is surrounded by resin (the current
capacity drops by 50% for wires in free air - that
is, in the case of hermetic packages,
When, however, one has to deal with very high
currents (more than 5A in single-point injection
actuators,. and more than 10A for windowlif1 motors) gold wires are no longer usable for obvious
cost reasons so it is necessary to turn to aluminum wires (figure 7) with a diameter from 180
microns to 375 microns; clearly in this case it will
be necessary to have adequately dimensioned
bonding pads on the die, with a significant waste
of silicon area.
Optimization is obtained with a mixed bonding
technology where signal pads are bonded with
thin gold wires and power pads with thick aluminum wires (figure 8). A further optimization is
obtained by orienting the pads in the pad-tobond-post direction. But while we are speaking of
power it is also important to speak of packages
(figure 9). These packages are part of a long
tradition of TO-220 type packages (with 3, 5 and
7 pins) but recently new needs in assembly are
bringing important evolutions of the classic tab
Figure 8.
5/11
----------------------------- ~~~~~~~~:~~~ ----------------------------39
APPLICATION NOTE
packages. Devices completely encapsulated in
completely isolated packages - called Isowattare already in production; in these devices isolation up to 1000V is obtained with a minimum reduction in the junction-to-case thermal resistance.
On the other hand, the practice of using clips,
rather than screws, for mounting packages is becoming always more common, both to save
space and to obtain better long-term reliability in
thermal conduction. This has led to the. TABLESS
isolated package which accumulates the previous
two needs, while for surface mounting a non-isolated package with a junction-case thermal resistance less than 3'C/W is in development in our laboratories and will be available in industrial
quantities in 1991.
Now that we have examined the means that technology places at our disposition, both in diffusion
and in assembly, we can now examine what typi,
cal structures smart power processes will allow us
to make, and which kind of circuit will normally be
driven by each structure (figure 10).
Figure 9: Power package Matrix.
NOT ISOLATED
FULLY ISOLATED
SCREW
MOUNTING
CLIP
MOUNTING
&
SMD
Figure 10: Intelligent power actuators basic configuration.
HIGH SIDE LOIJ SIDE HALF BRIDGE
FULL BRIDGE
Figure 11: Intelligent power actuators basic protection.
DVERTEMPERATURE
OVERCURRENT
OVERVOLTAGE
v
V
v
SIJITCH-OFF BV
THERMAL PROTECTION
CURRENT
LIMITATION
SIJITCH-OFF, BV
OVERVOLTAGE PROTECTION
-----------------------------
6/11
40
~~~~~~~~:oo~~
-----------------------------
APPLICATION NOTE
I.The typical, so-called High Side configuration,
in which the actuator is located between the
supply and the load, is traditionally used in
the supply of resistive loads,. typically lamps,
but is also suitable for mono-directional motors.
2.when the actuator is between the load and
the ground of the supply system we have a
"low side" configuration, very common for
driving inductive loads such as, for example,
the solenoids that control the opening of
valves (injectors, ASS system, automatic
transmission), but also ignition coils.
3.Finally, when we have to drive a motor that
rotates in both directions it will be necessary
to use a bridge structure; the choice between
integrating the whole bridge or just half of it
clearly depends on the current involved.
Today's technology allows us to realize efficiently a complete bridge to drive a door lock
motor, while it is necessary to use two half
bridges if the load is a windowlift.
In all of these structures there will always be integrated a certain number of protection circuits, to
guarantee survival of the device in the presence
of possible failures in the surrounding ambient
(figure 11).
Figure 12.
-----------------------------
These include, to name a few, the automatic
shutdown when the silicon reaches a critical temperature (which can be caused not only by a short
circuit in the load or its connections, but also by
the degradation of thermal contact between the
device and its heatsink). Today, in certain applications such as fuel injection this automatic shutdown tends to be replaced with a warning signal,
which informs the control unit when a critical situation has been reached, leaving the unit itself to
decide what to do (for example, reduce performance to guarantee functionality).
Another very common structure is output current
limiting, even in the case of a load short circuit.
Usually the intervention of the limitation circuit is
accompanied by a diagnostic signal that is made
available for the control system. Finally, in some
devices a circuit is included that is able to detect
overvoltages in the supply system, disabling the
output stage and placing it in the best conditions
to support the overvoltage.
Given the above, we will now describe a practical
case with the aim of identifying how the design
time can be optimized through a suitable interaction between the system designer and the silicon
manufacturer.
The circuit shown in figure 12 is a dual low-side
actuator designed to drive two independent loads
with currents up to 3A each (typically injectors).
The technology employed is mixed (bipo-
~~~~~~&~:~~~
----------------------------7/11
41
APPLICATION NOTE
Figure 13: Expertise partitioning when designing a smart power actuator.
POWER 1
POWER 2
\
DIAGNOSTIC I
CONTROL POWER I
SYSTEM KNOW-HOW
SILICON KNOW-HOW
lar/CMOS/OMOS) with a horizontal current flow
(BC060); if we pass from the photograph to a topographical diagram of the silicon (figure (3) it
becomes immediately evident that the chip is
divided into a limited number of macroblocks, for
each of which it is easy to attribute project
leadership. In fact it will be an essential task of
the system designers to define the criteria for the
driving of the actuator as it is to define the malfunctions for which the activation of a diagnostic
signal is necessary. On the other hand it is indisputable that only the silicon designer can optimize
the. design of the power section and take advantage of structures already available in his library to
realize those functions which are necessary and
also repeated frequently in different devices.
The system designer, too, can take considerable
advantage from the use of cell libraries so the
total design time can b~ reduced to a minimum
(7 -9 months from the start of the design to working silicon), reducing significantly the gap traditionally existing between a dedicated circuit (full
custom) and a semicustom circuit obtained from
gate arrays or standard cells.
A brief glance at another two circuits, each representative of a technology described above.
In the first we see a highly-innovative circuit for
use in ignition systems. This is the VB020 (figure
(4), a circuit realized in mixed vertical technology
(M2) able to drive directly the primary of the ignition coil, combining a darlington with a vertical
current flow with a driver circuit and TTUCMOS
compatible control circuit (figure (5). In the device
are integrated circuits to limit the collector voltage
(fixed at 450V max).
We conclude this series of examples with the
-----------------------------
8/11
42
L9937 (figure (5), a bridge circuit designed to
drive a door lock motor and therefore capable of
delivering continuous currents of 6A with starting
peaks up to 12A. The device is realized in horizontal bipolar technology and, as appears in the
photograph, is almost entirely occupied by four
large power transistors that constitute the output
stages of the circuit. In this case, too, you can see
the mixed bonding (gold for the signal wires, aluminum for power wires) and the pads oriented to
optimize silicon area. In the block diagram (figure
(6) you can see a chain of diodes which has the
function of monitoring the temperature of the chip.
This brief introduction to smart power technologies would not be complete if it did not dedicate
a few words to the price that the customer must
pay to buy circuits of this type. In fact a typical
question that semiconductor companies frequently hear is "How much does a square millimeter of smart power silicon cost?". Since the
price of a square millimeter of silicon depends on
the total area of the chip I believe that it can be a
pleasant surprise to discover that even for fairly
sizable chips - that is, up to 25/Smm2 - the price
of each mm2 increases very little (about 25%).
The curve of figure 17 gives the trend for areas
between 5 and 50mm2 and, though based on a
theoretical calculation, follows closely the present
commercial reality. Obviously the graph reflects
the current state of the art; if only three years ago
the elbow of the of the curve had been moved violently to the left without arriving at saying that
the evolution will continue indefinitely with the
same speed, it is however reasonable to expect
in the next few years a further extension of the linear zone at least towards the 40mm2 region. As
for the meaning of "1 mm2 of silicon", several
~~~~~~~~:~~n
-----------------------------
APPLICATION NOTE
Figure 14: Fully integrated high voltage darlington for electronic ignition.
'" PRIMARY COIL VOLTAGE UP TO 450V
• COIL CURRENT LIMIT
INTERNALLY
SET
TTL/CMOS
COMPATIBLE INPUT
• BUILT-IN
COLLECTOR-EMITTER VOLT- YIN
AGE CLAMPING
'" OVERVOLTAGE PROTECTION OF THE
DRIVING CIRCUIT
• FULLY
INSULATED
FIVE LEAD POWER
PACKAGE
~:...-.---t3
HV(
DRIVER
GND
Figure 15.
-------------------------~~~~;~~~:9n
9/11
-------------------------
43
APPLICATION NOTE
Figure 16: Full bridge motor driver.
•
•
•
•
•
•
6A OUTPUT CURRENT
LOW SATURATION VOLTAGE
VERY LOW CONSUMTION IN OFF STATE
OVERLOAD DIAGNOSTIC OUTPUT
INTERNAL TEMPERATURE SENSOR
GROUNDED CASE
VB
VO
oun
'--~_--u OUT2
GNO
aT
D--+----+---+-_I-+-l-+~--+---I
D---1HHHHif---'
DF
tN1
rN2
EN
Figure 17: Smart power silicon.
PRICE/mm2
1192~N4?1-81
2.13
1.8
II
UNIT
1.6
j
113cUS5
1.4
1.2
1.13
~
113
~
213
~
313
V
413
59 69 79
CHIP SIZE (Kmils2l
BC06B: 1 mm2 • 65B CMOS TRANSISTORS
1 mm2 • 8B 8IP TRANSISTORS
1 mm2 • B.90hm OMOS
-------------10/11
44
~~~~~~~::9~
--------------
APPLICATION NOTE
Figure 18: Smart power devices.
58
413
f192AN4?1-B2
~
L552
313
~9B42
~ i'---
U0·~
c USB
TDA2GGS
213
~
• ACTUAL/THEORETICAL
113
""" ~1
8
28%
313%
48%
58%
68%
78%
% OF POWER SECTION ON TOTAL AREA
possibilities are given at the foot of the table.
There is another way to evaluate the price of a
smart power circuit, and this is to estimate the
price for each ampere delivered to the load. This
method of calculation is less rigorous and can be
plotted as a graph assuming as size reference the
percentage of silicon dedicated to power compared to the total area of the chip. The line shown
in the figure 18 graph indicates that one ampere
costs approximately 30 cents but can rise to 45
cents for circuits containing particularly complex
control and diagnostic logic, and it can fall to 15
cents for devices consisting essentially of only
power stages. It must be underlined that two consumer devices (L552 and TDA2005 - both audio
power amplifiers) for which we can assume stable
specifications, mature technologies and ample
markets, lie exactly on the curve. This should be
indicative of the final trend for automotive devices
which are as yet young devices in a young market.
11/11
45
APPLICATION NOTE
HIGH CURRENT MOTOR DRIVER ICs
BRING AUTOMOTIVE MULTIPLEX CLOSER
by Riccardo Ferrari & Sandra Storti
Smart power ICs delivering up to 25A complete the family of power components needed in automotive multiplex systems, making it possible to drive even a windowlitt motor directly. With these
ICs the large-scale adoption of partial multiplex schemes moves much closer.
One of the essential prerequisites for the largescale introduction of multiplex wiring systems for
vehicles is the availability of high power ICs capable of driving lamps, motors, solenoids and relays. These ICs must be able to survive in an exceptionally hostile environment, they must be
highly reliable and - since so many are needed
in each vehicle - they must be inexpensive.
Many power ICs suitable for this emerging market
have already been introduced, but a gap was left
at the high current end of the range, where ICs
delivering 20A or more are needed to drive loads
like windowlift motors.
Today SGS-THOMSON has filled this gap with
new power ICs that exploit technologies that
make it possible to build very high current ICs that
are both reliable and economical. Two such ICs
are the L9936 half-bridge motor driver and the
L9937 full bridge motor driver.
The L9936 (figure 1a) contains a half-bridge circuit capable of delivering 20A dc current, which is
sufficient to drive directly a windowlift motor.
Since the motor is bidirectional two of these devices. are used to make a complete drive stage.
Designed for lighter loads, the L9937 (figure 1b)
contains a full bridge delivering up to 6A continuous (12A peak for starting). A single L9937
device drives a bidirectional dc motor.
Figure 1a: Capable of delivering 25A, the L9936 half bridge driver is a smart power IC suitable for
driving windowlift motors in automotive multiplex wiring systems.
VB
VO
IN1
OUT
IN2
OF
aT
AN451/1191
GNO
1/6
47
APPLICATION NOTE
Figure 1b: A full bridge driver, the L9937 delivers 6A (1 OA peak) and is used in motor driving
applications such as doorlock driving.
VB
VD
L..-_+-_----'n OLJT2
OLJT1
GND ~-~--*--~~~-+-1--~-+-~~-~
aT
. . . ._
~-
....-.!---'
DF
IN1
Both of these ICs are fabricated using an enhanced bipolar power process and a new mixed
bonding technology. Bipolar technology has been
adopted for these circuits - rather than the
''BC~'' mixed bipolar/CMOS/OMOS technology
used for other multiplex switches - for several
reasons. First of all, when very high currents are
involved the resistance of the silicon is no longer
dominant - half of the series resistance is
caused by the metallization tracks on the surface
of the chip and the bonding wires. Consequently
there is nothing to be gained by using OMOS
technology to further reduce the output transistor
IN2
EN
resistance. Figure 2 shows the contributions to
the saturation resistance of a power NPN transistor in the BHP20 process used for these ICs. The
use of thick metal (6 microns) significantly reduces voltage drop with high load currents in this
technology.
Another reason for using bipolar technology is
that the. substrate currents generated in the substrate when 20A load current recirculates would
affect low-level CMOS logic. In the L9936 and
L9937 high-level bipolar logic is used in the control stages to avoid this danger, giving excellent
noise immunity. Interfacing to this high-level logic
multiplex wiring
repair. The sim
lion between the
duce
three by the adoptio
Cruqialft"the successor multiplex'WlidngJ
theneq(J.9:sary reliability and perforrpftncf:!;
be adopt(J.don volume produced V?ni()i?s in
. 2/6
----------------------------- ~~~~;~~~:~~~
48
-----------------------------
APPLICATION NOTE
Figure 2: In very high current ICs the voltage drop of the metallization and the bonding wires becomes
significant. This example, a power transistor realized with the BHP20 process (used for the
L9936 and L9937) indicates typical values. Because of this problem it is more important to
optimize the metal resistances than that of the silicon.
POWER NPN
ISOLATED AREA
= 5.7 mm'
MAXIMUM CURRENT = 20A
R SAT = 30 mO
N+
p
is performed in the bus interface chip which will
be placed between the L9936/7 and the multiplex
bus. Since these interface chips are system dependent they are always developed for a specific
application, rather than being standard parts like
CONTRIBUTION TO R
• WIRES
6 mO
• METAL
10 mO
• SILICON
14 mO
SAT:
THIS IS OBTAINED BY:
• USING DOUBLE METAL
THICKNESS (0.7 + 5 ~m)
the power ICs.
The mixed wire bonding technology used in the
new ICs is clearly visible in the photo, figure 3.
Because of the high current it is not possible to
use the standard thin gold wires employed in
Figure 3: The mixed bonding technology used in the L9936 - shown here after bonding but before
encapsulation - reconciles the conflicting requirements of current and silicon area. Thick
aluminum wires are used for the power connections; thin gold wires for the signal connections.
3/6
----------------------------- ~~~~;~~~:~~ ----------------------------49
APPLICATION NOTE
standard ICs. Thick gold wires are out of the
question, partly because of cost, but also because they are too rigid to bond to the chip without damaging it.
One alternative, widely used in simple power ICs,
is to use thick aluminum wires. However, a thick
aluminum bonding wire needs a large bonding
pad on the die. In a simple device like a 3-terminal regulator this is not a problem because there
are few such pads, but for more complex ICs with
eight or more connections the wasted silicon area
would be excessive.
Another alternative, still used by some companies, is to use two or more thin gold wires in
parallel for each power connection. This solution,
however, is costly because more gold wire is
needed and it is prone to reliability problems because it is extremely difficult to verify each bond.
Moreover, for the currents used in multiplex applications so many parallel wires would be needed
this method would be totally impractical.
SGS-THOMSON has developed and industrialized a different solution: a mixed bonding
technology where thin gold wires (50um) are used
for signal connections and thick aluminum wires
(250um) are used for power connections. The two
bonding wire types can be clearly seen in figure
3. Note also that the bonding pads for the aluminum wires are oriented in the direction of the
wire to avoid needless waste of silicon area.
Because gold and aluminum are bonded using
different techniques this has necessitated a twostep bonding operation. Moreover, because of the
combination of different bonding metals the leadframe has to be plated with a special gold alloy.
This plating is selective, being applied only to the
bond area, partly for economy and partly to avoid
gold on the external leads, which could contaminate soldering baths, causing reliability problems
on PC boards.
Different bonding techniques are used to weld the
two types of wire to the surface of the chip. For
the thin gold wires the thermosonic method is
used where an electric discharge first creates a
small ball on the free end of the wire; this ball is
then pressed onto the bonding pad and vibrated
rapidly (in the ultrasonic range), causing the gold
ball and silicon surface to weld together.
The thicker aluminum wires are bonded using the
simpler ultrasonic method, where the wire is simply pressed onto the surface of the chip then vibrated rapidly to weld the wires to the pad. Because more vigorous vibrations are used in this
technique the aluminum wires are bonded first,
followed by the gold wires.
To guarantee automotive-level reliability the
bonds are pull tested on a sample of parts. In this
test the wires are pulled to determine their breaking strength. Gold wires must resist a force of at
least 15g; aluminum wires must resist a pull of
4_1_6___________________________
50
Figure 4: After molding and cropping the finished
part looks like this. This eight-lead
version of the Multiwatt package first developed by SGS-THOMSON in
1979 - has wider lead spacing to suit
the large high current PCB tracks.
130g. Moreover, the wire must break leaving the
bonds intact - if a bond detaches before the wire
breaks the part fails the test.
The L9936 is housed in a new eight-lead version
of the successful Multiwatt package, originally developed bySGS-THOMSON in 1979 (figure 4).
This version has eight leads in line at 0.1"
centers, rather than the usual two rows of leads.
This makes the Multiwatt-8 package suitable for
very high current devices where wide PCB tracks
are needed. An ii-lead Multiwatt package is
used for the L9937.
The new package also has a larger die flag - to
accommodate today's large chip sizes - which
has necessitated the addition of new antistress
features in the frame design. These features ensure a dependable adhesion between frame and
resin - essential for humidity resistance - and
isolate the die flag mechanically from the external
tab to ensure that the die is not damaged if the
tab is deformed during mounting.
In a typical application both the L9936 and L9937
are used with a customer specific interface chiP.
which handles bus interface and protocol handling functions. Two different approaches at the
system level are used today (figure 5). In the first
case each load has its own interface, connected
directly to the multiplex bus. An alternative is to
combines several load units into a single module;
this approach is very attractive in situations like
door multiplex where there is a high concentration
of loads in a distinct and fairly compact assembly.
Figure 6 shows a generic door multiplex solution
of the second type, illustrating the role of the new
high current bipolar driver ICs. In this example an
L9937 drives the door lock motor, two L9936's
drive the windowlift motor, a VN02 high side
~~~~~~~~~~n
_____________________________
APPLICATION NOTE
driver IC drives a hazard warning light (the light
on the edge of the door that turns on whenever
the door is opened) and an L9946 multiple halfbridge IC drives the three rear-view mirror motors
(two for mirror adjustment and one for "folding" of
the whole mirror unit for car washes and so on)
and the mirror de-icing heater. All of these integrated circuits are available today.
Pure bipolar technology is used only for the very
high current ICs. For all of the other parts a mixed
bipolar+CMOS+OMOS technology has been
chosen because of the higher efficiency of DMOS
power stages and because it allows the integration of complex parts. The L9946 multiple half
bridge, for example, has a four high power half
bridges plus a microprocessor interface all on the
Figure 5: Two approaches are being used for multiplex systems. In the first each load has it~. own bus
interface; in the second loads are grouped together and share a common electroniCs module.
This approach is used in door multiplex systems, where the loads are all close together and
multiplex wiring used primarily to reduce the number of wires passing from the body to the
door.
.....
~ .......... ~ ... .
. ..
~.~ ....
MASTER
-....~ ........ ~........ ~.~ ... .
POldER
POldER
POldER
ACTUATOR
ACTUATOR
ACTUATOR
BUS TRANS
MICROCONTR
POWER SUPPLY
j
MASTER
f19Bf1f1STER-B1
-----------------------------
~~~~~~~v~:~~©~
----------------------------5/6
51
APPLICATION NOTE
Figure 6: A typical door multiplex solution will use a mixture of high current bipolar power ICs and BCD
power ICs. Solutions of this type will be on production models in 1991.
MIRROR MOTORS
AND HEATER
HAZARD WARNING
LIGHT
WINDOWLIFT
MOTOR
DOOR
LOCK
MOTOR
~
-0-
-0-
~
I
VN02
HIGH
SIDE
DRIVER
L9936
25AHALF
BRIDGE
L9936
25A HALF
BRIDGE
L9946
MULTIPLE
HALF
BRIDGE
ST9040/E40
8/16 BIT
MICROCONTROLLER
BIMOS
CUSTOM
INTERFACE
L4936
MULTIFUNCTION
VOLTAGE
REGULATOR
L9937
6ABRIDGE
I I
LDP25A
BY239
TRANSIENT
SUPPRESSORS
L9150
BUS
INTERFACE
J1850 BUS
same chip.
6/6
------------------------------~~~~~~~~:~~n
52
------------------------------
APPLICATION NOTE
MIXED WIRE BONDING TECHNOLOGY
FOR AUTOMOTIVE SMART POWER ICs
by R. Ferrari and A; Massironi
By using a mixture of gold and aluminum bonding wires in the same IC, SGS- THOMSON has
found a reliable way to correct very high current ICs that avoids wasting die area.
One of the essential prerequisites for the largescale introduction of multiplex wiring systems for
vehicles is the availability of high power integrated circuits (ICs) capable of replacing relays,
driving directly lamps, motors and solenoids.
These ICs must be rugged and highly reliable yet
inexpensive. Many power ICs suitable for this
market are already available but a gap was left at
the high current - roughly 4A+ - end of the
range; ICs delivering 20A or more are needed for
loads like windowlift motors.
One of the main problems in high current IC design lies in the thin wires that connect the silicon
chip itself to the external connections of the IC
package. These. bonding wires are typically fine
gold wires (up to SOum thick) which cannot carry
more than a few amperes of current.
Increasing the thickness of the gold wires is ruled
out partly because of cost, and also because they
are too rigid to weld to the surface of the chip
without damaging it. It is possible in theory to use
two or more gold wires in parallel for each connection but this solution is generally impractical
because the large number of bonding pads waste
space on the chip (the cost of a silicon chip is proportional to its area), the cost of the wire is excessive and because testing each bond is difficult.
Figure 1: Part of an almost completed strip of integrated circuits utilizing the new mixed bonding technology. The gold and aluminum wires connecting the silicon chip - the small gray rectangle with the gold-plated external connections can be clearly seen.
AN483/1090
1/3
53
APPLICATION NOTE
Figure 2: After the wire bonding operation the
completed frame assembly is encapsulated in black plastic resin and the
parts of the metal frame that served as
a mechanical support are removed.
The finished parts are then tested and
marked with the type number and lot
tracing information.
One alternative, widely used in simple power ICs,
is to use thick (250um) aluminum wires. However,
a thick aluminum bonding wire needs a large
bonding pad on the die. In a simple device like a
3-terminal voltage regulator this is not a problem
because there are few such pads, but for more
complex ICs with eight or more connections the
wasted silicon area would be excessive.
SGS-THOMSON has developed and industrialized an effective and efficient solution to this
problem; a mixed bonding technology where thin
gold wires are used for low current connections
and thick aluminum wires used for power connections. Figure 1 shows a bonded frame of a 20A
windowlift motor driver that uses this method; the
two types of bonding wire can be clearly seen.
Figure 2 shows the same IC after encapsulation
with black molding resin and removal of the support elements of the frame.
Because of the use of aluminum bonding wires a
selective gold alloy plating of the leadframe is
necessary; gold is one of the few metals that will
weld reliably to aluminum. Apart from reasons of
cost, gold plating is used selectively -- rather than
the simpler overall plating -- because of gold were
used on the external lead part of the frame it
would contaminate the circuit board soldering
bath, leading to possible.reliability problems.
Different bonding techniques are used to weld the
Figure 3.
V
__
3 ______________~___________ ~~~~~~~~:~~ _____________________________
54
APPLICATION NOTE
two types of wire to the surface of the silicon chip.
For the thin gold wires the thermosonic method is
used where an electric discharge first creates a
small ball on the free end of the wire, this ball is
then pressed on to the bonding pad and vibrated
rapidly (in the ultrasonic range), causing the gold
ball and silicon surface to weld together.
The thicker aluminum wires are bonded using the
simpler ultrasonic method, where the wire is simply pressed onto the surface of the chip then vibrated rapidly to weld the wire to the pad. Because more vigorous vibrations are used in this
technique the aluminum wires are bonded first,
followed by the gold wires. On the production
lines two separate machines are used in tandem.
Reliability is an important consideration in automotive ICs therefore it is essential that wire bonds
be secure throughout the lifetime of the circuit. To
ensure that bonds are correctly executed some
parts are subjected to a pull test, where the wires
are pulled to determine their breaking strength.
Gold wires must resist a force of at least 15g; the
-----------------------------
thicker aluminum wires must resist a pull of 130g.
In both cases the wire must break; the bonds
must not detach.
These pull tests are also repeated on statistical
samples after accelerated life testing where parts
are subjected to humidity, thermal cycling, and
other stresses.
Mixed bonding technology can be used in various
different power IC packages, though the photos
here show the Multiwatt-8 package. This type has
eight leads in line at 0.1" centers - wider than is
usual - to suit high current circuits where wide
circuit board tracks are used. The metal frame design of such packages reflects the care taken to
ensure reliability in line with the needs of the auto
market. For example, the die-mounting zone of
the frame is isolated mechanically by notches and
groove from the external mounting tab area. This
ensures that deformation caused by overtightening the mounting screw will not subject to stress
that could adversely affect reliability.
~~~~;~~~~~n
----------------------------3/3
55
APPLICATION NOTE
HOW DESIGN RULES INFLUENCE THE HIGH FREQUENCY
SWITCHING BEHAVIOUR OF POWER MOSFETs
by A. Galluzzo, M. Melito, M. Paparo
ABSTRACT
Starting from the basic structure of a Power
MOSFET this paper describes the electrical
equivalent circuit, it analyses in detail the
relationship between the physical structure
and the switching behaviour of the device,
mainly in the high frequency range,
introducing RDS(on), C I and C OSS gate
charge concepts.
A comparison of power losses of devices rated
at different BV DSS of die size is carried out.
The influence of the state-of-the-art Power
AN474/0492
MOSFET structure on the ruggedness of the
devices (dV/dt induced from the application
circuit and unclamped inductive switching) is
also briefly analysed.
Some future structural modifications
improving both switching behaviour and
resulting ruggedness are described.
Lastly a brief overview of IGBT technology is
discussed underlining their advantages and
drawbacks compared with Power MOSFET
devices.
1/9
57
APPLICATION NOTE
INTRODUCTION
In spite of their relatively recent introduction
on the market Power MOSFET devices are
becoming certainly the most successful "high
runners" in the Power actuators and industrial
application field because of the inherent
advantages introduced in terms of switching
times and simplicity of the drive.
This paper aims to outline some of the factors
that are under the control of the Power device
designer that enable him to improve the
performance of Power MOSFETs for the
benefit of system designers while leaving the
basic Power MOSFET structure unchanged.
POWER MOSFET EQUIVALENT CIRCUIT
Fig 1 shows the cross section of an N-channel
enhancement mode Power MOSFET
structure while fig. 2 shows the equivalent
electrical schematic of the device including
the most important parasitic components
playing a crucial role for the switching and
ruggedness performance of the device.
A Power MOSFET is realized by fabricating
thousands of elementary square cells where
source regions are connected together by
means of a common surface metallization 1.
s
Gale
A polysilicon layer interconnects the gates of
all cells. The source region of a cell is inside
a P-Iayer which forms the channel region
necessary to control the vertical current flow
of the device.
The following list is a key to the drawing of
the simplified model shown in figure 2:
RG
=
Polysilicon gate resistance
C1 =, Capacitance between gate and source
C2 = Capacitance between gate and P
region
C3
=
Capacitance between gate and N
epytaxial layer
C4 = Capacitance of the channel depletion
zone
C5
=
Capacitance of the depletion zone in
the superficial epitaxial layer
C6
=
Capacitance of the body-drain junction
In the text, reference is also made to the
following capacitances:
C GO : total equivalent capacitance between
gate and drain
CGS : total equivalent capacitance between
gate and source
Cos: total equivalent capacitance between
drain and source
Rgo\e.
Rsource
C5
p+
',0,oC3
T
I
~
DRAIN
N-
C4
C1
N+
Fig. 1 - Power MOSFET structure:
Fig. 2 - Power MOSFET equivalent circuit.
219
-----------'--LV ~~~m~~:9J: ------------58
APPLICATION NOTE
The parasitic bipolar transistor shown in fig.2
is formed by the body region between the N
area of the source and the N epi layer of the
drain.
The body-source resistor is due to the P-body
bulk resistance and the P-body/metal contact
resistance.
For most of the applications it is sufficient to
substitute, on the schematic diagram, a "bodydrain diode" in place of this parasitic bipolar
transistor.
Device behaviour is straightforward in fact with
positive drain-source biasing, as soon as the
gate source voltage reaches the threshold
voltage (V th ), necessary to invert the P-well
region below the gate oxide, the current
begins to flow from drain to source regions.
The relationship between V DS' VGS and ID is
the typical input-output characteristic.
In switching applications, once the circuit
topology has been established (type of
converter, frequency, magnetics etc.), the
optimization of the design requires the
minimum of power losses possible.
During the device's on-state, R DS(on) is the
parameter to be taken as low as possible to
reduce losses; this parameter is normally
defined as follows:
RDS(on)= RCH + RACC + RJFET + R EP1
Where:
- RCH is the channel total equivalent
resistance, depending on the horizontal
layout of the device channel length and
channel perimeter,
- RACC is due to excess charges within the
drain region below the gate oxide,
- RCH and R ACC are the most dominant
contribution for low voltage devices,
- RJFET is the resistance of the drain region
between the P body regions of two adjacent
cells,
- R EP1 is due to the intrinsic epy bulk
resistance therefore strongly dependent on
BV DSS '
SWITCHING BEHAVIOUR
The switching behaviour of a Power MOSFET
is affected by the unavoidable parasitic
capacitances of the structure. Therefore
switching losses can be predicted taking into
account the gate charge curve and the output
capacitance, CDS' Second order effects due
to packaging and assembly will be neglected
in the following discussion as they can be
taken into account by means of suitable
macromodels for computer simulation [2.3]
The gate charge curve (fig.3). obtained by
injecting a constant gate input current is split
into several areas.
At the beginning, starting from
VGS = 0, Ci = C1 + C2 + C5.
ID remains equal to IDSS until V GS reaches
VTH (region 1); C4 decreases further when
VGS increases so that when
VGS
= VTH ,
Ci '" C1 + C4 + C5.
Therefore ID builds-up while VGS increases
from VTH up to VTH + ID/gm (region 2). Due to
the linear behaviour of the Miller body drain
capacitance, VGS remains constant while V D
decreases until the device becomes fully ON
(region 3 and 4)
Ci = C1 + C4 + C3
In the saturation region (5) a further increase
of V GS yields a V DS decrease down to
RDS(on) • ID·
The gate charge curve is obtained at constant
gate current hence the horizontal axis is
proportional to the stored charge and to the
time necessary to switch on and off under
defined driving conditions.
3/9
--------------------------~~~~~~::::~-------------------------59
APPLICATION NOTE
/
'0/ ~
J
-
V1ll
VGS
Vos
{I\
'0
o1
2
VX
~
3
VOSAT
VOSCON)
q "
Fig. 3 - Load line and dynamic characteristics versus gate charge.
Therefore it follows that a first comparison
between two devices rated at the same
voltage and ROS(on) can be made by simply
looking at their gate charge characteristics.
Cos capacitance does not influence the
evolution of the gate voltage but is responsible
for the power losses during switching.
Cos does not generally limit the dV/dt
. experienced by the drain region. In fact, for
a high voltage device (IRF830) with the
following bias conditions:
drain voltage V DO = 400V
gate voltage max VG = 15V
gate external resistor RG = 10 ohm
do
= charge
dV/dt
variation inside zone 3 of the
gate charge curve the dV/dt imposed by
the drain voltage is:
= VOo'
(VG - VTH)/(d o ' RG)
=
400 • (15-3.5) = 23 kV/msec
20 • 10-9 • 10
As: 10 = COS' dV/dt and Cos = 44 nF (typical)
10 is about 1A
10
4/9
= 44'
10-12 • 23' 109
= 1A.
- - - - - - - - - - - - - L"'!I
60
A current of roughly 1 Amp is then required to
charge Cos at the dV/dt set by the gate circuit:
because the device has a nominal current of
5 Amps, Cos has little influence when an
IRF830 is used in standard applications.
This means that in most of the cases it is
possible to take into account the effects of COs
when calculating the power dissipation during
both turn-on and turn-off.
The situation in resonant converters is quite
different, where the current or voltage is
negligible during switching and the previous
approach is no longer valid. Cos effects now
influence the stored energy.
Fig. 4 shows how ROS(on) and Cos limit the
device working frequency in resonant
converters.
The power dissipation versus working
frequency for devices rated at different
breakdown voltage, die size and ROS(on) has
been analysed,
It can be observed that a high voltage Power
MOSFET dissipation at low frequency is
greater than the power dissipation of a
medium voltage one with the same die size.
~~~~m~r::oo~l:
-------------
APPLICATION NOTE
BVdss • 500 V
Pd (W)
f (KHz)
100t--c--~-----------r--l"--I
Coss (pF)
l~~=-~~-u~~~~~u=~~lli
1.5
2.5
3.6
4.5
0.001
0.01
Ron (ohm)
0.1
1
10
100
1000
f (Khz)
Vdd· 350 V, ld· 5 A
Tc-25C
Fig. 4 -How ROS(on) and Cos limit the device
working frequency.
Fig. 5 - Power Dissipation versus frequency.
A simple explanation can be based on the
higher value of Repi of high voltage devices
in comparison to medium voltage ones.
Increasing the cell packing density, especially
for low voltage devices allows reduction of the
die size while maintaining the same R OS(on)
and gives an improvement in capacitance
values and of the power dissipation at high
frequency (where the power losses are more
significant during switching).
Fig. 5 shows that a well defined application
requires the right Power MOSFET device. A
device with a large ROS(en) will be preferable
for the same BV OSS if the target is optimised
efficiency at high frequency.
Cell dimension and the distance between
adjacent cells are respectively 19/1m and
15/lm for standard devices, 14/lm and 8 /lm
for very high density device, 10/lm and 6/lm
for ultra high density devices.
PERFORMANCE vs LAYOUT RULES
For low voltage devices it is possible to
improve the RDS(en) and the gate charge curve
by optimizing the horizontal layout and dopant
profile. Fig. 6 shows the improvement
obtained in gate charge characteristics for 3
devices rated at 60V, 20 milliohm, each with
different cell packing density and bonding on
the cells.
The different behaviour is obtained because
of better exploitation of the silicon area with
reduced cell dimensions and distances which
produce a reduced total device area for a
given RDS(en)
For high voltage devices the most significant
term that contributes to R OS(en) is R epi '
Nevertheless, optimization of horizontal
layout strongly influences the capacitance
values (C 1 to C5).
Starting from the standard 500V process of
0.35 Mceli/inch 2 performance can be
improved by both increasing cell density up
to 0.76 Mcell/inch 2 and the oxide thickness of
critical cell areas (reducing Cos capacitance)
(see fig.7).
5/9
---------------~~~~~~~~:~~-------------61
APPLICATION NOTE
500 V, 1.5 ohm DEVICES
11
Vg (V)
10
ro
~
~
~
~
ro
~
M
m
00
Og (nC)
-A-
-+- VHO
STD
Og (nC)
"""'*- UHD
Fig. 6 - Influence of cell packing density on gate
charge.
arll iOBi ~
~
I.
.11
~
II
. I
-
IU
~
~tIII
'J!!!!!!!
IIIF r =, .=
..
ml
~~
l1
,
.
_
=
--- . ...
Fig. 7 - Oxide and layout influence on gate charge,
-a;.,
ml
Oli ,
L'
,
u
..:
I
""
11'1.
~
~1
•
~~
.....
~
'-"
....
....
••
Diode' recovery
V = 50V/div
I = 5Ndiv
DlJdt = 200N~S, dV/dt = 2V/ns
l,l;;!j
•
~/' .\ \1
... - . &.' .--
•.•. ~.
.-- 1,.;;.;
O*--~--~--~--r--~-~
o
10
20
30
40
60
60
•
.
(.
,
I
~
~.
l~
~, r-
"t... -- ........ •
~
II
r.
.
I
.-.
~-,
I
hi
···.11
~
":::::i
"~
..... .. -
..
.... -.
-,-11
~~
Parasitic turn-on during
Diode recovery I = 10Ndiv
dlJdt = 250N~S, dV/dt = 4V~nS
Fig. 8 - Typical waveforms when failure occurs.
RUGGEDNESS
A very important characteristic of power
devices is ruggedness.
A Power MOSFET must withstand a static
and dynamic dV/dt U.I.S. (unclamped
inductive switching) caused by the application
and environment.
A failure due to static dV/dt occurs when a
sudden voltage variation is experienced
between the source and drain of a power
MOSFET in the off state; this causes a current
flow through both the body-drain capacitance
and the body resistance: if the current is big
enough the voltage drop across RB causes
the parasitic transistor to switch on and the
device fails because of the simultaneous
-------------- !fi ~~~~n_~~:~~:: ------------'--6/9
62
APPLICATION NOTE
::::-:-c--:--::::-:-c------,-----,---,----------:-~
100 r=ld-,:-(,:"AI)
. ... ......:::::~~ :::::::
.:~ . :r . . ".
INEW BUZll
2.2 Mc/sqi
I
1~~-~------_*-~~
a
w
~
~
~
~
~
ro
~
Vds (V)
switches on the whole Power MaS fails
because of the current focusing effect.
The failure mechanism is almost the same for
all described stress. A way to improve the
ruggedness of the device is to optimise its
vertical and lateral structure reducing RB and
the low current gain of the parasitic transistor
as much as possible.
Fig. 9 shOWS the improved ruggedness
obtained by the optimization of body doping
in comparison with the first generation Power
MOS.
Fig. 9 -Ruggedness improvement.
IGBT VERSUS POWER MOS
presence of high voltage and high current with
a subsequent hot spot generation.
The dynamic dV/dt occurs when fast voltage
variation finds the body-drain diode in
recovery conduction (after freewheeling
behaviour). Now the current flowing through
RB is the sum of the recovery current and the
current due to the body-drain capacitance.
Clearly a lower dV/dt than the previous case
can now produce device degradation.
Fig. 8 shows a typical waveform during this
kind of failure.
When the device switches an inductive load
and the drain-source voltage overcomes the
nominal defined breakdown value, then
unclamped inductive switching occurs.
When this happens the energy stored in the
load inductor discharges rapidly through the
device at breakdown voltage, forcing 10
current, to ·flow in the device and increase
junction temperature. Under effect of the.
temperature change the V BE of the parasitic
BJT decreases and can cause switch-on .of
the transistor itself, the current flowing in Rb
(body bulk).
When even a small portion of the parasitic BJT
-------.,------ 1>...,/
From the results of measurements referring
to switching speed and ruggedness the Power
MaS is an almost ideal device due to unipolar
conduction, but in some very high voltage
applications, the device's ROS(on) becomes a
real limitation.
For applications at high voltage where ROS(on)
losses are of primary importance, IGBTs find
a suitable environment.
An IGBT has the same structure as the Power
MaS and additionally has a P-Iayer under
the standard N doped drain. When the device
is on the P-N junction so realized injects
minority carriers into the drain region
modulating its total epi resistivity.
This means that the IGBT is a 'high voltage
device with an insulated gate having a low
voltage drop during the conduction phase.
In the structure of the IGBT it is easy to
recognize a PNPN (degenerative) structure
driven by a power MOS.
This implies that a device designer must
realize a device with a degenerative current
value (ILATCH) greater than the nominal
current in all working conditions, to ensure that
the PNPN structure never turns-on. This is
~~~n'~r:::n
-------------63
7/9
APPLICATION NOTE
lIt
I::
Vds·
80 V/div
Id
2 A/div
•
Vg·
..
l~
..,
II
I
r
rj
J'4
1Ga:n
w:....
~
.
5 V/div
Rg
• 100 ohm
L
• 180
T
• 100°C
~,
r.:
~h
:::
=.
D,
.
·m
"· ...
rr:~1lI.I
WITHOUT IRRADIATION
~
WITH IRRADIATION
Fig. 10 - IGBT switching characteristics.
well demonstrated in practice because I LATCH
> 5 ID nominal in all conditions. An additional
way to design latch free devices is to control
transfer characteristic gm so that for a given
driving condition drain current never exceeds
the permitted IDmax(ID latch}.
Currently the state-of-the-art fall time of an
IGBT's drain current is longer than that of
equiva.lent power MOSFET of same area. In'
fact when the power MOSFET in the IGBT
structure is switched off, the charge stored in
the base of the PNP parasitic transistor can
be removed only by intrinsic carrier
recombination.
Referri ng to fig.1 0 the first portion of t fall is
related to power MOSFET switch-off while the
tail is due tothe longer recombination time of
the carriers.
A well known method to speed-up the
switching off behaviour of the device is the
lifetime killing technique using gold and
platinum doping, ion implantation and B
irradiation. Fig.10 shows the improvement of
. Ps (kW)
0.1
10
100
1000
f (khz)
Fig. 11 - Power MOSFET versus IGBT.
IGBT's fall time obtained with B irradiation of
the device.
A comparison of the power handling capability
of a 1000V IGBT and a 1000V Power MOS of
both 25mm 2 is shown in fig.11 where Po is
kept constant (1 OW}.
It is undoubtedly advantageous to use IGBT's
at a frequency below 20kHz to reduce losses
and cut silicon costs.
------------- '''1' ~~~~~£~:oo~:: ------------~
8/9
64
APPLICATION NOTE
The 3rd generation of IGBTs showing a fall
time lower than 200nsec will allow the
crossover point of fig .11 to move up to 50kHz.
CONCLUSION
State-of-the-art power MOSFETs and IGBTs
have been shown to be rugged and reliable
as a result of many years of production and
technological know-how. Nevertheless, the
uninterrupted progress of the technology and
the constant relationship with final users and
system designers is a challenge for the device
designers. They must take into account
second order effects and new demands to
provide continuous improvement of field
controlled devices both in terms of
performance and lower cost
With the aim of reaching better performance
the main targets for improving the devices
have been defined. These concepts will also
be applied to the production of new devices.
Detailed design rule variation will produce
significant improvements in low voltage
devices; increasing cell density and tuning
dopant profiles. For medium-high voltage
devices switching losses will be greatly
reduced by varying the differentiating oxide
thickness in conjunction with the covered
active regions of the device layout.
These new design rules will therefore lead to
better power conversion efficiency and greater
ruggedness.
The predicted, reduced switch-off time as low
as 0.2msec,obtained by new life-time control
techniques (tested on 500V laboratory
devices) will allow IGBTs to be cost effective
competitors to power MOSFETs in the high
voltage, medium frequency range (30 to
50kHz).
REFERENCES
1] F. FRISINA, U. MORICONI, "High Density
POWER MOSFETS", SGS- Thomson
internal report, 1987
2] M. MELITO, F. PORTUESE, A. SINERI, "
COSMOS: A Tool for Optimization of
Layout and Process Parameters in Power
MOS Design", The Electrochemical
Society, 175th meeting, Los Angeles, May
1989
3] R. CAPOZZI, M. MELITO, F. PORTUESE,
A. SINERI,"Power MOS modtjl for Spice';
SGS-Thomson internal report, 1989.
9/9
-------------~ ~~~~m&r::~~::
-----------65
APPLICATION NOTE
GATE CHARGE CHARACTERISTICS LEAD TO EASY DRIVE
DESIGN FOR POWER MOSFET CIRCUITS
by M. Melito, F. Portuese
ABSTRACT
The traditional method of specifying input
impedance for power MOSFETs is not
incorrect, but it is incomplete and often leads
to confusion when it is used as a design tooi.
An alternative method is to use the gate
charge curve, which is directly related to the
total input impedance and allows a simple
evaluation of the drive energy and the
switching performance to be made.This paper
deals firstly with an analysis of the gate-charge
waveform which is related to the device
physics and develops an analytical
expression, which gives a very good
AN475/0492
approximation of the total gate-charge.
Secondly, the influence of the electrical
parameters, both external to the device
(e.g. 10 , V oo ) and the internal ones
(Vth' gIs' C iss ' COSS' Crss ' cell density) are
analysed.The paper also highlights how it is
possible to extrapolate the actual dynamic
behaviour of the device easily from this curve.
Finally, an evaluation criterion is suggested
that allows a comparison to be made between
the actual performances, both static and
dynamic, of devices with similar nominal
characteristics.
1/8
67
APPLICATION NOTE
GATE CHARGE MEASUREMENT
During the switching of a POWER MOSFET,
the gate current has the typical behaviour of
current in an RC circuit, see figure 1. The
transient lasts for some tens of nanoseconds
or more, due essentially to the RC time
constant and the maximum current available
in the driving circuit. If the current in the gate,
Ig' is constant and small enough, the switching
time can be increased to a level where the
voltage and the current waveforms are free
from the parasitic effects caused by the stray
r'\
\
Ig
\
~
Vg
/
~
inductances that are usually associated with
high frequency power switching. In this way
it is possible to isolate the influence of the
external factors and analyse only the internal
parameters. The test circuit and the related
waveforms are shown in figure 2.
GATE-CHARGE CURVE ANALYSIS
To get a better understanding of the
phenomena which occur during switching it
is useful to refer to the model of the POWER
MOSFET shown in figure 3b. The figure 3a
shows the cross section of a single cell
illustrating the parasitic capacitances. The
gate-charge waveform is strictly related to the
modulation of the gate-source equivalent
capacitances during switching. This is due
to the variation of the intrinsic capacitance of
the device with gate and/or drain voltage.
Figure 4 shows the load line and C gs ' Cgd
variation during each phase of switching.
Figure 5 shows a typical gate-charge curve:
the capacitances influencing the shape and
the length of each zone are marked.
Fig. 1 - Ig' V gs waveforms
'0: SA/OIV
IJ
o
\
V
Vos: lO'V/olv \
/
'I
IG: CONSTANT
/
VG:
2V/DI~
5
I \
US/DIV
'-
1Q:
7,
NC/OIV
Fig. 2 - Test circuit and related waveforms.
2/8
------------------------~.~~~~;~~::~~ ------------------------68
APPLICATION NOTE
C 1 : Capacitance between gate and source (both
Wand metal)
C2 : Capacitance between gate and P zone.
C3 : Capacitance between gate and epi N.
C4 : Capacitance of the depiction zone in the
superficial epi.
Cs: Capacitance of the depietion zone in the
superficial epi.
C6 : Capacitance of the body-drain junction.
Fig. 3 - Cross section of a Power MOSFET cell and its electrical equivalent.
c"
~
I
C,
I
I
I
...l.-
I
v
=Vth
I
~
l®
C",
~
y,
Vds
{1jo\t~l
o1
2 l
Fig. 4 - Load line and capacitances modulation.
3/8
----------------------------- ~~~~~~~~:~?~ ----------------------------69
APPLICATION NOTE
Vg IV)
VdIV)
10
100
(4+(2+(3
8
80
C9J
6
60
C3
40
4
2
Q,1
I
I
I
I
I
I Q..21
20
(U
0.4
Cs
1
0
0
0
0. 9 (n()
v, . . . r ..
Vd ,
VJJ
Fig. 5 - Gate charge curve
Fig. 6 - Cgd modulation
In the first zone the equivalent capacitance is
nearly equal to C iss because Vd is constant
and the variation of V 9 has no influence. The
charge supplied to the gate can be
approximated by the expression:
Looking at the drain voltage, figure 4 and
figure 5, a slope variation can be observed
occurring at a voltage, V x, physically
corresponding to the transition from a highly
charged P zone to simple depletion of the
MOSFET capacitor that exists between the
deep body cells. The first slope is related to
Cs '" CrSS' the second to C3 , the polarity of
Vgd being so that Cs » C3 . So the charge
supplied to the gate during the Miller effect
can be split into two parts:
01
= (C 1 + C2 + Cs ) • Vgm = Ciss
• Vgm
where V gm is the gate to source voltage
required to just carry the desired Id and it can
be easily deduced using the output
characteristic. In the horizontal zone the
equivalent capacitance seems to be infinite,
in fact Vgs remains constant though charge is
supplied to the gate. This phenomenon,
known as the Miller effect, is due to the
modulation of the capacitance Cgd by Vds'
The waveform of this capacitance variation is
typical of a MOS structure switching from
being strongly inverted to the accumulatiqn
status, see figure 6.
The only difference is due to the fact that
modulation of the depletion zone is caused
not only by the voltage but also by lateral
injection of the charge coming from the
channel.
02
= C s • (Vdd - Vx) '" Crss • (Vdd
0 3 = C3 • (Vx-Vd(sat))
- Vx)
being Vx = Vgm + Vth-epy + Repy' Id and Vd(sat)
the voltage drain corresponding to the "knee"
of the output characteristic with V gs = Vgm'
The slope of the final part is associated with
the oxide capacitances. (V th-epy is the
threshold voltage of the MOSFET capacitor •
existing between the P zone; Repy is the
resistance of the drain due to the epi). The
charge supplied during this phase is:
04
= (C 1
+ C2 + C3 ) • (Vg(max) - Vgm )
------------- ~ ~~~;m~~r::~~~ -----------4/8
70
APPLICATION NOTE
v V
V,m
P2ZZ2Z22222222722722272Z2/272227772722222/J
. _....
........•.....................•..............
..
.. - ...................
2
···
...
60
80
.
0~--~----4-----~--~--~
o
Fig. 7 - V x evaluation.
20
40
100
Qg(nC)
Fig. 8 - Gate charge curves as a function of Id and Vdd'
V V
1 0 ....................1· ....-.. ·.... . ~.....
11.0
MCI~gil:
.... ..~.............-.... ~- ...... . ........
:
10
:
!................!. 12:2 M~'g&U--·..·~ ...................
8
6· ..·..........-.... ~ ...... -....~ ..·..............·..1·..·.............. ~.................. ..
6
8 ....................
4
2
o
o
r··. . ·. . ·. . . ·t. ·. . ·. . . ·..+. ·. . . !~:·s.··~·~·'.·s.~·~L.
. --.. .r. . . . ·. . . . r. ·. . . . · . ·. r. ·. . ·. ··_·r. . · . ·. . . ·
•
20
•
I
40
60
QgrnC)
,
80
Crss
13 gfs
4
2
100
Fig. 9 - Influence of cell density on gate charge.
EFFECTS OF THE PHYSICAL AND
ELECTRICAL PARAMETERS ON THE
GATE-CHARGE CURVE
The previous discussion has shown that the
total charge supplied to the gate is influenced
by several parameters, which are essentially:
a) electrical parameters (V dd' Id)
b) structural parameters (cell density,
capacitances, Vth , gls)
The electrical parameters are imposed by the
external circuit and depend on the application;
the structural parameters are typical of the
o 1 Crs5
20
30
Og(nC)
40
50
Fig 10 - Comparison of gate charge curves of two
devices with different values of CiSS' gfs and
Crss '
device and can be adjusted during the device
deSign stage in order to optimise its
performance. Figure 8 shows the influence of
Id and Vdd on the shape of the gate-charge
curve.
Figure 9 summarizes the effects of the
structural parameters: the gate..charge curves
of devices having the same static
characteristics (RdS(on)' BVdss' Id) and different
5/8
------------- l:ii ~~~~m~¥r::~~:: --------~----
71
APPLICATION NOTE
Fig. 11 - Gate charge curve of IRF832. V g5 = 2V/div.
Vd = 1OOV/div. Og = 5nC/div.
Fig. 12 -IRF832 turn-off. Vg5= 5V/div. Vd = 100V/
div. Id = lA/div. t = 500ns/div. Rg = 180
Ohms.
14~~~--------------------~.
08 GIS/Qg
•
12
+
0.6
10
*
+
8
0.1
6
4
0.2
21.~_~
~
20
]0
~o
5U
60
O.S Mc/sql
+
1.3 Mc/sqi
..
2.2 Mc/sql
a
260 Kc/sql
"
720 I(c/sql
-- 0
0
0
"
o
09_to t
10
o.
O~-L--~~~~-J--~
o
100
200 300
~OO
500 600
OVdS5
Qg(nC)
Fig. 13 - Driving energy and gate charge.
Fig. 14 - Comparison of technologies.
cell densities. are shown. Figure 10 shows the
influence of the capacitances and of the
transconductance on the same curve.
Figure 11 and figure 12 show. respectively.
the gate charge curve and the turn-off of the
IRF832 measured under similar conditions of
Id and Vdd' Note that the horizontal axes of
the gate-charge graph are in nanocoulombs
(0 = Ig * t. Ig=const.) while the vertical axes
are in voits. Referring to figure 5 and figure
11. the values of the single contribution to gate
charge are:
Use of the gate-charge curve
The gate-charge curve analysis is useful for
obtaining important information about device
switching characteristics; The following
example evaluates the switching time of the
SGS-THOMSON IRF832 as an example.
01
=
5nC
------------------------- lifi ~~~~m~~:~~~ ------------------------6/8
72
APPLICATION NOTE
= 11 nC
= 13 nC
0 4 = 18nC
O2
03
During ta, Cgs is constant so this time is easy
to evaluate using the usual calculation for RC
circuits:
ta = Rg • Cgs • In(Vgs(to)/V gs(ta))
substituting:
Rgs
= 180,
Cgs = dO/dV = 18nC /4.7V = 3829pF,
Vgs(to)
= 10V,
= 5.3V
V gs(t a)
ta = 438ns.
From ta to te, Ig is constant and its value is
Ig = Vgm /Rgs = 29.4mA hence:
K1 = gl/Og
tb = Oilg = 442 ns
te = Oilg
= 374
ns
During td Cgd is constant and using the
previous expression:
td
= Rg
• CgS • In (V gs(te)/V 9S(lh))
Note Cgs = Ciss
Looking at figure 12 it is possible to see that
the calculated times are very close to the
measured ones.
The gate charge curve is also helpful because
it allows the driving energy to be calculated.
The area under the gate-charge curve
represents, in fact, the total amount of energy
needed to turn-on the device while
V gmax • 0g_lol is the total energy that the
driving circuit has to supply, see figure 13.
In order to obtain fast switching with low
driving energy and low energy dissipation
during the cross-over, the optimum device
should have low Og and high gls. To obtain
low power dissipation during the on state, the
optimum device should have low RdsonIt is useful to define two merit coefficients to
give a measure of device performance:
= 96ns
lI(RCn Og)
K2 = (Rds(on) • Og)"1
Devices having analogous nominal
characteristics (BV dss' Id) but manufactured
using different technologies can be quickly
compared, see figure 14 and figure 15. Note
that the two coefficients are not dependent on
device die size because of their definition.
They both depend on switching features (Og)
but K1 is related to the saturation zone (gls)
of the Power MOSFET out characteristics
whilst K2 is related to the linear characteristic
(Ron)·
o
+
.
0.1
0.5 Mc/sqi
1.3 Mc/sql
2.2 Mc/sqi
o
280 Kc/sqi
x
120 Kc/sqi
x
o
0.0 1 " - - ' - - ' - - ' - - - ' - - > - - - - - - '
o
100 200 300 400 500 600
8Vdss
Fig. 15 - Comparison of technologies.
CONCLUSION
The gate charge curve supplies useful
information about the actual behaviour when
the device switches.
From the user's point
of view, these curves allow the correct design
of the drive circuit and correct choice of the
device which best satisfies the design criteria.
The use of two merit coefficients allows a
quick comparison of devices having similar
7/8
-------------~~~~~~~~:~~-------------73
APPLICATION NOTE
nominal characteristics but manufactured
using different technologies.
REFERENCES
1. F FRISINA, U. Moriconi, "High Density
Power MOSFETs", SGS-THOMSON
internal report 1987.
2. M.MELlTO, F.PORTUESE, A.SINERI.
"COSMOS: A Tool for Optimisation of
Layout and Process Parameters in Power
8/8
3. R.CAPOZZI, M.MELlTO, F.PORTUESE,
A.SINERI, "Power Mos Model for Spice",
SGS-THOMSONinternal report. 1989.
4. A.GALLUZZO, M.MELlTO, M.PAPARO
"How Design Rules Influence the High
Frequency Switching Behaviour of Power
MOSFETs", PEC, Long Beach, February
'90.
r== SGS.ntOMSON _ _ _ _~------
- - - - - - - - - - - - . ..."
74
Design", The Electrochemical Society
175th meeting, Los Angeles, May 1989.
Il'AJDlI::fiiI@~~rnfflfiil@II!DII::®
APPLICATION NOTE
ANALYSIS AND OPTIMISATION OF HIGH FREQUENCY
POWER RECTIFICATION
By J.M. PETER
How can the performance of power electronics be
improved? Today, in many cases, it is the job of the
designer. The fast rectifier switching behaviour depends on the operating conditions. The analysis and
the optimisation of these conditions can be an important source of improvement in performance.
1. SWITCH-OFF OF FAST RECOVERY RECTIFIERS
It is possible to define theoretically two types of
switch-off1 .
of behaviour can be met in some applications such as
rectifiers in flyback converters and many functions in
thyristor circuits, (figure 3). Generally speaking a rectifier in the rectifier mode is always in series with an
inductance L and this inductance L defines the dIF/dt.
The fundamental difference between these two
modes is that in the rectifier mode there is a stored
energy 1/2L1RM2 due to the series inductance. After
the turn-off this energy is dissipated in the rectifier
and/or in the associated circuits.
1.3. TURN-OFF LOSSES
1.1. FREE-WHEEL MODE (figures 1 & 2)
Free-wheel mode
When the rectifier switches-off it is always in parallel with a voltage source. In this case the assumption is that the parasitic inductances are negligible.
This type of behaviour can be met in the majority or
rectifier applications such as free-wheel rectifiers in
step-down and step-up converters, full wave rectifiers, etc ... (figure 2). Generally, a rectifier in freewheel mode is always 'in parallel with a voltage
source when it turns-off.
WOFF is the energy dissipated in the rectifier during
turn-off.
1.2. RECTIFIER MODE (figures 1 & 3)
An inductance defines the dlF/dt (decreasing slope of
the rectifier current) and when the rectifier switchesoff it is always in series with this inductance. This type
AN37010689
WFR=
f
t2 Vldt (refer to figure 1)
t1
Low voltage « 200V) fast rectifiers have a high internal capacity and the minority carriers have a very
short life time. High voltage fast rectifier have a
thicker N silicon layer and the minority carriers have
longer life time and consequently different behaviour during the turn-off condition blocking state.
(Higher IRM and fiRM - more damping).
1/12
75
APPLICATION NOTE
Figure 1 : Fast Rectifier: the two turn-off modes.
a) Free-wheel Mode.
b) Rectifier Mode.
_....;.._.... dlF/dt
o
t1 t2
dlF/dt FIXED BY THE TRANSISTOR (or by
the external circuit)
dlF/dt FIXED BY THE INDUCTANCE
dlF/dt = VRIL
LOW LOSSES IN THE RECTIFIER
HIGH LOSSES IN THE RECTIFIER
WOFF = K . VR . IRM TIRM
(0.15 < K < 0.35)
WOFF = K· VR . IRM . TIRM + 1/2 L}RM
When a snubber is used some of the energy is dissipated in the snubber.
NO OSCILLATIONS AND OVERVOLTAGE
ALWAYS OVERVOLTAGE AND
OSCILLATIONS IN SOME CONDITIONS
5A1div. 50V/div. 0.05J.1s/div.
BYT30 -1000-IF = 3A -dlF/dt = -75A1J.1s - VR = 100V - TeAsE = 25°C
2/12
76
APPLICATION NOTE
According to the experimental results the turn-off
energy loss (W)FR in the free-wheel mode can be
written:
(W)FR = K X VR
X
IRM
X tlRM
K(I) is a constant that depends on the thickness of
the N type silicon layer.
(1)
Max Voltage Rating (V)
K
Rectifier mode
1. No circuit is without parasitic inductances.
Losses in this mode, (W)REC, are the sum of the stored energy 1/2 L IRM2 and the recovery energy
(W)FR :
2. The rise time (or the fall time) of the switch is
(W)REC = (W)FR + 112 L IRM2 (2)
Experimental results show that in all cases the following formula can be used:
In some cases, oscillations can occur. This depends
on the damping due to the current tail effect after
switch-off. When oscillations occur energy is dissipated during the oscillations partly in the rectifier and
partly in the circuit. When snubbers are used a significant part of the energy is dissipated in the snubber.
2. PRACTICAL SWITCH·OFF BEHAVIOUR '-The two cases, free-wheel mode and rectifier mode
are simplified cases that are easy to simulate in a
laboratory characterisation. In practical equipment
there is always a possible overlap between the two
theoretical modes, because:
Figure 2 : Rectifiers in Free Wheel Mode.
not infinitely fast when compared with the rate
of change of current, dlF/dt.
(W)OFF= (W)FR + 1/2 Ls IRM2 (3)
Where
Ls = series inductance
This important relationship is a useful tool for the
designer, giving him the main parameters that influence the turn-off energy.
N.B. : The following relationship (4) is only true for
the pure rectifier mode.
(W)OFF = OR
X
VR (4)
Where OR = recovered charge
(1) K is experimental- Defined
tronics fast rectifiers.
for SGS-THOMSON Microelec-
Figure 3 : Rectifiers in Rectifier Mode.
--,
'11
L . _ ~.-+-
·L
•
[~I]-n.[J
Vl
L_
--([J--
V2.J
L
}-~
l_~D_
3/12
77
APPLICATION NOTE
Figure 4 : Switch-off Behaviour of the Ultrafast BYT12-400V Rectifier (current rating 12A - voltage rating
400V).
Conditions: IF = 13A dlF/dt = - 150AIIlS VR = 1 OOV Tease = 25°C.
In the case of rectifier mode: l = O,6IlH.
The tum-off lost energy calculated by the current and voltage is :
(W)FR = 3flJ free-wheel mode.
(W)REC = 1011J rectifier mode.
The storage energy in the inductance is : 1/2 l IRM2 = 7.5I1J.
a) Free wheel mode.
b) Rectifier mode.
The use of this equation for a lot of practical circuits
can be considered as a first approximation. It leads
to over estimated losses, if the rectifier does not
operate in pure "rectifier mode".
a trade off between:
Speed (IRM)
- Max voltage rating (VRRM)
- Forward voltage drop (VF).
3. CHARACTERISTICS OF FAST RECTIFIERS
Example: 12A fast rectifiers.
:',',0 characteristics of fast rectifiers are the result of
...
V RRM
Type
Tj = 100'C
dlF/dt = - 50Alfjs
VF
200
400
BOO
1000
BYWB1
BYT12-BOO
6
BYT12-1000
0.160
1.3 + 0.031
0.200
1.3 + 0.031
IRM(A)
1.B
BYT12-400
3.7
tIRM(fjS)
(V)
0.05
0.66 + 0.0071
0.075
11 + 0.021
Operating conditions
IRM increases with dlF/dt (figure 5).
IRM increases with Tj (figure 6).
The important points that emerge are:
1. High voltage fast rectifiers are not so fast as low
voltage fast rectifiers, (comparing devices of
equal current rating).
2. Tj and dlF/dt have a strong influence on the
reverse recovery current.
4/12
78
7.B
4. EXAMPLES
4.1. FlYBACK CONVERTER (figure 7)
The behaviour is as a pure rectifier; the rectifier is
driven by a current source, the inductor, l.
For a frequency less than 100kHz the switching
losses are small in comparison to the conduction
losses, because dlF/dt defined by Vall is always
small, (see table figure 7).
APPLICATION NOTE
Figure 5: Switch-off Behaviour of the Fast Rectifier BYT12P 1000 (current rating 12A voltage rating 1000V).
Influence of the dlF/dt.
IRM(A)
30 r---------,---,---,-----,---,
~
~v
20 t----+----t----j~ ,,~00
-v----,..--.J----j
",0<:0\0
"!!~
ct·
10
1---+---- ~"'~'_+.."._+----_+--_l
o
10
5A1div, 50ns/div, Tj
= 25 C
C
Figure 6 : Switch-off Behaviour of the Fast Rectifier BYT12 1000 Influence of Ti.
One Curve Ti = 25 0 , one curve Tj = 60 0 •
1OOV/C, 2A/div, 50ns/div
Free·wheel mode
1OOV/C, 2A/div, 50ns/div
Rectifier mode
%
250
0«/
./
VI
200
ioo
.::-~
V
150
~V
~ --":- J.--
~
25
50
75
100
-?
125
150
T(Vj)(OC)
5/12
79
APPLICATION NOTE
How can the designer reducethelosses ?
1. The ratio I peakllAvG, is very unfavourable in this
type of circuit. It is essential when the peak voltage is less than 200V that the "high efficiency
ultra fast" family which have very low conduction
losses are used. When the peak voltage is
greater than 200V one solution is to use a rectifier with higher current rating.
Example:
In the same circuit at 12A with:
BYTI2-800: conduction losses = 7.6W, a 12A
rectifier.
BYT30-800 : conduction losses = 6W, a 30A
rectifier
2. Reduce the junction temperature. If Tj is decreased from 100 to 75°C the switching losses
are reduced by 20%.
4.2. SMALL CURRENT RECTIFIER (figure 8)
A transformer with a leakage inductance measured
on the secondary side Ls = IIlH supplies a fast diode
D. The average output current is 0.8A and the output voltage is 48V.
The designer wants to use the popular diode BA157.
This is not possible because the total power dissipation is 1.15W at 40kHz. At this frequency he can
only use a popular 2A current rated diode (for O.8A
rectified current) and at 200kHz there is no solution
with popular diodes (see table in figure 8).
How can the designer reduce the losses?
1. Choose a diode in the "high efficiency family". For
example he can use the BYW100 for 40kHz to
200kHz, (see table figure 8).
2. Reduce the leakage inductance :with a leakage
inductance Ls = O.IIlH, BY218 at 200kHz
(1.24W, L1Tj = 93°C).
4.3. FULL WAVE OUTPUT RECTIFIER
There are two different full wave rectifying circuits.
4.3.1. VOLTAGE SOURCE - CURRENT OUTPUT
Current and voltage behaviour are indicated in figure 9. The inductanceLs is the leakage inductance
of the insulation transformer.
The 4 rectifiers operate in an intermediate mode between "free wheel" and "rectifier", because there are
some 1/2 Ls IRM2 losses.
4.3.2. CURRENT SOURCE - VOLTAGE OUTPUT
(figure 10).
In this circuit, each rectifier operates in "free wheel"
mode. The series inductance does not introduce additionallosses. (This assummes there is no parasitic inductance between the rectifiers and the capacitor C).
How can the designer reduce the losses?
Figure 7 : Flyback Rectifier Output Average Current 4A.
Below 100kHz the switching losses are negligible, in comparison with the conduction losses.
The reason is limited dlF/dt, consequently limited IRM.
j
(~-f;
-11
20A
----+~T----+-~t/T=-O.4
IAVG
+ 4A
Pure .. rectifier mode"
Vo (V)
Rectifier
Conduction Losses (W)
12
BYWB1-100
"High Efficiency" .
48
100
BYT12-400
BYT12-BOO
3.2
6
7.6
Switching Losses a 50kHz (W)
0.006
0.05
0.B1
Switching Losses a 200kHz (W)
0.05
0.5
5.5
6/12
80
APPLICATION NOTE
Figure 8 : The Popular Diodes BA 157 - BY218 are not Fast Enough for High Frequency Rectifying. The
BYW100 is well adapted.
1.6A
-0.8A
48V
_
'---.J.------ '-
I<.__
l __•
t/1'=O.5
1<_______1''--_-+1
BA157
Popular
BY218
Popular
BYW100-200
High Efficiency
IRM a 100"C dl/dt =- 20A/fiS (A)
tlRM a 100"C dlldt = - 20A/fiS (A)
(W)FR (IlJ)
1/2 Ls I~M (fIJ)
2.8
0.14
2.08
3.9
2.8
0.14
2.08
3.9
0.75
0.05
0.01
0.28
Conduction Losses (W)
Switching Losses a 40kHz (W)
Switching Losses a 200kHz (W)
0.944
0.2
1.3
0.744
0.2
1.3
0.592
0.012
0.06
Total Diode Losses a 40kHz (W)
" Tj a 40kHz ("C)
1.15
115'
0.44
71°
0.6
60°
Total Diode Losses a 200kHz (W)
" Tj a 200kHz (''C)
1.97
191"
1.77
132 0
0.65
65 0
DIODE
a) Voltage source - current output
Reduce the transformer leakage inductance.
Table of figure 11 shows that in the case of the
400V 1OA 200kHz bridge circuit the suppression
of the inductance Ls can save 4 x 16.5W = 66W.
Replace in the same circuit the high voltage .fast
rectifier BYT12-600 by 3 "high efficiency"
BYW81-200 in series (see figure 12 - table). The
total losses decrease from 186W to 58W. This result is very important as it shows it is more efficient to use several "high efficiency" ultra fast
rectifiers instead of a single high voltage one for
high frequency operation.
b) Both
Use of sinusoidal current (resonant converter) instead of rectangular waveforms. Figure 11 shows
that for the same conditions (400V - 10A 200kHz) the switching losses with a sinusoidal
current are only 4 x 7.5 = 30W (4 x 22 = 88W with
rectangular wave forms).
4.4. STEP UP CONVERTER
The rectifier operates in free wheel mode. The main
losses in this case occur in the transistor during the
turn-on (similar to the step down converter).
Figure 13 shows that with 600V output at 40kHz, if
the rectifier switching losses are reasonable, the
transistor turn-on losses are too high.
How can the desig ner reduce these turn-on losses?
(fig. 13).
a) Decrease the rectifier junction temperature by
more efficient cooling.
If the BYT12-800 junction temperature decreases from 100 to 70°C, the transistor turn-on
losses decrease from 39.5W to 33W.
b) To replace one BYT12-800 by 4 high efficiency
BYW81-200 in series. The total balance is a reduction in losses from 39.5 to 16.6W in the transistor with same losses in the rectifier.
IN SUMMARY
Two major actions reduce switching losses caused
by fast recovery rectifiers:
1. APPROPRIATE CHOICE OF COMPONENT
• The fastest rectifier compatible with the peak
voltage in the application.
7/12
81
APPLICATION NOTE
• If the peak voltage VR exceeds 4DDV the designer must analyse carefully the switching
losses:
- These losses are proportional to 12RM x VR.
A 8DDV fa$trectifier has an IRM approximately two times higher than a 4DDV fast rectifier
(same current rating).
Figure 9 : Voltage Source, Output Current Full Bridge Circuit.
ru
+
Va
INPUT
[ (02 03)
I (D! 04)
V (02 03)
8/12
82
CURRENT
OUTPUT (CONSTANT)
APPLICATION NOTE
Figure 10 : Current Source, Output Voltage Full Bridge Circuit
CURRENT
SOURCE
V (D2 D3)
(Dl D4)
" ' " -I
9/12
83
APPLICATION NOTE
Figure 11 : Switching Losses (per leg) in a full Wave 200kHz Bridge Circuit. Output 10A.
In case of voltage source, current output, the (leakage) inductance Ls introduces Lsl2RM
losses.
In case D, the losses are smaller (6 x 4 = 24W instead of 22 x 4 = 88W) because dl/dt is smaller, consequently IRM is smaller.
Ls = O.5iJH (48V)
1iJH (200V)
1.5pH (400V)
1--
Va
Rectifier
200kHz
48
BYW81-100
200
BYT12-300
400
BYT12-600
O.76W
5.6W
38.5W
O.16W
2W
22W
O.16W
2W
22W
O.04W
O.6W
6W
[ll
(A) 1_
10/12
84
APPLICATION NOTE
Figure 12: Switching Losses (per leg) in the Full Wave 400V 200kHz Bridge Circuit with two Different
"rectifiers".
Replacing the high voltage BYT12 - 600 rectifier by 3 "high efficiency" ultra fast BYW81 - 200
in series reduces the total losses dramatically. This is why the IRM from BYW81 is very low and
the voltage drop of this high efficiency rectifier is very low.
BYT12-600 3xBYW81-200
Rectifier
Conduction Losses
(W)
F = 200kHz
8
11
Va = 400V
Switching Losses (W)
38.5
3.5
dlF/dt = - 120AliJs
Total Losses pe r Leg
(W)
46.5
14.5
tiT =0.5
IAVG
= 10A
Figure 13 : In the Step-up (or step down) Converter the Majority of Losses Occur in the Transistor, Specially
when a High Voltage Rectifier is used.
In some case replacing a high voltage rectifier by several faster rectifiers in series (and consequently with a lower voltage rating) can minimize the total losses despite the increase of the rectifier
conduction losses.
+
lOA
tiT
=
0.5
Reclifler current
I + lOA
Transistor turn-on currenl
VR
(W)ON
="2 [
I
dUdt + (I + IRM) tIRM]
11/12
85
APPLICATION NOTE
Figure 13 (continued).
Vo
Rectifier
(dr/dt = 120A//.Is) IRM (A)
(Tj = 100') trRM (/.Is)
. Rectifier Conduction Losses (W)
48
300"
600
600
BYWS1-100
BYT12-400
BYT12-S00
4 x BYTS1-200
3.S
0.04
6
0.06
10.5
0.12
3.S
3.65
6.5
S
14.6
0.04
0.6
6.7
0.5
Total Rectifier Losses a
40kHz (W)
3.7
7.1
14.7
15.1
Transistor Turn-on Losses a
40kHz (W)
1.32
1
0.7
39.5
Rectifier Switching Losses a
40kHz (W)
The rectifier voltage drop increases with the rating
voltage.
Example: BYW81 "high efficiency" 200V rating VF
= 0.85V (max).
BYT12-600 600V rating VF
= 1.8 (max).
IMPORTANT CONSEQUENCES:
If the switching frequency is greater than 40kHz in
many cases it will be more efficient to replace one
high voltage (600 - 800 - 1OOOV) rectifier by a series
of ultrafast rectifiers (200V or 400V). Despite the increase of conduction losses, a dramatic reduction
of 5,witching losses results in a decrease in the total
losses.
2. OPTIMAL OPERATING CONDITIONS
2.1. In many cases parasitic inductance gives additional losses. A reduction of those parasitic inductances Ls decreases not only the voltage spikes but
also the switching losses.
2.2. Junction temperature plays an important role.
The switching losses are approximately proportional
to Tj. Improving the rectifier cooling is, very-important for all high frequency rectifiers.
2.3. For full wave rectifying circuits, with an isolation
transformer the switching losses are always lower
in case of :
12/12
86
Current source ~ rectifying ~ voltage source
than:
Voltage source
~
rectifying ~ current source
because the impedance due to the transformer leakage inductance is integrated in the current source,
and does not play any part in the additional losses.
2.4. The use of the resonant circuit with sinusoidal
current waveforms results in a significant reduction
in the switching losses due to the limited dlF/dt or to
the smaller VR re-applied voltage.
CONCLUSION
Reducing the switching losses in high frequency
converters is team work.
The manufacturer has improved the fast recovery
rectifier characteristics. The designer has now some
tools to analyse, with a greater accuracy, the rectifier behaviour and choose the optimal solution in order to minimize the losses.
REFERENCE
111 "Switching behaviour of fast diodes in the converter circuits" - p.63 to 78 in the hand book
SGS-THOMSON Microelectronics "Transistors
& Diodes in Power Processing".
SMART POWER DEVELOPMENT
SYSTEM
87
..r==
.,l SGS-1HOMSON
~D©[Rl@rn[lJ~©'ITOO@[K!]D©~
APPLICATION NOTE
PC-BASED DEVELOPMENT SYSTEM CUTS DESIGN TIME
OF SMART POWER IC APPLICATIONS
by Thomas L. Hopkins
A Smart Power Development System allows the designer to evaluate a smart power device in
the final application, such as emulator systems allows designers to evaluate and debug microprocessors.
As smart power integrated circuits become more
complex they are approaching the realm where
they can be considered power peripheral chips.
These new devices can no longer be evaluated
with a simple bench set up using a few switches
and a function generator. Before the device will
operate in an application, one or more registers
must be programmed to set the operating conditions of the device. To speed development of applications using these devices a PC based system, the Smart Power Development System, has
been developed. The SPDS allows the user to
quickly develop and evaluate the device performance in a real application. This paper discusses
the SPDS and shows a typical application for a
stepper motor drive circuit, the L6223A.
The current generation of smart power integrated
circuits contain more logic than their predeces-
sors and many, like the L6280 and L6223A, contain one or more registers that must be programmed for the device to operate. This adds a
new dimension to the users task who must now
develop software to drive the devices before he
can start to evaluate the device operation. In addition such tasks as calculating the power dissipation and required heat sink for a power integrated
circuit is a more complicated task than for discrete devices.
To assist the user in evaluating such devices the
Smart Power Development System (SPDS) was
developed. This PC based system consists of
three parts: 1) a general purpose interface card
that interfaces to the PC bus, 2) a dedicated
printed circuit board for each device supported,
and 3) a dedicated software package for each device supported. The block diagram of the SPDS is
shown in figure 1.
Figure 1: PC-Based SPDS
HWPCI-ST
~~~ ~a~~ I
[][][] LJJ
<=l
111111111111
Ic{}= c{}=j
EVALUATION
BOARD
AN450/0190
1/9
89
APPLICATION NOTE
PC INTERFACE
To allow the PC to easily drive a variety of applications, a general purpose interface ?ard was
needed. The interface card chosen, Similar to the
Burr-Brown· PCI 2000 Series, provides 32 I/O
lines, 4 counter/timer channels, and a rate generator, as shown in figure 2.
The 32 I/O lines are general purpose parallel
lines that may be programmed, in groups of 8, as
either output or input lines. The 32 I/O lines plus
their associated control registers are mapped, as
eight bit registers, into the user address spac~ of
the PC and are easily addressed by the app!lcation program. In the SPDS system these 32 lines
are used as parallel outputs to drive the dedicated
application board.
The rate generator provides a stable timebase for
operation of the system. The frequency. of the
rate generator output is given by the equation:
8MHz
Fout
where N1 and N2 are integers between 2· and
65535. In this configuration, the output frequency
can then range from 2 MHz to approximately .002
Hz. This clock signal is used by the four counter
timer channels that provide the variable step rate
timing used in stepper motor applications or the
period of output patterns in pattern generator type
applications.
This flexible configuration allows the PC interface
to be independent of the device. being evaluated
and provides a general ~urpose Interface that can
drive many types of applications.
Figure 2: SPDS Interface Card
M
I/O Port 1
CHD- CH15
I/O Port 2
CHD-CH15
out
Timer
x4
2/9
LJ
J
4
Gate
Clock
Out
~ SCiS-THOMSON _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - - . .""!IIi1Al~~,,@~~~©'IT"@Iil~©i!l
90
U
Q
APPLICATION NOTE
DEDICATED HARDWARE
Each device, or family of devices, supported by
the SPDS has a dedicated application board that
connects to the PC interface card and includes
the dedicated circuitry around the evaluation de-
vice. In the case of the L6223A the dedicated
board includes two configurations for the L6223A
driving a unipolar stepper m~tor, a s.ingl.e device
application and a dual device application: The
schematic diagram for the L6223A Dedicated
Board is shown in Figure 3.
Figure 3: Dedicated Board for L6223A
~
- - - - - - - - - - - - - "''''!I
SCS·THOMSON _ _ _ _ _ _ _ _ _ _ __3/9
[i;ln©oo@~~~©voo@lIIln!:$
91
APPLICATION NOTE
This allows the user to choose the configuration
that best suits his application depending on the
current level required by the motor.[2] The software then allows the user to select which of the
two implementations will be driven for evaluation.
Other dedicated boards support devices in bipolar
stepper motor driver applications, DC motor driver
applications, and solenoid driver applications.
SOFTWARE
Each of the SPDS systems includes a software
package dedicated specifically to the devices. Although the features vary depending on the applicatio.n and. the specific devices, the L6223A package IS typical. The L6223A package includes: 1)
calculation of the acceleration and deceleration
ramps for a stepper motor, 2) a driver routine for
real ti!TIe operation and 3) a simulation package
that simulates the thermal behavior of the device
or devices.
ACCELERATION AND DECELERATION RAMPS
The acceleration/deceleration ramp section the
program is unique to step motor applications. This
routine calculates the step timing required to raise
the step mot.or fr?m zero up to the final speed.
The calculation IS made from the mechanical
characteristics of the application.
The required inputs include the characteristics of
the motor, specifically the static Torque (Tstat), the
slope of the Torque vs Speed curve (Tsl ope) and
the number of steps per revolution. The torque
characteristics for a typical stepper motor are
shown in Figure 4. In the simple model for a stepper motor the torque decreases approximately linea~ly as the speed increases from zero up to the
maximum motor speed where the Torque falls to
zero.[1] This curve can be approximated by a
straight line having a static Torque (Tstat) and a
slope (Tsl ope) as shown in Figure 4. Here the approximation for the torque curve allows for a
Torque utilization factor of less then unitY.[1] In
addition to the motor characteristics the program
needs the mechanical characteristics of the system, as referred to the motor shaft. The two required values are the frictional Torque (Tfrie) and
the total Inertia (Jtot). From these values the program calculat.es the period of each step during
the acceleration ramp. These values are then
saved and used by the real time program to drive
the motor.
Figure 4: Typical stepper motor torque characteristics
Pullout Torque (NM)
3,-----------------------------------------~
2.5
2
0.5
OL-__________-L____~~~_____ L_ _ _ _ _ _ _ _ _ _ _ _L __ _ _ _ _ _ _ _ _ __L~
o
2 4 6
8
Step Rate (Thousands Steps/Sec.)
._-- From Specification
4/9
--I-- Design Target
-------------- LV ~~~~mgr::i!~~
92
--------------
APPLICATION NOTE
Figure 5: SPDS entry screen
TEXT MOVEMENT
Number
of
2
Filename:
DEFTEST.DIM
RotBtion ~en~e
(FW / BW )
Acceleration current
(100% 85% 70% 55% 40%)
Frequency
(10 or 20 Khz )
Number of ~tep~ before the intermedie current
Intermedia current
(100% 85% 70% 55% 40%)
Frequency
(10 or 20 Khz )
Number of ~tep~ of con~tent ~peed
Co~tBnt speed current
(100% 85% 70% 55% 40%)
Frequency
(10 or ?n Khz )
Oeceleration current
(100% 85% 70% 55% 40%)
Frequency
(10 or 20 Khz)
St~nd by current ( OPen or CLo~e loop)
Stand by current
100% 85% 70% 55% 40%
Frequency
(10 or 20 Khz)
Half or Full
(H / F )
Time of ~tand by
(m.~ec)
FI
FW
100
20
10
85
20
199
55
20
70
20
CL
40
20
F
200
ESC to go back
to next movement.
divided into five segments, as shown in Figure 6.
Using the motion text entry screen, the user may
define the operating conditions of the driver chip
for each segment of the movement. The entry
screen allows the user to select one of five current levels and the chopping frequency, both of
which are selected by programming the internal
shift register in the L6223A [3], for each segment
of the movement.
REAL TIME OPERATION
One major advantage of the SPDS is the ability to
operate the devices in a real time application
without having to first write a driver routine. In the
real time operation section of the program the
user defines a sequence of movements and the
motion profile and operating parameters for each
movement. This is done using a simple text entry
screen, as shown in Figure 5. Each movement is
Figure 6: Stepper movements
Speed
Coil current
100%_
86% --'::7""00-:Yo-_-
55%--40% -
o
DA/OPLO
DNCLEV
-U
u
5/9
------------------ ~~~~~~~~~:~~~ ---------------------------93
APPLICATION NOTE
The entry screen also allows the user to define
the number of steps in the first segment and the
third segment of the movement. The number of
steps in the second and fourth segment of the
movement are defined by the acceleration ramp
and deceleration ramps being used.
The final segment of the movement is the
standby period, which is really the period where
there is no movement between two movements.
The user is allowed to select the period and operating conditions during standby. Utilizing the programmability of the L6223A,the user may select
either open loop or closed loop operation during
this time as well as the current level and the
chopping frequency.
The user may define any number of movements
in a sequence and then set the parameters of
each movement. Once this definition is completed, the SPDS will continually execute the sequence programmed in real time. In the execute
mode the SPDS displays some of the operating
parameters of the system, as shown in Figure 7
and 11. During the execution the user may modify
the step timing of either the acceleration or deceleration ramps and observe the affect on the
mechanical behavior of the system.
Once the user is satisfied with the system operation all of the values of the acceleration ramp,
deceleration ramp and motion profile can be
saved on the disk for future use.
SAFE (and SAVE) DESIGN BY SIMULATION
The final section of the SPDS system allows the
user to evaluate the thermal behavior of the device in the application. In this section the movement is simulated based on the average velocity,
as shown in Figure 8. Using the input electrical
parameters of the application and motor, the program calculates the chopping duty cycle and the
effect on power dissipation due to the step rate.
To these values are added the quiescent losses,
which are assumed to be constant, to get find the
power dissipation in the device. The program also
accounts for variation in the RDSon with die temperature.
The simulation outputs two representations of the
information. The first, shown in Figure 9, shows
the power dissipation and required thermal impedance from the junction to ambient (Rthi-a) to
limit the maximum junction temperature to a specified value versus the peak coil current (Ip). For
Figure 7: Operating parameter display
F1
F2
F3
F4
F5
Ace/Dec re~olution
Ace/Dec reeolution
Ace/Dec re:=;olution
Stand-By re~oluti on
Stand-By·re501ution
-.
a
10 lJ·eec
50 1-' .. ~ec
100 )J.:sec
..
=>
T"ce
I
to START
to
STOP
I
i
II
I
Stand-by
>
~
Time increment
Time +1
<
-
Time decrement
Time -I
ESC to
6/9
-
5200 I'."ec
I m. sec
10 m.~ec
Tdee
S
Type
Any key"
1
.
-
490
lJ·sec
200
m. sec
~
!
go back
----------------------------- ~~~~~~~:~~ ----------------------------94
APPLICATION NOTE
Figure 8: Stepper motor movement simulation
Vmax
Speed
Vavg
J
L
Simulation
I(
I
I
Motion
-I
I
Standby
Figure 9: Power dissipation and required thermal impedance
(UJ
("ClUJ
Ptot
RthJ-a
3.5G
55
2.72
44
Ip= 11.'199 II
Ptot=
11.918 W
Rthj-a.=
Ptat
\
42'C/W
CONDITIONs :
Tj= 11111
'c
Ta: (,0 "C
f (oscl=2I1HHz
Sil1sle L6223
Fu II Step
1.88
33
Total' On board'
heahink copper
area:
A= 5.127 emt
1.114
22
11.211
11
Rthj-a
(AJ
.~~~---.~--~~--~~---------------+
r---0.111
II.J2
Grid
0.55
11.77
ip
Step FINE
re~uired values of thermal impedance less than
55 C/W (the thermal impedance of the package
in free air) the power dissipation is calculated assuming a constant thermal impedance of 55°C/W.
For any give!] value of current, selected by moving the cursor, the calculated value for Pd and
Rthj-a are shown on the top of the graph. The program also calculates the number of square inches
of copper required on the printed circuit board to
achieve the required thermal impedance, for
---------------------------
1.1111
values that are achievable in this manner. When
the power dis~ipation exceeds the level that may
be dissipated in this configuration, a message
that an external heat sink is required is displayed.
The second output (see fig. 10) of the simulation
program calculates the power dissipation and die
temperature assuming constant values of Rthj-a.
For this simulation, three values of thermal impedance are chosen; the thermal impedance of
~~~~~~~~:~~©~
----------------------------7/9
95
APPLICATION NOTE
Figure 10: Power dissipation and die temperature
[UI
ptot
Peak Unh=! 35 'l.
Ip = B.SSo n
IjJB= 95 ·C
Pd:l8= 1.175 \I
3.82
/
2.32
Tj4B= 189 ·C
TjSS= 131
Pd48= 1.228 \I
PdSS= 1.296 II
r-
·C
COHDITIOHs
Ta= bll"C
{(osc) =2IlHHz
Single Lb223
Full step
1.&1
Hth=3S'C/U
Rth=46'C/W
lUll
Rth=SS"C/II
[AJ
_ _ _ _ l ____ . ____ ....l.....-_ _ _ _ _ _ _ - L -_ _ _ - - - ' - - . _ _ ,_........l _ _ _ _ _ _ _ _ • _ _ . _ _ _ _
0.32
1--------_·6.111
B.S5
Grid
0.77
~
S.28
Ip
1.06
Step COnRSE
ESC
to
904
Figure 11: Acceleration ramp timing
-:-
.
I
TIM E (
TI ME (
TI ME (
TIME (
TIME (
TIME(
TI ME (
TIME(
TIME(
1
)*
2
3
)~
)
)
)-
(,
)
7
8
9
)-
T.lME( 10
TI ME ( 11
Help
SlIve
--
4
5
.
)~
)) ~
)-
6200
4540
3130
2540
2200
1970
1790
1660
1550
1470
1390
IJsec
IJsec
IJsec
IJsec
IJsec
jJsec
IJsec
iJsec
iJsec
iJsec
IJsec
Delete
Page Up/Down
the ~ackage in free .air (55°C/W), the minimum
practical value of thermal impedance using only
copper on the PCB (40 oC/W) and the minimum
practical value using an external clip on heat sink
(30 oC/W).[4] Each of the graphs are interrupted
when the die temperature exceeds 150°C the
maximum rating of the device. When the cJrrent
level selected by the cursor would cause the device to exceed the maximum rating, a message is
displayed that the device will go into thermal shut
down at that level.
8/9
-,-------,-----c------
96
Number of TI MEs
Fin,,] SPEED
Current SPEED
FUll STEP
Chllnge
:
:
:
21
1023.62
161 .20
ESC to go b"ck
CONCLUSION
The Smart Power Development System allows
the user to quickly evaluate a smart power device
in the final application, much as emulator systems
allow user to evaluate and debug microprocessors. The system contains two key components
that allow the user to 1) quickly define the operation of the device and evaluate it in a real time
application and 2) verify that the device will operate within the its. safe operating limits. For compli-
LW·~~~~1:gr::n!?n
APPLICATION NOTE
cated devices that require the user to program
one or more internal registers before the device
will operate, the system can greatly reduce the
time required to evaluate the system, without requiring the user to write any specific software.
REFERENCES
1)A. Leenouts, The Art and Practice of Step
Motor Control, Intertec Communications Inc.,
Ventura Ca., 1987
2)T. Hopkins, "A Single Chip Driver for Unipolar
Stepper Motors", Proceedings of Motor-Con '89
(PCIM 89). Long Beach Ca, October 1989, pp
437-445
3)"L6223A Data Sheet", Industrial and Computer
Peripheral ICs databook 2nd Edition, 1992, pp
449 to 479.
4)T. Hopkins, "Designing with Thermal Impedance" Proceedings of the Fourth Annual IEEE
Semiconductor Thermal and Temperature Measurement Symposium, San Diego, Ca., Feb. 1988.
_ _ _ _ _ _ _ _ _ _ _ _ _ ~ SGS.1HOMSON _ _ _ _ _ _ _ _ _ _ _ _ _9_/9
b...,I
U-+---o
C.1.
IN4Q------+---+--~--~
5V
I-<>---+-C:::J--o 5 V
SENSE
RESISTORS
fl9211N468-8!
- - - - - - - - - - - - Gil
S[iS·THOMSON
• J,
3/11
1i
~ S(iS.THOMSON _ _ _ _ _ _ _ _ _ _ _ _7_/1_1
- - - - - - - - - - - - - - - """"'!I
i!iIn"'oo@~~~©1rIil@li!n"'$
107
APPLICATION NOTE
Figure 11: Spikes on the sense resistor caused by reverse recovery currents and noise can trick the
current sensing comparator.
SYNC
Motor
Current
Expected
Actual
Vref
"'1 '
-
-
-
"/'-
I
Vsense
_ _ _ _ L -_ __
drivers, like the L298N, internal parasitic structures' often produce recovery current spikes similar in nature to the diode reverse recovery current
and these may flow through the. emitter lead of
the device and hence the sense resistor. When
using DMOS drivers, like the L6202, the reverse
8/11
recovery current always flows through the sense
resistor since the internal diode in parallel with the
lower transistor is connected to the source of the
DMOS device and not to ground.
In constant off time FM control circuits, like the
PBL3717A, the noise spike fools the comparator
- - - - - - - - - - - - - - - - ~~~~~~~:~~~ ----------------108
APPLICATION NOTE
and retriggers the monostable effectively muitiplying the set off time by some integer value.
Two easy solutions to this problem are possible.
The first is to put a simple RC low pass filter between the sense resistor and the sense input of
the comparator. The filter attenuates the spike so
it is not detected by the comparator. This obviously requires the addition of 4 additional components for a typical stepper motor. The second
solution is to use the inherent set dominance of
the internal flip-flop in the L297 or L6506 [1 ][3] to
mask out the spike. To do this the width of the oscillator sync pulse is set to be longer than the sum
of the propagation delay (typically 2 to 3Jls for the
L298N) plus the duration of the spike (usually in
the range of 100ns for acceptable fast recovery
diodes), as shown in figure 12. When this pulse is
applied to the flip-flop set input, any signal applied
to the reset input by the comparator is ignored.
After the set input has been removed the comparator can properly reset the flip-flop at the correct point.
The corresponding solution in frequency modulated circuits, is to fix a blanking time during which
the monostable may not be retriggered.
T.he best V'!ay to evaluate the stability of the chopping CIrCUIt IS to stop the motor movement (hold
the clock of the L297 low or hold the four inputs
constant with the L6506) and look at the current
wave forms without any effects of the phase
changes. This evaluation should be done for each
level of current that will be regulated. A DC curr~nt probe, like the Tektronix AM503 system, provides the most accurate representation of the
motor current. If the circuit is operating stability,
the current wave form will be synchronized to the
sync signal of t~e control circuit. Since the spikes
discussed previously are extremely short, in the
r~nge of 50 to 150 ns, a high frequency scope
With a bandwidth of at least 200 MHz is required
to evaluate the circuit. The sync signal to the
L297 or. L6506 provides the best trigger for the
scope.
The other issue that affects the stability of the
constant frequency PWM circuits is the chopping
mode selected. With the L297 the chopping signal
may be applied to either the enable inputs or the
four phase inputs. When chopping is done using
the enable inputs the recirculation path for the
current is from ground through the lower recirculation diode, the load, the upper recirculation
diode and back to the supply, as shown in Figure
6c. This same recirculation path is achieved using
two phase chopping, although this may not be implemented directly using the L297 or L6506. In
Figure 12: The set-dominanct latch in the L297 may be used to mask spikes on the sense resistor that
occur at switching.
CLOCK
t-
VREF
LJr-p-AR-A-SI-Tl-C---------LJ~-------L-~t
I.
~
I
I
SPIKE
RS
V
-t
t
L297
REF
_____________________________ ~~~~~~~~:~~~ ___________________________
9/__
11
109
APPLICATION NOTE
this mode, ignoring back EMF, the voltage across
the coil during the on time (t1) when current is increasing and the recirculation time (t2), are:
V1 = Vs - 2 Vsat - VRsense
and
V2 = Vss + 2 VF
The rate of current change is given by (ignoring
the series resistance):
V=L~
dt
Since the voltage across the coil (V2) during the
recirculation time is more than the voltage (VI)
across the coil during the on time the duty cycle
will, by definition, be greater than 50% because tl
must be greater than t2. When the back EMF of
the motor is considered the duty cycle becomes
even greater since the back EMF opposes the increase of current during the on time and aides the
decay of current.
In this condition the control circuit may be content
to operate stability at one half of the oscillator frequency, as shown in Figure 13. As in normal
operation, the output is turned off when the current reaches the desired peak value and decays
until the oscillator sets the flip-flop and the current
again starts to increase. However since tl is
longer than t2 the current has not yet reached the
peak value before the second oscillator pulse occurs. The second oscillator pulse then has no effect and current continues to increase until the set
peak value is reached and the flip-flop is reset by
the comparator. The current control circuit is com-
pletely content to keep operating in this condition.
In fact the circuit may operate on one of two
stable conditions depending on the random time
when the peak current is first reached relative to
the oscillator period.
The easiest, and recommended, solution is to
apply the chopping signal to only one of the
phase inputs, as implemented with the L297, in
the phase chopping mode, or the L6506.
Another solution that works, in some cases, is to
fix a large minimum duty cycle, in the range of
30%, by applying an external clock signal to the
sync input of the L297 or L6506. In this configuration the circuit must output at least the minimum
duty cycle during each clock period. This forces
the point where the peak current is detected to be
later in each cycle and the chopping frequency to
lock on the fundamental. The main disadvantage
of this approach is that it sets a higher minimum
current that can be controlled. The current in the
motor also tends to overshoot during the first few
chopping cycles since the actual peak current is
not be sensed during the minimum duty cycle.
EFFECTS OF BACK EMF
As mentioned earlier, the back EMF in astepper
motor tends to increase the duty cycle of the
chopping drive circuits since it opposes current increased and aids current decay. In extreme,
cases where the power supply voltage is low
compared to the peak back EMF of the motor, the
duty cycle required when using the phase chopping may exceed 50% and the problem with the
stability of the operating frequency discussed
Figure 13: When the output duty cycle exceeds 50% the chopping circuit may sinchronize of a
sub-harmonic of the oscillator frequency.
SYNC
Vref
~
"' ..
" .......
,,/
Expected Motor Current
Actual Motor current
110
>.~.
APPLICATION NOTE
above can occur. At this point the constant frequency chopping technique becomes impractical
to implement and a chopping technique that uses
constant off time frequency modulation like implemented in the
PBL3717 A,
TEA3717,
TEA3718, and L6219 is more useful.
Why Won't the motor move
Many first time users of chopping control drives
first find that the motor does not move when the
circuit is enabled. Simply put the motor is not
generating sufficient torque to turn. Provided that
the motor is capable of producing the required
torque at the set speed, the problem usually lies
in the current control circuit. As discussed in the
previous section the current sensing circuit can
be fooled. In extreme cases the noise is so large
that the actual current through the motor is essentially zero and the motor is producing no torque.
Another symptom of this is that the current being
drawn from the power supply is very low.
Avoid Destroying the Driver
Many users have first ask why the device failed in
the application. In almost every case the failure
was caused by electrical overstress to the device,
specifically voltages or currents that are outside
of the device ratings. Whenever a driver fails, a
careful evaluation of the operating conditions in
the application is in order.
The most common failure encountered is the result of voltage transients generated by the inductance in the motor. A correctly designed application will keep the peak voltage on the power
supply, across the collector to emitter of the output devices and, for monolithic drivers, from one
output to the other within the maximum rating of
the device. A proper design includes power supply filtering and clamp diodes and/or snubber networks on the output [6].
Selecting the correct clamp diodes for the application is essential. The proper diode is matched
to the speed of the switching device and main-
tains a VF that limits the peak voltage wit~in the
allowable limits. When the diodes are not integrated they must be provided externally. The
diodes should have switching characteristics that
are the same or better than the switching time of
the output transistors. Usually diodes that have a
reverse recovery time of less than 150 ns are sufficient when used with bipolar output devices like
the L298N. The 1N4001 series of devices, for
example, is not a good selection because it is a
slow diode.
Although it occurs less frequently, excess current
can also destroy the device. In most applications
the excess current is the result of short circuits in
the load. If the application is pron to have shorted
loads the designer may consider implementing
some external short circuit protection [7].
Shoot through current, the current that flows from
supply to ground due to the simultaneous conduction of upper and lower transistors in the bridge
output, is another concern. The design of the
L298N, L293 and L6202 all include circuitry specifically to prevent this phenomena. The user
should not mistake the reverse recovery current
of the diodes or the parasitic structures in the output stage as shoot through current.
SELECTED REFERENCES
[1]Sax, Herbert., "Stepper Motor Driving" (AN235)
[2]"Constant Current Chopper Drive Ups StepperMotor Performance" (AN468)
[3]Hopkins, Thomas. "Unsing the L6506 for Current Control of Stepping Motors" (AN469)
[4]'The L297 Steper Motor Controller" (AN470)
[5]Leenouts, Albert. The Art and Practice of Step
Motor Control. Ventura CA: Intertec Communications Inc. (805) 658-0933. 1987
[6]Hopkins, Thomas. "Controlling Voltage Transisnts in Full Bridge Drivers" (AN280)
[7]Scrocchi G. and Fusaroli G. "Short Circuit Protection on L6203". (AN279)
11/11
----------------------------- ~~~~;~g~:~~ -----------------------------
111
APPLICATION NOTE
USING THE L6204, A BIPOLAR STEPPER AND
DC MOTOR DRIVER IN BCD TECHNOLOGY
by E Balboni
Containing two H-bridge drivers, the L6204 is a compact and simple solution for driving two-phase bipolar stepper motors and in applications where two DC motors mustbe driven.
The L6204 is a DMOS dual full bridge driver
mainly designed to drive bipolar stepper motors.
All the inputs are TTL/CMOS compatible and
each bridge can be enabled by its own dedicated
input. The windings current can be regulated by
sensing the voltage drop across two low value resistors at the low end of both the bridge: this is
the feedback for the current controller. To feed
the gates of the upper DMOS, a peak to peak rectifier charges a capacitor in series with the Power
Supply voltage at the optimum DC level defined by
an on-board square wave oscillator. The L6204,
with 0.5 A drive capability without extemal heatsink
up to 70 D e, is packaged in a 20 leads PowerDip
with four heat transfer pins. The Block diagram of
the device is shown in fig.t.
Figure 1 : Block diagram of the L6204 single chip dual full bridge driver.
...
m
:::>
...
'"
I- I:::J:::J
'"
m
:::>
00
'" ...
I- I:::J:::J
00
VBOOT
INt
IN4
" - - - - - - - 1 - - - - - 4 - . - - < 1 ENABLE 2
ENABLE 1
IN2
IN3
BOOTSTRAP
OSCILLATOR
L6204
SENSE 1
AN379/0690
GNO
SENSE 2
1f9BL62D.t-Bt
1/7
113
APPLICATION NOTE
Cycle of the input signal it is possible to vary in
Open Loop Mode the steady state speed of the
DC motor: this is possible because the average
current in the winding is dependent from the Duty
Cycle. The UR ratio must be a few times shorter
than the minimum DC. In a similar way it can be
dimmed a lamp connected to the supply (Z2) or to
ground (Z3). Very often, when a DC motor is
driven, peak current and speed must be booth
controlled in a Closed Loop Mode.
GENERAL APPLICATIONS HINTS
The L6204 can be used in a very wide range of
applications such as the drive of lamps, solenOids, DC motors or any other inductive loads.
The drive of different loads in single-ended configuration is shown in fig.2. The current in the
Load Z1, that may be a DC motor, can flow in
both the directions but its peak amplitude cannot
be controlled. By means of a change of the Duty
Figure 2: The L6204 is not intended only for Bipolar Stepper applications: here above three different driver
configurations are shown. Z1 is a DC motor to be driven in both CW and CCW direction. Z2 can
be solenoid like a relay or hammer. Z3 can be an alogen lamp which light intensity is controlled
by variable Duty Cycle.
100nF
D2
12
D1
C3
28
10nF
11
I }2
17.14
7
EN(Zl) <>----03
r---018
IN.L
11
1}
Z1
EN(Z2:Z3)
8
L6204
+-·--04
5.6
1 2 19 15.16 9
Us
13
13
12
Hl
L
1},
IN.H
uS/21
IN(ZU
IN(Z2)
IN(Z3)
(H: l)
(l)
(H)
This is achieved by the configuration shown in
fig.3A. The two independent motors (A and B)
can be controlled by only one controller (L6506).
The sensing resistor (RsA, RsB) generates a voltage proportional to the motor current, that is the
feedback for the current control loop. A second
loop, not shown in figure, can control the speed
stability while the direction is defined by the Input
stat~ Of. t~e L6506. The Enable Input (ENA, ENB)
can inhibit one motor or the other while the Power
Enable acts on both at the same time. D1 and D2
(BAT41 or equivalent), C3 and C4, generates the
bootstrap voltage by rectifiing the wave available
at pin. 11 of the L6204. When more than one
driver is used at the same Supply Voltage on a
common Printed Circuit Board, the bootstrap voltage can be generated only by one of them (master) and used to supply all the other L6204
(slaves) saving diodes and capacitors. R1 C1 (R2
1198L6284-85
C2) is a snubber network that must be closely
connected to the output pins and its use is recommended in all the application circuits using the
L6204. The values can be calculated as it follows:
R = Vs/lp and C = Ip/(dV/dt), where Vs is the
maximum Supply Voltage of the Application, Ip is
the peak of the load current and dV/dt is the Slew
Rate accepted as the optimum compromise between speed and transient generation/radiation
(SR of 200 V/!lS are commonly chosen). The network R5C5 sets the operating frequency according to f = 1/(0.69 R5C5) for R5 2 10Kohm. R3
!3-n9 R4 are used to protect the comparator input
inside the L6506 against possible negative transitions across the sensing resistor RsA or RsB. The
L6204 can be used with paralleled inputs and outputs to double the current capability of the single
bridge; for an optimized solution, however, 1.6
times the nominal current is recommended in-
2/7
- - - - - - - - - - L.,/
SCiS·1HOMSON - - - - - - - - - - •],
~oli::rnJ@rn~rnt1lrnJ@OOO!;~
114
APPLICATION NOTE
stead of two. This configuration is shown in fig.2
to drive the load Z1. A more complex circuit, in
wich one paralleled L6204 drives a DC motor, is
shown in fig.3B; in this example the two chopper
of the L6506 are used to implement two functions: 1) Current Control during speed variation at Ip
max = O.SA and 2) Current Control during brake
and/or direction change at higher current level
that depends from the brake repetition (it must be
in the Max Ratings limit). The divider R6R7
defines the brake current intensity as V17/Rs
while the product (Ip max.) x ( Rs) is the limit of
the reference voltage V16 for speed control. The
Enable function is driven via the L6506 . Since
during the brake time the Enable of the L6506 is
chopped, the motor current ricirculates via the
Supply; because of this a suitable large capacitor
must be connected in parallel to C2.
Figure 3A: Bidirectional DC motor drive. The L6204 can drive two motors.
Us
C3
1139nF
C5:I: 199nF
D2
D1
19nF
C4
ENABLE A
17
3
4
28
14
11
L6204
A
5.6
15.16
18
2
19
1
DIR A
14 13
16
ENABLE B
B
13
18
R3
22K
CURRENT lIo
SPEED A
8
7
12
9
R4
22K
18
15
11 12
17
L6506
5
7
6
CURRENT lIo
SPEED B
OIR B
8
18
Ucc
1
9
2
3
4
POWER ENABLE
----------------------------JC~I ~~~~~~~:~~~
N9BL 62B" - 86
3/7
----------------------------
115
APPLICATION NOTE
Figure3B: Bidirectional. DC motor drive. The L6204 can drive the !!l0tor in a parall~led configu~ation w~ile
the L6506 provides the peak current control both dUring normal rotation and dUring braking
time.
R1
11313nF
Us
18
4
14
17
11313nF
::I:
C2
5.6.15.16
19
14
18
22K
213
L6284
2
Uee
13
7
1
18
3
22K
22K
R2
RS
R3
R4
18
8
15
R5
9
11
12
113nF
13
12
L6586
1
3.3
nF
EN
6
DIRECTION
5
C5
9
4
7
17
8
11
2
3
16
U16
C6
::I:
R6
11313nF
U17
R7
Uref (SPEED)
Stepping Motor Driving
The drive of one stepping motor is shown in fig.4,
where the controller L297 generates the requested signals to drive the motor in Half-Step
Mode or in Full Step Mode.
The rotation speed or step change is controlled
by a clock signal or a single clock pulse at pin.18
(CK). The Mode depends from the logical state of
4/7
1199L6294-97.
the H / F input while the state of the CW/CCW
input defines the direction of the rotation. Depending on the numbered state, odd or even, of
an internal clock pulse at the moment at wich the
Full-Step Mode is selected, the motor is driven
with two-phases-on or with one-phase-on respectively. An open collector output (home) indicates
the translator state 0101 that occurs only during
an odd numbered state of the internal clock.
_______
-------------- "..,,1 SGS·1HOMSON
1ibJ~1:1iiI@~~~I:1i'IiiI@Iil~©@
116
~
~
_ __
APPLICATION NOTE
Figure 4: Bipolar stepping motor drive: phase sequence generation and current peak control are achieved
by means of the controller L297.
o
C1 R1
STEPPER MOTOR
C2 R2
4
18 7
13
16
15
17
6
5
14
L6204
1
20
18
2
3
19
9
12 11
8
18nF
RS8
R4
22K
Uss
4
13
6
5
7
180nF
9
8
I--.
12
22K
14
L297
R3
R5
RSA
2
C7
22K
16
18 28
1
15
I::l
0
4-
Z
Q)
L
W
u
z
:::>
19
18
17
11
3
....J
I::l
0
l-
LL
~
:3
W
":::c
U
U
0
"
I-
(f)
w
a::
>-
u
:3
u
a::
z
0
U
(f)
This last is obtained from the oscillator the frequency of which is fixed by the ratio 1/0.69 R5C5
about (R5 2: 10Kohm). The peak of the chopped
current is given by the. ratio of the reference voltage at pin.15 and the value of the sensing resis-
W
C5:r: 3. 3nF
ff98L6284-B8
E:
0
:::c
tors Rs. When the four phase signals needed at
the inputs of the L6204 are generated in any
other way than by the L297. (for example, via
IlProcessor), the motor driver needs one interface
to control the peak current. One possible solution
is shown infig.5.
- - - - - - - - - - - - - L"'!I ~~~;m~r::~~~
____________5~/7
117
APPLICATION NOTE
Figure 5: The.L6506 can be used to control the peak current in the windings of a bipolar stepper motor.
The power is supplied by the L6204.
STEPPER MOTOR
C6
4
18 7
16
13
6
5
ENA
15
17
14
L6204
3
28
118
2
19
9
12
D2
C3
C4
D1
8 11
18nF
RS2
ENS
R4
22K
22K
R3
RS1
15
18
14
13
12
Uss
188nF
11
b..
18
L6506
1
R5
C7
22K
C5::J:
3. 3nF
22K
Uss
R6
PHASE INPUTS
The motor can be driven in the Full-Step or in
Half-Step Mode. The chopped current Ip is controlled at the value Vref/Rs where Vref is the output voltage of the divider R6 R7. The pins 16
·and 17 (reference input voltage of the controller)
6/7
can be driven with two different signals. This arc
rangement allows to keep constant the motor current a~d the torque during the Half-Step Mode
revolution of the stepper. This behavior is well explained by the fig. 6.
--~-----------------------L~I ~~~1tl?~:~~
118
ff9BL62B4-B9
---------------------------
APPLICATION NOTE
Figure 6: Characteristics of the Half - Step Mode drive with constant torque control. It should be noted that
the resultant current is constant while the current in the windings alternates between
one-phase-on and two-phase-on with a ratio of .,,[2.
B
. Ip
(RESULTANT
B
HALF STEPS
8
8
1
2
3
4
5
6
7
8
8
PHASE ON
AB
A
AS
8
BA
A
AB
B
AB
Uref pin 16{
PHASE PEAK CURRENT
PHASE REDUCED CURRENT
(PhA)
ZERO CURRENT
PHASE PEAK CURRENT
PHASE REDUCED CURRENT
Uref pin 17{
(PhB)
e
ZERO CURRENT
PHASE CURREN{PhA
DIRECTION
DEFINED BY
THE INPUTS PhB
"!18L6284-18
- - - - - - - - - - - - - L."
~~~;m~~:~~lt
------------7/7
119
APPLICATION NOTE
BIPOLAR STEPPER MOTOR CONTROL
By Pierre PAYET BURIN
This application note is intended to provide design
details for the implementation of a stepper motor
control, built around the TEA3717.
This integrated circuit has been developed to offer
control and current regulation of up to 1A, in one
winding of a bipolar motor.
Two TEA3717s and a minimum of external components are sufficient to implement the full control
function of a two-phase bipolar stepper motor.
The system can be commanded, according to the
desired mode of operation, by either fixed or programmable logic.
FUNCTIONAL DESCRIPTION
The circuit is organized around a H-bridge configurated by four transistors and their integrated free
wheel diodes.
The "Phase" input controls the switching of the
bridge transistors and also determines the direction
of the current flow in the winding. The signal applied
to this input is first gated through a Schmidt trigger
and then through a delay element so as to avoid a
simultaneous conduction of transistors when direction of current in the bridge is reversed.
Regulation of winding current is performed by chopping action on the power supply for a duration toff
determined by a monostable.
This monostable is triggered by the output level
swing of a comparator, to the input of which a voltage proportional to delivered output current is applied.
The current spikes corresponding to the diodes
reverse recovery time are filtered by a low pass filter Rc Cc to not trigger the comparator.
Three comparators are available for this purpose:
their thresholds are internally fixed ratios of VR input
voltage. Each of them can be selected individually
by using hand 10 inputs.
Figure 1 : TEA3717 Block Diagram.
AN266J0189
1/12
121
APPLICATION NOTE
Figure 2 : Typical Operating Sequences.
PhA
rH, M, l
r
•-- -
:
f-- -
--
~-
~--...:.-:
fd : toff
'ton;
I
- - - - - - - - - - - - - - - - - - --
: "'-,
I
"-
I
3
2
5
4
VCH, M.l - - -
Vc
v~···'t;/l--
.n-_ . 11-2
;~j
c __
___ n--- 11
4
H
1
_ _ Direction of current flow
2/12
122
Transistors of the bridge are represented by switches:
- switch open: transisto r cut-off
- switch closed: transistor saturated
APPLICATION NOTE
CONTROL OF BIPOLAR TWO-PHASE MOTOR
The proposed diagram features two TEA3717s each controlling one winding. FUll-step and fraction-of-a-step
operation is performed by combined use of phase and current level selection control inputs.
Figure 3 : Control of a Bipolar Two-phase Motor.
ti'"
9'"
I
u
u
:::
>
o
z
~
~
CJ
~
~
1---"'------11·
M
'"_
C;;
w
1:
i0
>
u.
~
a
E
"'
0.
~
>
..'"
a
>
U.
0.
M
&l
11
E
E
>
o
C;;
+
M
z
~
::
CJ
t---1r-------II·
~
~
~
~
0
..M
:::
~
T min
b) incorrect operatktn : T
~
~ ~l
!
03
!
1
3
2
2
~
if
~
4
4
Normal circuit operation
- . . . Direction of current flow.
1b. 2b
3b :
128
3
~
T
5
Identical to 1a. 2a
Q1 cut-off due of conduction of D3.
Slow decrease of current since.
VMS - VMA:::: 0 instead of being - Vmm.
4b _
2b
5b_ 3a
6b_1b.
8/12
< Tmin
6
APPLICATION NOTE
CHOICE OF TOFF : SWITCHING TIME FOR
CURRENT REGULATION
The value of toff determines the quality of the current
regulation inane phase.
The larger the toff. the more important is the current
ripple.
Value of toff is found from the expression toff = 0.69
Rt.Ct where 1kQ :0; Rt:O; 100kQ
A suitable value of toff for the majority of applications
is 30l-1s.
*toff(max)
This is the loff value over which the ripple value
becomes excessive
Let's k be the desired ripple value and t = Llr. the
time constant of motor winding. then:
toff(max) is given approximately by : toff(max) ~ kt
Figure 10: Winding Current@ off (max).
tH,M, L
tmin
I
I
I
',..
It'
toff(max)
IH, M, L - Imin
k~
L
t~
IH. M. L
toff(max) =
kt
9/12
129
APPLICATION NOTE
*tolf(min)
This is the limit under which the current regulation
IS not guaranteed.
Even if the current continually exceeds the threshold
levels IH, 1M or IL, the device will ensure a minimum
conduction time ton(min) which is combination of two
periods;
- td : comparator trigger time and transistor desaturation time implosed by TEA3717
- t'd ; this is the time required by Vc to reach the comparator threshold level and is determined by low
pass filter Rc, Cc.
Therefore, toll must be selected to be long enough
to allow the current to fall to a level below IH, 1M or
IL.
Supply voltage Vmm and winding characteristics
both determine the value of toll(min).
Figure 11 : Winding Current @ TOFF(MIN).
toff
totflmin)
toff" Inllimini
Figure 11 Bis: Winding Current, VE and Vc Voltages @TOFF(MIN) .
•
't
at
.' •
Innfnllll;
VE and
Vc
- - vr
-~.
VCH.M.L
- Vc
__ __ _ _ _ _
.
\
.
\
\
\
\
L -_ _ _ _ _ _L -_ _---=l.-_\.\. _ _ _ _ _ ~_ ___>~~ . _ _ _ _ _ _ _ - - - .
10112
130
APPLICATION NOTE
SELECTION OF Rs VALUES
Three values of motor current IH, 1M and IL are determinated by the choice of Rs and VR values.
The value of Rs is calculated such that VCH
= Rs.IH
0.42
where VCH
=5
VR and IH is the maximum motor supply current.
A choice of Rs value around 1Q will guarantee a
fast increase of the winding current and offers the
possibility of operation with a voltage around 5 V for
VR, and thus is suitable for most applications.
It is also possible to vary the motor current in a continuous mode:
_ by VR adjustment
_ by feeding back a portion of the voltage drop
across Rs through a potentiometer whose wiper
is connected to the comparator input.
In order to minimize the differential voltage VE - Vc
due to comparator's input current, care must be
taken to avoid the appearance of a large impedance
between E and C terminals. Appropriates values of
P and Rc would be : P = 1 kQ and Rc = 470Q .
Figure 12: Continuous Variation of Current Level.
TEA3717
c
11/12
131
APPLICATION NOTE
CABLING
_ Connection link between RS and the TEA3717
must be kept as short as possible
_ Decoupling of Vmm by a ceramic capacitor (15 to
150nF) directly connected to the TEA3717 and
also by an electrolytic of higher value: 10 to 22~F,
_ Decoupling of Vee,
Since the TEA3717 operates in switch mode it is
essential to take particular cabling precautio~s so
~s to avo,id the generation of interferences susceptible to disturb the correct operation of the control
electronics,
Recommended precautions are:
_ Separated ground connection for Vmm supply
Figure 13: TEA3717 PC Board Layout.
1
Vmm
::
GND (Veel
GND (Vmml
=-~
1
TEA
3717
8
"n
RS
~
9
I
PI1~
LOGIC
CIRCUITS
LOGIC
CIRCUITS
11~
10~
VCC
I
I
CORRECT LAYOUT
16
1
~
Vmm
GND
I
TEA
3717
r-
8
9
Ph~
LOGIC
CIRCUITS
VCC
11
t--
10
t--
I
I
INCORRECT LAYOUT
12/12
132
LOGIC
CIRCUITS
APPLICATION NOTE
SHORT CIRCUIT PROTECTION ON L6203
By G. SCROCCHI and G. FUSAROLI
With devices like L6203 used as driver often interfacing the external world by means of wires, can be
easy to have short circuits.
A short circuit can occur for many reasons: a short
on the load, a mistake during the connection of the
wires between the device and the load (i.e. L6203
driving a motor), an accidental short between the
wires and so on.
The outputs of L6203 are not protected against the
short circuit and if a short occurs, the big amount of
current flowing through the outputs can destroy the
device.
To avoid this risk can be useful to add a circuitry to
protect the device: in this case, to have a total protection, we must consider three types of short circuit:
1 - output to output short circuit
2 - output to supply voltage short circuit
3 - output to ground short circuit
The first step is to sense the short circuit current.
In output to output (fig 1) or output to supply (fig 2)
short circuit can be used the sensing resistor (Rsl)
already used to set the current flowing in the load
during the normal operation.
Figure 1.
Us
OUTPUT
SHORT - C I RCU IT
rt=====*=::!:'..o LOAD
1188L62B3-0;'
Figure 2.
Us
Us
SHORT - CI RCU IT
OUTPUT TO SUPPLY
I.OAD
AN279/0189
1/3
133
APPLICATION NOTE
To sense the output to ground short circuit (fig 3) another sensing resistor (Rsu) must be added between the
supply pin and the supply voltage.
Figure 3.
Us
The second step is to create a threshold over which
the value of the current must be considered as short
circuit: for this way a transistor or a diode could be
used.
The complete protection will be given by the' or ' of
the signal coming from the upper and the lower sensing circuitry; this signal can be used to act on the ENABLE pin of the L6203 disabling the output stages.
A complete protection schematic diagram is shown
in fig. 4.
Figure 4.
Us
RSU
11. Hl
2N29B7A
2
5
3
DUH
INl
+5
I
I
7
IN2
9
LDAD
L6203
11
EN
I
TLS1B6-B5
6
22.,
0
lB
DUT2
TO L297
lN4148
68
0
8.1650
RSL
t188L6283·18
2/3
134
APPLICATION NOTE
In normal operation the circuit works up to 3N40V.
When a short circuit occurs the SCR is triggered and
L6203 disabled: due to the SCR memory L6203 is
kept disabled until the power is switched off and then
on, if the cause of short was removed.
R1 and R2 are used to scale the signal when the
transistor goes on and in conjunction with C1 to filter the short circuit signals in order to avoid false trig
ger of the SCR : this filtering should not be too much
heavy to avoid to introduce an excessive delay in
the short circuit loop.
The short circuit is detected when:
Isu and lsi must be calculated at the effective operating temperature being the Vbe and Vd temperature dependent.
Isu > VBE(T1) = ..Q.:.§. = 6A
Rsu
0.1
ISL> VD + VTHSCMT = 0.6 + 0.7 = 7.BA
Rsc
0.165
Instead of the SCR, a monostable with a long time
constant (0.3 ... 0.5 sec) can be used: in the case,
every time a short circuit occurs, L6203 is disabled
for the monostable time constant and then enabled,
if the short is still present L6203 is disabled again, if
the short was removed L6203 returns in normal
operation (fig 5).
The effective short circuit peak current is greater
than Isu and lsi: this is due to the high dl/dT during
the short and to the delay between the short circuit
detection and the ENABLE intervention:
Rsu and Rsl must be non inductive resistors.
Figure 5.
Us
2N2987A
5
3
OUT1
6
OUT2
IN1
IN2
L5283
MONOSTADLE
..--+--.-IT' i74HC1231 Q
8.3
to
11
EN
8.~5ec
18
lN41A8
Icc
IISU. ISL)
EN
~
/\
I
n
OUT~
OUT OFF
0~--~=-~~--~~
OUT OFF
NBSL 6283 - 11
R1, R1, C1, Rsu, RSL are choosen depending on the application.
The intervention of the protection circuit is determined by
VSE
Isu> - VD = VDIODE
Rsu
VIH = min Vlnput High T + Monostab
ISL >
V1H + VD
-:=---
RSL
3/3
135
APPLICATION NOTE
CONTROLLING VOLTAGE TRANSIENTS
IN FULL BRIDGE DRIVER APPLICATIONS
by Thomas L. Hopkins
In applications that involve fast switching of inductive loads, designers must consider the voltage transients that are generated in such applications. To
insure a reliable design, the voltage transients must
be limited to a level that is within the safe operating
conditions of the switching device. This application
note discusses the sources of voltage tran-sients in
full bridge applications and techniques that can be
used to limit these over-voltage conditions to safe
levels. Special attention will be given to applications
using monolithic implementations of full bridge circuits like the SGS-THOMSON L6202 and L6203.
exceed 60V. Therefore, the maximum ratings that
must be considered for the application are:
Vsupply
60V
Vds any output 60V
V01 - V02 :
60V
Similar maximum ratings will exist for any full bridge
application, with the exception of the differential output voltage limit, which will not exist for discrete implementations.
Figure 1 : DC Motor Drive Circuit using L6203.
MAXIMUM RATINGS
The maximum voltage rating for the bridge driver
can be derived from the maximum ratings of the devices used in the output stage and are generally the
BVceo or BVdss of the power devices. In addition to
the maximum allowable voltage across the output
device, additional limits may be needed on the maximum output voltage above supply or below ground,
depending on the implementation of the output
stage.
As an example of a full bridge circuit, consider the
SGS-THOMSON L6202 and L6203. These devices
are full bridge drivers implemented with DMOS transistors on a monolithic structure. Using these devices full bridge drive circuits, like shown in figure 1,
are easily implemented. The device has a maximum
rating for the supply voltage of 60V, which implies a
maximum BVdss forthe output devices of 60V. In addition, due to the monolithic implementation, the
voltage between the two output terminals must not
AN280/0189
L5282/L5283
lis
INl
TO {
CONTROL
LOGIC
OUT 1
I N2
libl
EN
lib2
t-.~---,
e.22uF
ff88L6287-Bli
1/7
137
APPLICATION NOTE
SOURCES OF VOLTAGE TRANSIENTS
To protect against the over-voltage that may occur
as a result of the inductive property of the load, voltage clamps are normally employed to limit the voltage across the output devices. In bridge
applications these clamps are normally a diode
bridge that clamps the voltage to one diode drop
above supply and one diode drop below ground.
However, if the diode switches slower than the transistor, there is a short time where neither the transistor nor the diode is conducting and the voltage
rise is limited only by the capacitance on the node.
The result is that a vol-tage overshoot occurs during the time before the diode turns on. When the
bridge is build with DMOS power transistors, the intrinsic body diode is often used as the clamp. This
is true for the L6202 and L6203. As can be seen in
the figure 2, the turn-off time of the DMOS device in
the L6203 is in the range of 25 to 50nS while the
turn-on time of the intrinsic drain to source diode is
in the range of 150nS. This difference in switching
time is characteristic of many DMOS devices.
the current flowing in these parasitic inductances is
rapidly switched, the inductive property of the wire
causes a voltage transient. When large currents are
rapidly switched, as with DMOS transistors, large
voltage transients can be induced across even small
parasitic inductances. For an inductive load driven
by an H-Bridge the change of current in the power
supply lead is equal to twice the load current when
the bridge is switched off or the bridge is switched
from one diagonal pair of transistors being on the
other pair. Here switching the bridge results in a
change of direction of current flow in the power
leads. The time that it takes to switch the current is
essentially the turn off time of the output device. In
this case the resu Iting voltage across the inductance
is given by the equation:
v= Ldildt=
~
Toff
(1)
Figure 3 : Parasitic wiring Inductances in DC
Motor Drive Circuit.
Figure 2 : Output Switching Waveform for L6203.
WIRE INDUCTANCE
L52B2/L62B3
Us
IN1
The second main factor contributing to the transients is the parasitic inductance in the wiring or
printed circuit board layout. Figure 3 shows the parasitic inductances in the DC motor application. When
2/7
138
DUT 1 hr----,
I N2
Ub 1
EN
Ub2
APPLICATION NOTE
In fast switching applications, like the L6202, where
the switching time is as short as 25nS, the induced
voltage spike can become quite large, For example
if the DC motor in figure 3 was driven with 4A and
the bridge was switched off, a parasitic inductance
of only 15nH would produce a 5V spike, Since the
current is reversed in both the supply and ground
leads the device would see a 1OV spike between the
power supply pin and chip ground, if the inductance
of both wires were the same,
As a design example, consider a DC motor driver
shown in figure 1 with the following system characteristics :
Supply Voltage
Max 46V
Min 38V
Peak Motor Current
5A
Chopping Frequency 50kHz
Figure 4 : Enable Input and Motor Current for
Examples,
For evaluation, the motor will be driven with a peak
current of 4A Figure 4 shows the input signals for
the L6202 and the motor current used in the evaluation,
Here the bridge is energized and the load current is
allowed to build up to 4A, When the 4A peak is
reached, th'e bridge is disabled and the current decays through the intrinsic diodes in the DMOS power
stage. All figures in the remainder of this note are
taken under these operating conditions,
POWER SUPPLY FILTERING
To reduce the effect of the wiring inductance a good
high frequency capacitor can be placed on the board
near the bridge circuit to absorb the small amount
of inductive energy in the leads, it should be noted
that this capacitor is usually required in addition to
an electrolytic capacitor, which has poor performance at high frequencies.
Operating Voltages.
Figure Sa : Supply Voltage.
3/7
139
APPLICATION NOTE
Figure Sa shows the spike on the power supply pin
of the L6203 and the output pins when the bridge
was disabled. These waveforms were present when
the device was mounted on a printed circuit board
where reasonable care was taken in the layout.
When a 0.21lF polyester capacitor was connected
between the supply and ground pin of the L6203 the
voltage spike on the power supply was significantly
reduced, as shown in figure 6a.
Figure 6a : Supply Voltage.
Figure 5b : V01 - V02.
Figure 6b : V01 - V02.
Looking at the voltage waveform at the output terminals of the L6202, shown in figure 6b, a large
spike is still present. The worst case spike is
measured between the output terminals of the device (VOUI1 - Vou t2) since the spikes above the supply and below ground are both present. After the
voltage spike on the power supply was eliminated,
the tran-sients on the output must be related to the
mismatch of switching times between the diodes
and power transistors. To control these spikes two
possible alternatives are present ; 1) use faster
diodes, or 2) use an external circuit to slow the voltage rise time across the output when the transistors
are turned off. Schottky diodes connected external
to the L6203 would more closely match the switching time of the DMOS power transistors, but are expensive and require additional board space.
Operating Voltages with 0.21lF Bypass Capacitor on
Supply Pin.
4/7
140
Slowing down the output voltage rise time can be
accomplished by connecting a snubber network
across the output ter minals of the device. Figure 7
shows the connection for a RC snubbing circuit used
with the L6203. With properly selected values the
slope of the voltage waveform can be limited to
where the diodes have sufficient time to turn on and
clamp the remaining inductive energy.
APPLICATION NOTE
SNUBBER DESIGN CONSIDERATIONS
The function of the snubber network is to limit the
rate of change of the voltage across the motor (output terminals of the L6203) when one of the DMOS
devices is turned off. Using the RC snubbing circuit
shown in figure 7, the rate of change of the voltage
on the output is dominated by the capacitor while
the resistor is used primarily to limit the peak current
flowing through the power transistor when it turns
on.
Figure 7 : DC Motor Drive Applications with Snubber Network and Bypass Capacitor.
current is switched into the snubber, the voltage
across the snubber network will jump to a value
equal to the snubber resistance times the motor current. Afterthe initial step, the rate of change is limited
by the motor current charging the snubber capacitor.
To properly size the snubber network the resistor is
selected such that the maximum motor current will
produce a voltage less than the minimum power
supply voltage. If the resistor is larger than this
value, the snubber will be ineffective since the capacitor will not limit the voltage rise until the voltage
has become greater than the power supply. For the
de-sign example, the maximum resistance for the
snubber is given by the equation:
Rmax = Vsmin/lpeak = 38V/5A= 7.6 Ohm
(2)
The snubber capacitor is calculated from the peak
current and the target rise time. The capacitance is
given by the equation:
C ;; Ipeak dtldv = 5A 150nS/50V = O.015)lF
(3)
When the snubber network is installed in the application the voltage transients on the terminals of the
L6203 are greatly reduced, as shown in figure 8.
The time constant of the motor current is much
longer than the switching time, due to the inductance of the motor. At the time of switching the DC
motor can be assumed to be a constant currentgenerator equal to the peak current at switching. If this
The drawback of a snubber network of this type is
that a current spike will flow into the transistor when
it is switched on as the capacitor is discharged. The
theoretical peak value of this spike is given by the
equation:
I = Vsmax/R = 42V/7.50hm = 5.6A
(4)
5/7
141
APPLICATION NOTE
Operating Voltages with Snubber Network and Bypass Capacitor.
Figure 8a : Sypply Voltage.
the snubber circuit current plus the .load current. In
practice the peak current measured is usually much
less than the calculated peak, due to the capacitors
internal resistance and inductance and the resistor
inductance. Figure 9 shows.the peak current in the
snubber network in the design example,
Current in the Snubber Circuit.
Figure 9a : Turn on 2.0Ndiv.
Figure 8b : V01 - V02.
The power dissipated in the snubber resistor is the
sum of the dissipation during the turn-on and turnoff of the bridge. The resistor dissipation is :
Pd = (11 2RDC) + (12 2 HDC) (5)
where
h = Current at turn-on
12 = Current at turn-off
R = Snubber resistor
DC = Duty Cycle of current flow
For the design example the power dissipation, not
considering the duty cycle is :
Pd = ((2.5f7.5".01) + ((5)27.50.01)
This peak current flowing in the snubber is added to
the load current when the device is turned on and
the total peak current in the transistor is the sum of
6/7
142
= 0.469 + 1.875
= 2.344 W (6)
APPLICATION NOTE
If the device is chopping for only a portion of the time
the dissipation in the resistor will be reduced.
Figure 9b : Turn off 2.0Ndiv.
CONCLUSION
With the O.2IlF bypass capacitor and the snubber
circuit in place the voltage transients measured in
the application have been limited to within safe
values for the L6202. As shown in figure 8, the
power supply voltage, the voltage across each of
the DMOS transistors and the voltage across tbe
output of the bridge (Vout1 - Vout2) are all within the
maximum rating of the device with some margin.
SUMMARY
To insure reliable performance of a H-bridge drive
circuit, the designer must insure that the device
operates within the maximum ratings of the device(s) used in the circuit. One of the critical parameters to consider is the maximum voltage capability
of the devices. To maintain the reliability, the voltage transients due to switching inductive loads must
be maintained within the ratings of the device.
Two techniques used to control the voltage transients in fast switching applications are proper bypass filtering of the power supply and snubbing the
outputs to control voltage rise times. Using these
two techniques the voltage transients in a DMOS
bridge application can be controlled to within safe
levels.
717
143
APPLICATION NOTE
A HIGH EFFICIENCY, MIXED-TECHNOLOGY
MOTOR DRIVQR
By C. CINI
A new mixed technology called Multipower-BCD allows the integration of bipolar linear circuits. CMOS logic
and DMOS power transistors on the same chip. This note describes a H-bridge motor driver IC realized with
this technology.
The miniaturization and integration of complex systems and subsystems has led in recent years to the
implementation of monolithic circuits integrating
logic functions and power sections.
For these applications SG8-THOMSON Microelectronics has developed a new technology called
Multipower BCD which allows the integration on the
same chip of isolated Power DMOS elements, bipolar transistors and C-MOS logic.
Thanks to high efficiency, fast switching speed and
the absence of secondary breakdown, this technology is particularly suitable for fast, high current sole-
noid drivers and high frequency switching motor
control. The free-wheeling diode intrinsic to the
DMOS structure (necessary if the device drives an
inductive load) and the great flexibility available in
the choice of the logic and driving section components allow the complete integration of power actuators without further expense in silicon area-and a
compact implementation of complex signal functions.
This technology has been applied to produce a
switching power driver - the L6202/3 - capable of delivering 4A per phase, which is suitable for speed
and position control in D.C. motor applications.
Figure 1 : A Schematic Cross Section of Bipolar, C-MOS, DMOS Structures (BCD).
L _____ ----' ._ _ _ _-"
POW EROM esc 1~1 05
s~
9351
MUL TIPOWER BCD TECHNOLOGY
Multipower BCD technology combines the well
known vertical DMOS silicon gate process, used for
discrete POWER MOS devices, and the standard
junction isolation, sinker and buried layer process.
The architecture of the process is centred around
the vertical DMOS silicon gate, a self aligned structure, which guarantees short channel length
(1.5 11m) with consequent low RDs(ON) for the device.
AN234/1088
L._._II_.~
HPN
.... J L ______..J
PNPH. V. P- CH
MOS
In standard IC technologies the voltage capability is
determined essentially by the thickness of the epitaxial layer and it is the same for signal and power
components. But if the epi thickness is increased to
allow the inclusion of high voltage transistors even
the linear dimension of small signal transistors must
be increased proportionally. In contrast MULTIPOWER BCD permits the realization of high voltage
lateral DMOS structures in an epi-Iayer dimensioned for low voltage bipolar linear elements. Thus
1/6
145
APPLICATION NOTE
it is possible to mix on the same die very dense
in switch mode applications. In fact DMOS, as a reCMOS logic, high precision bipolar linear circuits,
sult of the way by which it is realized, is almost a
symmetrical bidirectional device. That is, itcan opervery efficient DMOS power devices and high voltate with the electrical 1- V characteristic shown in the
age lateral DMOS structures.
3rd quadrant of fig. 2 ; that is, as a controlled resisIn this way the constraints which limit the complextor of value decreasing inversely with the gate
ity of signal processing circuits that can be intesource voltage applied to the power to which it is asgrated economically on a high chip are greatly
sociated, up to a minimum equal to the RDs(oN) of
reduced.
the device itself, shunted by the body-drain diode inThe active structures available in Multipower BCD
trinsic to the structure that limits the negative excurtechnology are represented in fig. 1.
sion of VDS. Of the devices represented in fig. 1 the
Within the vertical DMOS is indicated an intrinsic
table 1 lists the electrical characteristics.
diode that can operate as a fast free-wheeling diode
Table 1 : Devices in Multipower BCD Technology.
·
··
Vertical DMOS
Lateral DMOS
P-channel with Drain Extension
Bipolar NPN
Bipolar PNP
C-MOS Nand P-channel
BV DSS
BV DSS
BVDSS
LV cEo
LVcEO
BVDSS
Figure 2 : I-V Characteristic of DMOS N-channel
Power Device.
> 60 V
> 100 V
> 85 V
> 20 V
> 20 V
> 20 V
VTH" 3 V
VTH " 3 V
VTH" 3 V
B : 35
B : 20
VTH " 3 V
IT> 1 GHz
IT> 800 MHz
IT> 200 MHz
IT> 300 MHz
IT> 7 MHz
The system diagram representing the internal function blocks and external components (outside the
dashed line) is shown in fig. 3.
The integrated circuit has 3 Inputs: Enable, Input 1,
Input 2. When Enable is "low" all power devices are
off ; when it is "high" their conduction state is controlled by the logic signals Input 1 and Input 2 that
drive independently a single branch of the. full
bridge. When Input 1 (Input 2) is "high" DMOS 1
(DMOS 1') is "on" and DMOS 2 (DMOS 2') is "off",
when is "low" DMOS 1 (DMOS 1') is "off" and DMOS
2 (DMOS 2') is "on".
A thermal protection circuit has been included that
will disable the device if the junction temperature
reaches 150 "C. When the thermal protection is
removed the device restarts under the control of the
Input and Enable signals.
ON-OFF SYNCHRONIZATION CIRCUIT
THE L6202 & L6203 H-BRIDGE DRIVERS
Using this technology a H-bridge IC has been realized which accepts TIL or C-MOS compatible signals and is suitable for high efficiency, high
frequency switching control of DC and stepping
motor. The power stage consists of four DMOS Nchannel transistors with RDs(oN) '" 0.3 Q .
When this device is supplied with the maximum voltage of 60V it can deliver a DC current of 1 .5A in a
standard DIP.16 (L6202) and up to 5A in a MULTIWATI package (L6203).
The device can also operate with a peak current of
8A for a time interval essentially determined by the
time constant of heat propagation ( < 200ms).
2/6
146
ON-OFF synchronization of the power devices located on the same leg of the bridge must prevent
simultaneous conduction, with obvious advantages
in terms of power dissipation and of spurious signals
on the ground and on sensing resistors.
Because of the very short turn-on, turn-off times
characteristic of POWER MOS devices a dead time
(time in which all power transistors are "off") of 40
ns is sufficient to prevent rail-to-rail shorts. The circuit that provides this time interval is shown in fig. 4
with the voltage waveforms that explain how it
works. Let us suppose Enable = "high". Because of
the delay times introduced by INV1 and INV2, V2
and V3 are two waveforms contained one in the
APPLICATION NOTE
Figure 3 : L6202-6203 Block Diagram.
OUT 1 OUTl
CeOOT 1
ENABLEr-~____'-~
5-540'
Figure 4 : A Schematic Representation of ON-OFF Synchronism Circuit.
~
V
V
V
t
1
2
I
•
t
I
..
t
3
---+1
/+--t'~
•
dead limp
5- 935311
3/6
147
APPLICATION NOTE
other and of polarity suitable to assure that the turnon of a power transistor happens only after the turnoff of the other. The gate voltages V5 and V6 of DM1
and DM2 are represented in fig. 5. In fig. 3 we can
see also the modality of operation of the Enable signal, charge pump and bootstrap circuits.
Figure 5 : POWER MOS Gate Voltage Waveforms.
Concerning POWER MOS driving, it must be noted
that it is necessary to assure to all DMOS N-channel a gate-source voltage of about 1OV to guarantee full conduction of the POWER MOS itself. While
there are no particular problems for driving the lower
POWER MOS device (its terminals is referred to
ground) for the upper one it is necessary to provide
a gate voltage higher than the positive supply because it has the drain connected to the positive supply itself.
This is obtained using a system that combines a
charge pump circuit, that assures DC operation,
with a bootstrapping technique suitable to provide
high switching frequencies. The circuit that satisfies
to all these requirements is represented in the schematic diagram of fig. 6.
In the description of this circuit we can assume that
CSOOT is absent and IN commutes from the "Iow" to
the "high" level.
Figure 6 : Schematic Representation of Charge PUMP and BOOSTRAP Circuit used to Drive the Gate of
the Upper DMOS Device.
In this condition, by means of D1, the circuit charges immediately the DMOS1 gate capacitance to Vs
while the charge pump, activated by the signals IN
= "Iow", as it can be seen in fig. 7, must supply only
a voltage of about 1OV.
In the switching operation it will be CSOOT that guar-
416
148
antees a faster turn-on of the upper POWER MOS
and consequently high commutation frequencies.
In fact during the period in which DMOS2 is "on"
CSOOT is charged to a voltage of about 12V.
When Vout raises because DMOS2 is disactivated
D2 and D1 became "off" while D3, that remains "on"
APPLICATION NOTE
connects the gate circuit to CSOOT that raises higher
than Vs and makes DMOS1 full "on" in a very short
time interval (20 ns).
It must be noted that the switch M4 in the fig. 6 circuit, driven by a complementary phase respect to
M3 disconnects D4, D5 and D6 from 12 V when M5
goes "on" to assure the "turn-off" of DMOS1.
Figure 7 : Charge PUMP Abilitation Signal and
Gate Voltage of DMOS Upper Device.
Consider the typical Darlington power stage frequently used in integrated circuit and a DMOS
power stages both represented in fig. S.Neglecting
the power dissipation in the driving section, in static
conditions, the total dissipation of the two stages
when they are "on" is in the case (a) :
Pd(a)
= (VCESAT1 + VSE2)
X
IL
and in the case (b) :
Pd(b) = ROS(ON) x IL2
where IL is the load current.
Because the saturation loss of a power DMOS transistor can be reduced by increasing the silicon area
it is possible to satisfy the condition
ROS-ON x IL< (VCESAT1 + VSE2)
and then to obtain lower dissipation.
Conceming to the driving section, an other essential difference must be emphaisised.
While in case (a) during the time in which the power
is "ON" it is necessary to supply a current for maintaining 01 saturated, in the case (b) power is dissipated only during the commutation of the gate
Voltage.
Figure 8 : Darlington Bipolar and DMOS Power
Stages.
LOAD
(a)
5-9355
PERFORMANCE
One of the most important features is the very high
efficiency achieved.
To appreciate the benefits of low power dissipation,
and consequently of high efficiency, of a circuit realized in DMOS technology we must refer to the equivalent bipolar solution and also consider separate
DC and AC operation.
About AC operation, it must be noted that the greatest advantage, always in terms of power dissipation, is due to the inherently fast turn-on, turn-off
times of power MOS devices. In fact, if we suppose
that the load is of inductive type and that the current
waveform is triangular on the voltage commutation
of the output, the total power dissipation is :
Pd
= Vs IL TCOM. fSWITCH
where: Vs = Supply voltage, IL = Peak load current,
T COM. = TTURN-ON = TTURN-OFF,
fSWITCH = Chopper frequency.
Because TCOM. in DMOS case is ~ than in bipolar
case at a fixed frequency we have a lower dissipation or at fixed dissipation we can tolerate higher
switching frequency.
Considering all these aspects, with a power device
consisting of about 2200 cells we have realized
DMOS power devices characterized by ROS(ON)
0.3 Q and by switching times tr, tf of 50 ns. Other
characteristics of the device when is configured as
shown in fig. 9 are listed in table 2.
Fig. 10 shows the supply current with no load, vs.
switching frequency.
5/6
149
APPLICATION NOTE
Figure 9.
v
s
5-9357
Table 2 : Main Features of L6202/6203.
60 V
Vs (maximum supply voltage)
IL (maximum output current)
1.5 A DIP.16
5 A MULTIWATT Package
90 % {I L
= 1.5 A
fChopper = 50 KHz
1.5 W Vs
= 54 V
100 ns
Efficiency
Power Dissipation
td (turn-on, turn-off propagation delay)
Figure 10.
20
15
10
-4~------~------+-------4-------4-------4---~f(KHz)
o
50
100
150
200
250
5-9356
6/6
150
APPLICATION NOTE
STEPPER MOTOR DRIVING
By H. SAX
Dedicated integrated circuits have dramatically simplified stepper motor driving. To apply these ICs designers need little specific knowledge of motor driving techniques, but an under-standing of the basics will help
in finding the best solution. This note explains the basics of stepper motor driving and describes the drive
techniques used today.
From a circuit designer's point of view stepper motors can be divided into two basic types : unipolar
and bipolar.
Figure 2 : ICs for Unipolar and Bipolar Driving.
UNIPOLAR
A stepper motor moves one step when the direction
of current flow in the field coil(s) changes, reversing
the magnetic field of the stator poles. The difference
between unipolar and bipolar motors lies in the may
that this reversal is achieved (figure 1) :
Figure 1a :BIPOLAR - with One Field Coil and
Two Chargeover Switches That are
Switched in the Opposite Direction.
Figure 1 b : UNIPOLAR - with Two Separate Field
Coils and are Chargeover Switch.
a)
~
~
11
BIPOLAR
vss
vs
f-J +~s~
BIPOLAR
~
b)
5-93GB
AN235/0788
1/16
151
APPLICATION NOTE
The advantage of the bipolar circuit is that there is
only one winding, with a good bulk factor (low winding resistance). The main disapuantages are the
two changeover switches because in this case more
semiconductors are needed.
The unipolar circuit needs only one changeover
switch. Its enormous disadvantage is, however, that
a double bifilar winding is required. This means that
at a specific bulk factor the wire is thinner and the
resistance is much higher. We will discuss later the
problems involved.
Unipolar motors are still popular today because the
drive circuit appears to be simpler when implemented with discrete devices. However with the
integrated circuits available today bipolar motors
can be driver with no more components than the unipolar motors. Figure 2 compares integrated unipolar and bipolar devices.
CONSTANT CURRENT DRIVING
In order to keep the motor's power loss within a reasonable limit, the current in the windings must be
controlled.
A simple and popular solution is to give only as much
voltage as needed, utilizing the resistance (RL) of
the winding to limit the current (fig. 4a). A more complicated but also more efficient and precise solution
is the inclusion of a current generator (fig. 4b), to
achieve independence from the winding resistance.
The supply voltage in Fig. 4b has to be higher than
the one in Fig. 4a. A comparison between both circuits in the dynamic load/working order shows
visible differences.
Figure 4 : Resistance Current Limiter (a) and Current Generator Limiting.
L
BIPOLAR PRODUCES MORE TORQUE
L
RL
L
RL
-;~
/~~--~-j~
IL=IC
Figure 5 : At High Step Frequencies the Winding
Current cannot Reach its Setting Value
because of the Continuous Direction
Change.
Figure 3 : Bipolar Motors Driver Deliver More Tor-
-V
..
rt~"'__
>b--t --
TORQUE
'L
BIPOLAR
m
RL
IL=V/RL
If a higher torque is not required, one may either reduce the motor size or the power loss.
que than Unipolars.
L
~C:J
The torque of the stepper motor is proportional to
the magnetic field intensity of the stator windings. It
may be increased only by adding more windings or
by increasing the current.
A natural limit against any current increase is the
danger of saturating the iron core. Though this is of
minimal importance. Much more important is the
maximum temperature rise of the motor, due to the
power loss in the stator windings. This shows one
advantage of the bipolar circuit, which, compared to
unipolar systems, has only half of the copper resistance because of the double cross section of the
wire. The winding current may be increased by the
factor --12 and this produces a direct proportional affect on the torque. At their power .Ioss limit bipolar
motors thus deliver about 40 % more torque (fig. 3)
than unipolar motors built on the same frame.
,RL
-
.
{I-U_N_I_P_OL_A_R----..
-;L
8 ---
A
B
-
----.. log
FREQUENCY
SAX3
2/16
152
-'5 - 9373
APPLICATION NOTE
It has already been mentioned that this power of the
motor is, among others, proportional to the winding
current.
In the dynamic working order a stepper motor
changes poles of the winding current in the same
stator winding after two steps. The speed with which
the current changes its direction in the form of an
exponential function depends on the specified inductance, the coil resistance and on the voltage. Fig.
5a shows that at a low step rate the winding current
IL reaches its nominal value VL/RL before the direction is changed. However, if the poles of the stator
windings are changed more often, which corresponds to a high step frequency, the current no
longer reaches its saturating value because of the
limited change time; the power and also the torque
diminish clearly at increasing number of revolutions
(fig. 5).
fig. 8. The phase winding is switched to the supply
voltage until the current, detected across Rs,
reaches the desired nominal value. At that moment
the switch, formerly connected to + Vs, changes position and shorts out the winding. In this way the current is stored, but it decays slowly because of inner
winding losses. The discharge time of the current is
determined during this phase by a monostable or
pulse oscillator. After this time one of the pole
changing switches changes back to + Vs, starting
an induction recharge and the clock-regulationcycle starts again.
Figure 6 : With a Step Current Slew, itisnota Problem to Obtain, even at High Step frequencies Sufficient Current in Windings.
v
+
,,-
MORE TORQUE AT A HIGHER NUMBER
OF REVOLUTIONS
Higher torque at faster speeds are possible if a current generator as shown in Fig. 4b is used. In this
application the supply voltage is chosen as high
possible to increase the current's rate of change.
The current generator itself limits only the phase current and becomes active only the moment in which
the coil current has reached its set nominal value.
Up to this value the current generator is in saturation and the supply voltage is applied directly to the
winding.
/
I
I
Il f---------~--------+_\
\
,
EFFICIENCY - THE DECISIVE FACTOR
,,
/
I
,,
....
-
I
I
I
Fig. 6, shows that the rate of the current increase is
now much higher than in Figure 5. Consequently at
higher step rates the desired current can be maintained in the winding for a longer time. The torque
decrease starts only at much higher speeds.
Fig. 7 shows the relation between torque and speed
in the normal graphic scheme, typical for the stepper motor. It is obvious that the power increases in
the upper torque range where it is normally needed,
as the load to be driven draws most energy from the
motor ·in this range.
- - - IL= Rl
I
s- 9374
Figure 7 : Constant Current Control of the Stepper Motor Means more Torque at High
Frequency.
TORQUE
The current generator combined with the high supply voltage guarantees that the rate of change of the
current in the coil is sufficiently high.
At the static condition or at low numbers of revolutions, however, this means that the power loss in
the cu rrent generator dramatically increases, although the motor does not deliver any more energy
in this range; the efficiency factor is extremely bad.
Help comes from a switched current regulation
using the switch-transformer principle, as shown in
3/16
153
APPLICATION NOTE
Since the only losses in this technique are the saturation loss of the switch and that of the coil resistance, the total efficiency is very high.
The average current that flows from the power supply line is less than the winding current due to the
concept of circuit inversion. In this way also the
power unit is discharged. This king of phase current
control that has to be done separately for each
motor phase leads to the best ratio between the supplied electrical and delivered mechanical energy.
POSSIBLE IMPROVEMENTS OF THE UNIPOLAR CIRCUIT
It would make no sense to apply the same principle
to a stabilized current controlled unipolar circuit, as
two more switches per phase would be necessary
for the shortening out of the windings during the free
'p~~?lld thus the number of components would
be the same as for the bipolar circuit ; and more-
over, there would be the well known torque disadvantage.
From the economic point of view a reasonable and
justifiable improvement is the ''Bi-Level-Drive''
(fig. 9). This circuit concept works with two supply
voltages; with every new step of the motor both windings are connected for a short time to a high supply
voltage. This considerably increases the current rate
of change and its behaviour corresponds more or
less to the stabilized power principle. After a predetermined the switch opens, a no a lower supply
voltage is connected to the winding thru a diode.
This kind of circuit by no means reaches the performance of the clocked stabilized power control as per
fig. 8, as the factors: distribution voltage oscillation,
B.e.m.f., thermal winding resistance, as well as the
separate coil current regulation are not considered,
but it is this circuit that makes the simple unipolar
R/L-control suitable for many fields of application.
Figure 8: With Switch Mode Current Regulation Efficiency is Increased.
/
/
I
I
ANALOG
N\A,o'VI\A1'\A:A>"Ib SW ITCHED
5-9376
4/16
154
APPLICATION NOTE
Figure 9 : At Every New Step of the Motor, it is Possible to Increase the Current Rate with a Bilevel Circuit.
~
START
VOLTAGE
STOP
VOLTAGE
5-9377
ADVANTAGES AND DISADVANTAGES OF
THE HALF-STEP
An essential advantage of a stepper motor operating at half-step conditions is its position resolution
increased by the factor 2. From a 3.6 degree motor
you achieve 1.8 degrees, which means 200 steps
per revolution.
This is not always the only reason. Often you are
forced to operate at half-step conditions in order to
avoid that operations are disturbed by the motor resonance. These may be so strong that the motor has
no more torque in certain step frequency ranges and
looses completely its position (fig. 10). This is due
to the fact that the rotor of the motor, and the changing magnetic field of the stator forms a spring-masssystem that may be stimulated to vibrate. In practice,
the load might deaden this system, but only if there
is sufficient frictional force.
t
Figure 10 :The Motor has no More Torque in Certain Step Frequency Ranges with Full
Step Driving.
TORQUE
FUll STEP
RESONANCE
ZERO
TORQUE
--log
TORQUE
HALF STEP
RESONANCE
In most cases half-step operation helps, as the
course covered by the rotor is only half as long and
the system is less stimulated.
The fact that the half-step operation is not the dominating or general solution, depends on certain disadvantages:
_ the half-step system needs twice as many
clock-pulses as the full-step system ; the
clock-frequency is twice as high as with the
full-step.
_ in the half-step position the motor has only
about half of the torque of the full-step.
--log
5-9378
For this reason many systems use the half-step
operation only if the clock-frequency of the motor is
within the resonance risk area.
The dynamic loss is higher the nearer the load moment comes to the limit torque of the motor. This effect decreases at higher numbers of revolutions.
5/16
155
APPLICATION NOTE
TORQUE LOSS COMPENSATION IN THE
HALF-STEP OPERATION
It's clear that, especially in limit situations, the torque
loss in half-step is a disadvantage. If one has to
choose the next larger motor or one with a double
resolution operating in full-step because of some insufficient torque percentages, it will greatly influence
the costs of the whole system.
Figure 11 : Half Step Driving with Shaping Allows
to Increase the Motor's Torque to
about 95 % of that of the Full Step.
TORQUE
In this case, there is an alternative solution that does
not increase the coats for the bipolar chopping stabilized current drive circuit.
The torque loss in the half-step position may be
compensated for by increasing the winding current
by the factor..)2 in the phase winding that remains
active. This is also permissible if, according to the
rnotor data sheet, the current limit has been
reached, because this limit refers always to the contemporary supply with current in both windings in
the full-step position. The factor ..)2 increase in current doubles the stray power of the active phase.
The toal dissipated power is like that of the full-step
because the non-active phase does not dissipate
power.
The resulting torque in the half-step position
amounts to about 90 % of that of the full-step, that
means dynamically more than 95 % torque compared to the pure full-step; a neglectable factor.
The only thing to avoid is stopping the motor at limit
current conditions in a half-step position because it
would be like a winding thermal phase overload concentrated in one.
The best switch-technique for the half-step phase
current increase will be explained in detail later on
Fig. 11 shows the phase current of a stepping motor
in half-step control with an without phase current increase and the pertinent curves of stap frequency
and torque.
6/16
156
5-9379
HALF
STEP
5 - 93 ao
HALF STEP
WITH SHAPING
(VT" )
APPLICATION NOTE
Figure 12 : Only Two Signals for Full Step Driving are Necessary while Four (six if three-state is needed
on the output stages) for half Step.
ILA
J
ILB
J
I~Bu······I·············I~F~
ILA
ILB
ILA
ILB
o
5- 9382
7/16
157
APPLICATION NOTE
DRIVE SIGNALS FOR THE MICRO ELECTRONIC
choose full and half-step is desired, a good logic implementation becomes quite expensive and an application specific integrated circuit would be better.
Such an application specific integrated circuit could
reduce the number of outputs required from a microprocessor from the 6 required to 3 static and dynamic control line.
A direct current motor runs by itself if you supply if
with voltage, whereas the stepping motor needs the
commutation signal in for of several separated but
linkable commands. In 95 % of the applications
today, the origin of these digital commands is a
microprocessor system.
A typical control circuit that meets all these requirements is the L297 unit (fig. 13).
'In its simplest form, a full-step control needs only
two rectangular signals in quadrature. According to
which phase is leading, the motor axis rotates clockwise or counter-clockwise, whereby the rotation
speed is proportional to the clock frequency.
Four signals control the motor in all operations:
In the half-step system the situation becomes more
complicated. The minimal two control signals
become four control signals. In some conditions as
many as six signals are needed. If the Tri-state-command forthe phase ranges without current, necessaryfor high motor speeds, may not be obtaified from
the 4 control signals. Fig. 12 shows the relationship
between the phase current diagram and the control
signal for full and half-step.
1. CLOCK:
The clock signal, giving the stepping command
2. RESET:
Puts the final level signals in a
defined start position
3. DIRECTION: Determines the sense of rotation of
the motor axis.
4. HALF/FULL: Desides whether to operate in full
or in half-step.
Another inhibit input allows the device to switch the
motor output into the Tri-state-mode in order to prevent undesired movements during undefined operating conditions, such as those that could occur
during.
Since all signals in each mode are in defined relations with each other, it is possible to generate them
using standard logic. However, if the possibility to
Figure 13 : The L297 avoids the Use of Complicated Standard Logic to Generate Both Full and Half-step
Driving Signals Together with Chopper Current Control.
y,-,
ASI
~S2
'::>
D1 to D8 = 2 A fast diodes {
VF'; 1.2 V @ i = 2A
trr,; 200 ns
8/16
158
of,GIt.
APPLICATION NOTE
SWITCH-MODE CURRENT REGULATION
The primary function of the current regulation circuit
is to supply enough current to the phase windings
of the motor, even at high step rates.
The functional blocks required for a switch mode current control are the same blocks required in switching power supplies; flip-flops, comparators; and an
oscillator are required. These blocks can easily be
included in the same Ie that generates the phase
control signals. Let us consider the implementation
of chopper current control in the L297.
The oscillator on pin 16 of the L297 resets the two
flip-flops at the start of each oscillator period. The
flip-flop outputs are then combined with the outputs
of the translator circuit to form the 6 control signals
supplied to the power bridge (L298).
When activated, by the oscillator, the current in the
winding will raise, following the UR time constant
curve, until the voltage across the sense resistor (pin
1, 15 of L298) is equal to the reference voltage input
(pin 15, L297) the comparator then sets the flip-flop,
causing the output of the L297 to change to an equiphase condition, thus effectively putting a short circuit across the phase winding. The bridge is
activated into a diagonally conductive state when
the oscillator resets the flip-flop at the start of the
next cycle.
Using a common oscillator to control both current
regulators maintains the same chopping frequency
for both, thus avoiding interference between the
two.
The functional block diagram of the L297 and the
power stage (L298) are shown in Figure 14 alone
with the operating wave forms.
An important characteristics of this circuit implementation is that, during the reset time, the flip-flops are
kept reset. The reset time can be selected by selecting the impedance of the RIC network or pin 16. In
this way, the current spike and noise across the
sense resistors that may occur during switching will
not cause a premature setting of the flip-flop. Thus
the recovery current spike of the protection diodes
can be ignored and a filter in the sense line is
avoided.
THE RIGHT PHASE CURRENT FOR
EVERY OPERATING CONDITION
The Chopper principle of the controller unit reveals
that the phase current in the motor windings is controlled by two data: the reference voltage at pin 15
of the controller and the value of the sense resistance at pins 1 and 15 of the L298, that is IL =
VREF/Rs. By changing VREF it is very easy to vary
the current within large limits. The only question is
for which purpose and at which conditions.
More phase current means more motor torque, but
also higher energy consumption.
An analysis of the torque consumption for different
periods and load position changes shows that there
is no need for different energies.
There is a high energy need during the acceleration
or break phases, whereas during continuous operation or neutral or stop position less energy has to
be supplied. A motor with its phase current continuously oriented at the load moment limit, even with
the load moment lacking, consumes needlessly energy, that is completely transformed into heat.
Therefore it is useful to resolve the phase current in
at least two levels controllable from the processor.
Fig. 18 shows a minimal configuration with two resistance and one small signal transistor as changeover switch for the reference input. With another
resistance and transistor it is possible to resolve 2
Bits and consequently 4 levels. That is sufficient for
all imaginable causes.
Fig. 16 shows a optimal phase current diagram during a positioning operation.
9/16
159
APPLICATION NOTE
Figure 14 : Two ICs and very Few External Components Provide Complete Microprocessor to Bipolar Step-
per Motor Interface.
I
J
-
I
~
- - - - -:..- - - - - - - - ----
l_l ______ ~ _____
n
-c __
CONTROL A
CONTROL B
5-9383
10/16
160
APPLICATION NOTE
Figure 15: Because of the Set-dominant Latch Inside the L297 it is Possible to Hide Current Spikes and
Noise Across the Sense Resistors thus Avoiding External Filters.
CLOCK
L
---.U..----
ur---:
' 'l--ti~~:i"- t
J.,
Figure 16: More Energy is needed During The Acceleration and break Phases Compared the Continuous
Operation, Neutral or Stop Position.
SPEED
,'A
,
I
,
I
,
,DECELER.,
IACCELER.,
I
,6
I
TRANSPORT
J
STOP
STOP
5- 9 J 66
11/16
161
APPLICATION NOTE
HIGH MOTOR CLOCK RESETS IN THE
HALF-STEP SYSTEM
phases. The current diagram is not neat, the half
step is not carried out correctly (fig. 17 center).
In the half-step position one of the motor phases has
to be without current. If the motor moves from a fullstep position into a half-step position, this means
that one motor winding has to be completely discharged. From the logic diagram this means for the
high level bridge an equivalent status of the input
signals AlB, for example in the HIGH-status. For the
coil this means short circuit (fig. 17 up) and consequentlya low reduction of the current. In case of high
half-step speeds the short circuit discharge time
constant of the phase winding is not sufficient to discharge the current during the short half-step
For this reason the L297 controller-unit generates
an inhibit-command for each phase bridge, that
switches the specific bridge output in the half-step
position into Tri-state. In this way the coil can start
swinging freely over the external recovery diodes
and discharge quickly. The current decrease rate of
change corresponds more or less to the increase
rate of change (fig. 17 below).
In case of full-step operation both inhibit-outputs of
the controller (pin 5 and 8) remain in the HIGHstatus.
Figure 17 :The Inhibit Signal Turns Off Immediately the Output Stages Allowing thus a Faster Current
Decay (mandatory with half-step operation).
+
+
IL
+
VS HS
VS
HS VS
T
+
T
5- 9387
12/16
162
APPLICATION NOTE
Figure 18 : With This Configuration it is Possible to Obtain Half-step with Shaping Operation and Therefore More Torque.
I1
A
5
L297
CONTROLLER
8
15
REF
REF
1NH.1
6
B
C L298
1NH.2 11
12
0
5·gJ8B
MORE TORQUE IN THE HALF-STEP POSITION
A topic that has already been discussed in detail. So
we will limit our considerations on how it is carried
out, in fact quite simply because of the reference
voltage controlled phase current regulation.
With the help of the inhibit-signals at outputs 5 and
8 of the controller, which are alternatively active only
when the half-step control is programmed, the reference voltage is increased by the factor 1.41 with
a very simple additional wiring (fig. 18), as soon as
one of the two inhibit-signals switches LOW. This increases the current in the active motorphase proportionally to the reference voltage and
compensates the torque loss in this position. Fig. 19
shows clearly that the diagram of the phase current
is almost sinusoidal, in principle the ideal form of the
current graph.
To sum up we may say that this half-step version offers most advantages. The motor works with poor
resonance and a double position resolution at a
torque, that is almost the same as that of the fullstep.
BETTER GLIDING THAN STEPPING
If a stepper motor is supposed to work almost gliding and not step by step, the form of the phase current diagram has to be sinusoidal.
The advantages are very important:
_ no more phenomena of resonance
_ drastic noise reduction
_ connected gearings and loads are treated
with care
_ the position resolution may be increased further.
However, the use of the L297 controller-unit described until now is no longer possible of the more
semplicated form of the phase current diagram the
Controller may become simpler in its functions.
Fig. 20 shows us an example with the L6505 unit.
This IC contains nothing more than the clocked
phase current regulation which works according to
the same principle as L297. The four control signals
emitting continuously a full-step program are now
generated directly by the microprocessor. In order
to obtain a sinusoidal phase current course the reference voltage inputs of the Controller are modulated with sinusoidal half-waves.
The microprocessor that controls the direction of the
current phase with the control signals also generates the two analog signals.
For many applications a microprocessor with dedicated digital to analog converters can be chosen.
Eliminating the need for separate OfA circuits.
About 5 bit have proved to be the most suitable suddivision of the current within one fUll-step. A higher
13/16
163
APPLICATION NOTE
I.S" - motor in full-step will be received, as there are
several limits:
The rise rate of the torque diagram corresponding
to the twisting angle of the rotor for the 7.2" - motor
is flatter by a factor of 4 then for the original 1.S" motor. Consequently with friction or load moment,
the position error is larger (fig. 21).
For most of the commercial motors there isn't a sufficiently precise, linear relationship between a sinusoidal-current-diagram and an exact micro step
angle. The reason is a dishomogeneous magnetic
field between the rotor and the two stator fields.
Above all, problems have to be expected with motors with high pole feeling. However, there are special stepper motors in which an optimized micro step
operation has already been considered during the
construction phase.
resolution brings no measurable advantages. On
the contrary, the converter clock frequency is already very high in case of low motor revolutions and
very difficult to process by the processor-software.
It is recommended to reduce the DIA resolution at
high step frequencies.
In case of higher motor revolutions it is more convenient to operate only in full-step, since harmonic
control is no longer an advantage as the current has .
only a triangular waveform in the motor winding.
PRECISION OF THE MICRO STEP
Any desired increase of the position resolution between the full step position has its physical limits.
Those who think it is possible to resolve a 7.2"
stepper motor to I.S" with the same precision as a
Figure 19 :The Half-step with Shaping Positioning is Achieved by Simply Changing Reference Voltages.
A
INHIBIT 1
IL-_ _--IIIL-_ _ _ _ B
C
INHIBIT 2
L..-_ _
0
V~REFERENCE
}8 8
p. . . .
V
PHASE CURRENT
1.4
Tl ·
1 '='-="L.:]
I
V
5-9389
14/16
164
Ii
~
L
12
APPLICATION NOTE
Figure 20 : L6506 Unit Gives The Possibility to Modulate Separately the Two Reference Voltage Inputs in
Order to obtain a Sinusoidal Phase Current.
A
B
C
p
LOGIC
L6506
L298 N
o
r--
flP
I
I
DAC
I
t---DAC
CONTROLLER
5-9390
5- 91, 23
15/16
165
APPLICATION NOTE
Figure 21 : Better Resolution is achieved with Low Degree Motor but More torque is delivered with high
Degree Motor.
TORQUE
+
I..S"MOTOR
LOAD
TORQUE
+
ROTATION
ANGLE
TORQUE
CONCLUSIONS
The above described application examples of modern integrated circuits show that output and efficiency of stepper motors may be remarkably
increased without any excessive expense increase
like before.
16/16
166
5- 9391
Working in limit areas, where improved electronics
with optimized drive sequences allow the use of less
expensive motors, it is even possible to obtain a cost
reduction.
APPLICATION NOTE
CONSTANT-CURRENT CHOPPER DRIVE UPS
STEPPER-MOTOR PERFORMANCE
The most efficient and performant way to drive a stepper motor is to use a "chopper" drive circuit.
This note explains some basic theory then presents practical circuits based on power ICs.
PULSE WIDTH-MODULATED DRIVE IMPROVES MOTOR TORQUE AND SPEED
YET ADDS NO COMPLEXITY TO CIRCUIT
Designers opting to use a fractional-horsepower
stepper motor in applications such as computer
printers can improve the motor's efficiency and its
torque and speed characteristics by using a constant-current pulse-widt~-modulated (PWM) chopper-drive circuit. What's more, for high-power
drives, dedicated control chips and a constant-current chopper drive can be as simple to use as direct
drive.
A basic problem for a directly driven stepper is that
the motor winding's time constant (UR) causes the
current to increase slowly in the winding during each
pulsed input. It may, therefore, never reach full-rated
value, especially at high speed, or high pulsing
rates, unless the voltage (Vs) across the terminals
is high. In the simplest stepper drive (see fig. 1a),
transistor or Darlington switches sequentially activate the windings to drive the motor (see box, "Stepper motor basics").
This type of drive performs poorly because the supply voltage must be low so that the steady-state current is not excessive. As a result, the average
winding current - and hence the torque - is very low
at high drive motor speed.
Often, this problem is overcome by introducing a
series resistance, thereby increasing the overall
value by a factor of four - giving an U4R ratio - and
also by increasing the supply voltage (see fig. 1b).
This arrangement reduces the motor's time constant, which improves torque at high step rates.
However such an approach is inefficient, because
the series resistor constitutes a substantial waste of
power.
Figure 1: Common unipolar stepping drives (a) produce insufficient torque output becuase their supply
voltage must be kept low to limit current. Adding series resistance to an U4R ratio (b) and
raising the supply voltage proportionately improves torque output, especially at high step
rates.
HIGHER
VOLTAGE
L
Vs
MOTOR
WINDINGS
•
R
L/R
.sLJL
PULSED
INPUTS
}
SWITCHES
4R
3R
•
119211N468-tlf
AN468/0392
1/5
167
APPLICATION NOTE
Figure 2 : A Pulse-width-modulated, or chopper, drive overcomes most of the
problems of the simpler direct drive or
even linear constant-current drives.
only solves the UR time-constant problem but cuts
power dissipation too (see fig. 2).
A four-phase bifilar/hybrid unipolar stepper motor
could use a quad Darlington like the ULN2075B as
a chopper driver and a chip like the L6506 as a current controller (see fig. 3).
The L6506, which contains all the chopper circuitry,
is simple to use. An external RC network sets the oscillator frequency, and a voltage divider (or trimmer)
sets the reference voltages, and hence the phase
currents. Normally an oscillator frequency of over 20
KHz is chosen to avoid motor noise. The maximum
usable frequency depends on the UR time constant
of the motor.
us
MOTOR
WINDING
Control signals forthe four-phase inputs can be provided by a micro-computer chip or a simple repetitive sequence from a logic circuit. Note that the
L6506 contains just two independent chopper-controlloops ' sufficient for a four-phase unipolar stepping motor because opposing windings never
energize together.
SENSE
RESISTOR
ff92RN46B-B2
DRIVING BIPOLAR MOTORS
CONSTANT CURRENT IS BEST
Introducing a feedback loop to control the winding
current is a better solution. Linear constant-current
control is possible but is rarely used because of high
power losses in the power stage. However, a pulse:
width-modulation scheme - a chopper circuit - not
Bipolar stepper motors, preferred for their better
torque/weight ratio, however, are normally driven by
H-bridge output stages. They enable a single-polarity supply to drive each motor winding end sequentially to achieve a polarity-reversal effect on the
windings.
Figure 3 : Asimple chopper drive for a unipolar stepping motor, can be assembled with just two chips:
a Quad Darlington output driver IC and constant-current feedback controller IC.
lBBnF VSS
us
ENABLE
~
J:
INlo-----------r1~r-~~~-O~
IN2o-----+-----r1~~~~~"-''-'-'.''+-C::J-o
VREF
2/5
168
+SV
SENSING
RESISTORS
i88nF
APPLICATION NOTE
STEPPER-MOTOR BASICS
In computer-peripheral office-equipment applications, the most popular stepper motors are permanent-magnet types with two-phase bipolar windings
or bifilar-wound unipolar windings. Stripped to the
essentials, both types consist of a permanent-magnet rotor surrounded by stator poles carrying the
windings.
A two-pole motor would have a step angle of 90 '.
However, most motors have multiple poles to reduce the step angle to a few degrees.
A bipolar permanent-magnet stepper motor has a
single winding for each phase - and the current
must be reversed to reverse the stator field. Bifilar/hybrid unipolar motors, however, have two windings wound in opposite directions for each phase, so
that the field can be reversed with a single-polarity
drive. Unipolar motors were once popular because
the drive was simpler. But with today's dual bridge
(H-bridge) ICs, it is just as easy to drive a bipolar
motor.
In the most popular drive technique - two-phase-on
- both phases are always energized. In another
method - called the wave drive - one phase is energized at a time.
A third technique combines the two sequences and
drives the motor one half-step at a time. Half-stepping is very useful because motor mechanically designed for very small step angles are much more
complex - and costly - to built. ltis more economical
to use a 1~O-step motor in half steps rather than a
200-step motor in full step.
Recently designers have started microstepping, or
driving the motor at one-quarter stepping rather or
less. This type of operation can obtain fine step control without using mechanically complex motors with
small step angles.
A two-phase bipolar motor needing up to 2Nphase
can be driven by a single IC - the L298N
dual
bridge (see fig. 4). It contains two H-bridges with all
the necessary level shifters and gates to directly interface low-level input logic signals.
As before, a complete chopper drive can be built by
adding a current-controller chip and the necessary
protective diodes, an RC network to define the oscillator frequency and a reference-voltage divider to
set the current level. Four-phase signals to the controller are provided by a controlling microcomputer
or by another dedicated controller chip - the L297
stepper-motor controller.
Figure 4 : A Dual-bridge IC provides a simple power-stage design solution for a bipolar stepper motor.
1B~."F
~I
USS
-l
J
I
•b..
1
SURGE
SUPPRESSOR DIODES
1.-rC=
~
-vc=
--l
MOTOR
WI NDINGS
IN3
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L.-fC-
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.
IN4
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3.3nF
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1192AH468-84
3/5
169
APPLICATION NOTE
ripple and is suitable four unipolar motor, whereas
inhibit chopping retums energy to the supply and is
better for bipolar motors.
Containing an internal translator circuit controlled by
step-and-direction inputs, the L297 motor controller
(see fig. 5) allows operation in three modes: twophase-on, half-step and wave-drive.
In applications such as printer-paper feed, the motor
is often at rest. Since the full torque is not usually
necessary to hold the motor in pOSition, designers
can save power by switching the current to a lower
level between runs. With an L297 or L6506 control
chip, this task can be done by simply switching the
reference input between two levels.
The normal two-phase-on mode is selected by a low
level on the halflfull input when the device has been
reset to start.
Half-step drive is selected by a high level on the
halflfull step input. To initialize the wave-drive mode,
the user disables the output stage (brings enable
low), resets the device, steps the translator one
step, brings halfifuillow, and then reenables the outputs.
Where several chopper drives are used in the same
system, they should be synchronized prevent intermodulation effects. This is done by connecting the
sync pins to one another and omitting the oscillator
RC network on all but one device.
The L297 also lets the designer select either phase
or inhibit chopping. Phase chopping provides lower
Figure 5 : controlled by step, direction, and mode inputs, the L297 stepper-motor controller chip performs some of the functions of a controlling microcomputer.
USS.5U
US~46U
199nF
b.
CW/CCW
A
STEP
HALF/FULL
RESET
CONTROL
ENABLE
SYNC
EN
B
LOGIC
C
«2A/PHASEI
EN
0
+5U
22KO
+5U
3.3nF
J:
1'1.50
4/5
170
"92RN468~B5
APPLICATION NOTE
HANDLING HIGH CURRENT
For current drives greater than 2AJphase, the two
bridges in an L298N Ie can be paralleled by connecting inputs to the corresponding outputs. However, for a more equal distribution of the load and
chip heating, driver 1 should be paralleled with driver
4, and driver 2 with driver 3. Additionally, total current should be derated by 0.5 A to allow for the maximum possible imbalance between the current in
each bridge. Thus two L298s can drive motors rated
at 3.5 AJphase.
A different configuration for microstepping stepper
motors is employed in the PBL3717 A control circuit.
It contains all of the control and power circuitry for
one phase of a motor. An H-bridge output stage can
drive motors rated at up to 1AJphase. Two of these
devices are needed to drive a two-phase bipolar
motor.
The output current level from the PBL3717 A is set
both by an analog-reference input and two logic inputs (11 and 10), which select one of three preset current levels (the fourth combination disables the
outputs stage). This feature implements the microstepping, in which several current levels are used to
obtain very small step angles for even more precise
control (but at the expense of a less regular torque).
Unlike the L297 and L6506, the PBL3717A has a
constant off-time chopper driver which is ideal for
microstepping.
5/5
171
APPLICATION NOTE
USING THE L6506 FOR CURRENT CONTROL
OF STEPPING MOTORS
by Thomas Hopkins
Chopper-type current control circuits improve the performance of motor drives. This note shows how
this can be done simply using the L6506 current controller IC.
current is sensed by monitoring the voltage across
a sense resistor (Rsense) and using a Pulse Width
Modulated control to maintain the current at the
desired value.
The L6506 is a linear integrated circuit designed to
sense and control the current in stepping motors
and other similar devices. When used in conjunction
with power stages like the L293, L298N, or L7180
the chip set forms a constant current drive for inductive loads and performs all the interface functions
from the control logic through the power stage.
An on-chip oscillator drives the dual chopper and
sets the operating frequency. An RC network on pin
1 sets the operating frequency, which is given by the
equation:
The L6506 may be used with either two phase bipolar or four phase unipolar motor configurations.
The circuit in figure 1 shows the L6506 used in conjunction with the L298N in a 2 phase bipolar stepper
motor application. The circuit in figure 2 implements
a similar 4 phase unipolar application.
f~-----
forR1>10Kn
The oscillator provides pulses to set the two flipflops, which in turn cause the outputs to activate the
power actuator. Once the outputs have been activated the current in· the load starts to increase,
limited by the inductive characteristic of the load.
CURRENT CONTROL LOGIC
In these two circuits, the L6506 is used to sense and
control the current in each of the load windings. The
..
Figure 1 : Application Circuit for Bipolar 2 Phase Stepper Motor.
11313nF
5U
=
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7
14
13
12
-
8
L6586 11
C
3
6
5U
1 I3K[ 22K
6.8nF
AN469/1090
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5
113 L298N 3
RREF
9
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13
12
11
B
6
1
1
A
7
113
15
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9
2
17
16
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18
5
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15
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I'
-
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14
I"
_.
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11!12I1H45!1 - 83
1/5
173
APPLICATION NOTE
Figure 2 : Application Circuit for Unipolar 4 Phase Stepper Motor.
18BnF USS
us
ENABLE
.-I
INlo-----------~~~
OUTl
IN2o-----~----~~~
OUT2
}-<:r..::.;:";";:~-Q-l
IN3O-----~----~~~
IN40------+--~--~~
I--o----'--(H
MOTOR
WINDINGS
I-o----~:::::J--o
+5U
SENSING
RESISTORS
When the current in the load winding reaches the
programmed peak value, the voltage across the
sense resistor (Rsense) is equal to reference voltage
input (Vref) and the corresponding comparator
resets its flip-flop. This interrupts the drive and allows the current to decay through a recirculating path
until the next oscillator pulse occurs. The peak current in each winding is programmed by selecting the
. value of the sense resisJor and Vref and is given by
the equation:
Vref
Ipeak =
(2)
Rsense
The minimum output pulse width is determined by
the pulse width of the oscillator, or other signal applied to the sync input. The internal oscillator is
designed to provide narrow pulses to the sync input
but the pulse width should be considered carefully.
In some applications it is desirable to set the pulse
width of this sync pulseto be just longer than the turn
on delay time of the actuator stage. This may be
useful in systems where the switching noise or recovery current of the catch diodes, which passes
through the sense resistor, causes the comparator
to sense a current above the peak current. By mak2/5
174
1f9211N468-B3
ing the sync pulse wide enough to hold the flip-flop
set at the time the switching transient occurs will
cause the device to ignore this false data.
When the intemal oscillator is used the pulse width
can be modified by changing the value of the capacitor on pin 1.
Increasing the capacitance will widen the pulse
width .
The L6506 may be used with either a bridge driver,
as shown in figure 1, for bipolar motors or a quad
darlington array, as shown in figure 2, for 4 phase
unipolar motors. For eigher configuration, half step
may be implemented using the 4 phase inputs with
the input waveforms shown in figure 3.
The recirculation path for the motor current is
through a catch diode for unipolar motors, or a catch
diode and one of the lower transistors of the bridge
for bipolar motors. Both of these implementations
produce a low ripple cu rrent since the voltage across
the motor during the recirculation time is much less
than the power supply voltage. Figure 4 shows the
ripple current for bipolar motor applications using
the L6506 and the L298N.
APPLICATION NOTE
Figure 3 : Input Signal for Stepper Motor Drive.
SYNCHRONIZING MULTIPLE DEVICES
Ground noise problems in multiple configurations
can be avoided by synchronizing the oscillators.
This may be done by connecting the sync pins of
each of the devices with the oscillator output of the
master device and connecting the RIC pin of the unused oscillators to ground as shown in figure 5. The
devices may be synchronized to external circuits by
applying synchronizing pulses to the sync pins. It
should be noted, however, that the input pulse sets
the minimum on time of the outputs and will therefore set a minimum output average current.
A
c
POR
FULL STEP MODE
SELECTING THE OSCILLATOR COMPONENTS
A
When selecting the values for the external components for the oscillator one of the primary considerations is the operating frequency. In addition there
is another important consideration for these components.
c
D
Figure 5 : Synchronizing Multiple Devices.
POR
HALF STEP MODE
5-9344
When implementing a half step drive, both outputs
of the L6506 will be low during the half step of one
phase. This means a very long time is required for
the current in the "off" winding to decay when driving
bipolar motors.
Ucc
R
Altern3tely, the power stage (L298N) may be inhibited to put the output in the state and achieve a
laster current decay.
Since separate Vret inputs are provided for each
channel, each of the loads may be programmed independently allowing the device to be used to implement microstepping or applications with different
peak and hold currents. In this type of application,
changing the reference voltage (Vret) will change the
load current, effectively implementing a transconductance amplifier.
Figure 4 : Ripple Current in Bipolar Motors.
RIC
L6506
asc
SYNC
MASTER
asc
---( SYNC
r
L6506
RIC
f152f1N465-Bt
SLAVE
In many applications the reverse recovery current
of the free wheeling diodes and of parasitic elements in the power stage will flow through the
sensing resistor in addition to the load current.
Also there is sometimes noise- generated in the
system when the power stage is swiched on.
3/5
175
APPLICATION NOTE
These two sources of error can fool the current
limiting stage and make it appear to operate at a
subharmonic of the desired frequency. With the
proper selection of the oscillator components this
behavior can be avoided.
The design of the L6506 is such that the flip-flops
used in the device are set dominant so that whenever the sync input is low the Q output of the flip- flop
will be high even if the reset is applied by the cOiTlparator at the same time. This characteristic of the
flip-flops can be used to make the current sensing
immune to the recovery currents and noise spikes
that occur when the power devices switch. If the
sync pulse is longer than the tum on delay time of
the power stage, as shown in figure 6, these two
sources of errors will be ignored.
Figure 6 : Load Current and Sync Pulse.
The equations for the active time of the sync pulse
(T2), the inactive time of the sync signal (T1) and the
duty cycle can also be found by looking at the figure
7 and are:
R1 Ri
(4)
T2 = 0.69C1 R1 + Ri
T1
= 0.69 R1 C1
(5)
T2
DC
(6)
= T1 + T2
By substituting equations 4 and 5 into equation 6
and solving for the value of R1 the following equations for the external components can be derived:
R1 = (
dc -
2 ) Ri
T1
C1 = 0.69 R1
(7)
(8)
Looking at equation 4 it can easily be seen that the
minimum pulse width of T2 will occurwhen the value
of Ri is at its minimum and the value of R1 at its maximum. Therefore, when evaluating equation 7 the
minimum value for Ri of 7000 (1 KO -30 %) should
be used to guarantee the required pulse width.
For a typical application using the L298, which has
a maximum tum on delay of 2.5Ils, with the L6506
consider the following operating points:
f = 20 KHz
T1 + T2 '= 50 Ils
T2 min = 31ls
From equation 6:
To select the proper values forthe oscillator components a more detailed equation for the operating frequency and duty cycle of the oscillator is required.
The required equations can be derived from the
equivalent circuit for the oscillator section shown in
figure 7.
As can be seen from figure '7, the full equation for
the operating frequency includes not only the external resistance and capacitance but the internal discharge resistor as well. The full equation for the
operating frequency is :
1
f=
4/5
176
R1 .~
0.69C1 [ R1 + ( R1 + Ri ) 1
(3)
DC =
31ls = 0.06
50llS
From equation 7:
1
R1 = ( 0.062) 700 = 10.3KO
From equation 8:
47gs
_
_
C1 - (0.69) (1 0.3K) - 6.6nF
APPLICATION NOTE
Figure 7 : Oscillator Circuit and Waveforms.
I
Rl
555
1K
Cl!!!!!
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[ RI
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L
SYNCU
OSC~
T1
1f92I1N469-(J2
5/5
177
APPLICATION NOTE
HIGH-POWER"DUAL-BRIDGE ICs
EASE STEPPER-MOTOR-DRIVE DESIGN
In addition to simplifying design problems, a family of dedicated chips improves stepper-motor drive-circuit
reliability by significantly reducing the component count.
The L293, L293E and L298N dual-bridge ICs (see
box, "inside the dual-bridge ICs") significantly reduce the problems encountered in the design of
stepper-motor drive circuitry. They can, for example,
simplify the design and increase the efficiency of
constant-current choppers. And with a single chip
replacing the transistors and predriver stages, circuit performance improves. Best of all, the devices
have applications in complex as well as basic driver
networks.
Figure 1: The Simplest Stepper-motor Drive Technique is the Basic LlR Configuration. Adding Series Resistors and Raising the Supply to Make an Ll4R Drive Improves Torque at High Steps rates but
Reduces Efficiency.
lOGIC
SUPPl Y
6V124Vj
4 ,...
IN493S
3 OUI,
ENIO. 1
20 w30
rnH
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DR
TRANSlA10ll
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BIPOLAR
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,N4935
NOTES,
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AN238/0488
IN SERIES WITH EACH WINDING AND
RAISE suPPt Y VOL TAGE TO 24V
1/7
179
APPLICATION NOTE
SIMPLEST DESIGN IS AN LlR DRIVE
The simplest motor-drive configuration (fig. 1) consists of a ~C that performs the translator function in
software (see box, "Generating switching sequences") and drives the motor through a L293 dual
bridge. Only eight external components are required ; these are diodes that protect the device's
output transistors against inductive spikes generated when a winding de-energizes.
The L293 handles 1A continuous (for higher current
INSIDE THE DUAL-BRIDGE les
The L293, L293E and L298N (figure) contain two
power-transistor bridges, predriverstages, control logic
and protection circuitry. There's a control input for each
bridge and an enable input for each half bridge; inputs
connect directly to /lGs, GMOS or TTL. The IGs integrate level shifters with a separate logic-supply pin. For
current sensing, the L293E and L298N have external
emitter connections.
A single package drives a 2-phase bipolar stepper
motor, challenging the assumption held by many that
unipolar motors are easier to drive.
use and L298N). However, if you plan to run the
motor continuously with two phases on, dissipation
will be the limiting factor.
You can improve the performance of this basic UR
drive by increasing the series resistance and raising
the supply voltage to restore the original phase current. At high speeds, torque improves, but efficiency
decreases. Normally, you increase each winding's
resistance by a factor of four through the addition of
a 3R series resistance, resulting in the U4Rdrive.
You can use a bipolar motor - simpler and less expensive than a unipolar motor - without building complex
power stages. Furthermore, you don't have ·to worry
about simultaneous conduction of a half bridge's
source and sink transistors - a basic problem with discrete-component bridge circuits. Chip design makes it
impossible for both transistors to be on at the same
time.
Designers should also discard the mistaken idea that
constant-current chopper drivers are complicated and
expensive. You can build one with two bridge IGs and
a few passive components.
Dual-bridge driver ICs reduce the parts count of bipolar stepper motors and simplify design. The
schematic of the L298N is functionally similar to those of the L293 and L293E.
'---.-_ _+--0'",
5-"132(,
Type
L293
2/7
180
10
10(PEAK)
VS
Package
1A
1.5 A
36 V
16 DIP
L293E
1A
1.5 A
36 V
20 DIP
L298N
2A
2.5 A
46 V
Multiwatt 15
Sensing Connections
One Per Half Bridge
One Per Bridge
APPLICATION NOTE
MULTIPLE SUPPLIES BOOST PERFORMANCE
You can minimize this effect by disabling a bridge
only when the winding it drives is turned off ; because the ~i!~t of an inductor equals ElL, disabling
the bridge accelerates the current decay. This action discharges the winding's stored energy through
its supply and maintains the terminal voltage E at Vs
plus two diode drops. If you were to leave the bridge
enabled, the current would flow to ground through
one diode and one transistor, and it would lower the
terminal Voltage. This scheme doesn't apply with
drives with two phases on because no winding ever
de-energizes.
A dual-level supply also improves the performance
of a basic LlR circuit. A high supply voltage yields
good torque characteristics when the motor is running. A lower-than-rated voltage provides some
holding torque when the motor is at rest, thereby
saving power when the motor is idle.
Fig. 2 shows a suitable voltage-s;yitch circuit. Rx
sets the holding current, which can be low because
a permanent magnet or hybrid stepper motor provides some holding torque at zero current. However,
make certain the L293's motor-supply input never
goes below the logic-supply voltage. While there's
no danger of damaging the device, it's imposssible
to drive the output transistors correctly under such
conditions.
Figure 2 : Switching the Supply to a Lower Voltage when the Motor is Idle Saves Current without Compromising Driving
Power.
The dual bridge's enable inputs offer a means of extending the chip's flexibility. For example, you can
connect them directly to the logic supply - no resistors are needed - to enable the chip permanently.
As an alternative, use the enable inputs to disable
the motor during the power-on reset sequence.
24V
lN493!.
lN4935
In wave-drive and half-step modes, use the enable
inputs to increase torque at high speeds. When a
winding de-energizes, flux collapse is a function of
the current-decay rate. During this decay, the deenergized winding opposes the efforts of the next
winding in sequence, partially cancelling the torque.
v,
5-9335
Figure 3: Maintaining a Constant-average Phase Current this Fixed-ripple Chopper Provides Improved
Performance and Efficiency VREF Controls the Phase Current.
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3/7
181
APPLICATION NOTE
GENERATING SWITCHING SEQUENCES
In addition to selecting a motor and determining powerstage design, you must also decide how to generate
the switching sequences that step the motor. Programming a !lC or using a special piece of hardware
called a transistor accomplishes this task.
Software translation is more economical, and it is the
first choice for large-volume products. Fig. A shows a
basic step procedure (a) that you can integrate into a
routine (b) ; the routine executes a clockwise rotation
of N steps at a fixed rate. The step rate is defined by a
software loop, but you can also use programmed timer
interrupts.
Fig. A: A!lC can generate the phase sequence (a)
for a stepper motor. A routine (b). expands a
single-step routine into are that executes a
move of N steps.
a)
A simpler approach uses the software equivalent of a
shift register. For example, you can load a 99 (hex) into
a register and take the phases from bits 0 to 3. A Rotate Left instruction yields a clockwise step; a Rotate
Right instruction causes a counterclockwise move.
When software translation ties up your !lC, lighten the
load by adding a hardware translator. In applications
involving unidirectional motors, this logic circuit (fig. B)
requires only one pulse for each step; you'll also need
a direction signal (b) if your motor rotates in both directions. By adding a 7408 to a 2-phase translator, you
can satisfy a wave-drive application (c), while the addition of two OR gates provides fast turn-off in wave-drive
mode.
Fig. B : Built a simple 2-phase hardware translator
using a dual flip-flop, for single (a) or bidirectional (b) rotation. Add some extra ICs for
wave-drive· signals (c) and to provide fast
turn-off (d).
a)
(J)
5V-.lVV-+++--,
S-9327
5--9329
L -_ _ _---J
b)
5V
b)
RESETo-~~+----~-~
5--9330
c)
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5-9328
7408
~=Q--oB'
~=Q--oD'
5-9331
4/7
182
..
.v, 7432
~
B,~ENA
5-9332
APPLICATION NOTE
Often a fl C controls the translator, setting the direction
line and providing a pulse for each step. Software is
thus simplified, and if you use a programmed interrupt
scheme, the flC is free to handle other tasks. Fig. C describes an absolute-positioning routine for a step with
a direction-control translator; Fig. 0 outlines how programmed timer interrupts are used to relieve the
burden on the C.
Two special cases call for hardware translation. The
first is in a system for which you have already designed
in control circuitry to provide step and direction signals.
The second case involves single-quantity and smallrun applications, in which the cost of a few ICs is a small
price to pay for simplified software.
Noles: Enter with desired
position current position in
register or memory location.
Figure C : For use with a Hardware Translator this a Absolute-positioning
Routine Sets the Direction Line
and Sends the Appropriate
Number of Step Pulses.
YES
NO
5-9333
Figure D :To Seta motor Step Rate, used
• COMPLETE
TIMER
Programmed Timer Interrupts
in Place of Software Timing
Loops.
INTERRUPT
SERVICE
5-9334
5/7
183
APPLICATION NOTE
CHOPPER CIRCUIT OFFERS MORE ENHANCEMENTS
Vref adjusts the lower current limit, while the comparator's hysteresis sets the ripple, and hence the
peak current. Although a divider establishes the
value of Vref in this case, you can employ the dualsupply design approach and switch Vref to a lower
value when the motor is idle. In addition, use of a
D/A converter establishes Vref for micro-stepping
applications. This drive circuit, with its fixed-ripple
current characteristics, is well suited for such service.
Adding a chopper circuit to maintain a constantaverage phase current improves performance and
efficiency. Fig. 3 shown a simple constant-current
drive that employs a dual bridge, dual comparator
and a few passive components. This circuit requires
an L293E, because this dual-bridge IC offers access
to the lower emitter connections, thus letting you insert current-sensing resistors.
Operation of this fixed-ripple chopper drive is
straightforward. When the IlC or translator activates
a bridge, the increasing load current raises the voltage across the sensing resistor until it equals the
comparator's reference voltage. The comparator
then switches, clamping the translator signals
through the diodes to deactivate the bridge. As the
current decays, the voltage across the sensing resistor decreases until it equals the comparator's
lower threshold. The comparator switches again,
allowing the IlC or translator to activate a bridge and
restart the cycle. As long as the translator drives the
bridge, this sequence repeats to provide a constantaverage phase current with fixed ripple.
FIXED-FREQUENCY CHOPPER IS MOTOR
INDEPENDENT
Fig. 3's drive has some disadvantages. First, the
chopper frequency depends on motor characteristics, and these parameters vary from unit to unit. In
addition, it's impossible to synchronize the choppers, and this shortcoming can cause trouble on the
ground plane.
Using a flip flop/comparator arrangement (fig. 4) to
develop a fixed-frequency chopper overcomes
these problems. In this circuit, the NE555 timer
generates negative pulses that reset the flip flops to
enable the phase-control signals from the transla-
Figure 4 : This Fixed-frequency Constant-current Chopper Driver Enables the Synchronization of Several
Drives, thus Minimizing Potential Ground-plane Problems.
5V
'N,
,
IN,
7
7408
3611
'IM MR851
EN,
2·PHASE
BIPOLAR
STEPPER
IN,
1.
>N.
12
MOTOR
">-_+'!:!.j..C.:.~~+---4-4-~12AIPHASEI
EN.
4)( MRrlS1
.....
5-9337
6/7
184
APPLICATION NOTE
Figure 5 : A Special Translator-chopper Control Circuit cuts the Drivers Components Count to the Minimum.
,v
,
A
51 EPO-Fe---+j
HAlF;rLiu o - F - - - - I
RESE T o - F - - - - + j
.'
PttA~J~
IIIP()l All
<; I r 1'1'1
MOIOI!
I~
CONIROLo-F--------_
ENAel£o-b--------~1
)JnF
~,
'",
Q
....
I
'"""'--,.,-_ _ _ _ _ _ _ _ _- - '
1.. ,
V~fI
~-9jJH
tor. If these signals are set to energize a winding,
the current in that winding rises until the voltage
across the sensing resistor switches the comparator, thus setting the flip flop. This disables the phase
signals and deactivates the bridge. Current in the
winding falls until the next clock pulse resets the flip
flop, and the sequence repeats to maintain a constant current.
CONTROLLER IC REDUCES
COMPONENT COUNT
If you're using a hardware translation and constantcurrent choppers, you can further reduce the component count by using a controller chip such as the
L297 - a 20-pin DIP that houses a translator and a
dual fixed-frequency chopper circuit. Under the control of step and direction inputs, the L297 generates
normal, wave-drive and half-step sequences.
As shown in fig. 5, the controller connects directly to
adual bridge. External component requirements are
minimal: and RC network to set the chopper frequency and a resistive divider to establish the comparator reference voltage (Vret).
To accommodate motors with a phase current as great
as 3.5 A, replace the single dual-bridge IC with two devices configured in parallel (input to input, enable to enable, etc) to form a single bridge. It's extremely
important that you pair the half bridges - 1 with 4 and
2 with 3 - to ensure optimum current sharing.
Reprinted from EON. 11/24/83
© 1986 Cahners Publishing Company Division
of Reed Publishing USA.
7/7
185
APPLICATION NOTE
THE L297 STEPPER MOTOR CONTROLLER
The L297 integrates all the control circuitry required to control bipolar and unipolar stepper motors. Used
with a dual bridge driver such as the L298N forms a complete microprocessor-to-bipolar stepper motor
interface. Unipolar stepper motor can be driven with an L297 plus a quad darlington array. This note describes the operation of the circuit and shows how it is used.
L297 and a special version called L297 A. The
L297A incorporates a step pulse doubler and is designed specifically for floppy-disk head positioning
applications.
The L297 Stepper Motor Controller is primarily intended for use with an L298N or L293E bridge driver
in stepper motor driving applications.
It receives control signals from the system's controller, usually a microcomputer chip, and provides all
the necessary drive signals for the power stage. Additionally, it includes two PWM chopper circuits to
regulate the current in the motor windings.
ADVANTAGES
The L297 + driver combination has many advantages : very few components are required (so assembly costs are low, reliability high and little space
required), software development is simplified and
the burden on the micro is reduced. Further, the
choice of a two-chip approach gives a high degree
of flexibility-the L298N can be used on its own for DC
motors and the L297 can be used with any power
stage, including discrete power devices (it provides
20mA drive for this purpose).
With a suitable power actuator the L297 drives two
phase bipolar permanent magnet motors, four
phase unipolar permanent magnet motors and four
phase variable reluctance motors. Moreover, it
handles normal, wave drive and half step drive
modes. (This is all explained in the section "Stepper
Motor Basics").
Two versions of the device are available: the regular
Figure 1 : In this typical configuration an L297 stepper motor controller and L298 dual bridge driver combine to form a complete microprocessor to bipolar stepper motor interface.
~~
HALFJFUll '::.rEP
MCU
r
CHOPPER
RATE
I
_____
~EA
PHA.5E C
ENABLE
PHASE 0,
__H.!l~E____
L297
-
i
PHASE B
DIRECTION.
C~~P!E_R _Me~_
rr'"
STEPPER
MOTOR
L298
WINDINGS
!litHBIY 1
INHIBIT 2
~----SENSE I
5EN">£2
1
'--
'-
CURRENT
5V
SENSE
RESISTORS
LOAD
'--
CURRENT
PROGRA ....
5_5936
AN470/0392
1117
187
APPLICATION NOTE
For bipolar motors with winding currents upto 2A the
L297 should be used with the L298N ; for winding
currents up to 1 A the L293E is recommended (the
L293 will also be useful if the chopper isn't needed).
Higher currents are obtained with power transistors
or darlingtons and for unipolar motors a darlington
array such as the ULN20758 is suggested. The
block diagram, figure 1, shows a typical system.
Applications of the L297 can be fou nd almost everywhere ... printers (carriage position, daisy position,
paper feed, ribbon feed), typewriters, plotters, numerically controlled machines, robots, floppy disk
drives, electronic sewing machines, cash registers,
photocopiers, telex machines, electronic carburetos, telecopiers, photographic equipment,
paper tape readers, optical character recognisers,
electric valves and so on.
The L297 is made with SGS' analog/digital compatible h technology (like Zodiac) and is assembled in a 20-pin plastic DIP. A 5V supply is used and
all signal lines are TIUCMOS compatible or open
collector transistors. High density is one of the key
features of the technology so the L297 die is very
compact.
THE L298N AND L293E
Since the L297 is normally used with an L298N or
L293E bridge driver a brief review of these devices'
will make the rest of this note easier to follow.
The L298N and L293E contain two bridge 'driver
stages, each controlled by two TIL-level logic inputs
and a TIL-level enable input. In addition, the emitter
connections of the lower transistors are brought out
to external terminals to allow the connection of current sensing resistors (figure 2).
For the L298N SGS' innovative ion-implanted high
voltage/high current technology is used, allowing it
to handle effective powers up to 160W (46V supply,
2A per bridge). A separate 5V logic supply input is
provided to reduce dissipation and to allow direct
connection to the L297 or other control logic.
In this note the pins of the L298N are labelled with
the pin names of the corresponding L297 terminals
to avoid unnecessary confusion.
The L298N is supplied in a 15-lead Multiwatt plastic
power package. It's smaller brother, the functionally
identical L293E, is packaged in a Powerdip - a copper frame DIP that uses the four center pins to conduct heat to the circuit board copper.
Figure 2 : The L298N contains two bridge drivers (four push pull stages) each controlled by two logic
inputs and an enable input. External emitter connections are provided for current sense
resistors. The L293E has external connections for all four emitters.
QU12
OUT!
OU14
OUTl
~
I
A
I
B
10
15
6
SENSE I
2/17
188
0
- --D
-INH2
INHl
5-5981
SENSEZ
APPLICATION NOTE
STEPPER MOTOR BASICS
There are two basic types of stepper motor in common use : permanent magnet and variable reluctance. Permanent magnet motors are divided into
bipolar and unipolar types.
BIPOLAR MOTORS
Simplified to the bare essentials, a bipolar permanent magnet motor consists of a rotating permanent
magnet surrounded by stator poles carrying the
windings (figure 3). Bidirectional drive current is
used and the motor is stepped by switching the
windings in sequence.
For a motor of this type there are three possible drive
sequences.
Figure 3 : Greatly simplified, a bipolar permanent
magnet stepper motor consist of a rotaring magnet surrounded by stator poles
as shown.
A
mode. Only one phase is energized at any given moment (figure 4a).
The second possibility is to energize both phases
together, so that the rotor always aligns itself between two pole positions. Called "two-phase-on" full
step, this mode is the normal drive sequence for a
bipolar motor and gives the highest torque (figure 4b).
The third option is to energize one phase, then two,
then one, etc., so that the motor moves in half step
increments. This sequence, known as half step
mode, halves the effective step angle of the motor
but gives a less regular torque (figure 4c).
For rotation in the opposite direction (counter-clockwise) the same three sequences are used, except
of course that the order is reserved.
As shown in these diagrams the motor would have
a step angle of 90 Real motors have multiple poles
to reduce the step angle to a few degrees but the
number of windings and the drive sequences are unchanged. A typical bipolar stepper motor is shown
in figure 5.
0
•
UNIPOLAR MOTORS
A unipolar permanent magnet motor is identical to
the bipolar machine described above except that bifilar windings are used to reverse the stator flux,
rather than bidirectional drive (figure 6).
1111111 ,-r--- c
D-+-~III
5 _S937
B
The first is to energize the windings in the sequence
AS/CD/SNDC (SA means thatthe winding AS is energized but in the opposite sense). This sequence
is known as "one phase on" full step or wave drive
This motor is driven in exactly the same way as a bipolar motor except that the bridge drivers are replaced by simple unipolar stages - four darlingtons
or a quad darlington array. Clearly, unipolar motors
are more expensive because thay have twice as
many windings. Moreover, unipolar motors give less
torque for a given motor size because the windings
are made with thinner wire. In the past unipolar motors were attractive to designers because they simplify the driver stage. Now that monolithic push pull
drivers like the L298N are available bipolar motors
are becoming more popular.
All permanent magnet motors suffer from the
counter EMF generated by the rotor, which limits the
rotation speed. When very high slewing speeds are
necessary a variable reluctance motor is used.
3/17
189
APPLICATION NOTE
Figure 4 : The three drive sequences for a two phase bipolar stepper motor. Clockwise rotation is shown.
Figure 4a : Wave drive (one phase on).
A-
{~~.e/'
o
~
0
B+
B-
5-5952
Figure 4b : Two phase on drive.
B-
B.
B.
A+
AO
B-
Figure 4c : Half step drive.
A+
o&.~°
owe
B-
~
~e
B-
A-
~+ A+
Dy
c
BO
D~-e
B+
A+
+Jt:\~e
B+
4/17
190
B+
B-
APPLICATION NOTE
Figure 5 : A real motor. Multiple poles are normally employed to reduce the step angle to
a practical value. The principle of operation and drive sequences remain the
same.
phase-on is AC/CB/BO/OA and the half step sequence is NAC/C/BC/B/BO/O/OA. Note that the
step angle for the motor shown above is 15 ., not 45 •.
As before, pratical motors normally employ multiple
poles to give a much smaller step angle. This does
not. however, affect the principle of operation of the
drive sequences.
Figure 7 : A variable reluctance motor has a soft
iron rotor with fewer poles than the stator. The step angle is 15 • for this motor.
PM
STATOR A
A
c
STATOR
Figure 6 : A unipolar PM motor uses bifilar windings to reverse the flux in each phase.
A
.D
I
. I
GENERATING THE PHASE SEQUENCES
The heart of the L297 block diagram, figure 8, is a
block called the translator which generates suitable
phase sequences for half step, one-phase-on full
step and two-phase-on full step operation. This
block is controlled by two mode inputs - direction
(CWI CCW) and HALFI FULL - and a step clock
which advances the translator from one step to the
next.
Four outputs are provided by the translator for subsequent processing by the output logic block which
implements the inhibit and chopper functions.
VARIABLE RELUCTANCE MOTORS
A variable reluctance motor has a non-magnetized
soft iron rotor with fewer poles than the stator (figure 7). Unipolar drive is used and the motor is
stepped by energizing stator pole pairs to align the
rotor with the pole pieces of the energized winding.
Once again three different phase sequences can be
used. The wave drive sequence is NC/B/O ; two-
Internally the translator consists of a 3-bit counter
plus some combinational logic which generates a
basic eight-step gray code sequence as shown in
figure 9. All three drive sequences can be generated
easily from this master sequence. This state sequence corresponds directly to half step mode, selected by a high level on the HALFI FULL input.
5/17
191
APPLICATION NOTE
The output waveforms for this sequence are shown
in figure 10.
Note that two other signals, INH1 and INH2 are
generated in this sequence. The purpose of these
signals is explained a little further on.
The full step modes are both obtained by skipping
alternate states in the eight-step sequence. What
happens is that the step clock bypasses the first
stage of the 3-bit counter in the translator. The least
significant bit at this counter is not affected there-
fore the sequence generated depends on the state
of the translator when full step mode is selected (the
HALF/ FULL input brought low).
If full step mode is selected when the translator is at
any odd-numbered state we get the two-phase-on
full step sequence shown in figure 11.
By contrast, one-phase-on full step mode is obtained by selecting full step mode when the translator is at an even-numbered state (figure 12).
Figure 8 : The L297 contains translator (phase sequence generator), a dual PWM chopper and output
control logic.
A
HALF IFULl
STEP
B
C
INH2
cr-+-----.-o-f
RESET
DIRECTION
(CW/CCW)
INHI
I------+--u ENABLE
TRANSLATOR
o--+-~"'o
0
1-------+--oCON~
Q
C
FFJ
+-----+--0 SYNC
GND
SENS 1 Vref
SENS 2
osc.
Figure 9 : The eight step master sequence of the translator. This corresponds to half step mode.
Clockwise rotation is indicated.
lD01
1000
4
0001
OlDl
[ : ]
2
I
6 0010
8
HOME 0100
6/17
192
51010
7
0110
APPLICATION NOTE
Figure 10: The output waveforms corresponding to the half step sequence. The chopper action in not
shown.
Figure 11 : State sequence and output waveforms for the two phase on sequence. INH1 and INH2
remain high throughout.
CLOCK
A
1001
3
B
---.I
-,
I
L
c
L-
D
r--
lNHI
0-------------------______________________ _
lNH2
0------------------------------------------
7/17
193
APPLICATION NOTE
Figure 12: State Sequence and Output Waveforms for Wave Drive (one phase on).
CLOCK
1000
lD~
A
.-
n
B
"OO,~' 00.
8
[2]
C
0100
0
o
n
--II
"I
n
n
IL
iNHT
INH 2
S_S8LJ
INH1 AND INH2
In half step and one-phase-on full steQ modes two
other signals are generated: INH 1 and INH2. These
are inhibit signals which are coupled to the L298N's
enable inputs and'serve to speed the current decay.
when a winding is switched off.
Since both windings are energized continuously in
two-phase-on full step mode no winding is ever
switched off and these signals are not generated.
To see what these signals do let's look at one half
of the L298N connected to the first phase of a twophase bipolar motor (figure 13). Remember that the
L298N's A and B inputs determine which transistor
in each push pull pair will be on. INH1, on the other
hand, turns off all four transistors.
Assume that A is high, B low and current flowing
through 01, 04 and the motor winding. If A is now
brought low the current would recirculate through
D2, 04 and Rs, giving a slow decay and increased
dissipation in Rs. If, on a other hand, A is brought low
and INH1 is activated, all four transistors are turned
off. The current recirculates in this case from ground
to V s via D2 and D3, giving a faster decay thus allowing faster operation of the motor. Also, since the recirculation current does not flow through Rs, a less
expensive resistor can be used.
Exactly the same thing happens with the second
winding, the other half of the L298 and the signals
C, D and INH2.
8/17
194
The INH1 and INH2 signals are generated by OR
functions:
A+ B= INH1
C+ D = INH2
However, the output logic is more complex because
inhibit lines are also used by the chopper, as we will
see further on.
OTHER SIGNALS
Two other signals are connected to the translator
block: the RESET input and the HOME output
RESET is an asynchronous reset input which restores the translator block to the home position
(state 1, ABCD = 0101). The HOME output (open
collector) signals this condition and is intended to
the ANDed with the output of a mechanical home
position sensor.
Finally, there is an ENABLE input connected to the
outQut logic. A low level on this input brings INH1,
INH2, A, B, Cand D low. This input is useful to disable the motor driver when the system is initialized.
LOAD CURRENT REGULATION
Some form of load current control is essential to obtain good speed and torque characteristics. There
are several ways in which this can be done - switching the supply between two voltages, pulse rate
modulation chopping or pulse width modulation
chopping.
APPLICATION NOTE
Figure 13: When a winding is switched off the inhibit input is activated to speed current decay. If this
were not done the current would recirculate through 02 and 04 in this example. Dissipation
in Rs is also reduced.
Vs
,--;o--l-----O B
INHI
SENSI
DRIVE
CURRENT---·-~
RECIRCULATION - - - - - ......
The L297 provides load current control in the form
of two PWM choppers, one for each phase of a bipolar motor or one for each pair of windings for a unipolar motor. (In a unipolar motor the A and B
windings are never energized together so thay can
share a chopper; the same applies to C and D).
Each chopper consists of a comparator, a flip flop
and an extemal sensing resistor. A common on chip
oscillator supplies pulses at the chopper rate to both
choppers.
Figure 14 : Each chopper circuit consists of a
comparator, flip flop and external sense
resistor. A common oscillator clocks
both circuits.
--ulJl.J
osc
FROM
In each chopper (figure.14) the flip flop is set by each
pulse' from the oscillator, enabling the output and
allowing the load current to increase. As it increases
the voltage across the sensing resistor increases,
and when this voltage reaches Vref the flip flop is
reset, disabling the output until the next oscillator
pulse arrives. The output of this circuit (the flip flop's
output) is therefore a constant rate PWM signal.
Note that Vref determines the peak load current.
o
9/17
195
APPLICATION NOTE
PHASE CHOPPING
CHOPPING
AND
INHIBIT
voltage on the winding is low (VCEsat Ql +V03) (figure
16).
Why is B pulled high, why push A low? The reason
is to avoid the current decaying through Rs. Since
the current recirculates in the upper half of the
bjdge, current only flows in. the sensing resistor
when the winding is driven. Less power is therefore
dissipated in Rs and we can get away with a cheaper
resistor.
This explain why phase chopping is not suitable for
unipolar motors: when the A winding is driven the
chopper acts on the B winding. Clearly, this is no use
at all for a variable reluctance motor and would be
slow and inefficient for a bifilar wound permanent
magnet motor.
The alternative is to tie the CONTROL ingut to
ground So that the chopper acts on INH1 and INH2.
Looking at the same example, A is high and Blow.
01 and 04 are therefore conducting and current
flows through 01, the winding, 04 and Rs, (figure 17).
The chopper can act on either the phase lines
(ABCD) or on the inhibit lines INH1 and INH2. An
input named CONTROL decides which. Inhibit
chopping is used for unipolar motors but you can
choose between phase chopping and inhibit chopping for bipolar motors. The reasons for this choice
are best explained with another example.
First let's examine the situation when the phase
lines are chopped.
As before, we are driving a two phase bipolar motor
and A is high, B low (figure 15). Current therefore
flows through 01, winding, 04 and Rs. When the
voltage across Rs reaches Vref the chopper brings
B high to switch off the winding.
The energy stored in the winding is dissipated by
current recirculating through 01 and D3. Current
decay through this path is rather slow because the
Figure 15 : Phase Chopping. In this example the current X is interrupted by activating B, giving the recirculation path Y. The alternative, de-activating A, would give the recirculation path Z, increasing
dissipation in Rs.
Vs
!
I
_-D--+-~-"'O
•
r;._._ .....I
O------------------r---~
5EN51
!I
:1
.
• i'
x-·-·-~
y------
z ...... ..
10/17
196
5-5943
B
APPLICATION NOTE
Figure 16: Phase Chopping Waveforms. The example shows AB winding energized with A positive with
respect to B. Control is high.
A
ICHOPPER OSC. PERIOD
B
NOTE THAT CURRENT IN
SENSE RESISTOR IS
.INTERMITTENT
SENSE
RESISTOR
CURRENT
LOAD
CURRENT __
Figure 17 : Inhibit Chopping. The drive current (01, winding, 04) in this case is interrupted by activating
INH1. The decay path through 02 and 03 is faster than the path Y of Figure 15.
Vs
•
I
t ___ ,
_-D-+-~--{JB
INHI
SENSI
DRIVE
CURRENT-.-.-~
RECIRCULATION - - - - - ...
11/17
197
APPLICATION NOTE
In this case when the voltage accross Rs reaches
VREFthe chopper flipflop is reset and INH1 activated
(brought low). INH1, remember, turns off all four
transistors therefore the current recirculates from
ground, through D2, the winding and D3 to Vs. Discharged across the supply, which can be up to 46V,
the current decays very rapidly (figure 18).
The usefu Iness of this second faster decay option is
fairly obvious ; it allows fast operation with bipolar
motors and it is the only choice for unipolar motors.
But why do we offer the slower alternative, phase
chopping?
The answer is that we might be obliged to use a low
chopper rate with a motor that does not store much
energy in the windings. If the decay is very fast the
average motor current may be too low to give an
useful torque. Low chopper rates may, for example,
be imposed if there is a larger motor in the same system. To avoid switching noise on the ground plane
all drivers should be synchronized and the chopper
rate is therefore determined by the largest motor in
the system.
Multiple L297s are synchronized easily using the
SYNC pin. This pin is the squarewave output of the
on-chip oscillator and the clock input for the choppers. The first L297 is fitted with the oscillator components and outputs a sqarewave signal on this pin
(figure 19). Subsequent L297s do not need the oscillator components and use SYNC as a clock input.
An external clock may also be injected at this terminal if an L297 must be synchronized to other system
components.
Figure 18 : Inhibit Chopper Waveforms. Winding
AB is energized and CONTROL is low.
CHOP
CHOP
JLJl..JlSl..JU'
~~~~~OR
CURRENT
LOAO~
CURRENT
_
_ _ _ _ _ _ _ _ _ _ _ _ _
_ __
FAST DECAV
12/17
198
Figure 19 : The Chopper oscillator of multiple
L297s are synchronized by connecting
the SYNC Inputs together.
--I
11
SYNC
SYNC
L297
L297
OSC
VS
5V
rz
OSC
16
R
16
~
5_S8l.711
I
C
--
THE L297A
The L297A is a special version of the L297 developed originally for head positioning in floppy disk
drives. It can, however, be used in other application-
s.
Compared to the standard L297 the difference are
the addition of a pulse doubler on the step clock
input and th~availability ofthe output of the direction
flip flop (block diagram, figure 20). To add these
functions while keeping the low-cost 20-pin package
the CONTROL and SYNC pins are not available on
this version (they are note needed anyway). The
chopper acts on the ABCD phase lines.
The pulse doubler generates a ghost pulse internally for each input clock pulse. Consequently the
translator moves two steps for each input pulse. An
external RC network sets the delay time between
the input pulse and ghost pulse and should be
chosen so that the ghost pulses fall roughly halfway between input pulses, allowing time for the
motor to step.
This feature is used to improve positioning accuracy. Since the angular position error of a stepper
motor is noncumulative (it cancels out to zero every
four steps in a four step sequence motor) accuracy
is improved by stepping two of four steps at a time.
APPLICATION NOTE
Figure 20 : The L297 A, includes a clock pulse doubler and provides an output from the direction flip flop
(DIR-MEM).
A
INHI
B
C
INH2
0
L297A
HALF IFULL
STEP
0--+--------1
...----+--0 ENABLE
RESET
CCW/CCW
OIR-MEM
DOUBLER
GNO
HOME
APPLICATION HINTS
Bipolar motors can be driven with an L297, an
L298N or L293E bridge driver and very few external
components (figure 21). Together these two chips
form a complete microprocessor-to-stepper motor
interface. With an L298N this configuration drives
motors with winding currents up to 2A ; for motors
up to 1A per winding and L293E is used. If the PWM
choppers are not required an L293 could also be
used (it doesn't have the external emitter connections for sensing resistors) but the L297 is underutilized. If very high powers are required the bridge
driver is replaced by an equivalent circuit made with
discrete transistors. For currents to 3.5A two
L298N's with paralleled outputs may be used.
For unipolar motors the best choice is a quad darlington array. The L702B can be used if the choppers are not required but an ULN2075B is preferred.
SENS 1 Vre!
SENS 2
OSC.
This quad darlington has external emitter connections which are connected to sensing resistors (figure 22). Since the chopper acts on the inhibit lines,
four AND gates must be added in this application.
Also shown in the schematic are the protection
diodes.
In all applications where the choppers are not used
it is important to remember that the sense inputs
must be grounded and VREF connected either to Vs
or any potential between Vs and ground.
The chopper oscillator frequency is determined by
the RC network on pin 16. The frequency is roughly
1/0.7 RC and R must be more than 10 Kn. When
the L297A's pulse doubler is used, the delay time is
determined by the network Rd Cd and is approximately 0.75 Rd Cd .Rd should be in the range 3 kQ
to 100 kn (figure 23).
13/17
199
APPLICATION NOTE
Figure 21 : This typical application shows an L297 and L298N driving a Bipolar Stepper Motor with phase currents up to 2A.
Vs
!>v
(
( 36V
R1
-c:J-
c~
Un'
:J:
c~ --I~nF
~CL
:t
100nF
12 lin
_,..470
;,F
r
GNO
OSC
CW/CCW
(LOCII
1
12 A
16
"
~
18
Ii
HALF/ML
19
-RESET
ENABLE
1
L297
9
20
!>
10
Yr{,f
15
11 I
8
3
13
l
CONIROl
"I
8
C
0
INH I
INH2
!>
01
8
9
02
~
4
~
~~
D~
04
~~
01
I
)
~
f
1
3 02
10
L298N
1]
12
03
STEPPER
MOTOR
WINDINGS
Ii
14~f--
11
1
15
05
SENSEI
A~
SENSEI
-"-
HO..,E
06
~~
01
oa
A..
_.... --
-A~
SYNC.
5- 5646/4
RS1 RS2
~
D1 to D8
14/17
200
0.5
~
Q
2 Fast Diodes
VF ,; 1.2 @ I
trr ,; 200 ns
~
2 A
APPLICATION NOTE
Figure 22 : For Unipolar Motors a Quad Darlington Array is coupled to the L297. Inhibit chopping is used
so the four AND gates must be added.
.
Us.24U
.
2 x
8ZW84-48
1
A
J:
2 x
8ZW84-48
8
188nF
16
9
0
ULN
20758
IHH2
INH1
8
C
15
5ENS1
SENS2
Rs1
Rs2
N92I1N4?B-Bt
Figure 23 : The Clock pulse doubler inserts a ghost pulse 'to seconds after the Input clock pulse. Rd Cd
is clasen to give a delay of approximately half the Input clock period.
'f
Rd
~
L297A
Cdf
~
,
I
CLOCK
PULSE
DOUBLER
OUTPUT
U,
I
I
,
,I
U
U
,
W
I
I
U
LJ
'S-':l6'B
15/17
201
APPLICATION NOTE
PIN FUNCTIONS - L297
N°
Name
1
SYNC
Output of the On-chip Chopper Oscillator.
The SYNC connections of all L297s to be synchronized are connected together and the
oscillator components are omitted on all but one. If an external clock source is used it is
injected at this terminal.
2
GND
Ground Connection.
3
HOME
4
A
5
INH1
6
B
7
C
8
INH2
9
D
10
ENABLE
11
CONTROL
Function
Open collector output that indicates when the L297 is in its initial state (ABCD = 0101).
The transistor is open when this signal is active.
Motor phase A drive signal for power stage.
Active low inhibit control for driver stages of A and B phases. When a bipolar bridge is
used this signal can be used to ensure fast decay of load current when a winding is
de-energized. Also used by chopper to regulate loadcurrent if CONTROL input is low.
Motor phase B drive signal for power stage.
Motor phase C drive signal for power stage.
Active low inhibit control for drive stages of C and D phases. Same functions as INH1.
Motor phase D drive signal for power stage.
Chip enable input. When low (inactive) INH1, INH2, A, B, C and D are brought low.
Control input that defines action of ch~.
When low chopper acts on INH1 and INH2 ; when high chopper acts on phase lines ABCD.
5 V Supply Input.
12
Vs
13
SENS2
Input for load current sense voltage from power stages of phases C and D.
14
SENS 1
Input for load current sense voltage from power stages of phases A and B.
15
Vref
Reference voltage for chopper circuit. A voltage applied to this pin determines the peak.
load current.
16
OSC
An RC network (R to Vcc , C to ground) connected to this terminal determines the chopper
rate. This terminal is connected to ground on all but one device in synchronized multi L297 configurations. f '" 1/0.69 RC, R> 10 kQ.
17
CWICCW
Clockwiselcounter clockwise direction control input. Physical direction of motor rotation also
depends on connection of windings.
Synchronized internally therefore direction can be changed at any time.
18
CLOCK
Step Clock. An active low pulse on this input advances the motor one increment. The step
occurs on the rising edge of this signal.
19
20
16/17
202
HALF/FULL Half/full Step Select Input. When high selects half step operation; when low selects full
step operation. One-phase-on full step mode is obtained by selecting FULL when the
L297's translator is at an even-numbered state. Two-phase-on full step mode is set by
selecting FULL when the translator is at an odd numbered position. (the home position is
designated state 1).
RESET
Reset Input. An active low pulse on this input restores the translator to the home position
(state 1, ABCD =0101).
APPLICATION NOTE
PIN FUNCTIONS - L297 A
Pin function of the L297A are identical to those of the L297 except for pins 1 and 11.
N°
Name
Functions
1
DOUBLER
An RC network connected to this pin determines the delay between an input clock pulse and
the corresponding ghost pulse.
11
DIR-MEM
Direction Memory. Inverted output of the direction flip-flop. Open collector output.
Figure 24 : Pin connections.
REID
SYNC
19
GND
CLOcii
HOME
A
INH1
HALF/FULL
CW/CCW
4
L297
OSC
DOUBLER
20
RESET
GND
19
HALF/FULL
HOME
18
CLOCK
A
17
CW/CCW
16
OSC
INH1
5
L297A
B
Vr~f
B
15
Vref
C
SENS 1
C
."
SENS I
INH 2
SENS 2
Vs
D
ENABLE
CONTROL
INH,
SENS 2
8
Vs
D
DlR-MEM
ENABLE
S-'l>B40
!J-~aJg
17/17
203
DC AND BRUSHLESS MOTORS!
205
APPLICATION NOTE
TWIN-LOOP CONTROL CHIP
CUTS COST OF DC MOTOR POSITIONING
by H. Sax, A. Salina
Using a novel controllC that works with a simple photoelectric sensor, DC motors can now compare with stepper motors in positioning applications where cost is critical. The chip contains two
complete control circuits, so that two motors can be controlled with one IC.
Since the introduction of integrated power drive
stages, stepper motors have been the most popular choice for positioning drives in cost-critical applications like printer carriage control. Though DC
motors are cheaper, require less power and provide more holding torque, they were rejected because they needed a costly shaft angle encoder
to achieve comparable performance.
Today, however, it is possible to build a cheap,
fast and efficient DC motor positioning drive that
uses a simple optical encoder. What makes this
possible is an integrated circuit - the SGSTHOMSON type L6515 - that embodies a twinloop control system and uses a novel tacho conversion scheme which works effectively without
high precision sensors.
The new IC is designed to work in a system
shown schematically in figure 1. Actually the device contains two complete control circuits because most applications involve two motors. For
simplicity only one half is shown. The system is
controlled by a micro and uses a high-power
bridge IC as the output stage to drive the motor.
On the motor shaft is an optical encoder that provides two sinusoidal or triangular outputs 90° out
of phase.
Two closed-loop operating modes are used:
speed control and position control. At the beginning of a positioning action the system operates
in speed control mode. The microcontroller applies a speed demand word to the L6515's DAC,
normally calling for maximum speed. The motor
current rises rapidly, accelerating the motor to the
desired speed, which is maintained by a tacho
feedback voltage derived from the sensor signals.
A counter in the micro monitors the squared sensor outputs, counting pulses to determine the distance travelled. As the target position is reached
the micro reduces the speed demand word stepby-step, thus decelerating the motor. Eventually,
when the speed demand word is zero and the
final position very close, the micro closes the po-
Figure 1 : A highly integrated control circuit using novel circuit techniques makes it possible to design a
dc motor pOSitioning system that competes with stepper motors. This device is used with a
bridge power stage and optical encoder.
~--~
SPEED DEMAND
WDRD
BRIDGE DRIVER IC
~----~
ru
PWM
LrI
1/2 OF
MCU
L6515
COUNT
Jl.rIIU1...
.r
DIRECTION
TACHO FEEDBACK
\
SQUARED TACHO
SIGNAL FOR
POSITIDN COUNTING
AN457/0392
fl92f1N45?-B2
1/8
207
APPLICATION NOTE
Figure 2: Unlike conventional tacho converters the L6515 uses this circuit which does not depend on a
high-precision mechanism because it exploits the crossover points between the sine and
cosine signals from the encoder.
n92I1N45?-B1
S1
sition loop - where one of the sensor outputs is
connected directly to the error amplifier - forcing
the motor to stop and hold in a position corresponding to a zero crossing of the sensor signal.
This combination of closed loop speed control,
pulse counting and closed loop position control
gives very fast and precise positioning.
GENERATING THE TACHO SIGNAL
Systems working on this basic principle have
been used before, but ,they used a conventional
tacho conversion scheme where the encoder outputs are converted to a voltage proportional to
speed by differentiation and synchronous rectification. To make this scheme work the encoder
signals must be exactly sinusoidal or the tacho
output will not be sufficiently precise. This in turn
calls for great mechanical precision in the encoder construction and electronic brightness control for the light source. Such encoders are intrinsically expensive.
One alternative is to design a purely digital system, where the controller simply processes pulses
from a simple encoder. However, this would require an encoder with a large number of steps/rotation to keep the loop stable at low speeds and
guarantee the necessary precision. Also, at high
speeds the pulse rate would overload low cost
microcontrollers.
A completely new approach has been chosen for
the L6515 which solves this problem. Rather than
depend on the magnitude of the signals, this
method relies on sensing the tN/llt between
crossovers in the encoder signals (figure 2).
How this works can be seen in the waveforms of
figure 3. First the two encoder signals are in2_/8_ _ _ _ _----:_ _ _ _ _
208
Figure 3: Waveforms and truth table for the
tacho conversion circuit in figure 2.
POlA
POlB
. . . . . . . . -........
UREF
~
.
",
,
~ ~.
.,. ...._ ... :',_~.:
~
~
~
t
~~_
... '
.
.. "' .....
POlA ' PDlB '
C1
t
C2
t I
r
i
I
I
I
TRUTH TABLE, S1 - S7
C1
C2
CLOSED
S71N POSITION
L
H
H
L
H
H,
L
L
S1
S2
83
84
TSPO
T8PO
TSPO
TSPO
'r'l SGS-THOMSON
A.,~ ~DCI!I@rnl.lEC'ii'DlWlDCiII
_ _ _ _ _ _ _ _ _ _ __
APPLICATION NOTE
Figure 4:Th~ system ope~ates with a simple, inexpensive optical encoder which has only one
adjustment, which ensures that the maxima of the sine and cosine waveforms are within a
certain tolerance. All other tolerances are guaranteed by the construction of the encoder.
;. L2·· .. ···················· 'LP2':
LP3 :
Rl
LP6 :
39
U
AMPLITUDE
r----------------JL--------
4.3
3.B r-.f--~~~~---,r---~~
SEl
: K198P
:
2.Br---~+_--~--~~--~----;-.
M M1:
5
3
+ .
.LPB:
LP7 :
1.B~~+++_--~~.__,~--~---
R3
18K
2Cl
1.3r---+++_---,~-------------
LPS:
LP4 :
llnFL-------------~~~
LPl :
8
PHASE ERROR
Ll
. . . . . . . . . . _-_ . . . . _-- . . . • - - - - - - . . -!
± 20·
"92I1N457-94
verted, giving a total of four signals. One of these
is selected by the switches S1 to S4 depending
on the outputs of the two comparators which
cross-compare the sine and cosine signals. The
selected encoder signal is then differentiated and
the output inverted or not depending on the two
comparator outputs.
The beauty of this approach is that it is independent of the encoder waveforms - they can
e~~n b.e triangular. Th.e only requirement for precIsion IS that the maxima of the sine and cosine
waveforms must be within a certain tolerance, ensuring sufficient precision in the crossover points.
This can be achieved in practice with a simple
mechanical adjustment.
Figure 4 shows an encoder used in this system
and how it is attached to the motor. For an encoder of this type and a resolution of less than
100 steps/revolution no other adjustments are
necessary because the mechanical construction
guarantees all of the other tolerances.
CLOSING THE POSITION LOOP
As we have seen above, the tacho loop is augmented by a position loop for the final precise positioning and holding. How the two loops are connected in shown in figure 6.
The eight bits from the microcontroller consist of
five bits for the magnitude of the speed demanded, one bit for its sign (and hence the motor
direction) and two bits which select which half of
the Ie is addressed. If a speed demand word of
00000 is loaded one of the two switches S5 or S6
is closed, depending on the direction selected.
Thus one of the encoder signals is connected directly to the summing point of the error amplifier
input and the motor will be brought to a halt at the
zero crossover of the encoder signal. It will remain in this position until a new position operation
is initiated.
At the output of the error amplifier is the pulsewidth-modulation circuit which drives an external
power stage (figure 8).
In basic outline this circuit is very simple: the error
~ ~~~;m&r::oo~l:
__________________________3_/8
209
APPLICATION NOTE
Figure 5: Application Circuit
REF
16
12
.5
13
17
'5
~
)t
05C~
23
24
19
29
26
33
'5
...
25
L6515
27
28
34
21
30
"
. ENCODER
31
32
28
37
38
39
48
41
42
.
43
35
22
36
.5
LOAD
~a:::=)
~
1192L5515-1 J
Figure 6: Shown schematically, the complete system has a. main, velocity loop where the tacho signal
and the output of a DAC are compared in an error amplifier which drives a PWM output
stage. For final positioning S5 or S6 is closed, forming a position loop.
TO OTHER CHANNEL
!192ffNJ5?-f35
4/8
210
APPLICATION NOTE
Figure 7:Because there is a single sense resistor connected to the lower legs of the bridge the current
feedback voltage does not reflect the polarity of the motor current. Before the feedback signal
can be added to the error signal its polarity must be restored.
LOAD CURREI'IT
A
8
I
POSITIUE LOAD
CURREI'IT
I
.
A1IA2·B1182!
f-----~--_:___--t
!
8
A
f----:r--r--"".;::--.;-I--.;11'''"----+ t
I
I'IEGATIUE LOAD
I
CURREI'IT
j ....... j .... .
i
I
URS f--------1:----+-- t
A
tUs
B
tUs
Rs
Rs
"92I1H45?-86
A
B
tUs
tUs
Rs
Rs
5/8
--------------------------- ~~~~~~~~:~~ --------------------------211
APPLICATION NOTE
Figure 8: The pulse width modulator is formed by an oscillator (9) and a comparator (4). Switch S8 and
(1) restore the correct polarity to the voltage from the current sense resistor.
9
OAC
TACHO
FTB ~
56
Rp
FTB ~
55
R5
-
:I
.I
-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.~
amplifier output sets the threshold of the comparator 4, thus transforming the triangular wave
from the oscillator into a rectangular signal whose
duty cycle depends on the error amplifier output
amplitude.
Feedback is provided by the sensing resistor Rs,
which provides a voltage proportional to 1M.
The whole loop works in current mode which controls the torque 6f the motor.
Figure 9:The gain of the current loop is set by R5, while the maximum current can be set independently
by the sense resistor, Rs.
Us-BEMF
RM
~ WITHOUT LIMITING
,----- I M- - - -
!
~
,- '-
r--r---+-. MAX CURRENT
5ET BY Rs
SLOPEtTRANSCONOUCTANCEI
SET BY Rs
----------,r--------++
ERROR CURRENT
IOAC-ITACHO
ff92I1N45?-88
6/8
- - - - - - - - - - - - - - - - ~~~~~~~~~:~ ---------------------------212
APPLICATION NOTE
Figure 10:There are six distinct phases in an elementary positioning operation. These waveforms show
the corresponding speed demand word, actual motor speed and motor current.
+
f192f1N45?-99
However, in practice it is necessary to reconstruct
the polarity of the feedback voltage because the
voltage across Rs is always of the same polarity,
regardless of the direction of the drive current.
This is performed by the inverter in the feedback
path which is switched by S8 depending on the
direction of the drive signal, which controls the
current direction.
When the motor is accelerating rapidly to the set
speed the current control loop saturates so the
load current could increase to the point where the
power stage or motor may be damaged.
To prevent this a limiting circuit formed by stages
6, 7 and 8 has been included. Normally the flip
flop is reset periodically by the Rs oscillator and
remains in the reset state; consequently the
EXOR gate is "transparent", having no effect on
the PWM output. When, however, the current exceeds a positive or negative threshold the flip flop
will be set, thus the EXOR gate will invert the
PWM output thus reversing the bridge drive,
causing the current to drop rapidly.
Figure 8 shows the loop characteristics of the
system and how they are controlled.
The loop gain is set by the resistor R5, while the
maximum current is set independently by the
sensing resistor Rs. These components can be
set to accommodate a wide variety of motors and
conditions.
Now that the circuit functions have been explained it is possible to follow in detail the functioning of the device. A basic positioning operation would consist of six steps (figure 10):
A.Acceleration, where the current is at a maximum limited by stages 6/7/8 (indicated in figure 8)
B.End-of-acceleration, where the current is reduced under control of stages 3/4
C.Constant speed, where tacho feedback controls the current at a low value
D.Deceleration, where the current is limited by
stages 6/7/8
E.End-of-deceleration, where the current is controlled by 3/4
F.Positioning, where either S5 or S6 is closed.
In practice phase D will be replaced by a series of
decelerations to bring the motor speed down
smoothly to zero at the destination point. Figure
10 shows the corresponding waveforms.
HIGH POWER BRIDGE ICs
The L6515 control IC is designed to be used with
monolithic high power bridge driver ICs which are
widely used today for DC and stepper motor driving. These devices are very simple to use because they are controlled by logic level inputs and
include basic protection circuits to prevent damage in case of a fault in the controller or software.
Suitable types for output currents from 500mA to
4A are listed in Table 1. Note that bridge drivers
r== SGS.1HOMSON
-------------- ".,1
7/8
IiVID©liJml~©llliJ@i!DC$ - - - - - - - - - - - - - -
213
APPLICATION NOTE
Figure 11 : In a real positioning operation the deceleration of the motor is controlled smoothly by a
progressive reduction of the speed demand word.
IDAC
N> "
1
'"j=Ly "
n
I,.
N-STEPS
pos
SW ITCH
-/~
!1 !\
v
FTB
using DMOS power stages make it possible to
obtain 1.5A output current using a DIP package,
which is very compact and convenient for assembly. Also, single power ICs containing two bridges
are available, so it is possible to make a positioning system for two motors with just two ICs.
The same BCD technology used to make smart
power bridges like the L6202 and L6204 is also
employed in the L6515, even though there are no
power stages in the device. This technology is, in
fact, highly suitable for this IC because it combines high density logic with the precision of bipolar circuits. Moreover, it also allows the inclusion
of very low resistance MOS transistors which are
needed in the tacho conversion switching circuits.
SOFTWARE
Software to control the L6515 must initialize the
system at each reset then manage each positioning operation.The initialization routine is very
t
simple; bringing the two latch control inputs R & S
high together resets both of the latches at the
DAC inputs. (see Figure 5).
At the same time the position counters in the
micro will be zeroed. If the mechanical subsystem
is in an unknown position the motor will have to
be driven at a moderate speed to a known position during this phase. In a printer, for example, it
can be driven towards an endstop.
For each positioning operation the micro will have
to determine a suitable profile - in particular
when to begin deceleration. Then, once the first
speed demand word has been latched into a DAC
it will have to count the squared encoder pulses,
usually with an interrupt routine. At specific distances from the end point reduced speed demand
words will be loaded and then when the final position has been reached a zero speed demand
word will be loaded; this automatically activates
the position loop.
Table 1: High Power Bridge Driver ICs
HIGH-POWER BRIDGE DRIVER ICs
TYPE
FUNCTION
TECHNOLOGY
OCCURRENT
L6204
DUAL BRIDGE
DMOS
0.5A
L6201
BRIDGE
DMOS
1A
L6202
BRIDGE
DMOS
1.5 A
20 - PIN POWERDIP
L298N
DUAL BRIDGE
BIPOLAR
2A
15 - PIN MULTIWATT
L6203
BRIDGE
DMOS
4A
11 - PIN MULTIWATT
8_/8_ _ _- - - - - - - - -
20 - PIN SO
r== SCS-mOMSON _ _ _ _ _ _ _ _ _ _ _ __
.... , /
214
PACKAGE
20 - PIN POWERDIP
liIlu©liil@rn~rn©1rll@iilU©~
APPLICATION NOTE
HOW TO DRIVE DC MOTORS WITH SMART POWER ICs·
by Herbert Sax
There are many ways to control DC motors. Open-loop current control acts directly on torque
and thus protects the electronics, the motor and the load. Open-loop variable voltage control
makes sense if the motor and electronics are not overloaded when the motor stalls. Open-loop
variable voltage control with a current limiting circuit constitutes the simplest way of varying
speed. However, a closed-loop system is needed if precision is called for in selecting speeds.
No other motor combines as many positive characteristics as the direct current design: high efficiency, ease of control & driving, compactness
without sacrificing performance and much more.
And DC motors can be controlled in many ways
- open loop current control, variable voltage control or closed-loop speed control - providing
great flexibility in operational characteristics.
Before we turn to a detailed discussion of the various methods of control, it is worthwhile recalling
a few basics.
DC MOTOR BASICS
Generally speaking, the electric equivalent circuit
of a motor (figure 1) consists of three components: EMF, Land RM.
Figure 1: Electrical equivalent circuit of a DC
motor, consisiting of EMF, the winding
inductance L and the winding resistance RM.
RM
L
Us
EMF
1M
L...-----1~/·IIJj-f1-9-Bn-H-3-8....JB - Bt
The EMF is the motor terminal voltage, though
the motor is always a generator, too. It is of no
significance whether the unit operates as a motor
AN380/0591
or a generator as far as the terminal voltage is
concerned. The EMF is strictly proportional to the
speed and has an internal resistance of zero. Its
polarity represents the direction of motion, independent of the motor voltage applied.
The winding inductance, L, is the inevitable result
of the mechanical design of the armature. Since it
hinders the reversal of current flow in the armature, to the detriment of torque as speed increases, the winding inductance is an interference factor for the motor. It also obstructs rapid
access to the generator voltage (EMF).
Motors of coreless, bell armature or pancake design are considerably less susceptible to winding
inductance. The smaller mass of these motors improves their dynamic performance to a significant
extent. On the positive side, the winding inductance can be used to store current in pulse-width
modulation (PWM) drive systems.
The winding resistance. RM, is purely an interference variable because losses that reduce the degree of efficiency increase as the load torque on
the motor shaft increases, the latter being proportional to the current 1M. It is also due to the winding resistance that the speed of the motor drops
as load increases while the terminal voltage Vs
remains constant.
Some of the mathematical relationships are
shown below in simplified form:
EMF = VS-(IM.RM)
Motor current 1M = (Vs - EMF)/RM
Eft' .
EMF· 1M
IClency = Vs' 1M
POUT
= TN
The drive torque at the motor shaft is proportional
to the motor current 1M. Figure 2 shows the relationships graphed in a form commonly used for
DC motors. It is because of bearing and brush
friction that the efficiency tends towards zero at
low load torques.
1115
215
APPLICATION NOTE
Figure 2: Relationship between speed, efficiency
and motor current of a DC motor.
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n!lBIIH3BB-B2
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These basics show that essentially there are only
two parameters governing how an electrical
change can be made to act on the motor shaft:
a) with the current to vary the torque
b )with the mapping of the EMF on the speed
On account of the winding resistance RM, open
loop variable voltage control exercises no more
than an indirect effect on torque and speed and
can therefore be used only for simple functions
(speed variation).
A number of sample applications using smart
power ICs and illustrating open-loop variable voltage or current control and closed loop speed control are discussed here. All of these circuits permit
the motor to run in both directions. The modifications needed for unidirectional operation are slight
and generally involve a simplification of the design.
OPEN· LOOP VARIABLE VOLTAGE CONTROL
In technical terms variable voltage control is the
simplest to implement. Its main scope of application is in simple transport or drive functions where
exact speed control is not essential. Applications
of this kind are found, for example,in the automobile industry for driving pumps, fans, wipers and
power window lifts.
The circuit shown in figure 3 is an example of a
variable speed motor with digital direction control.
The motor voltage can be controlled via an analog input. If the polarity of the control signal is the
variable that determines the motor's direction of
rotation - as is usually the case in servo systems, for example- the design shown in figure 4
can be used.
One of the operational amplifiers is responsible
for the VMNiN voltage and the other has an gain
of 1, so that the voltage losses Vs - VM are divided evenly between the two parts of the
bridge.
Equivalents to the circuits in figures 3 and 4 are
shown in figure 5 and figure 6; these latter circuits, however, are switch mode and their efficiency is thus improved to a considerable extent.
Figure 3: Circuit for driving a variable-speed motor. Where the enable function is needed, the type
L6242 can be used.
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2/15
216
APPLICATION NOTE
Figure 4: A typical circuit for driving servo system.
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Figure 5: Equivalent circuit to that in Figure 3, but using PWM.
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Figure 6: Equivalent circuit to that in Figure 4, but using PWM.
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--------------------------- LW ~~~~~:~~i!~~ ---------------
217
APPLICATION NOTE
junction with open-loop variable voltage control or
closed loop speed control. Such an arrangement
would be designed to:
OPEN-LOOP CURRENT CONTROL
Open-loop co~trol is called for whenever a motor
has to supply a constant or variable torque. Applications include the head motors in tape recorders
or the motors used to tension threads when textile
fibers are wound onto spools. The speed of the
motor at any given time is of no significance. In
applications of this nature the motor shaft will
often rotate in the direction opposite to that determined by the current.
Two conditions are particularly important in a current controlled application. The circuit will not operate unless VMmax ~ EMF + (1M RM), if the motor
shaft is running in the same direction as the drive.
The equation applicable to a counter rotating
motor shaft is:
-VMmax -EMF s; 1M RM
Open-loop current control is often used in con-
• limit torque to protect the load and the motor
• protect the power ICs against overload
• obtain acceleration and deceleration
characteristics independent of speed.
Figure 7 shows the simplest form of open-loop
current control with a positive & negative supply.
Transferring the circuit to a bridge eliminates the
ground at one end of the shunt Rs and a way of
differentially sampling the sense resistor voltage
must be found. One solution is shown in figure 8.
As in figure 4, the second half of the bridge operates as a voltage inverter.
Figure 7: Current control circuit with bipolar voltage supply in its simplest form.
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Figure 8: This circuit permits differentiated sampling of the voltage at the sense resistor.
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-------------- ~ ~~~~m&r;,:I!~~ -------------218
APPLICATION NOTE
When the principle behind ~he circuit sho,,:,n i~ figure 8 is transferred to a sWltchmode circuit (figure
9) a considerable degree of complexity is called
fo; to reduce power loss. For this reason the circuit is shown.in slightly simplified form.
Operational amplifier 1 reconstructs the curre~t
proportional voltage VRS to ground as shown In
figure 7. Two sense resistors are needed, as.otherwise it would not be possible to detect the direction of the current in the bridge.
Operating as a PI controller and converting the
error signal in a PWM via comparator 3, OP2
compares the reference and. fe~dback values.
One major advantage of a circuit such ~s t~at
shown in figure 9 is its high transfer Iineanty
maintained even in the vicinity of the zero current
crossing. Open-loop current control also functions .
with a generator, the motor returning its own kinetic energy and that of the load to the supply
voltage in a controlled mann~r. ~raking i.s a c~se
in point, and for this reason circuits of this design
are usually found in servo positioning drives that
demand precise current control over a wide operating range.
CLOSED-LOOP SPEED CONTROL
Many circuits, often of completely different dec
sign, have been developed for closed-loop speed
control. The most suitable system has to be chosen on the basis of the requirements that a drive
concept has to meet. These requirements also
determine how the speed will be sensed and processed.
Figure 9: Operating principle of th.e circuit of figure 8 transferred to a PWM arrangement.
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SGS·THOMSON _ _ _ _ _ _ _ _ _ _ _
_
- - - - - - - - - - - - - - . ., , / ~O~lll@~~~II:1flll@OOO~$
219
APPLICATION NOTE
their influence on control characteristics and system costs.
The table provides an overview of the most common principles of sensing and processing and
PRINCIPLE OF SPEED SENSING
CHARACTERISTICS
CONTROL
ACCURACY
HIGH
MEDIUM
LOW
EXTENDED CONTROL
RANGE POSSIBLE
CONTROL
REACTION
FAST
SLOW
GOOD CONTROL
CHARACTERISTICS
AT LOW SPEEDS
SUITABLE FOR
SERVO DRIVES
SYSTEM
COST
HIGH
MEDIUM
LOW
DC
Tacho
·
·
·
·
·
·
V-I
EMF
Control Sense
AC
Tacho
SIGNAL PROCESSING
AC REFERENCE
ommu
PI
PID
PLL' Digital
P
tation
Control Control Control Control Sensor
Sense
. ·
·
·
· ·
· · ·
·
·
· ·
·
· · · · ·
·
·
·
· · · . ·
·
· · · · · ·
·
CLOSED-LOOP CONTROL PROCESSES
DC Tachogenerator
~ince a co~trol circuit with a DC tacho-generator
Yields a direct voltage that is proportional to
speed, th~ circuit itself is less complex than all
other designs. Nonetheless, high precision - a
constant voltage with low ripple - signifies high
cost. On the other hand, the actual electronic control circuit is simplicity itself, as figure 10 shows.
The bridge extension for a simple supply voltage
is identical to that shown in figure 8.
A closed loop current control system providing
braking and acceleration independent of the supply voltage and the internal motor resistance is
easy to superimpose on the circuit (figure 11).
~imil.ar,ly li,ttle difficulty i,s involved in modifying the
circuit In figure 10 to Yield a switched bridge, because the process entails no more than converting the control error signal into a PWM output (figure 12).
Figure 10: Control with DC tachogenerator: a direct speed proportional DC voltage is generated,
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220
APPLICATION NOTE
Figure 11: In this circuit, accel~ration and braking behavior is independent of the supply voltage and the
motor's Internal resistance.
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Figure 12: PWM conversion of the control error signal.
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V-I Control (Internal Resistance Compensation)
V-I control is based in the principle that the voltage drop at the motor internal resistance 1M that
incr.eases ~ith load torque can be compen~ated
by Increasing the motor voltage VM (figure 13).
However, compensation is less than complete because the winding resistance RM is heavily dependent on the temperature, and brush resis-
tance modulation makes itself felt as an additional
interference variable.
In. practice this means that the voltage drop is
slightly under compensated and positive feedback
is reduced even further as frequencies get higher.
The control action result improves with the ratio of
EMF to IM.RM. A sample circuit in which the effect
of the positive feedback loop can clearly be seen
is shown in figure 14.
____________ Gi,/ SCS-11fOMSON
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_ _ _ _ _ _ _ _ _ _ _7_/1_5
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221
APPLICATION NOTE
The desired speed is set with the aid of R1 and
R2. The relationship is expressed as:
EMF = VIN . R1/R2
The value selected for Rs is one tenth of RM and
VRS is amplified by a factor of 10 in OP2 (R5 =
R4/10).
The output voltage of OP2 is then identical with
the voltage drop at RM. When R1 = R3, the inter-
nal resistance is compensated by 90%. Residual
control instabilities can be cancelled out by C1.
The circuit can also be extended to a bridge, although this entails relocating resistor Rs (figure
15). It is surprising that the V-I controller circuitry
is again simplified to a considerable extent if amplification is not needed. The V-I control concept
can be adapted for a PWM motor control system;
the functional layout is rather complex, however,
as figure 16 shows. Even so, it is worthwhile in
many instances because DC tacho-generators
are expensive.
Figure 13: The principle of V-I control.
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Figure 14: Example circuit in which the positive feedback loop can clearly be seen.
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8/15
222
APPLICATION NOTE
Figure 15: Circuit as in figure 14, expanded to include a bridge.
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Figure 16: The principle of V-I control transferred to a PWM motor circuit: complexity is increased significantly.
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-------------9/15
223
APPLICATION NOTE
EMF Sensing
The EMF can also be sensed directly, rather than
be simulated as in the V-I control setup, when the
current 1M is zero (EMF = VM-IM.RM). To achieve
this the motor current must be switched off as
quickly as possible. Motor inductance represents
an obstacle since the energy it stores must first
be dissipated before an EMF measurement can
be made at the motor terminals. This is the reason why only coreless motors of bell armature or
pancake design are suitable. Figure 17 is a block
diagram showing how the EMF can be sensed.
In the major partial time t1. the fl.lotor car~ies current. This is followed by a time window t2 In which
the motor is de-energized and the motor inductance discharges. There then follows a short sampiing phase t3 in which the EM F is sensed and
Figure 17: Principle by which the EMF can be sensed.
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stored in a capacitor until the next sampling
phase. The number of cycling cycles per second
depends on the dynamic behavior of the load
torque. The interval between any two EMF measurements should be of a duration such that the
kinetic energy of the drive system bridges a load
change without a significant speed drop. Figure
18 illustrates a layout using a current-controlled
output stage that has a high impedance output
when the input is open.
The circuit for sensing EMF is particularly well
suited to switch mode motor control schemes. The
monolithic switching output stages available today
already have an enable input for releasing the
motor, but the concept will usually accommodate
this option even if discrete output stages are
used. An example circuit is shown in simplified
form in figure 19.
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Figure 18: Driver circuit with current controlled output stage with high impedance output when input is open.
HCF4066
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_10_/_15_ _ _ _ _ _ _ _ _ _ _ _ _
224
: ........... .
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APPLICATION NOTE
Figure 19: Circuit as in figure 18, but with PWM output stage.
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R2
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AC Te,=hogenerator
Economic and with a signal that is easy ·to process, the AC tachogenerator is the .most frequently used means of sensing the speed of a DC
motor. Problems arise, however, when the
tachogenerator frequency is low, due either to a
low speed or a lack of poles on the generator.
However, multiple pole tachogenerators are expensive regardless of whether they are magnetic
or optical. Most circuits convert the speed proportional tach a frequency back into a DC signal in an
fN converter (Fig. 20).
However, some circuits make use of the proportional relationship between speed and AC voltage
amplitude when the tachogenerator is inductive
(figure 21). Accuracy is wanting to a certain extent in this arrangement.
Since the output signal of an AC tachogenerator
contains no information concerning the direction
of rotation, the control loop functions in only one
quadrant. For the same reason it is common
practice to control the reference in a single quadrant. A separate digital signal determines the direction of rotation. Figure 22 shows a typical
Figure 20: The tachogenerator frequency can be converted back into a DC signal in an fN converter.
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11/15
-------------- !V ~~~;m~vr::~~~ --------------
225
APPLICATION NOTE
PWM circuit.
Comparator 1 converts the sinusoidal
tachogenerator signal into a squarewave voltage
that triggers the monostable. The ON time is constant, which means that the DC average. increases proportionally as the tachogenerator frequency increases. The error amplifier OP1 also
functions as an integrator (C1) and compares the
DC reference with the DC average of the monostable output. A DC signal superimposed by a triangular wave AC voltage component can be detected at the output of OP1 .
An analog power operational amplifier can also
be used instead of the switch mode output stage.
In an arrangement like this, the output of the error
amplifier OP1 drives the VIN input of the output
stage as shown in figure 3.
Figure 21: Alternatively, the proportionality between speed and AC amplitude can
be used if the tachnogenerator is inductive.
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Figure 22: In this PWM circuit the comparator 1 converts the sinusoidal tachogenerator signal into a
squarewave.
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R1
119BflN3BB-22
12/15
COMP 1
- - - - - - - - - - - - - - l . f j ~~~~m~~:oo~©~
226
--------------
APPLICATION NOTE
COMMUTATION Sensing
Commutation sensing is a process that exploits
the inherent ripple of the EMF of the motor current as an AC tachogenerator. However, only motors with few poles yield an adequate signal-tonoise margin. Three-pole motors with an AC
component equal to approx 30% of the DC value
are most suitable (figure 23).
The rapid current reversal is differentiated and
used as an equivalent tachogenerator signal (figure 24). The rest of the circuit follows the pattern
shown in figure 22, although only one output
stage of the type shown in figure 3 is used. A
sWitch mode output stage would interfere with the
ripple sensing so is not recommended. One drawback of commutation sensing is the exceptionally
low tachometer frequency. A three pole motor, for
example, produces a frequency of 200Hz at a
speed of 2000 rpm.
Since the AC component of the OP1 error amplifier output signal (figure 22) should not be more
than 10% of the DC component at rated speed
and nominal load torque, the integrator time constant C1 R1 is very large. Control response is
sluggish and no longer suitable for rapid load
changes.
Assistance can be obtained by superimposing V-I
control which has high-speed response to relieve
the tachogenerator control loop and accelerate
transient response by a considerable margin. Figure 25 shows a sample circuit for a bridge.
Superimposed V-I control can also be used with a
real AC tachogenerator to improve the transient
load response.
Figure 23: Principle of commutation sensing.
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f19BflN38B-23
Figure 24: The fastest current reversal is commutated and used as a substitute tachogenerator signal.
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REF
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f19BAN38B-24
13/15
-----------------------------~~I ~~~~~~~:~~~-----------------------------
227
APPLICATION NOTE
Figure 25: Example circuit for a bridge.
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Processing the Tachogenerator Signal
The control principle (figure 26) applied in pro-
cessing the speed feedback and reference signals in a controlled system depends on a number
of factors (table page 6).
Figure 26: P, I, PI and PIO controllers.
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119BIIN38B-26
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14/15
228
APPLICATION NOTE
The criteria governing the selection of a P controller, an I controller, a PI controller or a PIO controller .are ~s follows: .stability of the control loop, reaction time, transient response, load behavior,
speed range and control factor. For example, if
the reference signal is a frequency it would make
sense to use an AC tachogenerator as the feedback value sensor and process both signals on a
purely digital level. Powerful microcontrollers or
digital signal processors are used.
In special cases that demand a control error of
zero - for example, when two drive shafts have
to be phase synchronized as well as running at
the same speed - PLL control is the only option.
A system of this nature compares reference and
feedback value for phase as well as frequency. In
turn, of course, the AC tachogenerator must meet
extreme requirements regarding phase stability
since any jitter would be interpreted as a control
error, producing a spurious response in the system.
PLL speed control systems are used in video recorders, floppy and hard disk drives and in a
number of industrial drive systems. Figure 27
shows a typical PLL speed control circuit. The frequency comparator is phase comparator 2 of the
HCF4046 CMOS PLL circuit.
Figure 27: Typical PLL circuit for controlling speed.
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-------------- Iiii ~~~;m~=:i!~~ _____________1_5/_15
229
APPLICATION NOTE
LOAD CURRENT SENSING IN SWITCHMODE
BRIDGE MOTOR DRIVING CIRCUITS
by Herbert Sax
Switchmode drive circuits with pulse-width modulation control of the current are widely used in
motor driving because they give the best performance.
In such circuits it is important to sense the load current precisely. This note proliides practical
solutions to this problem.
When it comes to controlling or driving electromagnetic actuators precise sensing of the load
current is one of the key functions of any system.
A switchmode bridge, however, does not lend itself to direct measurement of the load current in
series with the actuator because the high common-mode levels that result from pulse-width
modulation are far from conducive to low-cost
measuring circuits. Even so, however, these problems can be overcome without resorting to costly
isolating amplifiers. Most of the functions needed
can be integrated in smart power circuits; some
have already been implemented.
CURRENT CONTROL OF A DC MOTOR
In the final analysis, the voltage reference determines the complexity of a circuit for sensing the
load current of a DC motor bridge. The simplest
arrangement calls for a measuring shunt at the
common source pin of the lower branch of a
power MOSFET bridge (Fig.1 A).
On virtually all the smart power bridges in widespread use this pin is accessible and is adequate
for straightforward current limitation functions.
During the load inductor'S charge phase, the current that also drives the motor has no alternative
but to flow diagonally to the shunt through the two
transistors T1 and T2 and can therefore be
sensed. Once the load current reaches its nominal value, it should be stored by the most efficient
possible means.
The best way of achieving this aim is to short circuit the terminals, in other words to turn on transistors T2 and T3.
Figure 1A: Switch Mode Current Control Circuit for Load Current Limitation.(DMOS Bridge Configuration)
AN452/0392
115
231
APPLICATION NOTE
Figure 1B: Switch Mode Current Control Circuit for Load Current Limitation.(Bipolar Bridge Configuration)
A significant difference now becomes apparent
between the new DMOS smart power bridges
(Fig.1 A) and the conventional bipolar configurations (Fig.1 B). Since active MOSFET transistors
and their body diode are reverse conductive, the
load current circulates in the lower circuit and is
no longer accessible at Rs. Neither the bridge nor
the controller circuit is at risk - always supposing
that the current in the short-circuited free-wheeling circuit drops - and the circuit illustrated in
Fig. 1A represents the classic solution for simple
clocked current limitation functions.
BRAKING
When a DC motor brakes, the counter EMF it
generates feeds the motor inductor. When the
two lower bridge transistors T2 and T3 are ON
and forming what amounts to a terminal short circuit the current increases rapidly to a value equal
to EMF/RM.
Dangers arise if the short circuit current is allowed
to exceed the maximum current rating of the
bridge. Transistors having a large surface area
can help avert damage, but they are costly irrespective of whether the board carries discrete
components or smart power chips. It must also be
borne in mind that merely short circuiting the terminals leads to a situation in which the motor's
kinetic energy is largely converted into heat by
the winding resistance, the time the motor needs
to come to rest is uncontrolled.
SENSING THE BRAKING CURRENT
Consequently the aim must be to render the current measurable during braking. There are two
approaches to this problem, both using current
measuring shunts connected to ground on one
side for the sake of simplcity.
The first arrangement is based on a bridge having
interconnected source pins and will be described
below. The alternative is a circuit with two separate shunts in the source pins of the lower bridge
transistors, as shown in Fig 2.
During the charge phase of the load inductor, the
current that causes the motor to turn in a given
direction flows diagonally through T1, T2 and
RS1. In the free-wheeling phase T2 and T3 are
conductive and the situation is as shown in Fig
1A. Despite the fact that during this free-wheeling
phase the current is sensed as a positive voltage
at RS1 and a negative voltage at RS2, the information is ignored because the current is dropping.
This no longer applies in the braking phase, when
the start-stop input goes low.
At this point a higher current in the free-wheeling
circuit activates comparator camp 2. Through the
equivalence circuit EC1, the comparator disables
T3 and makes T1 go conductive, thus inverting
the left side of the bridge for a maximum of one
oscillator period. The kinetically generated energy
of the counter-EMF stored in the motor inductor is
returned to the power input (Vs). This process is
repeated periodically.until the EMF divided by the
motor resistance RM yields a braking current that
is less than VREF/RS1. This controlled return of
energy has one major advantage in that the braking current and thus the braking time can be influenced, while on the other hand, a large proportion of the motive energy is recovered and the
winding resistance has to dissipate much less
heat.
Sadly, however, the configuration shown in Fig. 2
is not feasible with all smart power bridges with
DMOS power transistors. Not infrequently the
source pins of the lower half of the bridge are interconnected on the chip, either because a limited
number of pins are available or because the metal resistance would be too high. In cases of this
nature the only resort is to connect two les in parallel and form a bridge from two half bridges. Of
course this entails an additional advantage in that
since conductive losses are lower, too.
----------------------------- ~~~~~~~~:9~ -----------------------------
2/5
232
APPLICATION NOTE
Figure 2: Same As Figure 1a but Including Braking Energy Recovery.
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SOLUTIONS FOR SERVO SYSTEMS
Circuits such as those shown in figs 1 and 2 are
used primarily to protect the motor an? se~ico~
ductor bridge from overload. Torque limitation IS
often another major concern in stepper motor
drive systems and with DC motors. AlthouQh the
current can be varied within adequate limits by
varying the reference voltage, the tolerance factor
becomes larger as the values become smaller because only one-sided peaks can be measured, Instead of mean values. If the current fluctuates
close to or across zero, another strategy affording
greater precision is needed.
Servo systems, being closed-loop control sy.stems with position and speed sensors, are heavily
reliant on accurate current sensing In a form that
is perfectly reliable in the current reversal ranQe
close to zero. This further entails adopting a different drive strategy.
Since a short-circuited free-wheeling circuit in
which both lower transistors are conductive would
produce severe non-linearities in the current
reversal range close to zero, it is to be avoided at
all costs. Free-wheeling in this case means selectively inverting the bridge, thus causing the current to drop along a largely linear path, b~t no
more than five to ten percent before the onglnal
status is readopted. In a configuration of this nature a zero motor current means that the bridge
rem~ins active, but the sampling ratio is cut to
50%.
Since there are only two conductive states (either
T1 and T2 or T3 and T4), the current always flo~s
through Rs, irrespective of whether the circuit incorporates two separate shunts or one common
shunt.
Fig. 3 illustrates the current curves and t~eir effect on the sense resistors Rs. Reconstructing the
load current requires only an operational amplifier
that operates as a subtractor. Via resistor R1, !he
capacitors suppress the peaks that occur d.unng
changeover. Since the comm'!n-mode I.n.terference level is high, fast operational ampli.fl~rs
are the obvious first choice if high signal precIsion
is required.
Figure 3: Current Sensing by Reconstructor.
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233
APPLICATION NOTE
Figure 4: Current Sensing in the Load Circuit.
Fig. 4 shows another circuit that is feasibl.e for all
situations in Which, since they cannot be Inserted
in the source circuit, the shunts have to be connected directly in series with the load, with all the
disadvantages that this entails.
Although a single resistor suffices in theory, an
operational amplifier provides· the speed and
common-mode suppression characteristics that
make it virtually the ideal choice. Nonetheless,
the results can be improved considerably by
sensing the current on both sides of the load.
Since measurement is symmetrical, the useful
signals and the sense resistors are added
together, while the counter-phase edges are subtracted, thus significantly reducing the commonmode load on the operational amplifier. This is
true in so far as the matrix resistors are capable
of satisfying the very high requirements.
CURRENT RECONSTRUCTION
Bridges with a common source output show a~ interesting current pattern. The load current IS a
positive signal during the charge phase of t~e
coil, while it is negative in the in'(erted state, In
other words during the free-wheeling phase. The
only way to reconstruct this current is to periodically invert the sense voltage VRS.
Two of the many solutions to this problem are
shown in Fig. S. The VRS signal is applied to the
output alternately as a direct or inverted signal
(Fig. SA), or the operational amplifier can ~ork in
the inverting or non-inverting mode, depending on
the position of the switch: In both ca~es lat~ral
MOS transistors or even Simple smail-Signal bipolar transistors are perfectly adequate as switches.
The RC filter at the output smooths switching
peaks without distorting the time constant of the
current control loop.
Figure SA: Recovery of the Load Current Map.(Directllnverted Solution)
Us
IN
..
~----~~ ----~
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fl92f1N452-B6
4/5
-------------234
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APPLICATION NOTE
Figure 58: Accovery of the Load Current Map. (Inverting/non Inverting Solution)
I)s
PRACTICAL EXAMPLE
maximum.
Fig. 6 shows part of the circuit for a DC motor positioning system as use in a typewriter to control
four movements. It consists of a controller circuit
driving a smart power DMOS bridge with a single
current sensing output.
Motor current can reach a maximum of 1A and is
influenced by two control loops. The inner loop
limits the current by positive or negative peak
sampling of the reconstructed current information.
An exclusive OR gate inverts the bridge phase for
a maximum of one oscillator period, thus causing
the current to change its direction. This loop is not
delayed and therefore reacts very quickly. The
second loop operates in a conventional circuit as
a transconductance amplifier and converts an
input error signal into a proportional current. If the
difference between the measured value and the
set point is large enough to force the error amplifier into saturation, the inner circuit limits the acceleration of braking current to the permissible
The example circuits for sensing current and processing the signals shown in Figs. 1 to 6 are easily adaptable to other electromagnetic actuators
that receive a bidirectional feed. Microstepping
motors are a case in point, one in which inexpensive but nonetheless precise current control is
very much desired by every user. As power MOSFETS in the guise of discrete components or
smart power ICs become more popular, the techniques of sensing current in the source circuit
either directly by means of shunts or in directly as
sense FETs become correspondingly more important. The unavoidable errors caused by the
base current of the bipolar transistors used to
date thus become a thing of the past. Although
the gate source capacitance remains a potential
source of interference, its effect can be suppressed by analog or digital filters.
POTENTIAL APPLICATIONS
Figure 6:Part of a DC Motor Positioning Control Circuit.
119211N452-BB
5/5
----------------------------- ~~~~;~~:~~g -----------------------------
235
APPLICATION NOTE
A SOLID STATE BLINKER
FOR AUTOMOTIVE APPLICATIONS
by Sergio Ciscato
Using dedicated power ICs today it is possible to make a car blinker circuit without relays. The
benefits are simpler cablinng and better reliability.
Present car direction indicator system generally
use a dedicated integrated circuit as the SGSTHOMSON L9686 in conjunction with a relay to
control the flashing of the lamps. A high current
electromechanical switch is necessary to turn on
the right or the left direction indicator lamps; to
provide the emergency blinker feature a 3-pole
power switch is needed too (see Fig. 1).
The first disadvantage of this system is the high
number of power connections between the master module and the switches; in addition, the high
currents flowing through the switches and across
the relay contacts decrease their lifetime and consequently the reliability of the system.
Thanks to smart power devices is is possible to
implement a solid state car direction indicator
system (see Fig. 2), that solves these problems.
Figure 1: Traditional System
Figure 2: New Solid State System
EMERGENCY
...............
EMERGENCY
LEFT-OFF-RIGHT
1192L9686-81
AN454/0190
1192L9686-82
1/4
237
APPLICATION NOTE
CIRCUIT DESCRIPTION
The control device in the. system described here
is the L9686, but the relay is replaced by two
L9821 High Side Drivers; this device delivers up
to 25A peak output current with RON = 100mQ,
short circuits and thermal protection.
When a power devices is turned on, the local
supply voltage can drop several volt below its
nominal value because of the line inductance.
This voltage drop could cause disturbances to the
control logic that in some cases could produce
undamped oscillations on the suplly line itself.
To avoid these oscillations and to prevent EMI
disturbances, the L9821 was chosen as the
power device in this applications because of a
feature that limits the output current slew rate
(dildt) during the switching edges.
Fig. 3 and Fig. 4 show the rising and the falling
edges of the output current of an L9821 device
loaded with two 21 W lamps; the current level in the
first case is higher than in the second one because
of the inrush current of the bulbs (see Fig. 5).
Figure 3: Rising Edge of the Output Current
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Figure 4: Falling Edge of the Output Current
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2/4
---------------- ~~~~~~~~:~~~
238
-------------~
APPLICATION NOTE
Figure 5: Output Current Waveform
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Fig. 6 shows the complete schematic diagram of
master mo~ul.e: when 81 is closed (left or
right) the L9686 s Internal oscillator starts and pin
3 goes high; then the input voltage of one of the
two L9821 devices goes high too, resulting in the
lamps switching on. After a time equal to half of
the oscillation period pin 3 of the L9686 returns
low and the lamps are threfore switched off. The
flashing cycle stops and the circuit is reset to the
initial conditions when 81 is open.
The flashing frequency depends on the external
RC networkR1 and C1 according to the following
formula:
Fn = 1/ (1.5 x R1 xC1 (typ.)
t~e
R3. a~d C2 provid~ hysteresis to avoid spurious
sWitching of the oscillat?r comparator at every lamp
:urn o~; thiS ~yster~sls .IS not necessary if the
_9686 IS us.ed In conjunction with a relay, because
)f the relatively long delay time of this last one.
'lshunt senses the current flowing in the right or the
eft lamps (depending on the 81 position): when
)ne of the I~mps is defective the voltage drop
:!cross Rshun! IS reduced to a half and the failure is
ndicated by doubling the flashing frequency. 82
:!lIows the emergency blinker function: when it is
;Iosed the L9686 device drives, through the diodes
)1 and D2, both the L9821 smart switches and
hen both the right and the left lamps.
rhe emrgency blinker operation is monitored by
he flashing of both the dashboard lamps L 1 and
_2 while in normal operation only L2 flashes.
)VERVOLT AGE PROTECTION
\n L9821 device can withstand up to 60V load
lump transient. If a centralized overvoltage pro-
tection is not provided on the alternator it is
possible to increase the load dump capability of
this. application by placing a dedicated protection
device, such as a Transil, between the supply
voltage and the ground terminals. This transil
must withstand the double battery, a condition
often requested for the automotive equipment, so
a good choice is a device with at least 26V breakdown Voltage. The same protection device allows
the described application to withstand all the other
voltage transients. If a centralized load dump protection device is already present on the alternator a
small protection zener diode is sufficient to clamp
the low energy overvoltage transients due to the
disconnection of the several loads in the car. In this
cas~ the breakd~wn voltage of the local protection
device must be higher than the clamping voltage of
the centralized diode.
ADVANTAGES
Fig. 2 shows a possible wiring diagram of the described system in a car; the master module has
10 connections, compared to the four of the conventional system showed in Fig. 1, but from the
comparison between the two possibilities we can
see some advantages:
..
..
..
..
..
..
centralized wiring at the master module
less power connections
less power wire length
no power switches
no multipolar switch for the emergency blinker
short circuit protection between the lamps and
ground
.. inrush current limiting of the smart switches increases the lamps lifetime
3/4
239
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APPLICATION NOTE
REAR MIRRORS MULTIPLEXING USING L9946
by L. Valsecchi & S. Vergani
The application of the L9946 device in a real-world automotive multiplex system is described.
After a brief introduction to the multiplex concept, the hardware and software key points are discussed. It turns out that L9946 is very we/! suited for this kind of relatively complex applications.
THE MULTIPLEX CONCEPT
In this section a brief introduction to the basic
multiplex (MUX) concepts is given. Generally
speaking, a MUX is composed by a number of
units connected through a serial bus. There is a
set of meaningful serial messages and each unit
can recognise a subset of messages relevant to
it. Once a relevant message is received, the unit
performs an action according to the information
contained in the message. Usually an acknowledge technique is used, so that a bidirectional information flow between units can be established.
It is possible to draw a rough distinction between
MUX systems based on the communication
strategy. In increasing complexity order, a MUX
can be classified as follows.
1) MASTER-SLAVE:
One unit is qualified as master unit, and it is the
only one that can autonomously start a transmission. The other units (slaves) can transmit
only after the reception of a message out of a
defined set.
2) QUASI MULTI-MASTER:
As before, one unit acts like a master, but some
slave units can start an autonomous transmission
to the master. This happens usually when a significant event has occurred (e.g. a key has been
pressed).However, the slave units cannot communicate each other directly. The messages flow
is under the total control of the master unit.
3) MULTI-MASTER:
Every units can commuicate each other, and
there is no more a well defined master unit.ln fact,
the control, at a given time, is owned by the unit
currently autonomously transmitting.
The format of the serial messages, as well as the
characteristics of the physical interface of the bus
line are defined by a series of rules called the
PROTOCOL SPECIFICATION. These rules also
AN455/0392
define in details the behaviour of the transmitting
and receiving units when a situation of bus contention (i.e. when two units try to access the bus
simultaneously) occurs.
The ISO (International Organization for Standardization) has standarized, at various levels,
three protocols called CAN, VAN, J1850. This
means that documents exist as a reference to
achieve the compatibility between two systems
using the same protocol.
In fact, especially for slow speed data bus, custom protocols have been developed.
There are definite advantages in using a MUX
system in the automotive field. First, the number
of wires required to perform the same functions is
dramatically reduced. For example,with the MUX
approach, to connect a keyboard unit to other
units such as window lift motor control, rear mirror
control etc., only three (or four if a differential bus
is used) wires are required, independently of the
number of keys or motors used. This leads to a
reduction of costs of the harness of the vehicle.
Flexibility is another feature common to well designed multiplex systems.
The multiplex architecture allows a high degree of
freedom in the choice of the physical location of
the units inside the vehicle. For example, as long
as the serial bus line is provided, a control keyboard can be placed indifferently in the door or on
the dashboard without changing the vehicle wiring.
Furthermore, if a certain computational power (i.e.
a microcontroller) is located in the peripheral
units, the functional behaviour of the whole system can be defined by software so that upgrading and modification can be accomplished without
changing the hardware.
Also, a sophisticated diagnostic strategy can be
implemented. Usually one or more units collect diagnostic information that can be read by a tester
connected to the system when a car technical assistance is required. Such a tester generally includes a menu driven diagnosis procedure, lead1/8
241
APPLICATION NOTE
ing to easier fault detection and thus to shorter repair time.
Figure 1: System Block Diagram
REAR MIRRORS MULTIPLEX SYSTEM
INTRODUCTION
The application described here is an example of
how the L9946 can be used as a mirror controller
in a MUX system.
To explain in all the details a MUX system design
is beyond the scope of this application note. However, the key points in hardware and software design will be discussed in depth.
GENERAL DESCRIPTION
This MUX is composed by a keyboard unit, a left
mirror unit and a right mirror unit.
. The electronics is intended to be placed inside
the external rear mirror case, and inside the
physical keyboard. To achieve this, when
possible, devices available in small SO package
have been chosen. In this way, using surface
. mounting technique, very compact PCB layout
can be obtained.
The three units are connected through a differential bus.
Including power supply line and ground return,
only four connection wires are required, obtaining
a substantial saving compared to the traditional
solution, that requires eight wires.
The system block diagram is shown in fig. 1.
The functions implemented are:
L -_ _..,----'
"!J2f1N455-B4
- mirror plate movements
- open I fold
- wiper
The commands available are activated by 6 push
buttons located in the keyboard unit.
An additional three-way selector allows to switch
between the left or the right mirror. When this selector is in its central position, the only function
available is a simultaneusly mirroropen/fold
movement.
MIRROR UNIT DESCRIPTION
The block diagram of the mirror unit is shown in fig. 2.
The schematic diagram of the mirror unit is shown
in fig. 3.
The only difference between the left and right mirror unit is the position of a jumper that configures
the address of the unit.
Figure 2: Mirror Unit Block Diagram
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TWO WIRES
BUS
L9-946
ST6210
"!12f1N455-B5
-----------------------------
2/8
242
BUS LINE INTERFACE
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APPLICATION NOTE
In the following sections the main functional
blocks are described.
Protections
The units must be protected against a number of
possible anomalous voltages on the power supply
line coming from the battery.
This anomalous conditions are:
1} Reverse battery
2} Load dump
3} Short negative spikes
Voltage Regulator (L4949)
This device provides the five volts necessary for
the microcontroller and to the bus line interface. It
also provides to the microcontroller the correct
power on reset signal.
Microcontroiler (ST6210)
The microcontroller (uC) choosenfor this application is the ST621 0(1 K8 EPRPOM, 64 bytes
RAM).This is a 20 pin device, available in S020
package. The ST6 family is intended for low-medium complexity applications.
The heaviest task for the uC in this, or similar, application is the protocol handling, i.e. the reception and the transmission of the serial messages
on the bus.
Due to the low computational power and speed of
this uC, the protocol was chosen to be relatively
slow (3.3 kbits/sec) and the bit encoding was
chosen in such a way that the decoding algorithm
is tailored to optimize the hardware uC resource
usage.
In this case the uC also drives the L9946 and protects it against overcurrent and/or overtemperature reading back the dignostic signals DG1 and
DG2.
Mirror Actuator (L9946)
The L9946 in this application is used to drive the
four mirror motors: two. for the plate movements,
one for the open/fold movement and one for the
wiper motor. In this particular application the
wiper can be driven by· the high-side driver
thanks to a mechanical solution built into the mirror that performs automatically the wiper alternative movement.
Bus Line Interface
This is the circuitry that realize the physical interface between the unit and the bus line. Since the
functioning of the whole system relies on the correctness of the exchanged messages, the bus
line interface must be designed very carefully. A
complete discussion of the needed design criteria
is far beyond the scope of this application note.
A list of desirable features is:
a} High noise rejection
b} Line faults (short to GND or VCC, wire cut)
detection and real time recover.
c) High RF noise immunity
d} Low RF emission
The solution implemented here is a differential bus
line driven by two complementary MOS devices.
The passive components around the MOS polarize
and protect the devices against shorts, spikes and
negative voltages applied to the bus lines.
Capacitances placed on the bus lines filter out RF
noise, also reducing the bandwidth'of the bus channel in order to avoid too sharp edges during bus
transitions, i.e. RF emission and subsequently
possible interferencies with other equipment (dash- /'
board instrumentation, car radios etc.)
The three comparators in the RX section allow a
full fault detection and recovery. This means that
transmission and reception can continue also if
one line is shorted to GND or Vce or cut.
Figure 4: Keyboard Unit Block Diagram
TWO WIRES
BUS
KEYBOARD
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4/8
~
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244
BUS LINE INTERFACE
SGS-TlIOMSON _ _ _ _ _ _ _ _ _ _ _ __
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APPLICATION NOTE
been implemented so that a key transition is validated only if the new state has been stable for at
least fifty milliseconds.
KEYBOARD UNIT DESCRIPTION
The block diagram and .the schematic diagram of
the keyboard unit are shown respectively in fig. 4
and fig. 5.
Many blocks in the architecture of this unit are
very similar or identical to those used in the mirror
unit.
This blocks are protections, voltage regulator and
the bus line interface. The uC used is the same
adopted in the mirror units.
A 4 X 2 matrix-organized keypad is connected to
the unit. The schematic diagram of the physical
keyboard is shown in fig. 6.
Since the physical keyboard rows and columns
are directly connected to the uC pins, it must be
placed very close to the electronics to avoid induced noise. A software debouncing strategy has
Figure 6: Keyboard Schematic Diagram .
SOFTWARE DESCRIPTION
Introduction
Two different programs have been written, one
for the mirror units and one for the keyboard unit.
The software was developed using the ST6 hardware emulator, and the ST6 macroassembler and
linker. The mirror unit and keyboard unit programs are respectively about 1340 and 1280
bytes long. The main difficult in this software development was to overcome the uC limitations
(using some software tricks) without affecting the
overall program's readability.
.-----------~----------------~----------------~
MIRROR
SELECTOR
(AIGREY
LEFT ~
...-----(To
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6/8
--------------------------- ~~~~~~~~:~~ ---------------------------
246
APPLICATION NOTE
Mirror Unit's Software Description
The software developed for this unit can be
divided, at the functional level, into 3 main sections.
1) PROTOCOL HANDLER SECTION
This routines perform the serial bus message reception and transmission ..
The reception procedure starts when a vaiidSOM
(see BUS PROTOCOL DESCRIPTION paragraph) is detected. The reception ends successfully when the following conditions are obeyed:
a)Ten correct bits (i.e. with the right timing
between two edges) are decoded.
b)The received checksum field matches the
checksum calculated upon the preceding
eight received bits.
If an error occurs, the reception is aborted and
the unit starts to wait for a new valid SOM.
The transmission routine starts when the unit
must send a message on the bus line. The ST6
timer is used to obtain the desired time between
the edges.
Keyboard Unit Software Description
In the sotfware for this unit the protocol handler
section is the same code used in the mirror units.
The keyboard units acts like the master of the
system.
The matrix keyboard is scanned every five milliseconds. If no key status variation is detected,
every fifty milliseconds a stop message is sent to
the slave units as a polling. The slave units
should answer to this messages. If this is not the
case, the master unit knows that one or both
slaves are disconnected or broken.
When a key is pressed, a debouncing procedure
is started. If the pressure remains at least for fifty
millisecond the corresponding command message is sent to the unit selected by the position of
the three-way selector.
If this selector is in its central position, only the
fold/open command is enabled, and the subsequent command is sent to both slave units.
The keyboard unit keep sending the command
until the key is released. Then, the normal nooperation polling is executed.
2) MESSAGES DECODING AND ACTUATIONS
This section performs the message decoding and
the actual driving of the L9946.
Once a correct message is received, the mirror
unit compares the received address field with its
own address. If they are equal, the data field of
the message is decoded and the corresponding
action or series of actions are undertaken.
The data fields recognized by the mirror units and
their meaning are:
a1110 : wiper on
10000 : wiper off
01010 : fold/open
00010: up movement
00100 : down movement
001 to: left movement
01000 : right movement
10010 : stop motors
Immediately after the action has started, the mirror unit transmits an acknowledge message to the
master unit (i.e. the keyboard unit). This message
is the echo of the acknowledged reception.
BUS PROTOCOL DESCRIPTION
1. GENERAL
The information between the units is passed in
messages transmitted serially on the bus connected to all the units.
When the bus is in the idle state, i.e. no message
is transmitted, its state is called "passive state". It
is driven in the "active state" by a transmitting unit
at the start of a message for the "start of message" time.The state is passive for the first (most
significant bit) information time, active for the next
bit time and so on until the message is finished
(terminated) in the passive state. The value of the
bit is determined by the time elapsed between
two consecutive transition of the bus state. This
bit encoding is called VPWM (variable pulse width
modulation).
3) L9946 PROTECTION
The L9946DGl and DG2 pins are connected to
uC interrupts lines so that a fast switch off is executed when an overcurrent or an overtemperature occurs in the device.
2.1. START OF MESSAGE
This symbol appears at the start of every message when a transmitter drives the bus in the active state to start the message.
2. MESSAGE SYMBOL WAVEFORMS
The following sections show the nominal timing
requirements of the VPWM message simbols
generated by the software protocol handler as
they appear on one wire of the bus. On the other
bus wire the signal is inverted.
"SOM""
11<-1___
->l,1
8:..::G.::.Bu=-:sc::.e.=.c_ _
t192AN4S5-01
________________________ ~~~~~~~~:~~ ___________________________7__
/8
247
APPLICATION NOTE
2.2. DATA BIT
Each data bit is represented by the time between
two consecutive transitions. These are both
passive and active bit states that are used alternately.
2.2. "0" BIT
The two "0" bit waveforms are:
-e-
~
r-or J80~s~
C=:=J
400usec
11<--·~->I'I
n92f1N455-B2
2.3. "1" BIT
The two "1" bit waveforms are:
"1"
~
~
0
r
-------.l.L·
11<-.
~
f132Aff455-B3
8/8
48Busec
3. MESSAGE FORMAT
A message consists of a start of message (SOM)
field, an address (ADR) field (3 bits), a data
(DATA) field (5 bits) and a checksum (CHK) field
(2 bits), for a total of 10 bits transmitted.
With the timing given in the above sections, the
average transmission bit rate is 3.3 Kbps.
The SOM is the signal on wich every receiving
unit starts the reception procedure.
Once a successful reception has been completed,
the DATA field is decoded and the related action
undertaken only if the ADR field matches with the
wired address assigned to the receiving unit.
The CHK field is a way to detect some type of errors occurred during the DATA field bits transmission. During the reception procedure, a checksum value is calculated, and the reception is valid
only if this value is equal to the contents of the received CHK field.
The algorithm used to calculate the checksum is
the following.
a) Count the number of "1" bits in the DATA and
ADR fields.
b) Take the two less significant bits of this number.
c) Complement these bits.
----------------------------- ~~~~~~~~:~~~ ----------------------------248
APPLICATION NOTE
6A DOOR LOCK MOTOR DRIVER FOR AUTOMOTIVE
by Stefano Vergani
An application of the L9937 device (Full Bridge Motor Drive) is described. The interface between
the L9937 and a j.lC is discussed. A complete protections circuitry description is also given.
Figure 1.
VCC~~r-r-----uu~~=;==~-------------------------------------15K
B.luF
I
5U
OUlJ
AID
[N2
11
18
SC
UD
18BK
a:
""
N
0.
o
-'
1i
EN
2BK
IK
N
>-
'"
L9937
5.1K
[Nl
Ubat
3.9K
lK
t1!J2L9!J:J?-Btfi
The L9937 device is a full bridge for bidirectional
motor driver applications realized in bipolar technology; it can deliver up to 6A output current with
low saturation voltage.
Two diagnostic informations are provided to monitor overload conditions and the internal temperature, and the device is assembled in the MULTIWATT-11 package with the case connected to the
ground terminal.
The L9937 is particularly suitable to drive bidirectional DC motors in j.lC based systems.
Fig. 1 shows a possible application circuit, with an
analog interface between the power devices and
the j.lC.
AN456/0191
In the following, the functions of each block of the
analog interface are described.
1 - Overvoltage And Reverse Battery Protection
L9937 is particularly· suitable to drive the door
lock motors in automotive applications. Fig. 2
shows the circuit schematics; due to the hostile
automotive environment, it is necessary a transil
(suggested type LDP24A) between VD and GND,
to protect the L9937 against overvoltages higher
than 50V. The diode D1 suggested type BY239200A) supplies the voltage VD necessary for the
correct device's operation at the same time it
protects the device against the reverse battery.
1/5
249
APPLICATION NOTE
Figure 2
OF
2 - Switch-off Sequence
Referring to Fig. 2 and supposing i.e. T1 and T4
ON, T2 and T3 OFF (this means EN=H IN1=H
IN2=L), the following steps have to be observed
to allow a correct recirculation of the current in the
motor at the switch off (Ref, Fig. 3):
a) switch off T1 and wait for 100llS about in
this condition (EN = L IN1 = H IN2 = L)
b) after the a.m, delay switch ON T2 (EN = L
IN1 = H IN2 = H)
c) switch off both T2 and T4 after the motor
stop (EN = L IN1= L IN2 = L)
Step a) allows the recirculation of the motor cur-
11'11
IN2
EN
1192L993?-82f1
rent due to the inductive component of the motor
itself between DS1 and T4; the 100llsec delay
time is needed to avoid the cross-conduction in
the left half bridge.
In step b) the motor is short circuited to GND (T2
and T4 ON) and this allows the dynamic braking.
In step c) T1, T2, T3 and T4 are OFF to allow a
very low current consumption of the bridge.
If the dynamic braking is not requested, step b)
can be omitted. In any case the lower power transistor of an half bridge must be kept ON, after the
switph off of the upper transistor of the other half
bridge, for a time longer than T = 5 ',RLlLL, where
RI and LI are the resistance and the Inductance of
the load.
Figure 3: Switch-off Sequence
TURN-OFF
•
EN
11'11
IN2
..........
lJ...-___________+
.... , .....:..............
~t
1-------'-1)1............. ~
1BBus : :
t
t
BRAKING
~.~:~:.~-~~----~.:
11!J2L993?-B3
_2/_5_________________________
250
L~1 ~~~~~:oo~~-----------~------------
APPLICATION NOTE
3 - Input Driving Voltage
To allow a correct operation of L9937 over the full
t~mperature ra~ge, the driving voltage at the input
pins must be higher than 5.5V, with 4mA current
capability.
4 - Short Circuit Protection
It is possible to protect L9937 against short circuit
to ground and across the motor in the full bridge
application.
The circuit schematics shown in Fig. 4 uses two
voltage comparators (U1A, U1B) to detect the
Vce of the upper power transistors. U2A and U2B
are open drain NAND gates (Le. part no.
HCC40107) and U3A1B/C/D are non inverting
buffer to drive the L9937 (Le. part no.
74HC4050).
U1 A and U1 B sense the differential voltage VDOUT2 and VO-OUT1 respectively. Referring to
Fig. 4, chosen R1=100K and R2=20K, the values
of R3 and R4 may be calculated according to the
following formula:
R3 = (Vo- VCETH) - 0.166 Vo)
0.166Vo
* R4
where:
Vo = bridge power supply
VCETH = collector to emitter detection threshold.
Figure 4
Choosing:
VCETH = 2V @ Vo = 12V and R4 = 1K, the above
formula gives R3 = 4K.
When al~ signals from IlC are at low level (motor
off), the Inputs to the bridge are low too' in these
conditions the output voltage of the two bomparators is high and therefore the outputs of U2A1U2B
are free. yvhen the fIC sends, for example, IN2
and EN high, OUT2 of the bridge goes high and
OUT1 goes low.
~t this point the output of U1A pulls down the
Input of U2A before that the delay capacitor C1 is
c~arged (through R5) up to the U2A threshold; in
thiS way the U2A output remains free and the
bridge drives the motor.
If a short circuit occurs, the Vce of the upper
power transistor increases above the threshold
and then the U2A output pulls down the enable
input of L9937. At the SOME time the SC signal
to fIC, high in normal conditions, goes low; at this
point the fIC executes the switch-off sequence.
We have just explained what happens when a
short circuit occurs during the motor running
phase. Another faulting condition occurs switch!ng (:In the bridge. whe~ a short circuit is present;
In thiS case the bridge IS driven for a time depending on the time constant R5 • C1 = R6 • C2.
Choosing R5 = R6 = 3.3K and C1 = C2 = 1nF
then the time constant will be T = 3.3fIsec, that i~
5~sec about delay time. Longer delay time
might allow the short circuit current to reach
values beyond the absolute maximum ratings.
!--_t_-oUOO
11!12L!1!13?-84f1
TO L9937
-------------L'11 ~~~~~gr::oo~lt ____________..:.31-..:,5
251
APPLICATION NOTE
Figure 7
5 - Thermal Protecti.on
The L9937 has 5 built-in diodes series-connected
that can be used to implement a thermal protection for the device.
Fig. 5 shows the relationship between the voltage
across the diodes and the temperature at 1OO~A
diode current.
Figure 5
LEGEND
1SB·C-2.4S2U
12S·C-2.679U
1BB·C-2.9B8U
7S' C-3.136U
SB·C-3.361U
2S·C-3.S89U
B·C-3.8B2U
-2S·C-4.B13U
-SB·C-4.227U
(U)
5
4.5
~
..........
...................
3.5
3
..............
............
2
-58 -25
8
25
58 75 188 125 • C
Fig. 6 shows the simplest solution to do a thermal
protection; an AID converter of the ~C is used to
detect the voltage drop across the 5 diodes. The
15K resistor sets the current in the diodes and the
1OOnF capacitor acts as a filter against the noise.
When the ~C detects a voltage lower than the low
threshold chosen according to the diagram in
Fig. 5, it executes the switch-off sequence and rejects any command to the bridge until the diodes
voltage increases beyond the high threshold. The
recommended hysteresis value is 30'C.
Figure 6
5U,
6 • Overvoltage Protection
At point 1 we suggest a way to proted the L9937
against the voltage transients. This protection
allows the device to withstand overvoltages only
if the bridge is not operating. To protect the device against the overvoltages in all the operating
conditions it is possible to implement the circuit
shown in Fig. 7.
(Note: A-8 are connected to the nodes between
--------------L",
252
>-+-...,....~--+
N92L993?-B511
i'--. .......
Id.1BBuFi
6U/AT.8.8mU/·C
Ud2S·C.717mU
2.5
4/5
C....,~--I-t
ouu
1185L5536 - 81
Udiodes
4
UCC
FI
B
R3 and R4 (left side and right side) in Fig. 4; C is
connected to the node between R1 and R2 in Fig. 4).
When Vo reaches 18V the comparator output
pulls down A and 8, causing the intervention of
the hardware protection showed in Fig. 4; atthe
same time the OVV signal is sent to ~C, which
executes the switch off sequence. The ~C must
reject any command to the bridge during the overvoltage conditions.
With the values shown in Fig. 7, a 1V hysteresis
is provided.
It is possible to enhance the performances of the
system just described avoiding the braking of the
motor also for short duration voltage transients; to
do this the ~C, once received the overvoltage diagnostic signal (OVV), put at low level the
enable of the L9937, confirming the hardware
switch-off of the motor; in this condition an output
of the half bridge is in high impedance state and
the other one is low, allowing the recirculation of
the current and the free running of the
motor.
The system holds this condition until OVV is active; when the OVV signal is released the ~C
resets the hardware protection, sending EN = IN1 =
IN2 = L and then restore the previous command to
the bridge.
It is mandatory, however, to wait for the complete
current recirculation of the motor before to reset
the hardware protection; in facts, when EN = IN1
~ IN2 = L both the L9937 outputs are in high impedance conditions.
7 - Diagnostic Feedback Output
DF piri is an open drain output to monitor overcurrent and overtemperature conditions.
The overcurrent detection threshold is inversely.
dependent from the temperature of the chip.
Typical application of this function is to send the
DF signal, with an external pull-up to Vcc, to a
digital input of the ~C; when the DF signal goes at
low level, the ~C executes the switch-off sequence.
~~~~m~r::oo~::
-------------
APPLICATION NOTE
L9937 IN A BODY MULTIPLEX ENVIRONMENT
All the functions described above can be implemented in a custom integrated circuit together
with a bus transceiver and a protocol handler.
It is then possible to obtain a very small size module that 'can be integrated directly in the actuator. Fig. 8 shows a typical application of these
modules as peripheral units in a "Class A" wired
Multiplex System,
Figure 8: "Class A" Wired Peripheral Application
............... --- ..... .
ANALOG
INTERFACE
BUS RXITX
PROT.HANDL.
ANALOG
INTERFACE
BUS RXITX
PROT.HANDL.
ANALOG
INTERFACE
BUS RXITX
PROT.HANDL.
BUS
1f92L993?-B?
--------------L"fl
~~~;~~::O!~n
-------------5/5
253
APPLICATION NOTE
DRIVING DC MOTORS
By G. Maiocchi
INTRODUCTION
Driving DC motors with integrated circuits seems at
first to be rather simple. Yet by analyzing the actual
application it is possible to see if there exist conditions causing stresses to the IC during operation
which in the end can cause failure. With proper de-
sign and analysis in critical applications it is possible
to avoid conditions which lead to IC damage.
GENERAL CONSIDERATIONS
Figure 1 illustrates driving a DC motor using a power
MaS bridge.
Figure 1.
Us
TO THE CHOPPING
CONTROLLER ---~
CURRENT DIRECTION
-----. Cl.C4.0N
+- - - C2. Q3.0N
N89L6283-12
C2.C3.0FF
C1. C4.0FF
By driving the four MaS in the correct sequence the
direction of current flow through the motor is
reversed, consequently reversing the direction of
the motor's rotation. The motor torque is a function
of the current amplitude, the motor's internal parameters, and the external load. The resistive torque
is dependent on the motor's internal friction. The
current level can be controlled with current chopping. The controller checks the current level by
monitoring the sense resistor voltage and then
drives the appropriate power MOS. On the other
AN281/0189
hand this means that when current does not flow in
the sense resistor (which we will examine during recirculation) it is not possible to measure the current
level and thus limit it.
Figure 2 shows a more general application circuit
which includes an external control loop. Data relating to the actual motor speed is transmitted to the
controller by the system which stabi!izes the current
in the bridge as a fun,ction of the requested rotation
velocity. In this case also the current is limited
through chopping.
1/8
255
APPLICATION NOTE
Figure 2.
11'11
DRIUE (
11'12
OUTPUT
EN
CONTROLLER
OUTt
OUT2
CURRENT
FEEDBACK
FEEDBACK (
Rs
INPUT
SPEED FEEDBACK
1189L6283-13
Electrically a DC motor can be viewed as a series
RL network with a voltage generator V(ro). The generator represents the back electromotive force
(BEMF) generated by the motor's rotation and which
opposes the electromotive force of the supply.
The value of the BEMF is a function of the motor's
angular velocity. If the motor has no external load
and its velocity is not limited, it will accelerate up to
the velocity w such that V(w) equals the supply voltage Vs. In this situation the two EMF's cancel each
other and thus the motor torque responsible for acceleration will go away. In reality V(ro) is always
slightly less than Vs in which case a small motor
torque is necessary to compensate resistive torque
due to internal friction.
Thus it can be seen that the motor's BEMF can
reach elevated values which in some cases can creFigure 3a : Two Phase Chopping.
2/8
256
ate application problems due to a certain type of
stress.
RECIRCULATION CURRENT
Part of the energy delivered to the circuit by the supply is stored in the motor's inductance. When an inductive load is driven, during chopping and during
inversion of the diagonal of the bridge, there is always some. recirculation current which allows this
energy to discharge.
The following figures show the resulting current
paths based on the type of chopping method used.
In the first two cases, "two'phase" and "enable"
chopping, the current decays quickly and, is thus,
fast recirculaiion. When "one-phase" chopping is
implemented the current requires a longer time period to decay and, is thus, slow recirculation.
APPLICATION NOTE
Figure 3b : Enable Chopping.
~o.,
~-----t--
Figure 3c : One Phase Chopping.
~"., :',~ ~.,
'--------+--
DYNAMIC BEHAVIOUR
The driving of a DC motor will be analyzed dynamically during different motion phases. Fundamental
to the working conditions of the IC is the type of load
which the motor is driving. In fact if the load is frictional, the deceleration phase is not particularly serious for the IC since the load itself is supplying a
braking torque. However, when the load is inertial it
will appear to the IC to be a motor torque generator.
This could take the IC into critical operating conditions which can incur failure.
- Acceleration Phase: The current rises, delivering
a torque which allows the motor to accelerate, up to
the maximum velocity or till it is stabilized by the controlloop. The type of load essentially determines the
required current.
-Constant Velocity: In this case the required velocity is less than the maximum. The current is limited
by chopping. This can be done by turning ON and
IN1 =H
IN2 = H
EN =H
OFF a MOS of the diagonal which is in conduction.
- Deceleration: When a DC motor must be decelerated, the type of load being driven becomes important. As previously stated, in the case of a
frictional load, the load is essentially braking the
motor. Thus, in general, it could be sufficient to cancel the motor torque by opening the bridge (i.e. disable the driver). In the case of an inertial load,
however, the braking torque is provided by the
driver. It is this situation that is of most concern.
Since every change of direction involves a braking
phase, a detailed analysis of this situation will be
done.
ROTATION INVERSION
Initially the current flows in one direction as shown
in figure 4. Figure 5 illustrates the situation when the
diagonal is switched. The motor's inductance discharges the stored energy by fast recirculation
through diodes D2 and D3.
3/8
257
APPLICATION NOTE
Figure 4.
Figure 5.
Us
Us
~F
D~
o~
~F
o~
The inertial load of the motor, which can be viewed
as a flywheel, has stored energy during the phase
prior to inverting the diagonal. This energy is reo
turned to the motor providing a motor torque which
keeps the motor rotating. Greater still is the fly·
wheel's moment of inertia, greater than the motor
torque that it provides to the motor. The discharge
time is longer because the flywheel must discharge
its energy. Also associated with the motor's rotation
is the BEMF. Thus, in order to stop the motor a brak-
ing torque must be applied. This is generated when,
following completion of slow recirculation, the current begins to flow in the opposite direction from the
previous state.
It is precisely at this point which effectively the braking phase begins. When the sense voltage rises to
the preset level chopping is triggered. In figure 6
chopping results in slow recirculation (in practice the
motor is short-circuited).
Figure 6.
Us
~F
D~
NB9L62B3-16
4/8
258
APPLICATION NOTE
As it can be seen, the BEMF is dropped across the
relatively low resistances of the motor, the diode in
line and the MOS that is ON. The sense resistor does
not enter into this. If the motor's rotational velocity remains high the recirculation current could be very
large, enough to damage the IC. Actually the current
does not rise instantaneously to the steady state
value of : I = V(m)/(Rm + Rd + Rdson). Rather, the
current follows the graph shown in figure 7. In fact,
when chopping begins the sense current goes to
zero, thus tuming MOS M2 ON again~ The motor current flows through the sense resistor, re-enabling the
chopping. The cycle repeats in an iterative manner
with a recirculation current that continues to rise.
Due to the inertial load and the BEMF it generates
and the recirculation current as described above,
the current in the sense resistor will be greater than
the desired value set by 1m = Vref/Rsense. When
the current reaches the maximum level (see previous paragraph) the current will fall to the preset
level controlled by the chopping, the inertial load
having discharged its energy from the previous
phase. This elevated current level is temporary, but
can be damaging to the IC.
Figure 7.
I
I
I
I
I
I
I
I
I
I
....
t
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
t.t
f189L 6283 - 1?
[caption for figure 71
I = recirculation current
delta t = time interval during which current flows through Rsense.
Braking the motor by short-circuiting it involves an
accurate study of the mechanical system during the
design phase. Knowing the value of the BEMF
generated by the motor during braking, the motor
resistance, and the equivalent resistance of the
MOS and diode involved during recirculation it is
possible to determine the recirculation current and if
it is less than or greater than the maximum value
that the IC can tolerate.
5/8
259
APPLICATION NOTE
Figure 8.
Us
DIRECTIDNS~~;========1)-1-__i-1>
ENABLE
+5V
n89L6283-18~
If the recirculation current is too high it will be necessary to brake the motor with an alternative method.
Using fast recirculation in combination with slow recirculation it is possible to brake the motor. Even if this
is less than an efficient manner it avoids causing damage to the IC due to overcurrent. The basic circuit is
shown in figure 8. Figure 9 is the application circuit
which the Application Lab of Agrate, experimented
with. This circuit uses an L6203 as the power driver.
As seen in figure 8, as long as the recirculation current does not reach too high a value slow recirculation is used (one-phase chopping). Above a critical
threshold slow recirculation is replaced with fast recirculation achieved by enable chopping. The slow and
fast recirculations are triggered by two different reference voltages which determine the two current level
thresholds. The higher current level for triggering fast
recirculation is set little below the max current level
available by the IC.
6/8
260
Figure 10 is the current waveform observed on the
oscilloscope during few diagonal inversions. In this
figure we can see the general trend of the motor current during three inversions of the rotation. A more
detailed view of what really happens to the motor
current is showed in fig. 11. Before the rotation inversion the motor is sinking its steady state current
(about ± 250mA in this application, the sign depending from the current flow direction). At the rotation
inversion, first the current rises, as previous described, to the current level defined by Iref2. At this
moment ENABLE chopping is activated starting the
fast recirculation and the current level is clamped at
this reference current level. When the motor has
dissipated a sufficient rate of its inertial energy, the
current falls down, first to the level defined by Iref1
(slow recirculation) for all that interval time that is required to dissipate the remaining inertial energy and
then to its steady state working level.
APPLICATION NOTE
Figure 9.
Us,,35Umax
uc:c-su
DIRECTION
:J: 3.3nF
U5pced=2Umax
Ref 1
Speed
4
ENRBLE
ION/OFF)
2
3
R1
2.2K
17
L6585
14
5
12
11
13
7
19 R4
18K
15
Uc:c .. 5U
IN 1
")
3
J" " "
EN
IN 2
L52B3
R3
lBK
R5
8.SQ
18
15nF
D2
6
ffBBL6283-S6
Figure 10.
VERT.2NDIV
HOR.100ms/DIV
Three diagonal inversion of a unloaded
DC motor
This scheme prevents damage to the IC due to overcurrent. However, failure due to overvoltage is still
possible. An inertial load will return energy to the
supply. If the power supply is the type which cannot
sink current but can only source current, then the
eflergy from the motor will load the power supply capacitor to a voltage above Vs. If the capacitor value
is not large enough, during recirculation the capacitor voltage will rise rapidly. Meanwhile, the lower ac-
tive diode is below ground during recirculation.
.There is a differential voltage between the overvoltage and the point below ground. If this exceeds the
absolute maximum voltage of the IC, damage can
occur. Overvoltage can be limited with an appropriate value of power supply capacitor. For the below
ground condition of the lower diodes, the sources of
the upper MOS can be clamped to ground with
schotky diodes.
7/8
261
APPLICATION NOTE
When Vs is relatively low it may be sufficient to control the differential voltage drop by just limiting the
overvoltage with the power supply capacitor and not
having to use the schottky diodes. The feasibility of
this solution should nevertheless be verified experimentally in the specific application.
Figure 11.
IMOTOR
I
, IMAX TENOENTIAL
" " , / TREND
"v
IR EF2
vr
I
REFl
V
II
CLOCK
8/8
262
,
-~
-"'"
NB9L62B3-19
t
APPLICATION NOTE
APPLICATIONS OF MONOLITHIC BRIDGE DRIVERS
High power monolithic bridge drivers are an attractive replacement for discrete transistors and half bridges
in applications such as DC motor and stepper motor driving. This application guide describes three such devices - the L293, L293E and L298 - and presents practical examples of their application.
The L293, L293E and L298 each contain four pushpull power drivers which can be used independently
or, more commonly, as two full bridges. Each driver
is controlled by a TTL-level logic input and each pair
of drivers is equipped with an enable input which
controls a whole bridge. All three devices feature a
separate logic supply input so that the logic can be
run on a lower supply voltage, reducing dissipation.
This logic supply is internally regulated.
Additionally, the L293E and L298 are provided with
external connections to the lower emitters of each
bridge to allow the connection of current sense resistors. The L293E has separate emitter connections for each channel ; the L298 has two, one for
each bridge.
Figure 1 shows the internal structure of the L293,
L293E and L298. The L293 and L293E are represented as four push pull drivers while the intemal
schematic is given for the L298. Though they are
drawn differently the L293E and L298 are identical
in structure; the L293 differs in that it does not have
extemal emitter connections.
Figure 1 : The L293, L293E and L298 contain four push pull drivers. Each driver is controlled by a logic input
and each pair (a bridge) is controlled by an enable input. Additionally, the L293E has external
emitter connections for each driver and the L298 has emitter connections for each bridge.
Vss
ENABLE A
IN 4
IN,
ENABLE A
L293
16
V55
IN4
INI
OUTI
OUT4
OUT 2
OUTl
OUT 4
OUT'
SENSE'
SENSE 4
SENSE 2
SENSE 3
OUT 3
OUT 2
INl
IN 2
v.
ENABLE B
S-!l792
IN 3
IN2
ENABLEB
V.
S-!l661
AN240/1288
1/10
263
APPLICATION NOTE
Figure 1 (continued).
12
In4
In3
EnB
The L293 is packaged in a 12 + 4 lead POWERDIP
package (a 16-pin DIP with the four center leads
used to conduct heat to the PC board copper) and
handles 1A per channel (1.5 peak) at voltages up to
36 V.
Figure 2 : For higher currents outputs can be paralleled. Take care to parallel channel 1
with channel 4 and channel 2 with channel3.
The L293E, also rated at 1 N36 V, is mounted in a
16 + 4 lead POWERDIP package. A 15-lead MULTIWATT plastic power package is used for the L298N
which handles up to 2A per channel at voltages to
46 V.
All three devices includes on-chip thermal protection and feature high noise immunity. The high
switching speed makes them particularly suitable for
switch mode control.
Vs
IN!
IN Z
PARALLELING OUTPUTS
Higher output currents can be obtained by paralleling the outputs of both bridges. For example, the
outputs of an L298N can be connected in parallel to
make a single 3.5 A bridge. To ensure that the current is fairly divided between the bridges they must
be connected as shown in figure 2. In other words,
channel one should be paralleled with channel four
and channel two paralleled with channel three.
Apart from this rule the connection is very straightforward - the inputs, enables, outputs and emitters
are simply connected together.
5-5873/2
The outputs of an L293 or L293E can also be paralleled - in this case too channel 1 must be paralleled with channel 4 and channel 2 with channel 3.
But if two bridges are needed this is not a good idea
because an L298N may be used. However, if only
2/10
264
Vss
APPLICATION NOTE
one bridge is required an L293 connected as a
single bridge may be cheaper than an underutilized
L298N.
SHORT CIRCUIT PROTECTION
L293 and L298N drivers can be damaged by short
circuits from the output to ground or to the supply.
Short circuits to ground are by far the most common
and can be protected against by the circuit shown
in figure 3.
low after a delay of roughly 10 ~s, a period determined by the RC time constant. The upper transistor of the output stage is thus turned off, interrupting
the short circuit current. When the short is removed
the circuit recovers automatically. This is shown by
the waveforms of figure 4.
Note that if the short circuit is removed while V1 is
high the output stays low because the capacitor C
is charged to VIH. The system is reset by the falling
edge of V1, which discharges C.
When the output is short circuited the input is pulled
Figure 3: This circuit protects a driver from output short circuits to ground.
R:l0Kn
Figure 4 : Waveforms illustrating the short circuit protection provided by the circuit of fig. 3.
J)r v
ooce
Tsc ~l0.us
~==OL~_---LI_+====VOL=====I
t
SHORT CIRCUIT
~
SHORT CIRCUIT
REMOVED
_ ~B65
DC MOTOR DRIVING
remember when minimising control logic.
In application where rotation is always in the same
Each device can drive four motors connected in this
way. The maximum motor current is 1A for the L293
and 2A for the L298N. However if several motors
are driven continuously care should be taken to
avoid exceeding the maximum power dissipation of
the package.
sense a single driver (half bridge) can be used to drive
a small DC motor. The motor may be connected either
to supply or to ground as shown in figure 5.
The only difference between these two alternatives
is that the control logic is inverted - a useful fact to
3/10
265
APPLICATION NOTE
Each motor in this configuration is controlled by its
own logic input which gives two alternatives : run
and fast stop (the motor shorted by one of the transistors).
Figure 6 : A bridge is used for bidirectional drive of
DC motors.
The enable/inhibit inputs also allow a free running
motor stop by turning off both transistors of the
driver. Since these inputs are common to two channels (one bridge) this feature can only be used when
both channels are disabled together.
c
A full bridge configuration is used to drive DC motors in both directions (figure 6). Using the logic inputs of the two channels the motor can be made to
run clockwise, run anticlockwise or stop rapidly ..
+Vss
L_-'===:;:::;:;;:;;;:::;;~=:f--D
Figure 5 : For rotation in one direction DC motors
are driven by one channel and can be
connected to supply or ground.
Function
Inputs
Vinh
C=H ;
D=L
Turn Right
= H C = L;
D=H
Turn Left
I
I
V inh
16
+Vss
L_---.:==::;:::=:;::::~===:f--OVinh
5-5163/1
Vinh
A
M1
B
H
H
Fast Motor Stop
H
Run
H
L
Run
L
Fast Motor Stop
L
X
Free Running
Motor Stop
X
Free Running
Motor Stop
L = Low
H = High
M2
X = Don'l Care
Again, the enable/inhibit input is used for a free runni[lg stop - it turns off all four transistors of the bridge
when low. A very rapid stop may be achieved by reversing the current, though this requires more careful design to stop the motor dead. In practice a
tachometer dynamo and closed loop control are
usually necessary. Like the previous circuit, this
configuration is suitable for motors with currents up
to 1A (L293/L293E) or 2A (L298N).
The motor speed in these examples can be controlled by switching the drivers with pulse width modulated squarewaves. This approach is particularly
suitable for microcomputer control.
For undirectional drive with a single channel. the
4/10
266
Fast Motor Stop
C=D
A.
=L
L = Low
Vinh
.L4.5,12 ,13
s- 5165
C =X;
D=X
H = High
Free Running Motor Stop
X = Don't Care
PWM control signal can be applied to either the
channel input or the appropriate enable input. In
both cases the recirculation path is through the suppression diode and motor, giving a fairly slow decay.
From a practical point of view it is preferable to control the channel input because the circuit response
is faster. This is very convenient because each
channel has an independent input.
The situation is different for bidirectional motors
driven by a bridge. In this case the two alternatives
have different effects. If the channel inputs are
driven by the PWM signal, with suitable logic, the re~
circulation path is through a diode, the motor and a
~ransistor (figure 7a), givind a slow decay. On the
other hand, if the enable input is controlled the recirculation path is from ground to supply through two
diodes and the winding. This path gives a faster
decay (figure 7b).
Figure 8 shows a practical example of PWM motor
speed control. This circuit includes the oscillator and
modulator and allows independent regulation of the
speeds of the two motors. The channel inputs are
used to control the direction.
An interesting feature of this circuit is that it takes
advantage of the threshold of the enable/inhibit
input to economise on comparators. The TBA820M
audio amplifier generates triangle waves, the DC
APPLICATION NOTE
level of which is varied from
P1 and P2.
a to
5 V by means of
Since the switching threshold of the L293's enable/inhibit inputs is roughly 2 V the duty cycle of the
output current (and hence the motor speed) is controiled by the setting of the potentiometer.
In this circuitthe switching frequency is set by R 1/C1
and the amplitude of the oscillator signal is set by
the divider R2/R3.
Figure 7a : If the current shown by the solid line is interrupted by bringing A low the current recirculates rou nd
the dotted path. Decay is slow.
Vs
A ---.----/
INH
--~--------++---------~
Figure 7b : If the enable input is brought low to interrupt the current indicated by the solid line the current
recirculates from ground to Vs and the decay is faster.
A-_--;
INH
J----2""
In this case too, the variation 6 n is as much lower
as the error amplifier gain is higher. With the circuit
shown in fig. 26n is approximately 30 turns/min. with
6 I = 800 mA, 6n = 0.037 turns/mA.min approx.
It is possible to adopt a circuit which prevents the
variation in the number of turns in function of motor
current. The problem is to "sense" the current flowing through the motor and to send a current proportional to it to the sum point of the error amplifier. The
complete circuit which includes, beside the voltage
feed-back loop, also a current feed-back loop, is illustrated in fig. 4.
In the integrated circuit L292, a current proportional
to the mean current drained by the motor flows between pin 5 and pin 7.
An operational amplifier amplifies the voltage drop
provoked by this current across a 51 0 Q resistor and
sends a current to the sum point which is consequently proportional to the mean current in the
motor, the value of which can be made vary by acting on potentiometer P2. By properly adjusting P2,
a condition can be achieved in which the speed does
not change when the current drained by the motor
varies.
The discontinuity around the origin, which was present in the previous circuit (fig. 2), is practically negligible in the circuit shown in fig. 4.
The characteristic n = f (Vi) relevant to the circuit of
fig. 4 is shown in fig. 5, and this characteristic does
not substantially change over the whole range of
currents allowed by the L292 (up to 2A).
In the circuit described above if the motor stall condition is requested. It is preferable to act on the inhibits of the integrated circuit L292, for instance by
grounding pin 13, instead of adjusting potentiometer
P1 : as a matter of fact, the exact position of this
potentiometer is difficult to obtain, since the characteristic crosses the axis Vi in one only point (this
mean that n is only 0 for a very narrow interval of
Vi).
3/8
275
APPLICATION NOTE
Figure 4 : Complete Circuit with Current Feedback.
Rl
1.1Kn
3.3Kn
:1.
1 pF
0.1
n
1K
01
Figure 5 : Output Characteristics of the Circuit in
fig. 4.
(rpm)
/
'600
1200
BOO
+
04
{
VF'; 1.2 V @ I
trr ,; 200 ns
-6
_2
2
4
6
A simplified circuit diagram is shown in fig. 6.
Figure 6 : Simplified Circuit Diagram (digital
control).
8
10 Vi(V)
.toOO
."",
Im=200mA;. 2A
_1200
-1600
SYSTEM WITH DIGITAL CONTROL
In this system the speed information is given to the
circuit by a binary code made up of 5 information
bits plus one sign bit, which determines whether the
4/8
276
2A
movement shall the clockwise or counter-clockwise.
For the circuit implementation, the integrated circuits L291 (which includes a D/A converter and two
operational amplifiers) and L292 are used.
--:-:---::---:-----:--71'-----::-----.-8
=
Rl
APPLICATION NOTE
The current value i1 depends on the value of Irel and
on the value of inputs b1 through bs, where its sign
depends on the bs input.
The maximum value for i1, which is obtained whenever inputs b1 through bs are low, is :
31
i1
max
= Irel ----:r6 =
31
Vrel
-~
16
In order to have the system in a steady state condition (no current drained by the motor), it must be :
11
=-
12
By imposing the balance condition at the maximum
speed, one obtains: i1 max = - 12 max
V reI
-R-1-·
31
~
=
where
Kg = dynamo's voltage constant
nM
= maximum speed preset for the motor.
The current Iref, and consequently the ratio Vref/R1,
must lie within a certain range imposed by the D/A
converter actually used.
In our case, this range is 0.3 to 1 mAo The values of
R1 and R2 can be determined from the previous relationship. The same considerations made in the description of the DC control system apply for the
selection of R3.
A complete diagram of the circuit implemented is indicated in fig. 7, while the input versus output characteristics is shown in fig. 8.
Figure 7: Complete Circuit Diagram.
Rl
1.ZKD
Z7Kf'I'
01
03
D/A
L291
5 -58701'
01704
{
VF <; 1.2 V @ I = 2 A
trr <; 200 ns
5/8
277
APPLICATION NOTE
In the graph of fig. 8 the rotation speed of the motor
is represented on ordinates, while the decimal
speed code, corresponding to the binary code applied to inputs b1 throug h b5, is represented on abscissae.
The abscissa 1 corresponds to the minimum speed
code, i.e. input b1 low and remaining inputs high,
since the least significant input is b1 and the active
status of inputs is low. The abscissa 31 corresponds
to the maximum speed code, i.e. all inputs b1
through b5 low. The negative abscissae have been
obtained by changing the status of the bs input. The
graph in fig. 8 should have been made up of a number of dots; these dots have been joined together
with an ininterrupted line for convenience. This
graph has the same features as the graph in fig. 3,
i.e. the curve features a discontinuity around the
origin, and it lowers as long as the motor current
drain increases. In this case too, the circuit in fig. 7
can be modified in order to prevent that the speed
vary in function of the motor load, by adding a current loop in the control circuit, by using the remaining operational amplifier available in the integrated
circuit L291.
Figure 8 : Output Characteristic of the Circuit in
fig. 7.
n
(rpm)
2000
1600
1200
eoo
Spp~d
-32
_24
-16
16
24
code
J2
1:lm::.200mA
2:Jm=IA
-1200
·1600
-2000
6/8
278
Since this amplifier has only the inverting input available, while the non-inverting input is grounded, a circuit arrangement as schematically shown in fig. 9
has been adopted in order to have an output signal
referred to ground, given an input signal referred to
a reference voltage (in L292) of approximately 8 V.
Figure 9 : Translator Circuit.
!.-5171
o
Resistors RA and RB must be high-precision resistors in order to have output 0 with no 1m current present. In the practical implementation, resitors with an
accuracy of 5 % are used and the ends of a potentiometer are interposed between resitors RB and the
output to the sum point of the error amplifier is made
through the cursor. The gain of this current loop is
propotional to the ratio R3/RB. A complete circuit diagram is shown in fig. 10.
Since, for reasons of gain, resistor RB must be.27 kQ
and, if connected to pin 7 of L292, should have subtracted too much current by thus affecting the correct operation of L292, it has been connected to
pin 11, having the same potential as pin 7. Consequently, the resistance value between pin 11 and
ground has been modified, in order to maintain the
switching frequency of L292 unchanged. In order to
have a correct adjustment of potentiometer P1, it is
enough to set the 0 speed code (b1 through b5 high)
and turn the cursor until the motor stops.
The input versus output characteristic obtained with
the circuit of fig. 10 is indicated in fig. 11.
APPLICATION NOTE
Figure 10 : Complete Circuit with Current Feedback.
R2
01
D1
Figure 11 : Output Characteristic of the Circuit in
fig. 10.
n
(rpm)
2000
1600
1200
800
.00
-32
-2.
-16
-.
Spet>d codt>
16
2.
32
-BOO
Im:200mA-f2A
/
_1200
-1600
-2000
7
D4
{
OJ
V, S 1.2 V @ I = 2 A
Irr S 200 ns
RESPONSE TO INPUT STEP
Measurements have been taken on the circuits described in the previous paragraphs, in order to analyze how the motor speed varies when a step
variation is imposed to the input.
For the system DC control, the control voltage has
been changed from 0 to the maximum value ViM and
down to 0 again. For the digital system the speed
code has been changed from 0 (b1 through bs high)
to the maximum value (b1 through bslow) and down
to 0 again. When the control quantity changes from
o to the maximum value, the output voltage of the
error amplifier (Va, fig. 1 and fig. 6) assumes its maximum value, since the feed-back signal coming from
the tachometer dynamo initially O. In these conditions, L292 supplies the motor with the maximum
current (2A) and maintains it until the motor speed
is sufficiently close to the maximum value.
Since the motor is powered from a constant current,
it moves with a constant current, it moves with aconstant acceleration and consequently its speed
grows linearly from 0 up to the maximum value over
the time interval tao The time needed for the motor
to reach the maximum speed also depends, besides
7/8
279
APPLICATION NOTE
the current, on the electrical and mechanical characteristics of the motor and on the moment of inertial of the load applied to the motor. When the control
quantity changes from the maximum value to 0, the
output of the error amplifier Va assumes the maximum value, but with an opposite sign with respect
to the previous case, and the current flowing in the
motor is also reversed and tends to brake it, by making the speed linearly decrease from the maximum
value down to 0 over the time period tf. The no-load
characteristics, relevant to the motor used for the
previous tests, are shown in fig. 12. The times ta and
tf are not equal to each other, which circumstance
is basically due to the frictions which, during the acceleration phase, oppose increase of speed, while
during the deceleration phase they contribute to
make the speed decrease. As a matter of fact, from
the movement equation:
J
+ 0 8 + Tf = KT 1M
where:
J=
System moment of inertia
o = Coefficient of viscous friction
Figure 12 : Pulse Response.
Vi
o
20
40
60
80 t(msec)
\
e
Tf =
Kt =
8=
Braking couple
Motor constant
Angular speed
8=
Angular acceleration
and by disregarding the term De, one obtains:
KT . 1M - Tf
8=
J
where from it can be seen that I
is negative.
8/8
280
'e I is greater if 1M
D
APPLICATION NOTE
THE L290/L291/L292 DC MOTOR
SPEED/POSITION CONTROL SYSTEM
The L290, L291 and L292 together form a complete microprocessor-controlled DC motor servopositioning
system that is both fast and accurate. This design guide presents a description of the system, detailed function descriptions of each device and application information.
L291 generates a voltage control signal to drive the
L292 switchmode driver which powers the motor.
An optical encoder on the motor shaft provides signals which are processed by the L290 tachometer
converter to produce tacho voltage feedback and
position feedback signals for the L291 plus distance/direction feedback signals for the control
micro.
The L290, L291 and L292 are primarily intended for
use with a DC motor and optical encoder in the configuration shown schematically in figure 1. This system is controlled by a microprocessor, or
microcomputer, which determines the optimum
speed profile for each movement and passes appropriate commands to the L291 , which contains the
system's D/A converter and error amplifiers. the
Figure 1 : The L290, L291 and L292 form a complete DC Motor servopositioning System that connects
directly to Microcomputer Chips.
DIRECTlDN
SPEED
VELOCITY I POSITION
DEMAND
WORD (S BITS)
t-~--'-+_f--/M'-I0DE
MOTOR
SELECT
CURR ENT
(CONTROL VOLTAGE
LZ91
DIGITAL-ANALOG
f---'-t---,~ CONVERTER PLUS~-'-_--l~
ERROR AND
POSITION
AMPLIFIER
L292
SWITCHMODE
MOTOR
DRIVER
-POSITION FEEDBACK
MCU
ABSOLUTE
POSITION
SIGNAL FOR
INITIALIZATION
\
AN242/1088
r - - - i - - T ACHO VELOCITY
FEED BACK
t---f.--+--DAC REFERENCE VOLTAGE
~--'-----4--,
....---..--
1/23
281
APPLICATION NOTE
The system operates in two modes to achieve high
speed and accuracy: closed loop speed control and
closed loop position control. The combination of
these two modes allows the system to travel rapidly towards the target position then stop precisely
without ringing.
Initially the system operates in speed control mode.
A movement begins when the microcomputer applies a speed demand word to the L291 , typically
calling for maximum speed. At this instant the motor
speed is zero so there is no tacho feedback and the
system operates effectively in open loop mode (see
figure 2). In this condition a high current peak - up
to 2A - accelerates the motor rapidly to ensure a
fast start.
As the motor accelerates the tacho voltage rises and
the system operates in closed loop speed mode,
moving rapidly forwards the target position. The
microcomputer, which is monitoring the optical encoder signals (squared by the L290), reduces the
speed demand word gradually when the target position is close. Each time the speed demand word
is reduced the motor is braked by the speed control
loop.
Finally, when the speed code is zero and the target
position extremely close, the micro commands the
system to switch to position mode. The motor then
stops rapidly at the desired position and is held in
an electronic detent.
Figure 2 : The System operates in two Modes to achieve High Speed and Accurary. Tachometer
Feedback regulates the Speed during a Run and brakes the Motor towards the End. Position
Feedback allows a Precise Final Positioning.
MOTOR AC~ELERATES
RAPIDLY IN INITIAL
OPEN LOOP CONDITIONS
VELOCITY FEEDBACK
REGULATES SPEED
DURING RUN
I
MOTOR BRAK ED
PROGRESSIVELV BV
REDUCING SPEED
DEMAND WORD
MOTOR
SPEED
.
)
,
r
FINAL. PRECISE
POSITIONING
PERFORMED IN
POSITION MODE
2A
MOTOR
CURRENT
O~~~=============+AH~~h-2A
INITIAL HIGH
CURRENT PEAK
ENSURE S F AS T
STARTUP
t
s-
2123
282
s~51
MOTOR BRAKED AS
' - LOOP RESPONDS TO
REDUCTIONS IN SPEED
DEMAND WORD
APPLICATION NOTE
OPTICAL ENCODER
The optical encoder used in this system is shown
schematically in figure 3. It consist of a rotating
slotted disk and a fixed partial disk, also slotted.
Light sources and sensors are mounted so that the
encoder generates two quasi-sinusoidal signals
with a phase difference of ± 90· . These signals are
referred to as FTA and FTS. The frequency of these
signals indicates the speed of rotation and the rela
tive phase difference indicates the direction of rotation. An example of this type is the Sensor Technology STRE 1601, which has 200 tracks. Similar types
are available from a number of manufactures including Sharp and Eleprint.
This encoder generates a third signal, FTF, which
consists of one pulse per rotation. FTF is used to
find the absolute position at initialization.
Figure 3 : The System operates with an Optical Encoder of the Type shown schematically here.
It generates two Signals 90 out of Phase plus a one Pulse-per-rotation Signal.
0
HOLE TO GENERATE
ONE PULSE PER
ROTATION SIGNAL
CNE PULSE
P'OR ROTATION
OUTPUT
\
'-~--'
FTF
SINEWAVE
OUTPUTS WITH
±90· PHASE
OIFFERENCE
S 5972
THE L290 TACHOMETER CONVERTER
The L290 tachometer converter processes the three
optical encoder signals FTA, FTS, FTF to generate
a tachometer voltage, a position signal and feedback signals for the microprocessor. It also generates a reference voltage for the system's D/A
converter.
Analytically, the tacho generation function can be
expressed as :
dVAS
TACHO= - dt
FTA
dVAA
FTS
IFTAI
dt
IFTSI
In the L290 (block diagram, figure 4) this function is
implemented by amplifying FTA and FTS in A 1 and
A2 to produce VAA and VAS. VAA and VAS are differentiated by external RC networks to give the signals VMA and VMS which are phase shifted and
proportional in amplitude to the speed of rotation.
VMA and VMS are passed to multipliers, the second
inputs of which are the sign of the other signal before differentiation.
FTA
FTS
The sign (IFTAI or IFTSI
) is provided by the
comparators CS1 and CS2. Finally, the multiplier
outputs are summed by A3 to give the tacho signal.
Figure 5 shows the waveforms for this process.
This seemingly complex approach has three important advantages. First, since the peaks and nulls of
CSA and CSS tend to cancel out, the ripple is very
small. Secondly, the ripple frequency is the fourth
harmonic of the fundamental so it can be filtered
easily without limiting the bandwidth of the speed
loop. Finally, it is possible to acquire tacho information much more rapidly, giving agood response time
and transient response.
Feedback signals forthe microprocessor, STA, STS
and STF, are generated by squaring FTA, FTS and
FTF. STA and STS are used by the micro to keep
track of position and STF is used at initialization to
find the absolute position.
3/23
283
APPLICATION NOTE
Position feedback for the L291 is obtained simply
from the output of A 1.
Since the tacho voltage is also derived from VAA and
VAS it follows that the system is self compensating
and can tolerate variations in input levels, temperature changes and component ageing wifh no deterioration of performance.
The L290 also generates a reference voltage for the
L291 's D/A converter. This reference is derived from
VAA and VAS with the function:
Vref""-
IVAAI + IVAsl
Figure 4 : The L290 processes the Encoder Signals, generating a Tacho Voltage and Position Signal for
the L291 plus Feedback Signals for the Microprocessor. Additionally, it generates a Reference
Voltage for the L291 's D/A Converter.
OPTICAL ENCODER
SIGNALS
FTB
FTA
rTF
STF
AC
FEEDBACK
SIGNAlS
51B
FOR
MICROPROCESSOR
I
STAO -
REFERENCE
VOLTAGE OUTPUT
FOR O/JI,.' CONVERTER
IN L 1~1
4/23
284
0
TACI-tO VOLTAGE
POSITION
0 UTPUT TO !.. 291
FEEDBACK
TO l291
NETWORKS
APPLICATION NOTE
Figure 5 : These Waveforms illustrate the Generation of the Tacho Voltage in the L290. Note that the
Ripple is fourth Harmonic. The Amplitude of TACHO is proportional to the Speed of Rotation.
ANTICLOCKWISE
DIRECTION
CLOCKWISE
DIRECTION
I
I
I
VAA
VA"
C51
CS'
VM"
C56
CSA
TACHO
Figure 6 : The L291 Links the System to the Microprocessor. It contains the system DA converter, main
error amplifier and position amplifier.
OIA REFERENCE
FROM L290
POSJTJON
TACHO VOLTAGE
FROM U9C
FEEDBACH
FROM U90
REMovES
,.... FOURTH HARMONlC
RIPPLE
VELOCITY
LOOP
GAIN
J
CONTROL
>--f--l--t--~--Q ~gLT~~~2
DRIVER
SPEED
DEMAND
WORD
-....qf--l
OAC I - - - - f - l
r:
DIRECTION
(SIGN)
POSITION
MODE. SHECT
(STROBE)
_______
-
_________ -
-
I
_ _I
5 - S'l 54/2
5/23
285
APPLICATION NOTE
THE L291 D/A CONVERTER AND AMPLIFIERS
The L291 , shown in figure 6, links the system to the
micro and contains the system's main error amplifier plus a position amplifier which allows independent adjustment of the characteristics of the
position loop.
It contains a five bit O/A converter with switchable
polarity that takes its reference from the L290. The
polarity, which controls the motor direction, is controlled by the micro using the SIGN input.
The main error amplifier sums the O/A converter
output and the tacho signal to produce the motor
drive signal ERRV. The position amplifier is provided to allow independent adjustment of the position loop gain characteristics and is switched in/out
of circuit to select the mode. The final position mode
is actually 'speed plus position' but since the tacho
voltage is almost zero when position mode is selected the effect of the speed loop is negligible.
THE L292 SWITCHMODE MOTOR DRIVER
The L292 can be considered as a power transconductance amplifier - it delivers a motor current proportional to the control voltage (ERRV) from the
L291. It drives the motor efficiently in switch mode
and incorporates an internal current feedback loop
to ensure that the motor current is always proportional to the input control signal.
The input control signal (see block diagram,
figure 7) is first shifted to produce a unipolar signal
(the L292 has a single supply) and passed to the
error amplifier where it is summed with the current
feed-back signal. The resulting error signal is used
to modulate the switching pulses that drive the output stage.
6/23
286
External sense resistors monitor the load current,
feeding back motor current information to the error
amplifier via the current sensing amplifier.
The L292 incorporates its own voltage reference
and all the functions required for closed loop current
control of the motor. Further, it features two enable
inputs, one of which is useful to implement a power
on inhibit function.
The L292's output stage is a bridge configuration
capable of handling up to 2A at 36V. A full bridge
stage was chosen because it allows a supply voltage to the motor effectively twice the voltage
allowed if a half bridge is used. A single supply was
chosen to avoid problems associated with pumpback energy.
In a double supply configuration, such as the
example in figure 8 a, current flows for most of the
time through 01 and Ql. A certain amount of power
is thus taken from one supply and pumped back into
the other. Capacitor Cl is charged and its voltage
can rise excessively, risking damage to the associated electronics.
By contrast, in a single supply configuration like
figure 8b the single supply capacitor participates in
both the conduction and recirculation phases. The
average current is such that power is always taken
from the supply and the problem of an uncontrolled
increase in capacitor voltage does not arise.
A problem associated with the system used in the
L292 is the danger of simultaneous conduction in
both legs of the output bridge which could destroy
the device. To overcome this problem the comparator which drives the final stage consists of two separate comparators (figure 9). Both receive the same
Vt, the triangular wave from the oscillator, signal but
on opposite inputs.
APPLICATION NOTE
Figure 7 : The L292 Switchmode Driver receives a Control Voltage from the L291 and delivers a
switch mode regulated Current to the Motor.
CURRENT FEEDBACK
FRO,.. MOTOR
SENSE
RESISTORS
' - r-c"=O!l:r-- 5.6 kG
R18, R19
0.2 G
To set the transconductance
vatue of the L292.
Transconductance decrease
(R18 , RI5). 1m :S 0.44 V.
Transconductance
increase.
R20
15 kG
To set the oscillator
frequency.
Oscillator frequency
decrease.
Osciltator frequency
increase. R20 ~ 8.2 kG
R 21
33 G
Compensation Network
Cl,C2,C3
100 pF
Purpose
Larger than
Recommended Value
Smaller than
Recommended Value
Increase of the peak
current in the output
transistors during
the communications.
To filter the noise on the
encoder signals.
Bandwidth reduction of
the low pass filter.
Bandwidth increment of
the low pass filter.
C4, C6
15 nF
Differentiator Network
Tacho signal increase.
Tacho signal Decrease.
C5
2.2 ~F
By-pass Capacitor
Larger set-up time after
power on.
Reduced by-pass effect
at low frequencies.
C7
0.1 ~F
Low-pass filter for the
D/A input current.
C8
0.22
~
- Low pass filter for the
tacho signal.
- To determine the
dominant pole of the
speed loop.
Increase of the current
ripple at low speed.
Bandwidth reduction of
the speed loop.
Low filtering at low speed,
causing noise on the
motor.
- Lower value of the
damping factor.
- Danger of Oscillations
- Higher value of
dumping factor.
Cl0,Cl1
0.1 ~F
Supply By-pass Capacitor
C12
47 nF
To filter the feedback
current
C13
47 nF
To set the gain of the
error amplifier
C13 - R17 = LM/RM
C15
0.1 ~F
Supply By-pass Capacitor
Danger of Oscillations
C16
470 ~F
Supply By-pass Capacitor
Ripple increment on the
supply voltage.
C17
1.5 nF
To set the oscillator
frequency and the dead time
of the output transistors.
C18
1 nF
01,02,
03, 04
1A
Fast Diodes
Compensation Network
Danger of Oscillations.
- Oscillation Frequency
Reduction
- Dead time increment.
- Oscillation Frequency
Increment
- Dead time reduction.
Danger of Oscillations
Recirculation Diodes
11/23
291
APPLICATION NOTE
APPLICATION CIRCUITS
The complete circuit is shown in figure 12 ; a suitable layout for evaluation is given in figure 13. Component values indicated are for a typical system
using a Sensor Techonology STRE1601 encoder
and a motor with a winding resistance of 50 and an
inductance of 5mH (this motor is described fully in
figure 17). How to calculate values for other motors
is explained further on.
This is a preferable to simply adding a discrete driver
stagejn place of the L292 because the L292's current control loop is very useful.
Figure 15 shows how four transistors are added to
increase the current to 4, 6 or SA, depending on the
choice of transistor. When coupled to the L290 and
L291 this configuration appears to the system as an
L292.
The average motor current, 1m, is found from:
Figure 14 explains what each component does and
what happens if is varied. Maximum and minimum
values are also indicated where appropriate.
ADDING DISCRETE TRANSISTORS FOR
HIGHER POWER
In the basic application, the L292 driver delivers 2 A
to the motor at 36V. This is fairly impressive for an
integrated circuit but not enough for some applications: robots, machine tools etc. The basic system
can be expanded to accomodate these applications
by adding external power transistors to the L292.
Vi 0.044
Im = - - Rx
Where Vi is the input voltage and Rx is the value of
the sense and resistors R7 and RS.
Suitable transistors for this configuration are indicated below:
I(A) Vi(V Rx(mD) Q1,02 03,04
4
6
8
9.1
9.1
9.1
100
65
50
01 - 04
B0708
B0707 2A Fast Diodes
B0907 3A Fast Diodes
B0908
BOW52A BOW51A 4A Fast Diodes
Figure 15 : For higher power external transistors are added to the L292. This circuit delivers up to 4A,
if 2 BDW51A and 2 BDW52A are used it can deliver SA.
l
R7
D.lfi
S-4866/1
12/23
292
APPLICATION NOTE
The circuit shown in figure 16 is suitable for motor
currents up to 50A at voltages to 150V. Two sup lies
are used; 24V for the L292 and LS141 and 150V
for the external transistors and motor. This circuit
too behaves just like an L292, except for the higher
power, and connects to the L290 and L291 as usual.
The motor current is given by :
Vin
X
120
X 10'6
R
Im = - - - - - where Rs
Rs
3
= Rs1 = Rs2 = 12 x 10'
Q
and 390 Q < R < 860Q
This gives a range of transconductance values
(Im/Vin) from 3.0AN (R = 390 Q ) to 8.6AN
(R = 860Q).
In this circuit the L292 drives two transformers
whose secondaries drive the power transistors. The
coil ratio of the transformers is 1 : 20. To limit the
duty cycle at which the transformers operate from
15% to 85%, two zener diodes are inserted between
pin 7 and pin 9 of the L292. The LS141 op amp supplies current feedback from the transistor bridge to
the L292.
Figure 16 : For higher voltages and currents-up to 150V at 50A, this circuit can be used. It connects to
the L290 and L291 , behaving just like and L292.
+Vs lSOV
FREaUENCV
lo.7KIl
13/23
293
APPLICATION NOTE
DESIGN CONSIDERATIONS
The application circuit of figure 12 will have to be
adapted in most cases to suit the desired performance, motor characteristics, mechanical system
characteristics and encoder characteristics. Essentially this adaptation consists of choosing appropriate values for the ten or so components that
determine the characteristics of the L290, L291 and
L292.
The calculations include:
• Calculation of maximum speed and acceleration ; useful both for defining the control algorithm
and setting the maximum speed.
" Calculation of RB and R9 to set maximum speed.
• Laplace analysis of system to set CB, R11, R12,
R13 and R14.
• Laplace analysis of L292 loop to set the sensing
resistors and C12, C13, R15, R16, R17.
" Calculation of values for C4 and C6 to set max
level of tacho signal.
" Calculation of values for R6 and R7 to set D/A
reference current.
• Calculation of R20 to set desired switching frequency.
MAXIMUM ACCELERATION
For a permanent magnet DC motor the acceleration
torque is related to the motor current by the expression:
Ta + Tf = KT 1m
where:
It follows that for a given motor type and control loop
the acceleration can only be increased by increasing the motor current, 1m.
The characteristics of a typical motor are given in
figure 17. From this table we can see that:
KT = 4.3N cm/A
J m = 65g . cm 2
(6.07 oz.in/A)
(0.92 x 10-3 oz. in S2)
We also know that the maximum current supplied
by the L292 is 2 A and that the moment of inertia of
the STRE 1601 optical encoder, Joe, is 0.3 X10.4 OZ.
in. S2.
The moment of inertia of the load JL, is unknown but
assume, for example, that Joe + JL 2 J m. Therefore the maximum angular acceleration is :
=
a=
6.07 x 2
2 x 0.92 x 10-3
= 6597.Brad/s 2
Fig. 17- The Characteristics of a Typical DC
Motor.
Motor - Parameter
Value
18 V
4.5 mV/min- 1
3800 rpm
190 mA
0.7 N cm
4.3 N cm/A
65 g. cm. 2
5.4 Q
5.5 mH
(Vs)
C. emf. KE
. No (without load)
10m (without load)
T f (friction torque)
KT (motor constant)
Amature Moment of Inertia
RM of the Motor
LM of the Motor
UB B
1m
is the motor current
MAXIMUM SPEED
KT
is the motor torque constant
The maximum speed can be found from:
Ta
is the acceleration torque
Vs min
Tf
is the total system friction torque
where:
The acceleration torque is related to angular acceleration and system inertia by :
Ta = (J m + Joe + JL) a
where:
Jm
Joe
JL
is the moment of inertia of the motor
a
is the angular acceleration
is the moment of inertia of the encoder
is the moment of inertia of the load
In a system of this type the friction torque TI is normally very small and can be neglected. Therefore,
combing these two expressions we can find the angular acceleration from:
KT
a=
. 1m
J m + Joe + JL
14/23
294
= 2 VCEsat + Rs 1m + Ke Q + Rm 1m
E=
Ke Q is the internally generated voltage
(EMF)
Ke
is the motor voltage constant
Q
is the rotation speed of the motor.
For example, if Vs min = 20V
= 5V (from L292 datasheet)
= 10.BV (Rm = 5.4 Q)
2 VCEsat + Rs 1m
Rm 1m
we obtain:
Ke
Q (E)
= 4.2V
and
4.2V
Q
= 4.5 rnV/min-1 = 933.3rpm =
= 97.74rad/s
APPLICATION NOTE
The STRE1601 encoder has 200 tracks so this
speed corresponds to :
200
= 3111.1 tracks/so
60
The time taken to reach maximum speed from a
standing start can be found from
~t=
Q
a
=
97.74 rad/s
6597.S rad/s 2 = 14.Sms
We can also express the acceleration in terms of
tracks/s 2 :
V
~
3111.1
t
tracks/s2
14.S ms
= 21 0209.S
tracks/s 2
Therefore the number of tracks necessary to reach
the maximum system speed for our example is :
V2
p=
= 23 tracks
2K
This information is particularly useful for the programmer who writes the control software.
SETTING THE MAXIMUM SPEED
The chosen maximum speed is obtained by setting
the values of R6, R7, RS, R9, C4 and C6 (all shown
on the application circuit, figure 12). This is how it's
done:
The first step is to calculate R6 and R7, which define
the DAC current reference. From the L291 datasheet we know thatlref, the DA converter current reference, must be in the range 0.3mA to 1.2mA.
Choosing an Iref of roughly O.SmA, and knowing that
Vref (the L290s reference output) is typically SV, it
follows that:
Vref
R6 + R7 =
Ire!
= 10kQ
Therefore we can choose R6 = R7 = 4.7kQ (S%
tolerance).
Substituting the minimum and maximum values of
Vref (from the L290 datasheet) and the resistance
variations we can now check that the variation of Iref
in the worst case is acceptable.
Vrefmin
Irefmin
= (R6 + R7) max = 0.46mA
Vref (typ)
4.7 k + 4.7 k = 0.S3mA
Vref max
Iref max = -:C(R=-6c--+-=RC::C
7:-)m-:-in = 0.62mA
Ireftyp =
These values are within the 0.3mA to 1.2mA limits.
Now that the reference current is defined we can
calculate values for RS and R9 which define the
tacho current at the summing point.
The full scale output current of pin 12 of the L291
(the D/A converter output) is :
10 = 1.937 Iref
which is typically 1.02mA.
The worst case output current is when Iref is at a
maximum (0.62mA) and the lout error is maximum
(+2%) :
10 = 0.62 x 1.937 x 1.02 = 1.22mA
This less than the 1.4 mA maximum value for lout
specified in the L291 datasheet.
Assuming that the maximum DC voltage at the.
TACHO output of the L290 (pin 4) is 7V (this is the
tacho voltage generated at the maximum system
speed), we can find the sum of RS and R9 ;
Vtacho DC
RS + R9 =
7
= -- =
lotyp
6.SSkQ
1.02
Therefore we choose RS = 4.7kQ and a SkQ trimmer for R9. R9 is used to adjust the maximum
speed.
We can now calculate the ripple voltage and maximum tacho voltage:
It
Vripple pp
=-
4
({2- 1) Vtacho DC
=2.3 Vpp
It
Vtacho max = -
4
{2Vtacho DC
=7.S Vp
15/23
295
APPLICATION NOTE
This value is within the voltage swing of the tacho
amplifier (± 9V) ; that means the choice of
Vtacho DC = 7V is correct.
At this point we know the values of R6, R7, R8 and
R9. The maximum speed can now be set by choosing values for C4 and C6 which form the differentiation networks on the L290. These values depend on
the number of tracks of the optical encoder. For the
STRE1601 encoder the capacitor values can be
found from figure 18. These curves show how the
capacitor values is related to frequency (encoder rotation speed) for different tacho voltages and maximum speed. The example values are Vtacho DC = 7V
and maximum speed = 3111 tracks/sec therefore
the value for C4 and C6 is 15nF.
Figure 18 : C4 and C6 value versus rotation
speed for various maximum tacho
voltage values.
G
J.,
937
c.
(nF)
35
30
25
20
Illl
1\'1\
H\
~\\
l\\.
\\,
l'..l\.: r-.. ........
15
The values of R4 and R5 must be 820£1 to minimize
the offsets.
II
, \' .,
\
r-.. ....... :--....['0
"
10
-
t'-- :---;t' t--.
I 7V 8[
i
I I I
....... 6V
VtachoDC=5V
I
I
1
I
300
2
600
3
900
4
1200
111
5
6 f(KHz)-FTA
1500 1800 rpm
Figure 19.
(.) See L292 datasheet for an accurate analysis of this block.
List of
s
KT
Ta
Tf
J
16/23
296
terms
: Laplace variable
: Motor torque constant
: Acceleration torque
: Total system friction torque
: Total moment of inertia (J = Joe + Jm + JL).
KT
: Speed
: Angular position
: Conversion factor that links the motor rotation speed
and the TACHO signal.
: Conversion factor that links the motor position and the
Vpos signal.
APPLICATION NOTE
LAPLACE ANALYSIS OF THE SYSTEM
itable values for the components R11, R12, R13,
R14 and CS can be found from a Laplace analysis
of the system. Figure 19 shows a simplified block diag ram of the system which will be useful for the analysis.
The analysis is based on the angular speed nand
on the motor position 8. The motor is represented,
to a first approximation, by the current 1m and by the
acceleration torque, Ta, which drives an inertial
load J.
There are two conversion factors, Ksp and K8. They
link the mechanical parameters (position and
speed) with the equivalent feedback signals for the
two loops. The values of Ksp and K8 are determined
by the encoder characteristics and the gain parameters of the integrated circuits. The openloop and
closed-loop gains are fixed by four external resistors:
" Rref - fixes the reference current (R6 + R7)
" Rspeed - fixes the speed loop gain (RS + R9)
" Rpos - controls the position loop gain (R12)
.. Rerr - controls the system loop gain (R13).
For example, 1m = 2 A, Vi = 9.1 V, resistor values as
in figure 7 (L292 internal block diagram) .
0.044
Rs=
RS R9
RS + R9.
SETTING THE L292 COMPONENTS
The sensing resistor and feedback loop component
values for the L292 can be calculated easily using
the following formulae. A detailed Laplace analysis
of this block is given on the L292 datasheet.
a) Sense resistors.
Vs
=
L292 supply voltage
Rm = motor resistance
VR = L292 reference voltage
and
,/
~ =V
1m
R2 R4
I
R1 R3
Rs
=
R4C13
4R15 C12 G mo Rs
R4 = L292 internal resistor (400n)
Rs = R1S = R19
A good choice for ~ is 11 .v2. Substituting this value,
Gmo and the values of R4 and Rs :
~2=
1
400 C13
2
4R15 C12 x 0.2
1000 C13
=}
Also
=1
R15C12
0.9
IT=
21tR15C12
Assuming that IT is 3kHz, another recommended
value:
R15 C12",47 x 10·6s
Therefore we can find C13 :
1000 C13 =0 47 x 10.6
=}
C13 = 47nF
Since
=R17C13
Rs = R1S = R19
Vi
Rs
= 0.2 n
Gmo =
The fundamental characteristics of the speed control system can thus be determined by the designer.
is the time constant that determines the dominant pole of the speed loop and is determined by
CS, RS and R9
Vi
b)R17,R15, R16,C12,C13
The stability both of the speed loop and of the
speed-position loop are defined by external components.
1:sp
1m
R2 R4 Vi
R17 =
1m R1 R3
(These resistors are all inside the L292).
where:
1m
is the motor current
Vi
is the input voltage corresponding to 1m.
C13 Rm
Forthe example motor Lm = 5mH, Rm = 5.4n therefore:
R17 =
Lm
C13 Rm
= 22kn
From R15C12=o47x 1O·6 s,choosing a value of
R15 ; 510n, we have:
C12 = S2nF
Also, R16 = R15 = 510n.
17/23
297
APPLICATION NOTE
DEAD TIME
EFFICIENCY AND POWER DISSIPATION
C17 sets the switching delay of the L292 which protects against simultaneous conduction. The delay
is:
1: = R1: C17
Neglecting the losses due to switching times and the
dissipation due to the motor current, the efficiency
of the L292's bridge can be found from:
and R, is an internal 1.5k resistor. The suggested
1.5nF value gives a switching delay of about 2.25/lS.
This is more than adequate because the transistors
have a switch off delay of only 0.5I1S.
SWITCHING FREQUENCY
The switching frequency is set by C17 and R20 :
I
fose =
2 R20 C17
R20 must be at least 8.2kQ and is varied to set the
frequency: the value of C17 is imposed by dead
time requirements. Typically the frequency will be
15-20kHz.
It should be outside the audio band to reduce noise
but not to high or efficiency will be impaired. The
maximum recommended value is 30kHz.
CURRENT RIPPLE
To reduce dissipation in the motor and the peak output current the ripple, ~ Im,should be less than 10%
of the maximum current.
11- 1-
~
~
t1
Vsat
t1 - Llt2
Vs
~ t1
Vover
----"
Llt- ~ t2
Vs
where:
Vover == 2V (2VSE + Rs 1m)
Vsat == 4V (2VCEsat + 3 VSE )
Ll t1 = transistor conduction period
Ll t2 = diode conduction period.
If Ll t1
~ Ll
t2 and Vs = 20V we obtain:
4
11=1-
20
=80%
In practice the efficiency will be slightly lower as a
results of dissipation in the signal processing circuit
(about 1W at 20V) and the finite switching times
(about 1W).
If the power transferred to the motor is 40W, the
80% efficiency implies 1OW dissipated in the bridge
and a total dissipation of 12W. This gives an actual
efficiency of 77%. Since the L292's Multiwatt package can dissipate up to 20W it is possible to handle
continuous powers in excess of 60W.
Since
~Im=
T
(2"
T
POSITION ACCURACY
2
The main feature of the system L290, L291, L292 is
the accurate positioning of the motor. In this section
we will analyse the influence of the offsets of the
three ICs on the positioning precision.
= half period oscillator)
and
~
1m = 0.1 1m max
Vs
0.1 1m max =
2 f LM min
5 Vs
LM min =
f 1m max
Therefore there is a minimum inductance for the
motor which may not always be satisfied. If this is
the case, a series inductor should be added and the
value is found from:
Lseries =
18/23
298
5 Vs
f 1m max
When the system is working in position mode, the
signal FTA coming from the optical encoder, after
suitable amplification, is sent to the summing point
of the error amplifier (L291). If there were no offset
and no friction, the motor would stop in a position
corresponding to the zero crossing of the signal
FTA, and then at the exact position required. With a
real system the motor stops in a position where FTA
has such a value to compensate the offsets and the
friction; as a consequence there is a certain imprecision in the positionning. The block diagram, fig. 20,
shows the parts of the 3 ICs involved in the offsets.
First we will calculate the amount of the offsets at
the input of the IC L292 (point A of fig. 20).
APPLICATION NOTE
Figure 20.
TACHO
L292
R12
L..._ _ _ _ _ _ _..... 5-5965
L290
The offset of the TACHO signal, V2, is the main
cause of the imprecision of the positioning. Another
offset in L290 is Vi, the output offset voltage of Ai.
The contribution at point A is :
R14
R13
V1A=V1' R11 . R12
R13
V2A = V2'
R89
R13
VllA= 11· R14-R12
VI2A= 12. R13
V4A=V4(1+
R13
)
R1211R89
L292
11 = input bias current of the postion amplifier
Referring to this IC we must consider the input offset voltage V5. Moreover, we call V6 the input voltage that must be applied to the L292 to keep the
motor in rotation, i.e. to compensate the dynamic
friction. V6 is not an offset voltage, but has the same
effects, and for this reason we have to put it together
with the offsets.
12 = output offset current of the D/A converter plus
ER. AMP bias current
V5A = V5
L291
In this IC there are the following offsets:
V3 = input offset voltage of the position amplifier
V4 = input offset voltage of the error amplifier.
10
Vi
= Transconductance of L292
Their contribution at point A is :
V3A = V3 • (1 +
R14
R11
R13
).R12
19/23
299
APPLICATION NOTE
Ie = Motor current necessary to compensate the dynamic friction
The total offset voltage referred to point A is given
by the sum of all the precedent terms:
VA = V1A + V2A + V3A + Vi1A + VI2A V4A + VSA + VeA.
The amplitude of the signal FTA necessary to compensate the offset VA is :
R11
R12
VFTA= VA' - - , - R13
R14
A1
Calling VM the maximum value of the signal FTA,
the phase error of the system is :
ex = sin- 1
VFTA
a.c
15 120
22) '100
= 9.1mV
120
VhA= 0.3' 10-e . 15 '10 3 100
= 5.4mV
VI2A = 0.4 . 10·e . 120 . 103 = 4SmV
120
V4A = 2 . 10-3 . ( 1 + 5.6 ) = 44.9mV
VSA = 350mV
50
V6A =205= 244mV
VA = 2.346V
·100
100
In these calculations we have not considered how
the precision of the signal FTA, coming from the optical encoder, influences the positioning error. The
percentage value of the pitch accuracy must be
added to E to have the total percentage error in the
character positioning. Any DC offset of the mean
value of the signal FTA must be multiplied by A1 and
added to V1 to obtain its effect on the error.
VFTA = 2.329
'120'
ex = sin- 1
R11 = 22K R12 = 100K R13 = 120K R14 = 15K
RS9 = RS + R9 = 6K
From the data sheets of the three ICs we can find:
V2 = SOmV
V5 = 350mV
11
= 0.3~
V3 = 4.5mV
12 = 0.4f1A
A1 min = 22dB = 12.6
10
Vi min = 205
mA
---v--
VMmin = 0.4 V
For 16 we will consider the value 16 = 50mA
20/23
300
1
12.6
= 0.22SV
0.226
0.4
35
In this numerical example we will calculated the precision of the positioning in the worst case, i.e. with
all the offsets at the max value. The values of the
external components are taken from the application
circuit. (fig. 12).
V4 = 2mV
22
---:rs'
If we consider an optical encoder with 200
tracks/turn and a daisy wheel with 100 characters,
the phase between two consecutive characters is
ac = 720', and then the maximum percentage error
we can have is.
NUMERICAL EXAMPLE
V1 = 55mV
22
V3A = 4.5 ,10-3 (1 +
VM
ex
--
120
= 45mV
100
120
V2A = SO ' 10-3 , -6 = 1 .6V
If
24 spl'lc'd code
'8
SPEED ACCURACY
If we consider the complete system with L290-L291L292 driving a DC MOTOR with optical encoder, we
can note the speed of the motor is not a linear function of the speed digital code appied to L291. The
diagram of fig. 21 shows this function and it is evident that the speed increases more than a linear
function, i.e. if the speed code doubles, the speed
of the motor becomes more than the double. The
cause of this non linearity is the differentiator network R4 C4 and R5 C6 (see fig. 22) that has not an
ideal behaviour at every frequency.
Figure 22.
F
J96l
The phase angle between VMA and VAA should be
90' and then cp = 0, in our case cp increases with the
frequency according to the equation cp = tg- 1 w
R5C6, and inflences the amplitude of the output signal TACHO. In fig. 23 are shown the waveforms that
contribute to generate the TACHO signal. A and B
are the signals V AA and VAS in phase with the input
signals FTA and FTB. C and D are the signals VMA
and VMS: the continue line indicate the ideal case,
in fact the phase between VMA and VAA is 90' ; the
dotted line is referred to the real case in which the
phase is lower than 90'. By adding the two signals
shown in E we obtain the TACHO signal, whose expression is :.
Figure 24.
I/MA
~~bVMA
~l5
r\
f
I
wC6
I
,
:
~
,
IVAA
!, 'J9El.
1) VMA = VAA sin cp
cp = tg· 1
(J.I R5 C6
2) VMA = V AA sin
=R5 1
tg- 1
(J.I=2nf
(J.I R5 C6
f = frequency of the signal FTA
This last relation gives the amplitude of the signal
VMA ; it is evident there is not a linear function between VMA and (J.I, like VMA = K(J.I and the difference
is greater if the product (J.I R5 C6 doesn't respect the
disequation (J.I R5 C6« 1., i.e. at high frequencies.
5-5963
VTACHO = VMS. sign VAA - VMA. sign VAS.
The signals in E are reffered to the ideal case, the
ones in F to the real case. It is possible to demonstrate the mean value of the TACHO signal in the
real case is lower than the one we could have with
an ideal differentiator network and this explains why
in fig. 21 the speed of the motor increases more than
a linear funciton. The mean value of the waveforms F is (fig. 24).
21/23
301
APPLICATION NOTE
3) Vm =
It-cp
f- K1 sin ad a=
-cp
2K1
coscp
It
Figure 25.
Since the waveforms E are half sinewaves, the
mean value is
2 K1
4)V'm=~
We can conclude that two causes contribute to give
a TACHO signal lower than the theoretical one, both
due to differentiator network:
a) the amplitude of the signal VMA is lower than VMA
= Kro and we can call £1 the relative percentage
error.
sin tg· 1 ro R5 C6 - ro R5 C6
~~~~-=---=-,---~- . 100
£1 =
ro R5 C6
b) the mean value of. the signals VMA . sign VAS and
VMS. sign V AA is lower than the theoretical one because there is a shift in the phase of the signals VMA
and VMS. The relative percentage error only due to
the shift of the phase is
£2 = (cos cp-1). 100 cp = tg- 1 ro R5 C6
The total percentage decrease of the TACHO signal is given with a good approximation by the sum
of £1 and £2.
Example:
The value of the output current of the DAC 10 depends on Iref and on the digital code defined by the
inputs SC1-SC5, while its direction depends on the
value of the SIGN input, the max theoretical value
of 10, obtained with SC1-SC510w is:
10M =
±
31
16
Iref
The motor will run at a speed corresponding to the
following value of the TACHO signal:
31
VTACHO = - 10M . R89 = ±~ Iref . R89
16
C6 = 15nF
This last relation is true if we don't consider the
motor friction and the offsets. Consider now the
possible friction and the offsets. Consider now the
possible spreads we can have in the motor speed
due to the DAC. If we call1oM1 the value of the max
output current 10 corresponding to the SIGN LOW
and 10M2 the one corresponding to the SIGN HIGH,
the percentage error we have in the max speed from
the positive to the negative value is :
E2 =-2.6%
IOM1 + 10M2
Consider:
f = 3000Hz corresponding to
3000
. 60 = 900rpm of the motor if
n=
200
200 are the tracks/turn
of the encoder
£1 = - 2.6% withR5 = 8200
£3 = £1 + £2 = - 5.2%
10M
From the diagram of fig. 21 we note that at a speed
of 900 rpm corresponds· a theoretical speed of
855rpm with a percentage difference of about 5.2%.
SPEED ACCURACY DUE TO THE D/A
CONVERTER
To analyse the influence of the DAC precision on
the speed accuracy we will refer to the following
(fig. 25).
22/23
302
. 100
Note that we have consider the sum of IOM1 and 10M2
because they have opposite signs. This kind of error
is principally due to a different gain of the DAC between the two conditions of the SIGN LOW and
HIGH. An equal difference of IOM1 and 10M2, from
10M ( IIoM1 I - 110M I = I 10M2 I - 110M I ) doesn't constitute a speed error because this shift from the theoretical value can be compensated by adjusting the
resistor R89 that is formed by a fixed resistor in
series with a potentiometer.
~ SGS·THOMSON
~""I INOilD©I'iI@~~~It:'iTIRI@Il!D©ij;
APPLICATION NOTE
With the guaranteed values on the L291 data sheet
we can calculate for £4 the max value:
21
!lA
~~..
·100
= 1.5 %
1.4 mA
Another characteristic of a D/AC is the linearity, that
in our case is better than ± 112 LSB. This value is
sufficient to guarantee the monotonicity of 10, and
then of the speed of the motor, as a function of the
input digital code. The precision of ± 1/2 LSB implies a spread of the speed at every configuration of
the input code of ± 1.61 % referred to the maximum
speed. The max percentage error we can have is
then greater at low level speed (±50% at min speed)
and has its minimum value at the maximum speed
(1.61%).
ACCURACY DUE TO THE ENCODER
The amplitude of the signals FTA and FTB determines the value of the TACHO signal. This amplitude must be constant on the whole range of the
frequency, otherwise it is not possible to have a linear function between the TACHO signal and the
frequency. The spread of the amplitudes of the two
signals FTA and FTB between several encoder can
be compensated by adjusting the potentiometer R9
(see fig. 12). The phase between the two signals
should be 90' . If there is a constant difference from
this value, a constant factor reduction of the TACHO
signal results that can be compensated with the
potentiometer R9. If the difference from 90' is random, also the reduction of the TACHO signal is random in the same way, and by means of R9 it is
possible to compensate only the mean value of that
reduction.
23/23
303
APPLICATION NOTE
AN ECONOMIC MOTOR DRIVE WITH
VERY FEW COMPONENTS
INTRODUCTION
quenUy it is possible to drive it directly by means
of popular linear IC.
These characteristics are very suitable for motor
drive applications in general and make HIMOS the
new way of power switching in this area. An additional factor is that a HIMOS device has a smaller
chip area than Power MOSFETs, or bipolar transistors with the same ratings (V(SA) DSS and IDS max}·
The main objectives of this design are the economy and circuit simplicity which enable costs to be
reduced to a minimum. For this reason the design
is particulary suitable for domestic appliances powered by the 220 V AC mains. In this area, characteristics such as low cost, simplicity (and
consequently greater reliability) have priority.
With these objectives the choice of the power
switch is very important because the complexity of
the drive circuit, the number and the power of the
auxiliary supplies and the protection networks, depend on its characteristics. These factors lead to
the decision to use a HIMOS device (an IGBT) as
a power switch. The main characteristics of a HIMOS device are that:
- It switches high current with very low ON resistance, similar to a BJT (bipolar junction transistor).
It is very rugged and has very large safe operating areas similar to Power MOSFETs.
- It has high overload current capability.
- It is easy to drive (like Power MOSFETs) conse-
CIRCUIT DESCRIPTION
This DC motor drive circuit has a single switch topology and works in current mode; an STHI10N50
HIMOS is used as the power switch. The complete circuit schematic is shown in figure 1. Its main
features are as follows:
- 300V, 4A DC permanent magnet step down motor drive
- Current mode PWM control
- Output current adjustable pulse by pulse from 0
to 4A
- 220 AC ± 10% supply voltage
- 6KHz switching frequency
- From 6% to 95% operating duty cycle
Figure 1: Circuit diagram of the HIMOS motor drive
220V
AC
C1
"1SnF
;(
,20V
cJ
220}JlFT
"',[9
TR2.)
JR1
S6K
f--
1Bk
~
4
8
7
6
-
3
1
5
DC MOTOR
01
R6
3.3 K
RB
BYTOBPI4QO
TR111/ ~--Jf
10 nF ~ 02
STHI10NSO
47A
.£.7
1K
UC3842
2
101>.
2N2222 l..
RS
-
BYT03400
R10
(3..
nur-f
AN282/0589
OZ~ [t
C~
1BV 1I'1onT
P1
22K
R9
100K
.
I~
220pF
.~6
.~p
TsnF TnF
R11
18K
[8
J
:~30nF
R2
O.22n JR3
390n
1/4
305
APPLICATION NOTE
The PWM controller IC used is STUC3842. It is a
popular, economic eight pin IC widely used for offline and DC to DC converters. STUC3842 provides the features necessary to implement fixed frequency current mode control scheme with a
minimal external parts count.
Internally implemented circuits include under voltage lockout featuring start-up current less than
1mA, a precision reference, logic to insure latched
operation, a PWM comparator which provides current limit control and a totem pole output stage. It
can directly drive the gate of the 500V 10A HIMOS
switch STH110N50. The choice of this IC and its
current mode working matches the requirements
of economy and simplicity of this application.
Fig. 2 - STHI10N50 output characteristics
(I step = 6V)
Fig. 3 - STHI20N50 output characteristics
(I step = 6V)
.
~
liIj /
-
~/
:11
~ II
.
'
f
,-'-
-. •
~
~.
I
!!!
I
I
I
Ir3 ZIII!:OiI
..s:ii
'.
, 'I
' IP!.:!'
_.
~l!Ii
• '~'"'
:,C" -
,
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,
.
• •- !III
5
..
500
-,
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".
lIIV
-- .,.
--
_2/_4___________________________
306
A
2.5
The motor speed is controlled by the error voltage
which is variable from OV to + 5V, and is appliedto pin 2 of the IC by means of R9. This voltage sets
a constant current level at which the IC interrupts,
pulse by pulse, the current in the power switch: the
PWM control is therefore a "current mode" type.
The HIMOS switch used is STH110N50, for higher
power motors STHI20N50 can be used simply by
changing resistors R2 and R6 and free-wheeling
diode 01. Figures 2 and 3 show respectively the
output characteristics of STHI10N50 and
STHI20N50 devices.
An important part of the circuit is the snubber consisting of R3, C9, 02. This accomplishes two
functions:
a) it provides power for the UC3842 using the charge current of C9 during the STHI1 ON50 turn-off;
infact the IC requires about 20 mA DC as supply current and cannot be biased simply through
resistor R1 which should be 10Kohm 10W. Instead, using this active snubber, R1 can be set
to a value of 56Kohm 2W in order to apply the
start up power to the UC3842.
b) it reduces the energy dissipated in the power
switch during turn-off; consequently a smaller
heatsink can be used for STHI10N50 giving additional cost reduction.
To insure a continuous power supply to the IC,
using the active snubber C9, R3, 02, it is necessary that the capacitor C9 must be completely discharged before turn-off. Because C9 is discharged
by means otR3 during the ON phase of the power
switch, there is a limit to the minimum ON time
which cannot be less than 8 flos, consequently the
minimum duty-cycle is 6%.
Considering a peak current.lp = 4A, a fall time t f =
1.5 flos and the minimum ON time of 8 flos, the values of the snubber components are calculated as
follows:
C9 = (lp·t f)/2V cc = 10 nF
R3 = Ton (min/2. C9 =4000hm
The power dissipated across R3 is:
P = 1/2·C9·V2·f=3W
The adoption of this snubber does not affect the
efficiency of the circuit during normal operation because its power dissipation is very low and it has
the additional benefit of using this energy to supply the IC so reducing the dissipation in the power
switch. The extra cost is negligible with respect to
the cost of a transformer for supplying the low voltage powerto the IC.
The network of Tr2 and R6 adds a fraction of the
ramp oscillator voltage to the "current sense" si-
~~~~~~~~:~~~----------------------------
APPLICATION NOTE
gnal at pin 3 of the IC (via transistor Tr2 2N2222)
to allow slope compensation. Consequently dutycycles as high as 50% can be obtained.
Diodes D1 (BYT08PI400) and D2 (BYT03400) are
fast recovery types and have been used in order
to minimize stresses on the power switch.
MEASUREMENTS ON THE CIRCUIT
The DC motor drive was tested in several operating conditions. These were maximum and rated
output current and in blocked rotor conditions.
The waveforms of the drain voltage, Vos, drain
current, 10 , and gate voltage, VG , both with and without the snubber can be seen in figures 5 and 6
respectively.
Fig. 4 - STHI10NSO turn-off with snubber Id=
1A1div, Vds= VSOldiv, Vg=SVldiv
Here you can see the typical behaviour of a HIMOS
device at the turn-off when typical features of both
Power MOSFET and BJT are involved. The storage phase of the turn-off is dependent on the MOS
behaviour as the base collector junction of the PNP
transistor is reversed biased: the gate voltage decreases to a point where the Miller effect begins
to control the current in the drain and Vos start to
rise. The fall time phase can be divided into two
parts: the first part is the MOS turn-off and is very
fast, the second is slow and starts when the MOS
channel is closed and the PNP transistor has an
open base turn-off and is dominated by recombination of excess carriers. Therefore the first part
of the time is controlled by the gate drive circuit,
the second part is dependent on the PNP transistor life-time and gain.
Since the PNPgain increases as Vos increase,
the fall time consequently varies with Vos. Therefore, when the snubber is used and the Vos slope
is dominated by the capacitance, the fall time region due to the MOS is more evident (figure 6).
Figure 6 shows the turn-on behaviour of the HIMOS: it very fast (t-rise 30ns) and, as with Power
MOS devices, is a function of the impedance of the
driver circuit and the applied gate Voltage.
Fig. 6 - STHI10NSO
Vds=SOVldiv
turn-on
Id=
1Aldiv,
Fig. 5 - STHI10NSO turn-off without snubber Id=
1A1div, Vds= SOVldiv, Vg = SVldiv
Figure 7 shows the behaviour in the case of a blocked rotor and with the current control set at the maximum 4A. This condition was simulated, as worst
case, with and inductance of 300uH and a resistance of 1 n: the current does not exceed 6A. The overcurrent of 2A, with respect the control current of
4A, is due to the delay introduced by the network
_____________________________
~~~~~~?¥~~~©~
___________________________
3_/4
307
APPLICATION NOTE
of R7, C7 of about 2 fls. This filter network is necessary to suppress the leading edge spikes on the
IC current sense comparator input.
The losses in the circuit, for the maximum rating
of each component are approximately as follows:
P(R1)=2W, P(R3)=3W, P(R2)=3W, P(D1)=4W,
P(Tr1)=7W.
Fig. 7 - Blocked rotor' beheaviour Id= 1A/div,
Vds= 50Vldiv, Vg = 5Vldiv
CONCLUSION
A 300V 4A DC permanent magnet single quadrant
motor drive was developed with objectives of maximum circuit simplicity and economy, Consequently a current mode PWM control with a popular IC
was adopted and an STHI1 ONSO HIMOS (an IGBT)
was used.
The low drive energy requirement due to the high
input impedance of the HIMOS allows substantial
cost reduction in the control circuit. Conductivity
modulation of the drain produces a low ON resistance, an essential feature to work with high peak
currents in the switching element. The ruggedness,
due to the excellent safe operating areas, is especially relevant for motor control applications.
The easy drive, high current handling and excellent ruggedness make HIMOS the new way of power switching in the motor control field.
;;;;;
10.1 U
3
IDa·· •
n
. . ....
'"
'P'"!: ~
:' III :~ .....
~t;f~ .... .... ....
• Omlt!
Ei~u
.... .. ,
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....
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... !'!iIi
'II"I!.
,!'!JI.
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1
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., .... ....
~
l~
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.... ....
50 ns
_4 /4_ _ _ _ _ _ _ _ _ _ _
ru SGS-THOMSON _ _ _ _ _ _ _ _ _ _ __
•/."
308
Ii:llJ©Iiil@~'L~©lIliil@,;;]O©§
APPLICATION NOTE
VERSATILE AND COST EFFECTIVE INDUCTION MOTOR DRIVE
WITH DIGITAL THREE PHASE GENERATION
B. Maurice/JM. Bourgeois/B. Saby
INTRODUCTION
The three phase induction motor is a simple design,
rugged, maintenance-free which appears in home
appliances requiring cost effective solutions. For
speed control of these motors, a frequency variation
of the Inverter output voltage is required. The voltage/frequency ratio must be maintained constant,
so control of these motors normally require complex
control circuitry for the generation of the balanced
three phase sine wave outputs.
l!sually the generation of the three phase PWM
signals may be controlled by a dedicated circuit,
such as the SGS-THOMSON L6234 which is
driven by a separate microcontroller. This solution
is optimum while performance prevails over cost.
The solution demonstrated in this application note
is a simplified solution using a standard ST9 microcontroller which includes large on-chip ROM memory and an internal Direct Memory Access (DMA)
controller. This combination reduces the need of
dedicated ICs (hardware being replaced by software), and allows over 50% of the CPU time to
perform control, environmental and supervision
tasks.
A practical solution to quantize three phase sine-
AN424/0292
waves, and to create the corresponding DMA table
is shown allowing motor voltage and motor frequency to be chosen independently. A dead time
avoiding cross conduction through the bridge is
also created by software. Very low acoustic noise
operation can be achieved despite a switching
frequency below 10kHz, due to a shifting of the
switching instants leading to a virtual doubling of
switching frequency.
Each of .the six digital outputs of the ST9 sets
directly the state of the six power MOSFETs (or
IGBTs) of the bridge via an insulated interface. This
interface is described in the second part of this
note. The fully isolated pulse controlled gate driver
requires no floating auxiliary supply, meets safety
standards and achieves a large dV/dt immunity.
Figure 1 shows how to generate a three phase sine
wave by modulation of pulse width. This modulation is often obtained with a special dedicated IC
controlled by a MCU (above).
Using a MCU having large memory integrated on
the chip combined with DMA, spares the use of
dedicated IC (below). Hardware is replaced by
software. The sine waves are directly synthesized
by the MCU.
1/14
309
APPLICATION NOTE
Figure 1. Three Phase PWM Generation Techniques
+
Vee
DC line
MCU
dedicated IC
VR001508
+
Vee
Deline
ST9 MCU
with
DMA
'-------,.v,----"/
Pulse con trolled driver
_~1_4_ _ _ _ _ _ _ _ _ _ ~~~tn&~~~91
310
VR001509
___________
APPLICATION NOTE
DIGITAL CONTROL OF POWER SWITCHES
In this proposed solution, the ST9 microcontroller
controls simultaneously the ON- and OFF- states of
the six power switches of the inverter bridge. All
these instantaneous ON-OFF states are stored in
internal memory (ROM) and are sequentially transferred (every 5s for example) to six bits of a parallel
output port by DMA(see Figure 2). The voltage level
0-5V of each output bit drives directly the gate
interfaces of the six power switches.
All data corresponding to the switching duty cycle
values is permanently stored in ROM and generates the quantized three phase sine waves. A dead
time between adjacent Power switches is also
stored, avoiding cross-conduction through the
power bridge. The motor frequency and motor voltage are also stored independently.
The major part of the ROM is occupied by this
permanent data, used 'to generate, step by step, the
three phase sine-waves. This data is grouped in
several tables (patterns), constituting series of
bytes that have to be sequentially output on the
parallel output port. A full scrolling of each pattern
corresponds to a complete switching basic cycle of
the six power switches. This is repeated the necessary number of times to complete the step duration
of sine wave. The following pattern will then be
scrolled to realize the fo'!owing step.
This direct sequentiai"tran$fer from memory to output port is performed by DMA [2), and is self operating. The central unit only works when the last byte
of one pattern appears, the program then deter-
mines whether the same pattern must be scrolled
again, or if another new pattern has to be scrolled.
All patterns needed for an application, as well as
the program managing their scrolling order and
their number of repetitions, are to be created and
stored in ROM.
MOTOR DRIVE CONFIGURATION
Microcontrolier
The ST9036 microcontroller from the ST9 family
with 16k-byte of ROM or EPROM memory [1), of
which only one output port and one multifunction
timer are used for PWM generation. Six bits of its
output port are gathered in pairs, one pair for every
bridge leg (phases: u,v,w). The two bits remaining
free can be used, for example, either to control two
other power switches (i.e for heat control in a
washer), or to generate a synchronized signal to
perform measurement of V/I phase.
The ST9 microcontroller is able to manage two
further functions:
a) Slow operations for motor and environment controls, such as timing of sequential operations,
speed control, safety supervision tasks, etc. (These
are not detailed in this application note).
b) Faster operations for real time management of
the states of the power switches for PWM generation.
All others functionalities of the ST9036 remain
available, such as other I/O ports, Timers,
Analog/Digital converters and all interrupt functions.
Figure 2. DMA Transfer to control power switches
ST9
MICROCONTROLLER
--_. __......_.. __.__._.•..•_-----_._......,---
Voltages on
Microcontroller MEMORY
~ Patterns --~'#4
#3
#2
+
Deline
output port
#l
""" 1
010101
010001
011001
011001
gHg~g
101010
101010
101010
•
j7DMA
tIme
5
0
5
1010LO
101010
101010
001010
OllOOO
0
.g'"
u
2
c
011001
011001
Dllon
~
010001
011001
011001
011001
011000
001010
101010
101010
101010
l01010
101010
101010
001010
011000
0
5
X
not used
X
011001
5U~g~
010001
010101
- - - - - - - - - - - - - - - ~~~~;~~~~~~~
VR001519
3/14
311
APPLICATION NOTE
Figure 3. Driver for one Bridge Leg
Vee
Tl
bit Nbr 0
From Microcon troll er
Output Port
Phose U
SECONDARY
with
Short circuit
Protection
bit Nbr 1
T2
I sense
VR001510
In the practical example described in the following
sections, ST9 is not heavily occupied by these real
time operations:
Using DMA is similar to slowing down the ST9
and engages only 35-40% of the CPU time.
Speed control (frequency variation) needs only
few instruction lines but no memory space. The
memory space is mainly used to store necessary data to generate six various three phase
voltages supplying the motor (1 k-byte for each
voltage).
Drivers For Power Switches
The driver interfaces the ST9 output port to the gate
of the power switches.
it converts the output level (5V) to the required
gate-source voltage level (15V) of IGBT or
Power-MOSFET.
it provides a galvanic isolation.
it protects against current surges and short
circuits.
It is constituted by six independent circuits for the
six power switches. Each is a pulse controlled driver
[4] including: (see Figure 3)
a primary circuit to create a calibrated Pulse
with short duration.
a small pulse transformer.
(DIL molded package)
a floating secondary circuit operating without
any auxiliary supply and including the autonomous short circuit protection.
The primary circuit differentiates the logic level input
signal. The positive and negative calibrated output
pulses (±15V/0.5Ils) correspond to the switch-
on/switch-off command. The primary circuit output
stage is a full bridge having a low output impedance
in order to obtain short rise times and high amplitude current pulses.
The pulse transformer can be small. A ferrite core
of 6.3mm diameter with 10 turns is sufficient as it
has to sustain 15V for O.5lls. In this application,
three core transformers are' housed in the same
standard or SMD package [3].
The secondary circuit needs no supply and uses
the input gate capacitor of the Power-MOSFET or
IGBT like an R/S memory. latch. The required energy is limited to charge and discharge the input
gate capacitor. During the OFF-state, a low impedance is maintained across the gate-source of the
Power switch, avoiding any reconduction due to
externally applied dV/dt.
Figure 4. Transformer Core Size vs 16 pin OIL
VROO1511
4/14
~ SGS-1HOMSON
- - - - - - - - - - - - - - ""'11
liIilo©oo@rn~rn(i;"[lOO@;i!JO©i!i5
312
--------------
APPLICATION NOTE
In several applications, when isolation between the
power and control sections is not mandatory, the
low side driver can be a simple non-insulated driver.
Nevertheless, the fully isolated solution performs
high dV/dt immunity and meets insulation standards.
If ou is sinusoidal modulated, the average voltage
on half bridge middle point describes sinusoidal
wave form centered to Voc/2. To avoid DC components in the motor, each phase voltage has to be
symmetrical compared to Voc/2.
Motor voltage value
DC/AC Inverter
For this function, a three-phase bridge with six
switches (Power-M08FETs or IGBTs) is used. (Figure 1). The two switches of each bridge leg are
opposite phase controlled. A dead time, avoiding
simultaneous conduction, is generated directly by
the 8T9036 microcontroller.
Motor voltage is maximal when the duty cycle
modulation varies from 0% to 100% (modulation
depth: K=1 00%)
Motor voltage is minimal (nil) when modulation
depth K=O; 0 does not vary and is equal to 50%
(Figure 5b)
Sine wave frequency variation
Sine wave generation: (Figure 5)
The voltage on middle point of "u-phase" bridge leg
is given by:
Vu = Voc.ou
0= ton hilTs
Vuw = Vu - Vw
= u-phase duty cycle
ou
ton hi = "ON state" duration of
high side switch
= switching period
Ts
Vuw = phase to phase motor
voltage
This is obtained by varying the frequency of the duty'
cycle modulation.
CREATING TABLES OF DATA
The variable speed drive of induction motors requires generating three voltage sine waves and
control of their amplitude, phase and frequency.
The first step is to digitize the three phase system
in order to create all the necessary data to be stored
into the ROM of the 8T9 microcontroller.
Figure 5. Sine Wave Generation at the output of one bridge leg
a. Modulation depth 60%, duty cycle 20 to 80%
b. Constant duty cycle
Ts
r-----J
Vu
0=80%
ton hi
0=20%
P"",:D:1 g\floooBib[U---8:;;: ~::
p""",:D:1 8---il---ildl:ft:EJ 0 EJ8-il
P"",:D:11f1ftEHbil ~ JkR-f1nt
pb"",:D:1
8\n-n-Tfo-n--BnnnBSD%
VDC
VR001518
--~-----------
~ SCS-1HOMSON
b.."'!§
iiII,©WilJ~~lli©1flB@jlJD(i;§
5/14
--------------
313
APPLICATION NOTE
Fundamental period quantification
The fundamental period of motor voltage is divided
into 24 "segments"; (each segment equals 15· of
arc). This gives a good sine wave accuracy in ma~y
applications. During each "segment" the voltage IS
a percentage of the DC line voltage, given by duty
cycle (0). For example, the duty cycle must be 55%
during the segment from 165· to 180· for phase U
(Figure 6).
Creating the duty cycle table
The second step is to establish a table giving, for
each segment, the duty cycle value (0) for each of
the three phases. In fact 01, 03, 05 are duty cycle
values for each high-side switch (T1, T3, T5). The
low side switches are in the opposite states and
their duty cycie value is complementary to 100%.
This entire table defines exactly the three-phase
sine wave system during one period (To) and for
one motor voltage. (Figure 7) These table values
respect phase balance and avoid neutral currents.
To achieve these conditions it must be ensured that:
a) on each line, the sum of the three duty cycle
values is constant (equal to 150%).
b) The duty cycle has a symmetrical value either
side of 50%. In practice the quantized values have
to be chosen close to the mathematical value of
sinus for only a quarter of the period, then symmetrically repeated respecting the condition (a).
This duty cycle table is not stored in ROM. It, only
defines the necessary data to .create the patterns.
One line of this table defines one pattern (see
following section).
Figure 6. The fundamental period divided into "segments"
Deline Voltage
50
150
segment _
of period
250
!-- TO/24
I
fundamental period TO
VR001513
6/14
314
~ ~itltl~~911
--------------
APPLICATION NOTE
Figure 7 . Duty cycle table defining data to create patterns VPHASE = O.6XVLINE
V
01%
W
#
03%
05%
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
80
80
75
70
60
55
45
40
30
25
20
20
20
20
25
30
40
45
55
60
70
75
80
80
40
45
55
60
70
75
80
80
80
80
75
70
60
55
45
40
30
25
20
20
20
20
25
30
30
25
20
20
20
20
25
30
40
45
55
60
70
75
80
80
80
80
75
70
60
55
45
40
Pattern
U
Pattern definition
A pattern is a succession of bytes stored in memory.
Each bit (1 ;O) of these bytes gives the instantaneous state (ON;OFF) of each of the 6 six power
switches (Figures 7&9). Pattern contains number of
bytes necessary to define one entire basic switching cycle.
A particular pattern has to be created for each
segment of the sine wave period. All these patterns
are stored in the ST9036 ROM.
For example (Figure 8), a pattern contains sequence of 42 bytes defining one basic switching
One Pattern
010101
010101
1J10001
011001
011001
011001
011000
001010
101010
101010
101010
101010
101010
101010
001010
011000
011001
011001
011001
010001
010101
010101
010101
010001
011001
011001
OU001
011000
001010
101010
101010
101010
101010
101010
101010
001010
011000
011001
OU001
011001
010001
010101
cycle. The switching period Ts, shared into 42 units
of times, gives a good sensibility of duty cycle
adjustment of about 2.5% (1/42th). This time unit
corresponds to the rhythm of the DMA timer and its
duration is chosen as a multiple of the ST9 microcontroller clock period (O.25fLS).
In this example, one unit of time equals 4.75fLS in
order to have a pattern scrolling time or switching
period Ts = 200fLS. This corresponds to 5kHz of
switching frequency.
Two dead times (one time unit each) at every state
change of adjacent switches avoid cross conduction of the bridge leg.
315
APPLICATION NOTE
Figure 8. Example of switching cycle for transistor Tl
Vu (% of DC line)
100%.-______________________________________- .
+ DC line
I/V
I/V/
//V
/
/1/
.......--ou
//V/
/
/1/
/
/
/V//7
/
/
/7
I' /
30 ,L ,/.. /..
Vu
/
/ /
/
/
/ /
/
/
/ / /
/
/
//
////
/
o ///
1
////
3
5
7
9).: 11
13
Segment #9 : 6
15
17
19
21
23
= 30%
Repetition of 5 basic switching cycles
Vu
-
saSiC switching cycle
(;
T1 Gate
I
+
I
ON
OFF
Sequence of 42
1 1 1 1 1 1 11 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 / logic states
I
I
T
unit of
• t
time
ton
Ts : Basic switching period including 42 units of time
VR001520
_8/_14
________________________ l:1,f~~~~~~~9©~
316
__________________________
APPLICATION NOTE
Figure 9. Pattern table
to output
buffer
dead time
one pattern
time
a
Phose W {
Phase V {
00
o~
a
a
00
Phose U {
00
a
00
a
If)
nb. timer
underflow
o~
I<-N<")'
0=30%+30%) . The switching frequency is doubled
and acoustic noise is close to the inaudible region
and becomes very low (Figure 12d)
Figure 12. Pattern options affecting ripple and acoustic noise
T5 _ _ _ _ _ _ _ _ _ _ __
T3 _ _ _ _ _ _ _ _ _ __
Tl _ _ _ _ _ _ _ _ _ __
a
Switching
instants
T5 _ _ _ _ _ _ _ _'--_ __
T3 _ _ _--'_ _ _ _ _ _ _ _ _ __
b
Tl _ _ _ _ _ _ _ _ _ _"--_
Switching
"
II
instants
T5 _ _ _ _ _ _ _ _ _ _ __
T3 _ _ _ _ _ _ _ _ __ _
Tl _ _ _ _ _ _ _ _ _ _ _ __
T5 _ _ _ _ _ _ _ _---'_ _ _ __
T3_~_ _ _ _ _ _ _ _ _BL_ _
d
Tl---'_ _ _ _---'_ _ _ _L -
-
______ _______
~
-
T3 ______
~
T5 _ _ _ _ _ _ _ _ _ _ __
T1 _____. .______~_ _ _L _ _
VROA1526
12/14
320
APPLICATION NOTE
EXPERIMENTAL EXAMPLES
Figure 13 shows an example of generated three
phase PWM signals on microcontroller outputs. It
represents three control signals for T1, T3, T5. The
set of pattern corresponds to a modulation depth of
100% as shown on table Figure 10a. The phase
angle between each phase is 120%.
Figure 14 shows current measured in motor phase
(20ms/div, 2A1div).
a) obtained with set of pattern shown on Figure 10b,
and repeated twenty time, f= 10Hz
b) patterns are repeated twice, f=1 OOHz.
The used set of pattern (at 60%) of Figure 10b,
combined with doubly of switching instants (Figure
12d), gives a well defined sine wave.
Figure 13. Three microcontroller outputs:
5ms/div,5V/div
T5
controll[I[III~.1111
1111_111[1111111'
, .
,
I
T3 control
Very little ripple of current and doubling switching
frequency give a noiseless motor operation.
The motor is speeded up by repeating patterns only
twice (Figure 14b). Simultaneously the motor voltage is increased by using set of pattern (Figure 10a)
having modulation depth of 100%.
J
5ms/sqr
5V/sqr
Figure 14. Current measured in motor phase
~ SCS-mOMSON
- - - - - - - - - - - - - - A"'I!
~D:<;OO@~c~©UOOQ;@:D©\\)
13/14
--------------
321
APPLICATION NOTE
SUMMARY
For large volume applications such as washing
machines, air conditioning or cooling pump motor
drives, cost optimization is a key issue. The solution
to drive induction motor presented in this paper
simplifies conventional digital solution. Using a ST9
microcontroller with Direct Memory Access and fast
data transfer, replaces dedicated ICs by software
or more precisely by data stored in microcontroller
memory.
The proposed solution is very versatile because a
standard microcontroller, the ST9036, can be programmed for various applications, only the software will has to be adapted.
This note presents methods to generate data in
order to shift the switching instants of inverter
switches. This allows to reduce motor acoustic
noise in spite of· switching frequency being below
10kHz, and to minimize motor and converter
losses.
The described pulse controlled gate driver uses
standard components and small enough core
transformers that can be fitted into a Surface
Mounting Package. This way offers a cheap fully
galvanic insulation when required.
REFERENCES
[1].SH family high performance 8/16 bit MCU
SGS-THOMSON Microelectronics - Info pack
[2].3-phase motor drive I,Ising the ST9 multi-function timer and DMA
B. SABY - SGS-THOMSON Microelectronics - Application Note.
APPENDIX MICROCONTROLLER WITH DMA
The feature of microcontroller with DMA (direct
Memory Access) consists in having a possibility of
direct access between microcontroller memory and
its on-chip peripherals. Moreover, one of the parallel 1/0 ports can be coupled with the timer's DMA
channel, allowing fast data transfers between
memory and this 1/0 port with minimum CPU overhead. Data transfers are scheduled by the timer.
The only task of the Microcontroller software is to
specify which pattern is to be read by the DMA
channel at a given time in order to reproduce the
three-phase sinewaves, as described in the previous sections. After a complete pattern transfer,
the Micro-controller CPU is interrupted (DMA End
of block interrupt) and the DMA should start to read
the next pattern.
In order to achieve high speed continuous transfers
without stringent response time requirements for
this End of block interrupt, a "swap mode" is used:
while a pattern is read by the DMA channel, the
subsequent pattern can be prepared in advance;
so, once the last byte ofthe pattern is read, the DMA
automatically switches to the new pattern while the
old one can be updated during the DMA End of
block interrupt routine.
First tests show that the DMA operation in swap
mode, as described hereabove, accounts for 3540% of the total available CPU time of the Microcontroller. Therefore, thanks to its processing
power, the Microcontroller can easily perform any
control and supervision task in addition to this
DMA-driven PWM generation.
[3]. Data-book of F.E.E 39270 Orgelet France
[4].New Isolated Gate Drive for Power MOSFET
and IGBT
JM. BOURGEOIS - E.P.E' Firenzell Sept 1991
.[5].External DMA mode: 1/0 data transfer synchronized by tirner
P. GUILLEMIN - SGS-THOMSON Microelectronics
~Application Note AN418
[6].Environment design rules of MOSFET in medium Power application
B. MAURICE - P.C.I.M. Munich/G 1989 - Proceedings book
_14_1_14________________________ ~~~~~~~:9~
322
___________________________
APPLICATION NOTE
MOTOR CONTROL DESIGN USING VERTICAL
SMART POWER ICs
by R. Lelor, M. Melilo, A. Galluzzo
ABSTRACT
Readily available smart power devices can
greatly simplify a power designer's design
task by releasing him from the problems of
designing high current control circuits.
Whilst making this aspect of the design
transparent to the user, smart power ICs only
require a standard logic compatible input signal.
These features are illustrated by practical
examples of motor control using two different
circuit configurations, a single switch and a full
bridge circuit, working in continuous and in
switched current modes.
The paper demonstrates that the problems
of motor control (stalled motor, overload,
etc .. ) are simply and successfully resolved
by using smart power devices.
AN481/0492
The devices contain an integrated vertical
current flow power MOSFET, high side gate
drive, maximum current control, protection
circuits and a diagnostic status output.
The input and output control functions directly
interface to a microprocessor allowing
comprehensive control and fault diagnosis
of the condition of the load, i.e. short circuit,
open load and overload.
Designs safe-guarding the circuit against
extreme working conditions are considered,
such as a power supply disconnection with
an inductive load.
Finally, future developments in smart power
Ie design for motor control are reviewed.
1/10
323
APPLICATION NOTE
1.0
INTRODUCTION
In many application areas such as robotics,
process control, automotive actuators, etc,
the DC motor control board is, in effect, a
power peripheral device of a micro-processor
or micro-controller system.
Attaining high current, low power dissipation
and effective diagnostic feedback with these
peripheral boards can be a problem.
Using smart power ICs helps to overcome
these difficulties and, additionally, provides
a bonl)s: compact designs due to the reduced
circuit size as a result of the integration.
The technology, one of three Vertical
Intelligent Power (VIPower TM) technologies,
that includes, on a single silicon chip, a
vertical current flow power MOSFET and
analog and logic circuits, has allowed
different families of devices to be produced
that satisfy a wide range of applications.
Integrating a sense-FET on to the smart
power ICs allows very high current, equal to
that of discrete power MOSFET devices, to
be controlled, resolving the problems of high
current sensing even at high switching
frequencies.
This leads to the possibility of making a
wide range of interesting devices in a variety
of packages with high power dissipation,
some of which can be surface mounted.
The integration of analog and logic circuits
that perform the various protection,
diagnostic and current control functions,
permit the deSign of a system where the
peripheral circuit protects itself and the
motor.
The micro-processor is able to handle the
motor being aware of its working conditions.
2110
2.0 MAXIMUM CURRENT LIMITATION
AND CONTROL.
Current sense together with current limiting
circuits are necessary in motor driving
circuits, both for protection problems in
overload conditions and in motor torque
control.
The delay, the accuracy and the working
mode of these circuits can be varied
according to the application requirements and
with the working mode (switching or
continuous).
2.1 CURRENT SENSING.
The following disadvantages of the standard
current sense circuits using a sense resistor
or a current transformer highlight the
advantages of using an integrated current
sense circuit with a sense-FET:
- there is power dissipation (Pd=RsensI2)
- a high peak voltage is generated across
the stray inductance due to the high
switching speed (V peak = Lstray di/dt).
- the noise tolerance of the control circuit
is adversely affected due to capacitive
coupling.
Figure 1 shows that the sense-FET works
as a current mirror so only a part of the
current flows through the sense resistor,
hence the power dissipation in the sense
resistor is very low. In addition to this the
integrated device requires less wiring. As a
result there is less stray inductance. This, in
turn, means it is possible to design a current
sense circuit for very high switching speeds.
If linear and accurate current control is not
necessary, other methods of current sensing,
such as detecting the saturation voltage or
monitoring the junction temperature of the
power sensing element, can be successfully
employed.
------------- '" ~~~~1tl~~:oo~!:~ -----------324
APPLICATION NOTE
Figure 2 shows the generic block diagram of
the SGS-THOMSON Microelectronics high
side intelligent switch.
Figure 3 shows that when a smart power IC
temperature sense circuitry protects the
device to prevent its destruction in overcurrent conditions, the over-temperature
circuit turns the integrated power switch off
at a safe operating temperature (140°C). This
type of protection depends on the ability of
the device to dissipate heat.
2.2 CURRENT LIMITING WITH VIPower
The current limiting can be achieved using
linear or chopper techniques. Both solutions
allow the current control to be relative to an
external command and/or to internal
parameters (internal references, junction
temperature, voltage drop across the power
transistor during the on state, etc.) as shown
in figure 4 and 5.
o
Vsens.
o
_IL_ 01000
Isens.
0
VERY LOW
THANKS TO INTEGRATION
Vsens 0 Rsens.·ILll000 + Lp.sens'd(lL/l000)/dl
Figure 1 - Integrated current sense using a
sense-FET and ON state equivalent circuit.
Vee
'"'"' ".:•.
STATUS
=.-~~,~
~
~ ~""U
"",,;;-J- I:
[-- ~ENT i
()
~~ROL
[I;
5
LOAD
TEMP.
3.0 DRIVING HIGH SIDE N-CHANNEL
POWER MOSFETs
A Power MOSFET used in high side
configuration requires a voltage greater than
the power rail, high enough to turn on the
device in full saturation.
This supply can have different configurations
depending on the working conditions.
There are different methods of generating
this gate drive voltage.
The charge pump technique can be used
which is suitable for the continuous working
mode or there is the bootstrap circuit which
is suitable for switching applications.
These techniques or a combination of them
can be integrated into the control circuit of
the VIPower ICs, but some integration
problems must be considered.
Lp
/
[i]
GROUND
Figure 2 - Block diagram of a VIPower Ie showing
the main sense circuits.
lload
1
Inn r,
Tj~~~;~:g
status
11-----.
nn[
Figure 3 - Overload working mode of the VIPower
intelligent switch, VN05
3/10
---------------------------~~~~~~~::~ ---------------------------
325
APPLICATION NOTE
They are:
the silicon area is proportional to
capacitance value.
number of pins must be limited to reduce
the cost of the package.This means that
the design of the drive circuit must be
the best compromise between silicon
area, number of pins and in the
application under consideration that can
have the following requirements:
continuous working mode, switching
working mode, or both.
low switching losses (fast turn-on).
low voltage applications typically 6 to 36V.
complete turn-on of the power transistor
in all working conditions.
Figure 6 shows the schematic of an
integrated charge pump circuit that ensures
sufficient gate-source voltage even if power
supply is 5V or less.
This circuit multiplies the power supply
voltage by three.
The integrated charge pump can only supply
a few milliamperes and is therefore limited
to use in continuous mode applications (i.e.
solid state relays) because it needs a few
hundred microseconds to generate enough
charge to turn-on a Power MOSFET.
For switching applications, an external
bootstrap capacitor can be connected to an
internal control circuit, and, to ensure 100%
duty cycle, both the charge pump and the
bootstrap methods can be used (figure 7).
Figure 8 shows the turn-on switching
behaviour of a VIPower Ie with cr: Power
MOSFET output using a bootstrap circuit to
generate the gate drive voltage.
The switching time can be optimized in order
to match low switching dissipation and
electromagnetic compatibility.
4/10
Vee
r--------------0
1............. 1
I
¢r. . . . ·!
I L........ 1
GND
L-------------I----~
Figure 4 - Continuous current control in a VIPower
IC
Vee
1----------------
I
.-------------r-----,
I
G NO
Figure 5 - Switched current control in a VIPower IC
Vee
Ichrage = C*V~F
Figure 6 - Integrated charge pump that multiplies
Vee by 3.
- - - - - - - - - - - - - l i f i ~~~~m~::~~~
326
I
I
Ii
..............
Ii.
-------------
APPLICATION NOTE
Vee
----~~---r----..
Y-
...... -:-. r·...·~-r .......... ,.,..~-(~.~ .... ..--l,r~-.·,"" ..r-J._y-t-..~"....~"l'-l'i._~
:
\...../
,
(!]
j
(!]
,
I
I
y-----'
Figure 7 - Bootstrap and charge pump in a VIPower
IC, allowing switching and continuous mode.
Figure 8 - Switching waveforms of output voltage
and current in a VIPower IC V = 5V/div, I = 5Ndiv,
t = 1 us/div
4.0 FAULT DIAGNOSTIC.
The ability to process the diagnostic
information is very important in the design of
fault tolerant systems.
In a motor drive circuit, this process can be
complicated due to the changing working
conditions of the motor and to the large
variety of fault conditions, stalled motor,
overload, open circuit due to the brush
deterioration, etc.
The control circuit of a VIPower Ie must be
able to recognize these fault conditions and
others, such as power supply failure, and
differentiate between various fault conditions
using a minimum of output pins and to be
able to filter out false alarm signals.
This feature is achieved by the integration of
a digital delay network and logic circuit that
can, for example, operate as follows:
If a short circuit exists, when the device is
turned on the VIPower IC internally limits
the current and, after 33ms, it turns-off and
the diagnostic output goes low.
-------------
If an open load exists (lout < 50ma), when
the device is turned on, then the diagnostic
output goes low after 2ms.
If a fault condition appears during normal
operation, the diagnostic output goes low
immediately and the device turns-off.
If the device turns-off due to a fault condition,
the control circuit must be reset by taking
the input low.
These functions make it possible to
discriminate between a false alarm signal
given when the motor starts up and there is
an in rush current or due to the inductive
behaviour of the motor which can cause a
low current for few Ils.
By exploiting these features, it is possible to
create a program able to interact with the
VIPower IC and to identify the nature of the
fault condition; this is illustrated in figure 9.
A tri-state output can be used if only two
fault conditions are to be identified.
~ ~~~~~~~r::oo~©~
-------------
5/10
327
APPLICATION NOTE
RESET
==-1 ~
INPUT _
,/
I
' " " " 'r
""'---_
I
SHORTC.
,
, ,
:
"
OUTPUTU
CURREN
:
,
,
,
,
'OPB:N C.
DIAG.
OUTPUT
,
33ms
'2ms'
Figure 9 - Timing diagram of the diagnostic system in the VM201 intelligent switch and flow chart of a
subroutine able to differentiate fault conditions.
5.0 MOTOR DRIVE USING TWO VERTICAL
SMART POWER ICs IN A FULL BRIDGE
CIRCUIT.
5.1 CIRCUIT DESCRIPTION.
The circuit in figure 10 shows how a very
simple motor drive for an automotive electric
window lift can be made using two high
side smart power solid state relays and two
discrete power MOSFETs in a full bridge
configuration.
The SGS-THOMSON VIPower ICs used,
VN05, have a very low RDS(on) (150 mQ),
maximum current limiting at 15A, undervoltage detection at 6.5V, thermal shut down
(150°C), over-temperature and open circuit
diagnostic output and a digital filter that
makes the device able to distinguish between
real and false fault conditions. The VM201,
a power MOSFET plus the control circuitry
integrated on to one silicon chip, provides all
these features in a 5 pin HEPTAWATT
6/10
package. Each half of the bridge is comprised
of one VM201 and one standard power
MOSFET.
The motor control board is CMOS and TIL
compatible. This is possible because of the
CMOSniL compatibility of the VIPower IC
input and output and to the use of a low side
CMOS buffer driver.
The free-wheel diodes are the intrinsic diodes
of the discrete and integrated power
MOSFETs. No power sense components
are needed as the VIPower IC has an internal
sense-FET.
In this application, the purpose of the
diagnostic output (open COllector), is to detect
the stalled motor condition to protect the
window at its extremes of travel and any
accidental obstruction, eg an arm or dog!
-------------------------- ~~~~~~~::~~-------------------------328
APPLICATION NOTE
This condition is characterised by an overload
current caused by the stalled motor.
The ability of self decision of the VIPower IC
and of interfacing software as shown in the
previous section , 4, enables the circuit to
filter a false stalled motor condition and to
safeguard the power devices from over
temperature stress.
Open load fault diagnOSis can be used to
recognize deterioration of the motor brushes.
5.2 BEHAVIOUR OF THE VIPower
DEVICES.
The low ROS(on) (1 OOmn), allows the devices
to work at a high ambient temperature.
The worst case blockage of the window
creates a current in the motor of up to 7A 8A causing on-state power dissipation in
the VIPower IC of 10W - 13W at a junction
temperature, Tj = 100°C. This condition
allows the devices to operate under the worst
case conditions with a Rth junction-ambient
< 8°C/W, and with T ambient = 50°C.
This
avoids over-temperature detection during
normal operation.
The figure 11 shows the behaviour of the
current in the motor and of the diagnostic
output during turn-on and turn-off. This
behaviour is due to the overload current in
the motor when the window reaches its limits
of movement or is physically obstructed.
6.1 POWER SUPPLY DISCONNECTION
DURING OPERATION.
In some applications, such as process
controls, the main power supply protection
system can, under certain conditions,
disconnect the power supply during
operation.
If the loads are motors or inductive loads,
the collapsing magnetic field of the
------------
~
inductance can drive the output pin negative.
The control circuit of the IC is isolated from
the power MOSFET output section by an
isolating junction which forms a well in the
silicon surface; the control circuitry is
constructed in this well. If the MOSFET
cannot provide the current flow and the
junction of the control circuit insulation is
forward biased, this condition can prove
critical due to the activation of parasitic
components, and cause a current to flow
though the control pins of the VIPower IC
that can damage or disturb the microprocessor circuits.
The simple solution shown in figure 12,
shows a clamping diode that enables the
output power-MOSFET to conduct the energy
stored in the inductance. Figure 13 shows
the VIPower IC behaviour during a power
supply disconnection; however the negative
voltage spike on the diagnostic output can
cause an incorrect feedback signal which can
be avoided by using an RIC filter.
7.0 FUTURE DEVELOPMENT OF MOTOR
DRIVE ICs.
The future trends of the VIPower technology,
using a vertical current flow power MOSFET,
are influenced by the needs in specific
applications to drastically reduce the
dimension of the high current motor control
boards.
Surface mounting packages are being
developed to satisfy this requirement. They
will allow mounting in hybrid circuits without
the need for sophisticated die attach
technology.
These packages will have outlines that
conform to those of existing packages,
together
with
thermal
resistance
characteristics suitable for power devices.
7/10
SIiS·THOMSON - - - - - - - - - - - -
D:.."'!IJ ii:1Jrr!:Il@~~~!:1i'liI@ii!lrr!:il\
329
APPLICATION NOTE
Figure 10 - Motor drive for a window lift with two
VM201 intelligent switches
5V
Figure 11 - The VM201 during the in rush current at
turn-on of the left window and at turn-off due to a
stalled condition. INPUT=5V/div, DIAG=5V/div,
OUTPUT CURRENT =5A1div, t=100ms/div
~VCC
Figure 12 - Protection from accidental power supply
disconnection
Figure 13 - Waveforms during power supply
disconnection.
IN=5V/div,
DIAG=5V/div,
OUT =1 OV/div,
lout=2A1div
7.1 CONFIGURATIONS OF NEW LOW
VOLTAGE MOTOR DRIVE ICs.
To give some concrete example of future
ICs, typically power tool applications with a
single switch are considered.
For full bridge applications, where bidirectional rotation is required, a double high
side driver with two external low side discrete
8/10
power MOSFETs can be employed, figure
14. A full bridge cannot be integrated in one
chip using only VIPower technology because
the substrate of the IC forms a common drain
to all the integrated power MOSFETs.
However this can be resolved by using both
--------------------------~~~~;~~~:~~ -------------------------330
APPLICATION NOTE
Vee
Figure 14 - Chip of a double side driver
Duty cycle (%)
100+---------------~~~·I
oL---~----~----L---~----~~
-40
. 0
40
80
120
160
Tj(JC)
Figure 16 - Duty cycle reduction vs Tj in the circuit
of Fig. 15.
the VIPower and the BCD (Bipolar CMOS
DMOS) technologies. Figures 15 and 17
show examples of possible single switch
mode motor control configurations integrated
in VIPower technology:
Figure 15: The micro-processor sets the
maximum duty cycle and the VIPower IC
internally limits the operating junction
temperature; when the temperature reaches
the maximum value, the temperature sense
circuit operates in a feed-back loop and
Figure 15 - Limitation of the maximum CHIP
temperature using a temperature feedback.
reduces the duty cycle (figure 16) in order to
maintain the junction temperature at a safe
value; This feature allows the motor to work
in overload conditions safeguarding the
power ICs from the stress of overtemperature.
Figure 17: Speed and maximum torque
control of the motor can be achieved using
a feed-back control circuit for the current and
the motor speed, the latter employing a
frequency to voltage converter; this gives the
possibility of precise control including motor
acceleration control.
All these applications see the VIPower IC as
a peripheral device of a micro-processor with
the ability to make decisions; The VIPower
IC, however, is self protected from overcurrent, over-temperature, etc, and is able
to exercise rapid control over the process.
8.0 CONCLUSION.
Several problems are solved by the
integration of a power MOSFET with
appropriate control circuitry on one silicon
chip. It achieves:
high current capability in a compact
package
9/10
l:ii ~~~~m&~:O!~~ -----------------331
APPLICATION NOTE
---~
I
~BOOTSHIAP
OVERLOAD
DIAG.
1'1-----<..u---------
1
I
----------~~D-J
Figure 17 -Torque and/or speed motor control implementation
no power dissipation in the sensing
element using a sense-FET.
no interference of the control circuit by
stray induction in the external wiring.
the ability to drive a power device from a
logic circuit.
diagnostic control and information.
The internal protection, the ruggedness and
the wide range of working frequency make
the VIPower IC able to drive motors and
inductive loads under all working conditions
without external protection.
The CMOSmL compatibility of the input and
the output signals directly interface with a
micro-processor and allow it to be used in
many applications such as autol'notive
actuators, process control, and robotics.
2
Lossless Current SenSing with Sensfet
Enhances Motor Drive Design.
Warren Schultz. PCIM, April 1986.
3
Current Sensing Mosfet Simplify Current
Mode Control
Warren Schultz - Jade Alberkrack
Power Technics Magazine, May 1986.
4
N-Channel MosFet
Warren Schultz. PCIM, June 1987
5
1
Understanding Sensfet.
Warren Schultz
Motorola application note.
10/10
A New Monolithic Double High Side
Driver.
Michele
Zisa,
Microelectronics
PC Based Development System Cuts
DeSign of Smart Power Ie Application.
Thomas L. Hopkins, SGS-THOMSON
Microelectronics
PCIM EUROPE, November 1990.
r== SCS.11tOMSON _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - ..., / l>Jo!:lfJ@rn~rn!:vll@IIlO!:$
332
SGS-THOMSON
PCIM EUROPE, November 1989.
6
REFERENCES
Drive Techniques for High Side
DRIVERS AND IPS
333
APPLICATION NOTE
HOW THE TDE1897/8 BEHAVE IN
EXTREME OVERLOAD CONDITIONS
by U. Moriconi
The circuit designer may be interested and get some insight on how the TDE189718 behave, if
extreme overload conditions are forced on to them. Although the conditions may range outside
the limits of the datasheet guarantieed performances, erroneous connections during an installation phase may occur and momentarily create such conditions. The performed tests confirm the
extreme ruggedness of these devices and their ability to survive the accidental overload.
The TDE1897/8 is a monolithic Intelligent Power
Switch (IPS) in High Side Configuration and BCD
tecnology (see fig.1 ),dedicated to drive resistive
and inductive load such as lamps, Relays, electro-valves, etc. An internal voltage clamping diode
to +Vs creates, in inductive load, a fast demagnetization path without external components.
Suitable for industrial application, it operates in
the 18 to 35V supply range delivering output current up to 500mA . In typical application it can
drive up to 1 - 1.5H load coil (48 to 60Q typical
associated resistance).
OVERLOAD CONDITIONS
To investigate the behaviour of TDE1897/8 in extreme inductive overload conditions, that may
occur when too big a load is connected to the device output, tests were performed, in bias conditions that lead the device to function out of the
datasheet operatives and rated limits.
Figure 1 : Block Diagram
tUS
RSC.
SWITCHING
INTERFACE
tIN
RIN
lSSK
'---i>I-t---o OUTPUT
-IN
1 - - - 0 GNO
01
\N453/0392
02
OUT STATUS
1/5
335
APPLICATION NOTE
Test Conditions (referred to the circuit of fig. 2)
Vs = +24V; 10 = Internal Limited; Tamb = 25°C;
L = 1.4H (non saturating); RI = 12Q; Vi = 2V
(Vih)(#); Tj = from 0Lim-Hy to 0Lim and above (*)
(#)
The input signal asks lor a permanent "on" state.
n "Lim & Hy = thresholds of intervention and histeresis of the
internal thermal protection circuit.
Figure 2: Inductive Load Equivalent Circuit
and Demagnetization Cycle Waveforms
l'
..::.
I s
Vs
45V
10
R
lOAD
L-----......:::"I--_t
Uout I----~-t-
US-UCl
UOS
UCl
OVERLOAD OPERATION
Due to. the internal limitation (Isc), the output current (10) is .not limited by the load (VslRI = 2A; Isc
:,; 1.5A) but by the device itself. As soon as the
current reaches Isc, the I.P.S. goes out of the
minimum resistance state and increases its voltage drop so that 10 = Ics. The silicon temperature
of the D.U.T. increases rapidly up to the thermal
protection threshold value (0Lim) and such protection tries to cut-off the output DMOS. The turnoff of the output forces the demagnetization cycle,
that discharges the energy of the inductive load
(to Vs) through the device.
The higher clamped current value (Isc) will produce, during the demagnetization, more stress
conditions because of both:
- The higher energy in the magnetic load
-The higher peak power (1)
During the "on" state the power (Pdon) on the
D.U.T (see the 225msec. interval in fig.3) is
defined by the 10 (Isc) and RI values. The chip
temperature rapidly increases and reaches the
upper thermal protection threshold value (0Lim);
at that moment the protection is triggered on, inducing the attempt of switch-off, the associated
demagnetization phase (some 50msec. after the
225m sec. interval), and finally the switch-off.
The D.U.T. starts then to cool down staying in the
off-state, until the chip temperature goes down to
lower thermal threshold value (0Lim-Hy). When
lower limit (0Lim-Hy) value is underpassed, the
thermal protection circuit withdraws itself, the chip
resumes its normal functions and restarts another
cycle. In facts its input has been connected permanently to a voltage level of more than 2V,
meaning a continuos request for conduction. A
new overload cycle is so started, and a periodic
repetition of:
• load charging
• current limitation
• overtemperature and demagnetization
• cooling down in the off state.
It can be noted that, for given thermal parameters
(Zth, Thermal protection levels and hysteresis),
differences in Pdon affect only the "TON" and
"TOFF" duration and ratio of such periodic repetition.
The Minidip device (TDE1897BDP) suffers heavier stress conditions than the SI P9 option
(TDE1898ASP) because of the package differences (Minidip vs. SIP9 involves higher thermal gradients).
us
L-_ _1--L_ _~~-+t
1192rOct89?-84
Note(1)
During the demagnetization phase , the power
dissipated inside the I.P.S. Chip is: lo(t) • VCl
-Io(t) decays to zero from Isc.
-VCl is set by the I.P.S. itself to about 50V
----------------------------- ~·~~~~~~~:oo?~ -----------------------------
2/5
336
APPLICATION NOTE
SOME MEASUREMENTS AND CALCULATIONS
For a typical TDE1897BDP sample, thats is in
Minidip package, (see Fig. 3) in "thermal" periodic
repetition, the current (self-limited region) is
limited to 1.1 A and the voltage across the D.U.T.
is = 10.8V for 225msec. "on" time. The energy
dissipated on the D.U.T. in the demagnetization
cycle is = 1.28 J . (**) The repetition cycle rate is =
0.27Hz(t = 3.7sec.).
Pdon (average) = 1.1A ·10.8V· 0.225sed3.7s = 0.72W
Pdem. (average) = 1.28J . 0.27cycles/s = 0.346W
Adding the small power dissipated for operating
quiescent current and for lo(t)A2*RoN in loadcharging region, the total power p(tot)= 1.1 W is a
realistic value.
Minidip (on the test-socket) Rthj-amb is about
85 °C/W that leads the average temperature in
the hot region of the chip) to 115-120°C (the chip
isn't homogeneous in temperature. Higher temperatures are reached, during dissipation, in the
area of the output DMOS).
Figure 3: TDE1897BDP Output Voltage (CH2) and Output Current (CH1) vs. Time in Thermal Periodic
Repetition.
CH1
= 200mAIdiv
CH2 = 10Vldiv
t = 50msldiv
CHI9"
Figure 4: TDE1897BDP Output Current and Temperature in the Test Point, vs. Time.
CH1 = 200mNdiv
CH2 = 50°Cldiv
t = 50msldiv
CH2gncL
~
SGS-THOMSON
3/5
- - - - - - - - - - - - - - ....,/li!lll©OO@~~~©~OO@CI'lll©$ - - - - - - - - - - - - - -
337
APPLICATION NOTE
Note(**) The formula to use is :
W = VCL-URi'{lo-[(VcL-Vs)/R,]-log[1 +(lo-R,)/(VcL-Vs)]}
-It is also interesting to see ( Fig. 4 and B ) the
temperature versus time ( mesaured monitoring
the forward voltage drop of an internal diode
placed 1.5mm from. the center of the power
DMOS ) in a region of the chip at lower average
temperature.
On the "hot" region, the estimated temperature is
quite higher (up to + BO°C. on the peak temperature, during the demagnetization phase)
However no failure could be observed on the
cheked devices
also reducing the R, value
down to 8Q, on some Minidip samples.
For a typical TDE1898ASP sample, that is in
SIP9 package, ( see Fig. 5 ) in "thermal" periodic
repetition, the current (self limited region) is
limited to 1.15A and the voltage across the D.U.T.
is = 10.2V for 300m sec. "on" time. The energy
dissipated on the D.U.T. in the demagnetization
cycle is = 1.38J r*). The repetition cycle rate =
0.52Hz (t = 1.92sec.).
Pdon (average) = 1.15A· 10.2V . 0.3s/1.92s = 1.83W
Pdem (average) = 1.38J ·0.522 cycles/s = 0.72W
The total power = 2.BW
The Rth j·amb for SIP9 "on socket" is about 50
°CIW that leads the average temperature on the
hot region of the chip to 150°C.
Minidip
S020
SIP9
ORDERING NUMBERS:
TDE1898DP
TDE1897BDP
TDE1898ASP
TDE1898FP
Figure 5: TDE1898ASP Output Voltage (CH2) and Output Current (CHI) vs Time in Thermal Periodic
Repetition
CH1 = 200mAidiv
CH2
= 10Vidiv
~ri·~···
CH2gn
CHlgn
4/5
t = 100msidiv
,
,
II
/
300ms
\
1-1
,
-----------------------------~~~~;~~~:~~n
338
l
,
,
,
-----------------------------
APPLICATION NOTE
Figure 6: TDE1898ASP Output Current and Test Point Temperature vs. Time
CH1 = 200mNdiv
CH2 = 50"C/div
t = 100ms/div
Tmax" 165"C
/
/
Tmin" 120"C
CHIgnq.+--~
_ _ _--,
CONCLUSION
The complex protection sistem of TDE1897/8
proves effective also in extreme overloadconditions. Althougth the behaviour of such devices in
those conditions cannot be guaranteed due to the
high temperatures that accelerate the intrinsic
ageing mechanism, the test performed show that
there is a lot of margin beyond the guaranteed
limits of the device datasheet. These test also
show that it is very likely that such devices will
survive to non permanent overloads like the ones
possible in practice during the installation or
modification of an industrial control system.
----------------------------- ~~~~~~~~:oo~~ -------------------------
5/5
339
APPLICATION NOTE
SWITCH-MODE DRIVERS FOR SOLENOID DRIVING
This design guide describes the operation and applications of the L294 and L295 switch-mode solenoid drivers. Integrating control circuitry and power stage on the same chip, these devices replace complex discrete
circuits, bringing space and cost savings.
Many applications, particularly in computer peripherals, require a high power, fast solenoid driver circuit. In the past these circuits have been realised
with discrete components because the high powers
required precluded the use of monolithic technology.
SGS-THOMSON Microelectronics has overcome
this problem with a new high power bipolar technology that uses an innovative implanted isolation technique. This technology is used to fabricate two
switch mode solenoid driver chips, the L294 and
L295, which both incorporate high power output
stages and control circuitry. Both circuits are designed for efficient switmode operation and are
mounted in Multiwatt ® plastic package.
THE L294 SOLENOID DRIVER
The L294 is designed for solenoid driving applications where both very high speed and high current
are essential; needle and hammer driving in printer
mechanisms, for example. It delivers 4 A with supply voltages up to 46 V, handling effective powers
up to 180 W.
Shown in figure 1 , the L294 is controlled by a TTL level logic input and the peak load current is programmed by a reference voltage applied to the pin
labelled Vi.
Internal switchmode control circuitry regulates the
solenoid current by turning the output stage on and
off repeatedly to keep the load current between the
Figure 1 : Internal Block Diagram of the L294 Switch mode Solenoid Driver.
02
AN243/1288
1/11
341
APPLICATION NOTE
programmed peak value, Ip, and a lower limit of 0.9
Ip.
Other features of the L294 include thermal shutdown, output short circuit protection, overdriving
protection and a latched diagnostic output. This output indicates fault conditions such as a short circuit
solenoid.
CIRCUIT OPERATION
In most applications the L294 is used with a fixed
reference voltage (Vi) and the solenoid is controlled
by negative-going pulses on the ENABLE input.
When the ENABLE input is active (low level), the
output stage is enabled and the load current rises
as shown in figure 2.
The load current is sensed by an external resistor
(Rs) in the emitter of the sink stage. Through the op
amp and transconductance amplifier (OTA), the
sensed voltage charges an external RC network
(R1 C1) which determines the switching characteris~
tics of the device.
Figure 2 : Output Current Waveforms of the L294.
The Output Current in regulated by
Switching between a Peak Value, Ip, and
.
a lower Limit of 0.9 Ip.
OUTPUT
CURRENT
Vi~
__
~
-+_____
________
ENABLE
5-588811
Figure 3 : Two Level Current Control can be implemented by switching Vi .between two Values.
OUTPUT
CURRENT
LEVEL
2/11
342
-+l------'------~
5 - 5890
APPLICATION NOTE
The voltage across this RC network is compared
with the voltage Vi, which fixes the output peak current. When the current has reached the programmed peak value this comparator switches,
turning off the output source stage and closing a
switch which reduces the voltage on the non-inverting input to 0.9 Vi. The load current now recirculates
in 01. The voltage on pin 8 falls with a time constant
determined by R1 C1 or the load characteristics,
whichever is the longest. In other word. R1 C1 sets
the minimum recirculation time constant.
quired the Vss supply can be omitted. The short circuit protection, however, still functions, even without VSS.
Figure 4 : On-time Limiter Waveforms. After a Period defined by C2 the Output is disabled
regardless of the State of ENABLE, protecting against overdriving.
When the voltage across R1 C1 has fallen to the 0.9
Vi threshold the comparator switches on, turning the
output stage back on and restoring the Vi comparison threshold.
The output source stage is switched in this way,
regulating the load current, until the ENABLE input
goes high again. At this point the output stage is disabled - both source and sink - and the load current
recirculates through 01 and 02 to ensure a fast
decay. By varying the voltage Vi the peak load current can be programmed to any value in the range
0.6 A to 4 A. This feature can be exploited to implement two-level current control if the fixed reference
is replaced by a switched reference as shown in
figure 3.
PROTECTION
To protect the load and the L294 from overdriving
an on-time limiter inhibits the output stage independently of the ENABLE input if the duration of the
input pulse exceeds a period set by the external capacitor C2 (figure 4). This circuit is reset by taking
the ENABLE input high. Theon-time limiter can be
disabled by grounding pin 3.
Protection against overheating is incorporated in the
form of a thermal shutdown circuit which disables
the output stage when the junction temperature exceeds 150"C. The circuit restarts when the temperature has fallen about 20"C.
The L294 is also protected against short circuits to
ground, to supply and across the load. Triggered
when the source stage current exceed 5 A or the
sink stage current exceed 1 V/Rs, the short circuit
protection block inhibits the output stage and sets a
flip flop which is supplied by a separate supply voltage V ss. This flip flop is connected to the diagnostic output and signals that all is not well - a shorted
solenoid, for example. The diagnostic flip flop is
reset by removing the supply Vs.
A LED can be connected to the diagnostic output as
shown in figure 5. If the diagnostic function is not re-
PIN 3
VOLTAGE
USING THE L294
The basic application circuit for the L294 is shown
in figure 5 ; a suggested layout is given in figure 6.
The circuit is complete except for the source of Vi.
In most cases this will be provided by a simple resistive divider dimensioned to set the desired peak
current. With a 0.20 sense resistor as shown, the
L294 has a transconductance of 1AN for Vi above
600 mV. The device will not work with Vi less than
450 mV and operation is not guaranteed for Vi between 450 mV and 600 mV.
The on-time limiter delay - set by C2- is approximately 120000 x C2. Pin 3 must be grounded if the
on-time limiter isn't used.
Switching frequency depends partly on the timing
network R1 C1 and partly on the load characteristics.
R1 C1 determines the minimum value of t1 (see
figure 2), which is given by t1 ;:: 0.1 x R1 C1. C1 must
be in the range 2.7 - 10 nF to ensure stability of the
amplifierOTA. R1 must be at least 10 kO to give sufficient gain for OTA. The standard application circuit
of figure 5 has a switching frequency of about
10 kHz.
The recirculation diodes should be fast types and
rated at 3A (01) and 1A (02). If the full4A capability
of the L294 is not used these can be reduced.
3/11
343
APPLICATION NOTE
Figure 5 : Standard Solenoid driving Application of
the L294. Pin 7 must be connected to a
Suitable Reference Voltage to set the
Peak Current.
'5V
The peak current, IOEx, (see figure 7a) is found
from:
Vz
R2
IOEX =
5
Rs
R1 + R2
Vz is the zener voltage. The zener and R5 can be
omitted if a regulated 5 V supply is available for point
.V s
A.
The holding current, Ihold, is found from:
Vz
(R2 II R4)
1
..
Ihold =
5
R1 + (R2 II R4)
Rs
--~-~
Vj
ENABLE
The duration of the peak is determined by R3C1 and
is increased by raising R3 or C1.
"1...r
Typical component values are listed in the table
below:
5-531114
D1 : 3A Fast Diode
D2: 1A Fast Diode
trr:<;200ns
A high initial peak and low holding current can be
obtained with the circuit shown in figure 7a. This
example supplies a current peak for about 10 ms.
R1
R2
R3
R4
RS
D1
D2
C1
IOEX=4A
IHOLO=1A
IOEX = 2.5 A
IHo LO = 0.5 A
10 kQ
47 kQ
150 kQ
2.7 kQ
0.2 Q (1 W)
3A
O.S A
0.2 fIF
10 kQ
27 kQ
150 kQ
1.5 kQ
0.27 Q (O.S W)
1.S A
O.S A
0.2 fIF
Figure 6 : Suggested printed Circuit Board layout for the Application Circuit of figure 5.
4/11
344
APPLICATION NOTE
Figure 7a : Application Circuit for two Level Current Control. This Circuit generates a high Peak Current
for a Period determined by R3C1 then a lower holding Current.
5-5891/2
Figure 7b : Output Current Waveform obtained with the Circuit of fig. 7a.
5/11
345
APPLICATION NOTE
Figure 8 : Pin Functions\of the L294.
Function
N°
1
Solenoid Supply Voltage Vs (12-46 V)
2
Output, Source Stage
3
On-time Limiter Time Constant. A capacitor to ground sets delay period (120 000 x C2 seconds).
On-time limiter is disabled by grounding this pin.
4
Supply Input (5 V) for Diagnostic Flip Flop.
5
Diagnostic Output, Open Collector. Signals intervention of latched short circuit protection. Reset by
removing pin 1 supply.
6
Ground.
7
Vi Reference Input. Peak output current is proportional to Vi. Transconductance is 1 AN for Rs = 0.2 Q
and Vi ;:, 600 mV.
8
Timing. A parallel RC network from this pin to ground sets the minimum recirculation time constant.
The capacitor must be 2.7-10 nF to ensure stability.
The resistor must be greater than 10 kQ.
9
ENABLE. TTL-compatible logic input that controls the solenoid current. The solenoid is driven when this
input is at a low level. The on-time limiter overrides enable.
10
Connection for Load Current Sense Resistor.
11
Output, Sink Stage
THE L295 DUAL SWITCHMODE DRIVER
The L295 is a dual switch mode solenoid driver
which .handles up to 2.5 A per channel at voltages
up to 46 V - a total effective power handling of 220
W. Compared to the L294 it offers a more economical solation when 2.5 A is sufficient because there
are two drivers per chip. Like the L294 it features
switch mode regulation of the output current and
thermal shutdown. Additionally it has a separate
logic supply input so that the logic can be run at a
lower voltage, reducing dissipation.
Intended for inductive load driving, the L295 is particularly suitable for solenoids and stepper motors.
One L295 drives two solenoids and two L295s can
drive the four phases at a unipolar stepper motor or
the two phases of a bipolar stepper motor in bridge
configuration.
Each channel of the L295 is controlled by a TTLlevel digital input and the peak load current is programmed, independently for ea9h channel, by a
voltage reference input. A chip enable input is also
provided to disable both channels together.
INSIDE THE L295
Internally the L295 (figure 9) bears little resemblance to the L294. Looking at channel one, when
the VIN1 input goes high the output transistors 01
and 02 are switched on (the enable input EN is assumed to be active, i.e. low). The current in the load
then rises exporientially, as shown in figure 10, until
6/11
346
the voltage across the external sense resistor RS1
reaches the current program reference voltage
Vref1.
The comparator COMP1 switches and sets the flip
flop FF1 which turns off the source transistor 01.
The load current now recirculates through 02-02RS1 and decays.
What happens next is determined by the oscillator
components Rand C on pin 9. If these components
are present the flip flop is reset by the next clock
pulse before the current decays very far. The output
stage is therefore turned on again and the load current rises.
When it reaches the peak value COMP1 switches
again, setting the flip flop and disabling the output
stage. This process is repeated, regulating the load
current until Vin1 goes low. The output stage is then
disabled and the current falls off rapidly, recirculating through 01 and 02 (figure 10).
If the oscillator components are omitted and pin 9
grounded the current simply decays slowly until Vin1
goes low. The output stage is then disabled and the
load current recirculates through 01 and 02. This
case is illustrated by the waveforms of figure 11.
Note that in this case the peak current. level is controlled.
Unlike the L294, the switching frequency of the current regulation loop is determined by the oscillator
components Rand C (the L294 is also affected by
the load). Typically, the switching frequency will be
APPLICATION NOTE
10-30 kHz. Another difference between the two devices is that the L294 gives a constant ripple, the
L295 does not.
TWO LEVEL CONTROL
Since the peak load current is programmed by the
reference voltage (for each channel), two level cur-
rent control can be obtained by switching between
two reference Voltages. A high V,ef is selected initially to give a high initial current peak. Then, after
a suitable interval, V,ef is reduced to give the lower
holding current (figure 12). Two level current control
is very useful for solenoids which require a high initial current peak for fast actuation.
Figure 9 : Internal Block Diagram of the L295 Dual Switch mode Driver.
Gi
SGS·1HOMSON
~I ~D©UI@IlI!.rn©1rWJ@IllD©$
7/11
347
APPLICATION NOTE
Figure 10 : Waveforms illustrating Normal Operation of the L295.
I
'0
11 1 ' 2
:
I
I
r
1 I
r
I
I I
I I
I I
I
'31
:;
'415
:
I
Figure 11 : When the Oscillator Components are
omitted and Pin 9 grounded the L295
delivers a simple Current Peak to the
Load.
10
I
Iltnl
;
Vi
I
i
.,
.~_N_I~~~
t- -
Vref
____-,__________~____--..
I
I
--I~'---.------~----------~----~I
I
.,
:J --11------1
t
01
I
I
•
.,
5 - S8 62
, I
'i-SSG1
Figure 12 : Two Level Current Control is obtained
by switching V,ef between two Values.
I
I
I'
I:
II
I I
I
:I
I
I
: ::
: I
I
I I
I I
I
I
I
nn
8/11
348
"
APPLICATION NOTE
L295 APPLICATION HINTS
If the V,ef inputs are left open circuit the L295 assumes an internal default value of 2.5 V giving a
peak current of 2.5/Rs amperes.
provides switch mode regulation of the load current
with a chopper rate of about 25 kHz. The enable inputs (EN, connected together) enable/disable the
whole circuit and the channel inputs Vinl ... Vin4 are
driven by a suitable translator circuit. Phases 1 and
2 must not be energised together because they
share the same sense resistor. The same applies to
channels 3 and 4. However, ' two phase on' drive is
stili possible for bifilar motors where phases one and
two represent one winding and 3 & 4 the other, and
also for variable reluctance motors with phase 1 adjacent to phase 3 etc.
The L295 can also be used to drive unipolar stepper motors. For a four phase motor two devices are
used, connected as shown in figure 17. This circuit
Two L295s could also be used to drive a bipolar
stepper motor in systems where a translator already
exists.
The basic application circuit of the L295 is shown in
figure 14. A suitable layout is given in figure 15.
Suitable values for the oscillator components, Rand
C, can be found from the nomogram, figure 16. The
value for the reference voltages depends on the
desired peak current and is equal to IpRs ; it must be
in the range 0.2 V to 2 V.
Figure 13 : Pin Functions of the L295.
Function
N°
1
Solenoid Supply Voltage, Vs (12-46 V).
2
Channel one Output, Source Stage.
3
Channel one Output, Sink Stage.
Sense Resistor Connection, Channel one.
4
RSI.
5
Vref1 . A voltage on this pin sets peak current of channel one. If this pin is left open or connected to Vss
a default Vref of 2.5 V is assumed. An externally applied Vref must be in the range 0.2 to 2 V.
6
Vin1. Logic Input for Channel one. Driver is active when Vin1 is high and EN low.
7
EN. Chip Enable (active low). When high both channels are disabled.
8
Ground.
9
Oscillator Timing Network. This pin is grounded to produce a single peak.
10
Vss. Logic supply voltage, internally regulated. (4.75-10 V).
11
Vin2. Logic Input for Channel two. Driver is active when Vin2 is high and EN low.
12
Vref2 . Voltage input, controls peak current of channel two. If left open or connected Vs an internal 2.5 V
reference is assumed.
An externally applied V ref must be in the range 0.2 to 2 V.
13
Rs 2. Sense Resistor Connection, Channel two.
14
Channel two Output, Sink Stage.
15
Channel two Output, Source Stage.
9/11
349
APPLICATION NOTE
Figure 14: Typical pplication Circuit of the L295. R1 L 1 and R2 L2 are solenoids.
+Vss
+Vs
01
5-58601,
01 : 3A Fast Diode
02: 1A Fast Diode
trr 5 200ns
Figure 15: Suggested printed Circuit Board layout for the Circuit of figure 14.
C5_0171
10/11
350
APPLICATION NOTE
Figure 16: Nomogram for the Selection of Values for the Oscillator components. Re.
Figure 17:
Two L295s, connected as shown, can be used to drive a four Phase Unipolar Stepper Motor.
10
Vi 3
Vi'o-----l
11
V; 20-----l11
EN U""""t----,
Vi 4
L295
( 2)
L295
(, )
14
01.03.05,07 :lAFAST DIODES
02 ,04,D6,Og: 2AFAST DIODES
5-5&92
11/11
351
APPLICATION NOTE
FULLY PROTECTED HIGH VOLTAGE
INTERFACE FOR ELECTRONIC IGNITION
By S. PALARA ; M. PAPARO ; R. PELLICANO
INTRODUCTION
It is well known that an electronic car ignition system must be able to generate and supply the high
energy discharge to the spark plugs, firing the petrol/air mixture at a precise point in each piston
cycle. This job is performed by means of an high energy coil, its driver stage and the most suitable controller; an example is shown in fig. 1.
In the most recent car ignition systems the coil current loading signal is controlled by a microproces-
sor that can also optimize the ignition timing. This
ensures the correct spark at every speed for all environmental conditions.
The engine efficiency is so optimized ensuring the
minimum toxic exhaust gas emission.
The high voltage necessary to generate the spark
is obtained by charging the primary winding of the
ignition coil with a controlled energy, i.e. a controlled current.
Figure 1 : Car Ignition System.
SUPPLY
RDC ( 0. 1Q I
1
1
-
[BATTERY [ ______ +
1. UBm•
IHTERfACE
AIIIl
COHTROl
HI&H UIIlTA&E
POWER ACTUATOR
AItJ
SUPPLY
AN292/0189
1/6
353
APPLICATION NOTE
At the firing point this current is suddenly interrupted
transferring the stored energy to the secondary
winding and produces output voltage in excess of
20KV and therefore the spark.
The fig. 1 power actuator must also limitthe current
to a max of 10A and the voltage on the primary to a
maximum of about 400V.
The voltage clamp avoids any damage to the power
actuator: if the spark plug, for example, is disconnected, the energy stored in the coil is transferred
back to the power actuator.
The device described in this paper realizes these
power actuator functions with a very innovative integrated single chip solution.
THE VIPOWER M1 TECHNOLOGY
The VIPower M1 structure shown in fig. 2 combines
a vertical current flow NPN power transistor and a
Figure 2 : VIPower Technology Vertical Structure.
N - EPI
Nt SUBSTRATE
2/6
354
low voltage junction isolated I.C. on the same silicon substrate.
.
This is realized inside a diffused p-type well that
takes the place of a reverse-biased p-substrate of
conventionallCs and must be connected to the most
negative supply.
As in a standard discrete BJT, the first epitaxial layer
thickness and resistivity set the Vceo and the
ruggedness of the high voltage device, the second
epi growth fixes the features of the low voltage components (up to 100V VCBO).
The maximum voltage the power device can withstand is neverthless also dependent on the maximum field strentgh at the silicon surface and on the
n+/p--well parasitic diode breakdown Voltage.
APPLICATION NOTE
The high voltage termination ofthe integrated circuit
is achieved by a p-diffused resistor in spiral from
.connected between the substrate (power darlington
collector) and ground.
In the block diagram of fig. 3 the power Darlington
with its driver and input stage, the current limit, voltage clamp circuitry and the overvoltage protection
are shown.
DEVICE CHARACTERISTICS
The device realizes the ignition, power actuator subsystem of fig. 1.
Figure 3 : Device Block Diagram .
.--------p-------~---()
VBAH
HVC
DRIVER
RB
Rs
GND
S(-0261/1
A TTUCMOS compatible input signal coming from a
logic interface, like a microprocessor, determines the
turn on of the power darlington integrated in the chip.
The darlington collector current charges the coil Iinearly as long as a set level is reached, typically
6A ± 3%, sensed by an internal aluminium emitter
JII.••1<.,
resistance.
The voltage drop on this resistor is compared with
an internally generated threshold (- 200mV) and
limits the current, thus controlling the Darlington
base current until the input signal causes the output
Darlington to switch off.
SGS·ntDMSDN
3/6
IiliOC~iIl@XmDi:S
355
APPLICATION NOTE
Photo 1 shows the coil current behaviour together with the corresponding input signal.
Photo 1 : Collector Current and Corresponding Input Signal.
Input signal (5V/div)
Coil. current (2Ndiv)
The current loop is made by compensated operational amplifier ensuring enough precision of the
set value and hence of the stored energy without requiring external components.
The regulation stability is infact mandatory in the car
ignition system to avoid spurious sparks on the secondary coil winding.
During the current limiting phase, the Darlington collector voltage reaches the battery voltage minus the
voltage drop on the coil (due to the primary resistance). It causes high powerdissipation in the power
actuator which the microprocessor minimizes by delaying the output Darlington switch on.
The overvoltage on the power Darlington collector
during the transition from the coil charging to the current limiting phase is low enough to avoid undesiderable sparks.
At the input signal switch-off the power Darlington
is immediately turned off and the energy stored iri
the coil is transferred from the primary to the secondary winding causing the spark.
The collector voltage of the power Darlington then
rises very rapidly and is detected by the spiral resistor used as the high voltage termination for the chip.
Photo 2 : Collector Voltage During Coil Charging.
Coil. volt. (5V/div)
Coil. current (2Ndiv)
4/6
356
APPLICATION NOTE
This resistor, used as a divider, is connected to a
low voltage zener circuit that turns on the power Darlington, holding the collector voltage at a value
determined in the chip (- 400V± 10%) which is less
than the Darlington VCEO.
Photo 3 shows the collector voltage during the
clamp in absence of the spark plug i.e. the worst
case for stress on the integrated circuit.
Photo 3 : Voltage Clamp.
Input signal (5V/div)
Call. volt. (100V/div)
Fig. 4 shows the application circuit for this device.
Figure 4 : Application Circuit.
I
RsJ
300Il'
.) Ro
J
SOn.
4
~p
5
2
ijilit
I ~H.v.
VB020 ]
board
1
S(-OllO
Two separate pins for the supply: pin 4 and pin 2,
are connected to the battery by means of two different resistors.
Pin 2 represents the supply of the driver with a cur. rent of up to 200mA.
Pin 4 is the supply for the rest of the circuit
(k1 - 3mA).
A picture of the die is shown in photograph 4.
The device is assembled in a new fully insulated
five-lead plastic power package, ISOWATT 5 and
shown in figure 5.
5/6
357
APPLICATION NOTE
Photo 4 : The Die.
Figure 5.
ISOWATT5
CONCLUSION
The ignition controller described in this paper completely substitutes the existing hybrid solution which
requires additional components and manufacturing
processes (i.e. insulating substrates, ink layers, active and special passive devices, laser trimming, en-
6/6
358
capsulation etc .. ). This single chip solution leads to
an intrinsic increased compactness. The subsequent higher reliability is further enhanced by the
known advantages of integration.
Additionally to that a cost reduction benefit through
this approach is also achievable.
APPLICATION NOTE
TRANSISTORIZED POWER SWITCHES WITH
IMPROVED EFFICENCY
By M. Bildgen ., K. Rischmuller'
ABSTRACT.
An important objective for power electronic
design is the reduction of power losses. This
paper analyses the output characteristics of
bipolar and MOS power stages and indicates
limits for further on state loss reduction. A fast
high voltage driver/switch combination with very
low on state and switching losses is described.
The switch is designed with cellular bipolar junction transistors driven by a smart power switch
mode regulator. The driver handles duty cycles
from 0 ... 100 % and requires only one unregulated
auxiliary supply. The static and dynamic behaviour of the switch and its new driver stage are
shown and discussed. The switch exhibits low
losses and is able to operate at inaudible switching frequencies on the rectified mains.
Keywords. Mains supplied operation, on state
loss reduction, simplified base drive, smart
power, high switching frequencies, Darlington,
POWER MOSFET, cellular bipolar transistor.
INTRODUCTION
Loss reduction is a major objective in all power
electronic equipment. The switching losses of all
kinds of switching power semiconductors have
been significantly reduced by means of structures
, with increased interdigitation, cellular structures
and improved carrier lifetime control. Today performances are often close to those that physical
laws allow. The switching losses have been
reduced to such an extent, that lowering on state
losses has become the key for further loss reduction. Further loss reduction can only be achieved
through the reduction of on state losses which is
the major topic discussed in this paper.
HOW TO REDUCE LOSSES?
Lowering on-state losses is of particular importance in inverter circuits operating with switching
frequencies below 20kHz and in resonant converters where switching losses are already negligible.
For evaluation of on state losses, power semiconductor devices can be classified as:
AN813/0990
• SGS-THOMSON, Central Application Laboratory, Roussel, France
a) devices with dominating resistive output
behaviour
b) devices with dominating p-n junction behaviour of output characteristics (Fig.1).
The Power MOSFET (MOS), the Bipolar Modulated FET (BMFET)5 and the Bipolar Junction
Transistor (BJT) exhibit a resistive output behaviour (Fig.1 a). Their on state voltage drop can
be reduced through increasing die size, a question of technology and cost.
The Bipolar Darlington (DL T), the MOS Gated
Bipolar Transistor (MOSBIP), the Insulated Gate
Bipolar Transistor (lGBT) and Thyristors (GTO,
FCTh.,.) exhibit a dominating p-n junction output
behaviour (Fig 1b), The on state voltage drop of
these devices is the sum of the threshold voltage
of the p-n junction and the voltage drop across a
resistance. The threshold voltage is determined
by physical laws, only the resistive part of the on
state voltage depends on the die size. The influence of die size on on-state losses is relatively
limited and is not a feature that can be used to
give significant loss reduction.
MOSFET AND BIPOLAR TRANSISTOR
The MOSFET, the BMFET and the BJT can have
an on state voltage drop of less than 600mV and
fast switching: A high power MOSFET e,g. a
TSD4M450 (ROS(on) = 0,112, Vos =500V, 10 MAX
= 45A) handles a current of 5 Amps with an on
state voltage drop of only 500mV. The die area of
such a device is about 170 mm 2 . The MOSFET
requires only short gate current pulses for its
drive.
A very fast cellular BJT e. g. a BUF410
(450V/1000V, 15A) switches 5 Amps with about
500mV on state voltage drop. The die area of this
device is about 36mm 2 and has therefore a very
low silicon cost. The BJT requires base current:
- in excess of a fifth of the collector current
- and negative bias for fast turn oft switching,
immunity against reverse current and dv/dt.
Nevertheless, the power gain is very high, e.g.
when switching 400V x 5A = 2kW, a drive power
1/6
359
APPLICATION NOTE
Fig.1: Symbols, equivalent circuits and output characteristics of power semiconductor devices;
a) devices with resistive output behaviOur; b) devices with p-n junction behaviour
a)
IB~
~9
VGS
BJT
i
OLT
VGS
I~
VGS
-
~
i
iVaN
BM-FET
MOSFET
-g
b)
SC-1320
-~jl
~~j
Vth"
I
MaS-SIP
/'
Vt~
TvGS
1\SIG~h
I
i
~
VGS or
IB
~
....... 1 I+-
IGBT
Vth
GTO
VON
VON
= Vth
+
r . I
TABLE 1: On-state and driver losses of different device/driver configurations
On-losses VCE + Ic
BJT + (1)
0.5V x 20A = 10W
4A x 12V = 48W
58 W
DLT + (1)
1.5V x 20A = 30W
0.6A x 12V = 7W
37W
BJT + (2)
0.5V x 20A = 10W
10W
20 W
DLT + (2)
1.4V x 20A = 28W
4W
32W
of only 1A x 1V =1 W (base current multiplied by
base emitter .voltage) is needed.
The gap in die size between the POWER MOSFET and the cellular BJT, increasing with voltage
and current, is so important, that it is worth thinking about low loss base drive for bipolar transistors.1, 2, 3
TRANSISTORS AND DARLINGTONS
The Darlington is the most popular switch in
mains supplied, medium power applications. The
major reason for this choice is its .moderate base
current consumption.
A typical fast switching 20A,450V Darlington re2/6
---------------------------L"
360
Driver Consuptios Vs + 18 Total Conductive Losses
Device + Driver
quires a 0.6A base current. With a conventional
driver circuit operating from an 8V to 12V auxilary
supply, the worst case driver consumption would
be 12V x 0.6A = 7W (Table 1).
The collector-emitter on state losses of the Darlington can be typically calculated to be about
30W. The total conduction losses amount to
about 37W.
The bipolar junction transistor exhibits collector
emitter on state losses of only 10W but requires a
positive base current of 4A.
The total driver loss in the transistors is 4A x 1V =
4W (base current multiplied by base emitter voltage). With a conventional driver circuit operating
~~~~~~:~~
---------------------------
APPLICATION NOTE
Fig. 2: Example of a switch-mode driver circuit for fast switching applications
SC-1322
*--
]
470
15V n
o -1
47il
O~
LOfF
c-----'
Fig.3: Self generation of negative bias from a positive supply voltage
Rl
3300
]
R3
1000
2 x
1N4001
n
ON --I L
OFF
0---'-1 fAr
SC-1323
3/6
---------------------------- ~~~~~~gu~:~~~ ---------------------------361
APPLICATION NOTE
from an 8V to 12V auxilary supply, the worst case
driver consumption would be 48W - total conduction loss would be 58W. The poor efficiency of
conventional driver stages is the reason that the
transistor power switch exhibits higher conduction
losses than the Darlington. Using driver stages
with high efficiency allows BJT power stages to
be used instead of Darlingtons which results in
significant loss reduction.
DESCRIPTION OF THE SWITCH MODE BASE
DRIVER
An L4974 smart.power IC with a MOSFET output
stage operates as a buck regulator in current
mode. The IC is contained in a DIL package but
is able to supply a 4 Amp base current. (Fig.2).
The efficiency is so high that thermal conduction
to the PCB provides sufficient cooling. During the
off state of the power transistor, TP, a MOSFET
T1 applies a short circuit to the output of the buck
regulator. The IC operates with low duty cycle
and maintains constant current in the choke L.
For turn on of the power transistor TP, the MOSFET, T1, is turned off and the constant choke current flows into the power transistor's base. The
rate of rise of base current is limited only by the
MOSFET turn off speed. In order to obtain very .
fast switching, a high density MOSFET
(STVHD90) which has a very reduced input and
output capacitance, has been used.
If the power transistor base current is 4 Amps
and the auxilary supply voltage 20V, the driver
input current will be about 0.47 Amps. Increasing
the auxilary supply voltage further reduces the
input current.
NEGATIVE BIAS FOR FAST TURN OFF
SWITCHING
The first version of the circuit generates negative
bias with a Zener diode between auxilary supply
and driver stage (Fig.2). The current return path
to the auxiliary supply is through this diode. Losses in the Zener diode are small, due to the fact
that input current of the driver circuit is small. For
turn off, T1 and T2 are turned on, T2 applies the
negative bias to the power transistor base, thus
obtaining fast switching and immunity against
reverse current and dv/dt. 4
The second version of the circuit generates its
negative bias directly from a positive auxilary
supply:
a capacitor C1 (Fig.3) is permanently charged
via a resistor R1 and a diode D1. At turn off
switching, T2 is turned on·for a time t1, slightly longer than the power transistor's storage
Fig. 4: Test circuits for switching losses
5C-1321
+ vaux
OF
D.U.T.......-I,.-rrl'TT1'-c:::r-..
C
DRIVER
STAGE
BUF40S
BUF420
4/6
------------LV ~~~;m~r::9lf -------------
362
APPLICATION NOTE
Fig. 5: Turn-on and off switching waveforms with transistors and Darlingtons
SC-13e4
=
"
7',
IT\
SC-1326
- "'- -
r\
"
1
II
1-0.....
i\
,.'\
/
....Ie
J
v.
7
r<:'.CE
Darlington:
BUF405 + 8UF420/BYBO-600
Turn-on: VCE= 50V/div
Ie = 10A/div
l = 1DOns/div
dic/dt = 450A/J,ts
f'.. -.::::. Ie
\
........ /vCE
Bipolar Junction Transistor:
BUF420/BYT30-600
Turn-on: VCE= 50V/div
Ie = 10A/div
l = 1OOns/ div
dic/dt = 450A/p.s
SC-1325
~
I\,,- 18
'\.
-Ie
..J
SC-13e7
I,.J
I
\
\ V 18
V
~
II
i-"
Ie
VeE r-..
'-- 1/
VeE
~". D
Darlington:
8UF405 + BUF420/8YT30-600
Turn-off: VeE = 50V/div
I C 5A/div I B 2A/div
t = 500ns/div
=
=
Bipolar Junction TrlJn5i5tor:
BUF420/BYT30-600
Turn-off: VCE = 50V/div
I C = 5A/div I B= 2A/div
t = 500ns/div
- - - - - - - - - - l . f i ~~tm~r::a!?~
---------5/6
363
APPLICATION NOTE
TABLE2: Switching energy losses of transistor and Darlington with BUF420 and BYT30-600
TURN-ON ENERGY
TURN-OFF ENERGY
TOTAL SWITCHING
ENERGY
CELL. - BJT
1 mJ
0.5 mJ
1.5 mJ
CELL. - DLT
0.9 mJ
0.8 mJ
1.7 mJ
DEVICE UNDER TEST
(DUT)
time, ts. T2 connects the positive electrode of
C1 to ground, thus a negative voltage appears at the base of TP. T2 turns off after the
turn off switching of TP and C1 continues
charging. The state of charge of C1 is independant of duty cycle - sufficient negative
bias is available with any duty cycle.
same Darlington driven from the switch mode
driver exhibits conduction losses of 32W. The
conduction losses of the transistor with switch
mode driver are 0.5A x 20V + 0,5V x 20A =20W.
This is about 60% of the switch mode driven Darlington.
TEST RESULTS
CONCLUSION
Fast transistors and Darlingtons made using cellular technology (e.g.BUF420) have been tested
in a buck converter with 280V supply voltage and
20A output cu rrent (Fig.4) Both types of switches
have been driven from the same switch mode
driver circuit. The turn on and turn off waveforms
are shown in Fig. 5a and 5b. The devices were
operated at Tj =85°C.
As expected, the turn on speed dic/dt of the Darlington is twice as fast as that of the transistor
switch. The reverse recovery current of the free
wheel diode increases with di/dt. This makes the
difference in turn-on loss between the fast switching transistor stage and the faster switching Darlington stage insignificant (Table 2). The storage
time of a transistor stage is less than that of a
Darlington stage. The test results confirm this well
known fact.
With a given driver stage, the negative base current of a Darlington is reduced, due to the voltage
drop of the speed up diodes. (Fig. 4) This explains the observed increased turn off losses with
the Darlington.
Low loss driver circuits suffered from duty cycle
limitations, or from excessive circuit complexity.
New smart power devices reduce this complexity
to an acceptable level, allowing the introduction
of switch mode driver techniques in to transistorized power electronic equipment. The new
configuration can be used to simplify and improve
existing converter/inverter circuits (fewer auxiliary
supplies, smaller heatsinks, higher efficiency).
CONDUCTION LOSSES
The conduction losses, including driver losses
have been calculated and confirmed by measurement. With a duty cycle of 100% the total conduction losses of a 20A Darlington with conventional
driver are O.6A x 12V + 1.5V x 20A = 37W. The
6/6
The use of switch mode driver stages is not
limited to BJTs, but offers improved efficiency in
circuits with Darlingtons, BMFETs and GTOs.
REFERENCES
1) R.B.Prest, J.D.Van Wyk : Base drive for highcurrent low loss bipolar power transistors,
PESC'86 Record.
2) C:K.Patni : An efficient "Switch mode" base
drive for bipolar transistors, Internal note, SGSTHOMSON Microelectronics.
3) L.Perier,J.M.Charreton :25kHz Leistungsschalter mit 1000V Sperrspannung in dreiTechnologien,Elektronik Informationen H.9,1988
4) K.Rischmller: How to improve transistorized
bridge converters, Proceedings of PCI'81
5) S.Musumeci, J.Eadie, p.wilson, A.Galluzzo:
Bipolar mode JFET the BMFET, Technical Note
179, SGS-THOMSON Microelectronics.
---------------------------- ~~~~~~~~:~~ ---------------------------364
APPLICATION NOTE
ELECTRONIC IGNITION
WITH VB020 AND L497
by M. Melito
INTRODUCTION
OPERATING PRINCIPLE
The VB020 is a monolithic high voltage
integrated circuit which combines a vertical
power darlington with built-in protection
circuits for coil current limiting and collector
voltage clamping, The device interfaces
directly with a microprocessor which controls
the dwell angle.
This application note shows how it is possible
to use the VB020 in an electronic ignition
system not employing a microprocessor.
The IC used, the L497, is a more conventional
electronic ignition controller for breakerless
ignition systems using a Hall effect sensor.
The schematic of fig.1 shows how the two ICs
are connected to control both the coil current,
providing the required stored energy and the
dwell angle, for low power dissipation.
The L497 was designed to drive an external
Darlington and in a standard application circuit
the current control is performed monitoring the
coil current through a sensing resistor on the
emitter of the Darlington. When the voltage
drop across the sensing resistor reaches the
internal comparator threshold value the dwell
angle control circuit is enabled. Meanwhile the
coil current is kept constant forcing the
AN482J0492
1/4
365
APPLICATION NOTE
8200~;~----
lLl
0-
5
12
6 7
300
47
~-.-----o!-----------"-----;
3
15
2
14
L497
560
'" ~ ,;,,:t-~ i i'r-L
5
O.l~F
3
VB020
01
2-.
2-K n
\ :C .[1"'1_
4
~II~ "
---t-----~
lN4007
1.5K
100
------
Fig. 1 - Schematic of electronic ignition with VB020 and L497.
v~
lC011
=
2 V/div
r
lcoll = 1 A/div
t = 10 _/div
V13
=. 100 _/dlv
V, ,.------ '---
r--- f-'--,
V14 = 1 V/div
Icon = 1 IVdtv
t
Fig. 2 - V 13 ' V14 and
Icoil
= Z _/div
waveforms.
Darlington into the active region until the highlow transition of the input signal causes the
spark to occur. The collector voltage is
clamped to a value that is externally fixed by
a resistive network. The internal dwell angle
control circuit calculates the conduction time
for the output Darlington in relation to the
speed of rotation, to the supply voltage and
to the characteristics of the coil, thus avoiding
excessive power dissipation in the Darlington
itself.
'--
Fig. 3 - Duty-cycle = 30%; frequency = 20 Hz.
By linking together the L497 and the VB020 it
is possible to avoid both the coil current
sensing and the collector voltage clamping
networks because the VB020 has internal
built-in protection circuits which perform these
functions. The dwell angle control is performed
by supplying the L497 with the feedback signal
shown in fig.2. The diode, 01, keeps the
voltage at pin 13 of the L497 under the internal
comparator threshold voltage until the VB020
begins to regulate the coil current. At this point
214
~------------------------~~~~~~~::~
366
-------------------------
APPLICATION NOTE
leoll (
v, =
Icon
r
2 V/dtv
Icoll = 1 Aldtv
t
=
V5 = 2 V/dtv
ICCll
t
10 -tdtv
V,
=
= 1 A/dtv
2 -tdtv
v,
I
'--
Fig. 4 - Duty-cycle = 70%; frequency = 20 Hz.
V5
leo!!
Fig. 5 . Duty-cycle
= 70%; frequency = 100 Hz.
= 2 V/dtv
Iron
=
1
AldIV;1
"'-""1
v,
Fig. 6 - Duty-cycle = 70%; frequency = 140 Hz.
Fig. 7 - Turn-off in normal operating mode.
Xco11
Vee = 50 V/dtv
Icon = 1 Aldtv
t = 50 us/dty
Fig. 8 - Turn-off with open gap.
D1 is turned-off and the voltage on pin 13 can
reach the threshold voltage of the internal
comparator enabling the dwell control circuit.
Figures 3 to 8 show the system performance
(V in , Icoil ) under various conditions and fig. 9
shows the conduction angle versus r.p.m. for
a four cylinder engine.
--------------lifj ~~~~m~r::O!~~
-------------3/4
367
APPLICATION NOTE
t_c_~/T~(~%~I__________________________-,
80'",-
70'" .......)><-(-4)(?---¥-)(- - - I/"f-c
i ____
~-III_-_8I1___,_=__.m
/~./+
/'
................/....~ .... ,.,c.:: ...
60'"
T
17/
I
,-//
...... y;j7'
,-/
/./
/'
40'" ................/ ..... ..... / . / . ........................
/
)/f//r*'
~------
.
~
~.F'
... ~~~"'""4
-
Vbat-20V
. . . . . . - . . . ::::vV
30'" ···········¢77~ ········································+Viia~iiV
20,"~==·
........................................... ···························*·yjjiii;ij"V"
10'"
0"L-~
o
__~__~__~__~~~~~~~
2
3
r.p.m.
4
X
«;
1000
6
7
8
Fig. 9 - Conduction angle versus r.p.m.
CONCLUSION
REFERENCES
The VB020 can be used in electronic ignition
systems without using a microprocessor.
The overall cost of the system can be
competitive with th.e solution using a
Darlington because the current limiting and
voltage clamping function performed by the
VB020 are trimmed on silicon avoiding the
need for additional adjustment.
[1] F. Pellegrini, "L482 Development Report",
SGS-THOMSON internal report, August
1982.
[2] M. Paparo, "L497 Development Report",
SGS-THOMSON internal report, July
1985.
[3] "Automotive Products" Data-book,
SGS-THOMSON microelectronics
4/4
-------------~~~~~~&~:~~
368
-----------------
APPLICATION NOTE
INTELLIGENT AUTOPROTECTED DRIVERS
by 10M. PETER and LRATES
INTRODUCTION
FUNDAMENTALS
In industrial applications, where digital control signals are provided by automation equipment, suitable Drivers are required to control various loads
such as Relays, Lamps, Electrovalves, etc.
The control signal is applied to a comparator, the
output of which drives a current source. This current
source in tum drives the power transistor T1. A transistor T2 driven by the voltage drop across shunt
Rse is configured to provide feed-back to power
transistor T1. As soon as the voltage drop across
this shunt exceeds O. 7V, T1 T2 configuration will act
as a current limiting-unit so that llimit = O.8/Rsc. This
is how the device is protected against short-circuits.
What are the essential main characteristics of these
Drivers?
• Primarily, they must be autoprotected, that is,
they must be self-resistant to industry-originated
disturbances, short-circuits, over-currents, accidental load and ground disconnection, and so
on.
" Then, in case of fault occurrence, they must be
capable of providing interactive dialogue with the
central processor unit.
• And finally, they must meet the requirements of
the standards currently in force and those of the
forthcoming projects, imposing that one terminal
of the load should be directly connected to
ground (see figure 1).
The objective of this note is to discuss and illustrate
how a family of autoprotected control has been developed from basic concepts and also to outline the
likely future trends.
AN268/0188
Another internal unit monitors the junction temperature which varies as a function of dissipated power
(Le. Vee x lee) and cooling conditions. As soon as
this temperature exceeds + 175'C (upper threshold), the protection until is activated and will sink
the generator current Is thereby turning the device
off. In the off condition, the device will cool down,
and when the junction temperature falls below +
140'C (lower threshold), the thermal protection unit
is deactivated and the device is restored to its normal operating mode. However, if the overload conditions persist, the system will operate in low
frequency relaxation mode with a frequency ranging from 1Hz to a few Hz according to the nature of
the overload. Whatever the operating conditions:
" The current is limited at a programmable level.
" The junction temperature limit is never exceeded.
1/9
369
APPLICATION NOTE
Figure 1 : There are two possible configurations of load/controller combination. Some standards and
forthcoming projects will require one end of the load to be directly connected to ground.
+
Figure 2 : Basic Functional Diagram of TDE 1647.
Thermal
Protection
2/9
370
APPLICATION NOTE
These features make the TOE 1647 which is the
basic circuit of the family, a switch well-suited to applications implementing drives for lamps, inductive
loads, blinkers and relays, etc.
It is worth mentioning that the current limit feature
when used to limit the starting current, will in the
case of incandescent bulbs, result in a considerable
extension of their life duration.
INTERACTIVITY - A SECOND FAMILY OF
CIRCUITS
In many applications, the control system must re-
ceive the acknowledgement of the execution of an
issued command, or receive information reflecting
possible failures and disturbances. The TDE1798
has been designed to meetthese requirements (see
figure '3).
This autoprotected driver contains memory logic circuitry required to latch the device status and returl!
the stored information to the processor.
This device is protected against thermal overloads
exactly in exactly the same way as TOE1647 and in
addition, if Reset input is held low, the driver output
remains blocked after a thermal overload and this
condition is indicated by a signal sent through the
Alarm output pin. The Reset input is used to return
the circuit to its normal mode of operation. In fact, if
this input is maintained high, the device will operate
in exactly the same way as TOE1647 that is, in case
of continuous overloads, it will function in a low-frequency relaxation mode.
Figure 3 : TOE 1798 Autoprotected Control.
Alarm output
(Source)
Inverting input
2
Non-inverting input 3
Alarm outpul
(Sink)
3/9
371
APPLICATION NOTE
SHORT-CIRCUIT PROTECTION.
POWER SUPPLY VOLTAGE LIMITS.
a)- Do not connect any additional device across
the
load.
The
output
transistor
of
TDE1767/TDE1798 has been particularly designed to, operate. in avalanche mode and to
clamp at voltage VZA. This outstanding feature
eliminates the need of additional components
in the case of inductive loads and automatically
provides a rapid fall of load current.
All of the devices of the entire family operate in a
wide range of supply voltages: from + 6V to maximum voltage (between + 3V and + 6V, the protection logic is operational but the temperature
detection circuit becomes inactive).
As far as the users are concerned, this is an interesting feature. However, care must be taken
not to exceed the operating limit of this transistor; that is, energy dissipated in the transistor
~ Ll2) should be less than 100mJ.
This device is protected against short-circuits by a
current-limit feature operating exactly the same as
the preceding device. Under overload conditions,
the current is limited but the memory logic function
is inactive.
INDUCTIVE LOADS.
If a free wheel diode is connected across an inductive load, the voltage drop remains null while current
decays slowly (figure 4,l. Two distinct solutions are
possible to provide a rapid fall of this current:
b)- In the case where energy stored in the load
is very large, a Zener diode may be used to absorb this energy.
In case (b), the device and its internal logic circuits
are protected against negative voltage peaks appearing between output and ground (figure 4).
Figure 4: Current Decay in an Inductive Load.
ve
(b)
(a)
(el
a) - With free wheel diode.
b) ~ Without free wheel diode - the internal transistor operates in avalanche (@ voltage VzA).This condition offers the most rapid current fall.
c) - Addition of an auxiliary avalanche diode, Vz ~ V max.peak voltage accepted by the circuit. Note that these
devices have been designed to withstand peak negative voltages of as high as Vee - V ZA between output
and ground teminal.
4/9
372
APPLICATION NOTE
GROUND DISCONNECTION.
TDE1798 was particularly developed to meet
VDE422, the European standard which requires an
instantaneous disabling of the output circuitry in
case of accidental disconnection of ground
(figure 5).
Besides the protection against disconnection of the
power circuitry, these devices are also protected
against accidental disconnection of ground return
path. This is an outstanding security feature and the
Figure 5 : The auto protected control meet European security standard requirements. Output is automatically disabled in case of accidental disconnection of ground path.
~"\
~\II
1
ANOTHER PROGRAMMABLE CIRCUIT.
TDE1767 is another version of this circuit which in
combination with an external resistor, implements a
programmable short-circuit detection feature.
HIGHER POWER - OPTIMUM SECURITY
The control discussed so far are specified for output
currents of O.3A to O.SA. TDF1778 & TDF1779 are
dual auto protected control capable of handling up
to 2 x 2A. These monolithic devices contain 2 individual drivers which share a common monitoring
logic circuitry (figure 6).
Protection features offered by these circuits are:
A thermal protection feature similar to circuits
mentioned earlier.
Signalling Logic, Fault Memory and the availability of a Reset input (similar to preceding circuit).
Short-circuit protection. If the device is operated
with current of the order of 2A, safe operating
area of the transistor must be taken into account. Figure 7 illustrates the characteristics of
the integrated protection unit. The fault memory
feature is inactive when device is in current limit
mode.
The output transistor of these circuits is not protected in avalanche. However, in the case of
TDF1778, a 42V Zener diode inserted between the
positive supply and the base of the output transistor, will transform it to an avalanche protected transistor.
An additional feature, detection of load disconnection, is also offered by these circuits. A high-value
resistor (not shown in the figure 6) is connected between the power supply terminal and the outputs.
As long as the load remains connected to the output and the input is blocked, the output potential is
practically nUll. If the load is disconnected, this
potential will rise and correspondingly, a signal is
sent to the central unit through the Sense Output
terminal.
5/9
373
APPLICATION NOTE
Figure 6 : TDF1778 Autoprotected Control.
r-------I
Strobe
r-_.----~--------~--------~--_.--_t~Vcc
I
I
I
I
I
I
I
OulpUI I
Input 1
'--c=J-....-o Oulput 2
D-t--t=-J-...J
'----------4'"'"
D-t-------...J
Input 2
Sense
Alarm
oulput
outpul
I
C
I _________ _
Resel
Ground
input
Dual output: 2 x 2A. Fault memory. Thermal and short-circuit protection.
Detection of and protection against ground and load disconnection.
Figure 7.
I
Vee
(AI
TDF 177.
TDF 1779
10
20
30
40
Vee
0-
Va
tV)
Current protection limit. For TDFl778 and TDFl779 devices, this varies as a function of
Vee -Va voltage appearing across the controller. This limit corresponds to the safe operating area.
6/9
374
APPLICATION NOTE
APPLICATIONS
FUTURE EVOLUTION
Main characteristics of this family of AUTOPROTECTED CONTROL are:
• Particularly suited to 24V to 48V - 0.3A to 4A systems.
_ Operation from + 6V to maximum voltage.
_ Can be used in parallel configuration.
" Protection against:
_ Over-currents.
_ Excessive heating.
_ Accidental ground disconnection.
_ Interactive dialogue with central processor
unit (ALARM & RESET) terminals available
on certain series.
Detection of load disconnection (TDF1778 &
TDF1779).
_ Protection of output transistor by avalanche
(some families).
_ IlP and TIL compatible inputs.
Two trends for these circuits:
_ Enhancement of power handling capability.
_ Reduction of losses - A new circuit offering
considerable reduction of voltage drop .and
thus the losses, is forcast to be availaole in
1986. One of the consequences will be improving the circuit density in the equipment,
thus achieving size reduction.
Figure 8 illustrates some conventional industrial
automation applications built around these devices.
Power handling capability of these devices can be
readily enhanced by the addition of an external
power transistor as shown in figure 9. Further to
these conventional applications, autoprotected control are also well suited for the implementation of
choppers (figure 10) and more complex circuits
(Bridge, Half bridge ... ).
CONCLUSION
This new family of devices opens a new era of controllers which are:
_ On one hand stand-alone, i.e. self-protected
against external disturbances. If operated in
this mode, in case of fault occurence, the device itself will make the appropriate decision
without the intervention of the central processor unit.
On the other hand, capable of interactive dialogue, which means they are readily associated to processors and monitored by digital
systems.
7/9
375
APPLICATION NOTE
Figure 8 : Some Typical Applications of Autoprotected Controllers.
+ 24V
.. 24V
TOE 1647
+
OJA
Lamp driver
TOE 1647
TOE 1747
Small motor controller (constant torque breaking)
JL
JL
Electrovalve driver
8/9
376
Relay driver
APPLICATION NOTE
Figure 9 : TDE1767 Power Boosting.
Input
Safe operating
area in linear
mode.
p
z,
RSC resistor determines the short-circuit current.
Voltage V Z1 determines the abscissa of point M.
Resistor P determines the abscissa of point N.
VI (V)
R1 (KQ)
R2 (KQ)
+ 12
62
1.5
VO (V)
+5
+ 18
91
3.5
+ 12
Figure 10 : Voltage Step-Down Chopper.
V, __
~
____
~
__________- - ,
0.50
A1
'--------.-l.- Vo
100 kO
15 k{l
A2
9/9
377
APPLICATION NOTE
INTERFACES DEDICATED TO PROCESSES CONTROL
By J.M. BOURGEOIS & L. PERIER
Controlling tasks are very common in many areas,
for example the control functions associated with
buildings, the factory automation control, the production and control of energy, the chemical industries ...
These tasks are genrally managed by process controlers or industrial micro computers linked to a
supervisor and sometimes a dedicated computer.
At the control level, sensors and actuators are the
means of controlling the physical processes, and
are monitored and driven by the process controller
interfaces.
_ 90% of system failures are due to the wiring or
the sensors/actuors. Wiring may be reduced by
the use of a field BUS and the distributed interfaces.
_ Considering the remaining 10% of failures, 90%
of them are due to the input/output interfaces.
'Thus, if the reliability of the interfaces and the diagnostic functions are improved, the availability of the
system increases (working time/wirking time + stopping time). Agood means to achieve that is to use
integrated self protected interfaces allowing a telediagnostic from the controller. The devices have integrated on the same silicon chip the safety and
diagnostic functions and the power switch.
A better availability is achieved by mixing integrated
interface with field BUS, decreasing the first 80% of
errors, and the instanatiOn cost of the system.
A FAMILY OF INTEGRATED INTERFACES
The family of new circuits are dedicated to drive any
type of inductive and resistiv.e loads.
Their main characteristics are:
* No indeterminate states up on power on.
* Short circuit protection with the positive supply and
ground by current limitation.
* Over heating protection.
* Protected against overloads.
* Alarm output with delay.
* Open ground protection.
* Output voltage can be lower than ground for fast
inductive load demagnetisation.
* Differential input for universal logic compatibility.
* Output paralleling capability.
Generally, hybrid or discrete circuits are used for
these interface functions in process controller.
Using integrated devices is cost effective and provides a better thermal protection because of the integration of the temperature sensor. As
consequence, overload protection is totally reliable.
Integrated interfaces are available in high side and
low side configuration, for a range of current from
0.5A to 2A. They operate with a supply voltage
range of + 8V to + 32V, a typical block diagram of
one of these devices, the UAB/UAF 1780, is shown
in Figure 1.
APPLICATION CIRCUIT OF THE UAB/UAF 1780
+5U~~~--~~------~--~----~----.
3x
18K
AL 1
AN27010289
1/5
379
APPLICATION NOTE
Figure 1 : UAF 1780 Structure.
Rdl:f1lOCll
Alarm 1
InpUt 1
STROBE
~
Input 2
AIonn'
UnlylnGH--/1:J~-.on
APPLICATIONS
A local peripheral was designed for use by a micro
computer or process controllers. The circuit uses
four UAB/UAF 1780 which are dual integrated interfaces delivering up to 1A without heatsink and more
than 2A with. The interfaces are driven and monitored by a Z86E11 micro controller whose UART
allows the communication link with a serial field
BUS.
Figure 2 shows the block diagram of the system.
The configuration of the output of the integrated interface allows. each output to be used as on input
(via Po) if desired. Only one of the four UAF 1780 is
showed on the figure.
- In output configuration, the interface controls and
minotors the load. The feedback signal to the port
Po means that the state of the output can be monitored increasing the diagnostic capability
- In input configuration, the interface is off and the
signals are read via the Po port.
List of items:
* UAB/UAF 1780 : Intelligent full protected power switch
* Z86E 11 : 8 bits microcontroler
* TRANSIL TH6P04T6V5CL : Octal protection zener in OIL package
* L296 : High current switching regulator with reset output
* AM26LS31 : High speed differential line driver
* AM26LS33 : Oifferentialline receiver
* TRANSIL BZW5033 : Transcient voltage suppressors 5Kw/1 msec
* BYW1 00/1 00 : High efficiency ultra fast diodes VRRM = 1OOV trr = 25/60nsec Vf = 0.85V
2/5
380
M89UAF1780·01
"...
10'
c:
(D
I\)
OJ
(5
o
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o
Us-iS to 391)
'\llll1
33nFI947K
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ENABLE
rIEL
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BUS
~
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~en
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~:i!
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[Kt
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TH6P04
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SERIAL IN
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AL 1
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[
ZB6El1
P34
P35
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18K
.t
Uee
DC/DC
1
18
OUT 2
INPUT
GND
DELAV1
DELAV2
9
4
:~3p9FB
15K
7
r--
0
2u~~i:
OUTPUT
f rorn/ to
SENSOR
ACTUATOR
1'~
L296
.
B'rU188
-..J
"--
21
19BuH
1il
OUT 1
1+51)
12
:::rCD
UAF1780
RESET
-5-
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VREF Vee UDUT
INP 1
INP 2
STROBE
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w
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m
APPLICATION NOTE
MAIN CHARACTERISTICS OF THIS PERIPHERAL
a) Inductive load demagnetisation :
The ability of the integrated interfaces output to sustain negative voltage up to 30V, provide a very fast
demagnetization of inductive loads.
The size of the Zener diode depends on its voltage,
the load current and the commutation frequency.
b) Noise and spike immunity.
The interfaces are supplied directly from the local
24 V line. Because they withstand voltage spikes of
up to 60V for 1Oms, a transil is an effective protection for supply disturbances.
The outputs are protected by diodes connected to
the ground and to supply to ensure the interface outputs are not subjected to parasitic voltage spikes.
c) Interrupt priority register.
-The first priority is given to the switching regulator L296 which warns the· micro controller
when there is an interruption in the supply volt-
age. This regulator provides simultaneously two
auxiliary supplies one of which is isolated and
used for the field BUS interface AM26LS31.
-The second priority is used for the communication with the host computer via the UART.
-The third priority is used to monitor the deiault
signal of the UAF1780 interfaces.
d) Field BUS interface:
The galvanic isolation of this peripheral requires
only three opto couplers because of the mUltiplexing of the INPUT/OUTPUT and alarm signal.
e) Efficiency:
The high efficiency of these integrated interfaces is
due to an integrated DC/DC converter which reduces the on state voltage of the output Darlington
stage.
DIAGNOSTIC CONTROL
When alarm output is enabled, the following processus is started.
Memorise when the alarm occur and send
alarm register to host computer
YES
Diagnostic test
using feedback
control
4/5
382
>---·NO
APPLICATION NOTE
INTERFACE BEHAVIOUR
c) Over heating detection:
a) Inductive load.
Figure 5 shows the output current and alarm signal
in case of over heating detection. When the silicon
chip reaches 150°C, the current is switched off and
the alarm output actived. If the reset input·is low, the
switch restarts after the thermal hysteresis cycle and
a preset delay. If the reset is high, the switch will remain off and the alarm low.
Figure 3 shows the turn-off commutation with an inductive load, the demagnetisation zener diode used
was 10V. This diode provides a current path for the
load demagnetisation and a protection against negative spikes induced from in the wiring.
Figure 3 : I load: 0.4 A/div
V out: 10 V/div.
,
I
B
I
I
• .. .
..
••
•
I
... ,'
_:,B
_
••
!.
The set of devices used for this application is optimized and provides a high immunity against all disturbances from the line voltage, the wiring and the
loads.
-4
III
••
I
B
• D ~•
•
I III B
CONCLUSIONS
This family of integrated full protected interfaces
provides more reliability in process control. Due to
the alarm output, the real time diagnostic function
can easily be multiplexed with a low cost micro controller.
B
-I
~
-_.-
-.
!. --.
~--
BIBLIOGRAPHY
' .. ,
(1) AUTO PROTECTED CONTROLS
Selection guide SGS - THOMSON
(2) NEW INTELLIGENT POWER COMPONENTS
By K.RISCHMULLER, ELECTRONICA MUNCHEN 1986
t : 20 msec/div.
b) Short circuit behavior:
Figure 4 shows the output current and the alarm signal in case of short circuit. The current is internally
limited for a preset delay, after which a low level is
applied on the alarm output and the current switched
off. This device can be reactived by the reset input.
Figure 4 : V alarm: 2 V/div
I load : 2 A/div.
(3) THE FIELD BUS
by J.THOMESSE ENSEM/CRIN NANCY/FRANCE
(4) LA COMMUTATION A FAIBLES PERTES
D'INSERTION
by M.REFFAY, (Electronique Industrielle - 1
Mars 1987)
(5) RESEAUX ET TELEMATIQUES
by G.PUJOLLE, D.SERET, D.DROMARD, E.
HORLAIT, (EYROLLES EDITIONS)
t : 1 msec/div.
W:rtf/
SGS·THOMSON
C SOV
VTH = 3V
P-CHANNEL DRAIN EXTENSION
BVDss > 75V
= 1.9V
VTH = 0.9V
VTH = 1.9V
j3 = 30
j3 = 30
j3 = 250
j3 = 250
C-MOS N-CHANNEL
BV Dss > 15V
C-MOS P-CHANNEL
BVDss> 15V
BIPOLAR PNP
VCEO > 20V
BIPOLAR NPN1
VCEO > 20V
BIPOLAR NPN2
VCEO > 20V
BIPOLAR NPN3
VCEO > 20V
IT
=
1GHz
h = 200MHz
VTH
IT = 10MHz
fr = 300MHz
IT
=
1GHz
IT = 140MHz
Figure 4 : A Schematic Cross Section of Bipolar, CMOS and DMOS Structures.
L -_ _ _
POWER
---.l L. ____ J L _____ ~
OMOS
CMOS
s-
4/8
388
9351
NPN
1
L I_ _ _
-.J
L I_ _ _
PNP H.V. P-CH
MOS
APPLICATION NOTE
_ N-CHANNEL POWER DMOS able to withstand
VDS = 60V for the series element.
_ BIPOLAR NPN AND PNP TRANSISTORS mainly employed in analog circuitry where low offset
and high gain are needed e.g. voltage comparators and references, operational amplifiers.
_ CMOS TRANSISTORS to realize a dense logic
network with stand by currents practically neg ligable.
_ PASSIVE COMPONENTS as resistors with a
great variety of sheet resistivity (30+8500QlD)
to optimize both very high and very low resistive
circuitry and gate oxide capacitors (e.g. to realize
charge pump capacitors).
THE CIRCUIT
The circuit (fig. 5) is made by a power DMOS series
element, a driving circuit with a charge pump, an input logic interface and some protection and fault detection circuits.
Figure 5: Block Diagram of High Side Switch L9801.
+Ve 1
r---------------------- --------------------,
1
1
3 1
1
CURRENT
GND~
1
OPEN
LOAD
I
IIII I
~
OUT
5
1
1
1
1
1
~
1
U006: : DIS
___________________________________________ J
1
Q9
5-9895
5/8
389
APPLICATION NOTE
THE POWER DMOS
The power DMOS transistor is an array to 10,000
elementary DMOS cells that occupies an area of
about 19,000 mils2 and has a ROS(on) = 80mQ with
VGS = 1OV. The low value of ROS(on) is required both
to increase the power transferred to the load and to
minimize the power dissipated in the device. In fact
the switch must be operative also at very high ambienttemperature (125'C) as required in automotive
applications. For example to drive a 5A (60W) load,
the drop on the switch is 400 mV and the dissipated
power is 2W (Rth j·case 1.25'CIW).
Nevertheless a solution with a voltage reference
and comparator is not suitable because it needs a
bias current flowing also when the device is in the
OFF state.
This point is of great importance because the
switches are directly connected to the car battery
without the interposition of the ignition switch, thus
also a little current (> 50j.lA) multiplied for the number of the switches (e.g. 50), causes an appreciable
discharge current always flowing.
For this reason a threshold circuit has been designed
derived from a well known voltage reference (fig. 7).
Figure 7 : Input I;,terface.
THE CHARGE PUMP
The charge pump is a capacitive voltage doubler
(fig. 6) starting from power supply (car. battery), driven by a 500 KHz oscillator.
The pump capacitor is an integrated 80 pF capacitor, the storage capacitor is the gate capacitance of
the power itself (- 500 pF).
Figure 6 : Charge Pump.
OUT
IN n-....,-~---«:
+Vs
5 - 9903
Fixed a threshold value VIN = VIN*forthis value must
be, by design h = 12 = 10*.
500 KHz
OSCILLATOR
if
IX
=area ratio
must be
DISABLE
5-9902
OUTPUT·
A01
IX=--
A02
h -
/).VBE
R1
(h + 12) R2 + VBE (02) = VIN
R2 KT
that is VIN* = 2 -R 1 n IX + VBE 02
1 q
INPUT INTERFACE
Considering the very wide operating temperature
range (Tj = 40 to + 150'C) it is not possible to
obtain the logic threshold from the conduction threshold of any elementary device, because of its temperature coefficient, respecting TTL input levels.
6/8
390
Reasoning around the threshold point it can b~ noted that the transconductance of 02 is greater than
the transconductance in 01 branch (01 series R1).
For this
03 ON
if VIN > VIN*
03 OFF
if VIN < VIN*
APPLICATION NOTE
The choice of the values is made imposing:
1) VIN* '" VSG '" 1.2S0V band-gap voltage of silicon.
In this case VIN* is practically stable in temperature and centered respect TIL input levels
(VLMN< = O.SV. VHMIN = 2V).
The idle current lASS in the worst case, that is
when VIN = VLMAX = O.SV. Tj = 1S0°C, it must be
lASS = h + 12 < SOl! A.
The proposed circuit has also a third working region:
when VIN < VSE
lASS = 0
03 OFF
Observed that the TIL OUTPUT low level is VL MAX
O.4V with practical driving circuits the idle current of
this interface is zero: only at very high junction temperature (VSE < 400mV) or with noise margin = VSE
O.4V) this performance cannot be warranted.
The output of this circuit is useful to switch off not
only the power DMOS, but also all the other circuits
so that the idle current only the one of the input interface.
PROTECTION AGAINST OVERVOL TAGES
When the supply reaches the maximum operative
voltage (1SV) the device is turned OFF, protecting
itself and the load; moreover local zener clamps are
provided in some critical points to avoid that VGS of
any MOS transistor could reach dangerous values
even during 60V load-dump transistor.
PROTECTION AGAINST OVERLOAD
If the design of this device the peculiar inrush current of incandescent lamps must be considered, in
fact.
1) When the tungsten wire is cold its resistence is
about one tenth of the nominal steady state value (e.g. about 300mQ for a 12V/SOV lamp).
2) The decay time constant for the turn on extracurrent of an incandescent lamp supplied with
an ideal voltage source is on the order of some
milliseconds.
3) A lamp powered with a constant current slightly
higher than its steady state value has a turn on
time on the order of 1OOmsec. This time comparable with human reaction time is too much long
for all flash-signalling devices.
The design choice has been to put a 20A current limit (th~t is Imax = S Inom for a SOW/12V rated lamp).
This is a compromise between lamp turn on time
(40msec) and electric and thermal dimensioning of
the device (fig. S).
If the high current condition persists (e.g. load short
circuit) and the junction temperature rises above
1SS'C a thermal protection circuit turns off the device preventing any damage.
It must be noted that the power DMOS has no second breakdown, for this reason current limiting and
thermal shutdown are sufficient to protect the device
against any overload.
Some thermal hysteresis is provided to avoid a potentially critical condition (both current and voltage
present during thermal shut down) for the POWER
MOS.
Figure 8 : Lamp Current (IL) and Voltage (VL) vs.
Time with 20A Current Limitation and
12V/SOW Lamp.
. -__, -__, - - ,__-,~G~-~"=55--'VL
(V)
20 r-r------j------:1:::::::;:====j14
16 1----I"'1\-----i--
--
12
10
12 f-+----'---"'::--
6
L-~
o
__~__~__~__~__~
10
20
30
40
4
50 t(ms)
FAULT DETECTION
When the device is driven and one of the protections
(over temperature, overvoltage, overload) is present a fault detection open drain output tums-on.
This output is active also when the drop on the POWER MOS is less than SOmV (that is Iload < 1A) detecting the open load (disconnected or burned-out).
When the device is off the fault detection circuits are
not active and output transistor is turned off to allow
a minimum quiescent current.
MOTOR AND INDUCTIVE DRIVING
This device can drive unipolar DC motors and solenoids as well, in fact is can recirculate an inductive
current when the output voltage goes more than a
threshold lower than ground. The possibility to have
a high start-up current is useful also for DC motors.
7/8
391
APPLICATION NOTE
CONCLUSION - FUTURE DEVELOPMENTS
A process allowing the integration of power DMOS,
CMOS and BIPOLAR transistor makes possible the
construction of a monolithic switch comprehending
also protection and fault detection functions.
The power DMOS approach allows also the possibility to make a large range of power switches with
different ON resistance and current capability only
scaling proportionally the power area.
8/8
392
Moreover the CMOS structures can be utilized to
make also the coder/decoder circuit to interface directly the transmission line.
Those features and the possibility to integrate more
than one power element on the same chip makes
possible, in a near future, the integration of the
wholeperipheral unit.
POWER SUPPLY
393
APPLICATION NOTE
DESIGNING WITH THE L4963 MONOLITHIC
DISCONTINUOUS MODE POWER SWITCHING REGULATOR
by M Roncoroni
The L4963 is a new switching regulator designed to operate in discontinuous mode, reducing the
number of the external components, giving a very cost effective solution. This application note
explains how the device operates and how it can be used. Typical application circuits are also
described.
The L4963 is a new monolithic step down switching regulator IC operating in discontinuous mode.
This device, able to deliver 1.5A to the load at a
voltage of 5.1 V and up to 36V with derated current, is designed to satisfy very low cost applications due to the fact that the number of the external components are dramatically reduced.
Moreover the inductor value is reduced by a factor of three or four in comparison with a corresponding continuous mode solution. Also the
plastic package (Powerdip 12+3+3), that needs
no heatsink, contributes to decreasing the cost of
the overall application.
Although the L4963 is intended for very low cost
applications, it integrates features like remote in-
hibit, reset and power-fail outputs for microprocessor.
In the following we will explain in detail its principle of operation and the criteria that regulate the
choice of the external components.
CIRCUIT OPERATION
The L4963 operates in discontinuous mode. In
principle in this kind of operation the energy
stored in the inductor is fully discharged to the
load before to start a new cycle.
To operate in this way, the device contains, in its
regulation loop, additional blocks compared to the
usual Error/Amplifier, Oscillator and Pulse Width
Modulator used in the continuous mode devices.
Figure 1: L4963 Block Diagram
--
.......... .
. ucc
: uss 3
UOUT
1
.:!:. CI
:!
L4963
UCC
P.F.
R1
8
OUT
4-5-6
13-14-15
19
7
P. F. IN
C
:C0ELAY
AN458/0190
n!1IL4!163-8t
1/17
395
APPLICATION NOTE
Figure 2: Waveforms
T
IL
ton toff' toff"
f152f1N458-82f1
ton
·4
(A) FIXED FREQUENCY OPERATION
The L4963 control loop is shown in the block diagram of fig.1 and the blocks that take part to the
regulation loop, are determined by the system
operating conditions.
For a given value of the inductor L (that will be further calculated), if we examine the current across
the inductor ( IL ), we can have two different situations that modify the device operation. This two
different conditions depend on the load current
value that device has to deliver: changing the load
current ( 10 ), the current through the inductor can
have one of the shapes shown in fig. 2.
In both the waveforms, the current in the coil goes
to zero during the Toft period of the power stage,
but in the case shown in fig. 2A there is a "Dead
Time" during which, both the Power stage and the
Free-Wheeling diode are not conducting. The
dead-time period ("Toft") increases lowering the
load current. The system will start with a new
cycle at the next set pulse coming from the clock.
In this way the system operates in fixed frequency
mode, set by the External resistor RT connected
between pin. 17 and ground.
In fixed frequency mode, the current in the inductor reaches the peak value, determined by the
load current, following the law:
Vin - Vcesat - Vout
L
. ton (1)
2/17
toff
i4-:4---T
~:
T1
(8) UARIA8LE FREQUENCY OPERATION
When the output voltage reaches its nominal
value, the E/A output resets the power stage and
the discharge period starts.
When the power transistor turns off, the inductor
will try to mantain the forward current constant,
and the voltage at pin.2 will fly negative until the
diode D is brought into conduction. The current in
the inductor L will now continue to circulate in the
same direction as before, decreasing linearly from
the peak value to zero following the law:
Vout + VF
IL- = Ipeak L
. toff (2)
It follows, then, a third period toft" (dead time) during which there is no current neither across the
power transistor, nor in the diode D, nor in the inductor L (the inductor runs 'DRY'). This period
ceases when the next set pulse from the clock
circuit enables again the power stage repeating
the cycle.
The operation frequency is equal to the clock frequency, that is determined by the resistor Rt, connected between pin. 17 and ground:
0.033
fosc (KHz) = Rt (KQ)
In fig.3 are shown the voltage and current waveforms associated to this mode of operation.
------------------------ ~~~~~~~~:~~~ ----------------------------396
APPLICATION NOTE
Figure 3: Fixed Frequency Operation
!
ILlIG
,
,.
.
UR
::
S
..
:
.
I.
.
::
I
.
.
UO~
"
"
..
"
"
.
.'
'
..
.
.'
'
.
.'
OSCILL'~
SET PULSE ~.
RESET PULSEk ~
n ~L. .
·
COMP "8"
OUT
_ __
L
11!J2f1N458-83
- - - - - - - - - - - - - ....,1 SCiS·THOMSON
~
3/17
i!lrrl!:lll@rn~rnI!:VIll@OllII!:® - - - - - - - - - - - - -
397
APPLICATION NOTE
inductor is completely discharged and the diode D
ceases to conduct (see fig.4).
The system is working in a variable frequency
mode, with a switching frequency that is depending on the current delivered to the load.
Bigger is the load current higher is the stored energy and longer is the time during which the comparator will block the discharge of the. timing capacitor Ct, decreasing the system operating
frequency. In fig.4 are shown the waveforms associated with this mode of operation.
Referring again to the block diagram in fig. 1, and
with a given inductor L, we suppose to have a
load current that reduces the Dead Time toff" to
zero. At this point we suppose that the clock send
a set pulse to the latch and the power stage turns
on. The current in the inductor grows from zero
up to its peak value (lpeak=2Iout) following the law
stated in Eq. 1.
If the peak current is below the Current Limitation
threshold, it is again the Error Amplifier that turns
off the power stage and the inductor will discharge following the eq. 2.
If the system is not able to discharge completely
the inductor during the maximum toff time. allowed
by the fixed frequency operating mode an internal
comparator, (which compares the voltage on the
free-wheeling diode cathode with a precise internal
reference Vr = -100mV) will mantain the power
stage off until the inductor will be completely discharged.
This comparator prevents the discharge of the internal timing capacitor Ct, until the Energy in the
CALCULATION OF THE INDUCTANCE VALUE, L
To calculate the inductance, that is a critical element in the circuit, we have to consider that:
• The switching frequency increases reducing
the load current lout and increasing Vin.
• The switching frequency decreases increasing
the load Current lout and decreasing Vin.
So to calculate the inductor value we have to
Figure 4: Self-oscillating Operation
ILI~
"UJ
'" t
·
.
•
•
·· ..
. ,
OSCILL'~:
~.
:
~
·· .,
.. ..
'.
..
· .
,
.
·· .,
-
•
•
,
I
tt;~_-------lnL......;-::_PULSE
:
•
h
SET PULSE
RESET
~
· .
______
~~L-
_______
COMP "8" _....;...---;
OUT
fI!l2I1N458- 84
4/17
i::='= SGS.1lI0MSON
- - - - - - - - - - - - - - IA'!'
iI\IU©IliI@n~©~IiI@OOU©~
398
--------------
APPLICATION NOTE
specify the minimum operation frequency (higher
than 20KHz to avoid audible noise), for the minimum input voltage Vin at full load.
The equation to calculate the maximum inductor
value is:
(Vin(min)) - Veesat - Va) . D
L~
2· lout(max)' fmin
Va + VF
where: D = ,-:-----'-:-:---'----:-:-"'
Vin(min) - Veesat + VF
In overload or in short circuit conditions, the
switching frequency decreases below the minimum limit fixed in standard operative conditions
(fmin). For this reason is important to select a fmin
with margin to avoid values inside the audible
range in worst case.
Too low inductance values are not suitable because the increased ripple current in the core
may generate too high ~ipple voltage in the output.
Example:
We want to use the L4963 in an application in the
following conditions:
Vi = 15V to 35V
Va =5V
10 = 1.5A (max)
fmin > 25KHz
Veesat= 1.5V
VF = 1V
The right inductance for this application is calculated as follows:
5 + 1
Where:
ILpeak
Ve = -8---'==--'
. Cout .
21 0ut
8 . Cout . f
lout
4· Cout . f
(7)
VESR = ILpeak . ESR = 2· lout . ESR (8)
Once fixed the amount of ripple voltage desired
for the application, with the first term we determine the minimum suitable capacitor value and
with the second one we determine the maximum
ESR acceptable.
Normally, for frequencies above 20KHz, the maximum ESR defines the choice of the filter capacitor value. In general, lower capacitor values have
higher ESR ratings, so higher output capacitors
than is calculated in eq. (7) should be used.
To guarantee a proper operation of the internal
Error Amplifier, the minimum ripple voltage in the
output must exceeds 15mV, to ensure a minimum
voltage difference across its input terminals.
POWER DISSIPATION
It can be considered as the addition of three
values:
Ptot = Psat + Pq + Psw
where:
Psat: Saturation losses of the power transistor
plus the sensing resistor power dissipation.
Dmax = 15 _ 1.5 + 1 = 0.41
Psat = V32 . 10 . ton = V32 . 10 . Va
T
Vi
L ~ (15 - 1.5 - 5) ( 0.41 ) = 46 H
. 11
2 . 1.5 . 25 . 103
V32 = dropout voltage between input (pin 3) and
output (pin 2).
For worst case (for 12 = 3A switch current) the V32 =
2V
Pq: Losses due to the stand-by current and to the
power driving current.
Suggested value for L is in this case 40llH that
corresponds to about a 15% less the max.
allowed inductance.
OUTPUT CAPACITOR SELECTION
All the considerations for the choice of the filter
capacitor in a system working in continuous mode
are still valid in a discontinuous mode operation
(Ref. L296 Appl,note). Let summarize the results
with some useful suggestion for this specific system.
The Ripple Voltage imposed on the D.C. output
voltage is given by the sum of two terms. The first
term (Ve), depends from ILpeak, Switch. Frequency
and Cout values and the second (VESR) is due to
Equivalent Series Resistance (ESR) of the capacitor multiplied by the ILpeak current.
Va = Ve + VESR (6)
Pq = Vi . 1'3q + Vi . 1"3q =
t~ = Vi . 1'3q +Vo . I" 3q
In fig. 6 and fig. 7 are showed these two typical
values of quiescent current.
For the we worst case we can considered:
1'3q (0% d.c.) =13mA
1"3q (100% d.c.) = 17mA
Psw: Power transistor switching losses:
Psw=Vi·IO·
tr + If
2T
5/17
----------------------------- ~~~~~~~~:~~~ -----------------------------
399
APPLICATION NOTE
Figure 5: V32 Voltage vs. Output Current
1192AN45B·85
V32
I V)
1.2
::-- -
-25'~
1.1
1.0
13.9
-
0.B
f.--
0.7
r-
-
I--
---V
/
Vo.Vref
IlJ)
/
Io,,1.5A
/
1.8
/
0.9
0.5
/'
119tL 4963·28
Pd
,,;125'C
V
--
0.6
Figure 8: Power Dissipation vs. Input Voltage.
~ Axe
V
The fig. 8 shows the total power dissipation of the
device.
For Vout >5V the output current can be less then
1.5A. In fact we have to consider that the maximum power dissipation for this device is 2W at
Tamb of 70° and is this value that limits the output
current value.
121AI
1.7
1.3
Figure 6: Quiescent Drain Current vs. Supply
Voltage (0% Duty Cycle)
1.6
'\.
/'
V,
1.4
1.2
/
10 ·lA
V
./
119 tL 4963· Be
Iq
ImA )
/
-
~,/
14
10
20
30
40
50
ViIV)
13
EFFICIENCY
The system efficiency is expressed by the following formula.
12
11
1(3
9
8
---
f.--
10
- -- ------
20
Po
'11%=- 100
Pi
413 V i I V)
313
Figure 7: Quiescent Drain Current vs. Supply
Voltage (100% Duty Cycle)
1191L4963-B9
Iq
ImA)
14
13
12
f...-
---
-
f...-
where Po = Vo 10 (with 10 = Iload)
is the output power to the load and Pi is the input
power absorbed by the system. Pi is given by Po
plus all the other system losses. The expression
of the efficiency becomes threfore the following.
Po
Po + Psat + Pq + Psw + PD + PL
'11=~~~~~~--=-~
The three terms concerning the device power
losses have already been discussed in the previous paragraph.
We examine now the last two terms concerning
the external components losses.
---
PO - Losses due to the recirculation diode
These losses increase as Vi increase, as in this
case the ON time of the diode is greater.
11
113
9
PD = VF . 10 .
8
10
6/17
213
30
413 V i I V)
---------~---400
Vi - Vo
Vo
= VF· 10 . ( 1 - - )
Vi
Vi
where VF is the forward voltage of the recirculation diode at current 10.
liii ~~~~mg,r::U!~:: --------------
APPLICATION NOTE
Figure 9: Efficiency vs. Output Voltage
W = 0.568 , f1.23 . 8 2 .56
f1!31L436J-24
"C
(% )
913
80
/~ --LoB8uH
~~
V
W
78
where W = wattllb
f= KHz
Lo lS8uH
Lo 108uH
b
8 = KGauss =
Lo4GuH
N = number of turns
Ae = core cross section (cm 2 )
1001. SA
OoBY~98
Uio45U
Au to Oscillating
18
38
28
(Vi - Vo)·Vo·10 B
N . A e· f . V'I
copper losses:
P - pl20 ML T.N
N = number of turns
MLT = lenghtlturn for 20% of winding factor
p = copper resistivity (1.721 OE-6Wcm)
Refer to table 1 for some p/Aw suggest values.
Table 1
lJout
Figure 10: Efficiency vs. Output Current
t1!3JL4963-23
"C
(% )
DIODE
BY~9B
lJo=l)ref
AWG
Diameter
Copper
(em)
OHMS/CM
20C
OHMS/CM
100C
98
UIN-1SU
88
UIN 30U
78
18
.102
.000209
.000280
19
.091
.000264
.000353
20
.081
.000333
.000445
21
.072
.000420
.000561
22
.064
.000530
.000708
58
Typical efficiencies obtained with the test and application circuit of fig. 20 are shown below.
0.5
8.7
0.9
1.1
1.3
10
(AI
PL - Losses d~e to the coil
Wecan divide these losses in two parts: core
losses and copper losses.
The core losses for molypermalloy powder cores
are given by the following formula.
DEVICE DESCRIPTION
Fig.11 shows the pin connection of the Powerdip
12+3+3 plastic package. The internal block diagram of the device is shown in fig.1. Each block
will now be examined in detail.
Figure 11: Powerdip 12+3+3 Pin Connection
SIGNAL SUPPLY VOLTAGE
OUTPUT
SUPPLY VOLTAGE
GNO
GNO
GNO
P.FAIL INPUT
P.FAIL OUTPUT
RESET DELAY
R OSCILLATOR FREQ.
C OSCILLATOR
INHIBIT INPUT
GND
GND
GND
FEEDBACK INPUT
REFERENCE VOLTAGE
RESET OUTPUT
ff9tL4963-82
7/17
-------------- LW ~~~~m~~:U!~l: -------------401
APPLICATION NOTE
POWER SUPPLY
The device has two separate pins dedicated for
the supply source. Pin.1 is for the Signal (Vcc)
and Pin.3 for the Power (Vss) source; normally
these two pins are connected together (see the
typical application circuit Fig. 18). The L4963 is
provided with an internal stabilized power supply
that feeds the precise internal voltage reference
5.1 V (±2%) and the internal analog blocks.
UNDER VOLTAGE LOCK OUT (UVLO)
The UVLO circuit ensures that Vcc is adequate to
make the L4963 fully operational before enabling
the output power stage. The UVLO turn-on and
turn-off thresholds are internally fixed at 8.4V and
7.9V respectively.
This function acts also on the Power Fail and
Reset Circuits; their output voltages pin.8 and
pin.10 respectively, remain low state until the
turn-on threshold is reached.
OSCILLATOR
The oscillator circuit behaves in a completely different way compared to the usual Step-Down
regulator operating at fixed frequency and variable duty cycle. In fact, usually, the oscillator
generates a fixed frequency sawtooth waveform
that .is compared with the Error Amplifier output
voltage/ generating the PWM signal to be sent to
the power output stage.
In the L4963, the oscillator function is quite differ-
ent. In the following we will describe briefly its
operatio.n referring to the simplified interrial schematic shown in fig.12.
It is composed of a comparator (with inputs compatible to ground) with an hysteresis whose thresholds are 1V and 4.1 V respectively.
The oscillator uses an external resistor RT on
pin.18 to establish the charging and discharging
current of the internal timing capacitor CT = 50pF,
fixing in this way the maximum switching frequency;
0.033
fosc(KHz)= Rt (KQ)
It is also possible to increase the internal timing
capacitor value, connecting an external capacitor
between pin.17 and ground. The oscillator circuit,
as we have seen in the "CIRCUIT OPERATION"
paragraph, sends a set pulse to the latch that enables the power stage.
This set pulses train is at fixed frequency imposed
by the external resistor when the device operates
for low output currents (Dead time present in the
inductor current IL).
When we are operating in self-oscillating mode,
the comparator that senses the free-wheeling
status disables the oscillator pulses output until
the inductor is fully discharged, varying in this
way the switching frequency. It is also possible to
disable the osci!lator forcing the system to operate always in, self-oscillating mode, connectingtogether the internal oscillator capacitor (pin.17)
with the voltage reference pin.11.
Figure 12: Oscillator Circwit
Ui
1. 25U
3
INH 18 IT
RT
1192RN45B-8?
8/17
---------------------------~~~~~~~:9n
402
---------------------------
APPLICATION NOTE
CURRENT LIMITATION
Output overload protection is provided by a current limiter circuit. The load current is sensed by
an internal metal resistor (Rs) in series to the
power transistor. When the voltage drop on the
sense resistor, reaches the current comparator
offset voltage, the current comparator generates
a reset pulse for the latch, disabling the power
stage.
Typical current limiting threshold is around 4.5A.
The power stage will be enabled again only when
the energy stored in the inductor will be completely discharged, this due to the free-wheeling
sense comparator (see Circuit operation paragraph for details).
The current limiting circuit operates also as softstart during the device turn-on preventing overcurrents on the load.
In fig.13 is shown the simplified internal schematic circuit of the current limiter.
Figure 13: Current Limiter
"92RH"5B-BB
RESET
The reset circuit accomplishes a very important
function when the L4963 is used in applications
where it feeds microprocessors and logic devices.
The function block diagram is shown in Fig.14.
The Reset circuit monitors the output voltage and
generates a logic signal when the output voltage
is within the limits required to supply correctly the
microprocessor.
This function is realized through three pins:
• Feedback input (pin.12)
• Reset delay (pin.9)
• Reset output (pin.1 0)
When the monitored voltage on pin.12 is lower
than 5V, the comparator (A) output is high and
the reset delay capacitor is not charged because
the transistor 01 is saturated, also the transistor
02 is saturated, mantaining the voltage on pin.1 0
at low level.
When the voltage on pin 12 exceeds 5V, the transistor 01 switches off and the delay capacitor
(Cd) starts to charge through an internal current
generator of about 11 OIlA. When the voltage on
pin 9 reaches 4.5V, the output of the comparator
(B) switches low and pin 10 goes high.
As the output is an open collector transistor (02),
a pull-up external resistor is required.
On the contrary, when the Reset input voltage
goes below 5V, with an hysteresiS of 100mV, the
comparator (A) triggers again and sets istantaneously the voltage" on pin 10 low, therefore forcing to saturation the 01 transistor, that starts the
fast discharge of the delay capacitor.
As shown in the block diagram, the Reset output
is low when the UVLO or The INHIBIT signals are
present.
Inside the chip there is a digital filter that prevents
the Reset circuit activation if Vout drops below the
reset threshold for less than 2s.
In this way the Reset circuit neglects very fast
drops in the output voltage.
In fig.15 and Fig.16 are shown respectively the
Reset circuit Waveforms and a typical application.
Figure 14
9
Cd::c
12
"92RH45B-B9R
----------------------------- ~~~~~~~~:oo~~ ----------------------------9/17
403
APPLICATION NOTE
Figure 15
RISING P.FAIL
THRESHOLD
TURN-ON
THRESHOLD__
Ui
r-------------~
L-~
____________________
~
___TURN-OFF THRESHOLD
P.FAIL OU~
Uo-5.1U
• ~ ••
RISING RESET
THRESHOLD
,
•• 5U
.'. 199mU
: FALLING', ~HISTERESIS
,
RESET
:.
: THRESHOLD: :
OUTPUT RESET
~
.;;-----.;!-
tdr
tdr
DELAY RESET
If91LoI96S-33
Figure 16
POWER FAIL
R4
TP2
R3
Ui
11
138
Uo-Uref
2t-........rvv'--+---+-+----,,o
C1
L4953
9
R5
13.14.15
18 4.5,6
INHI8IT
C2
R2
GND
I1!HL4963-3B
10/17
----------------------------- ~.~~~~~~~~~~ ----------------------------404
APPLICATION NOTE
POWER FAIL
The Power-Fail circuit monitors the supply voltage
(Vss) via an internal voltage divider (Rl =115Kn,
R2=35Kn) as shown in Fig.l? When the supply
voltage reaches the typical rising threshold voltage of 22V, set by the internal voltage divider, the
Power Fail comparator output voltage goes low,
turning off the output transistor Ql. This gives an
high level on pin.S. As the power Fail output is an
open collector transistor (Ql), an external pull-up
resistor is required.
The Power Fail output goes low, giving an alarm
signal, when the input voltage decreases reaching the internal typical Falling threshold voltage
level of ISV. It is possible to change the rising
and the falling threshold voltages, connecting a
proper external voltage divider on pin.?
In fig. 15 are shown the power fail waveforms.
INHIBIT
The INHIBIT function, available on pin.16, disables the regulator with a TTL logic signal. An
high level at this pin (above 2.2V) switches off the
power stage and forces low the output reset.
This useful feature, is normally used for supply
sequencing and remote control ON-OFF.
THERMAL PROTECTION
The thermal protection function, operates when
the junction temperature reaches 150a C; it acts
directly on the power stage, turning it immediately
off.
The thermal protection is provided with hysteresis
and therefore, after an intervention has occurred,
it is necessary to wait for the junction temperature
to decrease of about 30 a C below the intervention
threshold.
APPLICATIONS
The L4963, thanks to the reduced external component count represents a very low cost effective
solution in many applications.
In Fig.1S the complete typical application circuit is
shown, where all the functions available on the
device are being used.
In fig.19 is shown the same application circuit for
reduced filter capacitor count and its PCB. As evident the PCB dimensions are reduced.
Below we will describe the design procedure to
follow and some suggestion regarding the external components to use.
Figure 17
Uss
P.FAIL
115K
7
35K
tf92f1N458-tB
11/17
----------------------------- ~~~~~~~~:~~ ----------------------------405
APPLICATION NOTE
Figure 18: Test and Application Circuit
POWER FAIL
1K
1K
Ui
3
1
8
12
2
11
11313uF
Uo
L4963
1K
RX
13.14.15
18 4.5.6
16
4.7K
INHIBIT
2.2uF
51K
GND
Uo:
Uo:
Uo:
Uo:
12U
15U
18U
24U
Rx
Rx
Rx
Rx
• 6.2K
• 9.1K
• 12K
• 18K
1f91L4963-34
PART LIST
CAPACITOR
Resistor Values for Standard Output Voltages
C1
1000flF 50V EKR (*)
Vo
R6
C2
2.2flF 16V
12
4.7Kn
6.2KQ
4700flF 40V EKR
15
4.7Kn
9.1KW
1flF 50V film
18
4.7Kn
12KW
24
4.7Kn
18KW
C3, C4, C5
C4
RESISTOR
R1
1KQ
R2
51KQ
R3
1KQ
R4
1KQ
R5,R6
see table
RS
Diode: BYW98
Core: L = 40flH Magnetics 58121-A2MPP
34 Turns O.9mm (20AWG)
n Minimum IOOflF if V; is a preregulated offline SMPS output or 1000flF if a 50Hz transformer plus rectifiers is used.
12/17
----------------------------- ~~~~~~~:~~~
406
-----------------------------
APPLICATION NOTE
Figure 29: Typical Application Circuit
POWER FAIL
R4
R3
TP2
Ui
11
1
3 8
HI
12
LI (*1
2
C1
L4963
16
9
13.14.15
18 4.5.6
INHIBIT
C2
R2
GND
f19tL4963-3B
PART LIST
CAPACITOR
Resistor Values for Standard Output Voltages
Vo
R6
RS
12
4.7Kn
6.2Kn
15
4.7Kn
9.1KW
50Vfilm
18
4.7Kn
12KW
RESISTOR
24
4.7Kn
18KW
C1
1000~F
C2
2.2~F
C3
4700~F
C4
1~F
50V EKR (*)
16V
40V EKR
R1
1Kn
R2
51Kn
R3
1Kn
R4
1Kn
R5,R6
see table
Diode: BYW98
Core: L = 40lJ,H Magnetics 58121-A2MPP
34 Turns 0.9mm (20AWG)
(.) Minimum 100llF if V; is a preregulated offline SMPS output or 1OOOIlF if a 50Hz transformer plus rectifiers is used.
13/17
--------------------------- ~~~~~~~~~~ --------------------------407
APPLICATION NOTE
Figure 20: P.C. Board and Component Layout of the Circuit of fig. 21 (1:1 scale).
L4963 Step-Down Regulator Design Example
Referring to the complete typical application circuit shown in fig.19, and defined the following
conditions:
• Vout = Regulated output voltage
• Vin(min)= Minimum input voltage
• Vin(max) = Maximum input volt'!-ge
• lout(max) = Maximum load current
• fmin = Minimum switch freq. in self-oscillating
.
mode.
We calculate the value of the external compo.
nents.
1. OUTPUT VOLTAGE SETTING:
The output voltage is established by the voltage
divider constituted by R5 and R6. To select the
right R5 value use the following formula:
R5 = (Vout-Vrel) . (R6)
Vrel
where: Vrel= 5.1V
R6 = Is normally set at 4K7Q
For a Quick calculation of some standard output
voltages, the following table is useful;
Resistor Values for Standard Output Voltages
Vo
R6
R5
12
15
18
4.7Kn
4.7Kn
4.7Kn
4.7Kn
6.2KW
9.1KQ
12KQ
18KQ
24
14/17
To obtain Vout = Vre!, the pin.12 is directly connected to the output, therefore eliminating both
R5 and R6.
2. INDUCTOR SELECTION:
The max. duty cycle is determined by the following formula:
Vout + VF
Dmax = :-;-----'-""7-;'--'-'---------:-c:Vin(min) - Vee(sat) + VF
Where: Vee (sat) = 1.5 V
VF = Catch diode forward drop
The maximum inductor value is then calculated:
L max = (Vin(min) - Vee(sat) -. Vout) . D max
2 . lout(max) . f(mln)
where:
f(min) 20KHz to be out of the audible range.
In discontinuous mode operation, the inductor
current may reach very high peaks (lPeak = 2Iout),
so it is important to verify that the coil will not
saturate in overload or short circuit conditions damaging the output power stage due to the high
dl/dt ratio.
Therefore, a correct dimensioning requires a
saturation current above the maximum current
limit threshold (12max - peak = 6A).
--------------------------~~~~~~T:9~
408
--------------------------
APPLICATION NOTE
3. Output Capacitor Selection:
The output voltage ripple depends on the current
ripple in the inductor and on the performance of
the output capacitor at the switching frequency
.The minimum value of the output filter capacitor
is obtained from:
lout(max)
Cout(min) = -:--:-:-""",""""'''''--:-:4 . Vripple(p--p) . fmin
where Vripple(p-p) is the amount of ripple voltage
desired.
Clearly this formula doesn't take care of the capacitor Equivalent Series Resistance (ESR) value,
that is the dominant factor to define the output
ripple voltage at switching frequencies greater
than 20KHz.
So we suggest to use also the following formula:
ESR(max) = Vripple(p-p)
2 . lout(max)
Where the ESR(max) requirement is not satisfied
by the capacitor value given by the first formula,
use an higher value or, better, put in parallel several capacitors in order to reduce the total ESR.
The capacitors' voltage rating should be at least
1.25 times greater than the given output voltage.
The big advantage of this system is to greatly reduce number of external components compared
to the continuous mode solution.
The only drawback is a higher ripple voltage on
the output that can be up three times larger than
in continuous mode.
A proper choice of low ESR filtering capacitors
can solve this problem greatly reducing the output
ripple.
4. CATCH DIODE SELECTION:
The catch diode must comply with several requirements and its choice requires special care.
The current rating must be at least 1.2 times
greater respect the maximum load current, but
this is not enough because in short circuit conditions, the maximum current limiter threshold is 6A
to which correspond an average output current of
lout = Ipeak/2 = 3A. This is the current requirement to useto choose the right diode.
The reverse voltage rating of the diode should be
at least 1.25 times the maximum input voltage.
The diode recovery speed is not so important because the power stage is turned-on only when the
inductor is fully discharged and the diode is definitely off. So there is not simultaneous conduction
between them.
This allows a reduction of the disturbances with
respect to the continuous mode, because they
are mainly radiated during the transistor switch
on, for the steep slopes during the simultaneous
conduction of transistor and reverse conductiondiode.
LOW COST APPLICATION
If the remote inhibit, the reset and the power fail
functions are not used we can reduce further the
external component count.
It is possible in this case, to have a very efficientswitch mode power supply for very low cost applications.
Two examples of minimal component count regulators are shown in fig.21 and fig.22.
Figure 21: A Minimal 5.1 Fixed Regulator - Very Few Components are Required
lJi
12
1000uF
501J
L4963
16
18 4.5.6
1uF
5131J
13.14.15
51K
Rose
GND
GND
(*1 COUT-1888uF WITH LOW ESR
-----------------------------
f192f1N458-tt
~~~~~~~~:~~n
-----------------------------
15/17
409
APPLICATION NOTE
Figure 22: A Minimal Components count for Vo = 12V
Ui
49uH
11
HH39u
L4963
16
50U
Uo
:1-
18 4.5.6
13.14.15
51K
Rose
GND
GND
ff91L4963-32
(*l COUT.1SBSuF WITH LOW ESR
the two outputs, we can reduce the number of the
auxiliary turns improving also the tolerance of the
secondary output using the configuration illustrated in fig.24.
For both this configurations, the discontinuous
mode is ideal because we have a good energy
transfer between primary and secondary windinngs, due to the high energy stored in the coil that is
function of the ripple current in the inductor.
DUAL OUTPUT POWER SUPPLY
The application shown in fig.23 is interesting b?cause it provides two output voltages. The main
voltage, is directly controlled by the feedback
loop, the second voltage is obtained throu~h an
auxiliary winding. As the auxiliary voltag.e I~ o~
tained through a completely separated winding, It
is possible to obtain either a positive or a negative
voltage. Where isolation is not required between
Figure 23: Multioutput isolated.
~
Ui
1BBBu
5BU
11
16
1
3
L4963
2
12
0
1N5822
o
1II1II
n1
+1~F
Uo2-12U/B.1A
Uo1-SU/1.SA
13.14.15
0:
51K
GND
ff9211N458-12
n2
Uo2.Uol 0 nl
GND
Po2~2B%Pol
16/17
~
- - - - - - - - - - - - - - ....."
410
SGS·mOMSON _ _ _ _ _ _ _ _ _ _ _ __
i'lAJU©rnl@~~~©1l~@II!U©il\
APPLICATION NOTE
Figure 24: Multioutput not isolated.
r---~--~---oU02.12U/9.1A
Ui
1888u
58U
Hl8uF
11
16
1
3
L4963
2 I-.....-.,ry-v-..~.......---o Uo 1 • 5U / 1. 5A
12
51K
GND
n1+n2
U02.Uo1
n1
GND
119211N45B-13
P02~28"P01
L4963 IN OFF-LINE POWER SUPPLV
The L4963 can be useful as post regulator in offline power supplies, where it can sobstitute the
usual linear post regulation increasing the efficiency and reducing the complexity of the transform8r, if the distributed power supply approach is
used (see fig.2S).
Figure 25: Typical off-line solution using L4963 as post regulator.
1K
49uH
2
L 4963
Uo.SU/1.SA
121-+----J
BVI.J9B
1999uF
16U
N92RN45B-f4
- - - - - - - - - - - - - - £;j ~~~gr::L!l~::
GND
--------------
17/17
411
APPLICATION NOTE
INTRODUCTION TO A 10A MONOLITHIC SWITCHING
REGULATOR IN MULTIPOWER-BCD TECHNOLOGY
byC.Diazzi
The L497X series of high current switching regulator ICs exploit Multipower-BCD technology to
achieve very high output currents with low power dissipation - up to 10A in the Multiwatt power
package and 3.5A in a DIP package.
can deliver to the load. The devices rated at 2A
and 3.5A are assembled in Power Dip (16+2+2),
while the others are assembled in the Multiwatt15
package. Each device integrates a DMOS output
power stage, a control section, limiting current
and supervisor functions like Reset and Power
Fail signal for microprocessors applications.
Output voltage can be adjusted starting from the
internal reference voltage (5.1 V) up t~ 40V, allowing a maximum output power of BOW for the 2A
version and of 400W for the lOA version. Maximum operating supply voltage is 55V.
Switched mode techniques led to the development of high efficiency circuits offering space saving and a reduction in costs, mainly of the heatsink and output LC filter. For these applications a
new technology, called MULTIPOWER-BCD, has
been developed which allows the integration on
the same chip of isolated power DMOS elements,
Bipolar transistors and CMOS logic.
The technology is particularly suitable for the
problems rising in the switch mode field, due to
the characteristics of high efficiency, fast switching speed, no secondary breakdown of the power
DMOS element.
The great flexibility that we have at our disposal
for the choice of the signal and driving sections
components allows optimization and compactness of the system. With MULTIPOWER-BCD it
has been possible to implement the family L497X,
a new series of fully integrated switching regulators suitable for DC-DC converters working in
Buck configuration. The complete family consists
of five devices which differ each other only by the
output current value (2A, 3.5A, 5A, 7A, lOA) they
THE TECHNOLOGY
The technology architecture is based on the vertical DMOS silicon gate process that allows a
channel length of 1.5 micron ; using a junction
isolation technique it has been possible to mix on
the same chip Bipolar and CMOS transistors
along with the DMOS power components (Fig. 2).
Figure 1 shows how this process brings a rapid
increase in power IC complexity compared to
conventional bipolar technology.
Figure 1: BCD process and increase in power ICs complexity.
Complexity (Nr.of tr.)
1~~~-.~---.-----.-----r-----.--~~----,
.....
....
-;'CD IA-D-P)
...........
Pur. an log
Power blp
1965
1970
1975
1980
1985
1990
1995
2000
Years
AN487/0592
1/11
413
APPLICATION NOTE
Figure 2: Cross section of the BCD mixed technology.
S GO
o
S GO
SGD DGS
' -_ _----'I LI_ _ _ _---'1 L--.J I
HV P-CH
VDMOS
P-CH
HV CAP
In the 70's class B circuits and DC circuits
allowed output power in the range of 70W. By
1980 ,with the introduction of switching techniques in power ICs, .output powers up to 200W
were reached ; with BCD technology the output
power increased up to 400W.
FUNCTIONS AND BLOCK DIAGRAM
The complete block diagram of the high power
L4970A is shown in fig.3. Each block is analysed
in the following.
BE C
N-CH
BeE
I LI_ _---' L-.,--_ _ _- '
C-MOS
NPN
LPNP
POWER SUPPLY
The device is provided with an internal stabilized
power supply ( Vstart =12V ). that provides the
supply voltage to the analog and digital control
blocks and also the supply voltage to the bootstrap section. The Vstart voltage .supplies als~ the
internal Reference Voltage section that proVides
accurate 5.1 V voltage to the control loop.
Through trimming techniques the 5.1 V reference
is within +- 2% limits.
OSCILLATOR and FEDFORWARD
The oscillator block (fig.4) generates the sawtooth
Figure 3: Block diagram of the 10A monolithic regulator L4970A.
VREF VSTART Vi
SYNC
o-r1:-::3: - - - - - ,
14
15
9
Rase
~'-----+-t-'""VV'T"'"
V fa edb
Va
o-+::::rt.-
COMPo
L4970A
2_1_1_1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~~~~~~~~:~~n
414
_________________
APPLICATION NOTE
Figure 4: Oscillator circuit.
ucco----...,--,
Rose
..-I
~
Case
PWM
COMPo
CLOCK
fl92L49?8-4?
Figure 5: Voltage Feeforward waveform.
U2
----~----~----~----~--Ui-38U
..
--~~--~~--~~--~~--Ui=15U
Ue
LJ--H-+-H---l--++--I--H-+--+
U7
t
'+I---if-- U i
...-~-t--
'---'--+
fl91L49?8-8?
waveform that sets the switching frequency of the
system. The signal, compared with the output
voltage of the error amplifier, generates the PWM
signal to be sent to the power output stage. The
oscillator features a voltage feed-forward technique which is completely integrated and doesn't
require any external component. Feed-forward
function works in the supply voltage range 1545V. The rate of increase of the sawtooth wavwform is directly proportional to the input volt~ge
Vcc. As Vcc increases, the output pulse-width
(transistor on-time) decreases in such a manner
as to provide a constant "volt-second' product to
the inductance(fig.5).
From fig.5 it is shown that the duty cycle changes
due to the ramp increase when Vcc increases.
The error amplifier output doesn't have to change
to keep the loop in regulation. This feature in~
= 38U
Ui .15U
t
creases significantly the line regulation performance.
A resistor, between Rosc and GND , defines a
current that is mirrored internally to charge the oscillator capacitor on the Cosc pin. The voltag~ at
pin.Rosc is a function of Vcc value .for the .Implementation of the feed-forward function (oscllI~
tor slope proportional to Vcc). A comp~rator IS
sensing the voltage across Cosc capacitor and
discarge it when the ramp exceedes an upper
threshold proportional to Vcc f.or the implemen~a
tion of the feed-forward function. The Cosc discharge current is internally controlled at a value of
about 20 mA. The lower threshold of the comparator is about 1.3V (2VBE). Here are reported
basic equations for the oscillator:
Vce - 9VSE
leHARGE =
for 15VsVees45V (1)
Rose.
3/11
SIiS·THOMSON _ _ _ _ _ _ _ _ _ _ _ _
_
- - - - - - - - - - - - - - - - - - - - - - - - - - - .... , / 1iIl~l<:iR@~~~i:'ITIil@Ill~I<:~
415
APPLICATION NOTE
IDISCH == 20mA
(2)
VTH.HIGH -- Vcc -9 9VBE + 2VBE for 15V s;
~Vcc s;
45V
VTH. LOW = 2VBE
(3)
(4)
9
FSWITCH == R
C
(5)
.
osc. osc.
Note that formula (5) does not take in account the
discharge time of Case, that is not negletable
working at high FSWITCH (200 KHz), and that is
dependent on Case value.
( VTH.HIGH - VTH.LOW ) . Case.
T DISCH. =
20mA
(6)
By which:
FSWITCH =
as soon as the error amplifier output voltage
crosses the ramp; the power stage starts to
switch with steadily increasing duty cycle (fig.9).
The eharge of the soft-start capacitor is started
every time the system begins to work after an
anomalous condition occurred (undervoltage and
thermal protection). The Css discharge current is
in the range of about 20mA.
Figure 6: Switching frequency vs. Rose
(L4970A/77 Al75A).
!19JL 4978-42
fSlJ
1KHz)
C9·nF
588
2G8
Rose Case T
9
+ DISCH
(7)
During the discharge time of Cosc a clock pulse is
generated that is available on pin.SYNC and that
can be used to synchronize max 3 devices of the
same family. See also fig. 6 and fig. 7 for the
switching frequency versus value of R4 (Rose).
18B
50
20
18
18
PWM
The· comparison between oscillator sawtooth and
error amplifier output generates the PWM signal
that feeds the driving stages. A PWM latch structure is implemented to avoid multiple pulses that
could be dangerous for the power stage. A maximum duty cycle limitation is implemented in the
PWM stage. Such limitation is obtained by the
synchronization pulse 'generated in the oscillator
section during the Cosc discharge time. When the
pulse is present the driver is inhibited. In this way
even if the error amplifier output completely overcomes the oscillator sawtooth, the power stage
can not work in DC conditions, but is switched off
during the clock pulse allowing a maximum duty
cycle tipically in the range 90 - 95 %
SOFT START
Soft start (see fig.S) is an essential function for
correct start-up and to obtain a monotonically increasing output voltage, without overstressing the
output power stage. Soft start operates at the
start-up of the system and after the intervention of
thermal protection. The function is realized
through a capacitor connected to soft start pin,
which is charged at constant current(about
100uA) up to a value of about 7V.
During the charging time. , through PNP transistor
01 the voltage at the output of the transconductance amplifier is forced to increase with the same
rising speed of Css capacitor. As the capacitor is
charged, the PWM signal begins to be generated
416
28
38
48
58
Figure 7: Switching frequency
(L4972A174A).
58
R4IK)
78
vs. Rose
t191L49?2
fSlJ
1?
I
C9.nF
1KHz)
5GG
28G
1GB
I'--.. ::::
~;;I'....
~
58
l'
1.2nF
r-I
--
............... ~.5nF
...............
~
4.~
28
2.2nF
1-1
3.3nF
1B
18
28
30
48
58
68
70
R4IK)
APPLICATION NOTE
Figure 8: Soft start circuit.
Iss
UNOERUOLTAGE
PROT.
TRANSC.
ERROR AMPL.
1
:1>-i
PWM
COMPo
~--~r-------~Q1
THERMAL PROT.
Css ~
f/92L4!1?8-4811
Figure 9: Soft start waveforms.
CLAMPED
ERROR AMPLIFIER
OUTPUT
- - - - - -.r!.~---7f-I---:.H-
t
OUTPUT
CURRENT
t
SOFT START TIME
f151L45?B-BB
Figure 10: Error amplifier circuit.
2.SK
18K
1
~---t::
4
TO PWM
COMPo
5/11
----------------------------- ~~~~~~~~:~~~ ----------------------------417
APPLICATION NOTE
UNDERVOLTAGELOCKOUT
The chip features a complete built-in under voltage lock out protection, keeps the power output
stage off up to the moment Vcc reaches 11 v, with
an hysteresis of 1V. After reaching the 11 V value
the system starts with the soft start feature.
ERROR AMPLIFIER
The error amplifier is a transconductance Operational Amplifier featuring a current output. The
simplified schematic is represented in fig.1 O.
The basic characteristics of the uncompensated
operational amplifier are the following:
- GM = 4mAJV,
- Ro = 2.5Mohm,
- Avo =80dB,
- Isource/sink = 200f1A
- Iinput Bias Current = O.3f1A
The frequency behavior of the uncompensated
amplifier is reported in fig.11.
by which
Ro
Av(s) = GM . 1 + SRo Co
where Co = 3pF.
The error amplifier is inserted in the regulation
loop and can be easily compensated, thanks to its
high output impedance, with a network between
its output and ground. The typical compensated
network is shown in fig.13.
Figure 13: Compensation network of the error
amplifier.
AMP.
Rc
:::c
Cc
n92L.f9?B-58
Figure 11: Open loop gain (error amplifier only).
The transfer function is:
A
) G
v (8 ~ M'
Av(dBl
RD (1 + S Re Ce)
s2 RD CD Re Ce + S (RD Ce+ RD CD + Re Ce) + 1
In the hypoteSis that RcCo, the
Bode diagram of the compensated amplifier is reported (see fig.14).
88 -1----;..
Figure 14: Bode plot showing gain and phase of
compensated error amplifier.
48
Gv
UNCOMPENSATED
(dB)
f
f192L49?B-5B
Neglecting the high frequency behav.ior (in the hypotesis that in the overall frequency compensation of the loop the second pole of the operational
amplifier is far below the 0 dB axis), we can make
a first order approx. by which the error amplifier
can be schematized by the equivalent circuit of
fig.12.
~~---k----~----~-------135
~------+----~~---+-~----- 98
2TTRoCc
2TTRcCc
2TTRoCo
2TTRcCo
1192L49?IJ-S9
Figure 12: Error amplifier equivalent circuit.
v+
----0
v - --;;;L.
6/11
f192L49?fJ-5!
The compensation network introduces a low frequency pole and a zero that usually is put at the
frequency of the resonant pole of the output LC
filter. The second high frequency pole is usually
at a frequency of no interest. If needed , more
sophisticated compensation circuits can be used
by feedback with the opamp. An example is
shown in fig.15.
----------------------------- ~~~~~~~~:~~ ----------------------------418
APPLICATION NOTE
Figure 15: One pole, two zero compensation
network.
C2
Figure 17: Block diagram used in stability
calculation.
~UREF
I
APPLICATION EXAMPLE
Consider the block diagram of fig.17, representing
the internal control loop section, with the application values:
Fswitch = 200KHz, L = 100~H, C =1 OOO~F,
Po=50W, Vo =5.1V, 10 =10A and Fo = 500Hz.
Gloop = PWM . Filter
N!J2L4!J?B-52
typ.
Such a configuration introduces a low frequency
pole and two zeros Z1 = 1/2TIR1C1 and Z2 =
1/20R2C2. Note that due to the high output impedance it is present also a second pole p2 =
gm/2TIC1. Usually it is better to use the highest
possible value for R1, to have a low value for C1
in such a way to put p2 at the highest frequency.
Limitations to R1 value are put by offset voltage
due to opamp. input bias currents.
If a resistive divider is used at the output of the
power supply, for voltages higher than 5.1 V, it is
possible to introduce a second zero with the network of fig.16.
12
!
UREF •
Uf
1192L.t97B~5.tn
Figure 18: Frequency behavior of the circuit of
fig 17.
dB Io-1I3A
Figure 16: Compensation network for output
voltages higherthan 51 V.
Uo
/f92L497B-S5
C1
Rc
J:
Cc
1192L49;'8-53
Such a configuration introduce 2 zeros at:
1
Z1 = 2TI Re Ce ;
The system requires that DC gain is maximum to
achieve good accuracy and line rejection. Beyond
this a bandwidth of some KHz is usually required
for a good load transient response. The error amplifier transfer function must guarantee the above
constraints. A compensation network that could
be used is shown in fig.19.
A
( 1. + SR1 C1 ) (1 + SR2 C2 )
C1
(s) =
SR1 C1 ( 1 + s GM)
Figure 19: Compensation network.
1
Z2 = 2TI R1 C1
and 2 poles at:
P
1
P2 =
1
. Rx = R1 R2
1 = 20 RaCe;
2TI Rx C1 '
R1 + R2
~ SGS·lltOMSON
- - - - - - - - - - - - - - A."'!I
Wlu!:Iffi@~~rn~mru@lI!lu~$
7/11
--------------
419
APPLICATION NOTE
Figure 20: Bode plot of the regulation loop with the compensation network of fig. 19.
.
dB
.
•
49
ACSJ
....~..
Gloop
"
,
"j""........- ""...
PWMtFIL TRO
".
--',<:.~"~
58Hz
.
588Hz
The criterium is to define Z1, Z2 close to the resonant pole of the output LC filter. The Gm/2DC1
pole must be placed at a frequency at which open
loop gain is below 0 dB axis (Fig. 20).
CURRENT LIMITATION
Current limitation is implemented intrnally to the
chip and doesn't need any external component.
.......... .
58Kz
The output current is sensed by an internal resistor in series with the drain of the power transistor.
On chip trimming guarantees ± 10% accuracy on
the value of peak current limitation.
Current limit protection works pulse by pulse with
lowering of tnhe switching frequency. Fig.21
shows circuital implementation of current protection.
Figure 21: Current protection circuit.
--~-----+------~Ucc
Rs
S
POWER
TRANSISTOR
MASTER
CLOCK
Q
TO SWITCH OFF
POWER STAGE
R
JlJl
8/11
- - - - - - - - - - - - Gi'l
SCiS-TlfOMSON
• J,
~~©U1@rn~rnC1fUl@Il!U©@
420
11!12U!l78-56
1192L4978-57
APPLICATION NOTE
When the comparator senses an overcurrent, the
flip-flop is set and an internal inhibit signal is
generated. The flip-flop remains set until next
reset clock pulse coming from the internal 40 KHz
oscillator. After the reset pulse the regulation loop
takes the control of the system and the output
current begins to increase to the load value at the
switching frequency of the master clock. If the
overload condition is still present the protection
cycle repeats. This mixed, pulse by pulse, lowering frequency current protection method, assures
a constant current output when the system is in
overload or short circuit and allows to implement
a reliable current limitation even at high switching
frequency (500 KHz) reducing the problems of
signal delay through the protection stage. Fig.22
shows behavior of the inductance current when
the system is in overload.
Figure 22: Overload inductance current.
The internal 40 KHz oscillator is synchronized
with the master clock. When the system works
with the master clock at a lower frequency of the
internal clock, than the internal clock tracks the
master frequency. This assures that the frequency does not increas during overload.
POWER FAIL-RESET CIRCUIT
The L4970A include a voltage sensing circuit that
may be used to generate a power on power off
reset signal for a microprocessor system. The circuit senses the input supply voltage and the output generated voltage and will generate the required reset signal only when both the sensed
voltages have reached the required value for correct system operation. The Reset signal is generated after a delay time programmable by an external capacitor on the delay pin. Fig. 23 shows
the circuit implementation of Reset circuit. The
supply voltage is sensed on an external pin, for
programmability of the threshold, by a first comparator. The second comparator has the reference threshold set at slightly less the ref. voltage
for the regulation circuit and the other input connected internally at the feedback point on the
error amplifier. This allows to sense the output
regulated Voltage. When both the supply voltage
and the regulated voltage are in the correct
range, transistor Ql turns off and allows the current generator to charge the delay capacitor.
When the capacitor voltage reaches 5V the output Reset signal is generated. A latch assures
that if a spike js present on the sensed voltage
the delay capacitor discharges completely before
initialization of a new Reset cycle. The output
gate assures immediate take of reset signal with-
Figure 23: Power fail and reset circuit.
o
R~Ji'~~__________~
----------------~------------ ~~~~~~~~:oo~n
5V
-----------------------------9/11
421
APPLICATION NOTE
Figure 24: Reset and power fail waveforms.
RISINIiz P. FAIL
THRESHOLD
TURN-ON
THRESH.
,t
5.1V
lOOmV
H1----HfSTERESIS
RESET
OUT
to
DELAY RESET
POWER FAIL TIME
out waiting for complete discharge of delay capacitor. Reset output is an open collector transistor
capable of sinking 20mA at 200m V voltage.Flg.
24 shows reset waveforms.
THE POWER STAGE
A simplified schematic of the output ,stage alo~g
with the external filter components IS shown In
fig.25.
Power stage and associated driving circuits are
among the most critical components to achieve
good performances at 'high switching frequency.
An external bootstrap capacitance, charged via
diode 01 at 12V, is needed to provide the com~ct
gate drive to the power OMOS N-channel transIstor. The driving circuit is able to deliver a current
peak of O.5A, during turn on and turn off phases,
to the gate of power OMOS transistor. The circuitdescribed shows commutation times of 50ns.
Figure 25: Power stage circuit.
~--+-------------------------~----~ Vee
REF.
12U
VOLTAGE
D1
~
C BOOTSTRAP
FROM
PWM COMPo
J1JL
L49?B
10/11
422
l:W ~~~~!tl~::~y~~ ------------------
APPLICATION NOTE
The five devices of L497X family differentiate
each other only for the level of current protection,
while the control part is the same and power device area is the same to guarantee low power
dissipation also for low current versions in DIP
package.
Table 1 and fig.26 shows electrical characteristics
of the power DMOS implemented in the chip.
Figure 26: Gate-charge curve for the power
DMOS.
1189L49?8·36
Ugs
UDSo4GU
I U)
// /
/
12
// ~
113
THERMAL PROTECTION
The thermal protection function operates when
the junction temperature reaches 150°C; it acts
directly on the power soft start capacitor, discharging it. The thermal protection is provided
with hysteresis and therefore, after an intervention has occurred, it is necessary to wait for the
junction temperature to decrease of about 30 degree C below the intervention threshold.
// ~
8
6
lGA
SA
4
2
/
/
~~
V'
1A
8
16
24
DglnC)
Table 1.
Bvoss > 60V
at 10 = lmA
ROSION) = 100mQ
at 10= lOA
Tj = 25°C
VGs= tOV
ROSION) = l50mQ
at 10 = lOA
Tj = 150'C
VGs= 10V
VTH = 3V
at 10 = lmA
VGS= OV
423
APPLICATION NOTE
SIMPLIFIED SWITCH-MODE BASE DRIVE CIRCUIT
WITH THE L4974 SMARTPOWER-IC
By Klaus RISCHMUllER
INTRODUCTION
internally - it can be supplied from a single, unregulated source.
Conventional driver circuits for bipolar-junction-transistors and Darlingtons have a high power dissipation. In order to reduce this dissipation, switch-mode
driver stages have been proposed 1. A new, very
simplified driver stage, taking advantage of the
switch-mode principle is presented here. It has been
designed around smartpower-IC L4974. The efficiency of the IC is so high, that even with a 4 Amp
base-current, the smartpower device is housed in a
DIL-package ... !
Bipolar-junction-transistors need negative bias in
order to obtain fast turn-off switching and a good immunity against reverse conduction followed by
dv/dt. This driver circuit generates the negative bias
The new configuration can be used to simplify and
improve existing converter/inverter circuits (less auxiliary supplies, less heats inks and higher efficiency).
CONVENTIONAL BASE DRIVE VIS S\AfITCHMODE BASE DRIVE
Conventional base driver circuits draw base current
from an auxiliary supply voltage between 6 to 12 Volts.
The base-current amplitude is limited by means of resistors or dissipative current sources. (figure 1) Such
a base driver has a very low efficiency. The power
transistors base-emitter voltage is about 1V, but 5V to
Figure 1 : Dissipative Driver Circuit.
Tr.
Vaux
6 ... 12V
]
4A
---r
.
IVUlMJl
CJ-
Tp
l_~~_
SC-l024
During permanent conduction with a 4A-base-current, the transformer Trs has to supply a power
of 56W. About 90% of this power is dissipated in the driver circuit.
\N36410689
114
425
APPLICATION NOTE
11 V are dropped inside the driver circuit. Applying the
switch-mode·principle to base driver circuits, substantial energy savings can be made. Auxiliary power supply and heatsinking costs can be greatly reduced.
circuit to the output of the buck regulator. Thus, the
smartpower IC operates with reduced duty cycle
and maintains a constant current in the choke L. In
order to tum-on power transistor TP, the MOSFET
T1 is turned off and the constant choke-current flows
into the power transistors base. The rate of rise of
base current is only limited by the MOSFET turn-off
speed. In order to obtain very fast switching, high
density MOSFETs (STVHD 90) with very low input
capacitances have been used in the circuii.
HOW IT WORKS
Figure 2 shows the principle of such a switch mode
driver circuit. A smartpower-IC with a MOSFET output-stage operates as a buck regulator in currentmode. During the off-state of the power transistor,
TP - figures 1-4., a MOSFET, T1, applies a short-
Figure 2 : Simplified Switch Mode Driver Circuit.
Tr.
Vaux
leI
20. 40V r - - - - - ,
:Il~
I
I
I
1
I
I
I
I
I
ff
I
1
I
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L,_~
DZ
3.GV
ON
n OFF
_I
L
()-,---4------------'
sc- '015
With an input voltage of 20V and a base current of 4A, the transformer supplies about 1OW to
the driver circuit. No device in the driver circuit has to be cooled with a heatsink.
During the on-state, the driver circuit input current
can be estimated using the term 2 • IB * VBElVaux,
where IB is the base current, VBE the base-emitter
voltage and Vaux the voltage of the auxiliary supply.
If the power transistor base·current is 0.5A. and the
auxiliary supply voltage 20 Volts, the driver input
current will be about 0.5 Amps. If the auxiliary supply voltage is increased, the input current will be further reduced.
NEGATIVE; BIAS OUT OF POSITIVE SUPPLY
The negative bias for fast turn-off switching can be
generated by various means.
A zener diode can be connected in series between
auxiliary supply and driver stage, Oz (figure 2). The
potential at the zener diode anode is negative compared to the emitter potential of the power transistor.
The losses in the zener diode are low, due to the re2/4
426
duced input current of the switch-mode base drive.
For turn-off switching, T1 and T2 are turned on. T1
applies a short circuit to the buck regulator output, T2
applies the negative bias to the power-transistor base.
It is also possible to generate a negative bias directly from positive auxiliary supply:
A capacitor C1 (figure 3) is permanently charged via
a resistor R1 and a diode 01. At turn-off switching,
T2 is turned on for a short time t1 . This time has to
be chosen to have a value slightly higher than power
transistor's storage-timets. T2 connects the positive
electrode of C1 to ground during t1. Thus a negative voltage is applied .to ·the base during turn-off
switching off TP. T2 remains' 'off' after turn-off and
C1 continues to be charged. The advantage of this
configuration is that the state of charge of C1 is independant of du1!' cycle - sufficient negative bias is
always available .
APPLICATION NOTE
Figure 3 : Modified Circuit with Dynamic Self-generation of the Negative Bias.
Tr.
3300
]
r------,
+--1f-TI-<;>-,
I
I
I
I
I
I
1
I
1
1
1
1
1
1
1
Tp
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.
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1 4148
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1-.
+---.-----<>---1-- - - ----t---"---+--~
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OFF
ONJL
sc- 1026
SL
I I
3ys
The capacitor C1 is charged during the conduction and the non-conduction time of TP.
Its state of charge is independant of the duty-cycle!
Figure 4: Complete Circuit Diagram for 4 Amp Base Current Supply.
.----..----BYn3 - 1000
Tr.
-j
~
2 :.""
~"~~V
.---1\1
1
1
L4974
Tp
1000
sc -1027
The L4974 is housed in a Dual-in-Iine package - the PCB is sufficient for
cooling. For higher base current, L4974 can be replaced by L4970.
3/4
427
APPLICATION NOTE
RESULTS
With a BUF 420 (a cellular ETD-transistor) in the
power stage, storage-times less than 111S and falltimes lower than 25ns have been obtained when
switching 20A, from a 400V supply.
The overshoot of the base-emitter voltage and the
influence of parasitic inductances in series with the
base are negligible due to the fact that the driver
acts, at turn'on, as a nearly ideal current source. A
turn-on speed dlddt for the power transistor as high
as 200A/I1s has been obtained without any special
design effort.
CONCLUSION
The application of the switch-mode principle to
driver stages gives significant loss reduction and a
very much reduced cost for auxiliary supply and
heatsinking. In the past switch-mode driver circuits
were considered as too complex. New smartpowerIC's allow a reduction in complexity and take advantage of the high efficiency achievable using a switch
4/4
428
mode circuit. The 4A-version of the driver uses a
Dual-in-line IC and no heatsinks. The combination
of switch-mode principle with self generation of negative bias further reduces cost of the driver and its
auxiliary supply. The concept shown appears to be
valid for base currents up to 20 Amps; its use for
gate drive for SeR and GTO could also be investigated.
1. C.K. Patni : An efficient "Switch-mode" base drive
for bipolar transistors, Internal report, SGS-THOMSON Microelectronics
2. Databook : POWER MOS DEVICES page 621 to
625 (STVHD 90), SGS-THOMSON Microelectronics
3. K. Rischmuller : Fast switching with power transistors and Dariingtons - state of the art, Application
note, SGS-THOMSON Microelectronics
4. Databook : Industrial and computer peripheral
IC's, page 401 to 416 (L4970), SGS-THOMSON
Microelectron ics.
~
L
Ii..,
SGS-1HOMSON
[j\Jj]O©OO@~!L~©'j]'OO@!RllO©~
APPLICATION NOTE
ULTRA FAST NiCd BATTERY CHARGING
USING ST621 0 MICROCONTROLLER
L. Wuidart, P. Richter
INTRODUCTION
Today many cordless and portable equipments are
supplied by a Nickel-Cadmium (NiCd) battery. The
ultra fast charging of these batteries in less than half
an hour is a very attractive service for users. Such
a short charging time requires an "Ultra Fast" battery, a supply with a relatively high output power,
and a charge control circuit more complex than for
standard chargers. Moreover, automatic battery
voltage identification is an appreciable feature.
The power converter proposed in this note is able
to fully charge a common NiCd battery pack of
1.2Ah/7.2V within 15 minutes. The power converter
has thus a corresponding output power capability
of roughly 80W. The converter operates as a current
source providing a constant 7A current to the battery while charging.
The battery charge is controlled by an economical
microcontroller, the ST6210, a member of the ST6
microcontroller family. The programmed control
provided by the ST621 0 allows the charging of NiCd
battery packs from 2 to 6 cells (2.4V to 7.2V). The
supply to the microcontroller is simply generated
from an auxiljary winding of the power transformer.
THE POWER CONVERTER
The asymmetrical half-bridge is today considered
as one of the most attractive topologies for the
primary side of a 220Vac off-line Switch Mode
AN433/0292
Power Supply (SMPS, see Figure 1). Adding the
SGS-THOMSON AVS10 kit allows the automatic
sensing and adaption to input voltages in the range
of 90 to 240Vac.
Contrary to single switch structures, the leakage
inductance of the power transformer is much less
critical. The two demagnetization diodes
(BYT01/400) provide a simple non-dissipative way
to systematically clamp the voltage across the
switches to the input DC voltage Yin. This allows
the use of standard 500V power MOSFET devices,
such as the IRF830FI (in isolated ISOWATT 220
package), simply driven by a small pulse transformer.
The power converter is totally controlled from the
primary side with a standard Pulse Width Modulation (PWM) control IC, the UC3845 regulating in
current mode. A single optocoupler makes this
SMPS operate as a battery charger. The SMPS is
turned on or off from the secondary by the ST621 0
microcontroller via this optocoupler.
The switching frequency is fixed at 100kHz in order
to keep the magnetic part to a reasonable manufacturing cost level. The power transformer and the
output inductor can be integrated on a single ferrite
core [4]. This integrated magnetic technique can be
optimised to allow a Significant shrinking of the
power converter size.
For more information on the power converter, refer
to reference [4] of the bibliography.
1/6
429
APPLICATION NOTE
Figure 1. Ultra Fast NiCd battery charger schematic
_2/_6 _ _ _ _ _ _ _ _ _ _ _
430
f;i
~~@m~~'9~
------------
APPLICATION NOTE
BATIERY CHARGE CONTROL
Ultra Fast Charge Control Method
For Ultra fast charge systems - under half an hour
- the majority of battery manufacturers recommend
the negative delta voltage method (-/,,v) otherwise
called the negative slope cut-off circuit [2] [3].
When a NiCd battery reaches full charge, its voltage
decreases slightly (Figure 2). The negative delta
voltage method (-/,,v) consists of stopping the
charge as soon as the voltage characteristic slope
becomes negative. This technique allows the very
rapid charge of a NiCd battery, near to its full
capacity. Moreover, no compensation for the age of
the battery is required because only relative voltages are measured.
In this application, the battery voltage is sensed by
a ST621 0 microcontroller housed in 20 pin dual in
line package. The integrated Analog to Digital converter (ADC) of this micro-controller is able to detect
a typical voltage drop of -10mV/cell.
MONITORING FUNCTIONS
The battery charge is totally monitored by the HCMOS ST6210 in PDIP or PSO 20 pin package, the
ST6210. By using this micro-controller, additional
monitoring functions can be easily added to the
Ultra fast charge control program.
Stand-by current charge: Burst mode
Once the negative voltage drop has been detected
by the ST6210, the ultra-fast charging is stopped
and the power converter supplies the battery with a
stand-by current around 170mA. This stand-by
charge is provided by burst mode current control.
The converter is successively turned on and off at
25Hz with a small duty cycle of 0.025. The ST621 0
manages this burst mode from the secondary side
via an optocoupler to the auxiliary supply of the
PWM control IC (UC3845).
A small 100f1F reservoir capacitor is sufficient to
keep the ST621 0 correctly supplied during the off
periods (39ms) of the burst mode. This is possible
due to the low current consumption in run mode of
the ST6210 HCMOS micro-controller (typically
3mA with an 8MHz oscillator, reducing to typically
1mA for a 2MHz oscillator).
Battery temperature protection
Temperature protection is simply realized by using
an NTCresistor placed on the battery pack. This
NTC resistor is directly connected to another input
of the ADC of the ST6210. When the battery
temperature reaches 40'C during an Ultra Fast
charge phase, the converter is switched into burst
mode to protect the battery.
BatterY presence
The ST621 0 program detects whether the battery
pack is connected or not. When the battery is not
connected, the converter is turned into burst mode.
The resulting stand-by current (170mA) flows into
the output Trarisil diode (BZW 50-12).
CHARGE CONTROL PROGRAM DESCRIPTION
Figure 3 shows the main flow chart of the program
for the complete charge control. The overall system
is reset after each new mains connection.
Battery voltage measurement:
The battery voltage is directly measured by the
ST621 0 Analog to Digital Converter through a resistor divider chain. The technique used allows the
ST621 0 to automatically adapt to the battery type
and voltage (from 2 to 6 cells, 2.4V to 7.2V).
Figure 2. One NiCd Cell Charge Characteristic
t
1.6
t------+-----b~::::::s~~t=t-t.v
-10mV/cell
Oi
u
1.4
'0
o
Z
1.3
I
Charging time (I) _ _
VR00160B
____________________________ ~~~~~~~~~~ ___________________________
3/_6
431
APPLICATION NOTE
Figure 3. Main flow chart of the Ultra Fast Charge control program
. - - - - - - - 0 . , , ' BATTERY VOLTAGE MEASUREMENT
YES
NO
NO
YES
1
1
1- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
.- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
STAND-BY CHARGE
NO
YES
NO
YES
1- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,
_______ I
VR001609
_4/_6_ _ _ _ _ _ _ _ _ _ _ _ _
432
~~~~@~~~9©~
_-------------
APPLICATION NOTE
Monitoring principle
The 8T621 0 averages a series of 256 battery voltage measurements (L Mn). The 256 conversions
are made in a time frame of around 19 ms, with an
inter-frame delay time of 0.5s (in this example). An
average AVr of the last 8 averaged values is made
according to the formula:
The response time to detect the battery voltage
drop ranges from 0.5 to 4 seconds, depending on
the slope of the battery voltage curve at the charge
completion. A longer delay time is able to increase
the noise immunity, but at the cost of an extended
response time.
PRACTICAL RESULTS
""" LMn .. 'LMn-B
8
Avr=,L..,
This AVr value is compared to the previous average
AVr-1 and the highest value is stored. This rolling
average value follows the battery voltage curve.
Once the AVr value begins to decrease, indicating
the battery is fully charged, the 8T6210 stops the
Ultra Fast charging.
Tests made with different battery packs confirm that
the battery charge is efficiently controlled by the
8T621 0 using its internal AID converter. Results on
the battery voltage and temperature pack versus
charging time are shown in Fig. 5.
These recordings have been made with a common
1.2Ah/7.2V NiCd battery pack for cordless drills.
The temperature of the battery pack does not exceed 33'C for an ambient temperature of 26'C.
Figure 4: Sequencing principle of the Battery Voltage measurement
256 V BAT
MEASURES
,
,
"
,
T-7\.
,
'" ,
"\
,, ,,,
,,
,,
,
,
" , , ,,,
,, ,,
, ,
""", \,
, ,
-----~
----~
Comparison
ITime•
VR001610
____________________________
~~i~@~~~~~~©~
___________________________5/_6
433
APPLICATION NOTE
Figure 5 . VBAT and Pack. Temp Vs time
Battery pack
35
30
25'
Battery Voltage (V)
9.5
8.5
8
1 2
Charging time (mn)
VR001611
SUMMARY
Charging a.NiCd battery in less than half an hour
saves battery packs and time. It can enlarge the use
of battery powered equipments, especially in
professional applications;
Suc~ ultra fast charging has to be carefully
monitored to maximize the lifetime of the battery
and the charge safety. Moreover, this improvement
needs to be achieved with a compact equipment
including a mil'1imum of components.
The proposed power. charger is realized with a
conventional1?MPS topology. The size and number
of the magnetic comporients are minimized by
using an integrated magnetic technique.
This note shows that an ultra. fast charge can be
totally monitored by a single 20 pin HCMOS microcontroller, the ST6210.
The program used in the, validation of this Battery
Charger is available. from SGS-THOMSON. This
software routine has the basic ultra fast charger and
many additional features including stand-by
charge, temperature· protection, battery presence
detection and automatic battery voltage sensing.
Given the flexibility offered by the programmability
of the ST6210, other specific requirements can be
implemented. Consult your local SGS-THOMSON
sales office or franchised distributor.
REFERENCES
[1] G.E. BLOOM, "CORE SELECTION FOR INTEGRATED-MAGNETIC POWER CONVERTERS", Powertec~lnics Magazine - June
1990.
[2] A. WATSON-SWAGER, "FAST-CHARGE BATTERIES", EON, Dec. 7, 1989.
[3] M. GROSSMAN, "FOCUS ON RECCHARGEABLE BATTERIES: ECONOMIC PORTABLE
POWER", Electronic Design, March 3, 1988.
[4] L. WUIDART, "ULTRA FAST NiCd BATTERY
CHARGER WITH INTEGRATED MAGNETIC",
PCIM - June 1991 - Nurnberg/G
--------------------------- ~~~~~~'~~4 --------------------------6/6
434
APPLICATION NOTE
DESIGNING WITH THE L296 MONOLITHIC
POWER SWITCHING REGULATOR
A cost-effective replacement for costly hybrids, the L296 Power Switching Regulator delivers 4A at an output voltage of 5.1 V to 40V and includes many popular supply features. This comprehensive application guide
explains how the device operates and how it is used. Typical application circuits are also presented.
The SGS THOMSON L296 is the first monolithic
switching regulator in plastic package which includes the power section. Moreover, the circuit includes all the functions which make it specially
suited for microprocessor supply.
Before the introduction of L296, which realizes the
step down configuration, this function was implemented with discrete power components driven
be integrated PWM regulator circuits (giving a maximum output current of 300 to 400mA) or with hybrid
circuits. Both of these solutions are characterized by
a low efficiency of the power transistor. For this reason it is generally necessary to operate at frequenAN244/1288
cies in the 20kHz to 40kHz range. Of the two alternatives discrete solutions are usually less expensive because they do not include as many functions
as the L296.
With the new L296 regulator the driving problem of
the power control stage has been eliminated.
Besides a higher overall efficiency, it is therefore
also possible to operate directly at frequencies as
high as 100kHz. At 200kHz the device still operates
(further reducing the cost of the Land C external
components) when a reduction of a few percent in
efficiency is acceptable.
1/42
435
APPLICATION NOTE
The device delivers a maximum current of 4 A to the
load, at an output voltage adjustable from 5.1 to
40V ; the maximum operating input voltage is 46V.
The high voltage and the high current capabilities of
the device are a result of the special technology
used and the special care taken in designing the
power transistor. Essential requirements for a good
power transistor are high gain and high current levels, low saturation voltage and good second breakdown robustness. To achieve high gain at high
current levels, the power transistor has to be designed to maximize the emitter's perimeter/area
ratio.
In the L296 power transistor, realized with a high
voltage (50V) process, current densities in the magnitude order of 1OmNMil 2 are achieved.
In its most complete configuration, in which all the
available functions are being used, a significant reduction of the external component count is achieved
compared with discrete component solution.
The L296 is mounted in a MULTIWATT® plastic
package with 15 pins, minimizing the cost per watt
and allowing a low thermal resistance of 3°C/W between junction and package and of 35°C/W be-'
tween junction and ambient. This thermal resistance
(inclucing the contact resistance) is comparable to
that of the more costly metal TO-3 packages.
THE STEP-DOWN CONFIGURATION
Fig. 1 shows the simplified block diagram of the circuit realizing the step-down configuration. This circuit operates as follows: 01 acts as a switch at the
frequency f and the ON and OFF times are suitably
. controlled by the pulse width modulator circuit.
When 01 is saturated, energy is absorbed from the
input which is transferred to the output through L.
The emitter voltage of 01, VE, is Vi-Vsat when 0 is
ON and -VF (with VF the forward voltage across the
D diode as indicated) when 01 is OFF. During this
second phase the current circulates again through
Land D. Consequently a rectangular shaped voltage appears on the emitter of 01 and this is then
filtered by the L-C-D network and converted into a
continuous mean value across the capacitor C and
therefore across the load. The current through L
consists of a continuous component, ILOAD, and a
triangular-shaped component super-imposed on it,
~IL, due to the voltage across L.
Figure 1 : The Basic Step-down Switching Regulator Configuration.
c
Dl
1
Vo
Vi
LOAD
ESR
in
5-6776
2/42
436
~ SCiS-THOMSON
...
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(LOAD
APPLICATION NOTE
Figure 2 : Principal Circuit Waveforms of the figure 1 Circuit.
Q,
OFF
I
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ON
'ON
JJ
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I
OFF
'OFF
I.
T
la
Vl
, OFF
o"
-,
..,
Ipeak
-~
b)
..,
~
Jl
a)
.~Lf=
r1 "~r1
Ipeak
10
ON
n1lr--
c)
..,
n_:"~:'OI
d)
~-(VF"VO)
"," --=-
I'"
-
'.0,"
.1
..
f)
Ie
g)
nvc=nQ= nIL
c
Sf[
h)
~ -lJ.VE~
t
..
5-6788
3/42
437
APPLICATION NOTE
Fig. 2 shows the behaviour of the most significant
waveforms, in different points of the circuit, which
help to understand beller the operation of the power
section of the switching regulator. For the sake of
simplicity, the series resistance of the coil has been
neglected. Fig. 2a shows the behaviour of the emitter voltage (which is practically the voltage across
the recirculation diode), where the power saturation
and the forward VF drop across the diode era taken
into account.
The ON and OFF times are established by the following expression :
TON
Va = (Vi - Vsat) T
T
ON + OFF
Fig. 2b shows the current across the switching transistor. The current shape is trapezoidal and the
operation is in continuous mode. At this stage, the
phenomena due to the catch diode, that we consider
as dynamically ideal, are neglected: Fig. 2c shows'
the current circulating in the recirculation diode. The
sum of the currents circulating .in the power and in
the diode is the current Circulating in the coil as
shown in fig. 2e. In balanced conditions the ~IL+current increase occuring during TON has to be equal
to the ~IL- decrease occurring during TOFF. The
mean value of IL corresponds to the charge current.
The current ripple is given by the following formula:
A
+
ulL
A
-
= ulL
=
(Vi - Vsat)-V
L
Va + VF
L
TON--
TOFF
It is a good rule to respect to 10MIN ~ hJ2 relationship, that implies good operation in continuous
mode. When this is not done, the regulator starts
operating in discontinuous mode. This operation is
still safe but variations of the switching frequency
may occur and the output regulation decreases.
Fig. 2d shows the behaviour of the voltage across
coil L In balanced conditions, the mean value of the
voltage across the coil is zero. Fig. 2f shows the current flowing through the capacitor, which is the difference between IL and ILOAD.
In balanced conditions, the mean current is equal to
zero, and ~Ie = ~IL. The current Ie through the capacitor gives rise to the voltage ripple.
This ripple consists of two components :a capacitive component, ~Ve, and a resistive component,
~ VESR, due to the ESR equivalent series resistance
of the capacitor. Fig. 2g shows the capacitive com-
4/42
438
ponent ~Vc of the voltage ripple, which is the integral of a triangular-shaped current as a function of
time. Moreover, it should be observed that ve (t) is
in quadrature with ie(t) and therefore with the voltage VESR. The quantity of charge ~O+ supplied to
the capacitor is given by the area enclosed by the
ABC triangle in fig. 2f :
~Q=~ . ~ . ~IL
2·22
which therefore gives:
~Ve=
.
-
Q
C
~IL
=8fc
Fig. 2h shows the voltage ripple VESR dl,le to the resistive component of the capacitor. This component
is VESR (t) = ie (t) . ESR. Fig. 2i shows the overall
ripple Va, which is the sum of the two previous components. As the frequency increases (> 20kHz),
which is required to reduce both the cost and the
sizes of Land C, the VESR component becomes
dominant. Often it is necessary to use capacitors
with greater capacitance (or more capacitors connected in parallel to limit the value of ESR within the
required level.
We will now examine the stepdown configuration in
more detail, referring to fig. 1 and taking the behaviour shown in fig. 2 into. account.
Starting from the initial conditions, where Q = ON,
ve = Va and iL = iD = 0, using Kirckoff second principle we may write the following expression:
Vi = VL + ve (Vsat is neglected against Vi).
diL
. diL
Vi = L CIt + ve = L ill + Va
(1 )
which gives:
diL
(Vi-Va)
dt = - L -
(2)
The current through the inductance is given by :
IL -
(Vi - Va) t
-
L
(3)
When Vi, Va, and L are constant, IL varies linearly
with t. Therefore, it follows that:
~IL+ _ (Vi - Va) TON
(4)
-
L
When 0 is OFF the current through the coil has
reached its maximum value, Ipeak and because it
cannot very instantaneously, the voltage across the
coil is inverted and the diode 0 becomes forward
biased to allow the recirculation of the current
through the load.
APPLICATION NOTE
When Q switches OFF, the following situation is
present:
vc(t)
=Va, iL (t) =io (t) =Ipeak
And the equation associated to the following loop
may be written :
diL
VF + L dt + Vc = 0
(5)
where:
vc = Va
dlL
Cit = -
(VF + Vo)/L
= _ VF + Va t
L
(7)
Po:
L
TOFF
(9)
if follows that:
(Vi - Va) TON
Va TOFF
losses due to the series resistance Rs of the
coil
PL = Rs 10 2
(15)
losses due to the stand-by current and to the
power driving current:
TON
Pq = Vi 1'3q + Vi 1"3q T
(16)
=-L-
where being:
TON
Vo
which allows us to calculate Va :
Vo = Vi
where VF is the forward voltage of the recirculation
diode at current 10 .
Pq :
But, because
i1IL+ = i1IL-
L
losses due to the recirculation diode. These
losses increase as Vi increases, as in this
case the ON time of the diode is greater.
Vi-Va
Va
Po = VF 10 -V-i- = VF 10 (1 - \Ii )
(14)
PL :
therefore:
~
Psat: saturation losses of the power transistor Q.
These losses increase as Vi decreases.
TON
Vo
Psat = Vsat. 10 T = Vsat 10 Iii
(13)
TON
Vo
where - - = and Vsat is the power
T
Vi
transistor saturation at current 10.
The negative sign may be interpretated with the fact
that the current is now decreasing. Assuming that
VF may be neglected against Va, during the OFF
time the following behaviour occurs:
Va
IL= -L-t
(8)
i1IL - =
DC LOSSES
(6)
It follows therefore that:
iL (t)
plus all the other system losses. The expression of
the efficiency becomes therefore the following:
Po
11=
(12)
Po + Psat + Po + PL + Pq + psw
TON
= Vi
TON + TOFF
TON
T
(10)
--=r=v;-
Pq = Vi 1'3q + Vo 1"3q
in which:
at 0 % duty cycle
where T is the switching period.
1'3q = 13q
Expression (10) links the output voltage Va to the
input voltage Vi and to the duty cycle. The relationship between the currents is the following:
TON
lioc= 10DC·-,=-
1"3q =
i3 q (100 % d.c.) -
The system efficiency is expressed by the following
formula:
Po
100
Pi
where
Po = Vola
(with 10 = ILOAO)
is the output power to the load and Pi is the input
power absorbed by the system. Pi is given by Po,
13q (0 % d.c.)
SWITCHING LOSSES
Psw : switching losses of the power transistor:
P sw = Vi 10
EFFICIENCY
it follows that:
tr + tf
---zr-
The switching losses of the recirculation diode are
neglected (which are anyway negligible) as it is assumed that diode is used with recovery time much
smaller than the rise time of the power transistor.
We can neglect losses in the coil (it is assumed that
i1IL is very small compared to 10 ) and in the output
capacitor, which is assumed to show a low ESR.
5/42
439
APPLICATION NOTE
Calculation of the inductance value, L
Calculation TON and TOFF through (4) and (9) respectively it follows that:
L
TON =~It.
---
TOFF
Vi-Va
Mi: . L
Finally, calculating C it follows that:
C = '(Vi - Va) Va
where:
L is in Henrys
C is in Farads
f is in Hz
Va
But because :
and
TON + TOFF = T
it follows that :
~IL' L
~IL' L
- - + - - =T
Vi-Va
Va
(20)
8Vi~Vcf2L
Finally, the following expression should be true:
~VCmax
ESRmax =
Calculating L, the previous relation becomes:
L= (Vi-Va) Va T
Vi~IL
(21 )
~IL
It may happen that to satisfy relation (21) a capacitance value much greater than the value calculated
through (20) must be used.
(18)
TRANSIENT RESPONSE
Fixing the current ripple in the coil required by the
design (for instance 30% of 10), and introducing the
frequency instead of the period, it follows that:
L = (Vi - Va) Va
Vi . 0.3 .1 0 • f
where L is in Henry and f in Hz
Calculation of the output capacitor C
From the output node in fig. 3 it may be seen that
the current through the output capacitor is given by :
Sudden variations of the load current give rise to
overvoltages and undervoltages on the output voltage. Since ie = C (dvddt) (22), where dVe = ~Vo, the
instantaneous variation of the load current ~Io is
supplied during the transient by the output capacitor, During the transient, also current through the
coil tends to change its value,
Moreover, the following is true:
VL = L
ie (t) = iL (t) - 10
FigiJre 3 : Equivalent Circuit Showing Recirculation when Q1 is Turned Off.
~
dt
where diL = ~Io.
(23)
VL=Vi-Vo
VL = Va
for a load increase
for a load decrease
Calculating dt from (22) and (23) and equalizing, it
follows that:
1LOAD
L diL = C dVe
VL
ie
Calculating dVe and equalizing it to
that:
c
~Vo=
~Vo =
5- 6777
From the behaviour shown in fig. 2 it may be calculated that the charge current of the output capacitor,
within a period, is ~1L.l4, which is supplied for a time
T/2. It follows therefore that:
~V =~2=~ILT=~
c
4C 2
(19)
8C' 8fC
but, remembering expression (4) :
~IL+
(Vi - Va) TON
dT
L
an
ON =
Va T
---v:-
therefore equation (1.9) becomes:
~V '= (Vi - Va) Va,
c
8 Vif2 L C
6/42
440
~102
C(Vi - Va)
~102
CVo
~Vo,
(24)
for + ~Io
(25)
for -
it follows
~Io
From these two expressions the dependence of
overshoots and undershoots on the Land C values
may be observed. To minimize ~Vo it is therefore
necessary to reduce the inductance value L and to
increase the capacitance value C, Should other auxiliary functions be required in the circuit like reset
or crowbar protections and very variable loads may
be present, it is worthwhile to take special care for
minimizing these overshoots, which could cause
spurious operation of the crowbar, and the undershoot, which could trigger the reset function.
APPLICATION NOTE
DEVICE DESCRIPTION
Fig. 4 shows the package in which the device is
mounted and the pin function assignments.
The internal structure of the device is shown in fig. 5.
Each block willl10W be examined.
voltage of 5.1 V for the whole system, also supplied
the internal analog blocks.
Special features of the voltage reference are its accuracy, temperature stability and high line rejection.
Through zenze-zap trimming, the voltage is within
±2% limits.
Power supply
The device is provided with an internal stabilized
power supply that, besides supplying the reference
Figure 4 : Pin Assignments of the L296.
~15
'4
~
13
I
11
10
9·
8
7
6
5
-+~
~1
CROWBAR DRIVE
RESET OUTPUT
RESET DELAY
RESET INPUT
OSClll"JOR
FEEDBACK INPUT
FREQUENCY COMPENSATION
GROUND
SYNC. INPUT
INHIBIT INPUT
SOFT-START
CUR RENT LIMIT
SUPPLY VOLTAGE
OUTPUT
CROWBAR INPUT
I
Tab connl"ctl"d to pin 8
Figure 5 : Block Diagram of the L296. In Addition to the Basic Regulation Loop the Device includes Functions such as Reset, Crowbar and Current Limiting.
I
RESET DELAV
INHIBIT
INPUT
7/42
441
APPLICATION NOTE
OSCILLATOR
The oscillator block generates the saw-tooth waveform that sets the switching frequency of the system. This signal, compared with the output voltage
of the error amplifier, generates the PWM signal to
be sent to the power output stage. The saw-tooth,
whose amplitude is between 1.2V. and 3.2V; is
generated by charging rapidly the Cose capacitor
which then discharges across the Rose resistance.
As shown in fig. 6, the oscillator is realized by a comparator (with grounded compatible iriput) with hysteresis whose thresholds are 1 .2V and 3.2V
respectively. The Cose capacitor and the Rose resistance are connected to the non-inverting input of the
comparator which set the oscillating frequency is
fixed. When the voltage on pin 11 is less than 3.2V,
the switch 81 is closed and the current generator
charges the Cose capacitor rapidly; in this phase 82
is also closed. As soon as 3.2V is reached the comparator output drives 82 open (therefore opening 81,
too) ; the inverting input voltage is reduced to about
1.2V and the capacitor starts to discharge itself
across the Rose resistor (the Ibias effect is neglected).
When the voltage reaches 1.2V, 82 and 81 close
again and a new cycle starts. The generated waveform is shown in fig. 7.
To achieve a good accuracy of the switching frequency it is essential to have a charging time of the
capacitor which is much smaller than the discharging time. In this way, the oscillation frequency only
depends on the external components Cose and Rose.
Forthis reason the capacitor charging current (when
81 is ON) is typically around 10mA. For example,
with a 2.2nF capacitor to switch from 1.2V to 3.2V
about 400ns is required, which is negligible compared to the 1O).lS period that occurs when the operation is performed at 100kHz. The diagrams shown
in fig. 8 allow the calculation of the Rose value (R1 in
fig. 8) with Cose as a parameter (C3 in fig. 8) when
the oscillation frequency required for operation has
been previously fixed.
Figure 6 : Internal 8che:matic of the Oscillator.
L296
I
______ J
5-67.'
8/42
442
APPLICATION NOTE
Figure 7a : Oscillator Waveform at Pin 11 with
f = 100Khz (Rose = 4.3KQ,
Cose = 2.2nF).
Fig. 8 shows two suggested values for the Cose capacitance. Excessively low capacitance value may
give rise to an inaccuracy of the upper threshold due
to the switching delays of the comparator. This inaccuracy in caused by an excessively short rise time
of the voltage. A capacitance value too high gives
rise to a charging time which is too compared to the
discharging time. An additional inaccuracy cause
would be therefore present for the switching frequency, now due to spread of the charge current.
The oscillation frequency is given by the following
formula:
fose
=
Rose Cose
(26)
PWM (see fig. 9)
Figure 7b : Oscillator Waveform at Pin 11 with
f = 50Khz (Rose = 9.1 KQ,
Cose = 2.2nF).
The PWM signal is generated on the comparator
output ; the triangular-shaped waveform and the
continudus signal coming from the output of the
trarisconductance error amplifier are sent to its inputs. The PINM signal is then transferred to the driving stage of the output power transistor.
SOFT START (see fig. 9)
Soft start is an essential function for correct start-up,
to prevent stresses and possible breakdown from
occurring in the power transistor and to obtain a
monotonically, ihcreasing output voltage.
In particular, the L296, as it does not have any duty
cycle limitation and due to the type of current limitation does not allow the output to be forced to a
steady state without the aid of the soft-start facility.
Soft-start. operates at the start-up of the system,
after the inhibit has been activated, after an intervention of the current limitation and after the intervention of the thermal protection.
Figure 8 : Nomogram for the Choice of Oscillator
Components.
....
4~11
G
r
(
)
.......
. ""
100
~
'\
O=\5nF
CJ.Z.2nF"r'\..
IIII
10
lUI
10
1",
"
RI (OA)
The soft-start function is realized through a capacitor connected to pin 5 which is charged at constant
current (= 100IlA) up to a value of about VREF. During the charging time, through PNP transistor 058,
the voltage on pin 9 is forced to increase with the
same rising speed as on pin 5. Starting from the discharged capacitor condition (pin 5 voltage = OV) the
power transistor is in the OFF condition, as the voltage on pin 9 is smaller than the minimum level of
the ramp voltage. As the capacitor is charged, the
PWM signal begins to be generated as soon as the
error amplifier output voltage crosses the ramp; the
power stage starts to switch with steadily increasing
duty cycle. This behaviour is shown in fig. 10. As
soon as the steady condition is reached the duty
cycle sets itself to the right value due to the effect of
the feedback network while the soft-start capacitor
completes its charging to a value very close to VREF.
9/42
443
APPLICATION NOTE
The soft-start effect is determined, apart from the
switch-on time, when the current limitation operates,
due to either an overload or a short circuit, to keep
the mean value of the current absorbed by the
power supply low.
mum ramp level and increase over the maximum
level no limitations have been provided on the duty
cycle, . which therefore may vary between 0 and
100%.
Moreover from fig. 1'1 it may be observed that since
the voltage on pin 9 can decrease under the miniFigure 9 : Partial Internal Schematic Showing PWM and Soft Start Blocks.
~
VREF
l296
p~
5OI'A!
VREF
I
10
a5S
S-6184
Figure 10: Soft Start Waveforms. When power is applied, or after an inhibit, the L296's output current
rises slowly under control of the soft start circuit.
05CILLATOR
OUTPUT
NOMINAL
ERROR AMP.OUTPUT
OUTPUT
CURRENT
5 _5835
10/42
444
APPLICATION NOTE
Figure 11 : Waveform for Calculation of Duty Cycle and Soft Start Time.
(V)
5
Vp in5
----------
1.2
tss
II
"
tstart-up
5-6798/1
CALCULATING THE DUTY CYCLE AND
SOFT-START TIME
where Css is the soft-start capacitor and 15so is the
charging current.
Assume, for simplicity, that the rising edge of the
ramp is instantaneous; V, is the output voltage of
the error amplifier and Ve the ramp voltage (see fig.
11). The PWM comparator block switches when
V, = Ve ; therefore:
Considering as the soft-start time the time required
for the soft-start capacitor to charge from
(1.2 V - O.5V) to V, - O.5V, gives:
Css (V, - 1.2)
tss = -----'.,.------'Isso
V,=Ve=Ee
substituting V, from (27) gives:
RoseCose
- ( 1-
Consequently:
t = Rose Case In V,
= ----:T=----E
Vo
=1-ln-=V,
Vi
)
substituting into (28) gives:
The time obtained from this expression is the TOFF
time of the power transistor. The duty cycle d is given
by:
E
TON
T - Rose Cose In Vr
d =T
~~
V,= Ee
E
(27)
Consequently, starting with the capacitor discharged, the output of the regulator will be at the
nominal level when the voltage at the terminal of the
capacitor (which is charged by a constant current)
hC!s reached V, - O.5V.
Css (V, - O.5V)
tstart.up =
15so
Css
tss = -1- (E e
sso
( Va -1 )
Vi
- 1.2)
SYNCHRONIZATION
The synchronization function is available on pin 7,
this function allows the device to be switched at an
externally generated frequency (leaving pin 11
open), or to mutually synchronize several devices,
using one of them as master and the others as slave
(fig. 12).
This allows several devices to be operated at the
same frequency, avoiding undesirable intermodulation phenomena. The number if mutually synchronizable devices is obviously much greater than the
three devices shown in the figure. It is anyway diffi-
11142
445
APPLICATION NOTE
cult to establish an exact maximum number of devices, as it depends on different conditions.
The first consideration concerns the accuracy which
must be achieved and maintained on the oscillation
frequency. Since the bias current on pin 7 is an output current, the sum of all the bias currents must be
much smaller than the capacitor discharge current in
close proximity to the lower discharge threshold.
Therefore, assuming Cose = 2.2nF and Rose = 4.3KQ,
it follows that:
~
4.3KO
=280 A
/l
Assuming that a 10% variation may be accepted, it
follows therefore that the number of synchronizable
devices is given by :
N=
28/lA
jbias max
This means that if the overall Ibias is too high it may
modify the discharging time of the capacitor.
The second consideration concerns the layout design.
In the presence of a great number of devices to be
synchronized, the lenght of the paths may become
significant and therefore the distributed inductance
introduced along the paths may begin to modify the
triangular shaped waveform, particularly the rising
edge which is very steep. This effect would affect
the devices thafare physically located more distant
from the master device.
The amplitude ofthe saw-tooth to be externally connected must be with in 0.5V and 3.5V, values also
representing the maximum swing of the error amplifier output.
'
CURRENT LIMITATION
The current limitation function has been realized in
a rather innovative way to avoid overload condition
during the short circuit operation. In fact, while for
all the other devices a constant current limitation is
implemented by acting on the duty cycle (therefore,
in short circuit conditions an output current is equal
to the maximum limitation current), the new control
approach allows operation in short circuit conditions
with a mean current much smaller than the allowed
4A value. Operation of the current limiter will now be
described.
Refer to the block diagram, fig. 13.
The current which is delivered from the output transistor to the load flows through the current sensing
resistor Rs. When the voltage drop on Rs is equal
to the offset voltage of the current comparator, the
comparator generates a set pulse for the flip-flop,
with a delay of about 1 flSec. The purpose of this
delay is to avoid triggering of the protection circuit
on the current peak that occurs dUQ!lg the recirculation phase. Therefore, the output Q goes low and
the power ..§.tage is immediately switched off, while
the output Q goes high and acts directly on the softstart capacitor dischargng the soft-start capacitor at
a constant current (about 50/lA). '
When the voltage on pin 5 reaches O.4V the comparator triggers, supplying a reset pulse to the flipflop; from now on, the power stage is enable and
the soft-start phase starts again. When the limitation
cause, either overload or short circuit, is still present
the cycle repeats again. The waveform of the output current on pin 2 is shown in fig. 14.
Figure 12: In multiple supplies several 1296's can be synchronized as shown here.
11
7
11
OSC
SYNC
OSC
I
1
sc
12/42
446
L296
L296
L296
±co~
7
SYNC
1
11
7
OSC
SYNC
I
J
S-~97&/l
APPLICATION NOTE
From fig. 14 it may be observed how this current
limitation technique allows the short circuit operation
with a very low output current value.
It is possible to reduce the maximum current value
by acting on pin 4. On this pin a voltage of about
3.3V is present; by connecting a resistance a constant current, given by 3.3/R, is sent to ground. This
current reduces the offset voltage of the current
comparator, therefore anticipating its triggering threshold.
Figure 13 : Partial Schematic Showing the Current Limiter Circuit.
l296
5
Q
FLIP
FLOP
R
Q
9
2
4
I
5-6785
C55
R
Figure 14a : Current Limiter Waveforms.
12
CURRENT
LIMITER
TRIGGERS
r-
LIMIT
:~~:::w"
CUR RENT
-~n;~ an-A~~~a~ ~
-'-----'--'...L- - -J...LL.LL...L- - --U....LLL.J.-- -
-----,-------
(
..
u.
t
..
S. &59611
13/42
447
APPLICATION NOTE
Figure 14b: Load Current in Short Circuit Conditions
(Vi = 4OV, L = 30011H, f = 100KQ).
II
L
•
,
I
Hi
I
.,
II
•
..
~ .~ ~
1
=
I
+- ••.••• -+-t-+-+-t
1
I,'; =II
=
i
II
II
•
t: 5ms/div
Figure 14c : Current at Pin 2 when the Output is
Short Circuited.
the limits required to supply the microprocessor correctly.
The reset function is realized through the use of 3
pins: the reset input pin 12, the reset delay pin 13
and the reset output pin 14. When the voltage on
pin 12 is smaller than 5V the comparator output is
high and the reset capacitor is not charged because
the transistor 0 is saturated and the voltage on pin
14 is at low level, since 02 is saturated, too. When
the voltage on pin 12 goes above 5V, the transistor
switches OFF and the capacitor can start to
charge through a current generator of about 100!lA.
When the voltage on pin 13 goes above 4.5V the
output of the related comparator switches low and
the pin 14 goes high. As the output consists of an
open collector transistor, a pull-up external resistance is required. In contrast, when the reset input
voltage goes below 5V, less a hysteresis voltage of
about 100mV, the comparator triggers again and
instantaneously sets the voltage on pin 14 low,
therefore forcing to saturation the 01 transistor, that
starts the rapid discharge of the capacitor. Obviously, the reset delay is again present when the voltage
on pin 13 is allowed to go under 4.5V.
o
To achieve switching operations without uncertainties the two comparators have been provided with
an hysteresis of about 100mV. In every operating
condition the reset switching is guaranteed with a
minimum reset input of 4.75V, the value required for
correct operation of the microprocessor even in the
presence of the minimum VREF value.
t: 5ms/div
RESET
The reset function is of great importance when the
device is used to supply microprocessors, logic devices, and so on. This function differentiates the
L296 device from all previous devices. The block diagram of the function is shown in fig. 15. A reset signal is generated when the output voltage is within
14142
448
Norl)1ally pin 12 is used connected to pin 10. When
it is connected to the output, the function may be
more properly called "reset" ; on the other hand,
when it is connected through resistive divider, to the
input voltage, the function is called "power fail". Fig.
16 and fig. 17 show the two possible usages.
The "power-fail" function is used to predict, with a
given advance, the drop of the regulator output voltage, due to main failures, which is enough to save
the data being processed into protected memory
areas. Fig. 18 summarizes the reset function operation.
APPLICATION NOTE
Figure 15: Partial Schematic Showing Reset Circuit.
L296
RESET
14 OUTPUT
13
I
CRESET
$-67f16
Figure 16: For Power - On reset the reset block is connected as shown here.
RESET
OUT
~
14
L296
13
12
~
CRESE
=
2
10
~
..
1 --
!
DVo
I
5 - 677]
Figure 17 : To obtain a power fail signal, the reset block is connected like this.
RESET
OUT
12
L296
I
15/42
449
APPLICATION NOTE
Figure 18 : Waveform of the Reset Circuit.
OUTPUT NOW
STABLE,RESET
GOES HIGH
I
IOOmV OF
-HYSTERESIS
RESET
THRESHOLD ----.
+
AN INTERRUPTION
OF SUPPLY C"'U~S
RESET OF MICRO
I
t
_J __ _ "'_-_-_-_-_-_-_-_-_-_""' - - -
I
AT POWER DOWN
MICRO IS INHIBITED
IMMEDIATELY
-------
MONITORED
VOLTAGE
RESET
OUTPUT
DELAY
CROWBAR
!his protection function is realized by a completely
Independent block, using pin 1 as input and pin 15
as output. It is used to prevent dangerous overvoltages from occurring when the output exceeds 20%
of rated value. Pin 15 is able to output a 1OOmA cur~ent to be sent to the gate of a SCR which, triggering, short circuits either output or the input. When
connected to the input, as the SCR is triggered a
fuse in series connected to power supply is blown
and to bring the system back to operation manual
intervention is requested. Figs. 19, 20 and 21 show
the different configurations.
DELAY
When the voltage on pin 1 exceeds by about 20%
the VREF value the output stage is activated, which
sends a current to the SCR gate, after a delay of
about 51lsec to make the system insensitive to lowduration spikes. When activated, the output stage
delivers about 1OOmA ; when not activated, it drains
about 5mA and shows a low impedance to the SCR
gate to avoid uncorrect triggering due to random
noise. If the crowbar fu nction is not used connect
pin 1 to ground.
Figure 19 : Connection of Crowbar Circuit at Output for 5.1 V Output Applications.
L296
15
5-6775
16/42
450
I
APPLICATION NOTE
Figure 20: Connection of Crowbar Circuit at Output for Output Voltages above 5.1 V.
Figure 21 : Connection of Crowbar Circuit to Protect Input. When triggered, the scr blows the fuse.
Vio-r=
FU~~
I
~~
(.~
~
I
5 -67 69
INHIBIT
The inhibit input (pin 6) is TIL compatible and is activated when the voltage exceeds 2V and deactivated when the voltage goes under O.8V. As may
be seen in the block diagram, the inhibit acts on the
power transistor, instantaneously switching it off and
also acts on the soft-start, discharging its capacitor.
When the function is unused, pin 6 must be
grounded.
THERMAL PROTECTION
The thermal protection function operates when the
junction temperature reaches 150"C ; it acts directlyon the power stage, immediately switching it off,
and on the soft-start capacitor, discharging it. The
thermal protection is provided with hysteresis and,
therefore, after an intervention has occurred, it is
necessary to wait for the junction temperature to decrease of about 30"C below the intervention threshold.
3
L296
15
I
1 l
...()INPUT
CROWBAR
applications. We will now examine these possibilities and show how the capabilities of the device
may be extended.
In fig. 22 the complete typical application is shown,
where all the functions available on the device are
being used. This circuit delivers to the load a maximum current of 4A and a voltage which is established by the voltage divider constituted by R7 and Rs
resistances. The following table is helpful for a quick
calculation of some standard output voltages:
Resistor Value for Standard Output Voltages
Vo
12 V
15V
18 V
24 V
Ra
4.7
4.7
4.7
4.7
kQ
kQ
kQ
kQ
Ry
6.2 kQ
9.1 kQ
12 kQ
18 kQ
To obtain Va = VREF the pin 10 is directly connected
to the output, therefore eliminating both R7 and Rs.
The switching frequency is 100kHz.
APPLICATIONS
Though the L296 is designed for step-down regulator configurations it may be used in a variety of other
17142
451
APPLICATION NOTE
Figure 22 : Schematic, PCB Layout and Suggested Component Values for the Evaluation Circuit used to
characterize the L296. This is a typical stepdown application which exercises all the device's
functions.
RESET
R6
Vi
Rl
3
14
10
II
12
~oo}'
VO
H
Ql
L296
13
R7
15
Cl
10pF
63V
R8
4.7
Kfi
GND~~----
__----------+---------------------------~--------~--~--~GND
5-62801l
INHIBIT
C7, C8 : EKR (ROE)
SUGGESTEDINDUCTOR(U)
Core Type
Magnetics 58930 A2MPP
Thomson GUP
.20 x 16 x 7
18/42
452
No
Turns
Wire
Gauge
43
65
SUGGESTED INDUCTOR (L1) (continued)
Air
Gap
Core Type
No
Turns
Wire
Gauge
1.0 mm.
Siemens EC 35/17/10
(86633 & - G0500 - x 127)
40
2 x 0.8 mm.
0.8 mm.
VOGT 250 IlH Toroidal Coil, Part Number
5730501800
1 mm.
Air
Gap
APPLICATION NOTE
Figure 23 : Oscilloscope Photographs Showing
Main Waveform of the Figure 22
Circuit.
-
--
fiI
...-.:
-~
- ~
--. -. --
-;;=,.1
~
-
ro. ';;"'?
II
~
I.
,!;;J
iii:!!
IIiii
~
,
iii:! i'::!!
=
~
1I":1
..
--I i.II---
two 100llF/40V capacitors have been connected in
parallel. The behaviour of the impedance as a function of frequency is shown in fig. 24.
Also the selection of the catch diode requires special care. The best choice is a Schottky diode which
minimizes the losses because of its smaller forward
voltage drop and greater switching frequency rate.
A possible limitation comes from the backward voltage, that generally reaches 40V max.
When the full input voltage range of the device is required in this application it is possible to use superfast
siodes with 35 to 50ns rated recovery time, where no
more problems on the backward voltage occur (on the
other hand, they show a greater forward voltage). The
use of slower diodes, with trr = 1OOns or more is not
recommended; The photographs in fig. 25 show the
effects on the power current and on the voltage on pin
2, due to the diodes showing different speeds. Diodes
showing trr greater than 35-50ns will reduce the overall efficiency olthe system, increasing the power dissipated by the device.
The third component requiring care is the inductor.
Fig. 22a shows the part numbers of some types
used fortesting. Besides having the required inductance value, the coil has to show a very high saturation current.
Therefore, a correct dimensioning requires a saturation current above the maximum value of 12L, the
current limit threshold.
achieve high saturation with ferrite cores an air
gap between the two core halves must be provided;
the air gap causes a leakage flux which is radiated
in the surrounding space. To better limit this phenomenon "pot cores" may be used, whose geometry
is such to better limit the flux radiated to the outside.
Using toroidal cores, for instance of Magnetic 58930A2 moly-permalloy kind, both the requirements of high
saturation and low leakage flux are satisfied. The saturation is softer that the saturation shown by the ferrite
materials. The air gap is not concentrated in one area,
but is finely distributed along the whole core ;this gives
the low leakage flux value.
Careful selection of the extemal components therefore allows the realization of a power supply system
whose benefits are significant when compared to a
system with the same performance but realized with
the linear technique.
T.o
t: 2/-Ls/div
The oscilloscope photographs of the main waveforms are shown in fig. 23. The output voltage ripple
!Y.Vo depends on the current ripple in the coil and on
the performance of the output capacitor at the
switching frequency (100kHz). A capacitor suitable
for this kind of application must have a low ESR and
be able to accept a high current ripple, at the working frequency. For this application the Roederstein
EKR series capacitors have been selected, designed for hig h frequency applications (>200kHz) and
manufactured to show low ESR value and to accept
high current ripples. To minimize the effects of ESR,
19/42
453
APPLICATION NOTE
Figure 24 : Typical Impedance/Frequency curves
for EKR Capacitors .
..
....
~
~
[0)
"'
r--.r-,
221'J
~
•
.......
1"-
r-- ~
..........
~'o
-----
I"'.r--
I'\."'"
~
~
~ 'I.
~,
"0
,~
'~.
I-~20f21
f--
r--1-----1-
0.01
..
'-..
I
5
7
t-
l
lOll
'..,H:
•
,.
T
I Il
~
Ii
___
t: 2J.ls/div
Figure 25 : Oscilloscope Photographs Showing
the Waveform obtained with Diodes
having Different trr Values.
LOW COST APPLICATION AND PRERE·
GULATOR
Fig. 26 shows the low cost application of a 4A and
Vo = 5.1 V power supply. A minimum amount of essential external components is required, which are
necessary for correct operation. It is impossible to
save other components, specially the soft-start capacitor. Without soft-start, the system cannot reach
the steady state and there is also a serious risk of
damaging the device.
t : 211S/div
20142
454
This application is very well suited not only as a lowcost power supply, but also as pre-regulator for postregulators distributed in different circuit points, or
even on different boards (fig. 27). The -post-regulators may be selected among the low-drop types, like
L4805 and L387 for example, still obtaining a high
efficiency, combined with an excellent regulation.
The use of L387 device allows us to use also the
reset function, useful to power a microprocessor.
APPLICATION NOTE
SWITCHING vs LINEAR
Linear
Switching regulators are more efficient than linear
types so the transformer and heatsink can be smaller and cheaper. But how much can you gain?
For a good linear regulator the minimum dropout w1ll
be at least 5V at 4A. The minimum input voltage is
given by:
1
Vi min = Va + Vdrop + 2
Vripple
We can estimate the savings by comparing equivalent linear and switching regulators. For example,
suppose that we want a 4 N5 V supply.
where:
10 t1
4 x S x 10 - 3
VriPPle:=C =
10x 10 3
V
Vf ---
I
I
I
I
,
I
I
i(min) -
._
t)
-----
=3.2V
-
~ =-= _IVripp'e
J
I,
.,
I
5-59%
(a good approximation is Sms for t1 at mains frequency of 50Hz and 1O.OOOIlF for C, the filter capacitor after the bridge). Therefore Vimin:= 1.6V. Since
operation must be guaranteed even when the mains
voltage falls 20%, the nominal voltage on load at the
terminals of the regulator must be :
Vnom = V,m,n = 10.6
0.8
=13.25V
0.8
Switching (L296)
Assuming the same nominal voltage (14V), the L296
data sheet indicates that the power dissipated in this
case is only 7W. And this power is dissipated in two
elements; the L296 itself and the recirculation diode.
It follows that the transformer must be roughly 30VA
and the heatsink thermal resistance about 11 "CIW.
Linear
To allow even a small margin we have to choose:
Transformer
Heatsink
Vnom = 14V
The power that the series element must dissipate is
therefore:
Pd = (Vnom Va) 10 = 36W
and a heatsink will be necessary with a thermal resistance of :
Rth heats. = O.S"CIW
and the transformer must supply a power of :
Pdiss = 14 x 4 = 56W
It must therefore be dimensioned for:
PD=
~
0.9
=62VA
Switching
62 VA
30 VA
0.8°C/W
11 °C/W
This comparison shows that the L296 switching regulator allows a saving of roughly 50% on the cost of the
transformer and an impressive SO-90% on the cost of
the heatsink. Considering also the extra functions integrated by the L296 the total cost of active and passive
components is roughly the same for both types.
Finally, it is important to note that a lower power
dissipation means that the ambient temperature in
the regulator enclosure can be lower - particularly
When the circuit is enclosed in a box - with all the
advantages cooler operation brings.
If for some reason it is necessary to use higher supply voltages the switching technique, and hence the
L296, becomes even more advantageous.
~ SGS·THOMSON
1It..,
I U<\Jll©~@~~~©1l~@lllll©$
21142
455
APPLICATION NOTE
Figure 26 : A Minimal Component Count 5.1 V / 4A Supply .
.. IOVlo.46V
r
1000jJFISOV
INPUT
11
300pH
10
12
14
13
Figure 27 : The L296 may also be used as a preregulator in distributed supply systems.
SV'",OOmA
Ll
5V'",OOmA
6V
LI.805
L296
r-t-~--....-05V
LlB7A
~-6lallZ
I
RE5ET
OUTPUT
(') L2 and C2 are necessary to reduce the switching frequency spikes.
22/42
456
APPLICATION NOTE
POWER SUPPLY COMPLETE WITH
TRANSFORMER
mains preregulator can be added to reduce the input
voltage to a level acceptable for the L296.
Fig. 28 shows a power supply complete of transformer, bridge and filter, with regulation on the output
voltage from 5.1 V to 15V.
In this case the pre-regulator circuit is connected to
the primary of the transformer which now operates
at the switching frequency and is therefore smaller
and lighter.
As already stated above, the output capacitors have
to show some speciale features, like low ESR and
high current ripple, to obtain low voltage ripple
values and high reliability. The input filter capacitors
must not be neglected because they have to show
excellent features, too, having to supply a pulsed
current, required by the device at the switching frequency. The current ripple is rather high, greater
than the load current. For this application, two parallel connected 3300IlF/50V EYF (ROE) capacitors
have been used.
Using a UC3840 which includes the feed-forward
function it is possible to compensate mains variation
within wide limits. The secondary voltage is therefore only affected by load variations. Using one or
more L296s as postregulators, feedback to the primary is no longer necessary, reduces the complexity and cost of the transformer which needs only a
single secondary winding.
Fig. 28A shows a mUlti-output supply with a mains
preregu lator.
POWER SUPPLY WITH MAINS SWITCHING PREREGULATOR
When it is desirable to eliminate the 50/60Hz transformer - in portable or volume-limited equipment-a
Figure 28 : A Typical Variable Supply showing the Mains Transformer.
BY251
20V~
10
5-5Bl2/5
*SGS6R20 OR BYW80
v, = 5.1
to 15V
I, = 4A max. (min. load current = 100mA)
ripple,; 20mV
load regulation (1 A to 4A) = 10mV (V, = 5.1 V)
line regulation (200V ± 15% and to I, = 3A) = 15mV (V,
= 5.1V)
23142
457
APPLICATION NOTE
Figure 28A : A Multiple Output Supply using a Switching Preregulator rather than a Mains Transformer.
RESET
OUT
o
+5V(4A)
I
I~C~- 1-12~(200mA)
L296
~-.-
I'12v(JA)
I
POWER SUPPLY WITH 0 - 30V
ADJUSTABLE VOLTAGE
When output voltages lower than 5V are required,
the circuit shown in fig. 29 may be used.
Calibration is performed by grounding the P1 slider.
Acting on P2, the current which flows through the
1OkQ resistor is fixed at approximately 2.5mA to Qbtain an output voltage of 30V. The equivalent circuit
is shown in fig. 30.
Acting now on the slider of P1, the current flowing
through the divider may be varied. The new equival~
ent circuit is shown in fig. 31.
.
Reducing the current flowing, also the voltage drop
across the 10kQ resistance is reduced, together
with Vo. When the current reaches zero, it follows
that Vo = VREF. When the voltage on the slider of P1
exceeds VREF, the current star! to flow in opposite
direction and Vo begins to decrease below 5V.
When 11 x 10kQ = VREF it follows that Vo = O.
24/42
458
DUAL OUTPUT REGULATOR
The application shown in fig. 32 is specially interes~
ting because it provides two output voltages. The
first voltage, the main one, is directly controlled by
the feedback circuit. The second voltage is obtained
through an auxiliary winding.
It often happens, when microprocessors, logic devices etc., have to be power supplied, that a main
5V output and an auxiliary + 12V or - 12V output
are required, the latter with lower current requirements (100 + 200mA) and a stabilization level not
excessively high. As the auxiliary power supply is
obtained through a completely separated winding,
it is possible to obtain either a positive or negative
voltage (compared to the main voltage or also a
completely isolated voltage. With Vi variable between 20V and 40V, Vo = 5.1 V and 10 = 2.5A, the
auxiliary- 12V/0.2A voltage is within a ± 2% tolerance.
APPLICATION NOTE
Figure 29 : Variable 0-30V supply illustrating how output voltages below 5.1 V are obtained.
10KA
11O~F
ZI
150~H
Vo
SGStlR20
O~
8ywOO
I
1000
~F
10Kll
2kll
PI
lOOK a
Figure 30 : When setting up the figure 29 circuit
the slider of P1 is grounded, giving the
equivalent circuit shown here, and P2
adjusted to give an output voltage of
30V.
l296
IO~--"
Figure 31 : Partial Schematic showing Output
Voltage Adjustment of Figure 29.
L296
10~------'
6V
s- 6771
25142
459
APPLICATION NOTE
Figure 32 :Dual output regulator showing how an additional winding can be added to the inductor to generate
a secondary output.
0-
W
.
(J)
--J
w
~
I\)
o-I
m
APPLICATION NOTE
LAYOUT CONSIDERATIONS
Both for linear and switching power supplies when
the current exceeds 1A a careful layout becomes
important to achieve a good regulation. The problem becomes more evident when designing switching regulators in which pulsed currents are over
imposed on dc currents. In drawing the layout,
therefore, special care has to be taken to separate
ground paths for signal currents and ground paths
for load currents, which generally show a much
higher value.
When operating at high frequencies the path length
becomes extremely important. The paths introduce
distributed inductances, producing ringing phenomena and radiating noise into the surrounding
space.
The recirculation diode must be connected close to
pin 2, to avoid giving rise to dangerous extra negative voltages, due to the distributed inductance.
Fig. 43 and fig. 44 respectively show the electric diagram and the associated layout which has been
realized taking these problems into account.
Greater care must be taken to follow these rules
when two or more mutually synchronized devices
are used.
Figure 43 : Typical application circuit showing how the signal and power grounds are connected.
RESET
R6
Vi
~~
__~__________- ,
Rl
14
10
l I
R7
Cl
10Jo'F
R2
100
KA
63V
RS
4.7
Kfi
C2
2.2"
__--->I<--______~"__---'L---TON in the conduction time of the
switching transistor causes a corresponding variation in the output voltage, L'>Vo, giving:
L'>Vo _ Y.J..
L'>TON T
Indicating with Vr the output voltage of the error amplifier, and with Vet the amplitude of the ramp (the difference between the maximum and minimum values),
TON is zero when Vr is atthe minimum value and equal
to T when Vr is at a maximum. Consequently:
L'>TON
T
L'>Vr = Vct
The gain-is given by :
I':No
Vi
L'>Vr = 'Jct
38142
472
G,
(dB)
60
50
" " G,
1'\.\
'f
30
-40
\.\
-80
"~
,6
-120
\
\
10
\
\
-10
10
100
IK
10K
lOOK
1M
f (Hz)
APPLICATION NOTE
The error amplifier is a transconductance amplifier
(it transforms a voltage variation at the input into a
current variation at the output). It is used in open
loop configuration inside the main control loop and
its gain and frequency response are determined by
a compensation network connected between its output and ground.
Inthe application aseries RC network is recommended
which gives high system gain at low frequency - to ensure good precision and mains ripple rejection and a
lower gain at high frequencies to ensure stability of the
system. Figure A2 shows the gain and phase curves
of the uncompensated error amplifier.
The amplifier has one pole at about 7kHz and a
phase shift which reaches about - 90' at frequencies around 1MHz.
The introduction of a series network Rc Cc between
the output and ground modifies the circuit as shown
in figure A3.
Figure A4 shows the gain and phase curves of the
compensated error amplifier.
Figure A3 : Compensation Network of the Error
Amplifier.
CALCULATING THE STABILITY
For the stability calculation refer to the block diagram shown in figure A5.
The transfer functions of the various blocks are rewritten as follows.
The simplified transfer function of the compensated
error amplifier is :
1
1 + s Rc Cc
GEA = gm Zc =
(gm = 2500 )
S Cc
The DC gain must be considered equal to :
Ao = gm Ro
PWM block and output stage:
Vi
GpWM=
LC FILTER:
1 + S C· ESR
S2 LC
+ S C ESR + 1
where ESR is the equivalent series resistance of the
output capacitor which introduces a zero at high frequencies, indispensable for system stability. Such a
filter introduces two poles at the angular frequency.
1
00 0 =
VIC
Refer to the literature for a more detailed analysis.
Feedback: consists of the block labelled ex
ex = 1 when Vo = VREF (and therefore Vo = 5.1V)
and
when Vo > VREF
Figure AS : Block Diagram Used in Stability
Calculation.
Figure A4 : Bode Plot Showing Gain and Phase of
Compensated Error Amplifier.
- - - UNCOMPE NSATED
--COMPENS ATEO
II"K:: - - - - - - -I
I
I
""
1
I
"-
"1
1
I
,
/' 'I
~
~~
J
1
2TTR o Cc
1
1
2TIRcCc
,',
,
"-
,
:""-"
I
I
"\!
!'\
:
1
1
2TrRoCo
2nRcCo
Vl
"'
ISO "'
a:
135
90
"''"0
':l"'r
"-
$-6957
39/42
473
APPLICATION NOTE
To analyse the stability we will use a Bode diagram.
The values of Land C necessary to obtain the required regulator output performancen, once the frequency is fixed, are calculated with the following
formulae:
(Vi- Va) Vo
Vi f L'>IL
C=
Figure A7 : Bode Plot of Complete System Taking
into Consideration the Equivalent
Series Resistance of the Output
Capacitor.
dB
(Vi- Va) Vo
8L f2 L'>Vo
Since this filter introduces two poles at the angular
frequency
(00
=
1
.j LC
we place the zero of the Re Ce network in the same
place:
1
COz = Rc Cc
Taking into account also the gain of the PWM block,
the Bode plot of figure A6 is obtained.
The slope where the curve crosses the axis at OdB
is about 40dB/decade therefore the circuit is unstable.
Taking into account now the zero introduced by the
equivalent series resistance (ESR) of the output capacitor, we have further condition for dimensioning
the Re Ce network. Knowing the ESR (which is supplied by the manufacturer for the quality components) we can determine the value of Re so that the
axis is crossed at OdB with a single slope. The zero
introduced by the ESR is at the angular frequency:
1
WzESR =
ESR· C
The overall Bode diagram is therefore as shown in
figure A7.
Figure A6 : Bode Plot of System Taking Filter and
Compensation Network into Account.
S· 6855
DC GAIN AND LINE REGULATION
Indicating the open-loop gain of the error amplifier
with Ao, the overall open-loop gain of the system is :
Vi
R2
Vet
When Va = VREF, the gain becomes:
Vi
At=Ao - Vet
Considering the block diagram of figure A8 and calculating the output variation L'>Va caused by a variation of Vi, from the literature we obtain:
L'>Vi
Va
AD Vi
Vet
• ~
Rl + R2
This espression is of general validity. In our case the
percentage variation of the reference must be
added by vector addition.
dB
Figure AS : Block Diagram for Calculation of Line
Regulation.
r-+
-
"-'0
5-6856
40/42
474
t--
AO
I
I
R2
Rl+R2
Vi
""Vct
I
I
5- 6853
APPLICATION NOTE
APPENDIX B
REDUCING INTERFERENCE
The main disadvantage of the switching technique
is the generation of interference which can reach levels which cause malfunctions and interfere with
other equipment.
For each application it is therefore necessary to
study specific means to reduce this interference
within the limits allowed by the appropriate standards.
Among the main sources of noise are the parasitic
inductances and capacitances within the system
which are charged and discharged fastly. Parasitic
capacitances originate mainly between the device
case and the heatsink, the windings of the inductor
and the connection wires. Parasitic inductances are
generally found distributed along the strips of the
printed circuit board.
Fast switching of the power transistors tends to
cause ringing and oscillations as a result ofthe parasitic elements. The use of a diode with a fast reverse
recovery time (trr) contributes to a reduction in the
noise flowing by the current peak generated when
the diode is reverse biased.
Radiated interference is usually reduced by enclosing the regulator in a metal box.
To reduce conducted electromagnetic interference
(or radio frequency interferences - RFI) to the levels
permitted a suitably dimensioned filter is added on
the supply line. The best method, generally, to reduce conducted noise is to filter each output terminal of the regulator. The use of a fixed switching
frequency allows the use of a filter with a relatively
narrow bandwidth. For off-line switching regulators
this filter is usually costly and bulky. In contrast, if
the device is supplied from a 50/60 Hz transformer
the RFI filter problem is greatly reduced.
Tests have been carried out at the laboratories of
Roederstein to determine the dimensions of a mains
supply filter which satisfies the VDE 0871/6.78,
class B standard. The measurements (see figs. B1
and B2) refer to the application with the L296 supplied with a filtered secondary voltage of about 30V,
with Va =5.1 V and 10 = 4A. The switching frequency
is 100kHz.
Figure B1 shows the results obtained by introducing on the transformer primary a 0.01 f.lF/250V class X capacitor (type ERO F1772-31 0-2030). To
reduce interference further below the limit set by the
standards an additional inductive filter must be
added on the primary of the transformer.
Figure B2 shows the curves obtained by introducing this inductive filter (type ERO F1753-21 0-124).
Measurements have also been performed beyond
30MHz ; the maximum value measured is still well
below the limit curve.
Figure 81 : EMI Measurements with a Capacitor Connected across the Primary Transformer with Screen
Grounded (A)
~
t--"--,
JO
!
j
20
i
,:w
I~I'
1\':~
I!
I ~j
iii
J
II
~
10
10KHz
JO
100
300
1MIt.
10
30
41/42
475
APPLICATION NOTE
Figure 82 : EMI results with the addition of an inductive filter on the mains input.
dB
90
80
70
60
50
~
30
20
10
10KHz
42142
476
30
APPLICATION NOTE
DESIGNING MULTIPLE-OUTPUT
POWER SUPPLIES WITH THE L296 AND L4960
Multiple output supplies can be realized simply and economically using the SGS THOMSON Microelectronics
L296 and L4960 high power switching regulators. This note describes several practical circuits of this type.
/
Most of the switching regulators produced today
have multiple outputs. The output voltages most frequently used - at least for powers up to 50W - are
+ 5V - 5V, + 12V and - 12V. In these supplies the
5 V output is normally the output which delivers the
highest current and requires the highest precision.
For the other voltages - particularly the negative outputs - less precision (± 5 % ± 7 %) is usually sufficient. Often, however, for high current 12V outputs
better stabilization and greater precision (typically
AN245/1288
±4 %
- the output tolerance of an L7800 series linear regulator) are required.
Multiple output supplies which satisfy these requirements can be realized using the SGS THOMSON
L296 and L4960 high power switching regulator ICs,
Several practical supply designs are described
below to illustrate how these components are used
to build compact and inexpensive mUlti-output supplies.
1/10
477
APPLICATION NOTE
DUAL OUTPUT 15W SUPPLY
Vo1 = 5V/3A, Vo2 = 12V/150mA
A single L296 is used in this application to produce
two outputs. The application circuit, figure 1, illustrates how the second output (12V) is obtained by
adding a second winding to the output inductor.
Energy is transferred to the secondary during the recirculation period when the intemal power device of
the L296 is OFF.
Since the 12V output is not separated from the 5V
output fewer turns are necessary for the second
winding, therefore less copper is needed and load
regulation is improved.
In applications of this type it is a good rule to ensure
that the power drain on the auxiliary output is no
more than 20-25% of the power delivered by the
main output.
Table 1 shows the performance obtained with this
dual output supply. This circuit operates at a switching frequency of 50KHz.
Figure 1 : Dual Output DC-DC Converter (5V/3A, 12V/150mA).
+12V
20V to 40V
D2
N2
2
11
2.2nF
rr
L296
33nF
Transformer: magnetics 58930, N1
= 30 turns,
220,...F
~ov
EKR
10
9
I
-.
I
SGSBR20
OR
BVW80
D1
S -8056 11
N2
= 40 turns.
Table 1.
Parameter
Output Voltage
101 =3A
Vi = 30V
102 = 150mA
Output Ripple
V0 1
V02
Unit
5.120
12.089
V
70
40
mV
Line Regulation
101 =3A
20V" Vi" 40V
102 = 150mA
15
30
mV
Line Regulation
101 = 700mA
20V" Vi" 40V
102 = 100mA
15
10
mV
Load Regulation
101 = 700mA-' 3A
Vi = 30V
102 = 150mA
10
130
mV
Load Regulation
101 = 700mA
Vi = 30V
102 = 100 .. , 150mA
0
40
mV
Load Regulation
101 =3A
Vi = 30V
102 =100 -, 150mA
0
40
mV
Efficiency
Vi = 30V
V01 = 5.120V 101 =3A
V02 = 12.089V 102 = 150mA
2/10
478
75
%
APPLICATION NOTE
DUAL OUTPUT 7.SW SUPPLY
VOl = 5VI1.SA, Vo2 = 12Vf100mA
The same technique - adding a secondary winding
- can also be used to produce an economical and
simple dual output supply with the L4960, a device
containing the same control loop blocks as the L296
and a 2A output stage (fig. 2). Though this circuit
costs very little the performance obtained (see
table 2) is more than satisfactory. The switching frequency is 50kHz.
Figure 2 : Dual Output DC-DC Converter (5Vf1.SA, 12Vf1 OOmA).
, K.n.
1nF
~~
BVV 28-50
1000 ,oF
~
+15V 10 35 V
•
02
N2
40V 20, 220f'F
Et 3A
Vi; 30V
102 ; 103 ;100mA
4
150
150
mV
Load Regulation
101 ;3A
Vi; 30V
102 ; 100mA
103; 50 --> 100mA
0
125
52
mV
Load Regulation
101 ;3A
102; 50 --> 100mA
Vi = 30V
103; 100mA
0
50
120
mV
Efficiency
4/10
480
76
%
APPLICATION NOTE
TRIPLE OUTPUT 7.5W SUPPLY
Vol
= 5V/1.5A, Vo2 = 12V/50mA, Vo3 = -
12/50mA
application may be replaced by an L4960 as shown
in figure 4. The performance of this circuit is indicated in table 4.
For lower output powers, the L296 in the previous
Figure 4: Triple Output DC-DC Converter (5V/1.5A, 12V/50mA, -12V/50mA).
BYV 26-50
02
...-____1>---____>l--_-{)+12V
~OVh220,uF
EKR
+15V to 35V
40V
EKR
22Oj.JF
03
'---____
I--~-{)
12 v
BVV 26-50
L4960
~--------~----------~+5V
220}JF
~OV
I EKR
5-805912
Table 4.
Parameter
Output Voltage
101 = 1.SA
V0 2
V03
Unit
5.040
12.020
- 12_020
V
VOl
Vi =2SV
102 = 103 = SOmA
60
30
30
mV
Line Regulation
101 = SOOmA
1SV" Vi" 3SV
102 = 103 =SOmA
5
80
80
mV
Line Regulation
= 1.5A
1SV"Vi ,,3SV
102 = 103 = 50mA
4
60
60
mV
Load Regulation
= O.SA --> 1.SA
Vi = 25V
5
120
120
mV
0
15
50
mV
0
50
15
mV
Output Ripple
101
101
Load Regulation
101 = 1.SA
103 = 20 --> 50mA
Load Regulation
= 1.SA
= 20 --, SOmA
101
102
Efficiency
= 103 =
Vi = 25V
102 = SOmA
102
Vi = 2SV
103 = 100mA
SOmA
70
%
5/10
481
APPLICATION NOTE
THE L296 AND L4960 HIGH POWER SWITCHING REGULATORS
The SGS THOMSON L296 is a monolithic stepdown
switching regulator assembled in the 15-pin Multiwatt package. Operating with supply input voltages
up to 46V it provides a regulated 4A output variable
from 5.W to 40V.
Internally the device is equipped with current limiter,
soft start and reset (or power fail) functions, making
it particularly suitable for supplying microprocessors
and logic.
'The preCision of the L296's internal reference
(± 2%) eliminates the need for external dividers or
trinning to obtain a 5V output.
The synchronization pin allows synchronous operation of several devices at the same frequency to
avoid generating undesirable beat frequencies.
The L4960 is a similar device assembled in the 7lead Heptawatt package. Like the L296 it has a
maximum input voltage of 46V and it provides a
regulated output voltage variable from 5V to 40V
with a maximum load current of 2.5A. Current limiting, soft start and thermal protection functions are
included.
Equating these expression and assuming that the
transistor and diode are ideal we obtain:
TON is the conduction time
TON
Vo=Vi' -Tof the transistor
T is the oscillator period
The absolute average current in the supply is there'
fore:
lioc = 10
,
T~N
Once the working frequency and desired ripple current have been fixed the value of the inductor L is
given by :
L=
(Vi-Vo)Vo
Vi f ~ IL
and the value of the capacitor C required to give the
desired output voltage ripple (~ V) is :
C- (Vi-Vo)Vo
- 8 L f2 ~ fo
This capacitor must have a maximum ESR given
by:
.
~Vo
ESRMAX=-~IL
The thermal protection circuit in both the L296 and
L4960 has a hysteresis of 30°C to allow soft restartingafter a .fault condition.
And, finally, the minimum load current, IOMIN, must
be:
~IL
(Vi - Vol Vo
IOMIN= 2 =
2 Vi fL
THE STEP DOWN CONFIGURATION
Figure 5 : Basic STEP-DOWN Configuration.
Figure 5 shows the basic structure of a step down
switching regulator. The transistor Q is used as a
switch and the ON and OFF times are determined
by the control circuit.
When Q is saturated current flows· from the supply,
Vi, to the load through the inductor L. Neglecting the
saturation voltage of Q, Ve =: Vi.
When Q is OFF, current continues to flow in the inductor L, in the same direction, forcing the diode into
conduction immediately therefore Ve is negative. In
these conditions the load current flows through L
and D.
The·average value of the current in the inductor is
equal to the load current. In the inductor a triangular current ripple equal to . ~IL is added to this average current.
VE
l
'l
;c
RI
1
v,
01
ESR
;0
Rl
I
During the tirne when Q is ON this ripple is :
~lL=
(Vi-Vo)ToN
L
and when Q is off it is :
Vo' TOFF
L
6/10
482
VR€F
LOAD
ILOAO
APPLICATION NOTE
30W DC-DC CONVERTER
even by designers with little experience and allows
the convenience of working with low voltages, Offline switching supplies are only preferable when the
weight and size of the mains transformer in a DCDC converter would be excessive.
Designing power supplies in the 30-40W range is
becoming increasingly difficult because it is here
that there is the greatest need to maintain performance levels and reduce costs. The application proposed here is very competitive because it exploits
new ICs to reduce size, number of components and
assembly costs.
This solution, the DC-DC converter, compares very
favourable with off-line switching supplies in terms
of cost. DC-DC converters can, in fact, be realized
In this circuit, figure 6 two devices are used, an L296
and an L4960. The L296 is used, to supply a 5V output with a current of 3A and the auxiliary - 5V/1 OOmA
output and the L4960 is used to provide the 12V/1.5A
output and the auxiliary - 12V/1 OOmA output.
Figure 6 : Multioutput DC-DC Converter with L296 and L4960 (5V I 3A, 12V / 1.5A, -12V/1 OOmA,
-5V/100mA).
20V!!-:;Vi~40V
0 - - - . . -..--.-T""---,
JOO"":r
SOV
EYf
:r
470
~f
SGS~.:-ll r--l
OR
BYWBO
II
-5.2V
.l2
lNS822
0.1 A
~-~--~-.----O
9
L296
lKll
10
3Jn,
:I
12
14
1000/0J'
T
2SV
•
EKR
lKll
RESET
13
2A
seR
I
I
9.1
Kn
L4960
S-&07311
7/10
483
APPLICATION NOTE
Table 5 shows the performance obtai ned with this power supply.
TableS.
Parameter
Output Voltage
101 =3A
102 = 100mA
Vi = 30V
103 = 1.5A
104 = 100mA
Output Ripple
V0 1
V02
V03
V0 4
Unit
5.080
- 5010
11.96
12.00
V
50
30
50
40
mV
15
10
20
mV
Line Regulation
101 .. 1A
103 = 0.5A
20V:;; Vi:;; 40V
102 = 100mA
104 = 100mA
13
Load Regulation
101 = lA to 3A
Vi = 30V
102 = 100mA
8
103 = 0.5 to 1.5A
104 = 100mA
Load Regulation
101 =3A
Vi = 30V
102 = 50
103 = 1.5A
104 = 50 -> 100mA
Load Regulation
Vi = 30V
102 = 50
101 = 1A
->
->
104 = 50 -> 100mA
Line Regulation
101 =3A
20:;; Vi:;; 40V
102 = 100mA
103 = 1.5A
104
80
mV
0
100
mV
mV
35
15
mV
0
90
15
40
45
IOOmV OF
HYSTERESIS
I
AN INTERRUPTioN
OF SUPl'LY CAUSES
RESEI OF MICRO
+
/
- j -- - -.:-...-----
I
I
8/10
484
AT POWER OOWN
. MICRO IS INHIBITED
IMMEDIATELY
-------
MONITORED
VOLTAGE
RESET
OUTPUT
mV
If a power fail function is required in place ofthe reset
function the figure 6 circuit should be modified as
shown in figure 8.
Figure 7 : Reset Output Waveforms.
OUTPUT NOW
STABLE,RESET
GOES ttlGtl
mV
mV
= 100mA
This application illustrates how two devices may be
synchronized. Note also that the reset Circuit is used
in this case to monitor the output voltage (see
figure 7):
3
100
0
100mA
mV
90
0
100mA
103 = 0.5A
.
APPLICATION NOTE
Figure 8.
RESET
OUT
12
l296
I
5-677.
CALCULATING THE POWER FAIL TIME
quired to maintain the regulated output (see
figure 9). From this definition we can evaluate
the energy balance.
The 'power fail time' is defined as the time from when
the power fail output (-pin 14) goes low to the time
when the input voltage falls to the minimum level reFigure 9.
Vi
I
I
I
t PF
L
1
P.F. WAVE fORM
I
(PIN 14)
I
I
I
I
I
I
I
-+t-0ELAY RESET
5-8074
9/10
485
APPLICATION NOTE
The energy which the filter capacitor C supplies to
the operating device while it discharges is :
E = 1/2 C (Vj2_ Vl)
(1)
The load drains a power of Po = Vo 10 . Taking into
consideration the average efficiency T\ (derived with
the input between Vj and V2), the power to be supplied at the input of the device is :
Po
P0 2= (2)
T\
Equating the expressions (1) and (2) gives:
2
2
Po
1/2 C (Vj - V2 ) = . tPF
Since the filter capacitor can have a high value and
be charged to high voltages the choice of SCR is
important. The type used in this circuit - the
TYP512 - is a plastic packaged SCR able to handle
12 Arms and 300A for 1Oms. The maximum forward
and reverse voltages are about 50V.
If the crowbar circuit is not used it is advisable to
connect pin 1 to ground or pin 10.
Figure 10 : Load Current in Short Circuit Conditions
(Vi = 40V, L = 300!-lH, f = 100KHz).
T\
where Vi is the input voltage at which the voltage on
pin 12 reaches 5V (through the divider Rj/R2) ; V2
is the maximum input voltage below which the device no longer regulates.
Rearranging this expression to obtain C :
2 Po tPF
C = T\ (Vj 2 _ V22)
EXAMPLE - Suppose that Vo = 5V, 10 = 3A,
Tpf = 10ms and Vi = 35V. Fixing Vj = 25V and
V2 = 10V we obtain:
_
2 Po tPF
_ 2 x 15 x 10 . 10-3 _
F
C - T\ (Vj 2 _ Vl) - 0.75 (25 2 -102) - 760!-l
t: 5ms/div
Current at Pin 2 when the Output is
Short Circuited.
We obtain choose a capacitor of 1000!-lF.
CROWBAR
The L296 includes an internal crowbar function; the
only external component needed is an SCR. The intervention threshold of this block is fixed intemally
at 20% of the nominal value of the internal reference.
In the figure 6 circuit the SCR is triggered by an overvoltage on the 5V output (usually the most important output to monitor) and shortcircuits to ground the
5V output and, through the diode which connects
the two outputs, the 12V output.
Since the intemal current limiter in the device is designed to function as shown in figure 10 (that is, with
pulsed output current) the SCR turns off in the gap
between pulses and is re-activated gain if, when the
device restarts softly, the fault condition has not
been eliminated. But if the fault no longef"exists the
SCR remains OFF and the output voltage returns to
the normal value.
If the designer prefers the supply to remain off after
the SCR has been activated the circuit can be modified as shown in figure 11. In this modification, when
the SCR is triggered a very high current flows in the
fuse, blowing it.
10/10
486
t: 5ms/div
Figure 11.
FUSE
V;
a-r=')-- 5 kn, td is small compared to Ie, and:
f~
1
~~
0.55 RT CT
RT CT
APPLICATION NOTE
During the discharge time, the internal clock signal
blanks the output to the low state. Therefore, td limits
maximum duty cycle (DMAx) to :
te
td
DMAx = - - - = 1 - - te + td
1:
where 1: = 1/f = switching period.
The timing capacitor discharge current is not tightly
controlled, so td rnay vary somewhat over tempera-
ture and from unit to unit. Therefore, when very precise. duty cycle limiting is required, the circuit of
figure 7b is recommended.
One or more UC3842 oscillators can be synchronized to an extemal clock as shown in figure 8.
Noise immunity is enhanced if the free-running oscillator frequency (f = 1/(tc + ld)) is programmed to
be _ 20 % less than the clock frequency.
Figure 7 : (a) Oscillator Timing Connections and (b) Circuit for Limiting Duty Cycle.
NE555
OI~CH
1
TRIG 2
GROUND
5
(a)
(b)
O
tc
MAX = (IH + IL)
IH = 0.693 (RA + Rs) C
IL = 0.693 Rs C
Figure 8 : Synchronization to an External Clock.
I
, - - - vREF
l
EXTERNAL
CLOCK
JlJU
Rr
v;
UC3842
f - - - Ryley
..
O.~:/JF
~
..
~ cr
GND
l
47ft
_i~-1'1l
ERROR AMPLIFIER
The error amplifier (ElA) configuration is shown in
figure 9. The non-inverting input is not brought out
to a pin, .but is internally biased to 2.5 V ± 2 %. The
EIA output is available at pin 1 for external compensation, allowing the user to control the converter's
closed-loop frequency response.
Figure 1Oa shows an EIA compensation circuit suitable for stabilizing any current-mode controlled topology except for fly back and boost converters
operating with continuous inductor. current. The
feedback components add a pole to the loop transfer function at fp = 112 nRt Ct. Rt and Ct are chosen
so that this pole cancels the zero of the output filter
capacitor ESR in the power circuit. Ri and Rt fix the
low-frequency gain. They are chosen to provide as
much gain as possible while still allowing the pole
formed by the output filter capacitor and load to roll
off the ioop gain to unity (OdS) at f ~ fsw itehi ng/4. This
technique insures converter stability while providing
good dynamic response.
Continuous-inductor-current boost and flyback
converters each have a right-half-plane zero in their
transfer function. An additionai compensation pole
is needed to roll off loop gain at a frequency less
than that of the RHP zero. Rp and Cp in the circuit
of figure 1Ob provide this pole.
5/15
491
APPLICATION NOTE
The E/A output will source 0.5 mA and sink 2 mAo A
lower limit for Rt is given by :
It is therefore desirable to keep the value of Ai as
low as possible.
VElA OUT(max) - 2.5 V = 6 V - 2.5 V 7 kQ
Figure 11 shows the open-loop frequency response
of the UC3842 E/A. The gain represent an upper
limit on the gain of the compensated EI A. Phase lag
increases rapidly as frequency exceeds 1 MHz due
to second-order poles at - 10 MHz and above.
Rt (MIN)
0.5mA
0.5mA
E/A input bias current (211A max) flows through Ri,
resulting in a DC error in output voltage (Va) given
by:
~
Va(max) = (21!A) Ri
Figure 9 : UC3842 Error Amplifier.
s_ 7108
Figure 10 : (a) Error Amplifier Compensation Addition Pole and (b) Needed for Continu
ous Inductor-current Boost ad Flyback.
Figure 11 : Error Amplifier Open-loop Frequency
Response.
PHASE
G"
C·)
(dB )
~~
60
"-
(a)
40
2.50V
~
0
·45
"0
";:K
"\II
~.
10
(b)
2.S0V
6/15
492
100
He.
10K
lOOK
1M
f{Hz)
'"
180
APPLICATION NOTE
CURRENT SENSING AND LIMITING
The UC3842 current sense input is configured as
shown in figure 12. Current-to-voltage conversion is
done externally with ground-referenced resistor Rs.
Under normal operation the peak voltage across Rs
is controlled by the ElA according to the following
relation:
VRS (pk) = Vc - 1.4 V
3
where: Vc = control voltage = E/A output Voltage.
Rs can be connected to the power circuit directly or
through a current transformer, as figure 13 illustrates. While a direct connection is simpler, a transformer can reduce power dissipation in Rs, reduce
errors caused by the base current, and provide level
shifting to eliminate the restraint of ground-reference sensing. The relation between Vc and peak
current in the power stage is given by :
.
VRs(pk)
N
l(pk)=N(
Rs
)= 3Rs(Vc- 1.4)
For purposes of small-signal analysis, the controlto-sensed-cu rrent gain is :
i(pk) _ _N_
Vc - 3 Rs
When sensing current in series with the power transistor, as shown in figure 13, current waveform will
often have a large spike at its leading edge. This is
due to rectifier recovery and/or interwinding capacitance in the power transformer. If unattenuated
this transient can prematurely terminate the output
pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant
should be approximately equal to the current spike
duration (usually a few hundred nanoseconds).
The inverting input to the UC3842 current-sense
comparator is internally clamped to 1 V (figure 12).
Current limiting occurs if the voltage at pin 3 reaches
this threshold value, i.e. the current limit is defined
by:
N·1 V
iMAX =
Rs
where: N = current sense transformer turns ratio.
= 1 when transformer not used.
Figure 12 : Current Sensing.
2R
IV
R
S _7109
7/15
493
APPLICATION NOTE
Figure 13: Transformer-coupled Current Sensing.
Figure 14 : Output Cross-conduction.
uc
3842
I)_781S
200ns/div.
TOTEM-POLE OUTPUT
SHUTDOWN TECHNIQUES
The UC3842 has a single totem-pole output. The
outputtransistors can be operated to ± 1 A peak current and ± 200 rnA average current. The peak current is self-limiting, so no series current-limiting
resistor is needed when driving a power MOS gate.
Shutdown of the UC3842 can be accomplished by
two methods ; either raise pin 3 above 1 V or pull
pin 1 below 1 V. Either method causes the output of
the PWM comparator to be high (refer to block diagram, figure 4). The PWM latch is reset dominant
so that the output will remain low until the first clock
pulse following removal of the shutdown signal at
pin 1 or pin 3. As shown in figure 18, an externally
latched shutdown can be accomplished by adding
an SCR which will be reset by cycling Vcc below the
lower under-voltage lockout threshold (10 V). At this
point all internal bias is removed, allowing the SCR
to reset.
Cross-conduction between the output transistors is
minimal, as figure 14 shows. The average added
power due to cross-conduction with Vi = 30 V is only
80 mW at 200 kHz.
Figures 15-17 show suggested circuits for driving
POWERMOS and bipolar transistors with the
UC3842 output. The simple circuit of figure 15 can
be used when the control IC is not electrically isolated from the power MOS. Series resistor R1 provides damping for a parasitic tank circuit formed by
the power MOS input capacitance and any series
wiring inductance. Resistor R2 shunts output leakage currents (1 0 ~ maximum) to ground when the
under-voltage lockout is active. Figure 16 shows an
isolated power MOS drive circuit which is appropriate when the drive signal must be levelshifted or
transmitted across an isolation boundary. Bipolar
transistors can be driven effectively with the circuit
of figure 17. Resistors R1 and R2 fix the on-state
base current. Capacitor C1 provides a negative base
current pulse to remove stored charge at turn-off.
PWMLATCH
This flip-flop, shown in figure 4, ensures that only a
single pulse appears at the UC3842 output in any
one oscillator period. Excessive power transistor
dissipation and potential saturation of magnetic elements are thereby averted.
8/15
494
Figure 15: Direct POWERMOS Drive.
12 t020V
UPS42
1 t0511
OUT~6~~~--~---4(~~
R1
GND
5
~-181f1
APPLICATION NOTE
Figure 16: Isolated POWERMOS Drive.
18 to 30Y
FERROXCUBE
1811
LOO-3ca
.1.
S_7817
Figure 17 : Bipolar Drive with Negative Turn-off Bias.
12to30V
UC3842
OUT~6~-I~--~---I-'--~--~
GND
,::»-78]8
AVOIDING COMMON PITFALLS
Current-mode controlled converters can exhibit performance peculiarities under certain operating conditions. This section explains these situations and
how to correct them when using the UC3842.
SLOPE COMPENSATION PREVENTS INSTABILITIES
It is well documented that current-mode controlled
converters can exhibit subharmonic oscillations
when operated at duty cycles greater than 50 %.
Fortunately, a simple technique (usually requiring
only a single resistor to implement) exists which corrects ihis problem and at the same time improves
converter performance in other respects. This
"slope compensation" technique is described in detail in Reference 6. It should be noted that "duty
cycle" here refers to output pulse width divided by
oscillator period, even in push-pull designs where
the transformer period is twice that of the oscillator.
Therefore, push-pull circuits will almost always require slope compensation to prevent subharmonic
oscillation.
9/15
495
APPLICATION NOTE
Figure 18: Shutdown Achieved by
(a) Pulling Pin 3 High
(b) Pulling Pin 1 Low.
(a)
UC381,2
SHUTDOWN
TO CURRENT
SENSE RESISTOR
(b)
most easily derived from the control chip oscillator
as shown in figure 20a. The sawtooth slope in figure
19b is m = m2l2. This particular slope value is significant in that it yields "perfect" current-mode control;
i.e. with m2/2 the average inductor current follows
the control signal so that, in the small-signal analysis, the inductor acts as a controlled current
source. All current-mode controlled converters having continuous inductor current therefore benefit
from this amount of slope compensation, whether
or not they operate above 50 % duty.
More slope is needed to prevent subharmonic oscillations at high duty cycles. With slope m = m2,
such oscillations will not occur if the error amplifier
gain (AV(E/A)) at half the switching frequency (fsl2) is
kept below a threshold value (reference 6) :
it 2 Co
Av (EtA)
<---c4-,,-m=m2
f = fsl2
where:
UC3842
SHUTDOWN
Figure 19 illustrates the slope compensation technique. In figure 19a the uncompensated control voltage and current sense waveforms are shown as a
reference. Current is often ·sensed in series with the
switching transistor for buck-derived topologies. In
this case, the current sense signal does not track
the decaying inductor current when the transistor is
off, so dashed lines indicate this inductor current.
The negative inductor current slope is fixed by the
values of output voltage (Va) and inductance (L) :
diL
VL
-VF-Vo
-(VF+Vo)
dt =-L-=
L
L
where : VF = forward voltage drop across the freewheeling diode. The actual slope (m2) of the dashed
lines in figure 19a is given by:
.
Rs
diL
- Rs (VF + Va)
m2=~· Cit =
NL
where: Rs and N are aefined as the "Current Sensing" section of this paper.
In figure 19b, a sawtooth voltage with slope m has
been added to the control signal. The sawtooth is
synchronized with the PWM clock, and practice is
10/15
496
Co = sum of filter and load capacitance
" = llfs
Slope compensation can also improve the noise immunity of a current-mode controlled supply. When
the inductor ripple current is small compared to the
average current (as in figure 19a), a small amount
of noise on the current sense or control signals can
cause a large pUlse-width jitter. The magnitude of
this jitter varies inversely with the difference in slope
of the two signals. By adding slope as in figure 19b,
the jitter is reduced. In noisy environments it is
sometimes necessary to add slope m > m2 in order
to correct this problem. However, as m increases
beyond m = m2l2, the circuit becomes less perfectly current controlled. A complex trade-off is then required ; for very noisy circuits the optimum amount
of slope compensation is best found empirically.
Once the required slope is determined, the value of
RSLOPE in figure 20a can be calculated:
_
3m-
0.7 V
"VRAMP •
_
"tRAMP
AVIE/A) -
'tI2
( RSLOPE) =
Z, I f,
~ ( RSLOPE
t
Z, I fs
)
3m"
RSLOPE = - - - (ZF I fs) = 2.1 . m . " . ZF I fs
1.4
.
where: ZFI fs is the E/A feedback impedance at the
switching frequency.
For m·= mL : il'tRAMP
+ Vol ) ZF I fs
RSLOPE = 1.7 " ( Rs (VF
NL
APPLICATION NOTE
Figure 19 : Slope Compensation Waveforms:
(a) No Compo
(b) Compo Added to Control Voltage.
(c) Compo Added to Current Sense.
L_
INDUCTOR
CURRENT
CURRENT SENSE
(TRANSISTOR CURRENT)
(a)
~ INDUCTOR
C.uRRE.NT
(b)
CURRENT
SENSE
I
TRANSI STOR
i.--::-- CURRENT
~_1829
Note that in order for the error amplifier to accurately replicate the ramp, ZF must be constant over the
frequency range fs to at least 3 fs.
For m = m2:
In order to eliminate this last constraint, an alternative method of slope compensation is shown in
figures 19c and 20b. Here the artificial slope is
added to the current sense waveform rather than
subtracted from the control signal. The magnitude
of the added slope still relates to the downslope of
inductor current as described above. The requirement for RSLOPE is now:
RSLOPE loads the UC3842 RT/CT terminal so as to
cause a decrease in oscillator frequency. If
RSLOPE » RT then the frequency can be corrected
by decreasing RT slightly. However, with
RSLOPE $ 5 RT the linearity of the ramp degrades
noticeably, causing over-compensation of the supply at low duty cycles. This can be avoided by driving RSLOPE with an emitter-follower as shown in
figure 21.
m
=
LlVRAMP (
Rf
)
LltRAMP
Rf + RSLOPE
=
0.7 (
Rf
,12
Rf + RSLOPE
1.4 NL
RSLOPE = Rf ( Rs (VF + Vo)
't
-1)
.
1.4 Rf
R ( 1.4
1)
RSLOPE = - - - - Rf = f - - -
mt
mt
11115
497
APPLICATION NOTE
Figure 20 : Slope Compensation Added (a) to Control Signal or (b) to Current Sense Waveform.
(a)
8 "REF
ZF
1
2.50V
UC3842
5 -7830
(b)
I
--l:
"SENSE
I
C,
FRO~
(/A
UC3842
5-78]1
Figure 21 : Emitter-follower Minimizes Load at
RT/CT Terminal.
8 VRH
",
2N2222
~
RSlOPE.
4 Ryley
i
C
'
2or3
UC3842
12/15
498
NOISE
As mentioned earlier, noise on the current sense or
control signals can cause significant pulse-width jitter, particularly with continuous-inductor-current designs. While slope compensation helps alleviate this
problem, a better solution is to minimize the amount
of noise. In general, noise immunity improves as impedance decrease at critical points in a circuit.
One such point for a switching supply is the ground
line. Small wiring inductances between various
ground points on a PC board can support commonmode noise with sufficient amplitude to interfere with
correct operation of the modulating IC. A copper
ground plane and separate return lines for high-current paths greatly reduce common-mode noise.
APPLICATION NOTE
Note that the UC3842 has a single ground pin. High
sink currents in the output therefore cannot be returned separately.
Ceramic bypass capacitors (0.1 flF) from VI and
ground will provide low-impedance paths for
high frequency transients at those points. The input
to the error amplifier, however, is a high-impedance
point which cannot be bypassed without affecting
the dynamic response of the power supply. Therefore, care should be taken to layout the board in
such a way that the feedback path is far removed
from noise generating components such as the power transistor(s).
VREF to
Figure 22a illustrates another common noise-induced problem. When the power transistor tu rns off,
a noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles the voltage at RT/CT is approaching its threshold level (- 2.7 V, established by
the internal oscillator circui\i when this spike occurs.
A spike of sufficient amplitude will prematurely trip
the oscillator as shown by the' dashed lines. In order
to minimize the noise spike, choose CT as large as
possible, remembering that deadtime increases
with CT. It is recommended that CT never be less
than - 1000 pF. Often the noise which causes this
problem is caused by the output (pin 6) being pulled
below ground at turn-off by external parasitics. This
is particularly true when driving POWERMOS. A
diode clamp from ground to pin 6 will prevent such
output noise from feeding to the oscillator. If these
measures fail to correct the problem, the oscillator
frequency can always be stabilized with an external
clock. Using the circuit of figure 8 results in an RT/CT
waveform like that of figure 22b. Here the oscillator
is much more immune to noise because the ramp
voltage never closely approaches the internal threshold.
Figure 22 : (a) Noise on Pin 4 Can Cause Oscillator to Pre-trigger.
(b) With External Sync. Noise Does not Approach threshold Level.
INTERNAL
THRESHOLD
--'--V-----A----=.-tl- '"" .. ~
NOISE INDUCED
OSCILLATOR PRE- FI RING
J
\ rF--'"""' ~
<; -7flll
(a)
MAXIMUM OPERATING FREQUENCY
Since output deadtime varies directly with CT, the
restraint on minimum CT (1000 pF) mentioned
above results in a minimum deadtime varies for the
UC3842. This minimum deadtime varies with RT
and therefore with frequency, as shown in figure 23.
Above 100 kHz, the deadtime significantly reduces
the maximum duty cycle obtainable at the UC3842
output (also show in figure 23). Circuits not requiring large duty cycles, such as the forward converter
and flyback topologies, could operate as high as 500
kHz. Operation at higher frequencies is not recom-
(b)
mended because the deadtime become less predictable.
The speed 'of the UC3842 current sense section
poses an additional constraint on maximum operating frequency. A maximum current sense delay of
400 ns represents 10 % of the switching period at
250 kHz and 20 % at 500 kHz. Magnetic components must not saturate as the current continues to
rise during this delay period, and power semiconductors must be chosen to handle the resulting peak
currents. In short, above - 250 kHz, may of the advantages of higher-frequency operation are lost.
13/15
499
APPLICATION NOTE
Figure 23 : Deadtime and Maximum Obtainable Duty-cycle vs. Frequency with Minimum Recommended
CT.
'd
100
\---+--+--+-----t-----i(.,.)
\---+-- -+--+--~---1
650
~-+-----l
(ns)
100
200
CIRCUIT EXAMPLES
1. OFF-LINE FLYBACK
Figure 24 shows a 25 W mUltiple-output off-line flyback regulator controlled with the UC3842. This
regulator is low in cost because it uses only two
magnetic elements, a primary-side voltage sensing
technique, and an inexpensive control circuit. Specifications are listed below.
SPECIFICATIONS:
Une Isolation:
3750 V
Switching Frequency:
40 kHz
Efficiency @ full load :
70 %
Input Voltage
95 VACto 130 VAC
(50Hz/60Hz)
Output Voltage:
A. + 5 V, 5 % : 1 A to 4 A load
Ripple voltage: 50 mV
P-P Max.
B. +12V,3%:0.1 AtoO.3A
load
Ripple voltage: 100 mV
P-PMax
. C. -12V,3%0.1 AtoO.3A
load
Ripple voltage : 100mV
P-PMax
14/15
500
r:::.c:'==---
300
400 1(KHz)
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TI:CDILCRAFT [-4140-8
PRIMARV-97TURNS
SINGLE AWG 24
SECONDARY·4 TURNS
4 PARALLEL AWG 22
2.SKD.
VF8
:!III:
lil(g
(1)
~
1I7V
!I! III
~
:r
"T1
AC INPUT
'.~
:E
~
IW
~
~
CONTROL -9 TURNS
J PARALLEL AWG 28
•
l.
~
I
I
I
I
I
I
UC1842
81
I
VREF
CUR
SEN
IOKII
RT/C T
IKn
I
I"70pF
GND
•
I
I
I
Cl.l5D.
I
I
I
I
~
"C
"C
ISOlATION
BOUNDARY
C
5-10\\
o
~
::!
oz
z
o
01
....
II.!!
~
01
o-I
m
APPLICATION NOTE
A 25W OFF-LINE FL YBACK SWITCHING REGULATOR
INTRODUCTION
This note describes a low cost switching power supply for applications requiring multiple output voltages, e.g. personal computers, instruments, etc ...
The discontinuous mode flyback regulator used in
this application provides good voltage tracking between outputs, which allows the use of primary side
voltage sensing. This sensing technique reduces
costs by eliminating the need for an isolated.secondary feedback loop.
The low cost, (8 pin) UC1842 current mode control
chip employed in this power supply provides performance advantages such as :
1) Fast transient response
2) Pulse by pulse current limiting
3) Stable operation
To simplify drive circuit requirements, a TO-220
power MOS SGSP369 is utilized for the power
switch. This switch is driven directly from the output
.
of the control chip.
POWER SUPPLY SPECIFICATIONS
1. Input voltage: 95VAC to 130VAC (50 Hz/60 Hz)
2. Output voltage:
A. + 5 V, ± 5 % :1 A to 4 A load
Ripple voltage: 50 mV P-P Max
B. + 12 V, ± 3 % : 0.1 A to 0.3 A load
Ripple voltage: 100 mV P-P Max
C. - 12 V, ± 3 % : 0.1 A to 0.3 A load
Ripple voltage: 100 mV P-P Max
across C2 reaches a level of 16 V the output of IC1
is enabled, turning on power MOS 01.
During the on time of 01 , energy is stored in the air
gap of transformer (inductor) T1. At this time the polarity of the output windings is such that all output
rectifiers are reverse biased and no energy is transferred. Primary current is sensed by a resistor, R1 0,
and compared to a fixed 1 V reference inside IC1.
When this level is reached, 01 .is turned off and the
polarity of all transformer windings reverses, forward biasing the output rectifiers. All the energy
stored is now transferred to the output capacitors.
Many cycles of this store/release action are needed
to charge the outputs to their respective Voltages.
Note that C2 must have enough energy stored initially to keep the control circuitry operating until C4
is charged to a level of approximately 13 V. The voltage across C4 is fed through a voltage divider to the
error amplifier (pin 2) and compared to an internal
2.5 V reference.
Energy stored in the leakage inductance of T1
. causes a voltage spike which be added to the normal reset voltage across T1 when 01 turns off. The
clamp consisting of 04, C9 and R12 limits this voltage excursion from exceeding the BVDSS rating of
01. In addition, a turn-off snubber made up of 05,
C8 and R11 keeps power dissipation in 01 low by
delaying the voltage rise until drain current has decreased from its peak value. This snubber also
damps out any ringing which may occur dueto parasitics.
BASIC CIRCUIT OPERATION
Less than 3.5 % line and load regulation is achieved
by loading the output of the control winding Nc, with
R9. This resistor dissipates the leakage energy associated with this winding. Note that R9 must be isolated from R2 with diode 02, otherwise C2 could not
charge to the 16 V necessary for initial start-up.
The 117VAC input line voltage is rectified and
smoothed to provide DC operating voltage for the
circuit. When power is initially applied to the circuit,
capacitor C2 charges through R2. When the voltage
A small filter inductor in the 5 V secondary is added
to reduce output ripple voltage to less than 50 mV.
This inductor also attenuates any high frequency
noise.-
3. Line Isolation: 3750 V
4. Switching Frequency: 40 KHz
5. Efficiency @ Full Load: 70 %
AN247/1188
1/5
503
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m
APPLICATION NOTE
Figure 2 : Block Diagram: UC1842 Current Mode Controller.
Vi
I-.,...---+---~--~- ~~
- ---VREf
,>v
50mA
GROUND
2 SOV
6
--D
OUTPU T
2R
R
COMP
0---------'
3
0-------------CURRENT
SENSE
TYPICAL SWITCHING WAVEFORMS
Upper trace: 01 - Gate to source voltage
Lower trace: 01 - Gate Current
3/5
505
APPLICATION NOTE
TYPICAL SWITCHING WAVEFORMS
.,
Upper trace: 01 - Drai'n.tq source voltage
Lower trace: Primary current- ID
;.
Upper, tr!lce:~5V charging current
Lower trace.: 5V output ripple voltage
+
PERFORMANCE DATA
5 V out
12 V out
- 12 V out
+ 5 V@ 1.0. A
4.0. A
5.21.1
4.854
12.0.5
12.19
-12.0.1
-12.14
+ 5 V@ 1.0. A
4.0. A
5.199
4.950.
11.73
11.68
-11.69
-11.63
± 12@ 10.0. rnA
+ 5 V@ 1.O..A
4.Q A
5.220.
4.875
12.0.7
12.23
-12.0.3
-12.18
± ,12@30.0. rnA
+5V@1.O.A
4.0. A
'5.20.8
4.90.6
11.73
11.67
-11.68
- i1.62
± 12@ 10.0. rnA
+ 5 V@ 1.0. A
4.0. A
5.20.7
4.855
12.0.6'
12.21
-12.0.2
-12.15
± 12 V@30.0. rnA
+ 5 V@ 1.0. A
4.0. A
5.20.0.
4.90.2
11.71
11.66
- 11.67
11.61
± 3:5 %
± 2.3·.%
f:2.4°ic,
Conditions
Low Line (95 VAG)
± 12@ 10.0. rnA
± 12@30.0. rnA
Nominal Line (120. VAG)
High Line (130. VAG)
Overall Line and Load Regulation
4/5
506
APPLICATION NOTE
APPENDIX POWER TRANSFORMER - T1
Core: Ferroxcube EC-35/3C8
Gap: 0.25mm. in each outer leg
Note: For reduced EMI put gap in center leg only.
UseO.5mm.
5 - 1931
TRANSFORMER CONSTRUCTION
CONTROL WINDING
N:10.AWG JO(O.25mm)
2 IN PARALLEL
2 LAYERS 3M MYLAR TAPE
2 LAYERS. 3M MYLAR TAPE
",,2v WINDINGS N:9. AWG30(O.25mm)
2WIRES IN PARALLEL.
BIFILAR WOUND
~
~RIMARY
":£5. AWG 26Co.£mm)
BOBBIN-lSPCBl
5/5
507
APPLICATION NOTE
FLEXIBLE LOW COST HIGH EFFICIENCY 130W SMPS
USING SGSD00055 AND TEA2018A
By R. LETOR • S. FLERES
ABSTRACT
A low cost, high efficiency, flexible and reliable
130W flyback power supply has been designed
using the new Fastswitch high voltage Darlington
SGSD00055 and the TEA2018A PWM controller.
The advantages of the new Darlington are low cost
together with low switching and driving losses, a
large safe operating area and simple drive requirements.
The TEA2018A provides the SMPS with comprehensive protection whilst using very few components.
The low cost of this design makes it a viable option
for use in personal computers, telecommunication
equipment, battery chargers and TVs.
The example evaluated in this paper is intended for
CTVapplications.
at turn-off, a voltage that standard Darlingtons are
unlikely to be able to handle.
An added advantage of this high voltage capability
is that smaller snubber networks can be used giving reduced dissipation in these networks.
The switch mode power supply characteristics are
summarised in the following table:
Operating
A.C. input
Maximum
Maximum
Outputs:
mode:
voltage:
frequency:
output power:
Line regulation:
Load regulation:
110W efficiency:
non continuous flyback
110/220V ± 15%
25kHz
130W
+ 200V
50mA
500mA
+ 150V
1.5mA
+ 25V
+16V
500mA
.016%/V
.035%/W
82%
INTRODUCTION
CIRCUIT DESCRIPTION
The SGSD00055 is a new 1000V Darlington designed in high voltage planar technology.
Figure 1 shows the complete circuit and component
list.
The main features of this device are fast switching
capability, large reverse safe operating area and
very low cost.
The rectified mains voltage applied to the primary of
the flyback transformer is switched at 20KHz by the
Darlington 01 with a duty cycle of about 30%.
This high efficiency 130W flyback SMPS capitalises
on the features of this transistor to produce a highly reliable power supply.
During the on-state the base current value depends
upon the collector current, the TEA2018A performing the proportional base drive.
By adding to this' the facilities offered by the
TEA2018A, significant component reduction can be
made whilst retaining all the desirable features.
The negative voltage necessary for the turn-off is
provided by the 06, R8, R9, C9 network, which charges the C6 capacitor during the on-state.
The high voltage that the Darlington can withstand
plus the large safe operating area allows the use of
a low cost transformer with high leakage inductance.
At turn-off, the inductor L 1 limits the reverse base
current and prevents the turn-off from being too fast
hence reducing any "tail turn-off" problem.
The leakage inductance of a low cost transformer is
likely to produce voltage spikes in excess of 850V
AN36210689
The snubber network R12, C10, 08 ensures safe
switch off inside the safe operating area and very
low switching losses at turn-off.
1/5
509
APPLICATION NOTE
Figure 1 : 130W SMPS Using SGSD00055.
C28
1101
C3
220
C19
V{J£
200u
15l1li
25U
£:18
.n
161}
COMPONENT LIST
R1
R2trimmer
R3
R4
R5
R6
R7
RS
R9
R10
R11
R12
R13
R14
R15
R16
1K
22K
1K
56K
100K
220K
10K
10
470
2.7
0.33
2.2K
1
0.75
4
100K
L1
4.71lH
C1 -C4
C5
C6
C7
1QF
6S0pF
4.71lF
100ilF
2/5
510
1/4W
1/4W
1/4W
1W
2W
1/4W
CS
C9
C10
C11 -C12
C13-C14
C15
C16
100J,lF
4.71l F
1.SnF
220llF
220llF
10llF
10llF
OZ1
OZ2
01 - 04
05
06
07
OS
09 - 010
011.- 012
Q1
IC1
T1
F1
F2
10V
4.7V
2A250V
1 N4001
BA157
1N4148
BYT13-800
BYW9S
BY299
SGSOOO055
TEA201SA
SAREA 29.6024
0.5 A FUSE
0.5 A FUSE
25V
6.3V
1kV
250V
63V EKA
250V
300V
1W
2W
1/2W
2W
7W
2W
4W
4W
1/2W
1kV
1kV
6.3V
16V
1W
1/2W
Rectifier Bridge
APPLICATION NOTE
Figure 2 shows the power losses in the Darlington
and in R12 as C10 is varied.
The minimum power losses occur when C10 has a
value of 1.0nF.
In fact a value of 1.8nF was used in order to give a
sufficient safety margin at turn-off.
In this way a 1W reduction of the power losses in
the Darlington was obtained (see figure 3).
This in turn reduced the working temperature with a
consequent improvement in reliability. To obtain the
same safety marg in with a 850V Darlington a 2.2nF
capacitor would have to be used for C1 O.
This would result in higher losses. Using the 1000V
Darlington permits the use of a cheaper "Iossy"
transformer as the Darlington itself will withstand the
higher voltage peaks caused by a leakage inductance 4 times greater than the peak that a 850V Darlington can withstand.
The TEA2018A demagnetisation circuit allows the
following features to be designed into the circuit:
_ non-continuous flyback mode for all load
conditions
_ soft start
_ short circuit protection
Figure 3 : Load Line Shape at Turn-off.
Figure 2 : Power Losses vs CSnubber.
PI'tIJ
7
lelA)
6
RB~OA
6
5
4
2
200
2
100
600
BOO
1000
ClnFI
Figure 4 shows the short circuit conditions both with
and without the demagnetisation control. During
normal operation the maximum current is limited by
the current mode control.
When a short circuit occurs without the demagnetisation circuit, the collector current increases until the
transformer core is saturated.
This happens because collector current continues
increasing even after the current limiter intervenes
due to the storage current, at a rate O.25A!~S.
Hence the energy stored in the transformer core
during tstorage eaches a value of about 50~J, while
during the discharge cycle the energy reduces to
about 3~J.
In this application the demagnetisation circuit inhibits the base drive until all the stored energy in the
core of the transformer has been discharged
through the diode, the secondary winding and the
short circuit resistances.
The demagnetisation current behaves in the same
way during start-up avoiding extra currents.
It also ensures non-coniinuous mode operation
under every load condition.
The following figures and photographs illustrate the
performance of this power supply.
3/5
511
APPLICATION NOTE
Figure 4 : Short Circuit Operation.
~ nn n
DRIVING
PULSES
.'.
"
"
II
t."
Ie
COLLECTOR
CURRENT
:'
I.
"
""
(0
""
"
,""
:i
D
II
" H
II
50 liS
to
"
""
:1"
II
r-k
.- __ I
r---_.J
,,..-_.1
c~
t
FLYBACK
.SENSE
without demagnetisation circuit
with demagnetisation circuit
Figure 5a : Efficiency versus Output Power.
Figure 5b : Heatsink Temperature versus Output
Power for Rth (heatsink) a"CIW.
1m we SfofPS
HEATSINKTEl\fP F\h=S CIW
70
4/5
512
80
to
'00
110
1tO
'0
go
100
110
'20
""
APPLICATION NOTE
Photograph 1 : Collector Voltage and Current
Waveforms.
Ie = 1Afdiv
VeE = 100Vfdiv
Vee = 250V
Photograph 3 : Collector and Base Current
at Tum-off.
Ie = 1 Afdiv
IB = O.2A/div
Photograph 5 : Output Ripple on the 25V Output.
V= 200mVfdiv
Photograph 2 : Turn-off Waveforms.
Ic = O.5Afdiv
VeE = 100Vfdiv
Photograph 4 : Transient Response to a step Load
V = 2Vfdiv
CONCLUSIONS
The new 1000V Darlington allows the construction
of a flexible, reliable and low cost switching power
supply.
It has a high efficiency even at low loads due to the
very low driving energy required, the low switching
losses and the reduced snubber losses.
I = 1.5A
5/5
513
APPLICATION NOTE
A SECOND-GENERATION IC SWITCH MODE CONTROLLER
OPTIMIZED FOR HIGH FREQUENCY POWER MOS DRIVE
INTRODUCTION
Since the introduction of the SG1524 in 1976, integrated circuit controllers have played an important
role in the rapid development and exploitation of
high-efficiency switching power supply technology.
The 1524 soon became an industry standard and
was widely second-sourced.
Although this device contained all the basic control
elements required for switching regulator design,
practical power supplies still required other functions which had to be implemented with additional
external discrete circuitry.
An additional development within the semiconductor industry was the introduction of practical Power
Mos which offered the potential of higher efficiencies at higher ,speeds with resultant lower overall
system costs.
In order to be able to take full advantage of the
speed capabilities of power MOS, it was necessary
to provide high peak currents to the gate during turnon and turn-off to quickly charge and discharge the
gate capacitances of 800 to 2000 pF present in
higher current units.
a
The development of second-generation regulating
. PWM IC, the SG1525A, and its complimentary output
version, the SG1527A, was a direct result of the desire
to add more power supply elements to the controllC,
Figure 1 : The SG1524 relating PWM block diagram.
This design was the first complete I.C. control chip for switch mode power supplies.
Vi
150
j GREF.~
1
REG.
'5.
OSc. OUT
]0---··
FLIP
FLOP
-r-'--,
6 ROT_ _ _
CT
osc
7 C)--I--L_~
(RAMP)
COMPENSATION
9O----------~-;
.SENSE
INV. INPUT
N.I.INPUT
.........- - - - - 0 4
ER~ ~-~--------------~
2o---~
SHUTDOWN
IKO
~--~~~J--------------O 10
S-61L411
AN250/1188
1/12
515
APPLICATION NOTE
as well as to optimize the interfacing of high current
power devices.
INTEGRATING MORE POWER SUPPLY
FUNCTIONS
Having achieved the greatest level of acceptance
among users of first generation control chips, the
1524 became the starting point for expanding IC
controller capabilities. This early device, shown in
figure 1, contains a fixed-voltage reference source,
an oscillator which generates both a clock signal and
a linear ramp waveform, a PWM comparator, and a
toggle flip-flop with output gating to switch the PWM
signal alternately between the two outputs.
With this circuitry already defined, a two pronged development effort was initiated : 1) to add additional
features required by most power supply designs and
2) to improve the utility of features already included
within the 1524. The resultant block diagram for the
SG1525A is shown in figure 2. Two general comments should be made relative to the overall block
diagram. First, in optimizing the output stage for bidirectional, low impedance switching, commitments
had to be made as to whether the output should be
high or low during the active, or ON state. Since this
is application defined there are needs for both output
states, so both were developed with the SG1525A
device defined by an output configuration which is
high during the ON pulse, and the SG1527 A configured to remain high during the OFF state. This difference is implemented by a mask option which
eliminates inverterQ4 (see figure 3) forthe SG1527A.
In all other respects, the 1525A and 1527A are identical and any description of the 1525A characteristics
apply equally to the 1527A. Second, a major difference between this new controller and the earlier
1524 is the deletion of the current limit amplifier.
There are so many system considerations in providing current control that it is preferable to leave this as
a user-defined extemal option and allocate the package pins to other, more universally requested functions. Current limiting possibilities are discussed
further under shutdown options.
Figure 2 : The SG1525A family represents a "second generation" of IC controllers.
r-~----------------------------
--I
,
I
Vc
I
-013
V,
150---
GPOUN[)
120---
,...-.-------,
SYNC
RT
, 0---- ... - - - - - I
DlSCHARGf
7 _ _ _ _-
(O~P
C,G1525A OUTPUT STAGE
, o---------~
IN:'~:".'_~
N
j. INf-'UT
2 (r---
Vc
RHOR
AMP.
OUTPUT A
t--+----u'
11
OUTPUT B
~---O".
5KJl
SGIS17A OUTPUT STAGE
L
2/12
516
_
~
____
~
-
-
-
---
-
-
_.-
-
APPLICATION NOTE
"TOTEM-POLE" OUTPUT STAGE
One of the most significant benefits in using the
SG1525A is its output configuration. For the first
time it has been recognized in an IC controller that
it is more difficult to tum a power switch off than turn
it on. With the SG1525A, a high-current, fast transition, low impedance drive is provided for both turnon and turn-off of an external power transistor or
Power MOS. The circuit schematic of one of the two
output stages contained within the device is shown
in figure 3. This is a two-state output, either Os is on,
forming a low saturation voltage pull-down, or 07 is
on, pulling the output up to Vc. Note that Vc is a separate terminal from the Vi supply to the rest of the
device.
This offers the benefits of potentially operating the
output drive from a lower supply than the rest of the
circuit for power efficiencies, decoupling of drive
transients from more sensitive circuits, and a third
terminal for extracting a drive signal. Note that even
though Vc can be set either higher or lower than Vi,
the output cannot rise higher than approximately
1 1/2 volts below Vi.
Figure 3: One of Two Power Output Stages Contained within the SG1525A which Conduct
Altemately due to the Internal Flip-flop.
Vc is shown in figure 4. This transient will normally
be decoupled from the rest of the control power by
a 0.1 j.lF capacitor from Vc to ground but it shou Id
not, otherwise, cause a problem unless very high
frequency operation is contemplated where it will
contribute to overall device power dissipation, by becoming a significant portion of the total duty cycle.
The output saturation characteristics of this stage
are shown in figure 5. The source transistor, 07 is a
straight forward Darlington and its saturation voltage remains between 1 and 2 V out to 400 mA under
the assumption that Vi ~ Vcc. The sink transistor,
Os, however, has a non-uniform characteristic
which needs explanation. At low sink currents, the
1 mA current source through 05 insures a very low
saturation voltage at the output. As load current increases past 50 mA, 08 begins to come out of saturation for lack of base drive but only up to about 2 V.
Here diode 02 becomes forward biased shunting a
portion of the load current through 05 to boost the
base current into 08. With this circuit, the sink transistorcan both support high peak discharge currents
from a capacitive load, as well as insure the low
static hold-off voltage required for bipolar transistors.
Figure 4: Current "spiking" on the Vc terminal caused by conduction overlap between
source and sink is minimized by highspeed design techniques.
Q7
~_~+--{) OUTPUT
A orB
PWM
DSC
F/ F
HORIZONTAL = 500nsIDIV
During the transition between states, there is a slight
conduction overlap between source and sink which
results in a pulse of current flowing from Vc to
ground. However, due to the high-speed design
configuration of this stage, this current spike lasts
for only about 1Dans. A typical current waveform at
A typical output configuration for a push-pull bipolar
transistor power stage is shown in fig. 6. With a
steady state base drive current from the SG1525A
of 100 mA, this stage should be able to switch 1 to
5 A of transformer primary current, depending upon
the choice of transistors. The sum of R1 and R2
3/12
517
APPLICATION NOTE
Figure 5 : The output saturation characteristics of
the SG1525A provide both high drive
current an low hold-off voltage.
Figure 7 : Base current waveforms (figure 6 circuit)
show the enhanced turn-on and turn-off
current possible with the SG1525A.
G-$ll.ltI
VeE
II
(V )
Vi ",20V
-
lamb'" 15-C
-
-
I--~
0.01
~
V
SOURCE SAT.Ve-VOH
5rNt< SAT, VOL
01
IIII
Illi
10 (A)
determine the maximum steady state output current
of the SG 1525Awhile their ratio defines the voltage
across C2which, at turn off, becomes the reverse
VBE for Q1. With the values given, the output current
and voltage waveforms are shown in figure 7 for a
one microsecond pulse. If power MOS are used for
the output switches as shown in figure 8, the interfacing circuitry can become even simpler with only
a small series gate resistor potentially required to
damp spurious oscillations within the power device.
Figure 6 : A Typical Push-pull Converter Power
Stage Using External Bipolar Power
Transistor Switches
R1
fJOn
n
5G1525A
GNO
12
4/12
518
HORIZONTAL = SOOns/DIV
Push-pull direct transformer drive is also particularly advantageous with SG1525A as shown in
figure 9. A version of this configuration is required
for isolation when the control circuit is referenced to
the secondary side of an off-line power system, and
to provide level shifting of drive signals for bridge
and full bridge switching. The configuration of
figure 9 has a couple of important advantages. First,
by connecting the drive transformer primary direct-.
Iy between the outputs of the SG1525A, no centertap is needed and the full primary is driven with
opposite polarities. Secondly, between each output
pulse, both outputs are pulled to ground which effectively shorts the two ends of the primary winding
together coupling a low-impedance turn-off signal to
the switching transistors.
A useful single-ended configuration, typical of buck
regulators, is shown in figure 10. Here the SG1525A
outputs are grounded and the PWM signal is taken.
from the Vc terminal which switches close to ground
during each clock period as the internal source transistors are alternately sequenced.
APPLICATION NOTE
Figure 8 : Replacing bipolar transistors with power
MOS provides even greater simplicity
due to the low driving impedances of the
SG1525A in each transition.
Figure 10 : A single-ended Ground-referenced Power Stage for a Flyback or Boost Regulator.
TO OUTPUT
FILTER
.vs
o~----~-------------.
Rl
T,
A
11
5G1525A
SG 157~A
B 14
GNO
12
5-6.1.1711
s-
6 JJ.B
Figure 9 : The SG 1525A is ideally suited for driving
a low-power base drive transformer and
eliminates the need fora primary centerc
tap.
.v, o-----..---------------~----___,
13
CI
5GIS2SA
GNO
T2
CONTROLLING POWER SUPPLY
START-UP
Although the advantages of the SG1525A's output
stage will often be reason enough for its selection,
there are several other important and useful features
incorporated within this product. One problem pre~iously overlooked in PWM circuits is keeping the
output under control as the supply voltage is turned
on and off. Undefined states, particularly the possibility of turning on an output before the oscillator is
running, can be quite awkward, if not catastrophic.
To prevent this, the SG1525A has incorporated an
under-voltage lockout circuit which effectively clamps
the outputs to the off state with as little as 2 112 V of
supply voltage which is less than the vol-tage required to turn the outputs on. This clamp is maintained until the supply reaches approximately 8 V
insuring that all the remaining SG1525A circuitry is
fully operational prior to enabling the outputs. The
clamp reactivates when the supply is lowered to approximately 7.5 V. There is about 500 mV of hysteresis built in to eliminate clamp oscillation at
threshold.
5/12
519
APPLICATION NOTE
Another important aspect of power sequencing is
restraining the outputs from immediately commanding a 100 % duty cycle when they are activated. This
is accomplished by a slow turn on (soft-start) which
is defined by an internal 50 JlA current source in conjunction with an externally applied capacitor. The
details of this power sequencing system are shown
in figure 11.
03 and 04 are the output gates normally driven by the
oscillator through 02 to provide output blanking between pulses. (One of these transistors is shown as
02 in figure 3). At low supply voltages, 02 conducts
with base drive from the 20 JlAcurrent source. 02 provides three functions. First, current through R4 acti-
vates the output gates with minimum voltage drop~
Second, current through Rs activates the shutdown
transistor 05 holding the soft-start capacitor, Css, discharged. Third, R2 provides a small bucking voltage
across R3 for hysteresis at the switch point.
When the input voltage becomes high enough to
provide a little more than one volt at the base of 01,
that transistor turns on. This tums off 02, activating
the outputs and allowing Css to begin to charge from
the internal 50 JlA current source. The time to reach
approximately 50 % duty cycle will be
t=
( 2 volts )
50 JlA
C
ss
Figure 11 : The Internal Power Turn-on, Soft-start, and Shutdown Circuitry of the SG1525A.
CLOCK
BL"NKING
Vi
VREF
~
D2
02
03
R4
R5
DI
OUTPUT
R2
R3"
10
R6
GATE5
R8
TO PWM
COMPARATOR
I.L
as
5HUTOOWN
(55
TO PWM
LATCH
Q6
s _6~"'1t
POWER SUPPLY SHUTDOWN
An important part of any PWM controller is t~e ability
to shut it down at any time for a variety of reasons,
including system sequencing requirements or fault
protection. Several options are available to the user
of the SG1525A, which require an understanding of
the capability of the shutdown terminal, pin 10.
Referring to figure 11, the base of 05 is turned on
by a signal which is clamped to approximately 1.4 V
by the action of D1 and the VSE of gates 03 and 04.
6112
520
This holds the outputs off and keeps Css discharged
by 05 which, with Rg, becomes a 100 JlA net current
sink.
If, during normal operation, pin 10 is pulled high,
three things happen. First, the outputs are turned off
within 200 ns through 01. Second, the PWM latch
is set by 06 so that eve n if th e sig nal at pi n 10 were
to disappear, the outputs would stay off for the duration of that period, being reset by the next clock
pulse. Third, 05 is activated commencing a 100 JlA
APPLICATION NOTE
discharge of Css. However, if the activation pulse
on pin 10 has a duration shorter than 1/3 of the clock
period, the voltage on Css will remain high and softstart will not be reactivated. Naturally, a fixed signal
on pin 10 will eventually discharge Css, recycling
soft -start.
Thus, the shutdown pin provides both sequencing
capability as well as a convenient port for protective
functions, including pulse-by-pulse current limiting.
REGULATING PWM PERFORMANCE
IMPROVEMENTS
The SG 1525A also offers significant performance
and application improvements in almost all of the
additional basic functions of a PWM over those obtainable with earlier devices. A general description
of these features is outlined below:
REFERENCE REGULATOR
The output voltage of this regulator is intemally
trimmed to 5.1 V ± 1 % during manufacture, eliminating the need for adjusting potentiometers in most applications.
ERROR AMPLIFIER
SG1525A uses the same basic transconductance
amplifier as the SG1524 with an important difference : it is powered by Vi rather than VREF. Now
the input common-mode range includes VREF eliminating the need for a voltage divider with its attendant tolerances. An additional feature relative to the
error amplifier is that the shutdown circuitry feeds
into a separate input to the PWM comparator allowing pulse termination without affecting the output of
the error amplifier which might have a slow recovery,
depending upon the external compensation network selected. An important benefit of a transconductance amplifier is the ease with which its current
mode output can be over-ridden by other external
controlling signals.
PWM COMPARATOR
The significant benefit of the SG1525A's PWM comparator is in its following latch. A common problem
with earlier devices was that any noise or ringing on
the output of the error amplifier would affect multiple
crossings of the oscillator ramp signal resulting in
multiple pulsing at the comparator's output. The
SG1525A's latch terminates the output pulse with
the first signal from the comparator, insuring that
there can be only a single pulse per period, removing all jitter or threshold oscillation from the system.
Another important advantage of this latch is the
ability to easily implement digital or pulse-by-pulse
current limiting by merely momenetarily activating
the shutdown circuitry within the SG1525A. This
could be as simple as connecting pin 10 to a groundreferenced current sensing resistor. For greater accuracy, some added gain may be advantageous.
Once a current signal causes shutdown, the output
will remain terminated for ihe duration of the period,
even though the current signal is now gone. An oscillator clock signal resets the latch to start each period anew.
OSCILLATOR
The functions of the oscillator within the SG1525A
have been broadened in two important aspects.
One is the addition of a synchronization terminal, pin
3, allowing much easier interfacing to an external
clock signal or to synchronize multiple SG1525A's
together. The other is the separation of the oscillator's discharge network from its charging current
source for deadtime control. Reference should be
made to the schematic of figure 12 for an understanding of the operation of this circuit. The heart of
this oscillator is a double-threshold comparator, Q7
and Qs, which allows the timing capacitor to charge
to an upper threshold by means of the current
source defined by RT and mirrored by Q1 and Q2.
The comparator then switches to a lower threshold
by turning on QlO and discharges CT through Q3 and
Q4 with a rate defined by RD. As long as CT is discharging, the clock output is high, blanking the outputs.
Since the overall oscillator frequency is defined by
the sum of the charge and discharge times, there
are three elements now in the frequency equation
which is approximately:
f=
CT (.07 RT + 3 Ro)
External synchronization can easily be accomplished with a 2.8 V positive pulse at pin 3. This will turn
on Qg, lowering the comparator threshold below
wherever the voltage on CT may happen to be. Two
factors should be considered: First, the voltage on
CT determines the amplitude of the PWM ramp, and
if the sync occurs too early, the loop gain will be
higher and the resolution may be worse. Second, the
sync circuit is regenerative within 200 ns ; and, while
a wider pulse can be used, CT will not begin to recharge as long as the sync pin is high. For synchronizing multiple SG1525A devices together, one need
only to define a master with the correct RTCr time
constant, connect its output pin to the slave sync pins,
and set each slave RrCT for a time constant 10-20 %
longer than the master.
7/12
521
APPLICATION NOTE
Figure 12 : A Simplified Schematic of the SG1525A's Oscillator Circuitry,
~EF~________~________~____~~______~~___________
7.4Kn
a7
S RA~P
a8
14KD
------4-------~------------+--------+---4----~~~:M
~-----_{2=K=n~_+--~~
Q9
alo
013
2SKfl
25KQ
DISCHARGE
Cy
OJ
IKQ
CLOCK
~T
Figure 13: 200 W, Off-line Forward Converter.
"
'-ll'
1000
"
" f---------------i
un
'"'
so
lS2SA
0-1.u F
Nln
].91(0
r- ,-'-----'
8/12
522
2On'
APPLICATION NOTE
A 200 WATT,
CONVERTER
OFF-LINE,
FORWARD
The ease of interfacing the SG 1525A into a practical power supply system can be illustrated by the
off-line, power converter shown in figure 13. This
200 W supply places the control circuitry on the primary side of the power transformer where direct
coupling can be used to drive the power switch.
While simplifying the drive electronics, this configuration usually requires an isolated voltage feedback
signal which is most easily accomplished by an optocoupler driven by some type of voltage regulator
IC such as a L 123 or LM723. One other undefined
block in figure 13 is the auxiliary power supply which
supplies the low voltage, low current bias supply for
the SG 1525A and the drive for 01 the power switch.
The choice of the SGSP479 power MaS for this
switch keeps the total power requirements from the
auxiliary supply at less than 1 W ; readily implemented with a small, line-driven transformer.
This converter is designed to operate at 150 kHz
which is accomplished by running the SG1525A at
300 kHz and using only one of the outputs. This also
automatically insures that the duty cycle can never be
greater than 50 %, a requirement of the power transformer in this configuration. The high operating frequency allows the output filter's roll-off to be set at 12
kHz, greatly simplifying the overall loop stability considerations as adequate response can be achieved
with only the single-pole compensation of the error
amplifier provided by the 0.05 IlF capacitor on pin 9.
The totem-pole output of the SG 1525A is used to advantage to drive 01 by providing a 400 mA peak current to charge and discharge the power MaS gate
capacitance while keeping overall power dissipation
low. Waveform photographs of this operation are
shown in figure 14.
Figure 14 : Current and Voltage Waveforms for the
200 W Off-line Forward Converter with a
SG1525A Direct Driven Power MaS
Switch (operating frequency is 150 KHz
with output current equal to 40 A).
0-
0-
0-
1 Ils/div
a) Waveforms of 10. IG. VG
b) Risetime
~ 90 ns
0-
0-
0"":'
c) Falltime
~ 30 ns
9/12
523
APPLICATION NOTE
When operating at full load, the efficiency of this converter is 73 % with by far the greatest power losses
occurring in the output rectifiers-even though
Schottky devices have been selected.
rise time due to Schottky rectifier capacitance.
Current limiting for this converter is provided by·
measuring the current in SGSP479 with the
0.1 Q resistor in series with the source and using
this voltage to activate the shutdown circuitry within
the SG1525A. While this will provide a fast-acting
short circuit protection on a pulse-by-pulse basis, a
comparator may need to be added for a more accurate current limit threshold.
Switching losses have been minimized by the fast
current transitions, primarily defined by the leakage
inductance of the transformer. Although this switching time could probably be even further reduced,
there could be problems with current spikes during
Figure 15: 500 W, 100 kHz Half-bridge Schematic.
-, -.
-,
now..c
,
I
Yl
~
~
~'"
Il : .'"
.w
...
...
:=JII
:=J
l~
--
'-----
524
IIJDnt'
--::'F
..
t
ji~
':-U
'1041.11
Ull
,
.-
:'.i:"
POL'PRQP
\
",ZOnf"
f I ...","
r-<
u
-Iii
1
"
-..
: 1;;:'"
'F .'"
"
I
Il_ ~~~'
...,.., 1
'pO
~ ,G".
-.
.w
115""'",(
10/12
:
---'J
......,,,
-- -
1.J1:a
1
.....
'"
.~...I
::
=.
1 ~:
,
..... - 1
.
_-
~
Jj.-
..
.
~,
f;
( p
.,.J ...
u.
~
50
l!5zsa
"d"-'
"
... 1-1-
.f-of--
.~.,..-
-_ ...
.-
...'"
.... 1~
......
....
f--
~G ....
'10;-"'"
APPLICATION NOTE
Transformer winding data
500 W, 100 kHz, Off-Line, Half-Bridge Converter:
T1
T2
T3
Core: Ferrox 4S6T250-3CS
Pri : 14 T #22AWG
Sec (2) : 7 T#22AWG
Core: Ferrox EC52-3CS (EE)
Pri : 14 T, 2 layers, 2 #16AWG in parallel
Sec (2) : each 2 T, C.T., copper strap
0.01" x O.S"
Core: Ferrox 4S6T250-3CS
Pri: 1 T
Sec: 20 T, C.T. #22AWG
T4
117 V/220 V, 25 V, 0.15 A, 50-60 Hz
L1
Core: Ferrox IF30-3CS
4 turns, 5 #12AWG in parallel
500 WATT, OFF-LINE, HALF-BRIDGE
CONVERTER
Waveforms of the converter are shown in the scope
'photos of figure 16. Current rise and fall times are
20 ns and 10 ns.
Figure 16 : Performance Waveforms for the Halfbridge, 500 W, 100 kHz Converter
with Output Current of SO A.
oAoA-
,v-
The circuit shown in figure 15 uses a pair of
SGSP479 power MOS in a half-bridge configuration
with the SG1525A chip referenced to the secondary
side of the power transformer.
The power MOS gates are driven directly from the
control chip output through step down and isolation
transformer T1. The SG1525A output terminals
(pins 11 and 14) provide active pull-up and pulldown (dual source/sink for the primary of T1. This
provides the fast, high current turn-on and turn-off
pulses needed for the power MOS gates. In addition, the two ends of the primary windings are
shorted to ground during deadtime, which prevents
accidental turn-on by transients. Note that the current supplied by the SG1525A outputs drops to a
small value when the gate capacitance has been
charged or discharged to the desired gate voltage.
Damping resistors with series blocking capacitors
across the two secondaries of T1 minimize ringing
due to the power MOS gate capacitance and the inductance of T1 and lead inductance, particularly
during deadtime.
Deadtime for the SG1525A is set very simply by a
single resistor between pins 5 and 7. Only a small
amount of deadtime is needed since the power MOS
have no storage time and a very short delay time.
2 !'s/div
a) Waveforms of ID. IG, VG
100 ns/div
b) Risetime
0-
0-
Slow turn-on is accomplished by a single capacitor
at pin S.
Current limiting is provided by current transformer
T3 in series with the primary of the power transformer T2. The Signal is rectified, threshold adjusted
and sent to the shutdown terminal, pin 10, of the
SG1525A.
0-
100 ns/div
c) Faittime
11/12
525
APPLICATION NOTE
IMPROVED PERFORMANCE;
LESS COMPLEXITY
Although power supply designers for some time now
have had an ever widening inventory of Ie components available to ease their design tasks, the final
measure of improvement has to be in terms of system performance versus cost. With fewer interface
components to the power stages, freedom from
potentiometer adjustments, protected start-up and
shut-down, a built in soft-start network and several
additional system-level features, the SG1525A pro-
12/12
526
vides a significant contribution to both performance
and costs while simultaneously making the designer's task easier. With these accomplishments,
it is clear that this device truly does represent a stepfunction improvement, introducing a second-generation of power control components.
© 1984 by Unitrode Corporation. All rights reserved.
This bulletin, or any part or parts thereof, must not
be reproduced in any form without permission of the
copyright owner.
APPLICATION NOTE
200kHz 15W PUSH PULL DC-DC CONVERTER
BY M. SUTERA
INTRODUCTION
and secondary side.
The 15 W DC-DC converter, shown in fig. 1 has a
push-pull topology and works in continuous mode
with two outputs (+ 6 V, - 6 V) and features primary side control with full protection against fault conditions. There is no insulation between the primary
Due to the high working frequency, the power switches used are the new SGS-THOMSON advanced
POWER MOS type: IRFZ20 with high density and
bonding on the active area.
+llV
R'
0--.
:r e•
R.O
D.
-+6 OUT
r"""'ru,
GUO
...()
R4
I
9
"G
".
-6
"
CUT
I
GR7
"Z
~
~-9~8,
GND
\N35210689
1/6
527
APPLICATION NOTE
The PWM controller is the linear integrated circuit
SGS3S2SA, with dual source/sink output drivers, internal soft-start, pulse by pulse shut-down and ad-
justable dead-time control.
Table 1 shows the power supply specifications.
Table 1.
Operating mode
DC Input Voltage
Switching Frequency
Total Power Output
Outputs
Push Pull
10V DC to 18V DC
200kHz ± 10%
15W
+ 6V ± 5% 0.1 to 1.3A
- 6V ± 5 % O. 1 to 1.3A
0.05%/V
Line Regulation (+ 6V output)
Load Regulation (+ 6V output)
O.2%/A
Efficiency (@ 1/2 load)
:
76%
Output Ripple @ Max Load + 6V. - 6V Outputs 50mV Peak to Peak
Figure 1.
-rr
n.
+lZV
RIO--
l
TRI
F"'·w',....-l_l..,
....J.15---.J13-.....J.,O-----.1I
I
~
8-1
SGS 3525A
9
:fe.
01
~ ~
___
TR2
T.
t
12
R.
AI
G
eL
R7
=---
R2
GNO
CIRCUIT DESCRIPTION
The OC input is chopped at a high frequency
(200kHz). This high switching frequency allows the
use of a very small transformer.
Oue to the push-pull configuration of the converter
the POWER MOS devices, the transformer and the
diodes work at the frequency of 100kHz
(photo 1 , 2) ; the output filters and the oscillator of
PWM controller work at a frequency of 200kHz
(photo 3).
When Tr2 is on and Tr3 is off, diodes 02, 03 conduct and diodes 01, 04 are off. When Tr3 is on and
Tr2 is off diodes 01 , 04 conduct and diodes 02 03
are oft
'
2/6
528
The snubber formed by CS, R17 is used to clamp
the voltage spikes on Tr2 and Tr3 drains. With a
leakage inductance Ld = O.S).1H, a primary current
Ip= 2.8 AatVINMIN and maximum load and an allowable voltage spike Vp = 30V we can calculate CS as
follows:
CS =
= 1.8 nF
Eq.1
The PWM controller SGS3S2A has the two drive
outputs in totem-pole configuration in order to drive
the POWER MOS. The feedback signal for the
PWM is directly connected to the inverted input of
APPLICATION NOTE
The efficiency is excellent: 70 % over a wide range
(fig. 3).
the error amplifier from the + 6 V output by the resistive divider R4-R1. The maximum current protection is sensed by Tr1, R9, RS and is connected to
pin 10 (shut-down).
The magnetic coupling of the series inductance in
the output filter is very important for good regulation
of the voltages. In this way when the load is very different in the two outputs (+ 6V max load; - 6V min
load or viceversa) the indirectly regulated output
(- 6V) has a very stable output voltage (see fig. 2).
The transient response is very fast : about 50ms.
Photo 4 shows the transient response of load regulation due to a load variation from 1OOmA to 1.3A
and from 1.3A to 100mA (+ 6Voutput).
Fig. 4 shows the P.C. board (track layout) and the
component positions.
Figure 2.
Vo (-6) •
o
101+61
Figure 3.
EFFICIEIJCY 1%1
___
---11~~-~-~
./-"'---
p
IWI
3/6
529
APPLICATION NOTE
Figure 4 : P.C. Board and Components Layout (1: 1 scale).
TRANSFORMER
For this design a Tomita E core of 2E 6 ferrite material was chosen. To calculate the core size we
used the following equations:
Ae' An >
105 . POUT
1.16·L'1B·f·d
where L'1V is the voltage drop on the R9 resistor and
on the POWER MOS, OMAX = maximum duty cycle,
T) = efficiency.
The turns ratio is given by the following equations:
Vprim.
= O.143cm 4
n= - - - 'OMAX
Vsec
Eq.2
where:
POUT = output 1,5 (W)
L'1B
= flux density swing (T) we chose
L'1B = 200mT
d
= current density we chose = 450A/cm 2
= working frequency of transformer
Ae
= effective area of magnetic path [cm 2 ]
An
= useful winding cross section [cm 2 ]
The core size is then EE 25 x 6.5 with Ae = 0.42cm 2 ,
An = 0.45cm 2 and Ae . An = 0.189cm 4 > 0.143cm4.
The maximum value of primary current at VMIN is :
POUT
Ip=
T)'
0.75· 0.8·9
4/6
530
VMIN-L'1V
VOUT + VI
. OMAX = 1.03
Eq.4
The nurnber of turns Np is calculated as follows:
NpMIN = _ _V_M_IN_[V_]_._OM_A_X_ _ _ .10 4 = 9.5turn
L'1B [T ] . Ae [cm 2] . f [Hz]
Eq.5
The number of turns used was Np = 10 and Ns = 10.
The prirnary inductance is tHen the same as the secondary inductance.
Lp = Ls '" Np2 . AL = 100 . 2400nH = 240/lH
The value of Ld (leakage inductance) was measured on the transformer:
OMAX' (VMIN-L'1V)
15
n=
=2.8A
Eq.3
Ld = 0.5/lH
APPLICATION NOTE
OUTPUT FILTER
COMPONENT LIST
The most interesting part of the output filter is the
transformer T2 which, coupling the output series inductance of the two outputs, gives good regulation
of the - 6V output (magnetic regulator).
T2 construction is very simple because the two inductance are directly wound on the same cylindrical
ferrite core. Each winding is made up of 200 turns
and is: L (+ 6V) = L (- 6V) = 17J.!H.
The lou r last recovery diodes used are BYW29 -1 00
type.
Capacitors C1 0, C11 are 220/lF Roederstein EKR low
ESR type lor application in switching power supplies.
The ripple value obtained is very low = 50mV peak
to peak (photo 3).
Photo 1 : Tr2, Tr3, Vds (Vds = 20V/div.).
Resistors
R1
R2
R3
R4
R5
R6
R7
RB
R9
R10
R11
R12
R13
R14
R15
R16
R17
B.2K
5.6K
1.2K
1.5K
1.2K
470K
3.3K
390Q
0.22Q
10Q
22Q
22Q
5.6K
5.6K
1BQ
47Q
33Q
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/2W
Capacitors
c
C1
C2
C3
C4
C5
C6
C7
100/lF
1nF
1/lF
10nF
1.BnF
2.2/lF
10nF
2.7nF
10nF
220/lF
220/lF
330nF
330nF
C8
o
Photo 2 : Tr3 Waveforms (VG = 10V/div,
Vds
= 20V/div, Id = 1A/div.).
C9
C10
C11
C12
C13
Transistors
TR1
2N2907
TR2, TR3 = IRFZ20
Diodes
D1, D2,
D3, D4
BYW2929-100
IC s
11
= SGS3525A
Transformers
T1 core
T2 core
TOMITA EE 25
= cylindrical 30
x 6.5 2E6 Material
x 20mm
a
5/6
531
APPLICATION NOTE
Photo 2a : Turn On.
Photo 2b : Turn Off.
Photo 3 : Ripple on + 6V and - 6V Outputs
(20mV/div.).
Photo 4 : Transient Response (20mV/div.).
6/6
532
APPLICATION NOTE
HIGH VOLTAGE TRANSISTORS WITH POWER
MOS EMITTER SWITCHING
BY M. SUTERA
INTRODUCTION
This paper summarizes the results of an investigation carried out on power devices with both MOS
and BIPOLAR parts working together in the same
circuit. The "emitter drive" configuration was considered, with switching power supply applications in
mind.
The devices used are :
PowerMOS
Bipolar transistors
Ultrafast bipolar transistors
(Hollow Emitter)
Fast darlingtons
Figure 1 : The Basic Circuit used forthe Evaluation
of the Emitter Switching System. The
Base Drive Circuit used is shown for
Comparison.
FAST DIODE
: SGSP321, IRFZ20
: BUV48, BU508A
: SGS463
: SGS443
: SGSD00055, BU810
In the case of flyback switching power supplies a
practical example is also described.
CIRCUIT DESCRIPTION
The term "emitter switching" describes a circuit configuration where a low voltage transistor (MOS or Bipolar) switches off the emitter current of a high
voltage transistor, and consequently the transistor
itself.
This configuration combines the fast switching of a
low voltage device with the high power switching of
a high voltage device, since:
high current x high voltage = high power switching.
The combination of a high voltage bipolar and a low
voltage Power MOS is preferable due to the high
switching speed and the low driving energy of the
combined power switch.
The base of the high voltage bipolar device is driven
by a constant voltage source. The energy dissipated
to drive the high voltage bipolar device depends on
the losses that the forward bias current IB1 generates in the resistance in series with RB, IB12. RB. t.
Thi·s power dissipation can only be reduced by using
high gain transistors or Darlingtons.
(see fig. 1).
The diode in series with the base serves to clamp
the base over voltage at turn-off.
The two transistor stage is driven by the gate of the
low voltage Power MOS. Very low driving energies,
about 180nJ per cycle, are involved in the charging
of the input capacitances.
AN357/0689
Consequently the stage can be directly driven by the
output of suitable linear integrated circuits.
The possibily of direct driving by an IC output
together with the excellent switching speed make
this configuration extremely suitable for switching
power supplies at frequencies of 50kHz or higher.
CIRCUIT OPERATION
As we have seen, the forward base current IB1 is
fixed by the external circuitry:
VBB - VBEsat - VOSon
IB1
=
RB
The collector current instead depends on the load,
and in general, varies with the time.
The turn-on and turn-off phases can be analysed
separately.
TURN-OFF
When the driving signal to the Power MOS is low
the drain current is interrupted and the emitter current of the high voltage bipolar falls to zero. The
emitter reaches the base voltage and will not carry
any more current. As a result the collector current
can only flow through the base, becoming a reverse
base current that depletes the base to collector junc1/6
533
APPLICATION NOTE
tion. This reverse base current 182, from the moment
when the emitter current disappears, coincides with
the collector current. See photo 1. The stored
charge is removed in a typically very violent, and
consequently rapid manner.
Photo 2 : Base and Collector Current at Turn-on.
Photo 1 : Base and Collector Current at Turn-off.
a) After the initial peak due to the recovery of the
diode present on the secondary winding, the collector current increases linearly starting from zero
As a result the storage time is substantially reduced.
The fall time, which is related to the recombination
under the emitter, is also generally reduced.
Typical values for the fall and storage time of the
SGS-Thomson devices used in the test are shown
in table 1, for both emitter and the base drive circuits.
b) After the same initial peak, the collector current
increases linearly starting from the value memorized in the magnetic circuit at the end of the
previous cycle.
Figure 2 : Collector Current Waveforms with Varying Load.
Table 1 : Typical If and ts on Inductive Load.
Emitter
switching
Device
IC(A)
BUX48
BU508A
SGSDOO055
BU810
SGSDOO035
SGSDOO039
10
5
10
5
10
5
tstarage
500ns
800ns
400ns
300ns
300ns
300ns
tfall
Base
Switching
tstorage
100ns 2,IS
300ns 6,IS
100ns 1.2>Ls
150ns 800ns
50ns 800ns
40ns 700ns
tfall
200ns
400ns
100ns
150ns
50ns
50ns
TURN-ON
When the Power MOS is the on state, the bipolar
device also starts conducting. The dynamic behaviour (see photo 2) does not differ in any substantial way from the usual case of the base drive.
The dynamic saturation transient VCEsat dyn is also
practically the same with a base drive as with an
emitter drive. The.collector current, when the collector load is the primary winding of a switching transformer, can vary according to two possibilities, (see
fig. 2).
2/6
534
5-&112
v1 v1
I
II
"1
.1
1
5-8111
REVERSE BIAS SAFE OPERATING AREA
A problem that occurs in bipolar transistors is damage caused by "current crowding".
Fig. 3a illustrates current flowing in a typical bipolar
device. Fig. 3b shows how, when the device is
APPLICATION NOTE
turned off and the current begings to die away, the
current focuses with a high concentration under the
emitter. This high current density can damage or destroy the transistor.
Figure 4b : Fast Turn-off. Crowding with Low Average Heating but Possible High Peak
Power.
Figure 3a.
5-8116
Figure 3b.
Figure 4c : Fast Turn-off (with VCE delayed by
snubber network).
Ie
COLLECTOR
The energy dissipated within a bipolar power transistor at turn-off can be found graphically from a plot
of Ic versus VCE at turn-off. Three cases are shown
in fig. 4a, band c. The shaded area is proportional
to the energy that is dissipated in the device during
turn-off.
5-8117
Consequently turn-off times affect the SOA of the
device, (fig. 5b). These problems can be overcome
using emitter switching.
Figure 4a : Slow Turn-off. No Crowding but High
Average Heating.
5-8115
The way the stored charge is swept away in the high
voltage bipolar device when it is driven by the emitter, produces some interesting consequences.
The stored charges are evacuated through the base
contact when the emitter current is zeroed and not
later than a few tens of nanoseconds after the beginning of the storage interval. Consequently, during the turn-off, no charge is injected from the emitter
irito the base. Although the reverse base current is
quite relevant, no focusing of the current in the
centre of the emitter fingers takes place.
3/6
535.
APPLICATION NOTE
The bipolar device therefore exhibits an ~nergy absorbing ability at the turn-off RBSOA that IS substantially higher than if a normal base drive were used.
With a base drive the emitter would inject charges
and the voltage drop across the distributed base resistance would induce the "emitter crowding" phenomenon.
The practical evidence for all the transistors investigated (BUV48, BU508A, SGSF463) shows that.the
reverse bias operating area (RBSOA) extends nght
up to the BVCES ! (see fig. 5).
This extreme effect is unfortunately much less pronunced when using fast Darlingtons. The higher
complexity of the charge extractio~ m~chanism and
the charge injection from the emitter Into the base
in the driver transistor imply that the RBSOA extension is almost irrelevant.
A POSSIBLE APPLICATION
A possible application of the "emitter switchin~" c?nfiguration is shown in figure 6, where a SWitching
power supply operating in a "flyback" mode has
been implemented.
The basic criteria used in choosing the value of the
circuit elements are given below. The purpose of the
study was to demonstrate the feasibility and to
evaluate the advantages. Exact circuit element
values can be further optimized, especially in the
case of the transformer.
The power source in the mains singlephase, 220V
a.c., and the switching frequency can be set to
50kHz or more.
The devices used were:
01 :
fast Darlingtons with BVCES 1000V
for 110V line
- SGSBU810 for current up to 5A
- SGSD0055 for current above 5A
Fast transistor with BVCES 2 800V for
220V line
- SGSF443 for currents up to 5A
- SGSF463 for current up to 10A
02 :
Low voltage POWER MOS
(BVoss = 50V)
- SGSP321/1RFZ20 for currents up
to 10A
03:
High voltage, low current POWER
MOS V(BR) oss ~ 450V)
Figure Sa : Reverse Bias Safe Operating Area.
G 5',1
Ie r:::l=q:::I=l=1r::q::p::p::p:::q:~~
(A)
15
12
BASE
rSWITCHING
Control
200
vee'''
800
Figure Sb : How Reverse Bias Safe Operating Area
Changes for :
i) slow turn-off.
ii) fast turn-off.
Ie
(A
15
DZ2:
D.1 :
25V diode, with Ie peak rating as high
as 1OA for 500ns
C6:
Electrolytic capacitor, 100IlF, 25V.
It absorbs possible variations of VBB.
R3:
Resistor setting the forward bias
. base current of the Darlington:
i
VCE - VBEsat - VOSon - R7 10
R3=------------------IBt
Its power rating must exceed R3 . IB2
. t (in practice 3W)
I
~
~~~~E_ROF~
TYPICAL
LOAD LINE
WITH
SNUBBING
J>,.
ON
OFF~
200
536
UC3842
Zener diode 2W/20V
'III! 111,111111 I111111
12
4/6
IC:
..
SLOWER
TURN-OFF
R7:
Shunt resistor to sense the switch
current. The over current Is max protection is set according to
1V
R7=---Ismax
APPLICATION NOTE
C4,R6:
RC network, filtering the disturbances induced by the switching transients on the Ismax protection input.
C3, R5:
RC network, setting the switching
frequency and the maximum duty
cycle, according to the UC3B42 data
sheet.
!charge = 0.55 Rs C3
Idischarge =
Rs x C31n [(6.3 Rs - 2.7)/(6.3 Rs - 4)]
f = 1/(!c + td)
RB, R9:
Resistive divider of the feedback
voltage from a secondary sense
winding, rectified by 05 and C5. The
divided voltage is compared by the
control IC to an internal reference of
2.5V.
C2, R4:
Compensating network in the error
amplifier of the feed-back voltage.
R1 :
Resistor biasing the 03 gate (1.2M,
1/4W)
R2:
Resistor that limits the inrush current
through the POWER MOS, 03, at
the turn-off (1.2, 2W)
.J
04:
Fast recovery diode
Its voltage/current ratings depend on
the particular secondary winding it
rectifies.
05 :
Low current/low voltage diode
03, R10, CB : Snubber network (fig. 6 shows just
one of the possible configurations).
Il
Ld
CB=-Vos2
R10 = 1/4fCB
P (R1O) = 1/2 Ld 102 . f
where:
f = switching frequency
ld = stray inductance of the transformer
Vas = maximum voltage overshoot
allowed
03 :
A 400V fast recovery diode
C7 :
The use of a capacitor reduces the
crossover of the Darlington {3 to 6nF)
It is important to note that, the power transistor 03
acts only at the turn-on of the power supply and
when the capacitor C6 supplies more energy to the
base of the Darlington and to the supply input of the
IC than is returned to C6 during the turn-off of the
Darlington, 01.
Figure 6 : "Emitter Switching" Circuit.
04
CE
D2
QJ
R3
7
C2
R9
UC
II 3842 6
,
3
5008118
5/6
537
APPLICATION NOTE
CONCLUSION
The "emitter drive" configuration exhibts some clear
differences with respect to the usual "base drive"
configuration, and they can be particularly useful in
switching power supply applications:
- Substantial reduction of the storage time and improvement of the fall time.
Switching frequencies of 50kHz and higher are
possible
- The dynamic drive circuitry is simplified. The negative voltage supply is not required to remove the
stored charge from the base. The energy needed
to drive the gate of the POWER MOS is very low
(180nJ per cycle).
6/6
538
Extremely high ruggedness at the turn-off of the
inductive load (i.e. very large RBSOA) if the high
voltage bipolar part is a transistor.
Higher power dissipation in the on-stage, due
to the additional losses in the POWER MOS
(102 . Ros (on) . ton).
This last point is the only disadvantage, but it is more
than compensated for if switching at high frequencies. The lower switching losses (a saving each
cycle) can justify the higher on-state losses (a fixed
expenditure) as soon as the switching frequency is
high enough, which is often the case in switching
power supplies.
APPLICATION NOTE
A TRANSISTOR FOR 100 kHz CONVERTERS: ETD
BY Luc WUIDART
INTRODUCTION
Power converter designers aim to reduce the size
and the weight of their equipment. Hence, there is
a trend towards higher operating frequencies. Consequently for the semiconductor manufacturers,
there is a growing demand for fast switches. The
POWER MOSFET transistor is now well known as
a fast device.
However, the development of ultra fast "ETD" bipolar transistors is now challenging this way of think-
ing in certain applications. As an illustration, we
have selected an example of a "300W - 1OOkHz forward" switch mode power supply (SMPS).
VOLTAGE CONSTRAINTS
This "forward" converter contains a single power
switch and operates directly from the 220V AC
mains. The principle wave forms are illustrated in
figure 1.
Figure 1 : Basic Theoretical Wave Forms of the Forward SMPS.
TOaD 018
L
AN361 10689
1/7
539
APPLICATION NOTE
The switch must be capable of withstanding a static
collector-emitter voltage which, to afirst approximation, is given by :
(1 + np/no) x Vin, where,
np = number of turns in the primary winding
- no = number of tums in the demagnetization winding
- Vin = rectified mains voltage
When operating on the 220V AC mains and when
np equals no,· the voltage across the switch termi-
nals should only reach 750V in the worst case
(corresponding to a maximum rectified mains value
of 375V AC).
In reality, the voltage across the switch terminals
reaches a peak value (Vpeak) which is much higher.
The peak value depends upon the switching time,
the circuit capacitance and the leakage inductance
Lf between primary winding np and the demagnetization winding no (see figure 2).
Figure 2 : Leakage Inductance Lf between Primary Winding npand Demagrietization Winding no.
TOOO-020
L
Tr.
+
D1
+
~.--------------~-------.
np
•
Is
Vs
1
1
s
-@~_L.DESIGN OF SNUBBER CIRCUIT
At turn-off, energy stored in the transformer leakage
inductance generates a voltage spike (figure 3). In
order to limit this voltage spike, the energy must be
transferred to the capacitor Cmin in the snubber circuit. The energy depends on the switching current.
In a 300W SMPS, the peak value of the current Imax
is 5A. It is this value of current which is used to calculate the value of the capacitance Cmin required.
With a maximum voltage Vpeak, the value of Cmin can
be calculated using the following formula:
Lf X Imal
Cmin = -----·-2·-------"2---·-····---·-·-2Vpeak - Vin max (1 + Np/No)
Figure 3a : Wave Forms of Switching Current and Voltage Across the Switch Terminals at Turn-off.
TOCO 021
I
I
rtfi~
2/7
540
APPLICATION NOTE
Figure 3b : Definition of the Voltage VCEoff. VCEoff is measured when the Collector Current Reaches 2 %
of the Collector ICend.
7000 011
I, V
We call VCE,If the voltage which appears during the turn·off at the moment when the collector current
Ie reaches 2% of its value
Iceno.
If the value
VCEoff
measured in the circuit is low compared to the rating
VCEW of the transistor. the safety margin between the SOAR and the stress on the transistor is large.
VCEW is the maximum VeE voltage at turn-off with current.
In practice, Vpeak can be set between 800 and 900V.
To provide a safety margin, a switch with a blocking
voltage capability of 1ooav must be used. This voltage
corresponds to parameter VCEV for bipolar transistors
and to VDSS for POWER MOSFET components.
For bipolar transistors, an additional parameter
must be considered : the Reverse Biased Safe
Operating Area: (RBSOA). The turn-off cycle must
remain within the RBSOA, otherwise, the value of
capacitance must be increased from Cmin to a higher
value Cr.
Thermal dissipation in the snubber resistor, Rs
(figure 6), will be increased in the same ratio:
tfi X Imax
Cr = .-.-----.----~.--2 X VCEoff
For the selected transistor, VCEoff must be less than
the specified VCEW (see figures 3a and 3b).
SWITCH TYPE
In this application, three different types of switch
using different technologies are considered. These
are:
conventional bipolar transistor,
- POWER MOSFET,
- ultrafast bipolar "ETD" transistor (see appendix).
Table 1 summarizes the performances of these
types of switches under operating conditions, i.e.,
for a junction temperature of 1OODC and with a well
adapted gate/base drive (optimized totem-pole
drive for POWER MOSFETs and negative bias drive
for bipolar transistors).
Table 1 : Transistor Characteristics.
Characteristics at Tj = 1oaoe "Totempole" gate drive. Base drive with negative bias. Same silicon
area for each switch.
Blocking Voltage
Capability
Switching Time
(Tj = 100°C)
Conduction
(Tj = 100°C)
"v CEs_t
t,
tfi
1000V
100ns
100ns
BUV 48
Conventional Transistor
1000V
85ns
(60A/ps)
250ns
2.8V
(5A)
BUF 410A
ETD Transistor
1000V
50ns
(100A/ps)
100ns
2.8V
(5A)
STHV 102
VDMOS
RDsan,
5An
3/7
541
APPLICATION NOTE
The first point to notice isthat at turn-off, an ETD
transistor is as fast as a POWER MOSFET.
More surprisingly, the ETD transistor is twice as fast
as a POWER MOSFET at turn-on.
Let us now consider the effects of the characteristics
upon the size of the snubber. With a leakage inductance of 6.51lH and a current of 5A, a capacitor Cmin of
value 680pF is sufficient to limit the voltage Vpeak to
900V (fig. 4) :
Figure 4 : Comparison of Turn-off Cycle Within the Safe Operating Areas for the Three Different Switches.
~~-.-
IcIA)
RBSOA of conventional bipolar transistor
15
Load-nne with
Cmln· I80PF
10
.
Loali-line with
C, .1.8nF
~l
"-.
'(
VCEon
10(.0.)
1000
VCE IV)
1000
VOS (V)
Vpeol<
SOA ofal'owerMOSFET
15
10
Load-llne with
Cmln ·~80pF
'''/.-
f
50D
VCEon
I
VpeBk
IcI A)
RBSOA of the ETD tran3 i:stor
1~
10
Load-linDwith
Cmln· 680pF
,/
'-..
VCE (V)
500
VCEon
4/7
542
l!fi
SGS·mOMSON
~I 1>ll~I:IiiI@rn~rn«:1i'IiiI@Ill~I:i!l
Vpeol<
APPLICATION NOTE
However, a capacitor Cr of 1.8nF is required to limit
the VCEoH voltage to a value that is within the
RBSOA of the bipolar conventional transistor.
In comparison, the POWER MOSFET and ETD
transistors can be kept within their safe operating
areas with a capacitor of only 680pF.
LOSS EVALUATION
For the 300W forward SMPS operating at 100kHz,
the following assumptions have been made.
The losses have been evaluated assuming a current Inom of 4A, corresponding to the nominal output
power. A current of 2.8A rms is obtained with a duty
cycle of 48.5%. For a realistic comparison, conduction losses were reduced by paralleling two POWER
MOSFETs (the conduction losses of a single
POWER MOSFETs would be approximately 43W).
The results of this evaluation are as shown in Table 2.
Table 2 : Results of Loss Evaluation for the Conventional Bipolar Transistor, the two paralleled Power
MOSFET and the ETD BUF 410A Transistor.
Silicon Area
Snubber
(RCO)
C,
PR'
BUV48A
2 x STHV102
BUF410A
30mm 2
40mm 2
30mm 2
1.8nF
680pF
680pF
51W
19W
19W
30W
34W
17.5W
Conduction
5AW
21.3W
5AW
Switching
20.7W
12.3W
9.2W
Drive
3.9W
OAW
2.9W
TOTAL
LOSSES
(RCO + COM)
81W
53W
36.5W
Losses in the Switch
PR is the power dissipated in the resistor of the snubber circuit.
for this application, the ETD transistor requires no
more silicon area than a conventional bipolar transistor.
the ETD transistor uses the same value of snubber
capacitance as a POWER MOSFET.
conduction losses in the ETD and the conventional
bipolar transistor are the same.
the ETD transistor has the lowest switching losses
of the three devices considered.
In our example, at 100kHz, the superior performance of an ETD transistor results in about a 50%
reduction in losses as compared to the BUV48A and
30% compared with POWER MOSFETs.
vices considered, the ETD transistor is the optimum
cost/performance solution.
In addition, as a result of its fast switching capability
(tr < 50ns ; tli < 1OOns) and its extended RBSOA, the
ETD transistor can be successfully used in other applications such as resonant converters, motor drives
or uninterruptible power supplies.
ETD transistors with blocking voltage capability
higher than 1000V are under development. These
transistors will enable higher switching frequencies
to be used in equipment supplied directly from the
380/440V mains supply.
CONCLUSION
The example described in this paper (300W 100kHz SMPS), figure 6 shows that of the three de-
5/7
543
APPLICATION NOTE
APPENDIX I
WHAT MAKES ETD TRANSISTORS SO ATTRACTIVE?
masking levels with respect to conventional high
voltage "mesa" power technologies.
The new generation of ETD transistors adapted for
high voltage applications is designed with an inovative
technology utilizing a high degree of interdigitation.
REGULATION DYNAMICS
The most innovative feature of this technology consists of the replacement of the traditional bipolar
structure with emitter fingers (size: 250/lm) by a cellular structure with much smaller dimensions (80/lm
cells). This cell design considerably eases the extraction of charge stored in the transistor during
each switching cycle, since access to the intrinsic
base is easier. This makes it possible to reduce
switching times to values as low as 100ns.
The "Planar" technology has been selected for two
reasons:
It permits extension of safe operating area at turnoff. Moreover, it requires a reduced number of
Figure 5 : Curve Illustrating the Variation of Storage
Time tsi versus Conduction Time tp.
(ETD trC).nsistor BUF41 ~Al.
S[-1106
lsi (~s If--
----.~-"
--
-f--
1\
1.2
1.0
li
-I
I
-
l-'"
1/
O.B
06
--
1/
f---
... _, --
10
6/7
544
vBB
--
IB=0.5A ~I- _._.,--
= -5V
~
-I- ~I~
-
--lj-H~H-
~I-
-
Tj
O. 2~ f---f--- -f---
--~
I( =5A
= 100 O(
04
~I-
._-
._-
-I--
I
15
20
25
30
f--- c--
35 Ip (~sl
InSMPS or motor drive applications, the minimum
conduction time is a fundamental parameter when
considering the dynamic regulation. The delay time
at turn-off of the POWER MOSFETs specified in the
data sheet is sufficiently low.
In the case of bipolar transistors, storage time depends on conduction time. In our application at
100kHz, conduction time must vary from less than
one microsecond to five microseconds. In the
BUF410A data sheet, the cu rve showing the variation of storage time, ts, versus conduction time, tp,
shows that storage time varies from zero to 750ns
maximum (see Figure 5). Consequently, the regulation dynamics are not limited.
APPLICATION NOTE
Figure 6 : Schematic Diagram of an ETD BUF41 OA Transistor Implemented in a 300W - 100kHz Forward
SMPS Application.
TOOO-026
DI
2:~ov---m-a-i-ns--------'_~
@--------+-----~
+
II<
_1- 11 :1.,-.1-1" ·
C:J~:L~jl
~_1O_0_0-t-BY;T~OO
_
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-
10
From galvanic
insu\ulion
12V
3300
--':~
J
~10A
""eo
6S0pF
To control Ie
Q
I
Q2
p-channel-45V. Dohms
p-channel-6DV, 1 ~6ohms
7/7
545
APPLICATION NOTE
AN INNOVATIVE HIGH FREQUENCY
HIGH CURRENT TRANSISTOR CHOPPER
By L. PERIER & J. BARRET
INTRODUCTION
age medium power converters operating at high
switching frequency, such as UPS, welding converters, motor drives and battery chargers.
Recent developments in power semiconductors and
associated technologies have made possible the realization of medium power converters (5-50kVA) operating at switching frequencies higher than 20kHz.
A 500A - 20kHz CHOPPER WITH DARLINGTON
IN PARALLEL
This paper presents the design of a high current
(500A), high frequency (20kHz) chopper using fast
Darlington switches operating from a low voltage
supply (60V). New optimised design techniques for
paralleling power semiconductor devices are described. The association of these methods allows
the switching of 500A in less than 200ns.
High frequency bandwidth and regulation is
achieved for the 500A output current by switching
at an ultrasonic frequency of 20kHz with a turn-off
time of less than 200ns. Consequently, high rates
of change of current (in excess of 2000N~IS) are experienced. Six Darlington transistors (ESM2012 D)
in parallel and four ultra fast rectifiers (BYV54-200)
in parallel are used to achieve the current rating.
These new techniques are also suitable for high volt-
Figure 1 : Switches used in the Chopper.
TOOO 092
r
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~
-.- - - - - -
I
~
:
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:1
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©
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1
.
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L _ _ _ _ _ _ _ _ • _ _ _ .J
ESM 2012 D
VCEW
VCEV
= 125V
= 150V
VCEsat (100°C) < 1,5V
BYV 54-200
VRRM
= 200V
VF(100°C) < O,85V for IF = 50A
Rth
= 1,2K/W
= 70A
Is = O,25A
for Ie
tl;( 100°C) < O,4ms
Rth
AN366/0689
=
O,7K/W
1/8
547
APPLICATION NOTE
Figure 2 : New Base Drive Concept which Automatically Generates the Negative Bias. The negative bias
generated is independent of the duty cycle.
QC -----J9
11 Power stage
r ---,
L. ___
r
:
L ___
-
c
---~
2 x IlYV 54 - 2 0 0 ·
~
--
TODD 093
:
~
-"-
@.--~--------------------~
G x
ESp,( 2012 fl
-,
- 1- ---T--t-+£
1
1
27U~1
1
aD-lOa
£ •
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- - - - _____ I
=----1
L - - -_ _
11
--~----4-+-l
[
1100
n L
-
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TODD 094
21 Base Drive
Bzxes
n:!.xlIJ
C3VO
C2V~
+ 7-13V
66
B
ON
Jl
@-~__~~__________~__~~~____~~~__~.
The 500A/60V/20kHz chopper
2/8
548
F./GNO
APPLICATION NOTE
A power Darlington and diodes are shown in figure 1
together with their important characteristics. Figure
2 shows the power stage and the base drive circuit.
A base current of 5A is sufficient to control a collector current of 500A. The static and dynamic sharing
of the collector and base current between the paralleled devices is better than 90% provided:
a) The devices are mounted in a circular layout on
a common heatsink as shown in figure 3.
Good utilization of the heatsink is achieved using
this physical layout.
b) The bases of the output stages of the Darlingtons must be linked together. The access to the
bases of the output stage of the ESM2012 D
Darlingtons enables this.
Due to excellent current sharing, the Darlingtons
can be used close to their nominal collector current
rating.
Figure 3 : Circular Geometry for the Physical Layout of Power Devices.
TODD 095
Top view
The BYV54-200 ultra fast rectifiers in parallel are not
derated as these fast recovery epitaxial diodes have
Side view
negligible voltage drop (VF) spread.
Figure 4 : Power Stage.
3/8
549
APPLICATION NOTE
Low wiring inductances are required for high performance switching as parasitic inductances cause
overvoltage spikes at turn-off,
Figure 5 : A Low Wiring Inductance is Necessary in Order to Avoid High Over Voltages at Switch off,
TOaD 097
+
I :.
/~ ~, .cr£:i-·Ie : - - :
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Off]
'\
i00nH
200ns
L
VeE
If
i0A
5V
Ie
@--
-
!'.v
The 500A chopper has been designed with a low inductance plate wiring method, The plate wiring con-
TODD 098
+
+
Load
Load
~--
Low .winng inductance
Technology
~-"
I
4/8
550
J
50011
250V
sists of 2 parallel copper plates separated by a thin
adhesive insulator (see figure 6),
Figure 6 : Low Inductance Wiring,
High· wiring inductance
I
AdheSIve LnsuLator
(Kapton)
APPLICATION NOTE
Wiring inductances as low as 5nH/m can be
achieved in a 500ARMs circuit using plate wiring.
the base drive allows:
* Very high switching speed of the Darlingtons
at turn-on and turn-off: 2000NIlS.
The parasitic inductance of the power stage of the
500A chopper (capacitor + Darlington + free-wheeling diode) has been estimated at 20nH. Such a reduction of wiring inductance in the power stage and
* At turn-off an overvoltage of only 50V is experienced by the Darlingtons for a dlldt of 2000A/IlS.
Figure 7 : Turn-off Switching of the Fast Darlington Switch.
TOOO 099
!,- r-...
IC,VCE
100A/div
20V/div
'-I.
/ i\
1
o
VCE
V
/\
"v
r-.. ' -
1\ Ie
'\
... V
----7
t
The ISOTOP package is used forall the powersemiconductor components in order to optimize cooling
and wiring.
~
1 OOns/div
case suitable for plate wiring, low parasitic inductance due to its low profile and internal insulation with
low thermal resistance.
The package has screw terminals on the top of the
Figure 8 : A High Current Package: ISOTOP.
Copper
Screws
......
PCB
Current
U
Heat
Heat sink
TOOO 100
CONCLUSION
The design of a 500A - 20kHz chopper using fast
switching Darlingtons and diodes has been
presented.
The power semiconductor components have been
packaged in the ISOTOP package, allowing screw
connections and plate wiring techniques to be used.
The techniques developed also can be applied in
the design of medium and high voltage converters.
5/8
551
APPLICATION NOTE
BIBLIOGRAPHY
111 G.A. FISHER
High Power Transistor Inverters
16th Power Engineering Conference/Sheffield (UK)
121 K. RISCHMOLLER
La commutation rapide des transistors et Darlingtons de puissance Electronique de Puissance n 15.
Schnell schalten mit Transistoren und Darlingtons
Elektronik 20/9/85
131 L. PERIER
High Current Switches for Bridge Leg
EPE 85/Bruxelles (B)
141 J.D. VAN WYK - R.B. PREST
Base Drive for High Current Low Loss Bipolar Power Transistor Switches
PESC 86 (June 86)
151 J.J. SCHOEMAN - J.D. VAN WYK - H.w. VAN DER BROECK
On the Steady-state and Dynamic Characteristics of Bipolar Transistor Power Switches in Low Loss
technology
lEE Proceedings 132 - Sept. 85.
6/8
552
APPLICATION NOTE
APPENDIX I
LOW INDUCTANCE WIRING
1. Modelling and inductance
The inductance of wiring made circular cross
section wire, can be modelled as the sum of two
terms:
a) Self inductance of one wire:
0
LI = 11
- (Him)
Eqn.1
8][
b) Mutual inductance of the loop:
110
b- a
L2 = Ln - - (Him)
][
TOOO 101
a
Eqn.2
,
---:,
,
The total inductance of the wiring as thus:
110
1
b- a
= (- + In - - ) (Him)
Eqn.3
LT
][
4
- ,,
- ,
,
a
b
..
=
:
LT depends strongly on the geometry of the circuit. The best way to decrease LT is to decrease the area of
the loop:
TODD 102
:>
2. TECHNOLOGY FOR LOW INDUCTANCE WIRING
TOOO 103
adhesive ~ copper
L
I
= 110.
d
W
EqnA
= 500A, 0 = 20A/mm 2 , W = 50mm, d = 1 mm
=} L = 20nH/m
7/8
553
APPLICATION NOTE
APPENDIX II
The cooling ability of a heatsink is not linearily dependent on its length
TOOO 104
~e
-- -- -- -- -- -- --
-c:.--- - - -
2,8~
~e
2
~--------__
Losses
Separation of heat sources is thus necessary to optimize the cooling
SOOw
SOOw
@J
tfu
TOOO 105
=
Weight + 0,7
=
Length, volume and weight can be reduced in some case by a factor of
over the heatsink
8/8
554
Weight
=1
J2 if heating sources are spread
APPLICATION NOTE
A POWER STAGE FOR A 20kHz 1OkW SWITCHED MODE
POWER SUPPLY FOR THE INDUSTRIAL 380/440V MAINS
By Jean BARRET
INTRODUCTION
The theory of transistor converters operating from
the single phase 220V mains is not the same as that
for switched mode power supplies operating directly from the 380V and 440V mains and delivering an
output power of more than 10kW. For the latter the
increased technological constraints must be taken
into account when designing such a converter. This
paper explains the design of a 10kW - SMPS
operating on the three-phase 380V - 440V mains
and the solutions which have been found to resolve
the technological problems.
CHOICE OF THE
TURE
CONVERTER STRUC-
The converter has been designed for a supply from
the 380V and 440V mains. It must provide an output voltage of 80V and an output power of 10kW.
The operating frequency has been chosen to be
20kHz. There are several possible solutions for the
topology of the converter. The choice of topology
has been strongly influenced by technological considerations.
CONVERTER TOPOLOGIES
10kW - POWER RANGE
FOR
THE
Considering the high supply voltage and the switching frequency of 20kHz, converter topologies applying a voltage in excess of the supply voltage to
the transistors, or necessitating a power transformer
with a low leakage inductance have been eliminated. Transformers with a low leakage inductance
that respect the insulation standards are difficult to
manufacture. The one transistor "forward" converter and "push pull" converter are thus eliminated.
The choice of the converter topology is reduced to
two converter types:
- The full-bridge (figure 1) which is a symmetrical
structure with alternating magnetic polarisation.
- The asymmetrical half-bridge (figure 2) in which
the magnetic polarisation is uni-directional.
Figure 1 : Full Bridge Converter.
AN367/0689
1/9
555
APPLICATION NOTE
Figure 2 : Asymmetrical Half Bridge FORWARD Converter.
CHOICE CRITERIA
Theoretically the complete bridge is the solution for
high output power: at equal output power the transformer is half as big as that of an asymmetrical half
bridge.
In practice, there exist a certain number of secondary parasitic phenomena which reduce the advantages of a symmetric structure in comparison to the
half bridge. One of these phenomena is that a full
bridge is never perfectly balanced. A circuit to correct the symmetry must therefore be designed in
and the transformer must be slightly larger to avoid
saturation due to dissymmetry.
The full bridge necessitates the use of 4 bidirectional
switches and therefore of 4 galvanically isolated
drive circuits, whilst the half bridge only requires 2.
Simple switching aid networks cannot be directly applied to a full bridge, due to the direct coupling be-
These different considerations led us to choose an
asymmetrical half bridge. The experiment has
shown that our choice was reasonable and we think
today that,for an output power in the 1OkW area, the
asymmetrical half bridge presents the best technical and economical compromise.
For a substantially higher output power the full
bridge seems to be preferable. AltemativelY,2
asymmetric half-bridge circuits can be used, operating in antiphase.
THE ASYMMETRICAL HALF BRIDGE
GENERAL CIRCUIT DIAGRAM
The figure 3 shows the basic circuit and the principal voltage and current waveforms of an asymmetrical half bridge.
s'vvitches.
!n this converter, the transistors T1 and T2 are dri-
Supplementary chokes therefore have to be added
which would complicate the circuit considerably.
ven simultaneously. They conduct for a time "C and
are off for the rest of the period, T - "C.
The asymmetrical half bridge does not have these
problems. The input current of the asymmetrical half
bridge has a bad form factor. Consequently and
contrary to a full-bridge, the input filter capacitors of
a half-bridge are subject to a high RMS-current.
The diode D1 on the secondary conducts while the
transistors are conducting (time "C). The secondary
current (during time "C) goes through the inductance
L. The diode D2 operates as a free-wheel diode
(time T -"C).
t'Neen
2/9
556
the
upper
nnd
!0\-:8:-
APPLICATION NOTE
Figure 3 : Forward Asymmetrical Half Bridge Converter.
IT, CI T2
I D3 CI n.,
..
Ii
.
r1...
l,
4------
...
----.-~
T
--
~
..
r--,
.
....
IL~
I ::::::::::;:'"
-~-------.
----=::::::;:::
./
----
THE MAIN FEATURES OF AN ASYMMETRICAL
HALF BRIDGE
work in parallel to each diode reduces 'the voltage
ripple on the output.
The main features of an asymmetrical half bridge
are:
- Safety. In power equipment, safety isa fundamental element which must be considered from the
very first stages of design. The principal active
safety elements we introduced are:
a, current limitation for the power switches,
b, a soft start,
c. protection against overload on the output,
d. control of auxiliary voltages,
e, control of the transformer core magnetisation,
I. minimum conduction time for complete discharging of the snubbers.
The power transformer and ferrite core. Litz wire
is used for the primary because of its reduced skin
effect. The low leakage inductance is obtained by
winding a half-primary and a half-secondary onto
each leg of the transformer. A reduction ofthe duty
cycle with increasing input voltage limits the magnetisation of the core. This reduces the transformer's volume to a minimum.
The Power Switches. The simultaneously driven
power switches must be fast.Their drive must not
be disturbed by parasitic signals. To obtain agood
voltage safety margin, turn-off snubbing networks
are necessary.
Rectifiers and filter components. The choke inductance is the prinCipal component of the output
circuit. As far as possible, the inductance must be
high, so that the maximum current in the power
switches and the recifier diodes is as low as
possible. Fast recovery diodes are used to reduce
the switching oscillations. The use of an RC net-
- Control. The control circuit was developed with an
integrated circuit, the UAA4006. Amongst other
things, this circuit contains several protection
functions. The output voltage is detected by
means of an extra winding on the filter choke. The
free wheel diode is conducting during the de magnetisation phase of the filter choke. During that
time interval the voltage across the filter choke is
equal to the output Voltage. This voltage is fed to
the control IC, The control IC also provides the
features a-f listed above for safe operation,
3/9
557
APPLICATION NOTE
THE POWER SWITCHES
For the 1OkW switched mode power supply operating from the 380V - 440V mains two fast power
switches able to switch 1OOA with a maximum supply voltage of 700V are required.
There are two possible solutions when choosing the
power transistors.
1. To choose transistors with VCEW higher than the
m.aximum voltage the switch has to sustain.
Theoretically, this would allow a design without
turn-off switching aid networks.
2. To choose transistors with VCEW higher than half
the maximum supply voltage and with a VCEV
rating higher than the maximum voltage the
switch has to support.
The second solution has the advantage of better
switching performance than the first one.
The switching times must be as .short as possible
since the minimum conduction time is of the order
of 7~s and during a short circuit at the output about
2 to 3~s.
Our choice is a Darlington combination using
ESM6045A (fig. 4).
PRINCIPAL CHARACTERISTICS OF THE TRANSISTORS USED
ESM6045A
VCEW > 450V
VCEV> 1OOOV (VSE = - 5V)
VCEsat> 2.0V
tfi < O.6~s }
tsi < 6.0~s
Ic = 60A and 18
te < 2.0~s
Ti = 100c C
= 2.4A
Figure 4 : Power Switch.
lIe
+
-
-
5 A max
20 A max
--,
I
I
<
100 A
I----------~,
I
I
I '
1I
I
I
I
I
I
I
I
I
I
-.l
Note that this type of transistor is mounted in an ISOTOP package. The insulation voltage between the
die and the bottom of the case is 2.5kV r.m.s. This
avoids not only external insulation but also considerably reduces the capacitance between the transistor and the heat sink, hence gives a reduction in RFI.
A l':p.rtrlin numher of preC8.utions are required when
using transistors with VCEW lower than the maximum
voltage, to which the switch is subjected:
A base-emitter resistance must be connected to
each transistor (value stated on the data sheet),
which insures a static blocking voltage of 700V
and therefore protects .the switch against any
problem arising from the negative bias. Nevertheless the auxiliary voltage should be monitored.
A turn-off switching aid network must be connected to each switch to insure that the load line
stays in the RBSOA at switch off. In our case, the
4/9
558
network has to be calculated so that the collectorcurrent reaches zero before the collector-emitter
voltage reaches 450V.
- The driver circuit must be capable of providing sufficient base current with an optimized waveform.
The conduction time of each transistor will always
have to remain higher or equal to the time necessary to discharge the snubber capacitor even in the
case of an overload.
If these precautions are respected, the voltage
safety margin is the same as if very high voltage
transistors were being used.
BASE DRIVE CIRCUIT
The base drive turns the transistor switches on and
off as determined by the electronic control and safety
circuit.
APPLICATION NOTE
The positive base drive is regulated in order to maintain the power transistors in quasi-saturation. This
reduces the effect of parameter spread of the power
transistors and simplifies the paralleling. The storage and fall times are also reduced by this means.
The base drive must have a high immunity to electrical disturbances (dV/dt for example). The input interface uses a driver transformer with a bobbin with
two segments. The base drive circuit for one switch
is shown in figure 5.
Figure 5 : Base Drive Circuit.
r------------l
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.Y
I
I
I
I
I
I
I
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x x
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000
N
+
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5/9
559
APPLICATION NOTE
Figure 6 : Wiring for High Power Switching.
a) Base Drive with Poor Wiring.
b) Base Drive with Recommended Wiring.
6/9
560
APPLICATION NOTE
WIRING PRECAUTIONS
Special care must be taken concerning the wiring of
the fast high power switches. The switching speeds
being in the order of 200Allls (much more if they are
not limited), current/voltage oscillations are induced
in the leads.
It is therefore necessary to pay particular attention
to the wiring to reduce the parasitic inductance:
The connections between transistors, and to the
drive must be as short as possible (figure 6) and
form very small wiring loop areas.
- Try to obtain the highest symmetry possible between the paralleled transistors. The spread of the
transistor -characteristics is only of second order,
(for components of the same type and from the
same manufacturer) the spread in switching times
is essentially a result of the wiring dissymmetry.
- The reference point for the driver must be the
emitter connection of the power transistor.
Figure 6a shows an example where the zero point
of the driver circuit is disturbed by voltages created by the fast rise and fall (d Iidt = 50AlIlS) of the
output current of the driver stage.
- The decoupling capacitors must be connected as
close as possible to the switches.
- The decoupling capacitors must have low equivalent series inductances and resistances. To further
reduce the impedance of the decoupling capacitor, multilayer film capacitors with low parasitic impedance have been connected in parallel to the
electrolytic capacitors.
THE SNUBBERS
A turn-off switching aid network is needed due to the
VCEW rating of the switching transistors which is lower than the supply voltage. To obtain high efficiency from the power supply, switching aid networks
with energy recovery have been choosen 121.
Due to the reverse recovery behaviour of the diodes
these snubbers do not operate in an ideal way. The
reverse recovery current of the diode DAc3 (fig. 7)
causes some problems.
The reverse recovery time, trr, is dependant on the
diode technology and the switching conditions.
The reverse recovery current of this diode has sev. eral consequences.
- With a low load on the output of the power supply
it produces a reverse collector-emitter current in
the transistor. The transistor can be protected
against this current by means of an anti parallel
diode between collector and emitter.
- The reverse recovery current of DAc3 partially recharges the capacitor C1 (and discharges C2),
figure 7.
- It also flows through the choke L. If the stored energy is not discharged it will generate overvoltages. The diode DAc4 clamps and limits this
overvoltage to the supply-voltage. Unfortunately,
the current through this "clamp" recharges C1 still
more (fig. 8).
Diode DAC3 must be chosen with care. To reduce the
parasitic phenomena it must have a very fast recovery
characteristic. The type BYT30-1 000 was used.
The resistor (R) parallel to the diode DAc1 allows the
complete discharge of the capacitor C1 during the
conduction time of the transistor (figure 8). This increases the snubber losses, but they are still significantly reduced (- 30%) when compared to those
of a conventional RCD-snubber.
These modifications to the snubber with energy recovery are justified with high switching frequencies
(e.g. : 20kHz) and when the minimum conduction
time is short. In this case the snubber must reset
very rapidly and the parasitic phenomena of the
components can no longer be neglected.
The other components of the snubber are chosen
in the same way as those for the conventional RCDsnubber.
7/9
561
APPLICATION NOTE
Figure 7 : Non Dissipative Snubber.
+ VA
I
wcJ__ ""
I WAf)
Ie
---....-~.-.- -~II
Figure 8 : Complete Diagram of a Power Converter Output Stage.
II
IJ'OO"' ___
o
8/9
562
Diodes:
BIT 30 - 1000 ( D AC .....
Transistors:
2 x i';SM n045A
.l
APPLICATION NOTE
CONCLUSION
The technological constraints are very important in
the design of converters supplied from the 380V 440V mains.
The use of high voltage transistors with a VCEW
rating lower than the supply voltage requires certain
precautions, but enables a fast switching speed to
be achieved.
The magnetic components (transformer, filterchoke), technological choices are also important
since they affect the overall performance. of the
equipment as well as their influence on the size of
the active components.
Adding the snubber with energy recovery increases
the efficiency of the power supply and the overall reliability.
This circuit constitutes a basis for the development
of switched mode power supplies in the power range
of 1 to 10kW for power supply, welding induction
heating, battery charger and other high power applications.
REFERENCES
111 "La securite de fonctionnement des equipements transistor".
Le transistor de puissance dans la conversion
d'energie - p. 123 - 136.
Joel REDOUTEY - SGS-THOMSON Microelectronics -1983.
121 "Transistor chalter im bereich hoher Leistungen
und Frequenzen" RTZ Bd 100 (1979).
Andreas BOEHRINGER und Helmut KNOLL University of Stuttgart.
131 "Retard, bruit, remise en cond~ction"
Le transistor de puissance dans la conversion
d'energie.·
.
Jean BARRET - SGS-THOMSON,Microelectronics 1983.
141 "Improved Transistorized High Power Choppers" PCI 83 - Geneve.
Klaus RISCHMULLER - SGS-THOMSON
Microelectronics.
.
161 "3KW switch mode power supply providing sinusoIdal mains current and large range of DC-output" PCI 80 - Munich.
Helmut KNOLL - University of Stuttgart.
a
9/9
563
APPLICATION NOTE
POWER SEMICONDUCTORS FOR HIGH FREQUENCY
AC/DC CONVERTERS SUPPLIED ON THE 380/440V MAINS
.By L. PERIER & J.M. CHARRETON
INTRODUCTION
This pape~ is the result of the development in our laboratory of different switches and converters able to
operate at ultrasonic frequency, supplied directly
from the rectified 380/440V mains.
This paper presents, in the first part, a typical specification for the converter and power switches.
The second part describes several switches and
driving circuits optimized for those requirements.
1. SPECIFICATION:
Our objective was to develop switches and drivers
optimized for AC/DC converters supplied on the industrial380/440V mains, switching at ultrasonic frequency as used in Switch Mode Power Supply,
battery charger or weldin\:!. converter applications.
We based our development on the design of a 5KW
asymetrical half bridge (2 transistor forward) converter. An equipment of 1 OkW could be design with the
same switches mounted in full bridge or in the assembly of two asymetrical half bridge operating in
antiphase.
Because of the high voltage supply, the blocking
voltage capability of the switches is 1000V. In order
to minimize the transformer and filters size and the
acoustic noises a switching frequency over 20kHz
is required.
.
In a 5kW asymetrical half bridge supplied on the
380V mains, the maximum duty cycle of conduction
of the power switches is 50% of the total period. The
current in the switch is 15A. Consequently the RMS
current in the switch is 11 A.
In order to use a very small heatsink the conduction
losses in each switch are minimized (30W).
Auxiliary supplies for the power switches are also
excluded in order to minimize the volume and the
cost of the auxiliary circuitry.
2. A 1000V MOSFET SWITCH:
Power MOSFET technology is well adapted for the
design of switches able to operate at high frequency. 1000V MOSFETs exist and they present
the classical advantages of the MOSFET technology : low drive consumption, good turn-off safe
operating area, high over current capability, ...
Butthe resistance olthe epitaxial layer required to widthstand the blocking voltage Vos (if 250V) is approximately proportionnal to Vol,5. Consequently, the on
resistance R(on) of the Power MOSFET increases
rapidly with the blocking voltage capability Voss.
The only way to ·reduce the conduction losses with
a 1000V MQSFET is to operate at very low current
density and to use very large die areas.
In our design, one switch requires a Ron of 0.15 ohm
(Tj = 25°C). That means the paralleling of
25xSTHV102 (3.5 ohms in SOT93 package) or
more reasonably 5xST5MG40 (0.7 ohm in ISOTOP
package).
Figure 1 : ON Resistance R(on) versus Blocking Voltage Volt.
(die area = 1mm2 - junction temperature = 100°C) .
....
.
..
Konln,
1 5 0 t - - - - -_ _ _;
3Ot--------f
5
2t=:~~:::::U~~
10
AN368/0689
100
500 1000 Blocking (V)
Voltage
1/5
565
APPLICATION NOTE
The gate drive presented in figure 2 provides the
galvanic isolation of the drive signal and avoids auxiliary supplies.
When the signal MOSFET T1 is on, the power MOS-
FET T is on. When the signal MOSFET T2 is on, the
driving transformer is short circuited and discharges
the gate source capacitance of T, turning Power
MOSFET T 'off'.
Figure 2 : Schematic of the Power Switch and Driver.
TOOO 060
BYVlO-40
STHV102
(T)
input.
+v
r€t:J.
l@-:~:~
337
(T2)
Core: 76A FT 25 (LCC)
3. A CASCODE/EMITTER SWITCHING SWITCH:
50V high density Power MOSFET can operate at a
current density 100 times the current density of
1000V MOSFET for the same conduction losses
(typically 2A/mm2 instead of 0,02A1mm2).
The current density of a 1000V bipolar transistor is
in the region of 0.4A/mm 2 . For applications requiring the same current capability and the same dissipation, the 1OOOV MOSFET requires about 30 times
more silicon than the equivalent bipolar solution resulting in a substantially higher power .switch cost.
Bipolar transistors developed with highly interdigitated technologies such as the Easy-To-Drive tech-
2/5
566
nology (ETD) have a very fast fall time compatible
with operation at high frequency.
Consequently a solution using a high density 50V
Power MOSFET (STVHD90) and a 1000V bipolar
in ETD technology (BUF420A) in cascode configuration has been developed.
The driving circuit presented in figure 3 requires only
one transformer to provide the voltage control of the
MOSFETand the base current of the bipolar.
When the signal MOSFET T1 is on, the power
switch T is on. The turn-on of.the signal MOSFET
T2 turns-off T.
APPLICATION NOTE
Figure 3 : Schematic of the Cascade Switch and Driver.
TOOO 061
BYVLO-40
15n
BYT13~1000
DYW90-IOO
IDY.90-IO~I------+
~..
~-~~-~-Y
InF
2xD2x
15C13V
Core: 76A IT 25 (LCC)
As presented in figure 4, the cascade switch is very
fast at turn-off. A Storage time less than 500ns and
fall time less than 20ns have been obtained. The
rate of fall of the collector current is very high
(2000A/l-ls). The use of low inductance wiring methods and packages is a condition for the design of
this circuit. A turn-off snubber (R, C) limits ascii la-
tions and maintains the bipolar switch inside its specified Reverse Bias Safe Operating Area.
The rate of rise of the collector current (dl/dt)on at
turn-on is limited in the converter by the leakage inductance of the power transformer. Therefore turnon speed of the switch is not very critical. A (dl/dt)on
of 50A/s has been obtained.
Figure 4 : Cascade Switching Waveforms.
turn-off
tu rn-on
TOOO 062
TOOO 063
f'\
/ \
II \
)
II
/
----
f'
""- I--- I-'
r~
1\
V
~h
V t-------
-...
1\/
I)
Ic, Ib : 5A/div.
Vcs : 200V/div.
t : O,2I-ls/div.
3/5
567
APPLICATION NOTE
4. BIPOLAR SWITCH:
The elimination of the 50V high density MOSFET is the
last step to reduce the conduction losses and the number of power packages. But the remaining bipolartransistor must be driven with a negative bias on the
base/emitter junction in orderto obtain fast tum-off and
a blocking voltage capability extended up to VCEV.
In the circuit presented in figure 5, when T1 is on the
power switch T is on. T is turned-off when T2 and
T3 are on. T2 drives the negative base current of T
and is turned-off after 3J.lS. T3 resets the magnetic
flux in the driver transformer before the next turn-on
ofT.
Figure 5 : Bipolar Switch and Driver.
TODD 064
'OV
ON
or£"
(T)
BUF420A
~.
ci
=::
(T3)
(l~)
4700
Core
BCl27
With this circuit, a BUF420A switches 20A with a
storage time of 21ls and a fall time of 50ns at
Tj = 100°C, see figure 6.
Figure 6 : The Bipolar Switching Waveforms.
I
J
,
j
4/5
568
-
r-- h
\
Ib ' 2 A Idiv
~
Ie: 10A/div.
-{>-
o.g
-{>-
0"
1'6,\ IT 2~ (Lee)
APPLICATION NOTE
5. CONCLUSION:
This paper proposes different switches and drivers
able to operate in AC/DC converters switching at
ultrasonic frequency and directly supplied from the
rectified 380/440V mains.
The availability of 1OOOV MOSFET makes possible
the design of switches with high frequency capability, large turn-off safe operating area, large overcurrent capability and easily controlled gate drive. A
limitation of this solution is in the trade-off between
the conduction losses and the current density. A medium current 1OOOV MOSFET switch needs several
packages in parallel or a big heatsink.
A switch developed with 1000V bipolar transistor
has low conduction losses and few parallel packages. Thanks to the use of highly interdigitated very
BIBLIOGRAPHY:
(1) Transformer coupled direct base drive technology for high power high voltage bipolar transistor PWM inverter by Swanepoel, Van Wyck and
Schoemen (IEEE 1987 Atlanta)
(2) Designing switched mode converters with a proportional base drive technique by J. Gregorisch
(3) Self-supplying proportionnal base drive by M.
Brkovic and Z. Veljokovic (PCI 1987)
fast technology (ETD) the switching speed is comparable to the MOSFET solution. But the turn-off
delay time is longer and the driving circuitry is more
complex than a MOSFET circuit.
A Cascode circuit has the advantages of both bipolar and MOSFET technologies. It allows low dissipation with short turn-off delay time and simple
driving circuitry. High density low voltage MOSFETs
minimises the increase of the forward drop. Because of the very fast turn-off speed, special care
must be taken with the wiring.
Driving circuits using only one transformer to provide the galvanic isolation power/logic and the energy to drive the power switches are also presented
and adapted to each configuration of power switch.
(4) New design considerations for increasing switching frequencies in transistorized high voltage
converters by P. Maugest and L. Perier (lEE
Birmingham 1986)
(5) Optimized power stages for high frequency
380/440V AC medium power switch mode supplies by C.K. Patni and L. Perier (lEE London
1988).
5/5
569
APPLICATION NOTE
OPTIMISED POWER STAGES FOR HIGH FREQUENCY
380/440VAC MEDIUM POWER SWITCH MODE SUPPLIES
By C.K. PATNI & L. PERIER
ABSTRACT
INTRODUCTION
System designers of switch-mode solutions forelectric welders, battery chargers and computer power
supplies need to choose the power-stage configuration, power semiconductors and regulation best
suited for their application. This paper provides data
necessary to make this choice.
Figure 1 illustrates a system block diagram of a typical medium power SMPS with the primary operating
directly on the 380/440VAC rectified mains. The
paper limits the discussion to the power-stage of the
SMPS. Power stage configurations such as asymmetrical bridge, full-bridge and half-bridge converters are compared. Bipolar and MOSFET
technologies are compared. Schottky and fast recovery epitaxial diodes are considered for the secondary rectification.
This paper presents the elements necessary to
make the optimum choice of power semiconductors
(for the transistors and secondary diodes) and the
power stage configurations for medium power
SMPS (from 1kVA to 15kVA).
The power stage practically realized comprises of
an asymmetrical bridge forward converter. An optimised power switch combining bipolar and MOSFET technologies is developed. It is capable of switching in excess of 50A at 25kHz on the 380/440VAC
rectified three phase mains.
Secondary diode choice depends largely on the
transformer ratio and the desired output D.C. voltage. Conduction losses at 25kHz govern the choice
of secondary diodes.
Figure 1 : Block Diagram of a Medium Power SMPS.
TOOO 002
r--------------I
I
I
RccliCication
360 V AC
440 VAC
3-Pho3e
>---
•
Sufl
St.art
--1-
Nol always
neceSS6 ry
r----
,,"
"~
'---
~~
I
Tru,nstormer
( >2SkHz)
Primary
Switch
Converter
~Ii
II
II
--------
-
•
~-----
p
~ulp ul
J
Switching
J
signl1ls
Current
r-----
-
feedback
Relullllion &
protedion
x"-
,~
AN369/0689
'---
'-----
<"
.-
I
I
I
I
I
I
I
I
,-----
r-tIL -
l
Reclification
Low vollft'~
power sup,..h e s
Voltage
reedbllck
1/7
571
APPLICATION NOTE
POWER STAGE CONFIGURATIONS
For medium power applications (1kVA to 15kVA),
the choice of the converter on the 3-phase industrial
mains is between the asymmetrical bridge, capacitor-split half-bridge and full-bridge converters [1].
The half-bridge and full-bridge converters aresymmetrical converters and thus require smaller input
filtering than asymmetrical bridge converters. However, it is possible to combine two asymmetrical
bridge converters operating in antiphase in order to
obtain a power stage, which viewed from its input
and output current waveforms, appears to be a symmetrical full-bridge converter.
The asymmetrical bridge converter (figure 2) comprises of two power switches in series with the load
connected between the two switches. Simultaneous
conduction of these power switches when a fault
condition exists on the secondary of the transformer
is not catastrophic as there is at least the leakage
inductance of the transformer limiting the rate of rise
of primary switch currents. The controlled rate of rise
of primary current enables low-cost feedback protection circuits to react to the fault condition and turnoff the primary switches.
Figure 2 : Asymmetrical Bridge Converter - The Developed Power Stage.
TOOO 083
HVDC (540V DC nominal)
BYTl2P[ lOOO
BYV255-200
)
lBV DC
~--,+----~~~
42
~
maximum pnmary SWllch dutY-CYCle
25kHz SwilChLng frequency
HVGND
The use of turn-off switching-aid-networks (snubbers) does not pose a problem in asymmetrical
bridges. In half-bridge and full-bridge converters,
the use of turn-off snubbers generally necessitates
the use of turn-on snubbers required to limit the rate
,....f. ... ;,....,..... ,...1 ...... i.-n ........ , ..... 'ui+,....h ""'11r-rant""
VI
live:; UI
t-'IIIIIUIY
~VYIL""II
V ...... '''-'I'L ....
rlJl
L.... J.
The developed power stage utilizes the asymmetrical bridge converter because of these reasons.
For very high output power capability (in excess of
1OkVA), the full-bridge converter can be ihe optimum choice provided the circuitry necessary to
maintain volts-seconds symmetry can be easily implemented. The full-bridge operates the transformer
in two magnetic quadrants. Consequently the size
of the transformer can be reduced. Figure 3 illustrates a full-bridge converter which incorporates the
advantages of the asymmetrical bridge structure (no
2/7
572
catastrophic simultaneous conduction of transistors
and easy snubber networks) with the advantages of
the symmetrical converter of reduced transformer
size.
TECHNOLOGY CHO!CE
Bipolar and MOSFET technologies are best adapted for high frequency (greater than 20kHz) medium
power SMPS. Fjpure 4 illustrates the on-state resistance for 1mm of silicon surface versus blocking
voltage for high voltage power MOSFETs. The resistance of the epitaxial layer required to withstand
blocking voltage Vas (in excess of 250V) is approximately proportional to VOS2 .5 . Consequently, even if
this theoretical limit is approached, the on-state resistance increases rapidly as blocking voltage Vos
increases for high voltage power MOSFETs.
APPLICATION NOTE
Figure 3 : A Quasi-asymmetrical Full-bridge Converter.
- Transformer provides inductance between two switches in series.
TODD 084
HYDe
r- - ---------- ----,
: .1 turn
.1 turn:
~~~~~~~
~~Lo~~--r.
1
.1
1 turn
\ turn:
1
1
1
HVGIffi
ns
Trar.sfar.ne!"
LOAD
Figure 4 : MOSFET Blocking Voltage versus on-state Resistance/mm 2 .
TOOO 085
Rd~OIl mm 2
(T i
100'C) 150
(tog scale)
lOY
10QV
soov
looav
3/7
573
APPLICATION NOTE
The current density for a 1000V bipolar transistor2
such as a BUF410A is in the region of O.4A/mm
when conducting a nominal current of 1OA with an
on-state collector-emitter voltage of 2V maximum at
100°C junction temperature. The equivalent onstate resistance for a 1OOOV bipolar is thus approximately S Ohm/mm 2 whereas for a 1000V Power
MOSFET is 100 Ohm/mm2. For an application specifying only nominal switching current capability, the
Power MOSFET solution requires 30 times more
silicon than the equivalent bipolar solution (not considering the drive requirements) resulting in substantially higher power transistor cost.
Even though higher current density is achieved with bipolar transistors, the Power MOSFET has the clear advantage of a larger safe operating area at turn-off,
larger peak current capability and easy voltage controlled gate drive. The 1OOOV bipolartransistor has the disadvantage of longer turn-off delay time (due to its
storage time) and high drive current requirements. A
cost comparison of a Power MOSFET based solution
with a bipolar based solution should thus be based on
cost of the switch together with its drive, protection and
auxiliary power supply circuits.
Quantitative comparison is complicated by the very different operational characteristics of Power MOSFETs
and bipolar transistors. However, qualitative comparison leads the authors to conclude the following:
1) In medium power SMPS, where bipolar and
Power MOSFET technologies can be used, the
technology comparison must be based on cost
evaluation of solutions meeting the specification
both for PEAK transistor switching current as well
as AVERAGE/RMS transistor switching current.
2) Generally the Power MOSFET is sized for the
RMS transistor switching current, whilst verifying
that the peak current capability of the device
meets the specification.
3) The bipolar solution is sized on the peak transistor switching current specified in the application.
THE DEVELOPED POWER STAGE
The developed power-stage has the characteristic
iisteu ill table 1. Ti-,8 asynliTietrical bridge fOi"vvard converter was used with the maximum duty cycle limited
to approximately 40%. The continuous rated primary
current was 20A (for 40% duty cycle). The peak primary switch current capability was SOA. The transformer design (provided in appendix I) had a primary to
secondary turns 'ffi/.io of 10 to 1. Consequently the
continuous rated secondary output current was 200A
at a secondary output voltage of approximately 18V.
The secondary output peak current was SOOA when
primary switch current was SOA.
4/7
S74
Table 1 : Developed Power Stage
Characteristic.
Comments
Input Supply Voltage
Continuous Primary Current
Peak Primary Current
Maximum Duty Cycle
Switching Frequency
Continuous Secondary Current
Peak Secondary Current
Secondary Voltage (nominal)
Value
380/415/440V AC
20A
50A
40%
25kHz
200A
SODA
18V
THE ASYMMETRICAL BRIDGE CONVERTER
A solution for the converter, based on bipolar and
Power MOSFET technologies, encompassing the
advantages of high switching current density and
voltage controlled drive, was developed: this converter for the power stage was based on the CASCODE switch [3]. Due to the relatively large nominal
primary switch current (20A), a bipolar based solution was necessary. The CASCO DE switch required
a simple voltage controlled drive signal. No floating
auxiliary supplies were required as the base current
for the bipolar transistor was provided by a proportional current transformer. Figu re S illustrates the
primary CASCODE switch (based on bipolar and
MOSFET technologies) which is used in the asymmetrical bridge converter.
The switch comprises of a BUV298A bipolar transistor (B1 lin ISOTOP package and a high density
SOV (23 mOhm at 2S°C) Power MOSFET STHVD90
(F1) connected in CASCODE. A 1000V Power
MOSFET STHV102 (F2) provides the initial base
current. A SOV Power MOSFET BUZ11 (F3) turnson when the STHVD90 CASCODE MOSFET (F1)
is turned-off. Consequently the collector current is
extracted via the base through Power MOSFET F3.
A turn-off snubber (comprising of R1, 01 and C1)
maintains the turn-off within the reverse bias safe
operating area (RBSOA) of the bipolar BUV298A.
The primary switch conduction losses (at nominal
20A current for 40% duty cycle) are approximately
30W at a 100°C junction temperature tor the CASCODE switch. The primary switch could be based
purely on 1000 volts Power. MOSFETs (STHV102,
3.S ohm at 2S0C) in parallel. However, for 1.0 of
these Power MOSFETs in parallel, under the same
operating condition, the conduction losses would be
approximately 90W.
Figure 6 illustrates a pulse transformer gate drive
used with the primary switches. This gate drive provides positive and negative bias of the Power MOSFETs in the CASCODE switch. The pulse
APPLICATION NOTE
transformer also provides the isolation between the
primary switches and the control logic. With this gate .
drive, the asymmetrical bridge converter requires no
auxiliary power supplies.
Figure 5: The Developed CASCODE Asymmetrical Bridge Converter.
TODD 087
"
602F
g:~ polY]lrtlpylene
Figure 6 : Isolated Pulse Transformer based Gate Drives for Power Stage.
TODD 086
-t
12V
10 tUrns
HJ4148
:.wu
10 turns
5/7
575
APPLICATION NOTE
ASYMMETRICAL BRIDGE OPERATION
Figure 8 : Secandary Diade Switching Waveforms.
Figure 7 illustrates the extremely fast switching and
shart (less than 500ns) starage time at turn-aff abtained using this CASCODE switch. The primary
switch was tested with a bridge high valtage DC rail
af 600Vac, primary current af 50A at 25kHz switching frequency.
Figure 7: CASCODE Primary Switch Cammutatian
- (I PEAK = 50A).
Vo I :::; 20V /div
10 = 50A!div
Ves
t::: lps/div
lB:: lOA/div
Ves::
ZO(]V!div
'e : : 20A/div
SECONDARY RECTIFYING DIODES
The transformer had a primary to. secandary turns
ratio. af 10 to. 1. Cansequently the valtage experienced by the secandary diades at 600Voc HVDC was
. 60V in additian to. any avervaltage due to. parasitic
inductances.
Schattky diades which have extremely law canductian valtage (appraximately O.4V) can nat be used
far this applicatian as they are limited in blacking vo.ltage to. appro.ximately 50V. If the seco.ndary o.utput
valtage was 5V (far example, camputer applicatians), the transfarmer ratio. wauld have. been higher
thus permitting the use af Schattky diades.
The diades best suited far the specified secandary
autput are fast recavery epitaxial diades ('FRED').
FRED diades BYV255V200 were used in the circuit
havinQ canductian valtages af approximately 0.85V
at rated current and at 125°C junctian temperature.
Figure 8 illustrates the blacking valtage experienced
by the secandary diades with resistor/capacitar
snubber netwarks.
.
At cantinuaus rated autput pawer, each secandary
di.ode canducts far approximately 50% af the time an
average current af 100A. Assuming a junctian temperature af 125°C, the instantaneaus farward valtage drop is 0.85V at approximately 100A. Hence
di.ode co.nductian lasses are approximately 85W ;
(0.85Vx100A= 85W).
6/7
576
VOl::: 20V/div
10'::- 50A/div
APPLICATION NOTE
The leakage inductance between primary and secondary of the transformer is generally large such
that the rate of decay of current in these diodes is
controlled. Hence the reverse recovery is not critical. Thus at 25kHz switching frequency conduction
losses are the prime criteria forthe choice of the secondary diodes.
CONCLUSION
For forward converter operation equation [1] provides an approximate practical method of calculating the ferrite cross-sectional area.
[1]
S = K VVOUTPUT.loUTPUT = 900mm 2
S = cross-sectional area in mm 2
VOUTPUT = Output secondary voltage
IOUTPUT = Output secondary current
K = 15 (for B50 ferrite material).
Two GER65/33/27 (LCC) E shape B50 ferrites were
sandwiched together to form a ferrite core crosssectional area (S) of 1064mm 2 .
Bridge converters for medium power SMPS(1 kVA
to 15kVA) have been discussed. Turn-off snubbers
and low-cost protection circuitry can be used with
asymmetrical converters. A quasi-asymmetrical fullbridge converter has been proposed for high power
SMPS which operate the transformer in two magnetic quadrants.
Minimum number of primary turns (N p) can be calculated using equation [2].
The 1000V Power MOSFET is a well adapted
choice for low continuous power SMPS especially
when high pulse current capability is specified for
the primary switch. Bipolartransistors have high current density and are better adapted for medium
powerSMPS.
The number of secondary tums can be calculated
using equation [3].
The choice of secondary diodes at 25kHz switching
frequency is based primarily on conduction losses.
The developed power stage utilized the CASCODE
configuration for the primary switch. This solution
had the advantages of both the bipolar and Power
MOSFET technologies. Fast epitaxial rectifying
diodes (FRED) have been used in this power stage.
Np>
VMAx.Duty cycle
BMAx.S.f
Np was made equal to 40.
Ns =
VOUTPUT.Np
-----~>
VMIN.Duty cycle
3.6
1. SGS-THOMSON Microelectronics, 1984, "Transistor and Diodes in Power Processing", 187198.
2. SGS-THOMSON Microelectronics, 1978, "The
Power Transistor in its Environment", Chapter 8,
181-206.
3. Robinson F. and Williams B.w., 1987, "Emitter
Switching High-Power Transistors", EPE Conference, 55-59.
ANNEX I
TRANSFORMER DESIGN
The transformer design parameters for the developed asymmetrical bridge forward converter are:
VMIN = 500Voc
VMAX = 600Voc
VOUTPUT = 18V
IOUTPUT =200A
Duty cycle = 0.4 (MAX)
Freq. (f) = 25kHz
[3]
Ns was made equal to 4. Hence the primary to secondary tums ratio was 10 to 1. Consequently peak
primary current (20A) was one tenth of 200A secondary current.
The primary RMS current can be calculated using
equation [4].
IRMS = IPEAK. \/Duty cycle = 20
REFERENCES
[2]
> 36
V 0.4 = 12.5A
[4]
Using a current density of 5Nmm 2 , the primary was
wound using two wires in parallel of 1.25mm
diameter.
The secondary wire cross-sectional area was
20mm 2 calculated in a similar manner as for the primary wire.
MEASURED PARAMETERS
Leakage inductance = 90llH
(secondary short-circuited)
Primary inductance = 17.5mH
Insulation material used between primary and secondary was capable of supporting 1500VAC at 50Hz.
Three pieces of 0.65mm plastic film were used for
this isolation.
7/7
577
APPLICATION NOTE
TEA2260 ! TEA2261
HIGH PERFORMANCE DRIVER CIRCUITS FOR S.M.P.S.
SUMMARY
Page
1.2
BURST MODE ....................................................... .
1.3
OPERATION OF MASTER SLAVE POWER SUPPLY IN TV APPLICATION ........ .
1.4
SECONDARY REGULATION ............................................. .
1.5
PRIMARY REGULATION ............................................... .
2
2
3
3
6
8
II
11.1
CIRCUIT DESCRIPTION ............................................... .
9
VOLTAGE REFERENCE AND INTERNAL Vcc GENERATION .................. .
10
11.2
11.3
OSCILLATOR ........................................................ .
ERROR AMPLIFIER ................................................... .
10
12
11.4
PULSE WIDTH MODULATOR ........................................... .
12
11.5
SOFT START OPERATION ............................................. .
13
11.6
BURST GENERATION IN STAND BY ..................................... .
13
11.7
IS LOGiC ............................................................ .
13
11.8
11.8.1
11.8.1.1.
11.8.1.2.
11.8.1.3.
11.8.2
11.8.2.1.
11.8.2.2.
11.9
SAFETY FUNCTIONS: DIFFERENCES BETWEEN TEA2260 AND TEA2261 ...... .
I max ............................................................... .
First threshold VIM1 ................................................. .
Second threshold VIM2 for TEA2260 .................................... .
Second threshold VIM2 for TEA2261 .................................... .
Logical block ......................................................... .
Logical block for TEA2260 ............................................ .
Logical block for TEA2261 .............. , ............................. .
OUTPUT STAGE ...................................................... .
15
16
17
18
18
18
18
19
19
III
111.1
111.2
111.2.1
111.2.1.1
111.2.2
111.2.2.1
111.2.2.2
111.2.2.3
111.2.3
111.2.4 .
111.2.5
111.2.6
111.2.7
111.2.8
111.2.9
111.3
TV APPLICATION 120W 220 VAC 16KHz SYNCHRONIZED .................. .
CHARACTERISTICS OF APPLICATION ................................... .
20
20
CALCULATION OF EXTERNAL COMPONENTS ............................. _
Transformer calculation ................................................. .
Transformer specification ............................................. .
Switching transistor and its base drive ..................................... .
Current limit calculation ............................................... .
Snubber network .................................................... .
Base drive ......................................................... .
Oscillator frequency ................................................... .
Regulation loop ....................................................... .
Overload capacitor .................................................... .
Soft start capacitor .................................................... .
Feedback voltage transformer ........................................... .
Start up resistor ....................................................... .
High voltage filtering capacitor ........................................... .
ELECTRICAL DIAGRAM ............................................... .
20
21
22
23
23
23
24
25
26
27
27
28
28
29
30
INTRODUCTION . ..................................................... .
1.1
MASTER SLAVE MODE ................................................ .
AN376/0691
1/34
579
APPLICATION NOTE
SUMMARY (continued)
Page
IV
TV APPLICATION 140W 220 VAC 32kHz SYNCHRONIZED " " " " " " " " " "
31
IV.1
APPLICATION CHARACTERISTICS ...................................... .
31
IV.2
TRANSFORMER CHARACTERISTICS .....................................
31
IV.3
ELECTRICAL DIAGRAM ....................................... , ....... .
32
V
V.1
V.2
V.3
TV APPLICATION 11 OW 220 VAC 40kHz REGULATED BY OPTOCOUPLER ......
33
FREQUENCY SOFT START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
APPLICATION CHARACTERISTICS .......................................
33
TRANSFORMER SPECIFICATION ........................................
33
VA
ELECTRICAL DIAGRAM
34
I. INTRODUCTION
1.1. MASTER SLAVE MODE (fig.1)
The TEA2260/61 is an integrated circuit able to
drive a bipolar transistor directly with an output
base current up to 1.2A.
So .the TEA 2260/61 covers a wide range of application from 80W to more than 200W with all safety
requirements respected.
The high performances of the regulation loop provide a very low output power due to an automatic
burst mode.
The TEA 2260/61 can be used in a MASTER
SLAVE STRUCTURE, in a PRIMARY REGULATION or a SECONDARY REGULATION.
The TEA 2260/61 is very flexible and high performance device with a very large applications field.
The only difference between TEA2260 and
TEA2261 concerns security functions (see paragraph 11.8)
In this configuration the master circuit located on
the secondary side, generates PWM pulses used
for output voltage regulation. These pulses are sent
via a feedback transformer to the slave circuit
(Fig.1 ).
In this mode of operation, the falling edge of the
PWM Signal may be synchronized with an external
signal. By this way the switching off time of the
power transistor, which generates lot of parasites,
can be synchronized on the line fly back signal in
TV applications.
An other advantage of the MASTER SLAVE
STRUCTURE is to have a very good regulation not
depending of the coupling between transformer
primary and secondary windings, which allows the
use of low cost switch mode transformers.
Figure 1.
Sync.
Pulses
PWM
Signal
I n
h
I
Pulse
Inpul
I
b
h
n
I I ..
I
I
D
Base
Current _ _ _
V
~
..
b
~
V90TEA2260/61·01
2/34
~~----------------------- ~~~~~~~,,?~
580
---------------------------
APPLICATION NOTE
1.2 BURST MODE (fig.2)
During start-up and stand-by phases, no regulation
pulses are provided by the master circuit to the
slave circuit.
The slave circuit operates in primary regulation
mode. When the output power is very low the burst
mode is automatically used.
This operating mode of the SMPS effectively provides a very low output power with a high efficiency.
The TEA2260/61 generates bursts with a period
varying as a function of the output power.
Thus the output power in burst mode can varied in
a wide range from 1W to more than 30W.
Figure 2 : Burst Mode Operation.
I"
Burst Period
typ:::30ms
-,
"'1
1
1
1
1
1
1
1
1
1
1
1
COLLECTOR CURRENT ENVELOP
~
1
Switching
Period
DETAIL OF ONE BURST
V90TEA2260/61·02
1.3. OPERATION OF MASTER SLAVE POWER
SUPPLY IN TV APPLICATION
The system architecture generally employed is depicted in Fig.3. On the secondary side a micro
controller is connected to the remote control receiver which generates control signal for the standby and normal modes of operation (FigA).
• In stand-by mode, the device power consumption is very low (few watts). The master circuit
does not send pulses and hence the slave circuit
works in primary regulation and burst mode.
--------------
o In the normal mode, the master circuit provides
the PWM signal required for regulation purposes. This is called MASTER SLAVE MODE.
The master circuit can be simultaneously synchronized with the line flyback signal.
• Power supply start-up. As soon as the Vcc(start)
threshold is reached, the slave circuit starts in
cor1tinuous mode and primary regulation as long
as the nominal output voltages are not reached .
After this start-up phase the microcontroller
holds the TV Set in stand-by mode or either in
normal mode.
~ ~~~~~~]m~~:R~
-------------3/34
581
(11
(Xl
I\)
"11
1-1>
W
.
cO"
c
-I>
CD
Col
--;
AUDIO
OUTPUT
STAGE
Muting
Control
<
»
--0
~
6-
~.
0
::J
(J)
"<
Remote
Stand-by
ra-
ro
3
0
0;(0
ill
3
~
Remote
~cn
Stand-by
©'"'
",UI
i:i!
!1lio
"iii:
;UI
~P
!:!~
INFRA-RED
RECEIVER
~PWM
Small signal primary ground
Power primary ground
CJ Secondary ground (isolated from mains)
'iJ
~
<
(0
o
--l
m
~
'"'"
~
6
'"
l>
1:1
"tI
r-
5
l>
-I
0
Z
Z
0
-I
m
I:!!
IC
I:
iil
",.
r-------~/r---------~
(J)
'<
(IJ
TEA2260/61
Vee voltage
CD
I"
:3
o
VCC(STOP) :
n
1
Collector
current
envelop
~
1
Output
voltage
~CII
~~
I:B::C
@cn
~~
TEA5170
i
(IJ
I
r~------~"~------~
I
n n n
-s:6'
:::J
.t
/I
n n n
~
i:
I
(\J
a
3
@
:
I
:
~p supply
;;~::-:y
control
voltage
'"'"m
~
I~
• t 1 and t
2 :
I
I
i
I
t
I
:
---------r---------------i-------
i@lii
I
Start-up
commands issued by
"I"
~p
•
:
~.
m
»
:
~I
G) j
_
i--
a
-;
I
1,...1
I
<
to
_,
I
~:~~I~~voltagel
G)
I~
(\J
Q
::
t
""0
~~
w
t
~
©n
",CII
(]I
(Xl
•
It1
Stand-by
"I'"
.
t
Normal operation
I I
17
I 2
,Stand-by
"I·
•t
l>
"C
"C
r
If-
/
o
~
5
z
z
~
m
APPLICATION NOTE
1.4. SECONDARY REGULATION (fig.5, 6)
In this configuration the TEA2260/61 provides the
regulation through an optocoupler to ensure good
accuracy.
The advantage of this configuration is the avaibility
of a large range of output power variation (e.g 1W
to 110W).
This feature is due to the automatic burst mode
(see paragraph 11.6).
The structure in a TV Set is simpler than the
MASTER SLAVE STRUCTURE because the
power supply switches from normal mode to burst
mode automatically as a function of the output
power.
Figure 5: TV Application System Diagram.
00:
Ww
0:>
Q
~
(11
00
(11
I~
Ig
0'
OJ
'/-'-------1
1/
n n n
~I
h~'----------~
Ii~:
/1 - - - - - - - r - - - - - - - - - - - r - - - - Start-up
• I 1 and I 2 : commar:ds issued by
~p
Q
~
I
I
It
I 1
<
<0
oCD
Ul
~
~
CD
0'
3
/I
7/
I
r
I
I
:
1
CD
3
~
I
I
~
I
::
~
CD ~p supply
vollage
I
Sland-by
~1
Normal operalion
//
I
~
I
»
"C
"C
It
I 2
~ 1•
•
r-
Sland-by
,If-
o
~
(5
Z
Z
o-I
m
APPLICATION NOTE
1.5. PRIMARY REGULATION (fig.7)
In this configuration the TEA2260/61 provides the
regulation through an auxilliary winding.
This structure is very simple but the accuracy de-
pends on the coupling between the transformer
primary and secondary winding.
Due to the automatic burst mode the output power
can vary in a large range.
Figure 7: TV Application System Diagram.
a:
t---C::::J----4---li!----t~
8
>
t----jl---,--------------··~-
V90TEA2260/61·07
8/34
----------------~~~~~~~~~~?~~
586
----------------
1:::!1 -n=
to 0'·
c: c: (")
CD CD Jj
(Xl
•
S
V+
Vcr.
i~----------------------------~
(Xl (")
en C
15"=t
:E C
enm
-en
~(")
_. JJ
::J -"tI
g:::!
ERROR AMPLlFLIER
010
co- Z
Vee MONITORING
l
LJ
VREF
l.4V
2.49V
Cl.
C
OVERVOLTAGE
PROTECTION
::J
n-
6-
10,3V
WffiEMt
::J
V'
~
PRIMARY
PULSES
i'iSUI
~n
~'f
;'J:i!
IS
'LOGIC
REGULATION
PULSES
'
I
I
LOGIC
PROCESSOR
~O
~3:::
""UI
©O
",2
O_15VT
iR'
SECONDARY
PULSE
l>
"C
"C
r-
<
(0
0
--<
m
»
'"'"en
0
m
01
(Xl
-.&
I~
I~
Ro
Co
IS IN
C2
I MAX
GND
c=;
~
(5
Z
Z
S
m
APPLICATION NOTE
valid as soon as Vcc exceeds 4V. IHs not directly
accessible externally but is transmitted to other
blocks of the circuit.
This block also generates an internal regulated
Vcc, VCC(int), the nominal value of which is 5V.
VCC(int) supplies the circuit when Vcc is higher than
VCC(start) (1 O.3V typ;).
This allows the circuit to achieve a good external
Vcc rejection, and to provide high performance
even with large Vcc supply voltage variations.
This block also generates initialization and control
sig nals for the logical block. It also contains the
VCC(Max.) comparator (typ threshold 15.7V).
The circuit contains 8 blocks:
• Voltage reference and internal Vcc generation.
• RC oscillator
• Error amplifier
• Pulse width modulator (PWM)
• "Is logic" for transformer demagnetization
checking.
• Current limitation sub-unit (IMAX)
• Logical block.
• Output stage.
11.1. VOLTAGE REFERENCE AND INTERNAL
Vcc GENERATION (fig.9)
This block generates a 2.5 V typo voltage reference
Figure 9 :Voltage Reference Block Principle.
r-----------~~------~16r_------~----_.
Vee
Vee MAX
lS.7V
Vre!
2.SV
~hreshold re~ched
VI~
N
VC2 < 2.6V
y
Vccmax
reached
Restart
number = 3
Reset C2
discharged
N
>'-'-------"
N
y
V90TEA2260/61-19
TEA2261 :
The safety detections are similar to TEA2260 for
Vcc(max) (overvoltage detection) VIM1, VIM2
(overcurrent detection), but each time a fault detection is operating the C2 capacitor is loaded step by
step up to 2.6V, (case of long duration fault detection) and the power supply stpos. To discharge C2
capacitor it is necessary to switch off the TV set and
to switch on again and the power supply starts up.
593
APPLICATION NOTE
Figure 20 : TEA2261 Safety Functions Flowchart.
First
threshold reached
VIMt
y
.Second
threshold reached
VIM2
N
Vccmax
reached
N
y
VC2 < 2.6V
y
VC2 < 2.6V
y
N
Reset C 2
discharged
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~y
V90TEA2260/61-20
11.8.1. I MAX (power transistor current limitation)
The current is measured by means of a resistor
inserted in the emitter of the power transistor. The
voltage obtained is applied on pin 3 of the
TEA2260/61 .
The current limitation device of the TEA2260/61 is
a double threshold device. For the first threshold,
there is no difference between the two devices, only
for the second threshold.
16/34
Figure 21.
- - - - "1
,
TEA2260
----~-----~
------------------------------- ~ ~~~~~g~~J?~~
594
POWER TRANSISTOR
RS
V90TEA2260/61-21
APPLICATION NOTE
11.8.1.1. First threshold: VIM1 (typical value)
Figure 22 : Current Limitation Schematic Principle. First Threshold Part.
I
VCCint(5V)
Logic part
pulse by pulse
limitation 11
$
CHARGE CURRENT
I CH
2.6V
I MAX
TO LOGICAL BLOCK
V90TEA2260/61-22
Two actions are carried out when the first threshold
is reached
• The power transistor is switched-oil (pulse by
pulse limitation). A new conduction pulse is necessary to switch-on again.
• The C2 capacitor, which is continuously discharged by Idisch current (1 GilA typically), is
charged by the current
Ich - I disch (451lA - 1GilA = 351lA typically), until
the next conduction pulse.
Figure 23 : Example of First Current Limitation Threshold Triggering.
Conduction pulse
VIM1
I
I
IMAX
Voltage
(pin 3)
Output current
(pin 14)
C2 Capacitor
current
(pin 8)
V90TEA2260/61-23
The capacitor C2 is charged as long as an output
overload is triggering the first current limitation
threshold. When the voltage across C2 reaches the
threshold VC2 (typically 2.55V), output pulses
(pin 14) are inhibited and the SMPS is stopped.
A restart may be obtained by decreasing Vcc under
the VCC(stop) threshold to reset the IC.
----------------------------
If the output overload disappears before the voltage across C2 reaches VC2, the capacitor is discharged and the power supply is not turned off.
Due to this feature, a transient output overload is
tolerated, depending on the value of C2 (see
111.2.5).
~~~~~~~~~~~~~
17/34
---------------------------595
APPLICATION NOTE
11.8.1.2. Second current limitation threshold
(VIM2) for TEA2260
In case of hard overload or short circuit, despite the
pulse by pulse current limitation operation, the
current in the power transistor continues to increase. If the second threshold VIM2 is reached,
the power supply is immediately turned off and the
internal counter is incremented. After 3 restarts, the
power supply is definitively stopped. Restart is obtained by decreasing Vcc below VCC(stop), as in the
case of stopping due to the repetitive overload
protection triggering.
11.8.1.3. Second current limitation threshold
(VIM2) for TEA2261
For this device, if the second threshold is reached,
the power supply is turned off, C2 is charged and a
new start-up is authorized only if VC2 < 2.6V.
11.8.2. LOGICAL BLOCK:
This block receives the safety signals coming from
different blocks and inhibits the conduction signals
when necessary.
11.8.2.1. Logical block for TEA2260
Figure 24 : TEA2260 Simplified Logical Block Diagram.
TC
Vee (reset)
----+--------'
V90TEA2260/6t -24
TB
is the conduction signal (primary or secondary)coming'from the Is logical
block.
TC
is the conduction signal transmitted to
the output stage.
is the output signal of the first current limitation threshold comparator. It is
memorized by the flip-flop-Bt.
12
is the output signal of the second current
limitation threshold comparator
VC2
is the output signal of the comparator
checking the voltage across C2.
VCC(Max.) is the signal coming from Vcc
checking comparator.
18/34
These three signals VC2, 12, VCC(Max.) are memorized by 82.
In case of B2 flip-flop setting (12 or VC2 or VCC(Max.)
defect) the current consumption on Vcc increases.
This function allows to decrease the Vcc voltage
until VCC(stop). After this the current consumption on
Vcc decreases to ICC(start) and a new start up is
enabled.
The VCC(Off) signal comes from the comparator
checking Vcc. A counter counts the number of
VCC(off) establishment. After four attempted starts
of the power supply the output of the circuit is
inhibited. To reset the circuit it' is necessary to
decrease Vce below 5.5V typically . .In practice this
means that the power supply has to· be disconnected from the mains.
--------------~~~~©~g~:~©'
596
--------------
APPLICATION NOTE
1I.8.2.2.Logical block for TEA2261
Figure 25.
----"'-'-E}OR
~S
VCC(Max)--
5L
~
--+-<"--1
~ --+---IR
--R
RESET
V90TEA2260/61-25
Vcc(off) is a signal coming from a comparator
checking Vcc. When Vcc > Vcc(stop),VcE(off) is
high.
Vcc(max) is a signal coming from a comparator
checking Vcc. When Vcc > Vcc(max),Vcc(max) is
high.
h is a signal coming from the first current limitation
threshold comparator:
When Imax x RSHUNT > VIM1, 11 is high.
12 is a signal coming from the second current limitation threshold comparator.
When Imax x RSHUNT > VIM2,12 is high.
TB is the conduction signal coming from the error
ampliflier system.
TC is the output signal transmitted to the output
stage.
11.9. OUTPUT STAGE
The output stage is made of a push-pull configuration : the upper transistor is used for power transistor conduction and the lower transistor for power
transistor switch-off.
Figure 26.
TC
V90TEA2260/61-26
A capacitive coupling is recommanded in order to provide a sufficient negative base current through the
power transistor .
-------------------------
~~~@~~~~~~
19/34
---------------------------597
APPLICATION NOTE
Figure 27 : Typical Voltage Drops of Output Transistor versus Current.
(v)
volt~ge
dr"op
----T1
-T2
1 -------
---
-----=~~
-
I
I
:
I
I
I
I
I
:
power transistor
~~~~~~~I~~~~~~c~ol~lec~to~,~c~u,_,e~n~t (A)
V90TEA2260/61-27
Important remark : Due to the internal output
stage structure, the output voltage (Pin 14) must
never exceed 5V. This condition is respected when
a bipolar transistor is driven_
Note that Power-MOS transistor drive is not possible with the TEA2260/61.
III. TV APPLICATION 120W - 220 VAC -16 kHZ
SYNCHRONIZED ON HORIZONTAL DEFLECTION FREQUENCY
General structure and operational features of this
power supply were outlined in section I.
The details covered below apply to a power supply
application using the master circuit TEA5170.
(refer to TEA5170 data sheet and TEA5170 application note "AN088" for further details)_
III. 1_ CHARACTERISTICS OF APPLICATION
• Discontinuous mode Flyback SMPS
• Standby function using the burst mode of
TEA2260/61
• Switching Frequency
- Normal mode: 15.625 kHz (synchronized on
- horizontal deflection frequency)
- Standby mode: about 16 kHz
• Nominal mains voltage: 220 VAC
• Mains voltage range: 170 VAC to 270 VAC
• Nominal output power: 120W
• Output power range in normal mode
14W < Po < 120W
• Output power range in standby mode
1W
2 x 600
2.25nF
3
R = T ON(min) =
4 10-6
= 5600
3 xC
3 x 2.25 10-9
2
1
P = '2 x C x VIN(max) + VR) x F
P = ~ x 2.25.10 9 x (370 + 172)2 x 16.103= 5.29W
In the final application a value of 2.7nF is chosen
to decrease the overvoltage on the transistor in
short circuit condition.
V90TEA2260/61·318
111.2.2.2.1 Overvoltage due to the leakage inductance
(See. 111.2.1)
The capacitor C of the snubber network influences
the overvoltage due to the leakage inductance.
Vpeak= IC(max)
2
~
C
Numerical application
with: Lf = 0.08 x Lp = 0.08 x 1.9 10 -3 = 15211H
Vpeak~X ~=
390V
2
2.25 109
so VCE(Max.) = VIN(Max.) + VR + Vpeak =
VCE(Max.) = 370 + 172 + 390:= 930V
111.2.2.3. Base drive
The output stage of the TEA2260/61 works in
saturation mode and hence the internal power
dissipation is very low.
Figure 32.
Is
vz
IB+= VCC+-Vp-VZ-VBE
Rl
V90TEE2260/61-32A
24/34
--~------------------------~~~~©~2~~~~~~
602
V90TEE2260/61-328
----------------------------
APPLICATION NOTE
in this case the current gain,
Vee+- Vp- Vz- VSE
Rl=
~~--~--~--~
Ie
Is+
Numerical application
R = 13 - 0.9 - 3 - 0.6", 1
1
0.85
-
on
3
BF = - = - - - = 3.5 but it is recommanded to
Is
0.85
verify the VCE sat dynamic behaviour on the transistor as follows:
Figure 33.
r-----,
]
I
:
I
I
I
I
:
I
I
I
I
I
I
I
I
I
:
'-+:-------'
Vm
Ie
OSCILLOSCOPE
V90TEA2260/61-33A
Ideal value: 1V
:0;
VCEsat + VD
:0;
2V
Vm
4V
f----..
V90TEA2260/61-33S
Remark :The mains of the TEA2260/61 must be
provided through an isolation transformer for this
measurement
111.2.3. Oscillator frequency
The free running frequency is given on 11.2.
The typical value of minimum conduction time
TONIMin.) on the output of the TEA2260/61 is given
by: T ON(Min.) = 1040 x Co
Note: the minimum conduction time TON(Min.) on
the transistor is longer due to the storage time.
25/34
----------------------------- ~ ~~~C~n&g:f~ii?r~ ----------------------------
603
APPLICATION NOTE
Figure 34.
"'""F-;1/3;z=\
:~
I
18
----I
I
I-- TON
I
I
I
I
MIN
ON TEA2260
I
I
I
I
I
I
I
I
t
I
~TON
Ie
I
I
MIN
:
~~AJ~'~TORI
I
I
I
V90TEA2260/61-34
Numerical application
Fa = 16kHz
Co is chosen at 1nF
so TON min on the TEA2260/61 = 11ls
Ro =
Ro
1
Fox Co x 0.66
1.57 . 10s
=
1
_ 1.57 . 10s
16 lOs x 1 10-9 x 0.66
Ro = 93kQ
Ro = 1OOkQ is chosen.
Note: Fa is chosen relatively low to avoid magnetization of the transformer during the start-up
phase.
• The R.C. filter is necessary to avoid the peak
voltage due to the leakage inductance. The time
constant't = RC is about 30llS < R.C. < 150llS as
a function of the transformer technology.
• To achieve a stable behaviour of the regulation
loop and to decrease the ripple on the output
voltage in stand by mode the time constant
should be approximately:
ROUT x COUT
(R1 + R2 + Rs) xC
15
=
with : COUT (filtering output capacitor) and ROUT
(load resistor on the output in stand by mode)
., To ensure a stable behaviour in stand-by mode
the amplifier gain is choosen to :
G=
111.2.4. Regulation loop
~=
R2+Rs-
15
In stand by mode the error amplifier of the
TEA2260/61 carries out the regulation.
Calculation of R, Rl, R2, R3, R4
Figure 35.
a) The resistor R is given by
R4
R= ..!.
r------------------- 7 -------
R
C
C choosen between 11lF < C < IOIlF
't = 80llS is chosen
C = 2.21lF is chosen
Numerical application
' - - - - - - - Vref
So R = ..!. = 80 1 0-6 = 36Q
C 2.2 10-6
V90TEA2260/61-S5
26/34
---------------------------~~~~~~g~~~9~~
604
-----------------------
APPLICATION NOTE
b) The resistors R1, R2, R3 are given by
COUT x ROUT
R1 + R2 + R3 =:
15 x C
with:
VREF : reference voltage of the error amplifier
VREF = 2.5V
Vcc(stand-by) : Vcc voltage in stand by mode.
Vcc(stand-by) = 0.9 x Vcc (in normal mode)
Figure 36 : Load of Overload Capacitor.
'::k1
R2 + R3 = 6.10 3 x
0.:~513 = 1.28kQ
values choosen :
R2 potentiometer resistor of 1kQ
R3 fixed resistor 1kQ
R1 = (R1+ R2 + R3) - (R2+ R3)
R1 = 6k - 1.28k = 4.7kQ
c) The resistor R4 is given by R4 =: 15 X (R2 + R3)
Numerical application
R4=: 15 x (R2 + R3) =: 15 x (1.2810 3) =: 18kQ
111.2.5. Overload capacitor
When an overload is detected with the first threshold VIM1 the capacitor C2 (pin 8) is charged until
the end of the period as shown in figure 36.
So the average load current is given by :
T- TON
IC2 = - - T - X ICH - IDISCH
the threshold to cut off the TEA2260/61 power
supply is 2.5V typically and hence the delay time
before overload detection is given by :
2.5 x C2
Toverload = -=----o;;----~-
T- TON
(--T- x ICH) - IDISCH
2T
---TON---"'"'1
----------T---------~
Numerical application
with:
Vcc = 13V
VREF = 2.5V
ROUT = 2kQ on output 135V
COUT = 100jJ.F on output 135V
C = 2.2jJ.F
COUT x ROUT
R1 + R2 + R3 =:
15 xC
-6
3
100 10 x 2 10 = 6kQ
15 x 2.210-6
VREF
R2 + R3 = (R1 + R2 + R3) x Vcc(stand py)
nnuu
!, I
1u-w,' I"'"' ~
V90TEA2260/6.1-36
Numerical application
with: maximum overload time = 40ms
the longer delay time is obtained when
TON = T ON(Max.)
I ) I
) Toverload
C 2 '" T - TON(Max.)
T
x CH - DISCH X ~
«
C2 = (0.55 x 45 x1 0-6_ 10 x10· 6 40~~0
-3
=: 220riF
Note : in practice, the overload capacitor value
must be greater than the soft start capacitor
(C2 ~ C1) to ensure a correct start up phase of the
power supply.
111.2.6 Soft start capacitor
Refer to paragraph 11.5 for the soft start function
explanation.
The soft start duration is given by :
(2.7- 1.5) X C1
TSOFTSTART =
9 . 10-6
C1'" 7.5.10-6 x TSOFTSTART
Numerical application
with: Tsoft start =30ms
C1 = 7.5 10-6 x 30 10-3 = 220nF
111.2.7. Feed back voltage transformer
A feedback voltage transformer is used to send
information from the secondary circuit (master circuit) to the primary circuit (slave circuit).
This transformer is needed to provide an electric
insulation between primary and secondary. side.
27/34
-------------- liii ~itlH~";1:~~~ --------------
605
APPLICATION NOTE
R
ffR1
2
Vif:} , C1
Figure 37.
.
.
np
ns
v,
restarts. and to cut off the TEA2260/61 on fault
detection when the power supply is switched off.
Hence it is recommended to connect the start-up
resistor as follows:
Figure 38.
Imoy
V90TEA2260/61-37
The feedback input of TEA2260/61 is fed with logic
level (threshold 0.9V)
It is necessary to have the same waveform on the
primary side as on the secondary side.
For this reason the time constant must be higher
than the maximum conduction time in normal
mode.
Hence the primary inductance Lp must be calcuc
lated as follows:
Lp > 3.R.ToN(Max.)
1- _
!l-1-1L
Rst
START UP RESISTOR
Icc start
V90TEA2260/61-38
Start-up delay time
Numerical application
with:
T ON(Max.) = 28~s
R = 2700
Lp > 3 x 270 x 28 10-6 = 22mH
-r-2 x VIN AC(min)
.
R
7t X ST
.
VCC START
Start-up delay time = Tst = I
I
xC
MOY - CC START
a) When the TEA5170 is used VIN = 7V
VS(min)
ns
-r-2 x VIN AC(min)
RST = --(O------:V-,-C-C-S-T--'A'-'-RT-'-==c..-'-----'J
7t X
Cx
TST
) + Icc START
np
7x
(11~5 0.45) =
Power dissipated in start-up resistor
0.389
b) When the TEA 2028 is used VIN = 12V
~~
l(
VIN x (1 _ T ON(maX»
T
~~
IMOY=
12 x (11: 0.45) = 0.227
Note: The R1.C1 filter is used to damp oscillation
on the secondary side of the feedback transformer.
The time constant R1 x C1 == 0.1 ~s.
111.2.8. Start up resister
After switching on the power supply the filtering
capacitor on Vcc of TEA2260/61 is charged
through a resistor connected to the mains input
voltage. Do not connect this resistor to the high
voltage filtering capacitor because there is enough
energy in this capacitor to cause three attempted
P = VIN AC(max)2
2 . RST
Numerical application
with:
start-up delay time = 1s
VIN(max) = 370V DC (VIN AC(max) = 265V)
VINAC(min) = 175V
VCCstart= 10.3V
ICCstart = 0.7mA
C = 220~F
2 x 175
~=
3=~ill
7t x (220 10-6 x 10.3 + 0.7 10- )
Value choosen = 22ill
Power dissipated
P=
(265)2
2 x 22 103
=-28::./=-34~ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m~~~~~J;~
606
1.6W
--------------
APPLICATION NOTE
1I1.~:9.
Determination of high voltage filtering capacitor
Figure 39.
c
V90TEA2260/61-39A
Vin
'\
!:N
\
\
\
I
\
( I
/
\
\
1
\/
\1
I--
T/4+t -----,
1-------- T
I
--------1·1
V90TEA2260/61-39A
Hypothesis:
/c,. V : ripple on the filtering voltage
VIN.AC(min) : minimal value of A.C. input voltage
T : period of the mains voltage
POUT: output power of the power supply
Numerical application
/c,.V = 40V
VINAC(min) = 170 VAC
T = 20ms
POUT = 120W
11 = 0.85
11 : efficiency of the power supply
C
=l
2n
-n + A rc S·1n(1 -
x 2
/c,.V . In)
VIN AC(min) x'l2 x POUT
/c,. V x VIN AC(min) x {2
11
value choosen : C = 120J.lF
29/34
--------------------------- ~~~~~~g:~p~ --------------------------607
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Small signal secondary ground
~ Power primary ground
CJ Secondary ground (isolated from mains)
POUT; 120W
f
: 16kHz
o»
-f
o
Z
z
o-f
m
APPLICATION NOTE
IV. TV APPLICATION 140W - 220 VAC - 32kHZ
SYNCHRONIZABLE
IV.2. TRANSFORMER CHARACTERISTICS
• Reference: OREGA.SMTS. G4S76-03
All details concerning the determination of external
components are described in section III.
• Electrical Data:
Figure 41.
IV.1. APPLICATION CHARACTERISTICS.
• Discontinuous mode flyback SMPS
• Stand-by function using the burst mode of
TEA2260.
• Switching frequency in burst mode: 16kHz
• Switching frequency in normal mode: 32kHz
• Nominal mains voltage: 220 VAC
• Mains voltage range: 170 VAC to 270 VAC
• Output power range in normal mode
2SW < Po< 140W
• Output power range in stand-by mode
2W < Po <4SW
• Efficiency at full load> SO%
• Efficiency in stand-by mode (Po = 7W) > SO%
• Short circuit protection
V90TEA2260/61·41
• Long duration overload protection
• Complete shut down after 3 restarts with fault
detection for TEA2260
• Complete shut down when VC2 reaches 2.6V for
TEA2261
Load regulation (VDC = 310V)
Output 13SV (± 0.1S%) --7 (1135 : 0.01 A to O.SA;
125=1A)
Output2SV(±2%) --7(1135: O.SA; 125 = O.SA to 1A)
Line regulation (h35 : O.SA; 125 : 1A)
Output 13SV (± 0.13%)--7 (21 OV < VDC < 370V)
Output 2SV (± 0.17%)
Winding
Pin
Inductance
np
3-6
790~H
naux
7-9
5.4~H
n2
19-13
338~H
n3
19-20
4.8~H
n4
14-17
3.4~H
n5
22-21
13~H
---------------------------~~~~~~g:~~~~~
31/34
---------------------------
609
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r
m
~
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BY218-600
r
C
PLR811
t
:;
12V
G>
"~O.5A
:II
4;~0F
~
s:
~
~~
">lUI
'D~
I
~i!
Wo
~i:
@UI
~o
!l\z
T
lN4148
100pF
"
Small signal secondary ground
%% Power primary ground
c:::::J Secondary ground (isolated from mains)
POUT : 140W
f
: 32k.Hz
47nF
150pF
~ I:I'~'~
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APPLICATION NOTE
V. TV APPLICATION 11 OW ·220 VAC· 40kHz
REGULATED WITH OPTOCOUPLER
This application works in asynchronous mode. The
regulation characteristics are very attractive (output power variation range from 1W to 11 OW due to
automatic burst mode (see 11.6). In this configuration higher is the regulation loop gain, lower is the
output voltage ripple in burst mode (e.g. ouput
voltage ripple 0.8% with a loop gain of 15).
V.1. FREQUENCY SOFT START
The nominal switching frequency is 40kHz but during the start-up phase the switching frequency is
shifted to 10kHz in order to avoid the magnetization
of the transformer.
Otherwise the second current limitation will be
reached at high input voltage and hence the power
supply will not start.
Line regulation (1135: O.6A; 125. 1A)
Output 135V (± 0.30%) -> (21 OV < VDC <, 370V)
Output 25V (± 0.30%)
Influence of the audio output on the video out·
put
Output 135V (± 0.1 %) ->(1135 = 0.6A; 125 : 0 -> 1A)
Output 135V (± 0.05%) ->(1,35 = 0.3A; 125 : 0 ->1 A)
V.3. TRANSFORMER SPECIFICATION
Reference: OREGA.SMT5. G4576-02
II
o Mechanical Data:
- Ferrite: 850
- 2 cores: 53 x 18
x 18
(mm) THOMSON LCC
• Electrical Data:
Figure 43.
V.2. APPLICATION CHARACTERISTICS
• Discontinous mode Flyback SMPS
• Switching frequency: 40kHz
• Nominal mains voltage: 220 VAC
• Mains voltage range: 170 VAC to 220 VAC
• Output
power
30W < Po < 110 W
in
normal
mode
• Output power in burst mode: 1 W < Po < 30W.
The transient phase between normal mode and
burst mode is determinated automatically as a
function of the output power. Hence the regulation of the output voltage is effective for an output
power variation of 1W < Po < 110W
• Efficiency as full load > 80%
V90TEA2260/61·43
• Efficiency in burst mode (Po = 8W) > 50%
• Short circuit protection
Winding
Pin
Inductance
np
3-6
790llH
naux
7-9
5.4Il H
n2
19-13
3381l H
n3
19-?-0
4.81lH
n4
14-17
3.4Il H
n5
22-21
131lH
• Open load protection
• Long duration overload protection
• Complete shutdown after 3 restarts with fault
detection for TEA2260
• Complete shut down when VC2 reaches 2.6V for
TEA2261
Load regulation (VDC
=
310V)
Output 135V (± 0.15%) -> (1,35 : 0.05A to 0.6A;
125 = 1A)
Output 25V (± 2.5%) ->(1135 = 0.6A; 125: 0.25 to 1 A)
33/34
-------------- ~ ~~c~~:mg~~CJ~~ --------------
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!! :<
."'"
..,.t1
CQ
c:
.-c=;
:II
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7!
Z
Z
c
~
~
:!::
7.5V
lA
~
"'len
.:ft':-'
",en
~i!
l"Io
~:I
@en
~O
:l,lz
220 Q
l6W
'f SmaU signal secondary ground
~
~
Power primary ground
Secondary ground (isolated from mains)
POUT: 110W
f
: 40kHz
~
~
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CD r
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APPLICATION NOTE
TEA2018A-TEA2019
FLYBACK SWITCH MODE POWER SUPPLY IMPLEMENTATfON
By : J-Y.COUET & T.PIERRE
SUMMARY
Page
INTRODUCTION
3
II
TABLE OF UNITS AND SYMBOLS
3
III
111.1
CURRENT MODE REGULATION
IV
IV.1
IV.2
IV.2.1
IV.2.2
IV.3
IV.3.1
IV.4
IV.4.1
IV.5
IV.6
IV.7
IV.8
IV.8.1
IV.8.2
IV.8.3
IV.8.4
FUNCTIONAL DESCRIPTION OF TEA2018A .
OUTPUT STAGE (POWER TRANSISTOR BASE DRIVE)
......... .
Transistor turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Proportional base drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transistor turn-off . . . . . . .
Minimum conduction time . . . . . . . . .
12
12
12
12
V
APPLICATION EXAMPLE . . . . . . . .
12
V.1
V.1.1
V.1.2
V.1.3
V.1.4
V.1.4.a
V.1.4.b
V.1.4.c
V.1.4.d
CUSTOMIZED APPLICATION DESIGN .
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of power elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .... .
Transistor switching aid network . . . . . . . . . . . . . . . .
Demagnetization sensing . . . . . . . . . . . . . . . . . . . .
Risk of flux runaway without demagnetization sensing . . . . . . ..
. .....
Implementing the demagnetization sensing function . . . . . . . . .
Damping network . . . . . . . . .
Transformation ratio considerations .
12
12
13
13
13
13
14
14
15
V.1.5
V.1.6
OSCILLATOR . . . . . . . . . . . . . .
Power transistor base drive . . . . . . .
16
17
V.1.7
V.1.7.a
V.1.7.b
SELF-SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive self-supply: Vcc.
. ...................... .
Negative self-supply: V· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
.
3
3
DESCRIPTION . . . . . . . . . . .
BLOCK DIAGRAM
.............. .
OSCILLATOR AND MAXIMUM DUTY CYCLE .
Simplified diagram ..
Waveforms . . . . . . . . . . . . . . . .
ERROR AMPLIFIER . . . . . . . . . . .
Functional behaviour on low-load . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CURRENT MEASUREMENT & LIMITATION . . . . . . . . . . . . . . . . . . . . . .
Disabling the current monitoring function
...................... .
DEMAGNETIZATION MONITORING. . . . . . . .
. ....... .
THERMAL PROTECTION
................
TEA2018A BEHAVIOUR AS A FUNCTION OF Vcc
AN406/0591
. . .
. ........ .
. ........ .
5
5
5
5
6
6
7
7
8
8
9
9
11
19
1/37
613
APPLICATION NOTE
SUMMARY
Page
(CONTINUED)
V.1.8
V.1.9
V.1.10
V.1.11
Regulation . . . . . . . . . . . . . . . . . . . . . .
Operation under overload & short-circuit conditions
Operation on low-loads . . . . . . . . . . . .
Complete Application diagram . . . . . . . .
19
19
20
21
VI
FUNCTIONAL DESCRIPTION OFTEA2019 .
22
VI.1
INTRODUCTION . . . . . . . . . . . . . . .
22
VI.2
BLOCK DIAGRAM
22
VI.3
V1.3.1
V1.3.2
V1.3.3
V1.3.4
VI.3A.a
VI.3A.b
VI.3A.c
V1.3A.c1
V1.3A.c2
VI.3A.d
V1.3A.d1
V1.3A.d2
VI.3A.e
VI.3A.f
VI.3A.g
V1.3.5
DIFFERENCES BETWEEN TEA2018A & TEA2019
Oscillator . . .
VeE monitoring . . . .
Output stage. . .. . .
PLL . . . . . . . . . .
Operating principles
Internal structure ..
PLL input signal ..
Transistor turn-off Signal: Tswo .
Synchronization Signal. .
Characteristics of the PLL
Synchronization . . . .
Capture Range. . . . .
Output filter calculation.
Numerical application .
Holding range . . . . .
Synchronization signal and the input filter.
23
23
23
24
24
24
25
26
26
26
VI.4
VIA.1
VIA.2
VIA.3
APPLICATIONS . . . . . . . . . . . . . .
Typical application with synchronization .
TEA2019 configuration for power boosting
Monitor application . . . . . . . . . . . .
29
30
30
31
VI.5
SYNCHRONIZATION SIGNAL TRANSMISSION.
32
VI.6
V1.6.1
V1.6.2
V1.6.3
VI.6A
V1.6.5
V1.6.6
APPLICATION VARIANTS
Regulation by optocoupler .. . . . . . . .
V· generator . . . . . . . . . . . . . . . . .
Overvoltage protection . . . . . . . . . . .
Application without demagnetization sensing
Full shut-down at overload . . . . . . . . .
Oscillator (TEA2018A only) . . . . . . . . .
33
34
33
33
34
34
34
35
. . . . . . . . . . . . ..
27
27
27
27
27
27
28
VII
FIXED FREQUENCY DISCONTINUOUS MODE FL YBACK .
VI1.1
FUNDAMENTALS . . . . . . . . . . . . . . . . . . . . . . .
36
VI1.2
TRANSFORMER CALCULATION AND POWER SEMICONDUCTORS SELECTION
VI1.3
MULTI-OUTPUT FL YBACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
2/37
---------------------------~~~i@~~:~~©~
614
---------------------------
APPLICATION NOTE
I - INTRODUCTION
The aim of this application note is to provide the
designer with information on how to design and
implement a simple and low-cost switching power
supply around the TEA2018A SMPS Controller.
This publication has been sub-divided into 3 distinct
sections, namely:
- An overview of the current mode regulation
- Detailed description of TEA20 18A characteristics
- Application example of a 30W discontinuous
mode flyback converter operating directly on
220VRMS mains voltage.
This document also covers a description of
TEA2019 which replaces the TEA2018A in appli-
cations requiring power transistor turn off synchronization with an external signal.
This function is particularly useful in video applications where the switching transistor turn off is synchronized with the line flyback signal.
SPECIFICATION OF A TYPICAL APPLICATION
- Discontinuous Mode Flyback
- Switching Frequency: up to 40kHz
- Power: the power handling capability is determined by the amount of available base current.
Assuming a forced gain of 6 for the power transistor: • PMAX ~ 60W (TEA2018A)
• PMAX ~ 90W (TEA2019)
II - TABLE OF UNITS AND SYMBOLS
Symbol
Function
Unit
fREF
Reference Frequency (TEA 2019)
Hz
Hz
Hz
lOUT
Output Current
A
Ip
Primary Current
A
Is
Secondary Current
A
Lp
Primary Inductance
H
Output Power
W
Switching Period
s
Reference Period (TEA2019)
s
Transistor ON time
s
f
fosc
POUT
T
TREF
tON
tON(L)
ts
Switching Frequency
Oscillator free-running Frequency
Conduction time fixed by current regulation
s
Power transistor storage time
s
VAC
Mains RMS Voltage
VSE
Power Transistor base-emitter voltage
VIN
Input DC voltage
V
Vcc
Positive supply voltage
V
VRMS
V
VeE
Power transistor collector-emitter voltage
V
VOUT
Output Voltage
V
"'ICHARGE
11
Average current delivered by the PLL of TEA2019
A
Power supply efficiency
%
III - CURRENT MODE REGULATION
111.1 - Description
In current mode operation, the regulation is performed by monitoring the peak current through the
power switch (switching transistor).
- At every period, the conduction of the power
transistor is initialized by a clock signal issued
from the oscillator.
- The power transistor is turned-off when its collector current reaches the threshold level fixed by
error amplifier.
3/37
------------------------------ ~ ~~~©~9j~~~?©' -----------------------------615
APPLICATION NOTE
Figure 1 : Current Mode Control
r
OSCII,LATOR' ./1 A './1 .SAWTOOTH
V V V,
....
'-------~
UTPU
FILTER
'-----is
ISENSE
Q
R
IC
OUTPUT
FLIP·FLOP
ISENSE
t~
" "
n_
91AN2018/9·01
The main advantage of Current Mode Regulation
in Discontinuous Mode Flyback Configuration is
that it offers an efficient rejection of all input voltage
variations.
The peak current value through the power switch,
at constant output power, is independent of the
input voltage value.
Variations of the input voltage have no effect on the
error amplifier output voltage.
Figure 2
Constant Error Amplifier Output Voltage
PRIMARY
CURRENT
:~/:
__
____
di=L; --
L_~ __ --l~::------di
VIN>
di=Li
Full Input Voltage Rejection
91 AN2018/9-02
4/37
-------------------~~~~~;~~~e~9~~ ----------~-------616
APPLICATION NOTE
IV· FUNCTIONAL DESCRIPTION OF TEA 2018A
IV.1 . Block diagram
(all values given in the following block diagram are typical values ).
Figure 3
Vee
I
L _______________
:~
~
I--------::G-ro-un-:id 2 f----------,,-iv.
91 AN2018/9-03
IV.2 - Oscillator and maximum duty cycle
IV.2.1 - Simplified diagram
Figure 4
,----------------[
RI
I
I
:
Vlh(1):
I
I
I
I
I
I
I
I
I
I
I~
I~
I·~
I'"
I
I
I
I
I
L
I
I
r---------~
• During Ct charge: Vth(t) = 0.66 Vcc
• During Ct discharge: Vth(1) = 0.33 Vee
• Vth(2) = 0.56 Vee
I
1
I
I
I
I
I
I
I
______ I_y~~~~~~c~_ ~
91 AN2018/9-04
~ ~~~©~~~i~2~
5/37
-----------------------------617
APPLICATION NOTE
IV.2.2 - Waveforms
Figure 5
OSCILLATOR
SAWTOOTH
INTERNAL
CLOCK SIGNAL
COMPARATOR
MAXIMUM
DUTY CYCLE
OUTPUT
BASE
CURRENT
91 AN2018/9-05
PERIOD:
T~
+ tDISCHARGE
tCHARGE
• tCHARGE ~
0.66
• tDISCHARGE ~
Rt . Ct
0.66
RDISCHARGE . Ct
IV.3 - Error am plifier
- The error amplifier gain is internally fixed at 30dB
typical value.
Internally implemented compensation networks
set the frequency response characteristics.
- Voltage Reference : The value of the reference
voltage applied to the inverting terminal is 2.4 V.
Figure 6 : Error Amplifier Frequency Response Characteristics
40
........ ,
20
,
iii
..'"
'"'"
I
II
,
II
,
,
,I
-20
-40
,
,
,I
i
10
1
I
I
I
~
6:
I
,
,
,
,I
I
I
,
w
-100
,
,
,
,
I
1
10
,
I
,
I
I
II
I
II
I
I
II
II
,
,
,
! Phase
,
I
-200
11'Margin
I
I
=56"I
,
,'10000
I
,
,
,,
I
,
,
,
I
,
,
,
,
,
,
I
I
I
,
I
100
1000
FREQUENCY (kHz)
6/37
---------------~ ~~~l;mr~:!~~~
618
,
1
100
1000
FREQUENCY (kH:)
I
c
ain Margin .. 17 dB
1
I
10000
91AN2018/9-06
APPLICATION NOTE
IV.3.1 - Functional behaviour on low-load
When the feed-back voltage exceeds the regulation range, the comparator output remains in high
state thereby avoiding the initiation of any new
conduction cycle.
Figure 7
FEED-BACK
Q
ll-----jrt+:
:
tN
I
:
=~~'h ~ H ~
r
I
I
I
I
r
! !
r
I
I
I
•
t
.,
BASE
CURREtIT
3 1--ISENSE
L -_ _ _ _--I
91 AN2018/9-07
Consequence: On low loads, the conduction' frequency becomes lower than the oscillator frequency_
IV.4 - Current measurement & limitation
Peak current through the power switch is set by the
error amplifier output voltage.
Clamping the amplifier output voltage at O.63V will
result in limiting the ISENSE pin voltage at 1V level.
Figure 8
,,"'' CK 6 __
~
m
.:<
o
as
Jl
"0
R2
u..
llkO
Q)
Q)
ERROR AMPLIFIER
~ISENSE
b
. .
.. t
OUTPUT VOLTAGE ______________ 0.63 V
L-_________________._.. t
Rl
10.5 kO
L-----------~3
_ _ _ _ _ _ _ _ _,
,~~k, o~~ 11
I,:'
91 AN2018/9-08
In cu rrent Ii mitation :
V+ = 1.23 V - VBE = O.63V
)
__
___R_1__ =:> V(PIN3) = -1 V
V - V(PIN3) + ( VREF - V(PIN3) ) R1 + R2
------------------------------
~~~~@~~~~~~~
7/37
-----------------------------619
APPLICATION NOTE
IV.4.1 - Disabling the current monitoring function
conduction cycle (T1 period on waveforms of
Figure 9).
- All parasitics such as those generated by the
recovery of secondary-connected diodes (without RC filter) are eliminated (period T2 on Figure 9).
During oscillator saw-tooth flyback, the output of
the PWM comparator is disabled and consequently:
- The minimum conduction time tON(min) required to
discharge the snubber network is fulfilled whatever the status of ISENSE input at the beginning of
Figure 9
"'''~W'~~
Q
INTERNAL
CLOCK
SIGNAL
UJ n
.. t
I PIN 3 VOLTAGE I
,,
• I
91 AN2018/9-09
IV.S - Demagnetization monitoring
No new conduction cycle is allowed as long as the
pin? voltage remains higher than 0.1 V .
When used in Discontinuous Mode F/yback configuration, this function will inhibit any new conduction
as long as the transformer is not fully demagnetized.
It is obvious that this function offers efficient security in case of overload and short-circuits.
Figure 10: Demagnetization Sensing
Q
91 AN2018/9-1 0
Comments:
- Demagnetization monitoring feature can be used
to implement an on-off function.
620
- This function is disabled by grounding the pin?
APPLICATION NOTE
Figure 11 : Waveforms
~:hJ:.=l=~
-0.60
--~=-F~LJt=F-'b=. : : t=-D-=t- '- [j-t- I:...~-
==-=-
U
~
W
~
iz
"'w
«tr
Ill§;
U
t
I
I
I
I
II
:I
n;,
u
~
u
... t
.... t
u
91 AN2018/9-11
IV.6 - Thermal protection
When the junction temperature exceeds + 150°C, an on-chip protection device will inhibit any new
conduction.
IV.7 - TEA2018A behaviour as a function of Vee
Figure 12: Vee Monitoring Circuit
r-I
I
I
I
I
Vee MONITORING
INTERNAL
BIAS
Vee
~
'--_--'''GOOd'' 4.9 V 6 V
I
Undervaltage
I
L ____ -,
S
I
I
I
Q
FLlp·FlOP
R
I
Q
I
IL
____________________
~
91AN2018/9-12
------------------------------
~~~~©~~~:~~~
-----------------------------9/37
621
APPLICATION NOTE
Figure 13: Waveforms
VCC RISING
VCC(STAR1) (SV)
-----------1- --VCC(STOP) (4.9V)
SUPPLY VOLTAGE (V)
I
I
SUPPLY
CURRENT (A)
REFERENCE
VOLTAGE (V)
I 24v-,...I----:l....:----
~
t
~t
NEGATIVE
OUTPUT
~t
- --- -- - --- VeC(START)
---O.SSVee
---0.33 Vee
OSCILLATOR
VOLTAGE (V)
Vose
=Vee
91AN2018/9·13A
Vee FALLING
-------1
SUPPLY VOLTAGE (V)
- -
- -
- - VCC(STOP) (4.9V)
1
I
SUPPLY
CURRENT (A)
REFERENCE
VOLTAGE (V)
OSCILLATOR
VOLTAGE (V)
NEGATIVE
OUTPUT
1
1
1.6 mA (max)
F
1- 2.4V
rvwwvvJ-
.. t
0,66 Vee
-0.33 Vee
t
... t
.. t
... t
91AN2018/9·13B
10/37
----~-----622
51
SGS-1HOMSON
'II. ii)Jua::oo@rn~lia::"D'L'll0U Forced gain ~ -
~
Rs
RE
COLLECTOR
CURRENT
VtpIN3) ~ RE. Ic
1V.8.3 - Transistor turn-off
The power transistor is· turned-off by the application
of a negative base current. A 500ns typical interval
duration between the positive stage turn-off and the
negative stage turn-on, will prevent simultaneous
conduction of complementary output stages and
also abrupt transistor turn-off.
• tON(min)
= tIB(ON) + ts
• ts : Power Transistor storage time
91AN2018/9-16
v - APPLICATION EXAMPLE
V.1 - Customized application design
V.1.1 - Specifications
Output Power
3.3W
Effective Input Voltage
176 VRMS
Input Voltage for Start-up and Regulation
200 Voc
S;
VIN
S;
350 Voc
Regulation Input Voltage after Start-up
130 Voc
S;
VIN
S;
350 Voc
Transistor Reflected Voltage
VR~.210V
~
S;
POUT S; 30W
S;
VAC
S;
245 VRMS
Switching Frequency
f
Expected Efficiency
11
27kHz
Output Short-circuit Protection
Yes
Open-load Protection
Yes
2 Outputs
(5V, 2A), (12V, 1.5A)
~70%
--------------- ~ ~~~~m~:lP~~
12/37
624
APPLICATION NOTE
V.1.2 - Calculation of power elements (see also section 7.1)
• VIN(MIN) = 200V
iii
(where tON(l)
• Ip(AV)
tON(l} = 0 426
T
.
= conduction time fixed in current limitation mode)
= 0.214
iii
• Lp = 3mH
Ip(PEAK) =; 1A
e POUT(MIN) = 2.65W
• 5V Output:
ns S 0.029
np
IS(PEAK)
= 9.4A => Diode: BYW98 - 50
• 12V Output:
ns S 0.061
np
IS(PEAK)
= 7.05A => Diode: BYW98 - 50
• Transistor selection
} => BUV 46A
{ " IC(MAX} = 1A
· " VC(MAX} = VIN(MAX} + VR + VSPIKES ~ 800V
V.1.3 - Transistor switching aid network
Figure 17
"C = I(PEAK}. tF = 1nF
2.V
" 3RC = tON (MIN)
R ~ 1kQ [ for tON(MIN) = 3/ls]
" Diode: BA159
" Maximum Power dissipated in R :
P=
2"1 C [VIN(MAX}] 2 . f = 1.8W
91 AN2018/9·17
V.1.4 - Demagnetization sensing
a. Risk of flux runaway without demagnetization
sensing
In the absence of demagnetization sensing, the
converter will operate in continuous mode flyback
at power supply start-up and also in the case of
overloads.
Due to the minimum conduction time imposed by
TEA2018A, there will be risk.of flux runaway within
the transformer and the current through the transistor.
---------~~--- ~ ~~~~m~~~R~
-------------13/37
625
APPLICATION NOTE
Figure 18
m==
,
.......
, _ ______________;. CPMAX
oNlm;nl
x
::I
it
_
I
I
I
I
I
,
I
I
I
I
I
I
I
I
T
2T
3T
,
t
,
Flux runaway at start-up or in case of short-circuit: VIN _tON(MIN) > VLOSS . (
91AN2018/9-18
~ ). [T -
tON(MIN)l
(Where VLOSS Z 1.5 V is the voltage drop accross the rectifier diode and the resistive component
of secondary winding).
Combining tON(min) and demagnetization sensing
functions, will yield highly secure operation ensuring the following functions:
• magnetic flux monitoring
• efficient discharge of snubber networks
b. Implementing the demagnetization sensing
The winding used for circuit power supply will also
reflect an image of the induced flux. The value of
the resistor "Ros" used for this function is not critical
and can fall within: 10kQ < Ros < 47kQ range .
Figure 19 : Configuration Arrangement and Short-circuit Waveforms
", ~1 lw!:1ak
Voe
~
V
8
T
,I
t..,
p__ vu-
1VC E I
v,,"
2T
"0
m_l"~~,~
.-O.6V
t
91AN2018/9-19
No new conduction cycle may be initiated as long
as the transformer is not fully demagnetized. On
start-up, and in the case of overloads, the demagnetization sensing function will modify the frequency of the conduction cycles accordingly.
c - Damping network
Once the transformer has been demagnetized,
626
positive voltage oscillations produced by the discharge of resonant "Lp.C" network may result in
unwanted activation of the demagnetization monitoring function.
To prevent this problem, all that required is to damp
the voltage oscillations, as shown in Figure 21,
through "Ro - Do" network where diode Do "shunts"
the resistor "Ro".
APPLICATION NOTE
Figure 20
0:
W
End of
l:::;:W
WCJ
ci:<
o!:;
ti°
W>
...l
...l
o
U
I
I
:
:
I
IX
W
.... ~
New Conducllon
noral/owed
;?;!:;
0.
0
>
91 AN201 819-21
Figure 21
UNDERDAMPING
B
CORRECT DAMPING
OVERDAMPING
V"~
Ro+R«
2~
elay
i
I
I
Ro+R~ 2~
Ro+R»
2~
91 AN201 819-21
• Resistor:
Ro
~ 2~- R ~ 2.2kn
• Power:
o
• Diode:
(BA 159)
IRMS
~
Ip(RMS)
VO(MAX) ~ VR
+
VSPIKES
91 AN201819-20
d - Transformation ratio considerations
On initial start-up, due to demagnetization monitoring function, the value of conduction frequency will
rise in multiples of the normal operating frequency
"f" as illustrated below:
BEGINNING
END
OF
START-UP
OF
fin -----.. f/n-1 _
... _
f/2 -----..
START-UP
627
APPLICATION NOTE
Employing a conventionally calculated transformer, the converter will stop operating at "f/2" frequency.
Figure 22
.IS
nS Vo
np
Lp
200V).
The "Cs" capacitor will accelerate V- settling process upon the initial power supply start-up. Resistor
"Rs" is used to limit the current upon the negative
power supply setup.
Figure 27
R
1N414B
1N4146
Figure 26
n
Cs
10llF
91AN2018/9·27
3.9V
91 AN201 B/9·26
The RC filter attenuates the parasitics due to voltage spikes generated by switching. However, the
cut-off frequency of this filter must be sufficiently
high so as to avoid excessive slow-down of the
regulation loop response.
V.1.9 - Operation under overload & short-circuit
conditions
• IAV
=
Is x ~
T
=
15 mA
(VIN. n:)-<1V-IV-ll
• RS(MAX) = - ' . - - - " - - - - - - - I(Av)
= 230Q (@ VIN = 200V)
Prefered value: Rs = 150Q
In case of any overload, the secondary voltage will
fall, circuit power supply will drop below VCC(STOP),
consequently TEA2018A stops operating and its
power consumption will fall under the current supplied by the start-up resistor.
The capacitor of "Vcc" begins charging up and a
new conduction cycle will be initiated as soon as
"Vcc" reaches "VCC(START)" level.
The system will function in relaxation mode as long
as the overload persists.
19/37
-------------- ~ ~~;~@mgm~~L~ --------------
631
APPLICATION NOTE
Figure 28
POSITIVE
SUPPLY
VOLTAGE
cg~~~~~~R 11---..1~---..I[]~----L~-----L~--~I--LI-----n n IIENVELOPE
...
-t
L_______
I
• 1
Short-circuit
91 AN2018/9-28
V.1.10 - Operation on Low-loads
When the output power lalls below:
p
=
OUT(MIN)
(V ,N
• t(ON(MIN/ .
2 . Lp
I.
the regulation becomes incompatible with the operating Irequency "I", conduction cycles occur in a
random lashion and at a frequency lower than "I".
11
Figure 29
OSCILLATOR
SAW·tOOTH
COLLECTOR
CURRENT
~
h_
I
I
.. t
I
:
llON(min)
H
r1
... t
91 AN2018/9·29
Note: This event has no impact on the power supply reliability.
20/37
--------------------J:fi ~~~;mgJ'~l~,,~lj
632
---~----------
"T1
to· :<
e
@
Ul
0
T
I
-.-~-:~
H;J' :
: ~., "F I!
47~F
~.Il
2x12mH 1
I
~jcn
~n
~Ljg
I
~cr
~i!
~o
.
I
J
;""·L.l4.7k!l
~
I
.
....
1111
~I
Ii
!
1
12 V
1
~
J,
[
;!.;
"Q.
o·
o·
r:"1
1~21
r-="1
'=
nO
I
0"""
...,
.
BYW 98·50
0 UB~BO~
5;
L:....JllN41484
TEA 2018 A
r:t
4. 70
-
I
co
~
1S9::f
I
0
"0
»
"0
~
BA·
:
0
3
CD
'OOO~F"'"
....
..!.J
47
k!l
,
220V AC
C::i
~
~ .+
1SV
I
Lj___~....J
05A
I..
I ~::~;N4148!
'
:~~FI:I ~1k!l
~
Q
BYW98·50
680
I n T.l. 4.7~F
T Ii
I
I I ill
~=F==~f=====~====~============~--~
I
~
I
i
RF Filter I
12~W
3B5V
1N4148
:.....
11 2.3W
2 }ill
~
1
!
•
4700~F
~
+
sV
0
iii'
<0
til
3
Lr-rJ '"
f?~y "JBAi IO::
46A
1500
1159
y".
1 nF
;: 1 kV
",3:::
1
.~
81)2
»
"tJ
"tJ
(J)
w
w
~
W
--J
II 3.5W ::; POUT::; 30W
III Output short-circuit protection
II Outputs:
II Open-load protection
• 5V . 2A
• 12V . 1.5A
r
n
~
o
z
z
o
-I
m
APPLICATION NOTE
VI - FUNCTIONAL DESCRIPTION OF TEA2019
VI.1 -Introduction
The TEA2019 has an internal architecture similar
to TEA2018A and offers the following additional
features:
- a true positive current source providing linear
charge-up of the timing capacitor "Ct"
- an internal PLL which allows syncl\ronization of
the power transistor turn-off with an external clock
signal
- power transistor desaturation monitoring
- possibility to dissipate externally the power required for transistor base drive
VI.2 - Block Diagram
Figure 31
IS
Vee
.-----------.., 5 ~--------__I31---------~
Vee "gooCr
PHASE
LOCKED
LOOP
Bias
n.
Demagnetlzatlon
Sensing
Sampling
Pulse
&
___ ..1
L-_ _ _ _ _ _ _ _ _ _~12~---~11~----~
ISENSE
Ground
VeE Monitoring
V-
91AN2018/9-30
22/37
--------------~ ~~~@lt&~If[0l~~
634
APPLICATION NOTE
V1.3· Differences between TEA2018A & TEA2019
V1.3.1 - Oscillator
The oscillator saw-tooth waveform is linear. The
capacitor "Ct" charging current is constant and is
determined by the value of resistor "Rt".
Figure 32
ooovccP=u:::
TEA 2019
0.33VCC
I
I
o
I
I-----...J
I
T
..
• T = tCHARGE + tDISCHARGE
• T = 0.69 Ct (Rt + 2000)
• Maximum Duty Cycle = 80 %
91 AN2018/9-32
V1.3.2 - VCE Monitoring
If during the power transistor conduction period the
pin 4 voltage exceeds 3.2V, the transistor would be
turned-off until the next conduction cycle. To disable this function, pin 4 must be grounded.
Figure 33
vee
10 kQ
• T1 = Transistor turn-off by
desaturation monitoring
•T2 = Transistor tu rn-off by
regulation
SIMPUFIEO OIAGRAM
91 AN2018/9-33
23/37
------------------------------ ~ ~i~~~2~~~~~~ -----------------------------635
APPLICATION NOTE
V1.3.3 - Output stage
An external resistor connected between Vcc and
VAUX will dissipate a portion of the power required
by the base drive. The value of this resistor is
calculated to be as large as possible but appropriately dimentioned to. avoid the saturation of the
output stage 01.
- Power dissipated in OJ (Flyback) :
P
18(MAX)
SE)'-2~-
(R
s+
R)
.
1!lIMAX)]
3
- Power improvement compared to TEA2018A:
~p
Y
Figure 34
tON [ (V
V
=-=r
ee-
2 . R. ISIMAX)
= 3 (Vee - VSE) - 2 . Rs . IS(MAX)
{at: Vee
= + 9 V =>
~:
= 0.5
i.e.
2 (Vee - 3.5 V)
Vee - 5V
50%}
R
91 AN2018/9·34
R
= Vee -
VSE - VeE(MIN)
IS(MAX)
Rs (where VeEIMIN)
~ 1.5 V)
VI.3.4 - PLL
In a discontinuous mode flyback configuration, the
power transistor turn-off produces significant
amount of noise. It is therefore interesting to synchronize this event with an external signal.
Since the transistor turn-off instant in current mode
operation is generally unknown, consequently, only
phase and frequency locking of the oscillator will
enable to synchronize the transistor turn-off time
without disturbing the voltage regulation loop.
a. - Operating principles
Oscillator phase and frequency can be accurately
controlled by adjusting the charge current of "Ct"
capacitor. The PLL behaves as a current generator,
the direction and the magnitude of which are function of the phase difference between transistor
turn-off and the synchronization signal.
Figure 35
~ICHARGE< 0
~ICHARGE> 0
Tosc
Vcc
ICHARGE
=2RT -tJ.lcHARGE
91 AN2018/9-35
24/37
------------------------------~ ~~~@~g~~~~~
636
------------------------------
APPLICATION NOTE
b - Internal structure
The major building block of the PLL is an analog
multiplier whose two inputs are the synchronization
signal and power transistor turn-off monitoring sig-
nal. Multiplier output signal has a complex spectrum; a low-pass filter is employed to extract the DC
and low-frequency components.
Figure 36
Sync. Pulse
/!
(fREF ,TREF)J
I7
91 AN2018/9·36
Figure 37 : Synchronization configuration waveforms
Tswo
0
•I
SYNCHRONIZATION
PULSES
f'-
'"en
ro
(;
N
Z
«
Oi
PLL
OUTPUT
CURRENT
I
I· Ts
D-
--+-i-Tsl2
I
I
I
I
I
o~ ~
~A
0
I
II
I
I
In phase
Maximum Delay
O
-W-Tsl2
I
I
[
[
I
lL
~
d
Maximum advance
The PLL will source or sink the maximal current when the shift interval between synchronization signal and
the transistor turn-off equals tsl2 .
637
APPLICATION NOTE
c - PLL input signal
c1 - Transistor turn-off Signal: Tswo
Due to transistor storage time, the PWM compara-
tor will generate a pulse which will be used as Tswo
signal.
Figure 38
o
(SENSE
CO~~~~OR
BASE
CURRENT
IS:lf___
,------~
t n
t .I
~ I
VEA
~
~t
......-&
I~
o
U
•
t
91 AN2018/9-38
c2 - Synchronization Signal
The characteristics of synchronization signal are
outlined in section 6_3.5.
d. - Characteristics of the PLL
d1 - Synchronization
When synchronization occurs, the average current
delivered by PLL is equal to dlcHARGE required for
frequency compensation.
Figure 39
TEA 2019
Tswo
SYNC.
(TREF)
.
,
~
I
tl~LL_j_
Fr
I d ICHARGE I = ~
I f rPLL(dt) + f IPLL(dt) I
91AN2018/9-39
-------------- ~ ~tmt"~~~
26/37
638
APPLICATION NOTE
d2. - Capture Range: I fa - fREF I MAX
The signal delivered by PLL prior to synchronization has I fa - fREF I component. GdB is the overall
gain of multiplier and filter stages. Phase locking is
possible if the frequency difference I fa - fREF I satisfies the following relationship:
GdB I fo-fREF I ~ 0 db
Figure 40
I
I
I
I
I
f3
c
I .,.el
L ______
f =
1
_!til
I
Log. fose - fREF
Rt
I
91AN2018/9·40
I
--1
R + R1
f3 = 2 It . C . R . R1
1
2 It (R + R1) Cl
e - Output filter calculation
R1
Go - G, = -20 log R + R1
For stability reasons, the output filter is calculated
at gain Gl ~ 0 dB.
- "f2" frequency determines the capture range.
- "f3" frequency is equal to the free-running frequency"fo".
- The "Go" gain is rather complex to evaluate. By
approximation, it is proportional to the switching
transistor storage time "ts".
At ts = 21ls , the gain Go = 24dB
f - Numerical application
The following calculations yield the optimum value
of capture range:
2 rr R1C1
R + R1
2rr. C. R. R1
=> R1
~
3.9kQ
=> C,
~
22nF
=> C ~ 3.3nF
g - Holding range
Once the capture occurs, the free-running frequency "fose" can rise within the holding range
without causing loss of synchronization.
When synchronization is achieved, the filter no
longer introduces any attenuation and thus the
holding range becomes larger than the capture
range.The holding range is given by :
• fa = 15.6kHz (switching frequency)
• f2 = 2.2kHz
(this is the selected
capture range ± 81ls with
respect to 641ls period)
Gl = OdB, Vee = 8V, ts = 21ls, Ct = 1.5nF ,
Rt = 56kW , Go = 24dB
R = Rt yields excellent noise immunity.
Ll. T = TREF . _ _ _-'-1- - -
I + 0.33 . Vee. CT
IpLL . ts
Where:
- TREF: the period of synchronization signal
- IpLL : the maximum current the PLL can source or
sink (0.7mA typ)
27/37
---~-------------~~ii;~~~~~~~~~ -~---------------639
APPLICATION NOTE
V1.3.5 - Synchronization signal and the input filter
The synchronization signal applied to PLL input (pin7) must respect the following conditions:
Figure 41
TREF
dv/dt> 0
PIN7VOLTA~
"I!
(V)
r:r:
•I
I"'
~_I
O.55V(typ)
2.5V (max)
I--l
Synchronization Range
91AN2018/9-41
The TEA2019 has been particularly designed for
video applications where the synchronization signal is obtained from the flyback signal generated
during the line flyback.
Figure below illustrates the configuration arrangement used in such applications.
Figure 42
VSYNC
I
'" 20kn
eI
-r~
f'
I~~
• In typical application: C3 = 47nF, C2 = 33nF
• R2 is calculated as a function of :
e
R2 '"
C2 log (
VSYNC )
VSYNC- VIN
91 AN2018/9-42
28/37
-------------~~~@mg:~~~1 --------------
640
"
tE·
.
BYT 11-800
-
~F
r
160V
.
~~
:....
"""
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(!)
to)
100 ~F
m
147
385 V
120V - OAA
::;;::;;
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c:
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() III
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BYT 11-800 24V - 0.5A
'1'470 ~F
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=>
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g
en
=>
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=>
0
=>
~
N'
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0=>
~cn
[~~
Mains
Input
18·
ee,",
~:I:
6;0
il
3.1N4001
»
"'0
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»
z
OJ
• PMAX; 60W
111 OutputS:
• Free-running Frequency: 15 kHz
III VCE Monitoring
~
OJ
en
~
IU
I~
16
• 155 VRMS s VAC s 250 VRMS
• 120V ± 3% .0.4A
• 24V±3%. 0.5A
r
o
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oz
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m
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=100
+ 24V
3.3 kll.
385V
+ 60~
0.5A
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22 k!l
10 k!l
4.7 kll
d:':
0 : :!
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90 - 260 VAC
OV\1fav
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ClC"l
BUI
O·
00.47
~:i!
U
Flyback Pulse
from
EHTTransformer
810
iii:
~UI
",0
10)2
3 x lN4001
»
"C
• Input voltage range: 90 VAC to 260 VAC
~
»
z
I\)
Ol
-I>
W
I~(;j
"
s:en
I~
• Scanning Frequency: 32kHz
iii Output:
• 60V + 1.5%, 0.5A
• 24V ± 2%, O.4A
I!Il Synchronization signals is transmitted via an
optocoupler inserted within the regulation loop.
• 20W:o;
POUT:O;
40W
"C
r-
o»
-t
oZ
Z
o-t
m
APPLICATION NOTE
VI.5 - Synchronization signal transmission
This signal is often generated from the secondary
of the power supply, and therefore requires gal·
vanic isolation.
Two solutions outlined below are both appropriate:
Figure 46 : Transmission through EHT transformer winding
Well-insulated wire
I
Ii\.
I
~
I . 4TI--~
'tEA 2019.
PrImary
Secondary
91 AN2018/9-46
Figure 47 : Transmission via the Optocoupler of Regulation Loop
~_----j=--
Vee
2.21<0
"tfov
Sync
Pulse
TEA 2019
Primary
Secondary
91 AN2018/9-47
In this configuration, the optocoupler is used for the transmission of both, feed-back voltage and the
synchronization signal.
32/37
~~----------------~IF~~~wf~~4
644
---------------------------
APPLICATION NOTE
VI.6 - APPLICATION VARIANTS
V1.6.1 - Regulation by optocoupler
Figure 48
I I
91 AN2018/9·48
V1.6.2 - V' Generator
Figure 49
3.3V
1W
Up to IC(AVI = O.SA
Up to ICIAVI = O.2SA
V1.6.3 - Overvoltage protection
Figure 50
Vz
Vee
TEA2018A
OR
TEA 2019
91AN2018/9·50
33/37
--------------- ~ ~~~o~~~~~~ ---------------
645
APPL.ICATION NOTE
VL6.4 - Application without demagnetization sensing
If the condition given below is satisfied, the demagnetization sensing function can be omitted without
(V OUT
+ V LOSS)
any risk of flux runaway in case of short-circuits or
at start-up.
V
::; V LOSS
T-t
IN(MIN)
T-t
ON(MIN) •
V1N(MAX)
tON(MIN)
~
tON(MAX)
Consequently, the damping network is no longer required and the "demagnetization sensing input" can be
grounded.
VL6.5 - Full shut-down at overload
In case of overload, the arrangement depicted below will completely shut-down the power supply. To re-start
the system, capacitor "C1" must be discharged.
Figure 51
>--..---.-__ H.V.
C1
a~t
:I:~
>
470 kn
~~--------------------.re-start inhibited
::;~
R
Vee
C2
a.c(
a.~
~o
~>
12V
L-L-L-______
~--~
____- .__
+
12V
Overload
C2
~·10
R~
C1
220 n
91 AN2018/9·51
VL6.6 - Oscillator (TEA2018A only)
Figure 52
Rt
Rt
OR
Both configurations are functionally equivalent
91 AN2018/9·52
34/37
---------------------------~~i~~~~~~~
646
---------------------------
APPLICATION NOTE
VII- FIXED FREQUENCY DISCONTINUOUS MODE FLYBACK
VI1.1 - Fundamentals
An operating phase includes 3 phases:
• tON S t s tdm : energy transfer toward the secondary
winding
• 0 s t s tON : energy is stored within the primary
inductance
• tdm S t s T : dead time, the transformer is fully
demagnetized.
Figure 53
t dm < t < T
K : closed
K: open
K : open
D : conducts
D: blocked
ns
Vo = Vour +- VIN
np
dis
dt -
Energy stored during tON
(V t )2
W=~
LP
2L
P
Transformer Flux
d 4> --L dIs
dt- Sdt
VIN
91AN2018/9·53d
35/37
--------------------------- ~~~~@~2:~2~ --------------------------647
APPLICATION NOTE
VII.2 " Transformer calculation and power semiconductors selection
Figure 54
Ip(AVERAGE)
tON
tON~T
-
VOUT=VINT
2Lp
1
o
T
tON
tdm
91AN2018/9-53d
• Maximum operation duty cycle:
(1)
VR
tON(L) =
T
VR + VIN[MIN)
(2)
VR
tON[L) _
T - VR + -Y2 . VIN(MIN)
POUT(MAX)
1
.--11
VIN[MIN)
• Maximum average primary current:
Ip(AV)MAX =
• Maximum peak primary current:
T
Ip[PEAK) = 2 Ip(AV)MAX . -tON[L)
• Primary inductance:
tON(L)
Lp = VIN(MIN) . I
P[PEAK)
• Maximum transformation ratio:
(1)
( ns )
= [VOUT + Vo 1[ T - tON(Lll
np [MAX)
VIN[MIN) . tON(L)
(2)
( ns )
_ [VOUT + Vo 1[T - tON(Lll
np [MAX)VIN(MIN) . tON(L) . -Y2
• Peak rectifier current:
T
IS(PEAK) = 2 IO~T (ldm _ tON)
• Minimum power transfer at frequency "f" :
POUT(MIN) = 11 .
Where:
[ VIN(MAX) . tON(MIN) f
.f
2. Lp
(1) : without demagnetization monitoring
(2) : with demagnetization monitoring
• tON(L) : Conduction time before current limitation
36/37
--------------------------~~~~~~J?I
648
--------------------------
APPLICATION NOTE
VI1.3 - Multi-output flyback
All transformer windings undergo the same flux change of dljJ/dt. Regulation of any output causes regulation
of all other windings.
Figure 55
91 AN2018/9-55
----------------------------~~~~~~g~~~?G~
37/37
----------------------------
649
APPLICATION NOTE
AN AUTOMATIC LINE VOLTAGE SWITCHING CIRCUIT
VAJAPEYAM SUKUMAR
THIERRY CASTAGNET
ABSTRACT
90V - 132V range.
The voltages found in line sockets around the
world vary widely. Power supply designers have,
most often, overcome this problem by the use of
a doubler/bridge switch that can double the
120V nominal line and simply rectify the 240V
nominal voltage.
b) 240V nominal, 50Hz systems. Equipment has
to be designed to run in the 187V-264V
range.
A two device solution (comprising an integrated
circuit and a customized triac) that will adapt the
power supply to various line voltages around the
world is described in the following paper. This
circuit replaces a manual switch and could also
open special markets. Other advantages of this
integrated circuit solution are ease of circuit design, lower power dissipation, a smaller component count and additional safety features.
Power supplies built to run off these voltages
have to be either wide range input or must use a
doubler/bridge circuit. The disadvantage of the
wide range input scheme - that all components
have to meet worst case current and voltage requirements - makes such a solution popular only
at less than 75W power levels. The popular
doubler/bridge circuit is shown in Fig. 1. When
the AC input voltage is 120V nom. (doubler
mode) the switch S1 is closed. During the positive half cycle of the input voltage capacitor C1
is charged. During the negative half cycle of the'
input voltage, capacitor C2 is charged to the
peak line voltage. When the line voltage is 240V
nom. (bridge mode), the switch S1 is open and
the circuit works like a conventional bridge rectifier.
INTRODUCTION CIRCUIT.
A good reference for the various line voltages
around the world is found- in [1).
THE DOUBLER/BRIDGE
AC line voltages the world over can be divided
into two main categories:
a)120V nominal, 60Hz systems. Electronic
equipment is usually designed to run in the
Figure 1.
Schematic Diagram of a Doubler/Bridge Circuit.
Cl
Sl
!
12:,
6~Hz
24~V.5~Hz
AN389/0191
0
24..."l ~~i@m~ml~~©~ ___________-'--3_/6
653
APPLICATION NOTE
Figure 4.
AVS10 Block Diagram
r,-----------MODE
7 -------"
""
"' - - -
M.
2--11
I
I
I
I
I
I
I
OSC/IN
OSCfO~ _
'----;1
__
~
__________________ //
The series circuit of D1, R6, R7 and C2 provide
power for the chip. Pin 1, Vss, is a shunt regulator that provides a -9V (nom.) output. R1 and R2
are resistive divider precision resistors that are a
measure of the input line. The voltage at Pin 8
varies with the input line. Thus the voltage at Pin
8 is not only a measure of the peak input voltage, but it can also sense line voltage zero
crossing. Pins 2 and 3 are inputs to an oscillator.
The resistor R3 and C1 set the oscillator frequency. Pin 5 drives the gate of the triac thf;,ough
a 3900 resistor. Pin 7 offers the user a choice of
two different modes of operation. The block diagram of the IC is given in Fig. 4.
1. Decreased Power Dissipation.
Decreased power dissipation is an important advantage of the AVS10. While most discrete AVS
schemes need 5W to 12W of power, the AVS10
uses about 2W. This performance is thanks to
an innovative gate triggering scheme (Patent
Pending). The gate current is made up of a
pulse train that has a typical duration of around
23~s (45kHz+/-5%). The duty cycle of the
pulses is typically 10%. The values of R2 and
C3 in Fig. 3 are chosen to give us the pulse
frequency.
2. Immunity To Voltage Transients.
The triac of the AVS1 0 is a sensitive gate triac
that is specified to remain off when subjected to
dv/dt of 50V/~s. Circuit layout is critical in preventing false dv/dt turn on of the triac [2]. The
IC of the AVS10 circuit has a built in digital filter
that suppresses the effect of all spikes of less
than 200~s duration.
3.
Operating
Vrnode = Vss.
In
The
Failsafe
Mode.
The mode pin on the AVS10 IC, Pin 7 deter'
mines the behavior of the circuit if it is turned on
into a line surge/sag situation. If Pin 7 is tied to
Vss (Pin 1), the AVS10 circuit is in a failsafe
mode.. This means that if .the device is turned
into a bridge mode, it will remain in the bridge
mode, even if the voltage were to suddenly dip
into the 11 OV range.
4. Operation In Reactive Mode. Vrnode
= VDD.
If Pin 7, the mode pin, is tied to VDD, then the
device will switch between bridge and doubler
modes if the input voltage changes. If the 11 OV
input changes to 220V, then the AVS10 turns
the triac off by the next mains cycle. If the 220V
input falls to 110V, the AVS10 circuit has a validation period of 8 mains cycles ( when it verifies
that the voltage is still at 110V) after which the
triac turns on. Thus, safety features are built into
the AVS10 circuit. Typical timing diagrams for
the two modes are given in Figs. 5 and 6.
-~_6-----------------------~~l ~i~@~~~~~~~~------------------------654
APPLICATION NOTE
Figure 6.
Timing diagram·
Vmode = Vss
Yac(RMS) .
240V
120V
I
TRIAC FIRING ORDER
1-TRIAC ON : O-TRIAC OFF
o
It
Tdelay
Figure 5.
Timing Diagram -
Vmode
<1 cycle
= Vdd
Yac(RMS)
240V
120V
TRIAC
~IRING
I
ORDER
1=TRIAC ON \ O=TRIAC
I
6FF
I
o
Tdelay
II
<1 cycle
------------J..-yl
8 cycles
<1 cycle
5/6
~~~@mY:l~~~~ - - - - - - - - - - - - = - - : : .
655
APPLICATION NOTE
A detailed account of how to set the input voltage threshold is found in [2].
1. High Efficiency. Losses are just 2W vs.
5W-10W for discrete schemes.
5. Additional Safety Features.
2. Safety. Uses digital spike suppression,
hysteresis, validation of range, a failsafe
mode and good control over. the triac trigger·
ing.
Additional steps are taken to enhance the safety
of design include starting up always into the
bridge mode. There is a delay of around 250 ms
at start up before the AVS10 goes into the doubler mode.
Hysteresis is also built into the comparator to
prevent small line voltage variations from causing toggling between bridge and doubler modes.
Only a voltage variation of over 10% of the line
voltage can cause the AVS1 0 to change modes.
3. Space Optimization., small supply resistor.
Good reliability.
4. Ease of Use. Eliminates manual line selection errors.
5. Suitable solution for various power range:
AVS10 up to 300W
AVS12 up to 500W.
CONCLUSION
REFERENCES.
This paper describes an efficient way of implementing an automatic doubler/bridge circuit. The
primary use of this circuit is in 75W to 500W
SMPS. Other innovative uses are possible. One
example would be industrial motor drives which
can be designed to accept either 120V line-toneutral or 208V line-to-line input.
The main advantages of the AVS1 0 solution are:
6/6
656
[1] PSMA Handbook of Standardized Terminology for the Power Sources Industry.
Appendix C.
[2] SGS-THOMSON technical note 'How To Use
The AVS Kit'.
APPLICATION NOTE
HOW TO USE THE AVS KIT
PRELIMINARY NOTE
I DESCRIPTION OF THE AVS KIT:
The AVS10, or AVS12, is an automatic mains
selector to be used in on line SMP supply with
Power up to 500W. It is made of two devices.
!
This switch modifies automatically the structure
of the input diodes bridge in order to keep a
.same DC voltage range.
C2
110V
OR
nov
------------------ Cl
G
vss
AVS10CB
or
AVS12CB
16K/l %
I
1 MOil %
The AVS is compatible with 50 and 60 Hz mains
frequency and operates on two mains voltage
ranges:
- On range I (110 VRMS) the AC voltage varies
from 88 to 132 V and the triac is ON : the
bridge operates as voltage doubling circuit.
-
On range 1\ (220 VRMS) the AC voltage varies
from 176 V to 276 V and the triac is OFF :
the circuit operates as full wave bridge.
II PERFORMANCE OF THE AVS :
The control of the switch is made by the comparison of the mains voltage (VM on pin 8) with internal threshold voltages (VTH and VH on pin 8).
AN390/0191
When mains voltage increases from range I to
range II the triac conduction is completly stopped
before one mains period because VM > VTH.
When mains voltage drops from range II to
range I VM becomes lower than VTH - VH.
There are two options (V mode on pin 7) :
-
V mode = VDD ; the triac triggering is valided
8 mains periods after power on reset.
V mode = VSS ; the triac control remains
locked to range II until circuit reset.
III USE OF THE AVS :
Calculation of the oscillator:
114
657
APPLICATION NOTE
The oscillator frequency is determined by the
mains frequency (50 and 60 Hz) and the gate
control : its required value must be 45 KHz ±
5%; so the value of components is :
C = 100 pF/5%
R = 91 KOhms/1%
C = supply capacitor = 33 flF
VRMS = mains voltage
Iss = quiescent supply current of AVS
Supply of the controller:
The frequency control is made on pin 3.
The structure of the supply regulator is a shunt
regulator and its current must be lower than Iss
max = 30 mAo
Adjustement of the mains mode change:
The measure of the mains voltage is made by a
detection of the peak value.
The change of mains range is made by adjustement of resistor bridge and we advice:
800 kOhms < R1 + R2 < 2 mOhms
Calculation of the change from range I to range
II (on pin 8) :
In order to have a good behavior of the circuit
against mains voltage spikes the pin 4 (VDD) of
the integrated circuit has to be connected
straightly with the A1 of the triac. In same way
the supply diode rectifier and R1 have to be connected to the diode bridge (see typical application piagram).
Triac control :
[VTH . (R1 + R2)]/(R2 . ...J2) + Vreg I ...J2 =
max.RMS voltage on Range I
Vreg typ = - 9 V and VTH typ = 4.25 V
Calculation of the change from Range II to
range I :
[(VTH - VH) . (R1 + R2)/R2 . ...J2] + Vreg I ...J2 =
min. RMS voltage on range II
Vreg typ
= - 9 V and
VH typ
= 0.4
V
Performance of the power on reset:
The power on reset permits the charge of the
bulk capacitors of the SMPsupply through soft
start circuit.
The triac triggering is valided (on range I) after
the validation of power on reset (charge of supply capacitor C) and a temporization of 8 mains
periods.
T delay = delay time between power on and
triac triggering
Td = 0,89 . Vreg . R . C/[(VRMS . ...J2/n)- R. Iss]
+ 8/f
f = mains frequency
R = supply resistor = 18 kOhms
658
Between pin 5 and triac gate there is a resistor
in order to limit the gate current; its value is
given by the controller supply and triac ; the required value is 390 Ohms (5%).
Thermal rating of triac:
The knowlegde of the maximum triac current ITM
and the current pulse width tp in worst case conditions allows to calculate the losses, PT dissipated by the triac:
ITAM = RMS triac current
= ITM x ...Jtp x ...Jf
PT = 4 . tp . f . hM . VTOln
+ rt . tp . f . (ITM2)
for AVS10CB :
VTO = threshold voltage of triac = 1.1 V
rt = on state triac resistance = 49 mohms
for AVS12CB:
VTO = 1V
rt = 45 mOhms
The figure 1 of DC general characteristics of
triac gives these losses PT versus ITRMs for this
application. The figure 2 allows to calculate the
external heatsink RTH versus PT and Tamb
when Tj = 110C
Tj - Tc = RTH j-c AC . PT
Tc - Tamb = RTH . PT
APPLICATION NOTE
Example on AVS10 :
so
100
I'.: .\1\
o
2
3
!J
•
IT IRI4S) IA)
6
7
e
,
10
30
50
110
130
110
Figure 1 and Figure 2 of AVS10 Datasheet
if tp
= 2ms and
ITRMS
= 5A
- PT = 3.SW
-Tc = 100°C
if Tj = 110°C
- RTH = 7.5 °C/W if Tj = 110°C and
Tamb< 70°C
Annex: AVS demo board
COMPONENT LIST FOR AVS10.
DESIGNATION
PRINTED CIRCUIT
RESISTANCE
RESISTANCE
"RESISTANCE
RESISTANCE
RESISTANCE
DIODE
CONDENSATOR
CONDENSATOR
TRIAC
INTEGRATED CIRCUIT
SUPPORT
INVERTER
SOCKET
PLUG
QTE
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
REFERENCE
4751
R1
R2
R3
R4
R6
D1
C1
C2
IC2
IC1
SW1
SL3W
BL3
_ _ _ _ _ _ _ _ _ _ _ t=='
..'Y1
OBSERVATIONS
1 MOhms 1%
1S KOhms 1%
91 KOhms 1%
9.1 KOhms 1W
390 Ohms 5%
1N4007
100 pF 5%
33J.lF 16V RADIAL
AVS10CB / AVS12CB
AVS1ACPOS
CIS PINS
MINIDIP
3 PINS
3 PINS
MARQUE
SGS-THOMSON
SGS-THOMSON
WEIDMULLER
WEIDMULLER
SGS.mOMSON _ _ _ _ _ _ _ _ _ _3_/4
Ii'j]D©OO@I'lu'I'l©1i'OO@[i:!]D©~
659
APPLICATION NOTE
Products PIN out
VM
Mode
VSS
Osclin
Osc/Out
Nc
VG
VDD
TO 220 AB
(Plastic)
DIP-8
(Plastic)
Components layout
--QgC2
Cl
C3
~
e
e
e
R
0
---1
.5
KO
---1
G
0
D
At
~
~
~
~
u••0
EJ
G
~
€V
leI
•
s
B
Printed circuit layout (Copper side) : 1/1 scale
- 4 / 4 - - - - - _ - - - - i ....
'L SCiS-THOMSON---------•J
~U©Ilil@[lllblli©'ITOO@lllU©ij)
J,
660
APPLICATION NOTE
POWER SUPPLY DESIGN BASICS
by P. ANTONIAZZI
Aimed at system designers whose interest focusses on other fields, this note reviews the basic power supply design knowhow assumed in the rest of the book.
In mains-supplied electronic systems the AC input
voltage must be converted into a DC voltage with
the right value and degree of stabilization.
Figures 1 and 2 show the simplest rectifier circuits.
In these basic configurations the peak voltage
across the load is equal to the peak value of the AC
voltage supplied by the transformer's secondary
winding. For most applications the output ripple produced by these circuits is too high. However, for
some applications - driving small motors or lamps,
for example - they are satisfactory.
If a filter capacitor is added after the rectifier diodes
the output voltage waveform is improved considerably. Figures 3 and 4 show two classic circuits commonly used to obtain continuous voltages starting
from an altemating voltage. The Figure 3 circuit uses
a center-tapped transformer with two rectifier diodes
while the Figure 4 circuit uses a simple transformer
and four rectifier diodes.
Figure 3 : Full Wave Rectified Output From the
Transformer/rectifier Combination is filtered by C1.
D1
5-7644
Figure 4 : This Circuit Performs Identically to that
Shown in Figure 3.
Figure 1 : Basic Half Wave Rectifier Cjrcuit.
f\{\
5-7639
Figure 2 : Full Wave Rectifier Wich uses a Center-tapped Transformer.
Figure 5 shows the continuous voltage curve obtained by adding a filter capacitor to the Figure 1 circuit. The section b-c is a straight line. During this
time it is the filter capacitor that supplies the load
current. The slope of this line increases as the current increases, bringing point c lower. Consequently the diode conduction time (c-d) increases,
increasing ripple. With zero load current the DC output voltage is equal to the peak value of the rectified
AC voltage.
Figure 6 shows how to obtain positive and negative
outputs referred to a common ground. Useful design
data for this circuit is given in figures 7, 8 and 9. In
particular, the curves shown in Figure 7 are helpful
in determining the voltage ripple for a given load current and filter capacitor value. The value of the voltage ripple obtained is directly proportional to the
load cu rrent and inversely proportional to the filter
capacitor value.
AN253/1088
1/5
661
APPLICATION NOTE
Figure 5 : Output Waveforms from the Half-wave
Figure 8 : DC to Peak Ratio for Half Wave rectifiers.
Rectifier Filter.
0.05
0.5
Vo
(V)
3
80
-~r
Rl
70
10
50
30
40
d
VAC
b
30
•
a
\
\
..
, '
\
.'
100
20
,, ,
10
I
5-1641
0.1
10
toDD
100
Note: C :farads.Rl:Ohms
Figure 6 : Full-wave Split Supply Rectifier.
Figure 9 : DC to Peak Ratio for Full-wave Rectifiers.
G-S1S"
,Voe
v",
01
"JII
+Vo
RS
FULL~WAVE
Jr5i3lID~
VM
(-,.)
.0
g, V
80
~ V.......-
70
GND
60 ~
f--
I--
50
-VO
5-761,5
4~
-
R
o.
1
3
1
!
~ ;:/ .......-
-
~
2
--
3
,.-
5
100
30
0.1
Figure 7 : Ripple Voltage vs. Filter Capacitor Va-
100
Figure 10 : DC Characteristics of a 50 VA Non-re-
lue (full-wave Reciifier).
VR
(Vpp)
I III
l~o~IJ/
gulated Supply.
G 5185
v
G .. 572/1
Yo
I
~
/
/
/
34
8000pF
32
300
"- i'.
0.2
0.1
30
~~~~~::E
t--
215
662
I
RIP~
-- --"
"F
~ I-"
...... 1'-.
........
/
V
RECTIFIER
.. f-"'"
==
2.
0.05
0.03
+
220V
\
VOUT(DC)
r--. t-....
-t0.05
0.1
Q2
as
(V pp )
:Jlj~
36
/
YR
I
(v )
2000,uF
0.5
1000
O.li
0.8
1.2
1.6
Vo
-
APPLICATION NOTE
Table 1.
DC Output Voltage (Vo)
Mains Secondary
(220V)
Voltage
0.1A 10
1A
10
0 10
=
+ 20%
+ 15%
+ 10%
-10%
-15%
-20%
28.8V
27.6V
26.4V
24V
21.6V
20.4V
19.2V
43.2V
41.4V
39.6V
36.2V
32.4V
30.6V
28.8V
=
42V
40.3V
38.5V
35V
31.5V
29.8V
28V
=
37.5V
35.8V
34.2V
31V
27.8V
26V
24.3V
The performance of a supply commonly used in consumer applications - in audio amplifiers, for example
- is described in figure 10 and table 1.
When a low ripple voltage is required an LC filter
network may be used. The effect on the output voltage of this addition is shown in figure 11. As figure
11 shows, the residual ripple can be reduced by 40
dB. But often the inductor is costly and bulky.
Often the degree of stability provided by the circuits
described above is insufficient and a stabilizer circuit is needed. Figure 12 shows the simplest solution and is satisfactory for loads of up to about SOmA.
This circuit is often used as a reference voltage to
apply to the base of a transistor of to the input of an
op amp to obtain higher output current.
The simplest example of a series regulator is shown
in Figure 13. In this circuit the transistor is connected
as a voltage follower and the output voltage is about
600 - 700mV lower than the zener voltage. The resistor R must be dimensioned so that the zener is
correctly biased and that sufficient base current is
supplied to the base of 01.
For high load currents the base current of 01 is no
longer negligible. To avoid that the current in the
zener drops to the point where effective regulation
is not possible a darlington may be used in place of
the transistor.
When better performance is required the op amp circuit shown in Figure 14 is recommended. In this circuit the output voltage is equal to the reference voltage
applied to the input of the op amp. With a suitable output buffer higher currents can be obtained.
The output voltage of the Figure 14 circuit can be
varied by adding a variable divider in parallel with
the zener diode and with its wiper connected to the
op amp's input.
The design of stabilized supplies has been simplified dramatically by the introduction of voltage regulator ICs such as the L78xx and L79xx three-terminal series reg ulators which provide a
very stable output and include current limiter and
thermal protection functions. Figures 16, 17 and 18
show how these circuits are used. Refer to the datasheets for more information.
Figure 11: Ripple Reduction Produced by a Single Section Inductance-capacitance
Filter.
G_5782
(dB )
1\
\.
.~r
:::r:
"\.
20
:1
L
\.
I.
I
f =60Hz
\.
\.
\.
30
I
I
\
f=120Hz
I\.
I
\.
\.
40
10
30
300
100
1000
L(H)· C()JF)
Figure 12 : Basic Zener Regulator Circuit.
Vi -Vo
=R
(IL+S)mA
Vi
[
---
+----'"'0
~ r'
Vo=12V
IL
• Z12
oc-'--------+----o GND
_ _
5·'646
Figure 13 :The Series Pass Zener-based Regulator Circuit can Supply Load Currents
up to about 100mA.
1.2Kfl
U1
Vi =15V-22V
+----~--o Vo=11.4V
C1
10116V
o--~--+-~----oGND
3/5
663
APPLICATION NOTE
Figure 14:The Op-amp-based Regulator can Supply 1 OOmA with Excellent Regulation.
RZ
Fig u re 15 : Zener Regulator Circuit Modified for Low-noise Output.
r---------------~~--------~).18V
+ 11.4V
5 -7652
Figure 16 :A Three Terminal 1A Positive Regulator Circuit is very Simple and Performs very Well.
4)( lN4002
Cl
2200/Z5V
4/5
664
C2
10116V
APPLICATION NOTE
Figure 17 :A Three Terminal1A Negative Voltage Regulator.
4xlN4002
1----_--0 Vo
C2
5-7650
Figure 18 : Complete ± 12V -1 A Split Supply Regulator Circuit.
T1
.=)',-T_+--+_0_4_4_X1_N.,.,1.OO2
01
'12V
05
1N4001
C1
GNO
C2
2200ll'SV
10116V
06
1N4001
-12V
S _7651
5/5
665
APPLICATION NOTE
VERY LOW DROP REGULATORS
ENHANCE SUPPLY PERFORMANCE
e'
By Paolo ANTONIAZZI and Arturo WOLFSGRUBER
Standard three-terminal voltage regulator ICs use
an NPN transistor as the series pass element, so
the input-output voltage drop is 1.5V-2V. Low dropout regulators using lateral PNP pass transistors
have been available for several years, but a lateral
PNP transistor has low gain, so the base current is
necessarily high, and a low fr, so the settling time is
poor. Moreover, for stability a large output capacitor
is needed.
Applying a new bipolar technology (see APPENDIX: Technology Is The Key) SGS-THOMSON has
developed two 5V low drop voltage regulators that
use a new vertical PNP transistor structure to obtain
low dropout and low quiescent current.
Type L4940 delivers up to 1.5A and offers an inputoutput voltage drop of 700mV at the fu111.5A output
current. A 1A version, type L4941 , has an input-output drop of 450mV at 1A (100mV at O.1A). Both
types have a quiescent current of 15mA at 1A (4mA
with no load). Consequently these devices dissipates less power, improving the efficiency of any
supply system (figure 1).
Figure 1 : A voltage regulator using vertical isolated PNR transistor is more efficient than regulators with
NPN pass transistors because the drop out is lower. And it is more efficient than a regulator
having a lateral PNP pass transistor because the quiescent current is lower.
G-6356
(~)
100
oil
t = ?; 25°(
10 = 500 mA
"'10·'.~
6.4V
-15·'.
Yin tl~.
for L 41
Vo = 5V
Vripple = 200V
90
BO
...
70
.. -15°'•
60
50
5
AN290110188
6
-15·'.
B.2V
Yin typo
for L 7805
+ 10·'•
•
6.55V
VintyP.
7
8
9
Vin(V)
1/9
667
APPLICATION NOTE
Compared to other "low drop" regulator the L4940
and L4941 have other advantages: regulation performance is guaranteed right down to the minimum
input voltage and the device is stable even without
an output capacitor. Additionally, a special circuit
limits' the quiescent current for input voltages from
3V to 5V, typically high for low drop regulators because of the saturation of the series regulator.
The two application areas which benefit the most
from second generation low drop regulators like the
L4940 and L4941 are post regulation and battery
supplies. However, the device brings cost savings
in any three"terminal regulator application.
LOW DISSIPATION REDUCES SIZE,
WEIGHT & COST
In simple series regulator applications the low dissipation of the L4940/1 reduces the size and weight
of the mains transformer, heatsink and printed circuit board. A comparison between equivalent 5V/1 A
circuits using the L4941 and a standard L7805 regulator (figure 2) shows that the L4941 solution is not
only more compact and lighter, it also costs less
since the difference in costs between an L4941 and
an L7805 is less than the cost saving.
Figure 2: In simple series regulator applications theL4941 can replace standard three-terminal regulators like the L 7805, reducing size, weight and cost. Heat dissipation is reduced, too.
j
1 N4001
~__~"""'_---------4
:t15%
::
II
L-_ _ _......- {
COMPARISON BETWEEN L7805 AND L4941
L4941
Component
L7805
Value
Cost'
Value
Transformer
220V/7,5V
9.4VA
$4.8
220V/8.6V
11VA
Cost'
$5.4
Diodes
2x1N4001
$0.1
2x1N4001
$0.1
Capacitors
4.7flF10V
10flF
$0.5
$0.1
4.7flF 16V
100n
$0.75
$0.08
Heatsink
20'C/W
$0.2
10'C/W
$0,3
PC Area
20cITf
$0.27
26cm"
$0.35
$5.97
$6.98
The L4941 solution, excluding the cost of the IC, is thus $1 cheaper. Moreover it is lighter, more compact
and dissipates 1.6W less.
* guide price for 1000 pieces.
2/9
668
APPLICATION NOTE
These low drop regulators also bring important
benefits in supplies using post regulation, the technique where one or more linear regulators follow another regulator (often switching), to improve
precision, reduce ripple and improve transient response. Though lightweight and cheap, an offline
switching regulator suffers from poor load and line
regulation and needs additional chokes and capacitors to reduce ripple.
Using standard reg ulators the efficiency of post
regulation systems is low because the intermediate
voltage must be high enough to allow for the post
regulator's voltage drop. Moreover, a lateral PNP
low drop regulator has a poor transient response so
it cannot reject switching ripple effectively.
If L4940s or L4941 s are used for post regulation the
intermediate voltage need only be 1V above the final
output voltage and 40dB SVR can be obtained at
30kHz. Consequently less power is dissipated both
in the post regulators and in the pre-regulator, making post regulation much more attractive -- designers can now have the precision, low ripple and
fast response without sacrificing efficiency.
Figure 3 shows a typical post-regulation power supply using a switching regulator, based on the L4960,
followed by L4941 low drop regulators.
Figure 3 : Low drop regulators like the L4941 improve the efficiency of post regulation supplies because
less power is dissipated and because the intermediate voltage can be lower. In this typical supply design an L4960 offline switching regulator is followed by L4941 post regulators, giving an
high overall efficiency.
1.2K.n.
1--..--o5V-1.5A
5-10325/1
3/9
669
APPLICATION NOTE
IMPROVING BATTERY SUPPLIES
The second application area where the L4940 and
L4941 are particularly useful is in battery-powered
equipment. Because of their lower dropout these
devices need fewer battery cells -- five, compared
to the six needed for an NPN regulator. In addition,
with five NiCd cells the efficiency is 77-96% and the
cells can be completely discharged.
The low quiescent current of the L4940 and L4941
reduces power consumption, prolonging battery life.
Moreover, since they will continue to provide a
stable 5V output with input voltages as low as 5.45V
they also extend. the effective battery life by allowing continued operation when the battery would previously have been discarded (figure 4).
Figure 4: The vertical PNP pass transistor permits a minimum dropout without the penalty of higher quiescent current, giving a 30-50% longer battery life in equipment drawing a constant current two
hours a day.
Vin
r-______.-______- r______~--------_r------_.------~r_~G~-~63~5~7--
(V)
6 CARBON - ZINC CELLS
AT 21·C WITH DISCONTINUOS USE
10
9
8
7
6
5
REGULATING
LIMIT OF L4941 - -
20
4/9
670
40
60
so
100
(h)DISCARCE TIME
APPLICATION NOTE
Figure 5 shows how an L4941 solution compares with five alternative 5V battery supplies.
Figure 5: The L4941 is also useful in battery-powered equipment, prolonging battery life by reducing current drain and supplying a regulated 5V output until the battery voltage has fallen to 5.45V. Here
the L4941 solution is compared with five alternatives.
R
..
>5
CELLS..:z:..
1. ZENER REGULATOR -- High current
consumption when battery fully charged and
high losses in Rser.
2. NPN SERIES REGULATOR -- Needs at least
7Znn/C, 6NiCd or 4Pd cells ..
3. DC-DC CONVERTERS -- Complicated and
costly. Generates EMi.and average efficiency
<= 75%.
5 to 6
CELLS
..:c..
4. DISCRETE LOW DROP REGULATOR -- Bulky and perforrns poorly in comparison with integrated solutions.
5/9
671
APPLICATION NOTE
Figure 5 (continued).
LM29XX
5 to 6
>47uF
CELLS
L4941....-.......-O
5 to 6
10uF
CELLS
HIGHER CURRENT
To obtain more than 1.5A output current a discrete
PN P transistor can be added to the L4940 as shown
in figure 6. In this circuit Q2 is a current limiter to pro-
5. LATERAL PNP LOW DROP REGULATORS -High quiescent current, limited output current
and stability problems.
6. L494x VERTICAL PNP LOW DROP REGULATORS -- Need only 6Zn/C cells or 5NiCd celis
(which are completely discharged). Quiescent
current is low and average efficiency 80%.
tect the external pass transistor when the output is
short circuited. An on-chip protection circuit prevents damage to the L4940.
When the load current does not vary greatly higher
Figure 6: An external PNP transistor can be added to the L4941 to obtain higher output current. Q2 is a
current limiter to protect the external transistor.
0-100mohm
IN
S.5V
1
6/9
672
OUT
t
MIN
G1
5V
G2
1A
100uF
APPLICATION NOTE
output current can also be obtained by using a shunt resistor as shown in figure 7.
Figure 7: If the load current does not vary much a simple way to obtain higher current is to add a shunt
resistor.
i.50hlll - 2W
Vin
6.2V
ti5~
L4941
5V - 1.3A
tl01
.L
Another way to obtain higher current is simply to
connect several devices in parallel as shown in
figure 8. This solution also increases the overall re-
liability of the system and is useful also when reliability is of prime importance.
Figure 8: Multiple L4941 s can be paralleled to increase both output current and reliability.
IN
OUT
7/9
673
APPLICATION NOTE
Finally, higher current can be obtained with two.devices in parallel connected to parallel sources (figure
9). This circuit provides an uninierruptable 1.2N5V
output by paralleling the normal line input with a
backup battery, which is charged through Rlim when
the AC input is present.
Figure 9: Connecting two L4941s in parallel with an AC input and a battery yields an efficient 1.2N5V
uninterrutable supply.
7.2U
5U-l.2A
AC
LINE
CELLS
5 Ah
NBBL 4941 - 82
USING THE L4941 AS A MODULATOR
basic circuit for an amplifier or generator driving resistive loads. The average output voltage can be
varied by adjusting the divider on the non-inverting
input of the op amp.
Apart from .power supply applications, the L4941
can be used as a modulator (figure 10). The modulator part of this circuit is also useful in the lab as a
supply for SVR measurements or generally as a
Figure 10 :The L4941 can be used as a modulator as illustrated in this circuit.
USUTA
MOO. RM
RUDIO
0---1
INPUT
lUpp Max.~
•
4.7K
18K
nBS
8/9
674
~ SGS·ntOMSON
"'''11
L'lilDi:liI@~~!reii'iii1@[lI)U©~
APPLICATION NOTE
APPENDIX: TECHNOLOGY IS THE KEY
In parallel with the emergence of mixed bipoSON MICROELECTRONICS Multipower-HDS 2 p2
lar/DMOS processes, pure bipolar technology has
(HDS 2 p2 = High Density Super Signal/Power Promade significant advances, too. One of the most imcess) used to design the l4940 & l4941 low drop
portant of these advances? the development of a
regulators, a 20V "Multipower" process which offers
NPN & ICV PNP power transistors, small signal
new power PNP transistor structure -- the isolated
collector vertical PNP (ICV PNP) -- which is similar
NPN & PNP transistors, III logic, ECl logic and a
in performance to NPN power transistors.
new low leakage diode structure (see fig. 11).
The ICV PNP is a key element in the SGS-THOMFigure 11 : Multipower bipolar process with new ICV-PNP (isolated collector vertical PNP), similar in performance to NPN power transistors.
Bee
BEe
ilL
NPN
C E BC
lev
PNP
s-
This process is characterized by an exceptionally
high current density -- 6A1mm 2 for NPN transistors;
2A/mm 2 for PNP transistors (at VSAT =1V, HFE =10)
-- and very high density in the signal processing section.
Thanks to the lev PNP power transistor structure,
designers can choose any output configuration -low side, high side, half bridge, bridge. In addition,
the low voltage drop of the ICV PNP is very useful
in applications where the dropout voltage is critical in voltage regulators and automotive solenoid drivers, for example.
Another new structure offered by Multipower-HDS 2
p2, the low leakage Diode (llD) is very useful in
power ICs driving inductive loads. With a parasitic
PNP gain about four orders of magnitude lower than
R
K R
LLD
9427
conventional diodes, the LLDs reduce dissipation in
the chip -- always an important consideration in
power IC design.
Multipower-HDS 2 p2 can be applied in simple products where an ICV PNP output stage is needed
such as the L4941. Moreover, because it allows the
integration of very complex control circuits it is also
used for power ICs which integrate a complete
power subsystem such as the L6217, a single chip
microstepping drive for stepper motors.
A similar process rated at 60V -- Multipower-S 2 p2
-- has also been developed. While Multipower-HDS2
p2 is aimed at 10w'voltatJe, high complexity applications, Multipower-S 2 P is intended for higher voltage applications with medium complexity control
circuits.
9/9
675
APPLICATION NOTE
A DESIGNER'S GUIDE TO THE L200 VOLTAGE REGULATOR
Delivering 2 A at a voltage variable from 2.85 V to 36 V, the L200 voltage regulator is a versatile device that
simplifies the design of linear supplies. This design guide describes the operation of the device and its applications.
The introduction of integrated regulator circuits has
greatly simplified the work involved in designing
supplies. Regulation and protection circuits required
for the supply, previously realized using discrete
components, are now integrated in a single chip.
This had led to significant cost and space saving as
well as increased reliability. Today the designer has
a wide range of fixed and adjustable, positive and
negative series regulators to choose from as well as
an increasing number of switching regulators.
The L200 is a positive variable voltage regulator
which includes a current limiter and supplies up to
2 A at 2.85 to 36 V.
The output voltage is fixed with two resistors or, if a
continuously variable output voltage is required,
with one fixed and one variable resistor.
The maximum output current is fixed with a low
value resistor. The device has all the characteristics
common to normal fixed regulators and these are
described in the datasheet. The L200 is particularly
suitable for applications requiring output voltage
variation or when a voltage not provided by the standard regulators is required or when a special limit
must be placed on the output current.
The L200 is available in two packages:
Pentawatt - Offers easy assembly and good reliability. The guaranteed thermal resistance (Rthj-case)
is 3 'C/W (typically 2 'C/W) while if the device is used
without heatsink we can consider a guaranteed
junction-ambient thermal resistance of 50 'C/W.
TO-3 - For professional and military use or where
partly compensated by the lower contact resistance
with the heatsink, especially when an electrical insulator is used.
CIRCUIT OPERATION
As can be seen from the block diagram (fig. 1) the
voltage regulation loop is almost identical to that of
fixed regulators. The only difference is that the negative feedback network is external, so it can be varied (fig. 3). The output is linked to the reference by :
R2
Vout = Vret (1 + - - )
R1
(1 )
Considering Vout as the output of an operational amplifier with gain equal to Gv = 1 + R2/R1 and input
signal equal to Vret, variability of the output voltage
can be obtained by varying R1 or R2 (or both). It's
best to vary R1 because in this way the current in
resistors R1 and R2 remains constant (this current
is in fact given by Vret/R1).
Equation (1) can also be found in another way which
is more useful in order to understand the descriptions of the applications discussed.
Vout = R1
h + R2 i2
and since in practice h " i4 (i4 has a typical value of
10 !lA) we can say that
Vout + R1 i1 + R2 i1 with i, =
Vrel
R1
Therefore
R2
R1
good hermeticity is required.
R2
Vout = R1
The guaranteed ju nction-case thermal resistance is
4 'CIW, while the junction-ambient thermal resistance is 35 'C/W.
In other words R1 fixes the value of the current circulating in R2 so R2 is determined.
Vret + Vret
= Vret (1+ - )
The junction-case thermal resistance of this package, which is greater than that of the Pentawart, is
AN255/1288
1/20
677
APPLICATION NOTE
Figure 1 : Block Diagram.
OUTPUT
INPUT
VOLTAGE
L----~---------~~4REFERENCE
'--------<~--------_-----------03
5·3928
Figure 2 : Schematic Diagram.
2/20
678
~
. .. , /
SGS·1HOMSON
i!iU©I!ImI!.~Ii©OOIl©$
GROUND
APPLICATION NOTE
Figure 3.
RJ
r-----L-j-------+---+------~V~I
Vs o----------~
4
OVERLOAD PROTECTION
THERMAL PROTECTION
The device has an overload protection circuit which
limits the current available.
The junction temperature of the device may reach
destructive levels during a short circuit at the output
or due to an abnormal increase in the ambient temperature. To avoid having to use heatsinks which
are costly and bulky, a thermal protection circuit has
been introduced to limit the output current so that
the dissipated power does not bring the junction
temperature above the values allowed. The operation of this circuit can be summarized as follows.
Referring to fig. 2, R24 operates as a current sensor. When at the terminals of R24 there is a voltage
drop sufficient to make 020 conduct, 019 begins to
draw current from the base of the power transistor
(darlington formed by 022 and 023) and the output
current is limited. The limit depends on the current
which 021 injects into the base of 020. This current
depends on the drop-out and the temperature which
explains the trend of the curves in fig. 4.
Figure 4.
la(mall)
tAl
.-~.
••. __
Vref- VSE17
R17+R16
(Vref = 2.75 V typ)
The base of 018 is therefore biased at :
. . ..
• __ .~.
In 017 there is a constant current equal to :
~~'~.~. :~"l
I-
~
~
_.
•
••
!
,-.
~ 20,.us
. ~
T- _'
-t -'o.Voo: 2"'.
I
~--t-~lJ=25·C'....,-___:___' • • ~- "duty-cyclp.::'-'o I
~
I
+--t-
...-----' '---'J,
0-
_.
•
Vref- VSE17
R16+R17
VSE18 =
t
•
•
•
••
•
·R16=350mV
Therefore at TJ = 25 ·C 018 is off (since 600 mV is
needed for it to start conducting). Since the VSE of
a silicon transistor decreases by about 2 mVrC,
018 starts conducting at the junction temperature:
Tj=
600;350
+25
=150·C
CURRENT LIMITATION
o
10
20
The innovative feature of this device is the possibility
of acting on the current regulation loop, i.e. of limiting the maximum current that can be supplied to
the desired value by using a simple resistor (R3 in
fig. 2). Obviously if R3 = 0 the maximum output cur-
3/20
679
APPLICATION NOTE
rent is also the maximum current that the device can
supply because of its internal limitation.
possible to obtain a wide range of fixed output voltages.
The current loop consists of a comparator circuit
with fixed threshold whose value is Vsc. This comparator intervenes when 10 . R3 = Vsc, hence
Figure 6.
10 =
5
~
(Vsc is the voltage between pin 5
R3
and 2 with typical value of 0.45 V).
Special attention has been given to the comparator
circuit in order to ensure that the device behaves as
a current generator with high output impedance.
TYPICAL APPLICATIONS
PROGRAMMABLE CURRENT REGULATOR
Fig. 5 shows the device used as current generator.
In this case the error amplifier is disabled by shortcircuiting pin 4 to ground.
Figure 5.
R
V5·2
The following formulas and tables can be used to
calculate some of the most common output voltages.
Having fixed a certain Vo, using the previous formula, the maximum value is :
10=-
R
5
Vo max = Vref max
(1 +
R2 max
R1 min
(1 +
R2 min
R1 max
)
and the
minimum value is :
Vo min = Vref min
The table below indicates resistor values for typical
output voltages:
5-Z4ZS/1
The output current 10 is fixed by means of R :
10 =
V5-2
R
The output voltage can reach a maximum value Vi
- Vdrop =' Vi 2 V (Vdrop depends on 10)'
PROGRAMMABLE \/,OLTAGEHEGULATOR
Fig.' 6 shows the device connected as a voltage
regulator and the maximum output current is the
maximum current that the device can supply. The
output voltage Vo is fixed using potentiometer R2.
The equation which gives the output voltage is as
follows:
Vo=
Vref
(1 +
R2)
R1
By substituting the potentiometer with a fixed resistor and choosing suitable values for R1 and R2, it is
4/2b
680
Vo ± 4 %
R1 ± 1 %
5V
1.5 kQ
1.2 kQ
12 V
1 kQ
3.3 kQ
15 V
750 Q
3.3 kQ
18 V
330 Q
l.8 kQ
24 V
510 Q
3.9 kQ
R2 ± 1 %
PROGRAMMABLE CURRENT AND VOLTAGE
REGULATOR
The typical configuration used by the device as a
voltage regulator with external current limitation is
shown in fig. 7. The fixed voltage of 2.77 V at the
terminals of R1 makes it pos?ible to force a constant
current across variable resistor R2. If R2 is varied,
the voltage at pin 2 is varied and so is the output
voltage.
APPLICATION NOTE
The output voltage is given by :
Vo = Vref •
(1 +
~),
R1
Figure 8.
with Vref = 2.77 V typ
and the maximum output current is given by :
V~2
10 max =
with VS-2 = 0.45 V typo
To maintain a sufficient current for good regulation
the value of R1 should be kept low. When there is
no load, the output current is Vref/R1. Suitable
values of R1 are between 500 Q and 1 .5 kO. If the
load is always present the maximum value for R1 is
limited by the current value (10 flA) at the input of
the error amplifier (pin 4).
Figure 7.
.I---] '0
R3
.------'-'---.,
'0
V5- 2
(max)= -
= V ref
R3
(
1+R
2)
Figure 9.
R1
L 200
I
0.23!
":;'"
3
R1 4
R2
82011
DIGITALLY SELECTED REGULATOR WITH INHIBIT
The output voltage of the device can be regulated
digitally as shown in fig. B. The. output voltage depends on the divider formed by R5 and a combination of R1, R2, R3 and P2. The device can be
switched off with a transistor.
When the inhibit transistor is saturated, pin 2 is
brought to ground potential and the output voltage
does not exceed 0.45 V.
REDUCING POWER DISSIPATION WITH DROPPING RESISTOR
If may sometimes be advisable to reduce the power
dissipated by the device. A simple and economic
method of doing this is to use a resistor connected
in series to the input as shown in fig. 9. The inputoutput differential voltage on the device is thus reduced.
R
5-5518/1
Where Vdrap is the minimum differential voltage between the input and the output of the device at current 10. Yin min is the minimum voltage. Va is the
output voltage and 10 the output current.
With constant load, resistor R can be connected between pins 1 and 2 of the IC instead of in series with
the input (fig. 10). In this way, part of the load current flows through the device and part through the
resistor. This configuration can be used when the
minimum current by the load is :
10min =
Vdrap
-R-
(instant by instant)
The formula for calculating R is as follows:
Vi min - (Vo + Vdrop)
10
5120
681
APPLICATION NOTE
LIGHT CONTROLLER
Figure 10.
Fig. 12 shows a circuit in which the output voltage
is controlled by the brightness of the surrounding environment. Regulation is by means of a photo resistor in parallel with R1. In this case; the output
vol-tage increases as the brightness increases. The
opposite effect, i.e. dimming the light as the ambient
light increases, can be obtained by connecting the
photoresistor in parallel with R2.
R
Vi C>--+------'-I
Figure 12.
5 ':151911
SOFT START
When a slow rise time of the output voltage is required, the configuration in fig. 11 can be used. The
rise time can be found using the following formula:
ton =
CVo R
0.45
At switch on capacitor C is discharged and it keeps
the voltage at pin 2 low; or rather, since a voltage
of more than 0.45 V cannot be generated between
pins 5 and 2, the Va follows the voltage at pin 2 at
less than 0.45 V.
Figure 11.
t
on
= C Va R
0.45
1 Kll
I
The circuit is shown in fig. 13. The primary supply is
shown taken straight from the car battery however
it is worth noting that in a car there is always the risk
of dump voltages up to 120 V and it is recommended
that some form of protection is included against this.
Capacitor C is charged by the constant current ie.
.
le=
Vse
-R-
Therefore the output reaches its nominal value after
the time ton:
Vo- Vse =
Ic • ton
-C-
Vo - 0.45
0.45
6/20
682
LIGHT DIMMER FOR CAR DISPLAY
Although digital displays in cars are often more aesthetically pleasing and frequently more easily read
they do have aproblem. Under varying ambient light
conditions they are either lost in the background or
alternatively appear so bright as to distract the
driver. With the system proposed here, this problem
is overcome by automatically adjusting the display
brightness during daylight conditions and by giving
the driver control over the brightness during dusk
and darkness conditions.
·R :=
CVoR
0.45
Under daylight conditions i.e. with sidelights off and
T1 not conducting the output of the device is determined by the values of R1 , R2 and the photoresistor (PTR). The output voltage is given by .
Vout
= Vrel
(1 +
R2
PTRl/R1
)
If the ambient light intensity is high, the resistance
of the photo resistor will be low and therefore Vout will
be high. As the light decreases, so Vout decreases
dimming the display to a suitable level.
APPLICATION NOTE
Figure 13.
BATT.
SIDELIGHT - SWITCH
In dusk conditions, when the sidelights are switched
on, T1 starts to conduct with its conduction set by
the potentiometer wiper at its uppermost positiolQ
the sidelights are at their brightest and current
through T1 would be a minimum. With the wiper at
its lowest position obviously the opposite conditions
apply.
Figure 14.
2
!
The current through T1 is felt at the summing node
A along with the currents through R2 and the parallel network R1, PTR. Since Vref is constant the current flowing through R1, PTR must also be constant.
Therefore any change in the current through T1
causes an equal and opposite change iri the current
through R2. Therefore as 1r1 increases, Vau! decreases i.e. as the brightness of the side-lights is increased or decreased so is the brightness of the
display.
The values of R2 and PTR should be selected to
give the desired minimum and maximum brightness
levels desired under both automatic and manual
conditions although the minimum brightness under
manual conditions can also be set by the maximum
current flowing through T1 and, in any case, this
should not exceed the maximum current through R2
under automatic operation.
.---......-:-_ _
R2
~
_ _ _ I TI
!>-SSll
Figure 15.
+
The circuit shown with a small modification can also
be used for dimmers other than in a car. Fig. 15
shows the modification needed. The zener diode
should have a VF;:: 2.5 V at 1= 10j.lA.
HIGHER INPUT OR OUTPUT VOLTAGES
Certain applications may require higher lriput or output voltages than the device can produce. The problem can be solved by bringing the regulator back
5-3997/1
7/20
683
APPLICATION NOTE
into the normal operating units with the help of external components.
Figure 17.
When there are high input voltages, the excess voltage must be absorbed with a transistor. Figs. 16 and
17 show the two circuits:
Figure 16.
SOY
The designer must take into account the dissipated
power and the SOA of the preregulation transistor.
For example, using the BDX53, the maximum input
voltage can reach 56 V (fig. 16). In these conditions
we have 20 Vof VCEon the transistor and with a load
current of 2 A the operation point remains inside the
SOA. The preregulation used in fig. 16 reduces the
ripple at the input of the device, making it possible
to obtain an output voltage with negligible ripple.
BDX53
Vi
j
If high output voltages are also required, a second
zener, Vz, is used to refer the ground pin of an Ie to
a potential other than zero; diode D1 provides output shortcircuit protection (fig. 18).
Figure 18.
Rsc
Vj(max) = 56V. Vz
L 200
1
j
Vi
4
r
01
~YZ~Rl_J ~.~
vllo
--1l
IO,..F
S-l9n'l
POSITIVE AND NEGATIVE VOLTAGE REGULATORS
The circuit in fig. 19 provides positive and negative
balanced, stabiliied voltages simultaneously. The
L200 regulator supplies the positive voltage while
the negative is obtained using an operational amplifier connected as follower with output current booster.
Tracking of the positive voltage is achieved by putting the non-inverting input to ground and using the
inverting input to measure the feedback voltage
coming from divider R1-R2.
8/20
684
The system is balanced when the inputs of the operational amplifier are at the same voltage, or, since
one input is at fixed ground potential, when the voltage of the intermediate point of the divider foes to 0
Volts. This is only possible if the negative voltage,
on command of the op-amp, goes to a value which
will make a current equal to .that in R1 flows in R2.
The ratio which expresses the negative output voltage is:
V-= V+'
R2
R1
(If R2 = R1,we'li get V- = V+)
APPLICATION NOTE
SincE) the maximum supply voltage of the op amp
used is ± 22 V, when pin 7 is connected to point B
output voltages up to about 18 V can be obtained.
If on the other hand pin 7 is connected to point A,
muGJ;! higher output voltages, up to about 30 V, be
obtli.lned since in this case the input voltage can rise
to 34 V.
Figure 19.
Fig. 20 shows a diagram is which the L165 power
op amp is used to produce the negative voltage. In
this case (as in fig. 19) the output voltage is limited
by the absolute maximum rating of the supply voltage of the L 165 which is ± 18 V. Therefore to get a
higher Vout we must use a zenerto keep the device
supply within the safety limits.
A : V;lm"i " ± 34 V
8 : Vi (max) :::; ± 22
v
If we have a transformer with two separate secondaries, the diagram of fig. 21 can be used to obtain
independent positive and negative voltages. The
two output diodes, D1 and D2, protect the devices
from shortcircuits between the positive and negative
outputs.
3 < Vo < 30
3 < Vo < 18
Figure 20.
L200
Vo .JIO(Vr 4 )V
lK.Il.
A : for ± 18 V ~ Vi ~ 32 V
Nole: Vz must be chosen in order
to verify 2 Vi - Vz = 36 V
B : for Vi ~ ± 18 V
IOK.Q.
lKll
O.1,AJF ..-_-j'=oK=.Q.:r-_ _- .
>=----*--------u- Vo
-Vio-----~-----J
9/20
685
APPLICATION NOTE
Figure 21.
COMPENSATION OF VOLTAGE DROP ALONG
THE WIRES
The diagram in fig. 22 is particularly suitable when
a load situated far from the output of the regulator
has to be supplied and when we want to avoid the
use of two sensing wires. In fact, it is possible to
compensate the voltage drop on the line caused by
the load current (see the two curves in fig. 23
and 24). RKtransforms the load current IL into a proportional voltage in series to the reference of the
L200. RK IL is then amplified by the factor
R2 + R1
R1
D
With the values of Rz, R2 and R1 known, we get:
R - R
R1
K - z R1 + R2
Rz, R1 and R2 are assumed to be constant.
If RK is higher than 10 n , the output voltage should
be calculated as follows:
~-lS(,()H
Va = Id RK+ V,et
R2 + R1
R1
Figure 22.
s
2
L200
R2
1
3
4
!
Id
Vi
I
10/20
686
RK
t
Vo
RI
5-5524/1
APPLICATION NOTE
Figure 23.
-
Figure 24.
----
-~-
-
~-
MOTOR SPEED CONTROL
Figure 25.
Fig. 25 shows how to use the device for the speed
control of permanent magnet motors. The desired
speed, proportional to the voltage at the terminal of
the motor, is obtained by means of Rl and R2.
VM = Vref
(1 +
R2
AT)
To obtain better compensation of the internal motor
resistance, which is essential for good regulation,
the following equation is used:
R3
~~
R2
RJ
• RM
5-1.124 11
This equation works with infinite R4. If R4 is finite,
the motor speed can be increased without altering
the ratio R2/Rl and R3. Since R4 has a constant
voltage (Vref) at its terminals, which does not vary
as R4 varies, this voltage acts on R2 as a constant
current source variable with R4. The voltage drop
on R2 thus increases, and the increase is felt by the
voltage at the terminals of the .motor. The voltage
increase at the motor terminals is :
Vref
R4+ R3
• R2
A circuit for a 30 W motor with RM = 4 n, R 1 = 1 kn,
R2 = 4.3 kn, R4 = 22 kQ and R3 = 0.82 n has been
realized.
POWER AMPLITUDE MODULATOR
In the configuration of fig. 26 the L200 is used to
send a signal onto a supply line. Since the iriput signal Vi is DC decoupled, the Vo is defined by :
Vo = Vref
(1 +
The amplified signal Vi whose value is :
Gv=-~
R3
is added to this component. By ignoring the current
entering pin 4, we must impose i1 = i2 + i3 (1) and
since the voltage between pin 4 and ground remains
fixed (Vref) as long as the device is not in saturation,
i1 = 0 and equation (1) becomes:
.12
.13 WI'th'13
= -Vi-
Vo=R2 i2=-
~
=-
R3
R3
(forXc «R3) Therefore
·R2
An application is.shown in fig. 27. If the DC level is
to be varied but not the AC gain, Rl should be replaced by a potentiometer.
R2)
Rl
11/20
687
APPLICATION NOTE
Figure 26.
Is
I
3
Vo·vo
2
L200
"V
4
RZ
l
liZ
R3
~
RI[
13
)!Ol
:~
......
IKn
!L551SI1
Figure 27.
39Kn
"-' v,
O-~~--~----~~----
HIGH CURRENT REGULATORS
To get a higher current than can be supplied by a
single device one or more external power transistors must be introduced. The problem is then to extend all the device's protection circuits (short-circuit
protection, limitation of Tj of external power devices
and overload protection) to the external transistors.
Constant current or foldback current limitation therefore becomes necessary.
When the regulator is expected to withstand a permanent shortcircuit, constant current limitation
becomes more and more difficult to guarantee as
the nominal Vo increases. This is because of the increase in VCE at the terminals of the transistor, which
leads to an increase in the dissipated power.. The
heatsink has to be calculated in the heaviest working conditions, and therefore in shortcircuit. This increases weight, volume and cost of the heatsinkand
increase of the ambient temperature (because of
high power dissipation). Besides heatsink, power
12120
688
__
transistors must be dimensioned for the short-circuit.
This type, of limitation is suited, for example, with
highly capacitive loads. Efficiency is increased if preregulation is used on the input voltage to maintain a
constant drop-out on the power element for all VOU!,
even in shortcircuit. Foldback limitation, on the other
hand, allows lighter shortcircuitoperating conditions
than the previous case. The type of load is important.
If the load is highly capacitive, it is not possible to
have a high ratio between Imax and Ise because at
switch-on, with load inserted, the output may not
reach its nominal value.
Other protection against input shortcircuit, mains
failure, overvoltages and output reverse bias can be
realized using two diodes, D1 and D2, inserted as
indicated in fig. 28.
APPLICATION NOTE
Figure 28.
Figure 29.
01
, - - - - - ~;(4-----
20V
Vi
.v,
0---.-4-=>+-4
2.50
IOpF
Dl
B20n
S-15J9/l
!J-'!IS17
USE OF A PNP TRANSISTOR
The latter is given by : IREG = Is +
Fig. 29 shows the diagram of a high current supply
using the current limitation of the L200. The output
current is calculated using the following formula:
I
=
o
VSC
RSC
'"
-
0.45 V
0.1 n
= 4.5 A
Constant current limitation is used ; so, in output
shortcircuit conditions, the transistor dissipates a
power equal to :
Po
= Vi • 10 = Vi •
Vsc
Rsc
The operating point of the transistor should be kept
well within the SOA ; with Rsc = 0.1 n, Vi must not
exceed 20 V. Part of the 10 crosses the transistor
and part crosses the regulator.
VSE
-R-
where Is is the base current of the transistor
(-100 mA at Ic = 4 A) and VSE is the base-emitter
voltage (- 1 V at Ic = 4 A) ; with R = 2.5 n, IREG :=
500 mA.
USE OF AN NPN POWER TRANSISTOR
Fig. 30 shows the same application as described in
figure 29, using an NPN power transistor instead of
a PNP. In this case an external signal transistor must
be used to limit the current. Therefore:
10 =
VSEQ1
Rsc
As regards the output shortcircuit, see par. 1.5.
Figure 30.
Rsc
lOll.
L 200
5-290'11
13/20
689
APPLICATION NOTE
12 V 4 A POWER SUPPLY
The diagram in fig. 31 shows a supply using the
L200 and t.he B0705. The 1 kQ potentiometer, PT1 ,
together with the 3.3 k resistor are used for fine regulation of the output voltage.
C~rrent limitation is of the type shown in fig. 32.
Tnmmer PT2 acts on strech AB of characteristic.
With the values indicated (PT2 = 1 kQ, PT3 =470 Q,
R = 3 kQ), currents from 3 to 4 A can be limited. The
field of variation can be increased by increasing the
value of Rsc or by connecting one terminal of PT to
the base of the power transistor, which, however,
provides less stable limitation. If section AB is
moved, section BC will also be moved.
The slope of BC can be varied using PT3. The voltage lev~1 at point B is fixed by the voltage of the
zener diode. The capacitor in parallel to the zener
ensures correct switch-on with full load. The B0705
should always be used well within its safe operating
area. If this is not possible two or more B0705s
should be used, connected in parallel (fig. 33).
Further protection for the' external power transistor
can be provided as shown in fig. 34. The PTC resistor, whose temperature intervention point must prevent.the Tj of the power transistor from reaching its
maximum value, should be fixed to the dissipator
near the power transistor. Oimensioning of RA and
Rs depends on the PTC used.
Figure 31.
sw
17V~Yj ~25V
0.22
f.lF
VOUT
12V
3
IKll
0.33
J.JF
lKll
L -_ _~_ _~~r-
____________
~~
__
~-SENSE
\
\
I
I
I
o-~~~
__-4~__~________________+-__~________-J~L-~_O/P
I
IN 1,1 1,8
2.7Kll
S-SS28
14/20
690
APPLICATION NOTE
Figure 33.
Figure 32.
Vo
(V)
A
L200
s- 5460
5-5529
VOLTAGE REGULATOR FROM 0 V TO 16 V 4.5A
Figure 34.
Fig. 35 shows an application for a high current supply with output voltage adjustable from 0 V to 16 V,
realized with two L200 regulators and an external
power transistor. With the values indicated, the current can be regulated from 2 A to 4.5 A by potentiometer PT2. PT1, on the other hand, is used for
constant current or foldback current limitation. The
integrated circuit IC2, which does not require a heatsink and has excellent temperature stability, is used
to obtain the 0 V output. It is connected so as to
lower pin 3 of IC1 until pin 4 reaches 0 V. 01 and
02 ensure correct operation of the supply at switchon and switch-off.
~-5!i1JO
15120
691
APPLICATION NOTE
Figure 35.
2A
.VOU !
ZA
!I-!l5J111
POWER SUPPLY WrfH Vo =2.8 TO 18 V, 10 = 0
T02.5A
The diagram in fig. 36 shows a supply with output
voltage variable from 2.8 V to 18 V and constant current limitation from 0 A to 2.5 A. The output current
can be regulated over a wide range by means of the
op. amp. and signal transistor TR2. The op. amp.
and the transistor are connected in the vOltage-current converter configuration. The voltage is taken at
the terminals of R3 and converted into current by
PT2.
10 is fixed as follows :
R410
PT2
= 11 (*)
(**) Isc=
Vsc
R2
When 11 = Isc, the regulator starts to operate as a
16120
692
current generator. By making (*) equal to (**) we
get:
R410
vsc
VSC
-- =
PT2
T~erefore
-
R2
10 = - - R2·R4
• PT2
Diodes D1 and D2 keep transistor TR2 in linear condition in the case of small output currents. If it is not
necessary to limit the current to zero, one of the
diodes can be eliminated: the second diode could
also be eliminated if TR1 were a darlington instead
of a transistor.
The op. amp. must have inputs compatible with
ground in order to guarantee current limitation even
in shortcircuit. With a negative voltage available,
even of only &a few volts, current limitation is simplified.
APPLICATION NOTE
Figure 36.
...
'0
Bmo5
R4
'·0
0.111
TRI¥ ,!U..,
III
DZ
j
ZXINIoOOI
2~ ~
~DI
.!!!..
~n
,I
I
.=25V
:ii~ :
L200
il
~v.f!!-
12
•
lUI
I
nF
[q
:Ql]jJF
"'!3
jJF
S
TR2
"
114 LS404
II~I
RS
Tn
4-7Kll..L
up·
~
LAYOUT CONSIDERATIONS
The performance of a regulator depends to a great
extent on the case with which the printed circuit is
produced. There must be no impulsive currents (like
the one in the electrolytic filter capacitor at the input
of the regulator) between the ground pin of the device (pin 3) and the negative output terminal because these would increase the output ripple. Care
must also be taken when i_nserting the resistor connected betWeen pin 4 and pin 3 of the device.
The track connecting pin 3 to a terminal of this resistor should be very short and must not be crossed
;..
by the load current (which, since it is generally variable, would give rise to a voltage drop on this stretch
of track, altering the value of Vref and therefore of
Va.
When the load is not in the immediate proximity of
the regulator output "+ sense" and" - sense" terminals should be used (see fig. 37). By connecting the
"+ sense" and "- sense" terminals directly at the
charge terminals the voltage drop on the connection
cable between supply and load are compensated.
Fig. 37 shows how to connect supply and load using
the sensing clamps terminals.
Figure 37.
A
5
B
+
1
3
Cl
CZ
Vi
_I
2200
j
t'F
5- 5 382
L'I.
•• SGS-THOMSON
IliIDlCli@lIII.IiC1J'llItmJlJIC1ll
o
17/20
693
APPLICATION NOTE
Figure 38.
CAD
HEATSINK DIMENSIONING
Figure 40.
The heatsink dissipates the heat produced by the
device to prevent the internal temperature from
reaching value which could be dangerous for device
operation and reliability:
Integrated circuits in plastic package must never exceed 150 'C even in the worst conditions. This limit
has been set because the encapsulating resin has
problems of vitrification:if~lJbjected to temperatures
of more than 150 'C for longperiods or of more,than
170 'C for short periods (24 h). In any case the temperature accelerates the ageing process and therefore influences the device life; an increase of 10 'C
can halve the device life. A well designed heatsink
should keep the junction temperature between
90 'C and 110 ·C. Fig. 39 shows the structure .of a
power device. As demonstrated in thermodynamics,
a thermal circuit can be considered to be an electrical circuit where R1, 2 represent the thermal resistance of the single elements (expressed in C/W) ;
B
R1
R2
DIE
DIE ATTACH
R3
R4
~- 5;'j\2
C1, 2 the thermal capacitance (expressed in 'C/W)
I the dissipated power
V the temperature difference with respect to
the reference (ground)
This circu,t can be simplified as follows:
Figure 41.
Figure 39.
5-5536
PLASTI C PACKAGE
DIE
DIE ATTACH
/
5-5511
18120
694
Where Ce is the thermal capacitance of the die plus
that of the tab.
Ch
Rjc
Rh
is the thermal capacitance of the heatsink
is the junction case thermal resistance
is the heatsink thermal resistance
But since the aim of this section is not that of studing the transistors, the circuit can be further reduced.
APPLICATION NOTE
Figure 42.
Figure 43.
If we now consider the ground potential as ambient
temperature, we have:
Ti = Ta + (Rjc + Rh) Po
(1)
Note 2 : In applications where one or more external
transistors are used together with the L200, the
dissipated power must be calculated for each component. The various junction temperatures can be
calculated by solving the following circuit:
Rth= Ti-Ta-RiCoPd
Pd
(1a)
Tc=Ta+RhoPd
(2)
Figure 44.
For example, consider an application of the L200
with the following characteristics :
Vintyp = 20 V
Vo = 14 V
ooooltioo.
10 typ = 1 A
Ta=40'C
] \yp'''''
Vin max = 22 V -_
Vo = 14 V
10 max = 1.2 A
overload conditions
Ta= 60'C
Pdtyp = (Vin - Vol 010 = (2014) 01 = 6 W
Pd max = (2214)01.2 = 9.6 W
Imposing Tj = 90 'c of (1 a) we get (from L200 characteristics we get Rjc = 3 'C/W).
Rh =
90 - 4~ - 306
= 5.3 'CfW
Using the value thus obtained in (1), we get that the
junction temperature during the overload goes to the
following value:
Tj = 60 + (3 + 5.3).9.6 = 140°C
If the overload occurs only rarely and for short periops, dimensioning can be considered to be correct.
Obviously during the shortcircuit, the dissipated
power reaches must higher values (about 40 W for
the case considered) but in this case the thermal
protection intervenes to maintain the temperature
below the maximum values allowed.
Note1: If insulating materials are used between device and heatsink, the thermal contact resistance
must be taken into account (0.5 to 1 'C/W, depending on the type of insulant used) and the circuit in
fig. 43 becomes :
This applies if the various diSSipating elements are
fairly near to one another with respect to the heatsink dimensions, otherwise the heatsink can no
longer be considered as a concentrated constant
and the calculation becomes difficult.
This concept is better explained by the graph in
fig. 45 which shows the case (and therefore junction) temperature variation as a function of the distance between two dissipating elements with the
same type of dissipator and the same dissipated
power. The graph in fig. 45 refers to the specific case
of two elements dissipating the same power, fixed
on a rectangular q.luminium plate with a ratio of 3 between the two sides. The temperature jump will depend on the dissipated power and one the device
geometry but we want to show that there exists an
optimal position between the two devices:
d=
+
0 side of the plate
Fig. 46 shows the trend of the temperature as a function ofthe distance between two dissipating elements
whose dissipated power is fairly different (ratio 1 to 4).
Gi
SCiS·nlOMSON
~I ~DICIlOO!Jrn!l.Im'I!@OODI:II
19120
695
APPLICATION NOTE
This graph may be useful in applications with the L:200
+ extemal transistor (in which the transistor generally
dissipates more than the L200) where the temperature of the L200 has to be kept as low as possible and
especially where the thermal protection of the L200 is
to be used to limit the transistor temperature in the
case of an overload or abnormal increase in the ambient temperature. In other words the distance between the two elements can be selected so that the
power transistor reaches the Tj max (200 "C for a TO3 transistor) when the L200 reaches the thermal protection intervention temperature.
Figure 45.
Tc (Oe)
70
5
55
50
-10
-7
-5
:4
-3 -2 -1
'
..
d (em)
5
7
6
8
9
10
."
5-55'6
Figure 46.
--T
150
---
140
T~
130
120
,A
I
;60
-10
-5:
-.
B
--
I . . . . . - - - .-JI
....... ,
.,
..
'
,5
d (em)
.'
A : Position of the device with high power dissipation (10 W)
B : Position of the device with low power dissipation (2.5 W)
20/20
696
10
5 - 5517
APPLICATION NOTE
DUAL REGULATORS SIMPLIFY
MICRO SYSTEM SUPPLY DESIGN
Combining two 5 V regulators and a reset circuit on a single chip, special purpose regulator chips simplify
the design of power supplies for microprocessor systems incorporating battery backup RAMs or shadowtype NV RAMs,
Power supplies for microprocessor systems are often complicated by the need to take care of the special requirements of non-volatile read/write memory. Where battery backup CMOS RAMs are used,
for example, it is important to ensure that the RAMs
are disabled when the primary supply is removed.
And when shadow-type NV memory is included the
backup transfer must be initiated and completed
when the supply is interrupted. Designed specificalIy for such applications, the SGS-THOMSON Microelectronics L4901 , and L4902 dual voltage regulators combine two 5 V regulators plus a reset circuit
on a single chip, simplifying the designer's task.
sients. Also included on the chip is a reset circuit
with externally programmable timing which depends
on the input voltage and the output of the V1 regulator.
Functionally, the two devices are identical except
that the L4901 has separate inputs to the two regulators and the L4902 has a common input plus a disable input which controls the V2 output (fig. 1).
Generally the V1 regulator is used to supply circuits
which must be powered continuously - volatile memory, a time-of-day clock and so on - while the V2
output supplies other 5 V circuits which may be powe red down when the equipment is inactive.
Assembled in the SGS-THOMSON Heptawatt [TM]
7-lead package, the L4901 and L4902 contain separate voltage regulators rated at 5 V/300 mA (the
"V1" output) and 5 V/400 mA (the "V2" output).
Both the V1 and V2 regulators have an output voltage precision of ± 2 % and include protection
against output short circuits and 60 V input tran-
The V1 output features a very low leakage current
at the output - less than 1 !lA - to allow the use a
backup battery. The V1 regulator also features a low
quiescent current at the input (0.6 mA typical) to minimize battery drain in applications where the V1 regulator is permanently connected to a battery supply.
Figure 1a : TWO 5V OUTPUTS - The L4901 Dual Regulator Provides 300 mA and 400 mA 5 V Outputs and
Includes a Microprocessor Reset Function. This Device is Ideal for Microprocessor Systems with
Battery Backup or Shadow RAM.
111 !N
"OnF
±
III IN
AN256/0189
1/7
697
APPLICATION NOTE
Figure 1b : DISABLE INPUT - The L4902 is Similar to the L4901 but also Features a Disable Input for the
V2 Regulator.
l4902
IN
7
Vl0UT
I
DISABLE
5-
'3)()7
Figure 2: WAVEFORMS - An Important Feature of the L4901 Series Regulators is that the Reset Circuit
Monitors the Input Voltage.
I
I
I
I
I
I
I
~--+--I
v02
IRD
SWITCH
ON
2/7
698
VOl
OVERLOAD
V02
VIN
OVERLOAD OVERLOAD
THERMAL
SHUT
SWITCH
DOWN
OFF
APPLICATION NOTE
VERSATILE DEVICES
The L4901 and L4902 are versatile devices which
simplify the supply circuitry of many systems and
can be used in a number of different ways.
One possibility, outlined in figure 3, is to connect the
V1 regulator permanently to a battery to supply a
CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. In this example the
V2 output supplies non-essential 5 V circuits. A typical use of this scheme is in trip computers or car
radios with programmable tuning.
An alternative, shown in figure 4, is to use the L4901
with a backup battery on the V1 output to maintain
a CMOS clock and a standby-type NMOS microcomputer chip. In this case the main on/off switch
disconnects both the V1 and V2 regulators from the
battery.
Figure 5 illustrates how the L4902's disable input
may be used in a CMOS microcomputer application.
In this example the V2 output, supplying non-essential circuits, is turned off under control of the micro-
processor circuit. Configurations of this type are
used in products where the "OFF" switch is part of
a keypad scanned by a micro which operates continuously, even in the "OFF" state.
The L4901 is also ideal for microcomputer systems
using battery backup CMOS static RAMs. As shows
in figure 6 the V1 output supplies the CMOS RAMs
and the V2 output supplies the microprocessor plus
other 5 V circuits. The L4901 's reset output is used
both to reset the Z80 and, through the M74HC138
address decoder, to ensure that the RAMs are disabled as soon as the main supply voltage starts to
fall. Note that the M74HC138 is supplied from the
backup battery.
It is important to make sure that the RAMs are disabled because the lithium cells used as backup batteries have a high internal resistance. If the RAMs
were not forced into the low consumption standby
state the battery voltage could drop so low that memory contents are corrupted. Moreover, to prevent
latch up, no input of a CMOS RAM should ever be
higher than the supply Voltage.
Figure 3: LOW QUIESCENT CURRENT at the V1 Input makes the L4901 Useful in Applications like this
where the V1 Regulator is always connected to the Battery.
INI
REG. 1
BATTERY
l.
O.22 ..... F I
RESET
REG. 2
l .....
FI
Voo
OTHER
LOGIC
CT
10nF
CMOS
IJP WITH
VOLATILE
RAM
@5V
I
5
RESET OUT
RESET
4
5_7710
3/7
699
APPLICATION NOTE
Figure 4 : LOW LEAKAGE at the VI Output makes the L4901 Ideal for Battery Backup Operation.
~
1.
INI
Y
I
~.
'''"'i
IN 2
,,",±
CT
10nF
...T
~J.JF ~~
REG. 2
BACKUP
BATTERY
~
IJP(3875-2875)
VIO
OUT2
6
CMOS
CLOCK
VSB
Y
2
J
OUTI I.LDI < 2IJA Voo
7
REG.'
WITH BATTERY
BACKUP
ItoIOJ.JF
I
RAM
RESET
VDO
3
~
5
.J..
RESET OUT
RESET
OTHER LOGIC
@ 5V
1
'=>_7771
Figure 5: STANDBY - The L4902 can be used in Applications where the Supply is connected Permanently and the Disable Function Used to Turn Off on-essential Circuits in the Standby State.
REG.1
7
OUT 1
I'J.JF
J:.
3
REG. 2
V02 DIS
VOO
VDD
OUT PORT
IN PORT
6
CMOS
IoJp WITH
VOlATILE
RAM
__Voo
OTHER
LOGIC
~5V
CT
10nF
I
5
RESET OUT
Rf.5£T
4
5-7843
IDEAL FOR SHADOW MEMORIES
Another interesting application forthe L4902 is supplying a shadow-ram microcomputer chip like the
SGS-THOMSON M38SH72 where a fast non-volatile memory is backed up on-chip by a slow EEPROM (figure 7). For these chips it is important to
4/7
700
ensure that the backup command is generated
when the supply is removed, a function which the
L4902's reset output can perform. Since the L4902's
reset function depends on the INPUT voltage the
power fail condition is sensed early enough to guarantee that the backup transfer will be successful.
APPLICATION NOTE
In figure 7 the reset output is forced low when the
input voltage falls below 6.3 V or when the V1 output goes below 4.S V. This allows 10 Ils for the
backup transfer (with 10 IlF capacitors) which is
more than sufficient.
Similarly, the L4902 can be used with shadow-type
RAMs such as the Xicor X2201. In the figure S circuit a capacitor on the V1 input ensures that the
X2201 is powered during the transfer operation.
When the input voltage is removed or goes below
6.3 V the L4902's reset output, connected to the
SOS5's TRAP input, forces the execution for a service routine which saves the state of the machine in
the RAM then issues a backup command. The V2
output drops immediately while the 6S0 IlF capacitor on the V1 input provides enough energy to keep
the X2201 running for the 10 ms needed to com-
plete the backup transfer. The low consumption of
the V1 regulator allows the use of a relatively small
capacitor for this function.
ADiNG A WATCHDOG
By adding a few components and two Schmitt trigger gates a watchdog function can be added tothe
L4902 (figure 9). Normally an output port of the micro
will supply a software-generated pulse at least every
10 ms. If something has gone wrong in the software
or hardware and these pulses are missing the disable input will be activated after a period set by
R1.C1, disabling all the circuitry connected to the V2
output of the L4902. The disable period could be usefur to prevent spurious operation of motors and so[enoids while the control processor is ma[funtioning.
Figure 6 : CMOS RAMs - The L4901 is Useful in Systems with Battery Backup CMOS RAMs Because the
Reset Output can be used to Ensure that the RAM Chips are disabled to Reduce Battery Drain
when the Main Supply is removed.
I
/,'22~
:r: L'
,
oon L~,I.'~
"" l4901
J: ".'
,.,
CUll
.-
5.V CHIPS
.~
R/W
1.8tolV
un. ....
BATT[AV
LIKE
TC~516
00 T~565
(",ND
J.
..l!
TO
OTHER
1
'5TATIC
,@-..
, - - en
.~CT
:t:
....,
040S
R(Ser ~ l -
10nF
1"00
I
"'no
J.
[
L
.ESE'
~
woU
MR[Q
ZB4DO
."
'DD
YO
L-..., 01
L
rn
ii
-
rn
M74HCl38
----_C
." f------."
.
•
"YrYi-
TO OTHER
M(MORT
;S I-
CHIPS
l&f-nI-
l.
l
~-1D1111
5/7
701
APPLICATION NOTE
Figure 7: NV MEMORY ~Cs - The L4902 is also Useful for Supplying Chips like the SGS-THOMSON
M38SH72 Single-chip Micro with NV Memory. In this Application the Reset Circuit initiates the
RAM-to-shadow Transfer.
Vi
Vol
VDD
7
Vo2
6
DISABLE
3
:c
L4902
TO OTHER
5V CHIPS
4 .7 f'F
1>
~F
5
2
M38SH72
RESET
VSH
4
100nF
I
I
GND
s· 3)62
Figure 8 : SHADOW RAMs - The L4901 's Reset Function also serves in Systems using Shadow Type NV
RAMs like the X2201 to ensure that the Backup Transfer is executed Correctly.
INI
Vi
J:
OUT I
680
v'"
7
J:
,..F
L4901
'Ie;,
OUT 2 6
IN2
I
3
lonFI
RESET 5
CT
702
DATA
ADDRESS
10f'F
8085
TRAP
GND
4
6/7
X2201
10}JF
S-8a~~ "
APPLICATION NOTE
Figure 9 : With a CMOS Schmitt Trigger and a few Components a Watchdog Function can be added for
Critical Application.
~------------------------------~__------~VDD
- - - - -
- - - - - - -
-I
OUTPUT
PORT
10K A
I
: JlJ1Jl
7/7
703
APPLICATION NOTE
LOW DROP VOLTAGE REGULATORS
FOR AUTOMOTIVE ELECTRON ICS
By S. CISCATO
Linear voltage regulators with an input-output voltage drop of less than 2Vare used to ensure continuity of
the stabilized output in applications where a battery supply is used. This note describes the characteristics
and operation of these devices.
Low drop linear voltage regulators are low voltage
(5 to 12V) regulators which are able to provide effective stabilization of the output voltage even when
the difference between input voltage and output
voltage is less than 2V.
This situation can arise accidentally for a brief period when the main supply source is overloaded. It
may also result from a deliberate design decision
aimed at reducing the power dissipated in the supply - for example, when the device is used as a post
regulator in portable instruments.
Low drop regulators are used widely in automotive
applications, a field where integrated circuits have
to be particularly rugged. For this reason most low
drop devices include protection functions not found
in standard regulators. Before describing the SGS
THOMSON family of low drop regulators we will
therefore begin with a brief description of the automotive electrical environment.
Figure 1 : Cold Starting Supply Voltage Drop.
AUTOMOTIVE ENVIRONMENT
In addition to the battery voltage drop during start-
Using standard regulators with a dropout of 1. 7V to
2.1V the minimum 4.75V supply necessary for essential functions such as ignition, injection and electronic engine control cannot be guaranteed. Another
unfortunate consequence is the loss of RAM memory contents in car radios and trip computers.
ing, the automotive field presents a number of other
serious problems concerning the regulator input
voltage: positive and negative high energy I high
voltage transients (load dump and field decay), positive and negative low energy/very-high-voltage
spikes (switching spikes), battery reversal and battery voltage doubling.
All of these hazards must be withstood by the regulator without damage over an ambient temperature
range very close to military standards (- 40 to
+ 125"C for underhood devices; - 40 to + 85"C for
other devices). Moreover, an output voltage precision of ± 4% to ± 2% is required overthe whole temperature range and in all conditions of input voltage
and load current.
BATTERY VOLTAGE DROP
During motor starting the battery is overloaded by a
peak current of up to 1OOA drawn by the starter
motor. In this condition, which persists for 20~30ms,
the battery voltage drops to about 6V in very. cold
weather (figure 1).
AN254/1088
14V
-
-
-
-
-
-
___ _
CHARGING
ALTERNATOR
12V
~
-6V
COMPRESSION
STROKE
I
KEY I KEY
OFF
ON
I
I
STARTING
TIME
, MOTOR RUNNING
t
A voltage regulator with a voltage drop of less than
1.2V is therefore necessary.
BATTERY VOLTAGE DOUBLING
To aid cold weather starting with a partially flat battery, sometimes two batteries are used in series,
doubling the Voltage. Regulators must therefore
withstand input voltages of 24-26V without disturbing operation.
BATTERY REVERSAL
Voltage regulators must be protected internally
against negative input voltages to guard against accidental.battery reversal.
LOAD DUMP TRANSIENTS
Load dump transients are high voltage, high energy
positive transients.
1/8
705
APPLICATION NOTE
The response time of the output voltage of an alternator to load variations is very long because of the
long time constant of the excitation winding and
mechanical inertia.
When the load is reduced instantaneously (by turning off lights, cooling fans and so on) the output voltage of the alternator tends to present a positive
peak, the amplitude of which depends on the speed
of rotation and the excitation current.
During normal operation this does not cause problems because of the high capacity of the battery
which, connected in parallel with the alternator output, is able to absorb the transient energy without a
sig nificant increase in Voltage.
However, motor manufactures impose the standard
that electronic devices must be protected against
load dump transients because it is possible for the
connection between battery and alternator to break.
The worst case voltage peak occurs when the battery-altemator cable is disconnected with the battery discharged and the motor running at its fastest
rotation speed. In this case, the load variation is at
a maximum and the voltage peak reaches a value
comparable with the no-load output of the alternator running at maximum speed with the maximum
excitation current.
on the supply rail. The peak value in modulo of this
transient is of the same orderof magnitude as a load
dump transient. In this case, too, the regulator must
protect itself and the load.
SWITCHING SPIKES
Windscreen wiper motors, lamp flashers and ignition sparks behave as high frequency noise generators with an equivalent series resistance of 50 to
500 Q. The energy associated with these transients
is much lower than load dump or field decay transients but the negative and positive peaks can reach
200V. Figure 3 shows the voltage waveform which
the. regulators must withstand.
Figure 3 : Switching Spikes.
""1TI
__ J~VJ__
h:PAUSE 90 ms
100 \0200'01
--
GNO
RISE TIME,. 50 ns
TlME CONSTANT = lOOns
100fS
10ms
PAUSE 90 inS
5-8062
Figure 2 shows a typical load dump waveform.
Motor manufacturers require that voltage regulators
are able to protect themselves and the load against
peak voltages of 60 - 1OOV with an equivalent series
resistance of 0.1 to 1Q, depending on the type of
alternator and external protection device used.
Figure 2 : Load Drump Transient.
(V)
I
VM =60V
,><
to laOY
RISE TIME 3: 5ms
.......
--(ms
100
200
300
400
S~8061
FIELD DECAY TRANSIENTS
Field decay transients are high energy, high voltage
negative transients.
'
If the ignition switch is turned off while current is flowing in inductive loads (electric motors, alternator field
coil and so on) a negative voltage transient appears
2/8
706
REGULATOR DESIGN
DROPOUT
The dropout voltage of a linear voltage regulator can
be defined for a given output current, 10, as the minimum difference between input and output voltage
below which the output voltage is 1OOmV lower than
the voltage measured at 10 with the nominal input
Voltage. The current 10 must be specified since the
dropout voltage increases as the load current increases .
To obtain a dropout voltage of 0.05 to 1V with an
output current of 10 to 50mA, the regulator types
L387A, L487, L47XX, L48XX, L4920, L4921 ,
LM2930A and LM2931A are configured with a PNP
series-pass transistor as shown in figure 4. The PNP
transistor is connected in the common emitter configuration and can therefore operate in saturation,
yielding the low dropout voltage desired.
For higher dropout values an NPN series-pass element in emitterfollower.configuration may be used.
This approach, shown in Figure 5, is used in the
L2600 series regulators which have a' maximum
dropout voltage of 1.9V at 500mA.
APPI-ICATION NOTE
Figure 4 : PNP Series Pass Transistor in Common Emitter Configuration for very Low
Drop Out Voltage Regulators.
Since vertical PNP transistors have higher gain the
current consumed in the regulator is significantly reduced. Vertical PNP transistprs will be used in future designs.
OUT
IN
VOLTAGE REFERENCE
The wide operating range of input voltage (6 to 26V)
and ambient tef11perature ( 40 to 125 DC) over which
high output voltage precision is required means that
a well stabilized voltage reference musi pe used.
GND
All low drop regulators use bandgap type voltage
references (see figure 6). In this structure the two
transistors Q2 andQ1 have an emitter area ratio of
10 and carry equal collector currents imposed by the
current mirror Q3, Q4, Q5. In'these conditions the
base-emitter voltages of 01 and 02 differ (at 25 DC)
5-8064
~:
Figure 5 : NPN Series Pass Transistor in Emitter
Follower Configuration.
IN
OUT
.
KT
A(Q2)
VBE = - - 1n - - = 60 mV
q
A(01)
A(Q2)
.
.
where A(Q1) = 10 (emitter area ratio)
KT
=26mV
q
K = Boltzmann's constant
T = Temperature in Kelvin
q = Charge on an electron
Figure 6 : Bandgap Voltage Reference Circuit in
Low Drop Voltage Regulators.
o---------~-------L---O
GND
1K
CURRENT CONSUMPTION/QUIESCENT CURRENT
The circuit configurations shown in figures 4 and 5
behave differently as far as concerns the current
consumed by the device but not delivered to the
load. In the case of figure 5, this current is that
necessary forthe functioning of the auxiliary circuitry
of the regulator (voltage reference, op amp and so
on). The base current of the output transistor flows
into the load.
05
n
04
03
:1------"'01-'- - 0 vREF
,x
In the Figure 4 circuit, in contrast, the base current
of the output transistor does not flow through the
load and, particularly in saturation, depends heavily
on the load current.
Normally lateral PNP transistors are chosen for ICs
because they can withstand high positive and negative overvoltages. When negative overvoltages at
the input do not occur, or are eliminated by external
protection devices, vertical PNP transistors can be
used in place of lateral types.
5- 80 65
3/8
707
APPLICATION NOTE
The rejection of Vrel to variations in the supply voltage is improved by supplying the reference circuit
from a stabilized voltage. This is achieved in the
L26XX, L48XX, L4920, L4921, LM2930A and
LM2931A regulators by means of a preregulator. In
the L487, analysing the Figure 6 circuit gives:
Vrel
ries Regulators.
OUT
IN
= VBE (01) + 2 B!. L1 VBE (02, 01)
"
Figure 8 : Block Diagram of L387A and L487 Se-
R2
To maintain'Vrel constant as temperature varies it
i~ necessary that d dVTrel = 0 which implies choosing
R2 so that 2R2 . ~ + dVBE(Ol) = 0
R1
R1 T(25')
dT
where T(25 ') = 298 K
d VBE ( 0 1 ) .
. .
dT
= negative temperature coeffiCient of
GND
s- 8067
the base-emitter voltage.
In L387 A and L47XX regulators, in contrast, the supply to the bandgap is switched from the input to the
output as soon as the nominal output voltage is
reached (figures 7, 8, 9). The variation in output
voltage with temperature is shown in figure 10.
Figure 9 : Block Diagram of LM2930A, LM2931A
and L4800 Series Regulators.
Figure 7: Block Diagram of L2600 Series Regu-
OUT
lators.
OUT
Figure 10: Outputs Voltage vs.Temperature .
GND
•. 9
I---.L.,.-.l--r+++-+-H-++-+-!-'-+t-H
~40
4/8
708
-20
0
20
40
60
eo
100
Tj C-C)
APPLICATION NOTE
PROTECTION AGAINST HIGH ENERGY
TRANSIENTS
PROTECTION AGAINST LOW ENERGY
OVERVOLTAGES
To protect the LM2930A, LM2931A, L4920, L4921
and L48XX regulators against high-voltage, highenergy positive transients the basic circuit shown in
Figure 11 is used. The zeners in this circuit limit the
supply voltage to the maximum operating value and
turn off the output stage. The output transistor can
thus withstand voltages up to the BVCES , breakdown voltage.
As shown in figure 3, the low energy overvoltages
which the devices must resist have very brief rise
time and can exceed the breakdown voltages. The
protection schemes described above are therefore'
insufficient. However, since the energy associated
with these transients is very low, the regulators can
withstand them without problems. Nevertheless it is
advisable to place a capacitor of around 1OOn F at
the input.
In the other regulators (L487, L387A, L47XX and
L26XX) the supply to the internal circuits is also
turned off.
The speed of intervention of these protection
schemes is fast enough to ensure that the regulator
can withstand high energy transients with a rising
slope of 1OV/IlS without problems, interrupting normal operation only momentarily.
All of .the low drop regulators except the L26XX
types need a compensation capacitor at the output.
This capacitor also provides extra filtering for low
energy transients because it has a low impedance
at high frequencies.
Figure 12 : Thermal Protection Circuit.
Protection against negative transients is provided by
the high series impedance of the possible current
paths and the reverse BVBEO breakdown voltage of
the lateral PNP transistors (BVCBO).
~>---------jl TRA~AS~~TOR ~
v REF
The breakdown voltages BVCES and BVCBO depend
on the technology therefore the transient capability
is ± 60V, ± 80V or ± 1 OOV for the various types.
DRIVER
Figure 11 : Overvoltage Protection Circuit.
GND
5- 8070
THERMAL PROTECTION
IN
When the junction temperature exceeds the safe
maximum for the device a thermal protection circuit
(figure 12) holds the output transistor off until the
overtemperature condition has passed.
In the figure 12 circuit the resistors R1, R2 and R3
are calculated so that the base voltage of 01 is
600mV, thus preventing the conduction of 01 and
FROM
OP. AMP
02.
DRIVER
As the junction temperature increases the minimum
VBE for conduction of the two transistors fall until, at
abo.ut 15 "C, 2 VSE =600mV, the two transistors conduct and 02 turns off the output transistor driver.
CURRENT PROTECTION
GND
s - 8069
In the L487, L387A and L26XX regulators the output current is limited to its maximum value in the
event of a short circuit. A special circuit acts on the
base of the output transistor, preventing the output
current from exceeding the limit set for the duration
of the overload.
5/8
709
APPLICATION NOTE
In the L4920, L4921 , LM2930A, LM2931 A and
L48XX regulators a foldback circuit (figure 13) is
used.to limit the power dissipated in both the devices
and the load in short circuit conditions. The current
is limited to.a low value (Isc) of about 200 mAas soon
as it exceeds the maximum value. The output voltage in this condition reaches a value corresponding
to the current Isc flowing through the load.
When the overload condition is removed the output
voltage only returns to the nominal load value if the
new static load line does not intersect the negative
slope region of the curve in figure 13. If it does, the
new operating point will be at the intersection.
It is important to note that when power is applied, if
the load line intersects the curve in the negative
slope region, the regulator will operate with a lowerthan-nominal voltage. This can happen with a
passive load greater than the normal load (even if it
is less than the maximum load 1M) or with' active
loads such as a current sinker which draw more than
Isc even at low voltages (figure 13, curve 3).
Figure 13 :1} Acceptable Load Line for Turn-on
2} Unacceptable Load Line for Turnon.
v0 r-r-TT--.-r-.--r-r-TT--.-r-.--r-r-.-T'--T"51181
Iv 1 H-+++-t-+-+-t-+++-t-+-H-++-H--1
3
1
~OO
500
600
lo(mAl
EXTERNAL COMPENSATION
Since the purpose of a voltage regulator is to supply a fixed output voltage in.spite of supply and load
variations, the open loop gain of the regulator must
be very high at low frequencies. This may cause instability as a result of the various poles present in
the loop. To avoid this instability dominant pole compensation is used to reduce phase shifts due to
other poles at the unity gain frequency. The lower
the frequency of these other poles, the greater must
be the capacitor used to create the dominant pole
for the same DC gain.
Where the output transistor is a lateral PNP type
there is a pole in the regulation loop at a frequency
6/8
710
The parassitic equivalent series resistance of the
capacitor used adds a zero to the regulation loop.
This zero may compromise the stability of the system since its effect tends to cancel the effect of the
pole added. In regulators this ESR must be less than
3Q and the minimum capacitor value is 47 F (100 IlF
for L4800 series).
In the L2600, which uses an NPN power transistor,
the stabilization capacitor is small enough to be integrated so no output capacitor is needed. Indeed,
if an output capacitor is used it may cause oscillation unless it is greater than 100 IlF, in which case it
would itself be the dominant pole. If an electrolytic
capacitor of more than 100 IlF is used, a small capacitor must not be added in parallel or with the ESR
of the electrolytic it would from another pole, worsening the stability of the system.
TURN-ON WITH CAPACITIVE LOADS
A load which presents a significant capacity between the output and ground (including the external
compensation capacitor) will be seen by the regulator as a short circuit when power is applied. The
regulator therefore delivers the short circuit current
until the load capacitor has been charged to the
nominal value.
This factor is extremely important for the dimensioning of the power source. Even a very small DC load
can in such cases behave like a maximum load and
the power drained from the supply is the sum of the
short circuit current delivered to the load and the
maximum current consumed in the regulator.
~~~~~~~~~~~j=
200
too low to be compensated by a capacitor which can
be integrated. For the L487, L47XX, L48XX, L387A,
LM2930A and LM2931 A external compensation is
therefore necessary so a very high value capacitor
must be connected from the output to ground.
Moreover, as explained above, in regulators with
foldback protection the static load line must not
cross the negative slope region of figure 13 or the
output voltage will not reach the nominal value when
power is applied.
SPECIAL FUNCTIONS
RESET
The L387A and L487 include a power on/off reset
function which inhibits the operation of circuits supplied by the regulator when the output voltage is too
low (4.7SV) to guarantee correct operation of logic
(figure 14). To avoid malfunctions a delay is also introduced so that the enable signal is only issued
some time after the safe output voltage has been
reached.
APPLICATION NOTE
Figure 14 : Reset Timing Waveforms.
OUTPUT
DELAV
3.7
CAPACIT.
t1
This function has been integrated into the voltage
regulator to exploit the basic advantage of taking information at the source. The use of double calibrations can thus be avoided.
For the correct operation of the reset function, two
basic relations must be satisfied in all cases
(1 )
Vres max < VOU! min
(2)
Vresmin > 4.75 V
where Vres maxIVres min are maximum/minimum value for the reset signal going high-low.
(1) means that the RESET signal must be high when
the device is regulating
I
RESET
$-B072
(2) means that the RESET signal must be low when
the output voltage goes under 95 % of the nominal (5V). Expressions (1) and (2) can be rewritten as:
(Vres max Vres min) + (Vnom YOU! min)
The reset circuitry (figure 15) consists of :
_ a comparator connected between the voltage
reference and a tap of the output divider, the
voltage of which is higher than the feedback
voltage;
an SCR to memorize any brief glitches in the
output voltage that can cause some trouble
with the logic.
_ a delay circuit with an external capacitor
charged by an internal current source
(3)
< Vnom 4.75V
This means that the sum of all the errors in the
worst case must be less than 5 % (250mV).
_ absolute spread of the reference
_ error due to the load regulation (1 % max)
_ error due to the offset of the reset comparator and error amplifier (0.5 %)
_ errors due to the output divider (0.5 %)
_ hysteresis of the comparator to speed up the
transitions (50mV that is 1 % referred to 5V
output)
Figure 15 : Schematic Block Diagram of a Voltage Regulator with Reset Function .
...,
IN
I
I
I
I
I
L __
5- 80 71
7/8
711
APPLICATION NOTE
VARIABLE OUTPUT VOLTAGE
below 4.5V (otherwise the internal circuits will not
work). For output voltages above 4.5V the input voltage must be at least equal to the output voltage plus
the dropout voltage. The L4920 and L4921 are
therefore low dropout regulators only for voltages
above 4.5V.
The L4920 and L4921 are structurally identical to
L48XX series regulators except that the voltage
divider in the feedback loop is available externally
(figure 16). The output voltage can therefore be varied from 1.25V (the reference voltage) to 20V. It
should be noted, however, that the minimum input
voltage is 5.1 V for operation with output voltages
A value of 6 Kn is recommended for R2 to match
the internal circuitry.
Figure 16 : The L4920 and L4921 are Structurally Identical to L48XX Series Regulators Except that the Voltage Divider in the Feedback Loop is Available Externally.
IN PUT
1
IPREREGI..lATOR
1
1.PROTECTKlNJ
DUMP
I
BANDGAP
REFEPENCE
AND
ERHOR
AMPLIFIER
ill
1
OUTP UT
I
I
[
I,PROTECTION
THeRMAL 1
I
FOLDBACK
C~~~i~;
ADJU 5T
R2
I
I
1
GN o
!._791&1"
8/8
712
Rl
POWER MOS & IGBTS
713
APPLICATION NOTE
SAFE BEHAVIOUR OF IGBTs
SUBJECTED TO dV/dt
by R. Lelor, M. Melilo
ABSTRACT
INTRODUCTION
When an IGBT in the off state is subjected to
a high dV/dt, parasitic turn-on can occur leading
to additional losses.
This paper describes the phenomenon and
indicates the main parameters influencing this
behaviour.
Several methods of suppressing this parasitic
phenomenon are described.
Using a suitable design of gate drive, it is
possible to increase the circuit reliability in all
conditions.
Practical examples and measurements are
~iven ..
The behaviour of IGBTs subjected to a dV/dt
differs according to the working conditions.
We can consider two distinct cases:
t\N476/0492
- static dV/dt
The static condition occurs when the dV/dt
applied to an IGBT in the off state, acting
through the reverse capacitance C 9 "" Cres '
causes the gate voltage to rise turning the
device on. This behaviour is typical of a
circuit in bridge configuration, where thedVI
dt is generated during complementary switch
turn-on. This undesired effect generates
1/9
715
APPLICATION NOTE
additional losses, mostly in devices in the
off-state, due to the presence of both high
voltage and high current on the collector.
Parasitic turn-on must be avoided and this
can be prevented by modifying the design of
the drive circuit.
dynamic dV/dt
In this condition the dV/dt is applied to an
IGBT during the recombination of minority
carriers in the substrate and a peak current
appears during the collector voltage rise
time even if the gate and the emitter are in
short circuit. The dynamic condition can
occur when the IGBT works in thyristor
mode, typically in aquasi resonant converter
with a zero curent switch (QRC-ZCS).ln this
case the power losses depend on the device
structure and on the converter resonant
frequency. Thus, this phenomenon sets a
limit to the operating frequency.
I = cog· dV/dt
1--~
.,... ccg
I
c
dV/dt
Rg
Fig.1 - Current flow through IGBT capacitances
due to dV/dt
1. SPURIOUS TURN-ON IN STATIC dV/dT
CONDITION.
1.1 Description of the Phenomenon.
The equivalent diagram offig.1 shows current
flow across the structure of an IGBT in the offstate when a rising collector-emitter voltage is
applied.
The current through the reverse capacitance
Cgc ( Cgc « Cge ", Cres => i = C res • dV/dt),
charges the gate capacitance; in this way, the
gate voltage can reach the IGBT threshold
voltage and a conduction current appears.
Photo 1 shows the waveforms du ring aspurious
dV/dt turn-on giving prominence to the
simultaneous presence of high voltage and
high current.
If the output impedance of the drive source is
high this phenomenon occurs more easily
because of the higher ratio between the
reflected Vge and the applied dV/dt.
219
Photo 1 - Waveforms during a spurious turn-on
due to static dV/dt condition.
Gate voltage = 2V/div,
Drain Voltage = 200V/div,
Drain current = 2A1div.
Thus the main parameters influencing an
IGBT's behaviour in staticdV/dt condition are:
- device characteristics (C res ' Cge , Vth , gls)
- temperature
- Rge , dV/dt value
- gate bias
--------------------------~~~~;~~~:9~
716
--------------------------
APPLICATION NOTE
1.2 The influence of temperature.
When the temperature increases, IGBT
parameters vary as follows:
- transconductance at low current increases
- threshold voltage decreases
- turn-off time increases
As a consequence, when the temperature
increases the power losses due to dV/dt turnon increase and the phenomenon occurs at a
lower dV/dt value.
Photo 2 shows a comparison of the peak
current at T j = 25°C and T j = 1GGoC with the
same static dV/dt conditions.
1.3 The influence of dV/dt and Rge'
The effect of Rge and dV/dt can be evaluated
with the simplified circuit in fig.2 but the
mathematical resolution is not easy because
of the influence of the voltage on C ge and Cge'
The behaviour of SGS-THOMSON's IGBTs
were characterized by the test circuit in fig.3,
taking care to measure the energy dissipated
in the devices at Tc = 1GGoC E =d v(t) • i(t)dt.
The curves in fig.4showthis measured energy
versus both Rge and a typical dV/dt.
Considering a single curve, dV/dt = ~onstant,
it can be observed that it has a minimum
constant value for Rge lower than the "knee"
value.
In this region IGBT parasitic turn-on does not
occur and the absorbed energy only charges
the IGBT output capacitance.
1.4 The influence of gate bias.
Gate bias voltage influence was analyzed for
negative voltage (V EE) using the test circuit in
fig. 3.
Figs.5 and 6 show that, when VEE = -5V
spurious turn-on does not occur even if the
value of the resistance connected to the gate
is high (18GQ). Looking at the waveforms in
fig. 7 we can note two different effects on the
gate voltage due to the negative bias.The first
is obviously that the gate voltage is offset from
V EE and the second is that there is a different
gate voltage peak even if the applied dV/dt is
the same. This happens because of the
influence of gate voltage on C ge .
Photo 3 shows the gate charge curve and
clearly demonstrates the variation ofthe slope
.--------------e c
Ceg • f(Veg)
G
Rgi
Cge • f(Vge)
dV/dt
Rge
'hoto 2 - Comparison between the peak current
due to static dv/dt with Tc = 25°C and
Tc = 100°C, 10 = 2Ndiv, V0 = 100V/div,
Rg = 100 W, E@25°C = 226 mJ,
E@1QQoC = 1. 2m6 mJ
E
- - - - - -_____ W'I SGS·1HOMSON
'J,
Fig. 2 - Simplified input circuit.
_ _ _ _ _ _ _ _ _ _ _3_/9
Ii>lD([;L1Im~rnIi:'ii'L1I@[;JDIGi§l
717
APPLICATION NOTE
/--
Vee
~iI
v" (100V/div)
;""'-
\Jh;~Ie
\1\ '
/i
'
~
~V'
(5A/div)
~
~~
l~ie~'G~) ~
1
Vetl " le\ (20 0 VA(diV:
Fig. 3 - Test circuit and related waveforms
EnergY(IlJ)
@
Tj • 100'C
STGH8N100
8kV IllS
500
4kV/IlS
400
1kV IllS
300
.5kV/IlS
200
100
0
20
40
60
Rge(ohm)
8
100
Photo 3 - Gate charge. Curve Vge = 2V/div.
Vee = 100V/div
Fig. 4 - Energy dissipated. versus Rge and dV/dt
of the voltage occuring at V ge =-2V. If Vge is
greater than this value then C ge = Cies (input
capacitance, output short circuited) if V ge is
lower than this then Cge is about four times
Cies and reduces the gate voltage peak.
a) connecting gate and emitter by a low turnoff resistance
2. HOW TO AVOID PARASITIC dV/dt
TURN-ON.
The previous paragraph shows that it is
possible to avoid undesired turn-on during
dV/dt by:
4/9
b) reducing dV/dt
c) biasing the gate, during the off state, with a
negative voltage
2.1 LOW Rge VALUE DURING THE OFF
PHASE.
Depending on the required performance, this
solution can be applied as follows:
- - - - - - - - - - - - - l i ; j ~~~;m&r::oo~J: ------------718
APPLICATION NOTE
6rE~ne=r~g~y~(m~J~)____________________- - .
6
200 Energy(uJ)
il.Rg~. 100 ohm
STGH20N50
160
4
3
Rge • 180 ohm
dV Idt • 8kV IllS
Tj • 100·C
100
STGH8N100
dV Idt • 8kV IlJs
Tj· 100·C
2
1 .
oL---------~=---~~--------~
2
3
456
o
Negative gate bias(V)
Fig. 5 - Dissipated energy versus negative gate
bias and Rge
STHI10N50
60
o~-----===~======~--~
o
234
6
6
Negative gate bias(V)
Fig. 6 - Dissipated energy versus negative gate bias
- Rge strongly influences dV/dt at turn-off
1/
I-
dV~dt
f-- I--
!/
--'
I.r"'(
v~ =
Vet
I
100 v/,,;V
I
0/
=-
2 V/"';v
"t--l"- I--5V
"r-
--
t - f-.
2 V/d;v
I I
Fig. 7 -Comparison of gate voltage behaviour with
and without negative bias
- the RBSOA is guaranteed for Rg = 100Q
Fig.9 shows this behaviour and the diagram in
fig.10 shows thatthe maximum Rge necessary
to avoid dV/dt problem is less than 100Q
Thus, the driving circuit of fig.9 is suitable for
applications where the full safe operating area
@ Rg = 100Q is not required.
The driving circuit of fig.8b turns-off the IGBT
with Rg = 1OOQ obtaining the full RBSOA but
the delay "d= tstorage + tfall " for each must be
optimised for each application.
2.2 Reduction of dV/dt.
1) Rge is the gate turn-off resistance as shown
in fig.8a.
2) Rge is connected just after turn-off as shown
in fig.8b.
The disadvantage of the driving circuit shown
in fig .8a is that this circuit does not guarantee
the full safe operating area (RBSOA) when
Rgs is less than 1OOQ, for the following reasons:
. the latching current depends on dV/dtduring
turn-off
The spurious turn-on problem due to dV/dt is
typical of the circuit shown in fig.11; in this
circuit, the free-wheeling diode in the parallel
with the lower IGBT, which is in the off state, is
turned off during the upper IGBT turn-on and
a high dV/dt is generated.
Thus, dV/dt value depends on :
- complementary IGBT turn-on speed (dl/dt)
- free-wheeling diode "softness"
- wiring inductances
5/9
-------------------------- ~~~~~~~:9~--------------------------
719
APPLICATION NOTE
l
Rg (on)
Jl
Jl
Rg (off)
!-.....
Age
(b)
(a)
Fig. 8 - IGBT driving circuits
STGP10N50
Rge (ohm)
250r=~------------------------------.
140 Ie (A)
.. Tc ......100~C
100 ...
Tj = 100 'c
200
120 ............................. Vce···400··V
150
.......................... V"JL~...15 ..V....
eo
STGH20NSO
100
60
40
20 ............................................................................... .
50
o+---~---+----~--~~-+--~
o
20
40
eo
so
100
2
120
4
6
8
10
Rg (ohm)
dV Idt (kV 11-18)
Fig. 9 - Ilatch versus Rgoff
Fig. 10 -Max Rge values that avoid static dV/dt
turn-on versus dVIdt
Vee
Vee
IRM
b h h t.
dV/dt DURING DIODE RECOVERY
lG8T CURRENT
Fig. 11 - Typical circuit where static dV/dt conduction can occur.
-------------------------- LV ~~~~m&~:oo~~ -------------------------6/9
720
APPLICATION NOTE
Diode current recovery
during turn-off = 10Aldiv
Drain voltage and dv/dt
due to the diode turn off 200V/div.
Current due to spurious
turn-on with Rgs = 100 Q2A1div
Photo 4 - Waveforms in the circuit of fig. 11 when: Rgon = 100 Q
Diode recovery
= 5A1div.
Dv/dt due to diode turn-off 200V/div.
Current in the IGBT in off state 2A1div.
Photo 5 - Waveforms in the circuit of fig. 11 when Rgon = 200Q. In this condition turn-on due the dv/dtdoes
not occur.
and it can be minimized:
- using fast soft recovery diodes.
resistance. In the case of photo 5 spurious
turn-on due to the dV/dt does not occur.
- reducing wiring length.
2.3 driving the IGBTwith a negative voltage.
- turning on IGBTs slowly, with a high value of
turn-on gate resistance.
Biasing the gate negatively, as shown in photo
6, causes a higherdV/dtduring turn off because
of the availability of a large gate current. It is
possible to avoid this drawback, which reduces
the effective RBSOA, simply by increasing the
Photo 4 and 5 show that the dV/dt is reduced
to a safe value in the circuit of fig.11. Photo 4
uses a low value of turn-on gate resistance
whereas photo 5 uses a high value gate
value of Rg(off)'
- - - - - - - - - - - - - l i f i · ~~~~mgr:::>!?::
------------7/9
721
APPLICATION NOTE
3. DYNAMIC dV/dt.
This condition may occur in a zero current
quasi resonant converter where the IGBT
works as a thyristor.
In this application, see fig. 12 and photo 6 the
IGBT is turned-off when the collector current is
zero and the collector voltage starts to rise
after a delay time td '" (2 • fresonance)-l,
corresponding to the end of the reverse
recovery phase of the anti parallel diode.
This increasing voltage causes a currentspike,
leading to power losses becauseofthe minority
carriers in the IGBT substrate. The amplitude
of the spike depends on several factors which
involve both IGBT and circuit characteristics.
One of the factors is the amount of the stored
charge when the dV/dt is applied. The stored
charge depends on the type of IGBT (slow or
fast), junction temperature and resonant
frequency.
Increasing temperature and/orfrequency leads
3.5
Cr
P~ea=k~c=ur~r=en~t~(~A~)
______________~~
i-
3
2.5
peak current_
2
Lr
:r
1.5
STGH8N100
delay time
Te • 100'C
5000V/IlS
dV/dt.
?5
oL---~--~--~--~--~--~--~
o
2
3
4
5
6
7
Delay time (us)
Fig. 12
Fig. 13 - Peak current versus tdelay
Gate voltage = 10V/div
Drain current = 2Ndiv
Drain voltage
= 200V/div
Photo, 6 - Waveforms in a resonant converter where dynamic dvldt occurs. Device = STGH8N100,
Tc=100°C
8/9
-------------------------- 11.." ~~~mgr::9J:
722
------------------------
APPLICATION NOTE
to a higher current peak. The diagram in fig.13
shows how increasing resonant frequency
affects the current peak.
For frequencies lower than about 120 kHz the
current peak is constant, because there is no
more stored charge and due solely to capacitive
effects that are similar to those in Power
MOSFETs.
The other factor is related to the rate of voltage
rise which depends strongly on the softness of
the diode. Using a slower IGBT emphasizes
the effects discussed above. In low frequency
working conditions the power losses are no
longer negligible and must be considered
during the circuit design in order to avoid
thermal runaway and consequent device
failure.
4. CONCLUSION.
The dV/dt phenomenon causes power
dissipation in IGBT devices and this may lead
to the failure due to thermal runaway. The
way to avoid this phenomenon depends on
the operating conditions.
When an IGBTworks in astatic dV/dt condition,
as for example in a bridge circuit, it is possible
to prevent the dV/dt phenomenon by modifying
the design of the IGBT drive circuit:
- reducing dV/dt.
- connecting a low gate-emitter resistance.
- driving the IGBT with a negative voltage at
turn-off.
If a high current is to be controlled with a
switched mode technique, it is necessary to
design the drive circuit to obtain the full
guaranteed RBSOA.
When the IGBT works in dynamic dV/dt
condition, as in a QRC-ZCS, it is not possible
to avoid power dissipation in the device by
optimization of the drive circuit. These kind of
losses can only be limited by selecting a
suitable converter resonant frequency and
antiparallel diode.
9/9
-------------------------~~~~~~~~::~-------------------------
723
APPLICATION NOTE
STATIC AND DYNAMIC BEHAVIOUR
OF PARALLELED IGBTs
by R. Letor
ABSTRACT
Problems associated with power device
characteristics when power devices are
connected in parallel, such as thermal stability
and balanced switching behaviour can be
solved by using insulated gate bipolar
transistors (IGBT).
This note deals with parallel IGBT behaviour
analyzing both static and dynamic
characteristics.
The influence of heatsink mounting, lay-out,
and drive circuit are described in order to
demonstrate the best way to parallel IGBTs
for optimum performance,
AN47710492
In addition the major advantages of the
ISOTOP package are shown.
I. INTRODUCTION
When switching devices are paralleled, the
following points must be carefully considered:
1) On-state losses balance.
2) Switching losses balance.
3) Thermal stability.
The loss unbalance, depending mainly on the
spread of the device parameters (V CEsat'
switching time), can cause excessive power
dissipation in one or more devices.
1/13
725
APPLICATION NOTE
The thermal instability, correlated to the
behaviour of the devices when the
temperature increases, can cause thermal
runaway and lead to the failure of the device.
This note explains the theory, describes
practical examples and suggests possible
solutions.
The behaviour of the IGBTs considered is not
dependent on type, hence, the results can be
extended to all SGS-Thomson IGBTs.
II. BEHAVIOUR OF PARALLELED IGBTS IN
THE ON STATE.
The IGBT is a voltage driven device, hence
when the devices are in parallel the drive
conditions are the same for all devices
(i.e. they all have the same V GE)'
Thus the influence of output characteristics
and of the transfer characteristics can be
studied separately.
A. Current balance in the on state.
Current balance can be studied with the
simplified circuit of fig.1 where the following
conditions are respected:
VCEsat1
= VCEsat2
= ILOAD
IC1 + IC2
VCEsat1 = f(l c1 , Tj1' VGE1)
VCEsat2 = f(I C1 ' Tj2' VGE2)
(1)
This system of equations (1) has a graphical
solution which is shown in fig.2 for the
extrapolation of current balance in two
paralleled IGBTs with the same junction
temperature (Tj1 = T j2)·
Figure 3 shows the influence of the spread of
VCEsat on the current balance.
B. The influence of the temperature on
current balance.
The fig.4 shows the basic equivalent structure
of the IGBT.
The device functions as a bipolar transistor
which is supplied base current by a PowerMOSFET.
The IGBTs output characteristic combines
both the bipolar and the Power-MOSFET
characteristics.
IC1
IGBT1
~
!'--...Ivc
IGBT2
t-,.....
I
1
I load
IC2
VCE2
VG
Fig. 1. Circuit where current balance depends only
on IGBT characteristics.
Fig. 2. Graphical extrapolation of current balance
in the on state for two STGP10N50 @
ILOAD = 10A; Tj1
VCE = O.5V/div.
2/13
= Tj2 = 25°C;
Ic
= 1Ndiv.:
------------- LV ~~~;mgr::oo~~ ------------726
APPLICATION NOTE
The curves in fig.S show these effects and
highlight the following points:
1 - The temperature coefficient of VCEsat is
negative at low current density (I < I NOM)
(bipolar effect).
2 - The temperature coefficient of V CEsat is
positive at high current density (I > I NOM)
(Power-MOSFET effect).
3 - The temperature coefficient of the
dynamic resistance (di/dv) is positive
(Power-MOSFET effect).
!50 Mell
40
I load • I NOM.
e
............................ .
18
0:
I
y
...
H
Ie • (It'B)IB
1
V GE··.;.··15V····Z ................................
20 ............
•••••••••••••••••••••••••••••••••••
"'
10 .
o
- At low current, current balance is worst
when the temperature difference increases,
but the temperature coefficient is low.
load (%)
Tj1 • Tj2 • 100 C
30·
The effect of this behaviour is that the
influence of the temperature on current
balance is small and that the current balance
improves when the temperature increases, if
Ti1 = Ti2 (~Tj = 0), (fig.6).
Figure 7 shows the effect on current balance
when the junction temperature of paralleled
devices are different (~Tj = 0) and the medium
temperature is constant (Tj1 + Tj2 )/2=K:
.............................................. .
5
W
~
~
~
~
~
$
~
00
~ VCE(satllVCE(sat} (%)
Fig. 3. Current balance versus the V CE(sat)
difference in two paralleled IGBTs.
coefficient
Fig. 4. Simplified equivalent circuit of an IGBT.
80 (101 - 102)/1 load (%)
CQ9ffic
ent
,
2
VCESAT
Fig. 5. Output characteristics versus the
temperature for STGP10N50. I = 2A1div.;
V = O.5V/div.
4
6
8
10
12
14
16
I load (A)
Fig. 6. Current balance versus ILOAD and
temperature in two paralleled IGBTs.
3/13
-------------- LV ~~~~m~r::O!~:= -------------
727
APPLICATION NOTE
- At high current the behaviour is similar to
the power- MOSFET behaviour; in fact,
current balance improves when the
temperature difference increases.
turned on, while the free wheeling diode is still
conducting; with this working conditiondildt
is not limited by. the stray inductances and
depends on the IGBTs switching speed
C.INFLUENCE OF THE TRANSFER
CHARACTERISTICS.
(dlldt » Vcc/(L s1 + Ls2 + Ls3).
When IGBTs are strongly saturated, the
influence of the transfer characteristics on
paralleled devices behaviour is small.
The figure 8 shows that the gate voltage
scarcely influencesthe V CEsat value; hence it
is not possible to improve the current balance
in the on-state by connecting an emitterground resistance.
III.
PARAMETERS
INFLUENCING
SWITCHING BEHAVIOUR.
The IGBT's switching behaviour depends on:
A. Turn-on.
During turn-on, the switching losses depend
mainly on the di/dt that influences the
peak current due to the diode recovery
(Eco '" Ipeak • tcross • Vcc/2).
In the circuit of figure 9, the voltage drop
caused by the inductance of the emitterground connection (L s1 ), reduce the drive
current (IG = (Vd - VG - Ls1 • di/dt) I RG), and
acts as a negative feedback during current rise
time. Taking into account the effect of L s1 ' the
value of di/dt is:
- Device parameters (V th , gis' Cj, CrSS'C o )'
- Drive circuit.
dildt", (Vd-V th ) I (RGCj I gls + Ls1)
For 1000V devices and with RG
- Lay-out (Parasitic inductances).
The switching behaviour is studied in the
circuit of figure 9 where the stray inductance
"Ls1+Ls2+Ls3" is small and the IGBTs are
The inductance of 1cm of wiring is:
Ls1 '" 10 • 10-9 H/cm
6 VcEsat (V)
1~IC~1(~~)-~I~c2~(~~)~~~)~__~
8.5 ····················2··.· STGP 1ON50
STGP10N50
5t~=::;~:~<~~:
::::::::::::::::::S;~::~:~:~:~~:::::::::
4"4 .
S.9 ........ .
II ........................... .
-
KT' - 0.03 Ale
-+-+-
KT'O
L--'---'-_.._. . . . . . _....--<.. --_..._....-L
....----.J
f
10
Tj • 90 C
20
80
40
50
eo
·· .. ··· .. ······· .. ········· ..(c .. ·1OA·· .... ..
3
.. ... ...........Ii..~..JQQ.G......... ..
11 .. ·· .... · · ......·.. ····· .... ·..·...... ·.. ·· .. ··.... ·.. ···· .. ·· .. ·.. ···+ ............................j
6VCE sat/VeE aat-25%
Voe' 15V
TI1-1J2 ( C)
Fig. 7. Influence of 11Tj on current balance during
the ON-state. KT is a temperature coefficient.
4/13
4
KT' 0.001 Ale
2.::L.-.._~dI~=:::=::""":~=::~.::;;.c~:::c:;;;A.::c:.:-:=:t
1.~
= 100Q:
15 • 10-9 < RGCj I gls < 25 • 10-9
O,L---'---~~~--~----'-'-;--~--~
6
79ft
~
ffi
V
m
GATE-EMITTER VOLTAGE (V)
Fig. 8. Typical V CEsat versus gate bias.
------------------------- L;i ~~~~~~:~~~ ------------------------728
APPLICATION NOTE
From this it can be seen that the spread of
device parameters has less influence on the
di/dt value than the parasitic inductance of the
emitter-ground connection.
B. Fall.
During current fall two distinct phases can
be seen (figure 10).
Phase 1 is similar to the current fall of powerMOSFET and the parameters influencing the
di/dt are the same parameters that influence
dildt during turn-on.
The tail during phase 2 which is due to the
minority carriers stored in the substrate mainly
affects the switching losses.
The tail amplitude depends on Tj and on the
turn-off current; hence, the turn-off current and
the working temperature mainly influence the
losses during the fall time (Fig. 11,12).
IV. PARALLELED IGBT'S SWITCHING
BEHAVIOUR.
The influence of the drive circuit, of the layout and of the device parameters was verified
using the following conditions:
- 1 Gate drive with separate gate resistances
(fig.13).
- 2 Gate drive with one gate resistance
(fig.14).
- 3 Unbalanced emitter-ground wiring
connection (fig.1S).
- 4 Paralleling devices with the maximum
spread of the parameters.
The voltage and collector current waveforms
are stable in all conditions, even in the worst
case condition where the gates are driven with
a common resistance and the wiring
inductances are strongly unbalanced
A. Turn-on.
C. Storage.
During the storage time "Ie = gls (V GE-Vth)",
"dildt = 0" ,and the current waveform depends
only on the IGBTs parameters (giS' Vth ) and
on the drive circuit.
c
~
,,' - - -
VQ
""
,,"
Photo 1,2 show that the drive circuit influence
on peak current balance is small and
photo 3 shows that the peak current
unbalance is significant in condition 3, where
.1Ls1 = 0.1SIlH.
'---<:I--~-oVcc
laS
P-MOS region
FREE WHEELING
PEAK DUE TO d1Idl
"/
Va
b
~
(
!
.~Iil
t
,I
II ~
I
Ie
storage
Fig. 9. Circuit showing the parasitic inductances
influencing the switching behaviour.
Bipolar region
~,
fall
t
Fig. 10. Gate voltage and current wavelorms
during turn-off time.
5/13
-------------------------- ~~~~~~:::~ ----------~-------------729
APPLICATION NOTE
Cross-over energy (mJ)
3
I
;
!
2.5 ..
lSTGP\0~50
1
J .......
2
···~~~ii~;~,
Nomalimd Eco (Eco/Eco • 100 C)
1.5 ;===;:.-=-::.....:::c;:..::..:.='---,-.:..:..:.-=..,...----'---,-----,
.... J
.1.
1.25 ..
. l . j ··1··
i
········r-··
0.76····
j
1.
0.6
...
0.6
0.25 .
-L__-L__~__·~
~__~__
16
20
Iswilch (A)
26
30
35
!
....i · · · · · j · i S T G P 1 0 N 5 0
i~.ro~
i
oL-__l -__
o
10
5
···i····
i
....l .......... .i.
1 .
I!
1.6·····!··j+·
i
············r· ............ ,. ..
"'r ·······:I·r~:~;i~i~T~h;.
oL-__
o
- L_ _ _ _L -_ _~_ _ _ _~_ _~_ _~
25
50
75
100
125
150
Tj ( C)
Fig. 11. Switching losses at turn-off V sturn-Off
current.
Fig. 12. Influence of temperature on turn-off losses.
=3
I'
.----------~---~~
Fig. 13. Driving with separate gate resistance.
Fig. 14. Driving with one gate resistance.
Vao
RaIl
WIRING
Vd
UN:W...ANCE
Fig. 15. Emitter ground wiring unbalance.
6/13
Photo 1. Turn-on with separate gate drive
(fig. 13) of an STGH8N100;
I = 2Ndiv., t = 200ns/div.
--------------~------------- ~~~~~~~~::~---------------------------730
APPLICATION NOTE
IGBTs with the maximum difference in
parameter values were paralleled; the
comparison of current waveforms in photo 1
and 2 demonstrates that the influence of
parameter spread is low (L s1 = 30 nH).
B. Fall.
switching loss unbalance in comparison to the
total turn- off switching losses.
The current unbalance just before current fall
that affects the tail amplitude can create
significant switching loss unbalance
(see fig 17).
Photo 4 and 5 show that the wiring inductance
unbalance affects only the power-MOSFET
phase; but this behaviour creates negligible
C. Storage.
Photo 2. Turn-on with one gate resistance
(fig. 14) of an STGH8N100;
I = 2A1div., t = 200ns/div.
Photo 3. Turn-on with unbalanced emitter-ground
wiring (fig. 15) ofa STGH8N100;
I = 2A1div., t = 200ns/div.
Photo 4. Turn-off with balanced gate-emitter
wiring (fig. 14) of a STGH8N100;
I = 2A1div., V = 200V/div., t = 500ns/div.
Photo 5. Turn-off with unbalanced emitter-ground
wiring (fig. 15) of a STGH8N100;
1= 2A1div., V = 200V/div., t = 500ns/div.
During the storage time, the spread of the
IGBTs parameters (gis' vth ) and the difference
------------- I:fi ~~~~~~::O!~~ ------------7/13
731
APPLICATION NOTE
between storage times causes current
unbalance thus creating switching loss
unbalance.
Photo 6 shows the effect of the storage time
differences when the gates are driven with
separate gate resistances.
The collector current begins to fall in the
device with the smaller storage time,
consequently the current increases in the
other IGBT so increasing storage current
unbalance.
Driving the gates with only one gate resistance
minimize this effect (photo 7); the device with
the higher storage time hold the gate voltage
to "Vth+glslc" until the fall time phase, so
equalizing the storage times.
Current unbalance due to the IGBTs
parameter spread can be calculated with the
equations (2) and (3).
The curves of fig.16, 17 show, respectively,
storage current unbalance and the
consequent switching loss unbalance
between two devices where the V th and gls
values are the limits of the parameter spread.
Photo 6. Effect of separate gate drive on
storage current waveform. I c=2A/div.,
V CE=200V/div., V GE=l OV/div., t=500ns/div.
8/13
Iload
= 11st +
Istorage
12st = VGE (gls1 + gls2)(glsl vth1 + gls2vth2 )
= 11st - 12st = VGE (g'Sl - g'S2) (glSl v th1 - gls2v th2 )
(3)
V. THERMAL STABILITY.
When IGBTs are connected in parallel the onstate current is greater in the device with the
smaller V CEsat (fig.2); thus, the power
dissipation and the junction temperature is
higher in this device.
This phenomenon can cause a thermal
instability because of the following reasons:
Current unbalance increases when junction
temperature difference increases (fig.7 ).
- Switching loss unbalance increases when
junction temperature difference increases
(fig.12).
The thermal stability can be achieved by
mounting the paralleled IGBTs on the same
heatsink; in this way the heatsink works as a
negative feedback, because it transmits the
heat from the device with the higher T j to the
device with the lower T j so reducing the
junction temperature difference.
In the ideal case where the thermal
resistances (R thj h,Rth x) are null, the thermal
stability is assured because the devices work
at the same temperature and the current
balance improves when the temperature
increases as shown in fig.6.
In real conditions the thermal resistances
"R th1h " are not negligible and the thermal
stability can be studied with the equivalent
thermal circuit of fig, 18 which can be simulated
with the system shown in fig,19,
The behaviour of the system near the final
working point, is simulated using two
paralleled IGBTs driving a constant inductive
load; the devices are only active when the
- - - - - - - - - - - - - l i f j ~~~~~~r::oo~!:
732
(2)
-------------
APPLICATION NOTE
heatsink temperature is uniform and at the
final temperature which is independent of the
current balance as the equations (4),(5),(6),
(7),(8) show.
(T heatsink= T amb+ Rth h-amb. (V CE(sat) (I C1+ IC2 )+
Switching losses} ~ canst.
(8)
T ambo = canst.
The stability was evaluated with the following
conditions:
- heatsink temperature constant (load
constant).
(4)
Initial junction temperature equal to the
ICI + IC2 = ILOAD = canst.
(5)
VCEsat ~ canst.
(6)
heatsink temperature (100°C).
Turn-off current unbalance constant and
Switching losses ~ canst.
(7)
Photo 7. Turn-off with one gate drive resistance;
Ic=2Ndiv., V cE =200V/div., VGE = 10VI
div., t = 50Dns/div.
equal to the maximum value (worst case).
Thermal capacitances disregarded.
Photo 8. Comparison of current balance at
Tj=25°C and 100°C; Ic=2Ndiv., t=1 0lls/div.
{I
•.~C1~-~lc~2~l/~[I~oa=d~(~~b~)________________
tOO'-
STGPION50
80 ............
································Tj~··l(jc:fC·············
.......... .
026 .............. .1. .......... .
.
I
0.2 .............
(glol-gf82)/gfe • 26'10
+..
0.16 ......
0 ..1
20 ................................................................................. .
0.05 ···········i······(vti/::vt;:i2ijyji'~25ijj,
oL-----~----~----~----~--~
o
6
10
16
20
.. STbp 1ON50 ....... .
i
···········1·, " ji···(gr8.~g;~2j;gla~25%·
TJ -1 100 C j
26
LOAD CURRENT (Al
Fig. 16. Storage current unbalance versus load
current.
OL---~IL---~----~----~----~
o
6
10
15
20
25
LOAD CURRENT (Al
Fig. 17. Switching losses unbalance due to
storage current unbalance.
--------------------------l.V ~~~;m~r::il~~ -----------------------9/13
733
APPLICATION NOTE
The blocks in fig.19 signify the following
computations:
1 - calculates initial current unbalance
(~Tj = 0) depending on the output
characteristics of paralleled IGBTs.
2 - Calculates junction
temperature
difference depending on the on-state
current unbalance (~Ion) and on switching
current unbalance (~Is)'
~Tj
= Rthjh
* (~
Power dissipation).
3 - Calculates the growth of current
unbalance (incr.~I) due to junction
temperature difference (fig.16).
If Rth x is negligible (Rth x «
Rth jh):
f(~lon) = Rth jh * ~Pdon =
Rth jh * VCEsat * (ton/T) * ~Ion = KR * ~Ion
(9)
f(~ls' ~ Tj) = Rth jh * Pdswitching =
Rth jh * f * ~Eco(~ls ' ~Tj)
(10)
~Eco(~ls' ~T j) = ~Eco(~ls' 100°C) *
* (1+~Tj
Ks) (see fig.12,17)
*
incr~lon=KT*~Tj
(seefig.7)
(11)
(12)
The equation (13) is the transfer function of
the system.
~T j = KR * ~Ion + Rth jh * f * ~Eco /
FRAME
\
I
_DIE
i-;::J
I
{d
(1-(K R * KT + Ks * Rth jh * ~Eco * f)) (13)
Thermal stability is guaranteed if the equation
(14) is true.
(KRKT + Ks Rth jh * ~Eco * f) < 1.
(14)
Fig. 18. Equivalent thermal circuit.
A. Example of two paralleled STGP1 ON50FI
(Fully insulated package).
Conditions:
f = 15KHz
ILOAD
EFFECT OFL\.Vc E8St
= iDA
b. V CEsatlV CEsat=20%
EFFECT OF RthJh
Rth jh = 3.5°C/W
tonlT = 0.5
EFFECT OF ~TI
Fig. 19. Simulation of the temperature changes
for two paralleled IGBTs.
10/13
Parameters
Reference
~Eco
= 0.2 mJ
See fig.17
Ks = 0.005;oC
See fig.12
KT = 0.007 ArC
See fig.7
--------------------------~~~~;~~:::~ --------------~---------734
APPLICATION NOTE
KR = 3.5
KR = 2 Rth jh • tonlT
lil on (liTj=O) = 2A See fig.3
VCEsat
= 2V
Solution of the equations (13) and (14):
KRKT + Ks * Rthjh * liEco * f) = 0.08« 1 (15)
r----_----.--{)
BYTl6P400A
I LOAD
.•• J
2 • STGP 1ONSO
H j = 19°C
(16)
lilon (liTj = 19°C) = 2.13 A
(17)
The equations (15) (16) (17) show that the
thermal stability is very high even when the
devices are insulated and switching loss
unbalance is high (worst case).
The conditions studied in this paper were
carried out by mounting the paralleled devices
in the chopper circuit shown in fig.20.
Photo 8 shows the current balance
improvement when the heatsink temperature
increases (25°C - 100°C) and the devices are
working in the chopper circuit.
The fig.21 shows the output characteristics of
the paralleled devices and the estimated onstate cu rrent.
VI. IGBTS IN THE ISOTOP PACKAGE.
Fig. 20. Chopper circuit where paralleled IGBT
behaviour was checked.
I
100·C
IGBT2
25
j.
I
III :~I
-r;
~100·C
·c-f /1 '--25
ILL
rl
.11
--t, .
1/
·c
I
I
When the ISOTOP packages are paralleled,
they give the following advantages:
IGBTl
I
I
·nI c@100·C
To reduce parameter spread, the IGBTs dice
are mounted in the ISOTOP package with the
"die sister" technique; the thermal resistance
between the device junctions is reduced to a
minimum and the gates are connected in
parallel.
H-
The small and compact size of the package
(fig.22) and the low Rthjc value (0.5°C/W)
give a minimal thermal resistance between
the paralleled devices.
I
..
1//
Jd '/
VCEsat
Fig.21. Output characteristics of the devices in
fig. 20 and estimation of current balance
at Tj1 = Ti2 = 25°C and 100°C.
- This package was designed in order to
minimize emitter ground wiring effects; In
fact Isotop packages provide an auxiliary
emitter pin' which makes it simple to
separate the driving circuit from the power
circuit (fig.22,23).
Photo 9 & 10 show that unbalanced wiring
connections have very little effect on the
--------------------------~~~~~~~:9~
11/13
-------------------------735
APPLICAnON NOTE
15 Inrn
fZ
min
LOAD
Photo 9. Turn-on of two TSG50N50DV with
unbalanced emitter ground wiring.
le=25Ndiv. VGE=1 OV/div. t=200ns/div.
Fig. 22. Dimensions of the ISOTOP package and
schematic diagram showing an auxiliary
emitter pin.
Photo 10. Turn-off of two paralleled TSG50N50DV.
Ie = 25Ndiv. VeE = 100V/div.
VGE = 1Odiv. t = 1~s/div.
switching behaviour: the difference in length
of emitter ground connections is 15 cm.
It can be seen in photo 10 that there is no
peak voltage due to di/dt (V = L di/dt) on the
gate-emitter auxiliary pin during current rise.
Fig. 23. Paralleling ISOTOP.
12/13
---------------------------~~~~~~~~:~~ --------------------------736
APPLICATION NOTE
VII. CONCLUSIONS.
The performances in terms of current balance,
thermal stability and switching behaviour
when SGS- THOMSON IGBT devices are
paralleled, are very satisfactory.
The transfer characteristics has no real
influence on current balance in the on-state.
The on state current and the switching current
balance are ensured respectively by the low
spread of the V CEsat values and by the low
spread of device parameters.
High thermal stability is obtained by mounting
the paralleled devices on the same heatsink
even when the devices are insulated (mica,
insulated package).
For an optimum switching behaviour of
paralleled devices, it is necessary:
- small thermal resistance between the
junctions of paralleled devices; thus,
temperature difference between the junction
of the devices in parallel is reduced to a
minimal value.
- to drive the gates with only one gate
resistance.
[4] D-S KUO, MEMBER IEEE, J-Y CHOI, D.
GIANDOMENICO, C HU, SENIOR MEMBER,
S.P. SAPP, K.A. SASSAMAN and BREGAR.,
"Modelling the turn-off characteristics of the
bipolar-mos transistor", IEEE ELECTRON
DEVICE LETTERS, vol. EDL.6, N°5, MAY 1985.
- to balance the emitter-ground wiring.
When IGBTs are in the ISOTOP package, the.
wiring unbalance tolerance is high and the
thermal resistance (R thjh ) is low; thus,the
advantages of the ISOTOP package are:
- easy to design the lay-out when paralleling
IGBTs in ISOTOP.
REFERENCES.
[1] B. JAYANT BALlGA, "Temperature behaviour
of insulated gate transistor characteristics"; Solid
state electronics vol. 28 N° 3, pp 289-297,1985.
[2] M. MELITO - F. PORTUESE, "Gate charge
leads to easy drive design for POWER MOSFET
circuits", PCI June 1990.
[3] SEBOLD R. KORN, "Parallel operation of the
insulated gate transistor in switching
operations.", PCI June 1986.
[5] M. HIDESHIMA, T. KURAMOTO & A.
NAKAGAWA, "1000V 300A bipolar-mode
mosfet (IGBT) module", Proceedings of 1988
International Symposium
on Power
Semiconductor Devices, Tokyo, pp. 80·85.
13/13
- - - - - - - - - - - - - l . f i ~~~;m~~:~?!:~ ------------737
APPLICATION NOTE
HOW SHORT CIRCUIT CAPABILITIES GOVERN THE
DESIRED CHARACTERISTICS OF IGBTs
by C.G. Aniceto, R. Letor
ABSTRACT.
Short circuit tolerance of IGBTs can be
obtained by the optimization of both the
protection circuit and the intrinsic ruggedness
of devices.
This note discusses application design criteria
and IGBT characteristics compared to the
intrinsic short circuit ruggedness.
1.0 INTRODUCTION.
The continuous growth of IGBT applications
requires more differentiation of device
electrical characteristics. In fact, the structure
of IGBTs makes them flexible to use and their
AN478/0492
switching performance can be specifically
matched to many different applications.
For the best match between application
requirements and IGBT characteristics, some
compromise between the saturation voltage,
switching speed and ruggedness is
necessary.
To define the suitable IGBT short circuit
ruggedness specification, this note analyzes
the parameters influencing their behaviour
during short circuit operation, and verifies
the performance of the more usual short
circuit protection compared to IGBT short
1/9
739
APPLICATION NOTE
circuit ruggedness.
It is also shown that modification of the IGBT
structure improves the short circuit
performance without compromising the
saturation voltage and switching speed.
2.0. SHORT CIRCUIT OPERATION OF
IGBTs.
Static and dynamic characteristics are not
sufficient to predict the short circuit behaviour
of IGBTs. Also, dynamic phenomena
correlated to stray parameters and to the short
circuits circumstances must be. carefully
considered.
2.1 SHORT CIRCUIT MODES AND
WAVEFORMS.
Real short circuit mode can be simulated
using the test circuits "A" and "B" illustrated
respectively in figure 1 and figure 5.
TEST CIRCUIT "A": The device is turned on
when the collector is directly connected to
the supply voltage and the short circuit
inductance can be changed.This circuit
simulates either a short circuit in one leg
of a bridge circuit, or a permanent short
circuit of the load [4].
The waveforms of figure 2 show the behaviour
in the test circuit "A" when all the stray
parameters are reduced to a minimal value.
The effect of a significant short circuit
inductance is shown in figure 4. The
inductance, the reverse capacitance "C RS .'
the gate capacitance "C G", RG, together with
the IGBT amplification, constitute a resonant
R,L,C circuit as shown in figure 3. Hence
dildt at turn-on generates a very high peak
current due to a gate voltage overshoot.
TEST CIRCUIT "B": The short circuit is
actived during the on-state. In this case a
dVldt is applied to the collector when the
gate voltage is high and the device is in
full conduction. This condition simulates
accidental short circuit of the load during
normal operation [4].
liL~
'100 Idlv
I
M
.
.
I
-100 Idlv
\
'w
Fig.1.
2/9
Testcircuit"A"LsHORT~4I!H,LSTRAy~150nH.
'10 IdIv
'10 Idly
Fig. 2. Short circuit test with short circuit
inductance = LSTRAY' Time scale: 2jJsJdiv.
-------------------------~~~~~~~~:~~ ------------------------740
APPLICATION NOTE
I
'"ll/A'
_ ' ,i,
I
~. I .
l. IIc·10DA/dlv
'r.:~i~'--¥;~J-...+++.I~"=---~-;-,~,,-t:::.,
-l
-...j.r;"-+'-I
,
I ~ :GATE OVERSHOOT-r--
l/i
i~
Fig. 3. Simplified equivalent circuit of the short
circuit condition.
Vec
-
,
I I
-:
: I
-
'\
I
i
i
vIG- 10V/dl"
! I I
Fig. 4. Short circuit test with short circuit
inductance = LSHORT' Time scale = 2l1sJdiv.
dV/dtl
.
.~~~
.',
I lY+~ I
i
' V e , ~ laav dlv I
.I
I' (l'VPEAK
! , T I I
1- i
l
i II
I ..~
I
CURRENT
I
I
I
I
')
I T III
E
I ir- ~ :GAT~ OVERVOLTAC
I
I I 1\ I
V' 'I I
.~I I~V(dl~
!
I I I"-+-
..
I
; IC· 100Aldiv
Va·
Fig. 5. Test circuit "B". Short during saturation.
Fig. 6. Effect of the dVldt when the short circuit
occurs during IGBT full conduction.
t = 2lls/div.
The waveforms of figure 6 show the effect of
the dV/dt in the test circuit "8". The dV/dt
acting trough reverse capacitance causes the
gate voltage to rise over the driving voltage
[6]. A peak current much higher than short
circuit current is generated.
- Static latch isduetothe high current density.
- Dynamic latching is due to the high dV/dt
at turn-off.
The influence of the temperature is critical
because the latching current decreases when
temperature increases. Moreover, during
short circuit there is a very fast temperature
rise due to the very high energy increase
dissipated in the device.
For this, gate voltage overshoot must be
avoided and the short circuit currentmust be
reduced as much possible. In fact:
2.2 SHORT CIRCUIT STRESSES.
The failure of IG8Ts during short circuit
condition occurs either with static latch or with
dynamic latch of the parasitic SCR of the
structure (figure 14) [2]:
- - - - - - - - - - - - - L."
~~~r:~~::
3/9
------------741
APPLICATION NOTE
During overshoot, the collector current
(ic = gFS (v - V TH )) can reach the static
latching c~rrent, especially if the
transconductance of the device is high.
At turn-off the junction temperature is higher
than at turn-on, so the dV/dt due to the stray
inductance "Lsc" can cause a dynamic latchup.
Moreover, the stray inductance "Lsc" creates
an overvoltage at turn-off (see figures 2,4,6)
due to the dildt. If the dildt at turn-off is not
controlled by a suitable gate resistance the
overvoltage can rea.ch breakdown causing
device failure.
- Ls c ' LS E (Stray inductance of lay-out and
of capacitance)
2.3 PARAMETERS INFLUENCING SHORT
CIRCUIT BEHAVIOUR (figure 7).
2.4
The main parameters influencing static and
dynamic short circuit behaviour. are:
In order to make test conditions as
reproducible as possible, the short circuit
capability characterization was implemented
using test circuit "A"' with stray inductances
reduced to minimum value.
- Transconductance gFS' CG, CRS (Device
parameters)
- Driving voltage V D' RG (Driving circuit)
- LSSHORT' dV CE/dt, V CE (Short circuit
conditions)
The stray inductances LS E (emitter-ground)
and LS G (gate-drive) mainly influence di/dt at
turn-on, but they are not critical for usual circuit
lay-out and must be carefully considered, only
when devices are paralleled [8].
Transconductance gFS is the most critical
parameter. In fact, a high value of gFS can
generate very high continuous short circuit
current and very high peak current during
transient.
SHORT CIRCUIT
CHARACTERIZATION.
f
L',"~+ UC[[~:C ::'
~ Ls c
)c
[_~
RG
lSGI ~
~LJ~
1 "-~
(n') Vo
G
~;
MAXhJs)
lell NOM 12
10
8
6
4
4
2 Te.· . 125C .
l· l:.
Va
CAPABILITY
2
Vee· 2/3 BVe S
LS E
07
8
9
10
0
11
12
13
14
15
16
GATE VOLTAGE(V)
Fig. 7. Circuit parameters influencing short circuit
current of the IGBTs.
Fig. 8. Short circuit performance versus gate bias
of IGBTs having a high transconductance.
Maximum current overshoot ~ 20%
ISHORT CIRCUIT'
4/9
------------742
r== &CiS.THOMSON
~"'fl i'>l~«::mJ@rn~rn©1rmJ@oo~«::$
_ _ _ _ _ _ _ _ _ __
APPLICATION NOTE
'i
±
11\
II I !i
t
9
II
H
II
I!
Ff=r
~4i
~:
~
V REF
15V
U
*±
I
Ii
I
I II
I
Vr."
I
I
I
Ie
it
~
.
.
±
I
I
I
1/"··
-
Ii
+
Ii
T
i
~
~
I
I
Vn
delay 2
I
V~.n.
I
I
dolay 1
I
!
VIN
,
Fig. 9. Short circuit protection with high false alarm
immunity.
Fig; 10. Timing diagram of the protection circuit at
turn-on and during overcurrent condition.
Short circuit capability is expressed in terms
of:
- MAX SHORT CIRCUIT TIME (twas
defined in figure 2)
- SHORT CIRCUIT CURRENT & PEAK
CURRENT (ISHORT' IpEAK )
Versus: - VG' RG, T C' Vcc·
Figure 8 shows a characterization example
of a IGBT having a high value of the
transconductance. For V G ~ 13V the device
fails at turn-on due to static latch-up.
saturation voltage for sensing. Sensing
resistors or current transformers can also be
employed without significant changes.
The zener diode limits the gate voltage during
a short circuit condition so limiting short circuit
current.
Delay 1 and delay 2 realized with a R, C filter
and Schmitt trigger avoid activation of the
protection circuit in case of false short circuit
conditions. Delay 1 must filter transitory
phenomena at IGBT turn-on, delay 2 gives
noise immunity to the circuit.
The diode "02" clamps gate voltage
overshoots due to dV/dt.When a short circuit
is detected the IGBT is turned off by its gate
resistor in order to limit dV/dt and collector
overvoltages.
The timing diagram in figure 10 shows the
working mode of the circuit at turn-on and with
an overcurrent condition during operation:
3.0 SHORT CIRCUIT PROTECTION.
To ensure short circuit tolerance of a power
control system and of its output power
switches, the following problems must be
carefully considered:
1 - Limitation of the short circuit current.
2 - Limitation of short circuit protection delay.
3 - Nuisance tripping creating false alarm.
3.1 DESCRIPTION OF THE PROTECTION
CIRCUIT.
The figure 9 shows the schematic diagram
of a protection circuit using the IGBT
- At turn-on, the input 1 of the "AND" becomes
high (IN HIGH = 8V) after delay 1; If IGBT
saturation
was
not
detected
(INLOW = 2V) during delay 1 the driving
circuit input taken low.
5/9
------------- LW ~~~m~r::oo~~ ------------
743
APPLICATION NOTE
It
....J
It
,f ;-'
CEo IOGVI Iv
fl-
1/.
,~
II 'I
l
•
.
.- .
~-.----
J
VCE" OOYI Iv
n,.
~
V
V-- r-- t\
/'
\
Va
10V/ Iv
-
IC" OOAI Iv
IC" IOOAI Iv
4
--- -
_._\\
Va 10Vt v
Fig. 11. Short circuit protection waveforms in the
test condition "B". IGBT isTSG50N50DV.
Time scale: 211S/div.
Fig. 12. Short circuit waveforms without voltage
reduction of a IGBT having low
transconductance compared to waveforms
of figure 11 in dotted lines. t = 211S/div.
- When, during normal operation, there is a
overcurrent condition, the IGBT saturation
voltage reaches reference voltage "V REF"
and the comparator activate the zener and
the delay 2. If the overcurrent condition
continues after delay 2, then the driver
input is pulled down and the IGBT is
turned-off.
condition even if the protection works
correctly.
In fact the protection circuit needs a delay to
pull the gate voltage to a safe value. This delay
depends on the saturation voltage detection
time and on the discharge time of the IGBT
input capacitance. The discharge time can be
significant due to the Miller effect during
collector voltage rise. Moreover a high value
of gFS can induce a very sharp rise of the
current during delay.
To avoid this phenomenon, IGBTs with a
lower value of saturation current and
transconductance should be employed. In
fact, if the short circuit current is limited by the
device itself, then it is not necessary to reduce
the gate voltage during short circuit time.
Figure 12 shows collector current and gate
voltage waveforms of an IGBT having
low saturation current (ICsa! = 3 • I NOM
@ VG = 15V) subjected to the same short
circuit condition shown in figure 11 and without
any gate voltage reduction, compared to the
STGP50N50 with high transconductance and
gate voltage reduction during short circuit
(same waveforms of figure 11 in dotted lines).
This circuit works as a monostable
multivibrator with positive edge triggering, but
the IGBT is "ON" only if VIN is high, so the
noise immunity is assured. If a overcurrent or
a short circuit condition were detected, it is
necessary to take V IN to the low.
3.2 PERFORMANCE OF THE PROTECTION
CIRCUIT.
When the short circuit exists at turn-on (test
circuit "A"), test conditions of the
characterization are respected.
The performances of the circuit can be critical
when the short circuit occurs during normal
working conditions and the device is in full
saturation. Figure 11 shows that a significant
current overshoot stresses the IGBT
(STGP50N50) under this short circuit
6/9
--------------------------~~~~~~~:~~ --~---------------------744
APPLICATION NOTE
~~-
YYI
r uu
Gl\
uL ~M"
ITH GATE CLA MP_
II
.f'--,
~
/
I
.
IC" OOA dlv
-
'I
VG" tOV div
-- -
Fig. 13. Gate voltage and collector current with and
without gate voltage clamping. t = 2~s/div.
Fig. 14. Cross section of IGBT structure and
simplified equivalent circuit.
If the gate voltage reduction is eliminated a
fast clamping circuit is necessary. Figure 13
shows a comparison of the gate voltage and
collector current waveforms with and without
gate clamping voltage. This diode also limits
gate voltage overshoots in the short circuit
condition.
Parameters influencing transconductance and
lesal (lesal = gFS' (V G-VTH) saturation current
also affect saturation voltage "VeEsal" [2] as
shown by (1) and (2).
lesat
(1 )
=
3.3 SHORT CIRCUIT SPECIFICATION OF
IGBTs.
The criteria for providing short circuit
protection to match the reliability of the more
usual protection circuits are:
- tw> SIlS
(delay to avoid false allarm)
- lesal < 3 • INOM (to ensure safe turn-off)
- Tc = 12SoC
(working temperature)
SIlS is the time necessary to ensure full
saturation of IGBTs.
To give sufficient margin for safe operation
tw'" 1OilS.
4.0 DESIGN OF AN IGBT UNDER SHORT
CIRCUIT CONDITIONS
The intrinsic short circuit ruggedness of IGBTs
was improved by a optimization of the device
structure aimed at obtaining a suitable value
of the saturation current ("Iesal" @ V G=1SV,
Tj=1S0°C).
VCE = KT
q
In
r
l
+
(1-u pNp )dl c
1+
2qWRZDaniF(d/La)
(1 - upNp)Lele
(2)
IlnsCoxZ(V G-VTH)
Where "Le" is the channel lengh, "Z" is the
channel perimeter, "Cox" is the oxide
capacitance (Cox = £ S/tox )'
lesal can be limited both by reducing the gain
of the PNP transistor (uPNP) and by acting on
the MOSFET characteristics (Lc' Z, Cox),
"uPNP" influence both the PN junction
threshold (first term of equation (2)) and the
second term. For this reason only the
MOSFET characteristics were optimized, so
gaining advantages both in dynamic
performances (C G reduction) and in thermal
stability [8].
- - - - - - - - - - - - - I i ; i ~~~~m~r::I!~~
------------7/9
745
APPLICATION NOTE
PNP gain effect
MOS structure effect
4.5;...V~CE:.....:::sa::.t..!.(v~)_ _ _ _ _ _ _---.:I.:::C/-.:..I.:.:N~O~M·18
4
16
3.5
14
3
12
2.5
10
2
8
1.5
6
4
M
o
2
1
2
3
4
5
6
7
8
9
10 11 12 13
100
80
60
40
20
o~~~~~~_~-i_i-~_L-~
o
2
4
6
t WMAX(lls)
Fig. 15. Trade"ofi between saturation voltage and
the short circuit ruggedness expressed as
MAX tw and saturation current@V G = 15V.
To reduce the saturation current by 70%,
channel lengh (Lc) and oxide thickness "tox"
were increased by 40%. This gives the best
compromise between short circuit
performances and saturation voltage as figure
15 and 16 show.
The lefthand side of figure 15 shows the effect
of the PNP gain reduction due. to life time
reduction processes.
5.0 CONCLUSION.
The analysis of parameters influencing short
circuit operation of IGBTs has led to the
design of a suitable protection circuit, even
for devices having modest short circuit
performance.
This solution allows the use of IGBTs with very
low saturation voltage.
However, an additional very fast circuit that
reduces gate voltage .during short circuit is
necessary. During the delay of this circuit the
dV/dt due to the IGBT desaturation can cuase
a dangerous peak current. IGBTs having low
transconductance .can solve this problem.
Deacreasing transconductance of a IGBT
8/9
m
~
u
re
ffi
~
VCE(V)
Fig. 16. Comparison of two IGBT output
characteristics, with low lesat (ICsat= INOM)
and HIGH leSa! (10 • INOM) @ VG = 15V.
causes saturation voltage to increase. The
optimization of the IGBT structure allowed the
realization of an IGBT with sufficient short
circuit capability (t w MAX = 10 J.ls), and with
a value of VCEsat that is 20% higher than the
VCEsat of a IGBT having tw MAX = 1J.ls. This
IGBT requires a simplified short circuit
protection network and it does not
compromise the efficiency or the short circuit
ruggedness of the system.
REFERENCES.
[1] CELL GEOM ETRY ON IGBT LATCH UP.
H. Ylmaz, member IEEE
IEEE electron device letters, vol EDL-6,
N°8, August 1986
[2] 'MODERN POWER DEVICES
B.J. Baliga
A Wiley Inter.
[3] PROTECTING IGBTs AGAINST SHORT
CIRCUIT
G. Castino; I.A. corporation Italy
EPE journal, vol.1 n02, october 1991.
----------------L~I ~~~~~~~~
746
8
-----------------------
APPLICATION NOTE
[4] THE APPLICATION OF AN IGBT IN
POWER ELECTRONIC CIRCUIT.
M. Felovob, H. Amann, H. Stut, L. Lorenz,
SIEMENS AG.
PCIM91. Proceedings.
[5] A MODULAR GATE DRIVE FOR
INSULATED
GATE
BIPOLAR
TRANSISTORS.
Sujit K. Bismas, Biswarup Basak, Hanshik
S. Rajashekara
CJadavpour univ., Calcutta
IEEE lAS conf. 1991 proceedings.
[7] OPTIMUM DRIVING CIRCUIT FOR
IGBT DEVICES SUITABLE FOR
INTEGRATION.
C. Licitra, S. Musuneci, A. Raciti, A.
Galluzzo, R. Letor and M. Melito.
SGS-THOMSON & UNIVERSITA' DI
CATANIA.
ISPSD'92 proceedings:
[8] STATIC AND DYNAMIC BEHAVIOUR
OF PARALLELED IGBTs.
R. Letor
IEEE 1990 proceedings.
[6] SAFE BEHAVIOUR OF IGBTs
SUBMITIED TO A dV/dt.
R. Letor, M. Melito SGS-THOMSON
PCIM, 1990 proceedings.
- - - - - - - - - - - - LV ~~~~:~:::= ----'---------9/9
747
r=-= SGS-1HOMSON
l
II..,
[KIA]D©OO@rn[brn©'[]'OO@[K!]D©~
APPLICATION NOTE
SWITCHING WITH IGBTS:
HOW TO OBTAIN A BETTER PERFORMANCE
by A. Galluzzo, R. Letor, M. Melito
ABSTRACT
IGBTs are now being used in a variety of
switching applications due to their attractive
characteristics, particularly their current
density, ruggedness and gate driving circuit.
To exploit the best aspects of IGBTs it is
necessary to understand how their switching
performance can be controlled by the designer
and how much the voltage and current
waveforms can be shaped to obtain an
acceptable compromise in terms of switching
speed, ruggedness, power dissipation and
EMI.
AN479/0492
This paper, starting with voltage and current
waveform analysis, highlights both the device
and driving circuit characteristics which govern
the switching. It suggests, by using a simple
driving circuit, how to control both voltage and
current slopes, independently.
The influence of negative gate bias and driving
impedance versus dV/dt ruggedness are
analyzed.
Finally the IGBTs switching behaviour, when
connected in parallel, is examined.
1/10
749
APPLICATION NOTE
1 - ANALYSIS OF PARAMETERS WHICH
INFLUENCE SWITCHING WAVEFORMS
The switching behaviour of IGBTs is affected
by the unavoidable parasitic capacitance of
the structure. Moreover the turn-off losses are
strongly dependent on the characteristic of the
tailing effect on the collector current during
turn-off. Nevertheless switching losses can be
predicted and then limited to an acceptable
value, that is compatible with the need for safe
and noiseless switching. The main parameters
governing switching behaviour: gate bias,
driving impedance, stray inductances, gate
charge must also be taken into account.
Fig. 1 shows a schematic circuit wh~re the
parasitic inductances which influence
switching behaviour are highlighted.
In the following discussion it has been
assumed that the stray inductances are small
enough so that dl/dt » VcC/{Ls+Lc+Ld).
1.1 TURN-ON
When the freewheeling diode is conducting
during turn-on switching (fig. 2) , increased
losses occur in the diode if the dlldt in the IGBT
collector is increased. However the losses in
the IGBT decrease with increasing dl/dt in the
IGBT collector (fig. 3).
Reducing dl/dt leads to higher losses in the
power switch but it makes the reverse recQvery
behaviour ofthe freewheeling diode softer, thus
reducing EMI problems. Fig. 4 shows dlldt
versus ,Rg with Lsas'a parameter. Ls includes
both stray inductances due to package and
external inductances due to source grounding
layout. These inductances strongly influence
dlldt at turn-on because they act as negative
feedback to the gate thus reducing the effective
voltage applied to the device. This effect is
emphasized in fig. 5 where the collector and
gate current are shown.
2110
The gate voltage was set at 15 V to give a
low Vcesat and also because this value is
applied as a standard gate voltage ,when
various device characteristics are defined in
data sheets.
1.2 TURN-OFF
The IGBTs turn-off (fig. 6) can be divided into
three consecutive phases:
a) the gate voltage begins to decrease until it
reaches the value when the Miller effect
occurs;during this phase the collector
voltage increases slightly changing the
output characteristics with Ic=constant.
b) this phase is the Miller effect and the gate
voltage remains constant because of
modulation of the collector-gate
capacitance.
This is due to collector voltage rapidly
increasing to its maximum value.
c)the collector current begins to fall quickly (it
is related to the turn-off of the MOS part of
the IGBT structure) then it continues with
a "tail" which is due to recombination of
minority carriers in the substrate.
This tail, which causes the major losses, is
strongly related to technology and its effect
can not be mitigated by driving circuit.
After the collector current, collector voltage
and junction temperature has been
determined, turn-off losses can be controlled
only during phase b) varying dv/dt through Rg
while losses occurring. during phase c) are
slightly influenced by the driving circuit.
Increasing dV/dt decrease~ losses but it is
necessary to take care not to exceed the
RBSOA boundaries which also depend on
junction temperature, collector current and
collector voltage.
------------ LV ~~~~~:=
750
----------,.---
APPLICATION NOTE
, - -......--OVcc
I
Ld
~.
II
Lc
\
\
Ls
Fig. 1: Parasitic inductances influencing the
switching behaviour
2 Cross-Over Energy (mJ)
Fig. 2: Turn-on switching during freewheeling
diode conduction
200 dl/dt (AlIIII)
switch turn-on losses
/
1.5
1110
total losses
100
0.5
00
o~~=========~
100
150
200
250
50
dl/dt
1000
100
(AI~s)
Rg (ohm)
Fig. 3: Switching losses comparison
Fig. 4: Rg and Ls int.luence on dlJdt during turn-on
vir
MOSFET TURN-OFF
I\IS
1\ /J,
'-''"
.......
J \U\
I
-
I
J
""'-.. ' - \ '\ r.
'"
-"'.
,...
.....
~
......
Ie
Fig. 6: IGBTs turn-off
Fig. 5: Ic and Ig during turn-on
-------'----------'''I'
~~~~mgr::~~::
-------------3/10
751
APPLICATION NOTE
2 - HOW TO MANAGE DI/DT AND DV/DT
Useful information about switching behaviour
of IGBTs. can be obtained from the gate
charge curve. Even if the measuring
conditions are quite different from the
operating ones the total charge supplied to
gate during switching is the same. The
switching speed of a voltage driven device is
strictly related to the rate of supplying charge
to the gate input. This is true for IGBTs too,
except during the falling edge of the collector
current.
If we are able to control the rate of supplying
this charge, i.e. if we can manage the
amplitude of the gate current during switching
we can independently vary both the voltage
and the current slope.
2.2 TURN-ON
The driving circuit shown in fig. 7 allows dl/dt
to be varied through R1 but at the same time
this resistance fixes the collector voltage
slope. Increasing R1 leads to a lower dl/dt and
also to a lower dV/dt which increases turn-on
losses.
It would be useful to have a di/dt low enough
to reduce EMI problems and a dV/dt fast
enough to keep power losses to a minimum.
It is possible to achieve that using a driving
circuit which operates according to the
schematic shown in fig. 8.
The current slope is fixed by R1 and voltage
slope by R2 by turning 02 on after 01 with a
suitable delay. The waveforms in figures 9a
and 9b show the difference between the
standard circuit and the improved version.
2.3 TURN-OFF
The driving circuit can only control the slope
of the collector voltage (fig. 10) and only
slightly influences the fall of the collector
current which is responsible of the major
losses due to the tailed turn-off.
Figures 11, 12 and 13 show the effect of Vc,
Ic and Tj on the amplitude of the tail of the
collector current.
To minimize turn-off losses it is best to choose
a device whose characteristics matches better
the required operating conditions in terms of
Vc, Ic and Tj.
R1
;----4-----'
)~I
~
1
l
Fig. 7: Standard driving circuit
4/10
- - - - - - - - - - - - - L " 1 1 ~~~m~r::oo~~
752
Fig. 8: Improved driving circuit
----,-----------
APPLICATION NOTE
Fig. 9 a: Switching waveforms with standard
driving circuit
Fig.9 b: Switching waveforms with improved
driving circuit
STGP1ON50
3000
STGP10N50
dV/dt (V/IJS)
.
,
120 Itall %
2500
100
2000
80
1500 .......,...... .
Te. = 100°C
.......................... ....................
60
1000 .
,
Ie = 10 A
40·····················....···...... Rg·ii·100 .. ofirif
500
....................... ..... "Vge'=-15'V'
20
OL---~--~--~--------~--~
o
20
40
50
80
100
120
Rg (ohm)
o~---+----~----~---+--~
o
Fig. 10: Rg influence on dV/dt during turn·off
100
200
300
Vee (V)
500
Fig. 11: Itail versus collector voltage
STGP10N50
STGP10NSO
SO !tall/Ie %
120~1~=a~II~~~.--------------------~
1:::. . . . .
40· .... · .. ·~··
30
~
..... Rif·....roo ..O/1lif
40
10
20 ................................ Vge
10
16
20
Ie (A)
Fig. 12: Itail versus collector current
26
o
. . . :. .:.
Vee = 400 V
Ie = 10 A
60 ..
20
5
400
o
26
50
75
=15 V
.
100
126
TeI"C)
Fig. 13: Itail versus Tj
5/10
---------------------------~~~~~~~~:~~ --------------------------753
APPLICATION NOTE
3 - HOW TO AVOID DV/DT PROBLEMS
The spurious turn-on problem due to dV/dt is
typical of the circuit shown in fig. 14.
The free-wheeling diodes in parallel with each
IGBT are turned off during the opposite IGBT
turn-on generating a dV/dt whose value
depends on :
- opposite IGBT turn-on speed (dl/dt)
- free-wheeling diode "softness"
- wiring inductances
- gate bias and driving impedance
This applied dv/dt, acting through the
cOllector-gate capacitance (fig.15) causes the
gate voltage to rise turning the device on and
leading to additional losses. This undesired
effect is emphasized when temperature
increases because of temperature
dependence of Vth arid gfs.
It is possible to avoid this effect either
minimizing the dv/dt value or making the
device less sensitive to dV/dt by a driving
circuit specifically designed for this purpose
or combining the two techniques above
mentioned.
The first item requires using fast soft recovery
diodes, reducing wiring length and turning the
IGBTs on slowly. The second one requires the
driving impedance to be fixed at such low
value that the gate voltage can not exceed
the threshold voltage during dV/dt. The value
of this driving impedance depends on die-size
of the device: fig. 16 shows the Rge needed
to avoid spurious turn-on due to dv/dt.
Another way of avoiding spurious turn-on is
to bias the gate negatively. Fig. 17 shows the
different behaviour of gate voltage with and
without negative bias.
The lower peak of the gate voltage is due to
the different equivalent input capacitance
when the gate is negatively biased.
4 - PARALLELED IGBTS SWITCHING
BEHAVIOUR
The influence of the spread of parameters, of
drive circuit and lay-out unbalance was
investigated splitting the analysis as follows:
a) driving IGBTs with one gate resistance for
each device (fig. 18);
b) driving IGBTs with a common gate
resistance for all the devices (fig.19);
c) unbalancing emitter wire connection (fig. 20);
d) paralleling devices with the maximum
spread of the parameters.
The performed analysis pointed out that
voltage and collector current waveforms are
stable even in the worst case conditions which
occur when the gates are driven with a
common resistance and the wiring
inductances are strongly unbalanced.
In detail:
- IGBTs behaviour during turn-on is not very
different in a) or b) conditions (fig. 21 and fig.
22).
If the paralleled devices have different storage
times, driving the gates with one resistance
for each device has the drawback shown in
fig. 23: the collector current of the device
having the smaller storage time begins to fall
before the other one do.
Consequently, because of the inductive load,
the 2nd IGBT has to switch-off a collector
current greater than the other device thus
increasing storage current unbalance. Driving
the gates with only one gate resistance
minimizes this effect (fig. 24): the device with
the higher storage time holds the gate voltage
to "V th + Ic/gfs" until the fall time phase, so
equalizing the storage times.
- The effect of a poorly balanced emitter
connection is highlighted during the rising and
the falling edge of the collector current.
------------- LV ~~~~m~r::~~~ -----------6/10
754
APPLICATION NOTE
Fig. 25 shows the peak current unbalance,
during turn-on, when the condition c) occurs.
In the case shown ~Ls = 0.15iJ.H.
Fig. 26 and fig. 27 show the corresponding
effect during turn-off: wiring inductance
imbalance affects only the power-MOSFET
phase.
This behaviour creates negligible switching
losses imbalance compared with the total turnoff ones. The current unbalance just before
current fall affects the tail amplitude and it can
create significant imbalance in the switching
losses.
- IGBTs with the maximum spread in
parameter values were paralleled; the
comparison of current waveforms in fig. 21
and fig. 22 demonstrates that, during turn-on,
the influence of parameter spread is low (Ls
= 30 nH).
The spread of IGBTs parameters (gfs, Vth,
gate-charge) leads to different storage times
and causes current imbalance thus creating
switching losses imbalance.
Current imbalance due to the IGBTs
parameter spread can be calculated with the
equations (2) and (3).
The curve of fig. 28 shows the imbalance in
switching losses between two devices where
the Vth and gfs values are the limits of the
parameter spread.
Iload
= 11st + 12st = VGE
- it is possible to manage separately both the
current and the voltage slope except the
collector current tail;
- negative gate bias reduces spurious turn on
caused by dV/dt in bridge configurations;
- negative gate bias without Rg adjustment
reduces the RBSOA because of increased
dV/dt;
- common resistor on the gate of paralleled
devices improves switching losses balance;
- stray inductance on emitter connection
reduces switching speed and can causes
losses unbalance in paralleled devices;
Performance improvements obtained by
optimization of gate driving circuit involve cost
increases. It is task of the system deSigner to
define a good trade off between cost and
performances.
Vee
(gls1 + gls2) -
(gls1 Vth1 + gls2 Vth2)
Istorage
gate bias, dVIdt influence and effects of device
paralleling.
The following statements were explained:
= 115t - 12st = VGE
(2)
(gls1 - gls2) -
(glSl Vth1 - gls2 Vth2)
(3)
CONCLUSION
A careful analysis of circuit and device
parameters, influencing switching waveforms,
was carried out taking into account negative
Fig. 14: Typical circuit where dVfdt conduction can
occur
7/10
------------- !.V ~~~~m~r::G!~i:~ ------------755
APPLICATION NOTE
I· Ceg • dV/dt
~R~ge~(o~h~m~)____, -___________
1--
...J..
T,Ce g
W~
250,
C
Tj = 100 'c
200
I
...J..
_Cee
dV/dt
150
STGH2bN50
I
100
E
50
Rg
01
0
~=-=
4
6
8
dV / dt (KV /1.15)
Fig. 15: Current flow through IGBT capacitance due
to dV/dt
,----------0
dV~ d lH/+--+--+_I---I---I--l
I
V"f =
Vee
II
I~
2 V/div
I
Rgl
oj
Vd
SV
I
10
Fig. 16: Rge values that avoid dV/dt conduction
versus dV/dt
100 V/div
I
I
J
Rg2
2 V/div
Irt-
O)--------------~----*------o
Fig. 17: Comparison of gate voltage behaviour with
and without negative bias
Fig. 18: Driving with separate gate resistance
,-----_>-----0
Vee
Vee
Rg/2
Rg/2
o-------c=
Vd
o)--------------~----*------o
Fig. 19: Driving with one gate resistance
8/10
Vd
o
Fig. 20: Emitter grounding unbalance
-----------------------------~~~~~~~:~~~ ---------------------------756
APPLICATION NOTE
Fig. 21: Turn-on with separate gate drive (fig. 18)
of an STGH8N1 00. Ie = 2A1div
Fig. 22: Turn-on with one gate resistance (fig. 19)
of an STGH8N1 00. Ie = 2A1div
+
! 2•• 11
i
I
Fig. 23: Effect of separate gate drive on storage
current waveforms. Ie = 2A1div,
Vee = 200/div, V ge = 10/div
Fig. 24: Turn-off with one gate resistance.
Ie = 2A1div, Vee = 200/div, V g e = 1O/div
Fig. 25: Turn-on with unbalanced emitter-ground
connection (fig. 20). Ie = 2A1div
Fig. 26: Turn-off with unbalanced emitter-ground
connection (fig. 20). Ie = 2A1div
9/10
-------------- ~ ~~~;mg::i!~J: --------------
757
APPLICATION NOTE
IOPllis
~D&II
I
Col· .
.....•
9
...
.
I
7
r
....
---.--
....
. ... ....
2'.l
...
, S18.&
,
I
-(
l.,.
... ...
!
....
I'
0.3
I
0.25
.rJ
I
,.J..
.. '. ·1
r~ ~
~
.",!!!!!! .
.~
..
I
,
I
~
'~'
-,-
~
L
0
-',--'-
UZRI8
i-lll I
0.2 .
I
! .1
~
. ...
-~ !!!!!!
I
I
I
•
Fig. 27: Turn-off current waveforms with balanced
gate-emetter wiring (fig. 19). Ie = 2Ndiv
:--~~;O~lO
0.15 -0.1 -
~--:~:~i;~:~::~~ ~~--~~~
0.05
oL---~--
a
.C-
j--.----,---------- ---------
5
__
L -__~
L __ _~_ _ _ _
10
15
load Current (Al
20
25
Fig. 28: Switching losses unbalance
REFERENCES.
B. JA YANT BALlGA, "Temperatu re
behaviour of insulated gate transistor
characteristics". Solid state electronics vol.
28 W 3, pp 289-297,1985.
2 M. MELITO - F. PORTUESE, "Gate charge
leads to easy drive design for POWER
MOSFET circuits", PCIM June 1990.
3 SEBOLD R. KORN, "Parallel operation of
the insulated gate transistor in switching
operations.", PCIM June 1986.
4 D-S KUO, MEMBER IEEE, J-Y CHOI, D.
GIANDOMENICO, C HU, SENIOR
MEMBER, S.P. SAPP, K.A. SASSAMAN
and BREGAR, "Modelling the turn-off
characteristics of the bipolar-mos
transistor", IEEE ELECTRON DEVICE
LETIERS, vol. EDL.6, N° 5, May 1985.
5 M. HIDESHIMA, T. KURAMOTO & A.
NAKAGAWA, "1 OOOV 300A bipolar-mode
mosfet (IGBT) module", Proceedings of
1988 International Symposium on Power
Semiconductor Devices, Tokyo, pp. 80-85.
6 R. LETOR - M. MELITO, "Safe behaviour
of IGBTs subjected to dV/dt", PCIM June
1990.
7 R. LETOR, "Static and dynamic behaviour
of paralleled IGBTs", IEEE-lAS Annual
Meeting October 1990.
------------------------ !fi ~~~~~~r::oo~~ ---------------------1 0/1 0
758
APPLICATION NOTE
SERIES CONNECTION OF MOSFET,
BIPOLAR AND IGBT DEVICES
by R. Letor
ABSTRACT.
Fast power switches with voltage ratings much
higherthan those of single fast switching devices
can be made byconnecting BipolarTransistors,
Power MOSFET and IGBTs in series.
Problems
associated
with
device
characteristics such as balanced switching,
steady state and thermal behaviour must be
carefully considered when designing with such
switches.
This note deals with the series connection
behaviour analyzing both static and dynamic
characteristics of the devices.
Two philosopies for driving circuits are
AN480/0492
described and design criteria are given for
obtaining optimum performance.
1.0 INTRODUCTION.
Advantages of BIPOLAR TRANSISTORS,
Power MOSFETs and IGBTs reside in the
simplicity of the driving circuit and on their high
switching speed. But, applications of these
devices are limited to maximum reverse
voltage, generally up to 1000V - 1500V.
Higher voltage ratings would make these
devices unattractive due to problems related
to their structure.
1/11
759
APPLICATION NOTE
For example, theoretical ROS(on) of a Power
MOSFET increases with the square of the
voltage breakdown (ROS(on) = 5.93 E-9 *
(VDSMAX)2.5). Figure 1 showing the real
behaviour of SGS-THOMSON Power
MOSFETs versus breakdown voltage,
demonstrates that the current rating of three
BOOV Power MOSFETs in series will be higher
than a single 2000V Power MOSFET.
Moreover, the design of IGBTs and BIPOLAR
transistors with higher voltage ratings can be
difficult due to the rise time of the switching
waveform shown in figure 2.
Therefore, in some applications like battery
chargers, inverters for medium voltage lines
such as railway traction using frequencies up
to 20kHz or high resolution TV deflection with
operating frequencies of up to 64kHz, the
series connection of fast switching power
devices can be an interesting solution.
When connecting switching devices in series,
vQltage sharing during the off-state, and during
transient must be carefully considered.
In fact the spread of leakage current creates
unequal reverse voltage sharing. Delay
between commutation due to switching time
RDSon (ohm*cm2)
1~--~--~------~~--~'
b~-------T.---:r--------1
0.1
differences causes transient overvoltage.
If the parameters are temperature dependent,
junction temperature difference must also be
considered.
2.0 STEADY STATE VOLTAGE SHARING.
2.1 HOW TO BALANCE STEADY STATE
VOLTAGE SHARING.
Figure 4 illustrates how the difference in
blocking voltage characteristics results in
unequal state voltage and how a resistor
connected in parallel to each device (figure
3) equalizes the voltage sharing.
Equations 1 and 2 can be derived from the
graphical information in figure 4 and to
evaluate the value of R that reduces the
difference of blocking voltage to a fixed value
~VR with a fixed V M .
~VR12
VM
=
f---_ _ _ _~L-........
---'I...
DE"-'A=-L.,..CU___R~VE=------1
1.000E-Q4
L---~~-'--"~~~~.~~~_--'---'
3.5
100
2/11
~IR12
(1)
(2)
/
~
/
i
I
--I
/*
o
500
1000
1?OO
2000
BVCES (V)
ROS(on)
vs
Fig. 2. Storage time behaviour versus rated BV CES
for bipolar transistors.
-----------------------.L~I ~~~;~g~:~~
760
/
/
1
VDSmax (Volt)
Fig. 1. Ideal and real behaviour of
breakdown Voltage.
*
VR1 + VR2 + ... + V Rn
--
2.5
o
1000
= R1
STORAGE TIME (~s)
0.5
10
- V R2
Equation (1) assumes that the leakage current
is constant, this approximation is errs on the
side of caution and introduces a safety margin.
1.5
1.000E -03
= V R1
-----------------------
APPLICATION NOTE
V~h
~
yRn
1000 ;--IJA""---_ _ _ _ _ _ _ _ _ _--:-~ _ ___,
I
INVERSE CHAR ACT . .. R
R2
-V-RI
~~
BOO
600
400
-
INVERSE
CHARACTERISTICS
V1·V2 .. V3
R1
Vl
V2
1
Thousands V
2
VM
Fig. 3. Connection of sharing capacitors.
Fig. 4. Graphical calculation of sharing resistors
when V M and tN R are fixed.
If we suppose that device 1 has the lower I RM'
VR1 will be the maximum reverse voltage (V R1
= V RM ) and developing the equation (2):
The difference in junction temperature
depends on both differences of power
dissipation and on the thermal resistance
between devices.
VM = V RM + V RM - ~VR12 + ...
... + V RM - ~VR1n = n • V RM -l:~ ~VR1n-(3)
The worst case condition, when n devices are
connected in series, occurs when (n-1)
devices have maximum leakage current and
one device has the lowest possible leackage
current: ~IR1n = ~IRmax·
In this case, setting R1 = R2= ... = Rn' the
solution of the equations 1 and 2 gives:
R = (n • V RRM - V M) 1 (n-1) • ~IRmax' (4)
2.2 EVALUATION OF
-
= ~ (R th • POISSIPATION)
Experience shows that ~ Tj = 10°C is the
maximum value for insulated devices mounted
on the same heatsink.
Using the derating shown in figure 5, for
~Tj = 1Q°C:
~IRT
+ ~IRT' where:
~IRo
is the maximum leakage current
dispersion at a fixed V Rand Tj.
~IRT
is due to the difference between the
junction temperatures of each device (~Tj).
For devices today available ~IRo = 0.61RM
@ V R = V RRM and Tj = 1QO°C.
= 0.2 IRM.
Taking a safety margin we can use:
~IR
~IRmax.
~IRmax is the sum of ~IRo
-
~Tj
= 0.85 IRM.
2.3 EXAMPLE 1: series connection of three
STHV82 Power MOSFETs:
Ratings:
Voss = 800V
loss max = 1000J.1A @ Tj=125°C
ROS(on) max = 20 @ Tj=25°C
Rthj-case
= 1°C/W
------------- LV ~~~~mgr::il~J: ------------3111
761
APPLICATION NOTE
2.4 IS IT POSSIBLE TO ELIMINATE THE
Conditions:
Maximum blocking voltage: V M = 2000V
Maximum Current and duty cycle:
1M = 3A, tonlT = 0.5
Case temperature:
TCASE = BO°C
Switching frequency: 50KHz.
SHARING RESISTORS?
For high frequency operation, it is necessary
to consider the impedance of the output
capacitance of the device which is in parallel
with the sharing resistors.
In the previous example the impedance of the
STHVB2 output capacitance (150pF) is much
lower than the calculated value of the sharing
resistors:
Calculation of sharing resistor values.
Tj can be estimated using:
ROS(on) @ Tj = 100°C"" ROS(on)(25°C)
Tj
Tcase +
""
ROS(on)
*
ID2
*
*
1.7
Rthj-Case *
ton/T "" 100°C.
For T j = 100°C using the derating of figure
5:
IRM = (1 - 0.6)mA "" OAmA
V RM "" 0.9 Voss = 720V.
Using equation (4):
*
720 - 2000)/(2
*
0.4 E-3) = 200 kn.
Maximum power dissipation of each resistor
when ton=O: V2/R = 2.6 W.
10 ;;.::LE:ccAKc:cA=GE=-C:..:Uc.cRRc.::Ec..:.NT:....:(:::cmA"'-)_-c-'-_ _ _ _-:;o+--,
BIPOLAR TRANSiSTORS ........
0.001
""-_~~
m
~
_ _ ~_~_~_----L_~
w
w
_
w
~
_
JUNCTION TEMPERATURE (OC)
Fig.5. Leakage current versus junction temperature.
4/11
- - - - - - - - - - - - - I.."
762
200Kn
Therefore, if only high switching frequency
conditions are expected, then .the sharing
resistors can be omitted.
3.0 DRIVING
CIRCUIT FOR FAST
SWITCHING DEVICES IN SERIES.
Two philosophies for driving switching power
devices in series and for optimizing transient
voltage sharing can be developed:
For safety operation and reliability
R = (3
ZCoss = 1/21tfCoss "" 21 Kn «
1) Driving each device in series with
syncronized pulses and masking the
difference of switching time.
2) Equalizing switching times with an
optimized driving circuit.
Syncronized driving pulses can be generated
by a transformer and delay turn-off time
difference can be masked by snubber
capacitors.
When continuous mode and wide range of
duty cycle are required, it is difficult to design
a method for driving the transformer. In this
case auxiliary supplies and optocouplers can
be used.
Equalization of switching times and
continuous mode can be achieved using
capacitive coupling between outputcircuit and
driving circuit and diode network can be used
for continuous bias.
~~~~r::i!~::
-------------
APPLICATION NOTE
3.1 DRIVING CIRCUIT GENERATING
SYNCRONIZED
PULSES
TRANSFORMER COUPLING.
AND
It is possible to achieve excellent
synchronization of the driving pulses together
with good control of the driving voltage and
current.
Figure 6 shows a driving circuit for both
voltage and current controlled devices.
The coupling inductances between the
primary winding and every secondary must
be as balanced as possible in order to
equalize all the transfer impedances.
In both circuits the device driving current is
limited on the primary side of the transformer;
this feature reduces the difference in delay
turn-off time of devices in series.
In fact during delay turn-off time or storage:
(101
+ 102 )
= 10 •
n2"n 1
Input impedances of devices'" 0
(-I B1 '" -I B2 = 10 /2),
At the end of storage for bipolar transistors or
at the end of Miller effect for voltage controlled
devices (Power MOSFET, IGBT) the input
impedance becomes very high and the driving
current fall, when the faster device turns-off,
the device with the higher turn-off delay time
increases its switching speed because it is
driven by all the available current
(-IB(G) '" 10 ' n2"n 1))·
3.2 EQUALIZATION
OF TURN·OFF
DELAY TIMES USING CAPACITANCES.
In the circuit of fig ure 7, the capacitors transm it
driving voltage to the high side devices and the
diodes supply continuous gate voltage during
the on state. The circuit works as follows.
During transition: We suppose that initially
all Power MOSFETs are in the off state and
capacitor voltages are balanced. When the
positive edge is applied to drive circuit, P 1
turns-on and pulls down the source of P 2'
The capacitor network charges the gate of P 2'
P2 starts turn-on phase and pulls down source
of P3 etc ...
The turn-off phase is similar to the turn-on
phase. When P 1 turns-off, the source of P 2 is
pulled up. A negative voltage discharges the
gate of P2 into the capacitor network turning
,------r---() D
Vee
cr-r--1'i
=
P3
L
I
D
P2
D
P1
Rd
DRIVE
Fig. 6. Syncronized Drive of fast switching power
devices in series using a transformer.
o s
Fig. 7. Capacitors and diode network driving Power
MOSFETs connected in series.
------------------~~~~~~~::~n
-------------------------5/11
763
APPLICATION NOTE
P2 off, etc.
For a better voltage balance during switching,
the capacitor must be charged to the same
voltage (VC1=VC2=",=VC3); imbalance is due
to Power MOSFET gate charge and discharge
of the capacitors network. For this
fN max = (n-1) * Q GATE CHARGE / n * C
During on state:
VGATE(n) = VORIVE - (n-1) * (VOS(on)+VFdiode)
Therefore, for full saturation of every device
connected in series a driving voltage greater
than 15V is necessary.
Possible configurations. This circuit
configuration can be used for series
connection of IGBTs and BIPOLAR
TRANSISTORS.
When connecting IGBTs, sharing capacitors
are necessary because the tu rn-off current tail
of IGBTs does not depend onthe driving circuit.
DISADVANTAGES: The circuit is critical
when driving bipolar transistors due to high
drive energy.
It is difficult to optimize switching waveforms.
You can see in Photo 1 that current fall
waveforms are not correct.
The driving voltage necessary for full
saturation can be greater than the rated gate
voltage.
For better on-state and switching
performances, a regulator for each POWER
MOSFET gate must be introduced (Figure 8)
and optimization of the driving circuit will be
necessary.
EXAMPLE 2.
Photo 2 shows POWER MOSFET drain
voltage balance and drain current behaviour in
the ci rcu it of fig ure 7, where STH V 102 devices
are connected in series and in parallel.
C = 1500pF.
ADVANTAGES: Using POWER MOSFETs
this circuit allows optimum dynamic voltage
balance with low values of capacitors so
minimizing energy dissipation.
(VG = 15V) = 2 * 85nc = 170nc
fN = 170 E-9 /2* 1500 E-12 = 56.5V
Photo 1. Voltage sharing and drain current of two
Power MOSFETs in series as described
in the example 1.
I = 2Ndiv, V '" .500V/div.
Photo 2. Load current and voltage sharing
behaviour of two BUV46 in series as
shown in figure 5. Cs = 4.7nF,
Is =O.5A/div,I LOAD = 2A/div, V = 500V/div.
6/11
Q GATE CHARGE of 2 * STHV102 @
-------------------------~~~~~~~~::~------------------------764
APPLICATION NOTE
4.0 TRANSIENT VOLTAGE SHARING
WITH SYNCRONIZED DRIVING CIRCUIT.
The transition overvoltages due to the
difference between turn-off times can be
controlled using sharing capacitors as shown
in figure 9.
During switching operation, discharge of the
sharing capacitors generates power losses so
reducing efficiency of the converter.
In this note we define the losses of efficiency
due to the capacitors discharge as follows:
Balancing losses/handled power = n • 0.5 • C
• V2 • f/(V M • Ie • duty cycle}.
4.1 HOW TO CALCULATE SHARING
CAPACITORS.
Worst case condition occurs at turn-off with a
inductive load. When the faster device in
series turns-off, all the current load charges
the capacitance in parallel to the slower device
output·, and generates a fast voltage rise.
Using suitable capacitances it is possible to
retard the voltage rise and to fix ~V R as shown
in figure 9.
C
= ~Q/~VR =
f '(1 1(t} - 12(t}} dt 1 ~VR
t
(5)
t,
For n devices connected in series and
setting C 1 = C 2 = .... = Cn' ~t and ~I are
fixed to the maximum value.
4.2 SERIES OF BIPOLAR TRANSISTORS.
At turn-off the difference in storage time must
be considered. In fact, denaturation at the end
of the storage will cause collector voltage rise.
For bipolar transistors the spread of this
parameter, about 50%, is much higher than
the fall time. For this ~Q "" IOFF • ~tslorage and
the equation (5) becomes:
CMIN
= IOFF • ~tslorage 1 ~ V R max'
(6)
EXAMPLE 3:
Series connection of two BUV46AFI.
Ratings:
VCES = 1000V
1.SIlS < tSlorage < 2.5 Ils @ Ie = 2.5A;
IS1
= -IS2 = 0.5A,
Te
= 2SoC.
IC nom. = SA
161.1021--------.--, .
o S
Fig. 8. Driving circuit of figure 7for optimized driving
voltage and switch-off.
11
12
Fig. 9. Evaluation of sharing capacitors reducing
the effect of delay turn-off time spread.
- - - - - - - - - - - - - l . 1 j ~~~~m&~:U!~~
------------7/11
765
APPLICATION NOTE
Conditions:
Maximum turn-off clamping voltage:
V M = 1600V.
temperature independance of gate charge,
temperature difference between junction
devices can be disregarded:
- I5.tOFF = 5/100
IOFF max. = 3A.
Switching frequency:
15 KHz, duty cycle = 0.5
'B1 = -I B2 = 0.5A
Solution:
*
(typical value of t OFF )
If each POWER MOSFET has its own driving
resistor, then tolierance of resistors must be
considered and delay turn-off time can be
calculated as follows:
- tOFF = ta + tb =
For safety margin:
RGC GS In3 + 02 RG / (V Drive - GmI D)
VCEmax = 0.9
*
I5.V R max= 2
VCEmax - V M = 200V
*
VCES = 900V
Ratings:
Using equation (6):
C2 M1N = (3
*
EXAMPLE 4: Series of two STHV102.
1 E-6)/200 = 15nF.
The power dissipation due to discharge of
sharing capacitors is:
Balancing losses = PD = C * V2 * F = 144 W.
V DS = 1000V
Gate charge: 01 + 02 = 62 nc ± 5%
Conditions:
'G = 100 mAo
(Balancing losses/handled power %) =
Maximum clamping voltage:
PD / I * V max
V M = 1600V
*
0.5
*
% =6%
For better efficiency this energy must be
reduced. For this, it is necessary to limit the
maximum spread by a selection of devices.
If L'ltstorage = 300ns, then a 4.7 nF sharing
capacitor can be used as shown in photo 2.
IOFF = 3A
F = 15 KHz, duty cycle = 0.5
Solution:
For safety margin:
4.3 SERIES OF POWER MOSFETs.
VDSmax = 0.9
*
The current fali in POWER MOSFETs is very
fast; equation (5) becomes:
15. VR max = 2
V DSmax - V max = 200V
I5.V R = IOFF
*
I5.tOFF / C
tOFFmax can be calculated using gate charge,
as shown in figure 7:
- tOFF = (01 + 0d'GATE
If 'GATE is balanced for ali devices in series,
then I5.tOFF max can be calculated using the
distribution of figure 11; moreover, due to
8/11
*
V DS = 900V
I5.tOFF = 15. (01 + 02)/IG =
6.2 E - 9/ 100 E - 3 = 62ns.
C M1N = (3
*
62 E-9) / 200 = 930pF.(1000pF)
PD @ F=15 KHz = C V2
*
f = 9.6 W
(Balancing Losses/handled power) = 0.4 %
Photo 3 shows devices behaviour with the
conditions of the example and C = 1500pF.
- - - - - - - - - - - - - L..,/ ~~~;t!'~r::I!~l: ------------766
APPLICATION NOTE
4.4 SERIES OF IGBTs.
Photo 4 shows the behaviour of two 1000 V
IGBTs in series at turn-off using an inductive
load with sharing capacitors (1500pF). Due
to the high fall time value (figure 9), the total
voltage (V CE1 + V CE2) can reach the
clamping voltage before the end of current
fall.
Therefore, the equation (6) can not be
simplified and eN R must be split as follows:
~VR = ~VR1 + ~VR2
EXAMPLE 5:
Series of two IGBTs STGHBN100.
Ratings:
VCESmax = 1000 V
ICmax = BA @ Tc=125°C
tFALL = BOOns
± 20% @ Tc =125°C
(see figure 9)
Gate charge = 60 nc ± 5%
(similar to STHV102)
Conditions:
where:
~VR1
= V 1 - V2 @t=ta (photo 4) is due both,
to the delay turn-off time difference, and
to the difference of current tail during
voltage rise.
~ V R2 is due to the difference of sharing
capacitor charge when V 1 + V2 = VCLAMP
= constant"due to the difference of current
tail and ~tFALL: ~ V2 = ~02/2C
The minimum value of sharing capacitor can
not be calculated easily due to the influence
)f dV/dt on the current tail behaviour.
For easy evaluation, the charge time of the
,haring capacitor (ta - to) must be equal to the
llaximum t FALL . In this case:
C=2
*
(IOFF - ITAIL/2)
W R = ~VR1 = (~tOFF
*
*
tFALLmax
(JOFF - ITAIL /2))/C +
~ITAIL
*
tFALLma/2C
~tOFF
depending on gate charge spread is
temperature independent.
TAIL' ~ITAIL' tFALL are temperature dependent
as shown in figure 13.
VCLAMP = 1600 V
~VRmax = 200V
ICmax = B A
Tjmax = 125°C
IGATE = 100mA
f = 15Khz, duty cycle = 0.5
Solution:
C=2
*
(JOFF - ITAIL/2)
*
tFALLmax 1 VCLAMP = 7.B nF
~tOFF = ~ (01 + 02)/I G =
6.2 E - 91 100 E - 3 = 62ns.
~VR = ~VR1 = (~tOFF
~ITAIL
*
*
(JOFF - ITAIL /2))/C +
tFALLma/2C = 113 V
Resulting ~VR« 200 V, a 6.B nF capacitor
can be used and ~VR=130V.
Balancing losses =
PD (15KHz) = C
*
V2
*
f = 65W
(Balancing Losses/handled power) =
PD / Vmax * 1* 0.5 = 1 %.
- - - - - - - - - - - - 1,1."11 ~~~m~r::Ll!~~~
------------9/11
767
APPLICATION NOTE
Photo 3. Load current and voltage sharing of two
Power MOSFET STHV102 in series as
shown in figure 5. C s = 1.5nf,
L'.toff = 60ns, I = 2Ndiv, V = 500V/div.
iD-""
11
Photo 4. Turn-off behaviour of two IGBTs
STGH8N100 in series with syncronized
driving pulses. C = 1.5nF, T j = 100°C.
I =2a1div, ICHARGE=0.5Ndiv, V=200V/div.
59.60
*..
62.92
*********
**************
'" ***** '" '" *** *** '" ** '" '" ** ***
*** ***** *"''''>Ie'''",*",,,, '" **
*** '" **** '" ********* '" ********* '" '"
*** '" **** '" "'' '*' ' ' **** ****** **** '"
**** '" '" ** *'" '" ** '" ******* *"'* ** **
****************
**********
*******
*••
VDS
>Ie
66.24
TURN-OFF WITH SNUBBER
Fig. 10. Turn-off behaviour of Power MOSFET
>I<
*.*
Fig. 11. Spread
of
the Power MOSFET gate
charge.
when connecting snubber capacitors.
Tfall (nsec)
Itaillioff (%)
1000-·---
900~
800
f
700 1600
t
70
Tlall
1
500[
50
Itaillioll %
400,
. 30
300
200
Ie
100 - -
STGH8N100i
--L _ _ ""._l.~--------.L _ _ _~_ _~_ _~J
25
delay turn-off
t fall
Fig. 12. Current fall behaviour of IGBT devices.
50
100
125
10
150
Tc (C)
Vce' 800V , le'8A , Vg'15V , Rgo 1000hm
Fig. 13. tFALL and current tail of IGBTs vs junction
temperature.
768
75
APPLICATION NOTE
5.0 CONCLUSIONS.
Every switching power device can be
connected in series successfully in order to
make a power switch for fast switching
applications working at a voltage greater than
1500 V.
For optimum voltage sharing during steady
state and switching, it is necessary:
- to make a compromise with the additional
power losses introduced by sharing
capacitors and by sharing resistors.
- that the junction temperature difference
between devices in series must be as low
as possible; especially for bipolar transistors
and IGBTs.
Bipolar transistors require a selection by
storage time.
Power MOSFETs are temperature
independent and have very low parameter
spread, making them easy to connect in
series.
IGBTs need considerable sharing capacitors,
but these devices are attractive thanks to
their very low saturation voltage and low
driving energy.
The driving circuit can be made either by using
a trahformer for syncronized driving pulses,
or with a diode and capacitor network.
When using a transformer, driving voltage or
current can be controlled easily, but,
continuous mode and a wide range of duty
cycle can be a problem .
The diode and capacitor network allows
equalisation of devices turn-off time, so
reducing sharing capacitors value when gate
voltage controlled devices are used. This
method requires hard optimization of the
circuit for very fast switching applications.
- - - - - - - - - - - - - Jjfj ~~~;m~~~:~~~
------------11/11
769
APPLICATION NOTE
NOVEL PROTECTION AND GATE DRIVES FOR MOSFETs
USED IN DRIDGE-LEG CONFIGURATIONS
BY C. PATNI
INTRODUCTION
The bridge-leg is an important building block for
many applications such as drives and switch-mode
power supplies. Simple gate drives with protection
for POWER MOSFETs need to be designed for the
"low-side" and the "high-side" switches in the
bridge-leg. The POWER MOSFET can conduct a
peak drain current, ID, which is more than three
times its continuous current rating. The POWER
MOSFET peak current capability and its linear operating mode are used to good effect in designing device protection ci rcu itry.
Bridge-leg configurations have a direct bearing on
the degree of protection that can be incorporated.
Consequently, bridge-leg configurations, protection
concepts and gate drives are created simultaneously to design optimised and reliable power electronic
circuits.
Figure 1 : Bridge Configurations.
H.Y.D.C.
P
A
~O----~~UT
Do=±H.Y. GND
a) Bridge-leg using Internal Parasitic Diode.
H.V.D.L
H-BRIDGE USING POWER MOSFETs
Three POWER MOSFET based bridge configurations are illustrated in figure 1. Figure 1a illustrates
a bridge-leg which uses the internal parasitic diode
as a free-wheeling diode thus reducing cost. However, since the reverse recovery of this parasitic
diode is in the order of a microsecond, the turn-on
switching times of the POWER MOSFET have to be
increased in order to reduce the reverse recovery
current. The turn-on time of the POWER MOSFET
is controlled such that the pulse current rating of the
intemal diode is not exceeded. Hence a compromise is made between maintaining the safe
operating area of the MOSFET and reducing turnon switching losses. For example, an SGSP477
MOSFET has a diode pulse current rating in excess
of BOA and a typical diode reverse recovery time of
300ns. A rate of change of current at turn-on, limited
to 50Als, is a realistic compromise between reverse
recovery current magnitude and turn-on losses.
Consequently switching speed is sacrificed for cost.
For switching frequencies up to 10kHz, when operating on a 400V DC high voltage rail, this configuration can be chosen as switching losses are limited,
thus enabling a realistic thermal design.
AN351/0689
OUTPUT
Bo--j-_____..J>-j
H.V. GND
S(-0324
b) Asymetrical Bridge-leg providing dildt Protection.
H.V.D.C.
,.
Ao--l~
,.
Bo--l1
OUTPUT
~
H.V. GND
$(-0]25
b) Bridge-leg with blocking Diodes.
1/6
771
APPLICATION NOTE
The turn-off speed of the POWER MOSFET in this
configuration has no restrictions. Thus a fast turnoff is desirable to reduce turn-off losses. As the rate
of change of current is limited, radio frequency interference (RFI) and electromagnetic interference
(EMI) are reduced.
An asymmetrical bridge-leg, illustrated in figure 1b ;
can be used to limit dildt during a short-circuit condition thus providing sufficient time to switch-off the
appropriate power devices. The inductors limit the
rate of rise of output current. They also limit the freewheeling current through the internal parasitic
diodes of the MOSFETs. Adding external freewheel diodes and inductors increases reliability at
the cost of increased complexity. The inductors reduce RFI and EMI as the rate of change of current
is limited.
The configuration illustrated in figure 1c has Schottky "blocking" diodes to prevent current going
through the MOSFET internal parasitic diodes.
Schottky diodes are often used since conduction
losses are kept to a minimum.
Bridge configurations shown in figure 1band 1care
considered for high frequency switching applications. The advantage of the asymmetrical bridge-leg
configuration over the bridge configurations in
figures 1a and 1c is that the bridge-leg is capable of
withstanding simultaneous conduction of the two
devices in the bridge-leg since there are series inductors which reduce the dlldt under this condition.
Hence the short-circuit detection loop time is not so
critical and the devices are not stressed with high
dlldt and high pulse currents.
The choice of the bridge configuration depends on
the technical specification of the application. For
·example, if the technical specification for a specific
application can be met by using the configuration
shown in figure 1a, then this configuration should be
used as costs are lower than with the other two configurations shown in figures 1band 1c.
GATE DRIVE CIRCUITS
The POWER MOSFET is a voltage controlled device, unlike the bipolar transistor which requires a
continuous base drive. An application of a positive
voltage between the gate and the source results in
the device conducting a drain current. The gate to
source voltage sets up an electric field which modu-.
lates the drain to source resistance. The following
precautions should be considered when designing
the gate drive;
1 - Limit VGS to 20V maximum. Use of a gate to
source voltage in excess of 16V has a marked
effect on the lifetime of the device.
2/6
772
2 - Gate drive parasitic inductance can cause oscillations with the MOSFET input capacitance.
This problem becomes more pronounced when
connecting devices in parallel.
3 - There should be sufficient gate to source voltage
for the transistor to be fully conducting.
Figure 2 : Gate Drive Circuits.
a) Isolated gate drive with controllable switching
times.
5(-0328
b) Simple gate drive for N-Channel MOSFETs in pa~
rallel.
.12V
c) Gate drive with VDS (on) control for short-circuit
protection.
+12V
APPLICATION NOTE
Bipolar, MOSFET, CMOS or open-collector TTL
logic can be used in the design of simple high performance gate drives. Totem-pole buffers, (figure
2a), are often effectively used to control the turn-on
and turn-off individually. Figure 2b illustrates a total
MOSFET based gate drive with which the switching
speeds at turn-off can be individually controlled.
CMOS or open-collector TTL logic can be used to
drive MOSFETs directly, provided an ultrafast
switching speed ( 50ns) is not necessary. In motor
drive applications switching speeds of 100 to 200
nanoseconds are sufficient as switching frequency
is seldom in excess of 50kHz. Discrete buffers are
used to provide high current source and sinking capability when improved switching speeds are required or when MOSFETs are connected in parallel.
Short-circuit protection techniques similar to bipolar
transistors may be considered for MOSFETs.
VDS(on) monitoring permits the detection of short-circuit conditions which lead to device failure. The device can be switched off before the drain current
reaches a value in excess of the peak pulse current
capability of the MOSFET. This form of protection is
very effective with MOSFETs as they can sustain a
pulse current in excess of three times the nominal
continuous current. Figure 2c illustrates a gate drive
which incorporates VDS(on) monitoring and linear
operating mode detection for the MOSFET in the
case of short-circuit conditions. When the MOSFET
is tu med on the on-state voltage of the device
(VDS(on)) is compared with a fixed reference Voltage.
At turn-on, VDS(on) monitoring is inhibited for a period of approximately 400ns in order to allow the
MOSFET to tum-on fully. After this period, if VDS(on)
becomes greater than the reference value, the device is latched-off until the control signal is turnedoff and turned-on again.
"HIGH-SIDE" SWITCH GATE DRIVES
The top transistor in a bridge-leg requires a "highside" gate drive circuit with respect to the bridge
ground. Three possible gate drive concepts are
shown in figure 3 :
Figure 3 ; Gate Drives for Top Transistor of Inverter Leg.
a) "Bootstrap" supply floating gate drive.
H.v.D.C.
BOOT-STRA'PPr~:::~~==~-rSUPPLY -
lOGIC
SIGNAL
5(·0329
b) Level shifting gate drive.
H:V.D.C. .12V
H.V.D.C.
~E'"'-'T
)_'M~ I,
)
~
lOGlWl
SIGNAL
SC-0330
c) Floating supply isolated gate drive.
H.V.D.C.
ISOlATE;-rGATE
DRIVE
lOGIC
SIGNAL
5(·0331
a) The "bootstrap" drive, requiring logic signal isolation, but no auxiliary floating supply.
b) The level shifting drive.
c) The floating gate drive with optically coupled isolators, pulse transformers or DC to DC chopper
circuit with transformer isolation.
Bootstrap supplies are particularly well suited to
POWER MOSFET gate drives which require low
power consumption. Figure 4 illustrates two bootstrap supply techniques. Bootstrap supplies limit
transistor duty cycle since they require a minimum
transistor off time during which they are refreshed.
3/6
773
APPLICATION NOTE
Supply efficiency and maximum duty-cycle are parameters which govern the design of the bootstrap.
Figure 4a illustrates a conventional bootstrap with
an additional capacitor, C1, which improves the
maximum duty cycle as the supply is refreshed even
during transistor on time by this capacitor. Figure 4b
illustrates a high efficiency bootstrap supply which
uses a small MOSFET, 01 , for regulation. In this design a low power bootstrap drives the gate of 01 .
Figure 4 : Bootstrap Supply Techniques.
a) Conventional bootstrap with additional capacitor
C1.
H.Y. O.c.
The level shifting gate drive, (figure 3b), requires a
high voltage p-channel MOSFET which drives the
n-channel power device. The p-channel MOSFET
is switched using a resistor divider network. No floating supplies are required. A power supply of 12V,
referenced to the high voltage d.c., is used to provide positive gate source voltage. for n-channel
POWER MOSFET. This circuit eliminates the need
for logic signal isolation and a floating supply. The
disadvantage of this circuit is the high cost of the pchannel drive MOSFET.
BOOTSTRAP
SUPPLY
S(-0331 11
b) High efficiency bootstrap.
H.V.D.C.
Figure 3c illustrates a floating gate drive with a floating supply. This drive is the most expensive out of
the three shown in figure 3. However, the floating
supply need only have a low output power, since
MOSFETs are voltage controlled devices. The advantages of this drive are its high efficiency and unrestricted transistor duty-cycle.
S(-03l3/1
Figure 5 : Isolated CMOS Drive with Vos Control for Short-circuit Protection .
• 12V
S[-0331./1
R1
= Dependent
R2
R3
=
=
4/6
774
on application
10kD
22kD
R4
R5
R6
IC1
=
=
=
=
1kD
120kD
56kD
HCF4093
IC2
C1
Dt
02
=
=
=
=
HCPL2200
560pF
1 N41448
BYT11/600
01
02
= BSS100
= SGSP477
APPLICATION NOTE
Figure 6 : Short-circuit Conditions for an SGSP477
VDS & ID.
VDS: 50V/OIV
ID: 10A/OIV
t : 2f.ls/OIV
a) Output to high voltage short-circuit.
·m,o
Short-circuit protection of a power MOSFET can be
achieved by either VDS(on) monitoring or a current
sense. In the previous section gate drives using the
VDS(on) monitoring technique were presented.
Figure 6 illustrates the MOSFET drain to source voltage, VDS, and the drain current, ID, when short-circuits are experienced by the POWER MOSFET,
SGSP477, driven by the gate drive illustrated in
figure 5.
The MOSFET is turned-off when the drain current
increases sufficiently and VDS(on) monitoring is inhibited for a period of 400ns to allow the device to
turn-on fully.
,...,..
l'--t-- t--
I
Il
t"-
- - - -..... 1
b) Outpulto Output Short-circuit.
5 -G]I.1
.
I--
An inductor is used in series with the device, as illustrated in figure 1b. This inductor saturates when
a large short-circuit current flows. The rate of
change of the short-circuit current due to the saturation of this inductor is illustrated in figure 6a and
6b. Figure 6a illustrates the POWER MOSFET drain
to source voltage, VDS, and the drain current, ID,
when a bridge-leg output to high voltage supply rail
short-circuit occurs. Figure 6b illustrates an output
to output short-circuit of two bridge-legs.
Another protection technique uses the "current mirror concept", (1). An image of drain current is obtained by having a small MOSFET, (integral or
discrete), in parallel with the main power MOSFET
as illustrated in figure 7.
Figure 7 : The Current Mirror.
o/"
V
/
/
r--.. r-....
~
t-
b
I::;
----_.t
PROTECTION
Power electronic circuits such as bridge-legs are
often required to have protection against output to
output short-circuit, over-temperature, simultaneous conduction of devices in series in a bridgeleg and output to high voltage supply or ground rail
short-circuit. These power stages are generally part
of an expensive system such as a machine-tool or
a robot motor drive. Thus the additional cost of protection circuitry is commercially acceptable. A compromise is generally reached between equjpment
costs and the degree of protection required.
T
N1 ~E
N» 1000
~o
IIR
f
Voltage proportional
to drain current
ViO
S(·0335
Figure 8 illustrates a floating gate drive which utilizes
a pulse transformer for transmitting simultaneously
the MOSFET on-signal together .and the gate to
source capacitance charging current. The current
mirror technique is used to provide short-circuit and
over-load current protection. The pulse transformer
operates at an oscillating frequency of 1MHz when
a turn-on control signal is present.
5/6
775
APPLICATION NOTE
The secondary is rectified to provide the gate source
capacitance charging. voltage. The current mirror
provides a voltage "image" of the main MOSFET
drain current. This voltage is compared with a fixed
reference voltage in order that the gate drive be
latched-off when the drain current becomes in excess of a specificed value. Figure 9 illustrates how
the MOSFET, SGSP477, is latched-off when the
drain current exceeds 10A with this gate drive circuit.
Figure 8 : Pulse Transformer Gate Drive with Current Mirror Protection for an SGSP477 .
. L.l
. ON
R1
R2
R3
R4
R5
R6
R7
R8
=
=
=
=
=
=
=
=
470Q
1kQ
33Q
2kQ
100Q
100Q
100Q
100Q
R9
C1
C2
C3
C4
01
02
03
=100Q
= 330pF
= 10nF
= 10nF
= 220pF
= 1N4148
= 1N4148
= 1N4148
Figure 9: Overload Current Protection using Current Mirror Concept with the Gate Drive
of Figure 8 for an SGSP477.
S( 0)42
-,
(
(ontro'l
sign;a\
o
-
V
i.--"
• t
Timescale: 5/ls1D1V -ID : 5NOIV - VDS : 100V/0IV
Control signal: 5V/0IV - VGS : 5V/01V.
6/6
776
04
05
06
07
08
= 1N4148
= 1N4148
= 1 N4148
= BZX85C15
= BZX85C15V
01 = {
02 =
03 =
small
signal
n-channel
MOSFETs
04
05
06
Q7
08
09
010
011
=SGS477
= BC337
= BC327
= BC337
= BC327
= BC337
= BC327
=BC337
CONCLUSION
MOSFET based bridge-leg configurations requiring
protection and floating gate drives have been
presented. Novel self-protecting gate drives for the
"high-side" and "low-side" switching have been discussed. These drives provide protection against output to high voltage d.c., output to ground and output
short-circuit. For the high-side switch "bootstrap"
supply gate drive, level shifting gate drive and floating supply isolated gate drives have been compared.
Protection against short-circuit condition has been
demonstrated using VDS(on) monitoring and the current mirror concept. Both techniques are well suited
for protection against short-circuit conditions. However, the current mirror concept also provides a sufficiently linear image of the current for regulation.
REFERENCES:
1. Fuy G.
Current-mirror FETs cut costs and sensing losses
EON September 4 th, 1986.
APPLICATION NOTE
USE OF INTERNAL MOSFET DIODE IN BRIDGE-LEGS
FOR HIGH FREQUENCY APPLICATIONS
By C.K. PATANI - D. STEED - J.M. CHARRETON
ABSTRACT
Reverse recovery of the intrinsic MOSFET diodes
is investigated for the classical MOSFET and the
MOSFET with minority carrier lifetime control. Turnon losses in bridge-legs using intrinsic MOSFET
diodes limit the switching frequency particularly in
the case of the classical MOSFET. Adapted bridgeleg configurations are presented which enable the
use of the intrinsic MOSFET diodes for the free
wheeling function in inductive load switching without any appreciable reverse recovery current and
MOSFET turn-on switching losses!
INTRODUCTION
The MOS field effect transistor (MOSFET) contains
an intrinsic PN diode within the structure which can
conduct a current from source to drain. The PN junction diode is in fact part of a parasitic NPN bipolar
transistor as shown in figure 1. Free-wheeling
diodes in bridge-legs are necessary when switching
inductive loads. The intrinsic diode can be used .to
fulfil this free-wheeling function. However, the intrinsic diode of the classical MOSFET has a long
reverse recovery time and "snap-off" characteristic
which can cause large dV/dt. The snap-off can result in the device failing in one of two ways. Firstly,
due to internal capacitances, Cdb and Cbe, a base
current may be established which turns-on the intrinsic bipolar transistor (see figure 1)1. Secondly,
the dV/dt may be such that the drain to source voltage of the MOSFET exceeds the blocking voltage
thus causing avalanche breakdown. This paper investigates various means of limiting the maximum
reverse recovery current of the intrinsic diode to ensure reliable operation. A comparison is made between the novel solutions presented permitting the
use of internal diode, and conventional solutions for
using MOSFETs in bridge-legs, such as lifetime
controlled MOSFETs and series blocking diodes.
Figure 1 : Equivalent Circuit for a MOS Field Effect Transistor (MOSFET).
Drain
Intrinsic NPN
transistor
AN356/0689
1/10
777
APPLICATION NOTE
METHODS OF LIMITING REVERSE
COVERY CURRENT
RE-
Limiting the reverse recovery current of the intrinsic
diode can be achieved by stopping current from passing through the blocked MOSFET by means of a
series blocking diode or limiting the rate of change
of current in the intrinsic diode. The snap-off characteristics of the internal diode can be limited by
having small RC snubbers across the drain to
source of MOSFETS in bridge-leg configuration.
Solutions which limit the rate of change of current in
the intrinsic diode are discussed below.
BRIDGE-LEG DESIGNS UTILIZING MOSFET INTRINSIC DIODES
a) SOLUTION WITH UNCOUPLED UNSATURABLE INDUCTORS
In the circuit shown in figure 2, if T1 is blocked and
T2 is conducting, the load current flows through T2.
As T2 turns-off the current transfers to the freewheeling diode D2, as the rate of change of current
into the intrinsic MOSFET diode of T1 is limited by
inductors L1 and L2. The zener voltage across Z2
causes the current to transfer from the external
freewheeling diode D2 to the intrinsic MOSFET
diode in T1until D2 no longer conducts (as shown
in figure 3). When T2 is turned-on subsequently the
current transfers from the intrinsic diode of T1 to T2.
The reverse recovery of the intrinsic diode is, however, lirnited by inductances L1 and L2. This can be
seen clearly in figure 4. The bridge-leg can be designed (by dimensioning L1, L2 and Vz) such that
the external freewheeling and zener or transil diodes
only conduct for a small fraction of the freewheeling
period. Consequently, they do not have to be
mounted on a heatsink. The disadvantage of using
the zener is that the MOSFETs must now be rated
for at least the high voltage DC rail HVDC, plus the
zener voltage.
'
Figure 2 : Bridge-leg with Uncoupled Unsaturable Inductors.
HVDC
SGSP477
Z2
RZW5018
Transi
I
02 BYW98 200
L1
7ull
Transi I
BYW5018
Inductive load
Z1
1-
BYW98 200
L2
7ull
D1
~
SGSP477
HVGNO
2/10
778
load
APPLICATION NOTE
Figure 3 : Transfer of Current to Intrinsic Diode.
[t'"
Time scale: 211S/DIV
Vos : SOV/DIV
10: 10AlDIV
::
Intrinsic
Diode: 10AIDIV
Current (110)
./
V
V
V
MOSFET : SGSP477
Figure 4 : Turn-off of the Intrinsic Diode.
h
/
"-
/
1/
Time scale: 1llS/DIV
Vos : SOV/DIV
10: 10A/DIV
Intrinsic
Diode: 10A/DIV
Current (110)
\
\
I.
I-!
Another advantage of inductances L 1 and L2 in the
circuit is that they limit the build up of current during
fault conditions such as simultaneous conduction of
the two devices.
L 1 and L2 must be chosen such that their inductances are big enough to prevent intrinsic diode reverse
recovery problems hence reduce losses. They must
be small enough to allow current to transfer from the
freewheeling diodes D2 and D1 to the intrinsic MOSFET diodes in T1 and T2 such that the average current passing through the external diode and zener
or transil is low.
MOSFET : SGSP477
inductance between transistors T1 and T2
(SGSP477), thus reducing the reverse recovery
problem of the intrinsic diode as the rate of change
of current is reduced. Coupling, therefore, saves the
cost of one core and less windings are necessary to
provide the same degree of protection as in the case
of uncoupled inductors. The voltage and current
waveforms of the MOSFETs and their intrinsic
diodes for this solution are similar to that obtained
with solution (a).
b) SOLUTION WITH MUTUALLY COUPLED INDUCTORS
Inductors L 1 and L2 can be mutually coupled as
shown in figure 5. Coupling L 1 and L2 doubles the
3/10
779
APPLICATION NOTE
Figure 5 : Bridge-leg with Mutual Inductors.
HVDe
D2
•
L1
Inductive
load
Transil
Z2
L2
~
-
L oad
Z1
Transil
D1
HVGND
C) SOLUTION WITH SATURABLE INDUCTORS
Saturable inductors such as toroids with a few turns
can be used in the bridge configuration shown in
figure 6. Saturable inductors are better suited than
non-saturable inductors in so much as they can be
used to limit the reverse recovery of the intrinsic
diode to an almost negligible level. The saturable inductor is designed to saturate after the intrinsic
diode has reverse recovered. Before saturation the
inductor presents a high impedance and only a low
magnetising current flows.
In figure 6, it is assumed that T1 and T2 are blocked
and the intrinsic diode of T1 is conducting. If T2 is
now turned-on, the current in the intrinsic diode decreases rapidly since inductor L 1 is saturated until
this current reverses resulting in negative volts-seconds across the inductor which thus desaturates.
The inductor thus presents a high impedance while
the current through it is equal to or less than the
magnetising current. The intrinsic MOSFET diode
4/10
780
begins to reverse recover as the current through it
becomes negative. The inductor is designed not to
saturate for a period of at least 1~s, thus enabling
the reverse recovery of the intrinsic diode without
excessive reverse recovery current. There is a certain degree of minority carrier recombination while
the inductor is unsaturated which also reduces the
maximum reverse recovery current, IRM. The
reverse recovery of the intrinsic diode can be seen
in figure 7.
While T2 is conducting the load current inductor L2
is saturated. When T2 turns-off the MOSFET current transfers to diode D2. The free-wheeling current path through the intrinsic diode of T1 has a high
impedance due to L 1 being unsaturated. Consequently the build-up of current through the intrinsic
diode of T1 is slow until this current reaches a value
equal to the magnetising current, Imag, of inductor
L1 which then saturates. This effect can be clearly
seen in figu re 8.
APPLICATION NOTE
Figure 6 : Bridge-leg with Saturable Inductors.
HVOC
02
Z2
L __ ......_ _ _ _
~
HVGNO
The turn-on of the MOSFET in the solution with saturable inductors (shown in figure 6) is illustrated in
figure 9. It can be seen that the MOSFET losses are
negligible, since the saturable inductor in series with
the MOSFET that turns-on, limits the rate of rise of
current while it is unsaturated. Figure 9 also illustrates that the reverse recovery of the intrinsic diode
of the free wheeling MOSFET is also limited ..
In the bridge-leg with saturable inductors (figure 6),
if transils (Z1 and Z2) and resistors (R1 and R2) are
removed, the external free-wheeling diodes have to
be of high current rating as they conduct all the load
current until the saturation of L 1 and L2. Subsequently the external diode shares part of the freewheeling current with the intrinsic diode. It is
advantageous to reduce the current through the external free-wheel diodes 01 and 02 as rapidly as
possible for the following reasons:
1. If 01 and 02 conduct for a small fraction of the
maximum free-wheeling duty cycle, then their
power rating is substantially reduced.
2. If the free wheeling current through the external
diode 01 orD2 is reduced rapidly, the inductor in
series (L 1 or L2) is no longer saturated. At the
consecutive turn-on of T1, L 1 presents a high impedance thus performing a turn-on snubber function. Transistor turn-on losses are thus minimised
particularly for inductive loads.
3. Output short-circuit protection is also enhanced if
the inductors are unsaturated prior to transistor
turn-on.
The current through the external free-wheeling
diodes can be reduced rapidly by increasing the rate
of release of inductor stored energy by transils (Z1
and Z2) and/or resistors (R1 and R2) as shown in
figure 6.
5/10
781
APPLICATION NOTE
Figure 7 : Reverse Recovery of Intrinsic Diode using Saturable Inductors in the Configuration of Figure 6.
,
~
Time scale: 500ns/DIV
"
Intrinsic
Diode Current
liD: 10AlDIV
~
-
Voltage across
MOSFET intrinsic
diode
VID: 50V/DIV
j
"/
Time scale: 500ns/DIV
Figure 8 : Transfer of Current to Intrinsic Diode using Saturable Inductors in the Configuration of Figure 6.
~
VDS : 50V/DIV
ID: 5A1DIV
J
)
h
-
H+
/'
\
/
./
Intrinsic
Diode: 5A1DIV
Current (liD)
MOSFET : SGSP477
Figure 9: Turn-on of the MOSFET in the Configuration with Saturable Inductors.
(The turn-on snubber and the intrinsic diode reverse recovery actions are illustrated).
Time scale: 500ns/DIV
VDS : 50V/DIV
ID: 10AlDIV
\.
:H++
/'" r-
~
V
"
6/10
7.82
t-'
Intrinsic
Diode: 10A/DIV
Current (liD)
MOSFET : SGSP477 .
APPLICATION NOTE
Table 1 : Advantages and Disadvantages of Solutions for limiting Reverse Recovery Current in the
Intrinsic MOSFET Diode.
Sol.
Type of Protection Used
Advantages
Disadvantages
a)
Unsaturable Inductors
- Reduction of turn-on losses.
- Controlled dlldt at turn-on.
- Controlled reverse recovery of
intrinsic diode.
- In order to use low current rated
freewheeling diodes, transi!
diodes have to be used .
increasing the voltage rating of
the MOSFETs in the circuit.
b)
Unsaturable Mutual Inductances
- Smaller and less expensive than
two inductors since only one
coupled inductor.
- As above.
- As above.
c)
Saturable Inductors
- Negligible turn-on losses.
- Negligible intrinsic MOSFET
diode reverse recovery losses.
- Controlled dlldt turn-on.
- As above.
COMPARISON OF USE OF INTRINSIC MOSFET DIODE WITH ALTERNATIVE SOLUTION
Figure 10 illustrates three bridge-leg configurations
that can be used with MOSFETs when switching inductive loads. Figure 10a) illustrates a bridge-leg
which uses the intrinsic diode of a classical MOSFET having a reverse recovery in the order of a
microsecond. The same configuration can be used
with a lifetime controlled MOSFET which has an intrinsic diode having a reverse recovery time around
250ns. An asymmetrical bridge-leg illustrated in
figure 10b), is similar to the above mentioned solutions permitting the use of the intrinsic diode. The
configuration illustrated in figure 10c) has series
"blocking" diodes which prevent conduction of the
intrinsic MOSFET diodes and thus avoid reverse recovery problems associated with the slow intrinsic
diodes. In this configuration fast recovery epitaxial
diodes are used as external free wheeling diodes.
Tests were performed using 500V, 0.6 ohm at 25°C
classical MOSFETs (BUZ353) and lifetime controlled MOSFETs in the bridge-leg illustrated in
figure 1Oa). Experimentally obtained losses within
the diode and the MOSFET at turn-on are presented
in figure 11. The solution enabling the use of the intrinsic diode without reverse recovery problems
(figure 1Ob) has practically no losses due to reverse
recovery of the intrinsic diode.
Figure 10: Bridge-leg Configurations.
a) Bridge-leg using
MOSFET diode
intrinsic
b) Asymmetrical
bridge-leg
providing dildt protection,
turn-on snubber and limited
reverse recovery problems
c) Bridge-leg
with
series
blocking diodes and fast
freewheeling diodes
7/10
783
APPLICATION NOTE
Figure 11 : Turn-on Losses in a Bridge-leg.
Turn-on Losses in the MOSFET
WT
(pJ)
4000
Classical MOSFET
3000
2000
Lifetime controlled MOSFET
1000
BYT12P600
L_~5-0--1OT"0--1'50--2::-:0'-':D:--~2::-:5~D:----'d i Idt (AI ~s)
a) Turn-on losses in the MOSFET when switching 10A inductive load current on 400Voc rail as a function of
the rate of change of MOSFET drain current (dlo/dt)
Reverse Recovery Losses in the Diode
lid
(I'J)
1500
1000
with classical MOSFET
500
wi th l Het ime cant rolled MOSFET
BYT12P600
o ~-~----~-----~--.
50
100
150
200
250
di Idt (AIl's)
b) Reverse recovery. losses in the freewheeling diode when switching 10A inductive load current on 400Voc
rail as a function of the rate of change of freewheeling diode current (dIFD/dt) during diode turn-off.
8/10
784
APPLICATION NOTE
Figure 12 : Turn-on Ilustrations of the MOSFET Drain to Source Voltage (Vos) and Current (10) at Turn-on
of the Transistor Limited to 1OOA/~s.
a) Classical MOSFET
(500V, 0.6 ohm)
BUZ353
Diode losses = 540~J
MOSFET losses = 3200~J
A
/
-It
/
"
/
I
a
Vos MOSFET drain to source voltage
100V/DIV
10 Drain current
5NDIV
Time 200ns/DIV
/
J
b) Lifetime controlled MOSFET
(500V, 0.6 ohm)
/~
/
\
/
/
- r--..
Diode losses = 460~J
MOSFET losses = 1600~J
11'"
I\,.
Vos 100V/DIV
105A/DIV
Time 100ns/DIV
tw.
""N
1'\
!'(
/
/
1/
J
It can be seen that due to the slow intrinsic diode of
the classical MOSFET, turn-on losses are twice that
with a lifetime controlled MOSFET. With external
c) External fast diode
BYT12P-600
Diode losses = 130~J
MOSFET losses = 560~J
Vos 100V/DIV
105A/DIV
Time 50ns/DIV
fast freewheeling diodes losses are only 20% of the
losses in the classical MOSFET.
9/10
785
APPLICATION NOTE
CONCLUSION
Reverse recovery of the intrinsic MOSFET diode
has been investigated. Losses caused by slow intrinsic diode recovery for the classical MOSFET
have been compared with losses using lifetime controlled MOSFETs in a bridge-leg and losses using
fast external freewheeling diodes. It has been
shown that turn-on losses in a bridge-leg using
classical MOSFETs are five times greater than
losses in bridge-legs with fast external freewheeling
diodes and two times greater than losses in bridgelegs using lifetime controlled MOSFETs.
By using different types of inductors (such as saturable inductors) in bridge-legs it has been shown
that negligible turn-on losses can be achieved as
reverse recovery of the intrinsic MOSFET diode can
10/10
786
be limited. Practical results confirm that by using
saturable inductors astutely in bridge-legs, it is
possible to use the intrinsic diode of the classical
MOSFET in high frequency inductive load switching
applications with negligible turn-on losses.
REFERENCES
SGS
"Power MOS Devices", 1st Edition, October
1985.
2
J.T. DAVIES - P. WALKER - K.I. NUTTALL
"Optimisation of VDMOS power transistors for
minimum on-state resistance", lEE Proceeding, vol. 134, PT.1, No.3, June 1987.
APPLICATION NOTE
ENVIRONMENT DESIGN RULES OF MOSFET
IN MEDIUM POWER APPLICATION
BY B. MAURICE
ABSTRACT
an over-voltage protection circuit is presented.
The use of POWER MOSFET allows high switching
speed in power applications above 10kW. Nevertheless the main limitations come from the characteristics of the circuit design. From a practical
example, this paper analyses and proposes solutions to adapt the POWER MOSFET and the layout
in order to minimize parasistic inductances. Special
emphasis is given to the driver circuit, package, wiring rules and voltage spike protection at turn-off.
I - INTRODUCTION
POWER MOSFETs are now considered standard
tools by circuit designers working at tens of Amps
and hundreds of Volts. Their traditional advantages
(easy drive and over current capability) remain true
when switching over 10KWatts. Nevertheless, the
main limitations encountered are not from the MOSFET itself as it can switch high cu rrent at high speed
(over 1000Amps/sec), but from characteristics of
the circuit design. After presentation of a specific
example of Power MOS drive, the optimisation of
the power devices and the layout will be analysed
in the practical example of a chopper operating with
ISOFET (1000V - O.7Q or 100V - O.014Q). Finally,
II - HIGH POWER MOS DRIVE
Even with high power switching (over 10KW), the
driver circuit can be very simple (fig: 1), comparable
to the ones used for low power circuits.
The major characteristics of a POWER MOSFET is
its high input capacitance (ie : Ciss ~ 12nF for 100V
- 14mQ MOSFET) which must be rapidly charged
and discharged when switching without creating oscillations.
The following rules have been used for the design
of the driver :
• A low dynamic internal impedance which permits
peak current greater than 1Amp for 300nanosec to
charge and discharge the ISOFET input capacitance.
.• A low impedance circuit reduces the sensitivity to
dVDs/dt at turn-off of the ISOFET.
• The total resistance of the gate circuit must be
greater than 5Q in order to sufficiently damp the
circuit preventing oscillatiohs and possible parasitic turn-on of the ISOFET.
Figure 1 : Driving Circuit for ISOFET Over 1OkW Switching.
VOCo-------------------~--------~._--
1SV
3.3I.rf'
lSOFET
TS05MG40V
SGSP322
~t
BZX55C
l8V
SGSP322
BZX55C
l8V
Qi = 1 OOV O.4Q P-channel MOSFET
AN358/0689
1/9
787
APPLICATION NOTE
• The links between drive and gate, short and noninductive, are made between the gate pin and the
"Kelvin Source" pin. The use of the "Kelvin Source"
pin is very important when driving Power MOS. It
avoids parasitic effects caused by dlldt in the
source lead.
• The gate protection Zener diode has to be
mounted close to the ISOFET package.
Figure 2 : Over Current Capability and Switching Speed with ISOFET TSD5MG40
(1000V -0.7Q-ID = 13A).
a. Turn-on; the ISOFET controls 30A-650V and sustains 11 OA peak (8 x ID). The over current is
due to the recovery of the free-wheeling diode (BYT230PIV 1000).
b. Turn-off; with dlldt = 1600A/usec ; and dV/dt = 15000V/usec.
The switched power = 25kW ; and the switching losses = 1.3mj
a. Turn-on
VO = 200Vldiv
1D=20Ndiv
b. Turn-off
t = 50nsldiv.
Rg=5Q
III - LAYOUT DESIGN FOR HIGH SPEED
SWITCHING
The reduction of the parasitic inductances is a major
challenge for power switching especially with a
power MOSFET switching over 1000Amps/usec
(figure 2). With this switching leading edge, a 10cm
diameter wiring loop causes a 100V voltage overshoot. To solve this potential problems two actions
are necessary: choosing a well adapted device and
optimise the layout design.
a. Adapting the device to the layout
ISOFET is a MOSFET housed in an ISOTOP
package (figure 3) :
2/9
788
VO = 100Vldiv
10= 10Ndiv
• The ISOTOP package can be directly screwed on
the printboard because all of its terminals are at the
same level. Therefore, all inductances due to the
length of external wiring connexions, are eliminated.
• As a result of a low profile package (12mm), the internal parasitic inductance is less than 10nH.
Moreover, its Kelvin source (KS) enables the minimisation of disturbances induced by the power circuit in the driver circuit.
• Even though it has a thermal resistance value of
only 0.25°CIW, the case is fully internally insulated
at 2.5kVRMS. Therefore it can be mounted near to
the diode package on a common heatsink in order
to obtain a very compact circuit layout.
APPLICATION NOTE
Figure 3 : An ISOFET is a MOSFET housed in an ISOTOP package, which has a low profile.
It is easily integrated in low inductive layouts.
The "Kelvin Source" lead (KS) separates the gate circuit from the internal inductance of the source
connection.
IS mm
12 mm
b. Design of the layout
The chopper shown in figure 4 contains two active
components: the Power MOS and the freewheel-
ing diode; both in ISOTOP package screwed side
by side, on a common heatsink and directly connected on the printed circuit board (PCB).
Figure 4 : a. Chopper Schematic showing the Inductive Loop to be Reduced.
b. The Same Circuit with two ISOTOP Packages (diode and ISOFET). The packages and links
adopt an "in line" configuration in order to reduce the inductive loop.
a
.
L»IXJCT:tVE LOOP
TO BE REDUCED
3/9
789
APPLICATION NOTE
b
LOAD
+
ee0V
..-..... -......... -.. -... -- ... .
~
o
9
G
~s
s
By observation of the facts presented in appendix
1, the design rules used for the layout are summarized:
• Use of double sided PCB where each high current
path is immediately above its returns path on the
other side of the board.
The current densigy has been reduced by enlarging the copper tracks in order to decrease the local
dlldt and consequently the resulting induced voltage.
Use of several links instead of one, between two
large copper tracks, avoids high current concentrations and reduces the inductance (figure 5).
• Oecoupling capacitors have been configured in the
same direction as the direction of current flow. This
prevents the formation of an inductive loop. (compare figure 6a and figure 6b hatched surfaces).
The use of several smaller capacitors in parallel
permits reduction of the equivalent internal parasitic inductance. (figure 6c).
• Choose components (e.g. capacitors) specified
with a low intemal inductance. (electrolytical capacitor 700llF/400V can have a parasitic inductance
of several tens of nH). Prefer the capacitor packages which minimize the inductive connection
length.
Figure 5 : Junction between two wide copper tracks is less inductive when several spaced links are used
rather then a single link.
-
e
e = L x dI/dt
4/9
790
-
e'
e'= 1/3 e
APPLICATION NOTE
Figure 6 : Configuration of Decoupling Capacitors:
a. An inductive loop is formed, perpendicular to the current flow, because the current flow is not
super imposed near the capacitor,
b. Capacitor lying in the same direction as the direction cif current flow. inductive loop minimised.
c. Several smaller capacitors in parallel reduce their equivalent internal parasitic inductance for
the optimum solution.
5/9
791
APPLICATION NOTE
As a result the residual inductance of the finished
layout (fig. 7) has been measured as 35nH. (fig. 8)
plus 15nH when a current sensing loop (15mm 2 ) is
added to the layout
Figure 7 : A Double Side Very Low Inductive Print Circuit Board. (scale: 0.5)
Note the Multi Links (A) to connect One Side to the Other.
I entree
cde
• ••
•
00
o
••
~OC70
•-
...
..o
drive. rnax1Bv
•
•
POWER
HT
rnaxBOOv
MOB .IBOFET
SIDEA
o
o 0
o
SIDE B
L
6/9
792
a
APPLICATION NOTE
IV - OVERVOL TAGE DURING TURN OFF
We have previously seen that by following these
sound rules a parasitic inductance value of 3SnH
can be achieved. It represents the sum of several
small components : active components. passive
components and PCB. It seems difficult to reduce it
further in a circuit without paralleling several power
switches.
In view of the ISOFET fast switching speed at turnoff (1 OOOAmp/usec), the inductive voltage spike with
3SnH will be 3S Volts. This overvoltage is accept-
able for devices rated over SOOV. It is not negligeable in low voltage applications such as battery
powered equipment.
Two solutions are possible:
a. Slowing down the ISOFET
The switching speed at turn-off can be slowed down
by increasing the gate resistor value. This' method
increases the commutating time and consequently
the switching losses. These losses are increased by
SO% when Rg increases fro S to 10n. (figure 8).
Figure 8 : Increased Gate Resistor reduces dlldt and Overvoltage at Tum-off. (driver circuit fig. 1). The
total parasitic inductive loop (SOnH) includes the inductance of the sense current loop.
ID = 10AIdiv VD = 100V/div t = SOns/div (ISOFET TSDSMG40V 1OOOV - o.m)
Switched power = 2SkW ; Switching losses = 1.3mJ in (a) and 2.0mJ in (b).
b. Protection against over-voltage at turn-off
Use of a MOSFETwith a low margin forthe rating voltage (VBR(DSS)) can be achieved by using active protection (i.e. Transil) in order to clamp the voltage spikes.
One solution is to connect a Transil acros the drainsource leads. In this case, the energy is dissipated
in the Transil which has to be cooled in order to dissipate the average power.
(1/2 Ll2f = 20W with 40nH, 100A, 100kHz)
We have chosen another solution by connecting the
Transil across the drain-gate leads (figure 9). When
the over voltage transient reaches the clamping voltage, the clamping current goes through the gate resistance and biases gate above SV. (ex: 1A into 5£1).
This way, the clamping power is dissipated in the
MOSFET and a smaller Transil is required (P ~ 1W
at 100kHz in our case).
As the Transil does not heat up, the clamping voltage does not vary with temperature. The equivalent
dynamic resistance is very low because the serial
resistance of the Transil is divided by Rg and by the
MOSFET transconductance.
The current though the Transil being low, the voltage to be considered for its choice is the breakdown
voltage at test level (VBR at IR) instead of the surge
clamping voltage (VcL). The Transil breakdown voltage should be chosen to be lower than the maximum desired clamping voltage less 5 Volts to take
into account the MOSFET gate threshold voltage.
7/9
793
APPLICATION NOTE
Figure 9: Over Voltage clamping by a Transil across the Drain-gate Leads durring turn-off. (ISOFET
TSD4M150V 1OOV - 14mQ). Upper Trace shows the Current in the Transil (IT).
ID = 20A/div, VD = 20V/div, IT = 1Aid iv, t = 100ns/div.
IT
IN4148
BZW06-78
I
.-
I
---- .
.'
v - CONCLUSION
MOSFETs switching power over 10kW have the
same basic advantages as lower power Mosfe!. The
driving circuit remains very simple and the over current capability is huge. A specific emphasis has
been placed on the minimization of circuit layout inductance. Because of the very fast switching (easily over 1000A/s) it is advantageous to use:
packages like ISOFETwhich minimise their intemal
inductance and allow easy connection to printed circuit board and to heatsink. Also Kelvin Source contact to minimise drive circuit interference.
double side printed circuit board with symmetrical
8/9
794
1
~ t------<>--~
•....
t
v,
copper tracks, reduced current concentration, and
components positioned in order to minimise parasitic inductance.
overvoltage protection which avoids oversizing the
voltage rating of MOSFETs in low voltage applications.
BIBLIOGRAPHY
[1] An Innovative High Frequency High Current
Transistor Chopper. L. PERIER ; E.P.E. Bruxelles
1985.
[2] POWER MOS DEVICES Data Book 1st edition
June 1988 SGS-THOMSON Microelectronics.
APPLICATION NOTE
APPENDIX 1
MEASUREMENT OF PARASITIC INDUCTANCES ON A DOUBLE SIDED PCB
_ In the figure below, the link between points C and
D simulates the connection of a capacitor with
nap internal inductance, connected on double
sided Printed Circuit Board.
Figure 10.
A
I,
dI/dt"~_~,,_
n
~~~---------200rnm
_ The measurements are made with ad I/dt generator:
_ I = a to 40Amps with a dl/dt = 1000Als
The measurement of the induction voltage
VL between A to B, and C to D, permits calculation of L = VL I (dl/dt)
MEASUREMENT RESULTS
Figure 11.
L,,=35nll (5+30)
~
I,,,=110nll
r.",=30nl!
L"9=10nll (3-1-7)
:J:
(90+30)
Lco=30nll
MEASUREMENT CONCLUSIONS
• Capacitors should be positioned in the same direction as direction of current flow.
Compare : a. to b.
• Several links between two large copper tracks are
less inductive than a single link.
Compare: b. to c.
Lco=7nl!
LA,=5nl!
(3+2)
AJ
L",=14nH
(12+2)
Lco=2nll
8·
r.",=2nll
Every current path should be exactly above its return path on the other side of the board.
Compare: d. to e.
• Decrease local dl/dt density by enlarging copper
tracks.
Compare: c. to e.
9/9
795
APPLICATION NOTE
COMPACT HIGH PERFORMANCE BRUSH D.C.
MOTOR SERVO DRIVES USING MOSFETS
By C.K. PATNI
ABSTRACT
For medium power (200VA to 6kVA) brush D.C.
motor SeNO drives, MOS field effect transistors
(MOSFET) are ideally suited. A compact high performance (20 to 50kHz) 1.2kVA brush D.C. motor
velocity servo drive, which has been developed and
tested, is presented. SGSP477 and BYW8PI200
high efficiency fast recovery epitaxial diode (FRED)
are used in the 1.2kVA power stage. A 6kVA motor
drive design using ISOFETs is also presented.
TSD4M250 (ISOFET) and BYV54V200 FRED diodes
are utilized in the 6kVA design in which FREDs are used
as the MOSFET series blocking diode and the freewheel diode. Different power H-bridge configurations
are chosen and justified for the 1.2 and 6kVA drives.
Particular emphasis is placed on short-circuit protection
techniques and simple gate drives.
INTRODUCTION
Brush D.C. permanent magnet motors are extensively used as velocity servo drives for high performance applications such as robotics and
machine-tools. The high voltage D.C. (HVDC) supply of the flower stage for such motors rated up to
6kVA is generally limited to 200V D.C. because of
sparking of the commutator and brush assembly.
The commutator has a maximum volts per segment
rating at rated power above wh ich there is excessive
brush wear. MOSFETs are well adapted for medium
power applications at voltages up to 500V. Consequently the ease of paralleling, high peak current capability and the ease with which MOSFETs can be
controlled and protected make them ideal power
semiconductor switching devices for such motor
drives. Medium power brush D.C. motor voltage
limitation of 200V D. C. enables fast recovery epitaxial diodes (FRED) to be used which have high efficiency due to very low conduction losses and
negligible switching losses:
BYW81 PI-200 : FRED: .
Vf < 0.85V (IF = 12A ; Tj = 100'C)
trr < 35ns
Block diagram schemes for brush D.C. permanent
magnet velocity servo drives are discussed. SeNo drive
specifications shown in table 1 are considered and solAN359/0689
utions for the 1.2kVA and 6kVA motor drives are
presented. The 1.2kVA motor drive is developed and
tested. Protection, efficiency and switching frequency
requirements have strongly influenced the designs.
Other than the power ratings, the parameters listed
in the specification are common for many high performance servo drives. The main component in the
design of the hardware is the power H-bridge
switching ideally above the audio-frequency range.
High frequency switching permits a compact power
output filter to be used to filter the switching frequency if so desired.
SWITCH-MODE MOTOR DRIVE CONCEPTS
Figure 1 illustrates a conventional pulse width moldulated (PWM) D.C. motor seNO drive. The velocity demand and the tachogenerator feedback
signals are compared and the resultant velocity
error is amplified. This error is fed to the current
seNO amplifier where it is compared with the actual
current flowing in the motor armature. The amplified
current error is fed into a linear PWM generator. The
control of the mark to space ratio of the PWM generator is achieved by comparing the input error signal with a constant frequency triangular waveform.
This results in a fixed frequency PWM signal which
is fed to the power stage.
A switch-mode drive designed to the specification in
table 1 com prises of :
11 Drive and protection for power devices
21 Power supplies
31 Regenerative energy clamp (4 quadrant control)
41 Cu rrent loop
51 Control and logic for PWM and velocity seNO.
The block diagram of the drive which has been developed is outlined in figure 2. (The complete circuit
diagram is provided in figure 14). The differences
between the two schemes outlined in figures 1 and
2 are that the current control loop and the PWM integrated circuit are eliminated in the second
scheme. In the second scheme the velocity error is
fed directly into a velocity compensation and modulation' circuit. The elimination of the current feedback
loop limits this scheme in so much as it can not be
used in torque control applications.
1/10
797
APPLICATION NOTE
Table 1 : Typical Brush D.C. Servo Drive Specification.
Specification
1.2kVA
Modulation Frequency
6.0kVA
I
> 20kHz < 50kHz
Continuous Power
1300VA
Maximum Continuous Current
6000VA
I
I
10A
Bus Voltage Input
50A
120Voc
Efficiency
> 90%
Short to Ground
Shut down
Short to Bus Voltage
Shut down
Armature Short
Shut down
Operating Temperature
o to 50"C
Velocity Demand
10V
Regenerative Energy Dissipation
10% of Continuous Rating
Figure 1 : PWM D.C. Servo Drive.
'\..,
A.C. MAINS
REGENERATIVE
8.
f----1 ENERGY
MAINS FILTER
CLAMP
BRIDGE
VELOCITY
ERROR
COMPENSA nON
PVM
DECODE
CURRENT
~-V"-:_-
TACHO
F~EDBACK
VELOCITY FEEDBACK
Figure 2: Schematic Diagram of Brush D.C.P.M. Motor Drive.
"'v
A.C. MAINS
11
I PO\lER SUPPLIES
t
. L .
.~
""
Veto
'---
2/10
798
VELOCITY
ERROR
COMPENSA TlON
MODULATOR
.....-
ru
&
HAINS rIL TER
I
1
BRIDGE
IT
Vy
M~
VELOCITY rEEDBACK _
REGENERA TIVE
ENERGY
CLAMP
APPLICATION NOTE
BRIDGE CONFIGURATIONS & MODULATION TECHNIQUES
The bridge design must be capable of supplying bidirectional current to the motor for optimal four quadrant control. This can be achieved by using a
"T-bridge" or an "H-bridge", as shown in figure 3.
The H-bridge is generally chosen since it requires a
single power supply. The voltage rating of the power
semiconductor devices matches the motor voltage
rating for the H-bridge alternative.
The H-bridge has eight operating modes when connected to a D.C. motor load. These modes can be
seen in figure 4. Two of the modes increase current
supplied to the motor winding in either direction. The
other six operating modes reduce current in the
motor winding and are commonly known as freewheeling modes. Numerous switching modes are
possible for PWM and current control. For example,
.it is possible to PWM both the top and bottom devices in the bridge or simply either the top or bottom
device. It is possible to use the PWM mark to space
ratio such that the mark provides a positive rate of
change of current in the motor winding and the
space provides a negative rate of change of current.
The control of the pulse width thus establishes a,n
adjustable average voltage across the motor load.
A modulation technique used in the developed
servo drive is illustrated in figure 5. This modulator
is based on "delta modulation" (reference 1). The
mark to space ratio of the modulator output (O(t)),
determines the conduction period of the MOSFETs
in the H-bridge. The modulator comprises of the
standard delta modulator (part A), the proportional
term (part B) and the integral term (part C) of the
PID controller.
Figure 3 : Bridge Configurations.
+v
D.C. MOTOR
D.C. MOTOR
+---+-o-c=---mC\TIT~
...
-v'
Figure 4 : Operating Modes of the H-bridge Showing Current Flow Paths.
v
v
v
8 8
t~I
~ tl
{M
+
v
3/10
799
APPLICATION NOTE
Figure 5: A PID Controller with Binary Output.
r-~-------------~
I
H
e(_t)~-.----rl-i
I
I
I
I
om:
HYSTERESIS
1----------1
I
L
SWITCHING DEVICES FOR A RANGE OF
D.C. MOTOR SERVO DRIVES
At medium power levels the MOSFET is ideally
suited offering high switching speed, ease of paralleling and simple gate drive and protection. SGSThomson has introduced a range of MOSFET
devices in plastic isolated packages. The 200V devices summarised in table 2, can be used to design
a ser~o drive range from 600VA to 6kVA without the
need to parallel MOSFETs in separate plastic packages.
The MOSFET internal parasitic diode is too slow for
applications requiring ultrasonic switching frequen-
4/10
800
I
~~~
®
I
I
I
I
I
I
-1
I
I
©I
_________ ..-J
cies. Excessive switching losses in the MOSFET
can result from the reverse recovery time of the internal parasitic diode (greater than 600ns). Noise is
also induced on the supply rails when the conducting diodes reverse recover. Table 2 specifies high
efficiency ultra fast recovery epitaxial diodes for
freewheeling. These diodes, having a conduction
voltage of less than O.85V at rated nominal current,
are ideally suited as MOSFET series blocking
diodes used to prevent the conduction of the internal parasitic diode.
Figure 6 illustrates possible techniques for utilizing
fast external diodes for the 6kVA brush D.C. motor
design.
APPLICATION NOTE
Figure 6: 6kVA MOSFET Switch Configurations Using ISOFETs and FREDs.
-~I -1 ____
I
I
BYV54V200
~-il II 20kHz
Manufacture: SGS - THOMSON MICROELECTRONICS
Part N°
MOSFET
SGSP367 '
SGSP477 '
TSD4M250 2
10
ROS(ON)
T) = 25°C Tc = 100°C
(Q)
(A)
0.45
0,17
0.021
I ",v"veo"
10
20
68
RTH
(OC/W)
1
0.83
0.25
Part N°
VF at
Diode FRED T) = 100°C
(V)
POWER
(VA)
Vnom
(V)
Inom
(A)
BYW80PI200
BYW81PI200
BYV54V200
7
12
50
600
1200
6000
120
120
120
5
10
50
0.85
0.85
0.85
IF
(A)
Table 2 A range of brush D. C. motor velocity servo drives.
1 - without insulation.
2· ISOFET : MOSFET chips in parallel in ISOTOP package.
1.2.KVA BRUSH D.C. SERVO DRIVE
switches connected in series across the HVDC. In
this asymetrical bridge-leg, (illustrated in figure 7),
the rate of change of short-circuit current is limited
by inductors (L1 and L2 : RM14 cores) which also
limit freewheeling current from going through the
parasitic diodes of the MOSFETs. At the 10A maximum continuous current rating of the drive, these
inductors are still a managable size. This bridge-leg
configuration is capable of withstanding simultaneous conduction of the two devices in the bridgeleg since there are series inductors which reduce
the rate of change of drain current. This provides
sufficient time for the short-circuit detection loop to
operate. The power devices are thus turned-off without being stressed with high rates of change of pulse
currents.
Figure 7 illustrates the block diagram of the developed 1.2kVA brush D.C. selVa drive. The Hbridge operates at a nominal voltage of 120Voc. The
D.C. motor in certain applications is driven by its
load and hence is a generator of energy. This regenerative energy causes the HVDC rail voltage to
increase as energy is stored in the smoothing capacitors.
At a maximum voltage of 160Voc, a resistive dump
is turned-on to dissipate the regenerative energy
and thus limit the HVDC to 160Voc. The drive
utilizes the velocity PID controller illustrated previously in figure 5. A current sense resistor is incorporated in the H-bridge to provide load current
feedback necessary to limit this load current to the
maximum continuous current rating of the drive.
MOSFET based bridge-leg configurations have previously been discussed (reference 2). The bridgeleg utilized comprises of "low-side" and "high-side"
At a maximum continuous current rating of 10A,
SGSP477 MOSFETs and BY81 PI200 fast freewheel diodes plastic packages are optimally rated
for the 1.2kVA power stage.
5/10
801
APPLICATION NOTE
Figure 7 : 1.2 Brush D.C. Motor Velocity Servo Drive (120VDC ; lOA: nom.f.
)
H.V.D.C.
MONITOR
lt
RESIST3
r-
~~~~
nRIVE
PROTECTION
RMl4
150\1
BY\J81PI
CMOS GATE
DRIVE \lITH
PROTECTION
+-
DC MOTOR
•
1t+-W
SGSP477
aI
ISOLATED
~t
GATE DRIvE
IJITH
PROTECTION
SGSP477 CMOS GATE
DRIVE \.lITH
HL_ _ _ PROTECTION
'LoV-SIDE' L-~~_
1.-1
I
CURRENT
SENSE
~
\
t
S\JITCH!NG
DECODE \.lITH
n
ti
H.V.GND
TRANSISTOR :::::::
SIJITCHING
SIGNALS
TRANSISTOR
VELOCITY Ft:EDBACK
r----
CURRENT
VELOCITY
LIMIT
CDMPEN$A nON
I\. MODULATION'
CONTROL
CROSS-r.
.c_OU_P_LE_ _ _ _ _ _ _
!.-
GATE DRIVES AND PROTECTION
Similar gate drives and protection circuits, (illustrated in figure 8), have been used forthe "high-side"
and "low-side" switches. This CMOS gate drive is
well suited as switching speeds of 100 to 250 nanoseconds are sufficient in motor drive applications requiring a switching frequency of around 20 to 30kHz.
Monitoring of the drain to source voltage while the
device is conducting permits the detection of shortcircuit conditions which lead to device failure. The
device is turned-off before the drain current reaches
a value in excess of the peak pulse current capability of the MOSFET. When the MOSFET is turned-
802
SGSP477
LI
L2
'---t--
TACHO
f-----''''1
DRIVE \.lITH
~
PROTECTION f----'''1
6/10
ri
TO 221)[
_ .JY\J8IP[ 200
CORE
200
CMOS GATE
~7GH-SIDE'
FL---
SGSP477
ISOLATED
~~~~~~_.J
MODULATED OUTPUT
-- ,....... VnFHLAONCnlTY
~-
on the on-state voltage of the device (VDS(on)) is
compared with a fixed reference voltage of approximately 8V. At the turn-on instant, VDS(on) monitoring
is inhibited for a period of approximately 400 nanoseconds in order to allow the MOSFET to turn-on
fully. After this period, if VDS(on) is detected to be
greater than the fixed reference voltage, the device
is latched-off until the control signal is turned-off and
turned-on again.
The "high-side" gate drives have isolated low voltage supplies and isolated command signals using
high speed opto-couplers.
APPLICATION NOTE
Figure 8 : An Isolated CMOS Gate Drive with Protection.
+12v
10K
22K
120
leI 4093
<1/4)
lei
(114)
IK
SGSP477
56K
OV
MOTOR DRIVE PERFORMANCE
BSSIOO
shoot in the velocity response (trace 2). The effects
of changing the proportional gain and the integmtor
time constant of the PID controller can be seell in
figures 10 and 11 .
Figure 9 illustrates the dynamic response of the
motor drive to a step demand of 4000rpm. The response has been optimised for the no-load case
(trace 1). Under heavy load inertia there is an overFigure 9 : Velocity Response of Motor Drive.
SPEED
(RPM)
--
4000
DEMAND
1. tiD LOAD RESPONSE
2. LOADED RESPONSE
RESPONSE
4000
~2
LL
I
Time scale: O.Ss/div
7/10
803
APPLICATION NOTE
Figure 10: The Effect Upon the Dynamic Response of the Analogue Velocity Servo System, When the Gain
of the Proportional Term in the PID Controller is Varied.
4000
Deno.nd
!\
ResponsE'
",,-/ -
4000
Time scale: 0.05sldlv
Figure 11 : The Effect Upon the Dynamic Response of the Analogue Velocity Servo System, when the Time
Constant of the Integrator in the PID Controller is Varied.
Speed
(R.P.M.l
4000
DeMo.nd
1\
Response
~V
Time scale: 0.05sldlv
6KVA BRUSH D.C. MOTOR SERVO DRIVE
Figu re 12 illustrates the block diagram of the proposed 6kVA (120Voc ; 50A) motor drive using ISOTOP packages for the MOSFETs in parallel
(ISOFET) and the FRED diodes.
Blocking diodes in series with the MOSFETs are
proposed to prevent the MOSFET internal parasitic
diodes from conducting. The asymetrical bridge-leg
configuration is not a cost-effective solution since inductors rated for 50A continuous operation are large
and expensive. The series blocking diode has to be
an ultra fast high voltage type. If the transistor F2
(shown in figure 12) is conducting, the drain to
source capacitance of the transistor F1 is charged
to the HVDC voltage. If F2 is turned-off, the load current transfers from F2 to the free-wheel diode, 01.
Consequently the series blocking diode, 02, supports the drain to source capacitance voltage of F1
(equal to HVDC) provided this capacitance is not
discharged by turning-on F1.
8110
804
An isolated D.C. current measurement device,
(such as an Hall-effect current sensor, LT80-P,
manufactured by LEM), is recommended for the
measurement of load current necessary for current
limit control.
Pulse transformer based floating gate drives illustrated in figure 13 can be used for the TS04M250
ISOFETs. The pulse transformer is used to transmit
simultaneously the ISOFET logic command signal
together with the gate to sou rce capacitance charging current. The current mirrortechnique (reference
2) is used to provide short-circuit and over-load current protection. The pulse transformer operates at
an oscillating frequency of 1MHz when a turn-on
control signal is present.. The secondary is rectified
to provide gate source capacitance voltage. The
current mirror provides a voltage "image" of the main
drain current. This voltage is compared with a fixed
reference voltage in order that the gate drive be
latched-off whenever the drain current exceeds the
specified overload current level.
APPLICATION NOTE
Figure 12 : 6kVA Brush D.C. Motor Velocity Servo Drive (120Voc ; 50A : nom.) .
.~L
I
H.v.D.C.
HDNlTOR
D2
ISOLATED
GATE DRIVE
RESIST]
BYIJ81Pl
aL
Dl X
IJITH
500\01
BYV54V200 ISOTOP
ISOLATED
GATE DRIVE
Fl
PROTECTlON
"'L...r
TSD4H2S0
\JrrH
PROTECTION
-
ISOTOP
200
D4
rSOLATED
GATE DRIVE~lt
Jt:.
VITH
PROTECTION
DRIVE \JITH
PROTECTION
I.J
1-----''1[I::J
~
D3
r-
TSD4M250
CMOS GATE
r
ISOTOP
ISOLATED
GATE DRIVE
"t....J
F2
TSD4."1250
m
'1
\.lITH
PROTECTION
ISOTOP
"
SGSP477
at
----~---+--+------H-V-G-N~D-~IS~D-L.~T~E-D-----t-~~---TRANSISTOR:::::::::
S\lITCHING
--
SIGNAL'~\\ TRANSISTOR,I
SVITCHING
\
CURRENT SENSE
I
CURRENT
DECODE \JITH 1-------1
CROSS-.CDUPLEj
L!MIT
CONTROL
I
I
VELOCITY FEEDBACK
I~D~~~~g~rcNI,
___V_E_L_D_CIOTY
8. MODULAT!ONr
J
~EH""ND
" -_ _ _ _ _ _ _ _--'M=ODULAED OuTPUT
Figure 13: Pulse Transformer Gate Drive with Current Mirror Protection for a TDS4M250.
9/10
805
APPLICATION NOTE
CONCLUSION
MOSFET based brush D.C. motor velocity servo
drives have been described, with particular emphasis placed on the bridge-leg configuration, the
PID compensation and modulation, the gate drive
and protection techniques. The PID compensation
and modulation circuits require few components to
achieve good velocity servo performance.
Figure 14 : 1.2kVA Switched-mode MotorDrive.
"-
'"0.
ro
~3
~M
OM
M m
~ t~
l~~
~ ~~
10/10
806
The development has led to a compact high performance 1.2kVA drive which is fully protected against
output short-circuit conditions. A 6kVA motor drive
is proposed using ISOFETs. MOSFET switching devices and their associated free-wheel and blocking
diodes have been specified for a range of brush D.C.
motor drives rated between 600VA to 6kVA without
the need to parallel MOSFETs in separate plastic
packages.
APPLICATION NOTE
SWITCHING WITH MOSFETs AND IGBTs:
50Hz TO 200kHz
by K.G. Rischmiiller
ABSTRACT
INTRODUCTION
The basics of IGBT and Power MOSFET
characteristics are discussed and their
switching behaviour analysed. Circuits for loss
evaluation of MOSFETs and IGBTs are
described and evaluation methods for output
charge and energy are shown. It is
demonstrated that on-resistance and output
capacitance are related and how loss
minimization can be achieved in different
PWM and resonant topologies. Gate drive
methods enabling reduced switching loss,
better overload behaviour and less driver
energy consumption are also shown.
The excellent switching behaviour of Power
MOSFETs is an incentive to power supply
designers to increase switching frequencies
and thus reduce the cost and size of the
magnetics. Nevertheless, low frequency
switching with controlled current and voltage
rise times can also lead to new concepts and
cost reduction. When optimising low and high
frequency power control circuits, the neglected
parasitic effects of Power MOSFETs and their
bipolar counterparts, IGBTs, become
important and have to be taken into account
for circuit - design.
AN463/0492
1/18
807
APPLICATION NOTE
A: UNDERSTANDING POWER MOSFET
AND IGBT BEHAVIOUR
THE DIFFERENCE BETWEEN POWER
MOSFETS AND IGBTS
Over the last few years, Power MOSFET high
voltage capability and on-resistance have
been very much improved. The on-resistance
per die area is a means by which these
improvements can be measured (fig.A 1).
On resistance per die area is close to the
physical limits for Power MOSFETs having a
600 - 1000V breakdown voltage, thus major
improvements in the on-resistance of these
devices can be obtained only by increasing
the die area.
Bipolar operation is the only way to decrease
on-resistance per unit area to below the
physical limit dictated by the resistance of the
n-body of the MOSFET.
The Insulated Gate Bipolar Transistor (IGBT),
the Bipolar Modulated FET (BM-FET) and the
Field Controlled Thyristor (FCTh) have bipolar
modes of operation.
The IGBT can be understood as a Power
MOSFET driving a PNP-transistor (fig.A2).
During conduction, the p-Iayer injects minority
carriers into the resistive n-Iayer, thus
significantly reducing the on-resistance of the
device (fig.A2).
The higher the breakdown voltage of the
device, the higher the difference in onresistance between a unipolar Power
MOSFET and a bipolar IGBT. Fig.A3 shows
the output characteristics of 1000V devices
having similar die-size.
The reduced on-resistance of IGBTs does not
come for free: IGBTs exhibit more turn-off
losses than Power MOSFETs (fig.A4) and
their protection against overload is more
difficult.
log RON. mm 2
9
30 mm 2
300 mn - 600 V
0.6
30 mm 2
20 mel - 60 V
60 V
600 V
log Uw
Fig. A1: MOSFETs on-resistance per silicon area versus breakdown voltage. With high voltage devices
it is close to bulk-resistance. Low voltage devices have much potential for improvement.
2/18
-------------------------L~I ~~~;~~~:~~------------------------808
APPLICATION NOTE
r
fLp
e
~G
~ ~I'"
L-j-
IHOS
I
c±>
G
$
n-
o--J
IeIP
n+
P
\,.
"-.I
(
~---
I
E
Ie
Fig. A2: Cross section and simplified equivalent circuit of an Insulated Gate Bipolar Transistor (IGBT).
This device combines Iowan-resistance with simple drive requirements.
IGBT
MOSFET
I
. . . . . . . . . . . . . . . . . . . . . . . 30
A-
/11----
I
J
3.5 A-
Yos
3.0 V
3.0 V
Fig.A3: Output characteristics of a 1000V-MOSFET and an IGBT having similar die-size.
c
OPEN BASE
D,3A
E
I--
0.6 Jl
S
~I
Fig. A4: IGBTs exhibit a turn-off collector current tail and significant turn-off losses in PWM circuits.
-------------------------- ~~~~~~~:~~
3/18
-------------------------809
APPLICATION NOTE
HOW TO CONTROL TURN-ON SWITCHING
Turn-on switching when the freewheeling
diode is conducting leads to losses in a Power
MOSFET and to similar losses in an IGBT
(fig.A5). Increasing the di/dt of the drain
current, or for an IGBT the collector current,
leads to reduced turn-on losses. Reducing
di/dt leads to higher losses, but makes the
reverse recovery behaviour of the
freewheeling diode "softer", thus reducing RFI
problems.
When switching a short circuit, drain-source
or collector-emitter voltage is at a constant
high level while the drain or collector current
increases at a certain di/dt (fig.AS). It
stabilises at a certain current value, Isc . The
amplitude and duration of this current should
be minimised in order to minimise energy
stress on the semiconductor device. The
output characteristics of the Power MOSFET
IRFP450 helps us to understand how we can
control di/dt and Isc (fig.A?). The time needed
to move the gate - source voltage from
approximately 2V to about SV determines the
rate of rise (di/dt) of drain-current. The
amplitude of.a short circuit current, I sc ' is
controlled through applied gate-source
voltage. An IGBT behaves similary (fig.A?b).
The dildt and Isc control can be implemented
with a driver stage which monitors drainsource or collector-emitter voltage (fig.AS).
The rate of rise of gate-voltage is controlled
through R1. The Zener diode, D2, clamps the
gate voltage to, for example, 6V and thus limits
Isc·
Under normal operating conditions, the drainsource or collector-emitter voltage decreases
after the reverse recovery of the freewheeling
diode, T1 blocks and the gate voltage can
increase to about 10V.
Such a circuit greatly limits energy stress
under short circuit conditions.
TURN-OFF SWITCHING
The switching device should not be damaged
during turn-off switching. A power transistor
datasheet usually contains the test circuit used
for establishing the safe operating area (SOA)
of the device (fig.A9). During operation the
load line should not cross the limits of the
SOA, but it is important to remember that the
SOA itself is valid for given drive, junction
temperature and dV/dt conditions.
Vs
R
DF
L
T
-1
~
i
I,V
IL
VDS
to
Fig, AS: Turn-on switching with a conducting freewheeling diode.
4/18
----------------~-------~~~~~~~:~--~--------------------810
APPLICATION NOTE
Vs
V"
DF
T
-l
I,V
+ID
1
VDS
t
Fig. A6: Switching-on to a short circuit.
lolAI
Vr, :\OV
I/S(
a
r
6V
6
VGS ,15V
50
/
TCilS I!=2S 0 (
40
1
SV
,
50
too
t50
1M
20
4.5V
VG!;
~'- I.-
4V
l1V
111/
30
6
131
IV
,15'(
T
v
V
IJj
10
V/
10V
v
9V
/
~
7V
... ~
5V
~
100
5 VoslVI
,)
POWER MOSFET IRFP450
IGBT STGH20N50
Fig. A7: Output characteristics of a POWER MOSFET and an IGBT
V,I
,- ...
--
I
v
t
t
Fig. AS: Principle 01 driver stage controlling dildt and short circuit current amplitude,
5/18
-------------- LV ~~~;m~r;,:~~©~ -------------811
APPLICATION NOTE
Reverse biased SOA
G( 1Q64
lolAI.
·
·,
··
··,
···
10'
10'
1
(a)
V _15V
T:.l00 0 (
R,.100n.
L.1BO~H
II
.
(b)
Fig. A9: Test circuit for the safe operating area (a) and SOA of IGBT STGH20N50 (b).
The rate of rise of collector-emitter-voltage
(dv/dt), junction operating temperature, Tj, and
drive conditions strongly affect the turn-off
behaviour of IGBTs. In particular, the latching
current is modified by these parameters.
The simplified equivalent circuit of an IGBT
(fig.A10) can be used to understand
modifications of latching current: transistor T1
conducts when the Power MOSFET structure
is on; T2 will conduct when the voltage drop
across Rs exceeds about 0.6V; the IGBT
"latches" if this happens. Once the device
latches removing the gate-emitter voltage will
not turn off the device and the device may be
destroyed.
The value of Rs doubles between 25°C and
125°C. The base-emitter threshold voltage of
T2 diminishes at about 2mV/oK - both
contributing to a reduction of latching current
from 100% at 25°C to 30% at 125°C. At turnoff switching, a dv/dt between collector and
emitter will add a capacitive current flowing
into Rs, thus reducing latching current further
and making it dependent upon dv/dt (fig.A 11).
6/18
The resistance Rg between gate and emitter,
strongly affects turn-off behaviour of Power
MOSFETs and IGBTs. When the collectoremitter (drain-source) voltage increases,
capacitive current flows into the drive circuit
and leads to a voltage drop across Rg, thus
maintaining Vge(V g5) at a dv/dt dependent
level. The resistor Rg can be used to control
dv/dt during turn-off. Thus turn-off losses, RFI
and latching current can be set to desired
values. The higher the Rg value, the lower
the turn-off dvldt and the higher the latching
current.
B - DRIVER CIRCUITS FOR POWER
MOSFETs AND IGBTs
Driver circuits have an influence on cost,
performance and reliability of the whole power
switching function.
Driver circuits should transform the logic level
control signal into a suitable voltage/current
waveform, exhibit low power consumption and
often offer galvanic isolation between input
and output.
------------- ~ ~~~;m~r::oo?l: -----------812
APPLICATION NOTE
c
cpJ
dV/dt
~c
E
Fig. A10: Equivalent circuit of an IGBT for understanding the latching behaviour.
I,V
Ie
t
Fig. A 11: Turn-off dV/dt as a function of gate resistance.
AVOIDING SPURIOUS TURN-ON
In bridge legs, Power MOSFETs and IGBTs
are subject to dv/dt, when the opposite
transistor switches on (fig.B1). This dv/dt will
charge the parasitic drain-source or collectorgate capacitance and lead to a current flow
out of the gate. If the voltage drop across Lp,
Rp and Rg exceeds about 1V to 2V, the
Power MOSFET/IGBT will conduct, leading to
extra switching losses.
A driver stage having three different states
gives a good compromise (fig.B2): dv/dt
during turn-off switching can be set by means
of Rg, thus obtaining excellent safety agajnst
latching and low RFI. After turn-off switching,
a low driver output impedance gives good
immunity against spurious conduction.
Nevertheless the parasitic resistance, Rp and
inductance, Lp, should not exceed certain
limits depending on dv/dt, die-size and
parasitic package inductances.
7/18
!V ~~~~n!~~:0l~l: ------------813
APPLICATION NOTE
Vs
T1
-M
---1~
)
L
Rp
VB
Fig. B1: Bridge leg with inductive load, where
transistor T2 is subject to "passive" dV/dt.
1
1
Fig. B2: Tri-state driver limiting turn-off dv/dt and
having high immunity againstpassivedv/dt.
MAXIMUM DRIVER
IMPEDANCE
PACKAGE
TO 220
100/300 nH
TO 218
ao/160nH
20/60nH
ISOlOP
-VB
NEGATIVE BIAS
MODULE
NEGATIVE BIAS
E
dV/dt-10kV/ ).IS
Fig. B3: IGBT with parasitic capacitances and
inductances.
MAXIMUM
DRIVER
NEGATIVE BIAS?
TABLE I: Maximum driver impedance as a function
of device package.
IMPEDANCEI
During dv/dt, the gate voltage should not
exceed about 1 volt. The maximum driver
impedance must be fixed at a value that is
dependent on the die size, which is related to
eCG and the parasitic package inductance
LP(int) (fig.B3). If LP(int) is very high, negative
bias may be required in order to avoid
spurious conduction. Table I indicates the
8/18
TO 240
maximum required driver impedance for a
dv/dt of 10kV/j..ls.
PULSE CONTROLLED DRIVER SUITABLE
FOR 0 - 1 MHz OPERATION
When applying a voltage pulse with, for
example, a 1OVamplitude and 500nsduration,
to the gate of a Power MOSFET (T) or an IGBT,
--------------------------~~~~~~~::n
814
--------------------------
APPLICATION NOTE
J
01
ONJL
OFF
fL
~l
~
C2
Fig. 84: Pulse controlled driver circuit memorizing
on-state and off-state.
Fig. 85: Pulse controlled drive with transformer
isolation. Even though there is no auxiliary
supply, any pulse width, at virtually any
relevant frequency, can be controlled.
SOOns!DIV
:ig. 86: Transformer output signal at gate-emitter!
gate-source voltage with pulse controlled
driver.
:harge will be stored in the gate capacitance
fig.B4). Thus the power device will remain
:onducting, even after removal of the input
)ulse. This is called the "memory-effect".
f a similar pulse is applied to a second Power
~OSFET (T2), the latter will conduct,
lischarge the gate of Power MOSFET (T) and
emain conducting - the off-state is
memorised. Supposing R is low enough,
dv/dt applied to Power MOSFET (T) does not
lead to spurious conduction.
It is possible to add a pulse transformer for
galvanic isolation and a third Power MOSFET
(or bipolar transistor) can be used to discharge
the gate of T2, whenever an "on-signal" is
generated (fig.BS).
When using the "memory-effect", only pulses
of about S!lVS have to be transmitted by the
transformer; a very small toroid transformer
is sufficient. Figure B6 shows the transformer
output voltage and resulting gate-source/gateemitter voltage. The circuit can handle any
duty cycle.
RESONANT DRIVER
MOSFETs AND IGBTs
FOR
POWER
Power MOSFET and IGBT driver circuits for
high frequency conversion should drive the
power devices in such away that the resulting
switching losses are low. Even at high
-------------l.V ~~~~m~~:O!~~ ------------9/18
815
APPLICATION NOTE
operating frequency, the driver circuit should
have negligible power consumption. Power
MOSFETs and IGBTs are charge controlled
devices. For turn-on one has to supply a
certain amount of charge into the gate. For
turn-off, charge has to be removed.
During switching, one can consider the drain
source path of a Power MOSFET as a fast
varying current source - moving in a drive
determined time from conduction to zero
current or vice versa.
Driving the gate with a rectangular shape
current (constant amplitude during a certain
amount of time) would enable faster charge
removal and faster switching but it is difficult
to realise. Resonant gate drive with an
inductance between driver and gate is easy
to realise - one can even use an increased
parasitic wiring inductance. With this
approach, the time to charge or discharge the
gate can be reduced by a factor of about two.
Depending on the circuit, gate charge can be
recovered and gate drive power consumption
reduced.
One of the possible resonant gate driver
D1
circuits can be supplied from a single 5V
source, and it generates a ten volt gate voltage
for conduction and a negative bias for the offstate.
Conventional gate driver circuits charge and
discharge a Power MOSFET's input
capacitance through resistors and a parasitic
inductance Lp (fig.B?).
Fig. B7: Principle of conventional driver circuit with
simplified equivalent circuit of MOSFET
51
+5~
T
D2
52
z
Fig. B8: Resonant gate driver. Power consumtion of the driver is 1/4 of a conventional driver.
------------- ~ ~~~~m~r::O!~l: ------------10/18
816
APPLICATION NOTE
At turn-on switching E = 1/2 CV2 is lost in Ron 1.
At turn-off switching, same amount of energy
is lost in Ron2. When driving power Power
M08FETs at high frequency these losses
become significant and should be reduced.
Resonance effects can be used for this
purpose (fig.BB).
When driver transistor 81 is turned on; a
sinusoidal current flows into the gate
capacitance of the power device. The gate
voltage reaches about twice the driver supply
voltage V aux . Thus, a Power M08FET
requiring a gate-source voltage of 1OV can be
driven from a 5V-supply. The diode D1 avoids
discharging the gate~ For turn-off switching,
82 is closed, a sinusoidal current removes the
charge from the gate. The gate-source, or
gate-emitter in the case of an IGBT, voltage
of the power device is inverted (negative).
Most of the stored energy is used to generate
a negative bias voltage (fig.B9). Diode D2
avoids discharging the negative gate charge.
Due to resonance overvoltage, gate voltage
would reach the breakdown voltage of the
gate oxide after a number of switching cycles.
A Zener diode, Z, has to be used to limit gate
voltage. The energy consumption of a
resonant gate driver is about a quarter of that
of a conventional driver.
The charging and discharging of a capacitor
with a given peak current, is achieved more
rapidly through an inductance of an
appropriate value. Resonance driver circuits
therefore have the ability for the fast switching
of power devices (fig.B10).
C - LOSS REDUCTION IN PWM
CONVERTERS
PARASITIC CAPACITANCES
CONTRIBUTE TO LOSSES
The influence of the Power M08FET output
capacitance is negligible in low voltage, low
frequency applications. This changes greatly
when increasing operating voltage and
switching frequency. The effect of the output
capacitance, C out ' has to be taken into
account in high voltage, high frequency
applications.
For switching loss evaluation, it is possible to
0,5 AI
OIV
(3,3nF parallel to G-E)
500 Ns/oIV
a) POWER - MOSFET IRFP450
b) IGBT STGH20N50
Fig. 89: Gate-current and gate-source/gate-emitter voltage waveforms.
11/18
--------------------------~~~~~~~::~~ -------------------------817
APPLICATION NOTE
. .I
........iH.H.1
..... , ..... J ········· ....•...
10V /0
... , VGS:
1
' j
..... ; .... , ..... _, .. ;:,.. r-';'--'---+--'---'-
l:rf. ...;.'_::.-+--:--:-......;,._~=7
!
'G:
lA/Diy
10:
20A/Div
"i.. J._
....
250 ns/Div
Fig.810: An ISOFET TSD5MG40V (1 OOOV, 0.7Q)
driven by a resonant driver. Switching
losses are greatly reduced.
use a simplified equivalent circuit of Power
MOSFETs (fig.C1).
The function of the output capacitance can be
understood as a built-in capacitive snubber.
At turn-off switching, this capacitance is
charged from Von to the maximum voltage
VOS(Off) applied to the Power MOSFET
(fig.C2). Once charged, the capacitor contains
energy. Depending on the converter structure,
this energy may either be recovered or
dissipated .
In PWM circuits (fig.C3) the Power MOSFET
discharges its output capacitance at turn-on
switching and (0.5 • Cout * V OS (01l)2) Joules
are lost. (C out is the effective output
capacitance of the Power MOSFET, V OS(oll)
the drain source voltage just before turn-on
switching).
The discharge-current flows inside the Power
MOSFET, it cannot be observed on an
oscilloscope.
HOW TO MEASURE STORED CHARGE?
A simple circuit can be used for evaluation
and specification of the output capacitance
(fig.C4): The device under test (OUT) is
connected to a high voltage supply via a
resistor. A second Power MOSFET is
paralleled to the OUT. The Power MOSFET
under test is permanantly blocked, the second
Power MOSFET switches periodically. At turnon of the latter, you can observe the discharge
current and time on an oscilloscope and
determine the amount of charge, energy and
the value of the capacitance.
SOURCE
SOURCE
It
BODY
p'
DRAIN
DRAIN
Fig. C1: Power MOSFET cross section· a) parasitic capacitors
b) equivalent circuit.
------------- LV ~~~~m=:U!~:: ------------12118
818
APPLICATION NOTE
.... •••• J':1
650V
o.
•I •
k
~
I·'
III
.... r.. . . ..... .... ...
•
~
,
.~
G
..0;; ;.;;::::
I:
-l
COUT
1600A/ys
s
--!>-
SONS
Fig. C2: Turn-off switching of a 1000V-O.7Q Power
MOSFET.
Fig. C3: Discharging output capacitance during
turn-on switching.
400V
VDS
f SOV/DIV
10
fO,IA/DIV
SONS/DIY
Fig. C4: Evaluation of Power MOSFET output capacitance,
a) test circuit,
b) waveforms with IRF450, V DS(ofl) = 400V.
ON-RESISTANCE - CAPACITIVE LOSSES
A Power MOSFET's contribution to converter
losses are conduction, switching and gate
drive losses. Conduction losses can be
reduced by increasing the die size, leading to
smaller on-resistance. Increased die size
introduces increased output capacitance and
switching losses (fig.C5).
Minimum losses are obtained when losses
due to discharge of the output capacitance
and conduction losses are equal (fig.C6).
Optimisation depends on the supply voltage,
the converter structure and the switching
frequency.
The consequences are: from a certain
------------- LV ~~~~m~::9~ ------------13/18
819
APPLICATION NOTE
~~!~c
:
Ron 1
~
Ptoto\ = P capacitor + P conduction
T
Cout 1
'" DRAIN
~
area. 2
Cout = Cout 1 + C out 2 •••
4
5
Silicon oreo
Fig. C5: Power MOSFET cross section. Increase
of silicon area or paralleling discrete
devices reduces on-resistance but
increases output capacitance.
11
Fig_ C6: Conduction and switching losses versus
area. Total loss has a frequency
dependent minimum.
-----------------------------.
!
(Jl
III
o...J
(Jl
f(kHz)
Fig. C7:Total losses versus frequency calculated asymmetrically with three 500V Power MOSFETs
(same technology, different on-resistance).
switching frequency upwards, a size reduction
of the Power MOSFET leads to improved
efficiency, even when it is associated with an
increased on-resistance.
In SMPS applications with PWM and with a
maximum drain-source voltage of 400V,
switching losses due to the discharge of the
output capacitance are dominant at switching
frequencies exceeding 100kHz to 150kHz
14/18
(fig.Cl). For loss reduction in SMPS operating
below 100kHz Power MOSFETs with low onresistance are preferable - above 100kHz
Power MOSFETs with low output capacitance
and higher on-resistance are better.
INFLUENCE OF TOPOLOGY
Comparing energy stored in the two Power
MOSFETs of an asymmetrical half bridge
--------------------------- 'fi ~~~~~~~:oo~J: -------------------------820
APPLICATION NOTE
max 800 V
160 pF
370 pF
26 pJ
120 J-IJ
Fig. C8: Energy stored in the output capacitance of two OAQ 1000V Power MOSFETs and in one
0.8 Q - 1000V MOSFET.
t
t
Fig. 01: Typical waveforms with zero voltage switching (a) and zero current switching (b).
flyback converter with a single switch flyback
shows that significantly more energy is stored
in the high voltage device used in the single
switch flyback (fig.C8). It is possible to
estimate that between 30% to 60% of that
energy is dissipated.
D - POWER MOSFETs AND IGBTs IN
RESONANT CONVERTERS
A large number of different resonant and
quasi-resonant topologies exist. For the
purpose of choosing semiconductors, one can
distinguish two basic modes of operation: Zero
voltage switching and zero current switching
(fig.D1). The other modes are in between.
IGBTs are as simple to drive as Power
MOSFETs and offer, in the area of high
.voltage switching, much better on-resistance
per unit silicon area and may offer less
conduction losses or lower costs.
Depending on the converter topology, either
Power MOSFETs or IGBTs may be more
suitable.
15/18
-------------------------~~~~~~~~:9~------------------------821
APPLICATION NOTE
ZERO VOLTAGE SWITCHING
A typical circuit with zero voltage switching
consists in a switch, T, with paralleled
capacitor and series choke (fig.D2). The whole
is supplied from a voltage source. During
conduction in the switch, the choke current
increases with time. At turn-off, the voltage
across C and the switch increases as a
sinuoidal function and may reach s.everal
times the supply voltage (fig.D3). Afterwards
it swings back to below zero where it is
clamped by the diode. The output capacitance
of the semiconductor switch and the capaCitor
are discharged via the inductance. Thus the
energy is recovered. The only losses are due
to the parasitic resistance Rs, which is a part
of the Power MOSFET's on-resistance.
Increasing silicon area reduces on-resistance,
Ron, and parasiti~ damping resistance, Rs.
An increase of silicon area is not paid for with
an increase of capacitive loss. Power
MOSFET switching losses can be considered
as negligible with this operation mode.
High voltage IGBTs exhibit significantly lower
conduction losses than high voltage Power
MOSFETs with similar die size. The IGBT can
be understood as a Power MOSFET driving
a PNP-bipolar transistor (fig.D3). The onresistance of the Power MOSFET is virtually
divided by the bipolar gain. It is possible to
compare the switching to that of a high voltage
PNP-transistor, switching with open base resulting in a collector current tail. This tail
cannot be ignored as the resulting loss is a
major limitation for the application of IGBTs
in converters with zero voltage switching.
ZERO CURRENT SWITCHING
A typical circuit using zero current switching
consists of a switch with a series choke, the
whole paralleled with a capacitor and supplied
~I
SA
---j
(au t
o.
I-Fig. 02: Typical circuit with zero voltage switching.
16/18
0.8 jl S
,I
Fig. 03: Equivalent circuit of an IGBT and waveforms in a ZVS-circuit. Even a small tail
current leads to significant turn-off energy
loss.
---------~--- L"fl ~~~~~~¥r::oo~~
822
-------------
APPLICATION NOTE
90 A I--- '--
,.....
II
o
I
I
t\
\
1\
. . ...
\
,
"
..
".,
.... ...
Ie
(out
T
200V
o
Fig. 04: Typical circuit with zero current switching.
c
I
E
+
Fig. 06: Equivalent circuit explaining the absence
of a current tail. When the collector-emitter
voltage of the IGBT is negative, a current
flows thourgh the body diode into the base
of the PNP. This current blocks the PNP
structure efficiently.
/(
""'-- ...J r....
....
I
Fig. 05: Collector current and collector emitter
voltage of a 10 Amp-500Volt IGBT
(STGP10N50) with zero current switching.
At turn-on switching, output capacitance is
discharged into the switch; capacitive losses
similar to PWM-converters can be observed.
IGBTs do not show current tail in this
configuration! After the zero crossing of the
collector current a short negative current pulse
can be observed (fig.OS). It flows through the
body diode into the base of the PNP,
sweeping stored carriers away, thus avoiding
current tail and corresponding losses (fig.06).
IGBTs are very suitable for resonance
converters with zero current switching where
they offer a better cost/performance
compromise than Power MOSFETs and can
be operated at frequencies of several hundred
kHz.
RESONANCE IN PWM CIRCUITS
from a current source (fig.04). At turn-on, the
current through the switch increases with a
sinuoidal function and then swings below zero
(fig.01). The negative half wave flows through
the diode.
The advantages of zero current switching with
IGBTs can also be used in PWM converters:
(this is similar to forced switching circuits as
used with SCRs - improved MORGAN circuit
(fig.D7).
------------ ru SCiS·THOIVISON - - - - - - - - - - -17/18
•J U
!kIlOI!:~@~~~I!:1Ta:J@1Il0I!:$
823
APPLICATION NOTE
L
Taux
~
phase control, soft start circuits etc ...
Through zero current mode operation, the
current tail of IGBTs can be avoided, and then
IGBTs can be operated in PWM circuits at up
to 20kHz and resonant converters even at
200kHz. Maybe some of the well proven
thyristor circuit topologies could be used and
even improved with IGBTs.
The key to all these new applications with
improved performance is in forgetting
prejudice and thinking about what really
happens inside the power semiconductor
devices.
REFERENCES
Fig. D7:Circuit using resonance in a PWM
converter. With this circuit the IGBT is
virtually free from turn-off losses and can
be used at inaudible frequencies.
With these circuits it is possible to take
advantage of the high current handling
capability of IGBTs without any risk of loosing
control as is the case with these earlier
thyristor circuits. Thus PWM operation of
IGBTs at inaudible switching frequencies is
possible.
CONCLUSION
Investing more effort into understanding and
designing driver cirCUitry for Power MOSFETs
and IGBTs opens the way to better
performance, lower costs and new
applications.
Through suitable gate control, Power
MOSFETs can be made even faster.
However, it is also possible to slow them down
in order to reduce RFl-filter requirements in
18/18
~-----------824
1) A. Galluzzo, M. Melito, M.Paparo: How
design rules influence high frequency
switching behaviour of POWERMOSFETs, Proceedings of PEG'90, Long
Beach
2) J.M.Bourgeois, B.Maurice: Losses of
Insulated Gate Bipolar Transistor in H.F.
resonant converters, Proceedings of lAS
conference, IEEE, Oct. 89
3) B. Maurice: Environmental design rules of
MOSFETs in medium power applications,
Proceedings of PGIM '89, Munich.
4)
H. Foch, P. Marty, J. Raux: Use duality
rules in the conception of transistorised
converters. Proceedings of International
Power Conversion '80, Munich.
5) N.O. Sakal, R. Redl: Computer-aided
design and optimization of regulated zerovoltage-switching single ended resonant
DC/DC conveter, including voltage-control
function, Tutorial Seminar, PEC '90
t::;j ~~~~n':=:oo~l:
-------------
APPLICATION NOTE
INSULATED GATE BIPOLAR TRANSISTORS IN HIGH
FREQUENCY RESONANT CONVERTERS
by J.M. Burgeois, B. Maurice
ABSTRACT
IGBT technology produces devices that are
easy to drive, are capable of switching at high
voltages and currents and operate at high
current density.
A common application for this class of device
is in off-line motor drives that use them in a
"hard" switching mode.
Designs are now begining to be made that
use the IGBT in resonant converters with "soft"
switching and that operate at higher
frequencies.
AN464/0492
This paper discusses the operating limits of
IGBTs in resonant circuits. In particular, this
analysis considers the thermal balance and
the maximum current density that can be
achieved by IGBTs in this type of application.
The major resonant sub-circuits are
highlighted and the duality rules that permit
the use of these circuits in place of other
configurations, discussed.
Finally, a practical circuit is given for driving
and protection of IGBTs.
1/12
825
APPLICATION NOTE
1. INTRODUCTION .
Resonant converters will operate at much
higher frequencies than conventional designs
of converters. For this reason they are
attractive because using a higher operating
frequency means that the size of passive
components in the circuit will be smaller. The
higher frequency is possible because the
converter switching losses are lower. The
extent of this improvement is dependent on
the converter structure and mode of operation.
Until recently resonant converters used SCRs,
bipolar transistors or Power MOSFETs as
switching elements.
The purpose of this paper is to consider the
use of IGBTs in resonant converters. IGBTs
combine some of the advantages of bipolar
transistors and Power MOSFETs. For example
easy voltage drive, fast and efficient protection
and low on-state dynamic resistance. The
paper also analyses IGBT losses and the
dependence of their maximum operating
frequency on the converter structure and mode
of operation. A practical example is discussed
that uses a fast IGBT, the STGP1 ON50, which
is rated at 10 Amps/500 volts.
2. RESONANT STRUCTURE
The resonant switch is the basic element of
any resonant converter. It is a single tuned
sub-circuit that includes a switching
component, a diode, an inductor and a
capacitor. Depending on the position of the
diode, this resonant switch is uni- or bidirectional, thus providing half or full wave
operation. The major feature of this type of
sub-circuit is its ability to switch at zero current
,(or zero voltage). This reduces the switching
losses as compared to "hard" switching
circuits. This means that current and voltage
do not occur simultaneously across the switch.
As a result the switch will only experience
either a voltage or a current.
There are two main resonant converter
configurations:
a) A quasi resonant converter which uses one
resonant switch excited in discontinuous
operating mode by pulse frequency
modulation. Because the current (or voltage)
wave is whole (the waveform is unbroken) the
switching behaviour of the resonant switch is
maintained. Evaluation of the losses in the
IGBT in these converters is made using the
two basic operating modes: zero current mode
(ZCM) and zero voltage mode (ZVM).
b) A resonant converter uses a minimum of
two resonant switches in a symmetrical
structure. It allows continuous operating mode
operation which changes the switching
conditions of the resonant switch: it is not a
whole wave mode and zero current (or zero
voltage) switching occurs, depending on the
switching frequency, only at turn on or at turn
off. So, a large fraction of the IGBT's losses
can be' deducted from the quasi resonant
analysis.
Section 3 gives an accurate analysis of IGBT
losses in quasi resonant converters. The
overview of switching conditions in resonant
converters provides the basis for loss
evaluation using the analysis of the previous
section.
3. IGBTs IN
CONVERTERS
QUASI
RESONANT
As already stated previously, in quasi resonant
converters the IGBT operates as a single
tuned resonant switch with a quasi sinusoidal
current (or voltage) waveform. This analysis
examines each mode.
2/12
--------~---------------- ~~~~~~~~:9~
826
A~PLlCATION
NOTE
3.1 IGBTs IN ZERO CURRENT SWITCHING
QUASIRESONANTCONVERTER&
a. Switching: The IGBT's switching behaviour
is analysed using the circuit shown in figure 1
- full wave mode zero current switching (ZCS)
quasi resonant converter.
Because the collector current is zero during
switching (see fig 2 & 3), the only switching
losses occuring are due to the internal
discharge of the IGBT output capacitance at
turn-on. The discharge current is not
detectable externally, but the charging current
appears in figure 3 when voltage is re-applied
to the collector. Integration of the current
waveform shows that the energy stored in the
output capacitance of this IGBT is about 10llJ
at 400V.
b. Conduction: Figure 4 shows that the current
factor is low due to the discontinuous
operating mode of the quasi resonant
converter. For this reason it is important to
be able to use the switch at high current
Fig.1: FUll-wave mode ZCS quasi resonant
converter IG8T STGP10N50 10N500V.
density and this is the major characteristic of
an IGBT.
Figure 5 shows the IGBT saturation at high
current and its dependence on gate source
voltage. The current saturation threshold is
virtually independent of temperature (less than
10% between B5°C and 95°C) and conduction
time (unchanged between 1Ilsec and 5Ilsec).
An IGBT with a nominal current of 10A can
conduct more than BOA without saturation.
However, with a ZCS quasi resonant
converter, the maximum operating current is
limited by conduction losses as follows:
Considering the maximum switching
frequency (duty cycle < 50%) and the transfer
characteristics given in figure 6, the
conduction losses are:
Pcond < (1.4 Ipk/rc) + (0.11B Ipk2/4) watts
for a 30A peak Pcond < 40W - a maximum
realistic value for a TO-220 package.
Fig.2:Turn on switching circuit defined in figure 1
Rc = 50 Ohms
Vos = 100V/div
10 = 20A/div
t = 100nsec/div
--------------------------i,1 ~~~~~~~~~ ________________________3/_1_2
827
APPLICATION NOTE
Fig.3:Turn on switching circuit defined in figure 1
Vos = 100V/div
VGS = 5V/div
10 = 20A/div
Tease = 50°C
RG = 10 Ohms
t = 100nsec/div
.- • • • ,. •
r,d,.I:
flit
~
•
I
• ..
•
11111
..-
~f'li
~
r~
IIII
Iitl
1111
IJ'..
fill
~
-_._-
I'll
•• '11
1,1,
~
~ I.
.1-.,
":II!
I It I
Ult
•
I
11 '11 ','
"<[
'/
co
~
•
.
,.
"1\
•
kt'
16 V Single shot
-/
I~ f/
1J1
l8V
l6V
rj
I f/"
.,;,:
~
0-
~.::
. . ~. . . .\;><~/
L5
II1I
• ••
•
<::>~
>
I
1liii '
,
0'
•
~
till
Fig.4: Drain current and voltage wave form.
Circuit defined in fig. 1 (a snubber is used
in order to avoid voltage oscillations)
10 = 1Ndiv VOS = 100V/div t = 5msec/div
~
l4V
l2V
IOV
8V
~~
[2V IdiV.J
Fig.S: Saturation test circuit defined in figure 1
10 = 20A/div VOS = 5V/div Vos = 100V/div
t = 1msec/div
Fig.6: Characteristics of STCP10N50
Tj = 100°C
VOS(on) = 1.4 + (0.118 x 1) for VGS
c. Operating range and limits: When the
STGP10N50 operates over its full frequency
ra~ge the peak current in this converter should
be limited to 30A by the conduction losses. In
any case the RMS current is compatible with
die bonding:
at maximum frequency with 30A peak
IRMS < 15A.
As there are no major switching losses
(10 IlJ). a ZCS converter is able to operate at
several hundred kilohertz.
I RMS
=
15V
= ~ / 12. = Ipk / 2
-------------I..V ~~~~m~¥r::oo~:= ------------4/12
828
APPLICATION NOTE
3.2 IGBTs IN ZERO VOLTAGE SWITCHING
RESONANTCONVERTER&
a. Switching: The IGBT's switching behaviour
is analysed using the circuit in figure 7, a halfwave zero voltage switch (ZVS) quasi
resonant converter.
The intrinsic properties of an IGBT create
specific losses due to the current tail induced
by stored minority carriers, in spite of the "soft"
voltage switching. Contrary to bipolar
transistors, these carriers are not discharged
rapidly as there is no access to the base and
they induce losses when voltage is re-applied
after current turn-off.
Figure 8 shows current and voltage
waveforms in the IGBT during conduction and
after current turn-off. Figure 9 shows an
example of the evaluation of the turn-off
energy (E ct ) by integration of the current, time
and voltage.
Current tail losses were measured with
respect to temperature, switched current and
re-applied voltage. The results of these
measurements are shown in figures 10 to 15.
They show that turn-off losses are proportional
to dV/dt when current and temperature are
constant and proportional to the square of the
current when temperature and dV/dt are
constant.
- Current tail losses = Pct = K(dvldt,Tj) • 12 • f
- As K is proportional to dV/dt (ref: figures 13,
14,15 - gradients of the curves) and dV/dt
is proportional to I in such an inverter, the
losses can be expressed as:
Pct
= K'(Tj)
• 13 • f
where I = switched current.
As K' increases rapidly compared to Ti , the
maximum switched current must be strictly
limited and the heatsink sufficiently sized to
avoid thermal runaway.
Vc;s
V~s
'u
Fig. 7: Half wave mode ZVS quasi resonant
converter
Fig. 8: Drain current and voltage wave form.
Circuit defined in figure 7.
ID = 5A1div
VDSan = 1V/div
VDS = 100V/div
VGS= 10V/div
- - - - - - - - - - - - - l ? i j ~~~m~r::I!~n
------------5/12
829
APPLICATION NOTE
b. Conduction. In this type of converter, IGBT
conduction losses are not a constraining factor
due to the low average current. They can
easily be calculated by integration, (current x
voltage) figure 8.
c. Thermal balance. The circuit shown in figure
7 is used where:
switched current = Ip = 20A
dV/dt = 1500V/sec
The losses due to the current tail can be
calculated by subtracting the conduction
losses from the total measured losses
(thermal balance). An alternative method is,
to use the numerical integration as shown in
figures 9 to 15:
As the results are similar, the numerical
integration allows easy calculation of the
losses.
d. Operating range and limits. Considering the
IGBT switching its normal current, the
ton = 9.5 msec
Frequency
Eel
(Thermal balance)
Eel
(numerical integration)
6kHz
8kHz
566mJ
725mJ
420mJ
600mJ
:+:
,.d
-
- - .- r -
- -- - r- -
-
.....
/ V
7 /
~
t:7
I
Fig. 9: Energy
curve a:
curve b:
curve c:
curve d:
6/12
Qo
c
Qo
~
44-
\,b
1,1 "-I.I.--a
v- 'k~
k---c e -
>.
~200
'\
-
-
--
?c 100
t..
:J
f-
f\ ~ ~h
lV
evaluation circuit defined in fig. 7.
current tail (1 Ndiv)
drain voltage (100V/div)
(curve a) x (curve b)
curve c x dt
200
400
600 800
dV Idt V lJi-sec
Fig. 10: Turn·off energy Ect 10A switching
-------------------------~~~~~~~:~~------------~----------830
APPLICATION NOTE
>,
>,
f'
f'
jLJ
jLJ
(lJ
(lJ
c
c
(lJ
(lJ
300
44-
4-
'tI 500
E 400
2 300
o
I
E 200
:J
f-
100
200
100
o
500
1000
1500
eN/eit
o
V/jLsec
1000
1500
elV /elt
V /jLsec
Fig. 12: Turn-off energy Eet 20A switching
Fig. 11: Turn-off energy Eet 15A switching
>,
jLJ
>. jLJ
f'
400
f' 400
(lJ
(lJ
c
c
(lJ
(lJ
44-
500
300
44-
300
o
o
c
5 200
c
5 200
f-
f-
100
100
225
100
maximum switching frequency can be
evaluated with, for example, the following
conditions:
", J.LJ
1" 400
= 10A dV/dt = 500V/msec
losses = 10W
Ipeak
'c"
'"
...
Switching
(Safety margin
...o 300
....
AMps2
Fig. 14: Turn-off energy Eet - Tj = 80 0 e
Fig. 13: Turn-off energy Eet - Tj = 45°e
~
400
200
=
33%) ref:- figures 10-15
= 80 e operating frequency = 110kHz
Tj = 11 ooe operating frequency = 80kHz
Tj
100
(switched current)
100
225
400
Anps2
Fig. 15: Turn-off energy Eet - Tj=110oe
-----------------------------
0
This shows that using IGBTs in this
configuration is possible up to 80kHz with fast
IGBTs.
~~~~;~~~:oo~n
----------------------------7/12
831
APPLICATION NOTE
4. IGBTs IN RESONANT CONVERTERS.
The switching conditions of this type of
converter are dependent on the switching
frequency because they work in the
continuous operating mode. For this reason,
close to the resonant frequency, the
constraints on the IGBT are similar to those
of the quasi resonant converter in the ZCS or
ZVS mode, whereas above or below the
resonant frequency, a different switching
mode occurs.
4.1 Voltage excited resonant converter.
An example of a voltage excited resonant
converter circuit is shown in figure 16. Voltage
excitation requires a current load, i.e. a series
resonant circuit.
a. Operating above the resonant frequency
At switch-on: IGBTs operate in the ZCS mode
without dV/dt and therefore have negligible
losses.
At switch-off: Currentand voltage are switched
together; as dV/dt is generally reduced by
using an external capacitor, the turn-off losses
are limited to current tail losses.
Consequently, in this situation, the results of
the ZVS quasi resonant converter analysis
can be applied again.
Conduction in the on-state: The maximum
conduction losses occur close to the resonant
frequency. They can be calculated using the
ZCS quasi resonant converter analysis.
Considering that the maximum conduction
losses = maximum switching losses
maximum conduction losses =
(0.445 • I) + (0.0295 . 1}2 = 15W (for 16A)
maximum switching losses"" Eel' f
(for 8A see the curve in figure 15)
The corresponding operating frequency is
from 30kHz (f r) to 60kHz (2fr). As in the case
of the ZVS quasi resonant converter, the
maximum switched current must be strictly
limited and the heatsink sufficiently sized in
order to avoid thermal runaway.
16A
[\
BA
r
b. Operating be/ow the resonant frequency:
At switch-on: Current and voltage are
switched together. The losses are due to the
discharge of the IGBT's output oapacitance
and to the recovery of the diode on the other
IGBT.
v
An example:
Conditions: Device STGP10N05 IGBT
Tj
= 110°C maximum
dV/dt
=
1000V/msec
maximum peak current
= 16A (close to f r)
maximum switched current"" 8A (f "" 2fr)
8/12
- - - - - - - - - - - - - L."
832
Fig. 16: Voltage excited resonant converter
~~~;m~~:9::
------------
APPLICATION NOTE
The maximum losses can be evaluated as:
1/2 Vf(lpeak max/ 2 + IRMf dVdl
IRM
= diode peak reverse
current
At switch off the IGBT is operating in ZCM
without switching losses.
Conduction: the maximum conduction losses
can be evaluated as for the ZCS quasi
resonant converters because it is operating
in full wave mode close to the resonant
frequency.
An example:
Conditions IGBT = STGP10N50
dlldt = 300Alsec
V = 300V
Tj = 110°C
IRM = 16A
maximum peak current = 20A
maximum switched current"" 1OA
Considering:
maximum conduction losses = maximum
switching losses
maximum turn-on losses = 338J
maximum conduction losses = 24W
The corresponding operating frequency is
from 70kHz (f/2) to 140 kHz (q. Contrary to
the previous mode, there is no risk of thermal
runaway and the IGBT seems to be a good
alternative to SCRs in this type of high
frequency converter.
4.2 CURRENT EXCITED RESONANT
CONVERTER.
behaviour depends on the operating·
frequency.
a. Operating above resonant frequency:
When one IGBT is switched on there is
reverse recovery current from the diode of the
second IGBT through the capacitor. This
means both current and voltage are switched.
The maximum losses can be evaluated as:
1/2 f.V(IRM + 10)2 dVdl
where:
V = maximum switched voltage
IRM = diode recovey current
10 = maximum switched current
At switch-off: the serial diode recovery current
reverses the IGBTs current and its collectoremitter voltage. Because of this the reverse
recovery charge, Orr, of the series diode must
be kept lower than that of the internal PIN
diode of the IGBT as this would cause the
IGBT's diode to exceed its breakdown voltage,
and conduct the leakage current of the series
diode.
However, current tail losses can occur when
re-applying voltage during the off state, and
depend on the minority carrier lifetime versus
the delay between the diode recovery and the
positive collector voltage rise. The maximum
turn-off losses occur close to the resonant
frequency and are similar to those of ZVS
quasi resonant converters.
Conduction: The current flowing is continuous
and the duty cycle is 50%. The losses are:
"" 1/2 10 ' VOS(on)
An example of a current excited resonant
circuit is shown in figure 17. It is the duality of
the previous circuit shown in figure 16. The
current excitation requires a voltage load
giving a parallel resonant circuit. The switching
b. Operating below resonant frequer.lcy.
At switch-on: The IGBTs operate in ZVS mode
giving negligible switching losses.
At switch-off: Current and voltage are
-------------JFij ~~~~m&~:U!~~~
------------9/12
833
APPLICATION NOTE
switched-off. Consequently, losses can be
evaluated using the ZVS quasi resonant
converter results.
Conduction: The duty cycle is not dependent
on the frequency so the losses are similar to
those above.
5. DRIVE AND PROTECTION CIRCUIT.
The analysis of IGBTs in resonant converters
sh6ws that many different switching conditions
can occur. The circuit shown in figure 18 is
suitable for driving an IGBT gate as it provides
the following functions:
- Short circuit protection and current limiting.
- Adjustable sinking and sourcing output
current.
- Very low output impedence after turn-off,
masking the Miller effect.
6. CONCLUSION
This analysis shows that IGBTs are perfectly
suited to resonant converters when the turn
off switching is zero current mode. In this
situation the switching frequency can rise to
several hundred k Hertz giving a controlled
current several times its own nominal current.
IGBT's are an attractive replacement for more
traditional switching components already in
use in resonant converters. They offer the
following advantages when replacing:
SCRs: the IGBT provides high dV/dt immunity
and virtually no dl/dt limit, no tq and very
fast dynamic behaviour. It is very easy
to protect under both dynamic and
static conditions.
Bipolar Transistors: the IGBT offers very
easy gate drive.
Power MOSFETs:
IGBTs have a higher
current density.
BIBLIOGRAPHY
1) Commutation and stresses of switching devices
in static power converters.
Henri FOCH/EPE
2) Resonant
switches,
topologies
and
characteristics.
K.H.LlU, R.ORUGANTI and F.C.LEE IEEE
Power elect. spec. conference 1985.
3) Generalisation of resonant switches and quasi
resonant DC/DC converters
K.D.T.Ngo/IEEE Power elect. spec. conf.198?
4) An unified analysis of converters with resonant
switches
S.FREELAND and R.D.MIDDLEBROOK/IEEE
Power elect.spec.conf.198?
5) Power MOS Device Databook
SGS-THOMSON Microelectronics
6) SGS-THOMSON POWER TRANSISTOR
APPLICATION MANUALS
Fig. 17: Current ecited resonant converter
------------- '"
10/12
834
~~~m~r::oo~:=
-------------
APPLICATION NOTE
T12
R7
Fig. 18: Gate drive circuit.
11/12
---------------------------~~~~;~~~:~~--------------------------835
APPLICATION NOTE
APPENDIX.
DUALITY CONSIDERATIONS
OF AN ELECTRIC CIRCUIT
1.
Every voltage source (or load) has a capacitive
nature.
Every current source (or load) has an inductive
nature.
3.
2.
Connected source and load must always have
opposing natures:
4.
A voltage source becomes inoperative when the
output is open.
A current source becomes inoperative when the
output is shorted.
Every circuit has duality. The duality rules are
set out below.
- Capacitive source with inductive load
- Inductive source with capacitive load.
Current source, 1
Voltage source, V
--1.:!:.
T
[Ii =0
Loop network [Vi =0
Node network
Inductance L
Capacitance C
Capacitance C
Series resistance
Parallel resistance
Inductance
L
"'". j
n switches
n switches
time
time (unchanged)
Resonant Circuit
12112
Inductive lood
Capacitive load
Capacitive load
Inductive load
Series oscillator
Parallel oscillator
r== SGS.THOMSON _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - - - a.""'!1
836
1lj]~1:1i@~~~I!:'ii'Ii@Ill~l:i!I
...~
.,l SGS-1HOMSON
[R'A]D©OO@rn[lJ~©1J'OO@~D©~
APPLICATION NOTE
BIPOLAR JUNCTION TRANSISTORS, POWER MOSFETs
OR IGBTs IN RESONANT CONVERTERS
by P. Fichera
ABSTRACT
Resonant switch topologies operating on the
principle of zero-current and zero-voltage
switching are discussed. Their advantages
with respect to the conventional PWM
converter are shown.·
The main advantages and disadvantages of
some resonant structures are considered
AN465/0492
when the ideal active switch is either a bipolar
junction transistor (BJT), a power MOSFET,
or an insulated gate bipolar transistor (IGBT).
Practical examples of power semiconductor
choices in these resonant topologies are
given.
1/12
837
APPLICATION NOTE
1. INTRODUCTION
The main advantage of resonant structures
is the reduction of switching losses, and also
less stress on the electronic switch occurs
compared with PWM structures.
These two advantages (lower switching
losses, less device stress) are generally
paid for in terms of higher conduction
losses.
The purpose of this paper is to present the
elements that permit the most suitable choice
of power semiconductor to be made in some
types of resonant structures.
2. RESONANT SWITCH
The resonant switch represents the basic
element of converters with resonance or quasi
resonance. It consists of semiconductors and
LC resonant elements. Depending on the
configuration of the resonant elements one
can obtain the structures of fig. 2 1,2
A family of quasi resonant converters (ORC)
is obtained by simply replacing the
conventional chopper power switch with a
resonant switch as shown in fig. 3.
In each case there is controlled switching
either at turn-on in the ZCS or at turn-off in
the ZVS.
3. ZERO-CURRENT AND ZERO-VOLTAGE
SWITCHED QUASI-RESONANT
CONVERTERS (ZCS-QRC and ZVS-QRC)
3.1 ZCS-QRC
This configuration permits the switch to be
controlled at turn-on, while the turn-off occurs
with zero current. The switched current, Is is
a quasi-sine-wave and is reduced to zero at
turn-off.
Switching losses are due to:
1) turn-on switching (although these losses
are much lower in comparison to the PWM
converter),
2) internal discharge of the power
semiconductor output capacitance Coss at
turn-on (see waveforms fig.4) 7
3) rectifier diode switch-off.
v.
"
SOA
SOA
-----"7~,
ON
I')
I
,,
OFF
Fig. 1
2112
----~~
ON
.... ,
"-
' ....
I
I
I
v.
Hard switching
OFF
v,
Soft switching
------------- Iiii ~~t1r:rr~:~ -----....,..------838
APPLICATION NOTE
s
Fig.2
ZC-OR switch (thyristor)
ZV-OR switch (Dual thyristor)
V
Load
r--
IS't I
~_
/
V
I
__ J
\
V
,-
----..,
I
f
I
I L,
I
f
f
Cr I
: s(
T:
:-~_J
Fig. 3
ZCS-ORC
------------lIii ~~~~m~r::O!~J:
ZVS-ORC
-----------3/12
839
APPLICATION NOTE
3.2 ZVS-QRC
This configuration permits the switch turn-off
to be controlled; the turn-on occurs with zero
voltage (the capacitive turn-on problem of
ZCS-ORC is eliminated). This operating mode
is called "dual thyristor" because the switching
properties follow the duality rules of the
thyristor, i.e. spontaneous turn-on at zero
voltage and controlled turn-off [Ref.1].
The voltage across the switching device is
quasi sine wave and is reduced to zero at turnon. The only switching losses occur at turnoff as shown in the waveforms of fig.S.
4. WHICH SWITCH?
We are interested in analysing the behaviour
of the two quasi resonant (OR) topologies
when the active switch, S, is a BJT, a Power
MOSFET or an IGBT.
Table 1 shows the main features of each
power semiconductor (V > 400V).
Because the cost of a power semiconductor
varies with the chip-size the curve of fig.6
gives a cost analysis.
4.1 THE PHYSICAL LIMIT OF A POWER
BIPOLAR TRANSISTOR.
The presence of storage time, t s' limits the
maximum frequency of operation. Extra
losses are due to the presence of V CEsat(dyn)
at turn-on.
4.1.1 A BIPOLAR JUNCTION TRANSISTOR
IN ZCS.
The storage time, t s' limits the duration of td
between the time that the current is zero and
the re-applied voltage (td is in the order of t s).
The transistor voltage does not reach zero
instantaneously at turn-on (V CEsat(dyn)). This
phenomenon could increase the conduction
losses for a short time.
4.1.2 A BIPOLAR JUNCTION TRANSISTOR
IN ZVS.
The storage time, t s' limits the maximum
frequency of operation of the converter.
4.2 THE PHYSICAL LIMIT OF A POWER
MOSFET.
If there are no economic limits the Power
MOSFET is almost a perfect component for
many applications, but has two real limitations:
a) internal capacitance;
b) the presence of the body drain diode. This
diode is:
b.1) a good diode during its turn-on behaviour
(very low peak voltage)
b.2) a poor diode during turn-off.
4.2.1. A Power MOSFET in ZCS
The Power MOSFET is not adapted well to
ZCS operation because the body drain diode
is subjected to very hard stress due to the
recovery phenomenon.
The only solution when using a Power
MOSFET in the ZCS mode at high frequency
(> 20kHz) is to add a fast diode (D2) and a
Schottky diode (D1) as shown in fig.8
The maximum frequency will be limited by
the losses due to the Power MOSFET internal
capacitance.
4.2.2. A Power MOSFET in ZVS.
In this type of operation, as in the "dual
thyristor" operation, the body drain diode is
not subjected to stress after it's current
becomes zero.
In addition, the turn-on occurs at zero voltage
and consequently the energy stored in the
parasitic MOS capacitance is not lost. The
nature of a Power MOSFET makes it very
suitable for ZVS operation.
------------- 'V ~~~~~~r::oo~:: -----------4/12
840
APPLICATION NOTE
Vs
Is
[\ (
!
1,
C,
VS
10
I
I
I
I
I
I
Qh
I
I
II/I I
Fig. 4 ZCS-QRC (with bidirectional current switch) and corresponding waveforms.
/(J
i
l;7'
Fig. 5 ZVS-QRC (with unidirectional voltage switch) and corresponding waveforms.
5/12
--------------------------~~~~~~~::~~ ------~-----------------841
APPLICATION NOTE
VeE
84:
ADVANTAGES
D ISADVANTAGES
- Very Iowan-state
voltage drop
- Reduced silicon area
- Low cost
I)~e
- Cost of base drive
- Storage time (ts)
ADVANTAGES
VOS
V
D
,~
•
.~
- Low voltage drop is
- Cost
- In some cases
obtained with large
silicon area
dangerous
- Cheap gate drive
to use body
- Reduced turn-off
drain diode
delay time
- Anti-parallel bodydrain diode can be used
10
Va;,
c
,
E.
~
,
IH
f---
D ISADVANT AGES
ADVANTAGES
, ,"
-
DISADVANTAGES
- Lowvoltagedropat
high current density
- Cheap gate drive
- Presence of threshold
voltage Eo
- Current tail effect at
turn off
Ie
mm2/A
10
VeE
2V
()'?
~
0"
fI
~
\\'J .l 1.
-
. illUlfl1J1f U
-l:~
.pf>1.
L1-'
iir":ftr:rlJl
100
Vol1s
600
Fig. 6 Chip surface vs maximum rated voltage
6/12
--------------~----------- ~~~~~~~v~:~~
842
---------------------------
APPLICATION NOTE
zcs
zvs
I
I
1.o1·f--_~~1
'.
I
I
I
41
Presence of a dead time td which limits f max (td is in
the order of ts and depends on the base drive circuit)
"
- The storage time (t d) limits f max
V CEsat (dyn)
Fig_ 7 - The physical limit of Power Bipolar Transistors in quasi resonant circuits.
o
s
Fig.8 Disabling a Power MOS body drain diode
- - - - - - - - - - - - - - I:;i ~~~~m~¥r::~~J:
-------------7/12
843
APPLICATION NOTE
- t = 0.2 ms/div.
- VCE = 100V/div.
-Ie = SA/div.
- V9 = SA/div.
- Te = SO°C
- dV/dT = 400V/ms
Fig. 9 IGBT behaviour during turn-off in ZCS mode. The waiting time, td , is not enough and a current
peak, bigger than that due to the capacitive effect, appears due to the effect of the re-applied
voltage.
4.3 THE PHYSICAL LIMIT OF AN IGBT.
4.3.1 AN IGBT IN ZCS.
The IGBT has an economic advantage in
comparison to the Power MOSFET
(smaller silicon area for the same voltage
drop), but its turn-off is influenced by the
bipolar transistor section. At turn-off. the
minority carriers which remain in the basecollector junction of the bipolar section
increase the turn-off losses (current tail
effect). If the IG!3T turn-off is controlled
by only acting on the gate. it is necessary
to wait for a time, td' before re-applying
the voltage. otherwise extra losses
generated may make the device fail due
to thermal run-away. This time. td' must
be longer than the duration of the current
tail effect (in the order of 3-411S for a
1000V IGBT)8.
The frequency is limited by td' consequently
the IGBT in ZCS can attain a relatively high
frequency (around 120kHz). The losses due
to the internal IGBT capacitance in this
frequency range are smaller than Power
MOSFET losses. In fact. for a given current
rating the IGBT capacitance is much smaller
than the Power MOSFET capacitance. The
only other limitations are the conduction
losses.
844
4.3.2 AN IGBT IN ZVS.
The main limitation of the IGBT in this
configuration is the high switching losses due
to the current tail effect. A larger value
capacitor. Cr. acting as a snubber. reduces
dV/dt at turn-off and, consequently, turn-off
losses 5.
APPLICATION NOTE
SUMMARY OF THE PHYSICAL LIMITS OF SEMICONDUCTORS
TABLE II
- Storage time -> frequency limitation
- Storage time-> frequency limitation
BJT
- V CEsat(on)
-> turn-on losses
- Recovery of body drain diode
Power
MOSFET
- Capacitive turn-on losses at high frequency
- High voltage
- Conduction losses
- Deadtime -> frequency limitation
IGBT
- Turn-off tail problems
- Von-state
-> conduction losses
5. TWO PRACTICAL EXAMPLES.
5.1 The first example we are going to consider
is a single-switch ZCS-QRC with the following
characteristics:
1.SkW - SOkHz - 220V mains.
The switch current waveform will be
characterized by:
Because the time t2 < t1 = 8jls (conduction
time of the antiparallel diode), this time is large
enough if compared with the fall-time, t f of an
IGBT « 1 jls) or the storage time, t s' of a
bipolar transistor (1-3jls) there are no
problems in using these semiconductors.
t1/T = 0.4
IAVG = SA
Ipeak
, ............ _ ,
= 20A
./
IRMS = 9A
T
--------------------------~I ~~~~~~:~~
9/12
-------------------------845
APPLICATION NOTE
ANALYSIS OF DIFFERENT POWER SEMICONDUCTORS
(Devices selected with similar current rating)
BUF420
450/850V - 20A ETD Bipolar Junction Transistor) [54 square mm.
silicon area]. Conduction losses calculation gives P cond = 8.1 W.
TSD4M451
(450V/R DS (on) = 0.15 Ohms at 100DC ISOFET) [176 square mm. silicon
area] To obtain conduction losses comparable to BJT losses, it is
necessary to choose a large silicon area Power MOSFET (P cond =12.1 W).
The main disadvantages are:
1) turn-on capacitive losses 5.5W at 50 kHz due to the big chip-size
(176 square mm total silicon area)
2) extra conduction losses (3W) due to the use of a power Schottky diode
STGH20N50 IGBT 500V/20A) [32 square mm. silicon area] conduction losses
calculation 5 gives Pcond = 12W.
STGP10N50 (IGBT 500V/10) [16 square mm. silicon area]. Due to its over current
capability a 10Al500V IGBT can be used in this application. Conduction
losses calculation 5 gives Pcond = 18.6W.
CONCLUSION: IGBTs and BJTs are concurrent solutions. IGBT advantages are:
1) gate drive simplicity
2) saving in silicon area.
BJT advantage is due to the optimum ratio of conduction losses to device cost.
However the storage time limits the BJT frequency operation to no more than 70kHz.
5.2 The second example we are going to
consider is a single - switch ZVS-QRC with
the following characteristics:
300W - 150kHz - 11 OV mains (± 20%):
The switch current waveform will be
characterized by:
(t 1+t2)/T = 0.6
IAVG
= 2A
Ipeak = 10A
IRMS = 3.65A
Vs(peak)
= 750V
(max.)
T
------------- ""
10/12
846
~~~~m&~:oo?:=
-------------
APPLICATION NOTE
ANALYSIS OF DIFFERENT POWER SEMICONDUCTORS.
(Devices selected with similar current rating)
BUF410
(4S0/8S0V - 10A ETD bipolar junction transistor). The storage time ts
(1 - 3/1s) is comparable with t1 + t2 = 4/1s. The use of a BJT at this
frequency of operation is not possible. For the ETD BJT technology
an upper frequency of operation is around 100kHz.
STH9N80
(800V/R DS (on) = 1.S Ohms at 100°C Power MOSFET). Conduction loss
calculations give Pcond = 20W. Turn-off losses are negligible. The
Power MOSFET body drain diode is not subjected to any stress and
can be used as an anti-parallel diode.
STGH8N100
(1 000V/8A IGBT). At Iswitch = 1OA and dV/dt ~ 1OOOV//1s the IGBT turnoff losses can be evaluated at around 0.6-0.7mJ/Hz. It means roughly
10SW at 1S0kHz only for turn-off losses. Conduction loss evaluations
give Pcond = 4.6W.
CONCLUSION: For this single-switch application, the Power MOSFET is the most
suitable choice.
At the given frequency of operation and duty
cycle one obtains: t1 + t2 = 4 /1s
ZVS - ORC:
SUMMARY OF EXAMPLES
Bipolar J unction Transistor (f < 100kHz)
The physical limit of the semiconductors
examined and the examples taken into
consideration show that in a single switch
ORC a correct choice of the switch is the
following:
(f
IF
ZCS - ORC:
Bipolar Junction Transistor (f < 70kHz)
Power MOS (f < 20kHz).
Higher frequency of operation could be
obtained disabling internal body drain diode
or using a FREDFET.
IGBT (f < 120 kHz)
IF
=
O.S to 1MHz)
IGBT (f < 20 - 30kHz)
Power MOSFET (0.5 MHz -1 MHz)
CONCLUSION
Each power semiconductor we took into
consideration shows physical characteristics
that limit its operation in single switch quasi
resonant converters.
In particular the bipolar solution is acceptable
for both ORC topologies at frequencies lower
than 100kHz. The power MOSFET solution
is disadvantageous in applications at high
- - - - - - - - - - - - ! i i i ''],! SGS·lltOMSON
~O©L1I@~~~!:1i'L1I@IIIIO©®
11/12
------------
847
APPLICATION NOTE
RMS currents such as those in discontinuous
ZCS-QRC. Despite this, power MOSFETs are
most suited to the ZVS-QRC due to their fast
switching times and the possibility of using the
body drain. diode even with their inferior
performance.
The IGBT solution is today the most popular
for resonant and quasi resonant applications.
However in ZCS-QRC where its use seemed
to permit very high working frequencies, the
dynamic dV/dt phenomenon may lead the
device to fail due to thermal runaway. This
can be overcome by careful design and the
use of an efficient heatsink.
References
1) Yvon Cheron, "La commutation douce dans la
conversion statique". Edition Technique et
documentation LAVOISIER - Paris.
2) Fred C. Lee, Wojciech A. Tabisz, Milan M.
Jovanovic, "Recent developments in high
frequency Quasi-Resonant and Multi-Resonant
Converter Tecnologies". EPE Aachen, 1989 pp.401 - 410.
3) J.P.Ferrieux, F.Forest, P.Lienart, "The insulated
gate bipolar transistor: switching modes". EPE
Aachen, 1989 - pp.171 - 175.
4) J.M.Bourgeois, B.Maurice, "Losses of insulated
gate bipolar transistor in H.F. Resonant
Converters". IEEE Industry Applications Society
Annual Meeting, 1989 - pp.1197 -1204.
5) P.Fichera, "Analyse des pertes dans un IGBT'.
Seminaire Technique 22 Septembre 89,
Grenoble (SEE) - pp. 3.1-3.12.
6) Power Transistors - SGS- THOMSON
Application Manual- 1st edition - pp. 91 - 97.
7) K. Rischmuller, "Improve efficiency of high
frequency power
conversion designs"
Proceedings of P.E.C. Californill., February 1990.
8) R.Letor, M.Melito, "Safe behaviour of IGBTs
submitted to a dVldt". Power Conversion Munich
June 25-28, 1990 (samE) proceedings).
9) J.P.Arches, N.Bonnet, F.Oms, D.Revel, J.Roux,
"Optimisation de la commutation de transistors
Mos haute-tension dans un onduleur a
resonance a 500kHz". L'electronique de
puissance du futur, SEE, Bordeaux 1-13 juin '88.
-------------- '1i ~~~;m~~:~~:: -------------12112
848
~ SGS-1HOMSON
It...,
~O©OO@~[b~©uOO@~O©~
l
APPLICATION NOTE
AN ANALYSIS OF LOSSES IN AN IGBT
by P. Fichera
1. INTRODUCTION
Insulated gate bipolar transistors are now
being used in a variety of switching
applications. These range from automotive
ignition, where they replace the mechanical
contact breaker, to electric motor drives,
where they provide an economic, easy to
drive. chopper switch with high voltage
capability.
More recently work has been done in using
these devices in various types of power
supplies.
They are attractive to use due to the high
AN466/0492
impedance input, a MOS gate that requires a
mimimum of only 8V and microjoules of
energy to turn it on and off and the bipolar
nature of the output that makes them capable
of controlling high current densities.
To obtain the optimum performance from
IGBTs it is necessary to understand the limits
imposed by the structure of the device and
their particular operating conditions.
This paper looks at the use of IGBTs in
chopper circuits and shows how to evaluate
the losses during switching and conduction.
1/7
849
APPLICATION NOTE
2. LIMITING FACTORS FOR IGBTS IN
CHOPPER CIRCUITS
Chopper circuits operate at frequencies
determined by the nature of the application
and of the power switch employed to control
the current flow. As is the case with Power
MOSFETs, power is dissipated in IGBTs at
turn-on of the device, during conduction and
at turn-off. The major difference between
IGBT and Power MOSFET switching losses
occurs in the turn-off switching behaviour.
Figure 1 illustrates the typical losses for an
IGBT used in a chopper application.
2.1 TURN-ON LOSSES
It is not sufficient to know the rise time, tr, of
the turn-on current. The free-wheeling diode
used in conjunction with the IGBT, figure 8, is
responsible for a large amount of the losses
as a result of its reverse recovery current.,
Within a given application it is necessary to
know the (dID/dt)on for this diode in order to
evaluate the reverse recovery current, I RM.
Once IRM is known it is possible to calculate
the turn-on losses.
2.2 CONDUCTION LOSSES
The following simple expression shows how
to calculate the conduction losses.
where:
Pon
= on-state power dissipation
IRMS
= RMS current value for the application
IAVG
= average
current value of the
application
Eo,Ro = are parameters defined by the IGBT
output characteristic Ie' Vee - see
figure 2.
= abscissa of the intersection between
Eo
the tangent to the output
characteristic calculated at Ie = 10 and
the Vee axis.
Ro
= inverse slope of the tangent to the
output characteristic curve Ic' VCE'
calculated at le=lo.
The area B in figure 1 illustrates these losses.
-
I
.~
/
VGE =15V
'--- T =100'C
j
/
Ro
y
J
10
VERTICAL/DIV
2A
HORIZONTAL/DIV
500rN
V
/
v.
Conduction
Fig. 1 - Typical IGBT losses
217
0
STGPlON50
Eo = 1.3V
} AT 100'C
RO = 015 Ohl')s
Fig. 2 - Output characteristics of STGP10N50
- - - - - - - - - - - - - l i f i ~~~~~~~:::: - - - - - - - - - - - - 850
APPLICATION NOTE
2.3 TURN-OFF LOSSES
5 CALCULATING CONDUCTION LOSSES
Calculation of the turn-off losses in an IGBT
requires more information than just the fall
time, t 1 . On its own it leads to erroneous
results. It is necessary to know how other
parameters influence these losses.
Most care has to be taken with the current tail
phenomenon of the IGBTwhen it is operated in
hard switching. Two parameters define the
current tail: its amplitude, It, and its duration, tt.
When calculating conduction losses at 1aaoc
it is better to base the calculation on the output
characteristics of the IGBT (Ie versus Vee) at
A) THE INFLUENCE OF THE SUPPLY
VOLTAGE ON TURN-OFF LOSSES.
The supply voltage and the current tail
amplitude are directly proportional. However,
the duration of the tail remains almost constant
when the supply voltage is varied.
8) THE INFLUENCE OF DV/DT ON THE
TURN-OFF LOSSES
A low dV/dt value at turn-off (imposed by an
external circuit, e.g. a snubber) reduces the
current tail amplitude, It. The tail duration does
not change when dV/dt is varied.
C) THE INFLUENCE OF TEMPERATURE
ON TURN- OFF LOSSES.
Operating temperature affects the duration
and amplitude of It and tt. Experimental
analysis shows that both increase in value by
the same percentage as the temperature
increases.
D) THE INFLUENCE OF THE GATE
RESISTANCE, Rg(off)'
The gate resistance does not affect the current
tail. Varying Rg(off) controls the slope of dVI
dt at turn off and consequently can give some
reduction in the turn-off losses. A minimum
value of Rg(off) is required to prevent
oscillations occuring during turn-off (as is the
case with power MOSFETs).
a given Vge'
Table 1. Additional parameters required to
calculate turn-off losses in IGBTs.
V
- the re-applied supply voltage
dV/dt - slope of re-applied supply voltage
Tj
- junction temperature
Rg(01f) - gate resistance at turn off.
3. SAMPLE CALCULATIONS.
It is possible, using the curves given in figure
9 and the energy curves characteristic of
figure 1a for different operating conditions, to
calculate the switching losses for a given set
of conditions. This in turn allows the maximum
operating frequency for the IGBT to be
calculated.
The basic circuit in figure 8 shows the
configuration used for the STGP1 ON50 50aV,
1aA IGBT and its switching waveforms.
3.1 CALCULATION OF THE TURN-ON
LOSSES AT T j = 100'C.
The value of the gate resistor during turn-on
is 47 Ohms. USing the graph in figure 9a this
gives a value for dl D/dton of 100Al!ls. As the
IGBT controls dlldt it follows that the recovery
current of the free-wheeling diode can be
determined from the diode datasheet (graph
of IRM versus dl/dt is shown in figure 9b). This
gives a value of I RM = 10A.
Applying the formula for the turn-on losses:
Wt(on)
= 112
Vsupply
(10
+ IRM)2 • 1/(dl/dt)on
Wt(on) is calculated to be: Wt(on)
= O.4mJ
3/7
--------------------------
~~~~~~~~:~~-------------------------851
APPLICATION NOTE
3.2 CALCULATION OF CONDUCTION
LOSSES AT Tj = 100o e.
The value of the parameters Eo and Ro have
been evaluated from the graph of Ie versus
Vee shown in figure 2.
Eo
Ro
= 0.15 Ohms
Pon = 9.6W
3.3
CALCULATION OF THE TURN-OFF
LOSSES.
(500V/~s)
Using Rg(Off) = 47 Ohms and switched current
of 10A again
W\(off) =
= 1.3V
Taking 'AVG to be 3.5A and I RMS as 5.8A, P on
can be calculated using the equation from
section 2.2
A. High dV/dt
B. LOW dV/dt
0.3 mJ/cycle.
Summarising these values show that the total
power dissipated is dependent on the
operating frequency.
Accepting that .the maximum power that can
be dissipated from the device at 1oooe is 40
Watts for this device in a TO-220 package, it
is simple to calculate that using high dV/dt the
IGBT has an upper limit of operation of 20kHz .
while with low dV/dt operation is possible up
to 40kHz.
(2500V/~s)
Using a value for Rg(off) = 470hms and taking
into account the dV/dt curve of figure 10 a;
at a switched current of 10A the energy
dissipated in turning off is
Wt(Off) =
Ie
1.1 mJ/cycle
Fig.4 - Influence of supply voltage on turn-off losses
Ie
low dVNt
Fig. 3 - Turn-off losses
4/7
Fig. 5 - Ov/dt effect
------------------------~~~~~~~~::=--------~-------------852
APPLICATION NOTE
Ie
Fig. 6 - The effect of temperature on It and
~
v
Ie
Rg
Vcr
Fig. 7 - The influence of gate resistance
---__
1---------
D89AN30 1-04
IH is very low with respect to the triac nominal
current (in the cold condition the maximum value of
IH guaranteed by the specifications never exceeds
a hundred mA, even for very large triacs; in the
warm condition, the value of IH decreases considerably). Therefore, its influence on the operation as
a switch does not have to be taken into consideration, as a general rule, in practical applications,
except in operating conditions in which the load
temporarily offers a high impedance at an instant
at which the effective supply voltage is low.
The delay in the rise of the current following the
application of the control does not exceed a few
microseconds. But, to achieve steady firing, current
IG must be applied for a sufficiently long time.
The gate pulse duration must a least be long
enough for a sufficient charge to be injected into
the gate region. The minimum duration !J.. t of a
rectangular-wave pulse of current IG having just the
specified value IGT min is on the order of about
twenty /-ls.
This required duration decreases when the value
of IG increases.
_4/_22_ _ _ _ _ _ _ _ _ _ _ _ _ ~ i~@mgl'~9~
868
______________
APPLICATION NOTE
If current Ic in the load does not immediately build
up (inductive load) it is necessary, in addition, to
hold the gate current until the load has given passage to a minimum current IL. The 21atching current" is equal to, or higher than, iH, depending upon
the respective polarities of A2 and G. It corresponds
to point E on the conducting-state characteristic
(Figure 4).
Current IG applie dto the gate to fire the triac with
either polarity of the supply voltage, can indifferently be of positive or negative sign with, however,
triggering abilities which, for average-power triacs,
can be somewhat different depending upon these
polarities'. There are four possible cases which are
determined in accordance with four "triggering
quadrants" defined in Table 1.
Figure 3 : Waveforms in a gate-controlled triac with resitive load.
IG
CONTROL CURRENT
o~--~~------------------~~--
____ ______________ ____
~
~
tl
t1
v
VOLTAGE ACROSS THE TRIAC
~Va
I
"-
/
\
'Ua /
/
/
\
/
/
o
l------t~~~~~~~~v2T~~~~~~~~~~~--------------Jf~---r.
V'T
.\
l\
: \
I
1\/
:
•
/
/
I
I
I
'-,-/
I
I
I
•
I
I
I
CURRENT IN THE TRIAC
I
I
I
I
I
Conduction
ofTh2
I
: Holding current
~OfTh2
o
~
____
+-~~
____________ __-L______
~
~~
____________
\
\
Conducted state
(Vr and IH exaggerated for clearness of figure).
,,
,
--
,
I'
,.
~~~
,,
,
__
I
'
Blocked state
D89AN3Dl·D5
Certain series are not specified in quadrat IV as regards firing current.
5/22
- - - - - - - - - - - - - ~ ~~~@m~~~~©~ - - - - - - - - - - - - - 869
APPLICATION NOTE
Figure 4 : Static Characteristics with IG = IGT (exaggerated around zero).
Steady firing pomt
________~~----------------------~~v
D8gAN301~06
Load straight 1/R1 : ensures steady firing (iT> iL).
Load straight 1/R2 : does not ensure steady firing (iT < IL).
Table 1.
Polarity
with Respect
to A1
Triggering
Quadrant
of A2
ofG
IGT
+
+
Low
0.11
+
-
Medium
0.111
-
-
Medium
0.1
O.IV
_61_22_ _ _ _ _ _ _ _ _ _ _
870
Firing Conditions for
Small Triacs
+
High
IL/IH
~
1
2 to 5
~
1
1.5to 3
..r=-=
..,1 SCiS-mOMSON
~in©Ill@Il(~~©II00©U\lJD~ -------------~-
APPLICATION NOTE
1.4. VARIOUS MODES OF CONTROL OF THE
TRIAC
cuits, the control by half-wave trains offers substantial advantages when, in addition, the firing of the
triac is allowed to occur only close to the point
where the voltage across the triac goes through
zero (i.e. just after zero crossing of the current).
Since the triac will next stop conduction also at the
zero crossing of the current, this mode of control
always ensures a whole number of complete "conducting" half waves (Figure 5 a). On the other hand,
triggering on going through zero eliminates any
sudden variation of the current flowing through the
load, which avoids parasitic radiations and strains
in the triac and user circuits. With this type of
control, the mean power allied to the load is merely:
On Figure 3, instants t1 of gate current application
were supposed to occur randomly with respect to
input voltage Va. This operation is similar to that of
an electromechanical relay; the difference, however, is that the triac switch becomes conducting at
the precise instant (to within a microsecond) of application of the control, and blocks again, after the
control has been removed, at the precise instant at
which the current drops below IH (i.e. practically to
zero with respect to the nominal current).
This precision can be made use of to carry out the
control in exact synchronism with voltage Va, in
order to sample periodically the voltage applied to
the load over intervals of several half waves * (control by half-wave trains), or over half-wave fractions
(control by conduction angle). By causing the respective durations of the "conducting" intervals to
vary with respect to the "blocked" intervals, a variation of the power applied to the load is achieved.
P AV. =
n Ta
2 T e VRMS olRMs
(1 )
with: n = number of "conducting" half waves in each
sampling period Te.
T a = period of the mains current (20 ms in the case
of a 50 Hz mains).
VRMS, IRMs = rms values of the input voltage and
current.
Whenever permitted by the inertia of the user cir-
Figure 5 : Modes of Control of the Triac in Syncronism with the Mains Voltage (theoretical wav.eforms on resistive load).
1-
\/0 .... _
Triac controiled by
~ompletc hal!- waves
I
I
I
I
I
I
I
I
I
I[
Ucom..-1~I'=======::
Control
sJ~na\
The tnac is triggered al !he Z2ro voltage pam',
and turns off at the lCro cur rent point
D89AN301·07
Triac, controlled by
conduction <1nC;le
adjustemenl
of ""
1,J2 ~ duration of a half wave
~
~
n· = phase shift of the trigger signal
~
trigger signal duration
Trigger signals in phase with the
mains voltage
D89AN301·08
• The term
«
half wave" designates each (positive or negative) half of the mains current alternating wave.
7/22
---------------------------- ~~~~@~~~~~©~ ---------------------------·871
APPLICATION NOTE
The fineness of adjustment of PAV obviously improves when Te increases with respect to Ta. A
sampling period of 1 second permits adjustment in
steps of 1/100. If the load does not not stand any
dc component, it is necessary to add to the circuit
a system of variation per couples of half waves (full
waves) requiring, for the same fineness of adjustment, a double sampling period.
with a phase shift (1t ex) with respect to the beginning of each half wave. Figure 5b illustrates the
principle of this control, with waveforms obtained
on resistive loads as well as a simple example of
practical application. The conduction angle of the
current is ex and the mean applied to the load is fairly
equal to:
In many cases, however (for instance for light
dimmers, for the control of highly loaded low-i nertia
motors or for regulators with low time constant), it
is necessary to sample the power at the frequency
of the ac supply mains. To do this, it is only necess,
ary to control the gate by current pulses occuring
P AV. =
.1
(VRMS)2
1t
RL
f
ex sin 2 ex. d ex
0
or P AV. = 2 ex+ sin 2 ex (VRMS)2
21t
R
Figure 6 : Triac Power Control.
8
Prmcip[p. of power control hy hrllf·w<1ve tmins (hurst contron
,'1,
1\
,f'I
I
,
,
I
I
I
I
I
,
,,
I
I I
I
,...''
,
I
I
I
'J
J
I
I
I
n' conducting hatl waves
I
I
Te
fa I
I_----------~~----------~~
RMS
l
I
12
PAV/
,
,
I
10
8
\
4
2
o
--V
30'
-7
,
~
60'
0,8
0,6
V
"b2:........
P1800
1
V~
\
6
o
D89AN301·09
,,
I
0,4
--. --- ~--.
90 •
120'
150
.
0,2
180
-
-
• Conduction
angle
In ful1line (right-hand scale) = Relative change of the power delivered to a resistive load RL
(operation at constant input power).
.
In dotted line (left-hand scale) = Change in the ratio IpliRMs of the peak current to the effectIVe
current on resistive load RL (operation at constant delivered current).
_8/_2_2_ _ _ _ _ _ _ _ _ _ _ _
872
OB9AN301-10
:.v ~i§@m~m~alj ---------------
APPLICATION NOTE
Figure 6 b shows the change in the delivered power
P as a function of conduction angle (1., when the
input power is kept constant. As can be seen, the
relationship between P and (1. is highly non-linear.
To obtain a linear relationship between the mean
vol-tage on the load and an adjustment voltage Vr,
the latter must act on (1. with an inverse law.
Figure 6 b also shows (in dotted line) the curve of
the change in peak current Ip as a function of the
conduction angle with left kept constant, i.e. for a
constant power in the load. The curve clearly shows
the dangerous condition which exists in case of
operation at low power with a low conduction angel
when Ip exceeds the permissible repetitive surge
current.
.
1.5. OPERATION ON INDUCTIVE LOAD
In the case illustrated by figure 3, where the triac
operates on a pure resistive load (cos .'1/l
UljJD©i&(g~~~©'iTIB(QJmJ©®
19/22
--------------
883
APPLICATION NOTE
Figure 19 : Switching with Triacs on the Primary (a), or Secondary (b) of a Transformer.
a
-b
DB9AN301-29
Figure 20 : Diac Controller with Progressive Energization of the Transformer.
Fast-acting fuse
220V
-Pt:::r
S
~
Application
of power
DB9AN301-31
20/22
~ SGS·1HOMSON
~O©l1I@~[lJ<©1l1lI@ilD©® - - - - - - - - - - - - - -
-----~-------- ....."
884
APPLICATION NOTE
CONCLUSION
The triac is a AC switch which changes from the
blocked to the conducting state when a current or
current pulses of any polarity are applied to the
control electrode. Turn-on of the device can be
achieved with precision in synchronism with the AC
input voltage, while turn-off occurs when the current
passes through zero following the control signal
removal.
This permits setting up systems for the switching,
variation or regulation of the power delivered to any
load (lamp, resistor, transformer, motor). Provided
an appropriate heat sink keeps the junction temperature below the specified maximum value, the
service like of the triacs used in these systems is
almost unlimited.
Owing to the remarkable overloads capabilities of
the triacs, users will but exceptionally experience
difficulties as regards the reliability of these devices.
We have insisted on the various cases of applications requiring particular precautions, in order to
give all the information necessary to solve possible
problems in the best possible way. Appendix I sums
up all useful instruction, in relation with the parameters specified by the individual datasheets.
21/22
IloiJO©OO@~~~©li'OO@illO©i\l - - - - - - - - - - - - - -
_ _ _ _ _ _ _ _ _ _ _ '="= SGS-THOMSON
""'11
885
APPLICATION NOTE
APPENDIX
RELATIVE CONSIDERATIONS TO A FEW TRIAC UTILIZATION PARAMETERS
Parameters
1) Thermal Stresse
ITRMS: Triac Nominal Current
(rms current at 80°C case
temperature).
RlhQc): Junction/case Thermal
Resistance; see Sub-section 2.1
To be Particularly
Consideredfor
Continuos Operational ITeff in
High Ambient Temperature tamb
Permanent Operation at Small
Conduction Angle, with High Peak
Currents
Precautions to be Taken
(together or separately)
Suitable Heat Sink
Its thermal resistance with respect
to tamb should e at the most:
Tj - tamb - Rthdc) - Rtj(cd)
P
Operation with High-frequency ac
Input Voltage
With:
P = Dissipated power: fig. 3, 4
Tj = max. permissible junction
temperature: see Sub-section 2.1
and 4) below (untimely firing)
2) Current Stresse
ITSM: non repetitive peak overload
current (peak current
permissible during one period only)
di/dt: critical rate of rise of the
current at turn-on; see Sub-section
2.2
- Capacitive Load (or capacitor
across the triac terminals)
- Utilization on Incandescent
Lamps (high current inc old
condition)
- Windingson Saturable Core"
transformer primary (magnetizing
current)
- Risk of Short-circuit on Load
- Risk of Untimely firing occuring
on overvoltages (see 4) below
- Inductive Circuit (addition of L
higher than a few hundreds of
[lH); see figure 13
- At least 30 Q in series with
possible capacitor
- Triggering at zero voltage
point
- Triggering through gate pulse
of steep leading edge, with
peak much higher than specified
IGT
- Non-delayed fuse rated for less
than 2/3 of triac ITeff
3) Holding of Firing
Instantaneous output value
(current in load) below which the
triac turns off (IH) or does
not steadily fire (IL) after
the removal of the gate current
(see Sub-section 1.3)
a) at End Conduction: holding
Current IH
b) at Beginning of Conduction:
Latching Current IL
- Highly Variable Loads (low
currents)
- Highly Inductive Loads (see
fig. 7)
- Presence of an LC Resonant
Circuit (for instance, underdamped
interference filter)
- Long trigger pulse or long trains
of closely spaced pulses
- RC network across triac terminal
(see fig. 15)
- Triac of Low IH (sensitive series)
4) Untimely Firing
a) Firing through breakower
(through momentary
over-shooting
of the maximum specified voltage
VDMW; see sub-section 2.3)
b) Firing by dv/dt (critical rate of
rise of the voltage in the blocked
state-parasitic triac firing, without
gate signal, by a voltage wavefront
acting on the triac terminals
c) Commutating dv/dt (critical
rate of rise of the voltage at
commutation-see fig. 11);
spontaneous
triac re-firing through the
voltage slope on inductive load at
the end of a current half wave
- High Mains Interference
- Atmospheric Interference
- Commutator-type Motors,
intermittent contacts
- Under-dimensioned heat sink
- High Input Voltage Frequency
- Forced commutation,
rectifiers switch inductive load
- Limit Junction Temperature
(largely dimensioned heat sink);
- ALTERNISTOR
- RC Network on Triac Terminals
22/22
--------------------------- ~~ii@~~~~~~~--------------------------886
APPLICATION NOTE
APPLICATION NOTE
THYRISTORS AND TRIACS, AN IMPORTANT PARAMETER:
THE HOLDING CURRENT
By E. Leblanc
The purpose of this note is to familiarize the user of
a triac (or a thyristo r) with the param eter IH : hypo·
static current or holding current.
After a short definition, we will illustrate the importance of this parameter by concrete examples. Then
we will describe how to measure it and finally its variation with the conditions of use and the sensitivity of
the components.
DEFINITION
To keep an electromagnetic relay in the conducting
state, it is necessary for a minimum current to circulate in its coil. Otherwise it would return to the
blocked state. The same phenomenon can be observed for a triac. This minimum current which
keeps the triac conducting is called the hypostatic or
holding current (figure 1).
In all cases we speak of triacs. However, the statements are also valid for thyristors.
Figure 1 : Controlled by gate pulse IG, the triac is fired and a current IT flows through it, fixed by the main
circuit. When the current IT falls below the triac hypostatic current IH, it is reblocked.
G
: Reblocking of
the triac
D89AN302-01
AN302/0289
116
887
APPLICATION NOTE
APPLICATIONS
Example 1 : Light dimmer (figure 2).
Figure 2: Dimmer with Interface Suppression Coil and Capacitor (RFI filter).
Load
220 V
C
~
nlerference suppression
LCfilier
D89AN302·02
Figure 3 : Current in the dimmer triac:
The interference suppression filter produces oscillations. If 10> IH (as in the figure) the triac remains fired. But if 10 falls
below IH, the triac will be blocked.
If the coil is a poor quality one, the oscillation is insufficiently damped. If the current in the triac falls
below the hypostatic current, IH, this results in untimely blocking of the triac. It is fired at the next current pulse IG and is blocked again. The lamp flickers.
This is known as the "flicker effect".
How can it be prevented? By eliminating the cause,
i.e. using an appropriate interference suppression
filter which does not produce extensive oscillations,
and then by choosing a triac with a lower hypostatic
current IH.
SGS-THOMSON Microelectronics has developped
a triac specially designed for applications where a
low hypostatic current IH is required, the BTA 06 400
GP.
This device is specified with a maximum holding current IH of 13mA in both current flow directions.
Example 2 : Motor Control (figure 4).
Figure 4 : Control of a Small Motor by Triac.
o
Induction motor
_2/_6_______________________ ~~L
888
The designer wishes to control a small high-impedance motor (25000hms for example) by triac. He obtains the parts and an operating manual and carries
out tests. The circuit operates smoothly. After one
year of production, the manufacturer complains of
low torque in his motor and blames the triac. What's
happened?
~i~@~~~~~~~~-------------------------
APPLICATION NOTE
Figure 5 : Voltage Accross the Triac and Current in the Circuit of Figure 4.
I~'"
I
v
I
I
'
\
,
\
\
I
I
I
\
~IH+
,
,
\,
,
"
~IH--
T
I
\
I
\
, --'
I
~
D89AN302·05
The circuit was designed with a type of triac whose
maximum specified holding current IH was 50mA.
But the components used for the tests were more
sensitive: IH + = 13mA and IH - = 8mA and the designer based his choice on these results. After a year
of delivery, the component manufacturer continues
to deliver parts which are in conformity with the specification but less sensitive: IH + = 40mA and IH - =
20mA. The conduction time decreases (figure 5),
the dissymmmetry is greater, a DC component appears and the motor loses torque.
To prevent this kind of difficulty, when designing the
circuit it is thus necessary to take into account not the
typical value of the sample used but the maximum
value specified by the component manufacturer.
Example 3 :
Take the diagram of the previous example (figure 4), the control of a small high-impedance motor
by triac.
This time, the designer selects a triac with a lower maximum specified holding current, IH. The motor seems to
operate without problems. The motor is meant for
mounting on out-door equipment. The equipmynt is installed in summerandworkswell. But in winter, the fault
described above occurs. What has happened? The
designer studied the operation of his circuit at an ambient temperature of 25°C. But the holding current IH
varies with the temperature: when the temperature decreases, the holding current increases (we will study
this variation in paragraph 4.6) and the phenomenon
described in example 2 occurs.
Thus when designing a circuit which is to operate at
low temperatures, it is essential to take into account
the corrected value of the holding current and not its
value at an ambient temperature of 25°C.
------------'-----..r.=-=
""11
These three examples illustrate the importance of
this parameter and the different problems it can
cause in a circuit if it is insufficiently known.
If the device is to remain in the conducting state, it
is imperative that the circuit in which it is used ensures a current higher than the holding current IH of
the device.
In our data sheets, for all the types of triacs, the hy,
postatic current IH is specified as a maximum value.
A suitable triac should then be chosen whose holding current IH is lower than the minimum value of the
current in the circuit, if the triac is to remain in the
conducting state; make the necessary corrections
to compensate for temperature variations.
MEASUREMENT OF THE HYPOSTATIC
CURRENT IH
Pushbutton P is used to fire the triac. The value of
current IT is chosen much higher than the latching
current. By increasing the value of the variable resistor R, current IT will decrease. The value of the hypostatic current IH is the value of IT read just before
the triac is blocked.
The hypostatic current IH is always measured with
the gate unconnected, i.e. disconnected from the
trigger circuit. Only sensitive thyristors (IGT ~ 500f,lA)
are measured with a 1kohm resistor connected between gate and cathode.
Forthe measurement to be regularly repeatable, the
triac should be suitably fired. The following rules
should be observed:
- Before decreasing current IT, it should be equal to
at least 5 times the triac IL current.
3/6
SGS.ntOMSON
Il:im©OO@~~Il:©"JOO@~~C©ill---------------
889
APPLICATION NOTE
= 25mA.
Example: BTA 12 600C
Example: BTA 12 600C : IH max
IL typ (01 and III) = 20mA thus IT = 500mA.
Depending on the production batch, IH can vary.
However, the dispersion remains below the limits
specified in the catalogue.
- if the IH current is measured by pulses (automatic
testers, for example), the triac should consult for at
least 500IJS before performing the measurement.
For a triac, the IH current has two values: (IH +)
when electrode A2 is positive with respect to electrode A 1 and (IH -) when electrode A2 is negative
with respect to electrode A 1. In the documentation
only one value is given for both quadrants. This
value is always the maximum value.
To give an idea of this dispersion:
- Sensitive triacs : IGT (01) 5mA (type T)
2mA::; IH ::; SmA (Specified IH max : 15mA).
- Standard triacs : IGT (01) 50mA (type B)
SmA::; IH ::;40mA (Specified IH max: 50mA).
Note: The minimum value of the IH parameter is
never specified in the data sheets.
Figure 6 : Circuit for Measurement of the Holding Current IH.
G
D89AN302·06
a) Variation of current IH with the sensitivity ofthe
devices and the direction of conduction (typical
value)
In the case of the triac (as distinguished from the
thyristor) it is important to note that current IH - (electrode A2 negative with respect to A 1) is generaly
lower than IH + (see figure S).
For low components (thyristors and triacs whose
rated current is less than 60A), the hypostatic current,
IH, is related to the firing current, IGT (see figure 7).
Figure 8 : Ratio between Holding Current IH +
. (A2 +) and Holding Current IH - (A2 -) for
Sensitive and Standard Triacs.
VARIATION OF THE HOLDING CURRENT, IH
Figure 7 : Ratio between the Holding Current, IH
(A2 +) and Current IGT (01) for Sensitive
and Standard Triacs.
IH +/IGT (01)
Sensitive triac 6 Arms (T type)
3
Standard triac 12 Arms(C type)
1.5
IH + I IH Sensitive triac 6 Arms (T type)
1.2
Standard triac 12 Arms (C type)
1.2
Example 2:
BTA 06 600T : if IH + = 4.3mA, IH - = 3.SmA.
BTA 12 600B: if IH +
= 15mA, IH - = 12.5mA.
Example 1 :
BTA 06 600T: if IGT (01) = 1.5mA then IH + =4.5mA.
BTA 12 600C : if IGT (01) = 10mA then IH = 15mA.
_4/_6______________________ ~~l
890
~~~@~~l~~©~------------------------
APPLICATION NOTE
Example: Triac TO 220, type BTA 12 600C
IH = 20mA at Tj = 25°C,
thus IH = 14mA atTj = 110°C.
b) Variation of the hypostatic current, IH, with
the junction temperature:
The value of the hypostatic current is physically related to that of the firing current, IGT. These two parameters thus vary with the junction temperature in
accordance with an analog law (see figure 9).
Figure 9: Relative Variation of the Holding Current IH, with the Junction Temperature, Tj (typical values).
IgtiTjJ
Igt(Tj-25'C]
.lh(Tj]
Ih(Tj-25'C]
2.5
2
1.5
I'"
I'"
I
Igt
'"
r---~ p,
l - I - Ih
0.5
~
f":: f::::
1J
:::::: c::
---- ---
Tj ('C)
o-40-30-20-10
0
10 20 30 40 50 60 70 80 90100110
c) Influence of the reapplied voltage:
The rise time and the level of the reapplied reverse
voltage across the triac after blocking have no influence on the value of its holding current, IH.
d) Influence of the external gate cathode
resistor, RGK
The user can wire a resistor, RGK, between the gate
and the cathode of the component, either to improve
its behaviour under voltage at high junction temperatures (by-pass for leakage current) in the case
D89AN302-07
of sensitive thyristors, or because it forms part of the
fliring circuit. This resistor has an influence on the
holding current, IH, in different proportions depending on its resistive value and the sensitivity of the
components:
1 - Sensitive thyristors (IGT:'; 5001lA)
Resistor RGK connected between the gate and the
cathode (figure 10) has an important influence on
the IH parameter of sensitive thyristors. For certain
applications, the designer would be well-advised to
define a high impedance control circuit.
Figure 10: Variation of the Hypostatic Current, IH, of a Sensitive Thyristor (e. g. TLS 106-6) as a Function
of the Gate-cathode Resistor (typical values).
5.5
F===1=t+tk=---l-I+ll--t-H-Il---l-.J-j.-Jj
Sensitive thyristor
5r---t-rtir--~~~r_--+_~~---+-+~
4.5
A
r---t-rtir---+-+"kIr_--+_~~---+-+~
3.5 1-----t-t-t1t--t-+H+-"~,+++i+---+--l-+H
3r---t-rtir---+-+~r_~~~~---+_+~
2.5 I---t-rtir---+_+~t---.p.d-l~---+_++H
21---t-rtir---+_+~t---+_~~---+_++H
1.5
1
1---t-H-tt-----t-+Ht------+-++11r-,..k:----H-+-H
1---t-rtir---+-++1t---+_~~'~
~~~+H
.51---t-rtir---+-+~r_--+_~~--_+_++H
o
o
o
Note: The hypostatic current for sensitive thYristors
IS
RGK (fl)
always specified for
DB9AN302·0B
RGC =
1000ohms.
-------------!~l ~~~~~~~~~~~-----_------5-/6
891
APPLICATION NOTE
2 - Standard thyristors, sensitive and standard triacs
e) Note:
A resistor between gate and cathode on one of
these components has no significant influence on
the value of its holding current, IH (on condition that
it is not too low, RGe > 200hms).
We have seen that the more sensitive the triac (Low
IG), the lower the value of the holding current, IH.
Now, in certain applications, a sensitive triac (direct
control by integrated circuit) with a high IH (or IL) may
be useful.
In this case, the circuit of figure 11 could be used.
The assembly is sensitive but has a higher hypostatic current.
Figure 11 : This Component, a «DARLINGTON TRIAC., combines a High Sensitivity with a High
Hypostatic Current.
T1 : standard triac
e. g. BTA 12 600B IGT (01)
IH+
~
SOmA
~SOmA
T 2 : sensitive triac
e. g. TLC 336T IGT (01)
~
SmA
IH + ~ lSmA
D89AN302·09
CONCLUSION
The choice of a thyristor or a triac does not depend
only on the voltage, the rated current and the sensitivity. Other parameters should be taken into account.
The hypostatic current, IH plays an important role in
many circuits.
The value of this parameter varies with:
Taking into account these elements, the designer
can obtain satisfactory operation of his circuit in industrial real life applications.
Knowing the problems which could be created by
this parameter, SGS-THOMSON Microelectronics
has introduced a new triac, BTA 06 400 GP, now
available for the designers. Its low holding current,
specified with a maximum value, enables it to be
used in most applications.
_ dispersion of characteristics at manufacture,
_ temperature,
_ eventually the control circuit (in the case of
sensitive thyristors),
_ the direction of current flow.
_6/_6_______________________ ~~l
892
~~~@~2~~~~©~-------------------------
APPLICATION NOTE
LATCHING CURRENT
By E. Leblanc
An important problem concerning the utilization of
components such as thyristors or triacs is the holding of the component in the conducting state after
the trigger current has disappeared during firing.
Very often, the firing problems supposedly due to
the gate current IG or to the firing time tGT are in reality due to the latching current IL.
After a definition we will illustrate the importance of
this parameter by concrete examples. Then we will
describe how to measure it and its variation according to the utilization conditions of the components.
The study will be based on the triac. The points
treated are valid for thyristors (except for the various
conduction modes).
DEFINITION
The latching current, IL, of a triac is the minimum
value of the main current (current flowing between
electrodes A2 and Al) which enables the component
to remain in the conducting state after the gate current IG has ceased (Figure 1).
Figure 1 : Controlled by the gate pulse, IG, the triac is fired, and a current IT flows through it, imposed by the main current. If the gate current IG is stopped before current IT reaches the value of the
latching current IL, the triac is blocked (as shown in the figure).
RL
Gate current
IT
A2
IG
".
".
IL
(T
A1
".
, "'
G
".
Main current
Da9AN303·01
AN303/0289
1/10
893
APPLICATION NOTE
APPLICATIONS
Example 1 : Control of a low power signalling lamp by triac.
Figure 2 : Control of a Low Power Signalling Lamp by Triac.
/
I
Lamp(10 W)
Main
current
-, \
\
\
I
t
/
/
220 V
A:;I--
1G
Gate
current
b
+-'-___--'-0--'--______
D89AN303-02
Current in the main circuit of the triac and gate current. The lamp power is too low (eg. : P s; 10 Wand
the triac BTA 12.400 B) to impose a sufficient current
(shown in dotted lines in the diagram) in the triac to
keep it in the conducting state after interruption of
the gate current IG. The triac does not conduct.
A BTA 12.400 B triac is used to control the flashing of
a 10 W signalling light. The peak current in the circuit
_2/_10_______________________ ~~l
894
will therefore be 65 mAo This value is very close to that
of the typical latching current given in the data book for
this type of triac: 50 mA (quadrant 1, 3 and 4). Thus
the user's case could be that described in figure 2, that
is, a triac whose latching current IL in the first quadrant
is equal to 70 mAo His triac will never be fired. For correct operation, the user should thus employ a sensitive
triac (e.g. T08-6A IL : 8 mAl.
~~~~~~~~~~~~-------------------------
APPLICATION NOTE
Example 2 : Control of an inductive load by triac,
Figure 3 : Voltage Accross and Current Through the Triac.
M
G
-
-
-
-
-
Control of an AC motor by triac
-
-
-
-
-
-
-
-
-j
Gate current
VT
I
I
I
I
Voltage across the triac
IT
IL4----------------r------'".-,
Current through the triac
,
\
\
,
In continuous lines : short gate signal : the triac
does not remain in the conducting state because the
main current did not reach the value of the triac latching current before suppression of the gate current.
--
,D69AN303-03
In dotted lines: long gate signal: the triac is fired
and remains in the conducting state until its current
falls below the holding current IH after suppression
of the gate current IG.
--------------~"'!L ~i~mVrr'~~~~~-----------3-1-10
895
APPLICATION NOTE
On a highly inductive load, the inductance limits the
current rise time to :
dlT
Va
d,
L
(Va: power supply voltage at the time the gate signal
is applied; L : load inductance).
triac increases. For triggering to be steady, the duration of pulse t2 should be long when compared with
a half-wave of the power supply voltage. The current
set up in the triac is imposed by the load impedance.
The triac remains in the conducting state until the
current falls below the holding current IH. It is
blocked if the IG current pulse has ended.
Another method consists of applying a train of
closely spaced pulses to the triac gate instead of a
square wave.
The SGS-THOMSON Microelectronics applications
laboratories have developed a number of triac control circuits, specially designed to work on inductive
loads (see bibliography, ref. N° 1).
Consider the operation on one full-wave of the
power supply voltage. If the duration t1 of the gate
current pulse IG is very small compared with a halfwave of the power supply voltage, the triac current
cannot reach the triac latching current level in the firing mode considered (here the 1st quadrant). Thus
firing will not take place and the voltage across the
Example 3: Control by triac of a load whose power varies considerably.
Figure 4 : Control of an Arc Welding Set by Triac.
D89AN303·04
The designer of an arc welding set whose power is
adjustable by triac, chooses a component capable
of controlling high currents. Forexample, if the maximum current to be controlled is 40 Arms, the designer, for safety, will choose a triac rated at 60 Arms,
thus a triac with a high latching current. Now, offload, the transformer magnetizing current could be
very low or even below the triac latching current IL
in one of the quadrants. This means that the triac
could fire correctly in the first quadrant and then not
fire if the next firing is to take place in the second
quadrant where the IL is much higher. A considerable unbalance then occurs, generating a DC cur"
rent heating the transformer and preventing the
equipment from operating correctly.
Since the latching current IL increases with the size
of components, and thus with their rating, the user
would thus be well advised not to select an excessively high rating for his triac in order to have the lowest possible latching current.
A.N : For this type of application, the SGS-THOMSON Microelectronics applications laboratories
place at the disposal of designers a number of schematics meant for this type of circuit (see bibliography, ref. N°1).
These three examples illustrate the importance of
the IL parameter and the problems that it can cause
in a circuit. To ensure stable firing of a triac or a thyristor, it is absolutely necessary for the circuit which
is controlled to impose a current which is higher than
its latching current.
_~_10______________________ ~~L ~i~~~~~~~~~~-----------------------896
APPLICATION NOTE
FAVORABLE EFFECT OF AN RC CIRCUIT ON
THE FIRING OF A THYRISTOR OR A TRIAC
In most inductive load applications of triacs or thyristors, the user connects an RC network between
the anode and cathode of the device to eliminate the
risk of premature firing by transients or spontaneous
firing by (dv/dt)c (case of triacs) (see figure 5). Capacitance C and the load impedance attenuate
steep voltage transients transmitted by the mains or
resulting from switching inductive loads.
Figure 5 : Reducing the Risk of Untimely Firing on Inductive Loads: the RC Circuit (called" Snubber»).
_I
D89AN303·05
This RC network has also a second advantage. In
fact, the energy accumulated in capacitor C after
turning off is fed back to the triac when firing. The
speed at which the current increases in the triac during discharge of the capacitor is then limited only by
the peak charge voltage of the capacitor and the in-
ductance of the circuit connecting the SNUBBER to
the triac. The current amplitude is the quotient of
peak charge voltage of the capacitor by the series
resis-tance R. This circuit thus helps the current to
rise very quickly above the latching current IL of the
device (see figure 6).
Figure 6 : Favorable Effect of the RC Circuit for Firing on a Highly Inductive Load.
IT1
+-----.,-......,--
/
IL
current
level
/
I : current in the load
Ic : discharge current of capacitor C
IT : I + IC : current in the triac
dlT/dt
D89AN303·06
Note:
When using an RC circuit, it is not advisable to work with aseries resistance R which is too low. In fact, the combined
effect during firing of Jr, (figure 6) (equal to the quotient of the capacitor peak charge voltage and resistance R)
and the current slope dlTfdt (equal to the quotient of the capacitance charging voltage by the inductance of the
connection between the triac and the RC circuit) could be dangerous for the triac. A value for R higher than 100
ohms is recommended.
--------------~~l ~~~~~~~~~~~~------------5-f1-0
897
APPLICATION NOTE
LATCHING CURRENT (IL) MEASUREMENT
Figure 7 : Latching Current (IL) Measurement Circuit.
V=
v
±12V
D89AN303·07
The closing of contact C enables passageof the
gate current whose is selected higher than that of
the triac firing current, IGT to be measured. By gradually decreasing the value of resistance R1, while
continuing to transmit pulses of gate current IG, the
main current IT is increased. As long as the value of
the IT current is lower than that of the device latching
current Il, the device does not remain in the conducting state. The value of the latching current Il is
the value of the IT current read as soon as the triac
remains on, after suppressing the gate current IG.
Only sensitive thyristors (IGT ~ 500 ~A) are measured
with a 1 KQ resistor between gate and cathode.
Parameter Il varies with the width of the gate current
pulse IGT and its level. For the measurement to be
reproduced correctly, the following rules should thus
be observed:
Fix a sufficiently wide control pulse IG. The width of
the pulse should be at least equal to 1 ms.
Impose a gate current IG sufficiently high with respect to that of the triggering current IGT of the device to be measured.
An _IIG ratio higher than or equal to 1.2 is advisable ..
Example: BTA 12.600 C
IGT max (Q IV)
IG = 60 mA
= 50 mA therefore
In the case of a triac, there are four latching current
Il values that correspond to the four quadrants of
triac operation:
- (Il + +) when the electrodes A2 and G are positive
with respect to electrode A1.
-(Il + -) when electrode A2 is positive with respect
to electrode A1 and electrode G is negative with respect to electrode A1.
- (Il --) when electrodes A2 and G are negative with
respect to electrode A1.
- (Il - +) when electrode A2 is negative with respect
to electrode A1 and electrode G is positive with respect to electrode A1.
GT
_6/_10______________________ ~~l
898
~i~~~~~~~~~------------------------
APPLICATION NOTE
VARIATIONS OF LATCHING CURRENT Il
WITH THE UTILIZATION CONDITIONS
a) Variations of the Il current with sensitivity of
triacs and the various directions of conduction
(typical values).
For the low power components (thyristors and triacs
whose rated current is lower than 60A) the latching
current Il is dependent on the value of firing current
IGT (see figure 8).
Figure 8 : Ratio of the Latching Current IL in the Different Ouadrants to the Triggering Current IGT in the
First Quadrant, for Sensitive and Standard Triacs (typical values).
IGT(OI)
IL (all)
IGT (01)
IL (0111)
IGT(OI)
IL (01 V)
IGT (01)
3.5
2
15
5
5
1.5
3
1.7
~I)
6 Arms Sensitive Triacs (T type)
12 Arms Standard Triacs (8 type)
Example 1 :
8TA 06.600 T :
Example 2:
8TA 12.600 C :
IL typ ~ 40 mA 01, III, IV
IL typ ~ 70 mA all
Depending on the production batches, parameter IL
shows dispersion. Shown below are approximate
values:
if IGT (01) ~ 1 mA
then: IL (01) ~ 3.5 mA ;
IL (all) ~ 15 mA
IL (0111) ~ 5 mA;
IL (QIV) ~ 3 mA
and 8TA 12.600 8
if IGT (01) ~ 15 mA
then: IL (01) ~ 30 mA;
IL (all) ~ 75 mA
IL (0111) ~ 22 mA ;
IL (OIV) ~ 25 mA
In the case of triacs, as opposed to that of thyristors,
note that: as underlined in the table of figure 8, the
current Il + - (electrode A2 positive with respect to
electrode A1 and electrode G negative with respect
to electrode A1 - 011) is much higher than the Il current in the three other quadrants.
sensitive triacs :
IGT (01) 0;; 5 mA (type T):
01, III, IV : 2 mA
all: 10 mA 0;; IL
0;;
0;;
IL 0;; 8 mA
40 mA
standard triacs :
IGT (01) 0;; 50 mA (type 8):
01, III, IV : 15 mA 0;; IL 0;; 50 mA
all: 50 mA 0;; IL 0;; 120 mA
In the data sheets two values are specified: one
value for quadrants I, III and IV and one value for
quadrant II. In general these values are typical.
b) Relation between the latching current Il and
the holding current IH
The holding current value IH (see bibliography, note
N° 2) is linked to the latching current value, Il. By definition, the Il current value will always be higher
than the IH current value.
The Il/ IH ratio varies following the sensitivity of the
triacs and their ratings (see figure 9).
Figure 9 : Ratio of the Latching Current IL to the Holding Current IH Depending on the Sensitivity and
Ratings of the Devices (typical values).
Sensitive
Triacs and Thyristors
IRMS 0;; 6 A
Medium Power
Thyristors and Triacs
6A 0;; IRMS 0;; 60 A
High Power
Thyristors and Triacs
60 A 0;; IRMS 0;; 300 A
1.1 to 1.5
1.5 to 2
2 to 5
IL / IH
(1 )
(1) 1 st quadrant in the case of triacs.
----------------------------~'r~ ~i~@IH~~:~~~~-------------------------7-/--10
899
APPLICATION NOTE
c) Variations of the latching current IL with the
junction temperature.
The value of the latching current IL is physically
linked that of the triggering current IGT. These two
parameters therefore way analogously with the
junction temperature (see figure 10).
Figure 10 : Relative variations of the latching current il versus the junction temperature tj (typ. values).
1. Quadrant 2
2. Quadrants 1, 3 and 4.
2.5
2
, .5
I"
,
'" ...-r..l i'-.
2
--I"--
:-::: j:::::.,
.5
°0"""
o
-- r- --
o
N
o
....
Example 3: Triac TO 220, type BTA 12.600 e
If IL (QI) = 20 mA at Tj = 25°C, then IL (QI) = 30 mA
atTj=-40oe
o
l""- I-
o
o
w
o
Tj(OC)
N
DB9AN303·0B
This resistor affects the value of the latching current
IL in different proportions depending on its resistive
value and the sensitivity of the component.
1. Sensitive thyristors (IGT < 500
d) Influence of the external gate-cathode
resistor RGC
When using sensitive thyristors, the designer could
wire a resistor RGC between cathode and gate to improve their voltage capability at high temperatures
(shunting of leakage currents).
IJA)
Resistor RGC connected between gate and cathode
(figure 11) has an important influence on the latching
current IL of sensitive thyristors. For some applications, the designer would be well advised to define
a high impedance triggering circuit.
Figure 11 : Variation of the latching current IL of a sensitive thyristor (e. g. TLS106-6) as a function of
the gate-cathode resistance RGC (typ. values).
o
IL(mA)
9
8
7
I""............
I"-
6
"-
5
4
3
2
" '"
I"-......
1
0 ....
o
o
o
o
8
Sensitive
thyristor
G
I"-o
RGK(O)
§
DB9AN303·09
Note: The latching current of sensitive thyristors is always specified with a 1ODD-ohm gate-cathode resistor.
900
APPLICATION NOTE
2. Standard thyristors, sensitive and standard triacs
the width of the triggering pulse IG. With a constant
pulse width« SOilS), an increase in the amplitude
of IG will lead to an increase in the latching current
IL and vice versa, if the amplitude of IG is kept constant, a decrease in the width of the triggering pulse
will lead to an increase in the latching current IL that
can even lead to an absence of firing of the device (figure 12).
A resistor connected between the gate and cathode of
one of these components does not have a significative
influence on the value of its latching current IL (on condition that its value is not too low RGC > 20 ohms).
e) Variation of the latching current IL with the
control conditions
The latching current IL of a triac or a thyristor rated
at less than 60 Arms varies with the amplitude and
Figure 12 : Variation of the Latching Current IL versus the Width tp and the Level of the Gate Current IG
(represented here as a multiple of the triggering current IGT of the triac under consideration)
Triac BTB 16.600 B (quadrant 1) (typical values).
,
IL(~
'100
SO
eo
7D
(iiU
50
•
it"
l""-
ra =101GT
"- i"o.,'\ ~:a =ISIGr
-
........
i"-.... ~
,
40
SO
20
!G=
2 IGT
10
oc
c
D89AN303·10
Negative biasing of the gate circuit (example: shape
of the pulse in figure 13a) increases the latching
current IL in considerable proportions. If the decreasing speed dlG/dt of the gate current is low
(example: pulse shape of figure 13 b) (less than 0.5
NilS) the value of the latching current approaches the
holding current IH.
Figure 13a : Gate Current Pulse with Negative
Current at the end of the Pulse:
Increase of the Latching Current IL.
Figure 13b : Gate Current Pulse (diac controlled
type) with tailing and without Negative Current: decrease of the
Latching Current IL.
-
v
D89AN303-11
D89AN303-12
-------------------------~~l ~ii@~Y~~~~©~-----------------------9-/1-0
901
APPLICATION NOTE
In order to obtain the lowest possible values for the
latching current IL, and thus ensure correct firing of the
device, it is advisable to work with an amplitude of IG
equal to 1.2 IGT and a width of the control current as
high as possible. The firing technique using trains of
closely spaced pulses ensures stable firing in total security. Control pulses with smooth tailing edges and
without reverse current allo reducing the latching current.
Triac and thyristor applications involving highly inductive loads or loads with considerable variations
of controlled power are the main applications where
the latching current IL plays a determining role.
Taking these elements into account will enable the designerto obtain satisfactory operation of his circuit in industrial applications.
CONCLUSION
1 - "Control of triacs for inductive loads" : technical
information TI 36/ SGS THOMSON
MICROELECTRONICS by X. DURBECQ.
2 - "Hypostatic current or holding current" by E. LEBLANC.
The choice of a thyristor or of a triac does not depend
only on the rated current, voltage and sensitivity.
Other parameters also play an important part in the
correct operation of a circuit and should be taken
into account. The latching current IL is one of these.
Its value varies with:
BIBLIOGRAPHIE
_ the way in which the device is controlled
(shape of the gate pulse)
_ the temperature
_ the trigger circuit (case of sensitive thyristors)
_ the direction of the current.
_10_/1_0______________________ ~~l
902
~i~@~g~i~~~~-------------------------
APPLICATION NOTE
DESIGN OF A STATIC RELAY
By X. Durbecq
The switching of a resistive load on the mains generates electromagnetic disturbances whose level is in
keeping with the voltage at the time of firing.
These disturbances can be reduced by switching on
the load when the mains voltage approaches o.
The convenience of firing control, the absence of rebound, and the response time of a semiconductor
device enable designing static relays which guarantee this synchronous type of switching.
The "mains zero" detection function can be obtained
by a circuit using discrete components.
This note provides a review of the principle of static
relays as well as the method of calculation for the
circuit component.
OPERATION A STATIC RELAY
The static relay consists of a power component, the
triac, triggered by a circuit ensuring the func,;tions of
"mains zero" detection and interfacing with the input
signal.
Figure 1 : Block Diagram of Static Relay.
I
I
--0
0--
Control
MAINS ZERO
VOLTAGE
DETECTION
~~
LOAD
l
I
I
Mains
~
j
D89AN306·01
OPERATING PRINCIPE
The firing of the triac can only take place when the
mains voltage is close to 0 volt (± 30 V max).
For a long-duration input signal (> 10 ms), the triac is
fired at the mains voltage zero. It continues to conduct
AN306/0289
for the full duration of this signal until the current drops
to zero after disappearance of the input signal.
An input pulse « 10 ms) should coincide with the
passing through zero of the mains voltage to enable
conduction of the. triac (figure 2b).
1/3
903
APPLICATION NOTE
'Figure 2 : Synchronous Static Relay: Waveforms
Figure 2a : Long Duration Input Signal (> 10 ms).
Figure 2b : Short Duration Input Pulse « 10 ms).
DB9AN306-02A
DB9AN306-02B
Mains voltage: V = 300 V/d.
Input signal: V = 10 V/d.
Mains current: I = 1 Ald.
T = 10 ms/d.
The triac is fired only when the input signal coincides
with the passage through zero of the mains voltage.
Mains voltage: V = 300 V/d.
Input signal: V = 10 V/d.
Main current: I = 1 A/d.
T = 10 ms/d.
CHARACTERISTICS OF THE STATIC
RELAY:
- No rebound.
- No electromagnetic disturbances.
- Opening of the circuit when the current passes
through zero.
- Closing of the circuit when the mains voltage
passes through zero (resistive and capacitive
loads).
- Control of the static relay by very low signals (logic
circuits, optocouplers, etc.).
- Insensitive to shocks and vibrations.
- High switching speed.
STATIC RELAY WITH DISCRETE
COMPONENTS:
The triac triggering circuit consists of a transistor Tr and
a sensitive thyristor Th. This circuit is biased by the
mains voltage after full wave rectification (figure 3).
Figure 3 : Schematic Diagram of a Static Relay with Discrete Components.
Load
Mains
Triggering by closing
control at mains zero voltage
2/3
904
DB9AN306-03
APPLICATION NOTE
OPERATION OF THE CIRCUIT:
Two distinct states can be observed:
1) Relay blocked: switch K open.
As soon as the mains voltage passes through zero,
the current in resistor Rl saturates transistor Tr, inhibiting the firing of thyristor T h by shunting the gate
current transmitted by R2.
3) For R3, a resistor of relatively low value
(4.7 kohms) is used in order to sufficiently bias all
the types of transistors which replace switch K.
4) Calculatit:m of Rl : switch K closed.
Transistor Tr is saturated only if the mains voltage
is higher than Va.
Rl
2) Relay fired: switch K closed.
The voltage divider composed of resistors Rl and
R3 results in blocking of transistor Tr, as long as the
mains voltage is lower than Va (generally 30 V).
The current which flows through resistor R2, passes
through the gate of the thryristor.
The thyristor T h can therefore be fired only during
this time To, which defines the mains zero operating
tol.erance.
EQUATIONS OF THE CIRCUIT: Switch K
closed.
1) Maximum firing time of triac, at the beginning of
each half-period.
To
=
Va
Vrmsxffxw
.. If Vo
«Vrms
2) Calculation of R2. A sensitive thyristor is used.
E.g. TLS 106-4 :
Ig\ max = 200 flA at 25°C
R2<
~ X R2 X R3 X (Va
-1)
0.7 X ~ X R2 + R3 X Va
The value of Rl determines the tolerance on voltage
Va. The value selected for resistor Rl is the standard
value immediately above the calculated value.
5) Calculation of Rg
In order to have a gate current Ig sufficiently high to
fire the triac, Rg is selected so that:
Rg«
Vo -4
Ig\ max triac
- RL
ADVANTAGES
- Very low power dissipated in the control circuit.
« 500mW).
- Operation of the triac in quadrants 1 and 3 ensuring a good symmetry of the latching current iL.
- High gate current available enables firing non sensitive tri acs.
DISADVANTAGES
- Utilization of a sensitive thrysitor requires the use
of an R.C. circuit across the triac, to prevent untimely triggering by transients transmitted by the mains.
Va - Vg\ max (Th)
----~----~~
Ig\ max (Th)
EXAMPLE OF APPLICATIONS:
Figure 4: Static Relay with Discrete Components and Isolated Control.
4xlN4004
Load
0.111 400V
220 V
T h : TLS 106-4 or TS08xx
~
D89AN306-04
CONCLUSION
Using discrete components allows the design of
simple circuits which achieve the synchronous
static relay work.
Their main advantages are to provide a high gate
current for the triac and to dissipate very low power.
3/3
905
APPLICATION NOTE
USE OF TRIACS ON INDUCTIVE LOADS
By J. Bellin
Although triac circuits are now well known by designers. The use of these components for inductive
loads requires certain precautions which should not
be neglected of optimum use is to be made of them.
That is the purpose of this article which reviews the
various triac control modes and recalls the principles
which guarantee its correct operation.
ing on the control mode (gate current, polarity and
width) and synchronization of the firing. In order to
build an optimal control circuit it is indispensable to
analyse the various possibilities.
PHENOMENA OCCURING WHEN THE CIRCUIT
IS CLOSED.
The triac is fired by a gate current Ig > Igt whose duration should enable the main current to reach the
triac holding current value (IL).
The triac is known as a component which is essential in controlling power from an AC source (mains).
In most cases, the circuit has an inductive component : either because of the nature of the load itself:
motors, transformers, ballast inductance ; or because of the source impedance: utilization of the
secondary of a transformer, length of the supply line,
etc. On inductive loads, the operating conditions
vary considerably, when closing the circuit, depend-
FIRING
CONTROL SIGNAL
The width of the control signal is determined by the
rate of increase of the main current (di/dt), limited by
the load inductance and by the choice of the firing
quadrant.
The loading current, IL, is highest in the second
quadrant (A2 positive with respect to A1, 19 negative) : (figure 1-a).
Figure 1 : Width of Control Signal Required as a Function of the Firing Quadrant (a) ; width of Control
Signal Required as a Function of the Moment of Firing (b).
I
t triac current
IL
quadranl tt
f------,..1ll
I
quadranls I.
ttl and IV
Ig quadranls I. Itt and IV
I
I
triac current
I
a
b
OL---~~+4L+------
__
Ig
Ig
Quadrants
Polarity
A2
G
with Respect to A 1
AN307/0289
II
+
+
III IV
firing at peak II!lltage
+
+
D89AN307-01
1/5
907
APPLICATION NOTE
The rate of rise of the hlain current, difdt, is proportional to the amplitude of the power supply voltage
at the moment of firing (difdt = VfL). The width of the
firing signal required is less when firing occurs near
the peak of the mains voltage than when its occurs
around zero of that voltage (figure 1-b).
To fire the triac and to ensure conduction in continuous operation, we can compare various types of
control circuits.
GATE CURRENT CONTROL BY SINGLE PULSE
To ensure correct operation, the gate pulse should
be synchronized with the triac current zero pOint and
should be long enough to enable the main current
to reach the latching current IL level (figure 2-a).
In case the pulse occurs before the triac current
reaches its zero point (incorrect synchronization) or
if its duration is too short to allow the main current
to exceed the latching current IL, the triac conducts
only during alternate half-cycles. The high DC component thus introduced in the load can produce considerable overloads due to saturation of magnetic
materials.
Figure 2 : Gate Control by a Single Pulse Synchronized with Zero Current (a) ; in Case of a Single Pulse
whose Duration is too Short, the Triac only Conducts during Alternate Half-cycles (b).
I triac current
[ triac current
D89AN307·02
GATE CONTROL BY PULSE TRAIN
The control by gate pulse train eliminates problems
of synchronization on the current. A recurrence frequency of several kilohertz guarantees correct operation of this type of control (figure 3).
This procedure, whose results are satisfactory, is
often used for controlling triacs in inductive circuits.
A variant of this principle consists in making use of a
circuit which monitors firing and which delivers pulses
to the gate as long as the voltage across the triac is
higher than a threshold, usually fixed at about 10 volts
(figure 4). This type of circuit enables delivering just
the amount of gate current required for firing.
GATE CONTROL BY DC CURRENT
Gate control by DC guarantees ideal firing but has
the disadvantage of high consumption, specially
when the control power supply is provided by the
mains. In this case, it is preferable to use a negative
current for the gate control (quadrants II and III).
Figure 3 : Gate Control by Pulse Train.
V mains voltage
I triac current
I
D89AN307.03
-----------J>."'!L ~i~~m~m~~~~~------------
_2/_5
908
APPLICATION NOTE
TRANSIENT PHENOMENA DURING
TRIGGERING
Principles
During continuous operation, the magnetic field H,
proportional to the current in the coil, varies with re-
spect to the induction B, with a delay as shown by
the hysteresis cycle in figure 5.
In transient operation, the induction can follow a different path and reach the saturation value Bs for
which the magnetic field H (according to the coil current) increases very rapidly (figure 6).
Figure 4 : Firing Monitoring Circuit: the Control Signal is repeated until Firing.
Firing
monitoring
Control
Threshold
vz
D89AN307 ·04
Figure 5 : Magnetic Field H with Respect to Induction B in Continuous Sinusoidal Phase.
Figure 6: Induction Bs Versus Field H Variation.
Bs
B
- - - - - - - --:=-;::-:.;::-"-,,,,---
o
H
H
H
D89AN307·05
In the circuits controlled by a triac, opening occurs
when the current is at zero. The induction thus has a
remanent value Br, corresponding to H = 0 (figure 5).
k.nI
D89AN307·06
When the triac begins to conduct, the transients depend on the instant of synchronization of the control
signal with respect to the mains voltage.
------------------------~~l ~~~~~~~~~©~-----------------------3-/5
909
APPLICATION NOTE
FIRING AT ZERO MAINS VOLTAGE
Peak induction thus reaches the value:
Peak induction tends to the value:
Bmax = 2 Bn - Br, because B rises between P and Q
on the hysteresis cycle.
Bmax = 2 Bn + Br,
thus in most cases reaching saturation induction Bs.
The amplitude of the current proportional to the magnetic field H becomes very high; this type of control produces the highest transient overloads (figure 7-a).
In order to limit the over current during firing at zero
voltage, control must be done by complete periods.
Since the triac allows an integral number of halfcycles to pass, the polarity of the mains voltage at
the moment of firing is the reverse of that at the moment the circuit is opened.
The overload is lower than previously but still remains high (figure 7-b).
FIRING AT PEAK MAINS VOLTAGE
Peak induction takes the value:
Bmax = Bn + Br
In general, the threshold of saturation Bs is not
reached and amplitude of the current remains within
acceptable limits (figure 7-c).
This type of synchronization is simple and efficient
and should be adopted whenever possible on loads
composed of materials which can be saturated.
Figure 7 : Transient Induction and Current at Beginning of Conduction.
V mai ns voltage
V mains voltage
V mains voltage
2 Bn + Br
B induction
,,'-'\,
Bs i-----.f""=---=~.
t
B induction
2 Bn - Br
Bsi--------.f="!.
B induction
Bs 1-------::=
I--~----r-_r~~---- O~----------~-------
triac current
A : firi ng at voltage zero
B : firing at voltage zero
conduction by complete periOds
_4!_5______________________
910
C : firing at voltage peak
D89AN307 ·07
~~l ~i~©~~~~?~~-----------------------
APPLICATION NOTE
FIRING AT INDUCTANCE PHASE SHIFT
WITH CONDUCTION BY COMPLETE
PERIODS
Firing atthe real inductance phase shift with conduction
by complete periods places the magnetic field and the
induction on the hysteresis cycle of continuous
operation: consequently, transients are eliminated.
However, the design of the control circuit for this firing mode is complex and consequently it is reserved
for special applications.
FIRING BY PHASE SWEEP
The triac is first fired at the end of a half-cycle. Then
progressively the difference of phase between the
voltage zero and the instant of firing decreases until
total conduction. With a sufficiently low sweep
speed, any transient overload is thus avoided
(figure 8). This procedure is widely used and gives
very good results.
Figure 8 : Firing by Phase Sweep.
V mains voltage
V
1
f triac current
0
t
F
r
I~'(
o
n
n
DB9AN307·0B
SPURIOUS FIRING
The control circuit plays an important role in normal
operation. However, in case of spurious firing, the
triac may have to withstand an accidental overload.
The peak amplitude of the current which could flow
through the triac should be known to select its
rating : the maximum current which could flow
through the circuit should not be higher than the accidental overload capacity of the triac (ITsM).
In this care the triac is oversized.
CONCLUSION
We have seen the essential points guaranteeing
correct operation of a triac. If the circuit is closed on
an inductive load, you need to :
Avoid transient overloads:
Fire the triac:
By synchronizing the control signal with respect to
the mains at the moment of firing (firing of the triac
at zero voltage should be avoided).
With a sufficiently wide gate control signal, in the
choosen quadrants (depending on whether higher
sensitivity or a low latching current is required).
Keep the triac in conduction:
By selection of the type of control (avoid gate control
by a single short pulse).
------------------------~~l ~~~@~~~~~~~~-----------------------5-/5
911
APPLICATION NOTE
CONTROL BY A TRIAC FOR AN INDUCTIVE LOAD
HOW TO SELECT A SUITABLE CIRCUIT
By X. Durbecq
Today triacs are well suited to the requirements of
switching inductive loads.
Nevertheless many users still encounter difficulties
when designing triac control circuits which are to be
both economical and applicable to inductive loads.
TRIGGERING WITH SYNCHRONIZATION
ACROSS THE TRIAC
The triggering circuit with "synchronization across
the triac" (fig. 1 and 2) turns on the component at an
angle ~ after the current drops to zero, such that
The purpose of this article is to present different
methods of triac control with their appl ications and to
analyze their relative advantages and disadvantages.
Time Tr is defined by the time constant (P + Rt)C.
A simple circuit offering all the guarantees of relia-
OJ
~ = OJ
Tr.
= 2 . 1t . f
with f = mains frequency.
bility is proposed for industrial loads.
Figure 1 : Typical Circuit: Synchronization Across the Triac.
T
Mains
c
p
At
D89AN306-01
Figure 2 : Synchronization Across the Triac. Shape of the Signals; General Case.
Mains voltage
Gate pulse
T
Triac voltage
T
/...--- ..
/
Triac current
T
q> : Current lag (full angle).
~
: Blocking of the component.
a : Conduction angle.
AN308/0289
D89AN308-02
1/11
913
APPLICATION NOTE
This is the simplest possible circuit but in certain
cases of utilization it can have an important drawback.
For example, consider a highly inductive load
(L 0) / R > 4) where the triac is turned on with a considerable delay ~ = 100 0 after the mains voltage
zero (figure 3).
The duration of conduction a of the triac turned on
at point A, is about 150 0 • The triac is blocked at point
B at a + ~ = 250 after the zero voltage point. At that
instant a negative voltage is applied to the triggering
circuitwhich turn on the triac at point C after an angle
~ of 100 0 , i.e. 350 0 from the starting point.
The second turn-on will occur ata very low voltage
0
and the angle a' will be much smaller than a. The following period begins under similar conditions and
the unbalance persists. This type of asymmetrical
operation is not only unacceptable but can be dangerous (saturation of the load by a DC component).
The unbalance is illustrated for a particular case,
starting from zero of the mains Voltage. Other
causes also produce this fault: variation of the load
impedance, transient operation, modification of the
adjustement... The reason for this is the principle of
the circuit which does not take its reference from the
mains voltage zero. Synchronization is by the voltage across the triac, which is a function of the current in the load.
Figure 3 : Synchronization Across the Triac. Shape of the Signals.
Mains voltage
Gate pulse
T
Triac voltage
T
Triac current
1---¥:.4----\-~---J~.~-~'----_
,
/
/
\
,
T
I
",
- -
~
.......
""
I full angle
D89AN308·03
Summing up, this first very simple triggering circuit,
synchronized by the voltage across the triac, has:
angle because it can result in unacceptable asymmetrical operation.
1) Definite advantages:
This very simple triggering circuit should be
reserved for low-cost applications with the following characteristics:
- Simple design and low cost.
- Connection by two wires, without polarity.
- Absence of a separate power supply.
- Little power dissipated in P and Rt.
2) A serious disadvantage:
Because of its principle, this circuit cannot be used
for highly inductive loads with a narrow conduction
- Resistive or slightly inductive loads.
- No stringent requirements concerning the accuracy of regulation.
- Variation on highly inductive loads between 85 and
100 % of the maximum power.
~2/~11~_____________________ ~~l ~~~~~~l~~~~------------------------914
APPLICATION NOTE
TRIGGERING WITH SYNCHRONIZATION
BY THE MAINS VOLTAGE
the mains voltage. The pulses are always shifted by
180 0 with respect to each other, whatever the type
of load.
This triggering circuit (figure 4) is synchronized by
Figure 4 : Typical Circuit - Synchronization by Mains Voltage.
T
Mams
~
c
DB9AN30B-04
Figure 5 : Synchronization by the Mains Voltage: Shape of Signals.
Mains voltage
Gate pulse
T
Triac voltage
I
"
~-
-
T
"-
/
'\
/
Tflac current
,
/
./
I
T
-..... I full angle
lJl : Current lag at full angle.
~ : Blocking of component.
a : Angle of conduction.
S : Triggering delay angle.
DB9P.N30B-05
-------------------------~~l ~i~;~g~~R~~~----------------------~3~/1~1
915
APPLICATION NOTE
Angle 9, characterizing the delay between the mains
voltage zero and the triggering pulse, can be adjusted by means of potentiometer P from 0 to 180°
to vary the voltage across the load. The current in
an inductive load (L.R) lags with respect to the voltage by an angle q> :
(tan q> = L.w / R).
For triggering angles 9 higher than q>,operation is
perfectly symmetrical and stable.
This simple circuit can still present the risk of a fault
in case angle 9 is smaller than angle q> (figure 6).
As an example, take the case of a highly inductive
load and an angle 9 = 60° . The triac is turned on at
point A (60°).
It will conduct during an angle CJ. greater than 180°,
in the neighbourhood of 250° . It is blocked at point
B : (290°). The second triggering pulse occurs at
point C : (9 + CJ. = 240°).
It has no action on the triac which is still conducting.
The triac is not turned on for the other half-wave. As
in the previous case, the operation is asymmetrical,
and thus unacceptable.
Figure 6 : Synchronization by the Mains Voltage - Shape of the Signals for 9 < q> - Asymmetrical Operation.
Mains voltage
Gate pulse
~~----~-+-----+--L---~~
__
Triac voltage
T
T
T
Triac current
I
/
~
I lull angle
DB9AN30B·06
To prevent this fault, it is necessary to insert a "stop"
to maintain 9 > q> . This is possible for loads whose
Land R parameters remain strictly constant.
Experience shows that for the majority of inductive
loads used in industrial applications (motor controls;
transformers, etc ... ) it is not possible to insert the
"stop" without considerably limiting the voltage excursion, since the values of Land R vary a great deal
during operation.
Summing up, this simple triggering circuit, synchronized by the mains voltage, is more developed
than the previous one. It has:
1) Advantages :
- Simple design.
916
- More accurate control than the previous circuit.
- No auxiliary power supply or transformer required.
2) Disadvantages:
- Connection of the circuit by 3 marked wires, instead of 2 without polarity in the previous circuits.
- Power dissipated in passive components P and Rt.
- Operation becomes completely asymmetrical if the
control angle 9 is less than q>.
This triggering circuit can only be used for applications in which the phase shift of the load remains
constant (air inductor) or if operation is restricted to
values of 9 much higher than q>.i.e. at low voltage.
APPLICATION NOTE
TRIGGERING SYNCHRONIZED BY THE
MAINS VOLTAGE AND SUITABLE FOR
INDUSTRIAL APPLICATIONS
This new circuit is derived from the previous one by improving the triggering pulse generator. The improve-
ment consists in maintaining the triggering signal
during each half-wave between values e and 180°.
This is done simply by sending a pulse train after the
initial pulse so as to maintain the triggering order
(figure 7).
Figure 7 : New Circuit - Triggering by Pulse Train Synchronization by the Mains Voltage.
Mains voltage
Gate pulse
Triac voltage
Triac current
tA
Current lag full angle.
a : 1st angle of conduction.
a 2 : 2nd angle.
~ : Blocking of triac.
e : Triggering delay time.
!p :
DB9AN30B·07
For example, suppose that angle !p is equal to 85 0
and e is equal to 60 0 • At the first pulse, the triac is
turned on at point A (60 0 ). It conducts for angle a 1
greater than 180° and close to 240°. It is blocked at
point B but is immediately triggered at point B' by the
next repetitive pulse. During the first half-waves,
operation is slightly asymmetrical but gradually the
durations of conduction become balanced (dotted
line curve in figure 7).
Figure 8 : Circuit with Triggering by Pulse Train
Synchronization by Mains Voltage.
Figure 8 gives the circuit diagram. A small sensitive
auxiliary triac is used to produce the pulse train
necessary for maintaining the control signal.
Capacitor C, compensating resistor Rt and potentiometer P define the angle e or delay time constant.
The capacitor is charged from 0 V and diac D triggers as soon as its breakover voltage (Vbo) is
reached. The angle is positioned identically for both
half-waves.
Mains
Ts
RI
DB9AN30B·OB
t==
--------------r::."Y1l
A first pulse is applied to the gate of the main triac,
T. A voltage pulse occurs across Rd and triggers
sensitive triac Ts. Once it has been turned on, this
triac bypasses potentiometer P. The remaining
charging cycles of the capacitor have a much shorter time constant Rt x C.
SGS.1HOMSOru
5/11
IifU©W@[H~©'G'OO:QiIii.JU©:ll--------------"'.-'-'
917
APPLICATION NOTE
A succession or train of pulses is applied to the gate
of the main triac, T, enabling elimination of the defects explained above. The pulse train continues
until the mains voltage crosses the 0 point. Triac Ts,
supplied through a resistive load, is blocked.
For the following half-cycle, the capacitor load is once
more based on the time constant determined by the
potentiometer. The cycle is resumed in inverse.
Summing up, the improved triggering circuit synchronized by the mains voltage has a number of advantages.
- Simplicity of design.
- Excellent accuracy of control.
- Absence of auxilliary separate power supply.
- Utilization of the circuit for all types of loads with different cos cp or variable cos cp values.
- No risk of failure over the whole adjusting range.
This circuit has been developed by the
SGS-THOMSON Microelectronics applications laboratory and used with success for a wide range of equipment.
6/11
CONCLUSION:
The difficult conditions of an inductive environment
require a critical choice of the triggering circuit. The
first two circuits described leave the user a very
limited adjusting range. A universal circuit can be
obtained by taking into account two decisive factors
- To obtain perfect symmetry of the first gate pulses
in both half-cycles, the triggering circuit should be
synchronized by the mains Voltage.
- The variation in phase angle enables perfect symmetry of the current if the triac is continuously triggered.
The circuit described in the last paragraph combines
these two principles in a very simple manner. It enables complete variation of power on an inductive
load without particular problems. It can thus serves
as the basis for a universal circuit for control by
phase splitting on a inductive load.
r=-= SGS-1HOMSON
.::::...:.-'--------------1I;.1l TIii~(Q:irulQ:c;rLll'&iJiru@i%(Q;~-------------918
APPLICATION NOTE
SYNCHRONIZATION ACROSS THE TRIAC
Figure 9 : Example of an Application: Speed-control Circuit for a Small Asynchronous Motor.
N
3,3 nF
3pF
400 V
3,3 nF
Ph
OB9AN30B-09
SYNCHRONIZATION BY THE MAINS VOLTAGE
Figure 10 : Example of an Application: 220/110 V Step-down Circuit.
h.
-I
D_l/IF
4(){)V
220VRMS
1
1.5KE68A
l
110VRMS
ZL
15 kll
4W
OB9AN30B-10
r.:::.-= SGs.THornsorn
7/11
--------------[},,"fll
[f:JJD@]l©"'~"'Ii;:ITIFJI[Ii/JD@:0---------------'--'----'919
APPLICATION NOTE
NEW TRIGGERING CIRCUIT
Figure 11 : Example of an Application: Power Variation Circuit for Arc Welding Transformer.
O.1!'F
400V
220 V
28.
+
27k 112W
-z-
_
1.5KE68A
D89AN308-11
::::.8/..:...11'--_ _ _ _ _ _ _ _ _ _ _
920
J...,l
~~~(~m~:~~?~~-------------
APPLICATION NOTE
APPENDIX
CONTROL BY TRIAC FOR INDUCTIVE LOADS
SUMMARY OF SOLUTIONS
A SYNCHRONOUS TRIGGERING ACROSS THE TRIAC
T
p
R
Synchronization across the triac based on crossing of the zero point by the current.
8 TRIGGERING SYNCHRONIZED BY THE MAINS VOLTAGE
T
Mains
Synchronization based on crossing of the zero point by the mains voltage
C NEW TRIGGERING CIRCUIT
Mains
Ts.
Synchronization by crossing of the zero point by the mains voltage and generation of
a pulse train from then onwards.
r=-=
--------------JJ..""'!l
DS9AN30S-14
SGS-lHOMSON
9/11
~DIGOO@[Ill1llilG'ii'OO@IiIlDIG:0---------------=.:.-'-'921
APPLICATION NOTE
TRIGGERING SYNCHRONIZED ACROSS
THE TRIAC
SCHEMATIC DIAGRAM (see page 10-A)
RESISTIVE LOAD:
Current and voltage are in phase: good synchronization. No fault over the whole adjusting range.
- Delay. angle
Correct synchronization of the triggering pulses enables balanced conduction for all variations up to the
lag angle.
Certain applications use this principle:
e.g. 200 V - 100 Vrms step-down circuit.
- Delay angle
INDUCTIVE LOAD:
The current lags by TC 12. Two cases should be considered:
- Broad conducting angle; narrow lag angle.
The time separating two conducting periods is very
brief. The positive and negative currents are practically equivalent. Little dissymmetry. Certain applications are covered by this case.
e.g. speed-control circuit for AC motors.
- Narrow conducting angle; broad lag angle.
The flow of current in one direction is a function of
the control and thus of the duration of the current
flow in the previous direction.
The triac can be triggered at the end of the mains
half-cycle. In this case no current flows through the
circuit and it acts as a rectifier.
ADVANTAGES OF THE CIRCUIT:
- Connection by two wires without polarity.
- No power dissipated by the passive components.
- Excellent power variation circuit for resitive or
slightly inductive loads.
- With highly inductive loads, the circuit can only give
satisfaction within the limits of a slight decrease in
the conducting angle.
e > the lag, 180 0 • It is
blocked after the gate pulse of the following halfcycle. The current does not flow in that direction. The
circuit th us acts as a rectifier.
ADVANTAGES OF THE CIRCUIT
- Accuracy of the triggering pulses.
- Current operation with a resistive load but circuit
too complex.
- Excellent operation for power variation circuits limiting conduction to small angles with inductive loads.
DISADVANTAGES:
- Connection by three wires. Necessity to obtain access to the mains terminals.
- Permanent power supply with power dissipated by
the passive components.
- Impossible to adjust the delay angle to values approaching or inferior to the current lag. This circuit
cannot be used for inductive loads where a variation
close to the highest conduction angles is required.
NEW TRIGGERING CIRCUIT
SCHEMATIC DIAGRAM (see page 10-C)
DISADVANTAGES:
RESISTIVE LOAD:
- For inductive loads, large current dissymmetry for
a variation towards the narrowest conduction
angles. For this type of application the circuit cannot
be used atall.
Absence of fault over the whole adjusting range.
TRIGGERING SYNCHRONIZED BY THE
MAINS VOLTAGE
SCHEMATIC DIAGRAM·(see page 10-B)
RESISTIVE LOAD:
No fault over the whole adjusting range.
INDUCTIVE LOAD:
Two cases should be considered:
922
INDUCTIVE LOAD:
Operation in the two possible cases:
- Delay angle
e > 100 AlIlS) since only the
inductance of the connections limits the rate at
which the current can increase.
Figure 1 : Typical Circuit.
The Triac is directly connected to the distribution network: risk of darnage.
R
Vmains
+
accidental
overvollages
Control
D89AN328DQ1
WHAT WE PROPOSE
The principle of the protection which we have studied consists in turning on the triac by the gate, as
soon as the voltage across it exceeds a certain value (figure 2), thus under conditions which ensure a
high level of safety. To do this we use a bidirectio-
nal TRANSIL diode whose current/voltage characteristic is recalled in figure 3.
When the voltage applied to the triac reaches th.e
VBR voltage of the TRANSIL, the latter conducts,
producing a current in the triac gate and turning it
on (figure 4). The triac continues to conduct till the
half cycle current passes through zero (figure 5).
Figure 2 : Protection of the Triac by a Bidirectional TRANSIL Diode.
The Triac is turned on by gate (current i) as soon as voltage A2 exceeds the voltage VSR of the
TRANSIL.
D89AN328DQ2
AN328/0489
1/4
925
APPLICATION NOTE
Figure 3 : Voltage-current Characteristic of a TRANSIL Diode.
VSR Specified at 1mA (tolerance 5 or 10%)
VCl limitation voltage, given for a high Ipp current level (from several amperes to several tens of
amperes, depending of the type.
Current
Ipp
_~-~V~B=R========~
__-t__c=========~L-~
+VBR
Voltage
_______________ Ipp
D89AN328D03
Figure 4 : Characteristic of the TRIAC + TRANSIL Assembly.
.
Case of a 600V/12A triac protected by a 440V TRANSIL diode (the dotted line gives the characteristic of the triac alone).
Current
(rnA)
Current in the
turned- Vmains x
In the absence of accurate 'specifications, add 20%
for the safety margin.
Example: 220V network:
VR > 220
v"2
+ 20% = 375V
POWER
The TRANSIL only conducts when turning on the
triac (t '" 1~s).
THE RESULT OBTAINED
We have carried out tests with repetitive overloads
(1 Hz) under various conditions:
Exponential shock waves of about 1ms, calibrated
in voltage (up to 2000V) and controlled in di/dt
(500Al~S maxi).
The tests were carried out with steep-edged voltage
pulses (dV/dt > 1OOOV/~s) and also with gradual
slopes « 50V/ms).
~II these tests were successful: zero failure.
SELECTION OF THE TRANSIL DIODE
REQUIRED FOR PROTECTING A TRIAC
VOLTAGE: VR
Obviously the triac associated with the TRANSIL
diode shmlld not be turned on by the maximum
mains voltage. An additional safety margin should
be given to prevent untimely turning on by the small
The current, during this time, can reach very high levels (several tens of amperes) in the case of disturbances with steep edges (> >1000V/~S), however
the dissipated power remains well within the possibilities of TRANSILS.
The BZW 04 (400W/1 ms) suffices iri all cases.
PRACTICAL EXAMPLE
Drive circuit for a 2kW heating element on 220V
mains (figure 6).
The BZW 04.376 type TRANSIL perfectly protects
the BTB 16.600 B triac (VDWM = ± 600V).
The 100 - Q resistor, R, between the gate and A 1
is not absolutely indispensable but it enables preserving the dV/dt characteristic of the triac which is
reduced (by about 20%) by the junction capacitance
of the TRANSIL between anode and gate.
Figure 6 : Practical Exampl~ of the Protection of a 12 or 16A Triac against Overvoltages.
2kW
BTB 16600 B
220 V
or BTA 12 600 B
'~
Control
D89AN328D06
CONCLUSION
With the protection circuit proposed by us, the triac
always operates under perfectly defined conditions
in case of overvoltages :
_The voltage remains limited to the maximum specified for the triac
4/4
928
_Turn-on is ensured by a gate current.
This circuit, which we have tested in a number of different setups (different loads, high amplitude overvoltages, disturbances of long duration, etc... ),
enables a considerable increase in the reliability of
circuits using triacs and is indispensable for driving
resistive loads on highly disturbed networks.
APPLICATION NOTE
POWER CONTROL WITH 8T621 0 MCU AND TRIAC
Philippe RABIER - Laurent PERIER
INTRODUCTION
BOARD OPERATION
Microcontroller (MCU) systems are progressively
replacing analog controllers even in low cost applications. They are more flexible, provide a faster
time to market and need few components.
Basic function
With an analog IC, the designer is limited to a fixed
function frozen inside the device. With a DIAC
control, features such as sensor feedback or enhanced motor drive can not be implemented. With
the MCU proposed in this note (ST6210), the designer can implement his own ideas and test them
directly using EPROM or One Time Programmable
(OTP) versions.
The LOGIC LEVEL triac BTA08-600SW is a good
complement to this MCU for low cost off-line power
applications. This triac requires a low gate current,
and can be directly triggered by the MCU, while still
maintaining a high switching capability.
This application note describes the main aspects
of a highly flexible, low cost power application
designed around an ST6210 MCU and a LOGIC
LEVEL triac.
Ilne3
MCUBOARD~~
Neutral
fl
Light dimmers with DIAC or analog controllers are
currently used today. These circuits have the disavantage that they can not easily drive inductive
loads like halogen lamps on the secondary of a
220V/12V transformer. They are also limited in the
choice of user interfaces.
A light dimmer circuit, supplied directly from the
110V/240V mains, has been realized using a MCU
ST6210 and a LOGIC LEVEL triac. This circuit
drives both resistive and inductive loads (e.g. halogen or incandescent lamps, transformers). The
control method is such that the same board can
drive a universal motor. The user interface is either
a touch sensor, a push button or a potentiometer.
The board contains a minimum of components
therefore saving cost and space. The auxiliary supply is derived from the voltage across the triac.
Power control
The output power is controlled by the phase delay
of the triac drive. In classical designs, the delay is
refered to the zero crossing of the line voltage. The
detection of the zero voltage normally requires an
additional connection to the mains neutral. In order
to avoid this connection and connect the circuit
directly in series with the load, the trigger delay is
referred to the previous zero crossing of the current
(fig.1 ).
AN392/0591
1/9
---------------------------- ~~~~@~g~~~~~~ ----------------------------
929
APPLICATION NOTE
BOARD OPERATION (Continued)
Figure 1. The·Power Control Is Based On The Monitoring Of The Zero Crossing Of The Current
Vpeak 2
Power
~
2Z
td
10 ms
V line
VAK
IA
Mains synchronisation
When the current in the triac is zero, the mains
voltage is re-applied across the triac. Synchronisation is achieved by measuring this voltage. This
voltage is monitored in each halfwave, which allows
the detection of spurious open load conditions. The
triac is retrigged with multipulse operation if it is not
latched after the first gate pulse.
Changing operation from 50Hz to 60Hz can be
achieved by making simple modifications to the
microcontroller EPROM/ROM table defining the
triac conduction angle versus the power level.
The risk of saturation of the transformer core is
avoided because the controller includes the following features:
At the start, the delay time between the first gate
pulse and the synchronisation instant is greater
than 5ms. This limits the induction in the transformer and hence reduces the risk of saturation.
Figure 2. First Gate Pulse Delay
Low power halogen spots use low voltage lamps
(12V typ.) usually supplied through a low voltage
transformer. The light dimming of these lamps is
simple with this circuit.
A phase lag between current and voltage as high
as 90 does not disturb the circuit because the
control method is based only on monitoring the
zero current crossing.
k
/;r-
Operation with a transformer
V line
/
/
td
I
/A
I magn
Saturation of the transformer at start is avoided.
2/9
---------------------------~~ii@~~~~~~©~ ----------------------------
930
APPLICATION NOTE
BOARD OPERATION (Continued)
The circuit starts on a positive halfwave and stops
on a negative halfwave (fig.3). So it starts with
positive induction and stops after negative induction has been applied. This helps to minimize the
size of the magnetic material.
Figure 3. Hysteresis Cycle in off/start/stop
Phases
B
Triac drive
The triac is mUlti-pulse driven. Therefore, inductive
loads can be driven without the use of long pulse
drives. As a result, the consumption on the +SV
supply can be minimized and the supply circuit
made very small.
The pulse driving the triac is SOflS long. The LOGIC
LEVEL triac is driven in quadrants 011 and 0111 with
a gate current of 20mA provided by two I/O bits of
the ST621 0 in parallel. The LOGIC LEVEL triac
has a maximum specified gate triggering current of
10 mA at 2S'C.
Before supplying the first drive pulse, the triac
voltage is tested. If no voltage is detected, a spurious open load or a supply disconnection is assumed to have occured and the circuit is stopped.
After the first driving pulse, the triac voltage is
monitored again. If the triac is not ON, another
pulse is sent. The same process can be repeated
up to four times. Thereafter, if the triac is not ON,
the circuit is switched off.
Imagn
STOP
The timer is very precisely tuned in order to obtain
precisely 1Oms delay between two gate pulses. As
a result, the triac is driven symetrically in both
phases so continuous voltage in the transformer is
avoided.
The voltage across the triac is monitored in order
to detect a spurious open load condition on the
secondary of the transformer.
The inrush current at the turn-on of a lamp (halogen
or incandescent) is also reduced due to the soft
start feature of the circuit (fig.B).
------------- @
User Interfaces
There are three different user interfaces: a touch
control,.a push button or a potentiometer. Four
modes can be selected on the board in order to
define how the transmitted power is related to the
user interface.
Three modes operate with the touch sensor or the
push button. Dimming is obtained when the sensor
or the button is touched for more than 400 ms. If
the touch duration is between 60 ms and 400 ms,
the circuit is switched on or off. A contact of less
than 60 ms has no effect. Modes 1 ,2,3 differ in the
way the ouput power is influenced by the contact
on the sensor or on the button.
Mode 4 directly relates the transmitted power to the
position of the potentiometer (fig.4).
All modes include a soft start function.
3/9
~~~@m~~~~~©~ - - - - - - - - - - - - 931
APPLICATION NOTE
BOARD OPERATION (Continued)
Figure 4. User Interface
Sensor
Sensor version
potentiometer version
D'--'--'-----~~s=l---+-----'--r--c;l------'-~--+--+-P~t
Mode 4
Pmax
Mode 1
I
~--l...
P
I
Pmax
Pmax
Mode 2
I
Pmax
Mode 3
I
I
I
I
I I
I I
U:Hi} ~
I
I
I
Vpot
VDD
I
..
t
Sensor Contact Duration
< GOms
GOms to 400ms
> 400ms
Mode 1
No effect
Switched ON to full power or
switched OFF
Same sense of variation as
previous action
Mode 2
No effect
Switched ON to previous level or
switched OFF
Opposite sense of variation to
previous. action
Mode 3
No effect
Switched ON to full power or
switched OFF
Opposite sense of variation to
previous action
4/9
~ SGS-THOMSON
- - - - - - - - - - - - - 1It.""!1
ililD©IR'@~~~©1l00@[1!D©il'
932
-------------
o
til
:0
r:::
!J1
Q
FUSE
3
100
MODE
+5V
A2
~
BTA 08-600SW
100k
13
PB2
1?
PB3
220k
~~
~O
5
z
iil
(3
o
3
~
;:t
CD
P81
NMI
I
PB4
TEST
10
I
P85
vss
I
1~
14
~
.e,
PUSH BUnON
OV
6
20
+5V
O;Dog:".M"
220k·
i!;lz
Qi'
s·
@.
!,!O
"tI
m
c
11
",(II
Ill~
~:i!
TOUCH SENSOR
o
o
:0
ca
~ ::
F~
OV
x 4.7M
:t>
t=l
§:
o
LINE
OJ
:!!
ca
220k
POTENTIOMETER
-y
OV
18p
OV
OV
»
"'C
"'C
100u
6.3V
LOAD
CD
W
W
01
to
1N4148
r(;
All resistors 1!4W unless otherwise specified
~
5z
z
S
m
APPLICATION NOTE
HARDWARE
The circuit uses an S bit MCU ST621 0 and a LOGIC
LEVEL triac directly driven by the MCU (fig.5). It
operates with 3 user interfaces, 4 modes of operation and 4 kinds of loads. When the board is
dimming a resistive load, an RFI filter must be used
in order to meet RFI standards (eg. VDE S75).
The ST621 0 includes 2K ROM, 64 bytes RAM, an
Sbit AID converter that can be connected to eight
different inputs, 4 I/O ports with 1OmA sink current
capability and a timer. Hysteresis protection is included in series with each I/O pin. The ST621 0 is
packaged in PDIP or SMD packages. The ports,
timer and interrupts configurations can be chosen
by software, providing great flexibility. With
EPROM and OTP versions, the equipment development and preproduction can be carried out directly from the design lab thus providing a fast time
to market.
The LOGIC LEVEL triac (BTAOS-600SW) has been
especially designed to operate with MCUs. It is a
sensitive triac (IGT=10 mA, IL=50 mAl trigged in
quadrants QII and Qili. In this application it is driven
by two I/O bits of the ST621 0 in parallel. This triac
has high switching capabilities ([dl/dtjc=3.5 Alms),
([dV/dtjc=50 V/IlS), so in this circuit, it can operate
without a snubber.
Total consumption of the board is less than 3mA
with an SMHz oscillator. The board receives its
supply only when the triac is off. So a minimum off
time of the triac (2ms) is necessary to ensure its
supply.
The 5V supply capacitance is mounted as near as
possible to the MCU with very short interconnecting
tracks in order to maximize the RFI/EMI immunity.
The touch sensor is a voltage divider between line
and neutral potentials. It operates when the supply
of the circuit is connected at the line potential and
not at the neutral. The user is protected from electrical shock by a very high impedance (10Mn )
connecting the sensor to the circuit.
SOFTWARE
All the features are included in a 700 byte program.
More than 1kbyte of ROM is available for additional
features. The architecture of the software is modular in order to provide maximum flexibility.
The table relating the delay time to the power
requirement contains 64 different levels. The conduction time of the triac can vary from 2ms to Sms.
The user can easily adjust the minimum and maximum power levels because the corresponding
delay times change with smaller increments at the
top and bottom of the table.
The table can be easily modified in the
ROM/EPROM space to meet different conditions
e.g. 60Hz operation or varying loads.
Software versions cover the four user interface
modes of operation without hardware change.
All inputs are digitally filtered, so that an input is
valid only if it remains constant for 1OilS or more.
This reduces the number of passive components
required.
'The mains supply carries disturbances (e.g. glitches, telecommand signals) which can disturb the
triac drive and generate lamp flickering. For this
Figure 6. Internal Timer Operation
~
N
Vtriac
N
01
II
10
4 ;1;
01
II
I0
2
3
,4,1, 2
.
line synchro
gate drive
timer modes
6/9
-------------~ ~ii@mi~:~~©~ -------------
934
APPLICATION NOTE
SOFTWARE (Continued)
reason, the triac voltage is not used directly as the
synchronisation parameter. The timing is carried
out internally by the MCU timer. The period of
operation can be slowly modified to follow the
variations of the mains frequency but not the spurious disturbances. The mains synchronization signal is received every cycle. The corresponding
mains period is measured and compared to the
internal timer period. If a difference remains for a
long time, the timer period is modified to follow the
mains. This block acts like a low band filter which
saves external filtering components.
Each 50Hz period, the timer operation is separated
in four steps (fig.6). The triac voltage synchronisation can only be validated during phase 4.
The software has been written with modular blocks
(fig.?). It can be enlarged to other applications such
as motor speed regulation, telecommand input or
IR remote control with additional blocks.
PRACTICAL RESULTS
Figure 8 shows the soft start operation with a
halogen lamp operating from the secondary of a
low voltage transformer and with a tungsten filament lamp.
Figure 8. Soft Start With Lamps
Halogen tamp at the secondary of a transfonner
Triac anode current: 1A/div
200msJdiv
Incandescent lamp
Figure 7. Major Steps of the Software
Initialization
Read version
Line synchronization
Figure 9. Universal Motor Drive
Sensor acquisition
Triac voltage VAK : 200V/div
Power level requirement
2ms/div
Delay time td1 in timer
Calculation next delay
f
0
----
\
Triac firing
--- -
Delay time td2 in timer
Calculation next delay
Triac firing
Delay time td3 in timer
.r
0
./"
V
""-.....
""-
Delay time td4 in timer
Triac anode current: 2A!div
r:=-=
- - - - - - - - - - - - - - - - &'111
SGS.1HOMSON
ifJD©IiiI@~~~©IIIii1@Ii[D©i!'
2ms/div
7/9
----------------
935
APPLICATION NOTE
PRACTICAL RESULTS (Continued)
Due to the soft start, the peak in-rush current is
about 3 times the. nominal current compared with
10 to 15 times without soft start. This extends the
lamp life time and prevents the input fuse· from
blowing.
The figure 9 shows the current and voltage in a triac
driving a universal motor.
SUMMARY
Microcontrollers (MCU) are in common use in most
areas of electronics. They now penetrate the very
cost sensitive arena of home appliance applications.
incandescent and halogen lamps supplied either
directly from the mains or through a low voltage
transformer. The same circuit can also drive· a
universal motor. It includes soft start and protection
features. Different user interfaces can be chosen:
touch sensor, push button or potentiometer.
All this is achieved with only few components: a
ST621 0 MCU in PDIP/PSO package with a BTA08600SW LOGIC LEVEL triac in T0220 package and
some passive components.
Additional features like presence detection, IR
remote control, homebus interface, motor speed
control or 60Hz operation can be implemented from
the existing solution.
The application described in this paper shows that
enhanced appliance circuits can be designed with
fast prototyping time using a ST621 0 MCU and a
BTA08-600SW LOGIC LEVEL triac. These circuits
are low cost and provide more features with less
components than classical solutions.
Thyristors and triacs application manual 1989
Microcontroller based universal motor speed control . M.Queroll SGS-Thomson Microelectronics
The circuit presented is an enhanced light dimmer
operating from the 120V/240V mains. It drives
Universal Motor Speed Control I P.Rault + Y.Bahout I
SGS-THOMSON Microelectronics
Bibliography
Application Note:
8/9
-------------Fii ~i~@m~~l~~©~ --------------
936
APPLICATION NOTE
ANNEX: Choice of a triac driven by a MCU.
When the software includes a soft start, the inrush
current in the load and therefore the current rating
in the triac can be reduced.
When using a LOGIC LEVEL or a SNUBBERLESS
triac the current rating of the triac can be reduced,
keeping fast commutation characteristics. For instance, a LOGIC LEVEL triac BTA08-600SW can
drive a 600W lamp and a SNUBBERLESS triac
BTA10-600BWa 1200W universal motor.
LOGIC LEVEL triacs are optimized on the drive
view point. Therefore they can be driven directly by
the ST621X 1/0.
SNUBBERLESS triacs are optimized on the power
view point, so they can drive loads which generate
very strong dynamic contraints.
These triacs are specified in a way that their behaviour can be pre-determined. The tables below
present with two examples the relation between the
major application constraints and the key parameters of the triac.
LIGHT DIMMER
Constraint
Key parameters on a LOGIC LEVEL triac
BTAOB-600 SW
Simple Drive
IGT=10mA - VGT=1.SV
No flicker
IH = 2SmA
Max power on the load
IRMS = BA
Max inrush current
(dl/dt)c = 4.SA!ms
No flashing
ITSM = BOA
(1)
Flash over (filament failure)
Note1: When the lamp is cold (start or low light intensity), there must not be spurious turn· on of the triac (flashing) due to a high commutation
dl/dl.
UNIVERSAL MOTOR DRIVE
Constraint
Key parameters on a SNUBBERLESS triac
BTA10-600 BW
Simple drive
IGT = SOmA - VGT = 1.SV
Max. start current
ITSM = 100A
IRMS = lOA
(dl/dtlc = 9A!ms
dV/dt = SOOV/~s
Max. power on the load
12t
Fuse sizing
= SOA2.s
_ _ _ _ _ _ _ _ _ _ _ _ ~ SCiS-1HOMSON _ _ _ _ _ _ _ _ _ _ _9_/9
"'!ff
Ii.
~O@OO@[g1~©TIm@llJJ@~
937
APPLICATION NOTE
TRIAC CONTROL BY PULSE TRANSFORMER
Ph. Rabier
Among the many ways to drive a triac the pulse
transformer is one of the easiest. By applYing
some simple rules it can be used to design an
efficient triac triggering circuit without reduction
of the commutation capability of the triac.
I. WHY USE A PULSE TRANSFORMER?
The use of pulse transformers in triac triggering
circuits offers many advantages:
-galvanic insulation between the power and
gate drive circuit (a few kV).
41 The area of the output pulse:
For a given magnetic material the voltage.time
product Vo.to of the output pulse is constant. For
each type of transformer the manufacturer gives
the maximum voltage.time product under no
load operation which corresponds to the figure 1.
51 The rise time tr :
This parameter tr defines the rise time of the
output pulse as shown in figure 2.
Figure 1 : Voltage across the secondary winding
for a rectangular pulse across the primary.
-gate drive circuit with a few components.
-choice of the ~ate current polarity
(triggering in the 2n and 3rd quadrants for
SNUBBERLESS triacs).
-optimization of gate signal (single pulse or
train of pulses).
VS
Vo
Vo/2
-possibility to drive several triacs with only
one drive circuit
II. THE PULSE TRANSFORMER:
To optimize the triac and the pulse transformer
in the application it is necessary to know the
main characteristics of the transformer:
1
to
.. I
Figure 2 : Specification of the rise time at the
output of the transformer.
1I The transformer ratio:
VS
It is the N2/N1 ratio, where N1 corresponds to
the primary winding and N2 to the secondary.
Vo
21 The Lp inductance:
~
G.7Vo
the primary winding inductance measured at a
given frequency.
31 The Rp resistance:
The primary winding resistance· .
AN436/0592
1/5
939
APPLICATION NOTE
Figure 3: Equivalent diagram of the transformer.
11 Thecommutation .
Review: during the conduction a certain quantity
of charges is injected into the triac.
During the fall of the current most of them
disappear by recombination. If the current
decreases too fast the charges do not have time
to recombine and some charge stays in the gate
area. This can provoke a spurious firing.
U N2/N1
The parameter which characterizes the
commutation is the anode current slope (di/dt)c,
that is to say the slope of current before zero
crossing.
The figure 3 shows the diagram
secondary of the transformer:
of the
The specified value in the data sheet is the
critical (di/dt)c. Above this value the triac is liable
to fire spuriously. Figure 5 shows the spurious
firing due to (di/dt)c.
III. GATE PULSE:
21 Case of a triac triggered by a transformer'
11 peak yalue .
When the triac is on, a voltage of about 0.6 V
appears across the gate and cathode. This
voltage is either positive or negative depending
on the anode current polarity. A current i can
flow through the secondary winding of the
transformer (see figure 4).
Due to the inductance of the transformer, at the
end of the half wave the current i continues to
flow in the gate and increases the risk of
spurious firing at the next cycle. (figure 5).
The transformer ratio and the power supply of
the primary winding define the secondary
voltage. With the equivalent diagram and triac
gate characteristics it is possible to determine
the output current. This has to be higher than
the specified gate triggering current (IGT). To
have an efficient triggering it is suitable to use a
safety coefficient of 2 :
IG >
2
IGT
21 Duration'
The Vo.to product defines the maximum pulse
duration at the output of the transformer. The
anode current has to be higher than the
specified latching current (IL) at the end of the
gate pulse.
For drives with a pulse train we can sometimes
use very short pulses ( for example tp =1 OilS
with a 151ls cycle ).
For proper triac triggering the gate current rise
time is very important in a circuit with very high
dildt (>20 AlIlS) : case of resistive load.
Figure 4 : Use of a triac with a pulse
transformeur : when the Triac is on a current i
flows through the gate.
IA
~
I
l§l
..
VGK
IV. THE COMMUTATION:
The use of a triac with a pulse transformer
neeqs some precautions in order not to
decrease the commutation capability.
940
t II
APPLICATION NOTE
Figure 5: Spurious firing of the triac.
spurious firing
I ANODE
5A1div
o ..--.
.'-
.-
-
",-...
'-
-
'-
VAK
::~~:;,:~ .lm~
The influence of the transformer can be
estimated by measuring the critical (di/dt)c of the
triac with and without the transformer.
NOMINAL
CURRENT
IARMS
STEADY
STATE
I (di/dt)c
TRANSIENT
STATE
I (di/dt)c
INCANDESCENT
LAMP
UNIVERSAL
MOTOR
1.35 A
3.8 A
0.6 Alms
1.7 Alms
2.6 Alms
5 Alms
V. THE SOLUTION:
To avoid the reinjected current through the
transformer it is necessary to connect a diode in
series with the gate (figure 6).
The drop voltage VF of the diode avoid the
reinjected current. The triac is triggering in the
2nd and 3 rd quadrants (figure 7).
Example : BT A06-400CW
The specified (di/dt)c of this triac is :
3.5 Alms min at Tj
= 125°C
Measurement of a sample without transformer:
Figure 6 : Bearing of the commutation capability.
(di/dt)c = 6 Alms
Measurement with transformer:
(di/dt)c = 3 Alms -7 on this sample the
commutation capability is divided by 2 !
It is necessary to consider this phenomena and
to take some safety margin (in some cases the
critical (di/dt)c of the triac + transformer can be
lower than the specified (di/dt)c of the triac as
shown in the previous example). This is very
important in the case of transient currents higher
than the nominal value, as is the case with the
cold filament of incandescent lamp, load
dispersion, etc ...
One has to take into account the maximum
(di/dt)c in the application in all cases, especially
in the transient state where (di/dt)c can be
higher than it is in the steady state. The
following example shows values for an
incandescent lamp and universal motor.
- - - - - - - - - - - - - Jb."Y1l
IA
VF
]
I
~- =- - - - - - .-_;1L--
~i~~jmg~~~~~
VAK
3/5
------------941
APPLICATION NOTE
Figure 7 : Correct running with diode.
Figure 9: Equivalent diagram.
no spurious firing
(Rp+R1)(N2/N1)
VF
Lp(N2IN1)
2
VGK
given by the following
Figure 8: Typical application diagram.
Where: tp is the pulse duration
220V
Keep in mind that VGK is negative because the
triac is triggering in the 2nd and 3 rd quadrants.
In practice the area of the pulse has to be lower
than 60 or 70% of the maximum voltage.time
product Vo.to.
VI. TYPICAL APPLICATION EXAMPLE:
The D2 transil diode protects the triac against
overvoltages (see "Protection of triacs and their
control circuits" in the "Thyristors and Triacs
Application manual").
The RC circuit across R1 allows an increase in
the current in the transformer at the beginning of
the pulse. When C is charged the resistance R1
limits the current through the transistor.
4/5
The maximum pulse duration in the output is :
t _ 0.7 VO.to
p- VF- VGK
These two formulae allow us to define the pulse
transformer according to the triac sensitivity.
Example . Numerical application with a
transformer having the following characteristics:
N2/N1
=1
Lp = 2.5 mH
Rp = 0.6 Ohm
Vo.to = 250 VllS
Triac: BTA08-700CW
IGT = 35 mA VGK = -2 V at IG = 2 IGT (quadants
II and III)
------------jI,-yl ~itmi~~~'-----------942
APPLICATION NOTE
diode: VF = 0.7 V
power supply:
VII. CONCLUSION:
U = 12 V
R1 = 100 Ohms
tp max = 65 fls
IG = 70 mA
t = 21 fls
We have measured :
The pulse transformer provides an excellent
method to trigger a triac when galvanic insulation
is required. This system is appropriate to
microprocessor systems.
IG
= 85
mA at t
= 21 fls
- - - - - - - - - - - - - iA."!l
Nevertheless it needs some precautions to avoid
a decrease of the triac commutation behavior.
This precaution is achieved by adding a diode in
series with the gate.
~i~@mgm~~~~~
------------515
943
APPLICATION NOTE
NEW TRIACS
IS THE SNUBBER CIRCUIT NECESSARY?
On inductive load triacs are designed with RC
snubber : these commutation aid networks are
badly optimized in most of applications.
T. Castagnet
Figure 1 : Synoptic of application circuit
with triac.
The subject of this paper is, first of all, to analyze the functions of snubber circuits for triacs
and to propose calculation methods.
But today snubber circuits must be reconsidered
by taking into account the progress of the triac
technology. This article explains how it is now
possible to reduce or to eliminate the snubber,
and thus simplify the AC switch function, thanks
to the high performance in commutation of the
SNUBBERLESSTM triacs.
LOAD
MAINS
INTRODUCTION:
The triac is today the only bidirectional device
able to control various loads supplied by the domestic and industrial mains. It is often designed
with a network made of a resistor R and a capacitor C, the SNUBBER circuil.
This circuit improves the operation of the triac in
its environment but what is its real function?
USE OF THE SNUBBER CIRCUIT ASSOCIATED WITH TRIACS.
DESCRIPTION OF THE TRIAC COMMUTATION.
The triac is a device similar to two SCR back to
back with a common control area.
At turn off the commutation of the triac is the
transient phase during which the load current is
passing through zero and the circuit voltage is
reapplied to its terminals.
The main function of this circuit is to improve the
switching behavior of the triac at turn off : we will
explain how and suggest some methods to
define il.
Figure 2 : Example of triac structure and its equivalent simplified circuit.
'"
AZ
AN437/0592
1/7
945
APPLICATION NOTE
Figure 3 : Commutation on inductive load
of BTB10-600BW
'"
~
!
ov :
..
!
;.- -
-j----
~
TRIAC VOLTAGE
100V/DIV
---OA
,
... ....
:t
....
~
TIME =
"
The circuit voltage Va is reapplied to the device
when IT = IR;
TRIAC CURRENT
50mAIDIV
"- ;?
_.
-.
I
!
.... t- ----t--
I···· !",L-"
At turn off a recovery current, IR,appears commonly when dlTfdt > 0.1 x (dlfdt}c; (see fig.3).
I
$
-----
Tj= 125°C; dlT/dt = 2.3A/ms dV/dt 21VJJ.1s--------
MAIN HYPOTHESIS ON COMMUTATION:
The analysis ot' commutation shows that:
20~s1D1V
CAPACITIVE
CURRENT
The spurious firing is possible as far as there is
a reverse current (made of recovery or Capacitive current) : mean while each dVfdt is able to
provoke the triac refiring; (see fig. 4).
Figure 5 : Application circuit (a) and its
equivalent diagram at commutation (b).
PARAMETERS OF COMMUTATION.
For a given device and a determined junction
temperature the risk of a spurious firing is
possible. It is linked to:
R
The rate of removal of the triac current dlTfdt
before zero crossing because it determines
the quantity of stored carriers which could be
injected in the gate area or the opposite thyr·
istor;
c
(a)
The rate of rise of the reapplied triac voltage,
dVfdt, which creates a current through the
gate because of the junction capacitance.
The parameters which characterize the perform·
ance of the triac commutation are the critical rate
of removal of the current (dlldt}c and the critical
rate of rise of voltage, (dVfdt)c : above these
values the triac fires again spontaneously.
Figure 4 : Spurious firing at commutation
for a BTB06-600S
AIM OF THE SNUBBER CIRCUIT.
The today method to choose a triac on inductive
load consists in :
- selecting one triac with RMS current, ITRMs,
suitable with dlTfdt of circuit ; because for conventional triac the specified (dlldt)c values is
linked to the current rating by the relation:
(dlldt)c= 2x I1 x fx -ffxITRMS
TRIAC
~~~-4-~~-+~-+-1-~¥~}~~?J
~
... , ........ \ ................ 1.. .... ..
~
I J
f-++-t-+-+--j\."\,~c-+-+--j TIME
~
This value must be higher than dlTfdt of circuit.
- limiting the maximum reapplied dVfdt below
the specified value (dVfdt)c·: this is the main
function of the snubber circuit.
~O~A~~~~~~.~~~~~~OV
""tv
(b)
=
20~s/DIV
~+-~-4-r-~-+-~~r-~--1
........................ \ ........ " " ..... TRIAC
l'..
I . .~
~~~~~~~~~--~
Tj = 100°C; dlT/dt = 1.SA/ms dV/dt =
CURRENT
50mAIDIV
17V/~s
_2/7_ _ _ _ _ _ _ _ _ _
r== SGS-mOMSON-----------
"'!1
It."
946
IilijO(!;II3@rn[\,~(!;'ii'OO@[lI]O(!;:li
APPLICATION NOTE
CHOICE OF THE SNUBBER CIRCUIT.
The aid circuit makes up a resonant circuit with
the load. At turn off it limits the slope of reapplied voltage dV/dt but generates an overvoltage
VM. Its choice results of a compromise in order
to respect triac specification ((dV/dt)c and repetitive peak off state voltage (VORM).There are two
possibilities:
11 for low VORM the resonant circuit must be
damped, reducing VM and dV/dt- (§ 2 of
annex) ;
PROGRESS MADE ON TRIACS.
PREDOMINANCE OF (dl/dt)c AND LIMITATION
OF dV/dt :
The study of the commutation behavior of triac
can be made thanks to the curve of the critical
commutation performance of each sample
(dlldt)c versus various reapplied (dV/dt)c.
Figure 7 : Critical (dl/dt)c versus (dV/dt)c
for BTB10-600B sample
21 with higher voltage possibilities the circuit can
oscillate and the capacitor adjusts straightly the
dV/dt (§ 3 of annex)
Today we use commonly triacs with VORM = 600
V or more. Therefore we suggest the second
way because capacitor is smaller (reduced 4
times).
dlTldt (Alms)
10
............
C
THE DISADVANTAGES OF THE SNUBBER
CIRCUIT.
The snubber circuit improves the triac behavior
but it imposes to the device stresses which limit
its use.
At turn on the discharge of the capacitor creates
a pulse current with high repetitive dlT/dt which
can destroy the triac by local overheating near
the gate. It is recommended to limit the amplitude of current with a resistor higher than 50
Ohms and the turn on dl/dt below 20 Nils.
Figure 6 : Triac turn on with snubber circuit
IT
dVldt
- d
-
AREA OF
(VI~s)
SPURIOUS~FIAING AT ~OM~UTATION
For a conventional triac (IGT > 25 mAl the critical (dlldt)c is not much sensitive to the (dV/dt)c :
so it represents the most significant parameter to
characterize the triac behavior in commutation
(fig.7).
Without snubber circuit the (dV/dt)c is limited by
the junction capacitance of the triac (point C).
In order to improve commutation behavior of
triac and to eliminate the snubber circuit the parameter (dlldt)c has to be increased on all range
of dV/dt.
R
We also notice the efficiency of the snubber circuit in commutation -(dlldt)c- is lower than two by
reduction of dV/dt from its natural limitation
( point C ) to 0.1 V/IlS.
c
Jl
PERFORMANCES OF THE SNUBBERLESS
TRIACS:
The current, which flows through the snubber circuit when the triac is off decreases the off state
quality of the switch : this leakage current (several mAl could create problems for small loads
like electro-valves, micro motors .......
_ _ _ _ _ _ _ _ _ _ _ r.=-=
.."'fl
This analysis permitted the development of new.
triacs with better performances in commutation :
the SNUBBERLESS triacs which have got a new
design with improved triggering mechanism and
better decoupling of single integrated thyristors.
SIiS.1HOMSON _ _ _ _ _ _ _ _ _ _ _3_17
IiiilD©iRJ©~D,IliQ;1i'iRJ©U\!D©®
947
APPLICATION NOTE
For same size and gate sensitivity the improvement ratio on (dlldt)c is higher than 3.
Figure 8 : Comparison between conventional and snubberless 10 A
, triacs.
dlT/dt (Alms)
50 """'3D -
__
~
Tj= Tj max,
~
_________________
20,
,
.......
,
>3TIMES
,
10
-._._._._._._.
5
3
2
1
conventional
k-~
-
----
snubberless
- In application the dlT/dt through the triac is not
adjustable because it is given by the circuit (Va
and L) ; its measure permits the choice of this
triac with the commutation parameter, (dlldt)c.
- The commutation behavior is no more straightly
linked to the current range and the high (dlldt)c
allows a reduction of the die size,
For example a universal motor of 1200 W - 220
V can be driven by a BTB 10-600 BW (*) instead
of the BTB15-600B(**).
(*)
10 Amps SNUBBERLESS triac with
VORM = 600 V and IGT = 50 mA; specified at
9 Nms without snubber.
(**) 15 Amps conventional triac with VORM =
600 V and IGT = 50 mA; specified at
6.7Nms with dV/dt limited to 10 V/IlS.
_ _~~_ _~_ _~~~~~~
0,1 0,2
0,5
1
2
5
10
20
50 100
dV/dt (V/us)
So we can specify now the commutation behavior with (dlldt)c for a value dV/dt from 0 to its
natural limitation by the junction capacitance
(without snubber circuit),
Table 1 : Commutation specification
(dl/dt)c of some SNUBBERLESS
triacs (Alms)
TRIAC SUFFIX
dl/dt on 50Hz
sine pulse
(Alms)
CURRENT
RANGE (A)
AW
BW
CW
6
8
5
3.5
2,7
10
12
9
5.5
4.4
16
21
14
8.5
7
25
33
22
13
11.1
CONSEQUENCES
CUlTS:
ON
APPLICATION
IS IT ALWAYS POSSIBLE TO REMOVE
THE SNUBBER CIRCUIT?
The answer is not in the affirmative because
sometirnes it has other functions:
- improvement of the triac immunity against transients in the off state ;
- compensation of latching current at turn on (not
dealt in this paper).
Switching on and voltage perturbations can provoke overvoltages and fast voltage variations
across the triac:
- this one could break over when the overvoltages are higher than its repetitive peak off state
voltage, VORM ;
- due to the junction capacitance fast voltage
variations create a gate current and could trigger
the triac; the device limit is the rate of rise of the
off -state voltage, dVIdt.
The snubber circuit can improve the triac behavior in off-state. But its efficiency is linked to the
values of series inductance L at the oscillation
frequency of perturbations (typically 100 kHz).
We could add a saturable inductor in series with
the triac when L is too low : particularly this is
the case of resistive load.
CIR-
The SNUBBERLESS triacs offer application ad.vantages:
- The function of commutation aid of the snubber
circuit disappears : we can remove it ;
IMPROVEMENT OF THE IMMUNITY TO TRANSIENT VOLTAGES (STATIC DV/DT) :
When the circuit has its specific overvoltage suppressor, as clamping diodes (TRANSIL), the aim
of the snubber circuit is to reduce only dV/dt for
- - - - - - - - - - - - - J..'Yl. ~i~~mYml~~~~ ------------4/7
948
APPLICATION NOTE
triac voltage lower than VDRM. It must be
damped, limiting its overvoltage and the current
in the suppressor. The § 2 of annex permits to
choose the values:
Figure 10 shows the maximum allowed overvoltage Vp versus ;j LxC remaining the triac voltage
below 600 V.
But the efficiency of this circuit is poor and we
prefer use other ways of overvoltage protection :
input filters and suppressor (see fig.8).
R< 0.8x Lx (d%t)IVDRM
For a 1200 W motor with L (100 kHz) # 5 mH a
BTB 10-600BW triac needs a snubber circuit of
3.3 kQ and 1 nF (fig.8).
Figure 9 : Example of improved off-state
immunity for triac
CONCLUSION:
Used today as commutation aid network the
snubber circuit can be well optimized thanks to
higher blocking voltage VDRM : we obtain a reduction of the capacitor size.
But with the SNUBBERLESS triacs the aid function of the snubber circuit disappears. Because
of the improvement of the commutation performance ( higher critical (dl/dt)c ) these new triacs
offer a cost reduction by decreasing of their size,
and permit to eliminate the snubber circuit in
most of applications.
However the snubber circuit, associed to series
inductance, could limit the off state voltage variations. But its efficiency against overvoltages is
poor and we prefer to replace it by specific protection devices.
PROTEC,TION AGAINSTOVERVOLTAGES:
The snubber circuit could be a simple circuit in
order to reduce overvoltage VM. It must operate
as a low pass filter with minimum resistance (50
Ohms) avoiding turn on current stresses.
Figure 10 : Snubber circuit efficiency
against overvoltage Vpp
(Triac voltage<600V)
vpp (V)
1.500
1.000
VDRM
500
r--
~
~
k
R",,500hms
V
,/
,
'0>
jf\
- Analysis and design of snubber networks for
dv/dt suppression in triac circuits (RCA) AN 4745
- 1971
JE WOJSLAWOWICZ.
- For energy conversion and motor control
triacs or alternistors.
Pierre RAUL T and Jean Marie PETER
THOMSON CSF for PCI September 1982.
VPP!2~
~
150
JL.C
REFERENCES:
- Improvement in the triac commutation 1989.
P.RAULT SGS THOMSON-Microelectronics.
5
7
tlo's)
10
.10E 5 (s)
-------------1t."1l
~~~@m~m~~~©~
------------5/7
949
APPLICATION NOTE
e
DETERMINATION OF THE COMPONENTS
OF SNUBBER CIRCUIT .
• 1 - SNUBBER CIRCUIT OPERATION
The load inductance L and the snubber circuit
make up a resonant circuit across which the
mains voltage is reapplied at turn off. The RC
circuit limits dV/dt but generates an overvoltage
VM which must be lower than VORM.
We can analyse VM and (dV/dt)max with their
relative parameter versus the damping factor F :
Figure A1 :overvoltage (e) versus damping factor F.
't---
.7
'\
.6
.4
'\
.3
Therefore these are the two methods in order to
choose the snubber circuit.
.!
.05
.1
.5
X
RIL
However F must be low (F = 1) in order to reduce the capacitor and the resistor dissipation
power PR :
f\
.2
.01
F> 0.5 and F < 0.1
R x {Cif/2> 0.5 and ( d\fdt)c > Va
\
.S
!
These curves show there are two intervalles
where variations if F -due to the tolerance of tile
components- don't almost modify the overvoltage value:
CIRCUIT WHEN F > 0.5 :
VM is limited first of all (e < 1.3) thanks to the
capacitor C ; the resistance R sets the slope
(dV/dt)max .
r---...
.S
F = Rx -VCIU2
• 2 - DETERMINATION OF THE SNUBBER
e
.9
= VMIVa
o = R x C x ( d\fdt )MAXI Va
Annex:
'-----
!O
r
C>4 x( Va)2/(L x (d\fdt)C 2 )
and
Figure A2 : rise slope (0) versus damping
factor F.
R< Lx (d\fdt )ciVa
with
500
PR < 2.C.Va2 .f
VMNa < 1.2
Va = Vac X {2 x sin<\>
Vac = RMS mains voltage
f = mains frequency
cos<\> = power factor of load
L = inductance of load when zero crossing
r = resistance of load
'00
100
50
/
!
.5
V
1
.05
,
.0
.0 1
6/7
.Cl5
.f.
.5
5
10
- - - - - - - - - - - - - ..."l
950
An inductive load of 2000 VA - cos<\> = 0.6 on
220 V-50 Hz mains can be controlled with a
~i~~m~ll~~@~-------------
APPLICATION NOTE
triac specified @ (dV/dt)c = 10 V/',lS by using:
with
PR < 2.C.Va2 .f
e = VMNa <1.9
Va = Vac x;)2 x sinVa/(LxC)
The resistance value has to keep a sufficient
value (F = 0.05) in order to limit stresses on triac
at turn on (see 1.5)
PR = 0.08 W
VM = 525V (choose a triac with VORM=600 V)
• 4 - COMMENTS:
Today the triac offers blocking voltage VORM up
to 800 V : so we suggest the second method
because the capacitor is smaller, (reduced by 4)
and the reapplied slope dV/dt is less sensitive to
damping factor variation and so better controlled.
These values obtained by calculation are slightly
overrated because the real slope of the reapplied voltage is limited also by the junction capacitance of triac.
and
R+ r< 0.1 x L x (d%t )clVa
----------J,.,,,.
•J, .
SGS-mOMSOM _ _ _ _ _ _ _ _ _ _7_17
IR:IU©Ilil@Il!~m©lIllil@li(i]u:Gi0
951
APPLICATION NOTE
TRIAC + MICROCONTROLLER
SAFETY PRECAUTIONS FOR DEVELOPMENT TOOL
Ph. Rabier
The goal of this paper is to analyse the different
ways to configure a micro-controller and a
development tool during the debbugging phase.
The major problem is due to the direct
connection of the computer I/O lines with the
mains power. Some precautions have to be
taken during the emulation in order to avoid
destruction.
The consequence is that there is no insulation,
the microcontroller is connected directly on the
line!
When the software is emulated on the
application board, the output port (RS232 port)
of the computer is connected on the line via the
emulator.
If some precaution
will be destroyed !
I - LOW COST POWER SUPPL V
In most low cost applications the step down
transformer is not used and the power supply
delivers low current, as shown for example in
figure 1.
is not taken "something"
Figure 2 gives an example of an application
using a triac and a microcontroller.
Figure 2 : Triac and microcontroller on the line.
Figure 1 : Uninsulated power supply.
Al
G
LINE
LINE
I
I3ZX55C5V6
~
I ~-L~~
~
1/2W
lN4148
n
A2
LOAD
220nF
ov
In domestic appliance applications, one of the
most important power switches is the triac.
The function of driving the triac becomes more
and
more
complex.
For
this
reason,
microcontrollers are becoming more and more
common. Furthermore, sensitive triacs with high
commutation parameters, for example LOGIC
LEVEL triacs can be triggered directly by the
microcontroller without any buffer. Sensitive
triacs and microcontrollers allow decrease in
power consumption.
In this way the power supply can be optimized to
reduce the cost. Optimisation can be achieved
by removing the transformer.
AN438/0592
In this case the micro-controller is supplied by
an uninsulated +5 V power supply connected
directly to the line, and a low level (OV) on the
output ports of the micro-controller is needed to
trigger the triac.
II - USE OF A DEVELOPMENT TOOL
During the debbuging phase, the micro-controller
is removed and is replaced by the emulation
probe. The circuit corresponding to the emulation
phase of the previous example is shown in fig. 3.
The line is connected directly to the +5V of
the emulator and a high (destructive) current
can flow through the emulator and/or the
computer.
1/3
953
APPLICATION NOTE
Figure 3 : Circuit without protection
Figure 5 : Optotriac drive.
(Beware: this circuit is dangerous).
100
.5V
LINE
LINE
(HIGH DESTRUCTIVE
CURRENT)
III - INSULATED SYSTEM
To avoid destruction of the development tool it is
necessary to have an insulation between line
and probe. This insulation can be achieved by
optocouplers, pulse transformers, or insulation
transformers.
Figure 4 shows the topology of the most
common insulation.
Figure 4 : Conventional insulation.
The main advantage of a such system is the low
cost of the optotriac, but it needs an isolated
auxiliary power supply.
For a zero crossing optotriac, the triac is
triggering with a gate current equal to the gate
trigger current with a very low dlG/dt. This does
not allow high dildt at turn on. That is to say the
control of high .current resistive load is not
recommended with this method.
21 The pulse transformer
Figure 6 shows the circuit with a triac and a
pulse transformer.
The triac is working in the 2nd and 3rd
quadrants.
Figure 6 : Pulse transformer insulation.
LINE
(Fram(lxlernal
inSulated
~~Ulse
powersupply)
·cstormer
POWER 1
DRIVE
LINE
11 Optotriac
Figure 5 shows the circuit with triac and
optotriac.
The triac is working in the 1st and in the 3rd
quadrants.
2/3
954
APPLICATION NOTE
This system is simple to use when the triac was
initially driven by a buffer transistor, but it needs
an external power supply. The high dlG/dt
through the gate allows high current resistive
loads to be driven. Due to the saturation of the
magnetic material, this system cannot drive
small loads because the gate current is
cancelled before the latching current has been
reached.
For more information refer to the application note
"Triac control by pulse transformer".
3/ The line insulation transformer
In the previous examples,the insulation was
between the triac and the microcontroller.
Another solution is to supply each equipment
connected to the board from the mains through
an insulation transformer.
If an oscilloscope is used, it also has to be
separately insulated.
The main advantage of this system is that we do
not need to modify the target system during the
debbuging phase and it can be used with the
microcontroller.
When a transformer is used between line and
triac it should be noted that the line impedance
is modified and then the behaviour of the triac,
load and line set can be different (waveform of
current).
Figure 7: Insulation with transformers.
IV - SUMMARY
New LOGIC LEVEL and SNUBBERLESS
triacs
can be connected directly to the
microcontroller without buffers or insulation.
Furthermore, low cost power supplies without a
transformer are becoming more common. There
is an increasing number of applications supplied
directly from the mains, and the microcontroller
is directly connected to it.
During the debbuging phase when connecting
the development tool, a galvanic insulation is
absolutely necessary.
This inSUlation can be done in 3 ways:
- With optotriacs :
• Need modifications on the target system
• Need external power supply
- With pulse transformer:
• Need modifications (transistor to drive the
pulse transformer)
• Need an external power supply
• Cannot drive small loads
- With insulation transformer:
• No modification on the application board.
• Modification of the line impedance due to the
transformer between line and load.
Therefore a microcontroller operating on the
mains with a triac may be directly connected to
the line.
955
APPLICATION NOTE
IMPROVEMENT IN THE TRIAC COMMUTATION
P. Rault
In the last few years, the use of triacs has
spread to all areas of electronics, including
domestic appliances and industrial applications.
The use of triacs has been traditionally limited by
their switching behavior in applications where
there is a risk of spontaneous firing after
conduction. In order to obtain the required
reliability in today's equipment, the designer
must take a certain number of precautions: over
dimensioning of the device, switching aid
networks (snubber), significant margin of security
of the junction temperature,etc. This generally
involves additional costs.
After a brief discussion of commutation problem
when a triac is turned off, this article will
describe the progress made in this area and the
newest possibilities now offered to triac user
thanks to the new series Logic Level and
SNUBBERLES&M triac.
THE COMMUTATION PROBLEM OF THE
TRIAC
In its electrical representation the triac can be
compared to two thyristors mounted in
anti-parallel and coupled with a control device
which allows activation of this AC switch with
only one gate (fig. 1a).
In considering the structure of a triac (fig. 1b),
one notices that the conduction zones,
corresponding to these two thyristors and which
control the current in one direction and then in
the other, narrowly overlap each other and the
control zone.
During the conduction time, a certain quantity of
charges is injected into the structure. The
biggest part of these charges disappears by
recombining during the fall of the current in the
circuit, while another part is extracted at the
moment of blocking by the inverse recovery
current. Nonetheless an excess charge remains,
particularly in the neighboring regions of the
gate, which can provoke in certain cases the
firing of the other conduction zone at the
moment when the supply voltage of the circuit is
reapplied across the triac. This is the problem of
commutation.
For a given structure at a determined junction
temperature, the switching behavior depends on:
11 The quantity of charges which remains at the
moment when the current drops to zero. this
number of charges is linked to the value of the
current which was circulating in the triac
approximately 100 microseconds before the
cut-off. (This time corresponds to two or three
times the life time of the minority carriers). Thus,
the parameter to consider here will be the slope
of the decreasing current which is called the
commutating di/dt, or (di/dt)c. (fig. 2)
21 The speed at which the reapplied voltage
increases at the moment when the triac turns off,
which is called the commutating dv/dt, or
(dv/dt)c. (fig. 2)
A capacitive current, proportional to the (dv/dt)c,
flows into the structure, and therefore injected
charges are added to those coming from the
previous conduction.
Figure 1 : (A) Simplified equivalent schematic of triac circuit.
(8) Example of a triac structure.
AN439/0592
1/10
957
APPLICATION NOTE
CHARACTERIZATION
Figure 2 : Triac voltage and current at
commutation.
In order to characterize the switching behavior of
a triac when it turns off, we consider a circuit in
which we can vary the slope of the decrease in
current (di/dt)c. In addition, we control the slope
of the reapplied voltage by using, for example, a
circuit of resistors and capacitors connected
across triac to be measured. For a determined
(dv/dt)c, we progressively increase the (di/dt)c
until a certain level which provokes the
spontaneous firing of the triac. This the critical
(di/dt)c value.
Ir
(Triac current)
,,
,
Therefore, for different (dv/dt)c values, we note
the critical (di/dt)c value for each sample. This
makes possible to trace the curve of the
commutation behavior of the triac under
consideration.
Vr
(Triac voltage)
Voltage in conducting
Slate
Figure 3 represents the results obtained with a
standard 12 Amp triac (lGT 50mA) and a
sensitive gate, 6 Amp triac (lGT 10mA). For
standard triacs the critical (di/dt)c is sightly
modified when we vary the (dv/dt)c. For sensitive
gate triacs, this parameter noticeably decreases
when the slope of the reapplied voltage is
increased.
Figure 3: Critical (di/dt)c versus (dv/dt)c (below the curve the triac turns on spontaneously.)
A1 and A2 : The rate of re-application of the off-state voltage of these points corresponds to the mains
(sinusoidal wave form) at zero crossing.
81 and 82 : The (dv/dt)c is limited by a snubber at the values generally specified in the data sheets
(5V/lls or 10V/lls).
C1 and C2 : These points are obtained without snubber.
(dl/dt)c
(Alms)
W
20 t---
CRITICAL
(dl/d~)c
/i
~-
I
VERSUS (dV/d~)c
I
SAMPLE /11
1ZA TRIAC
Az
10
5
J
I
r-.~
-r-- i""----
1j=11QoC
2
1
.1
2/10
.l!
.5
I
Vi
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z
5
'.I"
~~z
SAMPLE #2.
5EN51T1'11E TRIAC
c~··J
10
I
20
.
so
100
(dV/drlc
(YljJ~)
-------------~.,l ~~~@m~I~~~~~------------958
APPLICATION NOTE
In practice, the current wave form, and thus the
(di/dt)c, is imposed by the circuit. Generally we
cannot change it.
So, in triacs applications it is always necessary
to know the (di/dt)c of the circuit in order to
choose a triac with a suitable critical (di/dt)c.
This is the most important parameter.
Suppose a circuit in which the (di/dt)c reaches
15 Alms. The triac N"1 characterized by the
upper curve in figure 3 is not suitable in such a
circuit even if the (dv/dt)c is reduced nearly to
zero by connecting a huge snubber network
across it.
APPLICATIONS IN BASIC CIRCUITS
When
considering
the
constraints
in
commutation at the turn off of a triac, we can
distinguish two cases:
1/ The use of a triac on resistive load (fig. 4)
In this case the current and the voltage are in
phase. When the triac switches off (i.e. when the
current drops to zero), the supply voltage is
nullified at this instant and will increase across
the triac according to the sinusoidal law:
V = Vm sinoot
Figure 4 : Current and voltage ware forms for resistive loads
(A) Case On / Off switching
(8) Case of phase control
I
In
GOo
G,. """
.
t
'/n""
0 0 0
r
I Triac
I Triac
....t
V Triac
V Triac
, . -....,
,,
:
\
,..- ..,
,,
\
\
:
,
,
\
\
\
r
I
I
'-~ Supply Voltage
(B)
(A)
- - - - - - - - - - - - - - &"'Yil
~~~~m~~~~~!S~
-------------3/10
959
APPLICATION NOTE
Example:
2/ The use of a triac on inductive load
For the European mains of Vrms = 220 volts at
50Hz, the slope will be:
In this case there is a phase lag between the
current and the supply voltage (fig. 5).
(dv/dt)c = Vm x co = Vrms x -,f2 x co = 0.1 %8
When the currents drops to zero the triac turns
off and the voltage is abruptly pushed to its
terminals. To limit the speed of the increasing
voltage, we generally use a resistive/capacitive
network mounted in parallel with the triac. This
"snubber" is calculated to limit the (dv/dt)c to 5
or 10 volts/1l8 according to the specified value in
the data sheet. This case corresponds to points
81 and 82 in figure 3.The (di/dt)c is also
determined in this case by load impedance (z)
and the supply voltage.
This relatively low (dv/dt)c corresponds to points
A1 and A2 on the curves in figure 3. As far as
the (di/dt)c is concerned in the circuit, it depends
on the load. For a resistance of loads Rand
under a Vrms voltage, we will have:
(di/dt)c =Im x co = ( Vrms x -,f2/R) x co
Figure 5 : Current and voltage ware forms for inductance loads
(A) Case On / Off switching
(8) Case of phase control
o
l"
"
I Triac
I Triac
V Triac
,,
Cdl//dt)c
\
\
\
.
,
,
I
I
I
,
,
\
\
'-
'-'
I
"
Supply Voltage
(A)
4/10
(B)
- - - - - - - - - - - - L ' Y l ~~i@m~I1~~~©~-----------960
APPLICATION NOTE
THE USE OF A TRIAC WITHOUT A SNUBBER NETWORK
For example, the internal capacitance of a 12
Amp triac is about 70pF. Therefore, on inductive
load, the maximum (dv/dt)c without snubber will
be limited to 50 or 100 VIS according to the
characteristics of the load.
The triac can thus be considered as a switch
which turns off at the moment when the current
is cut off in the dampened oscillating circuit
constituted by the loads Land R and the internal
capacity of the triac Ct (fig. 6). In the case of a
pure inductive load, the maximum reapplied
(dv/dt) is:
It is interesting to know the behavior of the triac,
in particular the critical (di/dt)c value, in these
conditions. This characterization corresponds to
the points C1 and C2 of the curve fig 3.
(dv/dt)c = --.J2 Vrms x Irms x Ol/et
Figure 6 : Triac commutation on an inductance load without a snubber network
LOAD
o
~
I
LOAD
cSOOEooH
R
t"C
0
I
11
eI
r-
'IT
t'lc
r
A progress: THE NEW TECHNOLOGY
To make significant progress in the triac area is
to essentially improve the commutating behavior
at the turn off of the triac. In other words the
critical (di/dt)c has to be improved.
In order to reach this goal, a new structure has
been developed. In this structure, the different
active zones have been de-coupled to the
maximum in such a way as to separate the
elementary thyristors and the gate area. This is
made possible by sacrificing the gate triggering
in the fourth quadrant. In practice this does not
pose a problem because the gate drive circuits
of a triac generally use two of the third first
quadrants. (fig. 7)
Figure 7 : Basic gale drive circuits (the fourth quadrant is not used)
R
~OP10C(ItJPI.ELIR
'.halOni.cl
311
®
®
- - - - - - - - - - - - - ~~l
~~~@m~I~~~©~
®
SilO
-------------
961
APPLICATION NOTE
For a given technology, the commutating
behavior of triacs depends on the sensitivity of
the gate. The correlation between the critical
(di/dt)c and the gate current for 12 Amp triacs is
represented in figure 8.
In the same chart, we can see the results
obtained with conventional triacs versus the new
technology triacs. As can be seen, the progress
that has been made at this level is significant.
1/ The performances and specifications
Figure 8 : Correlation between commutating behavior and sensitivity.
(Measurements performed on several lots of 12 A triacs)
Critical
(di/dt)c
AimS
25
• NEW TECHNOLOGY PARTS
I.3!iJ CONVENTIONAL TRIACS
•
• •
20
15
•
•
• •
30
•
10
5
Igt 3rd quadrant (rnA)
0
10
40
30
2D
The new technology has been put into place
with the manufacturing of the two new series,
Logic Level and SNUBBERLESS Triacs. In the
data sheets of these new triacs a critical (di/dt)c
limit is specified at the maximum junction
temperature (Tj max).
I
I
50
60
In the data sheets of the Logic Level triacs a
minimum (di/dt)c is specified for the following
cases:
* Resistive load with
a (dv/dt)c of 01.V/lls.
* Inductive load with a (dv/dt)c of 20 V/IlS
a- Logic Level triacs
In this category we consider sensitive triacs in
which the maximum gate current (IGT) is SmA
for the TW type and 10mA for the SW one.
Symbol
tgt
For example the 6 Amp triac is specified as
follows:
Test conditions
Quadrant
Tj = 25°C
VD = VDm,; IG = 90 mA
I - II - III
Suffix
Unit
TW
SW
TYP
2
2
).ls
MIN
3.5
1.8
4.5
3.5
Alms
dlG/dt = 0.8 Alms
(dl/dt)c *
dV/dt = 0.1 V/).ls
Tj = 110°C
dV/dt = 20 V4ts
* For either polanty of electrode A2 voltage with reference to electrode A1.
_6/_10_ _ _ _ _ _ _ _ _ JI>...'L
962
.",
MIN
SCiS·1HOMSON---------iIlllD[:[i;]@I<~~(l;'jJITiI@If:IlD©ill
APPLICATION NOTE
b- SNUBBERLESS TRIACS
This series of triacs presently covers the range 6
to 25 Amps with gate currents of 35mA (CW
type) and 50mA (BW type) according to the type
required.This series has been specially designed
so that the triacs switches from the on state to
the off state without the use of an external
snubber circuit.
Whatever the nature of the load, there is
absolutely no risk of spurious firing at the turn off
of the triac as long as it is functioning under the
specified (di/dt)c value.
The SNUBBERLESS triacs are specified at
critical (di/dt)c values which are greater than the
decreasing slope of the nominal current in a
sinusoidal configuration. For example, the slope
of the current in a triac conducting 16 Amp when
the current drops to zero is:
(di/dt)c = Irms x -ff x (J) = 7A1mS at 50Hz
The BTAlBTB16-600BW is specified at (di/dt)c =
14A1ms.
The
following
table
summarizes
the
characteristics of the BW, CW SNUBBERLESS
triacs which are presently available:
WITHOUT SNUBBER
TYPE
CURRENT 1 VOLTAGE
SUFFIX
IGT
MAX
(rnA)
STATIC dV/dt
MIN
(V/IlS)
(dl/dt)c
MIN
(Alms)
BTA 1 BTB
06A
200 to 800V
BW
CW
50
35
500
250
5
3.5
BTA 1 BTB
08A
200 to 800V
BW
CW
50
35
500
250
7
4.5
BTA 1 BTB
10A
200 to 800V
BW
CW
50
35
500
250
9
5.5
BTA 1 BTB
12A
200 to 800V
BW
CW
50
35
500
250
12
6.5
BTA 1 BTB
16A
200 to 800V
BW
CW
50
35
500
250
14
8.5
BTA 1 BTB
20A
200 to 800V
BW
CW
50
35
500
250
18
11
BTB
24A
200 to 800V
BW
CW
50
35
500
250
22
13
BTA
26A
200 to 800V
BW
CW
50
35
500
250
22
13
21 The advantages and Applications
The specification of the critical (di/dt)c value on
both resistive and inductive loads allows one
a - Logic Level
The goal of these triacs is to be controlled
directly by logic circuits and microcontrolers like
the ST6 series:
Outputs of ST6 can sink currents up to 20mA
per 1/0 line, and therefore drive TW and SW.
11 to know the margin of security of the circuit in
relation to the risk of the spurious firing, which
results in improved reliability, and
21 to optimize the performance of the triac to be
used, which results in a cost reduction.
These triacs are ideal interface for power
components supplied by 110 or 220 volts, such
as valves, heating resistances, and small
motors.
-------------i.'1l
~~~~m~:~~~©~
------------7/10
963
APPLICATION NOTE
Figure 9: Light dimmer circuit with ST6210.
LINE
FUSE
3X4.7M
19
15
TOUCH SENSOR
18
ST621 0
MODE
14
PUSH BUTTON
A2
100kF
BTA 08-400SW
ov
ov
20
220k
100k
220k
220k
22k
10P
-r -r
ov
POTENTIOMETER
10P
ov
ov
OV
ov
All resistors
1/4W unless otherwise specified
NEUTRAL
b - SNUBBERLESS Triacs
The commutation of SNUBBERLESS triacs is
specified without a limitation (dv/dt)c. With the
suppression of the snubber in the circuit, there is
a noticeable cost reduction.
Each SNUBBERLESS triac series is specified
with a critical (di/dt)c value and the static (dv/dt)
at the highest possible level, taking into
consideration the gate sensitivity (Igt). The
minimum specified levels for these two
parameters allows the use of these products in
circuits where there is a need for high safety
factor, such as:
1. Static relays in which the load is not well
defined. With conventional triacs it is difficult to
·964
adapt the snubber to all possible cases.
SNUBBERLESS triacs resolve this problem.
(fig. 10).
Figure 10 : Solid state relay diagram
INPUT
....._-1-1
OPTO INSULATED
DRIVE CIRCUIT
ZERO CROSSING
CIRCUIT
r--,--+-I
APPLICATION NOTE
Figure 11 : Motor control circuit using
SNUBBERLESS triacs
(Ls + r = network for series protection)
Figure 13 : Example of a circuit with high
(di/dt)c
Inductive load
(Motor, valve ...)
GATE: MIVE CIRCUIT
/
2. Motor drive circuits. Figure 11 shows an
inversion circuit of an asynchronous motor where
spurious firing of the triac, normally assumed to
be in off- state, must be absolutely be avoided.
Circuits which generate wave forms with a very
high (di/dt)c, such as inductive load supplied by
a diode bridge (fig. 13). It is only limited by the
parasitic inductance of the AC circuit.
The critical (di/dt)c of SNUBBERLESS triacs is
greater than the slope of the nominal current of
the specific type under consideration. This is
important for several applications, including :
Circuits in which the (di/dt)c in a transient state
is greater than in the steady state. This is the
case for universal motors controlled by AC
phase control circuit. The table in figure 12
shows how to the use of a SNUBBERLESS triac
can optimize the efficiency of the circuit.
Figure 12: Universal motor control: Triac choise must comply with maximum {dl/dt)c
For example, a SNUBBERLESS 10 A triac is sufficient to control
a 110 V AC 600 W moytor
POWER
SUPPLY NOMINAL MAX CURRENT
VOLTAGE CURRENT TO CONTROL
TRIAC
RANGE
(dl/dt)e
MAX (1)
STANDARDS
TRIAC
SNUBBERLESS
TRIAC
BTA10-600B
BTA16-400B
(2)
BTA16-600B
BTB24-400B
BTA06-600BW
BTA10-400BW
600W
220V/50Hz
110V/60Hz
3 ARMS
6ARMS
3.5 A
7A
6A
10 A
AA/ms
7 Alms
1200W
220V/50Hz
110V/60Hz
6 ARMS
12 ARMS
7A
14 A
10 A
16 A
7 Alms
15 Alms
BTA10-600BW
BTA20-600BW
(1) Maximum transient (dl/dt)c. This parameter depends very much on the type of the motor.
(2) This type specified at 7 Alms munumum can be too small certain applications could need 25 A
standard triac.
9/10
- - - - - - - - - - ~'9' SCiS·THOMSON - - - - - - - - - •J I, ~O©OO@]~~©'iTOO@u;mJ©:ll
965
APPLICATION NOTE
CONCLUSION
Thanks to the recent progress made in triac
technology, the designer now has at disposal
devices with a commutating behavior which is
compatible with all applications in the 50 or 60Hz
range. This includes phase control and static
commutation for loads going from a few watts to
several kilowatts.
The capability of this new generation of triacs
allows:
1/ To increase the reliability of circuits,
particularly where there is a risk of spontaneous
firing even in the most difficult configurations.
10/10
2/ To reduce the cost by using sensitive gate,
LOGIC LEVEL triacs without the need for an
interface between the gate and the logic circuit,
or utilizing SNUBBERLESS triacs which are
specified without a resistive/capacitive network.
Additionally, the limit of the (di/dt)c parameter is
now listed in SGS-Thomson Microelectronics
data sheets.
This permits the optimization of the circuit by
specifying stricter guidelines in the choice of the
component.
- - - - - - - - - - - - ...'Yl ~~~@mym~~~©~-----------966
APPLICATION NOTE
TRIAC DRIVE CIRCUIT
FOR OPERATION IN QUADRANTS I AND III
Ph. Rabier
New triacs with high commutation and dvldt
performances are now available on the market.
To drive the triac in the 2nd and 3rd quadrants a
discharge capacitor is used as shown in figure 3.
Generally these triacs are only triggerable in the
3 first quadrants (case of SNUBBERLESS and
LOGIC LEVEL triacs) as shown in figure 1.
Figure 3 : Basic diagram of the trigger.
This paper describes a trigger circuit supplying a
negative gate current for quadrants II and III
implemented in a system using a positive power
supply.
+ Vee
Without a new design, just by adding a capacitor
and a diode new W series triacs can replace
conventional triac.
Figure 1 : The quadrants of a W series triac.
R2
LINE
R3
IA
+-
++
2
nd
1 sl
3
rd
4 Ih
11 Principle:
- The transistor is switched off, capacitor C is
charged through resistance R2 and diode D.
IG
NOT TRIGGEAABLE
I - PRINCIPLE:
Figure 2 shows the schematic of a system with a
sensor, logic and positive power supply (with
respect to the anode 1 of the triac).
Figure 2 : Synoptical diagram of a classical
system.
The diode is used to avoid a capacitor load
current through the gate of the triac. A schottky
diode could be used to improve the voltage drop
level lower than the gate non trigger voltage
(VGo).
- When the triac is triggered, the transistor Tr is
switched on, C is discharged through R1 and Tr
and a negative current flows through the gate of
the triac.
The capacitor C acts as a differentiation. We
have to consider different parameters to define
all the components:
- The gate trigger current of the triac (IGT)
- The time duration of the gate current
- The latching current (IL) especially for small or
inductive loads.
AN44010592
1/5
967
APPLICATION NOTE
The gate pulse is shown in Figure 5 :
21 Review:
--Definition of the latching current (IL) :
The IL of a triac is the minimum value of the
main current which allows the component to
remain in the conducting state after the gate
current IG has been removed:
Figure 5 : Gate pulse.
IG
That is to say the gate current has to be higher
than IGT until the main current reaches the
latcing current.
Example: for the CW SNUBBERLESS triac:
01 - 03 : ILmax = 50 mA
02 : ILmax = 80 mA
With : gate pulse duration of 20l1s at Tj = 25°C
12
IGM/2
IGM
IL max is specified in the CW series triac data
sheet.
Statistically, for BW series triacs we can use the
K ratio
t1 calculation:
K = ILmax/lGTmax
to say t1 min
The triac has to be triggered when the main
current is higher than the latching current, that is
i~ := larcsin ( h max)
co
K = 2,3
Two solutions are possible:
- Triggering with a delay after zero voltage
crossing such that the main current is higher
than IL.
- Triggering at zero voltage crossing with a long
discharge time in order to have no problem with
IL.
II - THE CASE WITH A RESISTIVE LOAD:
IRMS--!2
where co = 2 . It . f
IRMS : minimum RMS current in the worst case
(depending on line and load dispersion).
The curve given shows the minimum time versus
IRMS current through the anode (figure 6).
Figure 6 : t1 time versus IRMS for different
latching currents.
t1(us)
200
.11 First solution: delayed pulse current (figure 4).
180
\
160
140
Figure 4 : Triggering with delay 11 after zero
crossing.
:=IIIIIEIIJ
M" I
20mAlDIV
2/5
\1\
W SERIES
80
\
60
40
SERIE~"'"
I I I
r-cw
20
a
o
1
2
3
4
'----'----5
r- I-- -
~
6
7
8
9
10 11
12 13 14 15 16
IT(rms)(A)
The gate current calculation:
CURRENT
0.'_
\
120
100
1111119111
IGT is the maximum gate trigger current specified
in the data sheet. To ensure a good safety
margin and good triggering we have chosen IG =
2.IGT with a pulse duration t2 higher than 20l1s.
- - - - - - - - - - - - ! ' 1 l ~~i@m~f&'I~~~©'------C.------968
APPLICATION NOTE
All the components can be defined by the
following formulae:
R1 max = (Vcc - VGK - VCE)/(2.1GT)
= 2 V at IG = 2.IGT
with VGK
Cmin = t2/(R1.log2) with t2 = 20j.1s
= 0,001/C
R2max
Curve 7 gives the minimum capacitance versus
supply voltage for different sensitivity.
Figure 8 : Triggering at zero voltage.
.: uji frWll1
,,,. f
CURRENT
Figure 7 : Capacitance value versus supply
voltage for different sensitivity.
:::,:
C (uF)
2
1.8
1.6
II
1\
1\\
1.4
1.2
1
\
0.8
0.6
0.4
r--
cw
0.2
o
2
III~IJ IIIII
Note : In figure 8, the pulse through the
transistor base is cancelled before the capacitor
is fully discharged to save energy.
\~
All the components can be defined by the
following formulae:
W SERIES
SERIE~ ~l
J
I
I
N==:::I::----
4
6
8
10
12
14
vee
{V}
/2 min =
16
18
~o
22
24
~arcsin (IR~~ -ff) + 20j.1s
26
R1max = (VCC-VGK-VCE)/(2.IGT)
Cmin = t2/(R1.1og2)
In this way the RMS current is lower than the full
wave current, the RMS current/full wave current
ratio is :
K' = 1 -
2.
4 2~
+
.sin ( 4 it
4)
R2max = 0,001/C
In this way the RMS current is equal to the full
wave current.
The calculation gives for a 6 Amps CW triac with
a 2 Amps sine current and with an IL = 80 mA.
t1 = 90j.1s
K
= 0,99
That means the losses are lower than 1%.
21 Second solution: Wide current pulse at zero
crossing.
It consists of triggering the triac at zero voltage
crossing voltage as shown in figure 8.
___________
~
""!l
lilt..
SGS-THOMSON _ _ _ _ _ _ _ _ _ _3_/5
~O(l;w@rnlLrn(l;'ilw@IiIJO(l;~
969
APPLICATION NOTE
31 Comparison between these two solutions:
The calculation of all the components is shown
in the following table for 3 differents cases
Figure 9 : Component values for 3 differents cases: triac used: BTA08-600CW (IGT = 35 mAl
IRMs
~
IRMs ~ 2 A
Vcc ~ 5 V
5A
Vcc~10V
with delay
at zero
crossing
with delay
IRMs ~ 5 A
Vcc ~ 5 V
at zero
crossing
with delay
at zero
crossing
t1 min (IJS)
36
0
91
0
36
0
t2 min (IJS)
20
56
20
111
20
56
R1 max (0)
105
105
34
34
34
34
C min (IlF)
0.275
0.77
0.85
4.7
0.85
2.37
R2 max (0)
3.7
1.3
1.18
0.212
1.18
0.42
III - CASE OF INDUCTIVE LOAD:
With an inductive load another problem occurs:
the problem of the phase lag between load
current and load Voltage.
R2=(time between 2 pulses)/(5xC)
It can be solved by taking into account:
- the maximum phase lag to define a delay time
td.
- the latching current to define the time t1
- the inductance to define the time t2= VIL at the
moment when the triac is fired (t2 > 20flS) to
have an anode current higher than the latching
current IL.
The figure 10 shows the anode current and the
gate current in the triac, is the case of an
inductive load.
Figure 10 : Current through an inductive load.
une~
Anode current
/
IL
'j'
.. / .
.
/
, t2 .
IG
td
,,'-:
IGT .
21GT -
4/5
------------i..,l
970
If the phase lag is not constant a gate pulse train
can be used, the calculation parameters are the
same, except for R2 : the capacitor C has to be
charged between 2 pulses so the equation is :
IV - THE CASE OF A SMALL LOAD:
This trigger circuit can not be effectively used to
drive small loads (like valves, fan etc ... ) because
the latching current value is not very small
compared to the load current. In this case a DC
gate current is needed.
V - CONCLUSION:
In the case of controllers supplied by positive
voltage this solution allows of the replacement of
conventional triacs used in the 1st and 4th
quadrants by SNUBBERLESS or LOGIC LEVEL
triacs triggerable only in the 3 first quadrants
without a new design but only by adding a
capacitor and a diode.
Two configurations are possible:
First solution: Triggering after the zero voltage
crossing .
Advantage: capacitor value lower than 1flF.
Disadvantage : the need to have a delay after
the zero voltage crossing (delay system
needed).
.
Second solution
Triggering at zero voltage
crossing.
Advantage : 100% of the power used in the
load.
Disadvantage : capacitor value of a few
microfarads.
~~~~my,m~~~~~------------
APPLICATION NOTE
With inductive loads (motor, transformer, etc ... ) a
pulse train can be used because of the phase
lag between current and voltage.
With small loads (valve, fan, ... ) a DC gate
current has to be used to drive the triac because
of the latching current.
- - - - - - - - - - - - ..'Yl
In case of logic or transistor failure, the capacitor
C operates as an open circuit for DC current and
avoids all triggering. This factor acts as a safety
feature.
~i~@ml&1~~~©~
-----------5/5
971
APPLICATION NOTE
TRIACS FOR MICROWAVE OVEN
P. Rault
Triacs are now commonly used in microwave
ovens as static switches to control the power
transformer, the heating resistor for grill and
sometimes the motor for plate rotation.
10 to 16 Amp according to the line voltage but it
is necessary to take into account an overload
due to the magnetizing current through the
transfomer at turn on.
Due to the high turns ratio of this transformer
this overcurrent can reach a peak up to 20 times
the RMS current in steady state!
To reduce the stresses at every switching on the
circuit and particularly on the triac it is important
to limit the overcurrent by using a proper
triggering synchronization.
The conditions of operation of triacs for
transformer control and for heater control are
analysed here after in order to select the suitable
device, to define the gate drive circuit and to
implement an efficient protection.
I . POWER TRANSFORMER CONTROL:
Transient operation in inductive circuit with iron
core:
During continuous operation, the magnetic field
H, proportinal to the current in the cOil,generates
an induction B in the iron core with a delay as
shown by the hysteresis cycle in figure 2A.
The magnetron of a microwave oven is generally
supplied by rectified high voltage obtained with a
50/60 Hz transformer. The power supplied to the
oven is controlled by a triac in series with the
primary (fig.1).
In transient operation, the induction can follow a
different path and reach the saturation value BS
for which the magnetic field H (according to the
coil current) increases very rapidly (Fig.2B).
1/ Current stresses:
The power to be controlled is typically 1 to 2 KW
and the nominal RMS current is in the range of
Figure 1 : Magnetron power supply controlled by a triac.
r
T"'=' AC
AN441 10592
~
HV
1/8
973
APPLICATION NOTE
Figure 2 : A - Magnetic field H versus induction B (continous rating)
B - Saturation induction BS
Bs
B
-----
.......-.-
----~-~-:..::-
o
H
H
H
In the circuits controlled by a triac, switching
OFF occurs when the current is at zero. Thus
the induction has a remanent value Br (positive
or negative), corresponding to H = 0 (Fig.2A).
k.nI
very high ; this type of control produces the
highest transient overloads (Fig.3A).
Peak induction tends to the value:
In this case the transformer behaves like a short
circuit and peak current is limited only by the
series resistances of this circuit.
Nevertheless it is possible to reduce the
overcurrent if control at zero voltages done by
complete cycles i-e the polarity at the moment of
firing is the reverse of that at moment the circuit
is switched OFF.
Peak induction thus reaches the value :
Bmax = 2 Bn + Br
Bmax = 2 Bn - Br.
Thus in most cases B reaches the saturation
induction BS. The amplitude of the current
proportional to the magnetic field H becomes
The overload is lower than previously but still
remains high (Fig.3B).
When the triac begins 10 conduct, the transient
current
depends
on
the
instant
of
synchronization of the control signal with respect
to the mains voltage.
FIRING AT ZERO MAINS VOLTAGE:
_2/_8_______________________
974
~~l ~~~@~~~l~~©~
-------------------------
APPLICATION NOTE
Figure 3 : Transient induction and current at beginning of conduction.
V mains voltage
V mains voltage
B induction
B induction
"
t
V mains voltage
2 Bn - Br
B induction
Bsl----...:.:,..
Bsl-----JF-~
~~--~~~~----
__ OL-----------4-----__
triac current
A : firing at voltage zero
B : firing at voltage zero
conduction by complete periods
FIRING AT PEAK MAINS VOLTAGE:
In this case the peak induction takes the value:
Bmax = Bn + Br
The level of saturation is not reached and
amplitude of the current remains with in
acceptable limits (Fig.3c).
--7This type of synchronization must be used for
transformer control.
See in appendix actual osciliogrammes of
current through a transformer for different
synchronization modes.
Figure 4 : A - gate control by single pulse
synchronized with zero current
B - gate control by pulse train.
:f\f
V
o
MAINS VOLTAGE
'--\--+----1~
TRIAC CURRENT
o
------------------------ J.:.-YL
C : firing at voltage peak
e--I---\--~
~~~@m~I'~~~~~
o e-+----.,L-----I..
-----------------------3/8
975
APPLICATION NOTE
2/ Gate control:
After the first firing the gate pulse should be
synchronized with the triac current zero point
(FigAA).
The pulse duration must be sufficient to be sure
the main current through the circuit reaches the
triac latching current.(IL)
A pulse train can be used to avoid the problem
of misfiring or wrong synchronization (FigAb).
A frequency of several, kilohertz garantees a
correct operation.
Figure 6 : TRANSIL diode and RC network are
necessary to prevent spurious firing
by overvoltages and/or dv/dt.
I
rY"Y'Y""'.
~ 1~~
P-=" AC
Gate control by DC current is also an efficient
method to keep the triac on in case of inductive
load.
To reduce the consumtion of this kind of trigger
circuit a sensitive triac can be used as a driver
(Fig.5).
Figure 5 : Use of sensitive triac (5 rnA) as
driver to reduce gate control circuit
consumtion.
FILTER
F
l
L
Nevertheless one accidental misfiring is always
possible and in this case the triac must be able
to hold the surge current. Therefore it is
necessary to select a device with a sufficient
ITSM(max peak current for 10 ms) for example
120 to 250 Amp.
BTA06·600TW
BTA16·600BW
(IGT < 5mA)
4/ Prefered devices :
3/ Protection:
It is important to avoid as much as possible all
risk of misfiring of triac specially by overvoltage.
Transient voltages can be generated by internal
mechanical switches used for security system
(door, overbreak protection etc .... ) or
supperimposed to the line voltage. These last
ones must be attenuated by a filter at the input.
An efficient protection at the triac level consists
in use of TRANSIL diode across the triac to
clamp the spikes higher than its voltage ratings
(VDRM) associed with our RC network to limit the
off state dv/dt under the specified value. (Fig.6)
- Current ratings:
The nominal RMS current through the
circuit is not the main criteria but the surge
current capability. We suggest the following
current ranges.
ITRMS = 12 A with ITSM = 120 A
ITRMS = 16 A with ITSM = 160 A
ITRMS = 25 A with ITSM = 250 A
-Voltage rating:
VDRM = 600 V provides a good safety
margin for 220 VAC mains.
-Package:
Insulated cases are generally. used to
make easier mounting on chassis and thus
reduce the cost.
T0220AB and TOP3 cases are suitable for
printed board assembly. If the triac is
mounted close of transformer (far from
electronics board) RD92 with "FAST ON"
connections is a convenient solution.
-Protection devices:
A bidirectional silicon diode suppressor
(TRANSIL) with a peak power capability of
1500 W (1 ms) is a good compromise if
there is a filter (coil + capacitor) at the line
input. In fact it is necessary to have a
4/8
------------~.,L~~~@mR:l~~Al-------------
976
APPLICATION NOTE
current limitation (series indepance) in
of overvoltage.
The breakdown voltage compatible
220 VAC supply is VSR = 440 V.
-Part numbers:
triac
BTA12-600B/BW(1) 12 Amp T0220
BTA16-600B/BW(1) 16 Amp T0220
BTA26-600B/BW(1) 25 Amp TOP 3
BTA25-600B 25 Amp RD 91
case
with
AB
AB
Figure 8 : Controlled by the gate pulse, IG,
the triac is fired, and a current IT
flows through it. If the gate current
IG is stopped before current IT
reaches the value of the latching
current IL, the triac turns off.
'l1-=
IG >IGT
TRANSIL 1.5KE440CP
Figure 7 : Triacs in insulated cases
(UL approved)
Gate
c;~e:;;--~
TOP 3
T0220 AB
I
,
Main current
RD 91
G
II. HEATING RESISTOR CONTROL:
For triacs with max gate triggering current of 50
mA the latching current is lower than 120 mA.
1/ Triggering:
In this application the triac is used as a ON/OFF
switch to control the power in the grill heater.
It is the case of resistive load. Therefore it is
absolutely necessary to trigger the triac at zero
voltage in order to eliminate the turn on dr/dt
stresses and RFI problems.
To keep the triac on, a single gate pulse can be
supplied at every zero crossing of voltage that is
also the zero point of current in this case.
The pulse duration must be calculated in order
to allow the load current to reach the latching
current (IL) of the triac.
3/ Protection:
(1) BW : SNUBBERLESS TRIAC series with
high switching performance and high dv/dt
capability.
With
the
new
generation
of
triacs,
SNUBBERLESS
triacs,
the
commutation
(turn·off) is possible without external limitation of
(dv/dt)c, that is to say without RC network even
-------------I.:.'Yl
2/ Current rating:
For normal operation there is no particular
current stresses efficient cooling is required to
minimize the thermal fatigue due to the variation
of junction temperature and consequently
increase the life time of the equipment.
~~~illm2m~~~~
------------5/8
977
APPLICATION NOTE
gate current as soon as the voltage across it
exceeds a certain value which ensures a high
level of safety.
To do it we use a low power (i-e low cost)
bidirectional TRANSIL diode according to the
diagram. Fig.8
When the overvoltage reaches the breakdown
voltage VBR of the TRANSIL the latter conducts
and the current flows through the gate and turns
the triac on. Fig.7
if the load is inductive.
In case of overvoltages the triac could be fired
by exceeding its breakover voltage and generally
it is distroyed because of the too high dildt, that
is limited only by the inductance of the load (very
low for a heating resistor) and of the wiring.
A RC network across the triac cannot reduce the
spikes because there is not enough inductance
in series in the kind of circuit.
~RC snubber circuit in useless!
HOW TO PROTECT?
The solution consists in turning on the triac by a
Figure 9 : Protection by TRANSIL the triac is turned on by the gate at the beginning of the
overvoltage and continues conducting during the rest of the half cycle.
2kW
Bm16600B
orBTA12600B
--
220 V
Control
Ovcrvoltagc
fi ~
1"II
"
+VSR
I
"I
I I
__________________ '1. ________________________________ _
I
Mains
,/ voltage
L
I
I
,
I"
/--',
I
TRIAC
voltage
,
/
~
\.
\
\
-VSA
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
'TRIAC
,,
/
/
---",,/
_6/_8 _ _ _ _ _ _ _ _ _ _ _ _
978
jO,'Yl ~i~@m2ml~~©~ -------------
APPLICATION NOTE
What part number?
to protect a 600 V triac generally used for
220 VAC operation we recommend:
BZW04376B or BT.
for a 400 V triac (110 VAC mains) we propose a BZW04188B.
reduce peak inrush current, then triggering with
pulse train synchronized at zero current point.
Protection :
TRANSIL and RC network across the triac to
avoid all risk of firing by overvoltage and/or
dv/dt.
III . TO SUMMARIZE:
Heating resistor control:
Transformer control:
Triggering at zero voltage absolutely necessary.
Protection :
Select triac with high surge current capability
and
with
high
transient
immunity
(SNUBBERLESS series).
* with SNUBBER LESS triac, RC snubber circuit
is useless.
Triggering:
first switching on, firing at peak line voltage to
A2 achieves an efficient protection against
overvoltages.
* TRANSIL diode connected between gate and
- - - - - - - - - - - - - ~"'l ~~~@m~ll~l~~:r;~
_____________7_/8
979
APPLICATION NOTE
ANNEX
TRANFORMER CONTROL BY TRIAC
Triggering at voltage peak --> peak current = 22 A
-I
,----fli--1
TRIAC VOLTAGE
rl
- - - - ,--- -
0
-- - ----- - "
,
R
100 V I div
20 ms I div
Triggering at zero voltage --> peak current reaches 130 A !
••
TRIAC VOLTAGE
100 V I div
20 ms I div
(line voltage = 220 VAC)
'
1-- ------+-+---+---
-
_c_
50 A I div
20 ms I div
(unloaded transformer)
______
f-----!-i---+--f--- ----= ~-=-____
<------;t------'--'--L_---
CURRENT
---+--j---+-4
-_~---_
Steady state (without load)
TRIAC CURRENT
A
A
\
A
\
{
IV
{
IV
~
{
IV
A
IA
\.
\.
r
1\/
_8/8_ _ _ _ _ _ _ _ _ _ _ t==
980
""'1L
50 A I div
10 ms / div
r
II/
SCS.THOMSON _ _ _ _ _ _ _ _~_ _
f!AJO©Iiil@!ll~I'i©1JIiil@UilO©®
APPLICATION NOTE
TRIAC & MICROCONTROLLERS THE EASY CONNECTION
Ph. Rabier
The aim of this note is to show how to connect
an
SGS-THOMSON
triac
and
an
SGS-THOMSON microcontroller.
Figure 2: Conventional drive in the 2nd and
3rd quadrants.
I . CONVENTIONAL SOLUTION
+VDD
For many years the triac has been used to
switch load on the AC mains and thanks to the
low cost of microcontroliers (JlC) this solution is
widely used in the appliance market.
uC
LIN
Ali the system use a buffer transistor between
the output port of the microcontrolier and the
triac as shown in the figure 1.
Figure 1 : Drive in the 1st and 4th quadrants.
To save cost, manufacturers want to use fewer
and fewer components and of course want to
remove the buffer transistor, but a problem
arises.
uC
LINE
11 '----r-,--Y
IG
Due to the low output current of the
microcontrolier, the triac had to be very sensitive
and consequently was not able to withstand for
example the static dv/dt, and the commutation.
OV
II· NEW SGS·THOMSON SOLUTION
Two parameters have been improved :
- The sensitivity of the triacs.
Because of. the low sensivity of the triac in the
4th quadrant this type of drive is often
unpractical, and is replaced by the topology of
the figure 2 :
AN442/0592
- The output capability of the microcontroliers
in terms of sunk current.
A microcontrolier is now able to drive one
standard triac or several sensitive triacs,. without
buffer transistors (see figure 3).
112
981
APPLICATION NOTE
Figure 3: An easy connection
+VDO
SGS
THOMSON
uC
Where:
Voo supply voltagage
VOL output low voltage of the
microcontroller
VG gate - anode 1 voltage at IG
With:
Voo = +5 V
VOL = 1.3 V
VG = 1.5 V
IG = 20 rnA
LINE
THOMSON
Therefore: RG = 110 Ohms
A2
TRIAC
ov
Figure 4 shows the output capability of a range
of controllers and the sensitivity of the triacs.
Figure 4: Triac and microcontroller characteristics.
MICROCONTROLLERS &
OUTPUT CAPABILITIES
TRIAC
T & TWSERIES
ST621x SERIES
ST622x SERIES
IOL=20mA AT VOL= 1.3V
SENSITIVITY
'IGT=5mA
Tx05 SERIES
S& SW SERIES
Tx10 SERIES
1 PORTfTRIAC
AT
IG=20mA
1 PORTfTRIAC
C SERIES
IGT=25mA
VG =1.5V
AT IG =50mA
2 PORTS IN PARALLELfTRIAC
CWSERIES
IGT=35mA
VG=2V
AT IG =70mA
3 PORTS IN PARALLELfTRIAC
B & BW SERIES
IGT=50mA
VG =2V
AT IG= 100mA
4 PORTS IN PARALLELfTRIAC
To take into account of the dispersion on RG ,
Voo and on the temperature variation, we
generaly choose about:
IG = 2 .IGT
tp > 20jJ.s
VG =1.5V
AT
IG = 10mA
CONNECTION
VG =1.5V
IGT=10mA
IVSS=100mA
GATE
PARAMETERS
(IGT=Specified gate triggm- current)
III - CONCLUSION
Use SGS-THOMSON sensitive triacs driven by
an SGS-THOMSON microcontrollers and remove
the buffer transistors.
EXAMPLE:
This can be achieved thanks to the high current
capability of our microcontrollers which are
compatible with our new sensitive triacs (T410,
T, TW, S, SW series).
For +5V supply voltage and a LOGIC LEVEL
triac with IGT = 10 rnA, we have :
Furthemore a non sensitive triac can be driven
by several output ports in parallel.
Where tp is the pulse duration of gate current.
2/2
-------------~~l ~i~~mgl~~~~~------------982
APPLICATION NOTE
SERIES OPERATION OF FAST RECTIFIERS
B. Rivet
The use of several rectifiers connected in series
is necessary to obtain voltage ratings beyond the
capabilities of single diodes and also when some
special requirement, such as very low switching
losses, oblige to implement several low voltage
ultra fast diodes.
Rectifiers connected in series tend to share
unequally the voltage across the string in
blocking conditions because of the variations in
reverse characteristics : leakage currents and
turn off switching parameters.
To ensure that each diode operates within its
voltage rating it is generally necessary to add a
voltage sharing network.
In order to equlize the voltage, a resistor is
connected across each diode (Fig.2).
Figure 2: Use of shunt resistors for steady
state voltage sharing.
D1
D2
D3
Dn
~~ ~
~
1~~ I-v;;-']
~I
V2
'I
V3
'I
This paper gives the rules of calculation of this
auxiliary network and shows how this circuit
could be optimized : reduction of power
dissipation and cost.
1) Calculation of sharing resistors:
I - STEADY STATE VOLTAGE SHARING:
The difference in blocking characteristics results
in unequal steady state voltage (fig.1).
Figure 1 : Dispersion of diodes reverse
characteristics. The reverse current
through the string 01, 02, .... Dn is
IR and the voltages across the
diodes are respectively V1, V2j ...Vn.
The calculation of these resistances is based on
the worst case situation.
The maximum unbalance in blocking voltage
when n diodes are connected in series occurs
when (n-1) diodes have the maximum leakage
current and one diode D1 has the lowest
possible leakage current.
In this case D1 will support the highest voltage
V1 and this tendency is aggravated by the
assumption that the corresponding resistor R1 is
at the upper limit of its tolerance (a), while all the
others are at the lowest limit so,
R1 =R(1+a)
D2
Dn
R2 = R3 = .... Rn = R
i I
In order to calculate the current in the string we
approximate the reverse characteristic with a
straight line. We define the slope by the
coefficient k according to fig.3.
)
D1
IR
Vn
AN443/0592
V2
V1
VRRM
V
1/7
983
APPLICATION NOTE
Figure 3: Reverse characteristic modelisation
of a fast rectifier.
maximum reverse voltage VRRM. This current
depends on the junction temperature (Fig.4).
Generally in the data sheet the manufacturer
specifies a maximum value IRM at VRRM at
Tj=100De.
VR(I-k)
IR+ IRM(TJ).[k+ VRRM 1
With k = O.B
When we know the operating junction
temperature (Tj) it is possible to calculate IRM by
using the following relation:
IRM(Tj) = IRM(IOODC) exp[-0.054(100-Tj)]
IRM
Figure 4: Reverse leakage current versus
junction temperature.
Example:
BYT 261-1000 (typical value)
IR
k.IRM
10 0_ __
IR(uA)
L-~~~~-L~~~~~~~~.
VRRM
VR
10000~~!",,!!!~~
V
So the leakage current IRM of diodes 02 ... On
under the blocking voltage V2 ... Vn is :
100_~_
Vn (I-k)
1R2 = 1R3 = ... IRn = IRM [kl VRRM 1
where IRM is the maximum leakage current at
VRRM (maximum voltage specified for this
diode), and at the operating junction temperature.
For '01 the maximum reverse current at VRRM is
In these conditions the leakage current of diode
01 is:
= (/RM-!;.IR) (k+
V1(I-k)
VRRM )
Taking into account all these parameters, the
voltage VI across the diode 01 is given by the
relation:
V VM(I+a)(VRRM+(I-k)/RM RJ+k(n--I)(I+a)/';./R RVRRM
1 RIRM n(l-k)(I+a)+ VRRM (n+a)-RMFi (l-k)(1 +a)(n--I)
(I)
The resistance R must be choosen to limit the
'voltage V1 under the maximum value VRRM
specified for this rectifier. Thus:
R<
20 30 40 50 60 70 80 90100110120130140150
THoe)
3)
IRM-!;.IR
IR1
,~~~-L~-L~~~~~~
~
IR estimation
In fact
~
IR is the sum
~
IR1 and
~
IR2
- ~ IR1 is due to the leakage current dispersion
of the rectifiers
in the same conditions of
voltage and temperature.
For the fast rectifiers to day available on the
market the dispersion of the reverse current at
VR = VRRM and Tj = 100D is about :
e
!;.
IR1
=
0.6 IRM
This dispersion varies from one batch to another.
- ~ IR2 is due to the difference between the
junction temperatures of each devie (~Tj).
VRRM WRRM (n+a)- VM (I +a))
MR VRRM (I+a)(n--I )-IRM (l-k)(\+a)(nVRRM-VM)
(2)
For the to-day fast rectifiers we can use k=O.8
2) IRM evaluation
IRM is 'the maximum leakage current at the
2/7
-----------'----J,..,l
984
~~~~m~'~~~~~
-------------'-
APPLICATION NOTE
Figure 5: The variation AIR is the dispersion
of IR at max operation junction
temperature (AIR1) plus the
variation due to Tj (AIR2)
1- ------
As for the AIR the worst case is taken into
account.
AIR = IR
(100°C)
with IR = IR max at Tj max specified
IR
IRM
IR
~
-
--
R< n VRRM- VM
(n-1) IR
02,D3 •... Dn
lRt
01
IR2
This formula is "pessimistic" and induces a low
resistance and then a high power dissipation.
5) Example
I-----~===::::;:--~TJ{IC)
TJ
The junction temperature is given by the thermal
resistance junction to ambient Rth (j-a) and the
power dissipation due to the conduction losses
(PC) and the switching losses (PS).
PC is linked to the forward voltage (VF) and PS
is linked to the reverse recovery charge (ORR).
So the variation of the junction temperature is:
~ Tj=~Rth (PetPS)+Rth (~VVFPet ~QQRR PS)
F
RR
Where AVF is the dispersion of the forward
voltage and ORR the dispersion of the reverse
recovery charge.
- Given
Maximum blocking voltage: VM = 2500V
Part number used: BYT12-P11000
Power dissipation per diode: P = 7W
Case temperature: Tcase = 52°C
- Rectifier specification :
VRRM = 1000V
IR (Max at Tj=100°C) = 2.5mA
Rth j-c = 4°CIW
- Problem:
Calculation of sharing resistors for 3 diodes in
series.
- Solutions:
a) Simplified method :
.n VRRM- VM
(n-1) IR
For series operation, it is recommended to use
pieces coming from the same lot, so the
dispersion on the parameters VF, ORR and Rth is
minimized;
With
In most cases the evaluation of ATj is difficult
but, from experience, it is generally lower than
10°C.
Thus
We propose to take a safety margin and to use:
~IR = 0.S5 IRM
Power dissipation per resistor : 3.45 W!
duty cycle 1) = .5)
R<
n=3
VRRM = 1000V
VM = 2500V
IR = 2.5mA
Rmin - 100 kOhms
(with
b) Calculation with relation (2) :
4) Simplified formula
The relation (2) is often used by using the
following approximations
k = 1 : supposing the reverse current IRM
constant, whatever the blocking voltage across
the diode.
a = 0 : Neglecting the effect of the tolerance of
resistors. thus:
R< n VRRM- VM
(n-1)~ IR
R<
VRRM(VRRM(n+a)-VM(l+a))
MR VRRM (1+a)(n-1 )-IRM (l-k)(l+a)(nVRRM -VM)
General data for fast rectifiers :
~IR = 0.S5 IRM
k = O.S
Intermediate calculations:
Tj = P.Rth j-e + Tease =
soac
IRM = IRM(SO°C)
= IRM(100°C) exp[-0.0054(1 OO-SO)]
=0.S5mA
~IRM = 0.72mA
APPLICATION NOTE
Assuming we use resistors with 5% of tolerance,
then a = .10
Let:
Rmin = 220 kOhms
Figure 6: Reverse recovery current waveform.
Power dissipation per resistor=1.58W(with 1'=.5)
IF
6) Ouestion : is it possible to remove the sharing
resistors?
dlF/dt
/
With the relation (1) we can find the value of V1
when the value of R tends to infinite. Then we
calculate the condition to have
V1 < VRRM
Solving we find
QRR
"'IR < (1-k) (n VRRM- VM)
IRM
VRRM(n-1)
In the previous example this condition should be
MR=5%
IRM
If is obvious that this condition is generally very
difficult to meet without hard selection.
Voltage sharing during the reverse recovery
phase is achieved by using a shunt capaCitors
string connected across the diodes (Fig.?).
Figure 7: Use of shunt capacitors for
transient voltage sharing.
II - TRANSIENT VOLTAGE SHARING
01
02
03
C2
C3
1) The problem
When a diode is switched from the forward
conduction to the reverse blocking state, a
reverse current flows through the device during
the reverse recovery time trr.
After this delay all the charges (minority carriers)
stored in the junction are eliminated and the
diode turns off. The time integral of the reverse
recovery current is called reverse recovery
charge (ORR).
Fig.6 defines the reverse recovery parameters.
When a string of n diodes in series switches off,
the diode which has the lowest recovery charge
turns off the first and supports an important
proportion of the total voltage VM and its
maximum reverse voltage VRRM could be
reached or exceeded.
986
I~
Ct
H
~~~
erg
On
Cn
~
2) Calculation of sharing capaCitors
The calculation of capacitance C is also based
on the worst case situation.
We assume that (n-1) diodes 02, 03 ... On with
a reverse recovery charge ORR + tl.ORR, and one
diode 01 with lowest value ORR.
We suppose also that the corresponding
capacitor C1 is at the lowest limit of tolerance (a)
while the others are at the upper limit
so:
C1 = C
C2 = C3 = ... = Cn = C(1 +a)
When all the stored charges of diode 01 have
been evacuated, the charge remaining in the
other diodes is tl. ORR.
At this time the voltage across 01 is V1 and the
voltage across the other diodes of the string is :
APPLICATION NOTE
V2
= Vs=
... Vn
Figure 9: Example of reverse recovery charge
specification. (case of BYW 51)
VM-Vl
=~
So these diodes can be assimilated to a
capacitor
Co __/'.._O_R_R_
Vn
Figure
a:
02
IF IF(av)
90% CONFIDENCE Tj"1250C
= _/'..--c0~RR-'-('c-n-c-1--,-)
VM-Vl
Equivalent diagram when 01
swtches off. Diodes 02, 03, .... On
are equivalent to a capacitor
CD = ~QRR(n-1) I (VM-V1)
Dl
500 QRR (nC)
03
On
~
100
~
/'
~
10
10
1.50
50
100
dIF/dt(A/us)
20
200
500
QRR'IRMITj)/QRR-IRM[Tj-1250C]
1.25
~
1.00
IRM
0.75
In these conditions the voltage across 01 is :
V
1
/'..ORR (n-1) + C VM (ha)
C(n+a)
0.50
~
e----
%
~
~
0.25
0.00
In order to limit the voltage across 01 under the
specified value VRRM we calculate C by solving
thus:
V1 < VRRM
C>
(n-1 )/'..ORR
(n+alVRRM-VM(1+a)
3) ORR and ~ORR consideration
For a given diode the reverse recovery charge
ORR is function of the circuit commutation
conditions such as the magnitude of forward
current (IF), the rate of decay of this current
(dIF/dt) and the junction temperature.
Typical values of ORR are given in the data
sheet of each part number (Fig.9).
a
25
50
75
THoC)
100
125
150
For fast rectifiers coming from the same lot the
dispersion of this parameter is low and we can
use, with a good safety margin:
/'..ORR = .30 ORR
4) Is it possible to remove the equalizing capacitor?
In blocking state diodes have a junction
capacitance. For a given diode this capacitance
decreases with an increase in the applied
reverse voltage according to Fig.10.
5/7
--------------------------~~l ~i~~~g~:~~~~-------------------------987
APPLICATION NOTE
We have
Figure 10 : Junction capacitance versus
reverse voltage
(example: BYT 261-1000)
Vl = L1.QRR (f}-1)+ VM CJn
CJl (11+1 )+CJn
Auxiliary capacitors are not necessary if
V1 < VRRM
100 C(pF)
F-1Mhz Tj-250C
PER LEG
or
Q
II. RR <
VRRM[CJ1 (n-1)+CJnj-VMCJn
f}-1
Generally, the value of the junction capacitance
at the operating voltage is very close to the
value at VRRM (CJ1) so we can write
CJl (n VRRM-VM)
Q
f}-1
II. RR<
__~-U~
100
1000
10L-~LLLUUL~~LUDil
10
1
VR(V)
When 01 has evacuated all its stored charge it
is equivalent to a capacitor CJ1 and the other
diodes 02, 03 ... On are equivalent to a
capacitor which is the sum of the junction
CJn and the
capacitance CJ2, CJ3
capacitance
Figure 11 : Equivalent diagram when 01
switches off in case of low QRR :
The junction capacitances CJ1, CJ2;
.... CJn, play the role of sharing
capacitors.
This condition can be met by using very fast
rectifiers in applications where the dlF/dt is low
(like in some resonant converters or flyback
converters) and consequently low QRR.
III· EQUALIZATION BY TRANSIL DIODES
TRANSIL are avalanche diodes designed for
operation in breakdowl1 characteristic and they
are used as clamping device in a wide field of
applications. To limit the voltage across the
rectifiers of a string below the maximum value,
TRANSIL diodes can be used according to
diagram Fig.12.
Figure 12 : Voltage sharing by TRANSIL
diodes.
Dl
D2
Dl
02
03
On
Dn
D3
n;;~:t:-r 6~ .;2
I
V1
-I
V2
i-->I
Vn
-f-------->I
V3
TRANSIL operates as a voltage limiter at steady
state, during the switching phase, and also in
case of external voltage transients.
Fig.11 shows the equivalent circuit
In the worst case CJ 1 is the junction capacitor of
01 at the maximum voltage VRRM
Putting
CJ1 = CJ at VRRM
CJ2 = CJ3 ... CJn = CJ at
VM-VRRM
In blocking condition the TRANSILS connected
across the diode 01 (Which has the lowest
reverse current) operate in the breakdown
f}-1
6/7
------------J...,l
988
1) Steady state
~~~~mgm~~~~~ ----~--------
APPLICATION NOTE
IR = .85 x 2.5 ~ 2mA
VSRmax = 330V
P1<330mW
characteristic. The current through these
TRANSILS is IR and the power dissipation is :
VSR.",IR.o (0 ~ duty cycle)
with
Where VSR is the maximum breakdown voltage
of TRANSILS. In general this extra power
dissipation is lower than in the case of sharing
by resistors and TRANSILS in axial packages
can be used.
- Power dissipation in switching phase:
P2=E.F<1/2 (n-1) ORR. VSRmax. F
with t.ORR = .5 x .3 = .15~C
F = 25 kHz and n = 3
then P2 < 1.2W
2) Switching phase
- Max total power dissipation P1 + P2 1.530 W
When the fastest diodes of the string switches
off the TRANSILS across it operate in
breakdown characteristic and the reverse
recovery current of the other diodes flows
through these TRANSILS. The charge remaining
in the string at this moment is :
(n·1) "'ORR
Solution . 1.5
(1.5KE300CP)
and we can estimate the maximum energy in the
TRANSILS with
E < 1/2(n-1) . "'ORR. VSR
This relation does not take into account the
losses due to the capacitive current through the
string.
3) Example
GIVEN:
Use of a 3-BYT12-PI1 000 for VM ~ 2500V
Operating conditions:
Tj = 100°C
dildt = 20Al~s
F = 25 kHz
0= .5
RECTIFIER SPECIFICATION:
VRRM = 1000V
IRM at VRRM = 2.5mA at Tj = 100°C
ORR = .5flC (in operating conditions)
PROBLEM:
3 TRANSILS diodes are connected in series
across each rectifier. What is the suitable part
number?
DESIGN STEPS:
- VSR calculation :
KE
series
can
be
used
CONCLUSION
When using several fast rectifiers in series it is
necessary to make sure that any diode will not
be subjected to continuous or transient voltages
in excess of their ratings.
In most cases, this is achieved by using sharing
networks across each diode. It is important to
optimize this circuit in order to reduce power
consumption and to save space.
Parallel resistor can be optimized by using the
modelisation of the fast recovery diodes reverse
characteristic proposed in this paper. Then,
thanks to a good knowledge of the reverse
current and its variation in the operating
conditions (possibly by measurement and
selection) it is possible to implement a resistor
with a value as high as possible.
Parallel capacitors also have to be reduced as
much as possible with the knowledge the
switching characteristics of the string in the
actual conditions. The reverse recovery charge
(ORR) is not always accessible with the
datasheet and a measurement is often
necessary.
In certain applications using ultra fast diodes of
the same lot, where the ORR, and therefore the
t.ORR is very low, the sharing capacitor can be
reduced to zero.
In systems where there is a risk of external
overvoltages or where there are transient states
not well known, TRANSIL diodes are a solution
to the sharing voltage problem in sofar as the
total power dissipation of the TRANSIL string
remains compatible with the existing packages
for these devices.
References:
1. B.M. BIRD and K.G. KING:
"An introduction to Power Electronics"
2. J.M. PETER - SGS-THOMSON
Microelectronics: "Analysis and optimisation of
high frequency Power rectification"
1000
VBR max < -3- ~ 333 V
- Power dissipation in steady state:
P1< IR . VSR max.o
Ii."l
_ _ _ _ _ _ _ _ _ _ _ t==
SCS-mOMSON _ _ _ _ _ _ _ _ _ _7_/7
~iD©~Iill[jU©1JIi\lIill}IJ[©§
989
APPLICATION NOTE
TRANSISTOR PROTECTION BY TRANSIL :
DISSIPATION POWER AND SURGE CURRENT DURATION
B. Rivet
I - INTRODUCTION
In a great number of applications, we find the
diagram FIG.1 where a TRANSIL is used to
protect a switch which controls an inductive load.
The switch can
be a bipolar or aMOS
transistor.
The purpose of this paper is to calculate the
dissipated power in the Transil and the pulse
current duration.
VCl : clamping voltage
VBR : breakdown voltage
rd : apparent resistance
III - CURRENT IN THE TRANSIL
We can express the current i through the
TRANSIL by the following formula:
. f VBRmin-Vee
t
VBRmin-Vee
I=(p+
r
)exp (-r L)+ (
r
)
Ip is the current through the coil when the
transistor switches off. The FIG.3 shows the
current variation versus time.
Figure 1: Basic Diagram
Figure 3: Current Waveform
+ v cc
~I
(
••
)
~
~
00
l~
Ip
\
1"
- "
-
-'-----
VCC·VBR
II - CIRCUIT MODELISATION
When the switch tunis off we use the equivalent
circuit represented FIG.2.
The worst case is to consider VCl = VBR min.
This hypothesis will be used in all formulas.
t1 can be calculated by
t1
=_.b. 1n
r
VBRmin-Vee
(VBRmin- Vee - rIp)
Figure 2: Equivalent Circuit
IV - TRANSIL POWER DISSIPATION
L
r
1~=r(*
TTl
VCl=VBRmin
Q~rd
TVBR
I
We can consider two cases, single pulse
operation and repetitive pulses operation.
al Single pulse operation
VC
.
In this case, in order to define a TRANSIL we
need peak power Pp and the pulse current
standard duration tp.
Pp is given by
Pp = VBR min x Ip
AN444/0592
1/2
991
APPLICATION NOTE
If we assimilate the pulse current with a triangle
the standard exponential pulse duration tp is
calculated by the formula:
t = _ ~ In
p
(2r)
VSRmin- Vee
(VSRmin-Vee + rip)
W VSRmin.L[1
VSRmin-Vee I
VSRmin-Vee]
r
p+(
r
) n( VSRmin- VeC+rlp)
When r tends to zero we find :
2
a) Single pulse
We find
The energy in the Transil can be expressed by :
w=l LI
TRANSIL : 1.5KE36P VSRmin = 34.2V (cf data
sheet)
Pp = 34.2 x 4 = 136.BW
tp = -
(1.4;~ 10
-3
) In
(34~2~~~:~X4)
tp = 1.0Bms
VSRmin
p (VSRmin- Vee)
2
The data sheet gives Pp 1500W for tp = 1.0Bms
then this 1.5KE36P can be used in this
application.
b) Repetitive pulses operation
In repetitive pulse operation the power
dissipation can be calculated by the following
formula.
P=F x VSRmin.L[1
VSRmin- Vee In VSRmin-- Vee
r
P+(
r
) (VSRmin-VeC+rlp)]
b) Repetitive pulse operation
The commutation frequency is equal to 10HZ so
-3
p= 10X(34.2x10.10 )[4+(34.2-14) In (
3
3
34.2-14 )]
34.2-14+3x4
= 9BOmW
When r tends to zero we find :
Rth = 75°C/Wand Tj max. = 175°C
p= 1 LFI 2
VSRmin
2
P (VSRmin-Vee)
So Tj = P x Rth + Tamb.max.
Where F is the commutation frequency.
With Tamb.max. = 50°C we find:
v - EXAMPLE OF APPLICATION
Tj = 0.9B x 75 + 50 = 123.soC < Tj max
Commutation of a coil supplied by a battery. The'
different parameters of the application are :
So we can also use this Transil in repetitive
pulse operation.
Vcc = 14V
L = 10mH
r = 3 Ohms
Ip = 4A
2/2
------------J...,l
992
~~1i,;mg~~~~~~
-------------
MONITOR & TV CIRCUITS
993
APPLICATION NOTE
VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
by Alessandro MESSI
INDEX
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.5.
16.
17.
18.
19.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1/24
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/24
Ramp Generator ............................................................. 3/24
Blanking Generator and CRT Protection .......................................... 4/24
Power Amplifier Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4/24
Thermal Protection ........................................................... 5/24
Flyback Behaviour ........................................................... 5/24
Current - Voltage Characteristics of the Recirculating Diodes .......................... 11/24
Calculation Procedure of the Flyback Duration ...................................... 12/24
Application Information ........................................................12/24
Supply Voltage Calculation .....................................................14/24
Calculation of Midpoint and Gain ................................................17/24
Monitor Applications ..........................................................20/24
Power Dissipation ............................................................20/24
Blanking Pulse Duration Adjustment ..............................................22/24
Linearity Adjustment ..........................................................22/24
Facilities and Improvements ....................................................23/24
General Application and Layout Hints .............................................24/24
References .................................................................24/24
1. INTRODUCTION
In a general way we can define vertical stages
circuits able to deliver a current ramp suitable to
drive the vertical deflection yoke.
In Figure 1 is represented the more general
possible block diagram of a device performing the
vertical deflection.
Figure 1 : Block Diagram of a General Deflection Stage.
r---------~--~--~--~----------~Vs
Blanking
out
Rl
01
C3
Zo
VERT.
YOKE
R3
R4
R5
'l:'
+
C5
R7
+
CB
R6
V90VERT-01
AN373/0390
1/24
995
APPLICATION NOTE
Such a device will be called "complete vertical
stage" because it can be simply driven by a synchronization pulse and it comprises all the circuitry
necessary to perform the vertical deflection that is:
oscillator, voltage ramp generator, blanking genetor, output power and flyback generator.
At the right side of the dotted line in Figure 1 is
represented the circuitry characterizing a "vertical
output stage". This kind of device comprises only
the power stages and it has to be driven by a
voltage sawtooth generated by a previous circuit
(for example a horizontal and vertical synchronization stage.
In the first class there are the following devices:
TDA1170D, TDA1170N, TDA1170S, TDA1175,
TDA 1670A, TDA 1675, TDA 1770A, TDA 1872A,
TDA8176.
I n the second class there are: TDA2170, TDA2270,
TDA8170, TDA8172, TDA8173, TDA8175,
TDA8178, TDA8179.
There is also a third class of vertical stages comprising the voltage ramp generator but without the
oscillator; these circuits must be driven by an already synchronized pulse. In this third class there
are: TDA1771 and TDA8174.
2. OSCILLATOR
There are two different kinds of oscillator stages
used in SGS-THOMSON complete vertical deflections, one is used in TDA1170D, TDA1170N,
TDA 1170S, TDA 1175 and TDA8176, the other in
TDA 1670A, TDA 1675, TDA 1170A and TDA 1872A.
The principle of the first kind of oscillator is represented in Figure 2.
The following explanations will be the more general
possible; we shall inform the readerwhen we refer
to a particular device.
Figure 2 : First Kind of Oscillator Stage.
Jl
EV90VERT·02
When the switches T1 and T2 are opened the Co
capacitor charges exponentially through Ro to the
value V+(MAX) determined by the integrated resistors R1, R2, R3 and R4. At this point the switches
are closed, short-circuiting R3 and R4, so the volt-
To = Ro' Co' log VR -
v:
VR - V
(MIN)
(MAX)
+ R5' Co' log
with Ro = 360 kQ and Co = 100 nF, it results in 43.7
Hz.
The oscillator synchronization is obtained reducing
the superior threshold V+(MAX) short-circuiting the
2/24
age atthe non-inverting input becomes V+(MIN). The
capacitor Co discharges to this value through the
integrated resistor R5.
The free running frequency can be easily calculated resulting in :
v+ (MAX)
V+ (MIN)
1
fo= - To
R4 resistor when a vertical synchronization pulse
occurs.
The second kind of oscillator is represented in
Figure 3.
----------------------------~~~~~~~~~~~©~
996
(1 )
----------------------------
APPLICATION NOTE
Figure 3 : Second Kind of Oscillator Stage.
RO
VT
,------------------,/
1
Vo
V90VERT·03
When the switch T is in position 2, a constant
current Ico = V . I Ro flows through Co charging it
with a voltage ramp. When the voltage Vo reaches
VO(MAX), T passes in position 1, so a constant
currentlco = ( VB . V' ) / Ro discharges the capacitor causing the inversion of the voltage ramp slope
at the output Vo ( t ). The discharges stops when
Vo reaches the value VO(MIN) and the cycle takes
place again.
It is possible to calculate the free running frequency
fo with the following formula:
To = (VO(MAX) - VO(MIN)' Ro' Co + (VO(MAX) - VO(MIN)' Ro· Co
VVB- Vwith VO(MAX) - VO(MIN) = 3.9V, VB = 6.5V, V . =
0.445V, Ro = 7.5kQ and Co = 330nF it results in :
fo = 43.8Hz.
The oscillator synchronization is still obtained in the
above mentioned way.
In order to guarantee a minimum pull-in range of
14Hz the threshold value· has been chosen in
Vp = 4.3V.
The spread of the free running frequency in this
(2)
kind of oscillator is very low because it mainly
depends from the threshold values VO(MAX), VO(MIN)
and V . that are determined by resistor rates that
can be done very precise.
3. RAMP GENERATOR
The ramp generator is conceptually represented in
Figure 4.
Figure 4 : Ramp Generator.
Vregulated
Ix
height
control
linearity
cantral
V90VERT-04
3/24
997
APPLICATION NOTE
The Voltage ramp is obtained charging the group
R1, C1 and C2 with a constant current Ix.
VRAMP (t)
= (V(MIN) -
It is easy to calculate the voltage VRAMP That results
in:
t
R1' Ix) e- R1 . C + R1' Ix
where V(MIN) is the voltage in A when the charge
starts and C is the series of C1 and C2.
The resistor R1 is necessary to give a "C correction"
to the voltage ramp. The ramp amplitude is determined by Ix = VREG / P1 ,so the potentiometer P1 is
necessary to perform the height control.
The voltage ramp is then transferred on a low
impedence in B through a buffer stage.
Te P2 potentiometer connected between D and B
performs the ramp linearity control or "s correction"
that is necessary to have a correct reproduction of
the images on the TV set.
The voltage ramp in B grows up until the switch T1
is closed by a clock pulse coming from the oSciilator; in this way the capacitors discharge fastly to
V(MIN) that is dependent upon the saturation voltage of the transistor that realizes the switch.
At this point the exponential charge takes place
again.
4. BLANKING GENERATOR AND CRT PRO·
TECTION
This circuit senses the presence of the clock pulse
(3)
coming from the oscillator stage and the flyback
pulse on the yoke. If both of them are present a
blanking pulse is generated able to blank the CRT
during the retrace period. The duration of this pulse
is the same of the one coming from the oscillator.
If for any reason the vertical deflection would fail,
for instance for a short circuit or an open circuit of
the yoke, the absence of the fly back pulse puts the
circuit in such a condition that a continuous vertical
blanking is generated in order to protect the CRT
against eventual damages.
This circuit is available only in the following devices: TDA1670A, TDA1675, TDA1770A and
TDA1872A ..
The stages we will consider starting from this point
are common both to complete vertical stages and
vertical output stages.
5. POWER AMPLIFIER STAGE
This stage can be divided into two distinct parts :
the amplifier circuit and the output power.
The amplifier is realized with a differential circuit; a
schematic diagram is represented in Figure 5.
Figure 5 : Amplifier Stage.
vs~
____~__________~________~______________--.
to power
v -~-----I--I(
V90VERT-05
The open-loop gain of the circuit is variable from
60dB to 90dB for the different integrated circuits.
The compensation capacitor C determines the
dominant pole of the amplifier. In order to obtain a
dominant pole in the range of 400Hz, the capacitor
4/24
must be of about 10pF.
As an example in Figure 6 is represented the boole
diagram of the amplifier open loop gain for
TDA8172.
----------------------------~~~~@~~~~~~~
998
----------------------------
APPLICATION NOTE
Figure 6 : Amplifier Open Loop Gain and Phase.
100
~l'l~
80
iii'
~
45
"
60
z
«
(9
90
IIII
PHASE
40
Vi'
OJ
"
"
~
OJ
OJ
e.
UJ
- 45
"
"
20
0
"
o
(f)
---18
TDA 1 170N
C6
470pF
YOKE
Ry=lSO
Ly=30MH
llf---_+-----'
I
IOI--____~--------~-tR:':'I:50----_+
5.6KO
R6
18KO
12
R7
47KO
P2
100
R3
R4
C8
100Kl
680KO
O.IJlF
R9
I.SKJ
V90VERT·27
Figure 28 : Application Circuit for TDA 1670A.
+Vs
R3
10Kl
BLANKING
OUT
II
13
14
2
YOKE
15
1--~----15
TDA1670A
6
± 1%
CO
4
3
330nF
:t5%
R2
ISKO
R4
180Kl
RTI
.
C5
O.IJlF
•
RS
470KO
R7
RB
1.2Kl
12m
C8
47JlF
IOV
sERvlcEll 220K
SWITCH
HEIGHT
• The value depends on the characteristics of the CRT. The value shown is indicative only.
--~-----------------------------~ ~~~;~g~~~~~~
V90VERT·28
13/24
1007
APPLICATION NOTE
Figure 29 : Application Circuit for TDA8170.
ty
IN4001
Vs
Dl
I
I
C3
I 220,.r
I
6
3
TDA8170
!--~}
-a:
----2'.-
Rl
Ly
24.6MH
10KO
Ry
9.60
R2
5.6KO
-l\nRSl
y
~
V90VERT-29
In the following chapters we shall do the calculation
for television and monitor in order to choose the
right voltage supply and external network for the
yoke used and the current requirements.
11. SUPPLY VOLTAGE CALCULATION
minimum supply voltage necessary to have vertical
scanning knowing the yoke characteristics and the
current required for the given application.
Figure 30 shows the terms used in this section,
while the circuit part involved in the following calculations is depicted in Figure 31.
For television applications we shall calculate the
Figure 30 : Parameters Used in the Calculation of the Supply Voltage.
Vs
'-------'-_ _t_f_ _ _ _ _ _ _ _ _T_S_ _ _ _ _ _ _ _----1 V SAT2
V90VERT-30
14/24
--------------------------- ~~~~@~~~l~~~~
1008
APPLICATION NOTE
Figure 31 : Circuit Involved in the Calculation of
the Supply Voltage.
Figure 32 : Saturation characteristic of the Upper
Power Transistor.
VSATI
(V)
Vs
3.0
2.0
QI
----
I--'
I--'
---
--I1.0
o
o
1.0
0.5
1.5
Ip(A)
V90VERT-31
Vs
Vy
supply voltage.
nominal voltage required to produce the
scanning current including the feedback
resistance and the 20% increasing for
temperature variations in the yoke
current;
Vy = ( 1.2 Ry + RF) Iy
V90VERT-32
Figure 33 : Saturation characteristic of the Lower
Power Transistor.
VSATI
(v)
1.5
v
/
(19)
1.0
VSAT1 = nominal output saturation voltage due
to the upper power transistor 01
(see Figure 32);
VSAT2
nominal output saturation voltage due
to the lower power transistor 02
(see Figure 33);
VOM
nominal quiescent voltage (midpoint) on
the output powertransistors;
Vc
voltage peak due to the charge of Co
capacitor;
---- - -
V
---
-
0.5
o
o
0.5
1.0
1.5
Ip(A)
V90VERT-33
Vc=
~
8 . Co
(20)
Vo
T
voltage drop due to the yoke inductance Ly;
tF
nominal voltage drop on DB diode in
series with the supply;
vertical scan period;
flyback time;
2 ~ . ~
I
~_______V_L_=__L_Yt_~_I_y______(_2_1)______~I ~__________t_F_=_3__~~V~s~~__________~
----------------------------~~~i@~~~:~?©~
15/24
---------------------------1009
APPLICATION NOTE
scanning time;
ts
ts
=
• t"Vc.
due to the tolerance of Co and yoke current regulation;
T - tF
AVc=
Iy
Ry
Ly
RF
I
Vy
+ VSAT2 + Vc + VL
(27)
1.1 Iy 1.1 Ly
ts
-
V
(28)
L
I '-------------------'
(22)
.
2
AVL =
.
AVSAT1
AVSAT2
where:
VOM
Vc
due to the tolerance of Ly (± 10%) and
yoke current regulation;
Referring to Figure 30 it is easy to see that the
minimum supply voltage is given by :
Vs = VOM+ VWP
1.1lyts -
8 CO(MIN)
peak to peak deflection current;
nominal yoke resistance;
nominal yoke inductance;
feedback resistor.
VSAT1(MAX) VSAT2(MAX) -
VSAT1
VSAT2
For each parameter, it is necessary to calculate the
factor p, expressing the percentual influence of
every parameter variation on the nominal supply
voltage, with the following formulas:
(23)
and:
for VOM :
VTOP =
Vy
2
+ Va + VSAT1 - VL - Vc
(24)
P
I
So we obtain:
I
Vs = Vy + Vo + VSAT1 + VSAT2
(25)
The (25) gives the minimum voltage supply if we
do not consider the tolerances of the integrated
circuit and of the external components, but the
calculation, even if it was not realistic; it was useful
in order to understand the procedure.
Now we shall do the same thing considering all the
possible spreads; we can in this way obtain the real
minimum supply voltage.
We shall follow the statistical composition of
spreads because it is never possible that all of them
are present at the same time with the same sign.
We must consider the following spreads:
o t"Vy
due to the variation of yoke and feedback resistance and yoke cu rrent, supposing a 10% of regulation range in
scanning current and a precision of 7%
for resistors;
AVy = ( 1.2 Ry + RF) 1.07 ( 1.1 Iy) - Vy
(26)
1010
AV
VOM
,fo_r_V_T_O_P_:_ _ _ _ _ _ _ _ _ _ _ _ _--,
I
AV
L _ _--,-_ _ _ _P_=_V_T_O_P_ _ _ _ _ _---'
We have then to calculate the square mean root of
the spreads expressed as :
So if we call :
I
VOM1
and:
VTOP1 =
We can write :
Vs =
VOM1 + VWP1
(29)
APPLICATION NOTE
An example of calculation will better explain the
procedure. We shall consider a 26", 1100 ,
neck 29.1 mm tube whose characteristics are:
Iy = 1.2 App;
Ry = 9.6Q ± 7%;
Ly = 24.6mH ± 10%.
We shall use a coupling capacitance Co of 1500flF
with + 50% and - 10% tolerance and a feedback
resistance RF of 1.2Q.
a) Nominal minimum supply voltage:
( 1.2 Ry + RF) Iy =
Iy· ts
Vc = 8. CD = 2 V
Vy =
15.264 V
Ly· Iy _ 1.476 V
ts
VSAT1 = 1.25 V
VSAT2 = 0.68 V
Vo = 1 V
YOM = 11.788 V
VTOP = 6.406 V
We obtain: Vs
This is a real value for the minimum supply voltage
needed by the above mentioned application.
In this case we obtain a flyback duration of about:
2 Iy· Ly
tF = - - - = 900
3
Vs
~s
12. CALCULATION OF MIDPOINT AND GAIN
For the calculation of the output midpoint voltage,
it is necessary to consider the different feedback
network for the applications of the various integrated circuits.
We shall first consider the TDA 1170 family, the
TDA1175, TDA2170, TDA2270, TDA8170,
TDA8172, TDA8173, TDA8175 and TDA8176.
The equivalent circuit of the output stage is represented in Figure 34.
Figure 34 : Circuit Utilized for the Calculation of
midpoint and gain for TDA 1170,
TDA1175, TDA8176, TDA2170,
TDA2270, TDA8170, TDA8172,
TDA8173 and TDA8175.
= 18.2V
b) Statistical minimum supply voltage:
Vs
tJ.Vc = 2.702V
VY!2
PVYM =
YOM
PVYT =
VTOP
VY!2
tJ.Vc = 0.445 V
tJ.VL = 0.31 V
tJ.VSAT1
0.45 V
p2 VYM =
1.313. 10- 2
p2 VYT =
4.447. 10- 2
p2 VCM =
1.421 . 10- 3
p2 VCT=
4.813. 10- 3
p2 VLM =
6.914· 10- 4
p2 VLT =
2.341 . 10- 3
Rs
4.935· 10- 3
p2 VSAT1T =
V90VERT·34
tJ.VSAT2
0.27V
VOM1", YOM (1 +
VTOP1
5.246· 10- 4
p2 VSAT2M =
--JLjI=
13.268 V
= 0J=
VTOP (1 +
Vs = VOM1 + VTOP1
For DC considerations we shall consider the two
capacitors as open circuits. Because of the very
high gain of the amplifier we can suppose:
V- = YR.
We can so write :
7.930 V
(30)
21.2 V
--------------
~ ~~~r0m~~~~~;~
17/24
-------------1011
APPLICATION NOTE
where:
b
=
RF + Rs
Substituting into the (30) we obtain:
v
a
=
V
R
+ RB J l(1 + RA
RF + Rs
(Vi _ VR) RA + RB
(31 )
R1
The equivalent output circuit is depicted in Figure 35.
Let's consider now TDA 1670A, TDA 1675,
TDA1770A, TDA1771, TDA1872Aand TDA8174.
Figure 35 :Circuit Utilized for the Calculation of Midpoint and Gain for TDA 1670A, TDA 1675,TDA1770A,
TDA 1771 , TDA 1872A and TDA817 4.
Vs
VR
Vo
Vi
R
R1
11
R2
RA
Vx
12
13
Rc
R8
+
14
Cc
Cp
Rs
V90VERT-35
We can write:
I
,----,--.-
-I,
12
I I
(32)
- - - - - - - '
(33)
12 + 13 = 14
'-------
where:
b
=
Va - Vx
RA
14 =
Vx
RB + Rs
with the (32) and (33) we can calculate the DC output voltage. It results in :
(34)
Referring to Figures 34 and 35, it is possible to
calculate the transconductance gain of the power
amplifier. For this calculation we shall do the follow-
1W~
.
ing approximations:
- the capacitors are practically short circuits;
- the gain A of the amplifier is very high (A --7
---------------------------~~~~~~~~~~~
1012
00).
---------------------------
APPLICATION NOTE
For the circuit represented in Figure 34 we
obtain:
Iy = ~V'
R1 . Rs I
while for the application in Figure 35 the yoke
current results in :
Iy = R2 + RA / / Rs / / Rc Vi
R1' Rs
(36)
Using the (31), (34), (35) and (36) it is possible to
calculate the external feedback network for every
(37)
different yoke known the scanning current and the
midpoint output voltage.
Figure 36 : Open Loop Gain and Phase for the Application Circuit in Figure 27.
PHASE
DEG
GAIN
DB
60.00
40.00
45.0
-
.-..
.......
.......
20.00
'".....
0.00
.....
-
~
-20.00
........
-180.0
-40.00
10
100
IK
10K
lOOK
FREQUENCY IN HZ
1M
V90VERT-36
Figure 37 : Open Loop Gain and Phase for the Application Circuit in Figure 28.
PHASE
DEG
GAIN
DB
60.00
45.0
t-0.0
40.00
.....
20.00
"7
.......
.....
-45.0
.......
....,
........
I"
0.00
........
r--
-20.00
./
....-
-90.0
r-.. ......
-135.0
-180.0
-40.00
10
100
IK
FREQUENCY IN HZ
--------------
~ ~~~;mR~:.~~
10K
lOOK
1M
V90VERT-37
--------------
19/24
1013
APPLICATION NOTE
work. This calculation is useful in order to verify that
no oscillations can occur at any frequency.
We can now consider the open loop gain of the
whole system amplifier"plus external feedback net-
Figure 38 : Open Loop Gain and Phase for the Application Circuit in Figure 29.
GAIN
PHASE
DEG
DB
40.00
45.0
.....
20.00 r--
o
........
0.00
"-20.00
"'
i'oo..
,.,.
........
-40.00
-60.00
10
10K
lK
100
FREQUENCY IN HZ
We shall consider some typical applications; the
results are reported in Figures 36, 37 and 38.
It is easy to verify that in all cases, when the gain
reaches OdS, the phase margin is about 60°, so the
stability of the system is assured.
13. MONITOR APPLICATIONS
In monitor applications the flyback time needed
could be very smaller than the one we get using the
minimum supply voltage calculation.
It is possible to reduce the flyback time in two
different ways:
a) increasing the supply voltage, when the nominal
value calculated is lower than the integrated circuit
limit;
b) choosing a yoke with lower values in inductance
and resistance and by supplying the circuit with the
voltage needed for getting the right flyback time.
In both cases we have to calculate the biasing and
the gain conditions using the nominal voltage and
then we fix the supply voltage forthe flyback time
requested with the formula (18) :
-180.0
JM
lOOK
V90VERT·38
same as the one we have explained in the previous
chapters for television applications.
14. POWER DISSIPATION
We shall now examine the power dissipation of the
integrated circuit and the dimensions of the
heatsink.
To calculate the power dissipated we must consider
the maximum scanning current required to drive
the yoke IY(MAX) and the maximum supply voltage
VS(MAX) because we have to dimension the
heatsink for the worst case.
The current absorbed from the power supply is
depicted in Figure 39.
Figure 39 : Current Absorbed from the Power
Supply during Scanning.
ly/2=lp
2 Iy Ly
Vs = - - - 3
tF
T/2
The calculation procedure for monitors is so the
T
t
V90VERT-39
20/24
-------------~ ~~~~,i"Dmg:~,,~~~ --------------
1014
APPLICATION NOTE
The equation of the curve is :
i (1) =
~t
Iy
2
for 0 < t:o; T/2
T
(37)
for T/2
The "C" correction is obtained with a resistor in
series to a capacitor connected between Pin 15 and
the central point of the vertical DC feedbac:k of
vertical booster (R19 and CI4).
The value of R19 is strictly dependent on CRT used.
7. LAY-OUT SUGGESTIONS
It is necessary to take care not to connect the
horizontal output ground (Pin 6) directly to Pin 11,
to avoid horizontal interference on vertical stages.
The 15nF capacitors connected on Pins 10, 16 and
17 have the only aim to filter the DC control voltage
against horizontal noise, so they must be connected
as close as possible to the above mentioned pins.
Ramp at Pin 13
tu
--------------~l>
Vertical Sync.
V90TDA8102A·16
This operation is important because some internal
circuits are dimensioned for a 4vpp ramp.
8.3 Vertical amplitude and horizontal phase
8. ADJUSTING PROCEDURE
Here following it is shortly described the procedure
to adjust horizontal and vertical frequencies, verti-
----'------------
Looking at the display correct P2 for the right vertical
amplitude and adjust P3 in order to have the correct
horizontal phase.
~ ~~,~":J!1~~~B~
13/16
--------------1031
APPLICATION NOTE
8.4 Vertical linearity
If the vertical ramp at Pin 13 is correctly set the
central point of the "M" waveform at Pin 18 will be
at the center of the scan; in other case, using Ps,
lead the central point of "M" in correspondence of
the scan center (see Fig,17),
tsc ='scan centre
tc = period centre
In this way the S linearity correction has a uniform
behaviour on the top and bottom sides of the CRT.
Now looking at the display, adjust P1 to obtain a right
S correction and select R19 value to optimise the C
correction,
where: ts = scan time
tv = 1If v = vertical period
Figure 17.
: Rampat
Pin 13
4V
'~
Vertical
Scan
,
,
,
,
,
,
,
,
,
-------------------_ ...
Waveform'
at Pin 18
,
,
,
•
: tsc
,
,
,
,
,
:
~----':.ts
t9
~4r-------~Qr7_------~~tv
V90TDA8102A-17
14/16
------------------------------~ ~~~@~2~:~©~
1032
------------------------------
APPLICATION NOTE
Figure 18: Solder Side.
V90TDA8102A-18
Figure 19 : Component Side.
000
0
0
0
0
0
o·
0
0
0
0
a
a
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V90TDA8102A-19
-----'--------~--
i:fi ~~~~;rng~~J!~~~ _____________..:.15~/..:..:::16
1033
APPLICATION NOTE
Figure 20 : PCB Layout
~i
•
-
0
0
0
0
.=.
~RlZO"'AL
Qmcy
ADJ.
·CRtD·
Pl!ASE
ADJ.
ADI.
•
! ell.
'1 •
'CR!D'
aD
~ ~ .•
n
u;
mD:,,:tiD
•~ •
--am:::>-.. ~
•
.Cl!D'
vnmCAL
FREQUENCY
I'
•J
:~ §
. .
'Cl!D'
on +«ID
•
••
.CJt!C).
HOIUZOlfUJ.
~
... 8
:~:.~®~ ~ ~·8
~~
G
cb":fu H·~0 .. .~ ~Gl
'C!!D'
!JlJ.
~I~I
i;;
~
·0lD·
.CBS:).
VEIlTICAL
...
8
G)
VERTICAL
~~
1•
.CIlL).
AllPLlTlJIIE
ADJ.
§ ~i! 1)
~
•
(TID: :
•
,~,
~ aD
,
1•
•
§~B ~i
~ !!
«ID
"'8.
.c=.
'4
..
8~
C13
'OITD' .c" COWCTION
(2J ,
.. rnD.
.
n
N
0'
<.0<.-
"
~
~
@' W
,~
GD
"0
.. +
ADJ.
•
•I
~5 ~~
1:\:1"
S:'!'l
s
0
V90TDA8102A-20
9. COMPONENT LIST
--
Component
Value
R" R2, R23
R3
R4, R1Q, Rn, R26
3.3kQ
R5, R7
5.1kQ
R2S
R6, Rs
_R9
Component
Value
R20
R2l
150kQ
62kQ
C'0
Cn
22kQ
R22
220kQ
C'2, C'6
39kQ
R24
56kQ
10llF / 63V
6.8kQ
C'4
C,S
100kQ
C'7
1.8nF
2.2kQ
C'9
C20
2.21lF / 63V
220pF
82Q/2W
R'2
--
10kQ
R'3
120Q
P" P2, P3, Ps, P6
47kQ her.
R'4
_R1S
1.5Q
P4
47kQ ver.
1.5kQ
1Q
C" C6, C9
11lF
22nF
100nF
IC,
L7812
15nF
IC2
TOA8102A
IC3
TOA8172
2.7kQ
~-R'9
1.2kQ
C7
1000llF / 25V
33kQ
Cs
100llF / 16V
1034
220nF
470llF / 16V
~7
16/16
220llF / 25V
2200llF / 16V
C2l
0,
C2, C'3
C3, C4, Cs, C,S
R'6
Value
51kQ
R27
R2S, R29
f-
Component
1N4001
-------.J
APPLICATION NOTE
TEA51 01 A - RGB HIGH VOLTAGE VIDEO AMPLlFLIER
BASIC OPERATION AND APPLICATIONS
By: Ch. MATHELET
Page
SUMMARY
DESCRIPTION .
3
1.1
INPUT STAGE
3
1.2
1.3
1.4
1.4.1.
OUTPUT STAGE.
4
IA.2.
1.4.3.
II
11.1
11.1.1
11.1.2.
11.1.2.1.
11.1.2.2.
11.2
11.2.1.
11.2.2.
m
BEAM CURRENT MONITORING
4
PROTECTjON CIRCUITS
MOS Protection
Protection Against Electrostatic Discharges
Flashover Protection . .
4
4
4
4
FUNCTIONAL DESCRIPTION
VOLTAGE AMPLIFIER . . .
Bias Conditions ..
Dynamic Operation. . .
White To Black Transition
Black To White Transition
BEAM CURRENT MONITORING
Stationary State . . . . . .
.
Transient Phase . . . . . . . .
4
4
4
4
5
5
6
6
6
EXTERNAL COMPONENTS CALCULATION
COMPONENTS VALUE CALCULATION .
Feedback resistor . . . . . . . .
Input resistor . . . . . . . . . . .
Bias resistor . . . . . . . . . . .
Current measurement resistor ..
DISSIPATED POWER
Measurement method .. .
Results . . . . . . . . . . . . . .
Static power . . . . . . . . . . . . . . . .
Measurement with sinusoidal input . . . .
Measurement in a TV set . . . . . . . . .
Design of external components . . . . . . .
Heatsink . . . . . . . . . . . . . . . . . .
Power rating of feedback resistor . . . . . . .
10
10
10
10
IV.1
APPLICATION HINTS . . . . .
DYNAMIC PERFORMANCES.
10
10
IV.2
CROSSTALK . . . . . . . . . .
11
IV.3
FLASHOVER PROTECTION
IVA
OUTPUT SWING. . . . . . . . . . . . . . . . . . .
12
13
IV.5
LOW CURRENT MEASUREMENTS
15
V
V.1
APPLICATION EXAMPLES . . .
APPLICATION DESCRIPTION .
V.2
V.2.1.
V.2.2.
V.2.2.1.
V.2.2.2.
V.2.2.3.
PERFORMANCES EVALUATION
Measurements conditions
Results.
Bandwidth
Crosstalk ..
Transition times
111.1
111.1.1.
111.1.2.
111.1.3.
1I1.1A.
111.2
111.2.1.
111.2.2.
111.2.2.1.
111.2.2.2.
111.2.2.3.
111.2.3.
111.2.3.1.
111.2.3.2.
IV
AN377/0490
........... .
....... .
7
8
8
8
8
8
9
9
9
9
9
16
16
16
16
16
16
16
16
1/23
1035
APPLICATION NOTE
The aim of this Application Note is to describe the
basic operation of the TEA51 01 A video amplifier
and to provide the user with basic hints for the best
utilization of the device and the realisation of high
performance applications. Application examples
are also provided to assist the designer in the
maximum exploitation of the circuit.
• for automatic adjustment of cutoff and also,
where required, video gain in order to improve
the long term performances by compensation
for aging effects through the life of the CRT.
This adjustment can be done either sequentially (gun after gun) or in a parallel mode.
• for limiting the average beam current
GENERAL
A video amplifier must also be flashover protected
and provide high crosstalk performances. Crosstalk effects are mainly caused by parasitic capacitors and thus increase with the signal frequency. A
crosstalk level of -20dB at 5MHz is generally acceptable.
The control of state-of-the-art color cathode ray
tubes requires high performance video amplifiers
which must satisfy both tube and video processor
characteristics.
When considering tube characteristics (see fig 1314 on page 14),we note that a 130V cutoff voltage
is necessary to ensure a 5mA peak current.However 150V is a more appropriate value if the saturation effect of the amplifier is to be taken into
account. As the dispersion range of the three guns
is ± 12%, the cutoff voltage should be adjustable
from 130V to 170V. The G2 voltage, from 700 to
1500V allows overall adjustment of the cutoff voltage for similar tube types.
A 200V supply voltage of the video amplifier is
necessary to achieve a correct blanking operation.
In addition, the video amplifier should have an
output saturation voltage drop lower than 15V, as
a drive voltage of 130V (resp. 115V) is necessary
to obtain a beam current of 4 mA for a gun which
has a cutoff point of 170V (resp. 130V).
Note: For all the calculations discussed above, the
G1 voltage is assumed to be Ov.
The video processor characteristics must also be
considered. As it generally delivers an output voltage of 2 to 3V, the video amplifier must provide a
closed loop DC gain of approximately 40.
The video amplifier dynamic performances must
also meet the requirements of good definition even
with RGB input signals (teletext, home computer ... ),
e.g. 1mm resolution on a 54cm CRT width scanned
in 521ls. Consequently, a slew rate better than
2000V/IlS, i.e. rise and fall times lower than 50ns,
is needed. In addition, transition times must be the
same for the three channels so as to avoid coloured
transitions when displaying white characters. The
bandwidth of a video amplifier satisfying all these
requirements must be at least 7MHz for high level
signals and 1OMHz for small signals.
One major feature of a video amplifier is its capability to monitor the beam current of the tube. This
function is necessary with modern video processors:
2/23
Table 1 summarizes the main features of a high
performance video amplifier.
The SGS-THOMSON Microelectronics TEA51 01 A
is a high performance and large bandwidth 3 channel video amplifier which fulfills all the criteria discussed above. Designed in a 250V DMOS bipolar
technology, it operates with a 200V power supply
and can deliver 100V peak-to-peak output signals
with rise and fall times equal to 50ns.
The 5101 A features a large signal bandwidth of
8MHz, which can be extended to 10MHz for small
signals (50 Vpp).
Each channel incorporates a PMOS transistor to
monitor the beam current. The circuit provides
internal protection against electrostatic discharges
and high voltage CRT discharges.
The best utilization of the TEA 5101A high performance features such as dynamic characteristics,
crosstalk,or flashover protection requires optimized application implementation. This aspect will
be discussed in the fourth part of this document.
Table 1:
Maximum Supply Voltage
220V
Output voltage swing "Average"
100V
Output voltage swing "Peak"
130V
Low level saturation (refered to VG 1)
15V
Closed loop gain
Transition time
40
50ns
Large signal bandwidth
7MHz
Small signal bandwidth
10MHz
Beam current monitoring
Flash over protection
Crosstalk at 5 MHz
----------------------------~~~~~~gv~~9~~
1036
Main features of a high performance
video amplifier
-20dB
----------------------------
APPLICATION NOTE
I - DESCRIPTION
The complete schematic diagram of one channel of the TEAS1 01 A is shown in fig 1.
Figure 1.
9
feedback
output
(~;)
Voo
5
R7
cathode
output
D.3
R10
20K
cathode
current
T4
R1
T 1 350
350
T2
2.5K
.1--+--;-----,
C
3pF
V90TEA5101A-01
1.1 INPUT STAGE
The differential input stage consists of the transistor
T1 and T2 and the resistors R4,R5 and R6.
This stage is biased by a voltage source T3,R1,R2
and R3.
R2
VB(T1) = (1 + R3) x VB(T3) == 3.SV
Each amplifier is biased by a separate voltage
source in order to reduce internal crosstalk. The
load of the input stage is composed of the transistor
T 4 (cascode configuration) and the resistor R7. The
cascode configuration has been chosen so as to
reduce the Miller input capacitance. The voltage
gain of the input stage is fixed by R7 and the emitter
degeneratio.n resistors R5, R6,and the T1,T2 internal
emitter resistances. The voltage gain is approximately SOdB.
Using a bipolar transistor T4.and a polysilicon resistor R7 gives rise to a very low parasitic capacitance at the output of this stage (about 1.SpF).
Hence the rise and fall times are about SOns for a
100V peak-to-peak signal (between SOV and
1S0V).
3/23
---------------- ~~~iG~~~~~~~ ----------------
1037
APPLICATION NOTE
1.2 OUTPUT STAGE
II - FUNCTIONAL DESCRIPTION
The output stage is a quasi-complementary class
B push-pull stage. This design ensures a symetrical
load of the first stage for both rising and falling
signals. The positive output stage is made of the
DMOS transistor T5,and the negative output stage
is made of the transistors PMOS T 6 and DMOS T 7.
The compound configuration T 6-T 7 is equivalent to
a single PMOS. A single PMOS transistor capable
of sinking the total current would have been too
large.
The schematic diagram of one TEA51 01 A channel
with its associated external components is shown
in fig.2
By virtue of the symetrical drive properties of the
output stage the rise and fall times are equal (50ns
for 1OOV DC output voltage).
1.3 BEAM CURRENT MONITORING
11.1 VOLTAGE AMPLIFIER
11.1.1. Bias conditions Vin
= V,el
The bias point is fixed by the feedback resistor
Rt,the bias resistor Rp, and by the internal reference voltage when Vin = V,et.
If Vois the output voltage (pin 9) :
Rt
Va = (1 + Rp) x V,et
(1 )
This function is performed by the PMOS transistor
T s in source follower configuration. The voltage on
the source (cathode output) follows the gate voltage (feedback output). The beam current is absorbed via Ts . On the drain of Ts, this current will
be monitored by the videoprocessor.
In this state Tl and T 2 are conducting. A current
flows in R7 and T4 soTs is on. The Ts drain current
is fed to the amplifier input through the feedback
.
resistor. The current in R7 is:
1.4 PROTECTION CIRCUITS
and the current in Ts and Rt is:
= VDD-Va-VGs(Ts)", VDD-Va
I(R
7)
I(T
1.4.1. MOS protection
Four zener diodes DZ(I-4) are connected between
gate and source of each MOS in order to prevent
the voltage from reaching the breakdown voltage.Hence the VGS voltage is internally limited to
±15V.
1.4.2. Protection against electrostatic discharges
All the input/output pins of the TEA51 01 A are protected by the diodes Dl-D7 which limit the overvoltage due to ESD.
R7
-
R7
_ Va,- V,et _ Va
-R-t-- = Rt
S) -
Thus the total current absorbed by each channel of
the TEA51 01 A is :
VDD
1
1
-+Va x (---)
R7
Rf R7
The cathode (pin 7) output voltage is:
Va + VGs(Ts) = Va
The beam current is absorbed by Tsand Rm. The
voltage developed across Rm by this current is fed
to the video processor in order to monitor the beam
current.
1.4.3. Flashover protection
A high voltage and high current diode Ds is connected between each output and the high voltage
power supply. During a flash, most of the current is
generally absorbed by the spark gap connected to
the CRT socket. The remaining current is absorbed
by the high voltage decoupling capacitor through
the diode Ds. Hence the cathode voltage is
clamped to the supply voltage and the output voltage does not exceed this value.
4/23
11.1.2. Dynamic operation
The TEA51 01 A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and
Re.
Since the open loop gain Ais not infinite, the resistor
Rp and the input impedance Rin must be considered.Hence the voltage gain is
G=
_Bf x
Re
- - - - - - - - - - - - - ! f i ~i~@mg~~21;~
1038
. 1
1
Rf
1 + A(1 + Rp II Re II Rin)
(2)
-------------
APPLICATION NOTE
Figure 2.
c
~----------~~,----------------~----~~------~
9 feedback
output
(:~)
voo
5~r-----~r-----~~~---------.
D5
~~~~~71----,MA~-4
(:~)
R1
input o---J\AAf\--l----0-----.!--t
T1
350
350
R5
R6
2.5K
T2
C
R4
3pF
3500
R3
l.5K
V90TEA51 01 A-02
11.1 .2.1. Input voltage Vin < Vrel (black picture)
In this case the current flowing in R7 and T1 decreases whilst the collector voltage of T4 and the
output voltage both increase. In the extreme case,
I(T1) = I(R7) = 0 and Va= VDD-VGs(T5)
In order to charge the tube capacitor the voltage is
fed to the cathode output in two ways:
• through the PMOS (with a VGS difference) for
the low frequency part
• through the capacitor C for the high frequency
part (output signal leading edge)
To correctly transmit the rising edge, the value of
the capacitor C must be high compared to CL_
With the current values used (C = 1nF,CL = 10pF),
the attenuation is very small (0;99)
11.1.2.2. Input voltage Vin > Vrel (white picture)
In this case,the current in R7 and T 1 increases with
an accompanying drop of T4'S collector voltage until
T1 and T4 are saturated. At this point:
Va
=Ve(T4) =Vee
During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways:
• through the capacitor C and the compound
PMOS T6-T 7 for the high frequency part (faIling edge)
• through the PMOS T 8 and the resistor Rm for
the low frequency part.
APPLICATION NOTE
11.2 BEAM CURRENT MONITORING
effect does not occur with the TEA 51 01 A.
11.2.1. Stationary state
11.2.2. Transient phase: low current measurements
The beam current monitoring is performed by the
PMOSTs and the resistor Rm. When measuring low
currents (leakage, quasi cutoff),the Rm value is
generally high. When measuring high currents
(drive, average or peak beam current), Rm is generally bypassed by a lower impedance.
The cut-off adjustment sequence is generally as
follows:
In a first step, the cathode is set to a high voltage
(180V) in order to blank the CRT and to measure
the leakage current. In a second step, the tube is
slighly switched on to measure a very low current
(quasi cut-off current). This operation is performed
by setting the cathode voltage to about 150V and
adjusting it until the proper current is obtained. The
maximum time available to do this operation is
generally about 5211S.
It should be noted that the current supplied by the
three guns flows through this resistor.Hence,with
too large a value for the resistor Rm,the cathode
voltage of the tubes will become too high for the
required operating current values.This is a fundamental difference between the TEA51 01 A and discrete video amps. In discrete video amps, the
current monitoring transistor is a high voltage PNP
bipolar which may saturate. In this case the beam
current can flow through the transistor base and it
is no longer monitored by the video processor. This
Fig.3 shows the simplified diagram of the
TEA51 01 A output, the voltages during the different
steps, and the stationary state the system must
reach for correct adjustment.
Figure 3.
/~~5V
Vc
/
~
I
180V
I
,-------------------~;~19
150V
C
Vc
lnF
181.5V
1
152.5V
r---l
R
lKO
K
I
I
I
I
I
I
I
I
I
I
I
I
I
I
181.5V
~~1 =RxC L = IOns
I
CL:
*:
I
{~2 =RxC = IJ.Ls
I
152.5V
:~
I
L. _ _ _ ..J
151.5V
BLANKING
..
CUTOFF
V90TEA5101 A-03
6/23
----------------------------~~~~@~g~r~~~ ----------------~----------
1040
APPLICATION NOTE
During the blanking phase, the tube is switched off,
the PMOS is switched off and its VGS voltage is
equal to the pinch-off voltage (about 1.5V). The
voltages at the different nodes are shown in figure
3 (V(9) = 180V, V(k) = 181.5V). The falling edge of
the cutoff pulse is instantaneously transmitted by
the capacitor C. When the stationary state is
reached, the cathode voltage will be 152.5V if the
voltage on pin 9 is 150V, as the VGS voltage of the
conducting PMOS is about 2.5V.
We can see that the voltage on C must increase by
an amount of L'.Vc = 1V. This charge is furnished by
the tube capacitor which is discharged by an
amount of L'.VCL = 29V with a time constant equal
to R x CL (10 ns). By considering the energy
balance, we can calculate the maximum charge
L'.Vmax that CL can furnished to C
-ICL
L'.Vmax=·'VCXL'.VCL= 3V
Since this voltage is greater than L'. Vc, the capacitor
C can be charged and the stationary state is
reached without any contribution being required
from the tube current,i.e. the whole tube current
can flow through the PMOS and the adjustment can
be performed correctly.
Considering higher voltage and beam current
swings, the margin is greater because:
• the voltage swing across the tube capacitor is ,
greater
• the tube current is higher and the picture is not
disturbed even if part of the beam current is
used to charge the capacitor C.
111- EXTERNAL COMPONENTS CALCULATION
The implementation of the TEA5101A in an application requires the determination of external component values. These components are Rf, Re, Rp
and Rm (see figA). The dissipated power in the Ie
and in the feedback resistor Rf must also be calculated in order to correctly choose the power ratings
of the heatsink and resistors.
Figure 4.
V1N(BLK)
j\{
,------------------7---,
1
41
1
1
19
+
1
1
1
1
17
f--I----I~
t
r'o'"
V
Video f - - - - - '
Proc
V90TEA5101A-04
---------------------------
~~i~~~~~:~~~
---------------------------7/23
1041
APPLICATION NOTE
111.1 COMPONENTS VALUE CALCULATION
R _
Vrel
p - VOU! (BLK) - Vrel Vin (BLK) - Vrel
RI
+
Re
From equations 1 and 2 in section 11-1, both the
value of the DC output voltage and the voltage gain
depend directly on the resistor RI. Hence RI must
be determined first before calculating the value of
Re and Rp in order to obtain the correct gain and
DC output voltage.
I
Vin (BLK) = 6.7V
with RI= 39k£1
Re = 1.Sk£1
for a 150V black level
1
I Rp = 680£1 I
1
RI
1+1\(1 +Rpl/Re l/ R)
111.1.4. Cu rrent measurement resistor Rm
Rm must be determined by taking into account the
quasi cutoff current leo and the input voltage Vc of
the video processor.
G@_Bt.
Re
where Re is generally implemented as a variable
value for channel gain adjustment.
If the gain adjustment range Gmin, Gmax is known:
RI
RI
Re min = - G and Re max = -G
.
min
With Gmin = 15 and Gmax =80 :
Vin (BLK) =2.7V
with RI = 39k£1
Re = 1.Sk£1
Or
Since the open loop gain A is high enough (SOdB),
we can approximate the calculation:
I
*" Vrel :
I Rp = 1.2k£1 I
The voltage gain is calculated from the following
formula (see section 11-1):
max
with RI = 39k£1
Rp = 1k£1
- If Yin (BLK)
111.1.2. Input resistor Re
Re
Vrel
R
X I
yOU! (BLK) - Vrel
For a 1S0V black level:
111.1.1. Feedback resistor RI
The value of RI must be as low as possible in order
to obtain the optimum dynamic performance from
the TEAS1 01A (see section IV-1). A typical value of
RI is 39 k£1.
G=_Bt.
Rp =
- If Vin(BLK) = Vrel
,
Vc
Rm=leo
- With the videoprocessor TEAS031 D (Vc = 2V) :
Rm = 120kQ with leo = 16J..lA
- With the videoprocessor TDA3S62A (Vc = O.SV)
which requires a DC biased input "Black current
stabilization" (pin 18), the schematic diagram is
the following:
Re min = 470fl
Figure 5.
Re will be made of a 2.2k£1 potentiometer and 470£1
fixed resistor.
111.1.3. Bias resistor Rp
Rp must be chosen in such a way that the black
level output voltage VOUT(BLK) is equal to the cutoff
voltage, which is a characteristic of the Wbe currentlyused, when the DC black level input voltage
VIN(BLK) is the mean value of the adjustment range
of the video processor. This is the optimum condition to ensure a correct adjustment during the
lifetime of the tube. Rp can be calculated by considering the TEA51 01 A as an operational amplifier
and applying the usual formula:
6
112V
120K \l
I C.o.
TDA3562A
pin18
82KO
V90TEA5101 A-05
-------------- ~ ~~~,;m~::~~©~ -------------8/23
1042
APPLICATION NOTE
The DC bias is 12 x
12~! 82 = 5V
PSR
POR
= 0.8W
= 0.1W
The quasi cutoff current is
a.5 ( __1_ + -~-) x 1 x 10-3 = 10uA
,
1~
~
111.2 DISSIPATED POWER IN EXTERNAL COMPONENTS
The only components dissipating power are the
TEA51 01 A and the feedback resistor. The dissipated power has a constant static component and
a dynamic component which increases with frequency. The theoretical calculation is not sufficiently accurate to determine the correct dissipated
power. The best way consists of measuring the
power in different configurations of the circuit:
steady state (no input), sinusoidal input,and in situ
(in a TV set with a video input signal). The mea·
surement method will be described first and then
the results and calculations will be discussed.
Measurements are more difficult to carry out when
the IC is working in a TV set. VouT(AVG) can be
measured with an oscilloscope (difference of level
between AC and DC coupling) and VOUT (RMS) can
be measured by connecting an RMS voltmeter to
the feedback resistor. In this case we have the
following results (see section 2.2.3):
VOUT (AVG) = 130V and PSR = 1.3W
VOUT (RMS) = 32V and POR = 80cnW
In each case, the term POR can be neglected as a
reasonable approximation. Hence, the power dissipated by the IC will be:
Pi
= Voo
3V 2 OUT (AVG)
X 100· - - - - - - -
and the power dissipated in Rf will be :
Pr = V 2 OUT (AVG)
111.2.1. Measurement method
The dissipated power can be determined by measuring the average supply current 100 (principally
high voltage supply current Voo) and by subtracting
the power dissipated in the external components
from the calculated power delivered by this supply
Voltage.
The power delivered by the high voltage power
supply is : P = Voo X 100
The power dissipated in the external components
(principally the feedback resistor Rf) is:
.
3 x V2 OUT (AVG)
. for the static part: PSR =
Rf
.
3 X V 2 OUT (RMS)
. for the dynamic part: POR = ~- R j - - -
Rf
111.2.2. Results
111.2.2.1. Static power
Table 2 shows the measured values of 100 and the
calculated power for three values of Vout and for
Voo = 200V
Table 2
~UT
(V)
When the IC is driven by a sinusoidal signal (capacitive drive),the measurement and calculation
are straightforward:
VouT(AVG) = VouT(DC)
P,
Pi
100
(rnA)
e.-~--
-
(W)
-~-----
e.-.
(W)
50
16
3
0.065
100
15
2.2
0.25
1.2
0.6
150
-----_.-
_ 14.6__ ~
We can see that the static power dissipated in the
IC decreases with VOUT increasing, but obviously
the power dissipated by Rf increases as VOUT
increases.
111.2.2.2. Measurement with sinusoidal input
V M S ) _ VOUT (peak to peak)
oUT(R
2 x -{2
With VOUT (DC) = 100V and
VOUT (peak to peak) = 1OOV and Rf
Rf
= 39kQ
Table 3 summarizes the results obtained from prac·
tical measurements as functions of VouT(DC) and
of the frequency (the three channels are driven
simultaneously).
-------------- ~ ~~;~;m~:~~g~ - - - - - - - - - - - - - - - =9/231043
APPLICATION NOTE
Table 3.
VOUT
(V)
(DO
1MHz
(rnA)
(DO
7MHz
(rnA)
VOUT (PP)
1MHz
(V)
VOUT (PP)
7MHz
(V)
Pi
1MHz
(W)
Pi
7MHz
(W)
P,
(W)
50
20.7
44.6
66
50
3.9
8.7
0.065
100
20
59.5
100
80
3
11
0.25
150
18
45
100
67
1.7
8.2
0.6
We can see that when driving the IC with a HF
sinusoidal signal, care must be taken to avoid
excessive temperature increase.
111.2.2.3. Measurement in a TV set
We have determined the worst cases of dissipation
in a TV set. These trials have been carried out on
one particular TV set, and may not be representa-
tive for all TV sets. In this particular TV set, the worst
cases of dissipation occur with noise signal (from
HF tuner) and with a multiburst pattem (0.8 to
4.8MHz) in RGB mode.
Table 4 summarizes the results in these two cases
when the brightness control is set to min and max
value (the contrast control is set to max).
Table 4.
VOUT(AVG)
(V)
(DO
(rnA)
VOO
(V)
Pi
(W)
P,
(W)
148
188
22.2
23.3
218
224
3.15
2.5
0.56
0.9
131
158
23.6
213
221
3.7
2.9
0.44
0.64
Bright.max Noise
Bright.min
. Bright.max Multiburst
Bright.min
22
111.2.3. Design of heatsink and external components
Figure 6.
Cf
111.2.3.1. Heatsink
As discussed above, the power dissipated in the
IC in a TV set can reach about 4W. In this case, a
12°C/Wheatsink seems to be sufficient. Such a
heatsink will give Ti = 115°C for T room = 60°C.
The resulting margin guarantees correct reliability.
111.2.3.2. Feedback resistors
1 Watt type feedback resistors must be used, as
they may need to dissipate 0.9W when the TV set
is working and up to 1W when the TV is blanked
(VOUT = 200V), for example when the security of
the scanning processor is activated.
IV - APPLICATION HINTS
IV.1 DYNAMIC PERFORMANCES
Figur~ 6 shows the simplified schematic diagram
of the TEA5101A in AC mode.
Gf is the parasitic capacitor between the input and
the output.
10/23
V90TEA51 01 A-OB
Cin is the parasitic capacitor between the input and
ground. The voltage gain v'ersus frequency can be
deduced from the formula (2) in chapter" section 1.2 :
G(s)
=_
RI
Re (1 + RI GI s)
1 .
1 + _1_ (1 + ~ 1 + Reg Gin s)
A(~)
Req 1 + RI Gf' S
with Req=Rp-'/RellRin and A(s) open loop gain.
----------~--------------~~ ~~~~~g~~~~~~
1044
X
-----------------------------
APPLICATION NOTE
A(s) is a second order function such as
AO
1 + bs
+ as 2
with a = 9 x 10- 16 S2
b = 60 x 10-9 S
AO = 400
Assuming Req
G(s)~-
x Cin =
Rf
X
+ AO
with B
This capacitor is generally too high. It consists of:
o the self parasitic capacitor of the feedback
resistor
.. the parasitic capacitor due to the PCB layout.
Cf, we find:
1 -x
Rf
xRe (1 + Rf Cf s) 1
B 1
1
B
b
B
2
+ AO+B s+ AO+B as
= 1 +~
Req
We see that the closed loop amplifier is equivalent
to a combination of a second order circuit and a first
order one. The latter comprises the feedback resistor and the parasitic capacitor between input and
output. With the current values
Rf = 39kQ
Cf = 0.5pF
Re = 2kn
Cin = 15pF
Rin = 14kQ
Rp
= 1.2kQ
x Cin = 10ns
x Cf = 20ns
Req
B = 56
The second order circuit characteristics are:
Natural frequency:
1
Fn = - - 2x7txa
Practically,the best bandwidth performances are
achieved by:
.. the smallest input-output capacitor and
the smallest capacitor between an input and
ground
• using a feedback resistor with the smallest
possible value but large enough to yield a sufficiently high gain.
.. using a feedback resistor with small parasitic
capacitance (typ 0.2pF). Some resistors have
0.5 or O.B pF parasitic capacitor.
The parasitic capacitors discussed above are usually the ones which need to be taken into account.
However any other parasitic capacitor or inductor
can modify the frequency response. For instance,a
too large capacitor value between the feedback
output and ground can create a dominant pole and
cause a potential risk of oscillation.
we have
Rf
value of Cf is too low, the response curve will have
a peak (due to the second order circuit). A "ringing"
effect will be present on pulse-type signals and an
instability and oscillation can occur at some frequencies.
AO+ B
x-=
B
15MHz
IV.2 CROSSTALK
Figure 7 shows the different parasitic links inducing
crosstalk.
Figure 7.
damping factor :
b
B
z = 2 x a x AO + B
= 0.35
The cut off frequency of. the first order circuit is :
fc =
1
2 x 7t Rf X Cf
= BMHz
The amplifier response is thus the combination of
the responses of these two circuits. The contribution of the parasitic capacitor Cf to the frequency
response is very important. If the value of Cf is too
high, the contribution of the first order circuit will be
of overriding importance and the resulting
bandwidth of the amplifier will be too small. If the
The crosstalk can be caused by:
.. parasitic coupling between the inputs (Cpi)
• parasitic coupling between the outputs (Cpo)
.. parasitic coupling between an output and a
near input of another channel (Cp).
11/23
1045
APPLICATION NOTE
Parasitic coupling may be capacitive or be caused
by HF radiations.
The third type of parasitic coupling is predominant
since it involves the addition by feedback at relatively high level(output) signals to relatively low
level (input) signals. For example, a 0.1pF C p parasitic capacitor between an output and the input of
another channel will act as a differenciator with the
feedback resistor Rf = 39KO.
The transfer function of this integrator will be RI x
Cp X S (0.2j at BMHz) and thus the crosstalk will be
-14dB .at BMHz. The .parasitic coupling between
inputs and outputs must be minimized to achieve
an acceptable crosstalk (-20dB at SMHz). This can
be done by crossing only the input wires and separating the input and output leads. High voltage
components and wires must be laid out as far as
possible from small signal wires,even if this results
in a larger circuit board.
HF radiations from the feedback resistor must not
induced a voltage signal at the input of another
channel. This can be achieved by:
• spacing out the feed back resistors
• mounting these resistors in the same direction
and strictly aligned one under another.
• mounting these resistors 1cm above the PC
board
• using ground connections to insulate the input
wires
IV.3 FLASHOVER PROTECTION
flash" tubes). Nevertheless, some protection measures are suggested by the tube manufacturers:
.. connect spark gaps on each electrode
(1 to 3kV or 12kV for focus)
.. connect the spark gaps to a separated ground
directly connected to the chassis ground by a
non inductive link
" connect the cathodes or grids by protective resistors. These resistors must be able to withstand 12kV (20kV for focus)instantaneous
voltages without breakdown and without any
change of value following successive flashes.
These resistors must be of a non-capacitive type. 1/2W (1W for focus) hot molded carbon type resistors are well suited for this
application.
o the grid and cathode connections on the PC
board must be as short as possible and
spaced well away from other connections in
order to avoid parasitic inductions.
Furthermore, the TEAS1 01 A has been provided
with an additional effective feature to improve the
flashover protection.As described in section 1-4, a
protection device has been included comprising a
high voltage high current diode which is connected
between each output and the high voltage power
supply. The equivalent diagram of this protection is
shown in Figure B.
Figure B.
A picture tube has generally several high voltage
discharges in its lifetime. This is due to the fact that
the vacuum is not perfect coupled with the presence of metallic particles evaporated from the electrodes.Hence, short circuits (very brief fortunately)
can occur between two electrodes,one of which is
usually the anode (at EHT potential). An overvoltage can be induced on the cathodes or on the
supplies even if a flash occurs on an electrode other
than a cathode, because of the possibility of flashes
in series or overvoltages due to inductive links on
the video board or on the chassis. these overvoltages can destroy an IC particularly the video
amplifier which is the most vulnerable since it is
directly connected to the tube.
Two kinds of flashes can occur:
The tube manufacturers have made much progress in technology in order to reduce the frequency
of flashes and their associated energy (increased
quality of vacuum, internal resistance for "soft
1) low resistance flashes during which the spark
gaps are activated since the cathode voltage exceeds the breakdown value of the spark gap. In this
case the equivalent diagram is the following:
V90TEA5101 A-DB
The flash current is diverted to the ground through
the diode and the decoupling capacitor C.
12/23
-------------~ ~~;~,[0mg~l~g~ --------------
1046
APPLICATION NOTE
Figure 9.
2000
If V < 2 kV, I < -R- , I < 2A and Rt
=12kQ
The time constant of the flash is Rt x Ctube = 12 !ls,
the decay time is approximatevely 30 !ls. The value
of C must be
~txl
C>
--
~Vc
eg
C > 6!lF
in order to ensure a VC variation less than 10V.
The total decoupling will be made up by a 10!lF
electrolytic capacitor connected in parallel with a
22nF plastic film capacitor with good HF properties.
It flash current (oo 1000A)
Lf inductance of the connection (oo 10!lH)
V90TEA5101A-09
Ctube previously charged to 28kV is instantaneously discharged during
~t
It must be placed very close to the TEA5101 A to be
efficient. Otherwise, the equivalent diagram will be
the following (case of low resistance flash).
Figure 11.
V
= Ctube x ~It = 30ns
Since the voltage across the spark gap falls almost
instantaneously to 2000V, the peak current I flowing into the diode is (assuming Vc is held by good
decoupling) :
1= Ve
x~ t
Ctube
= 6A
Lf
To ensure a variation of Vc less than 10V, C must
be
I X~t
C>
-~Vc
eg
C> 18nF
The decoupling must have good HF characteristics.
2) high resistance flashes in which the spark gaps
are not activated. In this case the equivalent diagram is the following:
V90TEA5101A-ll
~Vc = I x ~ t + Lpl X I
C
~t
~Vt =
210V with LPl = 1 !lH and Lp2 = 0
In this case the VDD voltage can rise to a dangerous
value (+210V increase) and the protection is not
efficient.
Figure 10.
r
If the connection between the socket ground and
the chassis ground is inductive (L p2 0), the effect
is the same.
*"
Rt~ ~_~ID5
Ctube
hF
I
I
I
\.J. 7
L1j'V
I
I
I
I
L_II-_J
vet
I
C
.
However in this case, all the TV IC's,and not only
the TEA51 01A,will be exposed to destructive overVoltages.
IV.4 OUTPUT SWING
V90TEA5101A-l0
The simplified diagram of this function is shown
below (See Chapter II and chapter III ):
13/23
-------------- ~ ~~~Q.jn'~!:1~~l'! --------------
1047
APPLICATION NOTE
Figure 12.
The minimum value of Vk (due to all the voltage
drops in the resistors and in the amplifier) is given
by the equation (see fig 12 above):
Vk = (R + Ron + R1 + 3
X
Rm)
X
It = Req
X
It (1)
with Ron: on state PMOS resistance
To find the maximum available current Itmax,we can
draw the curves of the equation (1) on the tube
characteristics. Itmax will be given by the intersection point of the curves.Since the tube characteristics are: It Vs Vcutoff + VG1- Vk the equation (1) must
be changed to
~
~t:
.••••••.
1-1
TEA5101A
C
I
CRT
It = VCUTOFF + VG1 - Vk
Req
(2)
The current delivered by a CRT is given by the
characteristic curves (fig 13-14).
Assuming VG1= 0, we can draw the curves of
equation (2) for several.values of Vcutoff (eg 150V
and 200V) and several values of Req
(eg 5k,10k,15k,20k) (see fig 13 and 14). We can
see from these. curves that Req must have the
following values to allow the tube to source 4mA
per gun:
Figure 13.
Figure 14.
V90TEA5101A·12
,-----------------
,---------------~
HEATER VOLTAGE - 6.3V
ANDOE-TO-GRIO No, 1 YDLTAGE2SkY
GRID No. 3- TO-GRID No. 1 VOLTAGE
(EACH GUN) ADJUSTED TO
PROVIDE SPOT CUTOFF.
HEATER VOLTAGE - 6.3V
ANODE-TO-GRID No.1 VOLTAGE25kV
GRID No. J-TO-GRID No.1 VOLTAGE
(EACH GUN) ADJUSTED TO
PROVIDE SPOT CUTOFF.
200
VIDEO SIGNAL VOLTAGE PER GUN -
V
:=
Ycutoff -
400
600
VG\~
10
20
V90TEA5101A-13
14/23
------------------------------~ ~~~@~~~~~~~
1048
40
60
80 100
VIDEO SIGNAL VOLTAGE PER GUN -
'DO
V
=
Vcutoff -
400
600
YG,.
V90TEA5101A-14
------------------------------
APPLICATION NOTE
Req ~ 5kQ
or Req
~
15k£!
for a 150V cutoff point
for a 200V cutoff point
As Ron value is approximatively 1.7kQ, the measurement resistor must be as low as possible.
Working with higher cutoff point would be an alternative solution. But a 200V cutoff point seems to
be too high a value since in this case the supply
voltage would be greater than 200V and would
affect reliability performances.
Another solution consists of connecting a zener
diode as shown in Figure 15. With this device the
high current operation of the TEA51 01 A is similar
to that of a discrete amplifier (with PNP) operation.
Figure 15.
Since the power supply is 200V, 30V are available
to ensure correct blanking operation. The DC output voltage must be increased by 12V from its
previous value.
Note that all the phenomena described in this
section concern a static or quasi-static (15kHz)
operation (e.g. white picture or rather large white
pattern on a black background). When current
peaks occur (e.g white characters insertion or
straight luminance transition), the peaks will be
absorbed by the coupling capacitor and the voltage
amplifier,and hence the tube will be able to source
a greater current.
IV.S LOW CURRENT MEASUREMENTS
We have seen in section 11-2.2 how the beam
current monitoring works (see fig.3 page 6). We
have seen that the capacitor C must charge again
after the blanking phase.
V90TEA51 01 A-15
For low currents, if the zener voltage is greater than
the VGS voltage, the zener diode is biased off and
the beam current flows through the measurement
resistor. When the cathode voltage (pin 7) drop is
limited because of the pin 6 voltage and when the
pin 9 voltage continues to decrease,the zener
diode is switched on when V7 - V9 = Vz. In this case
the beam current is absorbed by the voltage amplifier and the tube can provide larger current values.Nevertheless, the pin 7 output voltage will
follow the pin 9 voltage with a Vz difference.
Since the pin 9 voltage is internally limited to 14V,
the output voltage will be limited to 22V with a 8V
zener diode.
The CRT bias voltages shown on the previous
curves are referenced to the G1 Voltage. The
TEA51 01 A is referenced to ground. We can choose
to work with a G1 voltage greater than ground and
thus the low level saturation is not taken into account. In this case, the cutoff points must be increased. When choosing VG1 = 12V, the cutoff
points will be adjusted to 170V (instead of 150V).
This charge is generally furnished by the tube
capacitor independently from the beam current. However,if during the blanking phase, the output voltage is too low (e.g. the PMOS is reverse
biased (- 20V) because of a too high leakage
current or when measuring with an oscilloscope
probe), the f..VC required to charge C again will be
greater than the maximum charge available from
the tube capacitor. Hence the beam current will
have to charge C in a first step.
Since this current is rather low during the cutoff
adjustement phase, a long time will be spent to
charge C. The current absorbed by the PMOS and
fed to the videoprocessor will not be equal to the
beam cu rrent and the cutoff adjustement will not be
correct.
Hence the reverse voltage across the capacitor C
must be limited by a diode connected as follows:
Figure 16.
1
-------i:t----r
j --
L-9
IN11~8
--I
.----
::=J---~
f---
J
[XJ6
V90TEA51 01 A-16
-------------- ~ ~~~(c]t~,g~~g~ -------------15/23
1049
APPLICATION NOTE
With this configuration, the voltage across C will be
-0.6V max. Since this voltage must be 2.5V in the
stationary state (see section 11-2.2), the voltage
across C must be increased by 3.1 V and this
charge can be supplied by CL. We can also slightly
decrease the value of C. However if C is too low,
the HF behaviour will be impaired.
v - APPLICATION EXAMPLES
V.1 APPLICATION DESCRIPTION
Figures 17 and 18 show two applications, one for
a 45AX tube and the video processor TDA3562A
(application 1), the other designed for S4 type tube
and the video processor TEA5031 D (application 2).
In these. two applications, the nominal gain is 28dB
and the output black level is 150V. The quasi cutoff
currents are respectively 1OIlA and 161lA for applications 1 and 2.
These applications are implemented using the
same PC board especially designed to allow different options for tube biasing, power supply decoupiing and connections. This PC board allows also
two different tube sockets (jedec B8274 or Bl 0277)
to be connected. Both beam current monitoring
modes (sequential and parallel) are possible.
The layout and the electrical diagram of the PC
board are shown in Figu res 19 and 20.
• AC GAIN = 50 by adjusting P1 0, P20, P30
• LOADING:
- by a 8.2pF capacitor and the probe capacitor
(2pF), the sum is equivalent to the capacitance
of a CRT with the socket and the spark gaps
- the 1Mn resistors connected between each
output and Voo allow the conduction of the beam
current monitoring PMOS transistor in such a
way that VAoc = VBoc= 100V.
• DRIVING by a l!1F capacitor, the HF generator being loaded by 50n.
• the dynamic power dissipated in the IC will increase with frequency. To avoid the temperature increasing, it is necessary to do very quick
measurements or to use a low Rth (7°CIW)
heatsink in forced convection configuration.
Such conditions are not present in a TV set
since the driving signal will be a video signal instead of a pure HF signal.
V.2.2. Results
V.2.2.l. Bandwidth
The curves Figures 23 and 24 show the frequency
responses of one channel with 1OOVpp and 50Vpp
output Voltages.
The bandwidths are approximatively 8MHz at
1OOVpp and up to 1OMHz at 50Vpp.
V.2.2.2. Crosstalk
V.2 PERFORMANCE EVALUATION
As seen in chapter IV, the dynamic performances
(bandwidth, crosstalk) of the TEA5101A is very
dependent on the PCB layout.Consequently, the
evaluation board has been designed to obtain the
best results.
The curves Figures 25, 26 and 27 show the crosstalk for this application.The crosstalk is almost the
same for the six different combinations of the three
channels. The worst value is -24dB at 5MHz.
V.2.2.3. Transition times
The curves Figure 28 show respectively the R, G,
B rise and fall times of respectively 49 ns and 48
ns with a 1OOVpp output voltage (between 50 and
l50V).
To evaluate the performance, the best way is to
work outside of the TV set by driving the amplifier
by an HF generator (or a network analyser) while
simulating the load conditions fixed by the CRT,
since AC performances are directly determined by
the load.
The difference between rise times of the three
channels is less than 1ns ..
V.2.1. Measurement conditions
The difference between fall times of the three channels is less than 2ns.
The schematic diagrams of the AC measurements
are shown in Figures 21 and 22. The conditions are
as follows:
• BIASING: VOUTDc= 100V by choosing
R11 = R21 = R31 = 1.5kn and Voo = 200V
The delay time at rising output is 48ns.
The delay time at falling output is 50ns.
The difference between the delay times is less than
2ns .
The slew ra'te is about 2000VIIlS.
16/23
-------------~ ~~~~;m~~~gL~ --------------
1050
APPLICATION NOTE
Figure 17 : Application 1 (45AX Tube, TDA3562A) - Electrical Diagram.
PIO
Rin
AI3
--iZJ
A cathode
o
Gin
G cathode
A33
lkU1I2W
B cathode
Bin
---r:---CJ----------~~
HEATER
110 LOW LEVEL CONNECTOR C 1
J v"";~,
TEA2031A
I
Yoke
1
OVNt
on the slide contact of potentiometer RT1. The
peak amplitude of this signal depends on the nominal voltage of the Zener diode 02 and on the
adjustment of RT1.
11.3 - LINE SAWTOOTH GENERATION
The line sawtooth signal is applied as a reference
at the +input terminal of the. comparator. It is obtained by integrating the line fly back and the constant current discharge of capacitor C3 in Pin 8
(Figure 23).
The role of Zener diode 02 is to maintain a constant
amplitude of the signal on the slide contact of RT1
whatever the variations in amplitude of the line
flyback signal.
11.3.1 - Role of resistors R7, RB, RT1 and 02
By means of the voltage divider bridge comprising
resistors R7, RT1 and R8, a signal that is the image
of the line flyback signal applied on R7, is obtained
This diode 02 can be also replaced by a single
diode connected to a regulated 12V or 15V power
supply.
Figure 23: Line Sawtooth Generation
.,."
R7
Parabola (50Hz)
Line Sawtooth
D2
18
RT1
/V\
N\I\
R8
TEA2031A
V91E-W-23
16/35
----------------------------~~~~~~9~:9©~
1074
----------------------------
APPLICATION NOTE
11.3.2 - Role of diode 01 and capacitor C3
During line flyback, diode 01 rapidly charges capacitor C3 at the potential available on the slide
contact of RT1.
Then during line scanning, 01 is blocked and C3 is
discharged at constant current (about 50IlA)
through Pin 8.
The peak-to-peak amplitude of the line frequency
sawtooth signal obtained in this way depends di-
rectly on the value of capacitor C3 since it is defined
by the discharge current of the capacitor and the
line period (Figure 24).
This amplitude can be calculated using the following equation:
dt· is
Vs (peak-ta-peak) = C3
where Dt = duration of line and is = current in Pin 8.
Figure 24: Peak-to-peak Amplitude of Sawtooth Signal versus Two Different Values of C3 (with RT1 =
constant)
C3
= 10nF
C3
= 3.3nF
~~/--~~--
Line Flyback Voltage
on RTI Slide Contact
Sawtooth Signal
on C3
250mvj
O.8V
OV
-1==="'---'===--=-""-------------- -- --------- -
t
OV
Same
Peak
Level
-----1> t
Line Flyback Voltage on R7
-
-
-1-----_____
r-
-
- - - - - I - f - - - - - - - - __ _
----/>
t
\
V91E-W-24
The continuous level of this sawtooth signal is set by adjusting potentiometer RT1 (Figure 25).
Figure 25: Continuous Level of Sawtooth Signal for Two Different Adjustments of RT1
Voltage on RTI
Slide Contact
j
Sawtooth Wave
I on C3
ov -1===-'-
Continuous
Level
----------1> t
V91E-W-2S
--------------
~ ~~:~;j~~,~j~.2~
____________
17/35
---'-'-'-C...:...
1075
APPLICATION NOTE
11.4 - OUTPUT STAGE
The output stage is controlled by the comparator
fed by signals applied on its inputs, i.e. the saw-
tooth signal at line frequency on +input (Pin 8) and
the parabola at vertical frequency on -input (Pin 7)
(see Figure 26).
Figure 26: Output Stage
TEA2031A
V91E-W·26
The comparison between the 50Hz parabola and
the sawtooth signal at line frequency (16kHz) produces pulses at line frequency with a duty cycle that
is modulated at vertical frequency. This allows, by
means of the diode modulator, the modulation of
the line scanning current during each field period
in order to carry out the pincushion correction (or
East/West correction) (see Figure 27).
Figure 27: PWM Output Signal (with adaptation of time scales)
Input +
Pin 7
Input Pin 8
20ms
Continuous
Level
OV
~----------------~------------------~--~
V91E-W-27
The role of the filter C2 and RT3 + R6 is to suppress the line frequency of the feedback output signal.
18/35
---------------- ~ ~~~(~mg~~l~~~ -------------------
1076
APPLICATION NOTE
11.4.1 - Operation of the Output Stage
11.4.1.a - Output in the low state (Figure 28)
The operation of the output stage can be considered as 3 separate cases according to the 3 possible states of output Pin 5.
In this case resistances R6 and RT3 are connected
to the ground, therefore they are in parallel with R5,
according to the following diagram.
Figure 28: Output in Low State
TEA2031A
V91E-W-28
The continuous level and the peak-to-peak amplitude of the parabola are at their minimum when the
RT3 value is minimum.
itor is equivalent to an open-circuit at vertical frequency.
It is possible to calculate the voltage for a given
point of the parabola (Pin 7) using the following
equation:
In this case, resistances R6, RT3 and R5 form a
voltage divider bridge which returns on Pin 7 and
capacitor C2 part of the continuous voltage available on the output terminal that is added to the
parabola voltage.
v
. R5 . eR6 + RT3)
7b =' 17' R5 + R6 + RT3
The capacitance of C2 is neglected as this capac-
11.4.1.b - Output in the high state (Figure 29)
The equivalent circuit diagram is the following:
Figure 29: Output in High State
ov
Continuous level
is maximum when
RT3 is minimum
.j---'-~~~~~~~-
TEA2031A
V91E-W-29
It is possible to calculate the voltage for a given point of the parabola (Pin 7) with the following equation:
V7h
='
i7 . R5 . eR6 + RT3) + V
R5
R5 + R6 + RT3
5 . R5 + R6 + RT3
19/35
~~~~~~~~~~~~~- ~ ~i~@mg~~~~t~ ~~~~~~~~~~~~~-
1077
APPLICATION NOTE
IIA.1.c - Output with commutation
In this case and if capacitor C2 is eliminated,
Figure 30 gives the signal obtained on Pin 7. It
corresponds exactly to the levels and amplitudes
of the parabolas for output in the high state and the
low state, linked by 16kHz commutations.
Figure 30 : Output with Commutation (without C2)
-
Parabola level
for high state
output
-
16kHz commutations
~-
Parabola level
for low state
output
20ms
ov
In normal circuit configuration, capacitor C2 is connected and constitutes a filter with R6 and RT3. The
•
t
V91E-W-30
preceding signal is filtered and is transformed into
the signal shown in Figure 31.
Figure 31 : Output with Commutation (with C2)
Mean continuous level
as a function of the
cyclic ratio of the
output pulses
OV +------------------'~ t
V91E-W-31
The 16kHz line frequency component has disappeared in the signal and only the 50Hz parabola
remains, but slightly modulated at line frequency
by the C2 charge when the output is in the high
state, and by the C2 discharge when the output is
in the low state; this gives a tiny triangular modulation signal.
We see that, when the cyclic ratio increases, the
continuous level of the parabola also increases and
approaches its maximum level when the output is
in the high state. Conversely, when the cyclic ratio
decreases, the continuous level of the parabola
also decreases since it approaches its minimum
continuous level when the output is in the low state.
So the continuous level of the parabola depends
only on the cyclic ratio of the output pulse train. This
level can be calculated by means of the following
equation: Vmean = M . V7h + (1 - M) . V7b
IIA.1.d - Conclusion
where
M
: output pulse cyclic ratio
V7h : mean level on Pin 7, output blocked in the
high state
V71
20/35
: mean level on Pin 7, output blocked in the
low state
For a given parabolic current i7, the parabola peakto-peak amplitude depends only on resistance values R5,R6 and RT3. Therefore by adjusting RT3,
it is possible to obtain a more or less pronounced
parabola and so adjust the importance of pincushion correction.
The continuous level of the parabola depends principally on the mean cyclic ratio at the output, and
much less on the adjustment of RT3.
~~-------------~~~~~~~~~~~
1078
----------------
APPLICATION NOTE
11.4.2 - Operation in association with the
diode modulator
In the majority of cases, the system operates by
drawing more or less high current from the modulator through the connecting inductor. The current
through terminal Pin 5 of TEA2031 A is entering into
the circuit. It flows, either to the ground when the
output is in the low state, or to Vcc through the
internal diode when the output is in the high state
and the output voltage tends to exceed Vcc. The
circuit can also produce current.
Figure 32: Operation with Diode Modulator
LS
ilf(j(j1 __
V91E·W·32
21/35
-------------- ~ ~~~;,ru~M~g~ --------------
1079
APPLICATION NOTE
Figure 33: Output Oscillagrams
amplitude of the line sawtooth wave. Now this
amplitude must be greater than the parabola amplitude (Pin 7) but not so far in order to have a
correction amplitude sufficient but permitting also
an horizontal amplitude adjustment:
Current in connecting
inductor LS
OA
+-----"'------"-~
OA -+++++-H+t-H++H-++HH+t-H-
t
Line deflection
current
- if the line sawtooth wave and the parabola have
the same amplitude, the pincushion correction is
maximum but the horizontal amplitude adjustment range is non-exutent
- if the line sawtooth amplitude is much greater
than the parabola's one, we will have a large
range for the horizontal amplitude adjustment,
but it will be to the detriment of the pincushion
correction amplitude.
Once the desired line sawtooth amplitude has been
fixed, we can calculate the value of C3 with the
following formula
C3 = Ot· ia
Va
V91E-W-33
11.5 - SELECTION OF THE. VALUES OF
CAPACITORS C2 AND C3
where
Ot
: line scan duration (around 53Jls)
Correct operation of TEA2031 A depends partly. on
the choice of these values for two reasons:
ia
: Pin 8 current (around 50JlA)
Va
: line sawtooth peak-to-peak amplitude (Pin 8)
- for a given amplitude of the parabola, the importance of fi nal pi ncushion correction at the output
of TEA2031 A is determined by defining,by
means of C3, the amplitude of the line sawtooth
wave.
- the absence of oscillation at circuit output is
controlled through adjustment of the value of C2
as described below.
11.5.1 - Selection of C3
As seen before (chapter 11.3.2), the value of C3 and
only this value (in the limits of the available voltage
on the slider of RT1) can fix the value for the
22/35
11.5.2 - Selection of C2
The selection of C2 is related to the values of R5,
R6 and RT3. The value of C2 must be large enough
to avoid any risk of oscillations at output for the
entire range of adjustment of potentiometers RT1
and RT3. The value of C2 must be small enough
not to influence the shape of the vertical frequency
parabola.
11.6 - APPLICATION EXAMPLE
A typical application diagram is given in Figure 34.
·~~-------------~~~j@~g~~R~
1080
---------------
APPLICATION NOTE
Figure 34: Typical Application
JL
R7
vee
o
24V
C1
10~F
+~
02
BZX
46C15
Output
3> (to diode
modulator)
Typical frame sawtooth
V91E-W·34
111- TDA4950 - TDA8145 GENERAL
DESCRIPTION
111.1 - INTRODUCTION
this functional block a suppression of the parasitic parabola is possible, see chapter 1.4}.
3. Parabola network producing the current
IA = k(liN}2 (k = constant).
The TDA4950 and TDA8145 consist mainly of 5
parts as seen in the simplified circuit diagram (Figure 35).
4. Comparator and output stage working as a
pulse-width modulator for driving the diode
modulator.
1. Full-wave rectifier for the input current liN.
5. Voltage reference and current reference which
produces the reference current IREF via exter- .
nal resistor RI between Pin 3 and Ground.
2. Current limiter in order to limit the rectified current liN to the maximum value of 40/lA (with
23/35
------------------------------ ~~i~~~9~~~~ ------------------------~~~
1081
APPLICATION NOTE
Figure 35: Simplified Circuit Diagram for TDA4950 - TDA8145
~----------~~~--------------------------~~r_----~
----~-------~
I
I
I--------------------~
Jl
II
u
>'
I
I
I
I
I
I
I
I
I
L _________ J
I ~
I
I
I
I
I
I
I
I
a'"
"
. II
'-----~___fu
-if>
I
I .g
Ifl
I l!'
I
1
~
.3:
"5
Ill..
I
I
I
V91E-W-35
111.2 - DESCRIPTION
ing on the sign of the input current liN.
Let us consider the blocks in detail:
The input amplifier OP1 drives the transistor 05 or
06. They offer two different signal paths, depend-
Assuming that liN is negative, the feedback loop is
closed via the transistor 05 and the output current
IC5 is given by
24/35
- - - - - - - - - - - - - - ~ ~~~@~~~Q~!?CG~ - - - - - - - - - - - - 1082
APPL:ICATION NOTE
IC5 = IE5
(~)=
1 + ~5
-
hN
(~)
1 + ~5
where ~5 is the current gain of the transistor 05. ~5
can be assumed to be more than 100, so the
mismatching between IC5 and liN is less than 1%.
For a positive current liN the output voltage of OP1
decreases: 05 is switched off the current liN is the
emitter current IE13 of 06.
Its collector current IC6 is given by
IC6 = liN (1
!6~6 )
Since the maximum input current is 40~, the
current gain of this PNP transistor is still high
enough. to give a reasonable small error. This current biases the current mirror 08 and 09. A good
matching between the current ICB and IC9 must be
provided. Thus the current Is is given by
!5~5 )
liN < 0
~6~6 )
+ liN. ( 1 +
liN> 0
- liN (1
Is =
Neglecting the base current of 06 and 05, Is is
nearly the absolute value of liN.
Note that for both signal paths, the OP1 has a
feedback factor of 1. This means OP1 must be
frequency compensated for unity gain.
The transistors 03 and 04 work as a normal current
mirror if the current Is plus IE is smaller than the
cu rrent liim :
.
21s < him
In this case the excess current is shunted via the
PNP transistor 01.
If the current Is becomes higher
Is> hi\fl/2
the transistor 01 switches off and 02 picks up the
current Is from the rectifier which exceeds the
maximum value of him/2.
Using the proposed reference resistor RI between
Pin 3 and Ground (11kQ) the current IE can be
described with
JliN
IE =
140llA
liN < 40llA
The parabola network produces an output current
IA which is approximately a parabola: IA = k IE2
The parabolic behaviour IA is obtained via piecewise linear approximation. For this purpose the
identical resistors Rz are connected with the four
emitters. The four different biasing currents iz, 3iz,
5iz, 7iz yield four different threshold voltages, so
the four emitter currents of 011 are switched stepwise. A schematic illustration of the single emitter
currents IEQ11 (1...4) of 011 as a function of the
current IE is given in Figure 36.
Due to the exponential character of the emitter
current as a function of the base emitter voltage,
the output current IA is smoothed.
For designing the values of Rz and iz of this parabola network we must take a compromise between
the smoothing effect and the temperature dependence. Small values of Rz and iz yield small threshold voltages for the 4 emitters of 011 . This means
a good smoothing of the edges, but a worse temperature dependence.
Large values of Rz and iz yield the opposite result.
Practical experiences show that a value of 0.5V for
the 4th emitter (R13 7iz) for IIN= 0 gives an acceptable cmpromise.
Due to different values of resistor Rz, the TDA8145
is adapted to flat square tubes (see Figure 37 for
the two different shapes of the parabola).
1083
APPLICATION NOTE
Figure 36 : Transfer Characteristic of the Parabola Network
V91E-W-36
Figure 37: Parabola Shapes for TDA4950 and
TDA8145
VPAR (V)
,,-
II
- ...... r\.
\\
J
rl
~
/
vi
~
TDA8145
\\
V
V
0.5
,r
TDA4950
2ms
t(ms)
V91E-W-37.
The parabolic output current IA produces a corresponding voltage drop across an external resistor
between Pin 7 and Ground (18kQ). The additional
constant current source 10 shifts the D.C. voltage
level to achieve an appropriate operating point of
the comparator. Its non-inverting input is connected
with a horizontal saw-tooth voltage. For this purpose an external capacitor is connected with Pin 8
and Ground which is discharged with the internal
current source Ie. It will be charged with the positive
26/35
flyback pulses produced in the line transformer
during the flyback time.
Due to the linear saw-tooth voltage on Pin 8 this
comparator works as a pulse-width modulator.
The output of this comparator controls the output
stage. If the output of the comparator OP2 is high,
021 and 012 are saturated. Therefore, the Darlington outPl:Jt transistor 019,020 is switched off. The
transistor 013 and the resistor R5 acts as a current
source biasing the current mirror 014, 015. The
transistor 016 is switched on.
If the output of OP2 becomes low, 012 and 021
are switched off. In this case the current in 014 and
015 dissappears and 016 is switched off. Synchronously the darlington stage 019 and 020 is saturated.
In order to achieve a fast commutation from 016 to
019/020 an active discharging of 016 is provided
with the aid of. the transistor 017.
During a normal operation range if the output current iouT is positive, only the Darlington stage (019,
020) Clnd the diode D1 are necessary to drive the
external inductor. With the aid of 016 and the
intrinsic substrate diode D4 the output current iOUT
can become negative, too; so that the modulation
range of the diode modulator becomes larger.
----------------------------~~~~@~~'lJ?~ ~--------------------------
1084
APPl.ICATION NOTE
The Zener diode Z1 serves as the voltage reference. With the aid of the diodes 02 and 03, a good
temperature compensation can be achieved.
Using an external resistor of RI = 11 kQ between
Pin 3 and Ground we get an accurate and temperature independent current reference to bias the
internal current sources.
111.3 - APPLICATION
A standard application diagram is given in Figure 39.
Pin 2 is biased from a linear saw-tooth voltage, the
resistor RIN produces the input saw-tooth current.
The non-inverting input (Pin 1) is connected with
an adjustable voltage (keystone correction). With
the aid of this trimmer, the symmetry of the parabola can be adjusted in order to correct a trapezoidal
error in the colour picture tube. A further adjustment
trimmer is responsible for the picture width and
influences only the DC-level of the comparator
input (Pin 8). (Since the discharging current sink on
Pin 8 is constant, the amplitude of the horizontal
saw-tooth voltage (Vpp) remains constant).
The thrid trimmer is in the feedback path and is
responsible for the parabola correction factor. With
the aid of this trimmer the distortion on the screen
can be changed from pillow-distortion up to an
over-correction (tu n-d istorsion).
For some applications the keystone adjustment
trimmer is not necessary (small trapezoidal error of
the picture tube). In this case, a symmetric parabola should be produced.
This can easily be obtained by AC-coupling the
input (Pin 2) as seen in Figure 38.
Figure 38: AC-coupled Vertical Saw-tooth Voltage, no Keystone (trapezoidal) Correction
CIN
--1+
RIN
V91E-W-38
Figure 39: Standard Application Diagram of TDA4950 and TDA8145
East-West amplitude
vee
o---~----~
26V
47nF
-II---;;b
12kQ
v"
-1
V91E-W·39
---------------- ~ ~ii;~~~:~e~ -~-------------27/35
1085
APPLICATION NOTE
In order to avoid any distorsion, the time constant
CIN . RINShouid be at least 10 times larger than the
time period (CIN' RIN > 10· 20ms). On the other
hand a too large time constant yields an undesired
bouncing effect in the East/West correction.
The DC voltage on Pin 1 is arbitrary.
For the sake of simplicity, connect Pin 1 with Pin 3.
Another possible application with parasitic parabola suppression is given in Figure 40.
The input current into Pin 2 is generated via the
voltage drop on RM. Due to the common mode
rejection of the input operational amplifier, the voltage change during the vertical scan time (sawtooth voltage) has nearly no effect. During the
flyback time, a positive pulse (> Vcc) is present on
Pin 1 and Pin 2. With this flyback pulse the current
limitation in the parabola generation circuit is activated and limits the parabola amplitude. Since the
flyback time is relatively long, this limitation is nec-
essary to suppress the parasitic parabola (see
chapter 1.4).
IV - TDA8146 GENERAL DESCRIPTION
IV.1 - INTRODUCTION
The TDA8146 was designed for TV and monitor
sets with various types of picture tubes, where a
programmable parabola is mandatory. The complete block diagram is shown in Figure 41.
The following features confer to this IC an ali-purpose su itability :
'- programmable parabolic current generator
- parasitic parabola suppression during vertical
flyback
- output sink current up to 800mA and source
current up to 100mA
- vertical current sense inputs ground compatible
Figure 40: Application of TDA4950 and TDA8145 with Parasitic Parabola Suppression
vee
RI
Deflection
unit
V91E·W·40
28/35
---=------------------------~~i~@~gL~~R~~
1086
----------------------------
APPLICATION NOTE
Figure 41: Block Diagram
OUT
c
IGND
PW
Z
GND
IREF
V91E-W-41
IV.2 - INPUT AMPLIFIER AND RECTIFIER
The input circuitry (Figure 42) is designed for a common mode range up to 12V.
Figure 42: Input and Rectifier Principle Diagram
V91E-W-42
The voltage drop on R1 gives on IGND (Pin 3) : VR1
= R1 ·IREF
The operational amplifier OP regulates the current through R2, thus:
IR2 = (VR1 - VIN) / R2 = (R1 . IREF - VIN) / R2
29/35
--------------- ~ ~~~~~gu~~~~t~ ---------------
1087
APPLICATION NOTE
IRP=~=80).lA
For VIN > 0, we note the output current of the input
amplifier IN :
10·10-
IN = IREF - IR2 = IREF - (Rl . IREF - VIN) I R2
For VIN < 0, we note the output current of the input
amplifier Ip :
Ip = IR2 - IREF = (Rl . IREF - VIN) IR2 - IREF
The rectifier is formed by 02, 03 and 04. For
VIN > 0, IN flows through 02 to the rectifier output,
thus IR = IN.
For VIN < 0, Ip flows through 03 from Vs into the
output of the input amplifier. 04 reflects the Ip
current, thus the rectifier output currrent will be
IR = IPM = Ip.
If the sign convention of IR is considered, we have:
IR = 1(R1 . IR;( -
VIN)
IREF 1= IIREF (~~ - 1
)+ ~I~ 1
IV.3 - VERTICAL CLAMPING
To avoid the parasitic parabola during the vertical
flyback time a vertical clamp circuit was used.
The vertical clamping principle is presented in Figure 43.
The rectified sawtooth current IR Flows through 02
to the output.
When V goes over Vs, 01 switches off and 02 on.
IREF flows now through 01 to the output and IR
through 02 to the ground. IRC = IREF is now the
clamped value of the output current.
IV.4 - REFERENCE AND STARTING CIRCUIT
Figure 44 presents the complete voltage and current reference circuitry.
In our case, Rl = R2 = 1OkQ and IREF = 120).lA
Thus, IR =
I~I~ I
If VIN is a symmetrical saw-tooth with GND as the
average value and 1.6 V peak'le-peak, the rectified
peak current will be :
The reference current is IREF = 1~'~:n = 82).lA
To guarantee the start of the device, it is necessary
to choose the value of the resistor R5 in order to
have a minimum current of 56).lA.
Figure 43 :- Vertical Clamping Principle Diagram
Reclified
Sawtooth
CUrrent
IR
j-~-~~~
Rectified and Clamped
I RC
'"':~.
Sawtooth Current
' - - - - - - - i - - 0 I RC
V91E-W·43
30/35
--------~------------------~~i~©~~~:~~
1088
----------------------------
APPLICATION NOTE
Figure 44: Reference and Starting Circuit
T1
Current Reference
R5
100kO
V91E-W-44
IV.5 - PARABOLA GENERATOR
Figure 45 presents the simplified circuit diagram of the parabola generator.
Figure 45: Parabola Generation
Parabolic Output
Current
PAR
Note:
12
• It is possible 10 replace the ~witches S4 and S5 by this configuration in order to have a
continuous shape variations.
V91E-W-45
1089
APPLICATION NOTE
The parabolic behaviour of the parabola output
current is obtained via piecewise linear approximation.
Two external pins permit an external adjustment of
the parabola shape (these pins can be connected
to ground or to resistors).
The parabolic output current on Pin 12 Produces a
corresponding voltage drop across an external resistor between Pin 12 and ground.
As it can be seen in Figure 46 the parabola can be
corrected in the following limits:
VC5/VC = K5 = 1.07 with Pin 5 to GND
VC4/VC = K4 = 1.17 with Pins 4 and 5 to GND
Figure 46: Parabola Correction
VF
during
fly back
--I-----I~---I----t-------_t--
-O.8V
-O.6V
·O.3V
V SE
+O.8V
V91E-W-46
An application specific correction can be thus obtained for various picture tube types.
IV.6 - PULSE-WIDTH MODULATOR AND OUTPUT
The simplified diagram of the pulse-width modulator and output is presented in Figure 47.
Figure 47: Pulse-width Modulator and Output
C
PAR
11
Q60
I-----<~_j
7
OUT
V91E·W-47
32/35
~~--------------------------~~~~~~~~:~~
1090
-----------------------------
APPLICATION NOTE
The non-inverting input of the comparator (Pin 11)
is connected to a horizontal saw-tooth voltage. An
external capacitor connected on Pin 11 is charged
during the flyback time and then discharged by the
internal current source generating the saw-tooth
voltage.
Due to the linear saw-tooth voltage on Pin 11, the
comparator works as a pulse-width modulator. The
output of this comparator controls the output stage.
If the output of the comparator is high, 067 and
064 are saturated. The Darlington output configuration 065/066 is switched off. 062 acts together
with R53 as a current source, biasing the current
mirror 058/059. The transistor 060 is switched on.
If the output of the comparator becomes low, 064
and 067 are switched off. The current through
058/059 disappears and 060 is switched off. Synchronously the Darlington stage 065/066 is saturated. In order to achieve a fast commutation, an
active discharging of the 060 base charge is provided with the aid of 063.
IV.7 - APPLICATION
An application diagram is presented in Figure 48.
The internal Zener configuration on Pin 9 can be
useful in certain application.
Figure 48: Application Diagram
+27V
~
1U
>Om"
Todiode
modulator
• Note: depending on flyback voltage
V91E-W-48
33/35
1091
APPLICATION NOTE
v - TDA8147 GENERAL DESCRIPTION
V.1 - INTRODUCTION
The TDA8147 was designed as an interface Ie
between the digital circuitry and the diode modula-
tor in digital chassis. The complete block diagram
is shown in Figure 49.
Figure 49: TDA8147 Block Diagram
.
PW
: modulated
. Parabola
Jl
H
Pinning for 8 + 8 OIL package
V.2 - INPUT AMPLIFIER
V91E·W-49
Figure 50: Input Amplifier
The pUlse-width modulator of the TDA814 7 is working with input voltages from 1V to 23V. To have the
same range for the parabola voltage an input amplifier is necessary. Digital TV sets deliver an analog parabola or a PWM-signal with small amplitude
(2V to 3V).
AMP
6
An additional signal ground (SGND Pin) separates
the digital ground from the deflection circuit ground.
The internal feedback loop of the amplifier gives a
voltage gain
Av = 1~.5 + 1 = 4.5 (see Figure 50)
SGND
V91E-W-50
34/35
~~~~~~~~~~~~~--~~~i@~~~~~~~~ ~~~~~~~~~~~~~--
1092
APPLICATION NOTE
V.3 - VOLTAGE REFERENCE AND STARTING
CIRCUIT
graph IV.6 for explanation.
The voltage reference and starting circuit have the
same configuration as for the TDA8146 (see paragraph IV.4).
V.5 - APPLICATION
V.4 - PWM MODULATOR AND OUTPUT
The PWM modulator (Figure 51) has the same
configuration as for the TDA8146. So see para-
A Standard application diagram is given in Figure 51.
Since all the adjustment of the parabola are made
by the digital processor, only the feedback loop of
the PWM modulator must be carefully designed.
The TDA8147 is well-suited for new TV concepts
with 32kHz line frequency.
Figure 51 : Application Diagram
pw
modulated
Parabola
Pinning for 8 + 8 OIL package
V91E-W·51
---------------
~ ~~~~m~mc~~~~
--------------35/35
1093
APPLICATION NOTE
TEA2028-2029
By : J-M.MERVAL I B. O'HALLUIN
SUMMARY
Page
TEA2028
GENERAL DESCRIPTION
4
II
MAIN FUNCTIONS . . . .
4
III
PIN CONNECTION (TEA 2028 B)
5
IV
INTERNAL BLOCK DIAGRAM ..
6
V
FUNCTIONAL DESCRIPTION ..
7
V.1
V.1.1
V.1.1.1
V.1.2
INTERNAL VOLTAGE AND CURRENT REFERENCES
1.26 V voltage reference
Generator block diagram ..
Current reference . . . . . .
7
V.2
V.2.1
V.2.1.1
V.2.2
LINE SYNC. EXTRACTION .
Black level locking . . . . . .
Application. . . . . .
Memorizing the sync pulse 50% value
V.2.2.1
Ic R'
.
TO
alia ca Icu Iallan
V.2.3
Sync pulse detection
V.3
V.3.1
V.3.2
V.3.2.1
V.3.2.2
V.3.2.3
V.3.2.4
V.3.3
V.3.3.1
V.3.3.2
V.3.3.3
V.3.3.3.a
V.3.3.3.b
V.3.3.3.c
V.3.3.3.d
V.3.3.3.e
V.3.3.3.f
V.3.4
V.3.5
V.3.5.1
FIRST PHASE LOCKED-LOOP STAGE "cj>1" .
Phase locked-loop "cj>1" block diagram
Functional duty of individual blocks
Phase comparator . . . . .
Low-pass filter . . . . . . . . .
VCO centered on 500 kHz . . .
Divider stage . . . '.' . . . . .
Functional description of building blocks
Phase comparator "cj>1" . . . . . . .
Low-pass filter . . . . . . . . . . .
VCO (Voltage Controlled Oscillator)
503 kHz Ceramic Filter. . . . . . .
Simplified Block Diagram of VCO .
Characteristics of the External Filter .
Study of the Internal Amplifier . . . .
Characteristics of the non-linear Amplifier "A4" .
Voltage-frequency transfer characteristics of VCO
"cj> 1" time constant switching .
Video identification stage
Block diagram . . . . . .
AN407/0591
7
7
7
7
8
9
9
. . . . . . . . . .
10
........ .
10
11
12
12
12
12
12
12
12
12
13
14
14
15
16
16
18
18
18
18
19
1/55
1095
APPLICATION NOTE
SUMMARY (continued)
Page
19
19
V.3.6
Characteristics of loop <\>1
V.3.6.1
Locking accuracy .
V.3.6.2
Dynamic study . . . .
V.3.6.2.a
Long time constant ..
V.3.6.2.b
Short time constant .
V.3.7
Phase comparator inhibition.
20
21
21
21
V.4
22
LINE SAW-TOOTH GENERATOR
V.5
SECOND PHASE LOCKED LOOP "<\>2" .
Duty of different building blocks .
V.5.1
V.5.1.1
"<\>2" phase comparator .
V.5.1.2
Low-pass filter . .
Phase modulator.
V.5.1.3
Flip-flop . . . . .
V.5.1.4
Output stage . . .
V.5.1.5
Line deflection stage .
V.5.1.6
Operation of building blocks.
V.5.2
Phase comparator "<\>2" .
V.5.2.1
Low-pass filter f(p) . . . .
V.5.2.2
Phase modulator. . . . .
V.5.2.3
Line flip-flop (TEA 2028 only)
V.5.2.4
Block Diagram .
V.5.2.4.a
T10 Calculation
V.5.2.4.b
16 ms Window .
V.5.2.4.c
Auto-set to "1" .
V.5.2.4.d
Maximum "T1 0" value as a function of "C1"
V.5.2.4.e
Line output stage & inhibitions .
V.5.2.5
Inhibition at start-up . . . .
V.5.2.5.a
Inhibition during line flyback
V.5.2.5.b
Safety inhibition . . . .
V.5.2.5.c
Line deflection stage . . . .
V.5.2.6
Characteristics of loop "<\>2" . .
V.5.3
Study of the static error . .
V.5.3.1
Phase shift error in case of no adjustment.
V.5.3.1.a
Study of shift adjustment. . . . . . . . .
V.5.3.1.b
23
23
23
23
23
24
24
24
24
24
24
25
25
26
26
26
26
26
27
27
27
27
27
30
30
30
30
VERTICAL DEFLECTION DRIVER STAGE
V.6
V.6.1
Frame sync extraction . . . . .
V.6.2
Frame saw-tooth generator . . . .
V.6.2.1
60 Hz standard switching . . .
V.6.3
Functions of frame logic block . . .
V.6.3.1
50/60 Hz standard recognition .
V.6.3.1.a
50 Hz Standard Recognition ..
V.6.3.1.b
60 Hz Standard Recognition ..
V.6.3.2
Vertical synchronization window - Free-running period
V.6.3.3
Frame blanking signal . . . . . . . . . . . . .
V.6.3.4
Frame blanking safety (TEA 2028 only) . . . .
31
32
32
33
33
V.7
V.7.1
V.7.2
V.7.3
V.7.4
37
37
38
38
2/55
SWITCHING POWER SUPPLY DRIVER STAGE
Power supply block diagram . . . . . . . . . .
General operating principles . . . . . . . . . .
Electrical characteristics of the internal regulation
Power supply soft-start . . . . . . . . . . . . .
.
.
loop
. . .
---------------------------~~ii@~~~~g~
1096
34
34
34
34
36
36
39
---------------------------
APPLICATION NOTE
SUMMARY (continued)
V.7.5
V.7.6
V.7.6.1
V.7.6.2
Page
Protection features . . . . . . . . . . . .
TV Power supply in standby mode . . . .
Regulation by primary controller circuit
Regulation by TEA 2028 . . . .
40
MISCELLANEOUS FUNCTIONS . . . . .
Super sand castle signal generator . . . .
Video and 50/60 Hz standard recognition output
41
41
41
42
42
42
TEA2028 APPLICATION DIAGRAM . . . . . .
43
VII
VI1.1
TEA2029 : DIFFERENCES WITH TEA2028
44
GENERAL . . . "
VI1.2
PIN BY PIN DIFFERENCES
VI1.3
TEA 2029C PIN CONNEXTIONS .
44
44
45
. V.8
V.8.1
V.8.2
VI
TEA2029
....... .
.. .
46
47
VII.4
FRAME PHASE MODULATOR .
VII.5
VI1.6
FRAME BLANKING SAFETY .
ON-CHIP LINE FLIP-FLOP . . .
VI1.7
AGC KEY PULSE . . . . . . . .
VIII
APPLICATION INFORMATION ON FRAME SCANNING
IN SWITCHED MODE (TEA2029 ONLY) .
VIII. 1
VII 1.2
FUNDAMENTALS ..
GENERAL DESCRIPTION . . . . . . . . . . . . . . . .
49
49
49
VII 1.3
TYPICAL FRAME MODULATOR AND FRAME OUTPUT WAVEFORMS
50
VIII.4
FRAME POWER STAGE WAVEFORMS.
VII 1.5
VII 1.6
V1I1.6.1
VII1.6.1.1
VII1.6.1.2
VII1.6.1.3
V1I1.6.2
V1I1.6.3
FRAME FLYBACK . . . . . . . . . . . .
FEED-BACK CIRCUIT . . . . . . . . . .
Frame power in quasi-bridge configuration
Choice of "r" value . . . . . . . . . . .
Influence of r3 value . . . . . . . . . .
"S" Correction circuit in quasi-bridge configuration
Frame scanning in switched mode using coupling capacitor
Frame safety . . . . . . . . . . . . . . . . . . . . . . . .
50
51
VII 1.7
V1I1.7.1
FRAME SCANNING IN CLASS B (WITH FLYBACK GENERATOR) .
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
54
54
54
IX
TEA2029 APPLICATION DIAGRAM
COMPLETE APPLICATION WITH TEA2164 .
55
48
48
52
52
52
52
53
53
3/55
------------- ~ ~~~.;mg~l~.~~ -------------
1097
APPLICATION NOTE
I - GENERAL DESCRIPTION
As depicted in figure below, the TEA2028 combines
3 major functions of a TV set as follows:
- Horizontal (line) and vertical (frame) time base
generation for spot deviation. The video signal is
used for the synchronization of both time bases.
- On-chip switching power supply controller synchronized on line frequency.
Figure 1
Miscellaneous
Power Supplies
Horizontal
Power Amp.
1-------'
oen
~
co
N
o
N
Miscel!aneous
Power Suplies
This integrated circuit has been implemented in
bipolar 12L technology, and various functions are
digitally processed. In fact, resorting to logic fu nctions has the advantage of working with pure and
accurate signals while full benefit is drawn from
high integration of logic gates (approx. 110 gates
per mm2 ).
The main objective is to drive all functions using an
accurate time base generated by a master 500 kHz
oscillator.
Also, horizontal and vertical time bases, are obtained by binary division of reference frequency.
This has the advantage of eliminating the 2 adjustments which were necessary in former devices.
One section of this integrated circuit is designed to
drive a switching power supply of recent implementation called "master-slave". Switching takes place
on the primary side (i.e., directly on mains) of a
transformer. The device ensures SMPS Control,
Start-up and Protection functions. Control signals
go through a small pulse transformer thereby providing full isolation from mains supply.
This new approach fully eliminates the bulky mains
transformers used in the past. In addition, it offers
Z
<{
Oi
optimized power consumption and reduction of TV
cost-price.
" - MAIN FUNCTIONS
- Detection and extraction of line and frame synchronization pulses from the composite video
signal.
- Horizontal scanning control and synchronization
by two phase-locked loop devices.
- Video identification.
- 50 or 60Hz standard recognition for vertical scanning.
- Generation of a self-synchroriized frame sawtooth for 50/60Hz standards.
- Line time constant switching for VCR operation
through an input labeled "VCR" (Video Cassette
Recorder).
- Control and regulation of a primary-connected
switching power supply by on-chip controller device combining:
• an error amplifier
• a pulse width modulator synchronized on line
frequency
• a start-up and protection system
4/55
--------------~ ~~~~;mW~l~9c~ ---------------
1098
APPLICATION NOTE
- Overall TV set protection input
- Frame blanking and super sandcastle output signals
Frame blanking safety input for CRT protection
in case of vertical stage failure.
III - PIN CONNECTION (TEA2028B)
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Horizontal output monostable capacitor
Frame blanking safety input
Frame saw-tooth output
Frame blanking output
Frame ramp generator
Power ground
SMPS control output
Supply voltage (Vee)
SMPS regulation input
Horizontal output
Super-sandcastle output
Horizontal fly back input
Horizontal saw-tooth generator
Current reference
SMPS soft-start and safety time constant capacitor
«>2 phase comparator capacitor (and horizontal phase adjustment)
Veo phase shift network
Vcooutput
Veo input
Frame sync time constant adjustment capacitor
Substrate Ground
»
5:
@~
~C!»
VCR Switching
Input
~""
'"'6
~~
~cn
,~~
+135V
.4.7k!J:
2.2~F
50/60 Hz
Video Standard
Identification
OutPut
2.7Mn
~
»
2
'"
o
'"CD
N
!'i:(I)
0
0
~
I
"tJ
-I
m
Z
3.J2kil, 1 %
»
"tJ
-I
APPLICATION NOTE
V. FUNCTIONAL DESCRIPTION
Majority of the on-chip analog functions were computer simulated and results such as temperature
variation, technological characteristic dispersion
and stability, have led to the enhancement and
implementation of actually employed structures. A
parallel in-depth study of the device implemented
in form of integrated sub-sections is provided to
analyze the overall performance in a TV set.
V.1 -Internal voltage and current references
V.1.1 - 1.26V Voltage reference
For optimum operation of the device, an accurate
and temperature-stable voltage generator independent from Vec variations is used (Band-gap
type generator).
The generated 1.26 V is particularly used as reference setting on input comparators.
V.1.1.1 - Generator block diagram
In practice, maximum drift due to temperature can
be +0.23 mVfC
i.e., ± 1.5 % for a L'.T of BOoC.
V.1.2 - Current reference
This is implemented using the 1.26V generator in
combination with an external resistor.
Figure 4
1re f
VBE1
1.26V
t
tI
Rex!
I
Band Gap
.3.32 kn, 1 %
____________ .J
Figure 3
IREF = 114
= V14
= 1.26 + VSEI - VSE2
REXT
Let's 114
REXT
= I and VSEI = VBE2
then: IREF
= R1 .26 = 3BOllA
EXT
91 AN2028/29-04
Thus, it follows that IREF is accurate and independent of both Vcc and temperature.
A set of current generators proportional to IREF
current are used in various circuit blocks.
V.2 - Line sync. extraction
with 'A = K· T = 25.7mV at +25'C
q
d'A = 1:<. = +0 OB6mVrC
dT q
.
dVBE = VBE(25') - 1.26 = -2mV/oC
dT
T
If A'A = 1.26 - VSE
Then: Vo = 1 .26V (temperature-independent)
Horizontal and vertical time bases should be synchronized with corresponding sync. pulses transmitted inside the infra-black portion of video signal.
The duty. of this stage is to extract these sync
pulses. The output signal, called composite sync,
contains the vertical sync which is transmitted by
simple inversion of line sync. pulses.
The vertical sync pulse is then extracted from this
composite signal.
7/55
- - - - - - - - - - - - - - ~ ~~;~~)~~~~~~~ - - - - - - - - - - - - - 1101
APPLICATION NOTE
Figure 5
Video
Input
Signal
Composite Sync.
Output Signal
I ...
~I
I__ Frame Sync.
91AN2028/29·05
The main advantage of this arrangement is its
ability to operate at video input signal levels falling
within 0.2V to 3V peak-to-peak range and at any
average value.
The operating principle is to lock the black level of
the input signal (pin 27) ontointernaly fixed voltage
(VN) and then memorize the average voltage of the
sync pulse by using an integrating capacitor connected to pin 26.
.
Finally, the composite sync signal is delivered. by a
comparator the inputs of which are driven by V50%
and video signals.
V.2.1 - Black level locking
Figure 6
V
S1
n-
Vp
:..d ~
.-------+-....
V
Vpp~~
Video
VN = 2V
1\
1\
I \
I
I
I
~..JL
C27
91 AN2028/29·06
The video signal is applied to pin 27 through the
coupling capacitor "C27". Since the sync pulse
amplitude is generally equal to 1'/3 of Vpp (i.e. 66mV
to 1V) and in order to obtain a good precision of the
black level, the sync pulse should be amplified by
a coefficient of - 14 before being applied to the
comparator "Ct". This comparator will charge the
8/55
"C27" capacitor as long as VS1 > VN. VS1 will
stabilize at VN during the line flyback interval "T,' if
the average charge of "C27" capacitor is nil for one
TH period.
IcllD is calculated such that the locking occurs at
the middle of the back porch.
---------------~~~~@~g~~i~
1102
---------------
APPLICATION NOTE
Figure 7
VN (2V)~f----:~.!..f-+------===~--,------
Ie
I
~~~~-------~~---.~~==
-5!JA ~
___
• I
91 AN2028/29-07
The to. VS1 produced by 10 during the line trace which
is:
must be equal to b.VS1 during the time interval "t1 ",
i.e. :
It follows that:
with respect to VN = 2V at the beginning of retrace
time
- Due to transposition on amplifier stage, the black
level voltage on pin 27 is equal to 2V.
- In practice, at low amplitude video signals, it is
recommended to insert a low-pass filter before
the "C27" capacitor so as to attenuate the chrominance sub-carrier and the noise components.
The aim is to reduce the phase variations of the
detected sync pulse and thus enhance the horizontal scanning stability.
Figure 8
substituting T H = 64 fls, tr = 12 fls, ts = 4.7 fls (which
are standard and constant values) into above
.
Ic = 62
equatIOn:
J;;
. 3
,,
~~~-CJ-4r_2~20~
Chroma
Burst
V.2.1.1 - Application
Atle = 5flA ==> 10 = 31 flA
- With C27 = 220nF, b.Vs will be
14x
5 x 52
220
= 16 mV
whieh yields 0.8 % maximum error in black level
~.100 pF
WE
,I
91AN2028/29-08
V.2.2 - Memorizing the sync pulse 50% value
The objective is to memorize the voltage corresponding to 50 % of the line sync pulse VS1 by using
an external capacitor connected to pin 26.
----------------~~~~~~~TI~~g~
9/55
---------------------1103
APPLICATION NOTE
Figure 9
v~c
"~:lJ
VN + Vo
--
1
0
1
'. b.
1
I
,
1
A
V
2R
50%1
11
,.'."b;:--;t' ! b.
1
t
VS1 + vo
r
A
I
~~
C26
}N
1
o
V26!
.
I
10:
I
!
i
V50% ::::::l;7" 1
1
1
1
1
1
F1
1
1
1
1
1
I
The overall arrangement comprises two comparators.
- Comparator C2 : delivers an output voltage "V1"
by comparing VS1 + Vo, V26 and the voltage drop
across two resistors.
- Comparator C3 : which delivers a constant output
current thereby maintaining on capacitor "C26",
the voltage V50% corresponding to 50% of peak
to peak sync pulse.
During the line scanning, diode "D" is reverse biased : VS1 + Vo = V1 < V26 and C3 will deliver a
current 10 which will discharge the capacitor.
During sync pulse interval, VS1 + Vo = Vp + Vo,
diode "D" begins conducting and thus:
V1 = (Vp + Vo) - (2 R il). Since the capacitor has
been slightly discharged ~ V1 > V26, comparator
C3 begins charging the capacitor until C2 is
brought to equilibrium. At this time,
I
i h
. V26 - Vo - VN
1 ="2 w ere I =
R
i
.
thus V1 = Vp + Vo - 2R"2 = Vp+ VN + 2Vo - V26
10/55
.. t
== ...
t
91 AN2028/29-09
VP+VN
and V1 = V26 ~ V26 = - - 2 - + Vo = V50%
A high value C26 capacitor will thus memorize the
voltage level corresponding to 50% of the line sync.
pulse.
V.2.2.1 -
~
Ratio calculation
During the line scanning period (TH - Ts), the
capacitor C26 will loose a charge equivalent to :
10 (TH - Ts).
This energy must be recovered before the end of
sync pulse such that: Ic· ts > 10 (TH - Ts)
Ic TH - ts
Ic
therefore J;; > - t s J;; > 12.6
In practice, for C26 = 100nF, 10 = 251lA and
Ic = 800llA
V.2.3 - Sync pulse detection
. This function is fulfilled by comparing the inverted
video signal (VS1 + Vo) whose black level is con. stant at 2V, with the sync 50% voltage level on pin
26.
---------------------------~~~i@~~~~~~~ ~-------------------------1104
APPLICATION NOTE
Figure 10
JL
Frame Sync.
Separator
V50%
26.f------{
I
V;'''V
- ____ r I
~
LS
tc::.T
I
250 ns
I
~
./"""-+-___
LS O--C::J---{
-- lJlJ
Line Sync. Output
toward Phase Comparator 'l'1
Comparator C4will deliver the line sync pulse (LS)
which will be used for 3 functions:
- Horizontal scanning frequency locking: output to
$1 phase comparator.
~
LS
On video
C Recognition Output
91AN2028/29·10
75dB, i.e. 15 to 20dB better than other sync processors.
- Detecting the presence of a video signal at circuit
input.
V.3 - First phase locked-loop stage "$1"
This stage is commonly called the first Phase
Locked-Loop "$1 ".
Its duty is to lock. the frequency and the phase of
the horizontal time base with respect to the line
sync signal.
The LS signal in two latter functions is filtered for
noise by using combination of current generator I
and a zener diode equivalent to a capacitor.
Using this extraction technique at a very noisy
video signal yields remarkable display stability.
The device also provides for scanning synchronization at aerial signal attenuation of approximately
In the absence of transmission (i.e. lack of line
sync), the horizontal scanning frequency is obtained by dividing the output frequency of a VCO
device. This VCO oscillates at approximately
500kHz and uses a low frequency drift ceramic
resonator. This method eliminates the need of horizontal frequency adjustment.
- Frame sync extraction for vertical scanning synchronization.
11/55
--------------- ~ ~i~~mg~~Ii~E~ ---------------
1105
APPLICATION NOTE
V.3.1 - Phase locked-loop "(j>1" block diagram
Figure 11
,..-----------,
I
I
I Phase Comparator
I
~~INI
A
Ii
i
I
~~
I
i
I
I
i:
I'-_ _ _ _ _ _ _ _ _ _ ...JI
Low·pass
Filter 1--_ _ _---,
F(p)
~ -~OUT
By-32·Divider
Stages
\0.2. 1 - Phase comparator
The duty of this comparator is to issue an output
current proportional to the phase difference between (j>IN and (j>OUT.
V.3.2.2 - Low-pass filter
This filter suppresses the parasitic component containing the sum of phases, smoothens the phase
difference component and determines the timing
characteristics of the loop.
V.3.2.3 - VCO centered on 500kHz
B (kHz/V)
o
Horizonlal
Frequency
V.3.2 - Functional duty of individual blocks
V.C.O.
<01
Ceramic Resonator
91AN2028!29·11
This is a voltage-controlled oscillator which generates an output frequency proportional to the voltage applied to its input.
This voltage is delivered by low-pass filter.
V.3.2.4 - Divider stage
It is used to divide the VCO frequency (500kHz) by
32 so that it can be compared with the line sync
signal frequency of 15625Hz.
\/'.3.3 - Functional description of building blocks
V. 3.3.1 - Phase comparator '\j) 1"
Figure 12
40UT
V'Pt Signal
I
I
I
26~
1.26V
1..
41N
I
I
Video Recognition
_
Mute
-0
2!
1mA
_.
LS~
~:
VCR~l"
~
Long !.pi Inhibition
VCR Mode
SwitchinQ
The comparator is functionally equivalent to a signal multiplier.
12/55
------------------------------~ ~i~~~~~:~~~
1106
91 AN2028!29·12
APPLICATION NOTE
.
Let's assume that:
iLS = I sin (OOHt + !\lIN)
and V~1 = k cos (OOHt + !\lOUT)
then:
IAV
t-.t
TH
= 21TH and t-.t =t-.~
The comparator conversion gain is thus:
iLS' k [ sm¢IN
.
'"
. 2ooHt + ""IN
'" + out) ]
I. = -2- ""out)
+ sln(
A =.i.- =J. (inNrd)
M) 1t
Figure 13
Later in our discussion we shall consider the two
possible values of the current I.
For the time being, let's define these values as
follows:
\
,
/
- I = SOOIlA for "long time constant" or normal
operation
- I = 1.SmA for "short time constant" VCR mode or
synchronization search (Mute).
I
"' .... _-",,,,/
The values of A are therefore:
- ALONG = 0.16 mAird
+1H-~-I
o~~--~~------~~----~
-1
..
91AN2028/29-13
- the low-pass filter will suppress the 2fH frequency
component
- !\lIN - !\lOUT difference being low:
sin (!\lIN - !\lOUT) ~ !\lIN - !\lOUT
- the output current will be therefore proportional to
the phase difference between the signals compared.
In other words, the average current over one period
is:
iAV
x TH = I
(~+I'.t)-I (~- t-.t)= 21 t-.t
- ASHORT = 0.47 mAird
Use of comparator inhibition signal is quite useful
under noisy transmission conditions. It eliminates
risk of incorrect comparison during the line scanning phase which would be due to the noise present
on LS signal. Horizontal phase and image stability
are thus highly enhanced.
Characteristics of this inhibition signal will be discussed at the end of. this chapter.
\1.3.3.2 - Low-pass filter
- Its main function is to reject the 2fH (31 kHz)
frequency component delivered by the phase
comparator.
- It also defines the characteristics of the loop in
transient mode.
The filter is built around two sub-sections which
determine the stability and the response time of the
loop in the following modes of transmission:
- Normal or VCR modes. See section V.3.6 "Dynamic study of 12 =--.
1+J
and Z = R1 + ~C «
JOO
19 input resistance
= 500kHz)
R~ i ~ il
Figure 22
R1
;18
;2
=?
;1
t
R
Z
V18
!'-!
.,
12
!'-!
91 AN2028129-22
R1 C1 network produces -45° phase lag of "i" with
respect to "i2", around 500kHz.
dr : dynamic resistance =
-
i1 AND ;2 calculation as a function of
pin 19
..
VS1
Rc 1200
- A1 Ampllfler:-=-=--=21
Vln dr1
57
"Vin"
on
A2 A
~
~
i2
1
1
I'f'
mp I ler : VS2 = 2dr2 = 54
i2
VS1 i2
= - x - = 0.395
VIN VIN VS1
-7
.
12 = 0.39 VIN
• i2 is in phase with VIN therefore:
i3 = -i2 = -0.39 VIN
16/55
---------------------------~~~~i~~~~g~ ----------------------------
1110
APPLICATION NOTE
Figure 23 : Vector representation of V18IVIN
Figure 25 : Vc = F(V22)
Vc(mV)
VOUT phase variation = f (V c)
/
VIN
V1s @il(max)
Ril
-R(i1 +12l
--~----~~~~~--
91 AN2028/29-25
91 AN2028/29-23
Figure 26 : 122 = F(V22)
- A3 Amplifier:
i1
= i3 -
(~~ + ~ ) = -
0.39
VIN (
122(~)
-4~c + ~)
0.7
"VIN" always leads the "iJ" by 180, only the amplitude of i1 is a function of Vc (See figure 23).
0.6
0.55 ------
VOUT =-R h(1 +jR1C1f1l)+i2
VIN
1 + J(R1 + R)CWl
i1 = - 0.39 VIN
(~- ~~
0.5
di22
j
-dV 22 ",33 MD.
1
dV 22 ""
_
:
820 kQ
:
di l2
0.4 +-~-Ll-'~--:",....::V2.2 (V)
5.6 6
6.5
and i2 = 0.39 VIN
91 AN2028/29-26
The following figure 24 illustrates the characteristics of V181VIN phase versus Vc.
- Phase variation determined by Vc falls between
+240 and +1350 range
- The gain is higher than 10 dB. The pin 18 output
signal of 30 to 40 dB has a rectangular component (See figure 24).
e. - Characteristics of the non-linear Amplifier "A4"
This is a differential amplifier whose equivalent
feed-back resistors of emitters vary as a function of
its input Voltage.
The maximum output voltage swing is set by two
"clamp" diodes connected to "V22" input.
f. - Voltage-frequency transfer characteristics of
VCO
The transfer characteristic is linear and centered at
5.6Vat 500kHz operating frequency.
- T transfer
= :~ =22.4kHzlV
and once it goes
through five divide-by-two stages:
T= 22.4 = 0.7kHzlV
32
Figure 24
V"
20Iog-(dB)
V,N
0
t--
~
A
~~
~ )'--...
+ 10 0
0
+2
~
•
a
/
/
+ 40
+ 30
+ 20
t-
- 150
-100
---------------
50
20
0
+20
~ ~~~;;1tlg~~~~~
+50;r
Vc (mV)
+100
91 AN202B/29-24
17/55
---------------
1111
APPLICATION NOTE
Figure 27
'N
520
518kHz /
:I:
,:0
V
13z
J-
w
gsa
0 -- w
I
u.
~
/
z
a:
48
T = 22.4 kHzIV
I
a:
or-V
I
I
I
,
I
I
5
5.68 6
7
PIN 22 VOLTAGE "V2i' (V)
91AN2028/29-27
V, 3.4, - "<1>1" time constant switching
When switching between stations or receiving signal via a VCR, the loop locking interval must be as
short as possible so as to avoid unwanted visible
effect on the picture, In fact, since the synchronization between the VCR motor drive and the playback head is rather imperfect, it will produce frequency and phase fluctuations in the output composite video signal. Under these conditions, phase
locking interval must be "short" (VCR Mode),
In the case of broadcast transmission, this loop
must also filter all pliase variations produced by
noisy sync signal. In this case, its locking time
constant must be "long" (normal mode).
18/55
In other "jungle" circuits, this time constant switching is carried out by capacitor switching within the
filter loop. In our case, this function is achieved by
changing the current amplitude of the phase comparator.
This a.mplitude changing modifies the open-loop
system gain and therefore the damping coefficient
and the locking time constant.
The device will be in short time constant mode
under the following two conditions:
- VCR Mode or SCART Connector Mode:
This mode is enabled by a low state on pin 23.
V23 < 2.1 V.
- Transmitter search and tunning.
In order to accelerate the capture, a "Video Identification" stage will detect the presence or the
absence of a video signal on input pin 27, and
deliver accordingly a signal called "Mute".
V.3.5 - Video identification stage
This stage will detect the coincidence between the
line sync pulse (if present) and a 2f.ls pulse issued
from the logic block. This 2f.ls pulse at line frequency is positionned at the center of line sync
pulse when the first loop " 1
The recognition time "Tr" is adjustable by an external capacitor, as soon as q>1 is locked:
Let's study the phase error "q>OUT - q>IN" under
steady state conditions:
The open-loop gain is :
_ T(p) _ AB I(p)
- IC25(Av)
~
= Ic x 64 I-1s
\1.3.6.1 - Locking accuracy
-
and:
VH
5
- T R = C25 x -I- - = 1.96 x 10 X C25
C25(AV)
- with C25 = 4.7 nF => Tr = 1 ms (which is clearly
quite last)
Figure 29
IN - q>OUT)
p-.O
with Video
- The closed-loop gain is :
_H
_ ~ _ ABI(p) _ cPOUT(p)
(p) - 1 + T(p) - P + ABI(p) - cPIN(P)
I
I
I
iC(25)
_ I( ) - R x
1 + "t1P
P (1 + "t2P) (1 + "C3P)
Where:
• R = Dynamic input resistance 01 VCO.
II a phase step 01 /lq> is applied to the input, the
following would be obtained as a function 01 (p) :
M>
cPIN(p)=-
P
2J.lS~
iC(25)
I
Where:
• A = 0.16 mAird (long time constant)
• A = 0.47 mAird (short time constant)
• B = 0.7 kHzlV or B = 4.4 103 rdls
I
: without Video
I
that is : limp (cPIN - cPOUT)
p-.o
Mute.
outPUo~ .!---I--!------lI~
. =ff o.~
VHYST=
VL VH
4.6 V
V25
= lim
p->O
'A:I(O) --; 0
P+
It is therefore deduced that the system can lollow
all input phase variations without producing any
.
static error.
In practice, there will be a slight error due to the
input bias current "IB" 01 VCO, which is 0.551-1A at
fa = 500kHz. This DC current is delivered by a
phase comparator which will generate a phase
error 01 :
---------------~~~i~~~M~~~~
19/55
--------------1113
APPLICATION NOTE
- long time constant:
L1 M = 5.5kHz//ls R = 500kQ
- short time constant:
IB
L1O
p->O P +
L1m
A8f()
0
L1m
= A8R
where R = 500KQ at f(o)
In this case, the phase error depends on both, the
magnitude of the frequency step and the static gain
A8R.
In general,
L1m = A8R = 21tL1f = A . 21t . 8' . R
L1 L1t = A8'R x T H (8' In kHz/V)
~: which is the open-loop static gain, is
taken into consideration.
• In VCR mode: ASHORT
L1f
=> L1t = 16.5kHzI/ls
= 0.47 mAlrd
Note : The capture range is specified within
Hz with respect to 15625 Hz.
± 500
Numerical Example
Let's suppose that in VCR mode there is a frequency variation of ± 100Hz, this will yield a phase
variation of 0.1/16.5, i.e. ± 6ns which, on a 54 cm
wide screen, will produce a horizontal shift of
L1L1NE = ± 0.06 mm !
It is obvious that an excellent image stability is thus
obtained.
V. 3.6.2 - Dynamic study
The loop response in transient mode is quite important. It determines the overall system stability
and the phase' recovery time, which are imposed
by the external filter "f(p)".
The close-loop transfer Junction is equivalent to a
second order system. These time constants are in
practice displayed on screen by a bar delivered by
a special pattern generator representing the phase
errors.
The following optimized results were obtained from
filter f(p) connected to pin 22.
Filter component values are:
R1 = 4.7kQ, C1 = 2.2/lF, C = 10nF
Figure 30 : On Screen Display.of Time Constants
+ 411S
1------~_ _ _ _~_---------
,."'......
Normal mode
Long time constant
VCR mode
Short time constant
N
""'1
n
91 AN2028/29-29
Where:
N : number of lines required for phase correction
n : number of lines required for the horizontal oscillator to fully stabilize
20/55
---------------------------~~~~©~y~~~~
1114
---------------------------
APPLICATION NOTE
a. Long time constant
• At 6t of 4!ls =; N=18 lines, i.e. 'tLONG = 1.15ms.
System oscillations are perfectly damped.
Image stability with a noisy video signal is very
satisfactory.
followed by bounced oscillations due to the characteristics of a second order device.
As given in application diagram section 6, an other
alternative would be to use the following component values :R1 = 3.9kQ, C1 = 4.7!lF, C = 1SnF
b. Short time constant
• At 6t = 4!ls =; N = 5 lines, i.e. "CSHORT = 0.32ms
• n = 5 lines
One should notice fast phase recovery, naturally
The phase comparator is disabled under two conditions :
- During frame sync pulse (see figure 30)
V.3.7 - Phase comparator inhibition
Figure 31
Inverted Pulses for Frame Sync.
VidOO
~~l~-r~~~JL/JW~Lx'r~-r-..-'r-"'~
4
Composite
Sync.
FrameSync. (FS)
I/'
y,'----..."fL
Frame 1 is controlled by the line sync pulse, the comparator must
be inhibited at the time of line sync inversions so
as to avoid occurence of phase errors at the beginning of each frame.
This inhibition is activated during FRI (Frame Retrace Inhibition) issued by frame logic circuitry. If tj>1
is locked before the vertical scanning synchronization occurs, (e.g. when switching between channels), and since FRI phase is not yet correctly
positioned, the V'3(MAX)
= .3.5V
In sync mode:
• T H = 641-1s, tRESET = 6.51-1s
• K = 0.527 ± 2 % •
22/55
--------------Eii ~~~©I/j~~[~2~· - - - - - - - - - - - - - - -
1116
APPLICATION NOTE
V.5 - Second phase locked loop "G>2"
This stage controls the horizontal deflection of the
electron beam i.e., the horizontal picture scanning.
The frequency of operation, in the absence of video
signal, is a multiple of the VCO frequency, i.e.
15625Hz - 500Hz.
When video signal is present, the scanning frequency is synchronized with the video signal
through the first phase locked-loop "G>l".
The output rectangular waveform signal drives the
line switching transistor. This transistor, when
turned-off, generates what is commonly called the
"line flyback".
In order to obtain a horizontally centered picture,
the line flyback (LF) must coincide with the blanking
time on tube cathodes.
The turn-off delay is due to transistor base storage
time. This time varies in different TV sets as the
transistors employed may have different operating
characteristics which are functions of temperature
variations, power rating and base drive.
Therefore, it follows that in order to obtain stable
image centering, the line flyback must be phase-
locked with respect to the video signal.
The second phase-locked loop also offers the possibility of horizontal phase-shift adjustment.
Figure 35
Blanking Time
Video
Signal
on Cathodes I
Line
Yoke
Current
I
I
I
0 i="!,~+---7-"""'i"'1'~-'-1__
I
l
I:
if\:
J
Line Transistor I
Collector Current I
;if\!I
Line~~
Flyback
~
__
l121ls
9·
L
T H = 64 IlS
~ 5.~saturation
"li)
:5
~~
f- E
~
15
~()
Turn-off
1~//;,
I I
--H- Turn-off Oelay
91AN2028/29·34
Figure 36 : Second Phase Locked Loop" G>2" Block Diagram
V.5.1 - Duty of different building blocks
V.5. 1. 1 - "G>2" Phase comparator
This block generates a current proportional to the
phase difference between the phase reference "G>2"
and the middle of the line flyback to be phaselocked.
11.5.1.2 - Low-pass filter
• Rejects the parasitic component "sum of
phases"
• Smoothens the "phase difference" component
• Allow "phase adjustment" by generating an
error within the loop
11.5.1.3 - Phase modulator
Uses the line saw-tooth voltage to convert the
voltage delivered by the low-pass filter into a phase
corresponding to the line transistor turn-off control
signal.
23/55
---------------- ~ ~~~@m~j~(~9c~ ----------------
1117
APPLICATION NOTE
\/.S. 1.4 - Flip-flop
Generates the turn-off control signal for a constant
time (fixed by the external capacitor), the phase of
which is set by the modulator.
V.5.1.S - Output stage
'. Delivers the control signal for line transistor
driver
• Disables the output during start-up and protection phases
At : I = 550 IlA and TH = 64 IlS
"A" will remain constant since "I" is a multiple of
current on pin 14.
"IREF"
Figure 38
\/.S. 1.6 - Line deflection stage
• Generates the saw-tooth current for line yoke
• Generates the high voltage required by picture
tube and other supply voltages
The line flyback information is provided by the EHT
transformer
V.5.2 - Operation of building blocks
To provide an easier understanding of the subject,
the "$2" loop study will be covered as a function of
various time intervals and not as a function of
phase.
\/.S.2.1 - Phase comparator "$2"
The operation is identical to that of "$1" loop.
~deoon
Cathodes
Figure 37
91 AN2028/29-37
- - - - - - . - - Vee
\/.S.2.2 - Low-pass filter f(p)
+--__ Filler F(p)
The horizontal phase-shift adjustment is taken into
account:
Figure 39
r---------
I Phase Modulator
I
91 AN2028/29-36
t!
'P2
The V~2 signal issued by logic block is phased with
respect to the middle of line sync pulse on pin 27
and delayed by a 2.6 Ils interval so as to be at the
middle of blanking time on video cathodes.
The output current c'ompoRent "2fH" is rejected by
the low-pass filter.
- The average current is i =
21~:
Where: t,t = tiN - tOUT
- The conversion gain is therefore:
i, 21
A='M=TH= 17IlAiIlS
RIN
Comparator
V
-
liN
I
_
IL _______
'"
+----Vee
Horizontal
p
R
Phase
Adjust
91 AN2028/29-38
24/55
---------------,~ ~~~©~~:cfi!~~· ---------------
1118
APPLICATION NOTE
- Filter V : f(i) transfer characteristic is given as :
V: Zi + ~ . K· Vee - Z . liN
Figure 41
V13(tl
3.5 V -
V
Where:
- ----------------
1
• Z: RINIIRII-C·p
• RIN, liN : modulator input characteristics
In Dynamic Mode
V
R'
- V: Zi =} f(p) = -;-: Z(p):-I
1 +1:p
Where:
• R': RIN II R (R» Potentiometer P)
• 1:: R' . C : Filter time constant
/
The network behaves as a first order low-pass filter
whose cut-off frequency at -3 dB is :
1
L3d8 : 21tR'C
Filter component values
- R: 470kQ and C : 22nF
• In practice, (K E [0,1]) Vec : 12 V
- RIN : 25MQ , liN: 0.65JlA (base input current)
F-3db : 15.7 Hz with adjustment and 0.3Hz without
adjustment
\1.5.2.3 - Phase modulator
This is built around a comparator which converts
the filter voltage to a rectangular waveform such
that its rising edge phase, variable as a function of
filter voltage "V", will trigger the line transistor turnoff control circuitry.
The conversion gain is determined by the slope of
the line saw-tooth applied to comparator.
Figure 40
91AN2028/29·39
11 H>--_..;:12c-=_f.c.(V_'_-->..._,
I I
V'OUT
'-:-:------:..-----=--=--=-1-->:---T
H
V VI3(MAX) ...
e. Maximum "Tl0" value as a function of "C1"
T10(MIN) : 16Ils(window) + 4lls(auto set) = 20llS
~ Cl(MIN) = 2.3 nF
T10(MAX) : for
Cl . VREF
Id _ Ie
+
Cl. VREF
Ie
s; 641ls
~ TlO(MAX) = 40llS ~C1(MAX) = 4.6 nF
For normal operation, C1 value has to be chosen
between 2.3nF and 4.6nF.
If pin 1 is grounded, output signal (pin 10) is inhibited and goes high.
_26_/5_5_ _ _ _ _ _ _ _ _ _ _ ~ SGS-mOMSON _--'-_ _ _ _ _ _ _ _ __
'".,L [i:j]nIi:OO@~~~©"iiOOw.'Il~~
1120
APPLICATION NOTE
back pulse. During this interval, in order to avoid
transistor destruction, the pin 10 output must absolutely remain high.
This is done internally with the line flyback pulse
(pin 12), which forces pin 10 output to high level
during the line flyback time.
V.5.2.S - Line output stage & inhibitions
Figure 44
Line Flyback
Input
TlO
OutPUI~
To
line "Driver"
Logic 1
for Security
at pin 28
91 AN2028/29-43
• Open-collector output V10(SAT) < 1.5V at
i10(MAX) = 20mA
The line output (pin 10) will go high if either the
following three inhibitions is activated:
a. Inhibition at start-up
This is generated by a hysteresis comparator which
is driven by "KVcc" and the "1.26V" reference
voltage.
This inhibition is mandatory since the device will
operate only at Vcc ::: 5 V.
z
,Q=~
i: -; 1
!::~
~
~d
:;
V.S.2.6 - Line deflection stage
This chapter will cover a general description of the
"horizontal deflection stage" employed almost
commonly in all recent TV sets.
Deflection of electron beam is proportional to the
intensity of magnetic field induced by the line yoke.
This yoke is equivalent to an inductor. The deflection is therefore proportional to the current through
inductor.
In order to obtain a linear deflection from left to right
as a function of time, a saw-tooth current must be
generated within the yoke. The approach is to
apply a switched DC voltage to the line yoke.
- When K is closed:
E
ryt
iL(t) = - (1 - e - L)
ry
Figure 45
m
c. Safety inhibition
The device has a security input terminal "pin 28".
If a signal lower than VREF (1.26V) is applied to this
pin, line and power supply outputs are all inhibited.
This function is particularly useful for TV chassis
protection. Referto section V. 7.5 for further details.
0
. VHYST
= 0.5 V
- 1:: is always higher than half of trace time:
ry
ttrace
2
= TH -
b. Inhibition during line flyback
The output signal pin 10 is high during line transistor turn-off. The leading edge of output signal pin
10 turns off the line transistor after a delay interval
(storage time).
The line transistor turn-off generates an overvoltage on the collector corresponding to the line fly-
= 64 -
12
= 26/1s
2
Figure 46
5.5. 6
SUPPLY VOLTAGE (V)
tLF
2
Deflection Yoke Resistance
iL(t)
ry
Deflection Yoke Inductance
(L)
91AN2028/29-45
27/55
------------------------------ ~ ~~~@~R~~~~~ ------------------------------
1121
APPLICATION NOTE
- "iL" variations as a function of ti me :
diL
E
Cit = L
_I}'t
e L
E(
~ L for t «
In practice, the power switch "K" is built by a
combination of "High Voltage Switching Transistor"
and "Fast Recovery Diode".
fyL)
The current will therefore be linear as a function
of time iL(t) =
~ .t
L
Figure 47
from "t1" to "12" which is the
second portion of the line trace interval.
E tTRACE
- Current at the end of trace: 1M = L . - 2 - Energy stored within inductor: W =
Endaf
Trace
if K remains
open
/
I
,"'-,,
O~------~~~~/--~\~~~-
~ . L· I~
If the switch is opened at t = t2, the "L.C" combination will enter into oscillation, the energy stored
within inductor is transfered to the capacitor,
which will return it to the inductor and so on.
i~
o~-----+--~----~~-
The circuit period is classically given by :
T=21t·~
If "K" is closed at time ''13'', the inductor will once
again have a voltage "E" across its terminals. The
current falls linearly until "t4". This phase corresponds to the first half of line trace interval.
The overvoltage across C is :
V - E ttrace
p-
2~+
during tLF
E
Vc
Vp
= 1t~
Th t · . V = E !TRACE· 1t E
a IS. P
2tLF
+
In practice, E is higher than 100V.
- tTRACE = 52~s
- t LF = 12~s
=}
ic
Vp ::>: 780V
Note that this overvoltage is almost 8 times higher
than the source voltage "E". This overvoltage is
applied to the primary winding of a "step-up transformer" (EHT Transformer) in order to generate the
high voltage required by picture tube anode.
I
E
,-,
\
__ -1.'__"-
O+-------~--~--~/---\~~
\
-,
V~o~--;
~
tLF
,-,
V
I
I
91 AN2028/29-46
28/55
--------------------------~ ~ii@m?:m:~~ --------------------------
1122
APPLICATION NOTE
Figure 48 : Simplified diagram of the horizontal deflection stage
EHT
E
TRANSFORMER ~ VEHT(anode)
(Rc"".dby SMPS)
+
~ ~
1" "
"'\J ~~
""I
____ ...IL
Mlocolianeous Powe, Supplies
IT,
Line Flyback
LINE
+12V
o
(pm
12.
TEA2028)
r--.Y-'2~~, Iy
ID
INPUT
91 AN2028/29-47
If considered in average value, it is seen that the
voltage across capacitor "CS" is almost equal to the
source voltage "E". The saw-tooth current through
this capacitor will produce a parabolic ripple around
"E", which will thus modify the equivalent source of
the line yoke and induce a modified current of "S"
shape within the yoke. This "S" current is used to
produce a linear picture as a function of the picture
tube geometry.
The basic arrangement can be reconstructed by
assuming that the equivalent inductor "L" is the
transformer "Lp" and line yoke inductors put in
parallel (since VC S(AV) = E).
The output pin 10 of TEA2028 is applied to a
matching stage called "line driver" the output of
which drives the power transistor "T". The matching stage is necessary for optimized base drive.
At middle of trace, the transistor enters into saturation and its current rises linearly. V1 0 will then issue
a control signal to turn the transistor off. The transistor will be in fact turned-off after a delay interval
"ts" (storage time) varying from 2 to 8)ls depending
on application. The system will then enter into
oscillation during its half-period thereby generating
the line flyback. At the end of flyback time, the line
yoke current is negative while the voltage across
capacitor "C" has fallen to zero. The energy transfer
automatically takes place by the recovery diode
during the first portion of trace time.
Also, it is clear that the line scanning phase with
respect to video signal is determined by the risingedge of pin 10 output signal.
High level duration (T10) of pin 10 output signal
Figure 49
S Correction
IY~\-o
Tr
c
0IfilIDJY
,
I
I
I
At..
veEl
I
I
(T: -t.___",O_--L.i---~_i.._ I
: 12Jls r
12V r-i'f--::----,
t 1:
Tl0
Vl~ +__-1-+:_2_9.:..JlS_~_ _ __
, I
,
IT,
-\--J.,
t
I
Is
: (tum-off delay)
,
o
..
,
I
II
,,
,
I
I
I
:-I-l------u~I.Ll.LLLW:c.l.h--.-...
t
29/55
----------------- ~~~~~~g~:g~ ----------------1123
APPLICATION NOTE
must be higher than the delay interval "tS(MAX)" +
the fly back time (Le. 8 + 12 = 20lJ.s) and must
turn-off before the end of diode conduction:
tTRACE
T10 < ts(MIN) + tLF + - 2 - ='> < 40IJ.s
It is therefore clear that the second phase-locked
loop does not cause any dynamic delay.
This can be explained by the fact that the phase
modulator responds instanenously to all variations
of "<\1z".
In practice, one will select the pin 1 capacitor
C1 = 3.3nF to yield T1 0 = 291J.s.
V.5.3.1 - Study of the Static Error
tiN = 0 (phase of V$z) is taken as timing reference.
The equivalent impedance of F(p) filter is :
• R' = 460kQ (R II RIN) : if an adjustment is applied
to pin 16, or
• Modulator input resistance RIN = 25MQ : without adjustment
V.5.3 - Characteristics of loop "<\1z"
The function to calculate is a time with respect to
the origin time set by "V$Z". In fact, it is an easy task
to inter-relate the horizontal displacement (in mm)
to a time interval specified in IJ.s.
For a large screen width of 540 mm, the horizontal
scanning time :64 - 12 = 521J.s, which corresponds
to : = 10mm/lJ.s.
Figure 50
with: T1 = ABRIN
Where:
tOUT
,
LFA
,
91 AN2028/29·49
(1 )
• i = A . (tiN -tOUT)
• V=Z .i+
~.
K· Vce - Z . liN
(2)
• tOUT - tiN = B . V + td - 59.71J.S
(3)
R
R'
1 + 'tP
·Z=--
tOUT = - 46ns
which
corresponds to a
picture shift of
0.46 mm!
The error is quite negligible and thanks to rather
high open-loop gain, the display accuracy with
respect to the phase set by "<\12", is very satisfactory.
•
•
•
•
RIN = 25MQ
liN = 0.65mA
td = 10lJ.s
T1 = 6.8 x 10 3 = 76dB
b. Study of shift adjustment
With R, P network connected to pin 16, the tout
becomes:
R'
- BR'liN
With: T2 = ABR' (where R' = R II RIN)
andKE [0;1]
(4)
1 +'tp
The system exhibits the characteristics inherent to
a first order circuit and is therefore stable.
combining equations (1), (2), (3) and (4), the tOUT
delay is found as follows:
Z
BZhN to - 59.71J.s BA . KVee
tOUT = tiN - 1 + T +
1+T
+
1+ T
~~_t_
Dynamic
Error
gain
term due
=1
to the
input
current
"hN"
Error term
due to
delay
t
Error term
due to phase
shift
adjustment
(if applicable)
Substituting the following values into above equation:
• R = 470kn
• R' = 470kQII 25MQ = 461kn
• A = 17x1 O·s NlJ.s
• B = 16IJ.sIV
·td=10lJ.s
·T2=125
• Vee = 12V
tOUT = - 38ns - 390ns + 1 .5lJ.sxK
therefore tout = 1.5xK - 0.43 ( in IJ.s )
If K varies between 0 and 1
~ tout [- 0.43ms to 1.07IJ.s]
which corresponds to a picture displacement of :
L1L1NE [- 4mm to + 11 mm].
---------------------------~~~~~~2~~~~~~
1124
}
to - 59.71J.s BR · KVee
tOUT=~+1 +T2 + 1 +T2
• R' = RIN II R
• A= 17IJ.NIJ.s
• 't= R'C
• B = 16.4lJ.slV
The open-loop dynamic gain is :
ABR'
• T=ABf(p)=ABZ=--
30/55
a. Phase shift error in case of no adjustment
Equation (5) becomes:
T
_ BRINIIN to - 59.71J.S
OUT - 1 + T1 +
1 +T1
---------------------------
APPLICATION NOTE
Shift variations as a function of Vee
(with adjustment)
BF
-'· K
R
BR
R'· K
dtout
K
dVee = 1 + T2 ~ ~ ~ AR
= KxO.12J.lSIV
1d~~c
at
= 0.34mmlV
KNOMINAL
= 0.28
Therefore, a constant Vee must be applied to the
potentiometer.
V.6 - Vertical deflection driver stage
This stage must constantly drive the vertical spot
deflection. Such deflection will horizontally scan the
screen from top to bottom thus generating the
displayed image. Similar to horizontal deflection,
the vertical deflection is obtained by magnetic field
variations of a coil mounted on the picture tube.
A saw-tooth current at frame frequency will go
through this coil commonly called "frame yoke".
Frame period is the time required for the entire
screen to be scanned vertically.
C.C.I.R. and N.T.S.C. TV standards require respectively 50Hz and 60Hz Frame Scanning Frequencies. Also, a full screen display is obtained by two
successive vertical scannings such that the second
scanning is delayed by a half line period with
respect to the first.
This method increases the number of images per
second (50 half imagesls or 50 framesls in 50 Hz
standard). This scanning mode called "Interlaced
Scanning" eliminates the fliker which would have
been otherwise produced by scanning 25 entire
images per second.
Figure 51 : Block Diagram of the Vertical Deflection Stage
r
Topol
H/2
Pictu((]
'"
,
I
Frame
Saw-tooth
[\,
... t
"''''
LBottomof
Picture
lFRAME
1 YOKE
91 AN2028f29-50
The circuit will generate a saw-tooth voltage which
is linear as a function of time and called "frame
saw-tooth". A power amplifier will deliver to the
"frame yoke" a current proportional to this sawtooth Voltage. It is thus clear that this saw-tooth
voltage reflects the function of the vertical spot
deflection; which must itself be synchronized with
the video signal. Synchronization signals are obtained from an extraction stage which will extract
the useful signal during line pulse inversion of the
composite sync signal.
Synchronization occurs at the end of scanning, in
other words, when the saw-tooth voltage at pin 5 is
reset. This function is accomplished by the "frame
logic circuitry" of full digital implementation.
This processing method offers various advantages:
- Accurate free-running scanning frequency
eliminates the frequency adjustment required by
previous devices.
- Digital synchronization locked onto half line
frequency thereby yielding perfect interlaced display and excellent stability with noisy video signal.
- Automatic 50/60 Hz standard recognition and
switching the corresponding display amplitude.
- Optimized synchronization in VCR mode.
- Generation of various accurate time intervals,
such as narrow "sync windows" thus reducing
considerably the vertical image instability in case
of for instance, mains interference, superimposed
on frame sync pulse.
- Generation of vertical blanking signal for spot
flyback and to protect the picture tube in case
of scanning failure.
31/55
--------------- ~ ~~~.Dm~,~C~~?c~ ---------------
1125
APPLICATION NOTE
V.6.1 - Frame sync extraction
The main duty of this stage is to extract the frame sync pulses contained in composite sync signal.
Figure 52 : Sync extractor block diagram
5.6V
Frame
~c
{
• 'c=2~
• 'c+ID=9~
• C=35pF
91AN2028/29·51
Two current generators are used to charge and
discharge the integrated capacitor "C". The discharge generator (Ie + 10) is driven by the composite sync signal.
The t:,.Ve across capacitor is: _ 10 . ~YNe
During frame trace, the capacitor is discharged at
each line sync pulse thereby generating a t:,.V of
-0.94V with respect to 5.6V and then recovers the
charge by current "Ie". The comparator output remains low.
The discharge time is 27!!s at the first line sync
inversion applied to comparator input. The voltage
"Vc" then falls from 5.6V to 0.2V and triggers the
comparator "Co" which will deliver a frame sync
pulse when "Ve" crosses the 2.8V level.
The overall arrangement behaves as an integrator
and will therefore suppress any noise susceptible
to be present on input signal.
An external capacitor pin 20 can be added to the
integrated capacitor C to increase the frame sync
time constant.
V.6.2 - Frame saw-tooth generator
Figure 53
FR~;;:O~;;L~;l
I
I
I
,,
--+,I
60Hz..
+
T
+
I
Frame
7~:)t
_____
..J --'L
+E
(200V)
+--_ Frame Saw-tooth
Output
91 AN2028/29-52
The frame saw-tooth is generated by an external
RC network on pin 5.
The time constant "R5 x C5" is much higher than
the frame period. Therefore, the generated saw-
1126
tooth is quite linear.
The',network is discharged by an internal transistor,
controlled by the frame logic block.
APPLICATION NOTE
Figure 54
~v
1.26V
(VREF)
-------------------
I
I
1
--I
I
I
I
1~~1
~
1
I
20ms (50Hz)
II-·~---="'-'-'----'.----·II
91 AN2028/29-53
V.6.2.1 - 60Hz STANDARD SWITCHING
The NTSC standard requires a vertical picture
scanning frequency of 60Hz, i.e. a saw-tooth period
of 16.66ms.
In order to obtain an identical deflection amplitude
whatever the standard (50 or 60Hz), the saw-tooth
amplitude for both periods must be the same.
60Hz standard recognition is performed automatically by the frame logic block, which will issue a
signal to drive a current generator ."£>160". This
current will be summed with the external charge
current and will increase the saw-tooth slope, so as
to yield same saw-tooth amplitude to that set in
50Hz standard. This current is centered around
14/1A and is a fraction of IREF applied to pin 14.
Employing the recommended component values
for network can nected to pin 5, this current will
result in identical amplitude in both standards.
160 x T60 150 X Tso
eNs = - - - = - - Cs
Cs
150
=~ =
Rs
200V
2.7MQ
therefore £\160 =
=0>
60
160 = 150 X 50
half line period (32/1s). The required periods and
time intervals are obtained by counting the clock
pulses.
For the sake of clarity, timing signals so obtai ned
are labeled by the line number corresponding to
video signal.
The time corresponding to "x" scanned lines with
respect to the beginning of frame saw-tooth
(RESET) is therefore:
Ix = 64/ls (x - 1) + 32/1s
Figure 55
SY~
I~I
__~_'_I~
I
[
RESET
(Counte:) -311-S---':'----2
I
= 1.2 X 150
HI2~
:
= 74~A => 160 = 88~A
14~A
V.6.3 - Functions of frame logic block
This section is fully implemented by 12L logic gates.
It is clocked by an accurate "H/2" clock running at
Frame
t
t
-L~
Saw-Ioolh
(pin 3
I
I
I
I
LX
IX
t
1.<--[
)/
- J
I
33/55
--------------- ~~~~~~~m!g~ ---------------
1127
APPLICATION NOTE
Figure 56 : Block Diagram
BINARY DIVIDERS
HI2
(3~5)--i
I--I--I-H+++H-Reset
t---
--------
(11
Jl..n... 64115
..rt..
-I
010
.J"""I....J
32.768ms
Frame Blanking
FRllnhlbltlon
(~1)
50!60Hz
\/.6.3.1 - 50160 Hz Standard recognition
This function is performed by two shift registers
which are loaded by sync pulses (if present) and if
these pulses fall within the time interval specific to
each standard. These intervals are called "Register
Windows"and labeled "WR(50)" and WR(60).
b. - 60 Hz Standard Recognition
Figure 57
L2Tl
L247
I
___-1'
I
1309
17.696ms
19.744ms 12o:128ms
I
I
j
s y n c - - -1-6 66
!-'
m-5....J.
L315
I
I
I
I!-__...J~!--_ __
WR(60Hz)
15.773ms
60Hz
The identification is not valid if two sucessive 50Hz
pulses are not detected. Identification signal is also
used to reduce the vertical synchronization window
in 50Hz standard thereby offering excellent noise
immunity against noise susceptible to be present
in sync signal and hence good display stabilitx.
I
'
50Hz
Sync
,
--2-!Omi-S- - 91 AN2028129·56
This identification is validated after three sucessive
sync pulses at 16.6~s period have been detected.
Three pulses are necessary to ascertain the identification prior to switching the saw-tooth amplitude.
The identification signal [10(60) = 1] is also used to
reduce the synchronization window and, in case of
one or two missing pulses close to 60Hz, to set the
free-running frequency.
a. 50 Hz Standard Recognition
\/.6.3.2. - Vertical synchronization window - Freerunning period
This identification is considered valid if two sucessive sync pulses applied to 50 Hz shift register fall
within the 50Hz window "WR(50)". At the time of
synchronization capture, the first pulse will reset
the counters. The second pulse, if present, will
then trigger the 50Hz identification 20ms later
[10(50) = 1].
In the absence of sync pulse various free-running
periods are specified. Since vertical scanning must
be always active, these free-running periods must
be higher than those of 50 and 60Hz standards so
as to ensure synchronization.
An other window, allowing synchronization only at
the end of scanning, is also necessary. Upon syn-
1128
APPLICATION NOTE
chronization, this window will allow vertical flyback
only at the bottom of screen. This window should
be narrow for good noise immunity but also wide
enough to yield, upon synchronization, a capture
time unperceptible on screen.
In our case, as long as no standard identification
takes place the window will remain wide, and once
one of the standards has been identified, the window will be considerably reduced.
In VCR mode, this window will be always wide since
frame frequencies delivered in high-speed search,
slow review and picture pause modes are very
much variable and must be taken into consideration.
In the absence of transmission (Mute = 0), synchronization is disabled (so as to avoid incorrect synchronization due to noise) and the free-running
frequency is around 50Hz. This will eliminate the
occurrence of picture overlay at the end of trace at
a lower free-running frequency.
Figure 58 : Definition of Synchronization Windows and Free-running Periods
L247
Register's
,
l2n
L309
L315
L.361
+
t t
I
I:
I
I:
:
:
I
+
W~~~>~~__~~~____~:~_
1
No Transmission
______T!______i~~!_____
I
I
: : 'i
WR_=_O__~!
Free-running Period
(Mute =OJ
~/////;////////~~
r/
. . . . . . .////. . . .
I
I
I
I
=a , lOGO =a
or
VCR Mode
Mute = 1
loso = 1
5QHz Standard
IDSO = 1
60Hz Standard
L
1
WR(WIDE)
Muled
1050
I
I
Reset
I
I
I
I
r////////,
Reset
1:
1,
,I
I
~~_________
1
WR(50)
i
1,
,
I
,
I
Res_e_t____7:____~~------~i~--------W~~______~___________
Reset
L----------l.----------------~----'91AN2028/29-57
Maximum capture time
Figure 59
The worst case capture time occurs when the first
sync pulse just precedes the sync window.
Let's find the number of periods necessary for the
capture to occur, i.e. tn = O.
=>n=T
TL-Tw
T
L-
SYNC
,TL=23ms, Tw=7.3ms
• 50Hz: the number of periods is 6
=> TCAPTURE(MAX) = 120ms
• 60Hz: the number of periods is 3
=> TCAPTURE(MAX) = 50ms
_________-L_______
Wide
Window
__TL__
Frame
I
saw.t~~~w
Sync
Pulses
I
I
I
I
I
t1
I
,
t2
,I=-:-=J:=-:=I
i
I
:~
o
I,·
I
I
I~
tN=O
(capture)
91 AN2028129·58
~ ~~~@~g~:~~~
35/55
_______________
_
1129
APPLICATION NOTE
V.6.3.3 - Frame blanking signal
This signal is necessay to blank the display during
each frame fly back. It is triggered at the beginning
of frame saw-tooth flyback. The duration of this
signal is 1.344 ms (or 21 lines).
Figure 60
TI.JLJLILJLIIfl~
FlrstFrame
1
1
I
:
,,, l
u~;U-
n n n n,-,,-,,-,,-,,--, rli- ...:.- U' U U
Second Frame U LJLJULJLJU U U U U
:
I
I
I
1
I
I
--l
I
Frame Blanking
(pin 4)
.wt
U- U
1
,,'
I ...
I
I
1.344ms
(21 lines)"
.. :
:
I
11\
'L
jL22
r\
---11~~
:.20llS II
I
L335
• 24 lines for TEA 2029
This "frame blanking" signal is available through
pin 4 (TEA2028 only) which is an open-collector
output.
It is also present within the normalized super
sandcastle signal on pin 11 (TEA2028 and
TEA2029).
I
I
12llS
I
ff\
I~---
91 AN2028/29-59
Its duty is to protect the phosphor coating of picture
tube in case of any problem with vertical deflection
function such as scanning failure.
A signal to monitor correct scanning is provided by
the frame yoke and applied to pin 2.
In case of any failure, all frame blanking outputs are
disabled and go high thereby blanking the entire
screen.
V.6.3.4. - Frame blanking safety (TEA2028 only, for
TEA2029 refer to section VII.S)
Figure 61 : Block diagram
12
o--I-'i--''i--lc_--V2
-70""
F~~~
Y~I
10DkQ
2
j-t::1--1
:
1- Fulllnhlbltlon
VlZZIII/OJ
..
1
10) and thyristor controt output (pin 4) for TEA 2029
91 AN2028/29-67
Pin 15 charging current: IC(Av)
= - IO(AV) = - 3.1!LA
V.7.6 - TV Power supply in standby mode
\1.7.6.2 - Regulation by TEA2028
\I. 7.6.1 - Regulation by primary controller circuit
In this case, all that is required is to disable the line
scanning function thus reducing the overall power
by 90%.
This mode of regulation called "Burst Mode" is
performed only by the primary controller circuit and
is activated in the c<).se of missing control pulses or
in the absence of power supply to TEA2028.
In this mode, power available through secondary
winding is limited. Refer to TEA2164 Application
Note for further details.
Higher powers can be obtained by using the regulation feature offered by TEA2028. In this case, the
horizontal output (pin 10) must be disabled.
The device power supply regulation loop remains
active, for minimum conduction period to be 1.5 ms
the power delivered through secondary must be
higher than 3 W.
Line Output Inhibition
Two alternatives are possible:
- Grounding flip-flop pin 1
- Apply a voltage higher than 3 V to pin 12.
Figure 69
R2
RI
LF Inputlnhlbltlon "" V 12> 3V
91 AN2028/29-68
--------------- ~ ~~~wm~~~ru?~~ ______________41_1_55
1135
APPLICATION NOTE
• 4.5V level
V.S - Miscellaneous functions
v.a.1 - Super sandcastle signal generator
Used for horizontal blanking, its du ration is determined by comparing the line flyback signal
on pin 12 to an internal voltage of 0.25V.
This signal used in video stage, is available on pin
11.
It has 3 levels at specified time intervals:
• 2.5 V level
Used for vertical blanking at each frame flyback.
Its duration is 21 lines and is generated by the
frame logic.
This level will be maintained if vertical scanning
failure is detected on pin 2.
• 10 V level
This signal is used by color decoding stage. Its
duration of 4~s is determined by line logic circuitry. With respect to the video signal on pin 27,
this level is positioned such that it is used to
sample the burst frequency transmitted just
after the sync pulse.
Figure 70
VIDEO SIGNAL
(pin 27)
--,,-,---,I
' -_ _ _.;11
II O.3~s
-rr
10V
I
iI
4.5V
4~s
I
I
--Line Blanking· (12I's) _
SUPER
~
SAND CASTLE
(pin 11)
1------FrameBlanking ( 2 1 I i n e S ) - - - - - _ L 91 AN2028/29-69
v.a.2 - Video and 50/60Hz standard recognition output
A 3-level signal is available at pin 24 for video identification (Mute) and for 50 and 60Hz standards
recognition.
Figure 71
+Vcc
+Vcc
Vccrr--
Vccl2r~
V24
O---i;-J __ .
Without
Video
160HZ
Standard
50Hz
Standard
I
Transmit
- - Identification
91 AN2028/29-70
42/55
---------------
1136
~ ~~~(~~~"I~~Rt;~
15kn
J
"11
to' ~
e: -I
(i3 m
lN4148
I
1<1
T
--J
+V
N
:t>
N
o
N
00
EHT
TRANSFORMER
:t>
"C
"C
r('5
V+cc
~
!ltLF
I
(5
Z
o
~JJ
:;
Gl
L _____
:0
:t>
is:
~
TEA 20288
~(I)
ljin
V+GC
'@CIl
~:i!
5.6kQ
Ii
50/60Hz Standard
&
Video Identifica.tion
Output
V
Video
Input
1 nF
II-
V+cc Safety
Input
~
:t>
~
W
--J
.".
~
01
VonicaJ
Phase
Shift
"C
j'"
(5
~
'"
o
z
':i
S
m
Z
o
~
»
"C
'"
~
CD
z
APPLICATION NOTE
VII - TEA2029 : DIFFERENCES WITH TEA2028
VII.1 - General
The TEA2029 has quite the same functions compared to TEA2028.
with a switched mode vertical stage using a thyristor.
The main difference is that the TEA2029 incorporates a frame phase modulator intended to work
The TEA2029 can also be used with a linear vertical
power amplifier such as the TDA 8170.
VI1.2 - Pin by pin differences
Pin number
1
TEA2029C
Differential inputs of the frame error amplifier
(including frame blanking safety in case of
vertical stage failure).
2
44/55
TEA2028B
Capacitor for horizontal output duration
adjustment
(29J.ls typo with c1 = 3.3nF)
Vertical blanking safety input
4
Frame output for thyristor control
Vertical blanking output
(21 lines duration)
10
Horizontal output
(26J.ls typo duration)
Horizontal output
(duration is adjustable)
11
Supersandcastle output
(with a frame blanking duration of 24 lines)
Supersandcastle output
(with a frame blanking duration of 21 lines)
12
Negative horizontal flyback input
(115 Vpp through a 47 kQ resistor)
positive horizontal flyback input
(1 OVpp through a 47kQ resistor)
20
Positive AGC key pulse output
(low level when no video)
Capacitor for frame sync. time constant
adjustment
28
Safety input
(inhibition of SMPS, Horizontal and Frame
outputs when V28 > 1.26V)
Safety input
(inhibition of SMPS, Horizontal outputs when
V28 < 1.26V)
------------------------------~1ii~~~~~~~
1138
------------------------------
APPLICATION NOTE
VI1.3 - TEA2029C Pin connections
Pin number
1
Description
Frame error amplifier non-inverting input
2
Frame error amplifier inverting input
3
Frame saw-tooth output
4
Frame output (for thyristor control)
5
Frame ramp generator
6
Power Grou nd
7
SMPS control output
8
VCC Supply voltage
9
SMPS regulation input
10
Horizontal output
11
Supersandcastle output
12
Horizontal flyback ioput
13
Horizontal saw-tooth generator
14
Current reference
15
SMPS soft-start and safety time constant
16
<1>2 phase comparator capacitor (and horizontal phase adjustment)
17
VCO phase shift network
18
VCOoutput
19
VCOinput
20
AGC key pulse output
21
Substrate Ground
22
<1>1 phase comparator capacitor
23
VCR switching input
24
Video and 50/60Hz identification output (Mute)
25
Video identification capacitor
26
Horizontal sync detection capacitor (50% of peak to peak sync level)
27
Video input
28
Safety input '
Package: DIP28
~ ~~~(~,m~(~~~~~
45/55
----------------
1139
APPLICATION NOTE
VII.4 - Frame phase modulator
The Tranconductance Amplifier "A1" converts the
differential input voltage into two output currents
"ls1" and "ls3".
• A1 transconductance
IS1
=-V
= 1011NmV
IN
IS2
• B transconductance = V2 = 4011NV
• Transfer characteristic
= b.tvOUT = 6.411s/mV
b.
IN
The filter time constant is maximum near the oper-
=
ating point when IS1
IS2
In this case:
• The base current of T1 = "ls2 - IS1"
• The filter band-pass = 15kHz
The maximum conduction period of "4011S" is determined by the horizontal logic circuitry.
The frame frame flyback is detected by transistor "T3".
There is no feed-back during frame flyback and
"ls3" is maximum (higher than 14) which will drive
the "T3" into conduction.
Figure 73
B
Horizontal
Saw-tooth
V~I
' - - _ _--I
V2
~! 3.5V
Safely Frame Logic
to
Super Sand Castle
r--_--"'Tl
Filter
641lS
I.F.
14
Phase Limitation
(Horizontal Logic)
Frame
Output
Horizontal Flyback
Safely&OnlOff
Switching Voltage .
91 AN2028/29· 72
Figure 74
VtS
~I!
I
40~ max
Horizontal Flyback
•
,t~,
Frame Output
Horizontal Saw-Iooth
-i-\...
6us
46155
------------------------------~·~~~@Ir~~~:8~'
1140
91 AN2028/29· 73
------------------------------
APPLICATION NOTE
VII.5 - Frame blanking safety
sandcastle low level remains constant at 2.SV so
as to protect the picture tube in the absence of
frame scanning.
- During trace: IS3 < 14 =; T3 is blocked.
- During flyback : IS3 > 14 =; T3 conducts.
In the absence of flyback detection or if the flyback
interval is longer than the blanking time, the
Figure 75 : Frame Blanking Safety Block Diagram
IF
S
Q
R
Q
Blanking
BlK'
R
Output
to Super
Q
Sand Castle
From
Frame
Counters
S
BlK'
RESET
if
91AN2028/29·74
• "IF" signal is delivered by Frame Error Amplifier (see Frame phase modulator figure)
Frame Flyback interval
. if is high during the
Figure 76
I
I
~
RESET
I
--ILI
I
f
~r-------'L
f
I
BLANK'
~
I
I
_+-1---!nL.-f
f
f
~
51
------.1
24 lines
I
I
I
L-
Blanking output
I
I
I
I
I
f
I
I
I
I
f
I
I
I
~
~i--------
Normal Operation
---------------
I
I
I
I
I
11--1
--.-J
I
I
I
I
Too Long Flyback Pulse (FRI)
~ ~~~i~m~~(~il~~
91AN2028/29·75
47/55
---------------
1141
APPLICATION NOTE
VII.6 - On-chip line flip-flop
Figure 77
-----------------------------------------~
161J,sWindow
I
~
I
A~MAX
I
LF
I
I
I
I
10
S1.
OUTPUT
91AN2028/29-76
Figure 78
TlO = 35 x Tvco - K· R14 . C13
::J1l7[
Vto
I
I
I
I
:
:
:
:
I
I
1
!
:
:
I
I
~
261lS
A¢MAX
=16/-ls
91 AN2028/29-77
= 70 x 10--6 - 4R14 . C13
Where Tvco is the Vco period of oscillation on
pin 18.
- If in synchronized mode:
• Tvco = 2~s
• R14 = 3.32kQ
• C13 = 3.3nF
ThereforeT10 = 26J..ls (nominal value)
VII.7 - AGe key pulse
Figure 79
VIDEO SIGNAL
(pin 27)
~
S~~~L
12V
_ _ _-'II'
r-+-'- - - - i - - - ,
fl>~s 1~1L....-----,J
OV
(pin 20) --'::':"---'
l
1-
As illustrated below, this signal is used in some
TV sets to perform sampling window for Automatic
Gain Control of picture demodulation network.
This system is called "clamped" AGC, and locks the
demodulated line sync amplitude and hence sets
Without
Video Signal
91AN2028/29-78
the video signal amplitude.
This signal generated by line logic circuitry is correctly positioned by the first phase locked loop " L = 120mH, ry = 60Q)
Figure 88
L
Where:
• Iy : Peak-to-peak yoke current = 380mApp
• T: 20ms
• C1 = 100011F
VII1.5 - Frame flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
"A" will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode "0". As a consequence, the capacitor "C"
starts charging up to the flyback voltage. The thyristor is triggered as soon as the yoke current
reaches the maximum positive value.
/
f
--
I
\
J
\. (THYRISTOR
"'--_/
• VLF
LOAD
YOKE
...... '\
(DIODE
"
c
/
= 21 OVpp
• IYOKE
= 380m App
• L = 500llH
• C = O.471lF
• VLF = 9.2 Iy(pp) . ry
• Flyback duration = 1 ms
91 AN2028/29-87
1145
APPLICATION NOTE
VII1.6 - Feed-back circuit
V111.6.1 -
Frame power in quasi-bridge configuration
Figure 89
FRAME
YOKE
Iy
Frame Reference
Saw-tooth
Frame Amplitude
Adjust
R2
~
Reference de
Adjust
v+
R'2
91 AN2028!29-88
This stage measures the frame scanning current in
differential mode and compares it to the reference
saw-tooth on pin 3.
The overall configuration is built around two symmetrical networks:
• "R1, R2, R3" network: determines the dynamic
saw-tooth voltage
• "R'l, R'2, R'3" network: sets the bias voltage and
the d.c. shift control.
.
R2
Iy
a.c. gain: G =-R =-V . 0'. . RM
1
IN
where:
• Iy : Peak-to-peak Yoke Current
• VIN : Peak-to-peak saw-tooth voltage (pin 3)
• 0'. E [0,1) : amplitude adjustment
VIII. 6. 1. t- Choice of "R" value
The saw-tooth generator output is an emitter follower stage. Pin 3 output current must therefore be
always negative.
R « R1
VIN(MIN)
VBIAS - VIN(MIN)
Where:
• VBIAS :
Bias voltage for pins 1 and 2
Saw-tooth voltage low level
• VIN(MIN) :
1146
Example:
• R1 = 22kQ
R1
• VBIAS = SV
• VIN(MIN) = 1.26V
=>
R =
10
VIII. 6. 1.2 - Influence of R3 value
R3 sets the bias voltage for pins 1 and 2. This
voltage should be lower than S.SV so as to enable
the frame to function upon initial start-up at
Vee = 6V.
If the bias voltage is higher than this S.SV level, the
d.c. open-loop gain will fall thereby rendering the
system more sensitive to d.c. drift.
Satisfactory results are obtained at VBIAS values
falling within 4V to SV range.
R3
= R,
VSIAS
Vs (V'N(MEAN) . G) - VSIAs(1 - G)
Where: VIN(MEAN) : saw-tooth mean value (pin 3)
Capacitor "C" connected between pins 1 and 2
determines the system stability. Its value must be
appropriately calculated as a function of "R1, R2
and R3" values so as to reject the line frequency
component.
APPLICATION NOTE
VIII. 6.1.3 - "S" Correction circuit in quasi-bridge configuration
Figure 90
TEA 2029
YOKE
01
R4
02
100n
Ve
I
91 AN2028/29-89
The "S" correction waveform is obtained using the non-linear "VDIODE" versus "IDIODE" characteristics of
"01" and "02" diodes.
The signal pre-corrected by "01", "02" diodes and the feed-back signal through "R5", are summed at "A".
The "S" correction level is determined by the ratio between "R4" and "R5" resistors.
V111.6.2 - Frame scanning in switched mode using coupling capacitor
Figure 91
TEA2029C
I1
I
I
I
1
I
__________ ...JI
LInearity
.,.....-Adjustment
+VS
--=--+--ll--+--=-+--~- --- - tP---]
10kn
220kn
R3
(680kO)
56kil
I
I
l (b)
To
Safely
Input
91 AN2028/29-90
The parabolic voltage at (a) is integrated by "R2,
C2" network and used for "S" correction.
The "S" waveform voltage at (b) is added to the
. saw-tooth voltage at (c). The "S" level is determined
by "C2, R2, R3" network.
53/55
---------------- ~~~i@~g~~~~~~ ----------------
1147
APPLICATION NOTE
piing capacitor "Cp" will reach an excessively high
value.
To avoid such situation, the voltage at point (a)
should be applied to the "Safety" input pin 28 after
it has gone through the matching network "R4, R5".
V1I1.6.3 - Frame safety
In case of failure in the loop, the thyristor may
remain turned-off while the inverse parallel-connected diode conducts. This will result in a hazardeous situation where the voltage across the cou-
VIII.7 - Frame scanning in class B with flyback generator
VIII. 7.1 - Application diagram
Figure 92
Pin 14
200V (TEA 2029)
+24V
ch ,mnf '~ . . . ._-,.
TEA 2029C
~
470nF
I
1nF
13kn
220
Q
:
--{D---
2 --
3
1SnF
10kQ
_ _ ...JI
150kQ
680kQ
470kQ
N.C.
+12V
10kn
Frame saw· tooth
_-=1---+
3.3kn
2.2kn
100nF
Vertical
1000~F
Phase
Shift
15kn
'-----t::>-------J 100n
Verticat Amplitude
Adjust
91AN2028f29·91
54/55
---------------~~~~©~~~~~l:l ----------------
1148
~ ~ X
I:
....
CD
CD
I\)
-0
-0
!!l."'O
_. "'0
o~ -r
:;:
(")
s:~
-10
mz
~O
~:;
"","G>
JJ
l>
5:
~
",en
~;
:=131:
~en
,~O
C0lZ
TEA 2029C
»
"'0
"'0
r-
a!.
Secondary Ground (isolated from mains)
-&
Primary Ground (connected to mains)
n
»
-i
o
Z
Z
.....
.j>.
co
(J1
(J1
0;
(J1
S
m
APPLICATION NOTE
TEA5170
SECONDARY CONTROLLER FOR MASTER-SLAVE STRUCTURE
By : T. PIERRE
SUMMARY
Page
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
"
11.1
11.2
11.3
OPERATING PRINCIPLES OF MASTER-SLAVE STRUCTURE .................
MASTER-SLAVE MODE .................................................
BURST MODE ........................................................
OPERATION OF A MASTER-SLAVE SUPPLY IN TV APPLICATION. . . . . . . . . . . . . .
2
2
2
3
III
111.1
111.2
111.2.1
111.2.2
111.3
lilA
111.5
111.6
DESCRIPTION OF TEA5170 .............................................
BLOCK DIAGRAM .....................................................
OSCILLATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation in free-running frequency mode .......................... . . . . . . . . .
Operation in synchronized mode ..........................................
ERROR AMPLIFIER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PULSE WIDTH MODULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTPUT STAGE ......................................................
Vcc MONITORING .....................................................
4
IV
IV.1
IV.2
IV.3
IVA
IV.5
IV.6
IV.?
IV.8
IV.8.1
IV.8.2
IV.8.3
IV.9
IV.10
TV POWER SUPPLY APPLICATION BUILT AROUND TEA5170 ................
MAIN APPLICATION CHARACTERISTICS ..................................
COMPONENTS EXTERNAL TO TEA51?0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FREE-RUNNING OSCILLATION FREQUENCY ..............................
ERROR AMPLIFIER COMPENSATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNCHRONIZATION SIGNAL MATCHING STAGE ...........................
SOFT-START PERIOD DURATION. . .. . . .. . .. . ... . . . .. . . . . . . . . .. . . . . . . . . . .
TRANSFORMER CHARACTERISTICS .....................................
OPERATION. . .. . . .. . . .... ... . . . . . . . .. . . . . ... . . . .. . . . . . . . . . . . . .. . . .. . .
START-UP.................................................. .... .....
STAND-By.................................................. ........ .
SYNCHRONIZED MODE ................................................
DELAY TIME IN SYNCHRONIZED MODE ......... : . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL DIAGRAM ................................................
?
?
?
8
8
9
9
9
10
10
10
10
10
11
V
V.1
V.2
V.2.1
V.2.2
V.2.3
DC-DC CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL DIAGRAM ................................................
OPERATION.. .. . . . .. . . . . . . . .. . . .. .. . ..... . .. . . . . . . .. . . . . . . .. . . . . . . . ..
Open-load Protection ...................................................
Short-circuit Protection ..................................................
Demagnetization monitoring .............................. . . . . . . . . . . . . . . . .
12
12
12
12
13
13
VI
CONCLUSION
13
AN408/0591
4
5
5
5
6
6
?
?
1/13
1151
APPLICATION NOTE
I - INTRODUCTION
• Burst mode (used during start-up and stand-by
phases)
The TEA 5170 is designed to work in the secondary
part of SMPS, sending pulses to the slave
TEA2164 which is located on the primary side. of
the main transformer.
The function of the regulation and synchronization
are carried out by the TEA5170.
An accurate regulated voltage is obtained by duty
cycle control.
The TEA5170 can be externally synchronized by a
frequency higher or lower than the free-running
frequency. This feature is particularly suitable for
TV applications.
11.1 - Master-Slave mode
In this configuration, the master circuit located on
the primary side, issues PWM pulses used for
output voltage regulation. These pulses are sent
via a pulse tranformer to the slave circuit (Figure 1).
In this mode of operation, the falling edge of PWM
signal may be synchronized by an external signal
(e.g. by line flyback signal in TV applications).
11.2 - Burst Mode
During start-up and stand-by phases, no regulation
pulses are issued by the master circuit and thus the
slave circuit operates in burst mode. In this config- .
uration, the slave circuit determines the switching
frequency and the burst period. (See figure 2)
\I - OPERATING PRINCIPLES OF
MASTER-SLAVE STRUCTURE
This architecture offers two modes of operation:
• Master-slave mode (for normal operation)
Figure 1
PWMh
Signal
Pulse
Input
Base
Current
t
o
•
~
_
y --.L>...--.,..,.r-----t"-----r7-
11/1
V
[k/)
V
~
91AN5170·01
Figure 2 : Burst Mode Operation
Period. . - _I
I- - - Burst
typ .. 30ms - - - - ;
t
I
I
I
I
I
I
I
I
I
1-- Switching
Period
I
COLLECTOR CURRENT ENVELOP
DETAIL OF ONE BURST
91 AN5170·02
1152
APPLICATION NOTE
11.3 - Operation of a Master-Slave Supply in
TV Application
The arrangement generally employed is depicted
in Figure 3. On the secondary side, a microcontroller is connected to the remote control receiver
which issues control signals for stand-by and normal modes of operation. (Figure 4).
• In stand-by mode, the device power consumption is low (few Watts). The master will no longer
send any control pulses to the slave which will
consequently begin operating in burst mode.
Power supply regulation is performed by the slave
circuit through the auxiliary winding.
• In normal mode of operation, the master circuit
issues the PWM signal for regulation. The
power supply operates in master-slave mode.
The master circuit is simultaneously synchronized with the line flyback signal.
• Power supply start-up. As soon as the
VCC(START) threshold is reached, the slave circuit begins operating in burst mode. While the
secondary voltages are being stabilized, the
microcontroller holds the TV set in stand-by
mode.
Once the start-up phase is terminated, the set may
remain in stand-by mode or switch into normal
mode of operation.
Figure 3
_____
~
_______
____ e
_______ M
______ 0
_________ 0_
00
eo
00.°.
______
00
____
eo
00
_0
00
00
0_
00
0
_ _ _ _ _ _ -.
Muting
Conlrol
R
MAINS
INPUT
,
. P2
c
Pl : Output voltage adjustment in normal mode
Pulso
Transformer
pz : Output voltage adjustment In stand-by
__ - _____ - ___ - __ - - - - - - - - - - - - - . __ - - - _.0 _. __________ •• _. __ • ____ • ____________________ . - - - - - '
91 AN5170-03
3/13
---------------- ~ ~~~":;m~,l'~l~2~ ----------------
1153
APPLICATION NOTE
Figure 4
TEA 2164
VCC1START)
Vee Voltage
CD voltage
pP supply
®
Stand-by
L~_~E_LAY_~--+,i.,--0~_P~~--jl..,-~~
itl
: 12
)II
t
---- start-up-------I-S-t-'"-d_-b·;+I-·---N-"-m'atf':p~.-,,-tlO-"---~·-tI---S-ta-"-d--b-y-Z70• T BURST: burst period
• TDELAY: time COrlStanl g~nera\ed by f1P
*B
*b
: burst envelop lout 01 regulalLQn)
SYSTEM DESCRIPTION: WAVEFORMS
: burst envelop (w,lh stand-by regulatJon)
:: I cQmm~nds Is~ueo
by uP
91 AN5170-04
III - Description of TEA 5170
The TEA 5170 is a fixed frequency PWM signal generator operating in voltage mode regulation.
111.1 - Block Diagram
Figure 5
LOGIC
(Sync.)
-<1,,+
POWER
OUTPUT
STAGE
~
L.._ _ _- ' COMPARATOR
Inverting
Input
Your
GND
Vee
PWMOUT
91 AN5170-05
4/13
1154
APPLICATION NOTE
111.2 - Oscillator
The oscillator generates a linear saw-tooth signal
and sets the free-running frequency. This oscillator
can also operate in synchronized mode.
111.2.1 - Operation in free-running frequency
mode. (See figure 6).
111.2.2 - Operation in synchronized mode
The oscillator is synchronized by forcing the sawtooth return.
Enabling the synchronized mode (Figure 7)
The synchronized mode is enabled when the signal
pulse on pin 8 (Rt) coincides with the oscillator
saw-tooth return. The "Ct" capacitor charge current
is then multiplied by a factor of 0.75.
The TEA5170 will remain in synchronized mode as
long as the synchronization pulses fall within the
following window:
(0.8 T1 + T2) < TSYNC < (1.33 T1 + T2)
Where:
• T1 : Ct charge time in non synchronized mode.
• T2 : Ct discharge time
Synchronization signal (Figure 8)
Synchronization signal is applied to pin 8 "Rt" and
the capacitor "Ct" is discharged when voltage "VAt"
exceeds the "2.7 V" threshold.
Figure 6
.----...:......,
VCI~__________
-----2V
V,hl = IV
VII12 =2V
-------- - - -
..JL
n·
"~:"1
1-----'
---tv
I
I
I
I
I----Tl---,~
I
..
I
1- T2
! - - - T : period~
Tl =0,5xRl xC,
T = C, (0,5 x R, + 1330)
T2= 1339xc,
91 AN5170-06
Comment:
The internal current generator used to charge the
"Ct" capacitor is disabled for the entire phase where
"VRt" is higher than 2V. Thus, in order to maintain
the saw-tooth shape of the oscillator signal, the
"VAt" voltage should fall to 2V before the capacitor
"Ct" full discharge.
Figure 7
, -t'--------' ' - - - - - ' ,---''-'------'--- ~ ~ V
-
ASYNCHFlONTZED
MODE
)
'<
..
91 AN5170-07
5/13
--------------- ~~~~~~~~~~ -------------~
1155
APPLICATION NOTE
Figure 8
2:R~1- --- ----A~
,
,
,
,
,
,
91 AN5170-08
111.3 - Error Amplifier (Figure 9)
The on-chip error amplifier can be accessed
through its inverting and output terminals.
The non-inverting input is internally tied to reference voltage level.
Comment:
An internal inverting amplifier sets the correct
phase polarity of the error amplifier output signal
for regulation.
111.4 - Pulse Width Modulation (Figure 9)
The TEA 5170 is a PWM signal generator operating
in voltage mode. The pulse width is determined by
comparing the error signal "VOM" with the oscillator
saw-tooth.
When the error signal "VOM" exceeds the regulation
range, internal threshold components' will set a
minimum conduction timetoN(MIN) and also limit the
maximum conduction time tON(MAX).
At initial start-up, a soft-start function implemented
by linear charge of soft-start capacitor "C(S-STARTJ"
is used to vary gradually the tON(MAX) threshold. The
output pulse width varies from tON(MIN) to tON (MAX)
nominal value for VC(S-START) voltage variation of 0
to 2V.
Figure 9
Amplifier
Output
PWM
Inputs
1_ _ _ _ _ _/\r\
VpIN5
, - - - Vp1N6
~/'\.
lz\Z; \
t LJ
I:
I
J.%~I
VOM ( "
I
I
I
LI._ .1_ D.
91 AN5170-09
6/13
-------------~ ~~~~~~~~2~ --------------
1156
APPLICATION NOTE
Figure 10
1mA
1mA
-~-- --
3-
LOGICAL
CONTROLLER
91AN5170-10
111.5 - Output Stage (see figure 10)
IV.1 - Main Application Characteristics
Characteristic
The output stage operates in on/off mode. For a
supply voltage higher than 8V, the output signal
value is independent of the supply voltage. (Typical
value: 7V)
Input voltage
170VAC to 270VAC
Output power
20Wto 120W
Output power in stand-by
mode
111.6 - Vcc Monitoring
Vcc Rising : When Vcc reaches the value
"VCC(STARTj", an internal switch enables the operation of the output stage and the soft-start capacitor
begins charging.
The internal logic circuitry becomes operational
before Vcc has reached the "VCC(START)" value.
Vcc Falling: When Vcc falls below the "VCC(STOP)"
level, the negative output stage is switched-on, the
transistor is turned off and the soft-start capacitor
is discharged.
IV - TV POWER SUPPLY APPLICATION BUILT
AROUND TEA5170 (Figure 15)
General structure and operational features of this
power supply were outlined in section 1.
The details covered below apply to a power supply
configuration using the slave "TEA2164" device.
(Refer to TEA2164 data sheet and application note
"AN40910591 " for further details).
Value
Switching frequency
1Wt06W
32kHz
Synchronization on line flyback Signal (positive)
IV.2 - Components External To TEA5170
Component Value Calculation
Also refer to TEA2164 application note "AN409/0591" for calculation methods applicable to
other power supply elements.
The external components determine the following
parameters:
• Operating frequency
• tON(MIN)
• Soft-start
• Error amplifier gain
Ideal Values
•
•
•
•
Period of operation "Tosc" : 32~s
tON (MIN) duration : 1.2~s
soft-start duration: 20ms
Error amplifier gain:
• DC gain GDC = 35
• AC gain at 1/10 x Tosc: GAC = GDc/5 = 7
-------------- ~ ~~~~~ru~~_~U{~~ -------------7/13
11.57
APPLICATION NOTE
IV.3 - Free-Running Oscillation Frequency
Where:
For efficient use of TEA5170 and TEA2164 synchronization windows, the periods of both devices
are determined as folows :
C _ tON(MIN) - 0.5 x 10-6
t1330
TSYNC
TOSC(5170)
= 1.06
T OSC(2164)
=
= 105kQ (1%)
= 560 pF (2%)
IV.4 - Error Amplifier Compensation
TOSC(5170)
1.223
Where:
• TSYNC : line flyback signal period
• T OSC(5170) : TEA5170 free-running period
• T OSC(2164) : TEA2164 free-running period
• A high DC gain is required for good accuracy.
• For stability reasons, the AC gain must be attenuated so as to avoid injection of the switching
frequency component into the regulation loop.
.
R2 + R1
• DC Gain: GDC = R3 x R2 x R1
1
Numerical Application
'.
• AC Gain. GAC =
Period of synchronization signal being
T SYNC
• Rt
• Ct
= 32/-1s :
1
R3 +.,...-C
R2+ R1
x R2 x R1
JOl
TOSC(5170)
TSYNC
1.06
30.211S
TOSC(2164)
TOSC(5170)
1.223
30.2
1.223
24.711S
The TEA5170 free-running period is determined as
follows:
TOSC(5170)
R3X~
= Ct (0.5 x Rt + 1330)
Assumptions:
• R2 > > R 1 since VOUT > 10 VREF so the value of
R2 does not modify the result of calculation and
only R1 and R3 influence may be taken into
consideration.
• R1 = 2.2kQ, R3 = 75kQ
• With cut-off frequency in AC regulation mode:
• fc = 10
1
x
T
osc
~ C = 2.2nF
Figure 11
c
t
VOUT
I
91AN5170·11
1158
APPLICATION NOTE
IV.5 - Synchronization Signal Matching Stage
(Figure 12)
lower than the saw-tooth fall time.
Thus, for a line flyback signal amplitude of 50V :
The synchronization signal is generated from the
line flyback.
The pulse amplitude is given by :
R = 6.8kQ, Rp = 75k£2, C = 150pF
VPIN8(MAX) = _._R_ With Rt > > R
VSYNC
R+ Rp
The pulse time constant is (R+ Rp)C and should be
Comment:
Practical and theoretical values may differ slightly
since the rise time of the line flyback signal is not
generally negligible.
Figure 12
EHT
TRANSFORMER
~c
91 AN5170-12
IV.6 - Soft-Start Period Duration
In this application, the duration of soft-start is
around 20ms,
With:
6
o CIS-START) = TIS-START) x 2 x 10- = 47nF
Figure 13
ffil
a
orr
O[X
3
A 6J1" :',,11
I,'7
°
~
o[b~
IV.7 - Transformer Characteristics
(Reference: G4453-02 OREGA)
Winding
Pin
Inductance
np
3-6
680 ~H
nAUX
7-9
7 ~H
n2
19-13
592 ~H
n3
19-20
12 ~H
n4
14-17
5 flH
n5
22-21
25 ~H
7
0
°
",22
1
!fi!1'
-------------- Fii ~~~;j~~~~g~ - - - - - - - - - - - - -9/13
1159
APPLICATION NOTE
IV.S - Operation
IV.S.3 - Synchronized Mode
IV.S.1 - Start-Up
The power supply of TEA5170 begins rising gradually upon initial start-up of the primary circuit.
When Vee reaches the value Vee(START) = 4V, the
oscillator has already begun running and the softstart capacitor "C(S-START)" begins charging. The
conduction time is tON(MIN) and rises gradually.
IV.S.2 - Stand-By
This function is externally activated by grounding
the "stand-by" input thereby disabling the power
supply of TEA5170. (Figure 15).
To return to normal mode of operation, this pin
should be left floating.
The differentiator at synchronization input will
transform the line flyback signal into a rectangular
pulse whose time constant is around 1 ms.
In this mode of operation, there is a lapse of time
between the falling edge of the synchronization
signal and the real transistor turn-off (Figure 13).
In TV applications, this time should be less than the
line fly back duration so as to avoid the occurrence
of on-screen visible disturbances.
t1 and t3 times are specific to TEA5170 (t1 + t3 =
SOOns typ.)
t4 is specific to the primary circuit (= SOOns typo with
TEA2164).
Only t2 = tON(MIN) and t5 = tSTG of the switching
transistor can be modified according to individual
application requirements.
IV.9 - Delay Time In Synchronized Mode
Figure 14
~-'~
SIGNAL
VAt
k\
------2.7V
2V
I :~ - - - - - .
II I
II I
, I I
~~
I--if-Tl
OSCILLATOR
VOLTAGE
(TEA 5170)
:
I .
_ _- - - - - - - - - - - - - I,
I
I
~ r
v,&~'/;1, 1
1----..".:
(TEA 5170) _
T3
.
oJ~, lL~_______~~i.-~__-.________________________~
!UI
I
I
COLLECTOR
CURRENT
"tI
"tI
r-
n
~
5z
z
S
m
APPLICATION NOTE
v - DC-DC CONVERTER
(9V ± 40% => 24V , 1 .5W) (Figure 16)
V.2 - Operation
This low power converter employs a transformer
wound on a low-cost ferrite former.
The configuration is protected against open loads
and short-circuits.
Transformer characteristics
• The period of operation is determined by Rt and
Ct components.
• Minimum conduction duration: 0.6 ~s
• Free-running period: 29 ~s
• Soft-start period duration: preset at 100 ms.
V.2.1 - Open-load Protection
• Primary inductance: 53.5 ~H
• Transformation ratio for 24V : ns I np = 2
Regulation Characteristics
• Line regulation at 4.9V to 15V : 24V ± 0.22%
• Load regulation for (O.4PMAX - PMAX) :
24V± 0.12%
• Power range: 0.24W to 1.6W
• Efficiency: 40%
In case of low load values, the minimum conduction
time tON(MIN) with respect to the period of operation
is too high to maintain the output voltage at its
nominal value. The only solution to stabilize the
voltage is to increase the period of operation by
reducing the charge current of the oscilator capacitor Ct. This is obtained by injecting additional current into resistor Rt as soon as the output voltage
VOUT rises.
V.l - Electrical Diagram
Figure 16
5V~~3V
---...----------------'1 .
Np
lN4148
r-----t-----t-I
2~gvF., ~b ~J
•
t-----------------~
24V
_.....
3.9kO[!
j;
'(r
1--:1-
I
I
BY10~;OO ~
Ns
J 47ko
... _.,,-
91AN5170·16
~1_2/_13_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~(;~9~~2~
1162
--------------
APPLICATION NOTE
V.2.2 - Short-circuit Protection
When the current through transistor becomes substantially high, the transistor is saturated and induces a high dlc/dt . The diode on switching transistor base is then forward biased and begins
deviating a portion of the base current. This phenomenon is self amplified and therefore results in
rapid transistor turn-off.
V.2.3 - Demagnetization Monitoring
In order to avoid magnetic flux runaway, thetransistor should be driven into conduction only once
the transformer has been fully demagnetized.
While the transformer is being demagnetized, the
secondary-connected rectifier diode is forward biased and thus maintains the error amplifier output
at 0 potential. The allowed conduction period is
consequently tON(MIN).
VI - CONCLUSION
The TEA5170 requires a very simple configuration
and yet offers excellent regulation quality combined
with synchronization possibility for flyback-type
converters.
The TEA5170 can be used in converters operating
at 16 kHz to over 100 kHz frequency range.
Access to error amplifier and soft-start input are
some of the remarkable features offered by this
device whose application areas are by no means
limited.
The TEA5170 belongs to the family of master
controller devices characterized by their outstanding flexibility of use and application performances.
- - - - - - - - - - - - ~ ~~S-TIJ~~~~~. - - - - - - - - - - -13/13
1163
APPLICATION NOTE
TEA2164
MASTER-SLAVE SMPS FOR TV & VIDEO APPLICATIONS
By : B. O'HALLUIN
Page
SUMMARY
INTRODUCTION
2
1.1
1.1 .1
1.1.2
1.1.3
1.1.4
MASTER-SLAVE STRUCTURE . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . .
Fundamentals . . . . . . . . . . . . . .
Principles of regulation . . . . . . . . .
Advantages offered by this architecture.
2
2
3
1.2
STAND-BY IN BURST MODE
II
THE TEA2164 INTEGRATED CIRCUIT . . . . . . . .
4
11.1
DESCRIPTION . . . . . . . . . . . . . . . .
4
11.2
TEA2164 SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . .
5
11.3
PIN CONFIGURATION
11.4
11.4.1
11.4.2
OPERATING MODES.
General description ..
Synchronized mode ..
11.4.3
Burst mode . . . . . . . .
5
5
5
6
6
III
APPLICATION EXAMPLE
111.1
CHARACTERISTICS & APPLICATION DIAGRAM.
.....
111.1.1
Characteristics
111.1.2
Application diagram . . . . . . . . . . . . . . . .
111.2
TRANSFORMER CALCULATION
111.3
111.3.1
111.3.2
111.3.3
111.3.4
111.3.5
111.3.6
SWITCHING TRANSISTOR & ITS BASE DRIVE . . . . . . . . .
Current limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
...... .
Switching transistor . . . . . . . ..
Switching aid (snubber) network . . . . . . . . . . .
Base drive . . . . . . . . . . . . . . . . . . . . . . .
Reopy Resistor calculation . . . . . . . . . . . .
Calculating the value of resistor connected to V+ .. .
111.4
111.4.1
111.4.2
INPUT PULSES & OSCILLATOR . . . . . . . . . . .
Input pulses (Pin 6) . . . . . . . . . . . .
Oscillator (Rosc ,Case - pin 7 and pin 8)
111.5
111.5.1
111.5.2
111.5.3
111.5.4
STAND-BY . . . . . . . ..
. .....
Very low frequency oscillator . . . . . . . . . . .
Regulation in stand-by mode . . . . . . . . . . . . . . . .
Maximum power in stand-by operation . . . . . . . . . . .
Booster circuit for higher stand-by output power . . . . . .
AN409/0591
.......... .
............... .
3
3
3
7
7
7
7
10
12
12
12
13
13
14
15
15
15
15
16
16
16
16
17
1/30
1165
APPLICATION NOTE
SUMMARY (continued)
Page
111.6
111.6.1
111.6.2
111.6.3
START-UP ..
Start-up resistor
Selfcsupply ..
Secondary controller circuit start-up.
18
18
18
18
111.7
111.7.1
111.7.2
111.7.3
111.7.4
PROTECTION FEATURES
Overload protection . . . . . . .
Short-circuit protection . . . . .
Repetitive overcurrent protection
Overvoltage protection ..
19
19
19
19
19
111.8
OSCILLOGRAMS . . . . .
20
IV
APPLICATION VARIANTS
26
IV.1
ALL MAINS APPLICATION
26
IV.2
117 VOLTS APPLICATION
28
IV.3
APPLICATION WITHOUT STAND-BY
29
I - INTRODUCTION
The TEA2164 is a Switching Power Supply Controller circuit designed to operate in Master-Slave
structure.
This device is located on the primary side of power
supply and requires the addition of other controller
device such as TEA2028 or TEA5170 connected
to the secondary side.
The main application of this circuit is in switching
mode power supplies operating in discontinuous
mode flyback configurations used in TV receivers
at 60 W to 150 W power ratings.
The device incorporates a "Burst Mode" feature
which offers excellent functional efficiency in
"Stand-by" mode of operation.
1.1 - Master-slave structure
1.1.1 - Block diagram
Figure 1
MAINS
-AcT
IN
SLAVE
91AN2164·01
2/30
- - - - - - - - - - - - - - {:7fi
1166
~~~~~JHg~~Hr:t
--------------
APPLICATION NOTE
1.1.2 - Fundamentals
The "Master" device located on the secondary side
of the power supply performs the following functions:
- Output Voltage Control: Monitors the Conduction
Period of the "Slave" circuit so as to provide
Output Voltage Regulation as a function of Mains
and Load variations.
- Switching Frequency Synchronization on Horizontal Scanning Frequency
The "Slave" circuit provides for the following functions:
- Power supply start-up
- Optimized Switching Transistor base drive
- Power supply regulation during stand-by operation
- Protection agai nst
• Overloads
• Short-circuits
• Open-loads
• Missing control pulses normally delivered by
secondary block.
1.1.3 - Principles of regulation
A fraction of the voltage to be regulated is obtained
from a voltage divider network and compared to an
internal reference voltage. The error voltage delivered by comparator is used to modulate the duration of the output pulse delivered by PWM (Pulse
Width Modulation) Controller. The frequency of
these pulses is determined by an internal oscillator
synchronized on the horizontal scanning of the TV
set.
PWM output signal is differentiated and forwarded
towards the primary controller via a small low-cost
pulse transformer which provides galvanic isolation
between primary and secondary sections.
The differentiated positive signal pulse will turn the
transistor on while the negative pulse will turn it off.
Conduction period variation will determine the
amount of energy stored within the transformer
during each cycle so as to maintain a constant
output voltage whatever load and mains voltage
variations.
1.1.4 - Advantages offered by this architecture
The "Master-slave" architecture offers the following
advantages:
- Excellent output voltage regulation
- Main output voltage is not influenced by significant variations of auxiliary voltages (no sound
interference within image display, even at audio
power levels as high as 2 x 30 W).
- The coupling between transformer primary and
secondary windings is no longer a critical requirement for regulation; which allows use of low-cost
transformers (such as SMT5 series manufactured by OREGA)
- Synchronization on TV line scanning frequency
will suppress anyon-screen interference produced by power transistor turn-off, and eliminate
the need of additional output voltage filtering
components.
- All power supply protection features are implemented on primary. side thereby allowing efficient
and fast response to :
• Current limitation
• Overvoltage protection
• Persisting overloads
- Other protections can be implemented to limit or
disable the duration of regulation pulses issued
by PWM, in case of failure detected within any
section of the TV set.
1.2 - Stand-by in burst mode
The secondary power required in stand-by mode is
often quite low (1 W to 5 W in majority of cases).
Instead of operating the system at low tON duration,
which is a difficult task with discontinuous mode
transformer, the TEA2164 offers a "Burst Mode" to
perform the stand-by function.
- T 1 : Burst duration
Figure 2
COLLECTOR
CURRENT
1c'
--T1-
T'----91 AN2164·02
- T 2 : Burst period (period of VLF oscillator)
The Tl/T 2 ratio is fixed internally.
The TEA2164 allows the switching transistor to
conduct only for typically 13% of the internal VLF
oscillator period.
A pulse train ''Tl'' called "Burst" is thus obtained.
The repetition period "T2" can be set externally by
capacitor "Cl" connected to pin 1O.
In this mode of operation, the power transferred to
the secondary windings is very low.
The collector current envelope has been optimized
to yield efficient soft start and to minimize the audio
---------------- ~~~~;~~~~R~ ---------------3/30
1167
APPLICATION NOTE
noise generated by switch mode transformer. Also,
the free-running frequency "fose" is shifted towards
20kHz so as to eliminate all audible noise in standby mode.
In this mode, the secondary output voltages are
regulated by a feed-back loop on primary side. The
TEA2164 will switch from synchronized mode (regulation by mastercircuiton secondary side) to burst
mode (stand-by) as soon as the synchronization
pulses, normally delivered by secondary block, are
no longer available.
It is therefore obvious that the most efficientsolution to implement the burst mode is to cut supply to
master which will consequently be unable to deliver
any synchronization pulse.
The stand-by function in burst mode offers the
following advantages:
- Eliminates the need for auxiliary stand-by power
supply and therefore its costly building elements
such as stand-by mains transformer, relay or
other specific components.
- Good power supply efficiency, thanks Ito burst
mode, allows low mains power consurl1ption in
stand-by.
11- THE TEA2164 INTEGRATED CIRCUIT
11.1 ' Description
The TEA2164 is cased in a 16-pin OIL package.
The 4 center pins (2 on each side) are connected
together and used to evacuate the heat.
The device includes the following functional
blocks:
- A free-running oscillator which can be synchro-
nized on the frequency of pulses issued from
secondary.
- A Very Low Frequency (VLF) oscillator used for
burst mode.
- An input stage to shape positive and negative
input pulses.
- An output stage with two complementary amplifiers:
• one, to provide the positive base current to turn
the switching transistor on,
• the other,to provide the negative base current
requi~d to turn the transistor off.
The positive base current is proportional to the
collector current.
- A sophisticated protection system featuring:
• Collector current limitation at 2 threshold levels
• A device to memorize the occurrence of overloads and short-circuits, and to disable the
power supply completely after a pre-determined
time constant.
• Vee monitoring device with 2 thresholds :
- Upper threshold: for overvoltage protection
- Lower threshold with hysteresis :. for system
start-up
- Supply Voltages:
• one pin for general supply (Vee)
• one pin for power supply of the positive output
stage (V+)
• four pins for power supply of the negative output
stage (V-)
(according to application type, these pins can
be grounded)
• one pin for ground connection
·~4/~3~O_________________________ ~~~~@~~~~~~~~
1168
____________________________
APPLICATION NOTE
11.2 - TEA2164 Simplified block diagram
Figure 3
Vee
TEA 2164
GROUND
91 AN2164·03
11.3 - Pin configuration
1
Ground
2
Icopy
3
C2
4
v-
5
v-
6
Input
7
Rosc
8
Cosc
9
R1
10
Cl
Batwing DIP16
11
ICMAx
12
v-
13
v-
14
Output
15
v+
16
vcc
(plastic package)
11.4 - Operating modes
11.4.1 - General description
The TEA2164 can operate in two distinct modes:
- "Normal" (or synchronized) mode:
Synchronization and regulation by secondary
controller circuit.
• "Burst" mode:
In this mode, the TEA2164 operates as a standalone device.
This mode is used upon start-up and in stand-by
mode.
5/30
------------------------------ ~~ii@~9~~~~©~ -----------------------------1169
APPLICATION NOTE
Two additional modes are also available:
- Long interval safety mode : the device is fully
turned-off although it is correctly supplied
(pin 3 capacitor has stored the occu rrence of
repetitive overcurrent)
- Start-up mode: the device is in low-consumption
mode, its Vcc has not yet reached the VCC(START)
threshold.
The normal start-up sequence is :
• Start-up Mode
• Burst Mode
• Synchronized Mode
11.4.2 - Synchronized mode
In synchronized mode, control pulses delivered by
secondary block are differentiated and then applied
to pin 6 input.
The positive pulse will synchronize the internal
osciJlator by discharging the "Cosc" capacitor,
which will generate a constant width pulse called
"START" signal to be applied to positive stage output
amplifier.
Similarly, the negative input pulse generates a
"STOP" pulse which is applied to negative stage
amplifier whose output is used to turn-off the
switching transistor.
The "START" signal is disabled under following conditions :
- voltage applied to Vcc terminal is higher than
+15V
- current protection device has detects a collector
current higher than "lc(M2)".
If the current reaches "lc(M1)" threshold, the current
limitation device will generate the "STOP" pulse.
Figure 4
IC(M2)
OR
Vee 2: 15V
IN
14 uuT
INPUT STAGE
le(M!)
1c(M2)
91AN2164-04
11.4.3 - Burst mode
If no control pulses are present at device input
terminal, the TEA2164 will operate as stand alone
in burst mode.
The switching frequency is given by the internal
oscillator whose value depends on external components "Rosc" (pin 7) and "Cosc" (pin 8).
The "START" signal is generated by the oscillator
and is used to turn the switching transistor on.
Transistor turn-off is performed by "lc(M1)" current
limitation through soft-start block or by "tON(MAX)"
value set by resistor "R1" connected to pin 9 (or
voltage applied to pin 9).
The VLF oscillator will enable the "START" signal for
13% of its periode duration.
6/30
-------------i:ii ~~iir;m~~~'1~~
1170
----------~---
APPLICATION NOTE
Figure 5
OSClLLATOR
IC{M2)
OR
Vee
~
15V
14 OUT
VERY LOW
FREQUENCY
OSCILLATOR
91 AN2164-0S
III - APPLICATION EXAMPLE
(120 W - Discontinuous mode flyback power supply with stand-by in burst mode)
111.1 - Characteristics & application diagram
111.1.1 - Characteristics
- Discontinuous mode fly back SMPS
- Standby function using the burst mode of
TEA2164
- Switching frequency:
• Normal mode: IS62SHz (synchronized on horizontal deflection frequency)
• Stand-by mode: 19kHz
- Nominal mains voltage: 220VAC (SOHz or 60Hz)
- Mains voltage range: 170VAC to 270VAC
- Nominal output power: 120W
- Mains power consumption:
• Normal mode: 150W max
• Stand-by mode : SW (with 3W at secondary
side)
- Efficiency:
• Normal mode: 8S% (under nominal conditions)
• Stand-by mode: 60%
- Regulation performance at high voltage output:
• better than O.S% versus mains variations of
170VAc to 270VAC
• better than O.S% versus load variations of 3SW
to 120W
- Overload and short-circuit protection with complete power supply shut-down after a pre-determined ti me constC!nt
- Open-load protection by output overvoltage detection
111.1.2 - Application diagram
The first diagram illustrates the primary block built
around TEA2164.
The system is set into stand-by mode of operation
by the switch connected to + ISV supply.
Regulation pulses can be generated by a PWM
device such as TEAS170 or delivered by a deflection circuit such as TEA2028 or TEA2029 which
includes on-chip power supply regulation.
The second diagram depicts the full application
diagram for a complete TV set power supply and
scanning built around TEA2164 and TEA2029.
A microprocessor will introduce lOOms delay interval for the system to start-up in stand-by and then
to switch into normal mode (synchronized and
regulated by TEA2029).
7/30
-------------- ~ ~~~@m~~'Ir~2c~ --------------
1171
APPLICATION NOTE
Figure 6: TEA2164 typical application
OREGA
Fusa
'.6A
Q •• '73.04
r----,
4 x 1N4007
BY216
I
220VAC ± 200/..
Malns Input
33ka
(1W1
'OOuF
365V
300""
100ka
(2W1
BA157
'BA157
.25V
BA157
~--~r-~---------- ,2A
(NldlG'
110
kn
~GlIOUND
a,2m
(1 WI
330u
100U
"V Small Signal Primary Ground
~ Power Primal)' Ground
ClSecondsty GroUnCl (isQlarecf from Mains)
...r-L
- r:-.-..r.----ic:Jf----.......-
l--;I;:
REGULATION
-
91 AN2164·06
1172
"e::
to"
iil
.....
-..J
220VAC
err
Mains (nput
(f)
mAHSFOR~R
300kn I
I
1
jJi--IIQ!
2, 47~F
385V
I
"'
SA 157
I
r
.
•
I
LiNE .24V
I..!...., FLYBACK
'.
s:
\J
(f)
Qo
Cl.
~
CD
no"
:::J
(")
o
3
"0
CD
r0m
"0
~
"Q.
f
.!..
~cn
Cln
0en
rq,
~i!
0
!li
8=:
I
0"
!'l.
0"
:::J
Cl.
TEA 2164
0;"
(Q
iil
~~3
~cn
~~
;100nF
3
e.
TEA 2029C
»
"'\J
"'\J
r
(5
V]....
~
}>
z
~
~
-..J
W
~
a
~
6
""
AGC
.....-----....v"",-"
IT '" 1~0- -- +r-10r-:
•
VIPIN 6)
IC:
~
IC(MAX)
.
~
t
t
I
r-~a--~7I I
I
I:
i
V{PIN III
!
_"
t
+:
;
" t
I!
\
~
Vc{Ml)~--~~---,
'
I
~
I
I
I
I
-!--'-
Is
The "Rs" resistor sets the switching transistor collector current limitation value. Power supply reliability is directly dependent on the value of this
resistor, which is calculated as a function of the'
maximum power required from the secondary
winding.
Lets set the secondary power limit at 150W value:
PIN
POUT
= -n- =}
PIN
(with efficiency n
= 175W
91 AN2164-09
84
7+
IC(MAX) = 00'2
200 -3 X 4 x 10-6 = 3.6A
.
1.55 x 10
At maximum mains voltage level, the slope is
sharper and the maximum current therefore becomes:
I
0.84
380
4
C(MAX) = 0.27 + 1.55 X 10-3 x
10-6
X
41A
=.
111.3.2 - Switching transistor
= 0.85)
IC(MAX) =
2PIN(MAX) x T
Lp
IC(MAX) =
_ 12 x 175 x 64 x 10\I 1.55 x 10-
6
3
= 3.8A
The storage time at this current value is approximately 41ls (with BU508A).
The collector current slope at nominal mains voltage is 0.2A!lls .
.
The current )imitation threshold level must therefore be fixed at 3A.
The "IC(M1)" voltage threshold is typically 0.84V :
therefore: Rs = 0.:4 = 0.280
In practice, the selected value is Rs = 0.270
At minimum mains voltage level, the slope is
smaller and the maximum current therefore becomes:
It was demonstrated that under normal operating
conditions, the maximum collector current value is
around 4.1 A while the maximum collector voltage
is approximately 530V.
Factors such as the overvoltage produced at the
time of transistor turn-off, transformer leakage inductance and peak currents generated in the event
of short-circuits, must be also taken into account.
At the time of transistor turn-off and under worst
case conditions (maximum mains voltage, significant overload), the "VCE" voltage across the transistor can reach 1OOOV.
Therefore, a transistor with VCES ~ 1200V must be
seleCted.
In case of short-circuit, transformer is magnetized
and the collector current value will reach 5A (with
0.270 measurement resistor and 1.35V typo VC(M2)
threshold).
Therefore, a transistor with IC(MAX) ~ 7 A must be
selected.
12/30
--------------'-W ~~~@m~,r~'Ic~~?c~ --------------1176
APPLICATION NOTE
• R = 220Q
• D: BA159
• T: BU508A
Whatever load and input voltage conditions, it must
be ensured that the system will operate permanently within the safe operating area of the transistor.
The BU508A and equivalents are perfectly suitable.
111.3.3 - Switching aid (snubber) network
The "Snubber" network is built using a combination
of "R , C , D" components to limit the dV/dt slope
and to reduce the collector current rise up at the
time of transistor turn-off.
Switching losses at turn-off which are proportional
to "V x I" product are thus minimized.
• C = 2.2nF
Figure 10
A 1OOQ resistor connected between transistor base
and emitter terminals will improve the voltage
behaviour.
lOon
91 AN2164·1 0
111.3.4 - Base drive
tive base current is necessary to turn it off.
A bipolar switching transistor requires a positive
base current to enter into saturation while a nega-
The shape of base current waveform is illustrated
in the following Figure.
Figure 11
19
I
I
3
:41
5
I
91AN2164·11
1 - Constant amplitude pulse to turn the transistor
on (duration depends on oscillator saw-tooth return)
2 - Base current proportional to the collector current
(Ieopy function on pin 2)
3 - Saturated base current to limit the circuit power
dissipation (function implemented through the re-
sistor in series with pin 15)
4 - On-chip delay interval of "0.7I1S" to prevent
simultaneous conduction of positive and negative
stages
5 - Negative base current to remove the charge
stored within base (storage time - duration of which
depends on type of switching transistor)
13/30
-----'---------- ~ ~i~@m~,.,,(~~9c~ --------------
1177
APPLICATION NOTE
Figure 12
91AN2164-12
• L = 2_5flH
• R = 100
• C = 47flF
• D : 1N4001
The base drive circuit is a "capacitive coupled"
device. There is therefore no need to apply a
negative voltage "V -" to pins 4, 5, 12 and 13 which
will be grounded. P.C.Board tracks connected to
these pins must be wide enough to allow efficient
evacuation of the power dissipated by device.
The positive base current goes through 3 diodes
connected in series. Capacitor connected across
these diodes will be charged to a value equal to 3
times forward diode voltage drop. This voltage is
sufficient to turn the transistor off.
This capacitor must be selected to withstand the
effective current through it, which is mainly the
negative turn-off current.
The inductor in series with base, limits the dlB/dt
slope· and thus the base current, at the time of
transistor turn-off. The inductance value must be
adjusted to yield efficient turn-off while the negative
current delivered by TEA2164 should not exceed
-1 .7 A . The 100 resistor connected across this
inductor helps the damping of base current oscillations at the beginning of transistor conduction.
Comment:
In order to avoid all problems at TEA2164 output
stage, it is recommended to connect a 1N4444
diode between the output terminal (pin14) and the
ground, as illustrated in Figure 12 above.
In case of capacitive drive and if a negative
voltage appears across output terminal (due to
inductor L), this diode will deviate the current
towards ground thereby preventing reverse bias
of the negative output stage.
111.3.5 - Rcopy Resistor Calculation
This input is used to set the switching transistor
forced gain, that is, to deliver the base current
necessary for a required collector current.
Input pin 2 can be considered as a virtual ground
terminal and therefore:
Rs x Ic = Reopy x leopy
Figure 13
91 AN2164-13
Also, the current gain between input (pin 2) and the
output (pin 14) is :
1000 => IB = 1000 x Icopy
The forced gain is therefore:
14/30
---------------------------1178
A forced gain of 2.25 (BU508A) with Rs = 0.270 will
yield: Rcopy = 6000
In practice, one would select the optimal value by
observing the dynamic aspect of the saturation
voltage on an oscilloscope. This is why Rcopy =
3900 is selected with BU508A.
~~~~~~~~~~~ ----------------------~----
APPLICATION NOTE
111.3.6 - Calculating the value of resistor connected
to v+
In order to prevent high current flow through the
integrated circuit and also to limit the power dissipation, the output stage is operated in saturated
mode in high positive output currents.
The maximum recommended positive base current
is 1.2A.
Selected maximum power supply voltage is + 12V.
Lets calculate the resistor value required to yield a
maximum current of +I A.
The voltage drop across three diodes connected in
series is typically 0.9V x 3 = 2.7V at IA.
The base-emitter saturation voltage of BU508A is
around 1V. The TEA2164 output stage voltage drop
is approximately lAV.
Therefore:
R = 12V-1V-(3xO.9V)-IAV =69£2
~
lA
.
Preferred value Rv+ = 6.8£2 is selected.
Figure 14
Comment:
- It is obvious that the maximum 18+ value is
directly dependent on the power supply voltage.
Therefore, Vcc variations as a function of mains
voltage, through the forward self-supply winding,
must be taken into consideration.
- All calculated values must be optimized on the
prototype board by taking into account all operating conditions of the switching transitor to be
used.
111.4 - Input pulses & oscillator
11104.1 - Input pulses (pin 6)
The regulation PWM and sync pulses issued by the
controller circuit on secondary side are sent to the
primary side through a pulse transformer that ensures galvanic isolation between primary and secondary sections. The PWM pulse is differentiated
by the pulse transformer.
The input signal (pin 6 ofTEA2164) frequency must
Pulse
Transformer
91AN2164-14
fall within the sync window:
0.65 fosc < fSYNC < fosc
The positive drive pulse will turn the transistor on
while the. negative pulse will turn it off. Prior to
transistor turn-off, the positive base current is interrupted and then after a constant time interval, the
negative base current is applied to turn the transistor off.
For appropriate system operation, the amplitude of
pulses applied to input pin 6 must fall within ± 0.5V
to ± 1V range.
The pulse transformer can be built by 2 few turn
windings wound on a tore or ferrite rod.
111.4.2 - Oscillator (Rosc , Cosc - pin 7 and pin 8)
The free-running frequency is given by :
lose
=
1
0.4 x Rose x Case + 470 x Case
Choice 01 fosc must take into account the following
constraints:
• fosc must fall within the sync range:
0.65 x fosc < fSYNC < fosc
• the free-running frequency fosc must not fall
inside audible frequency range in stand-by
mode:
fosc 2': 20kHz
The sync frequency value used in TV applications
is 15.7kHz.
The free-running frequency "fosc" value is selected
to be 19kHz so as. to iall at the center of sync
frequency range. This lrequency is close to 20kHz
and is therefore not audible.
The value 01 "Cosc" capacitor determines the oscillator saw-tooth discharge time. This time has a
direct inlluence on "tON(MINj" used by TEA2164 and
therefore should not be too long so as to allow a
15/30
-------------- ~ ~~~(llig1e2~(~~~c~ -~------------
1179
APPLICATION NOTE
low "ton(min)".
We shall select Cosc = 1.2nF
The corresponding value of Rosc is calculated as
follows:
.
Rose
1
0.4 x 19 x 103 x 1.2 X 10-9
470 = 10Bkn
0.4
Selected value is : Rosc = 11 Ok!)
The tolerance of these components is calculated
as a function of maximum admissible free-running
frequency dispersion while also taking into account
the minimum and maximum limits of the horizontal
scanning frequency.
111.5 - Stand-by
The system will enter into stand-by mode by simply
disconnecting the power supply to the secondaryconnected PWM regulation device (TEA5170 or
TEA2028). In the absence of control pulses normally delivered by the secondary block, the
TEA2164 will switch to "burst" mode in which case,
the power transfer falls to a low value.
111.5.1 - Very low frequency oscillator
The period of this VLF Oscillator is determined by
capacitor "C1" connected to pin 1O.
ForC1 = 100nF, the VLF oscillator per.iod is approximately 30ms. The typical burst duration is therefore 3.9ms - which is 13% of the VLF oscillator
period.
The ripple ratio of secondary output voltages in
stand-by mode depends on VLF oscillator period
and hence on the value of capacitor C1.
111.5.2 - Regulation in stand-by mode
A feed-back loop connected to pin 9 is· used to
modify the maximum conduction period in burst
mode and to allow the regulation of secondary
output voltages in stand-by.
The feed-back information is delivered by the selfsupply flyback winding of TEA2164. This signal,
once rectified and filtered, is an image of secondary
voltages. This voltage is applied to an adjustable
Figure 15
91 AN2164·15
divider bridge and then to pin 9 which is used for
output voltage adjustment in stand-by operation. It
is recommended to choose the voltage values in
stand-by slightly lower than nominal values used
under normal operating conditions. A 'l'nF capacitor
has been added to pin 9 which will improve the
16/30
filtering of the regulation voltage.
111.5.3 - Maximum power in stand-by operation
The collector current envelope shape varies as a
function of the secondary power consumption in
stand-by.
----------------------------~~i~@~~~~~Jl
1180
----------------------------
APPLICATION NOTE
It follows that the power which may be tranferred
to the secondary winding in stand-by is therefore
limited.
The maximum power in stand-by can be estimated
as follows:
Figure 16
91AN2164·1B
PMAX·
PSB(MAX)
~ -3- x 0.13 x
150
111.5.4 - Booster circuit for higher stand-by output
power
ISB
ISYNC
19 x 103
3
15.7x10
Comment:
When higher stand-by output power is required, it
is possible to add a network on pin 10, which
modifies the shape of the VLF oscillator saw-tooth
and increase the T1/T2 ratio.
- at PSB = PSB(MAX) , C3 capacitor (pin3) is slowly
charged and the voltage on pin 3 will reach the
protection threshold value (3V typ.) and the
SMPS is shut down.
The burst duration "T1" is not modified, only the
VLF oscillator period "T2" is shorter, which will
increase the available stand-by output power.
=}
P(SBMAX) ~-3
x 0.13 x
8W
Figure 17
TEA 2164
VC1
4V
r - - - - - - - - -..,
I
:
1~
IL-
t
VLF
I
OSCILLATOR
I
Discharge
___ ___
_ _ _ .J:
r--------,
I
I
1Skn
Vec
I
47kQ
I
I
I
I
VCl
tr
I
I
100:
nF I
I
~
150
kQ
I
_______ J
1.2V
"~
~
I
T1
~
:
1
~
..
t
I
I
t - - - - - T2 -----i
T11T2> 13%
91AN2164·17
17/30
--------------- ~ ~~i;;mg~,~2~ ---------------
1181
APPLICATION NOTE
111.6 - Start-up
111.6.1 - Start-up resistor
Upon initial system start-up, the mains filtering
capacitor is charged through the rectifier diode
bridge.
The voltage across the device power supply capacitor (pin 16) is low and less than the "VCC(STARTj"
value. The TEA2164 is therefore in low consumption state. The supply voltage capacitor "C16" begins charging through a high value (1 OOkQ) resistor
"RSTART" connected to the rectified mains voltage.
Figure 18
RSTART
(100kn)
iCC(STARn
"'---11
CIS
(220I1 F)
91AN2164·18
The capacitor charge up time is given by :
t
CHARGE
=
VCC(START) X
V,N
C's
RSTART - ICC(START
tCHARGE
9 x 220 x 10-6
310
(0.8 x 10-3)
100x 10-3
0.85s
At minimum mains voltage level : tCHARGE = 1.2s
- The power dissipated within "RSTART" resistor is :
P = (V IN
-
Vcc)2
RSTART
(310-12)2
.
3 = 0.9W (P = 1.4W at Mains max level)
100 x 10
P =.
An application variant is '4'hen the start up resistor
is directly connected to non-rectified mains.
In this case and in order to obtain an identical
start-up time, the value of "RSTART" resistor must
be divided by 1t. The power dissipation is thus
reduced by approximately 30%.
111.6.2 - Self-supply
As soon as the voltage on pin 16 reaches the
VCC(START) level of 9V, the TEA2164 will start-up
and deliver the base drive pulses to the switching
transistor at internal oscillator frequency (set by
Rasc and Casc). The duty cycle of these pulses
gradually increases (soft-start). During this cycle of
operation, the device does not receive any control
18/30
pulse from the secondary controiler circuit and
therefore operates in "Burst mode".
The start-up will correcty take place if the device is
rapidly self-supplied, that is, before the voltage
across the supply capacitor on pin 16 falls below
VCC(STOP) threshold.
TheTEA2164 is supplied by two distinct secondary
windings, one connected in flyback and the other
in forward configuration.
The forward voltage will rapidly provide the supply
required by TEA2164 whereas the flyback voltage
will begin rising slowly and depends on various
secondary time constants.
Main advantage of the flyback voltage is that it
provides a regulated supply voltage proportional to
the secondary Voltages.
A + 12V voltage has been selected for device power
supply at nominal mains voltage level. A lower
value such as + 1OV can be selected which will also
reduce the power dissipation. Note however that
since the overvoltage protection threshold is internally" set at + 15V, then the lower is the supply
voltage level the greater will become threshold
margin.
At nominal mains voltage, the forward voltage
value is selected to be 1V below the flyback voltage
value so that, the supply voltage at maximum
mains voltage, will not rise much above its nominal
value (and will remain below 15V threshold level).
111.6.3 - Secondary controller circuit start-up
After a time interval required for the secondary
--------------~. ~~tm~m~i!~11
1182
--------------
APPLICATION NOTE
power supply capacitors to charge up, the secondary-connected regulation controller circuit will be
powered and as soon as its supply voltage "Vcc"
reaches the "VCC(START)" level, it will begin delivering regulation and synchronization pulses. The
TEA2164 will receive these pulses and will consequently switch from "Burst Mode" to "Normal Mode"
synchronized and regulated by the secondary controller circuit.
The secondary controller circuits (TEA2028,
TEA2029 and TEA5170) have a "soft-start" function. This system allows better transition when
switching from stand-by mode to normal mode.
The TEA2028 and TEA2029 controllers have no
"tON(MIN)" function, and for this reason, it is necessary to choose lower voltage in stand-by mode than
in normal mode. Otherwise, switching from standby mode to normal mode will not be possible (secondary controller circuit will not issue regulation
pulses as long as the output voltage remains above
its nominal value).
The TEA5170 has a "tON(MIN)" function, butit is also
recommended to choose the stand-by voltage
under the nominal value so as to avoid overvoltage
when switching from stand-by mode to normal
mode.
For further details on secondary controller circuits,
please refer to TEA5170 and TEA2028-TEA2029
Application Notes (AN407/0591).
111.7" Protection features
111.7.1 - Overload protection
The current limitation is set by resistor "Rs" as a
function "1C(M1)" threshold, such that the power
transfer is limited at 150W. If the load connected to
secondary requires higher power, the current limitation is activated and will limit the power transfer
by lowering the output voltage.
111.7.2 - Short-circuit protection
In case of short-circuit, the secondary voltage falls
to zero and the time required for the transformer to
demagnetize becomes very long. The collector
current will no longer start at zero level but at the
final value of the preceding period. The current
value will rapidly reach "1C(M1)" and then "lc(M2)"
threshold levels.
Only the "lc(M2j" threshold will disable the device
and switch it into "Burst Mode". The device will
re-start at the beginning of the following VLF oscillator period. However, if the short-circuit still persists, the "lc(M2)" protection threshold is once again
activated.
Figure 19
Ic
IC(M2)
COLLECTOR
CURRENT
"Ic·
-------------------------- ---
(Burst Mode)
IA
~
(
t
--Tosc-91AN2164·19
111.7.3 - Repetitive overcurrent protection
Each time that "lc(M1j" or "lc(M2)" thresholds are
reached, an event counter will charge up the capacitor "C2" connected to pin 3. If the overload
persists, the voltage across capacitor will reach the
3V threshold level and TEA2164 is consequently
disabled (no power transfer to secondary will take
place).
To exit this protection mode, the mains voltage
must be disconnected during a time interval long
enough for all capaCitors to fully discharge. The
system can re-start only once the capacitors have
been discharged.
111.7.4 - Overvoltage protection
If an overvoltage (produced by improper adjustment or failure) appears at secondary terminals,
the primary flyback voltage will rise and if the +15V
threshold level is reached, the TEA2164 is disabled.
19/30
---------------------------- ~~~@!r~~~~~~~ --------------------------~
1183
APPLICATION NOTE
An overvoltage would be also generated if the load
on secondary terminals is disconnected. In this
case, if the secondary controller device is not equiped with tON(MIN) feature (TEA2028 , TEA2029), it
will stop sending the regulation pulses and the
TEA2164 will consequently enter into "Burst
Mode".
If the secondary controller device has a "tON(MIN)"
function (TEA5170), the protection is performed at
the primary side by the + 15V overvoltage threshold
level.
111.8 - Osciliograms
Figure 20
1 • NORMAL MODE: Base Current
VPIN 6 :
1V/div
Is: 1A!div
Mains: 220VAC
Load: 90W
Scale: 10flS/div
Figure 21
2. NORMAL MODE: Primary and Secondary Currents
J
I, Mid"
Mains: 220VAC
Load :90W
Scale: 10f1S/div
Is: 1A!div
20/30
- - - - - - - - - - - - - - ~·~~;~;)m~,~~~~~ - - - - - - - - - - - - - 1184
APPLICATION NOTE
Figure 22
3 - NORMAL MODE: ColleCior-emitter Voltage
VPIN 6: 1V/div
VCE: 200V/div
Mains: 220VAC
Load :90W
Scale: 1O~/div
IC: 2A!div
Figure 23
4 - NORMAL MODE: Current Limitation Voltage
oJ
VPIN 6: 1V/div
01
J
VPIN 11 : O.5V/div
Mains: 220VAC
Load :90W
Scale: 10).1Sldiv
J
Ic: 2A!div
o
Figure 24
S. NORMAL MODE: Oscillator Saw-tooth
o}
VPIN 6: 1V/div
l
VPIN B : 1V/div
-1.6V
Mains: 220VAC
Load :90W
Scale: 10~/div
Ic: 2A!div
21/30
---------------- ~ ~~i©m~~u~J?(C~ ----------------
1185
APPLICATION NOTE
Figure 25
6· NORMAL MODE: V+ Supply Voltage
VPIN6:
1V/div
12V
VPIN 15 : 5v/div
Mains: 220VAC
Load :90W
Scale: 101LS/div
Ic: 2Ndiv
Figure 26
7· NORMAL MODE: Output Voltage
VPIN 6 : 1V/div
VPIN 14 : ,2V/div
Mains: 220VAC
Load: 90W
Scale: 101LS/div
O.SV
Ic: 2Ndiv
Figure 27
8. NORMAL MODE: Flyback and Forward Voltages
(TEA 2164 Power Supply)
VFORWARD : 5v/div
VFlYBACK: 5V/div
o
Mains: 220VAC
Load :90W
Scale : 10l!Sldiv
22/30
~-------------- ~ ~~~~m~mlil~'G~
1186
---------------
APPLICATION NOTE
Figure 28
9· NORMAL MODE: Transistor tum-off
VCE: 200v/div
IC: 1A1div
Mains: 220VAC
Load: 90W
Scale: SOOnsldiv
o
Figure 29
10· NORMAL MODE: Saturation Voltage
18 : o.5A1div
Mains: 220VAC
Load :90W
Scale: 2J.1S.'div
01
VCE(SAT): W/div
Figure 30
11 • NORMAl MODE: Safe Operating Area
Mains: 220VAC
Load :90W
Ic : O.5A1div
VCE : 100V/div
--------------------------~--- ~ ~i~;~~~f~9c~
23/30
-------------------------------
1187
APPLICATION NOTE
Figure 31
12· STAND-BY MODE: VLF Oscillator
VPIN 10 : 1V!div
Mains: 220VAC
Load :3W
Scale: 5ms/div
Ic :c.5Ndiv
o
Figure 32
13· STAND·BY MODE: One Burst
VPIN 10 : 1V/div
Mains: 220VAC
Load :3W
Scale:
500~s/div
Ic: O.5Ndiv
Figure 33
14· STAND·BY MODE: High Frequency Oscillator
. VPIN 10 : 1V/div
1.6V
Mains: 220VAC
Load :3W
Scale: 101lS/div
Ie :O.5Ndiv
o
::.24~/::.30=--_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~@m~"~'Ifg~
1188
--------------
APPLICATION NOTE
Figure 34
15· START·UP SEQUENCE
Ii Start Mode
-12V
C!I
Burst Mode
III
Normal Mode
1
. V"""
2Vidt.
Scale: 200ms/div
1 Ie: 1Ndiv
Figure 35
16· OVERLOAD PROTECTION
(Pin 3)
1'0 ,N""
-0
Scale: 200ms/div
Figure 36
17 • SHORT-CIRCUIT PROTECTION
(Pin 3)
Ic:2NdiV
Scale : SOms/div
VPJN 3 ;
'J.VlOiv
25/30
-------------- ~ ~~~~I~tgm~R:~ -------------~
1189
APPLICATION NOTE
IV - APPLICATION VARIANTS
V.1 All mains application
IA wide input voltage range application can be
configured around TEA 2164. We have built a
power supply delivering 90W output power at
mains input voltage range of 90VAC to 260V AC.
Difficulties encountered in such application are
given below:
- Very wide regulation range: if a discontinuous
mode fly back transformer is employed, the conduction time would be highly variable.
The "tON(MAX)" duration is determined as a function of maximum power output and the minimum
mains voltage level.
The "tON(MINj" duration is determined as a function
of minimum power output and the maximum
mains voltage level.
- Start-up at minimum mains level : appropriate
selection of start-up resistor and self-supply windings.
- Optimized switching transistor base drive and
appropriately dimentioned protection features to
operate over the whole mains voltage range:
both, the base current, and supply voltage values
and hence the self-supply windings, must be ap-
propriately calculated.
FEATURES
- Discontinuous mode flyback SMPS
(Lp = 0.84mH)
- Standby function using the burst mode of
TEA2164
- Switching frequency:
• Normal mode: 15625 Hz (synchronized on horizontal deflection frequency)
• Stand-by mode: 19 kHz
- Mains voltage range: 90 VAC to 260 VAC
- Mains power consumption:
• Normal mode: 110 W max
• Stand-by mode:
6.7W (at 110V)
9.8W (at 220V)
(without degaussing coil)
- Efficiency:
• Normal mode:
83% (at 11 OV)
80% (at 220V)
(measured with 86W output power)
26/30
-------------~ ~i~@mR~~~~~
1190
"r::
REGULATION
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Small signal primary ground
Power primary ground
Secondary ground (isolated from mains)
~ _ REGUlATION
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Stand·by
Switch
SA 157
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m
APPLICATION NOTE
IV.3 - Application without stand-by
The application arrangement is simplified if the
stand by function is not required:
- The "Master" circuit on the secondary side is
permanently powered and as a consequence the
transistors used to cut its power supply are no
longer needed and can be eliminated.
- The feedback used for "stand-by" regulation func-
tion on the primary side configured around pin 9
of TEA 2164, can be simplified.
- The value of "C1" capacitor connected to pin 10
of TEA 2164 used to set the burst period and
therefore its duration, is increased (1 flF or 2.2flF)
so as to enable full load system start-up as soon
as the first burst is available.
-------------- ~ ~~e~m9,~~pm -------------29/30
1193
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91 AN2037-0B
11.3 - Line oscillator
Figure 9
In monitor application, the sync. signal is generally
separated from the video signal.
In this case, the sync. signal is applied to pin 15
through a single limiting resistor. Similar to the
former case, the sync. is detected when the input
voltage falls below 1.6 V level.
VCC1 ~~-----C~------~-i~
C
~
----,
I
I
I
11.2.3 - Frame sync. extraction
I
Figure 7
I
I
J
I
TEA 2037
I
I
I
91AN2037-09
Figure 10
91 AN2037-07
This function is processed internally and hence
does not require any external component. Line and
frame sync. pulses are distinguished by an integrated capacitor which is more or less discharged
during each sync. pulse interval as follows:
if the sync pulse duration is short, i.e. it is line
sync, then the capacitor is slightly discharged
on the other hand, if the pulse width is larger, the
capacitor is fully discharged and an internal
frame signal is thus generated.
4/17
UJ
~
6.6
!:i
§2
z'"
a::
----------------------------~~~~©~~~~ru~©~
1198
Line
I
-Period-
91AN2037-10
----------------------------
APPLICATION NOTE
The line saw-tooth is generated by charging an
external capacitor on pin 9 via a resistor connected
to VCCl (pin 16).
The capacitor is discharged via an internal 1.4 kQ
resistor. The saw-tooth amplitude is set by two
on-chip threshold levels:
- lower threshold: 3.2 V
- higher threshold: 6.6 V
The free-running period is approximately given by
the following relationship .:
Tose
~
so as to produce correct phase and frequency
relationships with respect to the synchronization
signal.
11.4 - Line output stage
The line output stage has been designed for direct
base drive of the horizontal scanning darlington
transistor.
The low level interval on pin 14, i.e. the power line
transistor blocking period, is determined by the time
when the voltage of the line oscillator capacitor (pin
9) is below 4.8 V (internally set threshold level). In
a typical application, this interval corresponds to
22).ls at 64).ls free-running period.
0.85 RC
The phase comparator will modify the capacitor
charge by injecting a positive or negative current
Figure 11
Vcc
Rl
6.6V~
3.2 V -- LilliJ-- --
Line
Yoke
I
Saw-tooth
I
I
I
J
I
_____
~~3~ _ _ _
J
Rl : 470 Q
R2 : 10 Q
R3: 47 Q
C : 2.21lF
D: 1N4148
T: BU184
91AN2037-11
Figure 12
11.5 - Phase comparator (PLL)
11.5.1 - Functional description
The duty of phase comparator is to synchronize the
horizontal scanning with the line sync pulse and
ensure correct line flyback during the horizontal
blanking phase.
PIN 9 VOLTAGE 64.6
(V)
.8
3.2
I
I
I
I
Figure 13
22 Jlsi
PIN 14 VOLTAGE
V(sat)
1!;::=t~==!:==1-----1-
DARLINGTON
VeE
YOKE CURRENT
Line Flyback
91AN2037·12
91AN2037·13
5/17
--------------- ~ ~i~~m~~~J?r~ ---------------
1199
APPLICATION NOTE
The line flyback signal (i.e. the pulse on the collector of the line scanning transistor) is compared with
the line sync. signal issued by sync. separator. If
the detected coincidence is incorrect, the compa-
rator will then generate an appropriate positive or
negative current so as to charge or discharge the
line oscillator capacitor thereby providing for frequency and phase locking.
11.5.2 - Phase comparator operation
Figure 14
.J-..-+-- V{roll
-
11
91AN2037-14
Figure 15
-1M L
Line
Flyback
Saw·tooth • _____ ~
(pin 11)
VCrs')
01--------
The comparator input stage is formed by the differential pair T1 and T2. T3 and T4 transistors are
arranged in current mirror configuration and thus:
is = i2
The sum of currents going through T1 and T2
transistors is determined by the current generator
"I" so that: I = h+ i2.
The comparator output current is the difference
current through the differential pair, i.e. :
,
)
m
Inlemal
Line sync Pulse
--.J :, L
Output current
(pintO)
..
-
riU.
91AN2037-15
The line flyback signal goes through integrator
network R1 C1 the output of which, a saw-tooth
signal, is applied to comparator input (pin 11) via
capacitor C2.
1200
The comparator is enabled by T5 transistor only
during the line sync. interval.
Transistor T6 inhibits the phase comparison during
the frame sync. interval.
During the first portion of the flyback, the voltage at
comparator input (pin 11) is lower than the reference Voltage. T1 is off and T2 conducts; consequently the comparator output goes positive:
ioUT~+1
During the second portion, the input voltage ex-
APPLICATION NOTE
ceeds the reference voltage and as a result, the
comparator ouput falls to negative level:
iOUT
= - I
If the line flyback is in retard with respect to the
horizontal sync. pulse (which is the case of too long
line periods), the interval for which the phase
comparator's output current is positive would in-
crease. This current is then filtered and applied to
the line oscillator capacitor (C5) thereby accelerating its charge-up phase and hence reducing the line
period.
Inverse action takes place if the line flyback is in
advance - the negative current at comparator's
output will rise, C5 is charged more slowly and the
line period is thus increased.
Figure 16
JL
I
Line Flyback
I
I
I
I
I
I
I
vera!) - - - - - : - I
I
I
JL
I
I
I
Saw-tooth
(pin 11)
I
I
----I-I
I
I
I
--0L-
I
Internal
Line sync Pulse
I
-1THELINEFLYBACK INRETARD
WITH RESPECT TO THE UNf SYNC PULSE
I
I
I
I
~
I
Output Current
(pin 10)
+
THE LINE FL YBACK IN ADVANCE
WITH RESPECT TO THE UNE SYNC PULSE
91AN2037-16
11.5.3 - Output filter
Figure 17
Figure 18
R3+R4
1, = 2rr(R3+ R4) C3
13 = 2rrR3R4C4
7/17
---------------- ~ ~~~~;m?::~f?~ ----------------
1201
APPLICATION NOTE
The duty of the output filter is to ensure the stability
of the locked loop and its characteristics will have
a partial influence on capture range and also on
capture time.
The holding range, which is larger than the capture
range, depends on the ratio of the current available
at the comparator output and the charging current
of the line oscillator. The holding range does not
depend directly on the cut-off frequencies of the
output filter. But, as the voltage range at the comparator output is limited, a too high value for R4 will
limit the holding range.
The sync. pulse duration has significant influence
on capture range and also on the holding range of
the device. The output current duration is directly
related to synchronization pulse width.
First the R5 x C5 product is selected to yield the
required free-running line oscillator frequency.
Then, the value of C5 capacitor is selected as
follows:
• for monitor applications (large holding range)
low value; e.g. :2.2 nF @ 16 kHz,
1 nF @ 32 kHz
• for TV applications
higher value; e.g. : 4.7 nF @ 16 kHz
Finally, the filter components are selected to
match the required capture range.
(R4 :s 100 kQ to prevent comparator output
saturation)
11.6 - Frame oscillator
Similar to line oscillator, the frame saw-tooth is
generated by charging an external capacitor on
pin 1 through a resistor connected to VCC1.
Figure 19
C
R
VCC1
_-_---c:}----...---I ~
r---
16 - - - - - - -
1
I TEA 2037
I
500n
Frame
Sync
Pulse
91AN2037-19
8/17
Figure 20
~
w
~
3.1
~
2
r;:,:::-::: 1.6 x 10-3 ,
it is necessary to increase the supply voltage to the
frame output amplifier so as to reduce the flyback
time. This surplus is required only for the frame
flyback and energy is wasted by boosting the supply to the amplifier at all times (during the frame
scanning time, the minimum voltage is substantially RI, where I is peak-to-peak frame current).
The configuration of the flyback generator is depicted in Figure below:
Figure 23
adjustment potentiometer "P" has been provided
for.
D.C. Feedback: The C1 capacitor is charged to
approximately 1/2 x VCC2. Divider bridge formed
by R2 + R4 and RS networks will set the d.c.
feedback. The component values of this divider
network will be choosen to avoid saturation at
top and bottom of the output voltage. (pin 6
biasing voltage is approximately 0.6 V)
During the second half of the vertical scanning
time, transistor T2 conducts and capacitor C is
charged to Vee through 01 , 02, R3 and T2. (Switch
K open)
- Linearity Correction : A parabolic signal at
frame frequency is available on "+" terminal of
the C1 capacitor. This signal is integrated by R2,
C2 network. An "S" waveform is thus obtained,
which is applied to pin 6 via resistor R4.
On fJyback, switch K closes and pin 3 is connected
to Vcc. The voltage at pin 7 (Vec2), which was
equal to Vce - VDt, is almost doubled during the
flyback time. The only external components required are therefore 01,02 and C.
Any correction to this "S" waveform depends on
C1 and C2 values. The linearity correction depends on ratio: R2/R4
In addition to reducing the fJyback time, the flyback
generator reduces the power consumed by the
power stage, and can in certain cases avoid the
9tAN2037-23
9/17
--------------- ~~~~@~g~~~?~~ --------------1203
APPLICATION NOTE
11.10 - Thermal considerations
Figure 24
In order to ensure reliable device operation, the
dissipated power should be accurately determined.
Calculation will allow an evaluation of the dissipated power and should be completed by package
temperature measurements in actual applications.
According to results obtained, a heatsink mayor
may not be required.
• Power drawn from VCC1 supply:
Pl = Vcc, .1,
'J\.J~'
t
91 AN2037 -24
need to use a heatsink.
Diode D2 is a low-signal diode (1 N4148) but diode
D1 must be appropriately rated since the positive
current in the first part of the saw-tooth is supplied
to the yoke through D1 and T1. A 1N4001 is generally used.
11.9 - The shunt regulator
The TEA2037 incorporates an internal shunt regulator which delivers the common supply voltage
Vcc to various blocks such as oscillators, comparator, sync separator and so on.
The voltage on pin 16 is 9.7 V (9 V min, 10.5 V
max). The value of the series resistor R must be so
calculated to obtain a 15 mA current on pin 16 - this
Where h is the current through the shunt regulator
(pin 16)
• Power drawn from VCC2 supply:
Where:
- Ipp = peak-to-peak current through the vertical
deflection yoke.
12 = Pin 7 quiescent current.
VCC2 = Pin 7 voltage.
• Power dissipated in deflection yoke and the
measurement resistor:
Figure 25
R
Vee -----I=r--.----<~-- Vee,
- Ry = Frame deflection yoke resistance
r----TEA2037
I
RM = Measurement resistor value
I
91 AN2037-25
current ca.n be 10 mA min. and 20 mA max.
The external current supply from VCC1 to both
oscillators (i.e. line and frame) can be neglected in
majority of cases.
The resistor value is found to be 1.2 kO at
Vcc = +28V.
At Vcc = + 12 V, and taking into account the voltage
tolerance on pin 16, a 150 0 series resistor must
be used.
10/17
Where:
Thus, the overall power dissipated in the integrated
circuit is :
Po = Pl + P2 - Py
In application using the flybackgenerator, the VCC2
specified above becomes "VCC2 - Vo", where Vo is
the voltage drop across the series diode.
----------------~~~~~~~mf~~~~
1204
---------------------
APPLICATION NOTE
Figure 26
Figure 27
Frame Yoke
Current
Vee2
Vee
Frame Yoke
Ly, Ry
91AN2037-26
91 AN2037 -27
III - APPLICATION EXAMPLES
111.1 - Monitor applications
111.1.1 - Low-cost monitor (French Minitel Type)
CHARACTERISTICS
,
Screen: 9" Monochrome
Frame deflection yoke: 72 mH, 40 n,
220 mA peak-to-peak
Vcc = + 25 V without flyback generator
Frame flyback time: 1.2 ms
- Vertical frequency: 50 Hz (20 ms)
Vertical free-running period: 24.5 ms
Horizontal frequency: 15 625 Hz
Capture range: ±5/ls
Holding range: ±1 OIlS
Input signal: composite video
Dissipated power: 1.15 W
Only one adjustment: vertical amplitude
Figure 28
100 nF
Video
Input
-t
1.5 kn
100 nF
1 MQ
LlnfL
15 kQ
22
FIYb'Ck~
nF
l
1 kQ
47 nF;t
91AN2037-28
11/17
--------------- ~ ~~~~m~~~~9CG~ ---------------
1205
APPLICATION NOTE
- This is a low-cost application used in French
Minitel type configurations and requires minimum number of additional components and adjustments. The input is a composite video signal
at line frequency = 15 625 Hz and frame frequency of 50 Hz.
The free-running horizontal frequency is determined by the component values of RC network
on pin 9. Since no adjustment is available, precision components must be used to ensure correct synchronization:
. [R = 35.7kQ, 1% and C = 2.2nF,
2% for fH = 15 625Hz]
The capture range is large enough to compensate
for possible variations.
Synchronization range of the vertical oscillator is
quite large which consequently allows use of
less accurate components:
[R = 910 kQ, 5 % and C= ,180 nF, 5 %]
- Since the frame flyback time is short enough at
supply voltage used 11ere, the flyback generator
is not used in this application.
111.1.2 - Monitor with geometry and frequency adjustments
CHARACTERISTI CS
Screen: 12" Colour
Frame deflection yoke: 18 mH, 10Q,
500 mA peak-to-peak
Vcc = + 12V with flyback generator
Frame flyback time: 0.7 ms
Vertical frequency: 50/60 Hz
Vertical free-running period: 23 ms
(adjustable)
- Horizontal frequency: 15.7 kHz
(adjustable)
Capture range: = ±5f..ls
Holding range: ±10f..ls
Input signal: negative TTL sync (line + frame)
Dissipated power: 0.9 W
Adjustments:
• Vertical amplitude
• Vertical linearity
• Vertical frequency
• Horizontal frequency
• Horizontal phase-shift
Figure 29
P1 ," Vertical Amplitude
P2 : Vertical Linearity
P3 ," Vertical Frequency
P4 : Horizontal Frequency
1N4002
Ps : Horizontal Shift
1~2·3
switching: Vertical Position
1N4148
lS
100 nF
10kn
mSync_C=J--\
fL
1SkQ 22nF
Line~
Flyback
_,.,.1
A..,.
VCC1 47 nF:t;
47 kn
VCC1
91AN2037-29
12/17
------------------------------- ~ ~~~@~~~~~~~~
1206
APPLICATION NOTE
111.1.3 - High frequency monitor
CHARACTERISTICS
Screen: 14" Colour
Frame deflection yoke: 11 mH, 7 Q,
750 mA peak-to-peak
Vec = + 14 V with flyback generator
Frame flyback time: 0.6 ms
Vertical frequency: 72 Hz
Vertical free-running period: 16 ms (adjustable)
Horizontal frequency: 35 kHz (adjustable)
Line fly back time : 5.5~s
Capture range : 5~s (@sync pulse = 4.7~s)
Input signal: negative TTL sync (line + frame)
Dissipated power: 1.4 W (heatsink required)
Adjustments:
• Vertical amplitude
• Vertical linearity
• Vertical frequency
• Horizontal frequency
Figure 30
2.2!l
'3.
---4--[::::J--T-~~r---' "F' g~
+14V
6:.
P1 : Vertical Amplituda
P2 : Vertical Unearity
Vee
P3 : Vertical Frequency
1 N4002
P4 : Horizontal Frequency
100 nF
1N4146
l..f
TTL Sync
fL.
Line
Flyback
10k!l
--C:J--i
Frame Yoke
11 mHo 7n
15 k!l 22 nF
---c:J---rI
• ___ 1
180n
47kn 68kn
47nF ;;\;
1
n
Line
Darlington
VCC1
91AN2037·30
~ ~~~~~g~~~~~~
13/17
----------------
1207
APPLICATION NOTE
111.2 - Black & white TV application
CHARACTERISTICS
-
Screen: 20" B & W 110°
Frame yoke: 30mH. 120. 850mA peak-to-peak
Vee = + 24 V with flyback generator
Frame flyback time: 1ms
Vertical frequency: 50Hz
Vertical free-running period: 24.5 ms
Horizontal frequency: 15625 Hz (adjustable)
Capture range: ±2 ~s
Holding range: ±4.5 IlS
Input signal: composite video
Dissipated power: 2.3 W
(10 0 Crw - heatsink required)
Adjustments:
• Vertical amplitude
• Vertical linearity
• Horizontal frequency
Figure 31
P1 : Vertical Amplitude
P2 : Vertical Linearity
P3: Horizontal Frequency
1N4002
24 V
2.2 k!l
r--l.+--{=J---
Video
1.5 k!l 100 nF
Input~
220 PF
r
~
LlnfL 15k!l 22nF
Frame Blanking
+_..,'OOl
. -_ _
1N_4_14_8_ _ _ _
680U
FIYbaCk~
47 nFJ:
91 AN2037-31
1208
APPLICATION NOTE
111.3 - Using composite TTL synchronization
Since the threshold level on input pin 15 is internally
set at 1.6 V, the device can directly accept TTL
signals.
However, a series resistor is required to limit the
current sunk by the on-chip transistor (pin 15).
such case, efficient synchronization can be
achieved by differentiating the signal so that it will
behave as a signal of only few lines duration which
is the condition required for appropriate frame and
line sync separation and also a picture without flag
effect.
111.4 - Direct frame synchro.nization
The vertical scanning can be directly synchronized
by the frame oscillator (pin 1) and without any need
of using the synchronization input (pin 15).
Figure 35 illustrates an example:
In this case, only the line sync pulse is applied to
pin 15.
Figure 32'
I
I REFERENCE
I
Figure 35
LT~":O~ ___ _
101cQ
~
Vee, __~----,~---t-----l16
91 AN2037 ·32
If
680 kQ
c~mposite sync signal is not available, line and
frame sync signals can be recombined at circuit
input as illustrated below.
220 nF
SL
Positive
Frame Sync
Figure 33
TEA 2037
10 kil
I
L
l __ -§-__
1
u~
NegatIve
UneSync
llr\eSyne
Input
~
.
L~~OE
91 AN2037-35
Ok!ll
15
IL________~I
FrameSynt
Input
91AN2037·33
Figure 34 : Application example
_--:c"SkOc-'-r---l15
111.5 - Constant amplitude 50/60 Hz switching
In applications requiring 50/60 Hz standard switching feature, the arrangement shown below allows
to maintain the amplitude of the oscillator sawtooth (pin 1) constant thus yielding uniform vertical
scanning.
Figure 36
I
Frame Sync
I
3300:
L2~~~
~L---..
,,"" ,'----------', ------;!'" -
VCC1--------1>----
47,",
60 Hz
Amplitude Adjust
Note : Specified component values are purely theoretical and must be calculated to meet specific application requirements.
60Hz
T50Hz r - - - - I
91AN2037-34
This arrangement is particularly interesting in applications where the available signals differ from
those commonly used. An example is the case
where the frame signal is of quite long duration
(sometimes as long as frame blanking period). In
I
TEA 2037
I VERTICAL
I OSCILLATOR
91 AN2037-36
15/17
---------------- ~~~~@~g~f~~~~ ----------------
1209
APPLICATION NOTE
Figure 37
Figure 39
~
~
R,
3.1/-_ _ _ _---'Up'-pe---"Th---,"',-,'hc:.0'-=-d_ _
g
Vee
L
R,
Constant
:z
TEA 2037
I
I
!:;
Amplitude
0:
~--~~~~~~~~~_t
91AN2037-37
A practical application configuration is illustrated
below.
Figure 38
Figure 40
i 6.6rn----------------- --o
4.8 -----
~
3.2,
>
vcc, _ - - -.......- - - - - ,
I
g: _
2.2kQ
910knl
TEA 2037
I
!'
:
r
~
?:.
l
~
1:
::
~
r10k(}
91 AN2037-39
..
l
I
!
!
I
~
I
I
t
1
t
>
~===-~====~-==--
__ t
91 AN2037 ·40
1150nF:
T
111.7 - Starting the TEA2037 from a +6V power
supply
50 Hz : T conducts
60 Hz : Tturned·off
91 AN2037-38
111.6 - Modifying the line output duration
The line output pulse duration is determined by two
internally set threshold levels. This interval can be
altered by modifying the charge current of the line
oscillator (pin 9)
The line oscillator of TEA2037 is capable of starting
at a low supply voltage « 6V). The period of
oscillation is practically the same as at nominal
operation. It is thus possible to initiate the line
scanning at a reduced supply voltage (e.g. +6V)
and then supply the overall configuration by the
power available on the line transformer.
Figure 41
+ 25 V
EHT
TIIANSFORMER
COO
LINE
YOKE
91AN2037-41
1210
APPLICATION NOTE
IV - DESIGN CONSIDERATIONS
IV.1 - Precautions for interlaced scanning
The links interconnecting the ground terminals
of Vcc and VCC1 power supplies, as well as those
of device decoupling capacitors, must be kept to
as short as possible
A high value decoupling capacitor can be used
for Vcc supply, provided that a good quality low
series resistance capacitor is employed. Interlacing is very sensitive to decoupling quality. The
value of the decoupling capacitor can vary from
22llF to 100llF.
The interconnecting links between the frame
oscillator capacitor, the line oscillator capacitor
and TEA2037 grounds must be kept to as short
as possible.
Perfect line and frame synchronization is achieved
by observing the above guidelines and recommendations.
IV.2 - Printed circuit board layout
- The usual precautions observed in design of TV
timebase pc boards must be employed
The line output stage handles high amounts of
voltage and current. Components employed
must therefore be appropriately rated, the width
of and the clearance between the wiring tracks
should be carefully selected. All connections
must be as short as possible and all signals at
the line frequE?ncy gathered at this section.
- The supply to the frame scanning section of the
circuit must not be influenced by the horizontal
scanning function, particularly when interlaced
scanning is used.
- Generally speaking, interactions on the pc board
between the high-gain/low-Ievel and the highcurrent sections of the output stages must be
minimized by as much as possible.
As indicated in previous chapters, the four center
pins of the device must be earthed. The pad used
for this purpose must be as large as possible
since it acts as the heatsink for the device. A
cruciform pad underlying the circuit should be
employed.
There should be a single connection to the chassis earth terminal.
-------------- ~ ~~~;JmR:~g~ _____________
1:.,:7.:..,/1...:,7
1211
THERMAL MANAGEMENT
1213
..!'=:-=
'1L SGS-1HOMSON
~D©OO@~[L~©'jj'OO@[t(!]D©~
APPLICATION NOTE
THE POWER DIP (16+2+2, 12+3+3) PACKAGES
by R. Tiziani
INTRODUCTION
This Application Note is aimed to give a complete
thermal characterization of the (16+2+2) power DIP
(modified 20 lead DIP with 4 heat transfer leads)
and of the (12+3+3) power DIP (modified 18 lead
DIP with 6 heat transfer leads) in association with
thermal modules integrated on the PCB.
Characterization is performed according with recomendations included in G32-86 SEMI guideline,
by means of a dedicated test pattern developed by
SGS-THOMSON. It refers to:
1. Junction to pin thermal resistance RthO-p)
2. Junction to ambient thermal resistance Rth(j-a)
3. Thennal resistance in DC and pulsed conditions,
with a typical extemal heat sink.
Most of the experimental work is related to the
thermal impedance, as required by the increasing
use of switching techiniques.
Figure 1. POWER DIP application on PC board
5-10798
Experimental conditions
The thermal evaluation was performed by means
of the test pattern P638, which is a 80x80 mils2 die
with a dissipating element formed by two transistors
working in parallel and one sensing diode. In order
AN467/0492
to characterize the worst case of a high power
density IC, the total size of the element is 3000
mils'2, with a power capability of 20 W. Measurement method is described in Appendix. A.
1/13
1215
APPLICATION NOTE
Samples with the indicated characteristics were
. prepared:
Package
DIP (16+2+2)
DIP (12+3+3)
Frame Material
Copper
Copper
Frame Thickness
Frame Thermal
Conductivity
O.4mm
O.4mm
3.9W/cmDC
3.9W/cmDC
against a water cooled heat sink, according with
fig. 2. A thermocouple placed in contact with the
plate measures the reference temperaturE!.
For junction to ambient thermal resistance Rth(j-a)
the samples are suspended horizontally in a one
cubic foot box, to prevent drafts.
The effect of "on board" external heat sinks shown
in fig. 1 is quantified, using a test board which has
two 4 x 4 cd dissipating areas, one of each side
of the package. These areas are mechanically
reduced in order to study the effect of their size on
thermal performance.
The measurement circuit shown in fig. A3 is used
for all of the thermal evaluations.
Measurement of junction to pin thermal resistance
Rth(j-p) is performed by holding the package (with
the heat transfer leads soldered on a copper plate)
Figure 2. Measurement of Rth(j-p)
PRESSURE
eLi PPI NG
CONNECTION
THIN WIRES
I
HEAT TRASFER LEAD
r-'-'=t
-~\\'~'11~~~~,\~\. .:::;
____ SOLDERED
SIGNAL LEAD
COPPER FOIL - - ._ /
JOINT
\
{
WATER-COOLED
COPPER-BLOCK
LTHERMAL
GREASE
5-9783
THERMOCOUPLE
JUNCTION TO PIN THERMAL RESISTANCE
The dependance of Rth(j-p) on the dissipated
power is negligeable compared to the absolute
value: starting from 1 Watt to 10 Watts the Rth(j-p)
increases of about O.5C/W due to the lowering of
silicon thermal conductivity with the increasing of
·temperature. An important contribution to Rth(j-p)
is given by the silicon die and in fig. 3,4 is showed
the relationship between Rth(j-p) and the dissipating area existing on the silicon die (power diodes,
poVlier transistors, high current resistors), for differ- .
2/13
1216
ent die sizes.
In the figures two curves area reported: the lower
one is referring the Rth(j-p) measured at the pin
stand-off, the upper one is referring to the Rth(j-p)
measures at 1.5 mm from the pin stand-off (1.5 mm
is the typical thickness of FR4 board).
The upper curve must be used for the application
in which the heat sink is placed in the lower side of
PCB and the lower curve must be used when the
heat sink il'j placed on the upper side of PCB.
~ SGS-1HOMSON
"'11
i'IID©OO@~~~mOO@U!JD©®
--------------
APPLICATION NOTE
Figure 3· POWER DIP 16+2+2 Rlh(j.p) vs on die dissipating area
POWER DIP 16+2+2
15
P638 THERMAL JEST CHIP
14 ...................
························b·I·E··PAb'·~··1·52··x··1·60
T
H
13
M
12
E
R
A
l
DIE SIZE
11
for heat sink on PCB lower side
R
E
sq. mils
=160 x 160 sq.mils
S
10
S
T
A
9
I
N
C
8
U·pin)
7
E
for heat sink on PCB upper side
(CIW)
6
0
2
4
6
8
10
12
14
16
DISSIPATING AREA (x 1000 sq. mils)
18
20
22
Figure 4 • POWER DIP 12+3+3 Rlh(j.p) vs on die dissipating area
POWER DIP 12+3+3
13
P638 THERMAL TEST CHIP
12
DIE PAD = 165 x 220 sq. mils
DIE SIZE = 160 x 160 sq.mils
T
H
E
11
A
L
10
R
E
S
I
S
9
R
M
T
A
N
C
forh.eatsin~.onPGBlo'Ner.side...
8
7
E
U·pin)
6
for heat sink on PCB upper side
(CIW)
5
0
2
4
6
8
10
12
14
16
DISSIPATING AREA (x 1000 sq. mils)
18
20
22
3/13
--------------------------- ~~i~~~~~'~~1 ---------------------------
1217
APPLICATION NOtE
JUNCTION TO AMBIENT THERMAL
RESISTANCE
sistors and the sensing diode. The lower curve is
obtained with a very large heat sink (35 11m thick
4 x 4cni copper area for each side) while the other
curve refers the packages mounted on board with
no heat sink.
Rth is decreasing when power is increased, due to
a better heat transfer efficiency at higher temperature.
Fig. 5,6 give the junction to ambient thermal resistance Rth(j-a) of the package vs dissipated power;
it evidences the effect of the board in improving the
exchange of the heat towards the ambient. The
upper curve refers to samples suspended in. air,
with eight thin wire connecting the dissipating tran-
Figure 5 - RthU.a) of DIP (16+2+2) package vs dissipated power
POWER DIP 16 + 2 + 2
110~-----------------------------------------,
P638 THERMAL TEST CHIP:
DIE PAD ~ 152 x 160 sq. mils
DIE SIZE 160 x 160 sq.mils
DISSIPATING AREA DIE ~ 80 x80 sCl:mils
T
H
E
90
R
M
FLOATING IN AIR
A
L
R
E
S
I
S
T
A
N
C
70
MOUNTED ON PCB:
~
WITH NO HEAT SINK
·········~c-c·"")I(:lIb-~---J)~K="==."'!I)I(E-'--'--"-'.::;...*'*.::::.....::::.::::~*
50
E
WITH COPPER HEAT SINK 32 sq. em area
O-a)
(C/W)
*
*
1.5
2
30L---__L -____)I(L-____L-__~L-__~)I(____~)I(______
o
Q5
1
~5
3
a5
DISSIPATED POWER (Watt)
4/13
1218
~ ~~~m~~~91
----------------------
APPLICATION NOTE
Figure 6 - Rth(j-a) of DIP (12+3+3) package vs. dissipated power
POWER DIP 12 + 3 + 3
100r---------------------------------------------.
P638 THERMAL TEST CHIP:
DIE PAD = 165 x 220 sq. mils
T
H
E
DIE SIZE 160 x 160 sq. mils
DISSIPATING AREA DIE", 80x80 sq,mils
80
R
M
A
L
R
E
FLOATING IN AIR
60
S
I
S
T
A
N
C
~
MOUNTED ON PCB:
~---;j'~-*~
" ~( ~~-*-----4
~(
~(
*
WITH NOHEAT SINK
40
E
*
(j-a)
(C/W)
*
*
*
*
WITH COPPER HEAT SINK 32 sq_ cm area
20L-____J -_ _ _ _- L_ _ _ _
o
0.5
1
~
_ _ _ _ _ _L __ _ _ _~_ _ _ __ L_ _ _ _~
1.5
2
2.5
DISSIPATED POWER (Watt)
The effect of on board heat sinks with different size
is summarized in fig. 8,9; thermal resistance in
given vs the side I of the two thick copper squares,
obtained in the lower side of the test board and
dedicated to heat dissipation (see fig. 7 for test
board). Standard thickness of 35).!m was used for
the characterization as the most part of PCb application but a large improvement can be easily ob-
3
3.5
tained with a thicker copper heat sink on board:
70).!m and 105).!m (respectively 2 and 3 oz.) are
strongly increasing the thermal performances of the
considered POWER DIP application. These solutions can be attractive for low complex PC board
with a cost saving in avoiding large external heat
sink or forced ventilation.
Figure 7 - Test board with two "on board" square heat sinks vs side I
P.C. BOARD
1219
APPLICATION NOTE
Figure 8 - Rlh(j-a) of POWER DIP 16+2+2 vs side I for heat sink on the PCB lower side
POWER DIP 16 + 2 + 2
50
P638 THERMAL TEST CHIP
T
H
E
R
45·
M
40
A
DIE PAD = 152 X 160 sq. mils
DIE SIZE: 160 x 160 sq.mils
"ON BOARD" COPPER AREA THICKNESS:
L
R
E
S
I
S
T
A
N
C
E
35
35J.1m
30
70j.1m
25
(CIW)
10!}lm
20
0
0.5
1.5
2
2.5
3
3.5
4
side I ( em) on PCB heat sink
4.5
5
5.5
Figure 9 - Rlh(j-a) of POWER DIP 12+3+3 vs side I for heat sink on the PCB lower side
POWER DIP 12 + 3 + 3
45
P638 THERMAL TEST CHIP
T
H
E
R
M
A
40
35
L
R
E
S
I
S
T
A
N
C
E
30
25
20
10!f1m
Pd = 2 Watt
(CIW)
15
0
6/13
0.5
1.5
2
2.5
3
3.5
4
side I ( em ) on PCB heat sink
4.5
5
5.5
--------------------------- ~~~~gml~~ --------------------------1220
APPLICATION NOTE
TRANSIENT THERMAL RESISTANCE
The effect of single pulse of different length and
height, is shown in fig. 10,11 for POWER DIP
16+2+2 and 12+3+3. Thicker copper heat sink on
PCB is effective also for short pulse width (less 1
sec.). Due to a significant thermal capacitance a
correspondingly long risetime, single pulse up to
10W can be delivered to the system for 1s with
acceptable junction temperature increase.
Figure 10 - DIP 16+2+2 Transient thermal resistance for single pulses
Power DIP 16 + 2 + 2
SINGLEPULSE
T
H
E
R
M
A
L
MOUNTED ON BOARD
P638 THERMAL TEST CHIP
die size: 160x160sq.miis
10
Pd.~2Wl.ltt ...
I
M
P
E
D
A
N
C
A = 35 um thick no heat sink
E
B = 35 um thick 4x4 sq. cm on board Cu area
C = 105 um thick 4x4 sq. em on board Cu area
(CIW)
1
0.001
0.01
0.1
1
10
TIME OR PULSE WIDTH ( sec. )
____________ 51'1 SGS-THOMSON
'],
1:ilD©OO@~~rn©mill@UiIlD©®
100
1000
_ _ _ _ _ _ _ _ _ _ _7_/13
.
1221
APPLICATION NOTE
Figure 11 - DIP 12+3+3 Transient thermal resistance for single pulses
POWER DIP 12+3+3
SINGLE PULSE
T
H
E
R
M
A
L
MOUNTED ON BOARD
P638 THERMAL TEST CHIP
die size: 160x160 sq.mils
10
I
M
P
E
D
A
N
C
E
(C/W)
C = 105 um thick4x4 sq.cm pn board Cu area
1 ~~~Will_ _LLLUWL-J-L~lliL~~illllL-L~LW~-LLL~
1000
0.001
100
0.01
0.1
1
10
TIME OR PULSE WIDTH ( sec. )
Repeatition of pulses with defined Pd, period and
duty cycle DC (ratio between pulse length and
signal period), gives rise to an average temperatu re
increase:
~Tavg = Rth X Pdavg
8/13
=
Rth X Pd X DC
Junction temperature is oscillating about the mean
value as qualitatively shown in fig. 12. The transient
thermal resistance corresponding to the upper limit
(peak transient thermal resistance) is reported in
fig. 13,14 and depends on pulse length and duty
cycle. It can be noticed that DC becomes less
effective for longer pulses.
--------------------------- ~~i~@~~~m~~ --------------------------1222
APPLICATION NOTE
Figure 12
T
E
M
P
E
50
R
A
T
40
R
30
U
R
E
I
S
E
20
(A.U.)
0
20
40
60
100
80
TIME (A. U.)
Figure 13 - Peak Transient Thermal resistance of DIP (16+2+2)
POWER DIP 16 + 2 + 2
P638 THERMAL TEST DIE
P
E
A
DC=(].5
K
T
R
A
N
S
I
DC = 0.4
10
DC=0,3
Pd = 5 Wat~
E
N
T
QC,,;().1
R
..... PULSE WIDTH
DC = DUTY CYCLE = - - - - -
t
PULSE PERIOD
h
mounted on PCB with 35 urn thick 4x4 sq.cm on board area
__
100
1L-~LLUllll--L~~llL~-LLU~
10
(OW) 0.1
~~llWL-~LU~
1000
10000
TIME OR PULSE WIDTH (millisec.)
______________ 51 SGS·1HOMSON
• J II
_ _ _ _ _ _ _ _ _ _ _ _9_/13
[ljJG©IliI@~[.~©'ir]l@j!G©i0
1223
APPLICATION NOTE
Figure 14 - Peak transient thermal resistance of DIP (12+3+3)
POWER DIP 12+ 3 + 3
P638 THERMAL TEST DIE
P
E
A
K
T
R
10
A
N
S
I
E
N
T
D,C. = DUIYCYCLE,,=
t
h
-".,-".,-".,--."..~
PULSE PERIOD
mounted on PCB with 35 um thick 4x4 sq.cm on board area
(C/W)
'1
0.1
10/13
PULSE WIDTH
DC = 0.1
R
10
100
TIME OR PULSE WIDTH (millisec.)
1000
10000
--------------------------- ~~ii@~~~19~ --------------------------1224
APPLICATION NOTE
APPENDIX
TEST PAITER P638
For thermal measurement
Test patterm P638 is designed for thermal measurement following SEMI guideline G32 (see SEMI
Standard Handbook, 1986/87).
It has two bipolar power transistor with area of about
3000 sq. mils and one sensing diode (see Fig. A 1).
The lay-out is optimized in order to have a uniform
temperature, once the two transistors are powered:
the sensing diode is placed at the center of this
area.
Figure A 1 - P638 test pattern
:
:
:
C B
..
..
:
: : :
:
E
p
N
...
E
B C
11/13
--------------------------- ~~it~~~~~~~ ----------~---------------
1225
APPLICATION NOTE
Die size of single unit is 80 x 80 sq. mils; wafer
thickness is about 280 microns.
The relationship between the forward voltage VI of
the diode at a constant current of 100 IlA and the
temperature is linear, with a coefficent K = 1.85
mV/C (see Fig. A2).
Therefore changes ~Tj in junction temperature of
the dissipating element formed by the two transistors, can be easily obtained from the diode for-
ward voltage drop:
~
Tj= (Vf1- Vf2)
K
(V12 is the diode forward voltage at ambient temperature and Vf1 is the voltage when the transistors
are dissipating).
For thermal resistance evaluation the measurement circuit is showed in Fig. A3.
Figure A2 - Calibration curve (sensig diode).
CALIBRATION CURVE
P638 TEST PATTERN
mV
F
a
R
w
A
R
::: -------"'---------1--
Id = 100 uA
I
650 - - - - - - - - - - - - '
-.------1----•
D
I
600
V
a
L
T
A
G
E
I
550
: : --------- :-1-----o
~
~M
I
I
_
M
100
1~
140
160
TEMPERATURE ( C )
Figure A3 - Measurement System
1U
12/13
10
--------------------------- ~~i~~i~'9~ --------------------------1226
APPLICATION NOTE
Tipical conditions are:
Pd (Watt)
Vee (Volt)
Ie (rnA)
0.1
1.0
100
0.2
2.0
100
0.3
3.0
100
100
0.5
5.0
0.75
7.5
100
1.0
10.0
100
100
1.5
15.0
2.0
20.0
100
3.0
15.0
200
5.0
25.0
200
10.0
25.0
400
Each transistor is able to dissipate up to 10 Watt
due to presence of second breakdown.
13/13
----------------------------- ~~f~@~g~~~~ ----------------------------
1227
APPLICATION NOTE
DESIGNING WITH THERMAL IMPEDANCE
BY T.HOPKINS, C.COGNETTI, R.TIZIANI
REPRINT FROM "SEMITHERM PROCEDINGS" S.DIEGO (U.S.A.) 1988.
ABSTRACT
Power switching techniques used in many modern
control systems are characterized by single or repetitive power pulses, which can reach several hundred watts each. In these applications where the
pulse width is often limited to a few milleseconds,
cost effective thermal design considers the effect of
thermal capacitance. When this thermal capacitance is large enought, it can limit the junction temperature to within the ratings of the device even in
the presence of high dissipation peaks. This paper
discusses thermal impedance and the main parameters influencing it. Empirical measurements of
the thermal impedance of some standard plastic
packages showing the effective thermal impedance
under pulsed conditions are also presented.
INTRODUCTION
Power switching applications are becoming very
common in many industrial, computer and automotive ICs. In these applications, such as switching
power supplies and PWM inductive load drivers,
power dissipation is limited to short times, with
single or repeated pulses. The normal description
of the thermal performance of an IC package,
Rth(j -a) (junction to ambient thermal resistance), is
of little help in these pulsed applications and leads
to a redundant and expensive thermal design.
This paper will discuss the thermal impedance and
the main factors influencing it in plastic semiconductor packages. Experimental evaluations of the thermal performance of small signal, medium power,
and high power packages wil be presented as case
examples. The effects of the thermal capacitance of
the packages when dealing with low duty cycle
power dissipation will be presented and evaluated
in each of the example cases.
THERMAL IMPEDANCE MODEL FOR
PLASTIC PACKAGES
The complete thermal impedance of a device can
be modeled by combining two elements, the thermal resistance and the thermal capacitance.
AN261/0189
The thermal resistance, Rth, quantifies the capability of a given thermal path to transfer heat. The
general definition of resistance of the thermal path,
which includes the three different modes of heat
dissipation (conduction, convection and radiation),
is the ratio between the temperature increase above
the reference and the heat flow, DP, and is given by
the equation:
L1T
L1T
Rth=-L1P
L10
L1t
Where: L10 = heat
L1t = time
Thermal capacitance, Cth, is a measure of the capability of accumulating heat, like a capacitor accumulates a charge. For a given structural element,
Cth depends on the specific heat, c, volume V, and
density d, according to the relationship:
Cth=cdV
The resulting temperature increase when the element has accumulated the heat 0, is given by the
equation:
L1T = L10/Cth
The electrical analogy of the thermal behaviour for
a given application consisting of an active device,
package, printed circuit board, external heat sink
and external ambient is a chain of RC cells, each
having a characteristic time constant:
.
'1:= RC
To show how each cell contributes to the thermal
impedance of the finished device consider the simplified example shown in figure 1. The example device consists of a dissipating element (integrated
circuit) soldered on a copper frame surrounded by
a plastic compound with no external heat sink. Its
equivalent electrical circuit is shown in figure 2.
The first cell, shown in figure 2, represents the thermal characteristics of the silicon itself and is characterized by the small volume with a correspondingly
low thermal capacitance, in the order of a few mJ/C.
The thermal resistance between the junction and
1114
1229
APPLICATION NOTE
the silicon/slug interface is of about 0.2 to 2 °C/W,
depending on die size and on the size of the dissipating elements existing on the silicon. The time
constant of this cell is typically in the order of a few
milliseconds.
When power is switched on, the junction temperature increase is ruled by the heat accumulation in
the cells, each following its own time constant according with the equation:
~T = Rth Pd [1 - e(II1)]
The second cell represents the good conductive
path from the silicon/frame interface to the frame periphery. In power packages, where the die is often
soldered directly to the external tab of the package,
the thermal capacitance can be large. The time constant for this cell is in the order of seconds.
The steady state junction temperature, Tj, is a function of the Rth 0 a) of the system, but the temperature increase is dominated by thermal impedance in
the transient phase, as is the case in switching applications.
From this point, heat is transferred by conductionto
the molded block of the package, with a large thermal resistance and capacitance. The time constant
of the third cell is in the order of hundreds of seconds.
A simplified example of how the time constants of
each cell contribute to the temperature rise is shown
in figure 3 where the contribution of the cells of
figure 2 is exaggerated for a better understanding.
After the plastic has heated, convection and radiation to the ambient starts. Since a negligible capacitance is associated with this phase, it is
represented by a purely resistive element.
When working with actual packages, it is observed
that the last two sections of the equivalent circuit are
not as simple as in this model and possible changes
will be discussed later. However, with switching
times shorter than few seconds, the model is sufficient for most situations.
Figure 1 : Simplified Package Outline.
Figure 2 : Equivalent Thermal Circuit of Simplified.
<
~--...:!~"-,
MOLD
CHIP
~:rFRAME
R fh si
R th frame
R th mold
T'L_~J~~-Tamb
11-· L-IJ---l LU_ J ~.
C In 51
C Ih frame C
th mold
~-106n
5-10621
Figure 3: Time Constant Contribution of Each Thermal Cell (qualitative example).
'.118'
2/14
1230
8.B'
B.t
•
tB
T1t'E OR Pl.l..SE UIOTII ( A.U.)
tIl
tBBB
APPLICATION NOTE
EXPERIMENTAL MEASUREMENTS
When thermal measurements on plastic packages
are performed, the first consideration is the lack of
a standard method. At present, only draft specifications exist, proposed last year and not yet standardized (1).
The experimental method used internally for evaluations since 1984 has anticipated these preliminary
recomendations to some extent, as it is based on
test patterns having, as dissipating element, two
power transistors and, as measurement element, a
sensing diode placed in the thermal plateau arising
when the transistors are biased in parallel.
The method used has been presented elsewhere
(2) for the pattern P432 (shown in figure 4), which
uses two small (1000 sq mils) bipolar power transistors and has a maximum DC power capability of
40 W (limited by second breakdown of the dissipating elements).
A similar methodology was followed with the new
H029 pattern, based on two D-Mos transistors (3)
having a total size of 17.000 sq mils and a DC power
capability of 300 W on an infinite heat sink at room
temperature (limited by thermal resistance and by
max operating temperature of the plastics).
Figure 4.
a) P432 Test Die
b) P432 Measurement System
D.C.
SUPPLY
D.C.
SUPPLY
FAST
DVM
PULSE
GENERATOR
5 -1062311
3/14
1231
APpLICATION NOTE
Using the thermal evaluation die, four sets of
measurements were performed on an assortment
of insertion and surface mount packages produced
by SGS-Thomson Microelectronics. The complete
characterization is available elsewhere (4). The four
measurements taken were:
1) Junction to Case Thermal Resistance (Power
Packages)
2) Junction to Ambient Thermal Resistance
3) Transient Thermal Impedance (Single Pulse)
4) Peak Transient Thermal Impedance (Repeated
Pulses)
.
Figure 5.
a) H029 Test Die
b) H029 Measurement System
D.C.
SUPPLY
FAST
DVM
STORAGE
SCOPE
5-10624 11
4/14
1232
APPLICATION NOTE
Figure 6 : Set-up for Rth (j - c) Measurement.
PRESSURE CLIPPING
CONNECTION
THIN WIRES
1
WATER-COOLEO
COPPER SLOCK
~THERMAL
GREASE
5-97&5
THERMOCOUPLE
The junction to case thermal resistance measurements were taken using the well known setup shown
in figure 6 where the power device is clamped
against a large mass of controlled temperature.
The junction to ambient thermal resistance in still air,
was measured with the package soldered on standard test boards, described later, and suspensed in
1 cubic foot box, to prevent air movement.
The single pulse transient thermal impedance was
measured in still air by applying a single power pulse
of duration to to the device. The exponential temperature rise in response to the power pulse is
shown qualitetively in figure 7. In the presence of
one single power pulse the temperature, /!,.T max,
reached at time to, is lower than the steady state
temperature calculated from the junction to ambient
thermal resistance. The transient thermal impedance Ro, is obtained from the ratio /!,.Tmax/Pd.
Figure 7 : Transient Thermal Response for a Single Pulse.
+--____---=="'-____
Tamb _ L_ _
Pd
J_____ .Il-_ __
10
5-978L
5/14
1233
APPLICATION NOTE
The peak transient thermal impedance for a series
of repetitive pulses was measured by applying a
string of power pulses to the device in free air. When
power pulses of the same height, Pd, are repeated
with a given duty cycle, DC, and the pulse length,
tp, is shorter than the total time constant of the system, thetrain of pulses is seen as acontiuous source
with mean power level given by the equation:
Pdavg = Pd DC
(Pb/Sn) die attach. The tab of the package is a 1.5
mm thick copper alloy slug. The thermal model of the
MULTIWATT, shown in figure 9b, is not much different from that shown in figure 2. The main difference
being that when heat reaches the edge of the slug,
two parallel paths are possible ; conduction towards
the molding compound, and convection and radiation
towards the ambient. After a given time, convection
and radiation taked place from the plastic.
Figure 8 : Transient Thermal Response for
Repetitive Pulses.
Figure 9.
a) MULTIWATT Assembly
-Yb:~0\
I
I
I
I
I
I
I
' ... mb
---i---.-----------
Pd'
b) Equivalent Thermal Circuit
On the other hand, the silicon die has a thermal time
constant of 1 to 2 ms and the die temperature is able
to follow frequencies of some kHz. The result is that
Tj oscillates about the average value:
ATjavg = Rth Pdavg
The resulting die temperature excursions are shown
qualitatively in figure 8. The peak thermal impede
ance, Rthp, corresponding to the peak temperature,
DTmax, at the equilibrium can be defined:
Rthp = AT max/Pd = F (tp, DC)
The value of Rthp is a function of pulse width and duty
cycle. Knowledge of Rthp is very important to avoid a
peak temperature higher than specified values
(usually 150·C). .
EXPERIMENTAL RESULTS
The experimental measurements taken on several
of the packages tested are summarized in the following sections.
MULTIWATT PACKAGE
The MULTIWATT (R) package, shown in figure 9a, is
a multileaded power package in which the die is attached directly t9 the tab of package using a soft solder
6/14
1234
R th mold
TI
R th
C th
SI
C th frame
TC'tmb
S -10625
Using the two test die, the measured junction to
case thermal resistance is :
P432
Rth U c) = 2'C/W
H029
Rth U c) = O.4"C/W
The measured time constant is approximately 1 ms
for each of the two test patterns, but the two devices
have a different steady state temperature rise.
APPLICATION NOTE
The second cell shown in figure 9 is dominated by
the large thermal mass of the slug. The thermal resistance of the slug, Rthslug is about 1 °CfW and the
thermal time constant of the slug is in the order of 1
second.
The third RC cell in the model has a long time constant due to the mass of the plastic molding and its
low thermal conductivity. For this cell the steady
state is reached after hundreds of seconds.
For the MULTIWATT the DC thermal resistance of
the package in free air, Rth j a, is 36 °CfW with the
P432 die and 34SCfW with the H029 die.
POWER DIP PACKAGE
The power DIP package is a derivative of standard
small signal DIP packages with a number of leads
connected to the die pad for heat transfer to external heat sinks. With this technique low cost heat
sinks can be integrated on the printed circuit board
as shown in figure 12a. The thermal model of the
power DIP, shown in figure 12b accounts for the external heat sink on the circuit board by adding a second RC cell in parallel with the cell corresponding to
the molding compound.
Figure 10 shows the single pulse transient thermal
impedance for the MUL TIWATT with both the P432
and H029 test die. As can be seen on the graph, the
package is capable of high dissipation for short periods of time. For a die like the H029 the power device is capable of 700 to 800 W for pulse widths in
the range of 1 to 10 ms. For times up to a few seconds the effective thermal resistance for a single
pulse is still in the range of 1 to 3 °CfW.
The peak transient thermal impedance for the
MULTIWATT package containing the P432 die in
free air is shown in figure 11.
In this model, the second cell has a shorter time constant than for the MULTIWATT package, due in
large part to the smaller quantity of copper in the
frame (the frame thickness is 0.4 mm compared to
1.5 mm). Thus the capacitance is reduced and the
resistance increased.
The increased thermal impedance due to the frame
can partially be compensated by a better thermal
exchange to the ambient by adding copper to the
heat sink on the board. The DC thermal resistance
between the junction and ambient can be reduced
to the same range as the MULTIWATT package in
free air, as shown in figure 13.
Figure 10 : Transient Thermal Response MULTIWATT Package.
'"en
""'
:=
~
Pd .. 2
II
ILoal! 9 In air
!'III:l
'"""'
HE'l
diD siz
on die dt
~lpalin9
Pd .. 2 lJa l
B.BBI
B.Bl
B.l
TltE OR PULSE
2
.. 34.808
q.mi l:5
co .. 16.6
e
~q.mt l~
rrounlcd on board
lB
lBB
lBBB
LJIoru ( s )
7/14
1235
APPLICATION NOTE
Figure 11 : Peak Thermal Resistance MULTIWATT Package.
'"u"..,
DC - 0.5
28
l!:!
B.4
:;;
..,
8.3
I!'
II">
'"
!
'"....
19
-
----------
~
i!i
...:z::
0.2
I!l
UI
z:
a:
f!!
""
a:
~
5
~
B.1
~
DC-DUTY
~
eve
~
Pd - 5 IJaH
free air
E____ - _f.UJ._~_"!. DJ!L ___
PULSE REPETI ION PERIOD
19
10B
TIrE DR PULSE LJIDTH (
1999
1115 )
Figure 12.
oq
R!hSi
Tj
C thsi
R
a) Power DIP Package
8/14
1236
~~
thlr~mel-y~
C thtrame
5 - 10626
R th mold
Tamb
C th mold
LA~~
y~Tamb
C th board
b) Equivalent Thermal Circuit
APPLICATION NOTE
Figure 13 : Rth (j - a) vs. PCB Heat Sink Size 12 + 3 + 3 Power Dip.
- '"'"
~
u
...z:
'"~
'"
'"
1\
\
a:
...
0
~
z:
~
t:;
z:
.., '"...
::J
~
tJ
z:
a:
~
~
'"'"
""
...J
~
!!l
~
~
~
--.
Pd • 2 LbH
....
'"
H.IIB
II.SII
1.IIH
1.SH
2.HH
2.SI1
3.HH
3.S0
4.00
1 ( em )
As a comparison, figure 14 compares the thermal
performance of the power DIP and the MUL TIWA TT
package. It is clearly seen that even though the DC
thermal resistance may be similar, the MULTIWATT
is superior in its performance for pulsed applications.
Figure 14 : Transient Thermal Impedance for Single Pulses in Power DIP and MUL TIWATT
Packages.
S0
SIN LE
~
Pd
-
2
DIP(12.3. ) wilh
6 SU. eM 0 BOARD
HEAT SINK AREA
IR
e.l
TIf""E OR PULSE IJIDTH (
Ie
5
lBB
IBBB
)
9/14
1237
APPLICATION NOTE
STANDARD SIGNAL PACKAGES
In standard, small signal, packages the easiestthermal path is from the die to the ambient through the
molding compound. However, if a high conductivity
frame, like a copper lead frame, is used another path
exists in parallel. Figure 15 shows the equivalent
thermal model of such a package. The effectiveness
of a copper frame in transferring heat to the board
can be seen in the experimental results in DC conditions.
Table 1 shows the thermal resistance of some
standard signal packages in two different conditions ; with the device floating in still air connected
to the measurement circuit by thin wires and the
same device soldered on a test board.
Table 1 : Thermal Resistance of Signal Packages
Frame Thickness & Material
Rth (i-a) Floating
°C/W on Board
DIP 8
Package
(OA mm Copper)
125-165
78-90
DIP 14
(OA mm Copper)
98-128
64·73
DIP 16
(OA mm Copper)
95-124
62-71
DIP 20
(OA mm Copper)
85-112
58-69
DIP 14
(0.25 mm Copper)
115-147
84-95
DIP 20
(0.25 mm Copper)
100-134
76-87
DIP 24
(0.25 mm Copper)
67-84
61-68
DIP 20
(0.25 mm Alloy 42)
158-184
133-145
SO 14
(0.25 mm Copper)
218-250
105-180
PLCC 44
(0.25 mm Copper)
66-83
48-72
The transient thermal resistance for single pulses
for the various packages are shown in figures 16
through 20.
The results of the tests, as shown in the preceding
figures, show the true capabilities of the packages.
For example, the DIP 20 with a Alloy 42 frame is a
typical package used for signal processing applications and can dissipate only 0.5 to 0.7 W in steady
state conditions. However, the transient thermal impedance for short pulses is low (11 C/W for tp =
100 ms) and almost 7 Watts can be dissipated for
100 ms while keeping the junction temperature rise
belowaO'C.
The packages using a 0.4 mm Copper frame have
a low steady state thermal resistance, especially in
the case of the DIP 20. The thicker lead frame increases the thermal capacitance of the die flag,
which greatly improves the transient thermal impedance. In the case of the DIP 20, which has the largest die pad, the transient Rth for 100 ms pulses is
about 4.3'CIW. This allows the device to dissipate
an 18 Watt power pulse while keeping the temperature rise below 80'C.
As with the previous examples the peak transient
thermal impedance for repetitive pulses depends on
the pulse length and duty cycle as shown in figure
14. With the signal package, however, the effect of
the duty cycle becomes much less effective for longer
pulses, due primarily to the lower thermal capacitance and hence lower time constant of the frame.
Figure 15.
t
P 1h mold
Tamb
~Tamb
5 - 10627
S _10621111
a) DIP Package Mounted on PCB
C th
l~d
C th board
b) Equivalent Thermal Circuit DIP
Package on PCB
10/14
1238
APPLICATION NOTE
Figure 16 : Transient Thermal Impedance DIP 20 (alloy 42).
188
SINC LE
P .JLSE
:3
"
u
Pd • 1 W II
...
mounle
~
a:
~
In
W
'"
~
18
~
t-
z:
I!l
In
z:
a:
I!'
I
B.81l1
V
8.Bl
on board
/
-
/
V
on die di:) ~ipDling a eo .. 2.666
die pad·
25
x
B.l
TIrE OR PULSE WIDlll (
1GB
q.mil~
III
5
~q.mil:t
10B
lBBIl
)
Figure 17 : Transient Thermal Impedance 0.4 mm Copper Frame DIP Packages.
TIllE OR FULSE WID T~ (
5
J
11/14
1239
APPLICATION NOTE
Figure 18 : Transient Thermal Impedance 0.25 mm Copper Frame DIP Packages.
IIIB F = = " ' j = = = = j = = = " j = = = = q : = = = : q = = = " " l
on die
i&&lpalin
Be
area = 2.
&q.mlls
28
mount.ed an boa,..d
tt SIrlGL PULSE
Pd • 2
BB x 135 ... mi I.
18 x 128 • • mib
DIP 24 :
58 x 28B ... mil.
B.I
·O.BI
B.B81
DIP 28 :
nno: OR
I
IBB
19
IBBB
PULSE WIDTH ( s )
Figure 19: Transient Thermal Impedance 0.25 mm Frame PLCC Package.
,
58
GLE
SIt
'"
.::.
Pd •
!Joll
Ij
z:
1=
I!l
III
...
18
'V
'"...J
i!:
~
'"
/
t-
ili
III
z:
~
V
0.881
0.01
die
die
1240
V
/
od • 2Se
2Se "'l.rnl •
ize • 35. 88 eq.mile
on die dl slpatlng a ea
3'.1
nno: OR
12/14
~
PULSE
mounl donSMPC 5 board
Ie
PULSE
L/loTli (
5
= 2.BBB
sq.mils
lee
)
188e
APPLICATION NOTE
Figure 20 : Transient Thermal Impedance 0.25 mm Copper Frame S014 Package.
1DD
SING E
...
:3
PULS
u
'"
i1
r=
;;:
'"
'"
..J
18
~
'"
'"~
--->\<- - 2 Wall
5 Wall
0-
z:
~
Ul
z:
0:
e:
mount.d on 5M
ID
CB1 B 5G5 board
lOu
10000
1000
TItI: OR PL1.5E WIDTH ( ms )
Figure 21 : Peak Thermal Impedance 0.25 mm Copper Frame 14 Lead DIP.
S8
~
~
~
D':
=
I
8.4
0,~w
8.3
~~/
I
;::
~!!l
''""
--
8.2
...'"
~/
~/
'"a!
:3
-
I
0.5
u
~
I
I
/- /
+-..........--..-~-~ //
//
-",.,..-
/
--------
10
I-
0.1
~
n.
~ die
W
I
t
•
I
DCoDUTY
I
pad
rrome
coppe
eye
moun
=
T1~t[
d on board
lOB. E:'; S'1omils
lh ickne::." '" 6.4 rrvn
E:- • __ . f.U.!.",!,. ~Ll .TtL ____
PULSE REPETIT ON PERIOD
180
10
0.1
Pd • 2 WaH
//
OR PULSE WIDTH (
WI>
)
13/14
1241
APPLICATION NOTE
CONCLUSION
This paper has discussed a test procedure for
measuring and quantifying the thermal characteristics of semiconductor packages. Using these test
methods the thermal impedance of standard integrated circuit packages under pulsed and DC conditions were evaluated. From· this evaluation two
important considerations arise:
1) The true thermal impedance under repetitive
pulsed conditions needs to be considered to maintain the peak junction temperature within the rating
for the device. A proper evaluation will result in junction temperatures that do not exceed the specified
limits under either steady state or pulsed conditions.
2) The proper evaluation of the transient thermal
characteristics of an application should take into account the ability to dissipate high power pulses
14/14
1242
allowing better thermal design and possibility reducing or eliminating expensive external heat sinks
when they are oversized or useless.
REFERENCES
(1) SEMI Draft Specifications 1377 and 1449, 1986
(2) T. Hopkins, R. Tiziani, and C. Cognetti, "Improved thermal impedance measurements by
means of a simple integrated structure", presented
at SEMITHERM 1986
(3) C. Cini, C. Diazzi, D. Rossi and S. Storti, "High
side monolithic switch in Multipower-BCD technology", Proceedings of Microelectronics Conference,
Munchen November 1986
(4) Application Notes 106 through 110, SGSTHOMSON Microelectronics, 1987
APPLICATION NOTE
THERMAL MANAGEMENT IN SURFACE MOUNTING
The evolutionary trends of integrated circuits and
printed circuits boards are, in both cases, towards
improved periormance and reduced size, From
these points of view, a factor of major importance
has been mutual thermal interaction between ICs,
even those with low dissipation.
2) Package Related Factors
• thermal conductivity of the frame
• frame design
3) Substrate Related Factors
• thermal conductivity of the substrate
It follows then that thermal design of medium and
high density applications has evolved to include factors such as power effects, die size, package thermal resistance, integration level of active devices
and substrate type. Added to this a trend towards
greater use of switching techniques exists.
• layout
Therefore a number of parameters can change the
thermal characteristics. These cannot be described
by a single thermal resistance, in fact a set of experimental curves gives the best presentation.
Today, in order to design reliable application circuits, it is necessary to have complete data on package thermal response characteristics. In fact, it is a
well known and long established fact that device lifetime has an exponential relationship with junction
temperature.
JUNCTION TO AMBIENT THERMAL
RESISTANCE Rth(j-a)
PRELIMINARY CONSIDERATIONS
At a given dissipation level Pd, the increase in junction temperature L\ Tj over ambient temperature T a
is given by :
Heat dissipation for DIPs with a low thermal conductivity frame (e.g. Alloy42) is due to convection and
irradiation from an emiting area corresponding to
the silicon die and the package die pad.
Since heat transmission through the lead frame is
very poor, dissipation does not depend greatly on
substrate type. In fact, samples soldered on printed
circuit boards, or inserted in connectors have nearly the same dissipation capability as samples suspended in air. The difference, in the range of just
10%, is commonly ignored and specifications for insertion ICs only give one thermal resistance value,
which is more than adequate for good thermal design.
The question then arises, is the approximation valid
for SO and PLCC packages?
The answer is no ! Thermal characteristics for these
devices are influenced by many factors.
1) Device Related Factors
size of the dissipating element
dissipation level
pulse length and duty cycle
AN262/0189
RthU-a) represents the thermal resistance of the system and comprises the silicon die, the package, and
any thermal mass in contact with the package to
dissipate heat to the ambient.
= RthU-a) X Pd
Rthlj-a) is made up of many elements both within the
device and external to it.
If the device is considered alone, Rth(j-a) is given by
the dissipation path from the silicon die to the leadframe, to the molding compound, to the ambient.
Experimental values are very large in this condition, especially for small packages such as
Small Outline types.
However, this situation is not met in practice and experimental data included in the present work indicates the worst case (floating samples). In most
applications, Suriace Mount Devices are soldered
onto a substrate (commonly epoxy glass (FR4) and
are in thermal contact with it through the soldered
joints and the copper interconnections. In this case,
the heat generated by the active circuit is transferred
to the leadframe and then to the substrate. A new
dissipation path thus exists in parallel with the previous one whose efficiency depends on the thermal
conductivity of the frame and on the length of the
printed circuit's copper tracks. Figure A shows the
experimental module.
L\Tj
1/14
1243
APPLICATION NOTE
Figure A : Device Soldered to the Best Board, for
Junction to. Ambient Thermal Resistance Measurement.
In high power applications R- .. Rhs and RthU-a)
= Rth(j-c) + Rhs
JUNCTION TO PIN THERMAL RESISTANCE Rth(j.p)
TEST DEVICE
p?
TEST BOARD
L.P'
CONNECTION
PINS
5-10673
In medium power packages RthU-p) is the thermal resistance of the heat transfer leads, from the junction
to the external heatsink. In most cases the external
heatsink is integrated on the board. Figure C shows
the experimental setup.
Figure C : Junction to Pin Thermal Resistance
Measurement.
PRESSURE CllPP1NG
JUNCTION TO CASE THERMAL RESISTANCE Rth(j-c)
CONNECTION
THIN WIRES
Rth(j'c) is the thermal resistance from the junction to
a given area of the peackage's external surface
where a heatsink is applied.
In signal packages, a suitable area is its upper surfac~. Measurements are made with the samples
in good thermal contact with an infinite heatsink
(fig. B).
===.,.
I
HEAT TRASFER LEAD
;~~~~§§~5_=-~-:."sOLDERED
WATER-COOLED
COPPER-BLOCK
' - - THERMAL
JOINT·
-7
GREAS~
5-9783
THE RMOCaUPLE
Figure B : Junction to Case Thermal Resistance
Measurement.
TRANSIENT THERMAL RESISTANCE FOR
SINGLE PULSES
PRESSURE CLIPPING
The electrical equivalent of heat dissipation for a
module formed by an active device, its package, a
PCB and the ambient, is a chain of RC cells, as
shown in fig. D, each with a characteristic rise time
('1:) = RC.
WATER- COOLED
COPPER - BLOCK
THERMAL
GREASE
Figure D : Equivalent Thermal Circuit Simplified
Package.
5-9150
THI!RMOCOUPLE
When a heatsink of thermal resistance Rhs is attached
to the package, the following relationship is valid:
Rhs x RRth(j.a) = RthU-c) +
R th si
R th frame R th mold
Ti
C th si
C th frame
C t h mold
5-10622
Where R- takes into account all the othfr dissipation
paths (i.e. junction/frame/substrate). R is the lowest
with low thermal conductivity frames.
2/14
1244
APPLICATION NOTE
The thermal capacitance of each cell is a measure
of its ability to accumulate heat and depends on the
specific heat, volume and density of the constituent
materials.
Figure F : Temperature Rise for Repeated Power
Pulses.
When power is switched on, the junction temperature after time it is governed by the heat impedance
of the cells, each of which follows its own time constant - this is analogous to the exponential charge
of RC cells in an electrical circuit.
For a pulse lenght to, the effective Tj can be significantly lower than the steady state Tj (fig. E) and the
transient thermal resistance Rth(to) can be defined
from the ratio between the junction temperature at
the end of the pulse and the dissipated power.
I
I
I
I
I
lamb
I
-~-l---~~-
,
,
Figure E : Temperature Rise for Single Power
Pulse.
The thermal resistance corresponding to the peak
of the steady state oscillations (peak thermal resistance indicates the maximum temperature reached
by the junction and, depending on duty cycle and
pulse width, may be much lower than the DC thermal resistance.
S-97BL
Obviously, this parameter is smaller for shorter pulses and higher power can be dissipated without exceeding the maximum junction temperature defined
from a reliability point of view.
The knowledge of transient thermal data is an important tool for cost effective thermal design of
switching applications.
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES
When pulses of the same height Pd are repeated
with a duty cycle, DC, and a pulse width to, which is
shorter than the overall system time constant, the
train of pulses is seen as a continuous source of
mean power Pdavg, where:
Pdavg = Pd x DC
However the silicon die has a time constant in the
order of 1 to 2ms and is able to follow frequencies
in the kHz range. Thus junction temperature oscillates about an average value given by :
Tjavg = Rth x Pdavg
as is graphically shown in fig. F.
EXPERIMENTAL METHOD
Measurements were performed by means of the especially developed thermal test pattern P432, which
is designed according to the Semiconductor Equipment and Materials Institute (SEMI) G32 guideline.
Test chip P432 is based on a dissipating element
formed by two npn transistors, each with 1OW power
capability, and one sensing diode (fig. G). The diode
is placed on the temperature plateau generated
when the two transistors are biased in parallel, and
gives the actual junction temperature Tj of the dissipating element, through the calibration CUNe (fig. H)
of its forward voltage Vf versus temperature at a
constant current of 100flA.
Figure G : ~hermal Test Pattern P432.
3/14
1245
APPLICATION NOTE
Figure H : Calibration Curve of P432 Temperature Sensing Diode.
V,
(mV)
680
MB'JTIZ 01
"
I"
Figure J : Test Board Lay-out for SO Packages
(150 mils body width)
Board size is : 23 x 42mm2.
I"
600
500
.'
ld =100 JJA
1
1
1
400
20
40
60
00
iOO
120
T
(OC)
Transistor size is intentionally limited to 1000sq.
mils, in order to simulate high power density, characterizing a worst case. Die size, which is found to
have little influence on thermal resistance when a
copper frame is used, is slightly smaller than the die
pad size and never exceeds 30k sq mils even in the
largest packages such as high pin count PLCCs.
Figure K : Test Board Lay-out for SO Packages
(3000 mils body width)
Board size is 38 x 43mm 2.
The measurement setup is shown in fig. I. it is compatiblewith DC and AC supplies and has an accuracy of better than 5%.
Figure'l : Experimental Setup.
Figure K : Test Board for PLCCs
Board size is 58 x 58mm 2 .
The advantages offered by the test pattern are:
• high power capability
• repeatable VI and temperature
(1.9mv(C) of the sensing element
coefficient
high resolution in pulsed 'conditions (1 OOIlS)
• better correlation from one package to another.
Both Alloy 42 and copper frames were considered
for narrow SO packages (150mils body). For wide
SO (300mils body) and PLCC packages only copper frames were examined. Suitable test boards
were deyeloped (figs J, K and L).
4/14
1246
APPLICATION NOTE
MEDIUM POWER PACKAGES
Figure N : Lead Frame for Medium Power 8020.
While surface mountsignallCs are readily available,
almost all power ICs are still assembled in traditional
insertion packages.
Medium power 8M packages (Pd < 2W) can readily be derived from existing small outline and chip
carrier packages by modifying the leadframe - in
much the same way that Powerdip packages were
derived from standard Dips.
This approach is particularly attractive because the
external dimensions of the package are identical to
existing low power packages, allowing the use of
standard automatic assembly and test equipment.
Frame modification is aimed at obtaining a low junction to pin thermal resistance path for the transfer of
heat to a suitable external heats ink. A number of
leads are connected to the die pad for this purpose.
Two possibilities are considered here: a medium
power PLCC44 with 11 heat transfer leads (fig. M)
and a medium power 8020 with 8 heat transfer
leads (fig. N).
Figure M1 : Test.80ard for Medium Power
PLCC44.
A cost effective heat spreader can be obtained on
the board by means of suitably dimensioned copper
areas. The heat transfer leads are soldered to there
areas (fig. Ml , Nl).
Figure M : Lead Frame for Medium Power
PLCC44.
Figure N1 : Test Board for Medium Power 8020.
5/14
1247
APPLICATION NOTE
THERMAL DATA OF SIGNAL PACKAGES
SUMMARY OF JUNCTION TO AMBIENT THERMAL RESISTANCE IN STEADY STATE POWER DISSIPATION (SGS'THOMSON test board)
Rth (i·a)
Die Size (millinches)
Power PO [W]
808 Alloy 42
Copper
90 x 100
94 x 125
0.2
0.2
250-310
130-180
8014 Alloy 42
Copper
Copper
98 x 100
78 x 118
98 x 125
0.3
0.5
0.7
200-240
120-160
105-145
S016 Alloy 42
Copper
98 x 118
94 x 185
0.3
0.5
180-215
95-135
S016W Copper
120 x 160
0.7
90-112
S020 Copper
140 x 220
0.7
77-97
PLCC-20 Cu
180 x 180
0.7
90-110
50-60
Rth(j-a)
[OC/W] on Board
PLCC-44 Cu
260 x 260
1.5
PLCC-68 Cu
425 x 425
1.5
40-46
PLCC-84 Cu
450 x 450
2.0
36-41
values correspond to low and high board density
SUMMARY OF JUNCTION TO CASE THERMAL RESISTANCE
Die Pad Size (millinches)
[DC/W]
Rth(j-a)
PLCC20
140 x 140
25
PLCC44
260 x 260
13
PLCC68
425 x 425
10
PLCC84
450 x 450
9
JUNCTION TO AMBIENT THERMAL RESISTANCE IN STEADY STATE POWER DISSIPATION
Figure 1 : S08.
Figure 2: S014.
I-'IS9T1Z 02
!
i
Rth j-a
("e/wl
.\
MIl9 TIZ OJ
Rlhj-a
DIE PAD=94x125sq milS.
I
t"e/wl
DIE SIZE::; 60 x90 sq. mils
260
...........
220
I---- I--
"I
,
I
-
,
f------ 1-180
......
ioa
.60
SM, PCB1A BOARD
I----I-
100
-
_.......
r-:
,
0,2
6/14
1248
I
I
Of,
i'...
........
MOUNTED ON:
~
140
I
I
IN AIR
06
5M PCBI
BOAR~-
120
ALUMINt
I
08
Plot (W)
80
........
r--..
-
'-
04
.....
FLOATING IN Al
~OUNTEO
I
ON:
SM PCB 14 BOARD
SMPCB 180ARD
AlUMINA
1.2
1.6 Ptot(W)
APPLICATION NOTE
Figure 3 : S016.
Figure 4 : S020.
M89't,Z 07
1-18911Z 04
210
I
,
140
100
....
....
-
i"--.
r-- FLOAr NG
I
tI
\
DIE PAO=Il,Q x220sq. mils
DIE SlZE:= 5000 sq. mils
..........
FLOATiNG IN AIR
I I I I
120
"- .........
100
SMPCB1BO:{
ALlt'Nl
OB
r-
AIR
SMFU31ABOARD
60
I I I I
[\"
140
OU~TEO ~N'
--
J I I I
I'C)
OlE SIZE = 60.90 sq. mils
.........
180
Rthj _a
1.2
.......
80
I I I I
""-
"-
MOUNTED ON SM PC82A BOARD
"I
MOuNTED ON SMPCBZ BOARD
I
Figure 5 : PLCC20.
DB
0.4
1.6 Ptot (W)
1.2
Figure 6 : PLCC44.
M89 TZ
I. 05
160
\
.........
r- -
100
60
P
I
__ rr=
[\"
120
M 89T IZ. 0 B
DIE SIZE :=80xllOsq. mils
DIE PAD =140.oclt.Osq.mils
r----:
-_~O'TlNG IN AIR
---
~ ;;;;:.
\
70
_\
60
MOUNTED ON"
SM PCB SA BOARD
__ Ll.
-_.
h
._-
50
"-~
'" -
~/,£;INAIR
"""""- r-
"'-
I
I
"'"- i--
MOUNTED ~:
M PCB SA 8OARO
I
J;M PCB '5 BOARD
1
5MPCB580ARD
l J
60
0.4
I
I
OlE SIZE:= 35.000 sq. mils
DIE PAD = 260. 260 sq.mils
so
as
!
40
1.2
0.5
i
1.5
,
i
2.5 PtotlW)
Figure 8 : PLCC84.
Figure 7 : PLCC68.
M!!9TIZ 05
Rthj_a
tOCIW)
DIE SIZE
= 35.000 sq. mils
DIE PAD =425)(4255
60
50
50
\
..
~
!\.
........
DIE AREA = 35.000 sq. mils
DIE PAD !: 450ll.t.50sq mils
mils
'I
55
MB9TIZ 09
Rthj_a
("C/W)
""
"'-..
45
-
"'"-
~G[NAIR
45
40
i'-
40
MOuNTED ON SM PCg 6ARD
I
35
0.5
1.5
I
"-
35
2.5 PtcdW)
U5
-
FLOATING IN AIR
-
:----
._--
-
~NTED
1.5
ON 5M PCB 5 BOARD
2.5Ptot(W)
7/14
1249
APPLICATION NOTE
JUNCTION TO AMBIENT THERMAL RESISTANCE VS BOARD LAY-OUT
(area of copper tracks on the board)
Figure 9 : 8016.
Figure 10: 8020.
M89 TIZ 12
MB9 TIz'lO
Rthj-a
('CIW)
Rthj_a
("C/W)
130
Ptol :lW
DIE SIZE = SOOOsq mils
BOARD SIZE:;: 2.8 sq. Inch
DIE SIZE:;: 60 Jt90sq. mils
BOARD AREA =0.72 sq. mils
1\
\
110
Pd ::: lW
f\
\
,20
100
\
110
\
1\~
90
r\
"-
100
~
90
40
80
-
120
-
.........
1""-
80
r- S016WIDE
'"
f-
SO 20
10
150
50
150 AI (xl(X)O
350 At (x 1000
250
sq. mils)
sq.mlls)
Figure 12 : PLCC20.
Figure 11 : PLCC44.
MB9TIZlJ'
M89 TIZ 11
Rthj-a
('e,We)
62
60
56
56
54
1
1 I
I! I
\'
Rthj-a
("CIW)
1
DIE SIZE = 35.000 Sq mils
DIE PAD::: 260 x 260 sq. mils
Ptol ::: lW
100
I
\ i
I
95
I
90
-'1
1
!
1\'
\
I
I
.I
I
I
52
I
!'+,
1 j
50
100
ZOO
JOO
I
L
400
I
65
:
80
-H-+
1 1
i
500
1250
\
, ,
,
T :,
I
'{
I\.
I
I
600 .0.\ (xIODO
I
100
I
i
i
I
~
I
1
I'l
,
I
50
1
I
I
.r-....
15
-~-
I
\
10
sq mils)
8/14
I
1
!
!
I
I
~-
I
\1
1 !
I
I 1 IP'o' ~lW
1 i :~:~ ~~z~ ;l~g :,'ig~· :i/:
150
I
!
200
-
;
250
At (x 1000
sq mils)
APPLICATION NOTE
TRANSIENT THERMAL RESISTANCE FOR SINGLE PULSES
Figure 14: S014, 16.
Figure 13: SOB.
M89
~
M89Hl,II,
R'h
R'h
SINGLE PULSE
MOUNTED ON SMA:81 BOARO
("CIW )
/ 'I - -
Ptol =lW
100
SINGLE PULSE
{OCIW )
PIOI ::: 1.SW
100
60
60
40
40
V
/7
SO 14
20
V
10
V
V
10
IE SIZE ::60x90 sq. mils
IE 00 ::94 x12Ssq. mils
pN DIE Ad :: 2000sq. mils
/
~
-
5016
MOUNTED ON 5MPCBl BOARD
OrE SIZE:: 60)( 90 sq. mils
ON DIE Ad :::lOOD sq. mils
10
10
Figure 16 : PLCC44.
Figure 15: S020.
MB'lTIZ
R,h
("GW)
M8911l18
I;'
R'h
SINGLE PULSE
MOUNTED ON SM peal BOARD
Ptol -lW
40
("(IW)
/
/
20
/
_.
L
BOARD ~
!------ P~\~;~L;~MPCB5
IOI :: 2.W
V
/
20
10
-
10
L
V
/
/
I
ON DIE Ad :: 2000 sq. mils
DIE PAO=l.l,O 11.220 sq. mils
DIE srZE:: 5000 SQ_ mils
/
DIE SIZE:: J5.000sq. mils
/
~I_E PAD:: 260 x 260sq mils
N DIE Ad::; 2. 000 sq. mils
II
Hr'
10
10 7 T{ 5)
'0
Figure 18: PLCCB4.
Figure 17 : PLCC6B.
M89TIl19
M89TI-16
Rth
~
('C/W)
c---
~1~~~~ED~S~MPCB5 BOARD ~
SINGLE PULSE
MClLNTEP ON SM PCBS BOARD
P tot =2W
20
V
10
R,h
("(IW )
~
Pto t=2W
20
!------
/
10
-;z
~
I-----
--
/
/
/
V
/
V
DIE SIZE:: 35.000sq mils
DIE PAD:: 300 x 300 sq. mils
ON DIE Ad :1.000sq.rnils
10
V
/
DIE SIZE '= 35.000 sq. mil s
DIE PAD 350 1\ 350 sq. mils
ON DIE Ad =2.000 sq. mils
=
10
9/14
1251
APPLICATION NOTE
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES
Figure 19: 8014.
Figure 20 : 8020.
OC=O.5
M'UNTED ON SM FeB 1 BOAHC
..
Ptot =ZW
10
4
..........:
OJ
30
~
0.1
20
~
--/
----
~
-- /
DC =0.5
50
10
---; ~
.I
O~
~
I-""""'
..-
./
tot=ZW
MOUNTED ON SM pca2 BOARD
PlJLS:~~~E~ID;:RIOD
DC=DUTYCVClE
f----
~U~~~~~~~~ PERIOD
-
---
L----
0.1
10
~v
DUTY CYCLE = PUl
-
M89TI110
M89TIZ22
Rih
("C!wl
10
Wi
10
T (ms)
10 2
10
T (ms)
Figure 22 : PLCC68.
Figure 21 : PLCC44.
M89T1Z 21
M89iIZ.])
R'h
'"CIW)
i-----t-===-;;t==""',6"'---j
OC=0.5
30
-~
OC"O.5
0.4
0.2
20
10
0.3
0.1
/'
./'
0.1
(l()5
10
~
Plot:: ZW
MOUNTED ON SM PCBS BOARD
DIE PAD:: 300
;J(
DC =CUTY CYCLE
300 sq. mils
PULSE WIDTH
PULSE REPEl PERIOD
10 2
10
T (ms)
Figure 23 : PLCC84.
--
DC =0.5
20
10
lIZ.2t.
"
Rth
:OCIW)
-0.2
01
0.05
~
---
~
V-
Ptol "SW
MOUNTED ON 5i'Y1R:85 BOARD
DIE PAD=J5D J:350sq, rnils
OC= DUTV CYCLE
10
10/14
1252
PULSE WIDTH
PU..5E j:£PETIT. PERIOD
10 2
T (ms)
10
10 2
T(ms)
APPLICATION NOTE
THERMAL DATA OF MEDIUM POWER PACKAGES
Rth(J-p)
[OC/Wj (AVERAGE)
Rth(l-a)"
80(12+4+4)
14
50
PLCC (33 + 11)
12
41
[OC/Wj
" with 6 sq. em. on board heat-sink.
JUNCTION TO PINS THERMAL RESISTANCE VS ON DIE DISSIPATING AREA
Figure 24: SO (12 + 4 + 4).
Figure 25 : PLCC (33 + 11).
t.o189TI128
M8911Z 25
RthJ_p
('Clwl
Rlhj_c
('CIW)
I
15
"" "-
11,'.5
"
12
-
"
r-
11
OlE SIZE ~ 20.000 sq mils
DIE PAO::140x220sq mIls
Ad :: 35.0.0.0. sq. mils
1
J
10
13
12
\6 Ad "'.1000
Sq.ffit(S)
10.
12 Ad(xlOOO
sq mils)
JUNCTION TO AMBIENT THERMAL RESISTANCE VS AREA ON BOARD HEAT-SINK
Figure 26: SO (12 + 4 + 4).
MB9TIZ2fi
Rthj_a
("CfW)
15
10
65
DIE SIZE - 120. x 130. sq. mils
DIE PAD::: 140. x 220. sq. mils
1\
P tot :IW
\\
\
'\,
.......
50
I"- -..
45
11/14
1253
APPLICATION NOTE
Figure 27 : PLCC (33 + 11).
M89 Til
n
Plot = 1.5 W
Tcopper = 35 ~
50
".6
"-
~
............
42
i'-..
~
38
TRANSIENT THERMAL RESISTANCE FOR SINGLE PULSES
Figure 28: SO (12 + 4 + 4).
Figure 29 : PLCC (33 + 11).
M891IZ 37
Rth
:"CIW)
SINGLE PULSE
MOUNTED ON BOARD
50
wn H:
NO HEAT
20
10
10
pulse length = 0.1 - 10ms.
Figure 30 : PLCC (33 + 11).
M aCT
~ I2 _30
Rth
("C/W )
I
20
. NOHEAT/
16
~
IV
14
12
/
"./
~ ~O"
,.,..
....-
HEAT SINK = 2 sq em
l
SINGLE PULSE
MOUNTED ON SMPC86 SOARD
10
I
o
pulse length = 1 - lOs.
12/14
1254
T (s)
APPLICATION NOTE
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES.
Figure 31 : PLCC (12 + 4 + 4).
Figure 32 : PLCC (33 + 11).
M8!) TIZ. 31
Rth
(OC/W)
MOUNTED ON BOARD WITH 9sq. em
COPPER AREA HEAT SiNK
DIE PAD;: IloO x 220 sq. mils
'0 j--'o:;.::c'-'-o"'OS'-t-_ _-,.._ _-"!'===-d
20
DC= 0.5
F=O::-'::j--==:::j:::-::::=t~~
0.'
0.2
to
OC ;: DUTY C'l'CLE
0.1
:_-,-P~UL=SE=-w",IO::cT,,-H_ _
PULSE REF£TnION PERIOD
to
10 2
T (ms)
APPLICATION EXAMPLES O.F THERMAL
DATA
Good thermal design begins with system and reliability considerations. This turn is based on correct
consideration of ambient and device temperature
parameters.
10-'
to
10 2
T (ms)
good reliability, takes into account the activation energy of the failure mechanisms which may differ for
various silicon and packaging technologies.
In plastic packages the maximum Tjmax is 150°C,
but lower values (100 to 120°C) may be specified in
high rei applications such as telecoms.
The ambient temperature Ta defined for applications
can range from 50 to 55°C, as is common in many
consumer and computer applications, through to
80°C or more in applications such as automotive systems. The ambient temperature depends on the various heat and cooling sources surrounding the device.
An important factor in device lifetime is junction temperature -lifetime is approximately halved when junction temperature Tj is increased by 10°C. The
maximum junction temperature commensurate with
When Tjmax and Ta are known, their difference Ll.Tj
indicates the permissible junction temeperature rise
for a given device. For a given power dissipation Pd,
the thermal design must ensure that the product Pd
x Rth(j-a) is lower than Ll.Tj ; where RthO·a) is the thermal resistance of the device from the junction to the
ambient at temperature Ta. This takes into consideration the many elements connected to the heat
source and includes the leadframe, moulding compound, substrate and heatsink, if used.
EXAMPLE 1 : Maximum dissipation for S016
packaged device soldered onto an FR4 board
(1 oz copper) under the following conditions:
SOLUTION
• Ambient temperature: Ta = 70°C
• Maximum Junction Temperature: Tjmax = 130°C
The average length of the 12mils wide copper line
connected to each pin is 80mils, soldering pads are
30 x 40mils. The total are is thus:
A
= [(80 x 12) + 1200 x 16] = 34560sq.mils
From fig. 13, the value for Rth(j.a) is 125°C/W for a
copper frame package. Comparing figs. 5 and 6, a
value of about 240°C/W can be assumed for Alloy
42 packages. The allowed rise in junction temperature is : Ll.Tjmax = 130 - 70 = 60°C
Maximum dissipation is given by Ll.Tjmax/RthO-a).
Therefore:
60/125 = 0.48W for Copper frame
60/240 = 0.25 for Alloy 42 frame
13/14
1255
APPLICATION NOTE
EXAMPLE 2 : Junction temperature for an S020
packaged device soldered on FR4, under the following conditions:
SOLUTION
• Ambient temperature Ta = 70°C
• Thermal Resistance Rth(j.a) = 90°C/W
• Dissipated Power Pd = 0.6W
A total trace-area of 200k sq.mils is assumed,this
then gives, from fig. 14 :
IITj = Pd x Rth(j.a)
• t,Tj=0.6x90=54°C
• Junction Temperature Tj = 54 + 70 = 124°C
EXAMPLE 3 : To determine the size of an integrated heatsink for a medium power application
using a PLCC (33 + 11) under the following conditions:
Ambient temperature Ta = 50°C
SOLUTION
By calculation the application needs an Rth(j-a) of :
(150 - 50)/2.2 = 45.5°C/W
From figure 32 the on board heatspreader can thus
be defined as needing an area of about 2 sq.cm.
Max. Junction Temperature Tjmax = 150°C
• Dissipated Power Pd = 2.2W
EXAMPLE 4 : Given the application described in
example 3 determine the maximum pulse width
for a single 4W pulse superimposed on a continuous 1.5W dissipation
SOLUTION
The continuous steady state junction temperature
at 1.5W dissipation is :
Tjss = (1.5 x 45.5) + 50 = 11B.25°C
The single pulse is allowed to cause a maximum increase of (150 - 11B.25°C) = 31. 75°C.
The related transient thermal resistance is (31.75/4)
= 7.9°C/W
From figure 33, the corresponding pulse width can
pe interpreted as being in the order of 200ms.
EXAMPLE 5 : In a medium power application
using an SO (12 + 4 + 4) calculate the average
junction temperature and the peak te!"peratur~
for repeated pulses under the followmg condItions :
• Ambient temperature Ta = 70°C
• On board heatsink area A = 9 sq.cm.
Pulse length = 100ms
• Pulse height = 5W
• Duty cycle = 20%
14/14
1256
SOLUTION
From figure 31, the thermal resistance is found to
be 49°C/W. Thus the average junction temperature
can be calculated:
Tjavg = (5 x 49 x 0.2) + 70 = 119°C
From figure 36, the peak thermal resistance is given
as around 15°C/W. The peak temperature can thus
be calculated as :
T p = (5 x 15) + 70 = 145
APPLICATION NOTE
THERMAL CHARACTERISTICS
OF THE MULTIWATT PACKAGE
By R. T1ZIANI
INTRODUCTION
This Application Note provides a complete thermal
characterization of the Multiwatt ® package (multilead double TO-220 - fig. 1).
Characterization is performed according with recomandations included in the G32-86 SEMI guideline, by
means of a dedicated test pattern. It refers to :
1. Junction to case thermal resistance Rth(j.c)
2. Junction to ambient thermal resistance Rth(j.a)
3. Junction to ambient thermal impedance for single pulses and repated pulses, with different
pulse width and duty cycle;
4. Thermal resistance in DC and pulsed conditions,
with a typical external heat sink.
Most of the experimental work is related to the thermal impedance, as required by the increasing use
of switching techniques.
Figure 1 : Multiwatt Assembly.
a power capability of 20W. Measurement method is
described in Appendix A.
Samples with the indicated characteristics were prepared:
Package Multiwatt 15 leads
Frame Material
Copper
Slug Thickness
1.5mm
Slug Thermal Conductivity
3.9W/cmoC
Die Attach
Soft (PbSn)
Measurement of junction to case thermal resistance
Rth(j.c) is performed by holding the package against
a water cooled heat sink, according with fig. 2. A
thermocouple placed in contact with the slug
measures the reference temperature of the case.
For junction to ambientthermal resistance Rth(j.a) the
samples are suspended horizontally in a one cubic
foot box, to prevent drafts.
Both DC and pulsed conditions are used; in the second case the contribution of package thermal capacitance is effective and transient thermal
resistances much lower than the steady stata
Rth(j.a) can be found, according to pulse length and
duty cycle.
The effect of the external heat sink is quantified,
using as test vehicle the commercially available heat
sink THM7023 especially developed by Thermalloy
for the Multiwatt package, whose thermal resistance
in still air is about g"CIW.
The measurement circuit shown in fig. A3 was used
for all the thermal evaluations.
EXPERIMENTAL CONDITIONS
The thermal evaluation was performed by means of
the test pattern P432, which is a 20K mils2 die with
a dissipating element formed by two transistors
working in parallel and one sensing diode. In order
to characterize the worst case of a high power density IC, the total size of the element is 2K mils2 with
AN257/0189
JUNCTION TO CASE THERMAL RESIS·
TANCE
The dependance of
is reported in fig. 3.
Rth(j-c)
on the dissipated power
It is well known that the main contribution to Rth(j-c)
of power packages in given by the silicon die.
1/8
1257
APPLICATION NOTE
Figure 2 : Measurement of Rth U-c).
Figure 4 : RthU-c) Thermal Resistance vs. Die Size
and on Die dissipating Area.
MB8MUll 02
RTHj_c
("CIW)
PRESSURE CLIPPING
1.5
~
CONNECTION
THIN WIRES
diE" size ,,51'1 sq. mIls
...,.,
1.5
12K
....... .......
20K
I"- r-
15K
05
10
THERMOCOUPLE
JUNCTION TO AMBIENT THERMAL
RESISTANCE
Figure 3 : Rth U-c) of Multiwatt Package vs. Power
Level.
M88MUL1.01
RTHj--c
(·CIW)
1-:-+-+-t----i-t-+--+-+-1---1
2.5
1-:-+-+-t----i-'--t-+--+-+-1---1
23
1~t:t=t=Ft=rt-H
I--
P1,32
In medium power applications (1.5-2W), the Multiwatt package can be used without external heat
sink, thanks to the significant size (about 3.5cm 2 ) of
its integrated thermal mass_
Its RthU-a) has two contributions: the RthU-c), mainly
due to the silicon die (as shown in fig. 4) and the
thermal resistanc~ of the copper slug Rth slug.
Figure 5 : RthU-a) of Multiwatt Package vs. dissipated Power.
M6BMLJlT 03
Pl.3Z
I,
I........ ........ .......
2.2
.........
2.1
die size ::20.000 sq.mils
dissipating area:: 2.000 sq. mils
9
PtotlW)
FOR DEVICES OTHER THAN THE TEST PATTERN P432 THE CALIBRATION CURVE OF
FIG. 4 IS NEEDED.
It shows the relationship between RthU-c) and the
dissipating area existing on the silicon die (power
diodes, power transistors, high current resistors), for
different die sizes.
218
1258
15
-
r-
FREE AIR
MOUNTED ON PCB SOARD
20
10
l -I-- MOUNTED ON THM 7023 HEAl
SINK
DIE SIZE:: 20.000 sq. mils
OISSIPATIf\(3 AREA WOO sq. mils
=
1.0
2.0
3D
4.0 Ptot(W)
APPLICATION NOTE
Fig. 5 gives the relationship between Rth(j.a) and the
power dissipation level for the P432 test pattern is
still air, on PC board and on a commercial heat sink.
IN ORDER TO HAVE AN ACCURATE VALUE FOR
OTHER DEVICES, WITH DIFFERENT DIE SIZE
AND DISSIPATING AREA, VALUES OF FIG. 5
SHOULD BE CORRECTED THROUGH THE CALIBRATION CURVE OF FIG. 4 CORRECTION
TERM IS ALWAYS IN THE RANGE OF 0-2"C/W;
THEREFORE, IT AFFECTS THE Rth(j.a) OF NO
MORE THAN 5% IN STILL AIR OR WITH THE
PACKAGE MOUNTED ON PC BOARD.
TRANSIENT THERMAL RESISTANCE IN
PULSED CONDITION (without external
heat sink)
The effect of single pulses of different length and
height for the Multiwatt package without any external
heat sink is shown in fig. 6.
This behaviour is discussed in Appendix B. Due to
a significant thermal capacitance (C = 2JI"C) and
correspondingly long risetime (1: = 80s), single pulses up to 30W can be delivered to the Multiwatt
package for 1s with acceptable junction temperature increase.
IN ORDER TO HAVE ACCURATE Rth (to FOR
OTHER DEVICES, WITH DIFFERENT DIE SIZE
AND DISSIPATING AREA, VALUES OF FIG. 7
MUST BE CORRECTED AS DESCRIBED IN
EXAMPLE 2 OF THE LAST SECTION.
Figure 6 : Transient Thermal Resistance for
Single Pulse.
Repetition of pulses with defined Pd, period and duty
cycle DC (ratio betwen pulse length and signal period), gives rise to oscillations in junction temperature
as described in Appendix B.
The transient thermal resistance corresponding to
the upper limit of the curve of fig. B4 (peak transient
thermal resistance) is reported in fig. 7 and depends
on pulse length and duty cycle. It can be noticed that
DC becomes less effective for longer pulses.
TRANSIENT THERMAL RESISTANCE IN
PULSED CONDITION (with external heat
sink)
Characterization has been repeated with acommercial heat sink (Thermalloy THM7023) in order to
have an example of the effect of an external thermal mass on the impedance of the thermal module.
Relationship between transient Rth and pulse length
is reported in fig. 8.
The effect of the increased thermal capacitance is
evident in fig. 9, where thermal data of fig. 6 and 8
are compared: it can be noticed that the curves are
definitely different for pulses longer than 1 s, corresponding about to the rise time of the slug. The effect of the thermal mass is to keep low the heating
rate of the silicon die thus allowing a better power
management of long power pulses. This conclusion
has general validity and can be applied to other heat
sinks than the one considered in this note.
Figure 7 : Peak Transient Rth vs. Pulse width and
Duty Cycle.
R'h
l"CJW )
I
10
P432]
I
i
I
:
M88MUL105
. I
[
I
!
f-
DC:: 0.5
10
10 <
I
0.3
i
q i
~
~ I!
I~ I-- l-
-I
I
i
[
01
!
IJ-ri
Pd~5W
FREE AIR
I I
PULSE WIDTH
DC:Dun C'iClE PUlSE REPEl. PERIOD
I
03 06 1
II
I
I
3
6 10
30
I I
100
300T(rrS;
3/8
1259
APPLICATION NOTE
Figure 8 : Transient Rth for single pulses, with
Heatsink.
Figure 9 : Comparison of Transient Rth for single
pulses, with and without Heat Sink.
M88MUlT 07
M 88~ULT 06
I
FTavg = Rth x Pd avg = Rth x Pd x DC
On the other hand, the silicon die (1: Sl = 1 + 2ms)
is able to follow frequencies of some kHz and junction temperature oscillates about the average, as
qualitatively shown in fig. B4.
The thermal resistance corresponding to the peak
of the oscillation at equilibrium (peak thermal resistance Rth peak) is now given by fig. 5, and can be ob-
APPLICATION EXAMPLES
EXAMPLE 1 - MAXIMUM Pd FOR SINGLE
PULSE OF ASSIGNED LENGTH
PROBLEM : define the maximum Pd for a single
pulse with a length of 20ms in the case of Heptawatt
package used without heat sink. Ambient temperature is 50"C ; maximum temperature is 130"C. Die
size is 15k mils2, with dissipating area of 2k mils2
(as in P432 test pattern).
SOLUTION: allowed temperature increase L'>T is
80°C. Having a RthU·a) of 60"C/W, Heptawatt package can dissipate about 1.3W in steady state From
fig. 8 the transient thermal resistance corresponding to one single pulse of 20ms in Rth (20ms)P432 =
2.2"C/W. A peak of 80/2.2 = 36.3W can be applied
to the circuit.
EXAMPLE 2 - CORRECTION FOR DIE SIZE
AND DISSIPATING AREA
PROBLEM: correct the results obtained in example
1, for assigned die size and dissipating area.
Pratical case: IC having a die size of 15k mils2 with
a dissipating area of 10k mils 2.
SOLUTION: from fig. 5, thermal resistance of P432
and of the IC under consideration are Rth P432 =
2.3°C/W and RthU-c)IC = 1's"C/W.
As the length of the pulse is 10-15 times longer than
the risetime of the silicon, the die (first cell of fig. B1)
7/8
1271
APPLICATION NOTE
can be assumed to have reached its equilibrium
condition.
Rth (20ms) found in previous example hasto be corrected in order to take into account the new value of
RthO'C)'
Rth (20ms)lc = Rth (20ms)P432- RthO·c)P432 + RthO'c)IC =
= 2.2 - 2.3 + 1SC/W = 1.4 °C/W
A single pulse of 80/1.4 '" 57W can be delivered to
such a device.
EXAMPLE 3 - CORRECTION FOR SINGLE
PULSES OF 1-3ms
PROBLEM: Correct the results of example 2, for
pulse length of 1ms.
SOLUTION: when the pulse has the same order of
magnitude of silicon rise time (T P432 is about 1ms)
another type of correction is needed. In first approximation it is considered that remains constant when
the dissipating area gets higher and the Rth for the
silicon die decreases as the reciprocal of the dissipating area. From relationship (1) :
8/8
1272
= Rth (1 mS)P432 x 2K!1 OK x Pd x [1- e-tlT] for to
1ms:
.
RthlC (1 ms) = 1.05/0SC/W '" 0.21°C/W
~T
=
A single pulse of 8010.21 '" 380W can be delivered
to such a device.
EXAMPLE 4 - Rth REPEATED PULSES
PROBLEM: find the peak power which can be dissipated by Heptawatt package without heatsink, when
power is continuously switched on 10ms and
switched off 90ms. Ambient temperature is 50°C.
maximum temperature is allowed to be 125°C.
SOLUTION: a maximum ~T = 75°C has to be considered. Fig. 9 indicated that for a pulse width of
10ms and a duty cycle of 0.1, Rthpeak is 8SCIW.
Maximum Pd is 75/8.5 = 8.8W, with an average temperature increase ~Tpeak of 60 x 0.1 x 8.8 '" 68°C.
REFERENCES
"Improved thermal evaluation, by means of a simple
integrated structure" T. Hopkins, C. Cognetti, R. Tiziani - SEMI THERM (USA, 1986).
APPLICATION NOTE
RESISTANCE TO SOLDERING HEAT
AND THERMAL CHARACTERISTICS OF PLASTIC SMDs
By C. Cognetti, E. Stroppolo and R. Tiziani
INTRODUCTION
Surface Mount Technology (SMT) has introduced a
number of new technical problems, which have delayed the conversion from insertion assembly.
This is not strange: what readily available source of
expertise existed a few years ago?
Plastic SO packages were introduced in Europe in
the early '7Os and widely used in hybrids, but hybrid
assembly has little relationship with the placement,
soldering, handling tools now considered for SM
PCB production. Was it surprising that even the
semiconductor suppliers with sound experience in
SO production could not give all of the answers
needed by the PCB manufacturer?
Japanese experience in SMT based consumer products is impressive : 87% of components used for
cameras are in SM versions. However, the degree
of complexity and performance of consumer products are somewhat different from the industrial,
automotive and telecoms applications the Western
world is interested in. On the other hand, in 1985 the
percentage of SMDs (active and passive) used in
industrial systems produced in Japan was 16.6% in
telephones, 5.5% in automotive applications, 5.1%
in cable communication, 0.7% in minicomputers 1 ;
that is, a level similar to US and European production, presumably with a similar level of expertise.
In the past few years confidence in SMT has increased. More experience exists, which is the result
of an expensive learning phase covered by both
SMD manufacturers and users.
The reliability of plastic SMDs has an important
place in this work. It needs a new approach in comparison with equivalent insertion devices, due to the
completely different use.
In 14 years of production, no distinction was made
in the authors' company between SO and DIP, from
the point of view of reliability. They had the same reliability targets and similar evaluation methodology;
the former was often hot plate soldered on leaded
ceramics for more convenient handling but no difference in long-term reliability existed.
With SMT, this is inadequate. Negative effects due
to the various assembly processes, and to some
AN26410289
thermo mechanical influence of the board, can limit
the device life.
The present work is focused on SMDs soldered onto
a plastic substrate, by means of the most common
industrial processes, and takes into account two aspects of reliability:
1. Resistance to soldering heat, i.e., the suitability
to withstand the thermal shock associated with
the soldering cycle, without reducing reliability.
This information is obtained by performing moisture resistance tests. Data about SO packages
will be presented. For PLCCs, evaluation is in
progress and will be concluded in the first half of
1988.
2. Heat dissipation, which influences the failure rate.
This information is obtained with test patterns
and test boards designed by SGS-THOMSON
Microelectronics and includes thermal impedance in pulsed conditions. A few case studies will
be included in this paper but comglete characterisations are available elsewhere. 2
RESISTANCE TO SOLDERING HEAT
In through-hole technology, devices are inserted
from the upper side of the board and wave soldered
from its lower side.
Only the lead extremities reach the temperature
(250-260°C) of the molten solder; the maximum
specified soldering time of 10s is short enough to
avoid over-heating of the package body, which
generally does not exceed 120-130°C during the
whole process.
This temperature is lower than the moulding compound glass transition temperature (160-170°C)
and the risk of permanent damage to the package
structure or to the silicon die is excluded.
Device reliability is defined almost independently of
the soldering time and temperature; devices under
reliability test are mounted on sockets, thus neglecting the effect of the assembly process.
On the contrary, in all industrial SMT processes, devices are soldered in a high temperature ambient
(215-260"C), with high heating rate, and the plastic
package is kept in glass transition conditions
1110
1273
APPLICATION NOTE
(figure 1) for a relatively long time (up to 60s). This
situation was never encountered before.
Figure 2 : SM PCB1 Test Board.
Concern over reduced reliability is justified and explains the trend towards defining SMD reliability
after the soldering cycle, in order to include the effects summarised in table 1.
j
Figure 1 : Thermal Expansion of Moulding Compounds, Compared with the Temperature of Different Soldering Techniques.
Uffi1T1frT I u,u1TrfrT
IUffi11rfrT
dPll~ dPlt~ dPlt~
-----
-----
-----
Uffi1TrfrTUffi1TIPr?Uffi1TlPr{
dPlt~
dPlt~
dPlt~
-------------
Uffi1TrfrT Uffil1rPrf Uffi1TlPr{
dPlt~ dPltl\U dPlt%
SMPCB1.
Table 2 : Soldering Processes Evaluated with
SO Packaged Devices.
Table 1 : Factors Affecting SMD Reliability on
Printed Board.
SMD Package
Design and Structure
Internal Contamination
Thermomechanical Properties
Volume and Thermal Inertia
Water Content
Lead Solderability
Contamination Level (flux)
Rinsing
Substrate
Thermomechanical Properties
Thermal Dissipation
Soldering
Number of
Cycles
1
Double Wave
120'C/30s
225'C/4s
Double Wave
120'C/30s
250'C/4s
1
Double Wave
110'C/30s
250'C/3.4s
1,2,3,4
Triple Wave
110'C/30s
Vapour Phase
Infra-red
Assembly Process
Soldering Method
Soldering Time/temperature
Pre-heating
160'C/30s
SM PCB1 test board can accept SO-8, 14, 16. It is
pre-grooved, in order to be cut in 35 positions, having the lay-out shown in figure 2 ; the SMD footprints
are electrically connected to through-holes, with a
pitch of 100 mils and placed in two parallel rows, 600
mils apart. Commercial pins inserted in the throughholes give the possibility of using the same equipment needed by DIPs.
The soldering processes from table 2 were used for
SO packaged bipolar Operational Amplifiers and CMos Standard Logic. In order to simulate a rework,
the soldering cycle was repeated on a number of
devices. Soldering is followed by the usual rinsing
in water or Freon, with or without ultrasonics.
2/10
1274
1.2.3
1,2
> 210'C/60s
1
The reliability evaluation was performed by means
of the following tests:
Operating Life
Pressure Pot
THB
EXPERIMENTAL
Reliability tests are performed on parts soldered
onto test boards (4.5 in. x 6.5 in. FR-4 substrates).
260'C/3s
215'C/20s
HAST
Thermal Cycles
Thermal Shocks
150"C
121 "C/2atm
85"C/85% RH
15V (bips)
6V (CMos)
130"C/85% RH
15V (bips)
6V (CMos)
- 55/+ 150"C
(30/5/30 min)
- 55/+ 150"C
(5/1/5 min liquid)
130"C/85%RH Highly Accelerated Steam Test
(HAST) has an acceleration factor of about 18-20
(ref. 3) in comparison with 85C/85%RH, and the
concrete possibility of reaching wear-out exists with
this test, after an acceptable time.
For PLCC packages a similar methodology is followed. At the time of writing, only partial data are
available, which will not be included here.
APPLICATION NOTE
EXPERIMENTAL RESULTS
Experimental results are summarised in tables 3-6.
Table 3 : Cumulative Reliability Data after
Multiple Wave Soldering.
Table 6 : Cumulative Reliability Data in Multiple
Wave Soldering with Repetition of the
Soldering Cycle,
Test Vehicles: LM2903 (SO·8), LM2901 and M74HCOO
(SO·14)
Test Vehicles: LM2904 (SO·8), LM2901 (SO·14) and
M74HC74 (SO-14)
Double Wave
22S'CI4s
Triple Wave
2S0'CI4s
Number of Cycles
260'CI3s
Pressure Pot
96h
S04h
Operating Life 1000h
0/lS4
0132
Pressure Pot 96h
0/104
0162
THB 8S'CI8S%RH 1000h
2000h
1/10S'
0/32
0132
HAST 130'C/85%RH 100h
200h
0/64
0/64
Thermal Shocks SOO
01231
0/77
, Parametric Failure
Table 4 : Reliability Data after Vapour Phase
Reflow.
Test Vehicle: LM2901 (SO·14)
215'C/20s
21S'CI40s
Operating Life 1000h
0132
Pressure Pot 96h
0132
THB 8S'CI85%RH
1000h
2000h
0132
0132
HAST 130'C/85%RH V ~ lSV
100h
200h
372h
4S8h
63Sh
Double Wave
250'CIS.4s
0/12
0112
1112
1111
3/10
0/S6
0lS6
0/24
2124
SI22
Thermal Cycles SOO
0132
All failures due to pad corrosion
Table 5 : Cumulative Reliability Data after
Infra-red Reflow.
Test Vehicles: M74HCOO and M74HC74 (SO·14)
> 210'C/60s
Operating Life 1300h
0134
THB 8S'C/85%RH 1300h
0134
HAST 130'C/8S%RH
100h
200h
SOOh
672h
0/32
0/32
0/32
0132
Thermal Cycles 7S0
0170
1
2
3
4
Triple Wave
260'Cl3s
1
2
3
0156
0lS6
100 Thermal Cycles
(- 40/150'C) Followed
by Pressure Pot
96h
168h
240h
0/30 0130 0160
0130 0130 0160
0130 0130 0/60
HAST 130'C18S%RH
V ~ 6V
100h
0132 0132 0132 1/32'
SOOh
0/18 0118
1000h
0118 0118
1118 1/18"
1150h
17117 17117"
1300h
• Parametric Failure .. Pad Corrosion
COMMENTS ON THE RELIABILITY RESULTS
Previous results do not reveal negative effects due
to the exposure of SM devices to the soldering heat,
for all of the industrial SMT soldering methods, in
combination with the most common solders and
cleaning solvents (Freon, water with and without
ultrasonics),
Wear-out in the HAST test (130'C/85%RH) is between 1100 and 1300 hours when the soldering
cycle is repeated up to 4 times with high temperature (250-260'C) multiple wave soldering, which is
considered to transfer the highest thermal stress to
the package body.
Pad corrosion is the final failure mechanism for all
samples.
This performance is about 7-10 times better than the
2000-3000 h THB 85'C/85%RH, which is currently
requested as qualification target in moisture resistance biased tests. Therefore, the reliability of surface mounted deVices considered in this work is high
enough to meet the most stringent requirements of
the professional market.
No evidence of cracks in the plastic case was found
in the previous evaluations. This effect (referred to
also as 'pop corn' effect) is attributed to some anom-
3/10
1275
APPLICATION NOTE
alous thermal expansion of the package in the soldering phase, caused by water absorbed by the
plastic encapsulation: a thermal treatment at a temperature higher than 100°C for a few hours is suggested in order to remove the absorbed water. 4
As this thermal pre-conditioning should be performed shortly before soldering, a serious problem
arises in the assembly line. Such thermal annealing
is not practical when the parts are supplied in plastic tapes or sticks: they should be removed from the
packs by the user, heat treated, and packed again
with additional costs and risks (co-planarity).
In this company's experience, the 'pop corn' effect
can be completely avoided by controlling the frameencapsulant interface, which is the easiest path for
the water. Furthermore, experience has indicated
that water at that interface does change the expansion characteristics of the package. About five years
ago, the curve of figure 3 was found in some parts
(coming from lots affected by the 'pop corn' problem) using Thermo-Mechanical Analysis (TMA). Devices under test were placed between the probes of
the TMA transducer and their expansion characteristics recorded.
In the first ramp (5°C/min), package expansion was
much higher than the moulding compound expansion between 50 and 10aoC ; over 1aaoc, it returned
on the curve typical of the encapsulant. Cooling
down and repeating the measurement, only the
lower curve of figure 3 was covered.
This behaviour was attributed to water having penetrated between the frame and the plastic body,
whose expansion was responsible for the package
deformation during the slow heating in TMA. When
the parts were soldered on the substrate, cracks
could occur due to the much faster heating rate.
Figure 3 : Thermal Expansion of SO Packages.
1/10
The problem was solved when the possibility of controlling the water content was found, by means of
an improved frame design and some dedicated production steps.
Millions of parts assembled in recent years showed
no evidence of the 'pop corn' effect, without any preconditioning before use.
The same solutions are successfully adopted for
PLCC packages.
THERMAL CHARACTERISTICS
Correlation between reliability and junction temperature Tj is known:
the device lifetime is roughly halved when Tj is increased by 10'C.
Mainly due to this fact, thermal dissipation is a second factor which caninfluence SMD reliability: a reduced body means worse dissipation and higher
power density on the board.
As careful thermal design is the key to improved reliability, a systematic characterisation of SM packages was performed, in order to study the main
factors affecting thermal dissipation at both levels of
package design and board design.
In the course of this work, the need for some critical
revision of the way of producing and using thermal
data was evident.
A point which cannot be under-evaluated is the
choice of measurement method, a:s will be discussed later.
Another important point is the following: the common way of specifying the junction to ambient thermal resistance Rth(j-a) is to associate one value of
Rth(j-a) to each device.
In the majority of data books, including this company's previous literature, little information is given
on the experimental conditions used to obtain that
value: the dissipated power and, above all, the kind
of interconnection between the package and the
measurement set-up (wi~es, socket or board), which
in some cases can become a far from negligible heat
transfer element.
Ignoring this contribution was probably justifie with
packages having a low thermal conductivity frame,
such as Alloy 42 or Kovar.
III
4/10
1276
For those packages, heat spreading was limited to
the silicon die and to the die pad; thermal dissipation was little affected by the surroundings and the
measurement assembly had little influence on the
final value of Rth(j-a).
APPLICATION NOTE
This is not the case concerning the same packages
with a copper frame, introduced a few years ago to
achieve a higher power capability; due to better
thermal conductivity of the leads they are much
more sensitive to external dissipating media, eventually used for the measurement.
Similar statements are valid for SMDs and become
more important on account of their reduced dimensions.
The concept is summarised in table 7, where the
thermal resistance of some dual-in-line (DIP), Small
Outline (SO) and Plastic Leaded Chip Carrier
(PLCC) packages is given. The influence of the
frame thermal conductibity is remarkable; but likewise remarkable are the differences obtained for the
same package, when it is connected by thin wires
(and 'floating' in still air) or soldered on a PC board
during the measurement.
Table 7 : Junction to Ambient Thermal
Resistance (C/W) for DIP and SM
Packages in Different Experimental
Conditions.
Power
Pd[W)
'Floating'
in Air
On SGS
Test Board
Ratio
0.5
0.6
156
125
138
90
1.13
1.39
SO·14 Leads
Alloy 42 0.25mm
Cu 0.25mm
0.4
0.6
280
190
195
105
1.43
1.80
PLCC·44 Leads ("')
Cu 0.25mm
1.0
70
52
1.35
n
die size:
A set of experimental curves was obtained for each
SM package,2 which gives the relationship between
these factors ; if used to feed back the board design, they should help to achieve a better thermal
performance.
The most significant results will be discussed
here.
Moreover, two other factors will be considered.
1. The thermal capacitance of the package, which
is significant especially in· higher pin count
PLCCs ; it delays Tj increase during power transients and is important in switching applications.
2. The frame design in association with a suitable
board design; a low resistance thermal path can
be obtained with modified frames; heat is then
conveyed to copper areas obtained on the board
and dissipated power can be increased to 2W
with SOs and PLCCs.
EXPERIMENTAL METHOD
n
DIP 14 Leads
Alloy 42 0.25mm
Cu 0.25mm
3. Specification of thermal characteristics should include more elements (power level, board density,
package design) which cannot be summarised in
one single thermal resistance value, as was commonly the case with Alloy 42 DIPs.
(') = 0.095 in. x 0.110 in.
(") = 0.060 in. x 0.090 in.
(''') = 0.180 in. x 0.180 in.
Especially for SO packages the influence of the substrate on thermal dissipation is noticeable. This fact
can help to explain the following points:
1. The Rth(j-a) values published by different SMD
suppliers are distributed in too wide a range
(more than 70'CIW for SO packages) which handicaps a correct thermal design. Most of the difference is probably due to different test boards,
and the availability of standardised measurement methodology should help to give more accurate information.
2. The board lay-out contribution shou Id be studied,
in order to quantify the effect of device density:
a suitable distance between two or more dissipating elements can be an effective solution for
improved reliability.
When thermal measurements on plastic packages
are performed, the first consideration is the lack of
a standard method: at present, only draft specifications 5 exist, proposed in 1986 and not yet standardised.
The experimental method used in this company
since 1984 has anticipated these preliminary recommendations to some extent, as it is based on the
P432 thermal test pattern (figure 4) having two npn
transistors, with 1OW each power capability. A sensing diode is placed on the thermal plateau ariSing
when the transistors are operating in parallel and
gives the actual value of Tj, through the calibration
curve of its forward voltage Vf (at constant current)
vs temperature.
Transistor size, which is not fixed by the documents
proposed for standardisation, was intentionally
limited to 1000 mils2, in order to simulate a high
power density and characterise the worst case. Die
size, which is found to have some influence on thermal resistance when copper frame is used, is slightly smaller than the die pad size and never exceeds
30000 mils2 in larger packages, such as high pin
count PLCCs.
The measurement set-up is shown in figure 5. It
is compatible with DC and AC power supply and
has an accuracy better than 5%.
5/10
1277
APPLICATION NOTE
The advantages offered by the test pattern are:
(i)
high power capability (wider evaluation range) ;
(ii)
repeatable electrical characteristics (Vf) and
temperature coefficient (1.9mV/C) of the sensing element (accuracy) ;
(iii) high resolution in pulsed conditions (evaluation
down.to 100s pulses) ;
Samples soldered op the FR-4 test board shown in
figure 2 have an approximately halved thermal resistance ; by reducing the copper pattern length of
the test board, different component densities are
simulated: thermal resistance is increased by about
30% when the track length has the minimum value.
Alloy 42 frames and copper frames were used for
narrow SO packages (150 mils body) ; only copper
frames were considered for the others : wide SO
(300 mils body) and PLCC packages.
Dependence of the thermal resistance on the total
area of the traces connected to the package is represented by the curve of figure 7. It quantifies the
effectiveness of the board lay-out to spread the heat
and dissipate it towards the ambient and can be conveniently used for determining the thermal resistance value associated with a given board design.
Suitable FR-4 test boards were developed, which
will be described case by case.
Figure 6: RthG-a) of SO-14 Package vs. Power
Level.
(iv) better correlation from one package to another.
SO
Figure 4 : Test Pattern P432 Layout.
"'-....
-.........
- ---
-
I"---
14
COPPER
floa ing i
~U"
air
ed on :
r--
'H PC 1A 5G
r----- -~
I
to
56
boo!"
SH PC 1 SG
bo~
'H PC
I--
bo~
alumi a
B.lf1
0.28
B.38
1:1.48
B.58
ILED
8.78
B.Ba
8.ge
1.BB
1.18
DISSIPATED PDLIR ( Lklll )
Figure 5 : Measurement System.
Figure 7 : Rth(j-a) of SO-14 vs. on Board Trace
Area.
SO
-
\
14
COPPER
Boo
Pd
1\
""
THERMAL CHARACTERISTICS IN DC CONDITIONS
Thermal characteristics of the SO-14 package in DC
conditions are shown in figure 6.
The upper curve is related to samples floating in still
air and connected to 8 thin wires needed for biasing
the disSipating transistors and the sensing diode of
the P432 test pattern.
6/10
1278
28
040
"......
....
~
area·
B. 2 sq. inch
r--- ---
68
80
lE1B
128
148
1lI:ACE AREA ( X 1888 sq. 11115 )
168
lBB
2BB
APPLICATION NOTE
Figure 8 : RthU-a) of SO-14 with Copper (SGSTHOMSON) and Alloy 42 Frame.
so
~
-
:-
14
---......
The electrical equivalent of heat dissipation for a
module formed by the active device, its package,
the board and the external ambient is a chain of RC
cells each having a characteristic risetime 1: = RC.
-----r--
RLLOV 0112' flW£
mgynlod on SN P BtU 5GS
Pd -
THERMAL IMPEDANCE IN PULSED CONDITIONS
oard
Thermal capacitance is the capability of heat accumulation and depends on the heat capacitance of
the materials, their volume and their density.
When the power is switched on,. the junction temperature after a time t is the result of the subsequent
charge of the RC cells, according to the well known
exponential relationship:
~Tj = Rth x Pd x (1 - etl1:)
.S U
~
leoPPEo n AI£
,
DIE AREA ( x Hlle! sq. mils )
Comparison of low conductivity (Alloy 42) and high
conductivity (copper) frames is shown in figure 8.
The data obtained forthe different SM packages are
summarised in table 8 ; the two thermal resistance
values refer to the two extreme cases of a low density and a high density board.
Table 8 : Summary of Junction to Ambient
Thermal Resistance in Steady State
Power Dissipation (SGS-THOMSON
test boards)
Die Pad Size
(milinches)
Power
Pd [W]
Rth(j-a) [OC/W]
on' Board
SO·8 Alloy 42
90 x 100
0.2
250·310
Copper
95 x 100
0.2
160·210
50·14 Alloy 42
98 x 118
0.3
200·240
Copper
78 x 118
0.5
120·160
Copper
98 x 125
0.7
105·145
50·16 Alloy 42
98 x 118
0.3
180·215
Copper
94 x 185
0.5
95·135
SO·16W Copper
120 x 160
0.7
90·112
50·20 Copper
140 x 220
0.7
77·97
PLCC·20 Cu
180 x 180
0.7
90·110
PLCC·44 Cu
260 x 260
1.5
50·60
PLCC·68 Cu
425 x 425
1.5
40·46
PLCC·84 Cu
450 x 450
2.0
36·41
When the pulse length 10 is an assigned value, effective Tj can be significantly lower than the steady
state Tj (figure 9) and a transient thermal resistance
Rth(to) can be defined, from the ratio between the
junction temperature at the end of the pulse and the
dissipated power.
Obviously, for shorter pulses, transient thermal resistance is lower and a higher power can be dissipated without exceeding the maximum junction
temperature defined in reliability considerations.
In a similar way, when pulses of the same height Pd
are repeated with a defined duty cycle DC and the
pulse is short in comparison with the total risetime
of the system, the train of pulses is seen as continuous source at a mean power level:
Pd avg = Pd x DC
Figure 9 : Qualitative Tj Increase for Single
Power Pulse.
Tmax -+--~
J_____
I < - '_
_
__
to
5-978.(,
RthU·a) values correspond to low and high board density
7/10
1279
APPLICATION NOTE
On the other hand, the silicon die has a risetime of
1·2ms and is able to follow frequencies of some
kHz: junction temperature oscillates about the aver·
age value:
~Tjavg = Rth oX Pdavg
Figure 12 : Transient Thermal Resistance for
PLCC·84 on Board.
84 LEAD PLCC
as qualitatively shown in figure 10.
The thermal resistance corresponding to the peak
of the oscillation at the equilibrium (peak thermal re·
sistance) gives information on the maximum tem·
perature reached by the device and, depending on
DC and pulse width, can be much lower than DC
thermal resistance.
Figure 10 : Qualitative Tj Increase for Repeated
Power Pulse.
/'
V
/I II
i ._)
10
1013
10013
TIr£ OR PULSe WIDTH (
Ift5
H10aa
)
The example is now given of a high pin count PLCC,
which has a large thermal capacitance, due to its
volume and weight.
Tmin~ -----'-,---'--~'"'-------="'-'---
,,
,
I
I
,
,
~
:
lamb _ _,_ _ _ _ _ _ _ _ _ _ _ __
Figure 11 : Test Board for PLCC.
Temperature increase for 84 lead PLCCs soldered
on the 8M PCB5 test board (figure 11) for single pul·
ses of different length is given in figure 12. A rise·
time of 50·60s is typical for this package, having a
thermal resistance of 38'C W in steady state (see
table 8).
For single pulses, the effective thermal resistance is
much reduced and acceptable junction temperature
is observed even for high power pulses. 10W can
be delivered for about 1s (9'CIW) and 5W for 10s
(18'CIW).
0
Peak thermal resistance for repeated pulses, with
different duty cycles, is represented in figure 13 and
the above considerations are valid in this case also.
Figure 13 : Peak Transient Rth for PLCC·84 on
The Board.
84 LEAD PLCC
I
The knowledge of thermal characteristics in the AC
condition is a valid tool to reduce redundancy (and
cost) in the thermal design of pulsed applications.
8/10
1280
'.1
~
o.
18
TItt: OR PlLSE IJIOlli ( laS )
Hi8
lBae
APPLICATION NOTE
MEDIUM POWER APPLICATION
The lack of power packages suitable for SMT requirements (standard outline, automatic handling)
is known.
Figure 15 : Test Boards for Medium Power SO-20
and PLCC-44 Package.
A simple way to achieve power dissipation in the
medium range (1-2W) is to transform the available
signal packages and modify their frame to obtain a
high conduction path.
In figure 14 the frame of medium power SO and
PLCC packages is shown : some leads are connected to the die pad, in order to have a low junction-to-pin thermal resistance Rth(j-p). Typical
values of this parameter are in the range of 1215·CIW, with a high conductivity lead frame.
Modification involves the internal part of the frame
only, while the external dimensions of the package
are not changed; the solution offers the undoubted
advantage of being compatible with existing handling and testing tools.
Figure 16 : Rth(j-a) of Medium Power PLCC-44
vs. Dissipating Area on Board.
!>I
~
~
The heat produced by the IC, and conveyed externally by the heat transfer leads, Gan be cost effectively transferred to the ambient by means of
dedicated copper heatsinks, integrated on the
board.
Figure 14: Medium Power SO and PLCC Frame.
mounl d on 5M PCB6 lJa rd
5l
DlSSI
~
~
~
*
~ ;;
'\
~
~
35 micron
"~
~
~
210·C/t = 60s (Tmax = 225·C)
A similar performance is possible with the medium
power SOs.
9/10
1281
APPLICATION NOTE
No crack in the plastic case was evidenced during
the above work or in the field, in recent years of production, and no thermal preconditioning was
needed. However, this result was obtained after optimisation of the frame design and of the production
process. Its extension to the totality of the products
existing on the market might be too arbitrary, but it
is possible to conclude that the structure of SM packages, when associated with suitable materials and
processes, is able to meet the user's requirements.
A similar evaluation is running for PLCC packages
and will be completed in the first half of 1988.
frame SO package can become better than the
equivalent Alloy 42 DIP and only 10-20% higher
than the equivalent copper DIP.
2. The thermal impedance, whose value is much
more suitable for the thermal design of switching
applications and can contribute to reduce the
cost of the system.
3. The new medium power SO and PLCC packages,
which offer the possibility of cost-effective power
dissipation in the range of 1.5-2W, still maintaining a standard outline.
HEAT DISSIPATION
REFERENCES
Some considerations have been made about the
consequence of the lack of some standard evaluation methodology. To standardise test chips and
test boards is very important, in order to reach a better knowledge and a better information exchange.
1. Nakahara, H., 'SMT Expands Options in Japan',
Electronic Packaging and Production, Vol. 26,
No.1, p. 58, January (1986).
By means of an internally developed test pattern
and suitable test boards, three points have been studied:
1. The influence of the substrate on thermal dissipation, whose effect has to be taken into account
much more than for insertion packages. With a
proper layout it is effective in reducing thermal resistance. For example, dissipation of copper
10/10
1282
2. SGS-THOMSON Application Notes 106 to 110
on SO-8, 14, 16, 16W, 20 and PLCC-20, 44 (33
+11),68,84.
3. Peck. D. S., 'Comprehensive Model for Humidity
Testing Correlation', Proceedings IRPS, p. 44
(1986).
4. Fukuzawa, 1. et ai, 'Moisture Resistance Degradation of Plastic LSI by Reflow Soldering', Proceedings IRPS, p. 192 (1.985).
5. SEMI Draft Specifications 1377 and 1449 (1986).
APPLICATION NOTE
HANDLING AND MOUNTING ICs
IN PLASTIC POWER PACKAGES
Integrated circuits mounted in plastic power packages can be damaged, or reliability compromised, by inappropriate handling and mounting techniques. Avoiding these problems is simple if you follow the suggestions
in this section.
Advances in power package design have made it
possible to replace metal packages with more economical plastic packages in many high power applications. Most of SGS-THOMSON Microelectronics
power driver circuits, for example, are mounted in
the innovative MUL TIWA TT® package, developed
originally for high power audio amplifiers. Though
the intrinsic reliability of these packages is now excellent the use of inappropriate techniques or unsuitable tools during mechanical handling can affect
the long term reliability of the device, or even damage it. With a few simple precautions, careful designers and production engineers can eliminate
these risks, saving both time and money.
straining the package and particularly the area
where the leads enter the encapsulating resin. If the
package/lead interface is strained the resistance to
humidity and thermal stress are compromised, affecting reliability.
There are five basic rules to bear in mind:
• Clamp the leads firmly between the package and
the bend/cut point (figure 1).
Bend the leads at least 3mm from the package
(figure 2a).
Never bend the leads more than 90 0 and never
bend more than once (figure 2b).
• Never bend the leads laterally (figure 2c).
BENDING AND CUTTING LEADS
The first danger area is bending and cutting the
leads. In these processes it is important to avoid
• Make sure that he bending/cutting tool does not
damage the leads.
Figure 1 : Clamp the Leads between the Package and Bend/cut Point.
w
W
Plastic
packag~1 I
Spaced?
'0039
m
~:~h~~~~~g
or culling
W
Clamp mechanism
Figure 2 : Bend the Leads at Least 3mm. from the Package, never Bend Leads more than 90 0 and never
Attempt to Splay the Leads Out.
3.0min
§I
-"':====':':::3
RIGHT
I-I] ."''
5-5)72
AN26010489
114
1283
APPLICATION NOTE
INSERTION
5-5368
When mounting the IG on a printed circuit board the
golden rule is, again, to avoid stress. In particular:
• Adhere to the specified pin spacing of the device;
don't try to bend the leads to fit non-standard hole
spacing.
TJ
("C)
260·C soldering bath
Exposed to air
:
h
150
,
100
,
,
• Leave a suitable space between the IC and the
board. If necessary use a spacer.
'.5mm:
50
Take care to avoid straining the device after soldering. If a heatsink is used and it is mounted on
the PC board it should be attached to the IC before soldering.
260.C
I
Solder
a
20
40 60
:
80 100
140
180
220
Time
(~C)
SOLDERING
HEATSINK MOUNTING
The greater danger during soldering is overheating.
If an IC is exposed to high temperature for an excessive period it may be damaged or reliability reduced.
To exploit the full capability of a power device a suitable heatsink must be used. The most important aspect from the point of view of reliability is that the
heatsink is dimen'sioned to keep the junction temperature as low as possible. From a ,mechanical
point of view, however, the heats ink mustbe designed so that it does not damage the IC. Care should
also be taken in attaching the IC to the heatsink.
The contact thermal resistance between the device
and the heatsink can be improved by adding a thin
layer of silicon grease with sufficient fluidity to ensure uniform distribution. Figure 4 shows how the
thermal resistance of a MULTIWATT package is improved by silicone grease.
'
An excessively thick layer or an excessively viscous
silicon grease may have the opposite effect and
could cause deformation of the tab.
Recommended soldering conditions are 260°C for
ten seconds or 350°C for three seconds. Figure 3
shows the excess junction temperature of a PENTAWATT package for both methods.
It is also important to use suitable fluxes for the soldering baths to avoid deterioration of the leads or
package resin. Residual flux between the leads or
in contact with the resin must be removed to guarantee long term reliability. The solvent used to
remove excess flux should be chosen with care. In
particular, trichloroethylene (CHCI : CCI2) - base
solvents should be avoided because the residue
can corrode the encapsulant resin.
Figure 3 : The Excess Junction Temperature of a
PENTAWATT Package in the suggested Soldering Conditions.
5-'51369
TJ
350·C soldering bath
I
E.xposed to air
(Oe)
Figure 4 : The Thermal Resistance of a MULTIWATT Package is improved by Silicon
Grease. Here Thermal Resistance is
plotted against Grease Thickness.
Rth r--'-_"'---r_-.-_,.-~_G::;:-~":c:.,J6
(OC/W)
150
100
50
a
10
20
30
40
50
60
Time(sec)
0.05
2/4
1284
0.10
0.15
Th(mm)
APPLICATION NOTE
SGS-THOMSON plastic power packages - MULTIWATT, PENTAWATT and VERSAWATT - are attached to theheatsink with a single screw. A spring
clip may also be used as shown in figure 5. The screw
should be properly tightened to ensure that the package makes good contact with the heatsink. It should
not be too tight or the tab may be deformed, breaking
the die or separating the resin from the tab.
The appropriate tightening torque can be found by
plotting thermal resistance against torque as shown
in figure 6.
Suggested tightening torques for 3MA screws are
8Kg/cm for VERSAWATT, PENTAWATT and
MULTIWATT packages. If different screws, or sping
clips, are used the froce exerted by the tab must be
equivalent to the force produced with these recommended torques.
Even if the screw is not overtightened the tab can
be deformed, with disastrous results. If the surface
of the heatsink is not sufficiently flat. The planarity
of the contact surface between device and heatsink
must be better than 50llm for PENTAWATT and
VERSAWATT packages and less than 40llm for
MULTIWATT packages.
Figure 5: MULTIWATT, PENTAWATT and VERSAWATT Packages are attached to
the Heatsink with a Single Screw or a
Spring Clip.
Figure 6 : Contact Thermal Resistance depends
on Tightening Torque.
c:. ~~eJ7
R'h
('OW )
~~~~~~TT
0.8
'\
0.6
0.4
i"-
" r-.....
"' r-.....
~hOU' .u;,on~ .J..
siliclne
tC'as~ ap~ied
0.2
Torqu~
(Kg/em)
Figure 7 : The Heatsink Tab may be deformed it
a Washer or a Wide-headed Screw is
not used.
hpat-sink
Similar problems may arise if the screwhead is too
narrow compared to the hole in the heatsink (figure 7).
The solution here is to use a washer to distribute the
pressure over a wider area. An alternative is to use
screws of the type shown in figure 8 which have a
wide flat head. When self-tapping screws are used
it is also important to provide an outlet for the material deformed as the thread is formed. Poor contact will result if this is not done. Another possible
hazard arises when the hole in the heatsink is
formed with a punch: a circular depression may be
formed around the hole, leading to deformation of
the tab. This may be cured by using a washer or by
modifying the punch.
3/4
1285
APPLICATION NOTE
Figure 8 : The recommended Screw Type Looks
Like this.
, ... ·oo..a
I
4/4
1286
Serious reliability problems can be encountered if
the heatsink and printed circuit board are not rigidly connected. Either the heatsink must be rigidly attached to the printed circuit board or both'must be
securely attached to the chassis. If this is not done
the stresses and strains induced by vibration will be
applied to the device and in particular to the
lead/resin interface. This problem is more likely to
arise when large boards and large heatsinks are
used or whenever the equipment is subjected to
heavy vibrations.
APPLICATION NOTE
TO 220AB - TOP 3 - TOPLESS
THERMAL RESISTANCE AND MECHANICAL ASSEMBLY
By O. DELA PATELLIERE
The behaviour of a semiconductor device is directly related to the temperature of its silicon chip.
To preserve the performances of the component
and to ensure optimal reliability, is to limit temperature by mastering the heat transfer between the chip
and the ambient atmosphere.
The purpose of this note is to underline the importance of the mechanical assembly of the component
on its heat sink by comparing different possibilities.
A - IMPORTANCE OF THE MECHANICAL
ASSEMBLY
1 - THERMAL RESISTANCE
Review: The thermal resistance (Rth) of a semiconductor assembly is the parameter which characterizes
its aptitude to channel the heat flow generated by the
junction during operation.
AT (OC/W)
It is expressed by : Rth =
P
Where P is the power dissipated by the component.
When a semiconductor component is assembled on a
heat sink, the total thermal resistance should be taken
into account. It is given by the following equation
Thermal resistance between junction and case
RthU-c) = Tj - Tc
-p-
Tj : Junction temperature
Tc : Case temperature
This value is specified in the data sheets and it
varies according to the type of component.
Thermal resistance between case and heat sink or
contact thermal resistance.
Rth(c.h) = Tc - Th
-p-
AN314/0289
Th: Heat sink temperature
Thermal resistance between heat sink and ambient air.
It is related mainly to the quality of the contact.
Rth(ha) = Th - Ta
--pTa : Ambient temperature
The thermal balance is elGpressed by the equation:
Tj - Ta = P X RthU - a)
where the thermal resistance between junction and
ambient air is :
RthU-a) = RthU-c)+ Rth(c-h) + Rth(h-a)
This equation of thermal balance helps to calculate
the junction temperature of the component.
A junction temperature which approaches the maximum temperature of the component could lead to a
decrease in the electrical characteristics and a reduction of the safety margin. A temperature exceeding the maximum junction. temperature· risks
damaging the semiconductor device. The junction
temperature should be known at all times.
2 - TYPES OF ASSEMBLY
The conventional assemblies can be divided into
two types:
_ assembly on heat sink,
_ assembly in the air (without heat sink).
The choice of the assembly results in a compromise
between the following criteria:
_ convenience of use: the component should be connectable and accessible for testing or replacement,
_ cost,
_ possibility of heat dissipation,
_ mechanical resistance,
_ aging and fiability.
1/6
1287
APPLICATION NOTE
TYPES OF ASSEMBLY AS A FWNCTION OF THE POWER (P) AND THE TYPE OF CASE USED BY
THE COMPONENT.
.
Power Range
P
~
Types of Cases
Types of Assembly
TOP 3
Heat Sink with Cooling Fins
50 W
2 W < P < 50 W
.PS,2W
I
TO 220
TO 220
I'
TOP 3
TOP 3
B - ASSEMBLY OF TOP 3 AND TO 220 ON
HEAT SINKS
I TOPLESS
Plain Heat Sink
Assembly in the Air (printed circuit
board)
Figure 1 : Attachment of the TO 220 or TOP 3
(insulated) by M3 Screw.
Among the various parameters of assembly on heat
sinks, three are particularly important:
_ the shape and condition of the heat sink surface,
_ the pressure ofthe component on the heatsink,
_ the contact grease (different types exist).
The layer spread on the flat heat sink surface should
be thin and uniform.
The Rth(c-h) of contact without grease ~ 1.5Rth (c-h) of
contact with grease.
1 - AITACHMENT BY SCREW (figure 1)
Contact
grease
Example: TO 220
Rth (c - h) ; 2°CfW for F ; 25N
Rth (0- h)
;
1.5 x 2 ; 3°C/W for F ; 5N
with F ; force
Advantages
_ good mechanical resistance
_ easy and quick disassembly
_ easy to perform for short series.
2/6
1288
Nut
D89AN314·01
APPLICATION NOTE
Figure 2 : Relative Variation of the Thermal Resistance of the Contact as a Function of the Pressure and
the Tightening Torque for an M3 Screw like Figure 1.
Multiplication factor
K =
Alh (c-h)lAlh (c-h) (25 N)
'-._-
2.5
2
\
1.5
\~
0.5
-
o
10
o
0.5
20
30
40
Pressing force F (N)
1.S
2
Tightening torque C (M /I. N)
089P.N314·02
The contact thermal resistance of assembly by
screw changes with the pressure of the case on the
heat sink. This force depends on the tightening
torque (figure 2).
Disadvantages :
_ deburring of the heat sink hole
_ mastering of the screw tightening torque
_ assembly not suitable for long series.
Figure 3 : Attachment of the TO 220 or TOP 3
(insulated) by Rivet.
Rivet
2 - ATIACHMENT BY RIVET (figure 3)
Advantages :
_ good mechanical resistance
_ quick assembly suitable for long series
Disadvantages:
_ difficult to disassemble
_ risk of deforming the plastic case during assembly
_ deburring of the attachment hole
_ difficult to master the force applied by the riet.
3 - ATIACHMENT BY CLIP
Two types of assembly by clip exist
4a and4b)
Heat sink
D89AN314·03
(figures
3/6
1289
APPLICATION NOTE
Figure 4 : Example of Attachment by Clip a. for TOP 3 (ref. mP 18055) b. for TO 220.
, ....... ,
/'
l
\
"
".~!
o
30 + 0.3
Heal sink
r
: 3
ro
...
2,3
12
3,18
(Dimensions in mm)
D89AN314-04
Advantages :
_ rapidity of assembly and disassembly (automatization),
_ low cost,
_ facility in controlling the pressure exercised by the
component on the heat sink,
_ stability in time.
Example:
Disadvantages:
_ difficulty in positioning the case with respect to the
heat sink.
N.B. : The fact of using a non-insulated component
for an application in which the case should not be at
the same potential as the heat sink makes the use
of an insulator necessary (mica).
This insulator whose thickness is about 0.1 mm introduces an additional thermal (contact) resistance of :
Clip MP 18055
F=20N
4/6
1290
- R1h (e-h)=0.8 °CIW for the TO 220 case {
Mica insulator
- Rth (e-h) '" 0.5 °CIW for the TOP 3
APPLICATION NOTE
C - ASSEMBLY IN THE AIR (WITHOUT
HEAT SINK) OF THE TO 220 - TOP 3 TOPLESS
The components in direct contact with the air (on a
printed circuit board) can only dissipate low power.
For example:
TO 220:
Tj _ T a 110 _ 50
Maximum dissipated power = - - = - - - = 1W
Rth
U-
60
a)
The evacuation of the heat produced during operation takes place at several levels :
_ the case,
_ the connections,
_ the soldering points of connections on the PC
board.
The influence of the length of connections, on one
hand, and the area of copper at the soldering point,
on the other hand, is given on figure 5 and figure 6.
Figure 5 : Relative Variation of the Thermal Resistance (junction-air) as a Function of the Length L of
Connections.
---Length L (mm)
D89AN314'()5
THERMAL RESISTANCE VALUES (junction-air)
TOPLESS
TO 220
TOP 3
75
60
50
Rth (i-a)
(OC/W)
Figure 6 : Relative Variation of the Thermal Resistance (junction-air) as a Function of the Area of Copper
at the Soldering Point.
Rth U-a)/Rth U-a) (1 em')
1.2
1.1
\.
\ r\.
""- .......
I'- ~ I-.
.9
.8
Area (cm"l
D89AN314.()6
5/6
1291
APPLICATION NOTE
CONCLUSION
the thermal requirements in the simplest manner.
The clip assembler, in most cases, meets these requirements. This assembly, because of the ease
with which it can be performed, the uniform pressure exercised on the case and the low cost, enables obtaining optimal contact thermal resistance
and mechanically reliable assembly.
When designing assembly of a plastic-case semiconductor device on a heat sink, several precautions need to be taken, particularly never to exceed
the maximum junction temperature (Tj max.).
The best assembly system is the one which satisfies
CHART FOR EVALUATION OF A FIAT HEAT SINK
100
·C/W
r:=f-l'=""::'
Copper
r-'---'~
...
-+-~
100
"-,- ,--
I
I- H t--I-
,
1\
Rth(h·a)
20
~
10
Aluminium
Ll
\
,
\
;0
l\
I
·CIW
1--
l
1\
20
~~
Thickness (e) of the
pJatcinmm
~
I
10
.,,~
"l'"
'&
~
~~
"\: ~
~ ~ t--.. ......
t\' t- t-...
"
r:::
2
0.5
2
5
10
·CIW
,
50
5
1\
20
10
- Vertical
- Semiconductor device at-the centre
. No ventilation
- x 0.7 if painted black
- square
~~
Thickness (e) ot the
plateinmm
= length of one side of the square with an area S
~
~ .......
_.
r--..
3
o
I
~
.~ ~
-
20 em
10
Conditions:
.~~ ~
-
o
- Bare convector
~
I
1292
~ 2
r---.
Steel
\
Rth (h-a)
6/6
0.5
i""""
2
20 em
1\
5
~
1
o
t
.'-
~
'"I'S:: lr"'t'--
5
1
100
Thickness (e) ot the
plateinmm
to
b
i"""- 2
f'
r--.
5
I
20 cm
Example: Copper heat sink. thickness e = 1 mm
Rth (h-a)
S"CIW I
10 cm
=
=
D89AN314·07
SALES OFFICES
EUROPE
DENMARK
ITALY
2730 HERLEV
20090 ASSAGO (MI)
Herlev Torv, 4
Tel. (45-44) 94.85.33
Telex: 35411
Telefax: (45-44) 948694
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Tel. (39-2) 89213.1 (10 linee)
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Telefax: (39-2) 8250449
FINLAND
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LOHJA SF-08150
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Telefax. (358-12) 155.66
FRANCE
94253 GENTILLY Cedex
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Tel.: (33-1) 47.40.75.75
Telex: 632570 STMHQ
Telefax: (33-1) 47.40.79.10
Via R. Fucini, 12
Tel. (39-51) 593029
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00161 ROMA
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Tel. (39-6) 8443341
Telex: 620653 SGSATE I
Telefax: (39-6) 8444474
NETHERLANDS
5652 AR EINDHOVEN
20, Place des Hailes
Tel. (33-88) 75.50.66
Telefax: (33-88) 22.29.32
Meerenakkerweg 1
Tel.: (31-40) 550015
Telex: 51186
Telefax: (31-40) 528835
GERMANY
SPAIN
67000 STRASBOURG
8011 GRASBRUNN
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Postfach 1122
Tel.: (49-89) 460060
Telefax: (49-89) 4605454
Teletex: 897107=STDISTR
1000 BERLIN 37
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Telefax: (49-30) 8015552
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Gutleutstrasse 322
Tel. (49-69) 237492-3
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Teletex: 6997689=STVBF
3000 HANNOVER 51
Rotenburger Strasse 28A
Tel. (49-511) 615960-3
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Telefax: (49-511) 6151243
8500 NORNBERG 20
Erlenstegenstrasse, 72
Tel.: (49-911) 59893-0
Telefax: (49-911) 5980701
7000 STUTIGART 31
Mittlerer Pfad 2-4
Tel. (49-711) 13968-0
Telefax: (49-711) 8661427
08021 BARCEL~NA
Calle Platon, 6 41 Floor, 5 th Door
Tel. (34-3) 4143300-4143361
Telefax: (34-3) 2021461
28027 MADRID
Calle Albacete, 5
Tel. (34-1) 4051615
Telex: 46033 TCCEE
Telefax: (34-1) 4031134
SWEDEN
S-16421 KISTA
Borgarfjordsgatan, 13 - Box 1094
Tel.: (46-8) 7939220
Telex: 12078 THSWS
Telefax: (46-8) 7504950
SWITZERLAND
1218 GRAND-SACONNEX (GENEVA)
Chemin Francois-Lehmann, 18/A
Tel. (41-22) 7986462
Telex: 415493 STM CH
Telefax: (41-22) 7984869
UNITED KINGDOM and EIRE
MARLOW, BUCKS
Planar House, Parkway
Globe Park
Tel.: (44-628) 890800
Telex: 847458
Telefax: (44-628) 890391
SALES OFFICES
AMERICAS
ASIA / PACIFIC
JAPAN
BRAZIL
AUSTRALIA
05413 sAo PAULO
R. Henrique Schaumann 286-CJ33
Tel. (55-11) 883-5455
Telex: (391 )11-37988 "UMBR BR"
Telelax: (55-11) 282-2367
NSW 2220 HURTSVILLE
Suite 3, Level 7, OtiS Hous.e
43 Bridge Street
Tel. (61-2) 5803811
Telelax: (61-2) 5806440
TOKYO 108
Nlsseki - Takanawa Bid. 4F
2-18-10 Takanawa
Minato-Ku
Tel. (81-3) 3280-4121
Telelax: (81-3) 3280-4131
CANADA
HONG KONG
NEPEAN ONTARIO
301 Moodie Dnve
Suite 307
Tel. 613/829-9944
WANCHAI
22nd Floor - Hopewell centre
183 Oueen's Road East
Tel. (852) 8615788
Telex: 60955 ESGIES HX
Telelax: (852) 8656589
U.S.A.
NORTH & SOUTH AMERICAN
MARKETING HEADOUARTERS
1000 East Bell Road
Phoenix, AZ 85022
(1-602) 867-6100
SALES COVERAGE BY SlATE
ALABAMA
Huntsville - (205) 533-5995
ARIZONA
Phoenix - (602) 867-6217
CALIFORNIA
Santa Ana - (714) 957-6018
San Jose - (408) 452-8585
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Boulder (303) 449-9000
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Schaumburg - (708) 517-1890
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Kokomo - (317) 455-3500
MASSACHUSETTS
Lincoln - (617) 259-0300
MICHIGAN
Livonia - (313) 953-1700
NEW JERSEY
Voorhees - (609) 772-6222
NEW YORK
Poughkeepsie - (914) 454-8813
NORTH CAROLINA
Raleigh - (919) 787-6555
TEXAS
Carrollton - (214) 466-8844
FOR RF AND MICROWAVE
POWER TRANSISTORS CONTACT
THE FOLLOWING REGIONAL
OFFICE IN THE U,SA
PENNSYLVANIA
Montgomeryville - (215) 361-6400
INDIA
NEW DELHI 110001
LiasonOffice
62, Upper Ground Floor
World Trade Centre
Barakhamba Lane
Tel. (91-11) 3715191
Telex: 031-66816 STMIIN
Telelax: (91-11) 3715192
MALAYSIA
PETALING JAYA, 47400
l1C, Jalan SS21/60
Damansara Utama
Tel.: (03) 717 3976
Telelax: (03) 719 9512
PULAU PINANG 10400
4th Floor - Suite 4-03
Bangunan FOP-123D Jalan Anson
Tel. (04) 379735
Telelax (04) 379816
KOREA
SEOUL 121
8th Iloor Shinwon Building
823-14, Yuksam-Dong
Kang-Nam-Gu
Tel. (82-2) 553-0399
Telex: SGSKOR K29998
Telelax: (82-2) 552-1051
SINGAPORE
SINGAPORE 2056
28 Ang Mo Kio - Industrial Park 2
Tel. (65) 4821411
Telex: RS 55201 ESGIES
Telelax: (65) 4820240
TAIWAN
TAIPEI
12th Floor
325, Section 1 Tun Hua South Road
Tel. (886-2) 755-4111
Telex: 10310 ESGIE TW
Telelax (886-2) 755-4008
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. Nn
license is granted by implication or otherwise under any patent or patent (ights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all informatinn previously supplied.
SGS-THOMSON Microelectronics products are nnt authorized for use as critical components in life support devices or systems without express
written approval of SC:;S-THOMSON Microelectronics.
© 1992 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
EMERGING TECHNOLOGY SALES, INC . .
Manufacturers Representative
373 Sinclair Frontage Road
Milpitas, CA·95035
(408) 263-9366
FAX (408) 263"9566
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