1992_TI_Linear_Circuits_Data_Book_Vol_2 1992 TI Linear Circuits Data Book Vol 2

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•
TEXAS
INSTRUMENTS

Linear Circuits
Data Conversion, DSP Analog Interface,
and Video Interface

1992

1992

Linear Products

Linear Products Quick Reference Guide
Data Book

Contents

Document No.

•

Optoelectronics and
Image Sensors

Optocouplers
CCD Image Sensors and Support
Phototransistors
IR-Emitting Diodes
Hybrid Displays

SOYD002A, 1990

•

Speech System Manuals

TSP50C4X Family
TSP50C10/11 Synthesizer
TSP53C30 Synthesizer

SPSS010, 1990
SPSS011,1990
SPSV006, 1991

•

Interface Circuits

Data Transmission and Control
Circuits, Peripheral Drivers/Power
Actuators, Display Drivers

SLYD006, 1991

•

Telecommunications
Circuits

Transmission, Switching, Subscriber,
Transient Suppressors

SCTD001 B, 1991

•

Linear and Interface
Circuits Applications

Op Amps/Comparators, Video Amps,
VRegs, Power Supply Design, Timers,
Display Drivers, Datran, Peripheral
Drivers, Data Acq., Special Functions

SLYA005,1991

•

Mass Storage ICs
Designer's Reference
Guide

Disk Drivers: Read/Write, Servo/System
Control, Interface/Linear, Digital ASIC,
LinASICTM, Applications

SSCA001, 1992

•

Macromodel Data Manual

Level I: Operational Amplifiers,
Voltage Comparators, Building Blocks
Levell!: Selected Operational Amplifiers,
Buildilng Blocks

SLOS047B, 1992

January 1992

LinASIC is a trademark of Texas Instruments Incorporated.

1IDI

~G_e_n_e_r_a_I_ln_fo__rm__at_io__n ___________________
General Purpose ADCs

lEW

...
~1IDI

~========================~
~G_e_n_e_r_a_l_p_u_rp_o_s_e__D_A_C_S________________

~V=id=e=o==a=nd==H=i9=h=-=s=p=e=ed==A=D=c=s=a=n=d==D=A=C=S====_
~D_S_P__A_n_a_lo_g__ln_t_e_rf_a_c_e_a_n_d__C_o_n_v_e_rs_io__n ____~11
Video Interface Palettes

IB

~========================~III
Analog Switches

.

~F_i_lt_er_s______________________________~
Data Manuals
Application Reports
Mechanical Data

II

Linear Circuits
Data Book
1992
Volume 2
Data Conversion, DSP Analog Interface,
and Video Interface

TEXAS
INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the rightto make changes to orto discontinue any
semiconductor product or service identified in this publication without notice. TI
advises its customers to obtain the latest version of the relevant information to .
verify, before placing orders, that the information being relied upon is current.
TI warrants performance of its semiconductor products to current specifications
in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty.
Unless mandated by government requirements, specific testing of all parameters
of each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Texas Instruments products are not intended for use in life-support appliances,
devices, or systems. Use of a TI product in such applications without the written
consent of the appropriate TI officer is prohibited.

Copyright © 1992, Texas Instruments Incorporated
Printed in the U.S.A.

INTRODUCTION
Texas Instruments offers an extensive line of industry-standard integrated circuits designed to provide highly reliable
circuits for peripheral support applications of microprocessor-based systems, DSP (digital signal processing) related
analog interfaces, video interfaces, video and high-speed converters, digitizing requirements that demand ADC and
DAC conversion, and general-purpose functions.
TI data acquisition system circuits reprsent technologies from traditional bipolar through LinCMOS'", Advanced
LinCMOS'", and LinEPIC'" processes. The LinCMOS'" and Advanced LinCMOS'" technologies feature
improvements in resolution, power consumption, and temperature stability. LinEPIC'" has both improved conversion
speed and reduced power consumption.
This data book (Volume 2 of 3) provides information on the following types of products.
• Single-Slope and Dual-Slope Analog-to-Digital Converters (ADC)
• Successive-Approximation Semi-Flash, and Flash ADC Converters
• Current Multiplying and Video DAC Converters
• High-Speed Converters for Control Applications
• Color Palette Chips for Computer Graphics
• Analog Interface Circuits for DSP Interface
• Analog Switches and Multiplexers
• Switched-Capacitor Filter ICs
• Other General-Purpose Functions
These products cover the requirments of PC and workstation multimedia applications such as audio, graphics,
communication applications, modems and cellular phones, video capture and image processing, industrial control and
disk-drive servo-loop control, automotive, electronic instrumentaion, consumer, digital audio and any DSP or
microprocessor-based system. New surface-mount packages (8-to-28 leads) include both ceramic and plastic chip
carriers, and the small-outline (D) plastic packages that optimize board density with minimum impact on
power-dissipation capability. Test equipment with handlers and automated assembly bonders strengthen the
production capabilities to provide a lower cost-to-performance ratio. TI continues to enhance quality and reliability of
integrated circuits by improving materials, processes, test methods, and test equipment. In addition, specifications
and programs are contiuously updated. Quality and performance are monitored throughout all phases of
manufacturing.
The alphanumeric listing in this data book includes all devices contained in Volumes 1,2, and 3. Products in this book
are shown in BOLD type. Thus, the reader can easily find the particular volume for a given device. Also included are
those new products added to this volume as indicated by a dagger(t). The selection guide includes a functional
description of each device by providing key parametric information and packaging options. Ordering information and
mechanical data are in the last section of the book.
Complete technical data for all TI semiconductor products are available from your nearest TI Field Sales Office, local
authorized TI distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. BOx 809066
Dallas, Texas 75380-9066
We sincerely feel that this new 1992 Linear Circuits Data Book, Volume 2, will be a significant addition to your technical
literature from Texas Instruments.

Lin CMOS, Advanced LinCMOS, and LinEPIC are trademarks of Texas Instruments Incorporated.

v

General Information

1-1

Contents
Page
Alphanumeric Index ............................................ , ........ 1-3
Selection Guide ..... " ................................................... 1-7
Cross-Reference Guide .................... , .. , ............... , .......... 1-11
Glossary, ........................................................ , .... , ... 1-17

1-2

ALPHANUMERIC INDEX

AD7524

.................

VOL 3

LP339

AD7524M ..• : .•••••..•••• 3-11
AD7528 •.••••••••••••.•. 3-19
AD7528M ..• :............ 3-31

•...•.••••••••••• 3-3

LM248 ..................
LM258 ..................
LM258A .................

VOL 1
VOL 1
VOL 1

LP2901
LT1004
LT1007

AD7628 •••• :............ 3--43
ADC0803 •.•••.•••••••••• 2-3

LM285-1.2

...............

VOL 3

LT1007A

LM285-2.5

...............

VOL 3

LT1009

LM293 ..................
LM293A .................

VOL3
VOL 3

LT10l3 .................
LT1013A

VOL 1
VaLl

LM301A

ADC0804

2-9

ADC0805
ADC0808

2-3
•.••.•••••.•..•• 2-15

ADC0808M
ADC0809

LM239A

................. .

VOL3

.................
.................

VOL3
VOL3
VOL 1

................

VOL 1

.................

VOL3

.................

VOL 1

LT1013D

................

VOL 1

••••••••••••.•• 2-21

LM306

..................

VOL 1

LT1013Y

................

VOL 1

.••....••••••••• 2-15

LM307
LM308

..................
..................

VOL 1
VOL 1

LT1037 .................
LTl037A ................

VOL 1
VOL 1

ADC0820B

2-29

ADC0820C

2-29

LM308A

.................

VOL 1

LT1054

.................

VOL3

ADC0831A
ADC0831B

2-39
2-39

LM3ll ..................
LM3l1Y .................

VOL 3
VOL3

LT1070 .................
LTl070HV .............. .

VOL3
VOL3

ADC0832A

2-39

LM3l8

..................

VOL 1

LT107l

VOL3

ADC0832B

2-39

LM324

..................

VOL 1

LT1071HV

.............. .

VOL3

ADC0834A
ADC0834B

2--47
2--47

LM324A

.................

VOL 1

LM324Y .................
LM336-2.5 ...............
LM337 ..................

VOL 1
VOL 3
VOL3

LT1072 ................ .
LT1072HV ...............

VOL3
VOL3

LT1084C
LTC1052

VOL3
VaLl

LM339 ..................
LM339A .................

VOL 3
VOL 3

MC1445
MC1458

VOL3
VaLl

LF351 ................... VOL 1
LF353 ................... VOL 1

LM339Y .................
LM348 ..................
LM358 ..................

VOL 3
VOL 1
VOL 1

LF411C .................. VOL 1
LF412C .................. VOL 1

LM358A
LM358Y

.................
.................

VOL 1
VOL 1

MC1558
MC3303
MC3403
MC3423 .................

Vall
VaLl
VOL 1
VOL 3

MC34060 ................

VOL 3

LM101A ................. VOL 1
LM107 .................. VOL 1

LM385-l.2 ...............
LM385B-l.2 ..............

VOL 3
VOL 3

LM108

LM385-2.5

MC79L05C .............•.
MC79L05AC .............
MC79L12C ...............

VOL 3
VOL 3
VOL3

MC79L12AC .............
MC79L15C .............. .
MC79L15AC ............ .

VOL3
VOL3
VOL3

MF4A-50

8-3

ADC0838A
2--47
ADC0838B •••••.••••••••• 2--47
ICL7135 •.••••••••••••••• 2-59
LF347 ................... VOL 1
LF347B .................. VOL 1

.................. VOL 1

LM108A
LM111
LMl18

................. VOL 1
VOL3
VaLl

LM124

VOL 1
VOL3
................. VOL 3

LM139
LM139A
LM148
LM158

.................. VOL 1
..........
VOL 1

LM158A ................. VOL 1
LM185-l.2 ................ VOL3
LM185-2.5 ................ VOL 3
LM193

.................. VOL3

LM201 A ................. VOL 1
LM207 .................. VOL 1

................ .

................
............... .

...............

VOL 3

LM385B-2.5 ..............
LM393 ..................

VOL 3
VOL3

LM393A
LM393Y

VOL3
VOL3

LM2900
LM2901

VaLl
VOL3

MF4A-l00 •••••••••••••••
MF10A •••••••••••••••••

8-3
8-15

LM29010 ................
LM2902 .................
LM29020 ................

VOL 3
VOL 1
VOL 1

MF10C

8-15

NE555 ..................
NE555Y .................

VOL3
VOL 3

LM2903

•••••••.••••••••

•••••••••••••••••

.................

VOL 3

NE556 ..................

VOL3

LM29030 ................
LM2904 .................

VOL 3
VOL 1

NE592 ..................
NE5532 .................

VOL3
VOL 1

LM29040

NE55321 ................
NE5532A ................

VOL 1
VOL 1

NE5532AI ...............
NE5534 .................

VOL 1
VOL 1

................

VOL 1

LM208 .................. VOL 1
LM208A ................. VOL 1

LM2907 .................
LM2917 .................
LM2930-5 ................

VOL 3
VOL 3
VOL 3

LM2ll

VOL3

LM2930-8 ................

VOL 3

NE5534A .............•..

VOL 1

LM2l8

.................. VOL 1

LM3302

.................

VOL 3

OP07C

LM3900

LM224 .................. VOL 1
LM224A ................. VOL 1
LM236-2.5 ................ VOL 3
LM237

.................. VOL3

LM239

.................. VOL3

.................

VOL 1

OP07D

VaLl
VaLl

LPlll ...................
LP2ll

VOL3
VOL3

OP27A
OP27C

VaLl
VaLl

LP239
LP3ll

VOL3
VOL3

OP27E
OP27G

VaLl
VaLl

tNew devices added to this volume.

TEXAS

.J!I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-3

ALPHANUMER~INDEX

OP37A
OP37C
OP37E
OP37G
RC4136
RC4558 .................
RC4558Y ................
RC4559 .................
RM4136 .................
RM4558 .................
RV4136
RV4558
SA555
SA556
SE555
SE555C .................
SE556 . . . . . . . . . . . . . . . . . .
SE556C . . . . . . . . . . . . . . . . .
SE592
SE5534 ..................
SE5534A
SG2524
SG3524
SN76494
SN76494A ................
SN76496 .................
SN76496A ................
TlOl0C ..................
TlOl01 ..................
TlOll . . . . . . . . . . . . . . . . . . .
Tl012 . . . . . . . . . . . . . . . . . . .
Tl014A ..................
Tl021 . . . . . . . . . . . . . . . . . . .
Tl022C . . . . . . . . . . . . . . . . . .
Tl022M
Tl026C
Tl027C
TL031 . . . . . . . . . . . . . . . . . . .
Tl031A . . . . . . . . . . . . . . . . . .
TL032 . . . . . . . . . . . . . . . . . . .
TL032A . . . . . . . . . . . . . . . . . .
Tl034 . . . . . . . . . . . . . . . . . . .
Tl034A . . . . . . . . . . . . . . . . . .
Tl040C . . . . . . . . . . . . . . . . . .
Tl041AC .................
Tl044C . . . . . . . . . . . . . . . . . .
Tl044M .................
TL051 . . . . . . . . . . . . . . . . . . .
Tl051A . . . . . . . . . . . . . . . . . .
TL052 . . . . . . . . . . . . . . . . . . .
TL052A ..................
TL054 . . . . . . . . . . . . . . . . . . .
Tl054A . . . . . . . . . . . . . . . . . .
TL061 . . . . . . . . . . . . . . . . . . .

Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Val 1
Vall
VOL1
VOl3
VOL3
VOl3
Val 3
VOl3
VOl3
VOl3
Vall
Vall
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOL 1
VaLl
VOl3
VOl3
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 3
VOL 3
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1

TL061A .................
TL061 B . . . . . . . . . . . . . . . . .
TL062 . . . . . . . . . . . . . . . . . .
TL062A . . . . . . . . . . . . . . . . .
TL062B . . . . . . . . . . . . . . . . .
TL064 . . . . . . . . . . . . . . . . . .
TL064A . . . . . . . . . . . . . . . . .
TL064B . . . . . . . . . . . . . . . . .
TL066C . . . . . . . . . . . . . . . . .
TL0661 . . . . . . . . . . . . . . . . . .
TL066M .................
TL066AC . . . . . . . . . . . . . . . .
TL070C . . . . . . . . . . . . . . . . .
TL071 . . . . . . . . . . . . . . . . . .
TL071 A . . . . . . . . . . . . . . . . .
TL071 B . . . . . . . . . . . . . . . . .
TL072 . . . . . . . . . . . . . . . . . .
TL072A . . . . . . . . . . . . . . . . .
TL072B . . . . . . . . . . . . . . . . .
TL074 . . . . . . . . . . . . . . . . . .
TL074A
TL074B . . . . . . . . . . . . . . . . .
TL080C . . . . . . . . . . . . . . . . .
TL08l
TL081A . . . . . . . . . . . . . . . . .
TL081 B . . . . . . . . . . . . . . . . .
TL082 . . . . . . . . . . . . . . . . . .
TL082A . . . . . . . . . . . . . . . . .
TL082B . . . . . . . . . . . . . . . . .
TL084 . . . . . . . . . . . . . . . . . .
TL084A . . . . . . . . . . . . . . . . .
TL084B . . . . . . . . . . . . . . . . .
TL087
TL088
Tl182
Tl185
Tl188
Tl19l ..................
TLSCSI285 . . . . . . . . . . . . . . .
TL287 . . . . . . . . . . . . . . . . . .
TL288 . . . . . . . . . . . . . . . . . .
TL430C . . . . . . . . . . . . . . . . .
TL4301 . . . . . . . . . . . . . . . . . .
TL431C . . . . . . . . . . . . . . . . .
TL431 1 . . . . . . . . . . . . . . . . . .
TL431 M . . . . . . . . . . . . . . . . .
TL431AC . . . . . . . . . . . . . . . .
TL431AI . . . . . . . . . . . . . . . . .
TL441AM . . . . . . . . . . . . . . . .
TL494 . . . . . . . . . . . . . . . . . .
TL494M . . . . . . . . . . . . . . . . .
TL496C . . . . . . . . . . . . . . . . .
TL497AC . . . . . . . . . . . . . . . .
TL497AI . . . . . . . . . . . . . . . . .

VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VaLl
VOL 1
VOL 1
VaLl
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VaLl
VaLl
7-3
7-3
7-3
7-3
VOL 3
VOL 1
VOL 1
VOL 3
VOL 3
VOL3
VOL 3
VOL 3
VOL 3
VOL3
VOL 3
VOL3
VOL 3
VOL 3
VOL 3
VOL3

TEXAS .JJI

INSlRUMENlS
1-4

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL499AC . . . . . . . . . . . . . . . .
Tl500
Tl501 ..................
Tl502 ..................
Tl503 ..................
TL50SC .................
TlS07 ..................
TL592 . . . . . . . . . . . . . . . . . .
TLS92B . . . . . . . . . . . . . . . . .
TL594C . . . . . . . . . . . . . . . . .
TL5941 . . . . . . . . . . . . . . . . . .
TL598 . . . . . . . . . . . . . . . . . .
TL598M . . . . . . . . . . . . . . . . .
Tl60l
Tl604
Tl607
Tl6l0 ..................
TL712 . . . . . . . . . . . . . . . . . .
Tl714C . . . . . . . . . . . . . . . . .
TL721 . . . . . . . . . . . . . . . . . .
TL7S0L05
TL750L08
TL750L10
Tl750L12
TL750M05
Tl750M08
TL750Ml0
TL750M12
TL751L05
TL751 L05M . . . . . . . . . . . . . .
TL751L08
TL751Ll0 . . . . . . . . . . . . . . .
TL751L12 . . . . . . . . . . . . . . .
TL751L12M . . . . . . . . . . . . . .
TL751M05
TL751M08
TL751Ml0
TL751M12
TL780-05
TL780-12 . . . . . . . . . . . . . . . .
TL780-15 . . . . . . . . . . . . . . . .
TL782C
TL7820
TL783C
Tl0808
Tl0809
TL851
TL852 . . . . . . . . . . . . . . . . . .
TL853 . . . . . . . . . . . . . . . . . .
TL1431C . . . . . . . . . . . . . . . .
TL 14310 . . . . . . . . . . . . . . . .
TL1431Y . . . . . . . . . . . . . . . .
Tl1451AC . . . . . . . . . . . . . . .
TL2217-285 ..............

VOL 3
2-77
2-77
2-77
2-77
2-91
2-99
VOL 3
VOL 3
VOL 3
VOL 3
VOL3
VOL 3
7-9
7-9
7-9
7-9
VOL 3
VOL 3
VOL 3
VOL3
VOL3
VOL3
VOL3

VOL3
VOL3
VOL3
VOL3
VOL3
VOL 3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL 3
VOL3
VOL3
VOL3
VOL3
2-71
2-71
VOL3
VOL3
VOL3
VOL3
VOL 3
VOL3
VOl3
VOL 3

ALPHANUMERIC INDEX

Tl2828Y
Tl2828Z
Tl2829Y
TL2829Z .. t ............. .
Tl5501 '"
Tl5601
..•..•.•.•....•.•
t
Tl5602
Tl7702A
Tl77028
Tl7705A
Tl77058
Tl7709A
Tl7712A
Tl7715A
Tl7757 ..................
Tl7759C .................
Tl7770-5 ................
Tl7770-12 ................
Tl7770-15 ................
Tl33071 .................
Tl33071 A ................
Tl33072 .................
Tl33072A ................
Tl33074 .................
Tl33074A ................
Tl34071 .................
Tl34071 A ................
Tl34072 .................
Tl34072A ................
Tl34074 .................
Tl34074A ................
Tl35071 .................
Tl35071 A ................
TL35072 .................
Tl35072A ................
Tl35074 .................
TL35074A ................
TLC04 •..•••••.•...••.••
TLC10
TLC14
TLC20 •••••...••••.•••.•
TlC139M ................
TlC251C ................
TlC251AC ...............
TlC2518C ...............
TlC251Y
TlC252C
TlC252Y
TlC254C
TlC254Y
TlC25l2C
TlC25l2Y
TlC25l4C
TlC25l4Y

t ............. .

Vall
Vall
VOll
Vall
4-3
4-9
4-13
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOL 3
VOl3
VOl3
VOl3
VOl3
VOL 1
VOL 1
Vall
VOL 1
Vall
VOL 1
VOL 1
VOL 1
Vall
Vall
VOL 1
VOL 1
Vall
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
8-3
3-15
8-3
3-15
VOl3
Vall
VOL 1
VOLl
VOll
Vall
VOLl
VOll
VOll
Vall
VOL 1
Vall
Vall

TlC25M2C
TlC25M2Y
TlC25M4C
TlC25M4Y
TLC271 .................
TlC271 A ................
TlC2718 ................
TlC272 .................
TLC272A ................
TlC2728 ................
TLC274 .................
TlC274A ................
TlC2748 ................
TlC277
TLC279 .................
TlC27L2 ................
TlC27L2A ...............
TlC27l28 ...............
TlC27l4 ................
TlC27l4A ...............
TlC27l48 ...............
TlC27l7 ................
TLC27L9 ................
TlC27M2 ................
TlC27M2A ...............
TlC27M28 ...............
TLC27M4 ................
TLC27M4A ...............
TLC27M48 ...............
TLC27M7
TlC27M9 ................
TLC339C ................
TlC3391 .................
TLC339M ................
TlC3390 ................
TlC352C ................
TLC3521 .................
TlC352M ................
TlC354C '. . . . . . . . . . . . . . ..
TlC3541 .................
TlC354M ................
TlC371 .................
TlC372C ................
TlC3721 .................
TLC372M
TlC3720 ................
TlC374C ................
TLC3741 .................
TlC374M
TlC3740 ................
TlC393C ................
TLC3931 .................
TLC393M ................
TlC532A .••••....•.••••.

Vall
VOll
VOll
VOLl
VOL 1
VOL 1
Vall
Vall
VOL 1
Vall
Vall
VOL 1
VOL 1
VaLl
VOL 1
Vall
Vall
Vall
VOL 1
Vall
Vall
Vall
VOL 1
Vall
VOLl
VOL 1
VOL 1
VOL 1
VOL 1
VaLl
Vall
VOL 3
VOL 3
VOL 3
VOL 3
VOL 3
VOL 3
VOl3
Val 3
VOl3
Val 3
VOL 1
VOL 3
VOL 3
VOL3
Val 3
VOL 3
VOL 3
VOl3
VOL 3
VOL 3
Val 3
Val 3
2-105

TlC533A ................
TlC540

~~~::~ :::X:::::::::::
TLC545
TlC546
TLC548
TLC549
TlC551C
TlC551Y
TlC552C
TlC555C
TlC5551
TlC555M
TlC555Y
TlC556C
TlC5561
TlC556M
TLC0820A
TLC0820B •..•••.........
TLC1078 ................

2-105
2-115
2-115
2-123
2-131
2-131
2-139
2-139
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
VOl3
2-29
2-29
VOL 1

~~~~~~: .. T ........... ~L 1

T :::::::::::

TlC1225 ::
TLC1540
TLC1541
t
TlC15501 ................
TlC15511 '"
TLC2201 ................
TLC2201A ...............
TLC22018 ...............
TLC2201Y ...............
TlC2202 ................
TlC2202Y ...............
TlC2272 ................
TlC2272A ...............
TlC2272Y ...............
TlC2652 ................
TlC2652A ...............
TlC2652Y ...............
TlC2654 ................
TlC2654A
TLC2654Y ...............
TLC3702C ...............
TlC37021 ................
TLC3702M ...............
TLC37020 ...............
TlC3704C ...............
TlC37041 ................
TLC3704M ...............
TLC37040 ............ .,
TLC4016 ••...•••••.•....
TlC4066 •..•...••.•...•.
TlC5502·5 ..

t . . . . . . . . . . ..

t . .. .. .... ...

5-15
2-147
2-147
5-29
5-29
Vall
VOL 1
VOL 1
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
Vall
VOL 1
VOL 3
VOL 3
VOL 3
VOl3
VOL 3
VOL 3
VOL 3
VOL 3
7-15
7-23
4-17

tNew devices added to this volume.

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-5

ALPHANUMERIC INDEX

TLC5503-2
TLC5503-5
TLC5602
TLC5602A

t

4-27
4-37
4-47
_._ ••• __ ••••• _. 4-47

:::C::::::::::
t

TLE2141

................

VOL 1

TLE2021 .................
TLE2021A
TLE2021 B ................
TLE2021 Y ................
TLE2022 .................
TLE2022A
TLE2022B ................
TLE2022Y ................
TLE2024 .................
TLE2024A
TLE2024B ................
TLE2024Y ................

VOL 1
VOL1
VOL 1
VOL 1
VOL 1
VaLl
VaLl
VOL 1
VOL 1
VaLl
VOL 1
VaLl

TLE2141A ............... VOL 1
TLE2141Y ............... VaLl
TLE2142 ................ VOL 1
TLE2142A ............... VOL 1
TLE2142Y
VaLl
TLE2144 ................ VOL 1
TLE2144Y ............... VOL 1
•............... VOL 1
TLE2161
TLE2161A ............... -VOL 1
TLE2161 B
VaLl
TLE2227 ................ VOL1
TLE2237 ................ VOL 1
TLE242SC ............... VOL 3
TLE242S1 ....•........... VOL 3
TLE2425M ............... VOL3
TLE242SY ............... VOL 3
TLE2426 ................ VOL 3
TLE2426Y ............... VOL 3
uA709C ................. VOL 1
uA709M ................. VOL 1
uA709AM ................ VOL 1
uA723C
VOL3
uA723M
VOL3
VOL3
uA733C
uA733M
VOL3
VOL1
uA741C
uA741 I .................. VOL 1
uA741M
VaLl
uA747C
VOL1
uA747M ................. VOL 1

TLE2027 .................
TLE2027A ................
TLE2037 .................
TLE2037A ................
TLE2061 .................
TLE2061A
TLE2061 B ................
TLE2061 Y ................
TLE2062 .................
TLE2062A ................
TLE2062B ................
TLE2062Y ................
TLE2064 .................
TLE2064A
TLE2064B ................
TLE2064Y ................
TLE2082 .................
TLE2082A
TLE2082Y ................

VOL 1
VaLl
VOL 1
VaLl
VOL 1
VaLl
VOL 1
VOL 1
VOL 1
VaLl
VOL 1
VOL 1
VOL 1
VOL 1
VOL 1
VaLl
VOL 1
VaLl
VOL 1

uA748C .................
uA2240C ................
uA780S ........•........
uA78050 ................
uA7806 ..........•......
uA7808
uA7810
uA7812 .................
uA78120 ........•.......
uA781S
uA7818
uA7824
uA788S .................
uA78L02C ...............
uA78L02AC ..............
uA78LOSC ...............
uA78LOSO ................
uA78L05AC
uA78L05AO ..............

TLC7135
TLC7524
TLC7528

2-59
3-53

3-61

TLC7628 - - •• 'f .... --. . . .. 3-75
TLC32040 _ •.••• _ •• __ • • • •• 5-37
TLC32041
TLC32042

5-37
5-37

f...........

TLC32044 - •••
TLC32044M ••••••••••••••
TLC32045 ••••f ...........
TLC32046 ••••
TLC32047 ••••
TLC32071 ••••

f...........
f...........
f...........

5-69
5-103
· 5-135
9-3
9-55
5-173

~~~~:~~: ::: :t: ::::::::::: :=~09

VOL 1
VOL 3
VOL 3
VOL 3
VOL3
VOL3
VOL3
VOL 3
VOL 3
VOL3
VOL3
VOL3
VOL 3
VOL 3
VOL3
VOL 3
VOL3
VOL3
VOL 3

tNew devices added to this volume.

TEXAS

.JJ1

INSlRUMENTS
1-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

uA78L06C
uA78L06AC
uA78L08C
uA78L08AC
uA78L09C
uA78L09AC
uA78Ll0C
uA78Ll0AC
uA78L12C
uA78L120
uA78L12AC
uA78L12AO
uA78L15C
uA78L1SAC
uA78M05C
uA78M05M
uA78M06C
uA78M08C
uA78M09C
uA78Ml0C

...............
..............
...............
..............
...............
..............
..............•
..............
...............
...............
............. .
..............
...............
..............

VOL 3
VOL 3
VOL3
VOL 3
VOL 3
VOL 3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL 3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3

uA78M12C
uA78M12M
uA78M15C
uA78M20C
uA78M24C
uA7905C
uA7906C
uA7908C
uA7912C
uA7915C
uA7918C
uA7924C
uA7952C
uA79MOSC
uA79M05M
uA79M06C
uA79M08C
uA79M12C
uA79M12M
uA79M15C
uA79M20C
uA79M24C ...........•...
UC2842 ....•............
UC2843
UC2844
UC2845
UC3842
UC3843
UC3844
UC3845

VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3
VOL3

DATA ACQUISITION AND CONVERSION
SELECTION GUIDE
single-slope and dual-slope AID converters
CONVERSION FUNCTION
Dual-Slope

ND with BCD Output

RESOLUTION

SPEED
(ms)

TYPE

PACKAGE

PAGE
NO.

41/2 DigilS

34

TLC7135
ICL7135

FN,N

2-59

41/2 Digits

Dual-Slope Analog Processors

TL500

31/2 Digits

Digital Processors With Seven-Segment Outpuls

41/2 Digits

Digital Processors With BCD Outputs

41/2 Digits

Dual-Slope Analog
Pulse-Width Modulator for Single-Slope Converter

80

TL501

DW,J
2-77

TL502
TL503

10 Bits

50

TL505

7 Bits

1

TL507

N

'2=91
P

2-99

successive-approximation and semi-flash converters
ADDRESS
AND
DATA I/O
,FORMAT

SIGNAL INPUTS
ANALOG
DEDICATED

ANALOGt
DIGITAL

RESOLU·
TION
(BITS)

CONVERSION
SPEED (IlS)t

POWER
DISSIPATION
(mWTYP)

UNADJUSTED
ERROR
(MAX)
±LSB
0.5

1§
1,0
10
100
8
0

0.5

8

Parallel

1§

1

5

6

1

0

1
1

15
30

6

10

35

6
10

TYPE

PACKAGE

2-3

ADC0803
ADC0804

PAGE
NO.

N

ADC0805

~
~

0.75

ADC0808

FN. N

2-15

0,75

ADC0808M

FK, JD

2-21

FN.N

~
~

1.25

ADC0809

0,75

TL0808

1.25

TL0809

2-·15

0,5

ADC0820B

1.0

ADC0820C

DW,FN,

1.0

TLC0820A

FK, J. N

0.5

TLC0820B

0.5

±O.5

TLC532A

2-29

FN, N

TLC533A
TLC1550

~
I----2-29

~
2-105

~

FN, N

5-29

±1

TLC1551
FN. N

5-3

OW,J,N

0

12

12

45

±2

TLCl125

0

12

12

45

1.0

TLC1225

5-15

t Analog/digital mputs can be used either as dlgltallo91c Inputs or Inputs for analog to digital conversion. For example: The TLC532/3A can have 11 analog Inputs, 5
analog inputs, and 6 digital inputs, or any combination in between.
t Includes access time
§ Differential input

TEXAS

l!}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-7

DATA ACQUISITION AND CONVERSION
SELECTION GUIDE
.
successive-approximation converters
ADDRESS
AND
DATA 110
FORMAT

SIGNAL INPUTS
ANALOG
DEDICATED

ANALOGt
DIGITAL

RESOLUTION
(BITS)

CONVERSION
SPEED (~s)t

POWER
DISSIPATION
(mWTYP)

UNADJUSTED
ERROR
(MAX)

1§

2§
84

10

4§

8

8

Serial

1.0

ADC0831A

0.5

ADC08318

1.0

ADC0832A

0.5

ADC08328

1.0

ADC0834A

0.5

ADC08348

1.0

ADC0838A

0.5
13

0

11

40

8

TLC541

10

TLC542

13

19

0.5

25
22

1

PAGE
NO.

PACKAGE

TLC545
TLC546

P

2-39
I

N
2-47
FN, N
DW, FN, N

2-115

FN, N

2-123

FN, N

2-131

D, P

2-139

FK, FN, J. N

2-147

TLC548

6

25

Tl.C549
TLC1540

31

11

ADC0838B
TLC540

6

25

TYPE

±LSB

1.0

TLC1541

t Analog/digital Inputs can be used either as digital logic inputs or inputs for analog to digital conversion. For example: The TLC532/3A can have 11 analog inputs, 5
analog inputs, and 6 digital inputs, or any combinationli~ between.
t Includes access time
§ Differential input

D/A converters (5 V to 15 V)
TTL COMPATIBLITY
AT15V

FUNCTION

RESOLUTION
(BITS)

SETTLING TIME
(ns)

TYPE

PACKAGE

PAGE
NO.

A07524A

N

3-3

Single Multiplying D/A

AD7524J

FN,N

3-3

Single MultiplYing O/A

A07524M

FK, J

3-11

TLC7524

O,FN, N

3-53

A07528B
A07528K

FN,N

3-19

No
100

8

TLC7528M

I Dual Multiplying D/A

TLC7528
Yes

I

FK, J

3-31

OW, FN, N

3-61

A07628

FN,N

3-43

TLC7628

DW, FN, N

3-75

TYPE

PACKAGE

PAGE
NO.

video interface palettes
FUNCTION
Color Palette

RESOLUTION

SPEED

Triple 8-bit

80,110,135 MHz

TLC34058

FN, PGA

Triple 8-bit with programmable pixel bus

66,85,110,135 MHz

TLC34075

FN

TEXAS

-IJ1

INSTRUMENTS
1-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-3
9-109

DATA ACQUISITION AND CONVERSION
SELECTION GUIDE
analog interface for digital signal processors
FUNCTION

TRANSFER
CHARACTERISTICS

Discrete Interfaces
AID and D/A

DYNAMIC
RANGE
(BITS)

Linear

RESOLUTION
(BITS)

8

SAMPLING
RATE

8

ON-BOARD
FILTERS

14

Linear

14

TLC08201
ADC0820

5 MHz (DIAl

TLC7524
AD7524

~

TLC7528
AD7528

~

No

16 kHz
(Programmable)

Yes
(Programmable)

TLC32040T
TLC32041t
TLC32042t

Yes

TLC32044
TLC32044M
TLC32045
TLC32046
TLC32047

Yes

TLC32071

16 kHz
Voiceband AIC

Linear

14

14

25 kHz
High-Speed AIC

Linear

8

8

PAGE
NO.

1 MHz (ND)

5 MHz
(Dual D/A)
High-Performance
Combo

TYPE

1.5 ~s ADC
100 ns DAC Settling

2-29
3-53
3-61

5-37
5-69
5'::;-03
5-135
9-3

~
5-173

t The TLC32040 and TLC32041 have two differential Inputs forthe 14-blt AID and a serial port input forthe 14-bit D/A. The NO conversion accuracy
for this device is measured in' terms of signal-to-quantization distortion and also in LSB over certain converter ranges. The package types are
FN and N. Please refer to the data sheet.

high-speed converters
CONVERSION
FUNCTION

Video AID Converter

RESOLUTION
(BITS)

Flash AID

POWER
DISSIPATION
(mW)

6
20

8
10

8

TYPE

TL5501

300

8
6

Video D/A Converter

CONVERSION
FREQUENCY
(MHz)

TLC5503-2

PACKAGE

PAGE
NO.

N

4-3

DW.N

4-27

325

TL5601

N

4-9

375

TL5602

N

4-13

125

TLC5602

DW,N

4--47

TLC5503-5

300

TLC5502·5

DW,N

4-37
4-17

analog switches and multiplexers
FUNCTION

POWER
SUPPLIES

VOLTAGE
RANGE

M

M

±15

±10

TYPICAL
IMPEDANCE
(OHMS)

TYPE

100

TL182

150

TL185

DualSPST

100

TL188

Twin Dual SPST

150

TL191

Twin SPDT

SPDT
Dual SPDT

100
±25

-17 to +25

TL604

100

TL607

SPST With Logic Inputs

80

TL610

50

TLC4016

30

TLC4066

12

2 to 12

PAGE
NO.

N

7-3

JG,P

7-9

TL601

SPST With Enable

Quad Bilateral Analog Switch

PACKAGE

D, J, N

7-15
7-23

TEXAS •

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-9

DATA ACQUISITION AND CONVERSION
SELECTION GUIDE
switched-capacitor filter res
FUNCTI9N
Dual Filter, General Purpose
Low Pass, Butterworth

FILTER ORDER
2
4

POWER SUPPLIES
(V)

TYPE
TLC1O/MF10A

±4 to ±5
±2.5 to ±6

TEXAS

TLC20/MF10C
TLC04/MF4-A-50
TLC14/MF4-A-100

-1!1

INSTRUMENTS
1-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE

PAGE
NO.

FN,N

8-15

D,P

8-3

DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE
Replacements are based on similarity of electrical and mechanical characteristics shown in currently published data.
Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the user should
compare the specifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information furnished and buyer assumes all risk in the use thereof.
No liability is assumed for damages resulting from the use of the information contained herein.
Manufacturers are arranged in alphabetical order.
ANALOG
DEVICES
AD570JN
AD7512DIJN
AD7512DIJO
AD7512DIKN
AD7512DIKO
AD7512DISD
AD7512DITD
AD7524AD
AD7524JN
AD7528BO
AD7528KN
AD7820K/B/T
AD7820L/C/U
AD7820
ADC82AG

DIRECT
TI
REPLACEMENT

SUGGESTED
TI
REPLACEMENT
ADC0803CN
TL182CN
TL1821N
TL182CN
TL1821N
TL182MJ
TL182MJ
TLC75241N
TLC7524CN
TLC75281N
TLC7528CN

AD7524AN
AD7524JN
AD7528BN
AD7528KN
TLC0820A, ADC0820CC
TLC0820B, ADC0820BC
TLC0820, ADC0820

TLC0820BIN,
ADC0820BCIN
TLC0820AIN,
ADC0820CCIN
ADC0803CN
TL500/1/3CN
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN
TL500(1/3CN
TLC7135CN
TLC7135CFN
ICL7135CN
ICL7135CFN

ADC82AM
ADC-830C
ADC-EK12DC

ADC-EK12DR

FUJITSU
MB4053P
MB40576
MB40578
MB40776
MB40778

DIRECT
TI
REPLACEMENT

SUGGESTED
TI
REPLACEMENT
TL5071N

TL5501
TLC5502
TL5601
TLC5602

PAGE
NO.
2-3
7-3
7--3
7-3
7-3
7-3
7-3
3-53
3-53
3-61
3-61
2-29
2-29
2-29
2-29
2-29
2-29
2-29
2-3
2-77
2-59
2-59
2-59
2-59
7-77
2-59
2-59
2--59
2-59
PAGE
NO.
2--99
4--3
4-17
4--9
4-47

TEXAS ~

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-11

DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE

HARRIS
CD4016AD
CD4016AE
CD4066AD
CD4066AE
CA3162E

INTERSIL
ADC0803LCD
ADC0803LCN
ADC0804LCD
ADC0804LCN
DGM182AK
DGM182BJ
DGM185AK
DGM185BJ
DGM188AK
DGM188BJ
DGM191AK
DGM191BJ
ICL7135CPI

LINEAR
TECHNOLOGY
LTC1060ACN
LTC1060CN

MAXIM
MF10BN
MF10CN

DIRECT
TI
REPLACEMENT

SUGGESTED
TI
REPLACEMENT

TLC4016MJ
TLC40161N
TLC4066MJ
TLC40661N
TL501 CN[TL503CN
DIRECT
TI
REPLACEMENT

MN5120/5130/5140

PAGE
NO.

TL604MP
TL604CP/IP
TL604MP
TL604CP/IP
TL610MP
TL610CP/IP
TL610MP
TL610CP/IP

2-3
2-3
2-9
2-9
7-3/7-9
7-3/7-9
7-3/7-9
7-3/7-9
7-3/7-9
7-3/7-9
7-3/7-9
7-3/7-9
2-59
2-59
2-59
2-59

DIRECT
TI
REPLACEMENT

PAGE
NO.

TLC10N
TLC20N

8-15
8-15
PAGE
NO.

DIRECT
TI
REPLACEMENT
TLC10N
TLC20N

8-15
8-15
SUGGESTED
TI
REPLACEMENT
TLC0820ACN[TLC0820BCN,
ADC0820BCN/ADC0820CCN
TLC0820ACN[TLC0820BCN,
ADC0820BCN/ADC0820CCN

TEXAS

-I!i

INS1RUMENTS
1-12

7-15
7-15
7-23
7-23
2-77

SUGGESTED
TI
REPLACEMENT

ADC08031N
ADC0803CN
ADC08041N
ADC0804CN
TL182MN
TL 182CN/IN
TL185MN
TL185CN/IN
TL188MN
TL188CN/IN
TL191MN
TL191CN/IN
ICL7135CN
ICL7135CFN
TLC7135CN
TLC7135CFN

MICRO
NETWORKS
MN5100/5101

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DATA ACQUISITION AND CONVERSION
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2~59

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TL5071N
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2--91
2-77
2~59

2--59
2~59

2--59
2--105
2~105
2~99

2~131
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2~115/2~115

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/

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2~9

2--9
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2~15/2~71
2~15/2~71
2~15/2~71

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DATA ACQUISITION AND CONVERSION
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NATIONAL
(Continued)
ADC0811BCN
ADC0811BCV
ADC0811BJ
ADC0811CCJ
ADC0811CCN
ADC0811CCV
ADC0811CJ
ADC0820BCD
ADC0820BCN
ADC0820BD
ADC0820CCD
ADC0820CCN
ADC0820CD
ADC0829BCN
ADC0829CCN
ADC0830BCN
ADC0830CCN
ADC0831BCJ
ADC0831BCN
ADC0831CCJ
ADC0831CCN
ADC0832BCJ
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ADC0832CCN
ADC0834BCJ
ADC0834BCN
ADC0834CCJ
ADC0834CCN
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TLC0820BCN,
ADC0820BCN
TLC0820BMJ,
ADC0820BJ
TLC0820AIN,
ADC0820CCIN
TLC0820ACN,
ADC0820CCN
TLC0820AMJ,
ADC0820CJ
TLC533AIN
TLC533AIN

ADC0831BIP
ADC0831BCP
ADC0831AIP
ADC0831ACP
ADC0832BIP
ADC0832BCP
ADC0832AIP
ADC0832ACP
ADC0834BIN
ADC0834BCN
ADC0834AIN
ADC0834ACN
ADC0838BIN
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TLC540lN
TLC540lFN
TLC540MJ
TLC540lN
TLC540lN
TLC540lFN
TLC540MJ

TLC532AIN
TLC532AIN
TLC5461N
TLC5461N
TLC5491N
TLC5491N
TLC5491N
TLC5491N

TLC15411N
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2-29
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2-39/2-139
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2-39
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2-39
2-39
2-47
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2-47
2-47
2-47
2-47
2-47
2-47
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5-15
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PRECISION
MONOLITHICS

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DATA ACQUISITION AND CONVERSION
CROSS-REFERENCE GUIDE

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TL500CN
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ICL7135CN
ICL7135CFN
TL503CN
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ICL7135CN
ICL7135CFN
ADC0808N, ADC809N

LD111ACJ

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LD121ACJ

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7-9
7-9
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2-59
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2-59
2-59
2-59
2-77
2-59
2-59
2-59
2-59
2-77
2-59
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2-59
2-59
2-15
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2-59
2-59
2-59
PAGE
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2-59
2-59
2-59
2-15
2-147
2-15
2-147
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2-59
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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS
INTRODUCTION
These terms, definitions, and letter symbols are in accordance with those currently approved by the JEDEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International
Electrotechnical Commission (lEG) for international use.

1.

GENERAL TERMS

Analog-to-Digital Converter (ADC)
A converter that uniquely represents all analog input values within a specified total input range by a limited
number of digital output codes, each of which exclusively represents a fractional part of the total analog input
range. (See Figure 1.)
NOTE: This quantization procedure introduces inherent errors of one· half LSB (least significant bit) in the
representation since, within this fractional range, only one analog value can be represented free of
error by a single digital output code.
Digital

CONVERSION CODE

Output
Code

Range of
Analog
Input
Values

4.5 5.5

a

Ideal Straight line

\:

Digital
Output
Code

.....--+-J

0 ... 101

: //

r'
~

Center

101

0 .. 100

, ....

\

f--c::-::-::::::-=t:::-::-::-:=:----1f\~e~_.- __ ------ ---- ---- -- ------ -?!::~--,
3.5 4.5

.... - - - - - - - -

{ 2.5-3.5

0 .. 100

--------,

0 ... 011 ;,

... _------- -------_ ..
1.5 2 5

a

I

.,

0 .. 011

r

\",---

I

.0

/1

.010

~

0 ... 010

I

0.5 1.5

005

a

,

____ -- ______ - - - - __ -- ~,:~'- --- ----,'
.'

I.'
.001

I'

.'1

.'1
~

0 .. 001

0 .. 000

I

/

1/

,;
/'

0.000

Analog

I

1'-"'"--f----1---t----1f----t---...

Input

a

Value

4

5

Midstep Value
of 0 ... 011

Quantization Error
-+

Yz LSB
Analog

+.-.....--4-.;--4:-+-i--1II..-....-1II..-....-1II..--- Input

Value

y, LSB

Inherent Quantization Error (± % LSBI

FIGURE 1. ELEMENTS OF TRANSFER DIAGRAM FOR AN IDEAL LINEAR ADe

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog-to-Digital Processor
An integrated circuit providin'g the analog part of an ADC; provision of external timing, counting, and
arithmetic operations is necessary for implementing a full analog-to-digital converter.
Companding DAC
A DAC whose transfer function complies with a compression or expansion law,
NOTE 1: The corresponding ADC normally consists of such a companding DAC and additional ex1ernal
circuitry,
NOTE 2: The compression or expansion law is usually a logarithmic function, e,g" A-law or fJ.-law,

Conversion Code (of an ADC or a DAC)
The set of correlations between each of the fractional parts of the total analog input range or each of the digital
input codes, respectively, and the corresponding digital output codes or analog output values, respectively,
(See Figures 1 and 2,)
NOTE: Examples of output code formats are straight binary, 2's complement, and binary-coded decimal,
Analog
Output
Value

. ' '\:::'/~

/

",

5

~

4

,_, /./"t_
r
;LJ
I.',

3

Step Height
(1 LSBI

Y

2

/ '"
/

Step Value

° ....--.---+----7-+-i--'--+---If----.
0",000

0,,001

step
CONVERSION CODE
Digital Input Code
Analog Output Value

0",000

°

--<'-)

0.,,010

0",001

0",0 1

0",100

r-----'

0",010 :0".011: 0".100

2

,

I

I

,

:

3

:

L _____ ..J

4

0",101

Digital
Input
Code

0, ,101

5

FIGURE 2, ELEMENTS OF TRANSFER DIAGRAM FOR AN IDEAL LINEAR DAC

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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Digital-to-Analog Converter (DAC)
A converter that represents a limited number of different digital input codes by a corresponding number of
discrete analog output values. (See Figure 2.)

NOTE: Examples of input code formats are straight binary, 2's complement, and binary-coded decimal.
Full Scale (of a unipolar ADC or DAC)
A term used to refer a characteristic to that step within the transfer diagram whose nominal midstep value or
nominal step value has the highest absolute value. (See Figure 3a for a linear unipolar ADC.)

NOTE 1: The subscript for the letter symbol of a characteristic at full scale is "FS".
NOTE 2:
Full

In place of a letter symbol, the abbreviation "FS" is in common use.

Sca~e,

Negative (of a bipolar ADC or DAC) (See Figures 3b and 3c)
A term used to refer a characteristic to the negative end of the transfer diagram, that is, to the step whose
nominal midstep value or nominal step value has the most-negative value.

NOTE 1: The subscript for the letter symbol of a characteristic at negative full scale is "FS-" (VFS-, IFS-).
NOTE 2:

In place of a letter symbol, the abbreviation "FS-" is in common use.

Full Scale, Positive (of a bipolar ADC or DAC) (See Figure 3b and 3c)
A term used to refer a characteristic to the positive end of the transfer diagram, that is, to the step whose
nominal midstep value or nominal step value has the most-positive value.

NOTE 1: The subscript for the letter symbol of a characteristic at positive full scale is "FS+" (VFS +, IFS+).
NOTE 2:

In place of a letter symbol, the abbreviation "FS+" is in common use.

Full-Scale Range, Nominal (of a linear ADC or DAC) (VFSRnom, IFSRnom) (See Figure 3)
The total range in analog values that can be coded with uniform accuracy by the total number of steps with this
number rounded to the nex1 higher power of 2.

NOTE: In place of the letter symbols, the abbreviation "FSR(nom)" can be used.
Example:

Using a straight binary n-bit code format, it follows:
- for an ADC: FSR(nom) = 2n x (nominal value of step width)
-- for a DAC: FSR(nom) = 2 n x (nominal value of step height)

Full-Scale Value, Nominal (VFSnom, IFSnom)
A value derived from the nominal full-scale range:
- for a unipolar converter: VFSnom = VFSRnom
- for a bipolar converter: VFSnom = 1/2 VFSRnom
(See Figure 3.)

NOTE 1:

In a few data sheets, this analog value is used as a reference value for adjustment procedures or as
a rounded value for the full-scale range(s).

NOTE 2:

In place of letter symbols, the abbreviation "FS(nom)" is in common use.

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GLOSSARY
TERMS, DEFINITIONS AND LETIER SYMBOLS
Digital
Output

Code

,

,,,
,,

t.........,f--f--+--+--+--+--.....-....
8
o
2
4
6
3

V's,"",
Analog Input
Value

""f.o>------V'SR -----0011
a. UNIPOLAR ADC
Digital
Output
Code

Digital

Output
Code

r--------------- ---------------,,
,,

---------------1
I

I

,

I

,
I

V's

+2

+3

+4

/11

- VFSnom

11

I.

I

" - - Ideal Straight Line

~ ------:..-------t-------------- -.!
1'4------- V'SR - - - - -........~

V F S R - - - - -........-i

VI

=

Analog Input Value

b. BIPOLAR ADC WITH TRUE ZERO

C.

BIPOLAR ADC WITH NO TRUE ZERO

FIGURE 3. IDEAL STRAIGHT LINE. FULL-SCALE VALUE AND ZERO-SCALE VALUE
(SHOWN FOR IDEAL LINEAR ADCs)

~

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Full-Scale Range, (Practical) (of a linear ADC or DAC) (VFSR, IFSR) (VFSRpr, IFSRprl (See Figure 3)
The total range of analog values that correspond to the ideal straight line.
NOTE 1: The qualifying adjective "practical" can usually be deleted from this term provided that, in a very few
critical cases, the term "nominal full-scale range" is not also shortened in the same way. This
permits use of the shorter letter symbols or abbreviations. (See Note 2.)
NOTE 2:

In place of the letter symbols, the abbreviations "FSR" and "FSR(pr)' are in common use.

NOTE 3:

The (practical) full-scale range has only a nominal value because it is defined by the end points of
the ideal straight line.

Example: Using a straight binary n-bit code format, it follows:
~ for an ADC: FSR = (2n - 1) x (nominal value of step width)
~ for a DAC: FSR = (2n - 1) x (nominal value of step height)
Gain Point (of an adjustable ADC or DAC)
The point in the transfer diagram corresponding to the mid step value (for an ADC) or the step value (for a
DAC) of the step for which gain error is specified (usually full scale), and in reference to which the gain
adjustment is performed. (See Figures 4 and 5.)
NOTE: Gain adjustment causes only a change of the slope of the transfer diagram, without changing the
offset error.
Ideal Straight Line (of a linear ADC or DAC)
In the transfer diagram, a straight line between the specified points for the most-positive (least-negative) and
most-negative (least-positive) nominal midstep values or nominal step values, respectively. (See Figures 1,2,
and 3.)
NOTE: The ideal straight line passes through all the points for nominal mid step values or nominal step values,
respectively.
Linear ADC
An ADC having steps ideally of equal width excluding the steps at the two ends of the total range of analog
input values.
NOTE: Ideally, the width of each end steps is one half of the width of any other step. (See Figure 1.)
Linear DAC
A DAC having steps ideally of equal height. (See Figure 2.)
LSB, Abbreviation
The abbreviation for "Least Significant Bit", that is, for the bit that has the lowest positional weight in a natural
binary numeral.
Example:

In the natural binary numeral "1010", the rightmost bit "0" is the LSB.

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Digital
Output
Code

Gain Point .........

---------------------------~

111

:,
I

.----..

110

I

i~

I,

~

~,

,

~

~

101

~

,......£

100

I~

~\Ideal

011

~

Straight Line

~

010

."

,r"
,

001

I

,
I
Analog
000 .......-'lc----/-----.'

~J

010

II ,

I.

001

,11
:-,~

3
,,;'

Extreme Value

of

th~

Error

linearity

In

,e"

,," \

;'

2

"

Extreme Value

of the linearity
Error in the

the

Diagram
1+% LSBI

Diagram
1- % LSB)

,

)1

, I I

000

oI
I"i'-

o
1

2

3

4

5

6

7

~--~~~-4--_4--_+--_+--~

oo~\ 001

Analog Input Value ILSB)

\

010

011

100

101

110

11 1

Digital Input Code
Remaining Offset
Error 1- Y. LSBI

Remaining Offset
Error {+ Y4 LSB)

a. ADC

b. DAC

FIGURE 12. BEST-STRAIGHT-LiNE LINEARITY ERROR OF A LINEAR 3-BIT NATURAL
BINARY-CODED CONVERTER (VALUES BETWEEN ± y.. LSB)

Linearity Error, Best-Straight-Line (of a linear and adjustable DAC) (EL(adj))
The difference between the actual step value and the nominal step value after offset error and gain error have
been adjusted to minimize the magnitude of the extreme values of this difference. (See Figure 12b.)
NOTE: For a uniformly curved transfer diagram, the extreme values will be very close to half of the magnitude
of the end-point linearity error. (See Figure 12b.)
Linearity Error, Differential (of a linear ADC or DAC) (ED)
The difference between the actual step width or step height and the ideal value (1 LSB). (See Figure 13.)
NOTE: A differential linearity error greater than 1 LSB can lead to missing codes in an ADC or to
nonmonotonicity of an ADC or a DAC. (See Figures 6 and 7.)
Linearity Error, End-Point (of a linear and adjustable AD C) (Ell
The difference between the actual analog value at the transition between any two adjacent steps and its ideal
value after offset error and gain error have been adjusted to zero. (See Figure 14a.)
NOTE 1: The short term "linearity error" is in common use and is sufficient if no ambiguity with the "beststraight-line linearity error" is likely to occur.
NOTE 2:

The inherent quantization error is not included in the linearity error of an ADC. The ideal value for
the transition corresponds to the nominal midstep value ± 1/2 LSB.

-1!1

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GLOSSARY
TERMS, DEFINITIONS AND lETIER SYMBOLS
Digital
Output
Code

o.. 110
o .. 101

r-I

I
I

~~yl

0 .. 100
0 ... 011

:
I

o.. 010

it-;;
,.

I

linearity
Error (+ Y, LSB)

1 LSB

~ LS~

0 .. 001

0 ... 000

I

Differential

Differential Linearity
Error (- V, LSB)

'---Y---t---+--+---(f-----.

o

2

3

4

Analog Input Value (LSB)

5

a. ADC

Analog
Output
Value
(LSB)

6

5
4

3
2

1 LSB/
I

,

'L'

\

,

I
I

---,----~I----~
\

,

/

I

I

\

Differential linearity

'-'

/

Error (+ % LSB)
Digital
Input Code

o
o
0 .. 001

o .. 011

.101
b. DAC

FIGURE 13. DIFFERENTIAL LINEARITY ERROR OF A LINEAR ADC OR DAC

~

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog
Output
Value
IlSB)

Digital
Output
Code
111

-----------------------------.......I ,
}'

~

Ideal

110

I
I

6

Act~~~nsition~1 J{
:,'

101

,
Transition

I,

\

100

~
I

1

I

: ,('
,...,......,::...J

010

I

'

I

I

4

At Transition

011/100
1- Y, lSSI

3

,

2

,

II
I

2

3

4

5

,

,*'End-Point Lin. Error

,~

/

.. -~ At Step 001
,
1+% lSS)

a

000

a

AtStep011
LSB)

7/'(+Y2

/

At Transition 00 1 10 1 a
....--'
)'
......
-.---- (- % LSS)
I "
I

.'

/

"

)'1

,

,

/1

End-Point lin. Error

I I ,,'

001

5

~

Y
'
~

,....,--:.:

011

7

6

7

~--+---~---+--~----~--4_--_+

000

00 1

Analog Input Value IlSB)

a 1a

011

100

101

110

111

Digital Input Code

a. ADC

b. DAC

FIGURE 14. END-POINT LINEARITY ERROR OF A LINEAR 3-BIT NATURAL BINARY-CODED ADC OR DAC
(OFFSET ERROR AND GAIN ERROR ARE ADJUSTED TO THE VALUE ZERO)
Linearity Error, End-point (of a linear and adjustable DAC) (Ell
The difference between the actual step value and the nominal step value after offset error and gain error have
been adjusted to zero. (See Figure 14b.)

NOTE: The short term "linearity error" is in common use and is sufficient if no ambiguity with the "best-straightline linearity error" is likely to occur,
Offset Error (of a linear ADC or DAC) (EO)

For an ADC:

The difference between the actual midstep value and the nominal midstep value at the offset
point. (See Figure 15a.)

For a DAC:

The difference between the actual step value and the nominal step value at the offset point.
(See Figure 15b.)

NOTE 1:

Usually, the specified steps forthe specification of offset error and gain error are the steps at the
ends of the practical full-scale range. For an ADC, the midstep value of these steps is defined as
the value for a point 1/2 LSB apart from the adjacent transition. (See Figures 11 and 15.)

NOTE 2: The terms "offset error" and "gain error" should be used only for errors that can be adjusted to zero.
Otherwise, the terms "zero-scale error" and "full-scale error" should be used.
Pedestal (Error) (Ep)
A dynamic offset error produced in the commutation process.

-Ij}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-35

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog
Output
Value

Digital
Output
Code

IlSB)

II'

,

Ideal .............. _ I~ __ ;,.,! __ J

~

I

}'

"
/1

r---,-'-_J

I~_-.l

"

.

,/ H'-+%
,

)'

/'/ : !
__

Actual'..
Diagram

'/
"
" ",

Diagram "": ,/

001

3

,

"

""
"
,~'

,/

r---,.:"'--- r--

011

010

,,

Actual

!

Actual

,
,,.

2

Offset,

Diagram

Point

"

,.

".

,fI'

"

,

, ""

'" "

•

',dea,
Diagram

LSB

---''-----+-e-''''--+---I-~~

Analog
Output

~---+---'-I-----+---

Value

__

Digital
Input
Code

Nominal

Offset Point

b. DAC

FIGURE 15. OFFSET ERROR OF A LINEAR 3-BIT NATURAL BINARY CODE CONVERTER
(SPECIFIED AT STEP 000)
Quantization Error, Inherent (of an ideal ADC)
Within a step, the maximum (positive or negative) possible deviation of the actual analog input value from the
nominal midstep value.
NOTE 1: This error follows necessarily from the quantization procedure. For a linear ADC, its value equals
± 1/2 LSB. (See Figure 1.)
NOTE 2: The term "resolution error" for the "inherent quantization error" is deprecated, because "resolution"
as a design parp,meter has only a nominal value.
Rollover Error (of an ADC with decimal output and auto-polarity) (ERO)
The difference in output readings with the analog input switched between positive and negative values of the
same magnitude (close to full scale).
Total Error (of a linear ADC) (ET)
The maximum difference (positive or negative) between an analog value and the nominal midstep value within
any step. (See Figure 16a.)
NOTE 1: . If this error is expressed as a relative value, the term "relative accuracy error" should be used
instead of "absolute accuracy error".
NOTE 2: This error includes contributions from offset error, gain error, linearity error, and the inherent
quantization error.

~

TEXAS
INSTRUMENTS
1-36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog
Output
Value
(LSB)

Digital
Output
Code

,

:
/' '
I

0 ... 111
0 ... 110

~,/

6

.I
I

5

,

, ,-

Q

0 .. 101

r-~II

0 ... 100

!

~'

0 ... 011

~"

~

>."
~

0 ... 001

(

2

3

4

5

6

7

o

.• 21'

~

3

2

0 ... 000 .........-+---t----+----1I---+---+---+~

a

, .,'" , ".'

./

Total Error
____ At Step O.. 001
+ Y, LSB)

,j' 1.........,'·t-'"I

,.'

4
Total Error
At Step 0 .. 101
(-1 Y. LSB)

,.'

~. " ;,,' .II

\'

!,,"

0 ... 010

."e

7

..

/

.,'

"

~/

Total Error
At Step 0 ... 011
(+1% LSB)

,I"

, ",' ",
. ,"
,,
/

0 ... 000
0 .. 001

Analog Input Value (LSB)

.. 011

0 ... 101

.111

Digital Input Code
b. DAC

a. ADC

FIGURE 16. ABSOLUTE ACCURACY ERROR, TOTAL ERROR OF A LINEAR ADC OR DAC
Total Error (of a linear DAC) (ET)
The difference (positive or negative) between the actual step value and the nominal step value for any step.
(See Figure 16b.)

NOTE 1: If this error is expressed as a relative value, the term "relative accuracy error" should be used
instead of "absolute accuracy error".
NOTE 2: This error includes contributions from offset error, gain error, and linearity error.
Zero-Scale Error (of a linear ADC or DAC) (EZS)
The difference between the actual midstep value or step value and the nominal midstep value or step value,
respectively, at specified zero scale.

NOTE: Normally, this error specification is applied to converters that have no arrangement for an ex1ernal
adjustment of offset error and gain error.

"!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-37

1-38

General Purpose ADCs

:.,"'........ ':-:-,- ..•.......... ::.-,:.:-:..:',,-

,.:":-,-,--:,_:,-,:.::",-",,,,:,-,

::--,:''''''''

.::

',""--,,

:'-"

,"-',,_:,:""

":: "'-":"- '-,:,'-

.

·'li.~.•~.2\~P~?~·j.~·~~§p·~··~.~·."'··~Q~§·.·• ~.·.P.~ rpj.\p§

2-1

2-2

ADC0803, ADC0805
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
02754, NOVEMBER 1983 ,REVISED SEPTEMBER 1986

•
•
•
•
•
•

•
•
•
•
•

8·Bit Resolution

N PACKAGE

Ratiometric Conversion

(TOP VIEW)

CS
RD
WR
ClK IN
INTR
IN+
INANlG GND
REF!2
DGTl GND

100-Jls Conversion Time
135-ns Access Time
Guaranteed Monotonicity
High Reference Ladder Impedance
... 8 kfl Typical
No Zero Adjust Requirement
On-Chip Clock Generator

VCC (OR REFI
ClK OUT
DBO (lSBI
DBl
DB2
DB3
DATA
DB4
OUTPUTS
DB5
DB6
DB7 (MSBI

Single 5-V Power Supply
Operates with Microprocessor or as
Stand-Alone
Designed to be Interchangeable with
National Semiconductor and Signetics
ADC0803 and ADC0805

description
The ADC0803 and ADC0805 are CMOS 8-bit, successive-approximation, analog-to-digital converters that
use a modified potentiometric (256R) ladder. These devices are designed to operate from common
microprocessor control buses with the three-state output latches driving the data bus. The devices can
be made to appear to the microprocessor as a memory location or an I/O port. Detailed information on
interfacing to most popular microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input
analog voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller
analog voltage spans or to make use of an external reference, ratiometric conversion is possible with the
REF/2 input open. Without an external reference, the conversion takes place over a span from VCC to
analog ground (ANLG GND). The devices can operate with an external clock signal or, with an additional
resistor and capacitor, using an on-chip clock generator.
The ADC08031 and ADC08051 are characterized for operation from - 40°C to 85 °C. The ADC0803C
and ADC0805C are characterized for operation from ooC to 70°C.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 1983, Texas Instruments Incorporated

".!}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-3

ADC0803, ADC0805
8·BIT ANALOG·TO·DlGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
functional block diagram (positive logic)

RD

12)

.--L.J

11)

WR

"START"
FLiP-FlOP~

~
-....-I

13)

S

ClKAP-R
ClK 119)
OUT
ClKIN

LT

ClK

REF/2

ClK

Cl

~:'"'

14)

DGTl 110)
GND

VCC

lD

ClK
GEN

ClK
ClK B

OSC

-

cll B

f-+I>f-+

120)

lADDER
AND
DECODER

(9)

SAR
lATCH

~

I-+-

f-+

~

S-BIT
SHIFT
REGISTER

~

,-

lE
ANlG IS)
GND

DAC

IN+ ~
IN

~P

1

.~

ClK A

R

....-lD

Cl

'---

IlYl

~~

lE

EN

3-STATE
OUTPUT
lATCH
..

~DBQIlSB)
~DBI
~DB2
~DB3

~DB4
~DB5

~DB6
~DB7

IMSB)

"'I1

2-4

R

R~

~

1 --

17)

~Il-

"INTERRUPT"

t--

Vcc

~~

D

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

S
~

~

INTR

ADC0803. ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
............... 6.5 V
Supply voltage, Vcc (see Note 1)
- 0.3 V to 18 V
Input voltage range: CS, RD, WR
Other inputs . . . . . . . . . . . . .
-0.3 V to VCC +0.3 V
Output voltage range . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC +0.3 V
Operating free-air temperature range: ADC080_1 . . . . . . . . . . . . . . . . . . . . .
-40°C to 85°C
ADC080_C . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together unless

otherwise noted.

recommended operating conditions
Supply voltage. V CC
Analog input voltage (see Note 2)

MIN

NOM

MAX

4.5

5

6.3

-0.05
0.25

Voltage at REF/2 (see Note 3), VREF/2
High-level input voltage at CS, RD, or WR, VIH

VCC +0.05

Low-level input voltage at CS, RD, or WR, VIL

Analog ground voltage (see Note 4)
Clock input frequency (see Note 5), fclock
Duty cycle for fclock above 640 kHz (see Note 5)

100

640

1460

Pulse duration, WR input low, tw(WR)

100

NOTES:

I
I

ADCOSO_ .. I
ADC080_C

V

1

275

Operating free-air temperature, T A

V

O.S
0

40%

V

15

-0.05

Pulse duration, clock input (high or low) for fclock be.low 640 kHz, tw(CLKI

V
V

2.5

2

UNIT

V
kHz

60%
781

ns
ns

-40

85

0

70

°c

2. When the differential input voltage (VI + - VI_) is less than or equal to 0 V, the output code is 0000 0000.
3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when
REF/2 is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs.
Thus, the differential input voltage range when REF/2 is open and VCC ~ 5 V is 0 V to 5 V. VREF/2 for an input voltage
range from 0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V.
4. These values are with respect to DGTL GND.
5. Total unadjusted error is specified only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns
to 937 ns). For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should
be observed for an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK)
remains within limits.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-5

ADC080J. ADC0805
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
electrical characteristics over recommended operating free-air temperature range,
fclock = 640 kHz, VREF/2 = 2.5 V (unless otherwise noted)
PARAMETER

Vol-i

Val

TEST CONDITIONS

High-level

All outputs

Vee

~

4.75 V,

IOH

output voltage

DB and INTR

~

4.75 V,

~

MIN

-360

~A

low-level

Data outputs

Vee
Vee

~

4.75 V,

IOH ~ -10 ~A
1 .6 mA
IOl

output

INTR output

Vee

~

4.75 V,

IOl

voltage

elK OUT

Vee

~

4.75 V,

IOl

1 mA

~

360

0.4

VT + - VT _ Clock input hysteresis
III

Low-level input Current

IOZ

Off-state output current
Short-current

IOHS

output current
Short-circuit

IOlS

output current

3.5

V

1.5

1 .S

2.1

V

0.6

1.3

2

V

0.005

1

~A

5 V

Output high

Va

~

0,

TA

Output low

Va

=

5 V,

VREF/2 ~ open,
es ~ 5 V

reference current

3

~A

~A

~

25°C

-4.5

-6

mA

T/I

=

25°C

9

16

mA

TA

~

25°C,

See Note 6

reference ladder

-1
-3

=

Input resistance to

RREF/2

3.1

-0.005

Supply current plus
ICC

2.7

Va - 0
Va

V

0.4

threshold voltage
High-level input current

V

~A

threshold voltage

IIH

UNIT

0.4

Clock negative-going

VT-

MAX

4.5

~

~

5 V,

2.4

Clock positive-going

VT+

Typt

Vee

1.1
2,5

1.8

mA
k(l

8

ei

Input capacitance (control)

5

7.5

pF

Co

Output capacitance lOBI

5

7.5

pF

NOTE 6: Resistance is calculated from the current drawn from a 5-V supply applied to pins 8 and 9.

operating characteristics over recommended operating free-air temperature,
VREF/2 = 2.5 V, fclock = 640 kHz (unless otherwise noted)
PARAMETER

TEST CONDITIONS

Supply-voltage-variation error
Total adjusted error

ADCOS03

Total unadjusted error

ADCOS05

MIN

Vee ~ 4.5 V to 5.5 V,

See Note 7

With full-scale adjust,

See Notes 7 and S

VREF/2

=

2.5 V,

VREFI2 open,
TA

tdis

Output disable time

TA - 25°C, Cl .. 10 pF, Rl -

td(INTRI

Delay time to reset INTR

TA

tconv

Conversion cycle time

CR

Free-running conversion rate

t All typical
NOTES: 7.
S.
9.

TA

~

Cl

~

lSB
lSS
lSB

± 1/16

± 1/8

135

200

ns

10 k!l

125

200

ns

300

450

See Note 9
CS at 0 V

66

73
8770

ns
clock
cycles
conv/s

values are at T A ~ 25°C.
These parameters are specified over the recommended analog input voltage range.
All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristic.
Although internal conversion is completed in 64 clock periods, a es or WR low-to-high transition is followed by 1 to B clock
periods before conversion starts, After conversion is complete, part of another clock period is required before a high-to-Iow
transition of INTR completes the cycle.

TEXAS

~

INSTRUMENTS
2-6

± 112

100 pF

100 kHz to 1.46 MHz,

25°C,

lS8

± 114

25°C

INTR connected to WR,

UNIT

±1

See Notes 7 and S

fclock -

MAX

± liS

± 112

DC common-mode error

~

Typt

± 1/16

See Notes 7 and S

Output enable time

25°C,

5 V,

See Notes 7 and S

ten

~

Vee

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0803, ADC0805
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
PARAMETER MEASUREMENT INFORMATION

cs

\~---- ....... ---;-----'/
_ - - - - 8 CLOCK PERIODS
1-11

(MIN)-----1.~1

1

1

AD

INTR

~~50_%

1

I
I
I

____________

t.I(lNTR)~
I
1
I
50%

+1----------------

__

I

1

~ __________~IJ

ten~

~~;:UTS

.•..••.

~~,
1

~ I4-tdis

\4-

----------

~

1

~)
I

I

I

CLOCK PERIODS

• 4

CLOCK PERIODS

~,O%

I

1414-------- tC O N V - - - - - - - - - - i L
WRITE OPERATION TIMING DIAGRAM

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-7

ADC0803. ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
PRINCIPLES OF OPERATION
The ADC0803 and ADC0805 each contain a circuit equivalent to a 256-resistor network. Analog switches
are sequenced by successive-approximation logic to match an analog differential input voltage
(Vin + - Vin -) to a corresponding tap on the 256R network. The most significant bit (MSB) is tested
first. After eight comparisons (64 clock periods). an eight-bit binary code (1111 1111 = full scale) is
transferred to an output latch and the interrupt (lNTR) output goes low. The device can .be operated in
a free-running mode by connecting the INTR output to the write (WR) input and holding the conversion
start (CS) input at a low level. To ensure start-up under all conditions. a low-level WR input is required
during the power-up cycle. Taking CS low any time after that will interrupt a conversion in process.
When the WR input goes low. the internal successive approximation register (SAR) and 8-bit shift register
are reset. As long as both CS and WR remain low. the analog-to-digital converter remains in a reset
state. One to eight clock periods after CS or WR makes a low-to-high transition. conversion starts.
When the CS and WR inputs are low. the start flip-flop is set and the interrupt flip-flop and 8-bit register
are reset. The next clock pulse transfers a logic high to the output of the start flip-flop. The logic high
is ANDed with the next clock pulse. placing a logic high on the reset input of the start flip-flop. If either
CS or WR have gone high. the set signal to the start flip-flop is removed. causing it to be reset. A logic
high is placed on the D input of the eight-bit shift register and the conversion process is started. If the
CS and WR inputs are still low. the start flip-flop. the 8-bit shift register. and the SAR remain reset.
This action allows for wide CS and WR inputs. with conversion starting from one to eight clock periods
after one of the inputs goes high.
When the logic high input has been clocked through the 8-bit shift register. which completes the SAR
search. it is applied to an AND gate controlling the output latches and to the D input of a flip-flop. On
the next clock pulse. the digital word is transferred to the 3-state output latches and the interrupt flip-flop
is set. The output of the interrupt flip-flop is inverted to provide an INTR output that is high during conversion
and low when the conversion is complete.
When a low is at both the CS and RD inputs. an output is applied to the DBO through DB7 outputs and
the interrupt flip-flop is reset. When either the CS or RD inputs return to a high state. the DBO through
DB7 outputs are disabled (returned to the high-impedance state). The interrupt flip-flop remains reset.

~

TEXAS
INSTRUMENTS
2-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC08041, ADC0804C
8-BIT ANALOG-TO-DIGITAL CONVERTER
WITH DIFFERENTIAL INPUTS
02755, OCTOBER 1983 - REVISED OCTOBER 1988

•
•
•

•
•
•
•
•
•

N DUAL-iN-LINE PACKAGE
(TOP ViEW)

a-Bit Resolution
Ratiometric Conversion

es
RD
WR
elK iN
INTR
IN+
INANlG GND
REF/2
DGTL GND

100-l's Conversion Time
135-ns Access Time
No Zero Adjust Requirement
On-Chip Clock Generator
Single 5-V Power Supply
Operates with Microprocessor or as
Stand-Alone

Vee (OR REF)
eLK OUT
DBO (lSB)
DB1
DB2
DB3
DATA
DB4
OUTPUTS
DB5
DB6
DB7 (MSB)

Designed to be Interchangeable with
National Semiconductor and Signetics
ADC0804

description
The ADC0804 is a CMOS 8-bit successive-approximation analog-to-digital converter that uses a modified
potentiometric (256R) ladder. The ADC0804 is designed to operate from common microprocessor control
buses, with the three-state output latches driving the data bus, The ADC0804 can be made to appear
to the microprocessor as a memory location or an 1/0 port. Detailed information on interfacing to most
popular microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input
analog voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller
analog voltage spans or to make use of an external reference, ratiometric conversion is possible with the
REF/2 input open. Without an external reference, the conversion takes place over a span from VCC to
analog ground (ANLG GND). The ADC0804 can operate with an external clock signal or, with an additional
resistor and capacitor, can operate using an on-chip clock generator.
The ADC08041 is characterized for operation from - 40°C to 85 DC. The ADC0804C is characterized for
operation from O°C to 70°C.

PRODUCTiON DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas-Instruments

:~~~~:~~i~at::1~1~ ~!:ti~~ti:; :IIO::~:~:t:;s~S not

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright

©

1983, Texas Instruments Incorporated

2-9

ADC08041. ADC0804C
8·BIT ANALOG·TO·DlGITAL CONVERTER
WITH DIFFERENTIAL INPUTS
functional block diagram (positive logic)

10

elK

Cl

eLK B

LADDER

---4-------l

REF/2 ,,'9.0..
'

AND
DECODER

I-+-----o%
10%

1

-------

--+l

IoII-td;s

READ OPERATION TIMING DIAGRAM

Cs\~_ _ _-J/
WR

---J/o%

\~o%
td(lNTR)~

I

14---

i

~tw(WR)--+I

INTERNAL
STATUS OF THE
CONVERTER

J

I

1

I

1

1

1

1

I

I

I

1 TOB
64Y,
~
CLOCK PERIODS--l·"'''---CLOCK PERIODS
"I

I

1

I

1
!+--INTERNAL tconv

~
I
1

I

.Jf

o%

.

50%1

50%

---------il,.--------.----------....J

INTR _ _ _ _ _ _

1

1

i '{.1 5500 %%

--~"-

1

1414---------'conv-------2...,

:

I

1

I

y, CLOCK PERIOD ~

I+--

WRITE OPERATION TIMING DIAGRAM

TEXAS

"'!1

INSTRUMENTS
POST OFF!CE BOX 655303 • DALLAS, TEXAS 75265

2-13

ADCOB041, ADCOB04C
B·BIT ANALOG·TO·DlGITAL CONVERTER
WITH DIFFERENTIAL INPUTS
PRINCIPLES OF OPERATION
The ADCOB04 contains a circuit equivalent to a 256-resistor network. Analog switches are sequenced
by successive approximation logic to match an analog differential input voltage (Vin + - Vin _) to a
corresponding tap on the 256-resistor network. The most-significant bit (MSB) is tested first. After eight
comparisons (64 clock periods). an B-bit binary code (1111 1111 = full scale) is transferred to an output
latch and the interrupt (INTR) output goes low. The device can be operated in a free-running mode
by connecting the INTR output to the write (WR) input and holding the conversion start (CS) input at a
low level. To ensure start-up under all conditions, a low-level WR input is required during the power-up
cycle. Taking CS low anytime after that will interrupt a conversion in process.
When the WR input goes low, the ADCOB04 successive approximation register (SAR) and B-bit shift
register are reset. As long as both CS and WR remain low, the ADCOB04 remains in a reset state. One
to eight clock periods after CS or WR makes a low-to-high transition, conversion starts.
When the CS and WR inputs are low, the start flip-flop is set and the interrupt flip-flop and B-bit register
are reset. The next clock pulse transfers a logic high to the output of the start flip-flop. The logic high
is ANDed with the next clock pulse, placing a logic high on the reset input of the start flip-flop. If either
CS or WR have gone high, the set signal to the start flip-flop is removed, causing it to be reset. A logic
high is placed on the D input of the B-bit shift register and the conversion process is started. If the CS
and WR inputs are still low, the start flip-flop, the B-bit shift register, and the SAR remain reset.
This action allows for wide CS and WR inputs with conversion starting from one to eight clock periods
after one of the inputs goes high.
When the logic high input has been clocked through the B-bit shift register, completing the SAR search,
it is applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next
clock pulse, the digital word is transferred to the three-state output latches and the interrupt flip-flop is
set. The output of the interrupt flip-flop is inverted to provide an INTR output that is high during conversion
and low when the conversion is completed.
When a low is at both the CS and RD inputs, an output is applied to the DBO through DB7 outputs and
the interrupt flip-flop is reset. When either the CS or RD inputs return to a high state, the DBO through
DB7 outputs are disabled (returned to the high-impedance state). The interrupt flip-flop remains reset.

TEXAS
2-14

"'!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0808, ADC0809
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH 8·CHANNEL MULTIPLEXERS
02642, JUNE 1981-REVISED MAY 1988

•

N

Total Unadjusted Error ... ± 0.75 LSB Max
for ADC0808 and ± 1.25 LSB Max for
ADC0809

•

Resolution of 8 Bits

•
•
•
•
•
•
•
•
•
•

100 /ls Conversion Time

DUAL-IN-LiNE PACKAGE
(TOP VIEW)

,,~,{

r}INPUTS

~}ADDRESS

Ratiometric Conversion
Monotonicity Over the Entire AID
Conversion Range

ALE
2 -1 (MSSI
2-2
2- 3
2- 4
2 - 8 (lSSI
REF2- 6

EOC
2- 5
OE
ClK
VCC
REF+
GND
2- 7

No Missing Codes
Easy Interface with Microprocessors
Latched 3·State Outputs
Latched Address Inputs
Single 5-V Supply

FN PACKAGE
(TOP VIEW)

Low Power Consumption

(OLOVMN..-O

Designed to be Interchangeable with
National Semiconductor ADC0808.
ADC0809

1-1-1-1-1-1-1:::J::J::J::J::J::J::J

a.. a.. a.. a.. a... a... a..
~~~~~~~

4

description

3

2 1 28 27 26

5

25

6

24
23

The ADC0808 and ADC0809 are monolithic
8
22
CMOS devices with an 8-channel multiplexer, an
OE 9
21
8-bit analog-to-digital (AID) converter, and
20
ClK 10
microprocessor-compatible control logic. The
19
VCC 11
121314151617 18
8-channel multiplexer can be controlled by a
microprocessor through a 3-bit address decoder
+ 0'" c.o I iii o::t
u... Z I I u.. (/) i
with address load to select anyone of eight
~(9NN~~N
single-ended analog switches connected directly
co
I
to the comparator. The 8-bit AID converter uses
N
the successive-approximation conversion
technique featuring a high-impedance threshold detector, a switched-capacitor array, a sample-and-hold,
and a successive-approximation register (SAR). Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity.
and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR
and latched inputs to the multiplexer address decoder. The single 5-V supply and low power requirements
make the ADC0808 and ADC0809 especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808 and ADC0809 are characterized for operation from - 40°C to 85 °C.

PRODUCTION DATA documents contain information
currant a8 of publication data. Products conform to

specifications pef tho tarms of Texas Instruments

standard warranty. Production processing do.s not
nacassarily includa tasting of all parameters.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1983, Texas Instruments Incorporated

2-15

ADcoaoa, ADCOa09
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH a·CHANNEL MULTIPLEXERS
functional block diagram (positive logic)
SAMPLE·AND·HOLD
BINARY·WEIGHTED
CAPACITORS

.-

(12)

REF+
(16)
REF-

o.~
(27)

-

THRESHOLD
DETECTOR

4>

~
ANALOG
INPUTS

3

J!!.

5

-

ANALOG
MULTIPLEXER

~

r-

SWITCH
MATRIX

(3)

OUTPUT
LATCHES

EN

.~

CLOCK
START CONVERSION (START)
OUTPUT ENABLE fOE)

(10)
(6)
(9)

(25)

ADDRESS A
ADDRESS B
ADDRESS C
ADDRESS LOAD ~
ENABLE (ALE)

i24l

~

ADDRESS
DECODER

>
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS

H
1

SELECTED

ADDRESS

ANALOG

A

STROBE

CHANNEL

0
1
2

C

B

L

L

L

t

L

L

H

L

H

L

L

H

H

H

L

L

H

L

H

H

H

L

H

H

H

t
t
t
t
t
t
t

~
~

3
4

5
6
7

high level, L ~ low level
low-to-high transition

TEXAS . "
INSTRUMENTS
2-16

~ 2-5
~ 2-4
~r 3

(LSB)

DIGITAL
OUTPUTS

rlli!t 2-2

TIMING
AND
CONTROL

po

~

~ 2-8
~ 2-7
~ 2-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~

2-1 (MSB)
(7) END OF
CONVERSION (EOC)

ADcoaoa, ADCOa09
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH a·CHANNEL MULTIPLEXERS
operating sequence

r

1lf ,

CLOCK

START
CONVERSION
ADDRESS LOAD
ENABLE

50%

50%

\. i

.;

tw(ALC)

~ADDRESSSTABLE

ADDRESS

5°illso%1
tsu~th

ANALOG INPUT

y
I
I·
___-+I~><}
I

I

MULTIPLEX OUTPUT
(INTERNAL)

::

t

~:

ANALOG VALUE

I

x'-_______

·1

INPUT STABLE

ANALOGVALU~~:____~><=,

___________

I
ENDOF
CONVERSION
OUTPUT
ENABLE

I

\

SO%

1,50%

t--tdIEOC) -i'-----------;(~;---------~ I

I·

tconv

-I

t

______________________-(:.~f_ _ _ _ _S_O·.,J'Io

--I :- ten
LATCH OUTPUTS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~'f~-------9-00~'Ior
HI-Z STATE

\

SO%

"'1 I- tdis
~

10%}l'---------4'.f 10%

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-17

ADC0808, ADC0809
CMOS ANAlOG·TO·DlGITAl CONVERTERS
WITH 8·CHANNEl MULTIPLEXERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 0.3 to 15 V
all other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 DC to 85 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150 DC
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . .. .......
260 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260 DC
NOTE 1: All voltage values are with respect to network ground terminal.

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

4.5

5

6

Vee

Positive reference voltage, Vref+ (see Note 21
Negative reference voltage, V ref-

0

Differential reference voltage, V ref + - VrefHigh·level input voltage, VIH

V

Vee +0.1

V

-0.1

V
V

5

Vee- 1.5

V

Low·level input voltage, VIL
-40

Operating free·air temperature, TA

UNIT

1.5

V

85

°c

NOTE 2: Care must be taken that this rating is observed even during power-up.

electrical characteristics over recommended operating free-air temperature range.
to 5.25 V (unless otherwise noted)

Vee

4.75 V

total device
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

10l

TEST CONDITIONS
10 = -360 p.A

I Data outputs
I End of conversion

Typt

MAX

0.45

10=1.2mA

0.45

Va = VCC

output current

Va = 0

II

Control input current at maximum input voltage

VI = 15 V

IlL

Low~level

VI = 0

ICC

Supply current

f clock = 640 kHz

Ci

Input capacitance, control inputs

Co

Output capacitance, data outputs

UNIT
V

10=1.6mA

Off-state (high-impedance-state)

control input current

MIN

Vee -0.4

3
-3
1

V
p.A
p.A

-1

p.A

0.3

3

mA

TA = 25°C

10

15

pF

TA = 25°C

10

15

Resistance from Din 1 2 to Din 16

pF
kll

1000

analog multiplexer
PARAMETER
Ion

loff

TEST CONDITIONS

Channel on-state current (see Note 3)

Channel off-state current

VI = VCC,

f clock = 640 kHz

VI = 0.1 V,

f clock = 640 kHz

VCC = 5 V,

VI = 5 V

TA = 25°C

VI = 0

VCC = 5 V

VI = 5 V
V = 0

MIN

Typt

MAX

2
-2
10

200

-10

-200
1
-1

UNIT
p.A
nA
p.A

tTypical values are at Vce = 5 V and TA = 25°C.
NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock
frequency.

~

TEXAS
INSTRUMENTS
2-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0808, ADC0809
CMOS ANALOG·TO·DlGITAL CONVERTERS
WITH 8·CHANNEL MULTIPLEXERS
timing requirements, Vee

Vref+

5 V, Vref-

PARAMETER

oV

(unless otherwise noted)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

10

640

1280

kHz

90

100

116

fclock

Clock frequency

teonv

Conversion time

tw(s)

Pulse duration, START

200

ns

tw(ALEI

Pulse duration, ALE

200

ns

tsu

Setup time, ADDRESS

50

ns

th

Hold time, ADDRESS

50

ns

td

Delay time, EOe

See Note 4

See Notes 4 and 5

operating characteristics, T A
otherwise noted)

25°e,Vee

PARAMETER
Supply voltage
kSVS

sensitivity

Vref+

TEST CONDITIONS

5 V, Vref-

MIN

Vee ~ Vref+ ~ 4.75 V to 5.25 V,
~ - 40°C to S5°e, See Note 6

TA

Linearity error

(see Note 7)

Total unadjusted
error (See Note 9)

o V, fclock

ADC0808
Typt
MAX

TA
TA
TA

ten

Output enable time

eL

tdis

Output disable time

eL

~
~

~

25°C

MIN

~s

640 kHz (unless

ADC0809
Typt
MAX

UNIT

±0.05

±0.05

%/V

±0.25

±0.5

LSB

±0.25

LSB

±0.25

Zero error (see Note 8)

14.5

0

~s

±0.25

-40°C to 85°C

±0.5

±0.5
± 1.25

±0.75

ooe to 70°C

LSB

±1

~

50 pF, RL

~

10 kf!

80

250

80

250

ns

~

10 pF, RL

~

10 kf!

105

250

105

250

ns

tTypical values for all except supply voltage sensitivity are at Vee ~ 5 V, and all are at TA ~ 25°C.
NOTES: 4. Refer to the operating sequence diagram.
5. For clock frequencies other than 640 kHz, td(EOe) maximum is 8 clock periods plus 2 ~s.
6. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and Vref + are varied together and the change in accuracy is measured with respect to full-sc~le.
7. Linearity efror is the maximum deviation from a straight line through the end pOints of the AID transfer characteristic.
S. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
9. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.

TEXAS

-Ij}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-19

ADC0808, ADC0809
CMOS ANAlOG·TO·DIGITAl CONVERTERS
WITH 8·CHANNEl MULTIPLEXERS
PRINCIPLES OF OPERATION
The ADC0808 and ADC0809 each consists of an analog signal multiplexer, an 8-bit successiveapproximation converter, and related control and output circuitry.

multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.

converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately onehalf the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bitcounting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.

THRESHOLD
DETECTOR.

TO
OUTPUT
LATCHES

FIGURE 1. SIMPLIFIED MODEL OF THE SUCCESSIVE-APPROXIMATION SYSTEM

-1!1

TEXAS
INSTRUMENTS
2-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0808M
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
NOVEMBER 1986-REVISED MAY 1988

•

•
•
•
•

•
•

•
•
•
•
•

Total Unadjusted Error ... ± 0.75 LSB Max

J
DUAL-IN· LINE PACKAGE

Resolution of 8 Bits

(TOP VIEW)

100 P.s Conversion Time

~})NPUTS

'NPurs{

Ratiometric Conversion
Monotonous Over the Entire AID Conversion
Range

~}ADDRESS

START
EOC
2- 5
OEN
ClK

No Missing Codes
Easy Interface with Microprocessors
Latched 3-State Outputs
Latched Address Inputs

ALE
2-1 (MSB)
2-2
2- 3
2- 4
2- 8 (lSB)
REF2- 6

VCC
REF+
GND
2- 7

Single 5-Volt Supply
Low Power Consumption
Designed to be Interchangeable with
National Semiconductor ADC0808CJ

FK PACKAGE
(TOP VIEW)
<01D~M

description

N

~O

1-1- 1-1- I- 1-1-

The ADC0808M is a monolithic CMOS device
with an 8-channel multiplexer, an 8-bit analogto-digital (AID) converter, and microprocessorcompatible control logic. The 8-channel
multiplexer can be controlled by a microprocessor through a 3-bit address decoder with
address load to select anyone of eight singleended analog switches connected directly to the
comparator. The 8-bit AID converter uses the
successive-approximation conversion technique
featuring a high-impedance threshold detector,
a switched capacitor array, a sample-and-hold,
and a successive-approximation register (SAR).
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.

=>=>
=>=> => =>=>
tl.tl. tl.tl. tl. tl.tl.
ZZ ZZ ~ Z Z
4

INPUT 7

3

2

1 28 27 26

5

25
24
23

8

22

OE
ClK

9

21

10

20

VCC

11

19
12131415 16 17 18

N

The comparison and converting methods used
eliminate the possibility of missing codes,
nonmonotonicity, and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs
from the SAR and latched inputs to the multiplexer address decoder. The single 5-volt supply and low
power requirements make the ADC0808M especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808M is characterized for operation over the full military temperature range of - 55°C to 125°C.

PRODUCTION DATA documents contain inform.tion
current •• of public.tion d.te. Product. conform to

specifications per the terms of TaxIs Instruments

st.nd.rd w.rr.nty. Production proce••ing do •• not
n.c.... rily include testing of .11 parameters.

Copyright

©

1986, Texas Instruments Incorporated

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-21

ADC0808M
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
functional block diagram (positive logic)
SAMPLE·AND·HDLD
BINARY·WEIGHTED
CAPACITORS
REF+
REF-

(12)
(16)

0~

\

SWITCH
MATRIX

.-

THRESHOLD
DETECTOR

ANALOG
INPUTS

3

J..!.!.

4

~

5

~

JEl 2-8

-[>

(27)

-

2~

~

ANALOG
MULTIPLEXER

J.!il.

~ 2-6
OUTPUT
LATCHES

TIMING
AND
CONTROL

EN

START CONVERSION (START)
OUTPUT ENABLE (OE)

(10)
(6)
(9)

(25)
ADDRESS A
ADDRESSB
ADDRESS
DECODER
ADDRESSC
.@.
ADDRESS LOAD
t>
ENABLE (ALE)

~

~

MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS

H
1

ANALOG

A

STROBE

CHANNEL

1
1
1
i
i
i
1
i

0
1

B

L

L

L

L

L

H

L

H

L

L

H

H

H

L

L

H

L

H

H

H

L

H

H

H

~
~

SELECTED
ADDRESS

C

2

3
4
5
6
7

high level, L ~ low level
low-to-high transition

-Ijj

TEXAS
INSTRUMENTS
2-22

~ 2-4

DIGITAL
OUTPUTS

E.!l

2-1 (MSB)
(7) END OF

CONVERSION (EOC)

~
CLOCK

.J!!.L 2-5
~ 2-3
~ 2-2

~

6~

(LSB)

2-7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0808M
CMOS ANALOG-TO-DIGITAL CONVERTER
WITH 8-CHANNEL MULTIPLEXER
operating sequence

rllfi
CLOCK

START
CONVERSION

50%

ADDRESS LOAD
ENABLE

SO%

:

~

i

twIALC)

r--:------+- ADDRESS STABLE

ADDRESS

ANALOG INPUT

SO~_SO_~_'~:________________~:,~'------------------------------__
tsu +-r-: th :

-y.,

I·
MULTIPLEX OUTPUT
(INTERNAL)

I

:

ANALOG VALUE

I

INPUT STABLE

x~

::

_____________________

-I

><

-----+-'

ANALOG

I

~

__

----------------------

I

ENDOF
CONVERSION

1

f--td( EOC)

----1\SO%

'----------~r,~'

150%

____________-.J 1

I""I·------tconv--------~·I

OUTPUT
ENABLE

LATCH OUTPUTS

________________________~:~f------5-0~%t
--I :- ten

\SO%

""I I- tdis

~ _____________~9~O~%f
~
-----------------H-I.-Z-S-T-AT-E-------jff 10% ~F---------4'.( 10%

-II}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-23

ADC0808M
CMOS ANALOG-TO-DIGITAL CONVERTER
WITH 8-CHANNEL MULTIPLEXER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 to 15 V
all other inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .. ~0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case ter:nperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
NOTE 1: All voltage values are with respect to network ground terminal.

recommended operating conditions
Supply voltage. VCC

MIN

NOM

MAX

4.5

5

6

Positive reference voltage, V ref + (see Note 2)

Vee
0

Negative reference voltage, V ref-

Differential reference voltage. V ref + - VrefHigh-level input voltage, VIH

Vee+ O.1
-0.1

5

UNIT
V
V
V
V
V

Vee- 1.5

Low·level input voltage, VIL

1.5

V

Start pulse duration, tw(S)

200

ns

Address load control pulse duration, tw(ALC)

200

ns

Address setup time, tsu

50

ns

Address hold time, th

50

Clock frequency, fclock

10

Operating free·air temperature, T A

-55

NOTE 2: Care must be taken that this rating is observed even during power·up.

~

TEXAS
INSTRUMENTS
2-24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ns
640

1280

kHz

125

DC

ADC0808M
CMOS ANALOG·TO·DlGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
electrical characteristics over recommended operating free-air temperature range. Vee = 4.5 V to
5.5 V (unless otherwise noted)
total device
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

10Z

TEST CONDITIONS
10 = -360 ~A

I Data outputs
I End of conversion

Typt

MIN

MAX

10=1.6mA

0.45

10 = 1.2 mA

0.45

Off-state (high-impedance-stBteJ

Vo = Vee

output current

Vo = 0

UNIT
V

Vee-OA

3
-3
1

V
~A

~A

Control input current at maximum input voltage

VI = 15 V

Low-level control input current

VI = 0

Supply current

Iclock = 640 kHz

ei

Input capacitance, control inputs

TA = 25°C

10

pF

Co

Output capacitance, data outputs

TA = 25°C

10

pF

1000

k!l

II
IlL
ICC

0.3

Resistance from pin 12 to pin 16

-1

~A

3

mA

analog multiplexer
PARAMETER
Ion

lolf

TEST CONDITIONS

Channel on-state current (see Note 3)

Channel off-state current

Typt

MIN

VI = Vee,
VI = 0,

Iclock = 640 kHz

Vee = 5 V,

VI = 5 V

TA = 25°C

VI = 0

UNIT

2
-2

I clock = 640 kHz

Vee = 5 V

MAX

10

200

-10

-200

VI = 5 V

1
-1

VI = 0

"A
nA
~A

tTypical values are at Vec = 5 V and TA = 25°C.
NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock
frequency.

timing characteristics. Vee

Vref+

5 V. Vref-

o V.

TA

25°e (unless otherwise noted)
MIN

TYP

MAX

UNIT

10

640

1280

kHz

90

100

116

See Figure 1

150

360

ns

Enable time, low

See Figure 1

90

250

ns

tdis

Output disable time

See Figure 1

200

405

ns

twlsl

Pulse duration, START

200

ns

twlALEI

Pulse duration, ALE

200

ns

tsu

Setup time, ADDRESS

50

ns

th

Hold time, ADDRESS

50

tdlEOCI

Delay time, EOC

PARAMETER

TEST CONDITIONS

Iclock

Clock Irequency

tconv

Conversion time

See Notes 4 and 5 and Figure 1

tenH

Enable time, high

tenL

See Notes 4 and 6 and Figure 1

0

~s

ns
14.5

~s

NOTES: 4. Reier to the operating sequence diagram.
5. For clock frequencies other than 640 kHz, tconv is 57 clock cycles minimum and 74 clock cycles maximum.
6. For clock frequencies other than 640 kHz, tdlEOCI maximum is 8 clock cycles plus 2 ~s.

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-25

ADC0808M
CMOS ANALOG-TO-DiGITAL CONVERTER
WITH 8-CHANNEL MULTIPLEXER
operating characteristics, T A
otherwise noted)

Vref+

TEST CONOITIONS

PARAMETER
kSVS

o V, fclock

5 V, Vref-

= Vref+ = 4.5 V to
= -55°e to 125°e,

Vee

Supply voltage sensitivity

MIN

5.5 V,

640 kHz (unless
Typt

MAX

UNIT

±0.05

%/V

Linearity error Isee Note 8)

±0.25

LSB

Zero error Isee Note 9)

±0.25

TA

Total unadjusted error. Isee Note 10)

TA
TA

=
=

See Note 7

25°e

±0.25

-55°e to 125°e

LSB
±0.5
±0.75

LSB

t Typical values for all except supply voltage sensitivity are at Vee = 5 V, and all are at T A = 25°e.
NOTES: 7. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and V ref + are varied together and the change in accuracy is measured with respect to full-scale.
8. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
9. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.

10. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.

PARAMETER MEASUREMENT INFORMATION
Vee
TEST
POINT

5 kll

OUTPUT--~-----------e-----MI---~

11.7 kll

100 pF

FIGURE 1, TEST CIRCUIT

TEXAS

-iii

INSTRUMENTS
2-26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0808M
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
PRINCIPLES OF OPERATION
The ADC0808M consists of an analog signal multiplexer, an 8-bit successive-approximation converter,
and related control and output circuitry.

multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.

converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 2). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately onehalf the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bitcounting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.

Sc
THRESHOLD
DETECTOR

TO
OUTPUT
LATCHES

FIGURE 2. SIMPLIFIED MODEL OF THE SUCCESSIVE-APPROXIMATION SYSTEM

TEXAS

..Ij}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-27

2-28

TlC0820A. TlC0820B. ADC0820B. ADC0820C
Advanced linCMOSTM HIGH-SPEED 8-BIT ANAlOG-TO-DlGlTAl
CONVERTERS USING MODIFIED "FlASH" TECHNIQUES
02873, SEPTEMBER 1996-REVISED FEBRUARY 1989

•

Advanced LinCMOS'· Silicon-Gate
Technology

•

8-Bit Resolution

•

Differential Reference Inputs

•

Parallel Microprocessor Interface

•

Conversion and Access Time Over
Temperature Range
Write-Read Mode ... 1.18 itS and 1.92 itS
Read Mode ... 2.5 itS Max

•

No External Clock or Oscillator Components
Required

•

On-Chip Track-and-Hold

•

Low Power Consumption ... 50 mW Typ

•

Single 5-V Supply

•

TLC0820B is Direct Replacement for
National Semiconductor ADC0820B/BC and
Analog Devices AD7820L/C/U;
TLC0820A is Direct Replacement for
National Semiconductor ADC0820C/CC and
Analog Devices AD7820K/B/T

All TYPES ... OW OR N PACKAGE
TlC0820_M .. , J PACKAGE
(TOP vlEWI

ANLG IN
(LSBI DO
D1
D2
D3
WR/RDY
MODE
RD
INT
GND

Vee
Ne
OFLW
D7 (MSBI
D6
D5
D4
es
REF+
REF-

TlC0820_M ... FK PACKAGE
TlC0820_1. TlC0820_C ... FN PACKAGE
AOC0820_CI. ADC0820_C ... FN PACKAGE
(TOP VIEWI

description
The TLC0820A, TLC0820B, ADC0820B, and
ADC0820C are Advanced LinCMOS'· 8-bit
analog-to-digital converters each consisting of
two 4-bit "flash" converters, a 4-bit digital-toanalog converter, a summing (error) amplifier,
. control logic, and a result latch circuit. The
modified "flash" technique allows low-power
integrated circuitry to complete an 8-bit
conversion in 1.18 itS over temperature. The onchip track-and-hold circuit has a 100 ns sample
window and allows these devices to convert
continuous analog signals having slew rates of
up to 100 mV//ls without external sampling
components. TTL-compatible three-state output
drivers and two modes of operation allow
interfacing to a variety of microprocessors.
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.

mZ

(fJ-

...Jl9
-...J

o

Z

U
UU

ooZ
3

D2
D3
WR/RDY
MODE
RD

2

1 20 19

4

18

5

17

6

16

8

14

15

OFLW
D7 (MSBI
D6
D5
D4

9 1011 12 13

I~

0
I
Zu..

~1t3

19UJ UJ

0:: 0::

NC - No internal connection

The M-suffix devices are characterized for operation over the full military temperature range of - 55°C
to 125°C. The I-suffix devices are characterized for operation from - 40°C to 85 °C. The C-suffix devices
are characterized for operation from O°C to 70°C. See Available Options.

Advanced linCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documonts contoin information
current as of publication dato. Products conform to
specifications per the terms of Texes Instruments
standard warranty. Production processing does not

necessarily include testing of all parameters.

Copyright © 1986, Texas Instruments Incorporated

-Ij}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-29

TLC0820A. TLC0820B •. ADC0820B. ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DlGlTAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
AVAILABLE OPTIONS
SYMBOLIZATION t
PACKAGE

DEVICE

OPERATING

TOTAL

TEMPERATURE

UNADJUSTED

RANGE

ERROR

SUFFIX

TLC0820AC

OW, FN, N

O°C to 70°C

± 1 LSB

TLC0820AI

OW, FN, N

-40°C to 85°C

± 1 LSB

TLC0820AM

OW, FK, J, N

TLC0820BC

OW, FN, N

TLC0820BI

OW, FN, N

TLC0820BM

OW, FK, J, N

AOC0820BC

- 55°C to 1 25°C

± 1 LSB

OOC to 70°C

±O.5 LSB

-40°C to 85°C

±O.5 LSB

-55°C to 125°C

±O.5 LSB

OW, FN, N

OOCto70°C

±O.5 LSB

AOC0820BCI

OW, FN, N

-40°C to 85°C

±O.5 LSB

AOC0820CC

OW, FN, N

OOC to 70°C

± 1 LSB

AOC0820CCI

OW, FN, N

-40°C to 85°C

+ 1 LSB

t In many instances, these ICs may have both TLC0820 and AOC0820 labeling
on the package.

functional block diagram
REF+
REF-

4-BIT FLASH
ANALOG-TODIGITAL
CONVERTER
(4 MSBsl

(121
(111

4

4

~
~ DO

4
~

a- c--

4-BIT
OIGITALTO-ANALOG
CONVERTER

,.--

OUTPUT
LATCH
ANO
3-STATE
BUFFERS

~

01

~

02

~

03

~

04

(LSBI

~ 05
~

'-- -1
ANLG IN

(11

+1

l:

-

4-BIT FLASH
ANALOG-TODIGITAL
CONVERTER
(4 LSBsl

~
4

D
MODE
WRIRDY
CS
RD

(71
(61

TIMING
ANO
CONTROL

(131
(81

~

TEXAS
INSTRUMENTS
2-30

06

--.J!2.I.. 07 (MSB)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~

DIGITAL
OUTPUTS

TLC0820A, TLC0820B, ADC0820B, ADC0820C
AdvanceJi LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DlGlTAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PIN
NAME
ANLG IN

DESCRIPTION

NUMBER
1

Analog input

es

13

DO

2

This input must be low in order for RD or WR to be recognized by the ADe.
Three-state data output, bit 1 (LSBI

01

3

Three-state data output, bit 2

02

4

Three-state data output, bit 3

03

5

Three-state data output, bit 4

04

14

Three-state data output, bit 5

05

15

Three-state data output, bit 6

06

16

Three-state data output, bit 7

07

17

Three-state data output, bit 8 (MSBI

GND

10

INT

9

Ground
In the WRITE-READ mode, the interrupt output, INT, going low indicates that the internal count-down delay time,
td(intl, is complete and the data result is in the output latch. td(intl is typically 800 ns starting after the rising
edge of the WR input (see operating characteristics and Figure 31. If RD goes low prior to the end of td(intl'
INT goes low at the end of tdRIL and the conversion results are available sooner (see Figure 21. INT is reset by the
rising edge of either RD or es.

MODE

7

Mode-selection input. It is internally tied to GNO through a

50~JlA

current source, which acts like a pull-down

resistor.

READ mode: Occurs when this input is low.
WRITE-READ mode: Occurs when this input is high.
Ne

19

No internal connection

OFLW

18

Normally the OFLW output is a logical high. However, if the analog input is higher than the VREF +, OFLW
will be low at the end of conversion. It can be used to cascade 2 or more devices to improve resolution (9

or 10-bitsl.
RD

8

In the WRITE-READ mode with es low, the 3-state data outputs DO through 07 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal

count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the READ mode with es low, the conversion starts with RD going low. RD also enables the three-state
data outputs upon completion of the conversion. The ROY output going into the high-impedance state and

INT going low indicates completion of the conversion.
REF

~

11

This input voltage is placed on the bottom of the resistor ladder.

REF+

12

This input voltage is placed on the top of the resistor ladder.

Vee

20

WR/RDY

6

Power supply voltage
In the WRITE-READ mode with es low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(intj,
provided that the RD input does not go low prior to this time. td(int) is approximately 800 ns.
In the READ mode, ROY (an open-drain outputl will go low after the falling edge of es, and will go into the
high-impedance state when the conversion is strobed into the output latch. It is used to simplify the interface
to a microprocessor system.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-31

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TQ-DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
TLC0820_M

TLC0820_1

TLC0820_C

ADC0820_CI

ADC0820_C

10

10

10

Supply voltage, VCC (see Note 1)

~

-0.2 to

Input voltage range, all inputs (see Note 1)

0.2 to

V

- 0.2 to

V

VCC+ 0 .2
-0.2 to

VCC+0.2
-0.2 to

VCC+0.2
- 0.2 to

Operating free-air temperature range

VCC+0.2
- 55 to 125

VCC+0.2
-40t085

VCC+0.2
to 70

Storage temperature range

-65 to 150

-65 to 150

-65 to 150

260

260

260

260

Output voltage range, all outputs (see Note 1)

Case temperature for 60 seconds: FK package

V

o

260

Case temperature for 10 seconds: FN package
Lead temperature 1,6 mm (1116 inch) from case

300

for 60 seconds: J package
Lead temperature 1,6 mm (1/16 inch) from case

260

for 10 seconds: DW or N package

UNIT

°c
°c
°c
°c
°c
°c

NOTE 1: All voltages are with respect to network ground terminal, pin 10.

recommended operating conditions
TLC0820_M

MIN

NOM

Supply voltage, VCC

4.5

5

Analog input voltage

-0.1

Positive reference voltage, VREF +

VREFGND

Negative reference voltage, VREFHigh-level inpu VCC
voltage, VIH

Low-level input VCC
voltage, V,L

=

4.75 V CS, WR/RDY, RD

to 5.25 V

=

MODE

(see Figures 1, 2, 3, and 4)
Delay time from WR to RD in write-read mode,
tdWR (see Figure 2)
Write-pulse duration in write-read mode, tww

(see Figures 2, 3, and 4)
Operating free-air temperature, T A

MIN

NOM

8

4.5

5

Vee+ O.1

-0.1

Vee

VREFVREF+ GND

MIN

NOM

8

4.5

5

Vee+ O.1

-0.1

Vee

VREFVREF+ GND

2

2

3.5

3.5

UNIT

MAX
8

V

Vee+ O.1

V

Vee

V

VREF+

V
V

0.8

0.8

0.8

1.5

1.5

1.5

V

500

500

500

ns

0.4

0.4

0.4

I's

0.5

50

0.5

50

0.5

50

I'S

- 55

125

-40

85

0

70

°c

TEXAS •
INSTRUMENTS
2-32

MAX

2

MODE

Delay to next conversion, td(NC)

TLC0820_C
ADC0820_C

3.5

4.75 V CS, WR/RDY, RD

to 5.25 V

MAX

TLC0820_1
ADC0820_CI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0820A, TLC0820B, ADC0820B, ADC0820C
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DlGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
electrical characteristics at specified operating free-air temperature, Vee = 5 V (unless otherwise noted)
PARAMETER

TEST CONDITONS
~

Vee
VOH

High-level autput valtage

Any D, INT, ar OFLW

4.75 V,

IOH ~ - 360
~

Vee

~A

4.75 V,

IOH ~ -10 pA
VOL

Law-level autput voltage

Any D, OFLW, INT,

Vee

ar WR/RDY

IOL

~

5.25 V,

~

1.6 mA

es ar RD
IIH

High-level input current

Low-level input current

Off· state (high-impedance
IOZ

state) output current

~

VIH

or MODE

5 V

VIL ~ 0
Vo

~

5 V

Vo

~

0

Any D or WR/RDY

VI

~

5 V

es at 5 V,
VI
ar WR/RDY

Vo

~
~

0
5 V

~

0

INT

Reference resistance

ICC

Supply current

ei

Input capacitance

ea

Output capacitance

4.6

Full range

0.4
0.34

25°C
0.005

1

0.1

0.3

50

170

-0.005

-1

Full range
25°C

0.1

0.3

-0.1

-0.3

-3

25°C
Full range

0.3

Full range

-3

8.4
-6
-4.5

25°C

- 5.3

Full range

1.25

Full range

ANLG IN
Any digital

-7.2

Full range

25°C

Full range

~A

-0.3

25°C

Full range

~A

7

Full range

and RD at 0 V

~A

3

25°C

es, WR/RDY,

~A

3

Full range

25°C

V

200

Full range

Full range

UNIT

3

25°C

25°C

Any digital

MAX

V

25°C

Any D ar OFLW
Vo

Rref

4.5

25°C

25°C

es, WR/RDY, RD,

Any D, OFLW, INT,

lOS

Full range

Full range

Analog input current

Short-circuit output current

2.4

TYPt

Full range

WR/RDY

es at 5 V,
II

Full range

Full range

MODE
IlL

MIN

1.4

14
rnA

-12

-9
6
2.3

5.3

7.5

13

15
5

kll
rnA
pF

45
5

pF

t All typical values are at T A ~ 25°C.

TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-33

TlC0820A. TlC0820B. ADC0820B. ADC0820C
Advanced linCMOS™ HIGH·SPEED 8·BIT ANAlOG·TO·DlGITAl
CONVERTERS USING MODIFIED "flASH" TECHNIOUES
operating characteristics, Vee = 5 V, VREF + = 5 V, VREF(unless otherwise noted)

0, tr

20 ns, TA

tf

TlC08208
PARAMETER

TEST CONDITIONS
MIN

Supply voltage
kSVS

sensitivity

Total unadjusted error t
Read mode
tconvR

conversion time

VCC

~

5 V ± 5%, T A

MODE pin at 0 V, T A

~

~

MIN to MAX

ADC0820C

TYP

MAX

±1116

±114

MIN to MAX

MIN

UNIT

TYP

MAX

±1116

± 114

lSB

1

lSB

112

MODE pin at 0 V, See Figure 1
~

TlC0820A

ADC08208

1.6

2.5

1.6

2.5

~s

800

1300

800

1300

ns

tconvR
+20

tconvR

tconvR

tconvR

+50

+20

+50

Internal count-

MODE pin at 5 V,

down delay time

See Figures 3 and 4

taR

Access time from RD.

MODE pin at 0 V, See Figure 1
MODE pin at 5 V,

Cl

~

15 pF

190

280

190

280

taRl

Access time from RD.

tdWR < tdlintl,
See Figure 2

Cl

~

100 pF

210

320

210

320

MODE pin at 5 V,

Cl

~

15 pF

70

120

70

120

taR2

Access time from RD.

tdWR > tdlintl
See Figure 3

Cl

~

100 pF

90

150

90

150

tdlintl

taiNT

Access time from INn

tdis

Disable time from RDI

tdRDV
tdRIH
tdRll
tdWIH

Cl

50 pF,

MODE pin at 5 V, See Figure 4
Rl

~

1 kD,

Cl

~

Delay time from

MODE pin at 0 V,
See Figure 1
~

Cl

Delay time from

Cl

RDI to INTI

See Figures 1, 2, and 3

Delay time from

MODE pin at 5 V,

RD. to INT.

See Figure 2

Delay time from

MODE pin at 5 V,

WRi to INTI

See Figure 4

~

tdWR
Cl

~

< td lintl'
50 pF,

50

20

50

ns

95

70

95

ns

50

100

50

100

ns

125

225

125

225

ns

200

290

200

290

ns

175

270

175

270

ns

0.1

Slew rate tracking

t Total unadjusted error includes offset, full-scale, and linearity errors.

TEXAS

-Ij}

INSTRUMENTS
2-34

ns

20

50 pF,

50 pF,

ns

70

10 pF,

See Figures 1, 2, 3, and 5

CS. to RDV.

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.1

VI~s

TLC0820A. TLC0820B. ADC0820B. ADC0820C
Advanced LinCMOS™ HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PARAMETER MEASUREMENT INFORMATION

cs ~'-_ _ _ _ _ _--'/

\,
~----

I

\~ __

\ _ _ _ _...Jf
I

WR/ROY

-41

x..l\

I

f.-td(NCI--\

~

I

r.:
:,--I

r+-WITH fXTERNAL PULL-UP

~~t-d-RO-Y-~

:

-+t

\.

I4--tconVR~

00-07

tdRIH

I

------T-------{

I }--------

f4--taR~

--+I

"\.-tdiS

FIGURE 1. READ MODE WAVEFORMS (MODE PIN LOW)

cs\

;:.:~

WR/ROY

I -------\~_-'C

~

~tdWR-lJ

=nI

I

j.- tdOntl---.j

00-07

t:tdRIH

I
I (-

--------------t{
----.I ~ --.J !.taR2

FIGURE 2. WRITE-READ MODE WAVEFORMS
[MODE PIN HIGH AND tdWR < td(int)1

1t

tdis

FIGURE 3. WRITE-READ WAVEFORMS
[MODE PIN HIGH AND tdWR > td(int)1

CS LOW - - - - - - - - - - - - -

WR/ROY

=-I
INT _ _

00-07

~tdWIH ~td(NCI

~lf

---~)

I

\.

!4-tdOntl~

<

i+-taiNT

e:~,~

)-

FIGURE 4. WRITE-READ MODE WAVEFORMS
(STAND-ALONE OPERATION. MODE PIN HIGH. AND RD LOW)

'iii

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-35

TLC0820A, TLC0820B, ADC0820B,ADC0820C
Advanced LinCMOS™ HIGH·SPEED 8·BIT ANALOG·TO·DlGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
PARAMETER MEASUREMENT INFORMATION
CL

VCC

TLC0820
OR

VCC RD

RD

DATA
OUTPUT

Dn
CS

-1-~90""'%""'--1

GND

50%
110%
1

~ Idisl4-

GND
CL

VOH

1 k!l
DATA
OUTPUTS

-=

I,

=

1

~O%
"""'-

GND------------~

20 ns

VCC

CL = 10 pF

~I'!4-

TLC0820

VCC-_.J.....J.~_--_
1
90%
RD
1 50%
110%
GND

OR
1 kr!

ADC0820
INPUT

10 pF

~I,t+-

ADC0820
INPUT

=

RD

DATA
OUTPUT

Dn
CS

1

----+t Idis 14VCC

GND
CL

DATA

I

:~

OUTPUTS VOL - - - 1 1 0 %
I,

Dn

=

=

20 ns

DO ... D7
VOLTAGE WAVEFORMS

TEST CIRCUIT

FIGURE 5. TEST CIRCUIT AND VOLTAGE WAVEFORMS

'I!J

TEXAS
INSTRUMENTS
2-36

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC0820A. TLC0820B. ADC0820B. ADC0820C
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DiGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRINCIPLES OF OPERATION
The TLC0820A, TLC0820B, ADC0820B and ADC0820C each employ a combination of "sampled-data"
comparator techniques and "flash" techniques common to many high-speed converters. Two 4-bit "flash"
analog-to-digital conversions are used to give a full 8-bit output.
The recommended analog input voltage range for conversion is - 0.1 V to VCC + 0.1 V. Analog input signals
that are less than VREF _ + % LSB or greater than VREF + - % LSB convert to 00000000 or 11111111
respectively. The reference inputs are fully differential with common-mode limits defined by the supply rails.
The reference input values define the full-scale range of the analog input. This allows the gain of the ADC to
be varied for ratiometric conversion by changing the VREF + and VREF - voltages.
The device operates in two modes, read (only) and write-read, which are selected by the MODE pin (pin 7).
The converter is set to the read (only) mode when pin 7 is low. In the read mode, the WR/RDY pin is used
as an output and is referred to as the "ready" pin. In this mode, a low on the "ready" pin while CS is low
indicates that the device is busy. Conversion starts on the falling edge of RD and is completed no more than
2.5 fiS later when INT falls and the "ready" pin returns to a high-impedance state. Data outputs
also change from high-impedance to active states at this time. After the data is read, RD is taken high, INT
returns high, and the data outputs return to their high-impedance states.
The converter is set to the write-read mode when pin 7 is high and WR/RDY is referred to as the "write" pin.
Taking CS and the "write" pin low selects the converter and initiates measurement of the input signal.
Approximately 600 ns after the "write" pin returns high, the conversion is completed. Conversion starts on
the rising edge of WR/RDY in the write-read mode.
The high-order 4-bit "flash" ADC measures the input by means of 16 comparators operating simultaneously.
A high precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After
a time delay, a second bank of comparators does a low-order conversion on the analog difference between
the input level and the high-order DAC output. The results from each of these conversions enter an 8-bit latch
and are output to the three-state buffers on the falling edge of RD.

"11

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-37

TlC0820A. TlC0820B. ADC0820B. ADC0820C
Advanced linCMOSTM HIGH·SPEED 8·BIT ANAlOG·TO·DlGITAl
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
TYPICAL APPLICATION OAT A

("\. es

(13)

WR

(6)

(20)
Vee 1 - - 5 V
(1)

ANLGIN

WRiROY ANLG
IN

n>
~p

es

~

DO

(2)

01

(3)

02

(4)

BUS 03

(5)

04

(14)

05

(15)

06

(16)

07

(17)

RO
(7)

DO
01

MODE f---5V
REF+

(12)

l

02
03
04
05

REF-

(11 )

06
07

08

~

(10)

(18)

OFL

OFLW

GNO

I~~
(13)
es
(6)

WRiROY

~
(2)

(15)
(16)
(17)

(18)

(20)
Vee 1--5 V
(1 )

ANLG
IN

01

MODE 1--5 V
REF+

(12)

02
03
04
05
06
07

OFLW

""~ "" I
~:":

lO.lllF

GNO

FIGURE 6. CONFIGURATION FOR 9-SIT RESOLUTION

~

TEXAS
INSTRUMENTS
2-38

POST OFFICE BOX 655303 • DALLAS,

t-

(7)

DO

(5)
(14)

.1 IlF

RO

(3)
(4)

*

~

5V

TE~AS

75265

ADC0831A. ADC0832A. ADC0831B. ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
02795, AUGUST 1985- REVISED JUNE 1986

ADC0831 ... P DUAL-iN-LINE PACKAGE

•

8-Bit Resolution

•

Easy Microprocessor Interface or StandAlone Operation

•

Operates Ratiometrically or with 5-V
Reference

(TOP ViEW)

•

•
•

CSUB VCC

Single Channel or Multiplexed Twin
Channels with Single-Ended or Differential
Input Options

•

Designed to be Interchangeable with
National Semiconductor ADC0831 and
ADC0832
DEViCE

7
6

GND

4

5

DB

eLK

DO
REF

(TOP ViEW)

CS

CHO
CHl

Inputs and Outputs are Compatible with
TTL and MOS
Conversion Time of 32 JlS at
ClK = 250 kHz

2
3

ADC0832 ... P DUAL-iN-LINE PACKAGE

Input Range 0 to 5 V with Single 5-V
Supply

•

IN +
IN -

Vec/REF

2

7

CLK

3

6

DO

GND . 4

5

01

TOTAL UNADJUSTED ERROR
A-SUFFiX

ADC0831

± 1 lSB

ADC0832

± 1 LSB

I

I

B-SUFFiX

± % LSB
± % LSB

description
These devices are 8-bit successive-approximation analog-to-digital converters. The ADC0831 A and
ADC0831 B have single input channels; the ADC0832A and ADC0832B have multiplexed twin input
channels. The serial output is configured to interface with standard shift registers or microprocesso·rs.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
The ADC0832 multiplexer is software configured for single-ended or differential inputs. The differential
analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value.
In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution,
The operation of the ADC0831 and ADC0832 devices is very similar to the more complex ADC0834 and
ADC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum
analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set
equal to VCC (done internally on the ADC0832), For more detail on the operation of the ADC0831 and
ADC0832 devices, refer to the ADC0834/ADC0838 data sheet,
The ADC0831 AI, ADC0831 BI, ADC0832AI, and ADC0832BI are characterized for operation from - 40°C
to 85 °e. The ADC0831 AC, ADC0831 BC, ADC0832AC, and ADC0832BC are characterized for operation
from O°C to 70°C.

PRODUCTiON DATA documents contain information

current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

~

Copyright © 1985. Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-39

ADC0831A, ADC0832A. ADC0831B. ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL

functional block diagram
START
FLIP-FLOP

eLK----.---------------------------~----,_~~L__S--,

Cs

>--------------_i>CLK
SHIFT REGISTER

ODDJEVEN

i - - - Di-;-~-+--+---------ID
: IADC0832 :

eLK

L_~~Y~_J

__--------------+-------~--_i>CLK
SINGLE/DIFFERENTIAL

5

CHOJIN " - -_ _--I
CH1/IN

ANALOG
MUX

COMPARATOR

CS
EN

es
EN
REF

AND
DECODER

CLK

EN

LADDER
BITS 0-7

SAR
LOGIC
AND

R

9-BIT
SHIFT

~

TEXAS
INSTRUMENTS
2-40

CS

cs

POST OFFICE BOX 655303 . DALLAS, TEXAS 75265

EOC

DO

ADC0831A. ADC0832A. ADC08318. ADC08328
AID PERIPHERALS WITH SERIAL CONTROL

sequence of operation
ADC0831

CLK
l.-:
-l'

2

4

3

6

10

I,

tsu..l

:

~

It

I

tconv------.tv

MUX
SETTlING--.I

I
I

~

,

J<-------!

I

,

I
IfN-----MSB~FIRST DATA-----_~I "

I

cs

JUlfUl

I

I

~

I I

O~:~£:M~

MSB
7

I-I_...;H.::I.;;~Z

:LSB
6

4

2

__

0

ADC0832
2

4

10

5

11

12

13

• ••

14

18

19

20

21

CLKJ1JlJlJlJll1J1J1JlJ1J1J1~
_I
""?I

cs

I

I

"'- t

,..

...-su

1

I

I

I

I'

::
I ,

START
+ SIGN
BIT
SGL
ODD

,
I

tconv

~

Il

:

·

,

,

I
::

I

:

I

I
I

I

I

I~I~~JII ~~
I
~
DIF

EVEN

MUX
SETTLING

I

I

I I~

MSB~FIRST D A T A - - -.1+--I
LSB~FIRST DATA

-+I I+-

~

O~:~:OJ_TIM---iEi I I

I---rlC

1 -'-1-'--1"'--'1

Cf---r-:

MSB

LSB

1

o

6

6

I

~I

HI~Z

r-

ADC0832 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS

CHANNEL NUMBER
1

SGLlDIF

ODD/EVEN

0

L

L

+

-

L

H

-

+

H

L

+

H

H

+

H = high level, L = low level,. - or + ::::- polarity of selected input pin

-I!}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-41

ADC0831A, ADC0832A, ADC08318, ADC08328
AID PERIPHERALS WITH SERIAL CONTROL
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise
noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V
Input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ........... ± 5 mA
Total input current for package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range: I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 DC to 85 DC
C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 DC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260 DC
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

recommended operating conditions
VCC

Supply voltage

VIH

High-level input voltage

MIN

NOM

MAX

4.5

5

6.3

UNIT
V

2

V

VIL

Low-level input voltage

fclock

Clock frequency

twHICSI

Pulse duration, CS high

220

ns

tsu

Setup time, CS low or ADC0832 data valid before clock;

350

ns

th

Hold time, ADC0832 data valid after clock;

TA

Operating free-air temperature

Clock duty cycle Isee Note 21

0.8

V

10

400

kHz

40

60

%

90

I I-suffix
I C-suffix

ns

-40

85

0

70

°c

NOTE 2: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended

duty cycle range, the minimum pulse duration Ihigh or lowl is 1

~s.

electrical characteristics over recommended range of operating free-air temperature,
fclock = 250 kHz (unless otherwise noted)

Vee

=

5 V,

digital section
TEST CONDITIONst

PARAMETER
VOH

High-level output

VCC

10H

VCC

=
=

4.75 V,

voltage

4.75 V,

10H

=
=

VCC

=

4.75 V,

10L

=

Low-level output
VOL

voltage
High-level input

IIH

current

Low-level input
IlL

current

VIH

=

5 V

VIL

=

0

High-level output
10H

(source) current

Isinkl current
High-impedance-

10Z

-360 p.A
-10

~A

1.6 mA

I SUFFIX
Typt
MAX

MIN

2.4

2.8

4.5

4.6

0.4

0.34

C SUFFIX
Typt
MAX

V
V

0.005

1

0.005

1

p.A

-0.005

-1

-0.005

-1

~A

=

VO,

TA

=

25°C

-6.5

-14

-6.5

-14

mA

VOL

=

VCC'

TA

=

25°C

8

16

8

16

mA

Vo

=

5 V,

TA

=

25°C

0.01

3

0.01

3

Vo

=

0,

TA

=

25°C

-0.01

-3

-0.01

-3

~A

state output
current 1001

UNIT

VOH

Low-level output
10L

MIN

Ci

Input capacitance

5

5

pF

Co

Output capacitance

5

5

pF

t All parameters are measured under open-loop conditions with zero common-mode input voltage.
t All typical values are at VCC = 5 V, TA = 25°C.

TEXAS

'1!1

INSTRUMENTS
2-42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0831A, ADC0832A, ADC0831B, ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL

electrical characteristics over recommended range of operating free-air temperature, Vee
fclock = 250 kHz (unless otherwise noted)

5 V,

analog and converter section
PARAMETER

TEST CONDITIONSt

TYP~

MIN

MAX

UNIT

-0.05

Common-mode input voltage range

V,CR

See Note 3

V

to
Vee +0.05

Standby input
Il(stdbYI

current

isee Note 41
ri(REFI

On-channel

VI

~

Off-channel

VI

~

On-channel

VI

~

Off-channel

VI

~

1

5 V at on-channel,

o at off-channel
o at on-channel,

~1

~1

5 V at off-channel

p.A

1

Input resistance to reference ladder

1.3

2.4

5.9

kO

total device
TEST CONDITIONS t

PARAMETER
ICC

Supply current

MIN

I ADC0831
I ADC0832

Typt

MAX

1

2.5

3

5.2

UNIT
rnA

t All parameters are measured under open-loop conditions with zero common-mode input voltage.
tAli typical values are at VCC ~ 5 V, TA ~ 25°C.
NOTES: 3. If channel IN ~ is more positive than channel IN +, the digital output code will be 0000 0000. Connected to each analog input
are two on-chip diodes that will conduct forward current for analog input voltages one diode drop above VCC. Care must
be taken during testing at low VCC levels i4.5 VI because high-level analog input voltage i5 VI can, especially at high
temperatures, cause this input diode to conduct and cause errors for analog inputs that are near full-scale. As long as the
analog voltage does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute
V to 5 V input voltage range requires a minimum VCC of 4.95 V for all variations of temperature and load.
4. Standby input currents are currents going into or out of the on or off channels when the AID converter is not performing conversion
and the clock is in a high or low steady-state condition.

o

operating characteristics Vee = REF = 5 V, fclock
(unless otherwise noted)

Supply-voltage variation error

~

4.75 V to 5.25 V

Total unadjusted error

Vref

~

5 V,

isee Note 51

TA

Common-mode error
Propagation delay time,

tpd

output data after CLK!
isee Note 61

LSB-first

CL

CSt

RL

± 1116

± 1/4

MIN

~

10 pF,

~

10 kO

UNIT

TYP

MAX

± 1/16

± 1/4

LSB

±1

LSB
LSB

± 1116

± 1/4

± 1/16

±1/4

650

1500

650

1500

250

600

250

600

125

250

125

250

ns

100 pF

data
CL

DO after

~

MAX

± 1/2

Differential mode

data

TYP

MIN to MAX

MSB-first

Output disable time,
tdis

MIN

VCC
~

AI, AC SUFFIX

BI, BC SUFFIX

TEST CONDITIONS§

PARAMETER

20 ns, TA

250 kHz, tr

ns

CL - 100 pF,
RL -- 2 kO

Conversion time (multiplexer
tconv addressing time not included)

500

500

8

8

clock
periods

§ All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,

use the appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The most signific'ant-bit-first data is output directly from the comparator and therefore requires additional delay to allow for
comparator response time. Least-significant-bit-first data applies only to ADC0832.

"!I

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2~43

ADC0831A, ADC0832A, ADC0831B, ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
PARAMETER MEASUREMENT INFORMATION
CLK
_ _...J 1

~

~

GND

I

~

I4- t su

~tsu

ClK

,,\:-:--- --t-:------'"
;0.4 V\
I

1
I

1
I
~th

I

DATA IN

--"'\
2V

I
I

I

14

I
1

----GND

.1

tpd

I

500;"
~
°
VOL

r---VOH

GND

DATA OUT
(DOl
____ -I

I~
1

VCC

I 50%

_---VCC

\1

FIGURE 2. DATA OUTPUT TIMING

(01)

FIGURE 1. ADC0832 DATA INPUT TIMING

i

VCC

FROM
OUTPUT
UNDER
TEST

I

J

TEST
POINT

Sl

CL
(See Note A)

S2

_

l

~ ~~

\:-=
~

LOAD CIRCUIT

..."'""90-%---

VCC
GND

DO AND
SARS OUTPUT

~tdis
DO AND
SARS OUTPUT

Slopen
S2 closed

GND

S 1 closed
S2 open

I

_1~'!...._ GND

NOTE A: CL includes probe and jig capacitance.

FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

TEXAS

~

INSTRUMENTS
2-44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-Vec

I

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

Vce

ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR

LINEARITY ERROR
vs
REFERENCE VOLTAGE

vs

REFERENCE VOLTAGE
16

Vii
1(+)

1.5

'0\'

="~/'
1(-) 1=

1

1

VCC='5V
fclock = 250 kHz
1.25 t-TA = 25°C

14
12
CD
~

CD

en
..J

10

I

e

w
Q;
~
....

0

1.0

I

~
Ui 0.75

8

'E'"

6

.~

\

2

0.5

..J

l',.

4

0.25

f',
t--

o
0.01

o

0.1

10

o

2
3
4
V ref-Reference Voltage-V

Vref-Reference Voltage-V

FIGURE 5

FIGURE 4
LINEARITY ERROR

LINEARITY ERROR

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.5

I

3

I

2.5

0.45
CD

en
I

e

0.4

w
.~ 0.35

tv

"""" ""

2

I

e

~

c

Ui 1.5
~

0.3

0

/

.~

"'"

::;

-25

/
/

CD

en

..J

CD

0.25
-50

I

Vref = 5 V
VCC = 5 V

Vref = 5 V
fclock = 250 kHz

..J

25

5

CD
C

~

50

::;

""1'75

0.5

100

~

850(/ 25°C

o
o

/'

40°C

100

T A - Free-Air Temperature - °c

200

300

400

500

600

fclock - Clock Frequency - kHz
FIGURE 7

FIGURE 6

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-45

ADC0831A, ADC0832A, ADC08318, ADC08328
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
ADC0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE

ADC0831
SUPPLY CURRENT
vs
CLOCK FREQUENCY
1.5 ,-----,r------,------,------,-------,
Vcc = 5 V
TA = 25°C

1.5.---,----,----,---.----,--~

fclock = 250 kHz

CS high

-

1.0

1--11--"1===+====1=::::::::::=1
,,---~

>-

0.

Q.

c.

0::J

::J

en

'1u

I

u

0.5 i-------ji----t-----/------+--------l

u

!:]

0.5 '--__...L.-._ _- - " -_ _----'_ _ _ _-"---_ _- - " -_ _----'
- 50 -25
0
50
25
75
100
T A - Free-Air Temperature-

o

100

200

°e

FIGURE 8

FIGURE 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
VCC = 5 V


Q~

2l>
-Ic

ANALOG MUX

::an
Cl

os

Q

r-CICI
W

COM

CICI

CCI

~ I'T1

~Z

E Ul~

os

os

SAR
LOGIC
ANa

9-SH
SHIFT

os

COMPARATOR

cs

'"

CLK

EN

~
~

0>

Cl)Q

r-

-0

;,8

'"

:J:oC

r-n

m
::an
-Q
l>CCI

l>CLK

CH5

CH7

c..
iii"

---I

CH4~

-1

~

n
';1f\

C

-----------1

CH6

SARS

CI):J:o

•

CHZ

~(J)

0"

0-

TO INTERNAL

CHO
CH1 _ _ _ _ _ _

'"

cs

'
,Ir--t------

"o".r --

"

0

fE..

-fl-

•

:J:ol>
cc
n
Q
-a
m CICI
W
::a
-01::>
""tIl>
:c •
m
::al>

REF ~--------------------------,

~

Vee'

•

•

LADDER
ANa
DECODER

BITS 0-7

BITSO--7

., TO INTERNAL
CIRCUITS

7V

NOTE A: For the ADC0834, DI is input directly to the D input of SELECT 1; SELECT 0 is forced to a high.

EOC

DO

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
functional description
The ADC0834 and AOC0838 use a sample data comparator structure that converts differential analog
inputs by a successive-approximation routine. Operation of both devices is similar with the exception of.
a select enable (SE) input, an analog common input, and multiplexer addressing. The input voltage to be
converted is applied to a channel terminal and is compared to ground (single-ended). to an adjacent input
(differential), or to a common terminal (pseudo-differential) that can be an arbitrary voltage. The input
terminals are assigned a positive ( +) or negative (-) polarity. If the signal input applied to the assigned
positive terminal is less than the signal on the negative terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial data link from the
controlling processor. A serial communication format allows more functions to be included in a converter
package with no increase in size. In addition, it eliminates the transmission of low-level analog signals
by locating the converter at the analog sensor and communicating serially with the controlling processor.
This process returns noise-free digital data to the processor.
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (01) line. The multiplexer address selects the
analog inputs to be enabled and determines whether the input is single-ended or differential. When the
input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent
channel pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels
cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the AOC0838 can be used for a pseudo-differential input. In this mode, the voltage
on the common input is considered to be the negative differential input for all channel inputs. This voltage
can be any reference potential common to all channel inputs. Each channel input can then be selected
as the positive differential input. This feature is useful when all analog circuits are biased to a potential
other than ground.
A conversion is initiated by setting the chip select (CS) input low, which enables all logic circuits. The
CS input must be held low for the complete conversion process. A clock input is then received from the
processor. On each low-to-high transition of the clock input, the data on the 01 input is clocked into the
multiplexer address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment
word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and
assignment word are shifted through the shift register. When the start bit is shifted into the start location
of the multiplexer register, the input channel is selected and conversion starts. The SAR Status output
(SARS) goes high to indicate that a conversion is in progress, and the 01 input to the multiplexer shift
register is disabled the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle.
The data output DO comes out of the high-impedance state and provides a leading low for this one clock
period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive
ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater
than or less than the resistive ladder output. As the conversion proceeds, conversion data is simultaneously
output from the DO output pin, with the most significant bit (MSB) first.
After eight clock periods the conversion is complete and the SAR Status (SARS) output goes low.
The AOC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If the shift enable
(SE) line is held high on the AOC0838, the value of the least significant bit (LSB) will remain on the data
line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, the SE
control input must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When
CS goes high, all internal registers are cleared. At this time the output circuits go to the' high-impedance
state. If another conversion is desired, the CS line must make a high-to-Iow transition followed by address
information.

"!1

TEXAS
INSTRUMENTS
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2-49

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL

functional description (continued)
The 01 and DO pins can be tied together and controlled by a bidirectional processor I/O bit received on
a single wire. This is possible because the 01 input is only examined during the multiplexer addressing
interval and the DO output is still in a high-impedance state.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
sequence of operation
ADC0834

2

3

4

5

6

10

7

I
I

I.

~ t+-tsu

II

-ll

CS

1

1

+SIGN
BIT

14

15

18

19

20

21

,I

tconv

I

1

~tsu

13

1

1

ISTART

12

1

• I

-+I

11

JlJlJlfUlJlJlJU1-l1Sl

ClK

;

:S

[

5S

I

1

~

1

I I
SELECT
CH BIT

1

1
01

S5

HI-Z
SARSl

I

I

.1.

jo---MSB·FIRST DATA

1

MAX SETTLING--.I
TIME

lSB-FIRST DATA--J

~I

1

1

I
DO

I I

HI-Z

I::

MSB

7

6

I I

lSB

I

0

2

CI

2

ADC0834 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS

CHANNEL NUMBER

SGL/DIF

ODD/EVEN

SELECT BIT 1

0

1

L

L

L

+

-

L

L

H

L

H

L

-

+

L

H

H

H

L

L

H

L

H

H

H

L

H

H

H

H : ;:;: high level, L = low level, - or

-+-

3

T

-

-

+

+
+
+
+
-

polarity of s81ectcd input pin

-Ii}

TEXAS
INSTRUMENTS
2-50

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I I
MSB

6

7

HI-Z

I

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL

sequence of operation
ADC0838
15

I

~

cs

I

I

IoIf-lt su

l'
II

I

I
:

17

18

19

20

21

22

23

24

25

26

27

I

,..I
..ri'----tconv----~.~I

I

I
I

I

16

MUX

I

I

I

I

I

I

I

I

~-ADoRESSING~

~ *-tsu

11~-----~------------------------~r-

I

I
I

1

I
STARTI

BIT I

DI~

SEL

SEll

SIGN BIT 1 BIT 0

SG L ODD

[ [[

1

DIF EVEN

1

I

I
I

I

I

I

I

0

1_~~7777777n7777~7777W2TT7TiJt37777_77777777TTTTTT777==77770
I

I

I
I

,--+1------jH~-----_i

HI-Z

SARSl~______________~

:

HI-Z

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

- - _1_:-

SE

I

HELD LOW OR CONNECTED TO

~~

CS

I

~ l~-------~~---__4H~---------------------------~rI

I

I

I

MUX SETTLING":
DO

HI-Z

TIM E

~-MSB-FIRSTDATA-

14-:

I

i: I

MSB [

I

I

[;

;f---.-[--,-,-'[
L~-'-B[ ---'------'--'-----'-----'----'[M------1SBi

HI-Z

~

7

-----~i~

--¥------LSB-FIRSTDATA----.~,

SE

USED TO CONTROL LSB FIRST DATA

---------~I~I----~i~------------,
I

~

~------------~I

1

MUX

1

SETTLING~
TIME

I

r4--MSB-FIRST DATA-_ _ _ _ LSB-HELD-----l....
_ - - ---'LSB-FIRST DATA-

14-1

---~

:

DO---~.--L-i

-----\I[::S--"----'----"-I_ _
LSB~_---L-'-----"-___'____L_...J....__'___[

MS--,-B
[

MS--,-B'[- - - - - 1

4

"'!1

TEXAS
INSTRUMENTS
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2-51

ADC0834A. ADC0838A. ADC0834B. ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
ADC0838 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADORESS

SELECTED CHANNEL NUMBER
SELECT

SGL/DIF

ODD/EVEN

L

L

L

L

L

L

H

L

L

L

H

H

L

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

H

L

L

L

H

L

L

H

H

L

H

L

H

L

H

H

H

H

L

L

H

H

L

H

H

H

H

L

H

H

H

H

0

0

L

L

+

L

H

1

1

0

-

1
-

2

2

3

+

-

COM

3

4

5

+

-

6

7

+

-

-

+

+
-

+
+

-

+

-

+
+

-

+

-

+

-

+

-

+

-

-

-

H = high level, L = low level, - or + = polarity of selected input

absolute maximum ratings over recommended operating free-air temperature range (unless otherwise
noted)
Supply voltage, VCC (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range: Logic................. ........
. . . . . . . . . .. - 0.3 V to 15 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V
Input current: V + input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 5 mA
Any other input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 5 mA
Total input current for package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Operating free-air temperature range: AI and BI suffixes .................... - 40°C to 85 °C
AC and BC suffixes. . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260°C
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Internal zener diodes are connected from the Vee input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to Vee through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
Vee input (6.4 VI is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.

-1!1

TEXAS
INSTRUMENTS
2-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
recommended operating conditions
VCC

Supply voltage

VIH

High-level input voltage

VIL

Low-level input voltage

fclock

Clock frequency
Clock duty cycle (see Note 3)

MIN

NOM

MAX

4.5

5

6.3

V

0.8

V

10

400

kHz

40

60

2

UNIT
V

%

Pulse duration, CS high

220

ns

tsu

Setup time, CS low, SE low, or data valid before clockl

350

ns

th

Hold time, data valid after clockl

twH(CS)

TA

Operating free-air temperature

90
IAI and BI suffixes

IAC

and BC suffixes

ns

-40

85

0

70

°C

NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 MS.

electrical characteristics over recommended range of operating free-air temperature,
Vee = V + = 5 V, fclock = 250 kHz (unless otherwise noted)
digital section
MIN

VCC

~

4.75 V,

10H ~ - 360

VCC

~

4.75 V,

10H ~ -10

~

5.25 V,

10L

~A

2.8

VOL

VCC

IIH

High-level input current

VIH ~ 5 V

IlL

Low-level input current

VIL ~

10H

High-level output (source) current

VOH ~ 0,

TA

~

25°C

-6.5
8

10Z

MIN
4.6

Low-level output voltage

10L

MAX

2.4

High-level output voltage

~A

TYP~

4.5

VOH

~

AC, BC SUFFIX

AI, BI SUFFIX

TEST CONDITIONSt

PARAMETER

TYP~

0.005
-0.005

a

0.005
-0.005

1
-1

-14

-6.5
8

1
-1

-14

V
~A
~A

mA

16

mA

Low-level output (sink) current

VOL ~ VCC,

TA

~

25°C

High-impedance-state output

Vo

~

5 V,

TA

~

25°C

0.01

3

0.01

3

current (DO or SARS)

Vo

~

0,

TA

~

25°C

-0.01

-3

-0.01

-3

16

UNIT
V

0.34

0.4

1.6 mA

MAX

~A

Ci

Input capacitance

5

5

pF

Co

Output capacitance

5

5

pF

t All parameters are measured under open-loop conditions with zero common-mode input voltage {unless otherwise specified).
tAil typical values are at VCC ~ V + ~ 5 V, TA ~ 25°C.

"'!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-53

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL

electrical characteristics over recommended range of operating free-air temperature,
= V + = 5 V, fclock = 250 kHz (unless otherwise noted)

Vee

analog and converter section
TEST CONDITIONSt

PARAMETER

See Note 4

Common-mode input voltage range

VICR

MIN
-0.05

TYP~

MAX

UNIT

to

V

VCC+ 0.05
On-channel
II(stdbyl

rilrefl

VI - 5 V at on-channel,
a at off-channel
VI

Standby input current

Off-channel

(see Note 51

On-channel

VI

~

Off-channel

VI

~

1
-1

~

o

1
1.3

Input resistance to reference ladder

~A

-1

at on-channel,

5 V at off-channel
2.4

5.9

kll

total device
PARAMETER

TEST CONDITIONSt

Vz

Internal zener diode breakdown voltage

ICC

Supply current

11= 15mAatV+ pin,
See Note 2

MIN

TYP~

MAX

6.3

7

8.5

V

1

2.5

mA

UNIT

t All parameters are measured under open-loop conditions with zero common-mode input voltage.
~AII typical values are at VCC = 5 V, V+ = 5 V, TA = 25°C_
NOTES: 2. Internal zener diodes are connected from the VCC input to ground and from the V + input to ground_ The breakdown voltage
of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
VCC input (6.4 VI is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
4. If channel IN - is more positive than channel IN +, the digital output code will be 0000 0000. Connected to each analog input
are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken
during testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures,
cause this input diode to conduct and cause errors for analog inputs that are near full-scale. As long as the analog voltage
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute V to 5
V input voltage range requires a minimum VCC of 4.950 V for all variations of temperature and load.
5. Standby input currents are currents going into or out of the on or off channels when the AID converter is not performing conversion
and the clock is in a high or low steady-state condition.

a

TEXAS

~

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC0834A. ADC0838A. ADC0834B. ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL

Vee

operating characteristics V +
otherwise noted)

Common-mode error
Change in zero-error from

tdis

±1/16

± 114

Differential mode

± 1/16

±1/4

II

= 5 V to internal zener

= 15 rnA at V + pin,
= 5 V, Vee open

Propagation delay time, MSB-first data
output data after eLK!
(see Note 7)
LSB-flrst data

eL

Output disable time,

eL

DO or SARS after eSl

eL

.

MIN

MAX

± 1/16

±1/4

LSB

±1

LSB

± 1/16

±1/4

LSB

1

LSB

1

= 100 pF

UNIT

TVP

± 1/2

Vref

diode operation (see !lliote 2)

I
I

= 4.75 V to 5.25 V
= 5 V.
TA = MIN to MAX
Vref

Total unadjusted error (see Note 6)

tpd

MAX

Vee

Supply-voltage variation error

AI. AC SUFFIX

TVP

MIN

°e (unless

20 ns. T A = 25

tf

BI. BC SUFFIX

TEST CONDITIONSt

PARAMETER

Vee

250 kHz. tr

5 V. fclock

650

1500

650

1500

250

600

250

600

125

250

125

250

ns

= 10 pF, RL = 10 k!l
= 100 pF, RL = 2 k!l

Conversion time (multiplexer
teenv addressing time not included)

500

500

8

8

ns
clock
periods

t All parameters are measured under open-I<;o0p conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,
use the appropriate value specified under recommended operating conditions.

NOTES: 2. Internal zener diodes are connected from the Vee input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to Vee through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
Vee input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow
for comparator response time.

PARAMETER MEASUREMENT INFORMATION

eLK

___.I'

-+l

GND

I

I+- tsu

-c\ : - : - - -

es 0.4

V\:

14- tsu

--t-:--I

I

---Vce

I

I I

GND

I I4-*--- th
I -+I
I
I
--"'\ I

_---Vee

I

DATA IN
(DI)

-.I

I

2 V

\

I

FIGURE 1. DATA INPUT TIMING

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-55

ADC0834A, ADC0838A, ADC08348, ADC08388
AID PERIPHERALS WITH SERIAL CONTROL
PARAMETER MEASUREMENT INFORMATION

GND
14---I.*-I-'tpd

~- - - -

DATA
OUT 100)

I+-I~lt:=vcc

tpd-+j
-

-

----

I

;"\50"10

,-..50"10

I \ ' - GND

- - - J

--+I

tsu

14--

SE------------'-""'\"O~

-

-

-

VCC

\,,·----GND

FIGURE 2. DATA OUTPUT TIMING

TEST
POINT
FROM
OUTPUT
UNDER
TEST

1

J

~ ~
CL
ISee Note A)

LOAD CIRCUIT
-.(

.... t r

I I

CS

~9""'0%""o- -

r-::9""0%""O- - - VCC

~

---""

I

!P~ ____ GND

GND

~tdiS

~td.jS

DO AND
SARS OUTPUT

S10pen
S2 closed

90%
GND

DO AND
SARSOUTPUT

VOLTAGE WAVEFORMS

S1 closed
S2 open

I
I

_1'!!y'!... _

VOLTAGE WAVEFORMS

NOTE A: CL includes probe and Jig capacitance,

FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS

TEXAS ' "
INSTRUMENTS
2-56

VCC

50%

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-Vcc
GND

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR

LINEARITY ERROR

vs

vs

REFERENCE VOLTAGE

REFERENCE VOLTAGE
1.5

16
:- VI(+1 = VI(-l = 0 V

fclock = 250 kHz
1.25 r-TA=25°C

14
12

/Xl

!j

/Xl

II)

..J

10

~

8

...~

1.0

I

e

I

w

I

VCC=15 V

w0.75

~
.;:

'"

6

.~

0
==

1\

4

\.

2

o

"-..

r-...

0.25

-

0.1
1.0
Vref-Reference Voltage-V

0.01

0.5

..J

o

10

o

2

FIGURE 4

LINEARITY ERROR

vs

vs

FREE·AIR TEMPERATURE

CLOCK FREQUENCY

I

3

L

V re f=5V
fclock = 250 kHz
0.45
/Xl

II)

..J

gI 0.4
w
~
.~ 0.35

"-

"-""'-

'"c

::i
0.3

0.25
-50

-25

o

I
Vref= 5 V
VCC = 5 V

2.5

el

/

2

..J

I

I

e

'" '"
25

5

FIGURE 5

LINEARITY ERROR

0.5

4

3

Vref-Reference Voltage-V

w1.5

II

oE
'"'c"

........

50

I

::i

"~

0.5

~

75

/

100

o
o

85°c/ ~
L

-40 o C

--=-

-

100

200

300

400

500

600

fclock - Clock Frequency··· kHz

T A-Free·Air Temperature-°c

FIGURE 6

FIGURE 7

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-57

ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
SUPPLY CUR RENT

SUPPLY CURRENT

vs

vs

FREE·AIR TEMPERATURE
1.5

"

E

...I

c;. 1.0
C.
::J

en
I

,

0.5
-50

Vee = 5 V
TA = 25°e

v.

«

~C"'S.S",

I
"-.... ~ v.CC"'S

tJ
tJ

1.5

fclock = 250 kH~
es= HIGH

~

"f:!

;;

C.

J

I

«

CLOCK FREQUENCY

----

~ I--I

It.
CC"'4S
---.:::... . II

E

...I
f:!"
;;

o

L..--"

tJ

>

C.

-

--=-

-25

1.0

C.
::J

en
I

---

0.5

tJ

~

-

0
50

25

75

100

0

100

T A - Free·Air Temperature - °e

200

FIGURE 8

FIGURE 9

OUTPUT CURRENT

vs
FREE·AIR TEMPERATURE
25

«

E
I

~

:;

20

Vee = 5 V

101 (II

~r---.
-I

II)

f- 01-/ (1/
-...:.:.
01-/ "'0
II)
15

~

tJ

r-- ::::-r-

-S

%10 f-~OH (VO H '" 2.4 VI

o
I

o

-..!..Ol (VOL
5

o
-50

-25

~ 0.4 VI

o

25

50

rt75

T A - Free·Air Temperature - °e
FIGURE 10

TEXAS

~

INSTRUMENTS
2-58

300

400

f clock - elock Frequency - kHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

100

500

ICL7135C. TLC7135C
Advanced LinCMOSTM 4 1/2-DIGIT PRECISION
ANALOG-TO-DlGlTAL CONVERTERS
02851, DECEMBER 1986-REVISED MARCH 1988

N PACKAGE

•

Advanced LinCMOS'" Technology

•

Zero Reading for O-V Input

•

Precision Null Detection with True Polarity
at Zero

(TOP VIEW)

•

1-pA Typical Input Current

•

True Differential Input

UNDER-RANGE
OVER-RANGE
STROBE
RUN/HOLD
DGTl GND
POLARITY

2
3
4

ClK
BUSY
D1 (lSDI
D2
D3
D4
B8 (MSBI
B4

Crel-

•

Multiplexed Binary-Coded-Decimal Output

•

Low Rollover Error:

•

Control Signals Allow Interfacing with
UARTs or Microprocessors

•

Autoranging Capability with Over- and
Under-Range Signals

±1

VCCREF
ANlG COMMON
INT OUT
AUTO ZERO
BUFF OUT

Cref+
ININ+

Count Maximum

VCC+
(MSD) D5
(lSBI B1
B2

FN PACKAGE
(TOP VIEW)

•

TTL-Compatible Outputs

•

Direct Replacement for Teledyne TSC7135,
IntersillCL7135, Maxim ICL7135, and
Siliconix Si7135

description
The ICL7135C and TLC7135C converters are
manufactured with Texas Instruments highly
efficient Advanced LinCMOS'" technology, This
4 1/2-digit dual-slope-integrating analog-todigital converter is designed to provide interfaces
to both a microprocessor and a visual display,
The digit-drive outputs 01 through 04 and
multiplexed binary-coded-decimal outputs, B1
through B4, provide an interface for LED or LCD
decoder/drivers as well as microprocessors.

4 3 2 1 282726
25
24
23
22
21
9
20
10
19
11
12131415161718

AUTO ZERO
BUFF OUT

5
6

Cref -

Crel +

ININ +
VCC+

The ICL7135C and TLC7135C offer 50-ppm
(one part in 20,000) resolution with a maximum
linearity error of one count. The zero error is less
than 10 p.V and zero drift is less than 0.5 p.V/oC.
Source-impedance errors are minimized by low
input current (less than 10 pA). Rollover error is
limited to ± 1 count.

AVAILABLE OPTIONS t
SYMBOLIZATION
DEVICE

PACKAGE

OPERATING
TEMPERATURE

SUFFIX

RANGE

ICL7135C

FN, N

O°C to 70°C

TLC7135C

FN, N

OOCto 70°C

The BUSY, STROBE, RUN/HOLD, OVER-RANGE,
and UNDER-RANGE control signals support
microprocessor-based measurement systems.
The control signals also can support remote data acquisition systems with data transfer via universal
asynchronous receiver transmitters (UARTs).
t In many instances, these ICs may have
ICL71 35C and TLC7135C symbolization on the
package.

The ICL7135C and TLC7135C are characterized for operation from OOC to 70°C,

Caution. This device has limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage.
Advanced

LinCMOS~

is a trademark of Texas Instruments Incorporated.
Copyright © 1986, Texas Instruments Incorporated

PRODUCTION DATA documents contain information

current as of publication datB. Products conform to

specifications pef the terms of Taxas Instrumants

standard warranty. Production procassing dolS not
necessarily include testing of .11 parameters.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-59

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·DIGIT PRECISION
ANALOG· TO·DIGITAL CONVERTERS
functional block diagram
POLARITY 1231

POLARITY
FLIP-FLOP

FROM ANALOG
SECTION

1201 D1 ILSD}
1191 D2
DIGIT

LATCH

1181 D3

. DRIVE

1171 D4

OUTPUT

1121 D5 IMSDI

ZERO
CROSS
DETECT

LATCH

CLK~12~2~1____________;

_ _ 1251
RUN/HOLD ' - ' - - - - - - ' - - - - - - ( CONTROL
OVER-RANGE 1271

MULTIPLEXER

COUNTERS

LOGIC

1- - - -......- - - - - - ;
UNDER_RANGE.:.;12:..:8c_ _ 1261

LATCH

STROBE~~--~~-----;

BUSy.:.;12~1c-1____......______;

DGTLGND~12~4,,-1------------~
LATCH

LATCH

1131 B1 ILSBI}
1141
BINARY
B2
CODED
1151 B4
DECIMAL
1161 B8 IMSBI

OUTPUT

ANALOG SECTION

C re!
181

rI
I

~f.!...

_

_

c:._

(71

A/Z

REF~--"
I
I

AIZ

A/Z

ANLG~13~1~+-

______

~

INPUT
LOW

___________

COMMON

l iNT
L _______ _

IN-~_ _ _ _ _ _ _~_ _ _ _ _ _ _ _~

___________ ...J

TEXAS ..J..!}
INSTRUMENTS
2-60

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2-DIGIT PRECISION
ANALOG-TO-DlGlTAL CONVERTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (Vee + with respect to Vee _) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Analog input voltage (pin 9 or pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee - to Vee +
Reference voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee - to Vee +
elock input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to Vee +
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260 0 e
ease temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e

recommended operating conditions
MIN

NOM

MAX

Supply voltage, vCC +

4

6

V

Supply voltage, VCC-

-3

5
-5

-8

V

1

Reference voltage, Vref
High-level input voltage, ClK, RUN/HOLD, VIH

V

2.8

V
0.8

low-level input voltage, ClK, RUN/HOLD, Vil
Differential input voltage, VID

NOTE 1: Clock frequency range extends down to

electrical characteristics, Vee +
(unless otherwise noted)

= 5 V, VCC-

VOL

output voltage

low-level output voltage
Peak-to-peak output noise voltage
(see Note 21

10
10
10

=
=
=

of output voltage

-10

~A

°C

=

Full Scale

VID

=

0,

O°C:5 TA:5 70°C

=
=

High-level input current

VI

Low-level input current

VI

II

Input leakage current. pins 9 and 10

VID

ICC+

Positive supply current

fclock

5 V,

a V,
=a
=
=

a
a

ICC-

Negative supply current

fclock

Cod

Power dissipation capacitance

See Note 3

MAX

5

4.9

5
0.4

0,

IIH

TYP

2.4

1.6 mA

=

III

NOTES:

MIN

-1 mA

VID

Zero-reading temperature coefficient

DiVO

70

- 5 V, Vref = 1 V, fclock = 120 kHz, TA
TEST CONDITIONS

I Dl-D5,Bl,B2,B4,B8
I Other outputs

V
MHz

a Hz.

PARAMETER
VOH

2

a

Operating free-air temperature range. T A

V

VCC+ -0.5

VCC- +1
1.2

Maximum operating frequency, fclock (see Note 11

High-level

UNIT

O°C :5 TA :5 70°C

a °c
TA

:5 T A :5 70 °C

=

0.5

=
=

~A

mA

10
250
2
3

-0.8

25°C

~V/oC

10

O°C :5 TA :5 70°C
TA

2

-0.1

1

25°C

V

0.1

O°C :5 TA :5 70°C
TA

V

-0.02
1

25°C

UNIT

~V

15

2 V

= 25°C

-2
-3

ooc :5 TA :5 70°C
40

pA
mA
mA
pF

2. This is the peak-to-peak value that is not exceeded 95% of the time.

3. Factor relating· clock-frequency to increase in supply current. At VCC +

5 V

ICC + = ICC + (fclock = 01 + Cpd x 5 V x fclock

~

TEXAS
INSTRUMENTS
POST OFF!CE BOX 655303 • DALLAS, TEXAS 75265

2-61

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1J2·DlGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
operating characteristics, VCC+ = 5 V, VCCT A = 25 DC (unless otherwise noted)
PARAMETER

TEST CONDITIONS

Full-scale temperature coefficient

"FS

VID ~ 2 V,

{see Note 41

1 V, fclock
MIN

120 kHz,
TYP

-2V:5 VID :5 2 V

0.5

Differential linearity error (see Note 5)

-2V:5 VID :5 2 V

0.01

± Full-scale symmetry error (see Note 6)

VID

Display reading with

a-v

input

VID

Display reading in ratiometric operation

~

~

±2 V
0,

0.5
ODe :5 TA :5 70 De

VID ~ V re !' TA ~ 25 De
ODe :5 TA :5 70 De

... 0.9998 +0.9999

T

UNIT

5

ppm/DC

1

count
LSB

1

count

-0.0000 ± 0.0000 + 0.0000
1.0000

+0.9995 +0.9999 + 1.0005

Digital
Reading
Digital
Reading

4. This parameter is measured with an external reference having a temperature coefficient of less than 0.01 ppm/DC.

5. The magnitude of the difference between the worst case step of adjacent counts and the ideal step.
6. Rollover error is the difference between the absolute values of the conversion for 2 V and - 2 V.

~

TEXAS
INSTRUMENTS
2-62

MAX

ODe :5 TA :5 70 De

Linearity error

(rollover error)

NOTES:

- 5 V, Vref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

.

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·0IG1T PRECISION
ANALOG·TO·DIGITAL CONVERTERS
timing diagrams
~

BUSyt

~J~<--------------------------------------

B1-BB

D5

END DF CDNVERSION

D5

-.J

D4

D2

D1

D5

201

200

--l4141---tot~

COUNTS

COUNTS

I

I

---t~ot-I

14-14

D4

D3

L

r

__~~--------------------~

---w~
200
j4

~I

~____~

COUNTS
D3

200
COUNTS
D2

\4

.,

~____,

------------------~
200 -l414---.t~
COUNTS

~____,

D1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~1

I

C~~~TS -+14t-----+t~
t Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input.

FIGURE 1
DIGIT SCAN"
,..,
,..,
D5
FOR OVER-RANGE I ' - - - - - - ' L--.....J L - -

~D4
~D3

~D2

____~rl~____~rl~____ D1
I..

1000

~I

COUNTS

FIGURE 2

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-63

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·0IGIT PRECISION
ANALOG· TO· DIGITAL CONVERTERS
timing diagrams (continued)

INTEGRATOR
OUTPUT

AUTOZERO
10,001
COUNTS

SIGNAL
INT,
10,000
COUNTS

DE-INTEGRATE
20,001
COUNTS MAX,

I+--- FULL MEASUREMENT CYCLE

~I

40,002 COUNTS
BUSY

OVER-RANGE ~
WHEN APPLICABLE

UNDER-RANGE ~
WHEN APPUCABLE .I.~"""""""""""--

_________~
FIGURE 3

STROBEl

I II I

r-AUTO ZERO
DIGIT SCAN
FOR OVER-RANGE

SIGNAL INTEGRATE+!4-DE-INTEGRATEt

na..;.;;.,...------"-1I.f-'- - - - - 'n,----,'n ' - - 05 t

~~D4_______________~h~,______~~n

~_D3________~:.~{______~~n
n~D2____________~'f-______~___~n
,1

-----I L

tFirst 05 of AUTO ZERO and DE-INTEGRATE is one count longe"

FIGURE 4

"11

TEXAS
INSTRUMENTS
2-64

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

rL-~

nL

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·DIGIT PRECISION
ANALOG·TO·DlGITAL CONVERTERS
PRINCIPLES OF OPERATION
A measurement cycle for the ICL 7135C and TLC7135C consists of the following four phases.
1.

Auto·Zero Phase. The internal IN + and IN - inputs are disconnected from the pins and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset
voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only
by the system noise, and the overall offset, as referred to the input, is less than 10 p.V.

2.

Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN - inputs are
connected to the external pins. The differential voltage between these inputs is integrated for a fixed
period of time. If the input signal has no return with respect to the converter power supply, INcan be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion
of this phase, the polarity of the input signal is recorded.

3.

De-integrate Phase. The reference is used to perform the de-integrate task. The internal IN - is
internally connected to ANLG COMMON and IN + is connected across the previously charged reference
capacitor. The recorded polarity of the input signal is used to ensure that the capacitor will be connected
with the correct polarity so that the integrator output polarity will return to zero. The time, which
is required for the output to return to zero, is proportional to the amplitude of the input signal. The
return time is displayed as a digital reading and is determined by the equation 10,000 x (VID/Vref).
The maximum or full-scale conversion occurs when VIO is two times Vref.

4.

Zero Integrator Phase. The internal IN - is connected to ANLG COMMON. The system is configured
in a closed loop to cause the integrator output to return to zero. Typically this phase requires 100
to 200 clock pulses. However, after an over-range conversion, 6200 pulses are required.

description of analog circuits
input signal range
The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below
the positive supply. Within this range, the common mode rejection ratio (CMRR) is typically 86 dB. Both
differential and common mode voltages cause the integrator output to swing. Therefore, care must be
exercised to assure the integrator output does not saturate.
analog common
Analog common (ANLG COMMON) is connected to the internal IN - during the auto-zero, de-integrate,
and zero integrator phases. If IN - is connected to a voltage which is different than analog common during
the signal integrate phase, the resulting common mode voltage will be rejected by the amplifier. However,
in most applications, IN LO will be set at a known fixed voltage (power supply common for instance).
In this application, analog common should be tied to the same point, thus removing the common mode
voltage from the converter. Removing the common mode voltage in this manner will slightly increase
conversion accuracy.
reference
The reference voltage is positive with respect to analog common. The accuracy of the conversion result
is dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high
quality reference should be used.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-65

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·01GIT PRECISION
ANALOG·TO·DlGITAL CONVERTERS
description of digital circuits
RUN/HOLD input
When the RUN/HOLD input is high or open, the device will continuously perform measurement cycles every
40,002 clock pulses. If this input is taken low, the IC will continue to perform the ongoing measurement
cycle and then hold the conversion reading for as long as the pin is held low. If the pin is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) will initiate a new
measurement cycle. If this positive pulse occurs before the completion of a measurement cycle, it will
not be recognized. The first STROBE pulse, which occurs 101 counts after the end of a measurement
cycle, is an indication of the completion of a measurement cycle. Thus, the positive pulse could be used
to trigger the start of a new measurment after the first STROBE pulse.
STROBE input
Negative going pulses from this input are used to transfer the BCD conversion data to external latches,
UARTS, or microprocesors. At the end of the measurement cycle, the digit-drive (D5) input goes high and
remains high for 201 counts. The most significant digit (MSD) BCD bits are placed on the BCD pins. After
the first 101 counts, halfway through the duration of output D1-D5 going high, the STROBE pin goes low
for 1/2 clock pulse width. The placement of the STROBE pulse at the midpoint of the 05 high pulse allows
the information to be latched into an external device on either a low-level or an edge. Such placement
of the STROBE pulse also ensures that the BCD bits for the second MSD will not yet be competing for
the BCD lines and latching of the correct bits is assured. The above process is repeated for the second
MSD and the D4 output. Similarly, the process is repeated through the least significant digit (LSD).
Subsequently, inputs D5 through D1 and the BCD lines will continue scanning without the inclusion of
STROBE pulses. This subsequent continuous scanning causes the conversion results to be continuously
displayed. Such subsequent scanning does not occur when an over-range condition occurs.
BUSY output
The BUSY output goes high at the beginning of the signal integrate phase and remains high until the first
clock pulse after zero-crossing or at the end of the measurement cycle if an over-range condition occurs.
It is possible to use the BUSY pin to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number
of clock pulses, which occur during the de-integrate phase. The conversion result can be obtained by
subtracting 10,001 from the total number of clock pulses.
OVER·RANGE output
When an over-range condition occurs, this pin goes high after the BUSY signal goes low at the end of
the measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement
cycle when an over-range condition occurs. The OVER-RANGE output goes high at end of BUSY and goes
low at the beginning of the de-integrate phase in the next measurement cycle.
UNDER-RANGE output
At the end of the BUSY signal, this pin goes high if the conversion result is less than or equal to 9% (count
of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.

TEXAS •
INSTRUMENTS
2-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·DIGIT PRECISION
ANALOG·TO·DlGlTAL CONVERTERS
PRINCIPLES OF OPERATION
POLARITY output
The POLARITY output is high for a positive input signal and is updated at the beginning of each de-integrate
phase. The polarity output is valid for all inputs including ± a and over-range signals.
digit·drive (05, 04, 02 and 01) outputs
Each digit-drive output (01 through 05) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit drive outputs are
blanked from the end of the strobe sequence until the beginning of the de-integrate phase (when the
sequential digit drive activation begins again). The blanking activity, during an over-range condition, may
be used to cause the display to flash and indicate the over-range condition.
BCD outputs
The BCD bits (B8, B4, B2 and B1) for a given digit are sequentially activated on these outputs.
Simultaneously, the appropriate Digit-drive line for the given digit is activated.

system aspects
integrating resistor
The value of the integrating resistor (RINT) is determined by the full scale input voltage and the output
current of the integrating amplifier. The integrating amplifier can supply 20 /LA of current with negligible
non-linearity. The equation for determining the value of this resistor is as follows:
R
_
INT -

FULL-SCALE VOLTAGE
liNT

Integrating amplifier current, liNT, from 5 to 40 /LA will yield good results. However, the nominal and
recommended current is 20 /LA.
integrating capacitor
The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages.
If the amplifier output is within 0.3 V of either supply, saturation will occur. With ± 5-V supplies and ANLG
COMMON connected to ground, the designer should design for a ±3.5-V to ±4-V integrating amplifier
swing. A nominal capacitor value is 0.47 /LF. The equation for determining the value of the integrating
capacitor (CINT) is as follows:
10,000 x CLOCK PERIOD x liNT
CINT = INTEGRATOR OUTPUT VOLTAGE SWING
where: liNT is nominally 20 /LA.
Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A
capacitor, which is too small could cause the integrating amplifier to saturate. High dielectric absorption
causes the effective capacitor value to be different during the signal integrate and de-integrate phases.
Polypropylene capacitors have very low dielectric absorption. Polystyrene and Polycarbonate capacitors
have higher dielectric absorption, but also work well.

-Ij}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-67

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·OIGIT PRECISION
ANALOG· TO·OIGIT AL CONVERTERS
PRINCIPLES OF OPERATION
auto-zero and reference capacitor
Large capacitors will tend to reduce noise in the system. Dielectric absorption is unimportant except during
power-up or overload recovery. Typical values are 1 ~F.
reference voltage
For high-accuracy absolute measurements, a high quality reference should be used.
rollover resistor and diode
The ICL7135C and TLC7135C have a small rollover error, however it can be corrected. The correction
is to connect the cathode of any silicon diode to the INT OUT pin and the anode to a resistor. The other
end of the resistor is connected to ANLG COMMON or ground. For the recommended operating conditions
the resistor value is 100 kO. This value may be changed to correct any rollover error which has not been
corrected. In many non-critical applications, the resistor and diode are not needed.
maximum clock frequency
For most dual-slope AID converters, the maximum conversion rate is limited by the frequency response
of the comparator. In this circuit, the comparator follows the integrator ramp with a 3 ~s delay. Therefore,
with a 160-kHz clock frequency (6 ~s period), half of the first reference integrate clock period is lost in
delay. Hence, the meter reading will change from 0 to 1 with a 50-~V input, 1 to 2 with a 150-~V input,
2 to 3 with a 250-~V input, etc. This transition at midpoint is desirable; however, if the clock frequency
is increased appreciably above 160 kHz, the instrument will flash "1" on noise peaks even when the input
is shorted. The above transition points assume a 2-V input range is equivalent to 20,000 clock cycles.
If the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since non-linearity and noise do not increase substantially with frequency. For a fixed clock
frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted
out digitally.
For signals with both polarities, the clock frequency can be extended above 160 kHz without error by
using a low value resistor in series with the integrating capacitor. This resistor causes the integrator to
jump slightly towards the zero-crossing level at the beginning of the de-integrate phase and thus,
compensates for the comparator delay. This series resistor should be 100 to 50 O. This approach allows
clock frequencies up to 480 kHz.
minimum clock frequency
The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference
capacitors. Measurement cycles as high as 10 s are not influenced by leakage error.
rejection of 50 Hz or 60 Hz pickup
To maximize the rejection of 50 Hz or 60 Hz pickup, the clock frequency should be chosen so that an
integral multiple of 50 Hz or 60 Hz periods occur during the signal integrate phase. To achieve rejection
of these signals, some clock frequencies which could be used are as follows:
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.

-I!}

TEXAS
INSTRUMENTS
2-68

POST OFFICE BOX 655303

4

DALLAS, TEXAS 75265

ICL7135C, TLC7135C
Advanced LinCMOSTM 4 1/2·DlGIT PRECISION
ANALOG· TO· DIGITAL CONVERTERS
PRINCIPLES OF OPERATION
zero·crossing flip·flop
This flip-flop interrogates the comparator's zero-crossing status. The interrogation is performed after the
previous clock cycle and the positive half of the ongoing clock cycle have occurred so that any comparator
transients which result from the clock pulses do not affect the detection of a zero-crossing. This procedure
delays the zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by
this delay, the counter is disabled for one clock cycle at the beginning of the de-integrate phase. Therefore,
when the zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct
number of counts is displayed.
noise
The peak-to-peak noise around zero is approximately 15 J.tV (peak-to-peak value not exceeded 95% of
the time). Near full scale, this value increases to approximately 30 JlV. Much of the noise originates in
the auto-zero loop, and is proportional to the ratio of the input signal to the reference.
analog and digital grounds
For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must
not be sent to the analog ground line.

power supplies
The ICL 7135C and TLC7135C are designed to work with ± 5-V power supplies. However, 5-V operation
is possible if the input signal does not vary more than ± 1.5 V from mid-supply.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-69

2-70

n0808, n0809
LOW· POWER CMOS ANALOG·TO·DlGITAL CONVERTERS
WITH 8·CHANNEL MULTIPLEXERS
D2642, FEBRUARY 1986-REVISED MAY 1988

•

Total Unadjusted Error ... ± 0.75 lSB Max
for Tl0808 and ± 1.25 lSB Max for
Tl0809 Over Temperature Range

•

Ideal for Battery Operated, Portable
Instrumentation Applications

•

Resolution of 8 Bits
100,.s Conversion Time

•

Ratiometric Conversion

•

Monotonic Over the Entire AID Conversion
Range
No Missing Codes

•

Easy Interface with Microprocessors

•

latched 3-State Outputs

•

latched Address Inputs

•

Single 2.75-V to 5.5-V Supply

(TOP VIEW)

~}INPUTS

'''",{

•

•

N DUAL-IN-LiNE PACKAGE

~}ADDRESS

START
EDe
2- 5
DE
elK

ALE
2 -1 (MSB)
2-2
2- 3
2- 4

Vee
REF+
GND
2- 7

2 - 8 IlSBI
REF 2- 6

FN PACKAGE
(TOP VIEW)
tOLDo:;tMN

0

I- I- I- I- I- I- I:::J:J::J::J::J:J::J

•

Extremely low Power
Consumption ... 0.3 mW Typ

•

Improved Direct Replacements for
ADC0808, ADC0809

CL Q...

a..

0... CL

2

1 28 27 26

CL

0....

~~~~~zz

4

INPUT 7
START
Eoe

description

3

25
6

24

ADDRESS

23

2- 5

22

DE

21

The TL0808 and TL0809 are monolithic CMOS
elK 10
20
devices with an 8-channel multiplexer, an 8-bit
Vee 11
19
analog-to-digital (AID) converter, and
121314151617 18
microprocessor-compatible control logic. The
+ or-.... co I coo:::t
u..ZI
I l.l..(/)i
8-channel multiplexer can be controlled by a
l1.JCJNNLU....JN
a:
a: microprocessor through a 3-bit address decoder
ro
with address load to select anyone of eight
single-ended analog switches connected directly
to the comparator. The 8-bit AID converter uses
the successive-approximation conversion
technique featuring a high-impedance threshold detector, a switched-capacitor array, a sample-and-hold,
and a successive-approximation register (SAR). Detailed information on interfacing to most popular
microprocessors is readily available from the factory. These devices are designed to operate from common
microprocessor control buses, with three-state output latches driving the data bus. The devices can be
made to appear to the microprocessor as a memory location or an I/O port.
The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity,
and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR
and latched inputs to the multiplexer address decoder. The single 2.75-V to 5.5-V supply and extremely
low power requirements make the TL0808 and TL0809 especially useful for a wide variety of applications
including portable battery and LCD applications. Ratiometric conversion is made possible by access to
the reference voltage input terminals.
The TL0808 and TL0809 are characterized for operation from - 40°C to 85 °C.

Copyright © 1986, Texas Instruments Incorporated

PRODUCTION DATA documents contain information

current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~~~~:~~i~a{::1~1~ ~!:~~~ti:f :I\o::~:~:t:~~s not

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-71

TL0808. TL0809
LOW-POWER CMOS ANALOG-TO-DlGlTAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
functional block diagram (positive logic)
SAMPLE-AND-HDLD
BINARY-WEIGHTED
CAPACITORS
REF+

REF-

(12)

SWITCH
MATRIX

.--

(16)

o~

THRESHOLD
DETECTOR

~
ANALOG
INPUTS

4

~

5

~

~

-{>

~
3 J2l

I---

ANALOG
MULTIPLEXER

OUTPUT
LATCHES

OUTPUT ENABLE (DE)

TIMING
~ AND
CONTROL

EN

(6)
(9)

(25)

~
~

ADDRESS
DECODER

~
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS

H
1

C

B

A

SELECTED

ADDRESS

ANALOG

STROBE

CHANNEL

0
1

L

L

L

t

L

L

H

L

H

L

.t
t

L

H

H

t

H

L

L

H

L

H

t
t

H

H

L

t

H

H

H

t

~

~

2
3
4
5

6
7

high level, L ~ low level
low-to-high transition

TEXAS . "
INSTRUMENTS
2-72

DIGITAL
OUTPUTS

2-1 (MSBI
r!El
(7)

END OF
CONVERSION IEOCI

(10)

ADDRESS A
ADDRESSB
ADDRESSC
ADDRESS LOAD ~
ENABLE (ALE)

~ 2-4
~ 2-2

~

START CONVERSION (START)

rJ!!- 2-5
(19) 2-3

6~

CLOCK

2-8 ILSB)

~ 2-7
~ 2-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

n0808. n0809
LOW-POWER CMOS ANALOG-TO-DiGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
operating sequence

CLOCK

START
CONVERSION

50%

ADDRESS LOAD
ENABLE

50%

i

~

tw(ALC)
t-+--+-ADDRESS STABLE
I.

ADDRESS

50~50%1

::'

~~-+I----------------fl"------------------------------:

tsu-+-r-; th
ANALOG INPUT

y

I

IMULTIPLEX OUTPUT
(INTERNAL)

I

ANALOG VALUE

I

INPUT STABLE

~;

x'-________

·1

I

>C
-----+~ I~--------------~;'~----~ ---------------------ANALOG

I
ENDOF
CONVERSION
OUTPUT
ENABLE

1

I---tdIEOC)

\50%

/50%

--1 '-----------11-------------'1

Itconv---------I·j
________________________-fOf____________5_O-J%f,

-1 :- ten
LATCH OUTPUTS

\50%
~

t- tdis

___________~~~~~~:.~------------9-0~%t
~
HI·ZSTATE
10%l-l------4'~10%

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-73

n0808, n0809
lOW-POWER CMOS ANAlOG-TO-DiGITAl CONVERTERS
WITH 8-CHANNEl MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................ 6.5 V
Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 0.3 to 15 V
all other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to Vee + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 °e to 85°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 0 e
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: N package . . . . . . . . . . . . 260 0 e
NOTE 1: All voltage values are with respect to network ground terminal.

recommended operating conditions
MIN

NOM

Supply voltage, Vee

2.75

Positive reference. voltage, Vref + (see Notes 2, 3, and 4)

2.75

Negative relerence voltage, Vrel- (see Notes 2,3, and 4)

-0.1

Differential relerence voltage, V rei + - Vrel- Isee Note 4)
High-level input voltage, control inputs, VIH

0.7 Vee

UNIT

5.5

V

Vee+ 0.1

Vee
0

V
V
V
De

0.3 Vee

Operating Iree-air temperature, T A (see Note 4)

V
V

3

Low-level input voltage, control inputs, VIL

NOTES:

MAX

-40

85

2. The accuracy 01 the conversion will depend on the stability 01 the relerence voltages applied.
3. Analog voltages greater than or equal to Vrel+ convert to all highs, and all voltages less than Vrel- convert to all lows.
4. For proper operation 01 the TL0808 and TL0809 at Iree-air temperatures below oDe, Vee and (Vrel+ - Vrel-) should not
be less than 3 V.

electrical characteristics over recommended operating free-air temperature range, Vee = 3 V to 5.25 V
(unless otherwise noted)
total device
PARAMETER
VOH
VOL

TEST CONDITIONS

High-level output voltage
Low-level output voltage

10

I Data outputs
1 End of conversion

10
10

~A

MIN

Typt

MAX

~

-360

~

1.6 mA

0.45

~

1.2 mA

0.45

Vee-0.6

UNIT
V
V

Off-state (high-impedance-state)

Va ~ Vee

output current

Va

II

Control input current at maximum input voltage

VI

IlL

Low-level control input current

VI ~ a

lee

Supply current

ei

Input capacitance, control inputs

TA

~

25°e

10

15

pF

eo

Output capacitance, data outputs

TA

~

25°e

10

15

pF

102

~
~

1
-1

0
15 V

~A

-1

~A

Vee

~

3 V,

I clock ~ 640 kHz

100

500

~A

Vee

~

5 V,

Iclock ~ 640 kHz

0.3

3

mA

Resistance Irom pin 12 to pin 16

1

tTypical values are at Vee ~ 3 V and T A ~ 25 De.

TEXAS

"!1

INSTRUMENTS
2-74

~A

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1000

kO

n0808, n0809
LOW-POWER CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
analog multiplexer
TEST CONDITIONS

PARAMETER
Ion

Channel on-state current Isee Note 5)

loff

Channel off-state current

Typt

MIN

MAX

VI

~

3 V,

Iclock ~ 640 kHz

2

VI

~

0,

I clock ~ 640 kHz

-2

VCC ~ 3 V,

VI

~

3 V

TA ~ 25°C

VI

~

0

VI

~

3 V

VI

~

0

VCC ~ 3 V

10

200

-10

-200
1
-1

UNIT
p.A
nA
/LA

tTypical values are at VCC ~ 3 V and T A ~ 25°C.
NOTE 5: Channel on-state current is primarily due to the bias current into or out 01 the threshold detector, and it varies directly with clock
frequency.

timing requirements, T A
tconv
Iclock

Vref+

o (unless

3 V, Vref-

Conversion time (see Note 6)

I VCC
I VCC

Clock Irequency

otherwise noted)

MIN

NOM

MAX

90

100

116

~2.75Vt04V

10

640

~

10

1280

4 V to 5.5 V

UNIT
/LS
kHz

twlsl

Start pulse duration

200

ns

twlALCI

Address load control pulse duration

200

ns
ns

tsu

Address setup time

50

th

Address hold time

50

tdlEOCI

Delay time, end of conversion output Isee Notes 6 and 7)

operating characteristics, T A
otherwise noted)

Supply voltage
ksvS

sensitivity

3 V, Vref-

Vref+

PARAMETER

TEST CONDITIONS

MIN

VCC ~ Vref+ ~ 3 V to 5.25 V,
TA ~ -40°C to 85°C, See Note 8

Linearity error
Zero error Isee Note 10)

I TA
I TA

fclock ~

error ISee Note 11)

125 kHz

ten

Output enable time

CL ~ 50 pr, RL

tdis

Output disable time

CL

~

10 pF, RL

0, fclock

TL0808
Typt
MAX

~ 25°C

/Ls

640 kHz (unless
TL0809
Typt
MAX

UNIT

±0.05

%/V

±0.5

±1

LSB

±0.5

±0.5

±0.05

Isee Note 9)
Total unadjusted

ns
14.5

0

±0.25

~ -40°C to 85°C

±0.5

MIN

±0.5

±0.75

LSB
±1
± 1.25

LSB

~

10 kll

80

250

80

250

ns

~

10kll

105

300

105

300

ns

tTypical values for all except supply voltage sensitivity are at VCC ~ 3 V.
NOTES:
6. Refer to the operating sequence diagram.
7. For clock frequencies other than 640 kHz, tdIEOC) maximum is 8 clock periods plus 2 /LS.
8. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and Vrel + are varied together and the change in accuracy is measured with respect to full-scale.
9. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
10. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
11. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-75

noaoa, nOa09
LOW-POWER CMOS ANALOG-TO-DiGITAL CONVERTERS
WITH a-CHANNEL MULTIPLEXERS
PRINCIPLES OF OPERATION
The TL0808 and TL0809 each consists of an analog signal multiplexer, an 8-bit successive-approximation
converter, and related control and output circuitry.

multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse, Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.

converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately onehalf the Vce voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bitcounting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
Sc

THRESHOLD
DETECTOR

TO
OUTPUT
LATCHES

FIGURE 1. SIMPLIFIED MODEL OF THE SUCCESSIVE-APPROXIMATION SYSTEM

-Ij}

TEXAS
INSTRUMENTS
2-76

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL500l, TL500C, TL501l, TL501C, TL502C, TL503C
ANALOG-TO-DIGITAL-CONVERTER BUILDING BLOCKS
02477 DECEMBER 1979-REVISED JANUARY 1989

TL5001, TL500C, TL5011. TL501C
ANALOG PROCESSORS
•

True Differential Inputs

•

Automatic Zero

•

Automatic Polarity

•

High Input Impedance ... 10 9 Ohms
Typically

TL5001, TL500C CAPABILITIES

•
•

•

TL5011. TL501 C CAPABILITIES

Resolution ... 14 Bits (with TL502C)
Linearity Error . . . 0.001 %
4 1/2-Digit Readout Accuracy with External
Precision Reference

•
•
•

Resolution ... 10-13 Bits (with TL502C)
Linearity Error ... 0.01 %
3 1/2-Digit Readout Accuracy
TL502C CAPABILITIES

TL502C/TL503C
DIGITAL PROCESSORS

•
•
•
•
•
•

•
•

Fast Display Scan Rates
Internal Oscillator May Be Driven or
Free-Running

Compatible with Popular Seven-Segment
Common-Anode Displays
High-Sink-Current Segment Driver for Large
Displays
TL503C CAPABILITIES

Interdigit Blanking

•

Over-Range Blanking

•

4 1/2-Digit Display Circuitry

Multiplexed BCD Outputs
High-Sink-Current BCD Outputs

High-Sink-Current Digit Driver for Large
Displays

Caution. These devices have limited built-in gate protection. The leads should be shorted together or the
device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS
gates.

description
The TL5001, TL500C, TL5011, and TL501 C analog processors and TL502C and TL503C digital processors
provide the basic functions for a dual-slope-integrating anaJog-to-digital converter.
The TL500 and TL501 contain the necessary analog switches and decoding circuits, reference voltage
generator, buffer, integrator, and comparator. These devices may be controlled by the TL502C, TL503C,
by discrete logic, or by a software routine in a microprocessor.
The TL502C and TL503C each includes oscillator, counter, control logic, and digit enable circuits. The
TL502C provides multiplexed outputs for seven-segment displays, while the TL503C has multiplexed BCD
outputs.
When used in complementary fashion, these devices form a system that features automatic zero-offset
compensation, true differential inputs, high input impedance, and capability for 4 1/2-digit accuracy.
Applications include the conversion of analog data from high-impedance sensors of pressure, temperature,
light, moisture, and position. Analog-to-digital-Iogic conversion provides display and control signals for
weight scales, industrial controllers, thermometers, light-level indicators, and many other applications.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~~~~:~~i~ar::1~1e ~~:~~~ti:f :llo::~:~:t:~~s not

~

Copyright © 1979, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-77

TL500l. TL500C. TL5011. TL501 C. TL502C. TL503C
ANALOG·TO·OIGlTAL·CONVERTER BUILDING BLOCKS

principles of operation
The basic principle of dual-slope-integrating converters is relatively simple. A capacitor, CX, is charged
through the integrator from VCT for a fixed period of time at a rate determined by the value of the unknown
voltage input. Then the capacitor is discharged at a fixed rate (determined by the reference voltage) back
to VCT where the discharge time is measured precisely. The relationship of the charge and discharge values
are shown below (see Figure 1).

Vcx

VCT

VCT

Vref t2
VCX- - - RX Cx

Charge

(1 )

Discharge

(2)

RX Cx

Combining equations 1 and 2 results in:

(3)

Vref
where:
VCT
VCX
VI
t1
t2

= Comparator (offset) threshold voltage
= Voltage change across Cx during

t1 and during t2 (equal in magnitude)

= Average value of input voltage during t1
= Time period over which unknown voltage is integrated
= Unknown time period over which a known reference voltage is integrated.

Equation (3) illustrates the major advantages of a dual-slope converter:
a. Accuracy is not dependent on absolute values of t1 and t2, but is dependent on their ratios. Longterm clock frequency variations will not affect the accuracy.
b. Offset values, VCT, are not important.
The BCD counter in the digital processor (see Figure 2) and the control logic divide each measurement
cycle into three phases. The BCD counter changes at a rate equal to one-half the oscillator frequency.

auto· zero phase
The cycle begins at the end of the integrate-reference phase when the digital processor applies low levels
to inputs A and B of the analog processor. If the trigger input is at a high level, a free-running condition
exists and continuous conversions are made. However, if the trigger input is low, the digital processor
stops the counter at 20,000, entering a hold mode. In this mode, the processor samples the trigger input
every 4000 oscillator pulses until a high level is detected. When this occurs, the counter is started again
and is carried to completion at 30,000. The reference voltage is stored on reference capacitor Cref,
comparator offset voltage is stored on integration capacitor CX, and the sum of the buffer and integrator
offset voltages is stored on zero capacitor CZ. During the auto-zero phase, the comparator output is
characterized by an oscillation (limit cycle) of indeterminate waveform and frequency that is filtered and
d-c shifted by the level shifter.

integrate-input phase
The auto-zero phase is completed at a BCD count of 30,000, and high levels are applied to both control
inputs to initiate the integrate-input phase. The integrator charges Cx for a fixed time of 10,000 BCD counts
at a rate determined by the input voltage. Note that during this phase, the analog inputs see only the high
impedance of the noninverting operational amplifier input. Therefore, the integrator responds only to the
difference between the analog input terminals, thus providing true differential inputs.

~

TEXAS
INSTRUMENTS
2-78

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL500l. TL500C. TL5011. TL501C. TL502C. TL503C
ANALOG·TO·DIGITAL·CONVERTER BUILDING BLOCK

integrate· reference phase
At a BCD count of 39,999 + 1 = 40,000 or 0, the integrate-input phase is terminated and the integratereference phase is begun by sampling the comparator output. If the comparator output is low corresponding
to a negative average analog input voltage, the digital processor applies a low and a high to inputs A and
B, respectively, to apply the reference voltage stored on Cref to the buffer. If the comparator output is
high corresponding to a positive input, inputs A and B are made high and low, respectively, and the negative
of the stored reference voltage is applied to the buffer. In either case, the processor automatically selects
the proper logic state to cause the integrator to ramp back toward zero at a rate proportional to the reference
voltage. The time required to return to zero is measured by the counter in the digital processor. The phase
is terminated when the integrator output crosses zero and the counter contents are transferred to the
register, or when the BCD counter reaches 20,000 and the over-range indication is activated. When
activated, the over-range indication blanks all but the most significant digit and sign.
Seventeen parallel bits (4-1/2 digits) of information are strobed into the buffer register at the end of the
integration phase. Information for each digit is multiplexed out to the BCD outputs (TL503C) or the sevensegment drivers (TL502C) at a rate equal to the oscillator frequency divided by 200.
BCD COUNTER VALUES

20,000

30,000

o

20.000

,

I

I

I

'AUTO ZERO I INTEGRATE I
I INPUT
}
:

I
I

I

I

:

I
INTEGRATOR

:

OUTPUT---~

I

I

I

V(pin 11 < V(pin 21
ANALOG VOL TAGEI

I (NEGATIVE
I

I

'

I

I
I

I
I

I

I

I

I

I

I

",M"~~~

I

___

~

________

I

I

i
I

-1---'
I
I
I

I

I

I

I

I
I

i

L:____:__

L;.;B:....._~'

CONTRO:-::

I

~XX'XXXJ

~XXXXXI

i
:

I

,

TRIGGER

I

I

I

CONTROL A
I
I

I

i

I

20.000

I

I

~

: :

i

I

I

'

I

o

I

I AUTO ZERO INTEGRATE I
INTEGRATE
REFERENCE
I INPUT I
I
I
H10LD I
I
I
I
I
:
I
:
_L __ I
I
V(pin 1) > V (pin 21
(POSITIVE ANALOG VOLTAGEI
I
I
I
I
I
I
I
--f---I
I
I
I
I
I

INTEGRATE
REFERENCE

I

30.000

I

I

I

I

I

I

-----!

I
I

;J,...-..

:

~~~~,......,D'""0-,N~'T7'Cm8882t""AR7'lE~~7't""7':"7I

I

I

I
- - - - - - OV

I

I
-

I
-

-V(pin21

I
i

I
I

I

I

I

:

~---

:

,

L_____
I

I

OV(

I

(
i

I

I

ov

I
I
"

I
I
---OV

'This step is the voltage at pin 2 with respect to analog ground.

FIGURE 1. VOLTAGE WAVEFORMS AND TIMING DIAGRAM

..Ij}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-79

.~
a

ANALOG PROCESSOR
TL50D OR TL5D1

RX
BUFFER
OUTPUT

DIGITAL PROCESSOR
TL5D2C OR TL5D3C

Cx
OSCILLATOR
INPUT

INTEGRATOR
OUTPUT

:J:Io-l
2 .....
:J:IoU'l

(See Note Al

... =

r - - - - -- - -- - - -~ -V;;;;+'
I
IJ
I
i

Q=

~

r-----o

i

1:).

TRIGGER
l~::':':'~J--~.~""
Y INPUT

------,

!

(See Note BI

I

. -I

-I .....

.=
.....

QU1

~

1:).

I

--I

;:~

t;""=

n N
~p
LEVEL
SHIFTER

<-I
m .....
::I:IIU'I
-1=

CONTROL
LOGIC

Cz

mW

::I:II

z

Cref

i=

;cr;;1

~4r

c:I

I
I
I

I
I
I
I

~

~~

n

=
c:

ANALOG SWITCH
LOGIC CONTROL

I
IL _ _ _ _

I
I

fl '

-LAND DRIVERS

I __ _
L

--- ---~ GROUND
ANALOG
_J
DIGITAL

+

I

i

--ll-------J

DIGIT·ENABLE
DUTPUTS
(D1 THRU D51

COMMON

NOTE5: A. Pin 18 oJ the TL502C provides an output of fosc (oscillator frequency)
B. The trigger input assumes a high level if not externally connected.

2
I:)

I
I

CDMMON

20,000.

FIGURE 2. BLOCK DIAGRAM OF BASIC ANALOG-TO-DIGITAL CONVERTER USING TL500 OR TL501 AND TL502C OR TL503C
MODE
Auto Zero
Hold t

ANALOG
INPUT

Positive

Input

Negative

Reference
H

CONTROLS

ANALOG SWITCHES

A AND B

CLOSED

Oscillation

X

Integrate
Integrate

COMPARATOR

L

H
L
L*

X
._-

..

-

H* - -

--

L

53,54,57,59,510

H

H

51,52

L

H

53, 56, 57

H

L

- ----

53, 55, 58

High, L '" low, X .. Irrelevant

t If the trigger input is low at the beginning of the auto-zero cycle, the system will enter the hold mode. A high level (or open circuit) will signal the digital processor
to continue or resume normal operation.
* This is the state of the comparator output as determined by the polarity of the analog input during the integrate input phase.

=

I"'"

Q

n

=

TL500l, TL500C, TL501l, TL501C
ANALOG PROCESSORS
J PACKAGE
(TOP VIEWI

description of analog processors
The TL500 and TL501 analog processors are
designed to automatically compensate for
internal zero offsets, integrate a differential
voltage at the analog inputs, integrate a voltage
at the reference input in the opposite direction,
and provide an indication of zero-voltage
crossing. The external control mechanism may
be a microcomputer and software routing,
discrete logic, or a TL502C or TL503C controller.
The TL500 and TL501 are designed primarily for
simple, cost-effective, dual-slope analog-todigital converters. Both devices feature true
differential analog inputs, high input impedance,
and an internal reference-voltage source. The
TL500 provides 4-1/2-digit readout accuracy
when used with a precision external reference
voltage. The TL501 provides 1~O-ppm linearity
error and 3-1/2-digit accuracy capability. These
devices are manufactured using TI's advanced
technology to produce JFET, MOSFET, and
bipolar devices on the same chip. The TL500C
and TL501 C are characterized for operation over
the temperature range of O°C to 70°C. The
TL5001 and TL5011 are characterized for
operation from -40°C to 85°C.

ANALOG INPUT 1
ANALOG INPUT 2

}cz
VCC +
BUFFER OUTPUT
INTEGRATOR INPUT

REF OUTPUT
REF INPUT
ANALOG GND
Cref +

INTEGRA TOR OUTPUT

Cref CONTROL B INPUT

VCCDIGITAL COMMON

CONTROL A INPUT ........_ _->-' COMPARA TOR OUTPUT
DW PACKAGE
(TOP VIEWI
ANALOG INPUT i

Cz

ANALOG INPUT 2

Cz

REF OUTPUT
REF INPUT
ANALOG GND
Cref +
CrefNC
CONTROL B INPUT
CONTROL A INPUT ---""'_ _-r-

VCC +
BUFFER OUTPUT
INTEGRATOR INPUT
INTEGRATOR OUTPUT
VCCNC
DIGITAL COMMON
COMPARATOR OUTPUT

NC -- No internal connection

AVAILABLE OPTIONS
LINEARITY

TA

ERROR

O°C to 70°C
-40°C to 85°C

0.005%
0.05%
0.005%
0.05%

FS
FS
FS
FS

PACKAGE
CERAMIC DIP
WIDE-BODY SO
(J)
(OW)
TL500CJ
TL501CJ
TL500lJ
TL5011J

TL500CDW
TL501CDW
TL500lDW
TL5011DW

TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

2-81

TL500l, TL500C, TL501l, TL501C
ANALOG PROCESSORS

schematics of inputs and outputs
COMPARATOR OUTPUT

CONTROL A AND CONTROL B INPUTS

OUTPUT

DIGITAL
COMMON

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Positive supply voltage, VCC + (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 18 V
Negative supply voltage, VCC - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -18 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VCC
Comparator output voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 V to VCC +
Comparator output sink current (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Buffer, reference, or integrator output source current (see Note 2) . . . . . . . . . . . . . . . . . . . . 10 mA
Total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range: TL5001, TL5011 . . . . . . . . . . . . . . . . . . . . . . .. - 40 to .85 DC
TL500C, TL501C . . . . . . . . . . . . . . . . . . . . . . . ODC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '............ - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW package ........... 260 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 DC
NOTES: 1. Voltage values, except differential voltages, are with respect to the analog ground common pin tied together.
2. Buffer, integrator, and comparator outputs are not short-circuit protected.
DISSIPATION RATING TABLE
PACKAGE

TA:5 25°C

DERATING FACTOR

TA = 70°C

POWER RATING

POWER RATING

TA = 85°C
POWER RATING

720mW

585 mW

656 mW

533 mW

DW

1125 mW

ABOVE TA = 25°C
9 mW/oC

J

1025 mW

8,2 mW/oC

TEXAS . .
INSTRUMENTS
2-82

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLSOOl, TLSOOC, TLSOll, TLS01C

ANALOG PROCESSORS
recommended operating conditions
MIN

NOM

MAX

7

12

15

V

Negative supply voltage, VCC-

-9

-12

-15

V

Reference input voltage, Vreflll

0.1

5

V

Analog input voltage, VI

±5

V

Differential analog input voltage, VID

10

V

-

Positive supply voltage, VCC +

I Control inputs
I Control inputs

High-level input voltage, VIH
Low-level input voltage, VIL

2

V
0.8

Peak positive integrator output voltage, YOM +

+9

Peak negative integrator output voltage, VOM-

-5

UNIT

V
V
V

Full scale input voltage

2 Vref

Autozero and reference capacitors, Cz and eref

0.2

Integrator capacitor, Cx

0.2

Integrator resistor, RX

/L F

15

100

/L F
kO

See

Integrator time constant, RXCX

Note 3

I TL5001, TL5011
I TL500C, TL501 C

Free-air operating temperature, T A

-40

85

0

70

Maximum conversion rate with TL502C or TL503C

system electrical characteristics at Vee ±
(unless otherwise noted) (see Figure 3)
PARAMETER

± 12 V. Vref

TEST CONDITIONS

TL501
MIN

=

VI

Full scale temperature coefficient

=

TA

Temperature coefficient of zero error

2 V to 2 V

conv/sec

1.000 ± 0,03 mV. TA
TL500

TYP

MAX

TYP

MAX

50

300

10

30

0.005

0.05

0.001

0.005

Zero error

Linearity error relative to full scale

12.5

3

°c

full range

MIN

6

6

4

1

UNIT
/LV
%FS
ppm/DC
/LV/oC

Rollover error t

200

Equivalent peak-to-peak input noise voltage

20
10 9

20
109

/LV

86

90

dB

50

50

pA

90

90

dB

Analog input resistance

Pin 1 or 2

Common-mode rejection ratio

VIC

Current into analog input

VI

= -1 V
= ±5 V

to +1 V

Supply voltage rejection ratio

500

30

100

/LV

0

tRoliover error is the voltage difference between the conversion results of the full-scale positive 2 V and the full-scale negative 2 V.
NOTE 3. The minimum integrator time constant may be found by use of the following formula:

Minimum RXCX

VID (full scalel t1

1YOM _I ,- VI (pin

21

where
VID
VI(pin 21
t1

=
=

voltage at pin with respect to pin 2

=

input integration time seconds

voltage at pin 2 with respect to analog ground

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-83

TL500l, TL500C, TL501l, TL501 C

ANALOG PROCESSORS
1 V, TA = 25°e (see Figure 3)

electrical characteristics at Vee ± = ± 12 V, Vref
integrator and buffer operational amplifiers
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIO

Input offset voltage

15

mV

liB

Input bias current

50

pA

VOM+

Positive output voltage swing

9

11

V

VOM-

Negative output voltage swing

-5

-7

V

AVO

Voltage amplification

110

dB

Bl
CMRR

Common mode rejection

SR

Output slew rate

Unity-gain bandwidth

MHz

3
VIC

~

100

- 1 V to + 1 V

dB

5

VII''"

comparator
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIO

Input offset voltage

15

mV

liB

Input bias current

50

pA

AVO

Voltage amplification

VOL

Low-level output voltage

IOL

IOH

High-level output current

VOH

100
~

1.6 mA
~

dB

200

400

mV

5

20

nA

MIN

TYP

MAX

UNIT

1.12

1.22

1.32

V

3 V

voltage reference output
PARAMETER
Vref(OI

Reference-voltage
aVref

ro

TEST CONDITIONS

Reference voltage
temperature coefficient

TA

~

full range

ppm/DC

BO

Reference output resistance

n

3

logic control section
PARAMETER

TEST CONDITIONS

IIH

High-level input current

VIH

~

IlL

Low-level inpu"t current

VIL

~

MIN

2 V
0.8 V

TYP

MAX

1

10

I'A

-40

-300

I'A

UNIT

UNIT

total device
TYP

MAX

ICC+

Positive supply current

PARAMETER

TEST CONDITIONS

15

20

mA

ICC-

Negative supply current

12

18

mA

TEXAS

~

INSTRUMENTS
2-84

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

TL500l, TL500C, TL501l, TL501 C

ANALOG PROCESSORS
PARAMETER MEASUREMENT INFORMATION
-12 V

12 V

100 k!1
100 kn

(1 )
}

ANALOG
INPUTS

(2)

2
kn

VCC-

VCC+
PRECISION
VOLTAGE
SOURCE

5V

(12)

(16)

COMPARATOR
OUTPUT

(10)
MPU
LOGIC
CONTROLLER
Isee Note C)

(9)

CONTROL A
Vref =
1.000 ±0.03 mV

-=

(4)

(8)

REF
INPUT

CONTROL B

(7)

Cret = 1 I'F
Isee Note D)

Cref+

BUFFER
OUTPUT

(6)

(15)

D

t1=100ms
from

Cref_

(18)

INTEGRATOR
INPUT

Cz

Cz = 1 /IF
Isee Note D)
(17)

INTEGRATOR
OUTPUT

Cz
ANALOG

VlDltull scale)tl
RXCX = VOM-VIIPIN 2)
(13)

Cx = 1 /IF
(see Note D)

DIGITAL

DIGITAL COMMON

NOTES;

C. Tests are started approximately 5 seconds after power-on.
D. Capacitors used are TRW's X363UW polypropylene or equivalent for CX. Cref. and CZ; however for Cref and Cz film-dielectric
capacitors may be substituted.

FIGURE 3. TEST CIRCUIT CONFIGURATION

external-component selection guide
The autozero capacitor Cz and reference capacitor Cref should be within the recommended range of
operating conditions and should have low-leakage characteristics. Most film-dielectric capacitors and some
tantalum capacitors provide acceptable results. Ceramic and aluminum capacitors are not recommended
because of their relatively high-leakage characteristics.
The integrator capacitor Cx should also be within the recommended range and must have good voltage
linearity and low dielectric absorption. A polypropylene-dielectric capacitor similar to TRW's X363UW is
recommended for 4-1/2-digit accuracy. For 3-1/2-digit applications. polyester, polycarbonate, and other
film dielectrics are usually suitable. Ceramic and electrolytic capacitors are not recommended.
Stray coupling from the comparator output to any analog pin (in order of importance 17, 18, 14,7,6,
13, 1, 2, 15) must be minimized to avoid oscillations. In addition, all power supply pins should be bypassed
at the package, for example, by a O.01-I"F ceramic capacitor.
Analog and digital common are internally isolated and may be at different potentials. Digital common can
be within 4 V of positive or negative supply with the logic decode still functioning properly.
The time constant RXCX should be kept as near the minimum value as possible and is given by the formula:
Minimum RXCX

VIO (full scale) t1
I VOM - I - VI(pin2)

where:
VIO(full scale) = Voltage on pin 1 with respect to pin 2
t1 = Input integration time in seconds
VI(pin2) = Voltage on pin 2 with respect to analog ground.

'Ii1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-85

TL502C, TL503C
DIGITAL PROCESSORS

TL502C ... N PACKAGE

description of digital processors

(TOP VIEW)

The TL502C and TL503C are control logic
devices designed to complement the TL500 and
TL501 analog processors. They feature interdigit
blanking, over-range blanking, an internal
oscillator, and a fast display scan rate. The
internal-oscillator input is a Schmitt trigger circuit
that can be driven by an external clock pulse or
provide its own time base with the addition of
a capacitor. The typical oscillator frequency is
120 kHz with a 470-pF capacitor connected
between the oscillator input and ground.

CONTROL B OUTPUT

VCC

D1 (LSB)
D2

DIGIT
{
ENABLE
OUTPUTS

CONTROL A OUTPUT
20,000t

D3
D4

OSCILLATOR INPUT
TRIGGER

D5 (MSB)~

COMPARATOR INPUT

7'SEGMENT{A
DRIVER
B
OUTPUTS
C

G}
7.'SEGMENT
F
E
DRIVER

DIGITAL COMMON

D

OUTPUTS

---""---'

The TL502C provides seven-segment-display
output drivers capable of sinking 100 mA and
compatible with popular common-anode
displays. The TL503C has four BCD output
drivers capable of 100-mA sink currents. The
code (see next page and Figure 4) for each digit
is multiplexed to the output drivers in phase with
a pulse on the appropriate digit-enable line at a
digit rate equal to fosc, divided by 200. Each
digit-enable output is capable of sinking 20-mA.

TL503C ... N PACKAGE
(TOP VIEW)
CONTROL B OUTPUT
DIGIT
{
ENABLE
OUTPUTS

CONTROL A OUTPUT
OSCILLATOR INPUT
TRIGGER

D4
D5 (MSBI~

COMPARATOR INPUT
03

00
DIGITAL COMMON

The comparator input of each device, in addition
to monitoring the output of the zero-crossing
detector in the analog processor, may be used
in the display test mode to check for wiring and
display faults. A high logic level (2 to 6.5 V) at
the trigger input with the comparator input at or
below 6.5 V starts the integrate-input phase.
Voltage levels equal to or greater than 7.9 Von
both the trigger and comparator inputs clear the
system and set the BCD counter to 20,000.
When normal operation resumes, the conversion
cycle is restarted at the auto zero phase.

VCC

D1 (LSBI
D2
D3

'-<..;'--_:;..1-'

02
01

tPin 18 of TL502C provides an output of fosc (oscillator
frequency) -;- 20,000.
:1:05, the most significant bit, is also the sign bit.

These devices are manufactured using 12L and
bipolar techniques. The TL502C and TL503C are
characterized for operation from 0 DC to 70 DC.
TABLE OF SPECIAL FUNCTIONS
VCC
TRIGGER

COMPARATOR

INPUT

INPUT

=

5 V ±10%
FUNCTION

VI<0.8V

VI<6.5V

2 V7.9 V

Display Test: All BCD outputs high

VI>7.9 V

VI<6.5V

VI <6.5

Both inputs to go VI2:7.9
simultaneously

v

Hold at auto-zero cycle after completion of conversion

Internal Test
System clear: Sets BCD counter to 20,000.
When normal operation is resumed, cycle begins with Auto Zero,

~

TEXAS
INSTRUMENTS
2-86

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL502C, TL503C
DIGITAL PROCESSORS

DIGIT 5 IMOST SIGNIFICANT DIGIT) CHARACTER CODES
TL502C SEVEN-SEGMENT LINES
CHARACTER

+
+1
-

-1

TL503C BCD OUTPUT LINES
Q3

Q2

Q1

B

4

2

1

L

H

L

H

L

A

B

C

D

E

F

G

H

H

H

H

L

L

QO

H

L

L

H

L

L

L

H

H

H

L

L

H

H

L

H

H

L

H

L

H

H

L

L

L

L

H

H

L

H

H

H

H

DIGITS 1 THRU 4 NUMERIC CODE ISee Figure 4)
TL502C SEVEN-SEGMENT LINES
NUMBER

H

~

TL503C BCD OUTPUT LINES
Q3

Q2

Q1

8

4

2

1

H

L

L

L

L

H

H

L

L

L

H

H

L

L

L

H

L

H

H

L

L

L

H

H

H

H

L

L

L

H

L

L

L

H

L

L

L

H

L

H

L

L

L

H

H

L

H

H

L

H

H

H

L

L

H

L

L

L

L

L

H

L

L

H

A

B

C

D

E

F

G

0

L

L

L

L

L

L

1
2
3
4
5
6

H

L

L

H

H

L

L

H

L

L

L

L

L

L

H

L

L

L

H

L

L

H

L

L

L

7

L

L

L

H

H

8
9

L

L

L

L

L

L

L

L

L

H

high level, L

~

QO

low level

schematics of inputs and outputs
SEGMENT DRIVERS-TL502C
BCD DRIVERS-TL503C

COMPARATOR AND TRIGGER INPUT

2.5 kn

2.5 kn

5kn

h

DISPLAY
- TEST OR
SYSTEM
CLEAR

J,

VCC--750 n

---

OUTPUT

'"

k~

-r"

INPUT

-vcc

5 kn
-COMMON

COMMON---

J,
DIGIT-ENABLE OUTPUTS

CONTROL A AND B OUTPUTS
VCC---

VCC- -

1 kn

10 kn

16.8 kn

OUTPUT
0--

1 kn

OUTPUT
>----

110n'

---

- 4.4 kn
COMMON

1 kn

~

I

....
5kn
COMMON---'Shorted on TL503C

1 kn

J,

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-87

TL502C, TL503C
DIGITAL PROCESSORS
absolute maximum ratings
Supply voltage, Vcc (see Note 4)

7
Oscillator

Input voltage, VI

Comparator or Trigger

Output current

V

5.5

BCD or Segment drivers

120

Digit-enable outputs

40

Pin 1 8 (TL502C only)

20

Total power dissipation at (or below) 30 DC free-air temperature (see Note 5)
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

mA

1100

o to

Operating free-air temperature range

V

9

mW
DC

70

-65 to 150

DC

260

DC

NOTES: 4. Voltage values are with respect to the network ground terminal.
5. For operation above 30 DC free-air temperature, derate linearly to 736 mW at 70 DC at the rate of 9.2 mW/DC.

recommended operating conditions
Supply voltage, VCC
High·level input voltage, VIH
Low-level input voltage, VIL

I Comparator and trigger inputs
I Comparator and trigger inputs

NOM

MAX

4.5

5

5.5

2

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
V
V

0.8
0

Operating free-air temperature

2-88

MIN

70

V
DC

electrical characteristics at 25 °C free-air temperature
PARAMETER
VIK

Input clamp voltage
Positive-going input

VT+

threshold voltage
Negative-going input

VTVT+ - VT-

threshold voltage
Hysteresis

TERMINAL

TL502C

TEST CONDITIONS

=

MIN

-

TL503C

TYP

MAX

-0.8

-1.5

MIN

TYP

MAX

-0.8

-1.5

UNIT

All inputs

Vee

=

4.5 V,

Oscillator

Vee

=

5 V

Oscillator

Vee

=

5 V

Oscillator

Vee

=

5 V

0.4

0.6

0.8

0.4

0.6

0.8

Oscillator

Vee

=

5 V

-40

-94

-170

-40

-94

-170

~A

Oscillator

Vee

=

5 V

40

117

170

40

117

170

~A

4.15

4.4

4.15

4.4

Vee

=

4.5 V,

4.25

4.4

4.25

4.4

4.25

4.4

II

-12 mA

1.5

V

1.5

0.9

V

0.9

V

Input current at

IT+

positive-going input

threshold voltage
Input current at

IT-

"

0

(J>

negative-going input

threshold voltage

-<

Q

~z

1300

Digit enable
VOH

High-level output voltage

~ IT!
~

VOL

Low-level output voltage

~

IOL
IOL

Control A and B

Vee

=

4.5 V

Input current

IIH

High-level input current

IlL

Low-level input voltage

Comparator, Trigger

Oscillator
Comparator, Trigger

Oscillator
Oscillator
Comparator, Trigger

High-level output current
(Output transistor off)

Low-level output current
IOL
ICC

~

<0

0

IOL

(Output transistor on)
Supply current

=
=
=
=
=

2 rnA
100 rnA

VI

=

5.5 V

Vee

=

5.5 V,

VI

=

2.4 V

Vee

=

5.5 V,

VI

=

0.4 V

Segment drivers

Vo

BCD drivers

Vo
Vo

=

Pin 18 (TL502e only)

Vo
Vee

=

4.5 V

Digit enable

Vee

=

4.5 V,

Vce

Vee

=

5.5 V

Vo

0.15

0.4

0.088

0.4

0.17

0.3

65

100

100 rnA

5.5 V,

=
=
=
=
=

Control A and 8

10 rnA

=

Vo

V

20 rnA

Vee

Digit enable
IOH

IOL
IOL

BCD drivers
II

~
~

'"'"

Digit enable
Pin 18 (TL502e only)
Segment drivers

Z

~ Ci1~

=

IOH

Control A and B

~...,

G;;cr;;1
8o C~
~

Pin 18 (TL502e only)

-0.6

0.088

0.4

-1

0.3

65

100

~A

1

rnA

-0.6

-1
0.5

-0.1

-0.17

-0.1

-0.17

-1

-1.6

-1

-1.6

0.5 V

-0.5

-0.9

0.5 V

-0.25

-0.4

V

0.17

0.5

-4

3.55 V

0.5

1

-2.5

0.5 V,

0.2

-2.5

-4

-0.25

-0.4

rnA
rnA

rnA

0.25

5.5 V

> .....

0.25
23
73

,... r-

rnA
110

C)

::::j

5.5 V
18

CI

73

110

rnA
--

-ag:

:aN
nOn

m-f
en,...
enUi
0=
:aw
enn

TL502C, TL503C
DIGITAL PROCESSORS

special functions t operating characteristics at 25 DC free-air temperature
PARAMETER
II

TEST CONDITIONS

MIN

Input current into

VCC = 5.5 V,

VI = 8.55 V

comparator or trigger inputs

VCC = 5.5 V,

VI =,6.25 V

TYP

MAX

1.2

1.8

mA

0.5

mA

UNIT

tThe comparator and trigger inputs may be used in the normal mode or to perform special functions. See the Table of Special Functions.

TYPICAL APPLICATION DATA

01-------,1
--i~_._---1~6~,7~~-s~(s-ee~N~o-te-E~)-----------------------------------------j4-316.7 ~s-=-j :
I
02----------------------~

03------------------------------------~

04---------------------------------------------------,
05-----------------------------------------------------------------,

r--

L--------,I
NOTE E: The BCD or seven-segment driver outputs are present for a particular digit slightly before the falling edge of that digit enable.

FIGURE 4. TL502C. TL503C DIGIT TIMING WITH 120-kHz CLOCK SIGNAL AT OSCILLATOR INPUT

-I!}

TEXAS
INSTRUMENTS
2-90

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL505C
ANALOG-TO-DIGITAL CONVERTER
D2366, OCTOBER 1977-REVISED FEBRUARY 19B9

•

3-Digit Accuracy (0.1 %)

•

10-Bit Resolution

•

Automatic Zero

•

Internal Reference Voltage

N PACKAGE
(TOP VIEW)

VCC
ANALOG IN

•

Single-Supply Operation

•

High-Impedance MOS Input

•

Designed for Use with TMS 1000 Type
Microprocessors for Cost-Effective
High-Volume Applications

•

BI-MOS Technology

•

Only 40 mW Typical Power Consumption

ZERO CAP 2
ZERO CAP 1

REF OUT
REF IN

INTEG RES
INTEG IN

GND
BIN

INTEG OUT
GND

A IN -""_ _r-" CaMP OUT

Caution. This device has limited built-in gate protection, The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MaS gates.

description
The TL505C is an analog-to-digital converter building block designed for use with TMS 1000 type
microprocessors. It contains the analog elements (operational amplifier, comparator, voltage reference,
analog switches, and switch drivers) necessary for a unipolar automatic-zeroing dual-slope converter. The
logic for the dual-slope conversion can be performed by the associated MPU as a software routine or can
be implemented with other components, such as the TL50210gic-control device.
The high-impedance MOS inputs permit the use of less expensive, lower value capacitors for the integration
and offset capacitors and permit conversion speeds from 20 per second to 0.05 per second,
The TL505C is a product of TI's BI-MOS process, which incorporates bipolar and MOSFET transistors on
the same monolithic circuit. The TL505C is characterized for operation from O°C to 70°C.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarilv include testing of all parameters.

~

Copyright

© 1983, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-91

TL505C
ANAlOG·TO·DlGITAl CONVERTER
functional block diagram
RX

1-----

(12)

------r-----:

(10)

(11 )

1
1
1

VCC (1)

1

I

(4):

S4

........---4>---~~-_I

,

">-_---OCOMP
: OUT

1
I

1

1

I

I
I

1

S2C

(13) I

1
1
1

Cz

1

1(61
I

VOLTAGE
REFERENCE

S3A

(2)'

ANALOG~
INPUT

,
I
(3),

~

LOGIC DECODE
AND
SWITCH ORIVERS

B
1 (7)

A
I
I

______________________ ~ ___ ~_J
(5)

GND

(9)

GND

NOTE: Analog and digital GND are internally connected together.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Input voltage, pins 2, 4, 6, and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2) . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . 260 DC
NOTES:

1. Voltage values are with respect to the two ground terminals connected together.
2. For operation above 25°e free·air temperature, derate linearly to 736 mW at 70 0 e at the rate of 9.2 mW/oe.

recommended operating conditions
MIN

NOM

MAX

Supply voltage, Vee

7

9

15

Analog input voltage, VI

0

4

V

Reference input voltage, VreH!)

0.5

3

V

High-level input voltage at A or B, VIH

3.6

Vee+ 1

V

Low-level input voltage at A or B, VIL

0.2

1.8

V

V

See "component selection"

Integrator capacitor, eX
Integrator resistor, RX
Integration time, tl
Operating free-air temperature, T A

~

TEXAS
INSTRUMENTS
2-92

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.5

2

M[J

16.6

500

ms

0

70

°e

TL505C
ANALOG· TO·DlGITAL CONVERTER
electrical characteristics, Vee
(unless otherwise noted)

25°e, connected as shown in Figure 1

1 V, TA

9 V, Vref(l}

PARAMETER

TEST CONOITIONS

VOH

High-level output voltage at pin 8

IOH

High-level output current at pin 8

IOH
VOH

VOL

Low-level output voltage at pin 8

IOL

MIN

TYP

7.5

8.5

V

7.5 V

-100

~A

1.6 mA

200

a

~

~
~

Maximum peak output voltage

VOM

Reference output voltage

VrellOI
"Vrel

-100

Irel -

Temperature coefficient of

TA

reference output voltage

~

High-level input current into A or B

IlL

Low-level input current into A or B

VI - 9 V
VI - 1 V

II

Current into analog input

VI

liB

Total integrator input bias current

ICC

Supply current

~

~A

1.15

ooe to 70°C

IIH

a to

400

4 V.

1.22

1.35

aV

system electrical characteristics, Vee
Figure 1 (unless otherwise noted)

1 V, TA

TEST CONOITIONS

PARAMETER
Zero error

VI

Linearity error

VI

- a
~ a to

10
200

~A

±10

± 200

pA

8

mA

Ratiometric reading

VI - Vrelill -

V relill constant and

ratio metric reading

TA

~

a °e to

1 V

MIN

0.998
~

1 V.

70 DC

pA

25°e, connected as shown in

4 V

Temperature coefficient of

~A

1

4.5

9 V, Vref(l}

V

10
±10

No load

mV

ppm/oe

±100

A input at

UNIT

V

Vee- 2 Vee- 1

RX '" 500 kQ

swing at integrator output

MAX

TYP

MAX

0.1

0.4

mV

0.02

0.1

%FS

1.000

1.002

±10

UNIT

ppm/oe

DEFINITION OF TERMS
Zero Error
The intercept (b) of the anolog-to-digital converter system transfer function y = mx + b, where y is the
digital output, x is the analog input, and m is the slope of the transfer function, which is approximated
by the ratiometric reading.

Linearity Error
The maximum magnitude of the deviation from a straight line between the end points of the transfer function.

Ratiometric Reading
The ratio of negative integration time (t2) to positive time (t1).

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-93

TL505C

ANALOG-TO-DlGlTAL CONVERTER
PRINCIPLES OF OPERATION
A block diagram of an MPU system using the TL505C is shown in Figure 1. The TL505C operates in a
modified positive-integration, three-step, dual-slope conversion mode. The AID converter waveforms during
the conversion process are illustrated in Figure 2.
Vcc

RX

Cx

1 Mn

0.01 "F

:----- (12)

(11)----- (10)

,
,

(1)

,I

I

(4):

S4

'(B)

1V~"""=--~"""""""'"

~~--o---r~IN

,
,
,,

MPU
CONTROLLER

(13) I

Cz

10 kn

rLO~~Ec;ltlE~~Q(71}-1-jJ A

1"F (14): S3A
ANALOG~

I N PUT

AND
8:>',-=-----''-1 B

(2) :
(3)'

I

'----------I~. ~----------------------;q.(51-~-J
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF TL505C INTERFACE WITH A MICROPROCESSOR SYSTEM
FUNcnON TABLE

I

A------t!

CONTROLS

I

I
B------~I
I

I

A

I

I
I

I

-V2

L

L

H

H

S3

I

L

H

S1, S4

I
I

IT

cO~~~:~~OR 1~!.'I.mi.\Df,ll~____,--_-,_liMrIl
I
I
I
- - t o - - -....."'I.f----t1
V1

= V2 -

V3

0\'

t2---<0>to1.---to--.-

= VI + VO(ofs}

FIGURE 2. CONVERSION PROCESS TIMING DIAGRAMS

~

TEXAS
INSTRUMENTS
2-94

S1, S2

I

I

INTEGRATOR
V1- rVo(ofs)
OUTPUT
...,......u____.~

SWITCHES CLOSED

I

I

-

I

I

ANALOG

B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL505C
ANALOG· TO· DIGITAL CONVERTER

PRINCIPLES OF OPERATION (Continued)
The first step of the conversion process is the auto-zero period to. By the end of this period, the integrator
offset is stored in the autozero capacitor, and the offset of the comparator is stored in the integrator
capacitor. To achieve this end, the MPU takes the A and B inputs low, which closes S 1 and S2. The output
of the comparator is connected to the input of the integrator through the low-pass filter consisting of RZ
and CZ. The closed loop of A 1 and A2 seeks a null condition in which the offsets of the integrator and
comparator are stored in Cz and CX, respectively. This null condition is characterized by a I'Iigh-frequency
oscillation at the output of the comparator. The purpose of S2B is to shorten the amount of time required
to reach the null condition.
At the conclusion of to, the MPU takes the A and B inputs both high, which closes S3 and opens all other
switches. The input signal VI is applied to the noninverting input of A 1 through CZ. VI is then positively
integrated by A 1. Since the offset of A 1 is stored in CZ, the change in voltage across Cx is due to only
the input voltage. Since the input is integrated in a positive integration during t1, the output of A 1 will
be the sum of the input voltage, the integral of the input voltage, and the comparator offset, as shown
in Figure 2. The change in voltage across capacitor Cx (VCX) during t1 is given by
(1 )

where R1 = RX + RS3B and RS3B is the resistance of switch S3B.
At the end of t1, the MPU takes the A input low and the B input high, which closes S1 and S4 and opens
all other switches. In this state, the reference is integrated by A 1 in a negative sense until the integrator
output reaches the comparator threshold. At this point, the comparator output goes high. This change
in state is sensed by the MPU, which terminates t2 by again taking the A and B inputs both low. During
t2, the change in voltage across Cx is given by
(2)

where R2 = RX + RS4 + Rref and Rref is the equivalent resistance of the reference divider.
Since LlVCX1 = -LlVCX2, equations (1) and (2) can be combined to give
VI = V

f R,-t2
re R2- t 1

(3)

This equation is a variation on the ideal dual-slope equation, which is
(4)

Ideally then, the ratio of R1/R2 would be exactly equal to one. In a typical TL505C system where
RX = 1 MO, the scaling error introduced by the difference in R1 and R2 is so small that it can be neglected,
and equation (3) reduces to (4).

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-95

TL505C
ANALOG·TO·DIGITAL CONVERTER

PRINCIPLES OF OPERATION (Continued)
component selection
The autozero capacitor Cz should be within the recommended range of operating conditions and should
have low leakage characteristics. Most film-dielectric capacitors and some tantalum capacitors provide
acceptable results. Ceramic and aluminum capacitors are not recommended because of their relatively
high leakage characteristics.
The integrator capacitor Cx should also be within the recommended range and must have good voltage
linearity and low dielectric absorption. For 10-bit applications, polyster, polycarbonate, and other film
dielectrics are usually suitable. If greater precision or stability is required, a polypropylene-dielectric capacitor
similar to TRW's X363UW might be appropriate.
Stray coupling from the comparator output to any analog pin (in order of importance, 13, 11, 10, 2, 4)
must be minimized to avoid oscillations. In addition, all power supply pins should be bypassed at the package,
for example, by a 0.01-/LF ceramic capacitor.
The time constant RXCX should be kept as near the minimum value as possible and is given by the formula:
Minimum RXCX =

Vl(max) t1
(VCC - 2 V - VI(max))

where:

t1 = Input integration time in seconds,
Vl(max) = the maximum value of the analog input voltage,
VCC - 2 V = the maximum voltage swing of the integrator input.

~

TEXAS
INSTRUMENTS
2-96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL505C
ANALOG·TO·DIGITAL CONVERTER
TYPICAL APPLICATION DATA
9V

ANALOG
COMP

INPUT

SIGNAL OUT

t--------i

K(X)

SEE NOTE 3
Tl505C

A

TMS1000
SERIES

10
kn

10kn
LOGIC

SEGMENT

R8

DRIVE

CONTROL
B

R9

DIGIT

LINES

DRIVE
TIL312 LED

FULL-SCALE
ADJUST
'::'

DISPLAYS

'::'

NOTE 3: Connect to either 9 V or

aV

depending on which device in the TMS 1 000 series is used and how it is programmed.

FIGURE 3. TL505C IN CONJUNCTION WITH A TMS1 000 SERIES MICROPROCESSOR
FOR A 3-DIGITAL PANEL METER APPLICATION
5V

12 V

56 n 1N914
1 k{l

FROM
AUDIO
SYSTEM

8 {l

OS
I'F

VCC

ANALOG
INPUT

COMP/LAMP
TEST

COMP

OUT
REF

IN

2.2 kn

1N914

VCC

A

A

B

B
470 pF

TL505C

GND

RX2

D2
2.2 kn

TlS91

D1
9

f

e

OSC
INPUT

d

TL502

T

b

CZ1
6.8I'F

,,,,a_ _ _.1'"_ _ _9..,,
GND

CX2

GND

D1 D2

SEGMENT
TIL807

FIGURE 4. AUDIO PEAK POWER METER

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-97

2-98

TL5071, TL507C
ANALOG·TO·DlGITAL CONVERTER
02503, OCTOBER 1979-REVISED OCTOBER 1988

P PACKAGE

•

low Cost

•

7·Bit Resolution

•

Monotonicity Over Entire AID Conversion
Range

(TOP VIEW)

•

Ratiometric Conversion

•

Conversion Speed ... Approximately 1 ms

•

Single-Supply Operation ... Either
Unregulated 8-V to 18-V (VCC2 Input), or
Regulated 3.5-V to 6-V (VCC1 Input)

•

12 l Technology

•

Power Consumption at 5 V ... 25 mW Typ

•

Regulated 5.5 V Output (:51 mAl

ENABLE u B RESET
ClK

2,

7

GND
OUTPUT

3

6
5

4

VCC2
VCC1

ANALOG INPUT

FUNCTION TABLE
ANALOG

ENABLE

OUTPUT

X

Lt

H

VI<200mV

H

L

V,amp>VI>200 mV

H

H

VI>V,amp

H

L

INPUT CONDITION

t Low level on enable also inhibits the reset function.
H = high level, L = low level, X = irrelevant

description

A high level on the reset pin clears the counter to zero,

The Tl507 is a low-cost single-slope analog-towhich sets the internal ,amp to 0.75 Vee. Internal
digital converter designed to convert analog
pull-down resistors keep the reset and enable pins low
input voltages between 0,25 VCC1 and 0.75
when not connected.
VCC1 into a pulse-width-modulated output
code. The device contains a 7-bit synchronous
counter, a binary weighted resistor ladder network, an operational amplifier, two comparators, a buffer
amplifier, an internal regulator, and necessary logic circuitry. Integrated-injection logic (1 2 l) technology
makes it possible to offer this complex circuit at low cost in a small dual-in-line 8-pin package.
In continuous operation, conversion speeds of up to 1000 conversions per second are possible. The Tl507
requires external signals for clock, reset, and enable. Versatility and simplicity of operation, coupled with
low cost, makes this converter especially useful for a wide variety of applications,
The Tl5071 is characterized for operation from - 40°C to 85 °C, and the Tl507C is characterized for
operation from OOC to 70°C.

functional block diagram (positive logic)
COMPARATOR 2

ANALOG~15~1__________. ______________________~~

INPUT
OUTPUT
CTR

R

MSBQ
Q

+

Q
Q

RESET 181
111

ENABLE

R

2R
4R
8R
16R

Q

R

32R
Q

REGULATOR

64R

171

LSB Q

VCC2
025 VCC1

161
VCC1
131
'------GNO

Q indicates

an n-p-n open-collector output.

PRODUCTION DATA documents contain information
currant as of publication dats. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

"'!1

Copyright

© 1979, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-99

TL5071, TL507C

ANALOG·TO·DIGITAL CONVERTER
schematics of inputs and outputs
EQUIVALENT OF ENABLE

EQUIVALENT OF CLOCK

AND RESET INPUTS

INPUT

EQUIVALENT OF ANALOG
INPUT
VCC1--------~--

75k!"!

'N'"'

~--

j----J

INPUT-VV'v-l

OUTPUT
....------~------- vCC1

OUTPUT

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 V
Input voltage at analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage at enable, clock, and reset inputs .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 V
On-state output voltage ."..................................................... 6 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 20 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . .. 1000 mW
Operating free-air temperature range: TL5071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 85 °C
TL507C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . .. 260°C
NOTES: 1. Voltage values are with respect to network ground terminal unless otherwise noted.

2. For operation above 25°C free-air temperature, derate linearly to 520 mW at 85°C at the rate of 8.0 mW/oC.

-1!1

TEXAS
INSTRUMENTS
2-100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL5071, TL507C
ANALOG-TO-DiGITAL CONVERTER
recommended operating conditions
MIN

NOM

MAX

Supply voltage, VCCl

3.5

5

6

V

Supply voltage, VCC2

8

15

18

V

Input voltage at analog input

0

5.5

V

Input voltage at chip enable, clock, and reset inputs

±18

High-level input voltage, VIH, reset and enable

2

UNIT

V
V

Low-level input voltage, VIL, reset and enable

0.8

V

On-state output voltage

5.5

V

Off-state output voltage

18

Clock frequency, f clock

0

125

150

V
kHz

electrical characteristics over recommended operating free-air temperature range.
VCC1 = VCC2 = 5 V (unless otherwise noted)
regulator section
PARAMETER
VCCl

Supply voltage (output)

ICCl
ICC2

MIN

Typt

MAX

5

5.5

6

V

VCC2 open

5

8

mA

VCCl open

7

10

mA

Typt

MAX

TEST CONDITIONS

Supply current

VCC2 = 10to18V,
VCCl = 5 V,

Supply current

VCC2 = 15 V,

ICCl =Oto -lmA

UNIT

inputs
PARAMETER
VT+

Positive-going threshold voltage t

VT-

Negative-going threshold voltage t

Vhvs

Hysteresis (VT + - VT-)

TEST CONDITIONS

MIN

4.5
Clock Input

2

2.6

4

17

35

VI = 2.4 V

IIH
IlL

Low-level input current

VI = 0

II

Analog input current

VI = 4 V

Reset, Enable, and Clock

VI = 18 V

130

V
V

0.4

High-level input current

UNIT

220

320

V
p.A

±10

p.A

10

300

nA

Typt

MAX

UNIT

0.1

100

p.A

10

15

mA

80

400

mV

Typt

MAX

UNIT

±80

mV

±20

mV

±80

mV

±80

mV

output section
PARAMETER

TEST CONDITIONS

IOH

High-level output current

VOH = 18 V

IOL

Low-level output current

VOL = 5.5 V

VOL

Low-level output voltage

IOL = 1.6 mA

MIN
5

operating characteristics over recommended operating free-air temperature range.
VCC1 = VCC2 = 5.12 V
PARAMETER

TEST CONDITIONS

MIN

Overall error
See Figure 1

Differential nonlinearity
Zero error t

Binary count = 0

Scale error

Binary count

Full scale input voltage!

Binary count = 127

= 127

Propagation delay time from reset or enable

3.74

3.82
2

3.9

V
p's

t All typical values are at T A = 25 DC.
+These parameters are linear functions of Vee1-

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-101

TL5071, TL507C

ANALOG-TO-DIGITAL CONVERTER

definitions
zero error
The absolute value of the difference between the actual analog voltage at the 01 H-to-OOH transition and
the ideal analog voltage at that transition.
overall error
The magnitude of the deviation from a straight line between the endpoints of the transfer function.
differential nonlinearity
The maximum deviation of an analog-value change associated with a 1-bit code change (1 clock pulse)
from its theoretical value of 1 LSB.

PARAMETER MEASUREMENT INFORMATION
SN74191

r--<: >CLOCK

4

OUTPUTS
r - DOWN/UP

ANALOG DEVICES
AD562
(or equivalent)

SN74191
RIPPLE
CLOCK

-

-<: >CLOCK
OUTPUTS
I - DOWN/UP

C)

'---

4

TEST
POINT

BITS9·12
BITS 5·8

-

5kll

BITS '·4

TL507

~1

DAC
OUT

rV"NW
_

CLOCK PULSE

SN74191
RIPPLE
CLOCK
100 kHz
CLOCK
INPUT

>

CLOCK
OUTPUTS

4

I- DOWN/UP

FIGURE 1. MONOTONICITY AND NONLINEARITY TEST CIRCUIT

~

TEXAS
INSTRUMENTS
2-102

POST Of;:FICE BOX 655303 • DALLAS, TEXAS 75265

ANALOG
INPUT
OUTPUT
> CLOCK

-

TL5071. TL507C
ANALOG·TO·DlGITAL CONVERTER
PRINCIPLES OF OPERATION
The TL507 is a single-slope analog-to-digital converter. All single-slope converters are basically voltageto-time or current-to-time converters. A study of the functional block diagram shows the versatility of
the TL507.
An external clock signal is applied through a buffer to a negative-edge-triggered synchronous counter. Binaryweighted resistors from the counter are connected to an operational amplifier used as an adder. The
operational amplifier generates a signal that ramps from 0.75· VCC1 down to 0.25· VCC1. Comparator 1
compares the ramp signal to the analog input signal. Comparator 2 functions as a fault defector. With
the analog input voltage in the range 0.25 • VCC1 to 0.75 • VCC1, the duty cycle of the output signal
is determined by the unknown analog input, as shown in Figure 2 and the Function Table.
For illustration, assume VCC1 = 5.12 V,
0.25 • VCC1

1.28 V
(0.75 - 0.25) VCC1

1 binary count
0.75 • VCC1 -

1 count

128

20 mV

3.82 V

The output is an open-collector n-p-n transistor capable of withstanding up to 18 V in the off state. The
output is current limited to the 8- to 12-mA range; however, care must be taken to ensure that the output
does not exceed 5.5 V in the on state.
The voltage regulator section allows operation from either an unregulated 8- to 18-V VCC2 source or a
regulated 3.5- to 6-V VCC1 source. Regardless of which external power source is used, the internal circuitry
operates at VCC1. When operating from a VCC1 source, VCC2 may be connected to VCC1 or left open.
When operating from a VCC2 source, VCC1 can be used as a reference voltage output.

ANALOG INPUT
LEVEL 1

RAMP INPUT TO
COMPARATOR 1

OUTPUT FOR
INPUT LEVEL 1

ou,,"''",

INPUT LEVEL 2

J

uu
FIGURE 2

TEXAS

L

-I!}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

2-103

\

2-104

TLC532AM. TLC532AI. TLC533AM. TLC533AI
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
D2819, NOVEMBER 1983-REVISED SEPTEMBER 1986

N PACKAGE
(TOP VIEW)

LinCMOS" Technology

•

8·Bit Resolution

•

Total Unadjusted Error ...

•

Ratiometric Conversion

•

Access Plus Conversion Time:
TLC532A ... 15 ,.s Max
TLC533A ... 30 ,.s Max

± 0.5

GND

VCC

2 - 1 (MSB)
2-2
2- 3

AO }
A2
A3

1/0
DATA
BUS

•

3·State. Bidirectional I/O Data Bus

•

5 Analog and 6 Dual·Purpose Inputs

•

On·Chip 12·Channel Analog Multiplexer

•

Three On· Chip 16·Bit Data Registers

•

Software Compatible with Larger TL530
and TL531 (21·lnput Versions)

•

On·Chip Sample·and·Hold Circuit

•

Single 5· V Supply Operation

•

Low Power Consumption ... 6.5 mW Typ

•

Improved Direct Replacements for Texas
Instruments TL532 and TL533. National
Semiconductor ADC0829. and Motorola
MC14442

REF + (A 11

REF -

LSB Max

ANALOG

2 - 4

A4

2 -5

A5

2 -6

A10lD1 }
A 11/02
A12/D3
A 13104
A 14105
A 15/06

2- 7
2 -8 (lSB)
READIWRITE IRiwl
CLOCK (ClK)
REGISTER SELECT IRS)
CHIP SELECT (CS)

'"1..._ _

INPUTS

ANALOGI
DIGITAL
INPUTS

RESET (R)

~

•

FN PACKAGE
(TOP VIEW)

m

~

(f)

::2;
N
I
N

0
I
N

4

description

3

I
L.L

+

L.L

Zw UJ
t:J0::: 0:::
2

U

uo
>«

1 2827 26

2- 3

5

25

2- 4

6

24

A3

23

A4

2- 5

The TLC532A and TLC533A are monolithic
LinCMOS" peripheral integrated circuits each
designed to interface a microprocessor for
analog data acquisition. These devices are
complete peripheral data acquisition systems on
a single chip and can convert analog signals to
digital data from up to 11 external analog
terminals. Each device operates from a
single 5-V supply and contains a 12-channel
analog multiplexer. an 8-bit ratiometric analogto-digital (A/D) converter, a sample-and-hold,
three 16-bit registers, and microprocessorcompatible control circuitry. Additional features
include a built-in self-test. six multipurpose
(analog or digital) inputs, five external analog
inputs, and an 8-pin input/output (110) data port.
The three on-chip data registers store the control
data, the conversion results, and the input digital
data that can be accesssed via the
microprocessor data bus in two 8-bit bytes
(most-significant byte first). In this manner, a
microprocessor can access up to 11 external
analog inputs or 6 digital signals and the positive
reference voltage that may be used for self-test.

A2

2- 6

8

22

A5

2- 7

9

21

2 -- 8 (lSBI

10

20

Riw

11

A10/D1
A11/D2
A 12103

19
12 13 14 15 161718

"J

COL0en>

iil

>e».
..........

CQ
289

6

290

~C

CLOCK

I
-I
I
I
START CONVERSION CYCLE
1'1141----+--- IF SC BIT IS LOGIC ONE (HIGH)

I;!

ii

.

0

'!l

I+t---lWRITEC~CLE
I

1

1

1

14I
1
I
RiW

I

1
I

i

T------+---~-~·II41-WRITE~
:

R~AD CYCLE

I

I

I

I

I

-

I

:::J

n

CD

!

1

.14 :

tsu(A)~

CD

.1

!

Cr CLE
I
I

I

0

!

U!Q.~

j

..:i"

3

=e.!::. ""t

-=nn
....
.....
=!:f.n
2i1!:

Q2i!
....
C) ..... ,n

»~

22"-'

~~~.

c:nQ

~'?;:!

C .....

n

>eU!

..... w

c_=. . .
.~W

"'CIS):io
"'CI )I. •::a:

:::l .....

Q .........

!3C/l

en"'CIh
mmU!

i:iz

m~~

_=w
C=en=

cs

2-W

"'CI"'CI>

~cl"'l

~ ~~.

1! I"'l

..... m

RS

~z

.

~"' ·Cil4r

~ ..n I

t su (bus)-I!1

1-

MS

~

...'"
s:

DATA

:

LS

~

I

I

-.. ~ton

1

.'en

!

:

1

LS

LS

n:
I

I

...:

~ ~ten
1

I

LS

.....

I'
1

-.. l4-'on
1
I

:

I

I

I

1

1

.en...c

I

j4MS

-+!

HI-Z STATE

BUS

-,

SEE NOTE A

NOTES: A.
B.
C.
D.
E.

This is a l6-bit input instruction from the microprocessor being sent to the control data register,
This is the 2-byte (16-bit) content of the digital data register being sent to the microprocessor.
This is the LS byte (S-bit) content of the analog conversion data register being sent to the microprocessor.
This is the LS byte (S-bit) content of the digital data register being sent to the microprocessor.
These are MS byte (S-bit), LS byte (S-bit). and LS byte (S-bit) content of the analog. conversion data register or digital data
register being sent to the microprocessor.
F. This is the 2-byte (16-bit) content of the analog conversion data register being sent to the microprocessor.

~.__

~

>
....
en

TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
read or write cycle time sequence
trlClK)..j

j.-

-.J f4- t t(ClK)

Shn

CLOCK ,,1

CLOCK #10

3
ClK
I

I

R

l . . .___

----J

(See Note AI

CONTROL
INPUTS

R/W
RS

I

~I

__I

tSU(A)~

END
1
CONVERSION-+I

1

II

--.jl4- t h(C)

(CS)---6i ' ~ 1-

~~l

I

:~

I

~

I

START
CONVERSION

~~____~__~__~I

XlX'IYX'llXlXI! :
t

28

I I

____~________J~~----------------~----------I

I

1

I

I

I

-+1 I+-tenI
~

r---"j
DATA BUS
DATA OUT
("READ")

lS I
HI-Z
----------------------------------1 BYT J~---1BYT~I-S-e-e-N-o-te-B-------------:---------HI-Z

MS

I

HI-Z

I

I

~
-+j j4- t dis

I+-

tsu(bus)-+I

c..--l
--'1 j4- t dis
-.j 14-- tsu(bus)

r-"f
DATA BUS
DATAIN
("WRITE")

HI-Z

----------------------------------~
MS
BYTE

I

I
I

.....l

r-"j
HI-Z

I

HI-Z

11---------------------------

lS
I
BYTE ~

th(bus)~j4-

~j4-th(bus)
)

1

MlI4Ir----- tacq

I
:
1

------1~~1

NOTES: A. The reset pulse (R lowl is required only during power-up.
B. The most significant byte output of Data Out occurs when elK is high. When elK is low, Data Out is in the high-impedance
(off) state. When elK goes high again, the least significant byte is placed on the data bus, At this point, the least significant
byte remains on the bus for as long as elK is kept high.

TEXAS

-II}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-109

TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCMOSTM 8-BIT ANALOG-TO-DlGlTAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS
DATA BUS
LINES 2 - 1

2- 2

IIM~B) I

X

2- 3
I

2- 4
I

X

X

2- 5
I

I

X

2 -- 6

2- 7

X

X

2- 8

,..:2:.-_1,-2=---_2-,.::2_-_3-,-=2=--_4-,..;2:.-_5-,-=:2_-_6-,.::2'--_7--,..:2:.-_8--,

II~sCBlI IIM~BII

X

I

X

I

X

I

A3

I A2

I

A1

I

I:S~I I

~t====~====L_-M-o~SLT-S-IG-N-ILFI-C-A-N-TLB-Y-T-E~~====~==~J ~~:==~====~=--L-E-A.LS-T-S-IG-N.LIF-I-CA-N-T-'--B-Y-TE-_.L_-_-_-_""_-'-_-_-_~:I,
-

16-BIT WRITE

Unused Bits (X) Start Conversion
channel begins
Analog Multiplex
analog channel

------------------+\-,

The MS byte bits 2 -1 through 2 -7 and LS byte bits 2 -1 through 2 -4 of the control register are not used internally.
(SC)- When the SC bit in the MS byte is.set to a logical 1, and analog-to-digital conversion on the specified analog
immediately after the completion of the control register write.
Address (AO-A3)- These four address bits are decoded by the analog multiplexer and used to select the appropriate
as shown below:

Hexadecimal Address (A3

=

MSB)

Channel Select

o

AO

1

REF + (A1)

2-5

A2-A5

6-9 (not used)
A-F

A10-A15

FIGURE 1. WORD FORMAT AND CONTENT FOR CONTROL REGISTER 2-8YTE WRITE
DATA BUS
LINES

2- 1

2 -2

2- 3

2- 4

2- 5

II~~~I ° ° ° °
I

I

I

2- 7

2- 6

I

°

MOST SIGNIFICANT BYTE
8-BIT READ

I

2- 1

2- 8

° IL~BII IIM~BII

2-2

2- 3

2- 4

2- 5

2- 6

2- 7

R6

R5

R4

R3

R2

Rl

I

j~

IIL:OBII

I

I

2.-8

LEAST SIGNIFICANT BYTE

16-BIT READ
AID Status (EOC)- The AID status end-of-conversion (EOC)bit is set whenever an analog-to-digital conversion is successfully completed
by the AID converter. The status bit is cleared by a 16-bit write from the microprocessor to the control register. The remainder of the
bits in the MS byte of the analog conversion data register are always reset to logical 0 to simplify microprocessor interrogation of the
AID converter status.
AID Result (RO-R7)- The LS byte of the analog conversion data register contains the result of the analog-to-digital conversion. Result
bit R7 is the MSB and the converter follows the standard convention of assigning a code of all ones (11111111) to a full-scale analog
voltage. There are no special overflow or underflow indications.

FIGURE 2. WORD FORMAT AND CONTENT FOR ANALOG
CONVERSION DATA REGISTER 1-8YTE AND 2-8YTE READ
DATA BUS
LINES 2-1

2- 1

II~~B)I
14------ MOST

SIGNIFICANT BYTE

/4---------8-BIT

------l~

2- 2

2- 3

2- 4

2- 5

2- 6

2- 7

AO

X

X

X

X

X

14

I

I

I

I

I

2- 8

I IL:BI I

LEAST SIGNIFICANT BYTE

READ-------~

14----------------------16-BITREAD------------------~

Shared Digital Port (A 1OlD 1-A 1 5/D6) - The voltage present on these pins is interpreted as a digital signal, and the corresponding states
are read from these bits. A digital value is given for each pin even if some or all of these pins are being used as analog inputs.
Analog Multiplexer Address (AO-A3)- The address of the selected analog channel presently addressed is given by these bits.
Unused Bits (X) - LS byte bits 2 - 3 through 2 - 8 of the digital data register are not used.

FIGURE 3. WORD FORMAT AND CONTENT FOR DIGITAL DATA REGISTER 1-8YTE AND 2-8YTE READ

TEXAS

~

INSTRUMENTS
2-110

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC532AM. TLC532AI. TLC533AM. TLC533AI
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V
Input voltage range: Positive reference voltage. . . . . . . . . . . . . . . . . . . . .. VREF _ to VCC + 0.3 V
Negative reference voltage. . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VREF +
All other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VCC + 0.3 V
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . .
± 10 mA
Total input current, (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range: TLC532AM, TLC533AM
- 55°C to 125°C
TLC532AI, TLC533AI . . . . . . . . . . . . . . . .
- 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: N package.
260°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTE 1: All voltage values are with respect to network ground terminal.

recommended operating conditions
TLC532A
MIN
Supply voltage, V CC
Positive reference voltage, VREF + (see Note 2)

Negative reference voltage, VREF _ (see Note 21
Differential reference voltage, VREF + -

High-level input voltage, VIH
low-level input voltage, Vil

VREFClock input
All other digital inputs

NOM

MIN

NOM

MAX

UNIT

4.75

5

5.5

4.75

5

5.5

V

2.5

vee

vee+ O.1

2.5

vee

vee+ 0.1

V

-0.1

0

2.5

-0.1

0

2.5

V

1

vee

Vee+ 0.2

1

Vee

vee+ 0.2

V

Vee - 0.8
2

Vee -0.8
2

Any digital input

Clock frequency, fClK

TLC533A
MAX

V

0.8
0.1

2

2.048

0.1

1.048

0.8

V

1.06

MHz

75

100

ns

Address (R/W and RSI setup time, tsu(AI

100

145

ns

Data bus input setup time, tsu(busl

140

185

ns

Control (R/W, RS, and CSI hold time, th(CI

10

20

ns

Data bus input hold time, th(busl

15

20

ns

305

575

CS setup time, tsu(CSI

Pulse duration of control during read, tw(C)

3

3

Pulse duration of clock high, twH(ClKI

230

440

Pulse duration of clock low, twL(ClKI

200

410

Pulse duration, reset low, twl{reset)

ns
Clock
Cycles
ns
ns

Clock rise time, tr(ClKI

15

25

Clock fall time, tf(ClKI

16

30

Operating free-air

TLC __ AM

- 55

125

- 55

125

temperature, T A

TlC __ AI

-40

85

-40

85

ns
ns

°c

NOTE 2: Analog input voltages greater than or equal to that applied to the REF + terminal convert to all ones (111111111, while input
voltages equal to or less than that applied to the REF - terminal convert to all zeros (00000000). For proper operation, the positive
reference voltage, VREF +, must be at least 1 V greater than the negative reference voltage, VREF _. In addition, unadjusted
errors may increase as the differential reference voltage, VREF + - VREF _, falls below 4.75 V.

-1.!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-111

TLC532AM, TLC532AI
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
electrical characteristics over recommended operating free-air temperature range, VREF + = Vcc,
VREF - at ground, fCLK = 2 MHz (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

l:Iigh-level output voltage

IOH

VOL

Low-level output voltage

IOL

= -1.6 mA
= 1.6 mA

VIH

=

5.5 V

VIL

=

0

IIH
IlL
IOZ
II

High-level

Any digital or Clock input

input current

Any control input

Low-level

Any digital or Clock input

input current

Any control input

Typt

MAX

UNIT

2.4

V

V

0.4
10

p.A

1
-10

p.A

-1

Off-state (high-impedance state)

VO=VCC

output current

Vo

Analog input current (see Note 3)

VI

=0
= 0 to
= 0 to

10

p.A

-10

VCC

Leakage current between selected channel

VI

and all other analog channels

Clock input at 0 V

Input capacitance

Ci

MIN

VCC,

±500

nA

±400

nA

Digital pins 3 thru 10

4

30

Any other input pin

2

15

1.5

3

mA

1.4

2

mA

ICC+IREF+

Supply current plus reference current

VCC = VREF+
Outputs open

ICC

Supply current

VCC

=

=

5.5 V,

5.5 V

pF

NOTE 3: Analog input current is an average of the current flowing into a selected analog channe.! input during one full conversion cycle.

operating characteristics over recommended operating free-air temperature range, VREF +
VREF - at ground, fCLK = 2 MHz (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

Typt

MAX

UNIT

±0.5

LSB

Zero error (see Note 5)

±0.5

LSB

Full-scale error (see Note 5)

±0.5

LSB

Total unadjusted error (see Note 6)

±0.5

LSB

.±1

teonv

Conversion time (including channel acquisition time)

30

tacq

Ch13nnel acquisition time prior to starting conversion

10

ten

Data output enable time (see Note S)

CL

tdis

Data output disable time

CL

Data bus output

tflbus)

Vcc,

Linearity error (see Note 4)

Absolute accuracy error (see Note 7)

trlbus)

=

High impedance to high level

rise time

Low-to-high level

Data bus output

High impedance to low level

fall time

High-to-Iow level

CL
CL

=
=
=
=

50 pF, RL
50 pF, RL
50 pF, RL
50 pF, RL

=
=
=
=

3 k!l
3 k!l
3 k!l

Cycles
Clock
Cycles
250

3 k!l,

LSB
Clock

10

ns
ns

150
300
150
300

ns
ns

t Typical values are at VCC = 5 V, T A = 25°C.
NOTES: 4. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
6. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step.
This includes all errors including inherent quantization error, which is the ± O. 5 LSB uncertainty caused by the AID converters'
finite resolution.
S. If chip-select setup time, tsuICS), is less than 0.14 p's, the effective data output enable time, ten, may extend such that
tsulCS) + ten is equal to a maximum of 0.475 p.s.

TEXAS

'1.!1

INSTRUMENTS
2-112

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC533AM, TLC533AI
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS
electrical characteristics over recommended ranges Vee, VREF +, and operating free-air temperature,
VREF - at ground, feLK = 1.048 MHz (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

10H = -1.6 mA

VOL

Low-level output voltage

10L = 1.6 mA

IIH
IlL

High-level

Any digital or Clock input

input current

Any control input

Low-level

Any digital or Clock input

input current

Any control input

II

VI = 0 to VCC

Leakage current between selected channel

VI = 0 to Vcc,

and all other analog channels

Clock input at 0 V

UNIT
V

10
1
-10
-1
10

VO=VCC

Analog input current Isee Note 31

MAX
0.4

VIL = 0

Off-state Ihigh-impedance statel output current

Input capacitance

Typt

2.4

VIH = 5.5 V

10Z

Ci

MIN

-10

Va = 0

V
~A

~A

~A

±500

nA

±400

nA

Digital pins 3 thru 10

4

30

Any other input pin

2

15

1.3

3

mA

1.2

2

mA

ICC+IREF+

Supply current plus reference current

VCC = VREF+ = 5.5 V,
Outputs open

ICC

Supply current

VCC = 5.5 V

pF

NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.

operating characteristics over recommended ranges Vee, VREF +, and operating free-air temperature,
VREF - at ground, fclock = 1.048 MHz (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

Typt

MAX

UNIT

Linearity error (see Note 4)

±0.5

LSB

Zero. error Isee Note 51

±0.5

LSB

Full-scale error Isee Note 51

±0.5

LSB

Total unadjusted error Isee Note 61

±0.5

LSB

Absolute accuracy error Isee Note 7)

±1

teonv

Conversion time (including channel acquisition time)

30

tacq

Channel acquisition time prior to starting conversion

10

ten

Data output enable time Isee Note 81

CL = 50 pF, RL = 3 kO,

tdis

Data output disable time

CL = 50 pF, RL = 3 kO

Data bus output
trlbusl
tflbusl

High impedance to high level

rise time

Low-to-high level

Data bus output

High impedance to low level

fall time

High-to-Iow level

CL = 50 pF, RL = 3 kO
CL = 50 pF, RL = 3 kO

LSB
Clock
Cycles
Clock
Cycles

335
10

ns
ns

150
300
150
300

ns
ns

tTypical values are at VCC = 5 V, TA = 25°C.
NOTES: 4. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
6. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step.
This includes all errors including inherent quantization error, which is the ±0.5 LSB uncertainty caused by the AID converters'
finite resolution.
8. If chip-select setup time, tsuICS), is less than 0.14 ~s, the effective data output enable time, ten, may extend such that
tsulCS) + ten is equal to a maximum of 0.475 ~s.

TEXAS

~

INSTRUMENTS
POST OFFtCE BOX 655303 • DALLAS, TEXAS 75265

2-113

2-114

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOS™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
02799, OCTOBER 19B3- REVISED OCTOBER 1988

DW OR N PACKAGE

•

LinCMOS'· Technology

•

8-Bit Resolution AID Converter

•

Microprocessor Peripheral or Stand-Alone
Operation

(TOP VIEW)

•

On-Chip 12-Channel Analog Multiplexer

•

Built-In Self-Test Mode

•

Software-Controllable Sample and Hold

•

Total Unadjusted Error ... ± 0.5 LSB Max

•

TLC541 is Direct Replacement for Motorola
MC145040 and National Semiconductor
ADC0811. TLC540 is Capable of Higher
Speed

INPUT AO
INPUT Al
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND

VCC
SYSTEM CLOCK
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF +
REFINPUT A10
INPUT A9

FN CHIP CARRIER PACKAGE
(TOP VIEW)
~

•

u

Pinout and Control Signals Compatible with
TLC1540 Family of 10-Bit AID Converters

0

-'

0

N

« « «
TYPICAL PERFORMANCE

TLC540

Channel Acquisition Sample Time

Conversion Time
Samples per Second

2

"S

9 "s
75 x 103

Power Dissipation

6 mW

f- f- f-

TLC541

:::J :::J ::J
0. 0. 0.

3.6 "s

~ ~ ~

17 "s
40 x 103
6 mW

description

3

INPUT
INPUT
INPUT
INPUT
INPUT

A3
A4
A5
A6
A7

2

U

~

LJ.J

ut;
u>>CfJ

1 20 19

4

18

5

17

6

16

1/0 CLOCK
DATA IN
DATA OUT

15

CS

The TLC540 and TLC541 are LinCMOS'" AID
8
14
REF +
peripherals built around an 8-bit switched9 1011 1213
capacitor successive-approximation AID
00 0 OJ 0
I
converter. They are designed for serial interface
« (9
z « ~u.
«UJ
to a microprocessor or peripheral via a threefI::J
::J f-CI:
state output with up to four control inputs
0.
0. ::J
Z
~ 0.
[including independent System Clock, 1/0 Clock,
~
Chip Select (CS), and Address InputJ. A
4-MHz system clock for the TLC540 and a
2, l-MHz system clock for the TLC541 with a
design that includes simultaneous readlwrite
operation
allow
high-speed
data
transfers and sample rates of up to 75,180 samples per second for the TLC540 and 40,000 samples per
second for the TLC541 . In addition to the high-speed converter and versatile control logic, there is an onchip 12-channel analog multiplexer that can be used to sample anyone of 11 inputs or an internal "selftest" voltage, and a sample-and-hold that can operate automatically or under microprocessor control.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
The converters incorporated in the TLC540 and TLC541 feature differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises.
A switched-capacitor design allows low-error (± 0,5 LSB) conversion in 9 p's for the TLC540 and 17 p's
for the TLC541 over the full operating temperature range.
The M-suffix versions are characterized for operation from - 55 DC to 125 °C, The I-suffix versions are
characterized for operation from - 40 DC to 85 DC.
LinCMOS is a trademark of Texas Instruments Incorporated

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~C~~~~~irvar~~I~tJ~ ~!~:i~~ti~f :"O~:~:~it::s~S

not

-1!1

Copyright

© 1983, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-115

TLC540M, TLC5401, TLC541 M, TLC5411
linCMOSTM 8-BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
functional block diagram
REF+

REF-

+
,,-

r-----

-

ANALOG
INPUTS

,--1

SAMPLE
AND
HOLD

+

8-BIT
ANALOG-TO-DIGITAL
CONVERTER
(SWITCHED-CAPACITORS)

r--

12-CHANNEL
ANALOG
MULTIPLEXER

8

I
-+-1

II

8

OUTPUT
DATA
REGISTER

INPUT
ADDRESS
REGISTER

8-TO-1 DATA,
SELECTOR AND
DRIVER

r

DATA
OUTPUT

4

---+--1

SELF-TEST
REFERENCE

I

'-

4

I

ADDRE SS
INPU T

I

INPUT
MULTIPLEXER

I
I

CONTROL LOGIC
AND 1/0
COUNTERS

2

t

1/0
CLO CK

CS
SYST EM
CLOCK

operating sequence

111213141516[718
1/0
CLOCK ----{

DON'T

~I

~~~t:4:==~tc~o:n~v----+-:
(See Note

I

AI"

I

I 1

1 2

1 3

I

4151 6 1718

I'4-ACCESS~

I

CYCLE C

I

Cs L,rf_....;("'S.:.;ee:.;Nc:.O::.;t"'e.::c"-)_ _ _ _ _ _ _ _ _~~W~(~Sr------~,/-'_ _ _ _ _ _ _ _ _ _ _ _ _ _
MSB

LSB

MSB

DON'T CARE

-'1

LSB
DON'T CARE

HI-Z STATE
A7

B7
_CONVERSION DATA B--------------I••
MSB
LSB MSB

4--- PREVIOUS CONVERSION DATA A---.
MSB
(See Note B)

NOTES:

LSB MSB

A. The conversion cycle, which requires 36 System Clock periods, is initiated on the 8th falling edge of the 1/0 Clock after CS
goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, the 1/0 Clock
must remain low for at least 36 System Clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
seven bits IA6-AO) will be clocked out on the first seven 1/0 Clock falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three System Clock cycles lor less) after
a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to
clock-in address data until the minimum chip-select setup time has elapsed.

~

TEXAS
INSTRUMENTS
2-116

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CPNTROL AND 11 INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted I
Supply voltage, VCC (see Note 1)
. . . . . . . 6.5 V
Input voltage range (any input)
-0.3VtoVcC + 0.3V
Output voltage range
-0.3 V to VCC + 0.3 V
Peak input current range (any input)
....... .
±10 mA
Peak total input current (all inputs) ..
. ..... .
±30 mA
Operating free-air temperature range: TLC5401, TLC5411 ...
TLC540M, TLC541 M .
Storage temperature range . . . . . . .
. ........... .
-65°C to 150°C
Case temperature for 10 seconds: FN package. . . .
. ...... .
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package . . . . . . . 260°C
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together lunless otherwise noted).

recommended operating conditions

Supply voltage,

MIN
4.75
2.5
-0.1

Vee

Positive reference voltage, VAEF + (see Note 2)
Negative reference voltage, VREF ~ (see Note 2)
Differential reference voltage,

1

VREF + ~ VREF _ (see Note 2)
Analog input voltage (see Note 2)

a

High-level control input voltage, V[H

2

TLC54Q
NOM
5

MAX
5.5

a

Vee+ 0.1
2.5

Vec

Vee +0.2

VCC

VCC

MIN
4.75
2.5
0.1
1

a

MAX
5.5

0.8

a

V
v
V

VCC

Vee+ 0.2

v

Vcc
0.8

200

400

a

a

UNIT

vee+ 0.1
2.5

Vee

2

Low-level control input voltage, VIL
Setup time, address bits at data input

TLC541
NOM
5

V
V
V
ns

before liD CLKt, tsu(A)

Hold time, address bits after 1/0 CLKi, th(A)
Setup time,

CS low

ns

System
before clocking in first

3

3

clock

address bit, tsu(CS) (see Note 3)

cycles

System

36

~ high during conversion, twH(CS}

36

clock
cycles

a

Input/Output clock frequency, fCLKO/O}

fCLKII(OI
110
100
200
200

System clock frequency, fCLK(SYS)
System clock high, twH(SYS}
System clock low, twL(SYS)
Input/Output clock high, twH{IJO)
Input/Output clock low, twL(l/O)
System
Clock transition time
(see Note 4)

1/0
Operating free-air
temperature, T A

fCLKISYSI .,; 1048 kHz
fCLKISYSI > 1048 kHz
fCLKll/OI .,; 525 kHz
fCLKll/OI > 525 kHz
TLC540M. TLC541 M
TLC5401. TLC5411

2.048
4

30
20
100
40
125
85

-55
-40

0
fCLKII(OI
210
190
404
404

- 55
-40

1.1
2.1

MHz
MHz
ns
ns
ns
ns

30
20
100
40
125
85

ns

ns

°e

NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "1 "s (11111111), while input voltages less than that
applied to REF - convert as all "O"s (00000000). For proper operation, REF + voltage must be at least 1 V higher than REF voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three System Clock cycles (or less)
after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made
to clock-in an address until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 p,s for remote data
acquisition applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-117

TlC540M, TlC5401, TlC541 M, TlC5411
UnCMOSTM 8·BIT ANALOG·TO·DlGlTAL PERIPHERALS
WITH SERIAL CO.NTROL AND 11 INPUTS
electrical characteristics over recommended operating temperature range.
VCC = VREF + = 4.75 V to 5.5 V (unless otherwise noted>. fCLK(IIO)
TlC540 or fCLKII/O) = 1.1 MHz for TLC541
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage (pin 161

Vee = 4.75 V,

10H = 360 ~A

VOL

Low-level output voltage

Vee = 4.75 V,

IOL=1.6mA

Off-state (high-impedance state I

Vo = Vee,

es at Vee
es at Vee

10Z

output current

Vo = 0,

IIH

High-level input current

VI = Vee

IlL

Low-level input current

VI = 0

lee

Operating supply current

es at 0 V
Selected channel at Vee,

Selected channel leakage current

Unselected channel at 0 V
Selected channel at 0 V,
Unselected channel at Vee

Input capacitance

Typt

MAX

2.4
10
-10
-0.005

-2.5

~A

1.2

2.5

mA

0.4

1

-0.4

-1

I eontrol inputs

5

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pA

pA

3

~

pA

2.5

55

TEXAS

V

0.005

7

INSTRUMENTS

UNIT
V

0.4

1.3

I Analog

VREF+ = Vee,

t All typical values are at T A = 25°e.

2-118

MIN

inputs

lee + IREF Supply and reference current
ei

es at 0 V

2.048 MHz for

mA
pF

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
operating characteristics over recommended operating free-air temperature range,
VCC = VREF + = 4.75 V to 5.5 V, fCLK(lJO) = 2.048 MHz for TLC540 or 1.1 MHz for TLC541,
fCLK(SYS) = 4 MHz for TLC540 or 2_ 1 MHz for TLC541 .
PARAMETER

TlC541

TYP

MAX

MIN

TYP

MAX

UNIT

Linearity error

See Note 5

±0.5

±0.5

LSB

See Notes 2 and 6

±0.5

±0.5

LSB

Full-scale error

See Notes 2 and 6

±0.5

±0.5

LSB

Total unadjusted error

See Note 7

±0.5

±0.5

LSB

Conversion time

Total access and
conversion time
Channel acquisition time

tacq

TlC540
MIN

Zero error

Self-test output code
teonv

TEST CONDITIONS

Isample cycle)

Input A 11 address

=

1011

ISee Note 8)

01111101

10000011

1125)

1131)

01111101
1125)

10000011
1131)

See Operating Sequence

9

17

See Operating Sequence

13.3

25

~s

~s

I/O
See Operating Sequence

4

4

clock
cycles

Time output data

tv

remains valid after

10

10

ns

I/O clock!
Delay time, I/O clock!
td

to data output valid

ten

Output enable time

tdis

Output disable time

trlbus) Data bus rise time
tflbusl Data bus fall time
NOTES:

See Parameter
Measurement
Information

300

400

ns

150

150

ns

150

150

ns

300

300

ns

300

300

ns

2. Analog input voltages greater than that applied to REF + convert to all "1 "51111111111. while input voltages less than that
applied to REF - convert to all "0"5 100000000). For proper operation, REF + voltage must be at least 1 V higher than REFvoltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-119

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
PARAMETER MEASUREMENT INFORMATION
1.4 V

VCC

3kn

CL
(SEE NOTE AI

UNDER TEST
CL
(SEE NOTE A)

l'

1

1

OUTPUT

OUTPUT
TEST
UNDER TEST-. . . . .-POINT

O"~"' !":'""'' '

TEST POINT

UNDERTEST+

3kn

CL

~

(SEE NOTE A)

(SEE NOTE B)

LOAD CIRCUIT FOR
tpZH AND tpHZ

LOAD CIRCUIT FOR
td. t f • AND tf

~

(SEE NOTE B)

LOAD CIRCUIT FOR
tpZL AND tpLZ

VCC
!SO% _ _ _ _ _ 0 V

I
I
I
I

SYSTEM
CLOCK

I

I

OUTPUT
WAVEFORM 1
(SEE NOTE C)

(SEE NOTE B)

-+I tpZL I+--

-+f tPLZ

II

:

1/

VCC

I '~S_Oo/,_O_ _+:_~.k.2.0~ ____ 0V

--.I

W~~;:~~M2

~

-+I tPHZ l+-

tpZH 14--

I

I

-f90~ -

_ _ _ _ _ _ _ _ _ _ _ _ _ _... VSO%

T'

(SEE NOTE C)

~

H
---VoOv

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

1/0
CLOCK

\- -

- - -O.8V
OUTPUT

I

~

I+--td--+t
DATA
OUTPUT

I I
tf-.l ~

Xl ----------2.4V

--------'

----2.4V

- - - - O.4V

I I

-.!

~tf

VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES

A. CL ~50 pF for TLC540 and 100 pF for TLC541 .
B. ten ~ tpZH or tpZL. tdis ~ tpHZ or tpLZ'
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

~

TEXAS
INSTRUMENTS
2-120

I

----------O.BV

VOLTAGE WAVEFORM FOR DELAY TIME

NOTES:

1\

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation
The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such
functions as analog multiplexer, sample-and-hold, 8-bit AID converter, data and control registers, and control
logic. For flexibility and access speed, there are four control inputs [two clocks, chip select (CSl. and
addressJ. These control inputs and a TTL-compatible 3-state output are intended for serial communications
with a microprocessor or microcomputer. With judicious interface timing, with TLC540 a conversion can
be completed in 9 I-'s, while complete input-con version-output cycles can be repeated every 13 I-'s. With
TLC541 a conversion can be completed in 17 I-'s, while complete input-conversion-output cycles are repeated
every 25 I-'s. Furthermore, this fast conversion can be executed on any of 11 inputs or its built-in "selftest," and in any order desired by the controlling processor.
The System and 1/0 Clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for
the device. Once a clock signal within the specification range is applied to the System Clock input, the
control hardware and software need only be concerned with addressing the desired analog channel, reading
the previous conversion result, and starting the conversion by using the 1/0 Clock. The System Clock will
drive the "conversion crunching" circuitry so that the control hardware and software need not be concerned
with this task.
When CS is high, the Data Output pin is in a three-state condition and the Address Input and 1/0 Clock
pins are disabled. This feature allows each of these pins, with the exception of the CS pin, to share a
control logic point with their counterpart pins on additional AID devices when additional TLC540/541 devices
are used. In this way, the above feature serves to minimize the required control logic pins when using
multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion
and obtain the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits
for two rising edges and then a falling edge of the System Clock after a low CS transition, before
the low transition is recognized. This technique is used to protect the device against noise when
the device is used in a noisy environment. The MSB of the previous conversion result will
automatically appear on the Data Out pin.
2. A new positive-logic mUltiplexer address is shifted in on the first four rising edges of the 1/0 Clock.
The MSB of the address is shifted in first. The negative edges of these four 1/0 clock pulses shift
out the second, third, fourth, and fifth most significant bits of the previous conversion result. The
on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling
edge. The sampling operation basically involves the charging of internal capacitors to the level
of the analog input voltage.
3. Three clock cycles are then applied to the 1/0 pin and the sixth, seventh, and eighth conversion
bits are shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to the 1/0 Clock pin. The falling edge of this clock cycle
completes the analog sampling process and initiates the hold function. Conversion is then performed
during the next 36 System Clock cycles. After this final 1/0 Clock cycle, CS must go high or the
1/0 Clock must remain low for at least 36 System Clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of mUltiple
conversion, special care must be exercised to prevent noise glitches on the 110 Clock line. If glitches occur
on the 1/0 Clock line, the 1/0 sequence between the microprocessorlcontroller and the device will lose
synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise,
a valid falling edge of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
1 through 4 before the 36 System Clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.

TEXAS

-I.!}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-121

TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOS™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation (continued)
It is possible to connect the System and I/O Clock pins together in special situations in which controlling
circuitry points must be minimized. In this case, the following special points must be considered in addition
to the requirements of the normal control sequence previously described.
1. When CS is recognized by the device to be at a low level. the common clock signal is used as
an I/O Clock. WhenCS is recognized by the device to be at a high level, the common clock signal
is used to drive the "conversion crunching" circuitry.
2. The device will recognize a CS low transition only when the CS input changes and subsequently the
System Clock pin receives two positive edges and then a negative edge. For this reason, after
a CS negative edge, the first two clock cycles will not shift in the address because a low CS must
be recognized before the I/O Clock can shift in an analog channel address. Also, upon shifting in
the address, CS must be raised after the sixth I/O Clock pulse that has been recognized by the
device, so that a CS low level will be recognized upon the lowering of the eighth I/O Clock signal
that is recognized by the device. Otherwise, additional common clock cycles will be recognized
as I/O Clock pulses and will shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
sampling upon the negative edge of the fourth I/O Clock cycle, the hold function is not initiated until the
negative edge of the eighth I/O Clock cycle. Thus, the control circuitry can leave the I/O Clock signal in
its high state during the eighth I/O Clock cycle until the moment at which the analog signal must be
converted. The TLC540/TLC541 will continue sampling the analog input until the eighth falling edge of
the I/O Clock. The control circuitry or software will then immediately lower the I/O Clock signal and hold
the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.

~

TEXAS
INSTRUMENTS
2-122

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC542C, TLC5421, TLC542M
LinCMOS™ a-BIT ANALOG-TO-OIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
03194, FEBRUARY 1989-REVISED OCTOBER 1991

•

LinCMOS'" Technology

N PACKAGE
(TOP VIEW)

a-Bit Resolution AID Converter

•

INPUT AO
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT AS
INPUT A6
INPUT A7
INPUT AS
GND

Microprocessor Peripheral or Stand-Alone
Operation

•
•
•
•

On-Chip 12-Channel Analog Multiplexer
Built-in Self-Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error ... :to.S LSB Max

•

Direct Replacement for Motorola
MC145041

•
•
•

On-Board System Clock

VCC

EOC
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A10
INPUT A9

FN PACKAGE
(TOP VIEW)

End-of-Conversion (EOC) Output
Pinout and Control Signals Compatible
With TLC540 and TLC1540 Family of 10-Bit
A/D Converters
INPUT A3
INPUT A4
INPUT AS
INPUT A6
INPUT A7

TYPICAL PERFORMANCE
Channel Acquisition/Sample Time

16 !-,S

Conversion Time

20

~IS

25 x 103

Samples per Second
Power Dissipation

10mW

I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+

description
The TLC542 is a LinCMOS'" AID peripheral built
around an 8-bit switched-capacitor successiveapproximation AID converter, The device is
designed for serial interface to a microprocessor
or peripheral via a 3-state output with three inputs (including I/O CLOCK, CS (chip select), and ADDRESS
INPUT). The TLC542 allows high-speed data transfers and sample rates of up to 40,000 samples per second.
In additioin to the high-speed converter and versatile control logic, an on-chip 12-channel analog multiplexer
can sample anyone of 11 inputs or an internal "self-test" voltage, and the sample and hold is started under
microprocessor control. At the end of conversion, the end-of-conversion (EOG) output pin goes high to indicate
that conversion is complete, Detailed information on interfacing to most popular microprocessors is readily
available from the factory.
The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate
ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switchedcapacitor design allows low-error (:to.5 LSB) conversion in 20 [!s over the full operating temperature range,
The TLC542M is available in both the Nand FN plastic packages. The TLC542C is characterized for operation
from O°C to 70°C, and the TLC542M is characterized for operation from -55°C to 125°C, and the TLC5421 is
characterized for operation from -40°C to 85°C.

LinBiCMOS is a trademark of Texas Instruments Incorporated.
'PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard

warranty.

Production

processing

does

necessarily include testing of all parameters.

not

Copyright © 1991, Texas Instruments Incorporated

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-123

TLC542C, TLC5421, TLC542M
LinCMOSTM a·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
functional block diagram
REF+

REF-

8-Bit
Analog-to-Digital
Converter
(Switched-Capacitors)

Sample and
Hold

12-Channel
Analog
Multiplexer

Analog
Inputs

DATA
OUT

4

4
' - - - -__~--_l

.--_.1...._--,

2

Control Logic
and I/O
Counters

ADDRESS - - - - 1 _ - - - - - - 1
INPUT

I/O CLOCK

----.~------_>------------__I-_+--------'

CS-------.~--------------------------------~
EOC-----------------------------------------------~

operating sequence

I/O
CLOCK - - - \

I
1 . - - lacq -----+----.i..- I

I I

*- ~~~~s~ 1
I : (see Note A)

Isu(A) ..... 1

I

I

--.:

tsu(CS)---f+---t.
CS

ADDRESS
INPUT

-l

:1

I I

Access
Cycle C

I

-.I ~ tacq - - ' :

I
cony
I
I
I
I~ 121riternal System Clocks s 12 fAs

\~
: !~____________...J!:

I
I
'

i~'J I

I
I
I
-H
I
I

*

I

---.1

LS8

I
I
I
I
MS8
LS8
Don't Ca e
I
~
Don't Care
}------+-----!,,....-+I----< C3 C2 C1 co -...;.;,.,....:..:.;,.,..---I
I
HI-Z Stale I

D~~~ ~~---~\~-.l....-~
I . . _~_.
.
J
I
--.....---- PrevIous Conversion Data A ::'T
I
I

EOC

MSB
(see Nole 8)

-r')
:.

(see Nole 8)

I
I
II Id(EOC-DATA)~1
td(I/O-EOC)~
I
LSB

~~r----------'L-

tcycle

~

NOTES: A. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two riSing edges and one falling edge of the
internal system clock after CS l before responding to control input signals. The CS setup time is given by the tsu(Cs) specifications.
Therefore, no attempt should be made to clock-in an address until the minimum chip select setup time has elapsed.
B. The ouput is three-stated on CS going high or on the negative edge of the 8th I/O clock.

TEXAS'~

INSTRUMENTS
2-124

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC542C,TLC542~TLC542M

LinCMOS ™ a-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .......................................................... 6.5 V
Input voltage range (any input) .............................................. -0.3 V to Vee + 0.3 V
Output voltage range ...................................................... -0.3 V to Vee+ 0.3 V
Peak input current range (any input) ...................................................... ±20 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range: TLC542C ........................................ O°C to 70°C
TLC5421 ...................................... -40°C to 85°C
TLC5421M .................................... -55°C to 125°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package ................................. . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .................... 260°C
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

recommended operating conditions,

Vee =4.75 to 5.5 V
UNIT

MIN

NOM

MAX

4.75

5

5.5

VREF-0.1

VCC
0

VCC + 0.1

V

VREF+

V

Differential reference voltage, VREF+ - VREF- (see Note 2)

1

VCC

VCC + 0.2

V

Analog input voltage (see Note 4)

0

High·level control input voltage, VIH

2

Supply voltage, VCC
Positive reference voltage, VREF + (see Note 2)
Negative reference voltage, VREF _ (see Note 2)

VCC

V
V

low-level control input voltage, Vil

0.8

Setup time, address bits at data input before 1/0 ClK I, tsu(A)

V

V

400

ns

Hold time, address bits after I/O ClKI, th(Al

0

ns

Hold time, CS low after 8th 1/0 ClK!, th(eS)

0

ns

3.8

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)

0

Input/Output clock frequency, fClK(l/O)
Input/Output clock high, twH(l/O)

404

Input/Output clock low, twl(I/O)

404
fClK(I/O) ~ 525 kHz

1/0 Clock transition time (see Note 4)

Operating free-air temperature, TA

MHz
ns
ns
100
40

fClK(I/O) > 525 kHz
TlC542C

~s

1.1

0

ns

70

TlC5421

-40

85

TlC542M

-55

125

°c

NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all ones (11111111), while Input voltages less than that applied to
REF-convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF-. Also, thetotal unadjusted
error may increase as this differential reference voltage falls below 4.75 V
3. To minimize errors caused by noise at the Chip Select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS I before responding to control input signals. The CS setup time is given bythetsu(CS) specifications.
Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to Vil max or to rise from Vil max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 21'S for remote data acquisition applications
where the sensor and the ND converter are placed several feet away from the controlling microprocessor.

TEXAS l!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-125

TLC542C, TLC5421,. TLC542M
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
electrical characteristics over recommended operating temperature range,
Vcc =VREF+ = 4.75Vto 5.5V (unless otherwise noted), fCLK(I/O) = 1.1 MHz
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage (DATA OUT)

Vee ~4.75V,

IOH ~ -360 f1A

VOL

Low-level output voltage

Vee ~4.75V,

IOL~

Off-state (high-impedance state)

Va ~ VCC,

CS atVcc

~o,

CS atVCC

output current

Va

IIH

High-level input current

IlL

Low-level input current

VI ~ VCC
VI ~ 0

ICC

Operating supply current

es atO V

Maximum static analog reference current
into REF+
Input capacitance

VREF+ ~ Vee,

10
-10

f1A

-2.5

!lA

2

mA

- 40°C to 85°C

0.4
1

O°C to 70°C

0.4

- 40°C to 85°C

-0.4

- 55°C to 125'C

-1

VREF-~ GND

10

I Analog inputs

7

55

I Control inputs

5

15

TEXAS

2-126

2

-0.005

0.4

~

INSTRUMENTS
POST OFFICE BOX 655303 • DAl,LAS, TEXAS 75265

V
~lA

0.005

ooe to 70°C

t All tYPical values are at T A ~ 25°C.

UNIT

V

- 55°C to 125°C
Selected channel at Vec,
Unselected channel at 0 V

MAX

0.4

1.2

Selected channel leakage current

Ci

TYpt

2.4

1.6 mA

Selected channel at V CC'
Unselected channel at 0 V

IREF

MIN

J.lA

f!A
pF

TLC542C, TLC5421, TLC542M
LinCMOS™ 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
operating characteristics over recommended operating free-air temperature range,
Vcc :: VREF+ :: 4.75 to 5.5 V, fCLK(I/O) :: 1 MHZ
PARAMETER

TEST CONDITIONS

MIN

TYPt

Linearity error (see Note 5)

MAX

UNIT

±0.5

lSB

Zero error (see Note 6)

See Note 2

±0.5

lSB

Full-scale error (see Note 6)

See Note 2

±0.5

lSB

±0.5

lSB

Total unadjusted error (see Note 7)
~

Self-test output code

Input A 11 address
See Note 8

tconv

Conversion time

See operatillg sequence

20

fls

tcvcl e

Total access and conversion cycle time

See operating sequence

40

fls

tacq

Channel acquisition time (sample cycle)

See operating sequence

16

tv

Time ouput data remains valid after I/O ClK

td(IO-DATA)

Delay time, I/O ClK

See Figure 5

400

ns

td(IO-EOC)

Delay time, 8th I/O ClK

See Figure 6

500

ns

td(EOC-DATA)

Delay time, EOC t to data out (MSB)

See Figure 7

400

ns

t{ZH, tpZL

Delay time, CS

I to data out (MSB)
Delay time, CS t to data out (MSB)

See Figure 2

3.4

fls

See Figure 2

150

ns

tpHZ, tplZ

I to data output valid
I to EOC I

1011,

I See Figure 5

01111101
(126)

128

10000011
(130)

10

flS
ns

tr(EOC)

Rise time

See Figure 7

100

ns

tf(EOC)

Fall time

See Figure 6

100

ns

tr(bus)

Data bus rise time

See Figure 5

300

ns

See Figure 5
300
ns
Data bus fall time
tf(bus)
t All tYPical values are at TA ~ 25'C
NOTES: 2. Analog input voltages greater than that applied to REF + convert to all ones (11111111), while input voltages less than that applied to
REF~convert to all zeros (00000000). For proper operation, REF + must be at least 1 V higher than REF~. Also, the total unadjusted
error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between
11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A 11 analog input signal is internally generated and
is used for test purposes.

TEXAS "l1

INSTRUMENTS
POST OFF!CE BOX 655303 • DALLAS, TEXAS 75265

2~127

TLC542C, TLC5421, TLC542M
LinCMOS™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
PARAMETER MEASUREMENT INFORMATION

-f
1.4 V

kQ

Output
Under Test

CL
(see Note A)

Output
Test
Under T e s t ] l : Point

Test
Point

CL
(see Note A)

I

LOAD CIRCUIT FOR
td, t r , AND tf

3 kQ

T

LOAD CIRCUIT FOR
tpZH AND tpHZ

LOAD CIRCUIT FOR
tpZL AN D tpLZ

NOTE A: CL = 50 pF.

Figure 1. Load Circuits
~ Address---.I

I
CS

~~
______2~VT:
\-.0.8V
/!

tPZH, tpZL

~
I
I

An

DATA OUT

.

1/0 CLOCK

2~VI J-

Figure 3. Address Timing

~

2Vr---:
/ !

\- 0.8 V ! (

~II

)}

2Vn

---f

i...
....._~It-~I
th(es)

~!

~r----/ CI~'~k ~

Figure 4. CS to I/O CLOCK Timing

TEXAS

-1!1

INSTRUMENTS
2-128

I

110 _ _ _ _ _ _ _

CLOCK

10%

Figure 2. CS to Data Output Timing

tsu(es)

X=

i..- tsu(A) ~

,90%

0.4 V

I

I

I

2.4V(
----<.

CS

=X~.~V

I
~
tpHZ, tpLZ

I

I

Valid

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

th(A)

TLC542C, TLC5421, TLC542M
LinCMOS™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
PARAMETER MEASUREMENT INFORMATION
1

tl(I/O)

: . - - tr(I/O)

--'-1

I/O CLOCK

:~

td(I/O-DATA)

Iclk(I/O) - - - .

~:

tv~11

t-

2.4 V {
2.4 V
0.4 V AO.4V
~I- - - - - - - - - - - - - - - - -

DATA OUT

------------~I

~

~

tr(bus). tf(bus)

Figure 5. Data Output Timing

I/O CLOCK
/
---./

Bth
Clock \

O.BV
1

td(I/O-EOC)

1

--1!.f----~
...
I'
'1

\.i

1

2.4 V

EOC

tl(EOC)

!II~;"";""-\; 0.4V

--.-1

1.--

1 1

Figure 6. EOC Timing

~
EOC

: . - - tr(EOC)

:J.

~!1

2.4V

I
1
~ td(EOC-DATA) ..... 1

flt:--=2....,..4~V-------

1 .

DATA OUT

0.4 V

\
1

~ ValidMSB ~

Figure 7_ Data Output to EOC Timing

TEXAS

.JJ1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-129

TLC542C, TLC5421, TLC542M
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation
The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as
analog multiplexer, sample and hold, 8-bit NO converter, data and control registers, and control logic. Three
control inputs (I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access
speed. These control inputs and a TTL-compatible 3-state output are intended for serial communications with
a microprocessor or microcomputer. With judicious interface timing, the TLC542 can complete a conversion in
20 !-Is, while complete input-conversion-output cycles can be repeated every 40 !-Is. Futhermore, this fast
conversion can be executed on any of 11 inputs or its built-in "self-test" and in any order desired by the co~trolling
processor.
When CS is high, the DATA OUT pin is in a 3-state condition, and the ADDRESS INPUT and I/O CLOCK pins
are disabled. When additional TLC542 devices are used, this feature allows each of these pins, with the
exception of the CS pin, to share a control logic point with their counterpart pins on additional AID devices. Thus,
this feature minimizes the control logic pins required when using multiple NO devices.
The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the
conversion result. A normal control sequence is as follows:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two
riSing edges and then a falling edge of the internal system clock before recognizing the low CS transition.
The MSB of the result of the previous conversion automatically appears on the DATA OUT pin.
2. On the first four rising edges of the I/O CLOCK, a new positive-logic multiplexer address is shifted in, with
the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the
second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-chip
sample and hold begins sampling the newly addressed analog input after the fourth falling edge ofthe I/O
CLOCK. The sampling operation basically involves charging the internal capacitors to the level of
the analog input voltage.
3. Three clock cycles are applied to the I/O CLOCK pin and the sixth, seventh, and eighth conversion bits are
shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to the I/O CLOCK pin. The falling edge of this clock cycle initiates a
12-system clock (= 12 !-Is) additional sampling period while the output is in the high-impedance state.
Conversion is then performed during the next 20 !-Is. Afterthis final I/O CLOCK cycle, CS must go high or
the I/O CLOCK must remain low for at least 20 !-Is to allow for the conversion function.
CS can be kept low during periods of multiple conversion. If CS is taken high, it must remain high until the end
of conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion
process.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1
through 4 before the 20-!-Is conversion time has elapsed .. Such action yields the conversion result of the previous
conversion and not the ongoing conversion.
The end-of-conversion (EOG) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent
low-to-high transition of EOC indicates the A/D conversion is complete and the conversion is ready for transfer.

TEXAS

-1!1

INSTRUMENlS
2-130

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC545M, TLC5451, TLC545C, TLC546M, TLC5461, TLC546C
LinCMOSTM 8-BIT ANALOG-TO-DiGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
02850, DECEMBER 1985-REVISED SEPTEMBER 1988
N DUAL-IN-L1NE PACKAGE
(TOP VIEWI

•

LinCMOS" Technology

•

8-Bit Resolution AID Converter

•

Microprocessor Peripheral or Stand-Alone
Operation

•

On-Chip 20-Channel Analog Multiplexer

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

•

Built-In Self-Test Mode

•

Software-Controllable Sample and Hold

•

Total Unadjusted Error, . , ± 0,5 LSB Max

•

Timing and Control Signals Compatible with
8-Bit TLC540 and 10-Bit TLC 1540 AID
Converter Families
TYPICAL PERFORMANCE

TL545

Channel Acquisition Time

1.5

Conversion Time

Sampling Rate
Power Dissipation

~s

9 ~s
76 x 10 3
6 mW

AO
A1
A2
A3
A4
A5
A6

VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REF-

INPUT A7
INPUT A8
INPUT A9
INPUT A10
INPUT A11
INPUT A12
GND

TL546
2.7 ~s
17 ~s
40 x 10 3

INPUT
INPUT
INPUT
INPUT
INPUT

A18
A17
A16
A15
A14

INPUT A13

FN CHIP CARRIER PACKAGE
(TOP VIEWI

6mW

~

U
0
-'

description
MN

The TLC545 and TLC546 are LinCMOS'· AID
peripherals built around an 8-bit switchedcapacitor successive-approximation AID
converter. They are designed for serial interface
to a microprocessor or peripheral via a 3-state
output with up to four control inputs [including
independent System Clock, 1/0 Clock, Chip
Select (CS), and Address InputJ. A 4-MHz
system clock for the TLC545 and a 2.1-MHz
system clock for the TLC546 with a design that
includes simultaneous readlwrite operation
allowing high-speed data transfers and sample
rates of up to 76,923 samples per second for the
TLC545, and 40,000 samples per second for the
TLC546. In addition to the high-speed converter
and versatile control logic, there is an on-chip
20-channel analog multiplexer that can be used
to sample anyone of 19 inputs or an internal
"self-test" voltage, and a sample-and-hold that
can operate automatically or under
microprocessor control.

~O

U~

<1:<1: <1:<1:

:2'U

l- I- 1-1-

U~ U

::;)

::;)

::;)::;)

ll. ll. ll.ll.

LJ.Jg

U>- 0
~ ~ ~~ >CIl::;;

4 3 2
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT A8
INPUT A9
INPUT A10

1 28 2726
25
24

5
6
7
8
9
10
11

23
22
21
20
19

ADDRESS INPUT
DATA OUT
REF+
REFINPUT A18
INPUT A17

12131415161718
OM ' 525 kHz
TLC545M, TLC546M

40

40

-55

125

-55

125

TLC5451, TLC5461

-40

85

-40

85

0

70

0

70

fClK(SYS)

1048 kHz

TlC545C, TLC546C
NOTES:

ns
ns

°C

2. Analog input voltages greater than that applied to REF + convert as all "1 "s (11111111), while input voltages less than that
applied to REF- convert as all "O"s (00000000). As the differential reference voltage decreases below 4.75 V, the total
unadjusted error tends to increase.
3. To minimize errors caused by noise at the Chip Select input, the internal circuitry waits for three system clock cycles (or less)
after a chip select falling edge or rising edge is detected before responding to control input signals. Therefore, no attempt
should be made to clock-in address data until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from V,H min to VIL max or to rise from V,L max to V,H min. In
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 p,s for remote data
acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

~

TEXAS
INSTRUMENTS
2-134

ns
30

30

fCLKISYS) '" 1048 kHz

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC545M. TLC5451. TLC545C. TLC546M. TLC5461. TLC546C
linCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
electrical characteristics over recommended operating temperature range,
VCC = Vref + = 4.75 V to 5.5 V (unless otherwise noted). fCLK(l/O) = 2.048 MHz for TLC545
or fCLK(lfO) = 1.1 MHz for TLC546
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage (pin 24)

Vee

VOL

low-level output voltage

Vee

~

IIH

High-level input current

III

Low·level input current

= 4.75
Vo = Vee,
Vo = 0,
VI = Vee
VI = 0

lee

Operating supply current

es at 0 V

Off-state (high-impedance state)
10Z

output current

V,

10l

=

Typt

MIN

10H ~ -360 pA

4.75 V.

es at Vee

10

es at Vee

-10

ei

Input capacitance

2.5
-2.5

pA

1.2

2.5

mA

0.4

1

-0.4

-1

t All typical values are at T A

=

Vref+

=

es at 0 V

Vee,

pA

pA

Selected channel at 0 V.

I Analog inputs
I eontrol inputs

pA

0.005

Unselected channel at Vee
Supply and reference current

V

-0.005

Selected channel at Vee,

lee + Iref

UNIT
V

0.4

3.2 mA

Unselected channel at 0 V

Selected channel leakage current

MAX

2.4

1.3

3

7

55

5

15

mA
pF

25°e.

operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.75 V to 5.5 V, fCLK(l/O) = 2.048 MHz for TLC545 or 1.1 MHz for
TLC546, fCLK(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546
PARAMETER

TLC545
MIN

TYP

MIN

TYP

MAX

UNIT

Linearity error

See Note 5

±0.5

±0.5

lSB

See Note 6

±0.5

±0.5

lSB

Full-scale error

See Note 6

±0.5

±0.5

LSB

Total unadjusted error

See Note 7

±0.5

±0.5

LSB

Conversion time

Total access and

Input A 19 address = 10011
(See Note 8)

01111101

10000011

01111101

10000011

(125)

(131)

(125)

(131)

See Operating Sequence

9

17

See Operating Sequence

13

25

conversion time

Channel acquisition
tacq

TLC546
MAX

Zero error

Self-test output code

tconv

TEST CONDITIONS

ps
ps

1/0
See Operating Sequence

3

time (sample cycle)

3

clock
cycles

Time output data
tv

10

remains valid after

ns

10

1/0 clock!
Delay time, 1/0 clock!
td

to data output valid

ten

Output enable time

tdis

Output disable time

tr(bus) Data bus rise time
tf(bus) Data bus fall time
NOTES:

See Parameter

Measurement
Information

300

400

ns

150

150

ns

150

150

ns

300

300

ns

300

300

ns

5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A 19 analog input Signal is internally generated
and is used for test purposes.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-135

TLC545M, TLC5451, TLC545C, TLC546M, TLC5461, TLC546C
linCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
PARAMETER MEASUREMENT INFORMATION
VCC

1.4 V

UNDER TEST
CL
(SEE NOTE A)

OUTPUT
TEST
UNDER TEST-.....~-POINT
CL
(SEE NOTE A)

1

I

OUTPUT

3kn

!":" "'N,

0"""

TEST POINT

UNDERTEST+

3kn

CL
(SEE NOTE A)

~

(SEE NOTE B)

(SEE NOTE B)

l'

LOAD CIRCUIT FOR
td. t r • AND tf

~

LOAD CIRCUIT FOR
tpZL AND tpLZ

LOAD CIRCUIT FOR
tpZH AND tpHZ

f

\\

VCC
SO

% _____ 0 V

1

I
I

SYSTEM
CLOCK

I
I

,
---+I

tPZL!4-

I

~ tPLZ

I

WAVEFORM 1
(SEE NOTE C)

1

(SEE NOTE B)

I

I

-..,11----'

\.._ _ _

~ tpZH I+-

l'
I

OUTPUT
WAVEFORM 2
(SEE NOTE C) _ _ _ _ _ _ _ _ _ _ _ _---'

VCC

y,:.1

.SO%

1

j4-

I

- - - - - - - - - - - + 1--',

OUTPUT

~ tPHZ

10-::' _

-

-

_

0V

-

-

VOH

*I

s~o

\::900/.0 -

-

V"

_____ 0 V

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

1/0
CLOCK

OUTPUT~

\-----0.8V

I

x'

I4-td~

DATA
OUTPUT

_ _ _ _ _- - J

I I
tr+j
----------2.4V

----2.4V

- - - - 0.4V

I I

-.!

j4-tf

VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES

= 50 pF for TLCS45 and 100 pF for TLC546
B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

A. CL

TEXAS

~

INSTRUMENTS
2-136

I

----------0.8V

VOLTAGE WAVEFORM FOR DELAY TIME

NOTES:

~

1\

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC545M, TLC5451, TLC545C, TLC546M, TLC5461, TLC546C
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
principles of operation
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such
functions as system clock, sample-and-hold, 8-bit A/D converter, data and control registers, and control
logic. For flexibility and access speed, there are four control inputs; Chip Select (CS), Address Input, I/O
clock, and System clock. These control inputs and a TTL-compatible 3-state output facilitate serial
communications with a microprocessor or microcomputer. The TLC545 and TLC546 can complete
conversions in a maximum of 9 and 17 p's respectively, while complete input-conversion-output cycles
can be repeated at a maximum of 13 and 25 p's, respectively.
The System and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for
the device. Once a clock signal within the specification range is applied to the System clock input, the
control hardware and software need only be concerned with addressing the desired analog channel, reading
the previous conversion result, and starting the conversion by using the I/O clock. The System clock will
drive the "conversion crunching" circuitry so that the control hardware and software need not be concerned
with this task.
When CS is high, the Data Output pin is in a high-impedance condition, and the Address Input and I/O
Clock pins are disabled. This feature allows each of these pins, with the exception of the CS, to share
a control logic point with their counterpart pins on additional A/D devices when additional TLC545/TLC546
devices are used. Thus, the above feature serves to minimize the required control logic pins when using
multiple A/D devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion
and obtain the conversion result. A normal control sequence is:
1.

2.

3.
4.

CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits
for two rising edges and then a falling edge of the System clock after a CS transition before the
transition is recognized. The MSB of the previous conversion result will automatically appear on
the Data Out pin.
A new positive-logic multiplexer address is shifted in on the first five rising edges of the I/O clock.
The MSB of the address is shifted in first. The negative edges of these five I/O clocks shift out
the 2nd, 3rd, 4th, 5th, and 6th most significant bits of the previous conversion result. The onchip sample-and hold begins sampling the newly addressed analog input after the 5th falling edge.
The sampling operation basically involves the charging of internal capacitors to the level of the
analog input voltage.
Two clock cycles are then applied to the I/O pin and the 7th and 8th conversion bits are shifted
out on the negative edges of these clock cycles.
The final 8th clock cycle is applied to the I/O clock pin. The falling edge of this clock cycle completes
the analog sampling process and initiates the hold function. Conversion is then performed during
the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O clock
must remain low for at least 36 system clock cycles to allow for the conversion function.

CS can be kept low during periods of multiple conversion. When keeping CS low during periods of mUltiple
conversion, special care must be exercised to prevent noise glitches on the I/O Clock line. If glitches occur
on the I/O Clock line, the I/O sequence between the microprocessor/controller and the device will lose
synchronization. Also, if CS is taken high, it must remain high until the end of conversion. Otherwise,
a valid falling edge of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
1 through 4 before the 36 system clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-137

TLC545M, TLC5451, TLC545C, TLC546M, TLC5461, TLC546C
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
principles of operation {continued)
It is possible to connect the system and I/O clocks together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the
requirements of the normal control sequence previously described.
1. When CS is recognized by the device to be at a low level, the common clock signal is used
as an I/O clock. When the CS is recognized by the device to be at a high level, the common
clock signal is used to drive the "conversion crunching" circuitry.
2. The device will recognize a CS transition only when the CS input changes and subsequently
the system clock pin receives two positive edges and then a negative edge. For this reason,
after a CS negative edge, the first two clock cycles will not shift in the address because a
low CS must be recognized before the I/O clock can shift in an analog channel address. Also,
upon shifting in the address, CS must be raised after the 6th I/O clock, which has been
recognized by the device, so that a CS low level will be recognized upon the lowering of the
8th I/O clock signal recognized by the device. Otherwise, additional common clock cycles will
be recognized as I/O clocks and will shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
sampling upon the negative edge of the 5th I/O clock cycle, the hold function is not initiated until the negative
edge of the 8th I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state
during the 8th I/O clock cycle, until the moment at which the analog signal must be converted. The
TLC545/546 will continue sampling the analog input until the 8th falling edge of the I/O clock. The control
circuitry or software must then immediately lower the I/O clock signal to initiate the hold function at the
desired point in time and to start conversion.
Detailed information on interfacing to most popular microprocesors is readily available from the factory.

TEXAS . "
INSTRUMENTS
2-138

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548, TLC549
LinCMOSTM 8-BIT ANALOG-TO-DlGlTAL
PERIPHERAL WITH SERIAL CONTROL
02816. NOVEMBER 1983- REVISED OCTOBER 1988

D OR P PACKAGE

•

LinCMOS" Technology

•

Microprocessor Peripheral or Stand-Alone
Operation

(TOP VIEW)

•

8-Bit Resolution A/D Converter

•

Differential Reference Input Voltages

•

Conversion Time . . . 17 fJ-s Max

•

Total Access and Conversion Cycles Per Second
TLC548 ... up to 45,500
TLC549 ... up to 40,000

•

On-Chip Software-Controllable Sample-and-Hold

± 0.5

REF+[JB
7
ANALOG IN 2
REF 3
6
GND 4
5

VCC
I/O CLOCK
DATA OUT
CS

•

Total Unadjusted Error ...

•

4-MHz Typical Internal System Clock

LSB Max

•

Wide Supply Range ... 3 V to 6 V

•

Low Power Consumption ... 6 mW Typ

•

Ideal for Cost-Effective, High-Performance Applications Including Battery-Operated Portable
Instrumentation

•

Pinout and Control Signals Compatible with the TLC540 and TLC545 8-Bit A/D Converters and with
the TLC 1540 10-Bit A/D Converter

description
The TLC548 and TLC549 are LinCMOS'" A/D peripheral integrated circuits built around an 8-bit switchedcapacitor successive-approximation ADC. They are designed for serial interface with a microprocessor
or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use only the
Input/Output Clock (I/O Clock) input along with the Chip Select (CS) input for data control.
The maximum I/O clock input frequency of the TLC548 is guaranteed up to 2.048 MHz, and the I/O clock
input frequency of the TLC549 is guaranteed to 1.1 MHz. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at
4 MHz and requires no external components. The on-chip system clock allows internal device operation
to proceed independently of serial input/output data timing and permits manipulation of the TLC548 and
TLC549 as desired for a wide range of software and hardware requirements. The I/O Clock together with
the internal system clock allow high-speed <;lata transfer and conversion rates of 45,500 conversions per
second for the TLC548, and 40,000 conversions per second for the TLC549.
Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit
that can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation
from logic and supply noises. Design of the totally switched-capacitor successive-approximation converter
circuit allows conversion with a maximum total error of ± O. 5 least significant bit (LSB) in less than 17 fJ-s.
The TLC548M and TLC549M are characterized for operation over the temperature range of - 55°C
to 125°C. The TLC5481 and TLC5491 are characterized for operation from - 40°C to 85 DC. The TLC548C
and TLC549C are characterized for operation from O°C to 70°C.

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documents contain inlDrmatiDn
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not

necessarily include testing of all parameters.

Copyright © 1983, Texas Instruments Incorporated

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-139

TLC548, TLC549
LinCMOSTM 8-BIT ANALOG·TO·DlGITAL
PERIPHERAL WITH SERIAL CONTROL
functional block diagram
REF+
REFANALOG
INPUT

(1)
(3)

J!L,

SAMPLE
AND
HOLD

-

I

I

INTERNAL
SYSTEM
CLOCK

ES
I/O CLOCK

a-BIT
ANA,LOG-TODIGITAL
CONVERTER
(SWITCHEDCAPACITORS)

-

OUTPUT
DATA
REGISTER

a
I

r+--

a-TO'1 DATA
SELECTOR
AND
DRIVER

~

DATA
OUTPUT

I

f---<

-

(5)

a

f-+-

(7)

CONTROL
LOGIC
AND
OUTPUT
COUNTER

i--

operating sequence
5 \ 6 \ 7
I/O
CLOCK---{

I

....

tsu(CSI~

ACCESS
CYCLE B

I

\a

!-~__~D~O~N'~T~'~~~CA~R~E,-~~,~
~jl

14- SAMPLE -+If----:-:_tconv ~
CYCLE B

I

_

14---.!-,

(See Note Al

I

I

ACCESS ---+t
CYCLE C

I

SAMPLE

I

If- CYCLE C 41

tsu(CS)

CSL.,:
:~,
I -----------------!_twH(CSI~

,f---------------'I

I

I
I

HI-Z STATE

DATA I
OUTJ"'f

I
I
I

I

I
I
'-"PREVIOUS CONVERSION DATA A--.{
ten~ MSB
LSB MSB
(See Note Bl

I

87
I I
I _CONVERSION DATA B - - 4 I
LSB
MSB
ten~ ~SB

NOTES: A, The conversion cycle, which requires 36 internal system clock periods (17 ~s maximum), is initiated with the 8th I/O clock
pulse trailing edge after CS goes low for the channel whose address exists in memory at the time,
8, The most significant bit (A71 will automatically be placed on the DATA OUT bus after CS is brought low, The remaining seven
bits (A6-AO) will be clocked out on the first seven I/O clock falling edges, 87-80 will follow in the same manner,

~

TEXAS
INSTRUMENTS
2-140

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548, TLC549
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL
PERIPHERAL WITH SERIAL CONTROL
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 6.5 V
Input voltage range at any input ... .
-0.3 V to VCC+ 0.3 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V
Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ....... ± 10 mA
Peak total input current range (all inputs) . . . . . . . . . . . . . . . . . . . . . . . .
±30 mA
Operating free-air temperature range (see Note 2): TLC548M, TLC549M
-55°C to 125°C
TLC5481, TLC5491 .
-40°C to 85°C
TLC548C, TLC549C ....... . . .. O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:

1. All voltage values are with respect to the network ground terminal with the REF - and GND terminal pins connected together,
unless otherwise noted.
2. The 0 package is not recommended below - 40 °e.

recommended operating conditions
TlC548
Supply voltage, VCC
Positive reference voltage, VREF + (see Note 3)

MIN

NOM

3

5

2.5

Negative reference voltage, VREF _ (see Note 3)

-0.1

TlC549
MIN

NOM

MAX

6
VCC VCC+ O.1

3

5

6

V

2.5

VCC VCC+O.1

V

2.5

-0.1

0

Differential reference voltage, VREF +, VREF _ (see Note 3)

1

VCC VCC+0.2

1

Analog input voltage (see Note 3)

0

VCC

0

High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)

2

low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)
Input/output clock frequency, fClKII/O)
(for VCC = 4.75 V to 5.5 V)

V

VCC VCC+0.2
VCC

V

2.048

0

V
V

0.8

V

1.1

MHz

404

ns

200

404

ns

100

(for Vce = 4.75 V to 5.5 V)

(for VCC = 4.75 V to 5.5 V)

2.5

200

Input/output clock transition time, ttli/O) (see Note 4)

Duration of es input high state during conversion, twH(CS)

0

2
0.8

0

Input/output clock high, twH(I/O) (for VCC = 4.75 V to 5.5 V)
Input/output clock low, twl(I/O) (for VCC - 4.75 V to 5.5 V)

UNIT

MAX

100

ns

17

17

I'S

1.4

1.4

I's

Setup time, CS low before first I/O clock, tsu(CS)
(for VCC = 4.75 V to 5.5 V) (see Note 5)
Operating free-air temperature, T A

TlC548M, TLC549M

-55

125

-55

TlC5481, TlC5491

-40

85

-40

85

0

70

0

70

TLC548C, TLC549C

125

DC

NOTES: 3. Analog input voltages greater than that applied to REF + convert to all ones (111111111, while input voltages less than that
applied to REF - convert to all zeros (00000000). For proper operation, the positive reference voltage VREF +, must be at
least 1 V greater than the negative reference voltage VREF _ . In addition, unadjusted errors may increase as the differential
reference voltage VREF + - VREF _ falls below 4.75 V.
4. This is the time required for the input/output clock input signal to fall from VIH min to VIL max or to rise from Vil max to
VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 I's
for remote data acquisition applications in which the sensor and the ADC are placed several feet away from the controlling
microprocessor.
5. To minimize errors caused by noise at the es input, the internal circuitry waits for two rising edges and one falling edge of
internal system clock after CS" before responding to control input signals. This CS set-up time is given by the ten and tsu(eS)
specifications.

"'!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-141

TLC548, TLC549
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL
PERIPHERAL WITH SERIAL CONTROL
electrical characteristics over recommended operating free"air temperature range,
VCC = VREF + = 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) = 2.048 MHz for TLC548
or 1.1 MHz for TLC549
PARAMETER

TEST CONDITIONS

=

MIN

VOH

High-level output voltage

Vee = 4.75 V,

10H

VOL

Low-level output voltage

Vee - 4.75 V,

10L - 3.2 rnA

Off-state Ihigh-impedance

Vo

state) output current

Vo

10Z

= Vee,
= 0,

-10

VI - Vee

Low-level input current, control inputs

VI - 0

Analog channel on-state input

Analog input at Vee

UNIT
V

0.4

es at Vee

High-level input current, control inputs

V
V

0.005

2.5

/LA

-0.005

2.5

/LA

0.4

1

/LA

current, during sample cycle

Analog input at 0 V

-0.4

-1

Operating supply current

es at 0 V

1.8

2.5

rnA

VREF+ - Vee

1.9

3

rnA

7

55

5

15

lee + IREF Supply and reference current
ei

MAX

10

IlL

lee

Typt

2.4

es at Vee

IIH

Ilion)

.,.360/LA

Input capacitance

I Analog

inputs

I eontrol inputs

pF

operating characteristics over recommended operating free·air temperature range,
VCC = VREF + = 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) = 2.048 MHz for TLC548
or 1.1 MHz for TLC549
PARAMETER

tconv

MIN

TLC548
Typt

MAX

MIN

TLC549
Typt

MAX

UNIT

Linearity error

See Note 6

±0.5

±0.5

LSB

Zero error

See Note 7

±0.5

±0.5

LSB

Full-scale error

See Note 7

±0.5

±0.5

LSB

Total unadjusted error

See Note 8

±0.5

±0.5

LSB

Conversion time

See Operating Sequence

8

17

12

17

Total access and conversion time

See Operating Sequence

12

22

19

25

Channel acquisition time
tacq

TEST CONDITIONS

Isample cycle)

/Ls
/LS
I/O

See Operating Sequence

4

4

clock
cycles

Time output data remains
tv

Delay time to data
td

10

valid after I/O clock I
output valid

ten

Output enable time

tdis

Output disable time

tr(bus) Data bus rise time
tflbus) Data bus fall time

ns

10

I/O clocU

300

400

ns

See Parameter

1.4

1.4

/LS

150

150

Measurement Information

ns

300

300

ns

300

300

ns

tAli typicals are at Vee = 5 V, T A = 25°e.
NOTES: 6. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
7. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
8. Total unadjusted error is the sum of linearity, zero, and full-scale errors.

TEXAS

-I!}

INSTRUMENTS
2-142

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548, TLC549
LinCMOSTM 8-BIT ANALOG-TO-DiGITAL
PERIPHERAL WITH SERIAL CONTROL
PARAMETER MEASUREMENT INFORMATION

1.4 V

CL
(SEE NOTE A)

OUTPUT
TEST
UNDER TEST-......-POINT
CL
(SEE NOTE A)

1

1

OUTPUT
UNDER TEST

3kn

UNDERTEST+
CL
(SEE NOTE A) ~

3kn

~

(SEE NOTE B)

(SEE NOTE B)

l'

LOAD CIRCUIT FOR

vI:,:"" ""N'

OW"'
TEST POINT

LOAD CIRCUIT FOR
tpZL AND tPLZ

LOAD CIRCUIT FOR
tpZH AND tpHZ

~.

VCC

~,-5_00_YO

cs

_ _ _ _ _ _ _ _ _ _5_0°.JYoL _ _ _ _ _ _ _ _ _ _ _ _ 0 V

)

I

j+-- tPLZ ----.!

j+--tPZL ~

OUTPUT
WAVEFORM 1
(SEE NOTE C)

---~----...,. I _

I

VCC

i
,\:0%
j.---tPZH~

OUTPUT

I

:

¥;------VOL

_ - - - - - - . : . : - - - - -....

WAVEFORM 2 _ _ _ _ _ _ _ _ _
(SEE NOTE C)

-J~I
l' 50%
.

VCC

_ _ _ _ --VOH

:
7\:0%
I+-- ---+I - - - I

tpHZ

0 V

(SEE NOTE B)
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

1/0
CLOCK

I

I4- t d---+l
DATA

X'

OUTPUT _ _ _ _ _..J

K

OUTPUT~

\ - - - - -O.BV

----2.4V

I

tr-.l

- - - - O.4V

I I

I I

-.t

I+-

j4-tf

----------2.4V
----------O.8V
/

VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES

VOLTAGE WAVEFORM FOR DELAY TIME

NOTES:

A. CL = 50 pF for TLC548 and 100 pF for TLC549; CL includes jig capacitance.
B. ten = tpZH or tpZL, tdis = tpHZ or tpLZ·
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-143

TLC548, TLC549
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL
PERIPHERAL WITH SERIAL CONTROL
PRINCIPLES OF OPERATION
The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and
access speed, there are two control inputs: I/O Clock and Chip Select (CS). These control inputs and a TTLcompatible three-state output facilitate serial communications with a microprocessor or minicomputer. A
conversion can be completed in 17 p's or less, while complete input-con version-output cycles can be repeated
in 22 P.s for the TLC548 and in 25 p'S for the TLC549.
The internal system clock and I/O clock are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Due to this independence and the internal generation of the system clock, the control hardware and software
need only be concerned with reading the previous conversion result and starting the conversion by using the
I/O clock. In this manner, the internal system clock drives the "conversion crunching" circuitry so that the control
hardware and software need not be concerned with this task.
When CS is high, the data output pin is in a high-impedance condition and the I/O clock pin is disabled. This
CS control function allows the I/O Clock pin to share the same control logic point with its counterpart pin when
additional TLC548 and TLC549 devices are used. This also serves to minimize the required control logic pins
when using multiple TLC548 and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and
obtain the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for
two rising edges and then a falling edge of the internal system clock after a CSt before the transition
is recognized. However, upon a CS rising edge, DATA OUT will go to a high-impedance state within
the tdis specification even though the rest of the Ie's circuitry will not recognize the transition until
the tsu(CS) specification has elapsed. This technique is used to protect the device against noise when
used in a noisy environment. The most significant bit (MSB) of the previous conversion result will initially
appear on the DATA OUT pin when CS goes low.
2. The falling edges of the first four I/O clock cycles shift out the 2nd, 3rd, 4th, and 5th most significant
bits of the previous conversion result. The on-chip sample-and-hold begins sampling the analog input
after the 4th high-to-Iow transition of the I/O Clock. The sampling operation basically involves the charging
of internal capacitors to the level of the analog input voltage.
3. Three more I/O clock cycles are then applied to the I/O pin and the 6th, 7th, and 8th conversion bits
are shifted out on the falling edges of these clock cycles.
4. The final, (the 8th), clock cycle is applied to the I/O clock pin. The on-chip sample-and-hold begins the
hold function upon the high-to-Iow transition of this clock cycle. The hold function will continue for
the next four internal system clock cycles, after which the holding function terminates and the conversion
is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the 8th I/O clock
cycle, CS must go high or the I/O clock must remain low for at least 36 internal system .clock cycles
to allow for the completion of the hold and conversion functions. CS can be kept low during periods
of multiple conversion. When keeping CS low during periods of multiple conversion, special care must
be exercised to prevent noise glitches on the I/O Clock line. If glitches occur on the I/O Clock line, the
I/O sequence between the microprocessor/controller and the device will lose synchronization. If CS
is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-Iow transition
of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1
through 4 before the 36 internal system clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.

TEXAS

-1!1

INSTRUMENTS
2-144

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548, TLC549
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL
PERIPHERAL WITH SERIAL CONTROL
PRINCIPLES OF OPERATION
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins sampling
upon the high-to-Iow transition of the 4th I/O clock cycle, the hold function does not begin until the high-to-Iow
transition of the 8th I/O clock cycle, which should occur at the moment when the analog signal must be converted.
The TLC548 and TLC549 will continue sampling the analog input until the high-to-Iow transition of the 8th
I/O clock pulse. The control circuitry or software will then immediately lower the I/O clock signal and start the
holding function to hold the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to the most popular microprocessor is readily available from Texas Instruments.

"'!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-145

2-146

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOS™ 10-81T ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
1991

D2859, DECEMBER 1

•
•
•
•
•
•
•
•

LinCMOS'" Technology

OW, J, OR N PACKAGE
(TOP VIEW)

10-Bit Resolution AID Converter
INPUT AD
INPUT A1
INPUTA2
INPUT A3
INPUT A4
INPUT AS
INPUT A6
INPUT A7
INPUT AS
GND

Microprocessor Peripheral or Stand-Alone
Operation
On-Chip 12-Channel Analog Multiplexer
Built-In Self-Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error
TLC1540: ±O.5 LSB Max
TLC1541: ±1 LSB Max

VCC

SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A1D
INPUT A9

FK OR FN PACKAGE

Pinout and Control Signals Compatible
With TLC540 and TLC549 Families of a-Bit
AID Converters

(TOP VIEW)

:.::
u

g

TYPICAL PERFORMANCE
Channel Acquisition Sample Time
Conversion Time
Samples Per Second
Power Dissipation

N~O

5.5",s

;::;::;::

21 ~s
32 x 103

::J ::J ::J U

::;;:

ill

tn

o..o..o..u>-

~~~:>({)

6mW

description

u

INPUT A3
INPUT A4
INPUT AS
INPUT A6
INPUT A7

I/O CLOCK
ADDRESS INPUT
DATA OUT

The TLC1540 and TLC1541 are LinCMOS'" NO
peripherals built around a 10-bit, switchedcapacitor,
successive-approximation
NO
REF+
converter. They are designed for serial interface to
a microprocessor or peripheral via a 3-state output
with up to four control inputs [including
independent system clock, I/O clock, chip select
(CS), and address input]. A 2, 1-MHz system clock
for the TLC1540 and TLC1541, with a design that
includes simultaneous read/write operation,
allows high-speed data transfers and sample rates of up to 32,258 samples per second. In addition to the
high-speed converter and versatile control logic, there is an on-chip, 12-channel analog multiplexer that can be
used to sample anyone of 11 inputs or an internal "self-test" voltage and a sample and hold that can operate
automatically or under microprocessor control. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
The converters incorporated in the TLC1540 and TLC1541 feature differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
switched-capacitor design allows low-error conversion (±O.5 LSB for the TLC1540, ± 1 LSB for the TLC1541)
in 21 ~s over the full operating temperature range.
The TLC1540 and the TLC1541 are available in OW, FK, FN, J, and N packages. The C~suffix versions are
characterized for operation from O°C to 70°C. The I-suffix versions are characterized for operation from -40°C
to 85°C. The M-suffix versions are characterized for operation from -55°C to 125°C.

LinCMOS is a trademark of Texas Instrumenls Incorporated.
PRODUCTION DATA infprmation is current as of publication dale.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production proces.sing does not

necessarily Include testing of all parameters.

"

.Ji1
INSTRUMENTS

Copyright © 1991, Texas Instruments Incorporated

TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-147

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOS™ 10-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
functional block diagram

ANALOG
INPUTS

2
3
4
5
6
7

10-81t
Switched-Capacitors
Analog-to-Dlgltal
Converter
12-Channel
Analog
Multiplexer

9
11
12

16 DATA
OUT

'-------1 Control Logic
and 110
Counters
ADDRESS
INPUT

17

I/O CLOCK

18

CS
SYSTEM
CLOCK

2

15
19

TEXAS •

INSlRUMENTS
2-148

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOS™ 10-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
operating sequence

Don't~

1/0
CLOCK--..,

I

'4-

I
CS - ,

II

Access
Cycle B

--.I

~

I

~ Sample -----1.~I4__ tconv-.l

I I

I

Cycle B

(

(see

I

~ Access

r'r----, (
I

I

I I

-.I

Cycle C

~ Sample

I I

I

-----.I

I

Cycle C

I

~~J----------------------------~I
~~J------------------------------~
(see Note C)
14-- twH(CS)--.I
MSB

I

LSB

I MSB

Don't Care

ADDRES~

LSB
Don't Care

INPUT
DATA --..,
OUT

.....1 - - - - Conversion Data B - - - -••

~ Previous Conversion Data - - - - - . .

MSB
(see Note B)

LSB MSB

MSB

LSB MSB

NOTES: A. The conversion cycle, which requires 44 system clock periods, is initiated on the 10th falling edge of the 1/0 clock after CS goes low
for the channel whose address exists in memory at that time. If CS is kept low during conversion, the I/O clock must remain low for
at least 44 system clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining nine bits
(AS-AD) will be clocked out on the first nine 1/0 clock falling edges.
C. To minimize errors caused by noise atthe CS input, the internal circuitry waits for three system clock cycles (or less) after a chip-select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until
the minimum chip-select setup time has elapsed.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ., ... , ....... , .. ".",.,., .. " ... ,.,....................... 6.5 V
Input voltage range (any input) .,............................................ -0,3 V to Vee + 0.3 V
Output voltage range ............. , ... , ............................. ,....... -0,3 V to Vee + 0.3 V
Peak input current (any input) ................... , ....... " .. ,.,., .. , ..................... ±10 mA
Peak total input current (all inputs) .......................... , ....... " .. ,." .............. ±30 mA
Operating free-air temperature range: TLC1540C, TLC1541 C .. , ...... , ................ , O°C to 70°C
TLC15401, TLC15411 .. " .................. , .... -40°C to 85°C
TLC1540M, TLC1541M ...................... ,. -55°C to 125°C
Storage temperature range ....................................... " .. "" ..... ,.. -65°C to 150°C
Case temperature for 60 seconds: FK package .......... , ... , .... , .. , .. " .... , .. ,........... 260°C
Case temperature for 10 seconds: FN package ., ............................ , .. " ... ,...... 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package .. ,.............. 300°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package .. ,........ 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

TEXAS

"!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-149

TlC1540C, TlC15401, TlC1540M, TlC1541C, TlC15411, TlC1541M
linCMOS™ 10-BIT ANAlOG-TO-DIGITAl PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
recommended operating conditions
MIN

NOM

MAX

4,75

5

5,5

2.5

VCC

-0.1

0

Differential reference voltage, VREF + _ VREF- (see Note 2)

1

VCC

Analog input voltage (see Note 2)

0

High-level control input voltage, VIH

2

Supply voltage, VCC
Positive reference voltage, VREF + (see Note 2)
Negative reference voltage, VREF- (see Note 2)

Low-level control input voltage, VIL
0

Input/Output clock frequency, fCLK(I/O)
System clock frequency, fCLK(SYS)

fCLK(I/O)
400

Setup time, address bits before I/O CLK!, tsu(A)

VCC+0.1
2.5

UNIT
V
V
V

VCC+0.2

V

VCC

V
V

0.8

V

1.1

MH~

2.1

MHz
ns

0

ns

3

System
clock
cycles

44

System
clock
cycles

$ystem clock high, twH(SYS)

210

ns

System clock low, twL(SYS)

190

ns

Input/Output clock high, twH(I/O)

404

ns

Input/Output clock low, twL(I/O)

404

Hold time, address bits after I/O CLK!, th(A)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)

CS high during conversion, twH(CS)

System
Clock transition time (see Note 4)
I/O

Operating free-air temperature, T A

ns

fCLK(SYS) " 1048 kHz

30

fCLK(SYS) > 1048 kHz

20
100

fCLK(I/O) " 525 kHz
fCLK(1I0) > 525 kHz
TLC1540C,TLC1541C

40
0

ns
ns

70

TLC15401, TLC15411

-40

85

TLC1540M,TLC1541M

-55

125

'C

NOTES: 2. Analog mput voltages greaterthan that applied to REF + convert as all "1"s (1111111111), while Input voltages less than that applied
to REF- convert as all "O"s (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF-voltage. Also,
the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after a
chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an
address until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 fls for remote data acquisition applications
where the sensor and the ND converter are placed several feet away from the controlling microprocessor.

TEXAS

.JJ1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOS™ 10-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
electrical characteristics over recommended operating temperature range, Vcc = VREF+ = 4.75 V
to 5.5 V (unless otherwise noted), fCLK(I/O) = 1.1 MHz, fCLK(SYS) =2.1 MHz
PARAMETER

TEST CONDITIONS

MIN

TYpt

MAX

VOH

High-level output voltage (pin 16)

Vee = 4.75 V,

IOH = 360 ~A

VOL

low-level output voltage

Vee = 4.75 V,

IOl = 3.2 mA

Vo = Vee,

es at Vee

10

VO=O,

es at Vee

-10

IOZ

Off-state (high-impedance state) output current

2.5

~A

es at 0 V

1.2

2.5

mA

Selected channel at Vee,
Unselected channel at 0 V

0.4

1

-0.4

-1

VI = 0

lee

Operating supply current

e,

Selected channel at 0 V,
Unselected channel at Vee

Input capacitance

t All typical values are at Vee

IAnalog inputs

~A

-2.5

VI = Vee

low-level input current

Supply and reference current

V

0.005

High-level input current

lee + IREF

0.4

-0.005

IIH
III

Selected channel leakage current

UNIT

V

2.4

VREF+ = Vee,

es at 0 V

I eontrol inputs

~A

!-lA

1.3

3

7

55

5

15

mA
pF

= 5 V and TA = 25'e.

TEXAS

~

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-151

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC1541I, TLC1541M
LinCMOS™ 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
operating characteristics over recommended operating temperature range, Vcc
to 5.5 V, fCLK(I/O) = 1.1 MHz, fCLK(SYS) =2.1 MHz
PARAMETER

TEST CONDITIONS

MIN

TLC1540
Linearity error

TLC1541

TLC1541

See Note 5

±1

TLC1541

±1

tconv

TLC1541

",1

",1
0111110100
(500)

Conversion time

See Operating Sequence

21

Total access and conversion time

See Operating Sequence

31

tv

Time output data remains valid after I/O clockl

td

Delay time, 1/0 clockl to data output valid

See Operating Sequence

6

I

ten

Output enable time

tdis

Output disable time

tr(bus)

Data bus rise time

tf(bus)

Data bus fall time

LSB

10

f!s
f!s
I/O
clock
cycles
ns

400
See Parameter
Measurement
Information

LSB

1000001100
(524)

Input All address = 1011 (See Note 8)

Channel acquisition time (sample cycle)

LSB

",0.5
See Note 7

Self-test output code

tacq

LSB

",0.5
See Notes 2 and 6

TLC1540
Total unadjusted error

UNIT

",0.5
See Notes 2 and 6

TLC1540
Full-scale error

.
MAX
",0.5

TLC1540
Zero error

=VREF+ =4.75 V

ns

150

ns

150

ns

300

ns

300

ns

NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all "1"s (1111111111), while Input voltages less than that applied
to REF- convert as all "O"s (0000000000). For proper operation, REF+ voltage must be at least 1 V higher than REF-voltage. Also,
the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the ND transfer characteristics.
6. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
7. Total unadjusted error comprises linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The All analog input signal is internally generated and
is used for test purposes.

TEXAS -IJ1

INSIRUMENTS
2-152

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265'

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOSTM 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
PARAMETER MEASUREMENT INFORMATION
1.4 V

Output
Under Test

~~kQ

Test Point

CL
(see Note A)

Output
Under Test

T

;rr

CL
(see Note A)

3kQ

Output
Under Test

Test Point

...L

(see Note B)

(see Note B)

LOAD CIRCUIT FOR
td, t r , AND tf

Test Point

T

CL
(see Note A)

3kQ

T

+
VCC

LOAD CIRCUIT FOR
tpZL AND tpLZ

LOAD CIRCUIT FOR
tpZH AND tpHZ

jl

r--------VCC

50%

T---------

OV

SYSTEM
CLOCK

1
1

tpZL~

1
1

Output
Waveform 1
(see Note C)

1
1

.1

i~,50%

-r!!!~

1

.1
1
1

:

tpZH
Output
Waveform 2
(see Note C)

tpLZ

1

t.,.

1

.;I

f
I

___

OV

tpHZ

~%---

50%

VCC

VOH
OV

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

I/O CLOCK

~-\:..::.::..::.
_____ _

0.4 V

I~
1

DATA
OUTPUT

.1
i

~I--------- 2.4V

Output

1

~:

td

!~O.4V

i l l 1

____){r-----------

tr

2.4 V

~ ~

~ ~

tf

0.4V
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL = 50 pF
S. ten = tpZH or tpZL, tdis = tpHZ or tpLZ'
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-153

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC15411, TLC1541M
LinCMOS™ 10-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation
The TLC1540 and TLC1541 are complete data acquisition systems on single chips. Each includes such
functions as sample and hold, 1O-bit ND converter, data and control registers, and control logic. For flexibility
and access speed, there are four control inputs: chip select (CS), address input, I/O clock, and system clock.
These control inputs and a TTL-compatible 3-state output are intended for serial communications with a
microprocessor or microcomputer. The TLC1540 and TLC1541 can complete conversions in a maximum of
21 fts, while complete input-conversion-output cycles can be repeated at a maximum of 31 fts.
The system and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the
device. Once a clock signal within the specification range is applied to the system clock input, the control
hardware and software need only be concerned with addreSSing the desired analog channel, reading the
previous conversion result, and starting the conversion by using the I/O clock. The system clock will drive the
"conversion crunching" circuitry so that the control hardware and software need not be concerned with this task.
When CS is high, the DATA OUT pin is in a 3-state condition and the address input and I/O clock pins are
disabled. This feature allows each of these pins, with the exception of the CS pin, to share a control logic pOint
with its counterpart pins on additional ND devices when additional TLC1540/1541 devices are used. In this way,
the above feature serves to minimize the required control logic pins when using multiple ND devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and
obtain the conversion result. A normal control sequence is:
1.

CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for
two rising edges and then a falling edge of the system clock after a low CS transition before the low
transition is recognized. This technique is used to protect the device against noise when the device
is used in a noisy environment. The MSB of the previous conversion result will automatically appear
on the data out pin (or "on DATA OUT").

2.

A new positive-logic multiplexer address is shifted in on the first four rising edges of the I/O clock. The
MSB of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the
second, third, fourth, and fifth most significant bits of the previous conversion result. The on-chip
sample and hold begins sampling the newly addressed analog input after the fourth falling edge. The
sampling operation basically involves the charging of internal capacitors to the level ofthe analog input
voltage.

3.

Five clock cycles are then applied to the I/O pin, and the sixth, seventh, eighth, ninth, and tenth
conversion bits are shifted out on the negative edges of these clock cycles.

4.

The final tenth clock cycle is applied to the I/O clock pin. The falling edge of this clock cycle completes
the analog sampling process and initiates the hold function. Conversion is then performed during the
next 44 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O clock must
remain low for at least 44 system clock cycles to allow for the conversion function.

CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
converSion, special care must be exercised to prevent noise glitches on the I/O clock line. If glitches occur on
the I/O clock line, the I/O sequence between the microprocessor/controller and the device will lose
synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise, a valid
falling edge of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1
through 4 before the 44 system clock cycles occur. Such action will yield the conversion result of the previous
conversion and not the ongOing conversion.

TEXAS ...,
INSTRUMENTS
2-154

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1540C, TLC15401, TLC1540M, TLC1541C, TLC1541I, TLC1541M
LinCMOSTM 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation (continued)
It is possible to connect the system and I/O clock pins together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the
requirements of the normal control sequence previously described.
1.

When CS is recognized by the device to be at a low level, the common clock signal is used as an I/O
clock. When CS is recognized by the device to be at a high level, the common clock signal is used to
drive the "conversion crunching" circuitry.

2.

The device will recognize a CS low transition only when the CS input changes and the system clock
pin subsequently receives two positive edges and then a negative edge. For this reason, after a CS
negative edge, the first two clock cycles will not shift in the address because a low CS must be
recognized before the I/O clock can shift in an analog channel address. Also, upon shifting in the
address, CS must go high after the eighth I/O clock that has been recognized by the device so that
a CS low level will be recognized on the falling edge of the tenth I/O clock signal that is recognized by
the device. Otherwise, additional common clock cycles will be recognized as I/O clock pulses and will
shift in an erroneous address.

For certain applications, such as strobing, it is necessary to start conversion at a specific point in time. This device
will accommodate these applications. Although the on-chip sample and hold begins sampling upon the falling
edge of the fourth I/O clock cycle, the hold function is not initiated until the faliling edge of the tenth I/O clock
cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the tenth I/O clock cycle
until the moment at which the analog signal must be converted. The TLC1540/TLC1541 will continue sampling
the analog input until the tenth falling edge of the I/O clock. The control circuitry or software will then immediately
lower the I/O clock signal and hold the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-155

2-156

General Purpose DACs

3-1

G)
(D

:::J

(D
"""'I

Q)

"'tJ

c:

"""'I

"C

o(f>

(D

c
o(f>

l>

3-2

AD7524
Advanced LinCMOSTM 8-BIT MUL TlPL VING
DIGITAL-TO-ANALOG CONVERTER
D3100, APRIL 1988

•
•

Advanced LinCMOS" Silicon-Gate
Technology

N PACKAGE
(TOP VIEW)

OUTl
OUT2
GND
DB7
DB6
DB5
DB4
DB3

Easily Interfaced to Microprocessors

•

On-Chip Data Latches

•

Monotonicity Over Entire AID Conversion
Range

•

Segmented High-Order Bits Ensure LowGlitch Output

•

Designed to be Interchangeable with Analog
Devices AD7524. PMI PM-7524. and Micro
Pow!!r Systems MP7524

•

RFB
REF
VDD
WR
CS
DBO
DBl
DB2

AD7524J .. , FN PACKAGE
(TOP VIEW)

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

N

~~U ~tt

Ooza:a:
3

GND
DB7
NC
DB6
DB5

KEY PERFORMANCE SPECIFICATIONS
Resolution

8 Bits

Linearity error

Y, LSB Max

Power dissipation

at VDD

~

5 V

Settling time
Propagation delay

5 mW Max

2

1 20 19
18

4

17
6

16

8

14

15

VDD
WR
NC

CS
DBO

9 10 11 12 13

100 ns Max

~

80 ns Max

C"lUN

aJ
aJ
a ~z~ a

NC - No internal connection

description

The AD7524 is an Advanced LinCMOS'M 8-bit digital-to-analog converter (DAC) designed for easy interface
to most popular microprocessors.
The AD7524 is an 8-bit mUltiplying DAC with input latches and with a load cycle similar to the "write"
cycle of a random access memory, Segmenting the high-order bits minimizes glitches during changes in
the most-significant bits. which produce the highest glitch impulse, The AD7524 provides accuracy to
% LSB without the need for thin-film resistors or laser trimming. while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, the AD7524 interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524 an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The AD7524A is characterized for operation from - 25°C to 85 °C. and the AD7524J is characterized
for operation from O°C to 70°C,
AVAILABLE OPTIONS
SYMBOLIZA nON
DEVICE

PACKAGE

OPERATING
TEMPERATURE

SUFFIXES

RANGE

AD7524A

N

~25°et085°e

AD7524J

N, FN

ooe to 70°C

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~~~~:~~i~ai~:I~~~ ~!~:i~~ti:f :llo::::~:t:~~s not

~

Copyright

© 1988, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3~3

AD7524
Advanced LinCMOS™ 8·BIT MULTIPL VING
DlGITAL·TO·ANALOG CONVERTER
functional block diagram
VDD

1( 14)
REF

R

(151

R

//

n

2R

R

2R

2R

2R

2R

(16)

liY

II

I
I

S -2

:1

I S-8

,,

,

I

I

I

I

I
I

//

(4)

(5)
DB6

(6)

Dun

(2)
DUT2

DATA LATCHES

DB7
IMSB)

(1)

I

(12)
(13)

R

:1

,
I

,

I: sf

(3)
GND

(11 )
DBO
(LSB)

DB5

'~----------~v~----------~
DATA INPUTS
operating sequence

---,I

14

tsulCS) ----~----t.j_

I

CS

~

________________~ __J

14

twIWR)---+f

I

WR

----"-\\'

-------------

/f--tsuIDI---+I

~th(D)

I
DBO-DB7

)>-------

------------«

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - O. 3 V to 17 V
Voltage between RFB and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Digital input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 "A
Operating free-air temperature range: AD7524A . . . . . . . . . . . . . . . . . . . . . . . . .. - 25°C to 85 °C
AD7524J . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1(16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260°C

~

TEXAS
INSTRUMENTS
3-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524
Advanced LinCMOS™ 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
recommended operating conditions
VDD = 5 V
MIN
NOM
MAX
Supply voltage, VDD

4.75

Reference voltage, V ref

5

5.25

VDD - 15 V
MIN
NOM
MAX
14.5

15

±10

High-level input voltage, VIH

2.4

V
V

13.5

Low-level input voltage, VIL

V

0.8

CS setup time, tsulCS)

15.5

±10

UNIT

1.5

V

40

40

ns

0

0

ns

Data bus input setup time, tsulD)

25

25

ns

Data bus input hold time, thlD)

10

10

ns

Pulse duration, WR low, twlWR)

40

40

CS hold time, thlCS)

I AD7524A
Operating free-air temperature, TAl

ns

-25

85

-25

85

0

70

0

70

AD7524J

electrical characteristics over recommended operating free-air temperature range, Vref
and OUT2 at GND (unless otherwise noted)
PARAMETER
High-level input
IIH

VI

current

=

DBO-DB7 at 0, WR
OUTl
Ilkg

and CS at 0 V,
Vref

current

DBO-OB7 at VOO,
OUT2

Quiescent
Supply current
Standby
Supply voltage sensitivity,
kSVS

Again/AVOD
Input capacitance,

Ci

DBO-OB7, WR, CS
OUT1

Co

Output

OUT2

capacitance

OUT1
OUT2

=

±10 V

DBO-OB7 at VIHmin
or VILmax
DBO-OB7 at 0 V
or VDD
AVDD
VI

~

=

10%

1

1

Full range

-10

-10

25°C

-1

-1

±400

±200

Full range
25°C

±10 V

WR and CS at 0 V,
Vref

100

=

Output leakage

= 15V
TYP
MAX
10

25°C

0

VDD
MIN

= 10 V, OUT1

10

Full range

VI ~ VOD

current
Low-level input

IlL

VDD = 5 V
MIN
TYP
MAX

TEST CONDITIONS

Full range

±50

±50

±400

±200

±50

±50

Full range

2

2

25°C

1

2

Full range

500

500

25°C

100

100

25°C

Full range

0.01

0.16

0.005

0.04

25°C

0.002

0.08

0.001

0.02

0

DBO-DB7 at 0, WR and CS at 0 V
DBO-OB7 at VOO, WR and CS at 0 V

5

5

30

30

120

120

120

120

30

Reference input impedance

5

IREF to GNO)

20

°C

UNIT
p.A
p.A

nA

mA
p.A

%/%
pF

pF

30
5

20

kO

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303' • DALLAS. TEXAS 75265

3-5

AD7524
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
operating characteristics over recommended operating free-air temperature range, Vref = 10 V, OUT1
and OUT2 at GND (unless otherwise noted)
PARAMETER

TEST CONDITIONS

Linearity error
Gain error

See Note 1

Settling time (to 1/2 LSBI

See Note 2

Propagation delay from digital input to 90%
of final analog output current

I Full range
1 25 °C

See Note 2
Vrel

=

I Full range

± 10 V (100 kHz

Feedthrough at OUT1 or OUT2

sinewavel, WR and CS at 0, \25 0C
DBO-DB7 at a

Temperature coefficient of gain

TA

=

25°C to tmin or t max

VDD = 15V
MIN
MAX

UNIT

±0.2

±0.2

%FSR

±1.4

±0.6

±1

±0.5

100

100

ns
ns

Vee = 5 V
MIN
MAX

80

80

0.5

0.5

0.25

0.25

±O.OO4

±O.OO1

%FSR

%FSR
%FSR/OC

NOTES: 1. Gain error is measured using the internal leedback resistor. Nominal Full Scale Range (FSRI = Vrel - 1 LSB.
2. OUT1 load = 100 {l, Cext = 13 pF, WR at a V, CS at 0 V, DBO-DB7 at a V to VDD or VDD to a v.

PRINCIPLES OF OPERATION
The AD7524 is an 8-bit mUltiplying D/A converter consisting of an inverted R-2R ladder, analog switches,
and data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded and these decoded bits, through a modification in the R-2R ladder, control three equally
weighted current sources. Most applications only require the addition of an external operational amplifier
and a voltage reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire
reference current, Iref, is switched to OUT2. The current source 1/256 represents the constant current
flowing through the termination resistor of the R-2R ladder, while the current source Ilkg represents leakage
currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital
input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2
and the on-state switch capacitance (120 pF maximum) appears at OUT 1. With all digital inputs low, the
situation is reversed as shown in Figure 1. Analysis of the circuit for all digital inputs high is similar to
Figure 1; however, in this case, Iref would be switched to OUT1.
Interfacing the AD7524 D/A converter to a microprocessor is accomplished via the data bus and the CS
and WR control signals. When CS and WR are both low, the AD7524 analog output responds to the data
activity on the DBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data
directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBO-DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs
are disabled regardless of the state of the WR signal.
The AD7524 is capable of performing 2-quadrant or full 4,quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively,

TEXAS

-1!1

INSTRUMENTS
3-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
PRINCIPLES OF OPERATION

}'""-R----- RFB

r----------:r:~-4I~---------

OUT1

~""25-6-~-_._-~--I-lk-g-~~=~i-----f""'-1-2-0-P-F-----

OUT2

J""'

,.."~t
Irel ---.
REF

FIGURE 1. AD7524 EQUIVALENT CIRCUIT WITH ALL DIGITAL INPUTS LOW
Vrel

VDD

RA - 2kU
ISee Note 3)

RB
.-----'v¥v---~_------------..,

DBO·DB7
~----_4~OUTPUT

CS----I
WR-----I
GND

FIGURE 2. UNIPOLAR OPERATION (2·QUADRANT MULTIPLICATION)
Vrel

VDD
20 kU

RA = 2 kll
ISee Note 3)

20 kU

DBO·DB7

10 kll

> .....---OUTPUT

CS -------I
WR - - - - - - I

FIGURE 3. BIPOLAR OPERATION (4·QUADRANT OPERATION)
NOTES:

3. RA and RB used only il gain adjustment is required.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-7

AD7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
PRINCIPLES OF OPERATION
Table 2. Bipolar (Offset Binary) Code

Table 1. Unipolar Binary Code

DIGITAL INPUT

DIGITAL INPUT
ISEE NOTE 5)
MSB

MSB

LSB

ANALOG OUTPUT

LSB

11111111

- V,e! 1255/256)

11111111

V,e! (127/128)

10000001

- V,e! 1129/256)

10000001

V,e! (1/128)

10000000

- V,e! (128/256)

01111111

- V,e! (127/256)

01111111

-V,e! (11128)

00000001

-V,e! (1/256)

00000001

-V,e! (1271128)

00000000

-V,e!

00000000
NOTES:

(SEE NO:rE 6)

ANALOG OUTPUT

~

0

10000000

- V,e!/2

0

5. LSB ~ 1/256 (V,e!)'
6. LSB ~ 1/128 (V,e!)

microprocessor interfaces

DATA BUS

00-07

Z-80A
WR

OUT1
~--------------~WR

AD7524
OUT2
CS

IORO t - - -.....--t>----i

AO-A15

DECODE
LOGIC

ADDRESS BUS

~----------------------------------~

FIGURE 4. AD7524-Z-80A INTERFACE

DATA BUS

DO-D7

N-

6800

<1>2

VMA

AO-A15

DBO-DB7

- r

OUT1

~

WR

AD7524
OUT2
CS

I

DECODE
LOGIC

tt

ADDRESS BUS

FIGURE 5. AD7524-6800 INTERFACE

..Jj}

TEXAS
INSTRUMENTS
3-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

'"
,

AD7524

Advanced LinCMOSTM 8·BIT MUl TIPl VING
DlGITAl·TO·ANAlOG CONVERTER
microprocessor interfaces (continued)
.....
A8-A15

ADDRESS BUS

-

8051
;--

,A

.....

8-BIT
LATCH

"

>
DECODE
LOGIC

>
CS

T

ALE
WR

ADO-AD7

-

OUT1
AD7524

WR

OUT2

I

n

DBO-DB7

ADDRESS/DATA BUS

.....

FIGURE 6. AD7524-8051 INTERFACE

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-9

3-10

AD7524M
Advanced linCMOSTM 8-81T MULTIPLYING
DlGITAL-TO-ANALOG CONVERTER
D3320, SEPTEMBER 1989

•
•

J PACKAGE

Advanced LinCMOS" Silicon-Gate
Technology

(TOP VIEW)

oun

Easily Interfaced to Microprocessors

•

On-Chip Data latches

•

Monotonicity Over Entire AID Conversion
Range

•
•

RFB
REF

OUT2

Segmented High-Order Bits Ensure lowGlitch Output

GND

VDD

DB7
DB6

WR
CS

DB5

DBO

DB4

DB1

DB3

DB2

Designed to be Interchangeable with Analog
Devices AD7524, PMI PM-7524, and Micro
Power Systems MP7524

FK PACKAGE
(TOP VIEW)
N~

•

~~ufftb

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with SMJ320
KEY PERFORMANCE SPECIFICATIONS
Resolution

8 Bits

Linearity error

Y, LSB Max

Power dissipation

at VDD

=

5 V

OOZa:a:
3

100 ns Max

Propagation delay

80 ns Max

1 20 19
18

VDD

DB7

17

WR

16

NC

NC

6

DB6

15

CS

DB5

14

DBO

5 mW Max

Settling time

2

GND

9 1011 12 13

'

2R

2R

2R

2R

2R

(161

I>S-8

)

II

:f :1 ~:Y
S-1

I
I

I

I

I

S-2

I

I

I

I
/

I

(11

I

I

(121
(131

R

:1

(21

:

DATA LATCHES

I

(31

J

~r

OUT1
OUT2

GND

4

(41

151

DB7
IMSBI

DB6

161

1111
DBO
ILSBI

DB5

\~----------~v~----------'
DATA INPUTS
operating sequence

--""""'\,1

tsu
CS
----~--tol--

14
I

CS

WR

--__

~

________________

~
1

~--J

tw(WRI----+t

~,I

_ _ _ _ _..J

~tsuIDI--+I

~thlDI

I
DBO-DB7

)~------

------------«

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 17 V
Voltage between RFB and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Digital input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V
Reference voltage, Vref . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 p.A
Operating free-air temperature range .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 260°C
Lead temperature 1.6 mm (1116 inch) from case for 60 seconds: J package ........... , 300°C

-1!1

TEXAS
INSTRUMENTS
3-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER
recommended operating conditions
Voo = 5 V
MIN
NOM
MAX
Supply voltage, VOO

4.75

Reference voltage, V ref

5

5.25

Voo = 15V
MIN
NOM
MAX
14.5

±10

High-level input voltage, VIH

15

15.5

±10

2.4

V

0.8
40

CS setup time, tsulCS)

V
V

13.5

Low-level input voltage, VIL

UNIT

1.5

V

40

ns

0

0

ns

Data bus input setup time, tsulD)

25

25

ns

Data bus input hold time, thlDI

10

10

ns

Pulse duration, WR low, twlWRI

40

40

CS hold time, thlCSI

-55

Operating free-air temperature, T A

125

ns

-55

125

electrical characteristics over recommended operating free-air temperature range, Vref
and OUT2 at GND (unless otherwise noted)
PARAMETER
High-level input
IIH

current

Low-level input
IlL

current

VI

~

VDD

VI

~

0

OUTl

and CS at 0 V,

current

OUT2

WR and CS at 0 V,
Vref ~ ±10 V

Quiescent

IDD

Supply current

Standby

Supply voltage sensitivity,
kSVS

t.gain/t.VDD
Input capacitance,

Ci

DBO-DB7, WR, CS
OUTl

Co

Output

OUT2

capacitance

OUTl
OUT2

10
1

Full range

-10

-10

25°C

-1

-1

±400

±200

25°C
Full range

25°C

DBO-DB7 at VIHmin or VILmax
DBO-DB7 at 0 V
or VDD
t.VDD ~ 10%
VI

~

voo = 15V
TYP
MAX

MIN

1

Full range

Full range

± 50

± 50

±400

± 200

±50

±50

2

2

500

500

25°C

100

100

Full range

0.16

0.04

0.002

25°C

0.02

0.001

DBO-DB7 at 0, WR and CS at 0 V
DBO-DB7 at VDD, WR and CS at 0 V

30

30

120

120

120

120

5

IREF to GND)

20

UNIT
~A

~A

nA

mA
~A

%/%
pF

pF

30

30

Reference input impedance

0.02
5

5

0

°C

10 V, OUT 1

10

25°C

Vref ~ ±10 V
DBO-DB7 at VDD,

Output leakage

MIN

Full range

DBO-DB7 at 0, WR

Ilkg

Voo = 5 V
TYP
MAX

TEST CONDITIONS

=

5

20

kD

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-13

AD7524M
Advanced linCMOSTM 8·BIT MULTIPLYING
DIGIT Al· TO·ANAlOG CONVERTER
operating characteristics over recommended operating free-air temperature range, Vref = 10 V, OUT 1
and OUT2 at GND (unless otherwise noted)
PARAMETER

TEST CONDITIONS

Linearity error
Gain error

See Note 1

Settling time (to 1/2 LSBI

See Note 2

Propagation delay from digital input to 90%
of final analog output current

I Full range
1 25 °C

See Note 2
Vref

=

± 10 V (100 kHz

I Full range

Feedthrough at OUll or OUT2

sinewavel, WR and CS at 0, 1 25 °C
DBO-DB7 at 0

Temperature coefficient of gain

TA

=

25°C to tmin or t max

Vee = 5 V
MIN

MAX

VDD = 15V
MIN

MAX

UNIT

±0.2

±0.2

± 1.4

±0.6

±1

±0.5

100

100

ns
ns

80

80

0.5

0.5

0.25

0.25

±O.OO4

±O.OOl

%FSR
%FSR

%FSR
%FSR/'C

NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSRI = Vref - 1 LSB.
2. OUll load = 100 0, C ext = 13 pF, WR at 0 V, CS at 0 V, DBO-DB7 at 0 V to VDD or VDD to 0 v.

PRINCIPLES OF OPERATION
The AD7524M is an 8-bit mUltiplying D/A converter consisting of an inverted R-2R ladder, analog switches,
and data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded and these decoded bits, through a modification in the R-2R ladder, control three equally
weighted current sources. Most applications only require the addition of an external operational amplifier
and a voltage reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire
reference current, Iref, is switched to OUT2. The current source 1/256 represents the constant current
flowing through the termination resistor of the R-2R ladder, while the current source Ilkg represents leakage
currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital
input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2
and the on-state switch capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the
situation is reversed as shown in Figure 1. Analysis of the circuit for all digital inputs high is similar to
Figure 1; however, in this case, Iref would be switched to OUT1.
Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS
and WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data
activity on the DBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data
directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBO-DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs
are disabled regardless of the state of the WR signal.
The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.

TEXAS . .
INSTRUMENTS
3-14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
PRINCIPLES OF OPERATION

i

r -

''''

Irel

- - - - - RFB
R

~r-i-----f._--<3.0-p-F- - - -

OUTl

-+

25-6-~
..
=~~--llk-g-~
..
_>--i-----I----___>-- OUTPUT
CS----j
WR----I

=
FIGURE 2. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)
Vrel

VDD
20

RA

~

2 kll

20

kn

kn

(See Note 31

10 kll

DBO·DB7

CS

> ....--OUTPUT

----I

WR - - - - I

GND

=
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT OPERATION)
NOTES

3. RA and R8 used only if gain adjustment is required.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-15

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
PRINCIPLES OF OPERATION
Table 2. Bipolar (Offset Binary) Code

Table 1. Unipolar Binary Code

DIGITAL INPUT

DIGITAL INPUT
(SEE NOTE 5)
MSB

MSB

LSB

ANALOG OUTPUT

LSB

11111111

- V,e! (255/256)

11111111

V,e! (127/1281

10000001

- V,e! (129/2561

10000001

V,e! (1/128)

10000000

-V,e! (128/256)

01111111

- V,e! (127/2561

00000001

-V,e! (1/2561

00000000
NOTES:

(SEE NOTE 6)

ANALOG OUTPUT

~

10000000

- V,e!/2

0

0

01111111

-V,e! (111281

00000001

-V,e! (127/1281

00000000

-V,e!

5. LSB ~ 1/256 (V,e!).
6. LSB ~ 1/128 (V re !)

microprocessor interfaces

DO-D7

DATA BUS

~--------------------------~

Z-80A

W R I - - -.....

~--------------~WR

DECODE
LOGIC

AO-A 15

ADDRESS BUS

~----------------------------------~
FIGURE 4. AD7524M-Z-80A INTERFACE

DATA BUS

DO-D7

W

6800

"2

VMA

AO-A15

DBO-DB7

~

OUTl

Lr

WR

AD7524M
OUT2
CS

I

DECODE
LOGIC

n

ADDRESS BUS

FIGURE 5. AD7524M-6800 INTERFACE

TEXAS

~

INSTRUMENTS
3-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

"
-,

AD1524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
microprocessor interfaces (continued)

ADDRESS 8US
DECODE
LOGIC I--~--,

8051

. . - - - - - - ; WR

1--+-+-......---'
WR 1--+-+------'

ALE

ADO-AD7

ADDRESS/DATA BUS

t----------------------~7

FIGURE 6. AD7524M-8051 INTERFACE

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-17

3-18

AD7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DlGITAL-TO-ANALOG CONVERTER
03112, JULY 1988

•

Advanced LinCMOS'" Silicon-Gate
Technology

N PACKAGE
(TOP VIEW)

•

Easily Interfaced to Microprocessors

•

On-Chip Data Latches

•

Monotonic Over the Entire AID Conversion
Range

•

Designed to be Interchangeable with Analog
Devices AD7528 and PMI PM-7528

•

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

AGND
aUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4

aUTB
RFBB
REFB
VDD
WR
CS
DBO (LSB)
DB1
DB2
DB3
FN PACKAGE

KEY PERFORMANCE SPECIFICATIONS

~~§1~ffi

1/2 LS8

Linearity Error

Power Dissipation at V DD
Settling Time at VDD

(TOP VIEW)

8 bits

Resolution

=

=

5 V

5 V

Propagation Delay at VDD

=

li.:J(9:Jli.

a:O«Oa:

5 mW
100 ns

5 V

3

80 ns

REFA
DGND
DACA/DACB
(MSB)DB7

description

2

1 20 19

4

18

REFB

5

17

6

16
15

VDD
WR

The AD7528 is a dual 8-bit digital-to-analog
7
converter designed with separate on-chip data
14
DBO(LSB)
DB6 8
latches and featuring excellent DAC-to-DAC
910111213
matching. Data is transferred to either of the two
L!l-o-C'lN
CD CD CD CD CD
DAC data latches via a common 8-bit input port.
00000
Control input DACA/DACB determines which
DAC is to be loaded. The "load" cycle of the
AD7528 is similar to the "write" cycle of a random-access memory, allowing easy interface to most popular
microprocessor busses and output ports. Segmenting the high-order bits minimizes glitches during changes
in the most significant bits, where glitch impulse is typically the strongest.
The AD7528 operates from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). Excellent
2- or 4-quadrant multiplying makes the AD7528 a sound choice for many microprocessor-controlled gainsetting and signal-control applications.
The AD7528B is characterized for operation from - 25°C to 85 DC. The AD7528K is characterized for
operation from O°C to 70°C.
AVAILABLE OPTIONS
SYMBOLIZATION
DEVICE

PACKAGE

OPERATING
TEMPERATURE

SUFFIX

RANGE

AD7528B

FN, N

-25°C to 85°C

AD7528K

FN, N

ooe to

70°C

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documents contain information

current as of publication date. Products conform to
srecifications per the terms of Texas Instruments
standard warranty. Production processing does not

necessarily include testing of all parameters.

"'!1

Copyright © 1988, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-19

AD7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DlGITAL-TO-ANALOG CONVERTER
functional block diagram
DBO (14)

REFA

(13)

DATA
INPUTS

•
•
•
•
•
•

(3) RFBA
(4)

(12)

(2) OUTA

8

(11 )
INPUT
BUFFER

(10)

LATCH
A

8
DAC A

(9)
(B)
(1) AGND

DB7 (7)

(19) RFBB

WR (16)
CS (15)

(20) OUTB

8

DACA/DACB (6)

LATCH
B

LOGIC
CONTROL

8

REFB

operating sequence

I

14

'\

tsu(DAC)

~

~ th(DAC)

I

I
~tw(WR)~

'{
~tsu(D)

DBO-DB7

I
I

I

'\
DACA/DACB

~ th(CS)

~jIII

tsu(CS)

1'1

X

t

~Iol

DATA IN STABLE

X

-1.!1

TEXAS
INSTRUMENTS
3-20

th(D)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 17 V
Voltage between AGND and DGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± VDD
Input voltage, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD+0.3 V
Reference voltage, VrefA or VrefB (to AGND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Feedback voltage, VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Output voltage, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Peak input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 JlA
Operating free-air temperature range: AD7528B . . . . . . . . . . . . . . . . . . . . . . . . . . - 25°C to 85 °C
AD7528K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: N package ...... . . . . .. 260°C

recommended operating conditions
VDD = 4.75 V to 5.25 V
MIN

NOM

MAX

vDD = 14.5 V to 15.5 V
MIN

±10

Reference voltage, V ref A or V refB
High-level input voltage, VIH

50

UNIT
V

13.5
0.8

CS setup time, tsu(CS)

MAX

±10

2.4

Low-level input voltage, VIL

NOM

V
1.5

V

50

ns

0

0

ns

DAC select setup time, tsu(DAC)

50

50

ns

DAC select hold time, th(DAC)

10

10

ns

Data bus input setup time tsu(D)

25

25

ns

0

0

ns

50

50

CS hold time, thlCS)

Data bus input hold time th(D)
Pulse duration, WR low, tw(WR)

I AD7528B
Operating free-air temperature, TAl
,

ns

-25

85

-25

85

0

70

0

70

AD7528K

TEXAS

°c

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-21

AD7528
Advanced linCMOSTM DUAL 8-BIT MUL TIPL VING
DIGITAL-TO-ANALOG CONVERTER
electrical characteristics over recommended operating temperature range. VrefA
VOA and VOS at 0 V (unless otherwise noted)
PARAMETER
IIH
IlL

TEST CONDITIONS

High-level input current

VI

Low-level input current

VI

~

~

Ilkg

OUTB

10

10

25°C

0

25°C

8

(Pin 15 to GND)
OUTA

VDD = 15V
MAX
MIN

Full Range

Reference input impedance

Output leakage current

VDD - 5 V
MIN
MAX
Full Range

VDD

DAC data latch loaded with
00000000, VrelA

~

±10 V

DAC data latch loaded with
00000000, VrelB

~

± 10 V

Full Range
25°C
Full Range
25°C

1

1

-10

-10

-1

-1

15
±400

VDD ~ ±10%

IDD

Supply current

Quiescent

DBO-DB7 at VIHmin or VIl.max

Standby

DBO-DB7 at 0 V or VDD

Input capacitance

. WR, CS,

VI

~

±50

±400

±200

± 50

±50

±1%

0.04

0.02

25°C

0.02

0.01

1

1

Full Range

0.5

0.5

25°C

0.1

0.1

10

10

15

15

0 or VDD

DACA/DACB
Co

Output capacitance

DAC Data latches loaded with 00000000

50

(OUTA,OUTB)

DAC Data latches loaded with 11111111

120

.J./}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT
~A

~A

kD

±200

±1%

DBO-DB7
Ci

15

Full Range

(REFA to REFB)
Ll.gainILWDD

8

± 50

Input resistance match

DC supply sensitivity

10 V.

VrefS

nA

%1%

mA

pF

50 .
120

pF

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
operating characteristics over recommended operating free-air temperature range,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
VOO - 5 V
MIN
TYP
MAX

TEST CONOITIONS

PARAMETER
Linearity error
Setting time (to 1/2 LSBI

See Note 1

Gain error

See Note 2

AC feedthrough

l REFA to OUTA
I REFB to OUTB

Full Range

90% of final analog output current)

MAX
± 1/2

100

100

±4

±3

±2

±2

-65

-65

25°C

-70

-70

0.007

0.0035

80

80

Temperature coefficient of gain

Propagation delay (from digital input to

TYP

± 1/2

Full Range

25°C

See Note 3

VDD - 15V
MIN

See Note 4

UNIT
LSB
ns
LSB
dB
%FSR/'C
ns

Channel.to-channell REFA to OUTB

See Note 5

25°C

77

77

I REFB to OUTA

See Note 6

25°C

77

77

160

440

nVs

30

60

nVs

-85

-85

isolation

dB

Measured for code transition from
Digital-ta-analog glitch impulse area

00000000 to 11111 111 ,
TA - 25°C
Measured for code transition from

Digital crosstalk glitch impulse area

00000000 to 11111111,
TA

Harmonic distortion

NOTES: 1.
2.
3.
4.
5.
6.

Vi

~
~

25°C
6 V, f

~

1 kHz, T A

~

25 'C

OUTA, OUTB load - 100 n, Cext - 13 pF; WR and CS at a V; OBO-OB7 at a V to VOO or
Gain error is measured using an internal feedback resistor. Nominal Full Scale Range (FSR) =
Vref ~ 20 V peak-to-peak, 100-kHz sine wave; OAC data latches loaded with 0000000.
VrefA ~ VrefB ~ 10 V; OUTA/OUTB load ~ 100 n, Cext - 13 pF; WR and CS at 0 V; OBO-OB7
Both OAC latches loaded with 11111111; VrefA ~ 20 V peak-to-peak, 100-kHz sine wave;
Both OAC latches loaded with 11111111; VrefB - 20 V peak-to-peak, 100-kHz sine wave;

dB

VOO to a v.
Vref - 1 LSB.
at 0 V to VOO or VOO to 0 V.
VrefB ~ O.
VrefA ~ O.

principles of operation
The AD7528 contains two identical8-bit mUltiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of
the switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both
DACs share the analog ground pin 1 (AGND). With all digital inputs high, the entire reference current flows
to OUT A. A small leakage current (llkg) flows across internal junctions, and as with most semiconductor
devices, doubles every 10°C. Co is due to the parallel combination of the NMOS switches and has a value
that depends on the number of switches connected to the output. The range of Co is 50 pF to 120 pF
maximum. The equivalent output resistance ro varies with the input code from 0.8R to 3R where R is
the nominal value of the ladder resistor in the R-2R network ..
Interfacing the AD7528 to a microprocessor is accomplished via the data bus, CS, WR, and DACA/DACB
control signals. When CS and WR are both low, the AD7528 analog output, specified by the DACA/DACB
control line, responds to the activity on the DBO-DB7 data bus inputs. In this mode, the input latches are
transparent and input data directly affects the analog output. When either the CS signal or WR signal
goes high, the data on the DBO-DB7 inputs is latched until the CS and WR signals go low again. When
CS is high, the data inputs are disabled regardless of the state of the WR signal.
The digital inputs of the AD7528 provide TTL compatibility when operated from a supply voltage of 5 V.
The AD7528 may be operated with any supply voltage in the range from 5 V to 15 V, however, input
logic levels are not TTL compatible above 5 V.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-23

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER

2R

2R

2R

2R

2R

R

"""''VV--RFBA
~-+--~~~-*~+-1r--*~+----+-4~----OUTA
~--~

__--~~~f----~~--~-------AGND

FIGURE 1. SIMPLIFIED FUNCTIONAL CIRCUIT FOR DACA
RFBA
R

VREFA-"Nv__--_---------1_----...........- - - OUTA
_1256

FIGURE 2. AD7528 EQUIVALENT CIRCUIT, DACA LATCH LOADED WITH 11111111.
MODE SELECTION TABLE
DACAl
DACB
L
H

L

CS

WR

DACA

DACB

L
L

X

L
L
H

X

X

X

H

WRITE
HOLD
HOLD
HOLD

HOLD
WRITE
HOLD
HOLD

= low level, H = high level, X = don't care

-1.!1

TEXAS
INSTRUMENTS
3-24

POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
TYPICAL APPLICATION OAT A
The AD7528 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
VilA}
± 10 V

VDD~114}

DBO

··• ·••

17}

--INPUT
BUFFER

~--""'VOA

DB7

I DACAl
16}

DACB

115}

CS

116}

WR

CONTROL
LOGIC
~--""'VOB

DGN~

-=

LRECOMMENDED TRIM
RESISTOR VALUES

NOTES:

R1, R3

500 !l

R2, R4

150 !l

VilB}
±10 V

1. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
2. C 1 and C2 phase compensation capacitors 110 pF to 15 pF} are required when using high·speed amplifiers to prevent ringing
or·oscillation.

,

FIGURE 3. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)

l!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-25

AD7528
Advanced LinCMOSTM DUAL 8·BIT MUlTIPl VING
DIGITAL· TO·ANAlOG CONVERTER
TYPICAL APPLICATION OAT A
VilA)

± 10 V

RS (See Note 2)
20 k!l

VDD~(14) I DBO

.

-

I.

-REFA

(See
Note 2)

INPUT
BUFFER

I:
(7)

---- -- -

R5

R7
10 k!l
Rll

DB7

VOA

5 k!l

R4 (See Note 1)
(S)

(15)

R8
LOGlC

(1S)

DGND~
.J.. •

10 k!l

REFB

VOB

-= .... _ - - - - - - - - - -

(See Note 2)

Rl0
20

± 10 V
ViiS)
NOTES:

k{J

1. Rl, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust Rl
for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for V08 = 0 V with 10000000 in DAC8 latch.
2. Matching and tracking are essential for resistor pairs R6. R7, R9, and Rl0.
3. C 1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A 1 and A3 are high-speed amplifiers.

FIGURE 4. BIPOLAR OPERATION (4-QUADRANT OPERATION)
TABLE 1. UNIPOLAR BINARY CODE
DAC LATCH CONTENTS
MSB

LSBt

ANALOG OUTPUT

TABLE 2. BIPOLAR (OFFSET BINARY) CODE
DAC LATCH CONTENTS
MSB

ANALOG OUTPUT

11111111

- Vi (255/256)

11111111

Vi (127/128)

10000001

- Vi (129/256)

10000001

Vi (1/128)

10000000
01111111
00000001
00000000

- Vi (128/256)

= - Vi/2

- Vi (127/256)
-Vi (1/256)
- Vi (0/256)

=

0

10000000

OV

01111111

-Vi (11128)

00000001

-Vi (1271128)

00000000

-Vi (1281128)

t 1 LS8 = (2-8)Vi

-1!1

TEXAS
INSTRUMENTS
3-26

LSB*

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAl·TO·ANAlOG CONVERTER
TYPICAL APPLICATION DATA
microprocessor interface information

A8·A15

ADDRESS BUS

I--~

ADDRESS
DECODE
LOGIC

CPU
8051

r-----.----i DACA/DACB

A

AD7528

WRI---'"
ALE

ADO-AD7

NOTE:

DATA BUS

1-----------~----7'----~

A ~ decoded address for AD7528 DACA.
A + 1 ~ decoded address for AD7528 DACB.

FIGURE 5. AD7528 - INTEL 8051 INTERFACE

A8-A15

VMA
CPU
6800

ADDRESS BUS

1----..,
ADDRESS
DECODE
LOGIC

A

r-----.----i DACA/DACB
AD7528

A+ 1

q,21---LJ

DO-D7

NOTE:

DATA 8US

I-----------------~-----~

A ~ decoded address for AD7528 DACA.
A+ 1 ~ decoded address for AD7528 DACB.

FIGURE 6. AD7528 - 6800 INTERFACE

TEXAS

-'!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-27

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGIT AL· TO·ANALOG CONVERTER
TYPICAL APPLICATION OAT A

A8-A15

t---n

ADDRESS
DECODE
LOGIC
CPU
Z80-A

A
AD7528

A+ 1

WR I---L...-"

DO-D7

NOTE:

DATA BUS

~------------------------~--------~

A ~ decoded address for AD7528 DACA.
A + 1 ~ decoded address for AD7528 DACB.

FIGURE 7. AD7528 TO Z·80A INTERFACE

programmable window detector
The programmable window comparator shown in Figure 8 will determine if voltage applied to the DAC
feedback resistors are within the limits programmed into the AD7528 data latches. Input signal range
depends on the reference and polarity, that is, the test input range is 0 to -Vref. The DACA and DACB
data latches are programmed with the upper and lower test limits. A signal within the programmed limits
will drive the output high.

o

DATA ,..---"-..J......"..-t

•

L - _......,..~-I

•

INPUTS

(17)

1 k(l

(7) DB7

(1 )

_-+~~(1~5~) CS

_-+~~(!...:1~6'-1) WR

VCC

VDD

TEST
INPUT-....~-----......,(3)
TO -Vref
RFBA

AGND __-r-e~~,

PASS/FAIL
OUTPUT

AD7528

_-++1f---!(.:::.6)'-I DACA/DACB
(20)

+ V ref

_-+....~(..;.1.;:.;8)+-'RE;;.;F..;;B_-I
(5) DGND
RFBB
(19)

FIGURE 8. DIGITALLY PROGRAMMABLE WINDOW COMPARATOR (UPPER· AND LOWER·LlMIT TESTER)

TEXAS . "
INSTRUMENTS
3-28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA

digitally controlled signal attenuator
Figure 9 shows the AD7528 configured as a two-channel programmable attenuator. Applications include
stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB
range.
Attenuation db
VDD

~

-20 10910 D/256, D

=

digital ilnput code


17)r-----~::::::::::~~~13~)~________- ,
RFBA (2)

VINA--------------1"'4"")I-'R.::E:.;.F.:.;A'-j

OUTA

OUTPUT

•

AD7528

DB7
CS (15)
WR (16)

DACA/DACB .,1",6-,-)_____________
(18)
VOB

REFB
AGND (1)

FIGURE 9. DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
TABLE 3. ATTENUATION vs DACA, DACB CODE
ATTNldB)

DAC INPUT CODE

CODE IN
DECIMAL

ATTNldB)

DAC INPUT CODE

CODE IN
DECIMAL

0

11111111

255

8.0

01100110

102

0.5

11110010

242

8.5

01100000

96

1.0

11100100

228

9.0

01011011

91

1.5

11010111

215

9.5

01010110

86

2.0

11001011

203

10.0

01010001

81

2.5

11000000

192

10.5

01001100

76

3.0

10110101

181

11.0

01001000

72

3.5

10101011

171

11.5

01000100

68

4.0

10100010

162

12.0

01000000

64

4.5

10011000

152

12.5

00111101

61

5.0

10010000

144

13.0

00111001

57

5.5

10001000

136

13.5

00110110

54

6.0

10000000

128

14.0

00110011

51

6.5

01111001

121

14.5

00110000

48

7.0

01110010

114

15.0

00101110

46

7.5

01101100

108

15.5

00101011

43

-II}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-29

AD7528
Advanced linCMOS™ DUAL 8·BIT MULTIPL VING
DIGlTAL·TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA
programmable state·variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications in which microprocessor control of filter parameters is required.
As shown in Figure 10, DACA 1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2
control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for
the cutoff-frequency equation to be true. With the AD7528, this is easily achieved.
1
fc = 2rr R1 C1
The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to
4.5. This defines the limits of the component vallJes.
C3

OUTA (2)

(4) REF A

VI

(17)

vDD
(14) DBO

DATA
IN

(7)
(15)
(16)
(5)

-=

(6)

••

DB7

RFBA
AD7528

CS

(3)

AGND (1)

. -_ _I-HIGH PASS
OUT

OUTB (20)

WR
RFBB

DGND

(19)

-=

(18)
REFB

DACA/DACB

BANDPASS
OUT

DACA1 AND DACB1

(4) REFA

OUTA (2)

(17) VDD

(14) DBO
DA TA ~-'---'I •
IN
(7).
(15) DB7
CS
(16) WR

RFBA (3)
AD7528

AGND (1)

C2

OUTB (20)

>-_...._LOW PASS

RFBB (19)

OUT

(5) DGND
REFB (18)
(6) DACA/DACB
DACA2 AND DACB2

NOTES:

Q=

Ao

A. Op·amps A 1, A2, A3, and A4 are TL287.
B. C3 compensates for the op·amp gain-bandwidth limitations.
C. DAC equivalent resistance equals

=

.!2.
R4

RF
Rfb(DACB1)

RF
RS

256 x (DAC ladder resistance)
DAC digital code

FIGURE 10. DIGITALLY CONTROLLED STATE-VARIABLE FILTER

-1!1

TEXAS
INSTRUMENTS
3-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
03321. SEPTEMBER 1989

•

Advanced LinCMOS'· Silicon·Gate
Technology

•

Easily Interfaced to Microprocessors

•

On· Chip Data Latches

•

Monotonic Over the Entire AID Conversion
Range

•

Designed to be Interchangeable with Analog
Devices AD7528 and PMI PM· 7528

•

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with SMJ320

J PACKAGE

(TOPVIEWI

AGND
QUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4

vDD
WR
CS
DBD ILSB)
DB1
DB2
DB3
FK PACKAGE

KEY PERFORMANCE SPECIFICATIONS

(TOPVIEWI

8 bits

Resolution

~~~~~
Ll.:Jt?:JLl.

1/2 LSB

Linearity Error

Power Dissipation at VDD
Settling Time at VDD

QUTB
RFBB
REFB

=

=

5 V

=

a:O«Oa:

100 ns

5 V

Propagation Delay at VDD

5 mW

5 V

3

80 ns

REFA
DGND
DACA/DACB
IMSB)DB7
DB6

description

2

1 20 19

4

18

REFB

5

17

6

16
15

VDD
WR

The AD7528M is a dual 8-bit digital-to-analog
converter designed with separate on-chip data
14
8
DBDILSB)
latches and featuring excellent DAC-to-DAC
9 10 11 12 13
matching. Data is transferred to either of the two
DAC data latches via a common 8-bit input port.
Control input DACA/DACB determines which
DAC is to be loaded. The "load" cycle of the
AD7528M is similar to the "write" cycle of a random-access memory, allowing easy interface to most
popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during
changes in the most significant bits, where glitch impulse is typically the strongest.
The AD7528M operates from a 5-V to 15-V power supply and dissipates less than 15 mW (typical).
Excellent 2- or 4-quadrant multiplying makes the AD7528M a sound choice for many microprocessorcontrolled gain-setting and signal-control applications.
The AD7528M is characterized for operation from - 55°C to 125°C.

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documants contein information
currant as of publication date. Products conform to
specifications par tha tarms of Ta.as Instrumants
standard warranty. Production processing does not
nac...arily includa testing of aU parameters.

TEXAS

+

Copyright © 1989, Texas Instruments Incorporated

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-31

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGlTAL·TO·ANALOG CONVERTER
functional block diagram

DBO (141

REFA

(131

DATA
INPUTS

•
•
•
•
•
•

(31 RFBA
(41

(121

(21 0UTA

8

(111
INPUT
BUFFER

(101

LATCH
A

8
DAC A

(9)
(8)

(11 AGND

DB7 (71

(19I RFBB
(201 0UTB

8
DACA/DACB (61
WR (161
CS (151

LATCH
B

LOGIC
CONTROL

8

REFB

operating sequence

'\
\:

I
~

Isu(DACI

I
~lw(WRI---+I

14--- Isu(O)

.t

X

~~~I

DATA IN STABLE

Ih(DI

X

~

TEXAS
INSTRUMENTS
3-32

th(CSI

~ Ih(DACI

I

'{
OBO-DB7

I
I

I

j4

DACA/DACB

~

~joI

tsu(CSI

14

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VDD (to AGND or DGND) ............................... - 0.3 V to 17 V
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ± VDD
Input voltage, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V
Reference voltage, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Feedback voltage, VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Output voltage, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 10 p,A
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 D C
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package ............ 300 D C

recommended operating conditions
VDD - 4.75 V to 5.25 V

MIN

MAX

VDD -

MIN

±10

Reference voltage, V ref A or V refS
High-level input voltage, VIH

NOM

14.5 V to 15.5 V

NOM

MAX

±10

V

13.5

2.4
0.8

Low-level input voltage, VIL

UNIT

V

1.5

V

CS setup time, tsu(CSI

50

50

ns

CS hold time, th(CSI

0
50
10
25
0

0
50
10
25
0

ns

DAC select setup time, tsu(DACI
DAC select hold time, th(DACI
Data bus input setup time tsum!
Data bus input hold time thlD!
Pulse duration, WR low, tw(WR!
Operating free-air temperature, T A

50
-55

125

50
-55

ns
ns
ns
ns
ns

125

°C

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-33

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER
electrical characteristics over recommended operating temperature range. VrefA = VrefS -= 10 V.
VOA and VOS at 0 V (unless otherwise noted)
PARAMETER
IIH
IlL

TEST CONOITIONS

High-level input current

VI

Low-level input current

VI

=
=

VOO

Ilkg

OUTa

0

25°C
a

DAC data latch loaded with
00000000, VrefA

=

±10 V

DAC data latch loaded with
00000000, VrefB

=

± 10 V

VDD
Quiescent

100

Supply current

Standby

=

±10%

Input capacitance

WR, CS,

VI

=0

15

a

15

±50

±400

±200

±50

±50

±1%

±1%

25°C

0.04

0.02

25°C

0.02

0.01

1

1

Full Range

0.5

0.5

25°C

0.1

0.1

10

10

15

15

or VDD

Output capacitance

DAC Data latches loaded with 00000000

50

50

(OUTA,OUTB)

DAC Data latches loaded with 11111111

120

120

~

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
I'A
I'A
kO

±200

Full Range

TEXAS
INSTRUMENTS
3-34

-1

±50

DACA/DACB
Co

-1

±400

DBO-DB7
Ci

1
-10

25°C
Full Range

DBO-DB7 at VIHmin or VILmax
DBO-OB7 at 0 V or VOD

1
-10

Full Range

(REFA to REFB)
Again/AVDD

10

25°C

Input resistance match

DC supply sensitivity

10

Full Range

(Pin 15 to GND)
DUTA

VOO - 15V
MIN
MAX

Full Range

Reference input impedance

Output leakage current

VOO - 5 V
MIN MAX

nA

%1%

mA

pF

pF

AD7528M
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
operating characteristics over recommended operating free-air temperature range,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VDD - 5 V
MIN
TYP
MAX

Linearity error

Setting time Ito 112 LSB)

See Note 1

Gain error

See Note 2

AC feedthrough

I REFA to OUTA
I REFB to OUTB

Full Range
25°C

See Note 3

90% of final analog output current)

TYP

MAX

± 1/2

±1/2

100

100

±4

±3

±2

±2

Full Range

-65

-65

25°C

-70

-70

0.007

0.0035

80

80

Temperature coefficient of gain

Propagation delay Ifrom digital input to

VDD-15V
MIN

See Note 4

UNIT
LSB
ns
LSB
dB
%FSR/'C
ns

Channel-to-channell REFA to OUTB

See Note 5

25°C

77

77

I REFB to OUTA

See Note 6

25°C

77

77

160

440

nVs

30

60

nVs

-85

-85

dB

isolation

dB

Measured for code transition from
Digital-to-analog glitch impulse area

00000000 to 11111111,
TA

= 25°C

Measured for code transition from
Digital crosstalk glitch impulse area

00000000 to 111 11111 ,

= 25°C
Vi = 6 V, f = 1 kHz, T A = 25 'C

TA
Harmonic distortion
NOTES: 1.
2.
3.
4.
5.
6.

OUTA, OUT8 load = 100 fl, Cext = 13 pF; WR and CS at 0 V; DBO-DB7 at 0 V to VDD or VDD to 0 V.
Gain error is measured using an internal feedback resistor. Nominal Full Scale Range IFSRI = V ref - 1 LSB.
Vref = 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 0000000.
VrefA = V re f8 = 10 V; OUTA/OUTB load = 100 fl, C ext = 13 pF; WR and CS at 0 V; DBO-DB7 at 0 V to VDD or VDD to 0 V.
Both DAC latches loaded with 11111111; VrefA = 20 V peak-to-peak, 100-kHz sine wave; VrefB = O.
Both DAC latches loaded with 11111111; VrefB = 20 V peak-to-peak, 100-kHz sine wave; VrefA = O.

principles of operation
The AD7528M contains two identical 8-bit multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of
the switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB, Both
DACs share the analog ground pin 1 (AGND). With all digital inputs high, the entire reference current flows
to OUT A. A small leakage current (Ilkg) flows across internal junctions, and as with most semiconductor
devices, doubles every 10 DC. Co is due to the parallel combination of the NMOS switches and has a value
that depends on the number of switches connected to the output. The range of Co is 50 pF to 120 pF
maximum. The equivalent output resistance ro varies with the input code from 0.8R to 3R where R is
the nominal value of the ladder resistor in the R-2R network.
Interfacing the AD7528M to a microprocessor is accomplished via the data bus, CS, WR, and DACA/DACB
control signals. When CS and WR are both low, the AD7528M analog output, specified by the DACA/DACB
control line, responds to the activity on the DBO-DB7 data bus inputs. In this mode, the input latches are
transparent and input data directly affects the analog output. When either the CS signal or WR signal
goes high, the data on the DBO-DB7 inputs is latched until the CS and WR signals go low again. When
CS is high, the data inputs are disabled regardless of the state of the WR signal.
The digital inputs of the AD7528M provide TTL compatibility when operated from a supply voltage of
5 V. The AD7528M may be operated with any supply voltage in the range from 5 V to 15 V, however,
input logic levels are not TTL compatible above 5 V.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-35

·AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER

2R

2R

S1

S2

2R

2R

2R

S8

R

........iV'r-RF8A
L....!-I-_~_-I--~a.....:.--l---i

1--._-+---+-...- - - OUT A

L-_~~--~~'~-~~-~~----AGND

FIGURE 1. SIMPLIFIED FUNCTIONAL CIRCUIT FOR DACA
-RFBA
R
VREFA--~~--1~---~---1~~---OUTA

_1-

256

FIGURE 2. AD7528M EQUIVALENT CIRCUIT, DACA LATCH LOADED WITH 11111111
MODE SElECTION TABLE
DACAl
DACB
L

DACB

CS

WR

DACA

L

L

WRITE

HOLD

H

L

L

HOLD

WRITE

X

H

X

HOLD

HOLD

X

X

H

HOLD

HOLD

L ;- low level, H --: high level, X -: don't care

TEXAS

~

INSTRUMENTS
3-36

POST OFFICE

sox

655303 • DALLAS, TEXAS 75265

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
APPLICATION DATA
The AD7528M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
Vj(AI

± 10

VDD~(141

DBO

··• ··•

(71

v

--S

INPUT
SUFFER

>---"'VOA

DB7

I DACAl
(61

DACB

(151

CS

(161

WR

CONTROL
lOGIC
>--"'VOB

DGN~

-=

LRECOMMENDED TRIM
RESISTOR VALUES

NOTES:

Rl, R3

500 !l

R2, R4

150 !l

Vi(B)

± 10

v

1. Rl, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
2. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing

or oscillation.

FIGURE 3. UNIPOLAR OPERATION 12-QUADRANT MULTIPLICATION)

TEXAS

-1.!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-37

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
APPLICATION DATA
VilA)

± 10 V

R6 ISee Note 2)
20 kl!

VDD~-(14)1 DBO

I •

-- -

-REFA

R5

ISee
Note 2)

INPUT
BUFFER

I :
(7)

--- -

R7
10 kl!
Rll

DB7

5 kfl
(6)
(15)

R8

LOGIC

(16)

DGND~
...L

-=

•

10 k[l

REFB

VOB

'------------

ISee Note 2)
Rl0
20 kfl

± 10 V
ViIB)

FIGURE 4. BIPOLAR OPERATION (4-QUADRANT OPERATION)
NOTES:

1. Rl, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust Rl
for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
2. Matching and tracking are essential for resistor pairs R6, R7, R9, and Rl0.
3. C 1 and C2 phase compensation capacitors (10 pF to 15 pFI may be required if A 1 and A3 are high-speed amplifiers.

TABLE 2. BIPOLAR (OFFSET BINARY) CODE

TABLE 1. UNIPOLAR BINARY CODE
DAC LATCH CONTENTS
MSB

LSBt

MSB

11111111

- Vi (255/2561

LSB*
11111111

10000001

- Vi (129/2561

10000001

10000000
01111111
00000001
00000000

t 1 LSB

DAC LATCH CONTENTS

ANALOG OUTPUT

=

(2-8IVi

- Vi (128/2561

= -

Vi/2

-Vi (127/2561
-Vi (1/2561
- Vi (0/2561

=

0

t 1 LSB

Vi (12711281
Vi (1/1281

10000000

OV

01111111

-Vi (1/1281

00000001

- Vi (127/1281

00000000

-Vi (128/1281

=

(2 - 71Vi

~

TEXAS
INSTRUMENTS
3-38

ANALOG OUTPUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528M
Advanced linCMOSTM DUAL 8·BIT MULTIPLYING
DIGlTAL·TO·ANALOG CONVERTER
APPLICATION DATA
microprocessor interface information

A8-A15

ADDRESS BUS

r----~----t

ADDRESS
DECODE
LOGIC

CPU
8051

DACA/DACB

A
AD7528M

WRI----t

ALE

ADO-AD7

NOTE:

DATA BUS

r-------------------------~--------~

A ~ decoded address for AD7528M DACA.
A + 1 ~ decoded address for AD7528M DACB.

FIGURE 5. AD7528M - INTEL 8051 INTERFACE

A8-A15

VMA
CPU
6800

ADDRESS BUS

1---<"1

ADDRESS
DECODE
LOGIC

A

r - - - - - + - - - ; DACA/DACB
CS
AD7528M
r---~-----t WR

,...----'''<-f DBO
tl>21---L~

00-07

NOTE:

DATA BUS

r-------------------------~--------~

A ~ decoded address for A07528M DACA.
A + 1 ~ decoded address for AD7528M DACB.

FIGURE 6. AD7528M - 6800 INTERFACE

TEXAS

l!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-39

AD7528M
Advanced LinCMOS™ DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
APPLICATION DATA

A8-A15

1---",

ADDRESS
DECODE
LOGIC
CPU
Z80-A

A

A+1

WRI---L~

DO-D7

NOTE:

DATA BUS
r-------------------------~--------~

A = decoded address for AD752BM DACA.
A + 1 = decoded address for AD752BM DACB.

FIGURE 7. AD7528M TO Z-80A INTERFACE

programmable window detector
The programmable window comparator shown in Figure 8 will determine if voltage applied to the DAC
feedback resistors are within the limits programmed into the AD7528M data latches. Input signal range
depends on the reference and polarity, that is, the test input range is a to -Vref. The DACA and DACB
data latches are programmed with the upper and lower test limits. A signal within the programmed limits
will drive the output high.
VCC

VDD

TEST
INPUT--....--------,131
o TO -Vref
RFBA

1171
1 kll

DATA r--~~~;
INPUTS <---.,--.-7'-; •
171 DB7

(1)

_-+~~11~5~1 CS

_-++-1_1:...:1;::6"'11 WR

AGND __-r-e~~~

PASSIFAIL
OUTPUT

AD752BM

_-++-1,.......:1-,-61"1 DACAIDACB
(20)

+ V ref _-+-..-:1-C,.1B.:.;)+-=-RE",F-:;B_-I
151 DGND
RFBB
(19)

FIGURE 8. DIGITALLY PROGRAMMABLE WINDOW COMPARATOR (UPPER- AND LOWER-LIMIT TESTER)

TEXAS

l.!}

INSTRUMENTS
3-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7528M
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
APPLICA TION DATA
digitally controlled signal attenuator
Figure 9 shows the AD7528M configured as a two-channel programmable attenuator. Applications include
stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB
range.
Attenuation db

VDD

~

- 20 log 10 D/256. D

~

digital ilnput code

117)r---;:=====;;:;;;~.f13~)_ _ _ _ _..,
RF8A 12)

OUTA

OUTPUT

080 114)
:
17)
087
CS 115)

AD7528M

WR 116)
DACA/DACS ",1",,6,-1_ _ _ _ __
118)

Vas

REFS
AGND 11)
DGND 15)

FIGURE 9. DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
TABLE 3. A TTENUAnON vs DACA, DACB CODE
ATTN(d8)

DAC INPUT CODE

CODE IN
DECIMAL

ATTN(dS)

DAC INPUT CODE

CODE IN
DECIMAL

0

11111111

255

8.0

01100110

102

0.5

11110010

242

8.5

01100000

96

1.0

11100100

228

9.0

01011011

1.5

11010111

215

9.5

01010110

91
86 .

2.0

11001011

203

10.0

01010001

81

2.5

11000000

192

10.5

01001100

76

3.0

10110101

181

11.0

01001000

72

3.5

10101011

171

11.5

01000100

68

4.0

10100010

162

12.0

01000000

64

4.5

10011000

152

12.5

00111101

61

5.0

10010000

144

13.0

00111001

57

5.5

10001000

136

13.5

00110110

54

6.0

10000000

128

14.0

00110011

51

6.5

01111001

121

14.5

00110000

48

7.0

01110010

114

15.0

00101110

46

7.5

011011!JO

108

15.5

00101011

43

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3--41

AD7528M
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER
APPLICATION OATA
programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications in which microprocessor control of filter parameters is required.
As shown in Figure 10, DACA 1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2
control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for
the cutoff-frequency equation to be true. With the AD7528M, this is easily achieved.

fc = 2n R1 C1
The programmable range for the cutoff or center frequency is
4.5. This defines the limits of the component values.

°

to 15 kHz with a Q ranging from 0.3 to
C3

OUTA (2)

(4) REF A
(17)

VDD
(14) DBO

DATA....",.,........~

(7)

IN

(15)
(16)
(5)
":'

(6)

••

DB7

(3)

RFBA

AGND (1 )

....__+- HIGH PASS

AD7528M

OUT

CS

OUTB (20)

WR

(19)

RFBB

DGND

(18)
REFB

DACA/DACB

BANDPASS
OUT

DACAl AND DACBl

(4) REFA

OUTA (2)

(17) VDD
(14) DBO
DATA
•
IN ~_,,-17-i).
115) DB7
CS
116) WR

RFBA (3)
AGND 11)

AD7528M

C2

OUTB (20)
RFBB 119)

(5)

>_...~lOW PASS
OUT

DGND
REFB 118)
16) DACA/DACB
DACA2 AND DACB2
Q=

~.
R4

NOTES:

Ao = -

A. Op-amps A 1, A2, A3, and A4 are TL287.

RF
RfbIDACB1)

RF
RS

8. C3 compensates for the op-amp -gain-bandwidth limitations.
C. DAC equivalent resistance equa:s

256 x IDAC ladder reSistance I
DAC digital code

FIGURE 10. DIGITALLY CONTROLLED STATE-VARIABLE FILTER

TEXAS •
INSTRUMENTS
3-42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7628
Advanced LinCMOS™ DUAL 8-BIT MULTIPL VING
DlGITAL·TO·ANALOG CONVERTER
03198, JANUARY 1989 - REVISED FEBRUARY 1990

•

Advanced LinCMOS" Silicon-Gate
Technology

•

Easy Microprocessor Interface

•

On-Chip Data Latches

•

Digital Inputs are TTL-Compatible with
10.8-V to 15.75-V Power Supply

N PACKAGE
(TOP VIEW)
AGND
OUTA
RFBA
REFA

VDD
WR

DGND
DACAIDACB
(MSB) DB7

•

Monotonic Over the Entire AID Conversion
Range

•

Designed to be Interchangeable with Analog
Devices AD7628

•

OUTB
RFBB
REFB

CS
DBO (LSB)

DB6

DB1

DB5
DB4

DB2
DB3

Fast Control Signaling for Digital Signal
. Processor Applications Including Interface
with TMS320

FN PACKAGE
(TOP VIEW)
0 co co
ZI- co
co ::J (,:J
::J LL
a:: 0 «0 a::

«
« I-

description

LL

The AD7628 is a dual 8-bit digital-to-analog
converter designed with separate on-chip data
latches and featuring excellent DAC-to-DAC
matching, Data is transferred to either of the two
DAC data latches via a common 8-bit input port.
Control input DACAIDACB determines which
DAC is loaded. The "load" cycle of the AD7628
is similar to the "write" cycle of a randomaccess memory, allowing easy interface to most
popular microprocessor buses and output ports.
Segmenting the high-order bits minimizes
glitches during changes in the most significant
bits, where glitch impulse is typically the
strongest.

1 20 19

REFA
DGND
DACA/DACB
(MSB)OB7
DB6

18

REFB

5

17

VDD

6

16

WR

15

8

14

CS
DBO(LSB)

9 10 11 12 13

en

<:t

("')

N

0

0

0

0

co co co co co
0

The AD7628 operates from a 1 0.8-V to 15. 75-V power supply and is TTL-compatible over this range,
Excellent 2- or 4-quadrant mUltiplying makes the AD7628 a sound choice for many microprocessorcontrolled gain-setting and signal-control applications,
The AD7628B is characterized for operation from - 25°C to 85 DC, The AD7628K is characterized for
operation from O°C to 70°c'
AVAILABLE OPTIONS
SYMBOLIZATION
DEVICE

PACKAGE

OPERATING
TEMPERATURE

SUFFIX

RANGE

AD7628B

FN, N

-25°C to 85°C

AD7628K

FN, N

O°C to 70 D C

Caution, These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

:~~~~:~~i~ai~:1~1~ ~~~:i:~ti~; ~lo::~:~:t:r~~S not

~

Copyright

© 1990, Texas Instruments Inc:orporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265

3-43

AD7628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
functional block diagram
DBOl141

REFA

1131

DATA
INPUTS

•
•
•
•
•
•

131 RFBA
141

1121

1210UTA

8

1111
INPUT
BUFFER

1101

LATCH
A

8
DAC A

191
IBI
111 AGND

DB7 171
1191 RFBB
1201 0UTB

8
DACAIDACB 161
WR 1161
CS 115.1

LATCH
B

LOGIC
CONTROL

8

REFB

operating sequence

'\'"14
DACAiDACB

\

I
I

I
~

tsulDACI

I
j4-- twlWRI--.l

if

~tsuIDI~thIDI

X

DATA IN STABLE

TEXAS

X

~

INSTRUMENTS
3--44

thlCSI

~ thlDACI

I

'\
DBO-DB7

.!

·14

tsulCSI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7628
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DlGITAL-TO-ANALOG CONVERTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (to AGND or DGND) . .
. ..... .
-0.3Vto17V
Voltage between AGND and DGND. . . . . . . . . . . . . . . . .
. . . . . . .. ± VDD
Input voltage range, VI (to DGND) . . .
. . . . . . ..
. . . . . . . . .. - 0.3 V to VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Reference voltage, VrefA or VrefB (to AGND).
Feedback voltage, VRFBA or VRFBB (to AGND) ......... .
±25 V
Output voltage, VOA or VOB (to AGND) ...... .
. . . . . . . . . . . . . . . . . . . . . . . ±25 V
Peak input current ...
. . . . . . . . . . . . 10 p.A
Operating free-air temperature range: AD7628B
. . . . .. .
. .. - 25°C to 85 °C
AD7628K . . . . . . . . .
.. O°C to 70°C
Storage temperature range .......
. . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .......... "
260°C

recommended operating conditions
MIN
Supply voltage, VDD
High·level input voltage, VIH

CS hold time, thlCSI

-..'-'-

------.--.--.
-----"" ._,--,----,-----'..

V
V

0.8

CS setup time. tsulCSI

UNIT
V

2.4

Low·level input voltage, VIL

DAC select hold time. thlDACI

MAX
15.75

±10

Reference voltage, VrefA or VrefB

DAC select setup time, tsulDACI

NOM

10.8

V

50

ns

10

ns

60

ns

10

ns

25

ns

10

ns

..

"

Data bus input setup time tsulDI
Data bus input hold time thlDI

..

---~----

50

Pulse duration, WR low, twlWRI
Operating free-air temperature T A
,

----------.
~~8B
AD7628K

.

ns

-·25

85

0

70

°C

.~---

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-45

AD7628
Advanced LinCMOS™ DUAL 8·BIT MULTIPLYING
DIGITAL· TO· ANALOG CONVERTER
electrical characteristics over recommended ranges of operating free-air temperature and VOO.
VrefA = VrefB = 10 V. VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

IIH

High-level input current

VI

=

VDD

IlL

Low-level input current

VI

=

0

MIN
Full Range

OUTA
OUTB

-10

25°C

-1

8
DAC data latch loaded with

Full Range

00000000, VrefA = ± 10 V
DAC data latch loaded with

Full Range

00000000, VrefB

=

25°C

±10V

25°C

Input resistance match
IREFA to REFB)
AVDD

Again/AVDD
Supply current

=

±5%

Quiescent

DBO-DB7 at VIHmin or VILmax

Standby

DBO-DB7 at 0 V or VDD

Input capacitance

WR, CS,

VI

=

0 or VDD

DACA/DACB
Co

{LA
kll

±200
±50
±200

nA

±50

I
I

Full Range

0.02

25°C

0.01

I
I

Full Range

0.5

25°C

0.1

%/%

2

15

Output capacitance

DAC Data latches loaded with 00000000

25

IOUTA, OUTB)

DAC Data latches loaded with 11111111

60

TEXAS .."
INSTRUMENTS
3-46

{LA

mA

10

DBO-DB7
Ci

15

UNIT

± 1%

DC supply sensitivity

IDD

1

Full Range

IPin 15 to GND)

Output leakage current

10

25°C

Reference input impedance

Ilkg

MAX

POST OFFICE BOX- 655303 • DALLAS. TEXAS 75265

pF

pF

AD7628
Advanced LinCMOSTM DUAL 8·81T MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
operating characteristics over recommended ranges of operating free-air temperature and VOO,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

Linearity error

Setting time (to 112 LSB)

See Note 1

Gain error

See Note 2

AC feedthrough

I REFA to OUTA
I REFB to OUTB

90% of final analog output current)
Channel-to-channel
isolation

I REFA to OUTB
I REFB to OUT A

UNIT
LSB

100
Full Range

±3
±2

25°C

See Note 3

Full Range

-65

25°C

-70

Temperature coefficient of gain
Propagation delay (from digital input to

MAX
± 112

0.0035
See Note 4

80

See Note 5

25°C

80

See Note 6

25°C

80

ns
LSB
dB
O/OFSRloC
ns
dB

Measured for code transition from
Digital-to-analog glitch impulse area

00000000 to 11111111,

330

nV-s

60

nV-s

TA ~ 25°C

Measured for code transition from
Digital crosstalk glitch impulse area

00000000 to 11111111,
TA

Harmonic distortion

Vi

~
~

25°C
6 V, f

~

1 kHz, T A

~

25°C

-85

dB

NOTES: 1. OUTA, OUTB load ~ 1000, Cext ~ 13 pF; WR and CS at 0 V; DBO-DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal Full Scale Range (FSR) ~ Vref - 1 LSB. Both DAC latches
are loaded with 11111111.
3. Vref ~ 20 V peak-to-peak, 10-kHz sine wave.
4. VrefA ~ VrefB ~ 10 V; OUTAIOUTB load ~ 1000, Cext ~ 13 pF; WR and CS at 0 V; DBO-DB7 at 0 V to VDD or VDD to 0 V.
5. VrefA ~ 20 V peak-to-peak, 10-kHz sine wave; VrefB ~ O.
6. VrefB ~ 20 V peak-to-peak, 10-kHz sine wave; VrefA ~ O.

principles of operation
The AD7628 contains two identical 8-bit mUltiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of
the switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both
DACs share the analog ground pin 1 (AGND). With all digital inputs high, the entire reference current flows
to OUTA. A small leakage current (llkg) flows across internal junctions, and as with most semiconductor
devices, doubles every 10°C. Co is due to the parallel combination of the NMOS switches and has a value
that depends on the number of switches connected to the output. The range of Co is 25 pF to 60 pF
maximum. The equivalent output resistance ro varies with the input code from 0.8R to 3R where R is
the nominal value of the ladder resistor in the R-2R network.
Interfacing the AD7628 to a microprocessor is accomplished via the data bus, CS, WR, and DACA/DACB
control signals. When CS and WR are both low, the AD7628 analog output, specified by the DACA/DACB
control line, responds to the activity on the DBO-DB7 data bus inputs. In this mode, the input latches are
transparent and input data directly affects the analog output. When either the CS signal or WR signal
goes high, the data on the DBO-DB7 inputs is latched until the CS and WR signals go low again. When
CS is high, the data inputs are disabled, regardless of the state of the WR signal.
The digital inputs of the AD7628 provide TTL compatibility when operated from a supply voltage of 10.8 V
to 15.75 V.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3--47

AD7628
Advanced LinCMOS™ DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
R

R

R

2R

2R

2R

2R

S1

S8

R
~"",,"-RF8A

~-+--~~~

__

~~~

~--~~--~

__

__

~+----+-e------OUTA

~~-----e~--

__-------AGND

FIGURE 1. SIMPLIFIED FUNCTIONAL CIRCUIT FOR DACA
RFBA

R

......--- OUT A

VREFA -'VY
r_--_----------<_----..-

-~
256

FIGURE 2. AD7628 EQUIVALENT CIRCUIT, DACA LATCH LOADED WITH 11111111.
MODE SELECTION TABLE
DACAl
DACB

L

:c:

cs

WR

DACA

DACB

L

L

L

WRITE

HOLD

H

L

L

HOLD

WRITE

X

H

X

HOLD

HOLD

X

X

H

HOLD

HOLD

low level. H "-- high level, X

don't care

TEXAS"'"

INSTRUMENTS
3--48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7628
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
TYPICAL APPLICATION OAT A
The AD7628 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
vitA)
± 10 v

VDD~-

. I .•

(141

DBO

(71

INPUT
BUFFER

">---.... VOA

DB7

I DACAl
(61

DACB

(151

CS

(161

WR

CONTROL
LOGIC

">---.... VOB

(51

DGN~

-= '--

RECOMMENDED TRIM
RESISTOR VALUES
R1. R3

500 !.l

R2. R4

150 !.l

VilBI
± 10 v

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pFI are required when using high-speed amplifiers to prevent ringing
or oscillation.

FIGURE 3. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-49

AD7628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
TYPICAL i APPLICATION DATA
VilA)
R6 (See Note B)

± 10 V

20 kfl

··

I

I
(7)

DB7

(6)

I DACAl
I DACB

115) CS
116)

(See
Note B)

WR

R5

R7

INPUT
BUFFER

10 k[l
Rll

VOA

5 k[l

RFBA

(See
Note B)

CONTROL
LOGIC

R8

R9

15)

DGN~
-= L..

10 k[l

_ _ _ _ _ _ _ _ _ _ REFB
_

VOB

RECOMMENDED TRIM
RESISTOR VALUES
Rl, R3

500 [l

R2, R4

150 [l

20 k[l

± 10 V
Vii B)

-=

NOTES: A. Rl, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust Rl
for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and Rl0.
C. Cl and C2 phase compensation capacitors 110 pF to 15 pF) may be required if Al and A3 are high-speed amplifiers.

FIGURE 4. BIPOLAR OPERATION (4-QUADRANT OPERATION)
TABLE 1. UNIPOLAR BINARY CODE
DAC LATCH CONTENTS
LSBt
MSB

DAC LATCH CONTENTS

ANALOG OUTPUT

MSB

LSB*

- Vi (255/256)

11111111

Vi 1127/128)

10000001

-Vi (129/256)

10000001

Vi 11/128)

01111111
00000001
00000000

=

-Vi 1128/256)

=

-Vi/2

- Vi 1127/256)
-Vi (1/256)
- Vi 10/256)

=0

10000000

OV

01111111

-Vi 11/128)

00000001

-Vi 11271128)

00000000

- Vi 1128/128)

* 1 LSB =

12 -8)Vi

TEXAS

12- 7 )Vi

~

INSTRUMENTS
3-50

ANALOG OUTPUT

11111111
10000000

t 1 LSB

TABLE 2. BIPOLAR (OFFSET BINARY) CODE

POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

AD7628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA

microprocessor interface information

A8-A15

ADDRESS BUS

I--~

r - - - -....- - - - f DACA/DACB
ADDRESS
DECODE
LOGIC

CPU
8051

A
AD7628

WRr---.:.j

ALE

ADO-AD7

NOTE:

DATA BUS

I-------------~----~

A = decoded address for AD7628 DACA.
A + 1 = decoded address for AD7628 DACB.

FIGURE 5. AD7628 - INTEL 8051 INTERFACE

ADDRESS BUS

A8-A 15 r - - - "

VMA
CPU
6800

ADDRESS
DECODE
LOGIC

A

r - - - -....- - - - I DACA/DACB

AD7628

. - - - -....- - - - - 1 WR
.--_>M D: O
,,2 I-----IL,.-/

DO-D7

NOTE:

DATA BUS

I-------------~----~

A = decoded address for AD7628 DACA.
A + 1 = decoded address for AD7628 DACB.

FIGURE 6. AD7628 - 6800 INTERFACE

~

TEXAS
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3-51

A07628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
TYPICAL APPLICATION OAT A

voltage-mode operation
The AD7628 current-multiplying D/A converter can be operated in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output pin. The analog output voltage is then available at the reference
voltage pin. An example of a current-multiplying D/A converter operating in voltage mode is shown in
Figure 7. The relationship between the fixed input voltage and the analog output voltage is given by the
following equation:
Analog output voltage = fixed input voltage (D/256)
where D = the digital input. In voltage-mode operation, the AD7628 meets the following specification:
LINEARITY ERROR

TEST CONDITIONS

TYP

MIN

MAX

L-A_na_l~og~ou_t~pu_t_v_o_lta~g~e_f_or_R_E_F_A~,_B-L_______V~D~D~~__
12__
V~.OUTAor._O_U_T_B_~
__5_V________L -_ _ _ _ _ _ _ _ _ _ _ _- L_ _ _ _~

R

R

R

REF~~~---'~~~--~--~~----'--------,

(Analog
output

voltage)

2R

2R

2R

2R

R

L----+-4..-----+---it-------t-....- - . - - OUT

(Fixed input

voltage)
L-------4..------~t---------

__~~---AGND

FIGURE 7. CURRENT-MULTIPLYING D/A CONVERTER OPERATING IN VOLTAGE MODE

TEXAS

l!1

INSTRUMENTS
3-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7524
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
D3008, SEPTEMBER 1986-REVISED AUGUST 1991

•

D DR N PACKAGE

Advanced LinCMOS'" Silicon-Gate
Technology

(TOP VIEW)

•

Easily Interfaced to Microprocessors

•

On-Chip Data Latches

•

Monotonic over the Entire AID Conversion
Range

•

Segmented High-Order Bits Ensure LowGlitch Output

•

Designed to be Interchangeable with Analog
Devices AD7524, PMI PM-7524, and Micro
Power Systems MP7524

•

OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3

RFB
REF
VDD
WR
CS

DBO
DB1
DB2
FN PACKAGE
(TOP VIEW)

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

N

~~ug::±;

ooza:a:
3212019

KEY PERFORMANCE SPECIFICATIONS
Resolution

8 Bits

Linearity error

Y, LSB Max

Power dissipation

at VDD

=

5 V

100 ns.Max

Propagation delay

80 ns Max

4

NC

6

DB6
DB5

5 mW Max

Settling time

GND
DB7

17

VDD
WR

16

NC

15

CS

14

DBO

18

8
9 1011 12 13

"''''UN0 0

OJOJZOJOJ

00

NC - No internal connection

description
The TLC7524 is an Advanced LinCMOS'M 8-bit digital-to-analog converter (DAC) designed for easy interface
to most popular microprocessors.
The TLC7524 is an 8-bit multiplying DAC with input latches and with a load cycle similar to the "write"
cycle of a random access memory. Segmenting the high-order bits minimizes glitches during changes in
the most-significant bits, which produce the highest glitch impulse. The TLC7524 provides accuracy to
Yo LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5 milliwatts
typically.
Featuring operation from a 5-V to 15-V single supply, the TLC7524 interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the TLC7524 an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from 0 ac to 70 ac. The TLC75241 is characterized for
operation from - 25 ac to 85 ac. The TLC7524 E is characterized for operation from - 40 ac to 85 ac.

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is cOrrent as of pUblication
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright

© 1991, Texas Instruments Incorporated

3-53

TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
functional block diagram
VDD

114
REF

R

15

R

2R

//
n

R

2R

2R

2R

2R

16

~

:,

S-1

I
I

I S-2

:1
,
I

,

1

:1

,
:

I

,
4

5

DUT1
DUT2

GND

11

6

DB6

3

I

1,

DB7
(MSB)

1
2

Data Latches

,

R

1

,
,
'/

I

S-8

:1

1

12
13

/1

, S-3

DBO
ILSB)

DB5

'~-----------v~----------~
Data Inputs
operating sequence
""14----tsuICS)----~"___I..!_

CS

------..,"

~------------~~

-----,'

,14

WR

tw(WR)--~

_ _ _ _ _ _....J

j4-- tsu(D)---+I

~thID)

I

)>-------

DBO-DB7 - - - - - - - - - - - - (

~

TEXAS
INSTRUMENTS
3-54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGlTAL·TO·ANALOG CONVERTER
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16.5 V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VDD + 0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 /lA
Operating free-air temperature range: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to 70°C
TLC75241 .......................
- 25°C to 85 °C
TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package ........ 260°C

recommended operating conditions
VDD - 5 V
MAX
MIN
NOM
4.75

Supply voltage, VDD
Reference voltage. V ref

5

5.25

vDD - l5V
MIN NOM
MAX
14.5

High-level input voltage, VIH

15

15.5

V

13.5

2.4

Low-level input voltage, VIL

0.8
40

CS setup time, tsu(CS)

V
V

±10

±10

UNIT

1.5

V

40

ns

a

a

ns

Data bus input setup time, tsu(D)

25

25

ns

Data bus input hold time, th(D)

10

10

ns

Pulse duration, WR low, tw(WRI

40

40

CS hold time, th(CS)

Operating free-air temperature,

I TLC7524C
TA I TLC75241
I

TLC7524E

ns

a

70

a

70

-25

85

-25

85

-40

85

-40

85

± 10 V.

electrical characteristics over recommended operating free-air temperature range. Vref
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
IIH

High-level input current

VI = VDD

IlL

Low-level input current

VI = a
DBO-DB7 at

Output leakage
Ilkg

IDD

current

Supply current

oun
OUT2

Cj
Co
Co

a V,

WR, CS at

a V,

Vref = ±10 V
DBO-DB7 at VDD, WR, CS at

a V,

DBO-DB7 at VIHmin or VILmax

Standby

DBO-DB7 at

Again/AVDD
Input capacitance,

Output capacitance
Output capacitance

a V or VDD

AVDD = ±10%
VI =

DBO-DB7, WR, CS

VDD - l5V
MIN
TYP MAX

0.01

a

10

10

p.A

-10

-10

p.A

±400

±200

±400

±200

1

2

500

500

p.A

0.04

%FSR/%

0.16

0.005

5

5

oun

DBO-DB7 at

30

30

OUT2

WR and CS at

120

120

OUTl

DBO-DB7 at VDD,

120

120

OUT2

WR and CS at

30

30

a V,
aV
aV

Reference input impedance

5

(Pin 15 to GND)

UNIT

nA

Vref = ±10 V

Quiescent

Supply voltage sensitivity,
kSVS

VDD - 5 V
MIN
TYP
MAX

TEST CONDITIONS

°c

20

5

20

mA

pF
pF
pF
k[J

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-55

TLC7524

Advanced LinCMOSTM 8·BIT MUl TIPl VING
DlGITAl·TO·ANAlOG CONVERTER
±10 V,

operating characteristics over recommended operating free· air temperature range, Vref
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

MAX

VDD = 15V
MIN Typt
MAX

UNIT

vDD = 5 V

TEST CONDITIONS

MIN

TYP

±0.5

±0.5

LSB

Gain error

Linearity error
See Note 1

±2.5

±2.5

LSB

Settling time Ito Y, LSB)

See Note 2

100

100

ns

See Note 2

80

80

ns

Propagation delay from
digital input to 90% of
final analog output current

Feedthrough at OUT1 or OUT2

Vref ~ ± 10 v 11 OO-kHz sinewave)
WR and CS at a v, DBO-DB7 at a

Temperature coefficient of gain

TA

NOTES:

~

0.5

v
±O.OO4

25°C to MAX

0.5

±O.OOl

%FSR

O/OFSR/"C

1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range IFSR) ~ V ref - 1 LSB.
2. OUT1 load ~ 100 0, Cext ~ 13 pF, WR at 0 V, CS at 0 V, DBO-DB7 at 0 V to VDD or VDD to 0 V.

principles of operation
The TLC7524 is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches,
and data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded and these decoded bits, through a modification in the R-2R ladder, control three equally
weighted current sources. Most applications only require the addition of an external operational amplifier
and a voltage reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire
reference current, Iref, is switched to OUT2. The current source 1/256 represents the constant current
flowing through the termination resistor of the R-2R ladder, while the current source Ilkg represents leakage
currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital
input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2
and the on-state switch capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the
situation is reversed as shown in Figure 1. Analysis of the circuit for all digital inputs high is similar to
Figure 1; however, in this case, Iref would be switched to OUT1.
Interfacing the TLC7524 D/A converter to a microprocessor is accomplished via the data bus and the CS
and WR control signals. When CS and WR are both low, the TLC7524 analog output responds to the data
activity on the DBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data
directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBO-DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs
are disabled regardless of the state of the WR signal.
The TLC7524 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.

TEXAS . "
INSTRUMENTS
3-56

POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

TLC7524
Advanced LinCMOSTM 8·BIT MUL TIPLVING
DIGITAL·TO·ANALOG CONVERTER
principles of operation (continued)
} I " " - R - - - - - RFB

.------1
.....-.1-----

OUT1

~...25-6-~-_._-~--I-lk9-~~_=t-t-----f~_=t-1-2-0-P-F----

OUT2

'.."~t

J""

Iref - - .
REF

Figure 1. TlC7524 Equivalent Circuit With All Digital Inputs low
VDD

RA - 2k{l
(see Note 3)

DBO-DB7
>---_~Output

cs----I
WR----I
GND

Figure 2. Unipolar Operation (2·Quadrant Multiplication)
Vref

VDD
20 kr!

RA - 2 k{l
(see Note 3)

20 kr!

RB

10 kr!

DBO·DB7

>"'--Output

CS - - - - i

WR----I

-=Figure 3. Bipolar Operation (4-Quadrant Operation)
NOTES:

3. RA and RB used only if gain adjustment is required.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

~

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-57

TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
principles of operation (continued)
Table 1. Unipolar Binary Code

Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT

DIGITAL INPUT
(SEE NOTE 5)
MSB

MSB

LSB

ANALOG OUTPUT

LSB

11111111

- V ref (255/256)

11111111

Vref (127/128)

10000001

- Vref (129/256)

10000001

Vref (1/128)

10000000

-Vref (128/256)

01111111

- Vref (127/256)

00000001

- Vref (1/256)

00000000
NOTES:

(SEE NOTE 6)

ANALOG OUTPUT

5. LSB
6. LSB

=
=

=

0

10000000

- V re f /2

01111111

0

-Vref (1/1281

00000001

-Vref (127/128)

00000000

-Vref

1/256 (Vrefl.
1/128 (Vref).

microprocessor interfaces

00-07

Data Bus

r---------------------------~

Z-80A

WRI----\

~-------~WR

Decode
Logic

AO-A15

Address Bus

r-----------------------------------~

Figure 4. TLC7524-Z-80A Interface

00-07

>

Data Bus

M

6800

DBO-DB7
<1>2

VMA

OUT1

~

WR

OUT2
CS

I

Decode
Logic

t}
AO-A15

,
Address Bus

Figure 5. TLC7524-6800 Interface

TEXAS

~

INSTRUMENTS
3-58

TlC7524

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

>

TLC7524
Advanced linCMOSTM 8·BIT MULTIPLYING
DIGITAL· TO·ANAlOG CONVERTER
microprocessor interfaces (continued)
"-

A8-A15

Address 8us

8051

"r--

/"r-

WR

r--

"

Decode
Logic

>
cs

1

ALE

ADO-AD7

8-8it
Latch

>

1

OUTl

TLC7524

WR

OUT2
D80-DB7

Address/Data Bus

1i

.....

Figure 6. TLC7524-8051 Interface

TEXAS . "
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-59

TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
APPLICATION INFORMATION

voltage· mode operation
It is possible to operate the TlC7524 current multiplying O/A converter in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output pin. The analog output voltage is then available at
the reference voltage pin. Figure 7 is an example of a current multiplying O/A, which is operated in voltage
mode.
R
R
R
REF (Analog Output Voltage) ...JV\,..,.........-.J\IVv----4J~...\--J'M,...-...-....,
2R

2R

2R
"0"

R

"1"

~

L...-+------i----t---it--- OUTl (Fixed Input Voltage)
__- -__~t_---OUT2

~--~t----~

Figure 7. Voltage Mode Operation
The relationship between the fixed input voltage and the analog output voltage is given by the following
equation:
Vo = VI (0/256)
where
Vo = analog output voltage
VI = fixed input voltage
o = digital input code converted to decimal
In voltage-mode operation, the TlC7524 will meet the following specification:
PARAMETER
Linearity error at REF

VDD

=

5 V,

TEST CONDITIONS
OUT2 at GND, TA

oun = 2.5 V,

=

"!1

.
TEXAS
INSTRUMENTS
3-6D

POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

Doe to 7Doe

TLC7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
D2979, JANUARY 1987-REVISED AUGUST 1991

•
•

ow

Advanced LinCMOS"' Silicon-Gate
Technology
Easily Interfaced to Microprocessors

•

On-Chip Data Latches

•

Monotonic Over the Entire AID Conversion
Range

•

Designed to be Interchangeable with Analog
Devices AD7528 and PMI PM-7528

•

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

•

Voltage-Mode Operation

AGND
OUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4 '""\... _ _...r-

(TOP VIEW)
8 bits

Power Dissipation at VDD
Settling Time at VOO

<{~~~CXl

fE:::>t.:J:::>fE

a:O<{Oa:

1/2 LSB

Linearity Error

=

=

5V

5 V

Propagation Delay at V OD

=

5 V

OUTB
RFBB
REFB
VDD
WR
CS
DBO (lSB)
DB1
DB2
DB3

FN PACKAGE

KEY PERFORMANCE SPECIFICATIONS
Resolution

OR N PACKAGE
(TOP VIEW)

5 mW

3

2

1 20 19

100 ns

4

18

80 ns

5

17

6

16

8

14

DACA/DACB
(MSB)DB7
DB6

description

15

REFB
VDD
WR
CS
DBO(lSB)

The TLC7528 is a dual 8-bit digital-to-analog
9 1011 12 13
converter designed with separate on-chip data
Ln"\tMN
latches and featuring excellent DAC-to-DAC
CXlCXlCXlCXlCXl
matching. Data is transferred to either of the two
00000
DAC data latches via a common 8-bit input port.
Control input DACA/DACB determines which
DAC is to be loaded, The "load" cycle of the
TLC7528 is similar to the "write" cycle of a random-access memory, allowing easy interface to most
popular microprocessor busses and output ports. Segmenting the high-order bits minimizes glitches during
changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7528 operates from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). Excellent
2- or 4-quadrant mUltiplying makes the TLC7528 a sound choice for many microprocessor-controlled gainsetting and signal-control applications. It can be operated in voltage mode, which produces a voltage output
rather than a current output. Refer to the typical application information in this data sheet.
The TLC7528C is characterized for operation from O°C to 70°C. The TLC75281 is characterized for
operation from - 25°C to 85 DC. The TLC7528E is characterized for operation from - 40 °C to 85°C.

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.

~

Copyright

© 1991, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-61

TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPL VING
DlGlTAL·TO·ANALOG CONVERTER
functional block diagram
DBO (14)

REFA

(13)

Data
Inputs

••
•
•
•
•

(3) RFBA
(4)

(12)

(10)

(2) OUTA

B

(11 )
Input
Buffer

Latch
A

8
DAC A

(9)
(B)
(1) AGND

DB7 (7)

(19) RFBB

WR (16)
CS (15)

(20)OUTB

8

DACA/DACB (6)

Latch
B

Logic
Control

8

REFB

operating sequence

j4

DACA/DACB

'\14
\

~j4

tsu(CS)

I

I

...I

tsu(DAC)

I

j+--tsu(D)

X

~

TEXAS
INSTRUMENlS
3-62

~ th(DAC)

/

if~~~I
X

Data In Stable

POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

th(CS)

I

j4--tW(WR)~

'{
DBO-DB7

.!

th(D)

TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGlTAL·TO·ANALOG CONVERTER
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage range, VOO (to AGNO or OGNO) ......................... -0.3 V to 16.5 V
Voltage between AGND and OGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± VOD
Input voltage range, VI (to OGNO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VOO + 0.3
Reference voltage, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ±25 V
Feedback voltage VRFBA or VRFBB (to AGNO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Output voltage, VOA or VOB (to AGNO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Peak input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 J.'A
Operating free-air temperature range: TLC7528C . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to 70°C
TLC75281 .......................... - 25°C to 85 °C
TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: OW or N package ....... 260°C

recommended operating conditions
Voo - 4.75 V to 5.25 v
MIN

NOM

MAX

voo MIN

±10

Reference voltage, VrefA or VrefS
High-level input voltage, VIH

MAX

50

UNIT
V

13.5
0.8

CS setup time. tsulCSI

NOM
±10

2.4

Low-level input voltage. VIL

14.5 V to 15.5 V

V
1.5

V

50

ns

0

0

ns

DAC select setup time, tsulDACI

50

50

ns

DAC select hold time. thIDAC)

10

10

ns

Data bus input setup time tsulD)

25

25

ns

0

0

ns

50

50

CS hold time. thlCSI

Data bus input hold time thlDI
Pulse duration. WR low, twlWRl
Operating free·air temperature, TA

TLC7528C

ns

0

70

0

70

TLC75281

-25

85

-25

85

TLC7528E

-40

85

-40

85

°C

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

3-63

TLC7528
Advanced linCMOSTM DUAL 8·BITMULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
electrical characteristics over recommended operating free-air temperature range,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

"H

High-level input current

"L

Low-level input current

V,
V,

=
=

VDD = 5 V
MIN Typt
MAX

VDD = 15V
MIN Typt
MAX

,

10

VDD
0

-10

Reference input impedance

5

(Pin 15 to GND)

12

20

5

12

UNIT

10

~A

-10

~A

20

kll

DACA data latch loaded
OUTA
"kg

with 00000000,

current
OUTB

VrefB

=

DC supply sensitivity,

aVDD

a gain/a VDD
100

Supply current (quiescent)

100

Supply current (standby)
Input

=

± 10%

DBO-DB7 at V'Hmin or

±1%

± 1%

0.04

0.02

%/%

1

1

mA

0.5

mA

DBO-DB7

10

10

WR, CS
DACA/DACB

15

15

50

50

120

120

DBO-DB7 at 0 V or VDD

Output capacitance.

with 00000000

(OUTA, OUTB)

DAC data latches loaded

t All typical values are at T A

=

25°C.

TEXAS

pF

pF

with 11111111

-1!1

INSTRUMENTS
3-64

±200

0.5

V,Lmax

DAC data latches loaded
Co

±400

±10 V

(REFA to REFB)

capacitance

±200
nA

with 00000000,

Input resistance match

Ci

±400

VrefA = ±10V
DACB data latch loaded

Output leakage

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
operating characteristics over recommended operating free-air temperature range.
VrefA = VrefB = 10 V. VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

VDD = 5 V

TEST CONDITIONS

MIN

TYP

VDD -

MAX

MIN

15V

TYP

MAX

UNIT

± 112

± 112

Settling time (to 112 LSB)

See Note 1

100

100

ns

Gain error

See Note 2

2.5

2.5

LSB

-65

-65

-65

-65

0.007

0.0035

Linearity error

AC feedthrough

I REFA to OUT A
I REFB to OUTB

Temperature coefficient of gain
Propagation delay (from digital input
to 90% of final analog output current)
Channel-tochannel isolation

I REFA to OUTB
I REFB to OUTA

See Note 3
See Note 4
See Note 5

80

See Note 6
See Note 7

80

LSB

dB
%FSRIOC
ns

77
77

77
77

dB

160

440

nVs

30

60

nVs

-85

-85

Measured for code trar.sition from
Digital-to-analog glitch impulse area

00000000 to 11111111.
TA = 25°C
Measured for code transition from

Oigital crosstalk glitch impulse area

00000000 to 11111111.
TA = 25°C

Harmonic distortion
NOTES:

1.
2.
3.
4.
5.
6.
7.

Vi = 6 V rms.

I = 1 kHz.

TA = 25°C

dB

OUTA. OUTB load = 100!l. Cext = 13 pF; WR and CS at 0 V; OBO-OB7 at a V to VOO or VOO to a V.
Gain error is measured using an internal feedback resistor. Nominal Full Scale Range (FSR) = Vref - 1 LSB.
Vref = 20 V peak-to-peak, lOa-kHz sine wave; OAC data latches loaded with 00000000.
Temperature coefficient of gain measured from ODe to 25°C or from 25°C to 70°C.
VrefA = VrefB = 10 V; OUTA/OUTBload = 100!l, Cext = 13 pF; WR and CS at a V; DBO-DB7 at a V to VDD or VDD to a V.
Both OAC latches loaded with 11111111; VrefA = 20 V peak-to-peak. lOa-kHz sine wave; VrefB = 0; TA = 25°C.
Both DAC latches loaded with 11111111; VrefB = 20 V peak-to-peak, lOa-kHz sine wave; V ref A = 0; T A = 25°C.

principles of operation
The TLC7528 contains two identical8-bit multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg incjependent of
the switch state. Most applications require only the addition of an extemal operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both
DACs share the analog ground pin 1 (AGND). With all digital inputs high, the entire reference current flows
to OUT A. A small leakage current (llkg) flows across internal junctions, and as with most semiconductor
devices, doubles every 10 DC. Co is due to the parallel combination of the NMOS switches and has a value
that depends on the number of switches connected to the output. The range of Co is 50 pF to 120 pF
maximum. The equivalent output resistance ro varies with the input code from 0.8R to 3R where R is
the nominal value of the ladder resistor in the R-2R network.
.
Interfacing the TLC7528 to a microprocessor is accomplished via the data bus, CS, WR, and DACA/DACB
control signals. When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB
control line, responds to the activity on the DBO-DB7 data bus inputs. In this mode, the input latches are
transparent and input data directly affects the analog output. When either the CS signal or WR signal
goes high, the data on the DBO-DB7 inputs is latched until the CS and WR signals go low again. When
CS is high, the data inputs are disabled regardless of the state of the WR signal.
The digital inputs of the TLC7528 provide TTL compatibility when operated from a supply voltage of 5 V,
The TLC7528 may be operated with any supply voltage in the range from 5 V to 15 V, however, input
logic levels are not TTL compatible above 5 V.

TEXAS

"'!J

INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265

3-65

TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING·
DIGITAL· TO·ANALOG CONVERTER
R

R

R

VREFA
2R

2R

51

52

2R

2R

2R

58

R

I

L

~'VIr-RFBA

I
I

r--4~~----r-e------OUTA
~--~~--~~~r----~~--~--------AGND

And Drivers

Figure 1. Simplified Functional Circuit for DACA
RFBA
R

VREFA--~~--~~------~----~~~---OUTA

_1-

256

Figure 2. TLC7528 Equivalent Circuit. DACA Latch Loaded With 11111111.
MODE SELECTION TABLE
DACAl
DACB
L
H

L

~

cs

WR

DAC.A

DACB

L
L

X

L
L
H

X

X

X

H

WRITE
HOLD
HOLD
HOLD

HOLD
WRITE
HOLD
HOLD

low level, H

~

high level, X

~

don't care

~

TEXAS
INSTRUMENTS
3-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7528
Advanced LinCMOSTM DUAL 8-BIT MUL TIPL VING
DIGITAL-TO-ANALOG CONVERTER
APPLICATION INFORMATION
The TLC7528 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
VilA)

± 10 V

VDD~(14)

DBO

·••

••
•

(7)

(6)

8

Input
8uffer

VOA

087

I DACAl
DAC8

(15)

CS

Control

(16)

WR

Logic

VOB

DGN~

-=

LRECOMMENDED TRIM
RESISTOR VALUES

NOTES:

Rl, R3

500

R2, R4

150

n
n

1. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
2. C 1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing
or oscillation.

Figure 3. Unipolar Operation 12-Quadrant Multiplication)

~

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-67

TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
APPLICATION INFORMATION
Vi(AI
±10 V

R6 (see Note 2)
20 kll

VDD~-(1411 DBO

---- -- -

-REFA

(see
Note 2)
R7

Input

I :

Buffer

R5

10 kll

(71

Rll
5 kll

(61
(151

Control

(161

Logic

R8

DGND~
.L •

10 kll

REFB

VOB

-= ' - - - - - - - - - - - -

(see Note 2)
Rl0
20 kll

± 10 V
Vi(BI

NOTES:

1. Rl, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust Rl
for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
2. Matching and tracking are essential for resistor pairs R6, R7, R9, and Rl0.
3. Cl and C2 phase compensation capacitors 110 pF to 15 pFI may be required if Al and A3 are high-speed amplifiers.

Figure 4. Bipolar Operation (4·Quadrant Operation)
Table 2. Bipolar (Offset Binary) Code

Table 1. Unipolar Binary Code
DAC LATCH CONTENTS
MSB

LSBt

ANALOG OUTPUT

DAC LATCH CONTENTS
MSB

ANALOG OUTPUT

11111111

- Vi (255/2561

11111111

Vi (1271128)

10000001

-Vi (129/2561

10000001

Vi (11128)

10000000
01111111
00000001
00000000

-Vi (128/2561

=

-Vi/2

- Vi (127/256)
-Vi (1/256)
-Vi (0/256)

=

0

10000000

OV

01111111

-Vi (1/128)

00000001

- Vi (1271128)

00000000

- Vi (128/128)

TEXAS . "
INSTRUMENTS
3-6B

LSB*

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DlGlTAL-TO-ANALOG CONVERTER
APPLICATION INFORMATION
microprocessor interface information

A8-A15

Address 8us

t--"-7I

,-----+---~DACA/DACB

Address
Decode
Logic

CPU
8051

A

TLC7528

WRI----'
ALE

Data Bus

NOTE:

A = decoded address for TLC7528 DACA.
A + 1 = decoded address for TLC7528 DAC8.

Figure 5. TLC7528 - INTEL 8051 Interface

A8-A15

Address Bus

1---..,
A

VMA
CPU
6800

00-07

NOTE:

, - - - - - + - - - ; DACA/DACB

Address
Decode
Logic

TLC7528

Data Bus
~--------------~~-----~

A = decoded address for TLC7528 DACA.
A + 1 = decoded address for TLC7528 DACB.

Figure 6. TLC7528 - 6800 Interface

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-69

TLC7528
Advanced LinCMOSTM DUAL 8-BIT MUL TIPL VING
DIGITAL-TO-ANALOG CONVERTER
APPLICATION INFORMATION

Address Bus

AS-A 151-_ _",

,------+----1 DACA/DACB
cs
TLC752S
CPU
ZSO-A

DO-D7~_ _ _ _ _ _ _ _ _D_a_ta_Bu_s_ _ _~~_ _ _ _ _- J

NOTE:

A
A

=

decoded address for TLC7528 DACA.

+ 1 = decoded address for TLC7528 DACB.

Figure 7. TLC7528 TO Z-80A Interface

programmable window detector
The programmable window comparator shown in Figure 8 will determine if voltage applied to the DAC
feedback resistors are within the limits programmed into the TLC7528 data latches. Input signal range
depends on the reference and polarity, that is, the test input range is 0 to -Vref. The DACA and DACB
data latches are programmed with the upper and lower test limits. A signal within the programmed limits
will drive the output high.
Test
Input -

o to

- Vref

Data
Inputs

VCC

VDD
..... . - - - - - - - - ,
RFBA

•

(71 DB7
__~~~(1~5,1 CS
_-++-l_(c;.1.;:.61'-1WR

(171

(31

1 kG

(11
AGND __-I-~~-,

PASS/FAIL
OUTPUT

TLC7528

_-+..-t~(6"-11 DACA/DACB
1201

+ Vref __-+~""Ic;.l.::.SI+-,R::.:EF-=B'---I
(51 DGND
RFBB
(191

Figure 8. Digitally Programmable Window Comparator (Upper- and Lower-Limit Tester)

TEXAS

~

INSTRUMENTS
3-70

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7528
Advanced LinCMOSTM DUAL 8-BIT MULTIPLYING
DlGlTAL-TO-ANALOG CONVERTER
APPLICATION INFORMATION
digitally controlled signal attenuator
Figure 9 shows the TLC7528 configured as a two-channel programmable attenuator. Applications include
stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB
range.
Attenuation dB

VDD

=

=

-20 1091O D/256, D

digital input code

(17lr---;:=====~::;:}fI3!l.1_ _ _ _ _,
RFBA 121

OUTA

Output

D~O I-~'--

_ _---.

•
DB7

TLC7528

CS 1151
WR 1161
DACA/DACB .,.1~61,--_ _ _ _ __
(181
VOB

REFB
AGND 111

Figure 9. Digitally Controlled Dual Telephone Attenuator
Table 3. Attenuation vs DACA. DACB Code
ATTN(dBI

DAC INPUT CODE

CODE IN
DECIMAL

ATTN (dB)

DAC INPUT CODE

CODE IN
DECIMAL

0

11111111

255

8.0

01100110

102

0.5

11110010

242

8.5

01100000

96

1.0

11100100

228

9.0

01011011

91

1.5

11010111

215

9.5

01010110

86

2.0

11001011

203

10.0

01010001

81

2.5

11000000

192

10.5

01001100

76

3.0

10110101

181

11.0

01001000

72

3.5

10101011

171

11.5

01000100

68

4.0

10100010

162

12.0

01000000

64

4.5

10011000

152

12.5

00111101

61

5.0

10010000

144

13.0

00111001

57

5.5

10001000

136

13.5

00110110

54

6.0

10000000

128

14.0

00110011

51

6.5

01111001

121

14.5

00110000

48

7.0

01110010

114

15.0

00101110

46

7.5

01101100

108

15.5

00101011

43

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-71

TLC7528
Advanced LinCMOSTM DUAL 8·BIT MUlTIPl VING
DIGITAL· TO·ANAlOG CONVERTER
APPLICATION INFORMATION
programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications in which microprocessor control of filter parameters is required.
As shown in Figure 10, DACA 1 and DACBl control the gain and Q of the filter while DACA2 and DACB2
control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for
the cutoff-frequency equation to be true. With the TLC7528, this is easily achieved.

1
fc = 2n Rl Cl
The programmable range for the cutoff or center frequency is
4.5. This defines the limits of the component values.

°

to 15 kHz with a Q ranging from 0.3 to

C3

14) REFA

VI

OUTA 12)

117)

VOD
114) DBO
Data

17)

In

115)
116)

••

DB7

RFBA

AGND 11)

TLC7528

CS

OUTB 120)

WR
RFBB

IS) DGND
"::"

16)

13)

119)

REFB
DACA/DACB

Bandpass
Out

DACA1 AND DACB1

D.t.

In

·

17).
115)

"::"

118)

C2

TLC7528

~7

CS
116) WR

OUT8120)

Low Pass

RFBB 119)
IS) DGND

Out

L-__________~R~EF~B~I~1~8)~========:r--r_-t~

16) i5ACA/DACB

Circuit Equations:

DACA2 AND DACB2

Cl = C2. Rl = R2. R4 = RS
Q=

Ao
NOTES:

A. Op-amps Al, A2. A3. and A4 are TL287.

=

R3
R4
_ RF
RS

8. C3 compensates for the op-amp gain-bandwidth limitations.
C. DAC equivalent resistance equals

256 x (DAC ladder resistance)
DAC digital code

Figure 10. Digitally Controlled State-Variable Filter

TEXAS •
INSTRUMENTS
3-72

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RF
Rfb(DACB1)

TLC7528
Advanced LinCMOS™ OUAl 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
APPLICATION INFORMATION

voltage-mode operation
It is possible to operate the TLC7528 current multiplying D/A converter in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output pin. The analog output voltage is then available at
the reference voltage pin. Figure 11 is an example of a current multiplying D/A, which is operated in voltage
mode.
R
R
R
REF (Analog ..."VI.,..,......--'VI/'v-......~---'\IV\..-...- - . .
Output Voltage)

Figure 11. Voltage-Mode Operation
The relationship between the fixed input voltage and the analog output voltage is given by the following
equation:
Va
where
Va
VI
D

= VI (D/256)
= analog output voltage
= fixed input voltage
= digital input code converted to decimal

In voltage-mode operation, the TLC7528 will meet the following specification:
PARAMETER
Linearity error at REFA or REFS

TEST CONDITIONS

VDD

~

5 V, OUTA or OUTS at 2.5 V, TA

~

oDe

to 70 0e

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-73

3-74

TLC7628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
D3269, APRIL 1989-REVISED AUGUST 1991

•
•

OW OR N PACKAGE

Advanced LinCMOS,M Silicon-Gate
Technology

(TOP VIEW)
AGND

Easy Microprocessor Interface

•

On-Chip Data Latches

•

Digital Inputs are TTL-Compatible with
10.8-V to 1S.7S-V Power Supply

OUTB

OUTA

RFBB

RFBA

REFB

REFA

VDD
WR

DGND
DACAiDACB

•

Monotonic Over the Entire AID Conversion
Range

•

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320

CS

(MSB) DB7

DBO (LSB)

DB6

DBl

DB5

DB2

DB4

DB3

FN PACKAGE
KEY PERFORMANCE SPECIFICATIONS
Resolution

(TOP VIEW)

8 bits

Linearity Error

112 LSB

Power Dissipation

20mW

Settling Time

100 ns

Propagation Delay

80 ns

0 ro
--.... VOA

DB7

I DACAl
6

DACB

15

CS

16

WR

Control
Logic

>---"'VOB

5
DGN~

-=

L-

RECOMMENDED TRIM
RESISTOR VALUES

NOTES:

R1, R3

500 Il

R2, R4

150 Il

VilBI

± 10 V

1. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment
with digital input of 255.
2. C1 and C2 phase compensation capacitors 110 pF to 15 pFI are required when using high-speed amplifiers to prevent ringing
or oscillation.

Figure 4, Unipolar Operation (2-Quadrant Multiplication)

TEXAS

~

INSTRUMENTS
3-80

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC7628
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DlGITAL·TO·ANALOG CONVERTER
APPLICATION INFORMATION
ViiAI

± 10 v

R6 Isee Note 2)
20 kQ

R1 Isee Note 11
17
VDD""i4iDso

• I •

I :

Isee
Note 21

R5

R7

Input
Buffer

10 kn
R11

7

5 kn

6
Isee
Note 21

15
Logic

16

5
DGN~
-::-

10 kn

L..

R3 Isee Note 11

RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
NOTES:

R8

R9

Isee Note 21
R10
20 kn

± 10 V

n
150 n

500

VOB

Vil81

1. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for
VOA ~ 0 V with code 10000000 in DACA latch. Adjust R3 for VOB ~ 0 V with 10000000 in DACB latch.
2. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
3. C1 and C2 phase compensation capacitors 110 pF to 15 pFI may be required if Aland A3 are high-speed amplifiers.

Figure 5. Bipolar Operation (4·Quadrant Operation}

A8-A15

Address Bus

r - - - - -....- - - ; DACA/DACB
CPU
8051

TlC7628

WR~---l

ALE

ADO-AD7

NOTE:

Data Bus

~------------------------~--------~

A ~ decoded address for TLC7628 DACA.
A + 1 ~ decoded address for TLC7628 DACB.

Figure 6. TLC7628 -

INTEL 8051 Interface

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-81

TLC7628
Advanced LinCMOSTM DUAL 8·81T MULTIPLYING
DIGITAL· TO·ANALOG CONVERTER
APPLICATION INFORMATION

A8-A 15

r----",

Address Bus

Address
Decoder
Logic

VMA

A

,------.----i DACA/OAC8
TLC7628

CPU
6800

,------+-----i WR
r----'~080

o2r----ILJ

00-07

Data Bus

~-------------------------.~--------~

A = decoded address for TLC7628 OACA.
A + 1 = decoded address for TLC7628 DACB.

NOTE:

Figure 7. TLC7628 -

6800 Interface

voltage-mode operation
The TLC7628 current-multiplying D/A converter can be operated in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output pin. The analog output voltage is then available at the reference
voltage pin. An example of a current-multiplying D/A converter operating in voltage mode is shown in
Figure 8. The relationship between the fixed input voltage and the analog output voltage is given by the
following equation:
Analog output voltage = fixed input voltage (D/256)
where 0 = the digital input. In voltage-mode operation, the TLC7628 meets the following specification:

LINEARITY ERROR

MIN

TEST CONDITIONS

Analog oulput voltage for REFA, B

VDD

R

= 12

V, OUTA or OUT8 at 5 V, TA

R

=

TYP

MAX

25°C

R

REF~~~--'~~~--~---V~---'-------,

(Analog
output
voltage)

2R

2R

2R

2R

R

'-------+---4I......----+~....------+-....---...-OUT (Fixed input
voltage)
~------~~------~'---------__~~----AGND

Figure 8. Current-Multiplying D/A Converter Operating in Voltage Mode

-1!1

TEXAS
INSTRUMENTS
3-82 .

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-1

S

0CD

o

Sl)

:J
0-

:::r:
CO

:::S'
I

en

"C
CD
CD
0-

»
o
(")
(J)
Q)

:J
0-

o

»
(")
(J)

4-2

TL5501

6-BIT ANAlOG-TO-DiGITAl CONVERTER
D3163, DCTOBER 1988--REVISED APRIL 1990

N PACKAGE

•

6-Bit Resolution

•

Linearity Error ...

•

Maximum Conversion Rate ... 30 MHz Typ

•

Analog Input Voltage Range ..
VCC to VCC -2 V

•

Analog Input Dynamic Range ... 1 V

•

TTL Digital I/O Level

•

Low Power Consumption ... 200 mW Typ

(TOP VIEW)

± 0.8%

•

5-V Single-Supply Operation

•

Interchangeable with Fujitsu. MB40576

(lSB) 00
01
02
03
04
(MSB) 05
elK
GNO

GNO
OGTl
ANlG
REFB
ANlG
REFT
ANlG
OGTl

Vee
Vee
INPUT
Vee
Vee

description
The TL5501 is a low-power ultra-high-speed video-band analog-to-digital converter that uses the Advanced
Low-Power Schottky (ALS) process, It utilizes the full-parallel comparison (flash method) for high-speed
conversion. It converts wide-band analog signals (such as a video signal) to a digital signal at a sampling
rate of dc to 30 MHz, Because of this high-speed capability, the TL5501 is suitable for digital video
applications such as digital TV, video processing with a computer, or radar signal processing.
The TL5501 is characterized for operation from 0 °C to 70 °C,

functional block diagram
CLK------------~

ANLGINPUT--------,
REFT
EN

R

D5 (MSB)

D4

R
D3
63-TO-6
ENCODER

LATCH
AND
BUFFER

D2

R
D1

DO (LSB)

R

R
REFB

PRODUCTION DATA documents contain information

current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~~~~:~~i~ai~:1~1~ ~!:~~~ti:r :1~O::~:~:t:~~S not

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1990, Texas Instruments Incorporated

4-3

TL5501
6·BIT ANALOG·TO·DlGITAL CONVERTER

equivalents of analog input circuit

ANlG Vcc - - - - - - - - - . -

o

(See Note Al

NOTE A: Cj - nonlinear emitter-follower junction capacitance
q - linear resistance model for input current transition caused by comparator switching. VI
V refB - voltage at REFB terminal
Ibias - constant input bias current
base-collector junction diode of emitter-follower transistor

< VrefS: Infinite; eLK high: Infinite.

o -

equivalent of digital input circuit

DGTlVCC----e~------~--------~---

Vref -

GND---__~------~--~~--~-

TEXAS

'1!1

INSTRUMENTS
4-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1.4 V

TL5501

6-81Y ANAlOG-TO-DlGITAl CONVERTER
FUNCTION TABLE
STEP

ANALOG INPUT

DIGITAL OUTPUT

VOLTAGEt

3.992 V
4.008 V

0
1
I

CODE
L

L

L

L

L

L

L

L

L

L H

I
I

I

31

4.488 V
4.508 V
4.520 V

32
33

L

I
I

L H H H H H
H L

L

L

L

H

L

L

L H

L

L

I
I

:

62
63

4.984 V

H H H H H L

I
I

5.000 V

H H H H H H

t These values are based on the assumption that
V refB and V refT have been adjusted so that the
voltage at the transition from digital 0 to 1 (VZTI
is 4.000 V and the transition to full scale (VFTI is
4.992 V. 1 LSB = 16 mV.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANLG Vee (see Note 1) . . . . . . . . . . . . . .
- 0.5 V to 7 V
Supply voltage range, DGTL Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 V to 7 V
Input voltage range at digital input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- O. 5 V to 7 V
Input voltage range at analog input, VI . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to ANLG Vee+0.5 V
Analog reference voltage range, Vref . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to ANLG Vee+0.5 V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 °e to 1 50 °e
Operating free-air temperature range. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
NOTE 1: All voltage values are with respect to the network ground terminal.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage. ANLG VCC

4.75

5.25

V

Supply voltage. DGTL VCC

4.75
2

5
5

High-level input voltage. V,H

4
4

Analog reference voltage (top sidel. VrefT (see Note 2)
Analog reference voltage (bottom sidel. VrefB (see Note 21

3
-400

High-level output current. IOH
Clock pulse duration. high-level or low-level. tw

25
0

Operating free-air temperature, T A

NOTE 2: VrefB

<

V,

<

5
4

0.8
5
5.1
4.1

VrefT. VrefT - VrefB

V
V
V
V
/LA

4

Low-level output current. IOL

V
V

Low-level input voltage. V,L
Input voltage at analog input. V, (see Note 21

5.25

mA
ns

70

°c

1 V ± 0.1 V.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-5

TL5501
6·81T ANALOG·TO·DlGITAL CONVERTER

electrical characteristics over operating supply voltage range, T A
PARAMETER

25°C (unless otherwise noted)

TEST CONDITIONS
VI

~

5 V

VI

~
~

4 V
2.7 V

~

0.4 V

~

7 V

MIN

II

Analog input current
Digita: high-level input current

IlL

Digital low-level input current

VI
VI

II

Digital input current

VI

IrefB

Reference current

VrefB ~ 4 V

73
-400

Reference current

High-level output voltage

IOH

Low-level output voltage

IOL

ri

Analog input resistance

~

0
-40

20

UNIT
fJ-A
fJ-A
fJ-A

100

VrefT ~ 5 V
~ -400 p.A

IrefT

MAX
75

IIH

VOH
VOL

TYP

-4

-7.2

fJ-A
rnA

4

7.2

rnA

2.7

V

1.6 rnA

0.4
100

V
kll

1Ci

Analog input capacitance

35

65

pF

ICC

Supply current

40

60

rnA

operating characteristics over operating supply voltage range, T A
PARAMETER

25°C (unless otherwise noted)

TEST CONDITIONS

MIN

Typt

Linearity error

EL
f rnax

Maximum conversion rate

td

Digital output delay time

20
See Figure 3

MAX

UNIT

±0.8

%FSR

30
15

MHz
30

timing diagram
~twH-~~~-twl----+l

ClK . . . /

I

ANALOG
INPUT

Sample
N

\

I I

I
I

...

D1-D6_:_ _ _

l.

\0._ _ _ _oJ. I

..JX~~~A

Sample

N+1

~

~I

_....Jl.

.......
_

I

Sample

I

N+2

I

~4V

~

~~-~-A-T-A--------~~~~~A

TEXAS

+

INSTRUMENlS
4-6

I

POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

ns

TL5501
6-81T ANALOG-TO-DiGITAL CONVERTER

TYPICAL CHARACTERISTICS
IDEAL CONVERSION CHARACTERISTICS
111111

~

See Note 1
111110

..

""o

A; ~

111101

.YVI VFS

··

~

VZT
VZS + 1/2 LSB~ V

011111
•

·

/

•

••

I
: •
VFT = VFS - 33
Co
1/2 LSB
32 !
en
I
I 31

,II
000001

I
I

'/

~"

VZS /

000010

000000

V

~V

o

is

61

A:, "

...
5"" 100000

.0,

62

1

(.) 100001

~

63

I

~/

en
C7!

C")

I

<:t

CIO
0
0

N

0

.;

.;

2

I

~/

N

·••

I

CIO
CIO

•••

<:t

<:t

0

III

.; .;

0

N
III

.;

... '"
CIO

en

.;

<:t

o

>0
CIO
en NO

.; enC!
en III

.;

VI-Analog Input Voltage-V
NOTE 1: This curve is based on the assumption that V refB and V refT have been adjusted so that the voltage at the transition from·
digital 0 to 1 IVZT) is 4.000 V and the transition to full scale IVFT) is 4.992 V. 1 LSB = 16 mV.

FIGURE 1
END-POINT LINEARITY ERROR
111111

~ 63

!

111110~-+--4_~~~--+--+--4---~-+~62

111101

Ji/ V :

I-----f---

•

I

/

61

f.o{I.EL61
I

:
~": 33
<;~ 100001
"5" 100000 I---l---+---+--+--+--rrhl

.,I

••
•
4.520

Cl

l!! 4.504

-0

>
5

e::l

0
I
0

4.488

,-/'

·••

V

I

Vref - 3.976 V
4.984

V

V

V

V

/'

,,-

>
4.024

~.

V
.. .. ... ....
....

4.008

I

3.992 /i
0
0
0
0
0
0

0
0
0
0
0

0

0

0
0
0
0

0

2

31

..

0
0
0
0
0

... ....
0

0
0
0
0

62 63

32 33

Digital Input Code

FIGURE 2. IDEAL CONVERSION CHARACTERISTICS
V

5.000

-t--t-t-t-

FS-4.984

>

··

.,I

4.520

l!!

4.504

>...

4.488

VCC
f- Vref

=5V
= 3.976

-

EL6?
V

/

EL~>-EL3~ ...........

::l

e::l

0
I
0

>

··

,,/'

VzS-3.992

/'

EL2_ ~,El1 ..

.¥

4.024
4.008

V
o

8o
o
o

o

.. ..
...

0
0
0
0
0

0

0
0
0
0

;;

2

31

0
0
0
0
0

32

..
0
0
0
0

...

33

0

......

62

63

Digital Input Code

FIGURE 3. END·POINT LINEARITY ERROR

TEXAS

~

INSTRUMENTS
4-12

~

ELL ~

Cl

-0

-:i-

-

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

..

TL5602
H-BIT DlGITAL-TO-ANALOG CONVERTER
03094, SEPTEMBER 19BB-REVISED OCTOBER 1990

•

8-Bit Resolution

N PACKAGE
(TOP VIEW)

•

± 0.2% Linearity

•

Maximum Conversion Rate ... 30 MHz Typ
20 MHz Min

•

Analog Output Voltage Range ... VCC
to VCC -1 V

00 (lSB)
01
02
03
04
05
06
07 (MSB)
elK

GNO
OGTl Vee
eOMP

REF
ANlG Vee
AOUT

•

TTL Digital Input Voltage

•

5-V Single-Supply Operation

•

Low Power Consumption ... 250 mW Typ

•

Interchangeable with Fujitsu MB40778

ANlG Vee
OGTl Vee
GNO

description
The TL5602 is a low-power ultra-high-speed video digital-to-analog converter that uses the Advanced LowPower Schottky (ALS) process. It converts digital signals to analog signals at a sampling rate of dc to
20 MHz. Because of such high-speed capability, the TL5602 is suitable for digital video applications such
as digital television, video processing with, a computer, and radar signal processing.
The TL5602C is characterized for operation from O°C to 70°C.

functional block diagram

ClK
8

MASTER
SLAVE
REGISTER

8

8

CURRENT
SWITCH

BUFFER

8

RESISTOR
NETWORK

(6)

AOUT

00-07

(4)

COMP

REF

FUNCTION TABLE
STEP
0
1

07
l
l

06
l
l

05
l
l

l
H
H

H
l
l

H
l
l

DIGITAL INPUTS
02
04
03
l
l
l
l
l
l

128
129

H
l
l

OUTPUT
VOlTAGEt
3.980 V
3.984 V
I
I

H

H

H

H

l

l
l

l

l

l
l

4.488 V
4.492 V

H

4.496 V

l
H

4.996 V
5.000 V

I
I

I
I

I
I

254
255

DO
L
l

I
I

I
I

127

01
l
l

H

H

H

H

H

H

H

H

H

H

H

H

H

H

tFor Vee = 5 V, Vref = 3.976 V
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

~~~~~~~~i~ar::1~1e ~~~:i~~ti:; :IIO::~:~:t::s~S

not

Copyright © 1990, Texas Instruments Incorporated

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-13

TL5602
8·BIT DlGITAL·TO·ANALOG CONVERTER

schematics of equivalent input and output circuits
EQUIV ALENT OF EACH DIGITAL INPUT

EQUIVALENT OF ANALOG OUTPUT

DGTlVCC--__- - - -__~------~~--~._--

25 kll

3.5 kll

3.5
kll

- -__~----- ANlG VCC

25 kll

....- - - - AOUT

1.4 V

-

......- - - - G N D

GND----~--------_e~------~~--

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage range, ANLG Vee, DGTL Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . /. . . . . . . . . . . . .. - 0.5 V to 7 V
Analog reference voltage range, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V to Vee +0.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 °e to 150 °e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260 0 e

recommended operating conditions
Vee

Supply voltage

Vref

Analog reference voltage (see Note 1)

VIH

High-level input voltage

Vil

low-level input voltage

tw

Pulse duration, elK high or low

tsu

Setup time, data before ClK;

MAX

UNIT

5

5.25

V

3.8

4

4.2

V
V

0.8

ns

12.5

ns

12.5

ns

0

caMp and GND.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

25

1

Operating free-air temperature

NOTES: 1. VCC - Vref S 1.2 V
2. This capacitor should be connected between

4-14

NOM

2

Hold time, data after ClK;
th
Ccomo Phase compensation capacitance (see Note 2)
TA

MIN
4.75

I'F
70

°c

TL5602
8·BIT DlGlTAL·TO·ANALOG CONVERTER

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
Typt

MAX

II

Input current at maximum input voltage

Vee

~

5.25 V, VI

~

7 V

0

100

IIH

High-level input current

Vee

~

5.25 V, VI

~

2.7 V

0

20

~A

IlL

Low-level input current

Vee

~

5.25 V, VI

~

0.4 V

-40

-400

~A

PARAMETER

TEST CONDITIONS

MIN

Vref ~ 4 V

Iref Input reference current
VFS Full-scale analog output voltage
VZS Zero-scale analog output voltage

10

Vee ~ 5 V, Vref
10 ~ 0 (no load)
~

ro

Output resistance

TA

lee

Supply current

Vref

~

Vee- 15

3.976 V,

3.919

25°e

~

70

4.05 V

Vee Vee+ 15
3.980 4.042

UNIT
~A

~A

rnV
V

80

90

[J

50

75

rnA

t All typical values are at Vee ~ 5 V, Vref ~ 4 V, TA ~ 25°e

operating characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
EL
f max

TEST CONDITIONS

MIN

TYP

linearity error

20

Maximum conversion rate

30

MAX

UNIT

±0.2

%FSR
MHz

PARAMETER MEASUREMENT INFORMATION
~tsu

I
00-07

_ _ _ th~

I

----..*50%

I

*"5-0-%---

i

~tw---;~~I~--tw----H
I
CLK

AOUT

,-----~I

'----,,[
I
I
I
I

I
I

,,---

±1/2LSB

50%

I
I
I

~tpd~

FIGURE 1. VOLTAGE WAVEFORMS

"!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-15

TL5602
8·BIT DlGITAL·TO·ANALOG CONVERTER

TYPICAL CHARACTERISTICS
5.000
Vref - 3.976 V
4.996

>

..
I

·•

"
"
/1

4.496

J!! 4.492

"0

>

Sc. 4.488
S

I

0

I
0

>

/

3.988
3.984
3.980

"

V
,V

Ol

V
0
0
0
0

~

0
0

0
0

0

,,'

V
0
0
0
0
0

0

/

,,-/''"

V

0

~

~

~

0
0

0
0
0
0

~

0

0

~

0
0

~
~

0
0
0
0

0
0
0
0

~

2

0

0
0
0

~

~

~
~

~

127 128 129

254 255

Digital Input Code

FIGURE 2. IDEAL CONVERSION CHARACTERISTICS
5.00
VFS-4.996 -VCC = 5V
I- Vref = 3.976 V

-t- -t-.-.t - t -

-+-

>

.
I

Ol

J!!

4.492

sc.

4.488

-i-

-

7

EL254 A

:=

J/

'I !I

4.496 1---

"0

-

--

EL1L ' -

I El128

>

El1127

v. .

S

o
I
o
>

,

, ./'

1-/
I

-,

E~

3.988

~EL1

ViJ

3.984
VZS-3.980
0
0
0
0
0
0
0
0

0

~

0
0

0

0

0

0
0

.... '

I

I
0

.-

0
0
0
0
0
0

2

...

~
~
~
~

....
~

0

0
0
0
0
0

0

0

~

0
0
0
0
0
0

0

... ....

127 128 129

.-

~

~

~

~

254257

Digital Input Code

FIGURE 3. END-POINT LINEARITY ERROR

-1!1

TEXAS
INSTRUMENTS
4-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5502-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
JANUARYi991-REVISED OCTOBER 1991

•
•
•

LinEPIC'" 1-ftm CMOS Process

NPACKAGE

(TOP VIEW)

a-Bit Resolution
OGTL GN01
(LSB) DO
01
02
03
04
05
06
(MSB) 07
CLK
OGTLGN02

Differential Linearity Error . .. ±0.2% Max

•

Maximum Conversion Rate . .. 20 MHz Typ
.. . 10 MHz Min

•
•
•
•

Analog Input Voltage Range ... 0 V to Vee
TTL Digital I/O Level
Low Power Consumption ... 150 mW Typ
5-V Single-Supply Operation

ANLG GNO
OGTL Voo1
ANLG Voo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLGVoo
OGTL Voo2
ANLG GNO

description
OM/PACKAGE

The TLC5502-5 is a low-power ultra-high-speed
8-bit analog-to-digital converter that uses the
LinEPIC'" CMOS process. It utilizes the full
parallel comparison (flash method) for high-speed
conversion. Because of such high-speed
capability, the TLC5502-5 is suitable for hard disk
drive, motor control, multimedia, and high-speed
signal processing.

(TOP VIEW)

OGTLGN01
(LSB) DO
01
02
03
04
05
06
(MSB) 07
CLK
OGTLGN02
NC

Separate analog and digital supply pins are
provided to reduce coupling between the
high-speed digital switching sections and the
lower-frequency analog signal comparators. This
pin partitioning minimizes crosstalk and unwanted
spurious signals.
The TLC5502-5 is characterized for operation
from O°C to 70°C.

ANLG GNO
OGTL Voo1
ANLG Voo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLGVoo
OGTLVoo2
ANLG GNO
NC

NC-No internal connection

Ouring storage or handling, the device leads should be shorted together orthe device should be placed in conductive foam. In a circuit,
unused inputs should always be connected to an appropriated logic voltage level, preferably either V CC orground. Specific guidelines
for handling devices of this type are contained in the publication Guidelines for Handling Efectrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies available from Texas Instruments.
LinEPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily Include testing of all

parameters.

TEXAS

.JJ1

Copyright © 1991, Texas Instruments Incorporated

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-17

TLC5502-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
functional block diagram
ClK

------~----------~-----------,

ANlGINPUT
REFT -

EN
R1

07 (MSB)

R

06

R
05
latch
and
Buffer

255-to-8
Encoder

04

REFM

03
R/2
02
01

R

DO (lSB)
R

R2
REFB

operating sequence

elK

~Sample \I..___.J/ISample
N

ANALOG
INPUT

~

1

\1..---.JfsamPle

N+1

N+2

~

~

~
_ _ _ _ _ _ _ _~_-~------=--

--'X ~~~a

14

~I

td
----)(~~-a-ta----------------~

00-07 _ _ _ _

Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at
time tN and latches sample N-1 at the output. Sample N is encoded to eight digital lines on the next falling edge
of the clock and then the following high clock level latches these eight bits to the outputs (with a delay td) and
acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence for the next
cycle.

TEXAS .JJ1

INSTRUMENTS
4-18

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5502·5
8·BIT ANALOG· TO·DIGITAL CONVERTER
equivalents of analog input circuit
ANALOG INPUT

SAMPLE AND HOLD
ANlG
VDD

REFT
ANlG
INPUT
mRt
Vref'

*

S

H

-ANrl...--4

~
c

ANlGINPUT

SampleandHold
Circuit

REFT

'I

(256-m)R

ANlG
GND

REFB

-OUT1

---

OUT 2

C

(256-m)R
REFB

t m ~ comparator position along the resistor string.
t Vrcr'

= [VrcIT -

VrcfB]

[1 - ~] +
256

VrefB

equivalent of digital input circuit
DGTlVDD

ld
ClK -.J\f\/'v-....- - .

ANlG
GND

-=-

J-

J :-+1
,.n
~GND

TEXAS .J!I

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

4-19

TLC5502·5
a·BIT ANALOG· TO·DIGITAL CONVERTER
FUNCTION TABLE

ANALOG INPUT

STEP

DIGITAL OUTPUT
CODE

VOLTAGEt

0

0.000 V

L

L

L

L

L

L

L

L

1

0.019V

L

L

L

L

L

L

L

H

127

2.413 V

L

H

H H H

H

H H

128

2.432 V

H

l

l

l

L

L

L

L

129

2.451 V

H

L

L

L

L

L

L

H

254

4.826 V

H

H

H H H

H

H

L

255

4.845 V

H

H

H H H

H

H H

t These values are based on the assumptJon that V refB and V refT
have been adjusted so that the voltage at the transition from digital

o to 1 (VZT) is 0 V and the transition to full scale (VFT) is 4.8545 V.
1 lSB = 19 mY.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANlG VDD (see Note 1) ........................................ -0.5 V to 7 V
Supply voltage range, DGTl VDD (see Note 1) ........................................ -0.5 V t07 V
Input voltage range at elK, VI ........................................ -0.3 V to DGTl VDD + 0.3 V
Input voltage range at analog input, VI .................................. -0.5 V to ANLG VDD + 0.5 V
Analog reference voltage range, Vref ................................... -0.5 V to ANLG VDD + 0.5 V
Operating free-air temperature range, T A .............................................. DoC to 70°C
Storage temperature range ....................................................... -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: Voltages at analog inputs and ANLG VDD are with respect to the ANlG GND terminals. Voltages at the digital outputs and DGTl VOD
are with respect to the DGTL GND terminals.

recommended operating conditions
MIN

NOM

MAX

Supply voltage, ANLG VDD

4.75

5

5.25

V

Supply voltage, DGTL VDD

4.75

5

5.25

V

0.8

V

5

V

2

High-level input voltage, VIH, CLK

V

Low-level input voltage VIL, CLK
Input voltage at analog input. VI

0
ANLG

Analog reference voltage (top side), VrefT

V rcfT - V refB
2

Analog reference voltage (bottom side), VrefB

0

Differential reference voltage, VrefT - VrefB

5

High-level output current, IOH
low-level output current, IOL
Clock pulse duration, high or low, twH or twL

V
V
V

-400

!!A

4

mA

70

'C

50

Operating tree-air temperature, T A

0

TEXAS

~

INSlRUMENTS
4-20

V

VDD

Analog reference voltage (midpoint), VrefM

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

ns

TLC5502·5
a·BIT ANALOG·TO·DIGITAL CONVERTER
electrical characteristics over operating supply voltage range, TA = 25°C
PARAMETER

TEST CONDITIONS

High-level output voltage

IOH = -400

VOL

Low-level output voltage

IOL=4 mA

II

Analog input current

VI = Oto 5 V,

IIH

Oigitial high-level input current

VI =5V

IlL

Digital low-level input current

VI = 0

IrefB

Reference current

VrefB = 0
VrefT = 5 V

IrefT

Reference current

Ci

Analog input capacitance

IDO

Supply current

MIN

f1A

VOH

TYP

MAX

2.4

V
0.4
±0.5

fclock = 10 MHz

UNIT

V
mA

1

f1A

-1
-10

-20

J.lA
mA

10

20

mA

30

60

mA

MIN

TYP

MAX

UNIT

10

20
±0.2

%FSR

±0.4

%FSR

50
fclock = 10 MHz

pF

operating characteristics over operating supply voltage range, T A = 25°C
PARAMETER

TEST CONDITIONS

Maximum conversion rate

fc(max)
ED

Linearity error, differential

EL
SNRT

Linearity error, best straight line

VI = 0 to 5 V

Signal to noise ratio

THO

Total harmonic distortion

fclock = 9.9 MHz, fiN = 97 kHz,
BW = 5 MHz

BW

Analog input bandwidth (3 dB)

fclock = 10 MHz

td

Digital output delay time

CL= 15 pF

±0.1

VI = 0 to 5 V

MHz

-50

dB
dB

51

MHz

5

10

30

ns

t SNR is total noise without THO.
timing diagram

CLK~

!.---

Sample
N

\

1

twH

' - - - - - - ' I Sample

--*-

'\

twL

-.!

1

'--_ _ _..J

N+1

Sample
N+2

~v

~
I~
~
Input~
_______________~~----~-----------~----

Analog

~td=j

DO.D7 ________..J)x(~~-~-~-a-----------------

----

~~_~_at_a________________~~

TEXAS ~

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-21

TLC5502-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
11111111
11111110

Se~ Note A

l,t

"

"C

0

;;

.s-

••
•
10000001

::I

10000000

:g,

01111111

0
iii

C

Vz:r
VZS+1/2 LSB .

v: A::
/

l-t ~

VFT=VFS
-1/2 LSB

V

••
I
V '
l/
•
v(
00000010 VZ~/
IL [& V
00000001
00000000

254

lI/j ~r 253
lI/jVI vrs •
,IjV II II ••

11111101

()

255

~

V

III
Ol Ol
0
0

0

c:i c:i

CIO

C')

•••

C')

0

c:i

:;;:

N

...N'"
C')

I

129
a.

-j 128 3l
127
I •
•
I 2•

I
I

... ..

co

~

'"CIO

N

VI - Analog Input Voltage - V
NOTE A: This curve is based on the assumption that VrefB and VrefT have been adjusled so Ihat the voltage at the trans ilion from digital a to 1
(Vz:r) is a and the transition to full scale (VFT) is 4.8545 V. 1 LSB = 19 mY.

Figure 1. Ideal Conversion Characteristics
SUPPLY CURRENT

REFERENCE CURRENT

vs

vs

OPERATING FREE-AIR TEMPERATURE

OPERATING FREE-AIR TEMPERATURE

40r--~1~1---r--~--~-'--~

14

Voo =5V

VOO =5V
35 I- fclock = 8 MHz _+---1--+---+----1

«

~ 30~=i===t===t==~==1===1==1
;:
~
::I

I

~

25r_-+--~-_+--r_-+--~-_1

Q)

0

"~

is.

a.
::I

en

15r_-+--~-_+~-r_-+--~-_1

'a:*

I

o
o

10

()

20~-+_-~-_+--~-+_-~-_1

-- -- -- -r---

E

;:
~
::I

I

V re fT=5V
VrefB=O

12 -

I

8

'-

r--

6

0
0

10~-4_-_+-_4--~-4_-_+~__I

4

5~-+_-~-_+--~-+_-~-_1

2

o

10

20

30

40

50

60

o

70

10

30

Figure 3

Figure 2

TEXAS

-'!1

INSTRUMENlS
4-22

20

40

50

60

T A - Operating Free-Air Temperature - 'C

TA - Operating Free-Air Temperature - 'C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

70

TLC5502·5
8·BIT ANALOG·TO·DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
OPERATING FREE·AIR TEMPERATURE

o

I

I

TOTAL HARMONIC DISTORTION
vs
OPERATING FREE·AIR TEMPERATURE

o

I

VOO = 5V
!g -10 f-- fiN = 100 kHz
I
fclock = 10 MHz
~ -20

OJ

*

o'"o
'g

"o

1:

*

-30

J:

'g

-40

'"

-50

J:

iii

;§

-60

-401----t----t-----t----j----t----t----j

I

~

o

J:

I-

-30 I----t----t-----t----j----t----t----j

E

"iii
I

-20~--+---~---+----~--+---~---4

oo

E
<;;

;§

-10

1J
I

"

VO~

=5V I
fIN = 1.25 MHz
fclock = 10 MHz

I-

-70
-80

-50

....+--+....,=F==:j::==+==1

b=~

-60~--~--~--~----~--~--~--~

o

10

20

30

40

50

60

o

70

TA - Operating Free-Air Temperature _ "C

10

20

Figure 4

0.35

~

0.3

g

;:-

0.25

.;:

"

I
0
W

0.25

QI

"

0.2

C

0.15

~
is

0.1

::;

0.2

~

e

0.1.5

QI

::::
i5

0.3

w

iii

e

0.35

OJ

QI

:g

70

"I

Ui

:c>'"
::;
"

60

0.4

1J
I
~

50

DIFFERENTIAL LINEARITY ERROR
vs
OPERATING FREE·AIR TEMPERATURE

0.4

e

40

Figure 5

DIFFERENTIAL LINEARITY ERROR
vs
SUPPLY VOLTAGE

OJ

30

TA - Operating Free-Air Temperature - "C

0.1

I

0

w

0.05 I- TA = 25"C
VI = Ot05/
0
4.75

o
4.875

5.0

5.125

51

0.05 f-- VOO = 5 V
VI =1 Oto

5.25

VOO - Supply Voltage - V

o

10

20

30

40

50

60

70

TA - Operating Free-Air Temperature - 'C

Figure 7

Figure 6

TEXAS

.JJ1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-23

TLC5502-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION

TOTAL HARMONIC DISTORTION

vs

vs

SUPPLY VOLTAGE

SUPPLY VOLTAGE
Or-----~------~-----,------~

or------r------~----~------,

~
I

J

TA=25
-10 _ fiN = 100 kHz
fclock = 10 MHz
o

~
I

c:

c:

o

o

:e
~

:e
~

-20

5

'"g

-301----+----+---+-----1

-301----+----!-----+--------1

10

J:

J:

~O~--_+---_+---+_--~

t=

$

~O~--_+---_+---_+_--_____l

t=

I

~

'g"
E

10

o

-20

5

E

$

TA = 25 1C
-10 f- fiN = 97 kHz
fclock = 9.9 MHz

I

-50~~~~=======f--~~t-----_J

~

-60~----~------~------~----~

4.75

4.875

5.0

5.125

-50 F:::===I=""".--t---=~=::;;:::::l
~O~----~------~------~----~

5.25

4.75

Voo - Supply Voltage - V

5.0

4.875

Figure 9

Figure 8

PARAMETER MEASUREMENT INFORMATION
Measurement
Point
5V

To
Digital
Output

(05)

RL=2 kQ

Figure 10. Load Circuit

TEXAS -1!1

INSTRUMENTS
4-24

5.125

Voo - Supply Voltage - V

POST OFFICE BOX 555303 • DALLAS. TEXAS 75265

5.25

TLC5502·5
8·BIT ANALOG· TO·DIGITAL CONVERTER
APPLICATIONS INFORMATION
The following design recommendations will benefit the TLC5502-5 user:
1.

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

2.

RF breadboarding or PCB techniques should be used throughout the evaluation and production process.
Breadboards should be copper clad for bench evaluation.

3.

Since the ANLG GNO, OGTL GN01, and OGTL GN02 are not connected internally, these pins need to be
connected externally. With breadboards, these ground lines should be connected through separate leads
with proper supply bypassing. A good method to use is a separate twisted-pair cables for the supply lines
to minimize noise pickup. An analog and digital ground plane should be used on PCB layouts.

4.

Since the ANLG Voo, OGTL Voo1, and OGTL V002 are not connected internally, these pins also need to
be connected externally. To connect ANLG Voo, DGTL Voo 1, and DGTL Voo2, a 50-Q resistor should be
placed in series with the OGTL Voo 1 pin and then a 0.1-[.lF capacitor to ground before being connected to
the ANLG Voo and OGTL V002.

5.

ANLG Voo to ANLG GNO, OGTL Voo 1 to OGTL GN01, and OGTL Voo2 to DGTL GND2 should be
decoupled with 1-~tF and O.01-[.lF capacitors, respectively, as close as possible to the appropriate device
pins. A ceramic chip capacitor is recommended for the O.01-[.lF capacitor. Care should be exercised to
assure a solid noise free ground connection for the analog and digital grounds.

6.

The no connection (NC) pins on the small-outline package should be connected to ground.

'7.

ANLG VOO, ANLG GNO, and the ANLG INPUT pins should be shielded from the higher-frequency pins, CLK
and 00-07. If possible, ANLG GND traces should be placed on both sides of the ANLG INPUT traces on
the PCB.

8.

In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Q or less within the analog frequency range of interest.

TEXAS

-1!1

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4--25

4-26

TLC5503·2
8·BIT ANALOG·TO·DIGITAL CONVERTER
D3739, FEBRUARY 1991-REVISED NOVEMBER 1991

•
•
•
•
•
•
•
•

N PACKAGE

LinEPIC'" 1-flm CMOS Process

(TOP VIEW)

a-Bit Resolution
OGTLGN01
(LSB) 00
01
02
03
04
05
06
(MSB) 07
CLK
OGTLGN02

Differential Linearity Error ... ±0.4% Max
Maximum Conversion Rate ... 25 MHz Typ
... 20 MHz Min
Analog Input Voltage Range ... 3 V to Voo
TTL Digital I/O Level
Low Power Consumption, .. 190 mW Typ
5-V Single-Supply Operation

ANLG GNO
OGTL Voo1
ANLGV oo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLGVoo
OGTL Voo2
ANLG GNO

description
ow PACKAGE

The TLC5503-2 is a low-power ultra-high-speed
video-band 8-bit analog-to-digital converter
manufactured using the LinEPIC'" CMOS
process. It uses full-parallel comparison (flash
method) for high-speed conversion of a wide-band
analog signal (such as a video signal) to a digital
signal at a sampling rate of dc to 25 MHz. Its
high-speed capability makes the TLC5503-2
suitable for digital video applications such as
digital TV, video processing with a computer, or
radar signal processing,

(TOP VIEW)

OGTL GN01
(LSB) 00
01
02
03
04
05
06
(MSB) 07
CLK
OGTLGN02
NC

ANLG GNO
OGTL Voo1
ANLGVoo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLG Voo
DGTL Voo2
ANLG GND
NC

Separate analog and digital supply pins are
provided to reduce coupling between the highspeed digital switching sections and the lowerfrequency analog signal comparators. This pin
NC-No internal connection
partitioning minimizes crosstalk and spurious
signals. The two analog inputs (pins 17 and 18 on
the N package; pins 19 and 20 on the OW
package) should be connected together externally. The REFM input (pin 16 on the N package; pin 18 on the OW
package) can be used to adjust for small tolerances in the resistor voltage divider by applying an external
midpoint voltage.
The TLC5503-2 is characterized for operation from O°C to 70°C,

During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit,
unused inputs should always be connected to an appropriated logic voltage level, preferablyeitherVcC or ground. Specific guidelines
for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies available from Texas Instruments.
LinEPIC is a registered trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Produtts
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does nol necessarily include testing of all
parameters.

TEXAS

-III

Copyright © 1991, Texas Instruments Incorporated

INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-27

TlC5503·2
a·BIT ANAlOG-TO-DIGITAl CONVERTER
functional block diagram
CLK

ANLGINPUT
REFT -

EN

R1
07 (MSB)

R2

06
05

R127
Latch
and
Buffer

255-10-8
Encoder

Iill.B
2

04

REFM

03

Iill.B
2

02

R254

01
DO (LSB)

R255

R256
REFB

operating sequence

CLK

Analog

tN

Encode
Sample N

I
I

I
I

-1'

Ir
I

Sample
N

~ td ~

)(
----'I

Encode
Sample (N+2)

I
I
I _ _ _-,. I

I~
I

II/"

't-

}'--_-J{-

Sample
N+1

I

~~~a

tN+2

I
I
I _ _ _-,. I

~'----{-

Input~

00-07

Encode
Sample (N+1)

tN+1

~ td j

X~ata

I

Sample
N 2
+

~ td~

~
I

Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at
time tN and latches sample N-1 at the output (with a delay td). Sample N is encoded to eight digital lines on the
next falling edge of the clock and then the following high clock level latches these eight bits to the outputs (with
a delay td) and acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence
for the next cycle.

TEXAS

~

INSlRUMENTS
4-28

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5503·2

8·BIT ANALOG·TO·DIGITAL CONVERTER
equivalents of analog input circuit
SAMPLE AND HOLD

ANALOG INPUT
ANLG
VOO

REFT
ANLG
INPUT

mRt
Vref' ;

S

SampleandHold
Circuit

H

~

ANLGINPUT

REFT

(256-m)R
ANLG
GND

REFB

I

C

I

C

-OUT1
--OUT2

(256-m)R
REFB

t m = comparator position along the resistor string.

t Vrer' = [VrcIT - VrcfB]

[1 -~] +

VrcfB

256

equivalent of digital input circuit
DGTL VOO

ld
eLK --'\/\/'v-.....-~

.....
ANLG
GNO '7

J-

~ ~OGn

TEXAS

7GNO

l!1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-29

TLC5503-2
8.BIT ANALOG-TO-DIGITAL CONVERTER
FUNCTION TABLE

t

STEP

analog Input
VOLTAGEt

DIGITAL OUTPUT
CODE

0

2.960 V

L

L

L

L

L

L

L

1

2.968 V

L

L

L

L

L

L

L H

127

;>.976 V

L

H

H H H

H

H H

128

3.984 V

H

L

L

L

L

L

L

L

129

3.992 V

H

L

L

L

L

L

L

H

254

4.992 V

H

H

H H H

H

H

L

255

5.000 V

H

H

H H H

H

H H

L

These values are based on the assumptJon that V refS and V refT
have been adjusted so that the voltage at the transition from digital
to 1 (VZT) is 2.964 V and the transition to full scale (VFT) is
4.996 V . 1 LSB = 8 mV

o

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANlG VDD (see Note 1) ........................................ ~0.5 V to 7 V
Supply voltage range, DGTl VDD (see Note 1) ........................................ -0.5 V to 7 V
Input voltage range at elK, VI ......................................... -0.3 V to DGTl VDD + 0,3 V
Input voltage range at analog input, VI .................................. -0.5 V to ANlG VDD + 0.5 V
Analog reference voltage range, Vref ................................... -0.5 V to ANlG VDD + 0.5 V
Operating free-air temperature range, TA .............................................. DoC to 70°C
Storage temperature range ....................................................... -55°C to 150°C
lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: Voltages at analog inputs and ANLG VDD are with respect to the ANLG GND terminals. Voltages at the digital outputs and DGTL VDD
are with respect to the DGTL GND terminals.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, ANLG VDD

4.75

5

5.25

V

Supply voltage, DGTL VDD

4.75

5

5.25

V

2

High-level input voltage, VIH, CLK

V

Low-level input voltage, VIL, CLK

3

Input voltage at analog input, VI

V

5

V

ANLG

Analog reference voltage (top side), VrefT

V

VDD
VreIT - VrefB
2

Analog reference voltage (midpoint), V refM

2.5

Analog reference voltage (bottom side), VrefS
Differential reference voltage, VrefT - VrefB

V
V

3
2

V

4

~
mA

70

'C

-400

High-level output current, IOH
Low-level output current, IOL

25

Clock pulse duration, high-level or low-level, twH or twL

0

Operating free-air temperature, TA

TEXAS

-IJ1

INSTRUMENTS
4-30

0.8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ns

TLC5503-2
8-BIT ANALOG-TO-DIGITAL CONVERTER
electrical characteristics over operating supply voltage range, TA = 25°C
PARAMETER

TEST CONDITIONS

High-level output voltage

IOH = -400

VOL

low-level output voltage

IOl = 4 mA

II

Analog input current

VI =:3 to 5 V,

IIH

Digitial high-level input current

VI = 5V

III

Digital low-level input current

VI = 0

IreIB

Reference current

V re fB=3V
V reIT=5V

IreIT

Reference current

Ci

Analog input capacitance

IDD

Supply current

MIN

f'A

VOH

TYP

MAX

004
",0.3

fclock = 15 MHz

UNIT
V

204

V
mA

1

flA

-1
-12

-20

"A
mA

12

20

mA

37

60

mA

MIN

TYP

MAX

20

25

pF

50
fclock = 15 MHz

operating characteristics over operating supply voltage range, TA = 25°C
PARAMETER
f max

TEST CONDITIONS

Maximum conversion rate

UNIT
MHz+

ED

Linearity error, differential

VI = 3 Vto 5 V,

fclock = 15 MHz

",004

%FSR

El

Linearity error, best straight line

VI = 3Vt05V,

fclock = 15 MHz

",004

%FSR

Gdiff

Differential gain

diff
SNRt

Differential phase
Signal to noise ratio

fclock = 1604 MHz,

THD

Total harmonic distortion

BW = 8.2 MHz

td

Digital output dalay time

Cl = 15 pF

0.9%

NTSC 40-IRE modulated ramp, fclock = 1404 MHz

0.6 0

fiN = 1.248 MHz (90% P-P),

48

dB
dB

-50
10

30

ns

t SNR does not Include THO.
:j: No missing codes.

timing diagram

i+-

ClK

J

'r

\ . . . --'f

1

twL ----[

'\'------'t~---"'~ v

1

Sample
N

Analog
1
Input ~
1

1
00-07

~

twH

____..IX ~~~a

1

1

1

~ Sample
N+1

1.--1

I'"

.1

td

1

¥~

1

1
1

Sample
N +2

______

1

Xl.._~_at_a_ _ _ _ _ _ _ _......~

TEXAS

.JJ1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-31

TLC5503·2
a·BIT ANALOG·TO·DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
11111111

.,

11111101

0

,~ V

u
'5Co 10000001
'5 10000000

~V

0

VIT =
VZS+1/2 LSB

iii

~ 01111111
C

vt:V

II

253

I
••
l/
•
00000010 VZ~/ vi'
IL ~ V
00000001
g

~

V

~ -

30

TA - Operating Free-Air Temperature - 'C

T A - Operating Free-Air Temperature - 'C

~

0.15

Cf

0.1

~

0.1

Cl

Cl

w

w 0.05 1-_ TA = 25'C
VI = 0 to 5 V
0
4.75

I
4.875

0.05 -

Vee=5V
VI = Oto 5 V

o
5

5.125

o

5.25

I

I

10

20

30

40

50

60

70

TA - Operating Free-Air Temperature - 5C

Vee - Supply Voltage - V

Figure 6

Figure 7

TEXAS

-1!1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-33

TLC5503·2
8·BIT ANALOG·TO·DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION

TOTAL HARMONIC DISTORTION

vs

vs

SUPPLY VOLTAGE

SUPPLY VOLTAGE
or-----~-------r------~-----,

Or-----~-------r------,------,

m
"0

I

25°~

-10

TA = 25'C

TA=
fiN 100 kHz
fclock = 10 MHz

=

m

"0

I

c

c
o

o

t:o

Vi

t:o

-20~-----+------~------4-----~

Vi

Ci
o

'15

o

'15

f__----_+------_+_------+-----~

-30 f__----_+------_+_------+_----~

E
.,

:r:

ro
;§

~0~----_+------~------4-----~

I

o
~

-20

Ci
-30 ~----_+------~------4-----~

E

m
:r:
ro
;§

I

fiN = 97 kHz
fclock = 9.9 MHz

-10

~Of__----_+------_+_------+_----~

I

-50~====~~~~~---=--1-----~

~ -50F=~===r~~--_r------~~~~

~0L-----~------~------~----~

-60L-----~------~------~----~

4.75

4.875

5.0

5.125

5.25

4.75

Voo - Supply Voltage - V

5.0

4.875

Figure 8

Figure 9

PARAMETER MEASUREMENT INFORMATION
Measurement
Point
5V

To (05)

RL = 2 kQ

Oigital <4-'----'-1t
Output

'--14-'

Figure 10. Load Circuit

TEXAS

~

INSTRUMENTS
4-34

5.125

Voo - Supply Voltage - V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5.25

TLC5503·2
8·BIT ANALOG·TO·DIGITAL CONVERTER
APPLICATION INFORMATION
The following design recommendations will benefit the TLC5503-2 user:
1.

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

2.

RF breadboarding or PCB techniques should be used throughout the evaluation and production process.
Breadboards should be copper clad for bench evaluation.

3.

Since the ANLG GND, DGTL GND1 , and DGTL GND2 are not connected internally, these pins need to be
connected externally. With breadboards. these ground lines should be connected through separate leads
with proper supply bypassing. A good method to use is separate twisted-pair cables for the supply lines to
minimize noise pickup. An analog and digital ground plane should be used on PCB layouts.

4.

Since the ANLG VDD, DGTL VDD1, and DGTL VD02, are not connected internally, these pins also need
to be connected externally. To connection ANLG VOD to DGTL VDD 1 or DGTL VDD2, a 50-Q resistor should
be placed in series with the DGTL VDD 1 pin and then a 0.1-fAF capacitor to ground before being connected
to the ANLG VDD, and DGTL DV DD2 supply.

5.

ANLG VDD to ANLG GND, DGTL VDD1 to DGTL GND1, and DGTL VOD2 to DGTL GND2 should be
decoupled with 1-fAF and 0.01-fAF capacitors, respectively, as close as possible to the appropriate device
pins. A ceramic chip capacitor is recommended for the O.01-fAF capacitor. Care should be exercised to
assure a solid noise-free ground connection for the analog and digital grounds.

6.

The no connection (NC) pins on the small-outline package should be connected to ground.

7.

ANLG VDD, ANLG GND, and the ANLG INPUT pins should be shielded from the higher-frequency pins, CLK
and DO-D7. If possible, ANLG GND traces should be placed on both sides of the ANLG INPUT traces on
the PCB.

8.

In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Q or less within the analog frequency range of interest.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-35

TLC5503-2
8-BIT ANALOG-TO-DIGITAL CONVERTER
APPLICATION INFORMATION
REFB
ANLG

12 V
AVOO

50

~F

0.1

1Vv-----i OGTL VOOl

r1

(LSB) DO

r---+

AVOO

011---.

ANLG VOO

OVOO

0.1

OGTLGNOl

Q

'---+----+---1 REFB

021---.
031---.

~F

TLCSS03-2

041---.

REFM
, - - - - - + - - - - + - - j REFT

0.1

~

061---.

~F

ANLGVOO
'-----+---lOGTLV002

0.1

(MSB) 07 1 - - - .
CLKI---.

~F

ANLG GNO

REFT
NOTES: A. All resistors are 1/4 W carbon.
B. Ql is 2N3414 or equivalent.
C. All capacitors are ceramic with as short leads as possible.

TEXAS -'II

INSfRUMENlS
4-36

051---.

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

OGTL GN02

TLC5503-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
03637, OCTOBER I 990-REVISED OCTOBER 1991

•
•
•
•

LinEPIC'" 1-[!m CMOS Process

N PACKAGE
(TOP VIEW)

a-Bit Resolution
Differential Linearity Error ... ±0.4% Max
Maximum Conversion Rate ... 20 MHz Typ
... 10 MHz Min

•
•

Analog Input Voltage Range ... 0 V to Voo

OGTLGN01
(LSB) 00
01
02
03

04

TTL Digital I/O Level

•
•

ANLG GNO
OGTL Voo1
ANLG Voo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLG Voo
OGTL VDD2
ANLG GNO

05

06

Low Power Consumption ... 150 mW Typ

(MSB) 07
CLK
OGTLGN02

5-V Single-Supply Operation

description
The TLC5503-5 is a low-power ultra-high-speed
8-bit analog-to-digital converter that uses the
LinEPIC'" CMOS process. It utilizes the full
parallel comparison (flash method) for high-speed
conversion, Because of such high-speed
capability, the TLC5503-5 is suitable for hard disk
drive, motor control, multimedia, and high-speed
signal processing,
Separate analog and digital supply pins are
provided to reduce coupling between the
high-speed digital switching sections and the
lower-frequency analog signal comparators, This
pin partitioning minimizes crosstalk and unwanted
spurious signals.
The TLC5503-5 is characterized for operation
from O°C to 70°C.

ow PACKAGE
(TOP VIEW)

OGTL GN01
(LSB) 00
01
02
03

04
05

06
(MSB) 07
CLK
OGTLGN02
NC

ANLG GNO
OGTL Voo1
ANLG Voo
REFB
ANLGINPUT
ANLGINPUT
REFM
REFT
ANLGVoo
OGTL Voo2
ANLG GNO
NC

NC- No internal connection

Ouring storage or handling, the device leads should be shorted together orthe device should be placed in conductive foam. In a circuit.
unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines
for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies available from Texas Instruments.
LinEPIC is a registered trademark of Texas Instruments Incorporated.
PRODUCTION DATA Information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does nol necessarily include testing of all

parameters.

.J!I
INSlRUMENTS

Copyrighl © 1991, Texas Instruments Incorporated

TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-37

TLC5503-5
8-BIT ANALOG-TO-DIGITAL CONVERTER
functional block diagram
ClK

ANlGINPUT
EN

07 (MSB)

06

latch

255-to-8

and
Buffer

Encoder

05

04
03

02
01
DO (lSB)

R2

REFB

operating sequence

ClK

J

Sample

\

N
Analog

~

--JI

'--_ _

1

\'-----'/samPle
-

Sample

N+1

N+2

1 ~
~
_ _ _ _~~
_ _ _ _~_

Input~

--JX ~:~a

I..

00--07 _ _ _

.1

td

-----

)(~-~a-t-a---------~

Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at
time tN and latches sample N -1 at the output. Sample N is encoded to eight digital lines on the next falling edge
of the clock and then the following high clock level latches these eight bits to the outputs (with a delay td) and
acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence for the next
cycle,

TEXAS

.J!1

INSTRUMENTS
4-38

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5503·5
8·BIT ANALOG·TO·DIGITAL CONVERTER
equivalents of analog input circuit
ANALOG INPUT

SAMPLE AND HOLD
ANLG
VDD

REFT

S

ANLG
INPUT
mRt
Vref'

~

SampleandHold
Circuit

H

c

ANLGINPUT

REFT -V0rl>--'1

~
I

(256-m)R
ANLG
GND

REFS

t

-OUT1

- - - OUT 2

C

(256-m)R
REFS

m = comparator position along the resistor string.

t Vrer' = [VrcfT - VrcfB]

[1 - ~]
256

+ VrcfB

equivalent of digital input circuit

CLK

-~~~---

ANLG
GND 7

TEXAS

.J!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4--39

TLC5503-5
8-BIT ANALOG-TO-DiGITAL CONVERTER
FUNCTION TABLE

ANALOG INPUT

STEP

DIGITAL OUTPUT

VOLTAGEt

CODE

0

0.000 V

l

l

l

l

l

l

L

L

1

0.019 V

l

l

l

l

l

l

l

H

127

2.413 V

l

H

H H H

H

H H

128

2.432 V

H

l

l

l

l

l

l

l

129

2.451 V

H

l

l

l

l

l

l

H

254

4.826 V

H

H

H H H

H

H l

255

4.845 V

H

H

H H H

H

H H

t These values are based on the assumpllOn that V refB and V refT
have been adjusted so that the voltage at the transition from digital

a to 1 (VZT) is a V and the transition to full scale (VFT) is 4.8545 V.
1 lSB = 19mV.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANLG Voo (see Note 1) ........................................ -0.5 V to 7 V
Supply voltage range, DGTL Voo (see Note 1) ........................................ -0.5 V to 7 V
Input voltage range at eLK, VI ......................................... -0.3 V to DGTL Voo +0.3 V
Input voltage range at analog input, VI .................................. -0.5 V to ANLG VOD + 0.5 V
Analog reference voltage range, Vref ................................... -0.5 V to ANLG Voo + 0.5 V
Operating free-air temperature range, TA ............................................... ooe to 70°C
Storage temperature range ....................................................... -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: Voltages at analog inputs and ANlG VDD are with respect to the ANlG GND terminals. Voltages at the digital outputs and DGTl VDD
are with respect to the DGTl GND terminals.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, ANlG VOD

4.75

5

5.25

V

Supply voltage, DGTl VDD

4 ..75

5

5.25

V

High-level input voltage, VIH, ClK

2

V

low-level input voltage, Vll, ClK

0.8

a

Input voltage at analog input, VI

5
ANlG
VDD

Analog reference voltage (top side), VrefT

Analog reference voltage (bottom side), VrefB

a

Differential reference voltage, vrefT - VrefB

5

High-level output current, IOH
low-level output current, IOl
Clock pulse duration, high or low, twH or twl

a

TEXAS ~

INSlRUMENTS
4-40

V
V
V

-400

f'A

4

rnA

70

·c

50

Operating free-air temperature, TA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V
V

vrcfT - V refB
2

Analog reference voltage (midpoint), VrefM

V

ns

TLC5503-5
8-BIT ANALOG-TO-DIGITAL CONVERTER

electrical characteristics over operating supply voltage range, TA = 25°C
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH = -400 ~A

VOL

Low-level output voltage

IOL= 4 mA

II

Analog input current

VI = Oto 5 V,

IIH

Digital high-level input current

VI =5V

IlL

Digital low-level input current

VI = 0

IrefB

Reference current

VrefB = 0
V re fT=5V

IrefT

Reference current

Ci

Analog input capacitance

IDD

Supply current

MIN

TYP

MAX
0.4

,,0.5

fclock = 10 MHz

V
mA

1

f!A

-1

f!A

-10

-20

mA

10

20

mA

30

60

mA

MIN

TYP

MAX

UNIT

10

20
,,0.4

%FSR

,,0.4

%FSR

50
fclock = 10 MHz

pF

=25°C

operating characteristics over operating supply voltage range, T A
PARAMETER

UNIT
V

2.4

TEST CONDITIONS

fc(max)

Maximum conversion rate

ED

Linearity error, differential

VI = 0 to 5 V

EL
SNRT

Linearity error, best straight line

VI = 0 to 5 V

Signal to noise ratio

THO

Total harmonic distortion

fclock = 9.9 MHz, fiN = 97 kHz,
BW=5MHz

BW

Analog input bandwidth (3 dB)

fclock = 10 MHz

td

Digital output delay time

CL = 15 pF

,,0.1

MHz

-50

dB
dB

51

MHz

5
10

30

ns

t SNR IS total nOise Without THD.

timing diagram

elK

-i

'r
-<--

Sample
N

I
I

I

---l
'\I....__

\ . . __-J{

I

Analog
Input

-+-

: . . - twH

.IX ~~~a

00-07 _ _ _ _

twl

I

I

I~
I

1"1

I

Sample
N +1

I

I

-I*,...--.. .~v
I

____

.1

td

X....:.~_at_a

TEXAS

I
I

.r~ Sample
N +2
_____

I

_________~

lJ1

INSlRUMENlS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

4-41

TLC5503·5
a·BIT ANALOG·TO·DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
11111111
11111110

..

~

Se~ NoieA

••

'tI

•

0

"v: II

:; 10000001
Q.
:; 10000000

l,.t V

0

~

C>

01111111

i5

••
•

00000010
00000001
00000000

254

lAj ~'41 253
lAjVI vrs •
••
I
V

11111101

()

255

Vzr
VZS+l/2LSB
V

I

VZ~! k{
IL lJ:; V
~V

,v:V~

17

CD

~

0

I

I

II

,/

I
N

~

N

N

••• '"~ '"":
N

129
Q.

128 ~
127

I •
••

,

...

It)

'" '"

0_
0 "!
d 0

VFT=VFS
-1/2 LSB

2

'"
N

CD

.,;

VI - Analog Input Voltage - V
NOTE A: This curve is based on the assumption that VrefB and VreIT have been adjusted so that the voltage at the transition from digital 0 to 1
(VZT) is 0 and the transition to full scale (VFT) is 4,8545 V. 1 LSB = 19 mY,

Figure 1. Ideal Conversion Characteristics
SUPPLY CURRENT

REFERENCE CURRENT

vs

vs

OPERATING FREE·AIR TEMPERATURE

OPERATING FREE·AIR TEMPERATURE

40r---,----,---,----r---,----,---,

14

I

35

r--

VOO =15V
fclock = 8 MHz

 REGISTER

1---,'---11 x 4
07-00

~-T:--~'

63

DECODE

~+---I

A OUT

......--.'----i 1x 1
3

During storage or handling, the device leads should be shorted together orthe device should be placed in conductive foam. In a circuit,
unused Inputs should alw~ys be connected to an appropriated logic voltage level, preferably either Vee or ground, Specific guidelines
for handling devices of thiS type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
DevIces and Assemblies available from Texas Instruments,
LinEPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA documents contain information

current as of publication date. Products. conform to
specifications per the terms of Tens Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 1990, Texas Instruments Incorporated

TEXAS

-I!}

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-47

TLC5602. TLC5602A
LinEPICTM 8-BIT DlGlTAL-TO-ANALOG CONVERTERS
FUNCTION TABLE
STEP

DIGITAL INPUTS
07

06

05

04

03

02

01

DO

OUTPUT
VOLTAGEt

0

L

L

L

L

L

L

L

L

3.980 V

1

L

L

L

L

L

L

L

H

3.984 V

I
I

I
I

I
I

127

L

H

H

H

H

H

H

H

4.488 V

128

H

L

L

L

L

L

L

L

4.492 V

129

H

L

L

L

L

L

L

H

4.496 V

I
I

I
I

I
I

254

H

H

H

H

H

H

H

L

4.996 V

255

H

H

H

H

H

H

H

H

5.000 V

tFor VOO = 5 V, Vref = 4.050 V.

schematic of digital input and analog output
EQUIVALENT OF EACH DIGITAL INPUT
OGTl
VOO

EQUIVALENT OF ANALOG OUTPUT

OGTl

~;~r

}---ANLGt
GNO

~

_..,._ _ _ _ ANLG
V001

....----,AOUT

ANLGt
- - - ' - - - - - - GNO

OGTlt
GNO

t ANLG GNO and OGTL GNO are not connected internally and should be tied together as close to the
device pins as possible.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANLG VDD, DGTL VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Digital input voltage range, VI ......................................... - 0.5 V to 7 V
Analog reference voltage range, Vref .......................... VDD-1.7 V to VDD+0.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 55°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C

TEXAS •
INSTRUMENTS
4-48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5602, TLC5602A
LinEPICTM 8·BIT DIGITAL·TO·ANALOG CONVERTERS
recommended operating conditions
Supply voltage, VDD

MIN

NOM

MAX

UNIT

4.75

5

5.25

V

3.8

4

4.2

V

Analog reference voltage, V ref

High-level input voltage, VIH

2

V

low-level input voltage, Vil

0.8

Pulse duration, ClK high or low, tw
Setup time, data before ClK!, tsu

l TlC5602
l TlC5602A

Hold time, data after ClK!, th

V

25

ns

16.5

ns

12.5

ns

4.5

Phase compensation capacitance, Ccomo (see Note 1)

1

Operating free-air temperature, T A

0

I'F
70

°C

NOTE 1: The phase compensation capacitor should be connected between COMP and ANlG GND.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER

TEST CONDITIONS

I Digital
I inputs

IIH

High-level input current

III

low-level input current

Iref

Input reference current

VFS

Full-scale analog output voltage

MIN

Typt

MAX

UNIT

VI

~

5 V

±1

I'A

VI

~

0 V

±1

itA

Vref ~ 4 V
VOO

~

10

5 V, Vref

~

4.05 V

VZS

Zero-scale analog output voltage

ro

Output resistance

TA

Ci

Input capacitance

fclock

IOD

Supply current

fclock ~ 20 MHz, Vref ~ VOD - 0.95 V

~

25°C
~

1 MHz, TA

~

VOD-15
3.919

VOO
3.98

60

80

25°C

mV

4.042

V

100

(J

pF

15
16

itA

VOO+15

25

mA

operating characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER

TEST CONDITIONS

El

Linearity error, best straight line

El

Linearity error, end point

ED

Linearity error, differential

MIN

Typt

MAX

UNIT

±0.2%
±0.15%
±O.2%

Gdiff Oifferential gain

NTSC 40 IRE modulated ramp,

0.7%

<7>diff Differential phase

fclock ~ 14.3 MHz

0.4°

tpd

Propagation delay, ClK to analog output

Cl

~

10 pF

25

ns

ts

Settling time to within Y, lSB

Cl

~

10 pF

30

ns

t All typical values are at VOO

5 V and T A ~ 25°C.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

4-49

TLC5602, TLC5602A
LinEPICTM 8·BIT DlGlTAL·TO·ANALOG CONVERTERS
PARAMETER MEASUREMENT INFORMATION
I+--t su

*"

~

th

07.00 ----"""'j
...

~

•

6 3 .988
3.984

V~EP
0
0
0
0
0
0
0
0

;;
0
0
0
0
0
0

*- k-l?~~
V

...
•

0

...

0
0
0
0
0
0

•

...

.

...
...
'::...
......
0

......
......
.........
0

......
......
.........
...

I:L-- ....

£..1

EL1

r-

Vzs

0

;;
0
0
0
0
0

• •

...
.........
......

;;

0
0
0
0
0
0
0

...
0
0
0
0
0
0

• •

... ...

FIGURE 3

FIGURE 2

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

...
......
......
......

0

Digital Input Code

Digital Input Code

4-50

EL253

*- ~~~+~

EL 127
4.492

'"
o 4.488

0
0
0
0
0
0
0

-J ~

~ ,t:.- ~
h../,

EL 129

6 3.988
>
......
• ......
...

EL25f --:i

I
EL128~

4.496

ct

VFS~22.5 ~-:j

I

I

3.984

0

0
0
0
0
0
0

..

coc

STEP , /
- . 2 ,/'

3.980

I

o

//

.ii
>

~

12~1

'" 4.488

I

~ 4.992
~

V

I

_ VDO = 5.000 V
Vref = 4.050 V

4.996

..

STEP
,//
129
STEP
128
STEP /

o

5.000

...
.........
......

0

.........
......
......
...

TLC5602, TLC5602A
LinEPICTM 8-BIT DIGITAL-TO-ANALOG CONVERTERS

TYPICAL CHARACTERISTICS
ZERO-SCALE OUTPUT VOLTAGE
vs
TEMPERA TURE

OUTPUT RESISTANCE
vs
TEMPERATURE
100

4.02

>

.,I

Cl

4.00

5

Cl

I

"0

i

>
:;

f...--

j

So
::l

VDD = 5 V
VDD - Va = 0.5 V
90 - DATA INPUT = FF
TA = 25°C

VDD = 5 V
r- Vref = 4.050 V
See Note 2

3.98

~

.,

0

r--

- -

iij

.,I
"c
5
'iii
.,
a:

80

II>

:;

en"
0
;;

r--- r-'

N

I

en

70

So
::l

3.96

0
I

I

.9

60

3.94

N

>

50

3.92

o

10

20

30

40

50

60

o

70

10

20

FIGURE 4

«

..

5

I

VDD = 5 V
Vref = 4.050 V
fclock = 20 MHz
See Note 2

~ 4.8

.,

:;

Cl

17

-:....

u

----

>-

I

Q.

§- 16
en
I

o
E

-t----

I

--l~.
,

r-----i15

I
14

I

1

..-

!

10

20

30

40

/
+-'/

70

04.2 -.

.,
en" 4 - f - 6
;;
'I 3.8

- --r--

iij

I

-~

!

N

>

I

70

3.6
3.4
3.4

--

,,

c-lL

I

i
I

/1

en

I

/

I

~
I

i/

So
::l

I

60

I

:; 4.4

::::::::

I

50

~

>

-- - -

i

i

V~D

= V
TA = 25°C-~
See Note 2

"0

I
o

~

5 4.6 -

._--

I

~

60

ZERO-SCALE OUTPUT VOLTAGE
vs
REFERENCE VOLTAGE

E
c

50

FIGURE 5

SUPPLY CURRENT
vs
TEMPERATURE

18

40

T A - Free-Air Temperature - °C

TA-Free-Air Temperature- °C

20

30

I

/

I
3.6

3.8

4

4.2

4.4

4.6

T A - Free-Air Temperature - °C

Vref-Reference VOltage-V

FIGURE 6

FIGURE 7

4.8

5

NOTE 2. Vrel is relative to ANlG GNO. VOD is the voltage between ANlG VOO and DGTl VOD tied together and ANlG GND and DGTl
GNO tied together.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-51

TLC5602, TLC5602A
LinEPICTM 8-BIT DIGITAL-TO-ANALOG CONVERTERS
APPLICATION INFORMATION
The following design recommendations will benefit the TLC5602 and TLC5602A user:
1. External analog and digital circuitry should be physically separated and shielded as much as possible
to reduce system noise.
2. Use RF breadboarding or RF printed-circuit board (PCB) techniques throughout the evaluation and
production process.
3. Since ANLG GNO and OGTL GNO are not connected internally, these pins need to be connected
externally. With breadboards, these ground lines should be connected to the power supply ground
through separate leads with proper supply bypassing. A good method is to use a separate twisted
pair for the analog and digital supply lines to minimize noise pickup.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic
inductance and resistance. The ground plane is the better choice for noise reduction.
4. ANLG VOO and OGTL VOO are also separate internally, so they must be connected externally. These
external PCB leads should also be made as wide as possible. A ferrite bead or equivalent inductance
should be placed in series with the ANLG VOO pin and the decoupling capacitor as close to the device
pins as possible before the ANLG VOO and OGTL VOO leads are connected together on the board.
5. ANLG VOO to ANLG GNO and OGTL VOO to OGTL GNO should be decoupled with a 1-{tF and 0.01-{tF
capacitor, respectively, as close as possible to the appropriate device pins. A ceramic chip capacitor
is recommended for the 0.01-{tF capacitor.
6. The phase compensation capacitor should be connected between the CaMP pin and the ANLG GNO
pin with as short a lead-in as possible.
7. The no-connection (NC) pins on the small-outline package should be connected to the ANLG GNO pin.
8. ANLG VOO, ANLG GNO, and the A OUT pins should be shielded from the high-frequency pins, CLK
and 00-07. ANLG GNO ground traces should be placed on both sides of the A OUT trace on the PCB.

~

TEXAS
INSTRUMENlS
4-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-1

c

en
"'C

»

::s
Q)

o-

(.Q

...::s
CD

:l,.
Q)
(')

CD
Q)

::s
a.
('")

o
::s
<
CD

..,

_.

tn

o

::s

5-2

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
FEBRUARY 1990-REVISED AUGUST 1991

•
•

•
•
•
•
•
•

N PACKAGE

Advanced LinCMOS'" Technology

(TOP VIEW)

Self-Calibration Eliminates Expensive
Trimming at Factory and Offset Adjustment
in the Field

ANlG VccININ+ 3
ANlG GNO
REF
ANlG Vec+ 6
TIE HIGH
ClKIN
WR
CS
RO
OGTL GNO
REAOY OUT
INT

12-Bit Plus Sign Resolution
11-Bit Linearity
12-[1s Conversion Period (clock = 2 MHz)t
Compatible with All Microprocessors
Single 5-V and ±5-V Supply Operation
True Differential Analog Voltage Inputs with
-Vref to Vref Differential Input Range

•

For Single 5-V Supply, Input CommonMode Voltage Range is 0 V to 5 V

•

For ±5-V Supplies, Input Common-Mode
Voltage Range is -5 V to 5 V

•
•
•

Unipolar or Bipolar Operation

~

2s Complement Output

c:l

OGTl Vce
012
011
010
09
08
07
I/O
06
BUS
05/015
04/014
03/013
02/012
01/011
00/010

FN PACKAGE
(TOP VIEW)

00

;9-Y

:3+ 1:3~N

~~~~8CiCi

Low Power ... 85 mW Maximum

description

REF
ANLG Vcc+
TIE HIGH
ClK IN
WR
CS
RO

4

3 2 1 28 27 26

0
25 010
The TLC1125 converter is manufactured with
6
24 09
Texas Instruments highly efficient Advanced
7
23 08
LinCMOS'" technology. The TLC1125 CMOS
8
22 07
analog-to-digital converter can be operated with
9
21 06
a single 5-V supply or with ±5-V supplies. The
10
20 05/015
differential input range is -Vref to Vref in both
11
19 04/014
supply configurations. The common-mode input
12 1314 15 16 1718
range is ANLG Vce- to ANLG VCC+. For single
0
0 ~ N <'l
5-V supply operation, grounding IN- corresponds
zc:l
~ 12.
12. 12. 12.
O~N<'l
to standard unipolar conversion. For ±5-V supply
~
0 0
operation, grounding IN- corresponds to standard
~
bipolar conversion. Conversion is performed via
a:
the successive-approximation method. The TLC1125 outputs the converted data in a parallel word and
interfaces directly to a 16-bit data bus. Negative numbers are given in the two's complement data format. All
digital signals are fully TTL and CMOS compatible.
5

f-If-

6

is

bOO

This converter uses a self-calibration technique by which seven of the internal capacitors in the capacitive array
of the AID conversion circuitry can be automatically calibrated. The internal capacitors are calibrated during a
nonconversion capacitor-calibrate cycle in which all seven of the internal capaCitors are calibrated at the same
time. A conversion requires only 24 clock cycles. Self-calibration requires 300 clock cycles. The calibration or
conversion cycle may be initiated at any time by issuing the proper command word to the data bus. The
self-calibrating technique eliminates the need for expensive trimming of thin-film resistors at the factory and
provides excellent performance at low cost.
The TLC11251 is characterized for operation from -40°C to 85°C.
t The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and ND conversion times.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

TEXAS

-If

Copyright © 1991! Texas Instruments Incorporated

INSIRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

5-3

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
functional block diagram

r---------,
I
ANLGVCC_

8-Bit
Calibration
DAC

,-

,IN +

13-Bit
Capacitor DAC
and SIH

;:::~

7>

[

~

13-Blt
Capacitor DAC
and SIH

INREF

~

13-Blt Switch Control

I

13-Bit SAR

Address
Counter
1

Address
Counter
2
/

Clocks

6

Input Data Latches

I

I

I r---

13

I

6/,
1~.

I

TIE HIGH

'I

INT

I

MUX

I
Control
ROM

L--

Program
Counter

L--J-+t- - I

CS
WR
RD
READY OUT

TEXAS

~

INSTRUMENTS
5-4

a-Bit
Data
Path

I
I
I
I

a-Word
RAM

I

13-Blt Calibration
Control Logic

13

a-Bit SAR
Register 1

AUL

1

5-V 10-V Translator

,

a-Bit Switch
Control

Register 2

I
I
I

13-Blt Data Latch

Microprocessor

la

13

1/0 BUS

a

I

13

13

I
I ,---.I
I

a-Bit
Calibration
DAC

'--

~

I

a

POST OFFICE BOX 655303 • DALLAS, TEXAS 7,5265

_..J

TLC1125
SELF·CALIBRATING 12-BIT·PLUS·SIGN
ANALOG·TO·DIGITAL CONVERTER
operation description
calibration of comparator offset
The following actions are performed to calibrate the comparator offset:
1)

The IN+ and IN- inputs are internally shorted together so that the converter input is zero. A course
comparator offset calibration is performed by storing the offset voltages of the interconnecting
comparator stages on the coupling capacitors that connect these stages. Refer to Figure 1. The
storage of offset voltages is accomplished by closing all switches and then opening switches A and
P;, then switches Band B', and then C and C'. This process continues until all interconnecting stages
of the comparator are calibrated. After this action, some of the comparator offset still remains
uncalibrated.

Figure 1. Comparator Offset Null
2)

An AID conversion is done on the remaining offset with the a-bit calibration DACs and a-bit SAR and
the result is stored in the RAM.

calibration of the ADC's capacitive capacitor array
The following actions are performed to calibrate capacitors in the 13-bit DACs that comprise the ADC's
capacitive array:
1)
2)

3)

4)

5)

The IN + and IN- inputs are internally disconnected from the 13-bit DACs.
The most significant bit (MSB) capacitor is tied to REF, while the rest of the array capacitors are tied
to GND. The AID conversion result for the remaining comparator offset, obtained in Step 2 above,
is retrieved from the RAM and is input to the a-bit DACs.
Step 1 of the Calibration of Comparator Offset sequence is performed. The a-bit DAC input is
returned to zero and the remaining comparator offset is then subtracted. Thus, the comparator offset
is completely corrected.
Now the MSB capacitor is tied to GND, while the rest of the array capacitors, Cx, are tied to REF.
An MSB capacitor voltage error (see Figure 2) on the comparator output will occur if the MSB
capacitor does not equal the sum of the other capacitors in the capacitive array. This error voltage
is converted to an a-bit word from which a capacitor error is computed and stored in the RAM.
The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB
capacitor grounded and then performing the above Steps 1-4 while using the next most significant
capacitor in lieu of the MSB capacitor. The seven most significant capacitors are calibrated in this
manner.

TEXAS ."

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-5

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
Vref (Step 3)
GND (Step 4)

~
-L CMSB + -L Cx

}
T

Cx

T

MSB Capacitor
Voltage Error
(Step 4)

CMSB-

'-v-"
GND (Step 3)
Vref (Step 4)

Figure 2. Capacitor Array Null
analog-to-digital conversion
The following steps are performed in the analog-to-digital conversion process:
1)

2)
3)

Step 1 of the Calibration of Comparator Offset Sequence is performed. The ND conversion result
for the remaining comparator offset, which was obtained in Step 2 of the Calibration of Comparator
Offset, is retrieved from the RAM and is input to the 8-bit DACs. Thus the comparator offset is
completely corrected.
IN + and IN- are sampled into the 13-bit capacitive arrays.
The 13-bit analog-to-digital conversion is performed. As the successive-approximation conversion
proceeds successively through the seven most significant capacitors, the error for each of these
capacitors is recovered from the RAM and accumulated in a register. This register controls the 8-bit
DACs so the total accumulated error for these capacitors is subtracted out during the conversion
process.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (ANLG Vcc + AND DGTL V cel (see Note 1) .................................... 7.5 V
Supply voltage, ANLG Vcc- .......................... : ................................... -7.5 V
Control and Clock input voltage range ................................... -0.3 V to DGTL Vcc +0.3 V
Analog input (IN +, IN-) voltage range, V, + and V,_ .......... ANLG VCC- -0.3 V to ANLG Vcc+ +0.3 V
Reference voltage range, Vref ........................................ -0.3 V to ANLG Vcc+ +0.3 V
Pin 7 voltage range ................................................. -0.3 V to ANLG Vcc+ +0.3 V
Output voltage range .................................................. -0.3 V to DGTL Vcc +0.3 V
Input current (per pin) .................................................................... ±5 mA
Input current (per package) .............................................................. ±20 mA
Operating free-air temperature range, T A ............................................ -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
NOTE 1: All analog voltages are referred to ANLG GND and all digital voltages are referred to DGTL GND.

TEXAS

~

INSlRUMENTS
5-6

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
recommended operating conditions
ANLGVCC+
ANLGVCC_

Supply voltage

All digital inputs except CLK IN

(VCC = 4.75 V to 5.25 V)

CLKIN

Low-level input voltage, VIL

All digital inputs except CLK IN

(VCC = 4.75 Vto 5.25 V)

CLKIN

MAX

4.5

6

-5.5

UNIT

ANLG GND

4.5

DGTLVCC
High-level input voltage, VIH

MIN

V

6

2
V

3.5
0.8

V

1.4

Analog input voltage, VI+, VI_

ANLGVCC_-0.05

Pin 7 (TIE HIGH)

V

ANLG VCC+ 0.05

2

Clock input frequency, fclock
Clock duty cycle

V

0.3

2

40%

60%

MHz

Pulse duration, CS and WR low, tw

15

ns

Setup time before WR 1 or CS 1, tsu

60

ns

Hold time after WR 1 or CS 1, th

50

ns

-40

Operating free-air temperature, TA

°c

85

electrical characteristics over recommended operating free-air temperature range,
ANLG Vcc+ :: DGTL VCC :: Vref:: 5 V, ANLG VCC-:: -5 V or ANLG GND (unless otherwise noted)
(see Note 2)
PARAMETER

TEST CONDITIONS

110=-1.8mA

MIN

MAX

2.4

High-level output voltage

DGTL VCC = 4.75 V

I 10 =-50 ~A

VOL

Low-level output voltage

DGTL VCC = 4.75 V,

10 = 3.2 mA

rref

Input resistance, REF terminal

IIH

High-level input current

VI =5V

IlL

Low-level input current

VI = 0

High-impedance-state

VO=O

-3

output leakage current

VO=5V

VOH

10Z

V

4.5
1

0.4

V

10

MQ

5

~A

-5

~

3
-6

VO=O

UNIT

~A

mA

10

Output current

DGTL ICC

Supply current from DGTL V CC

fclock = 2 MHz,

CS high

6

mA

ANLG ICC+

Supply current from ANLG VCC +

fclock = 2 MHz,

CS high

9

mA

8

Vo =5V

-3
rnA
CS high
fclock = 2 MHz,
NOTE 2: The Input voltage range IS defined as: VI + = -5.05 V to 5.05 V, VI_ = -5.05 V to 5.05 V, and I VI + - VI_I s 5.05 V when ANLG
VCC- = -5 V. The input voltage range is defined as: VI + = -0.05 V to 5.05 V, VI_ = -0.05 V to 5.05 V, and I VI + - VI_I s 5.05 V when
ANLG VCC- = ANLG GND.
ANLGICC_

Supply current from ANLG VCC-

TEXAS

-Ill

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-7

TLC1125
SElF·CALlBRATING 12·BIT·PlUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
electrical characteristics over recommended operating free-air temperature range,
ANLG Vcc+ =DGTL Vcc =Vref =5 V, ANLG Vcc- =-5 V or ANLG GND, fclock = 2 MHz (unless
otherwise noted) (see Note 2)
PARAMETER

EL

TEST CONDITIONS

TYpt

VCC+=5V, VCC_=-5V
0< (IN+-IN-) < 5.05 V,

Differential linearity

VCC+=5V,

VCC-= 0

>-1

2

>-1

2
±1.5
±2

Unadjusted positive and negative full-scale error
15

ppmtC

Temperature coefficient of offset point

1.5

ppmtC

kSVS

Supply voltage sensitivity

CMRR

Common-mode rejection ratio

±0.75

Positive and negative
full-scale error

ANLG VCC+ = 5 V ±5%,
ANLG VCC- = -5 V ±5%,
DGTL VCC = 5 V ±5%

Common-mode rejection (maximum code
change from code 0000000000000)

LSBi=§

±0.75
±0.25

Linearity error
IN-=IN+=-5Vt05V

65

IN-=IN+=-5Vt05V

4

dB
LSB:j:
24

Conversion period (1/fclk) (see Note 3)
Access time (delay from falling edge of

tdis

LSB+
LSB:j:

Temperature coefficient of gain
Zero error

ta

UNIT
FSR:j:

LSBH

Zero error

tperiod

MAX

±0.024%
-5 V < (IN+ -IN-) < 5 V,

ED

MIN

Integral linearity error

CL= 100pF

CS . RD to data output)
Disable time, output (delay from rising

RL = 2 kR,

edge of RD to high-impedance state)

CL = 100 pF

clock
cycles

95

ns

90

ns

Idl(READY)

Control signal edge to READY OUT delay time

td2(READY)

Control Signal edge to READY OUT delay time

100
100

ns

tdllNT)

RD or WR to reset of INT delay time

100

ns

ns

t All typical values are at T A = 25°C.
:j: FSR is Full-Scale Range: 0.024% FSR linearity error is equivalent to II-bits of linearity with 1 LSB = 1.22 mV defined for 12 bits.
§ No missing codes.
NOTES: 2. The input voltage range is defined as: VI + = -5.05 V to 5.05 V, VI_ = -5.05 V to 5.05 V, and I VI + - VI_ I " 5.05 V when
ANLG VCC-=-5 V. The input voltage range is defined as: VI+ =-0.05 Vt05.05V, VI_=-0.05Vt05.05V, and I VI+-VI_I ,,5.05 V
when ANLG VCC- = ANLG GND.
3. In practical use of the device, if INT and RD go low within the same fclock period, INT will not be reset until WR is brought low. If INT
and RD do not go low within the same fclock period, INT will be reset.

TEXAS "11

INSTRUMENTS
5-8

POST OFFICE BOX 65S303 • DALLAS. TEXAS 75265

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
PARAMETER MEASUREMENT INFORMATION
l1li
1

.1

I..

rLfU1.JLfL.fVV
o

RD

INT

11

11

1

I

:

:

3

Input Sampling

I

114--------'•.r
-

1

10

Conversion

I
24

Li
I

~I

td(INT)

---+:----~I------------------------~"
-1

1

"I

tdl (READY) -..:

14-I

I

14--

t

1

I

)1- :

'---+1..J

d2(READY)

1
1

tdl (READY)

~

I

READY OUT

_

"I

14--

td2(READY)

I

I

I

tsu
I/O BUS

I
__....:_ _ _ _ _ _ __

~

'4---to~,f--th
:

:

ta4

14--~~- tdls
I

_In_-')>------------------«~-O-u-t- . . , [ ) > - - - - - -

(.,..-I-n-..,j>---<.....
Command to Calibrate
7 Capacitors & Offset
(Requires 300 Clock Cycles)

Command to
Initiate Conversion

Figure 3. Timing Diagram

TEXAS -1!1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-9

TLC1125
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO~DlGITAL CONVERTER
PARAMETER MEASUREMENT INFORMATION
DGTL
vee

vee
RD
GND

Data
Output
RL
-::-

-::-

---.I
VOH
Data Output
GND

-::-

90%
1

10%

~tdiS

~

DGTL
Vee

~

Vee
RD
GND

I

I

RL
Data
Output

90%
1 10%

==r:---.I 14- tdis

Vee
Data Output
VOL

10%

Figure 4. Load Circuits and Waveforms

APPLICATION INFORMATION

unipolar and bipolar operation
For single-ended signal input, the IN+ input is connected to the analog source and the IN- input is connected
toANLG GND.lnthe unipolar configuration, the ADC uses aSingle 5-V supply and the analog input voltage range
is 0 V to 5 V. Data bit D12 will always remain low. In the bipolar configuration, the ADC uses ±5-V supplies and
the analog input voltage range is -5 V to 5 V. Data bit D12 indicates the sign of the input signal. In both
configurations, the 13-bit data format is extended sign with 2's complement, right justified data.

power-up sequence
Calibration is not automatic on power-up. Calibration is initiated by writing control words to the six leastsignificant
bits of the data bus. Vref must have fully settled before calibration is initiated. If addressed or initiated, conversion
can begin after the first clock cycle. However, full ND conversion accuracy is not established until after internal
capacitor calibration.

conversion .start sequence
The writing of the conversion command word to the six least significant bits of the data bus, when either CS or
WR goes high, initiates the conversion sequence.

analog sampling sequence
Sampling of the input signal occurs during clock cycles 3 thru 10 of the conversion sequence.

completed AID conversion
When INT goes low, conversion is complete and the AID result can be read. A new conversion can begin
immediately. The AID conversion is complete at the end of clock cycle 24 of the conversion sequence.

TEXAS

~

INSTRUMENlS
5-10

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1125
SELF·CALIBRATING 12·BIT-PLUS-SIGN·
ANALOG·TO·DIGITAL CONVERTER
aborting a conversion in process and beginning a new conversion
If a conversion is initiated while a conversion sequence is in process, the ongoing conversion will be aborted
and a new conversion sequence will begin.

reading the conversion result
When both CS and RD go low, all 13 bits of conversion data are output to the I/O bus. The format of the output
is extended sign with 2's complement, right justified data. The sign bit 012 is low if VI + - VI_ is positive and high
if VI + - VI_ is negative.

general
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD will reset
INT. The falling edge of the low-going combination of CS and WR will also reset INT.
ready out
For high-speed microprocessors, READY OUT allows the TLC1125 to insert a wait state in the microprocessor's
read or write cycle.
reference voltage (Vref)
This voltage defines the range for I VI + - VI_I. When I VI+ - VI_I equals Vrel, the highest conversion data value
results. When I VI+ - VI_I equals 0, the conversion data value is zero. Thus, for a given input, the conversion
data changes ratiometrically with changes in Vrel' Calibration should be performed with the same value of Vrel
as will be used during conversion.
TIE HIGH
This pin is a digital input and should be tied high.

calibration and conversion considerations
Calibration of the internal capacitors and NO conversion are two separate actions. Each action is independently
initiated. A calibration command should be initiated prior to subsequent conversions. It is not necessary to
recalibrate before each conversion. Capacitor calibration is expected to last indefinitely as long as the clock
signal and power are not interrupted. However, the offset calibration may drift with temperature changes. The
temperature coefficient ofthe offset pOint is shown in the electrical characteristics table. We recommend periodic
calibration at the user's convenience. Calibration and conversion commands require 300 and 24 clock cycles,
respectively.
The calibrate and conversion commands are initiated by writing control words on the six least significant bits
of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of
these commands is illustrated in the Timing Diagram. The bit patterns for the commands are shown in Table 1.
Table 1. Conversion Commands
1/0 BUS
COMMAND

cs +WR

Conversion

1
1

Calibrater

REQUIRED NUMBER
OF CLOCK CYCLES

015

014

013

012

011

010

H

L
X

x

x

X

L

24

L

L

L

L

300

L

t Calibration is lost when clock is stopped.

TEXAS

l!1

INSffiUMENlS
POST OFFICE BOX 65S303 • DALLAS, TEXAS 7S265

5-11

TLC1125
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
analog inputs
differential inputs provide common-mode rejection
The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN+ and INinputs, such as 60-Hz noise. There is no time interval between the sampling of the IN + and IN- so these inputs
are truly differential. Thus, no conversion errors result from a time interval between the sampling of the IN + and
IN- inputs.
input bypass capacitors
Input bypass capacitors may be used for noise filtering. However, the charge on these bypass capacitors will
be depleted during the input sampling sequence when the internal sampling capacitors are charged. Note that
the charging of the bypass capacitors through the differential source resistances must keep pace with the charge
depletion of the bypass capacitors during the input sampling sequence. Higher source resistances reduce the
amount of charging current for the bypass capacitors. Also, note that fast, successive conversion will have the
greatest charge depletion effect on the bypass capacitors. Therefore, the above phenomenon becomes more
significant as source resistances and the conversion rate (I.e., higher clock frequency and conversion initiation
rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between conversions,
voltage drops across the source resistances will result due to the ongoing bypass capacitor charging currents.
The voltage drops will cause a conversion error. Also, the voltage drops increase with higher I VI + - VI_I values,
higher source resistances, and lower charge on the bypass capacitors (I.e., faster conversion rate).
For low-source-resistance applications (Rsource < 100 Q), a 0.001-!J.F bypass capacitor at the inputs will prevent
pickup due to the series lead inductance of a long wire. A 100-Q resistor can be placed between the capacitor
and the output of an operational amplifier to isolate the capacitor from the operational amplifier.
input leads
The input leads should be kept as short as possible, since the coupling of noise and digital clock signals to the
the inputs can cause errors.
power supply considerations
Noise spikes on the Vee lines can cause conversion error. Low-inductance tantalum capacitors (> 1 !J.F) with
short leads should be used to bypass ANLG Vec and DGTL V cc. A separate regulator for the TLC1125 and
other analog circuitry will greatly reduce digital noise on the supply line.

TEXAS

-1!1

INSTRUMENlS
5-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1125
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO-DIGITAL CONVERTER

r

APPLICATION INFORMATION
(4095) 0 11111111 1111
(4094) 0 111111111110

(2) 0 0000 0000 0010
(1) 0 0000 0000 0001
(0) 0 0000 0000 0000

"o

'C

()

'5

7r"':: - - - -

a.

~

POSiltlVe
Full-Scale
Transition

1 111111111111 (-1)
- Vref

+ Vref

1111111111110 (- 2)

ANALOG
INPUT VOLTAGE
LSB t

CODE
TRANSITION
(DECIMAL)

- 4095.5
-0.5
0.5
4094.5

- 4096 to - 4095
-1100
Oto 1
4094 to 4095

1 0000 0000 0001 (- 4095)
1 0000 0000 0000 (- 4096)
Analog Input Voltage [VIN(+) - VIN(-)]

t LSB = Vrel + 4095.5

Figure 5. Transfer Characteristic

, - - - - - ; IN +

TIE HIGH
DGTLVCC ~~~--------~+------~

'J? 10 IAF

t__----; INANLG VCC+

See Note A

1---..---------...+--------.

i

'J?

, - - - - - + - - / REF

ANLG VCC-

lOIAF

1---.f--------111

T

O.lIAF

0.11AF

H

1

....------~HH ANLG GND
Signal GND

, - - - -....-1 DGTL GND
PowerGND ~--------------~
NOTES: A. The analog input must have some current return path to ANALOG GND.
B. Bypass capacitor leads must be as short as possible.
C. For high·accuracy applications, use a larger capacitor to reduce reference noise.

Figure 6. Analog Considerations

TEXAS •

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-13

TLC1125
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG·TO·DIGITAL CONVERTER
APPLICATION INFORMATION
5V
15V

>--V0.~

___"

IN(+)

ANLG Vcc +

r

TLCl125

+

10~F

-15 V
IN(-)

Figure 7. Input Protection

5V

4kQ

...---------,

VXDR
I-s-e-e-N-ot-e-s-+---lIN(+)
500Q
ZERO
ADJ
500Q

ANLG Vcc +

1---------....

T

IN(-) See Note A

0.1

~F

+

T- 10~F

DGTLVCC I-------~-----

0.1

TLCl125

flFT

10~F

+

T-

3.9kQ

TIE HIGH

REF

I---.......-~-<

1 kQ
FS
t----Jl.> ADJ
8.2kQ

NOTES: A. VI = 0.15 x ANLG VCC+.
B. 15% of ANALOG Vee" VXDR ,,85% of ANALOG Vee·

Figure 8. Operating With Ratiometric Transducers

TEXAS

~

INSIRUMENlS
5-14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1225
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO·DIGITAL CONVERTER
03611 AUGUST 1990-REVISEO JULY 1991

•
•

N PACKAGE

Advanced LinCMOS'" Technology

(TOP VIEW)

Self-Calibration Eliminates Expensive
Trimming at Factory and Offset Adjustment
in the Field

•

12-Bit Plus Sign Resolution

•
•
•

12-Bit Linearity

Compatible With All Microprocessors

•

Single 5-V and ±5-V Supply Operation

•

True Differential Analog Voltage Inputs
With -Vref to Vref Differential Input Range

•

For Single 5-V Supply, Input
Common-Mode Voltage Range is 0 V to 5 V

•

For ±5-V Supplies, Input Common-Mode
Voltage Range is -5 V to 5 V

ANlG VccININ+
ANlG GND
REF
ANlG Vcc+
TIE HIGH
ClKIN
WR
CS

12-~IS Conversion Period at fclock = 2 MHzt

DGTl Vcc
D12
D11
D10
D9
DB
D7
D6
D5/D15
D4/D14
D3/D13
D2/D12
D1/D11
DO/DID

1

2

3

6

DGTl GND
READY OUT
INT

I/O
BUS

FN PACKAGE
(TOP VIEW)

o
z

•
•

2s-Complement Output

•

Low-Power ... 85 mW Maximum

Unipolar or Bipolar Operation

19
19
..J

+

I

~~~
REF
ANlG Vcc+
TIE HIGH
ClKIN
WR

description

4

5
6

3 2 1 28 27 26
0
25

24

D10
09
DB
D7
D6
D5/D15
D4/D14

7
23
The TLC1225 converter is manufactured with
22
8
Texas Instruments highly efficient Advanced
21
9
LinCMOS'" technology. The TLC1225 CMOS
20
10
analog-to-digital converter can be operated with
19
11
a single 5-V supply or with ±5-V supplies. The
12 1314 15 16 1718
differential input range is - Vref to Vref in both
supply configurations. The common-mode input
range is ANLG VCC- to ANLG VCC+' For single
5-V supply operation, grounding IN-- corresponds
to standard unipolar conversion. For ±5-V supply
operation, grounding IN- corresponds to standard
bipolar conversion. Conversion is performed via the successive-approximation method. The TLC1225 outputs
the converted data in a parallel word and interfaces directly to a 16-bit data bus. Negative numbers are given
in the twos-complement data format. All digital Signals are fully TTL and CMOS compatible.

This converter uses a self-calibration technique by which seven of the internal capacitors in the capacitive array
of the AID conversion circuitry can be automatically calibrated. The internal capacitors are calibrated during a
nonconversion capacitor-calibrate cycle in which all seven of the internal capacitors are calibrated at the same
time. A conversion period requires only 24 clock cycles. Self-calibration requires 300 clock cycles. The

t The conversion period is the reciprocal of the conversion rate and includes the access. sample. setup, and ND conversion times.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty_ Production processing does not necessarity include testing of all
parameters.

lJ1
INSTRUMENTS

Copyright © 1991, Texas Instruments Incorporated

TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-15

TLC1225
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO·DIGITAL CONVERTER
description (continued)
calibration or conversion cycle can be initiated at any time by issuing the proper command word to the data bus.
The self-calibrating technique eliminates the need for expensive trimming of thin-film resistors at the factory and
provides excellent performance at low cost.
The TLC12251 is characterized for operation from -40°C to 85°C.

functional block diagram

,--------,
I

ANLG vcc13-Bit
Capacitor DAC
and S/H

IN +

{

---

13-Bit
Capacitor DAC
and SIH

INREF

t---

I

13

a-Bit
Calibration
DAC

f
l

I
I -...
I

a

8

~

I

/

Clocks
Input Data Latches

II
I

13

MUX

6/,
13

1~.

-

"

TIE HIGH

I

INT

I
Control
ROM

Program
Counter

~---+t---

CS

•
~

TEXAS

-1!1

INSTRUMENTS
5-16

Address
Counter
2

I

13-Bit Calibration
Control Logic

RD

Address
Counter
1

I

13-Bit SAR

8-Bit
Data
Path

8-Word
RAM

I 6

13-Bit Switch Control

READ YOUT

AUL

I
,
I
I

a-Bit
Calibration
DAC

13

WR

8-Bit SAR
Register 1

la

5-V-l O-V Translator

IIOBUS

8-Bit Switch
Control

Register 2

I

13

13-Blt Data Latch

Microprocessor

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

.J

TLC1225
SELF·CALIBRATING 12-BIT·PLUS·SIGN
ANALOG·TO·DIGITAL CONVERTER
operation description
calibration of comparator offset
The following actions are performed to calibrate the comparator offset:
1)

The IN+ and IN- inputs are internally shorted together so that the converter input is zero. A course
comparator offset calibration is performed by storing the offset voltages of the interconnecting
comparator stages on the coupling capacitors that connect these stages. Refer to Figure 1. The
storage of offset voltages is accomplished by closing all switches and then opening switches A and
A', then switches Band B', and then C and C'. This process continues until all interconnecting stages
of the comparator are calibrated. After this action, some of the comparator offset still remains
uncalibrated.

Figure 1. Comparator Offset Null
2)

An ND conversion is done on the remaining offset with the 8-bit calibration DACs and 8-bit SAR,
and the result is stored in the RAM.

calibration of the ADC's capacitive capacitor array
The following actions are performed to calibrate capacitors in the 13-bit DACs that comprise the ADC's
capacitive array:
1)
2)

3)

4)

5)

The IN+ and IN- inputs are internally disconnected from the 13-bit DACs.
The most significant bit (MSB) capacitor is tied to REF, while the rest of the array capacitors are tied
to GND. The ND conversion result for the remaining comparator offset, obtained in Step 2 above,
is retrieved from the RAM and is input to the 8-bit DACs.
Step 1 of the Calibration of Comparator Offset sequence is performed. The 8-bit DAC input is
returned to zero and the remaining comparator offset is then subtracted. Thus the comparator
offset is completely corrected.
Now the MSB capacitor is tied to GND, while the rest of the array capacitors, ex, are tied to REF.
An MSB capacitor voltage error (see Figure 2) on the comparator output will occur if the MSB
capacitor does not equal the sum of the other capacitors in the capacitive array. This error voltage
is converted to an 8-bit word from which a capacitor error is computed and stored in the RAM.
The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB
capacitor grounded and then performing the above Steps 1-4 while using the next most significant
capacitor in lieu of the MSB capacitor. The seven most significant capacitors are calibrated in this
manner.

TEXAS ~

INSTRUMENTS
POST OFF!CE BOX 655303 • DALLAS, TEXAS 75265

5-17

TLC1225
SELF-CALIBRATING 12-81T-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
Vref (Step 3)
GND (Step 4)

~
---L CMSB + ---L Cx

}
T

Cx

T

MSB Capacitor
Voltage Error
(Step 4)

CMSB-

'-v--"
GND (Step 3)
vref (Step 4)

Figure 2. Capacitor Array Null
analog-to-digital conversion
The following steps are performed in the analog-to-digital conversion process:
1)

2)
3)

Step 1 of the Calibration of Comparator Offset Sequence is performed. The NO conversion result
for the remaining comparator offset, which was obtained in Step 2 of the Calibration of Comparator
Offset, is retrieved from the RAM and is input to the 8-bit DACs. Thus the comparator offset is
completely corrected.
IN + and IN- are sampled into the 13-bit capacitive arrays.
The 13-bit analog-to-digital conversion is performed. Asthe successive-approximation conversion
proceeds successively through the seven most significant capacitors, the error for each of these
capacitors is recovered from the RAM and accumulated in a register. This register controls the 8-bit
DACs so the total accumulated error for these capacitors is subtracted out during the conversion
process.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (ANLG Vcc+ and DGTL Vce) (see Note 1) .................................... 7.5 V
Supply voltage, ANLG VCC- .............................................................. -7.5 V
Differential supply voltage, ANLG Vcc+ - ANLG Vcc- ......................................... 15 V
Clock input voltage range ................................................... -0.3 V to Vcc + 0.3 V
Control input voltage range ................................................. -0.3 V to Vcc + 0.3 V
Analog input (IN +, IN-) voltage range,
VI + and VI_ ....................................... ANLG Vcc- -0.3 V to ANLG VCC+ +0.3 V
Reference voltage range, Vref ........................................ -0.3 V to ANLG Vcc+ +0.3 V
Pin 7 voltage range ................................................. -0.3 V to ANLG VCC+ +0.3 V
Output voltage range .................................................. -0.3 V to DGTL Vcc +0.3 V
Input current (per pin) .................................................................... ±5 mA
Input current (per package) .............................................................. ±20 mA
Operating free-air temperature range, T A ............................................ -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
NOTE 1: All analog voltages are referred to ANLG GND and ali digital voltages are referred to DGTL GND.

TEXAS .Jf

INSlRUMENTS
5-18

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1225
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO·DlGITAL CONVERTER
recommended operating conditions

Supply voltage

MIN

MAX

ANlG VCC+

4.5

5.5

ANlG Vec-

-5.5

High-level input voltage, VIH
(VCC

~

4.75 V to 5.25 V)

low-level input voltage, Vil
(Vee

~

4.75 V to 5.25 V)

ANlG GND

4.5

DGTlVCC
All digital inputs except elK IN

UNIT

V

5.5

2

ClK IN

V

3.5

All digital Inputs except ClK IN

0.8

ClK IN

1.4

Analog input voltage, VI+, VI_

ANlG VCC- - 0.05

V
V

ANlG VCC + 0.05

Pin 7 (TIE HIGH)

VCC

~

5V

2

Clock input frequency, fclock

VCC

~

5V

0.3

2

Clock duty cycle

VCC

~

5V

40%

60%

Pulse duration, CS and WR low, tw

VCC

~

5V

15

Setup time before WR I or CS I, tsu

Vce ~ 5 V

60

ns

Hold time after WR I or CS I, th

Vce

50

ns

~

5V

V

ns

-40

Operating free-air temperature, T A

MHz

85

°c

electrical characteristics over recommended operating free-air temperature range,
ANLG Vcc+ = DGTL VCC = Vref = 5 V, ANLG VCC- = -5 V or ANLG GND (unless otherwise noted)
(see Note 2)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

110 ~-1.8 mA
DGTl Vec ~ 4.75 V 110 ~ -50 [iA

VOL

low-level output voltage

DGTl VCC

rref

Input resistance, REF terminal

IIH

High-level input current

VI

~

5V

III

low-level input current

VI

~

0

High-irnpedance-state

Vo

~

output leakage current

Vo

~5V

10Z
10

Output current

~

4.75 V,

10

~

MIN

3.2 mA

0

0,4

V

10

MQ

5

IlA

-5

IlA

-3
3

IlA

-6

VO~O
~5V

UNIT

V

4,5
1

Vo

MAX

2.4

mA

8

DGTlice

Supply current from DGTl Vec

fclock ~ 2 MHz,

CS high

6

mA

ANlG ICC+

Supply current from ANlG VCC +

fclock ~ 2 MHz,

es high

9

rnA

ANlG lec-

Supply current from ANLG Vec-

fclock ~ 2 MHz,

CS high

-3

mA

NOTE 2: The input voltage range is defined as: VI + ~ -5.05 V to 5.05 V, VI_ ~ -5.05 V to 5.05 V, and I VI + - VI_ I ~ 5.05 V when ANlG
Vee- ~ -5 V. The input voltage range is defined as: VI + ~ -0.05 V to 5.05 V, VI_ ~ -0.05 V to 5,05 V, and I VI + - VI_I ~ 5.05 V when
ANlG VCC- ~ ANlG GND.

TEXAS ""
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-19

TLC1225
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG· TO·DIGITAL CONVERTER
electrical characteristics over recommended operating free-air temperature range,
ANLG Vcc+ = DGTL Vcc = Vref = 5 V, ANLG Vcc- = -5 Vor ANLG GND, fclock = 2 MHz (unless
otherwise noted) (see Note 2)
PARAMETER

EL

TEST CONDITIONS

-5 V < (IN + -IN-) < 5 V,
ED

MIN

TYpt

Integral linearity error
VCC+ = 5V, VCC_=-5V
o «IN+-IN-) < 5.05 V,

Differential linearity

VCC+=5V,

VCC-= 0

1

>-1

1

LSB§

±1.5

Unadjusted positive and negative full-scale error

±2

Temperature coefficient of gain
Temperature coefficient of offset point
Zero error
Supply voltage sensitivity

CMRR

Common-mode rejection ratio

LSB
LSB

15

ppml'C

1.5

ppm/"C

±0.75

Positive and negative
full-scale error

ANLG VCC+ = 5 V ±5%,
ANLG VCC- = -5 V ±5%,
DGTL VCC = 5 V ±5%

±0.75

Linearity error
Common-mode rejection (maximum code
change from code 0000000000000)
tperiod

UNIT

FSR*

>-1

Zero error

kSVS

MAX
±0.012%

LSB

±0.25
IN-=IN+=-5Vt05V

65

IN- = IN + = -5 V to 5 V

2

dB
LSB
24

Conversion period (l/fclk) (see Notes 3 and 4)

clock
cycles

Access time (delay from falling edge of
ta

CL = 100 pF

CS . RD to data output)
Disable time, output (delay from rising

RL = 2 kQ,

tdis

edge of AD to high-impedance state)

tdl(READY)

Control signal edge to READY OUT delay time

td2(READy)

Control signal edge to READY OUT delay time

CL = 100 pF

95

ns

90

ns

100

ns
100

ns

RD or WR to reset of INT delay time
100
ns
t(jJ!NTl
t All tYPical values are at T A = 25'C.
FSR is Full-Scale Range: 0.012% FSR linearity error is equivalent to 1 LSB = 1.22 mY.
§ No missing codes.
NOTES: 2. The input voltage range is defined as: VI + = -5.05 V to 5.05 V, VI_ = -5.05 V to 5.05 V, and I VI + - VI_I s 5.05 V when ANLG
VCC- = -5 V. The input voltage range is defined as: VI + = -0.05 V to 5.05 V, VI_ = -0.05 V to 5.05 V, and I VI + - VI_I s 5.05 V
when ANLG VCC- = ANLG GND.
3. If INT and RD go low within the same fclock period, INT will not be reset until WR is brought low. If INT and RD do not go low within
the same fclock period, INT will be reset.
4. The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and AID conversion times .

*

. ..t"il S

TEXAS Y

INSTRUMENTS
5-20

POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

TLC1225
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
PARAMETER MEASUREMENT INFORMATION
~I

1<1
1
1

1

Input Sampling

1

"I--OUT

Command to
Initiate Conversion

Figure 3. Timing Diagram

TEXAS ~

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-21

TLC1225
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
PARAMETER MEASUREMENT INFORMATION
DGTL
vee

vee
RD
GND

Data
Output
RL
-::-

-::-

--.I ~tdiS
VOH
Data Output
GND

-::-

90%
110%

~

DGTL
Vee

~

Vee
RD
GND

RL
Data
Output

90%
110%

--.I

Vee
Data Output
VOL

*- tdls

=I
10%

Figure 4. Load Circuits and Waveforms

APPLICATION INFORMATION

unipolar and bipolar operation
For single-ended signal input, the IN+ input is connected to the analog source and the IN--: input is connected
toANLG GNO.lnthe unipolar configuration, theAOC uses a single 5-V supply and the analog input voltage range
is 0 V to 5 V. Data bit 012 will always remain low. In the bipolar configuration, the AOC uses ±5-V supplies and
the analog input voltage range is -5 V to 5 V. Data bit 012 indicates the sign of the input signal. In both
configurations, the 13-bit data format is extended sign with 2s-complement, right-justified data.

power-up sequence
Calibration is not automatic on power-up. Calibration is initiated by writing control words to the six least significant
bits ofthe data bus. Vref must have fully settled before calibration is initiated. If addressed or initiated, conversion
can begin after the first clock cycle. However, full ND conversion accuracy is not established until after internal
capacitor calibration.

conversion period start sequence
The writing of the conversion command word to the six least significant bits of the data bus, when either CS or
WR goes high, initiates the conversion sequence.

analog sampling sequence
Sampling of the input signal occurs during clock cycles 3 through 10 of the conversion sequence.

completed AID conversion
When INT goes low, conversion is complete and the NO result can be read. A new conversion period can begin
immediately. The NO conversion is complete at the end of clock cycle 24 of the conversion period.

TEXAS

~

INSTRUMENTS
5-22

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1225
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DiGITAL CONVERTER
aborting a conversion period in process and beginning a new conversion
If a conversion period is initiated while a conversion sequence is in process, the ongoing conversion will be
aborted and a new conversion period will begin.

reading the conversion result
When both CS and RD go low, all 13 bits of conversion data are output to the I/O bus. The format of the output
is extended sign with 2s-complement, right-justified data. The sign bit D12 is low ifVI+ - VI_ is positive and high
if VI + - VI_ is negative.

general
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD will reset
INT. The falling edge of the low-going combination of CS and WR will also reset INT.
ready out
For high-speed microprocessors, READY OUT allows the TLC1225 to insert a wait state in the microprocessor's
read or write cycle.
reference voltage (Vref)
This voltage defines the range for I VI+ - VI_I. When I VI+ - VI_I equals Vref, the highest conversion data value
results. When I VI + - VI_I equals 0, the conversion data value is zero. Thus, for a given input, the conversion
data changes ratiometrically with changes in Vref. Calibration should be performed with the same value of Vref
as will be used during conversion.
tie high
This pin is a digital input and should be tied high.

calibration and conversion period considerations
Calibration of the internal capacitors and ND conversion are two separate actions. Each action is independently
initiated. A calibration command should be initiated prior to subsequent conversions. It is not necessary to
recalibrate before each conversion. Capacitor calibration is expected to last indefinitely as long as the clock
signal and power are not interrupted. However, the offset calibration may drift with temperature changes. The
temperature coefficient of the offset point is shown in the electrical characteristics table. Periodic calibration is
recommended. Calibration and conversion commands require 300 and 24 clock cycles, respectively.
The calibrate and conversion commands are initiated by writing control words on the six least significant bits
of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of
these commands is illustrated in the Timing Diagram. The bit patterns for the commands are shown in Table 1.
Table 1. Conversion Commands
COMMAND

CS+WR

Conversion

f
f

CalibrateT

REQUIRED NUMBER

I/O BUS

015

014

013

012

011

010

OF CLOCK CYCLES

H

L

X

X

X

L

L

X

L

L

L

L

24
300

t Calibration IS lost when clock IS stopped.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-23.

TLC1225
SELF·CALIBRATING 12·BIT·PLUS·SIGN
ANALOG·TO·DIGITAL CONVERTER
analog inputs
differential inputs provide common-mode rejection
The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN+ and
IN- inputs, such as 60-Hz noise. There is no time interval between the sampling of the IN + and IN- so these
inputs are truly differential. Thus no conversion errors result from a time interval between the sampling of the
IN + and IN- inputs.

input bypass capacitors
Input bypass capacitors can be used for noise filtering. However, the charge on these bypass capacitors will be
depleted during the input sampling sequence when the internal sampling capacitors are charged. Note that the
charging of the bypass capacitors through the differential source resistances must keep pace with the charge
depletion of the bypass capacitors during the input sampling sequence. Higher source resistances reduce the
amount of charging current for the bypass capacitors. Also, note that fast, successive conversion has the
greatest charge depletion effect on the bypass capacitors. Therefore, the above phenomenon becomes more
significant as source resistances and the conversion rate (i.e., higher clock frequency and conversion initiation
rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between conversions,
voltage drops across the source resistances will result due to the ongoing bypass capacitor charging currents.
The voltage drops cause a conversion error. Also, the voltage drops increase with higher I VI+ - VI_I values,
higher source resistances, and lower charge on the bypass capacitors (i.e., faster conversion rate).
For low-source-resistance applications (Rsource < 100 Q), a 0.001-[lF bypass capacitor at the inputs prevents
pickup due to the series lead inductance of a long wire. A 100-Q resistor can be placed between the capacitor
and the output of an operational amplifier to isolate the capacitor from the operational amplifier.

input leads
The input leads should be kept as short as possible since the coupling of noise and digital clock signals to the
the inputs can cause errors.
power supply considerations
Noise spikes on the Vee lines can cause conversion error. Low-inductance tantalum capacitors (> 1 [IF) with
short leads should be used to bypass ANLG Vee and DGTL Vee. A separate regulator for the TLC1225 and
other analog circuitry greatly reduces digital noise on the supply line.
A ferrite bead or equivalent inductance can be used between the analog and digital ground planes if the digital
ground noise is excessive.

TEXAS

~

INSTRUMENTS
5-24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1225
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
APPLICATION INFORMATION
(4095) 0 111111111111
(4094) 0 1111 1111 1110

Positive
Full·Scale
Transition

'"

'0

o

U

:;
Q.

8- Vref

S~

............- ............Negative
Full·Scale
Transition

1 1111 1111 1111 (-1)
1111111111110 (-2)

+ Vref
CODE
TRANSITION
(DECIMAL)

1 0000 0000 0001 (- 4095)
1 0000 0000 0000 (- 4096)

Analog input Voltage [VIN(+) - VIN(-)]

- 4096 to - 4095
-1 toO
Oto 1
4094 to 4095

ANALOG
INPUT VOLTAGE
LSB t
-4095.5
- 0.5
0.5
4094.5

t LSB = Vre! + 4096

Figure 5. Transfer Characteristic

TEXAS .JJ1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-25

TLC1225
SELF-CALIBRATING 12·BIT-PLUS-SIGN
ANALOG·TO-DIGITAL CONVERTER
APPLICATION INFORMATION
IN(+)
~

TIE HIGH
DGTLVCC

Signal In

+

'J?
IN(-)
ANLGVCC

:. (see Note A)

+

.i-=-

'J?
-=V-

Vre!

T

0.1 I"F

0.11-'F

ANLG GND

Signal GND
, - - - - - . - 1 DGTL GND
PowerGND ~------------~
NOTES: A. The analog input must have some current return path to ANALOG GND.
B. Bypass capacitor leads must be as short as possible.
C. For high-accuracy applications, use a larger capacitor to reduce reference noise.

Figure 6. Analog Considerations
5V
15 V

ANLG VCC +

>--~\NIr-__-'-1IN(+)

TLC1225
-15 V
IN(-)

Figure 7. Input Protection

TEXAS

lJ1

INSTRUMENTS
5-26

10 fAF

-=-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10 fAF

II~

TLC1225
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTER
APPLICATION INFORMATION
5V

~----~---------------l-.~--~
4 kQ

.----------,

VXDR
1-=-=-'---+----lIN(+)
(see Note B)
500 Q
ZERO
ADJ

1

50012

ANLG VCC + 1 - - + - - - - - -

T

IN(-) (see Note A)

0.1 iJ-F

T-+

10i,F

DGTLVCC ~.---~----.

+

10!lF

TLC1225

T-

3.9 kQ

TIE HIGH

Vref 1 - - - " - - - <

1-1+

1uF

NOTES: A. VI = 0.15 x ANLG Vec+.
B. 15% of ANALOG Vee,; VXDR ,; 85% of ANALOG Vee.

Figure 8. Operating with Ratiometric Transducers

TEXAS •
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-27

5-28

TLC15501, TLC15511
Advanced LinEPICTM 10·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
OCTOBER

MAY 1

NWPACKAGE
(TOP VIEW)

•

Single-Poly Advanced LinEPIC'M
Silicon-Gate 1-ftm CMOS Technology

•

Power Dissipation (Max) ... 40 mW

•

Advanced LinEPIC'M Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy

REF+
REFAGNO
AIN

CS
09
08
07

•

Fast Parallel Processing for DSP and ftP
Interface

AVOO
OGN01
OGN02

•

Either External or Internal Clock Can Be
Used

OVOO1
OVOO2
EOC

06
05
04
03
02

00
01

• . Conversion Time ... 6 fts

•

RO
WR
ClKIN

Total Unadjusted Error ... ±1 LSB Max
FN PACKAGE

description

(TOP VIEW)

The TLC1550 and TLC1551 are data acquisition
converters using a 10-bit, switched-capacitor,
successive-approximation
network.
A highspeed, 3-state parallel port directly interfaces to a
digital signal processor (DSP) or microprocessor
(ftP) system data bus. DO through 09 are
the digital output pins with DO being the leastsignificant bit (lSB). Separate power pins for the
analog and digital portions minimize noise pickup
in the supply leads. Additionally, the digital power
is divided into two parts to separate the lower
current logic from the higher current bus drivers.
An external clock can be applied to the ClKIN pin
to override the internal system clock if desired.
The TLC15501 and TLC15511 are characterized
for operation from -40°C to 85°C.

o

I +
Zu.u.

Z

2
w w
I~ 0...J
«a:a:za:

(.!)

AIN
AVOO
OGN01
NC
OGN02
OVOO1
OV OO2

5

° 10

4 3 2 1 28 27 26

25

24
6
7
23
22
8
21
9
10
20
19
11
12 1314 15 16 1718
0

0

~

0

N

09
08
NC
07
06
05

(") ....

1OOOzOOO

W

NC - No internal connection

Advanced LinEPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information Is current as of publication date. Products
conform 10 specllications per the lerms of Texas Instruments standard
warranty. Production processing does nol necessarily include testing of all
parameters.

TEXAS

"J1

Copyright © 1991, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-29

TLC15501, TLC15511
Advanced LinEPICTM 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
functional block diagram

r

~
~
~

++

I
DVDDl;

-

r+-

100kQ
NOM

I

Frequency
Divided by2

00-09

10

Internal
Clock
10-Bit
Capacitor
DAC and S/H

t

+

ClKIN

10

SuccessiveApproximation
Register

Control
logic

sf>-

Clock Detector

REF+
REFAIN

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kQ (Max)

AIN~

I

AIN~

.

CI = 90 pF (Max)
(Equivalent Input Capacitance)

TEXAS

-1!1

INSlRUMENlS
5-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

J,

5 MQ (Min)

TLC15501, TLC15511
Advanced LinEPICTM 10-BIT ANALOG-TO-OIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
Terminal Functions
PIN
NAME
AGND

3 [4J

AIN

4 [5J

Analog voltage input pin. The voltage applied to this pin is converted to the equivalent digital output.

AVDD
ClKIN

5 [6J

The analog positive power supply voltage is applied to this pin. The voltage applied to this pin is designated VDD3'

22 [26J

This pin can be used for external clocking instead of using the internal system clock. It usually takes a few microseconds
before the internal clock is disabled. To use the internal clock, this pin should be tied high or left unconnected.

This pin is the analog ground and is the reference point for the voltage applied on pins AVDD, AIN, REF+, and REF-.

CS

21 [25]

The chip·select input must be low for RD or WR to be recognized by the

DO

11 [13]

Data bus output. DO is bit 1 (lSB).
Data bus output. 01 is bit 2.

01

12 [14]

02

13 [16J

Data bus output. 02 is bit 3.

03

14 [17]

Data bus output. 03 is bit 4.

04

15 [18J

Data bus output. 04 is bit 5.

05

16 [19]

Data bus output. 05 is bit 6.

06

17 [20]

Data bus output. 06 is bit 7.

07

1B [21]

Data bus output. 07 is bit B.

DB

19 [23J

Data bus output. DB is bit 9.

09

20 [24]

Data bus output. 09 is bit 10 (MSB).

NO converter.

DGND1

6 [7]

DGND2

7[9J

DVDD1

B [10]

This is the digital positive power·supply voltage pin that supplies the logic. The voltage applied to this pin is designated

DVDD2

9 [11]

VDD1·
This is the digital positive power-supply voltage pin that supplies only the higher-current output buffers. The voltage
applied to this pin is designated VDD2.

Digital ground 1 is the ground for power supply DVDD1 and is the substrate connection.
Digital ground 2 is the ground for power supply DVDD2.

EOC

10 [12]

End of Conversion output signal. This signal going low indicates that conversion is complete and the results have been
transferred to the output latch. This pin can be connected to the flP or DSP interrupt pin or can be continuously polled.

RD

24 [28J

When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The output latch stores
the conversion results at the most recent negative edge of EOC. The falling edge of RD resets EOC to a high within the
td(EOC) specifications.

REF+

1 [2]

Positive voltage· reference input. Any analog input that is greater than or equal to the voltage on this pin will convert to
1111111111. Analog input voltages between REF+ and REF-will convert to the appropriate result in a ratiometric manner.

REF-

2 [3]

Negative voltage reference input. Any analog input that is less than or equ::.: to the voltage on this pin will convert to
0000000000.

23 [27]

When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds the analog input
until conversion is completed. Before and after the conversion period, which is given by tconv, the ADC remains in the
sampling mode.

WR

t

DESCRIPTION

NO.t

Brackets indicate pin number for FN package.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-31

TLC15501, TLC15511
Advanced LinEPICTM 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Voo 1, V00 2, and V003 (see Note 1) ......................................... 6.5 V
Input voltage range (any input) .............................................. -0.3 V to Voo + 0.3 V
Output voltage range ....................................................... -0.3 V to Voo + 0.3 V
Peak input current (any digital input) ...................................................... ± 10 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range ................................................ -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: NW package ............... 260°C
NOTE 1: VDD1 is the voltage measured at the DVDD1 pin with respect to the DGND1 pin. VDD2 is the voltage measured at the DVDD2 pin with
respect to the DGND2 pin. VDD3 is the voltage measured at the AVDD pin with respect to the AGND pin. For these specifications, all
ground pins are tied together (and represent 0 V). When VDD1, VDD2, and VDD3 are equal, they are referred to simply as VDD.

recommended operating conditions
Supply voltage, VDD1, VDD2, VDD3

MIN

NOM

MAX

4.75

5

5.5

Positive reference voltage, VREF+ (see Note 2)
Negative reference voltage, VREF- (see Note 2)

VDD3
0

Differential reference voltage, VREF+ - VREF-, (see Note 2)

VDD3

Analog input voltage range

0

High-level control input voltage, VIH

2

Low-level control input voltage, VIL

0.5

Input clock frequency, f(ClKIN)

UNIT
V
V
V

VDD3
VDD3

V
V
V

0.8

V

7.8

MHz

Setup time, CS low before WR or RD goes low, tsu(CS)

0

ns

Hold time, CS low after WR or RD goes high, th(CS)

0

ns
ns

50

WR or RD pulse duration, tw(WR)
Input clock low pulse duration, twL(ClKIN)
Operating free-air temperature, T A

40%01
period

80% 01
period

-40

85

°C

NOTE 2: Analog Input voltages greater than that applied to REF+ convert to all '1's (1111111111), while Input voltages less than that applied to
REF- convert to all 'O's (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.

TEXAS .J!1

INSTRUMENTS
5-32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC15501, TLC15511
Advanced LinEPICTM 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
electrical characteristics over recommended operating free-air temperature range,
Voo = VREF+ = 4.75 to 5.5 V and VREF- =0 (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD = 4.75 V,

10H = -360 ",A

VOL

Low-level output voltage

VDD = 4.75 V,

10L = 2.4 mA

Va =VDD,

CS and RD at VDD

VO=O,

CS and RD at VDD

10Z

Off-state (high-impedance state) output current

IIH

High-level input current

VI = VDD

IlL

Low-level input current (except CLKIN)

VI = 0

IlL

Low-level input current (CLKIN)

lOS

Short-circuit output current

100

Operating supply current

Ci

Input capacitance

TYpt

MIN

TA=25°C

10
-10
-2.5

-0.005

-150

-50

7

14
-12

TA=25°C

Va =0,

CS low and RD high

I Analog inputs
I Digital inputs

UNIT

V
0.4

0.005

Va = 5 V,

MAX

2.4

See typical equivalent inputs

2.5

V
",A
~lA

",A
I1A
-6

2

8

60

90

5

15

mA
mA
pF

operating characteristics over recommended operating free-air temperature range with internal
clock and minimum sampling time of 4 ~s, VOO =VREF+ = 5 V and VREF- = 0 (unless otherwise
noted)
PARAMETER
EL

Linearity error

EZS

Zero-scale error

EFS

TEST CONDITIONS
TLC1550
TLC1551

I
I

MIN

TYPT

±0.5

See Note 3

±1

See Notes 2 and 4
TLC1550

Full-scale error

TLC1551

Total unadjusted error

I
I

±1

See Notes 2 and 4

±1
±1

fCLK (external) = 4.2 MHz or internal clock

Conversion time

ta(D)

Data access time after RD goes low

tv(Ol

Data valid time after RD goes high

tdis(D)

Disable time, delay time from RD high to Hi-Z

td(EOC)

Delay time, RD low to EOC high

UNIT
LSB
LSB

±0.5
See Note 5

tconv

MAX

See Figure 1

6

",s

35

ns

30

ns

ns

5
0

LSB
LSB

15

ns

t All typical values are at VDD = 5 V, TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all '1's (1111111111), while input voltages less than that applied to
REF- convert to all'O's (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.
3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value
after zero-scale error and full-scale error have been removed.
4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale. Full-scale
error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.
5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal
value. It includes contributions from zero-scale error, full-scale error, and linearity error.

TEXAS •

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC15501, TLC15511
Advanced LinEPICTM 1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
PARAMETER MEASUREMENT INFORMATION

Test Point
Output
Under Test

(see Note A)

--+--1---'

Vep = 1 V

NOTE A. Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement.

Figure 1. Test Load Circuit

PRINCIPLES OF OPERATION
The operating sequence for complete data acquisition is shown in Figure 2. Processors can address the TLC1550
and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder
output to the CS pin. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when
CS is low. Once CS is low, the on-board system clock permits the conversion to begin with a simple write command
and the converted data to be presented to the data bus with a simple read command. The device remains in a sampling
(track) mode until conversion begins with the rising edge of WR, which initiates the hold mode. After the hold mode
begins, the clock controls the conversion automatically. When the conversion is complete, the end-of-conversion
(EOG) signal goes low indicating that the digital data has been transferred to the output latch. Lowering CS and RD
then resets EOC and transfers the data to the data bus for the processor read cycle.

II-

--:x :
I I

cs

I

~ th(CS)

tsu(CS)

:
I

i"

~ tw(WR) ---I>j I

----~I
WR

1.4v\~

I

VO.8 v

\ ....._0._8_v_ _ _ _ _ _

tconv --~I>I

I

I
I
lf~------------~.----~I-----------------+I-------It.t~
I
I
~

0.8 V \ ; .

~

I

I

ta(O)

i

tsu(CS)

------------------+i--O.-8V"'~
00-09

.;.....~1 0.8 v

II

--f.I

- - - - - - - - - - - - - - - - - -......:......- - -....:-« ~.~V

2V

tv(O)
Data Valid

th(CS)

~~

tdIS(O)

~I

~.~ V )>-----

I
j4- td(EOC) ~
\~II_________--J/~~2~V~------0.8 V \ ; .
Figure 2. TLC1550 or TLC1551 Operating Sequence

TEXAS

.J!}

INSTRUMENTS
5-34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC15501, TLC15511
Advanced LinEPICTM 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
APPLICATIONS INFORMATION
Using the equivalent circuit in Figure 3, the time required to charge the analog input capacitance from 0 to Vs within
1 LSB can be derived as follows:
The capacitance charging voltage is given by
-t IRtC.)
Vc = Vs (1-e
C'
I

(1 )

where
Rt = Rs + rj
The final voltage to 1 LSB is given by
(2)

Vc (LSB) = Vs - (Vs/1024)
Equating equation 1 to equation 2 and solving for time te gives

Vs-(Vs/1024)=Vs(1-e- t c/R t Cj)

(3)

and
te (LSB) " Rt x Cj x In1024

(4)

Therefore, witl the values given
te (LSB) = (Rs + 1 kQ) x 60 pF x In1 024

(5)

I

I

Driving Source t ..

•

TLC1550 or TLC1551

I
RS

I

VI

ri

VS~VC
I
1 kQ (Max)

I

I
I
I

-

C.
I

90 pF (Max)

VI = Input Voltage at AIN
Vs = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci =Equivalent Input Capacitance

Figure 3. Equivalent Input Circuit Including the Driving Source

t Driving source requirements for 1a-bit measurements
1. Rs s 100 Q
2. Noise and distortion s 80 dB
3. Rs must be real at the input frequency.

TEXAS

~

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-35

5-36

TLC32040C. TLC320401. TLC32041 C. TLC320411
TLC32042C. TLC320421

ANALOG INTERFACE CIRCUITS
D2964. SEPTEMBER 1987-REVtSED MAY 1991

•

Advanced LinCMOS" Silicon-Gate Process
Technology

•

14-Bit Dynamic Range ADC and DAC

•

Variable ADC and DAC Sampling Rate Up to
19,200 Samples per Second

•

Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter

•

Serial Port for Direct Interface to
TMS32011, TMS320C17, TMS32020, and
TMS320C25 Digital Processors

•

Synchronous or Asynchronous ADC and
DAC Conversion Rates with Programmable
Incremental ADC and DAC Conversion
Timing Adjustments

•

Serial Port Interface to SN74299 Serial-toParallel Shift Register for Parallel Interface
to TMS32010, TMS320C15, or Other
Digital Processors

•

N PACKAGE
(TOP VIEW)
NU
NU
IN+
IN AUX IN+
AUX INOUT+
OUT-

NU
RESET
EODR
FSR
DR
MSTR CLK
VDD
REF
DGTL GND
SHIFT CLK
EODX
DX
WORD/BYTE
FSX

VCC+
VCCANLG GND
ANLG GND
NU
NU
FN PACKAGE

(TOP VIEW)

600-mil Wide N Package (CL to CLl
4

PART
NUMBER
TLC32040

DESCRIPTION
Analog Interface Circuit with internal
reference. Also a plug-in replacement

TLC32041

for TLC32041 .
Analog Interface Circuit without internal
reference.

TLC32042

DR
MSTR CLK
VDD
REF
DGTL GND
SHIFT CLK
EODX

Identical to TLC32040. but has a
slightly wider bandpass filter bandwidth

3

1 28 27 26
25

6

24

23
22

8
9

21

10

20
19

11

INAUX IN +
AUX INOUT +
OUTVCC +
VCC-

12131415161718

XI~IX Z ZZZ
O>-~
ClCl

:::J :::JOO

to

description

2

5

0a:

ClCl
-'-'

zz

0
The TLC32040, TLC32041, and TLC32042 are
<{<{
complete analog-to-digital and digital-to-analog
input/output systems, each on a single
NU- Nonusable; no external connection should be made to these
monolithic CMOS chip. This device integrates a
pins.
bandpass switched-capacitor antialiasing input
filter, a 14-bit-resolution A/D converter, four microprocessor-compatible serial port modes, a 14-bitresolution D/A converter, and a low-pass switched-capacitor output-reconstruction filter. The device offers
numerous combinations of Master Clock input frequencies and conversion/sampling rates, which can be
changed via digital processor control.

:s:

Typical applications for this IC include modems (7.2-,8-,9.6-, 14.4-, and 19.2-kHz sampling rate), analog
interface for digital signal processors (DSPs). speech recognition/storage systems, industrial process control,
biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17,
TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive
sections of the Analog Interface Circuit (AIC) are operating synchronously, it will interface to two SN74299
Advanced LinCMOSrn is a trademark of Texas Instruments Incorporated
Copyright © 1991, Texas Instruments Incorporated

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments

standard warranty. Production processing does hot
necessarily include testing of all parameters.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-37

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
description (continued)
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry . .output data pulses
are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate
between two transmitted bytes. A flexible control scheme is provided so that the functions of the IC can
be selected and adjusted coincidentally with signa'i processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer, The input filter is
implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate
any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite
filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided
for applications where more than one analog input is required.
The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no
missing codes and monotonic operation. An internal voltage reference is provided on the TLC32040 and
TLC32042 to ease the design task and to provide complete control over the performance of the IC. The
internal voltage reference is brought out to a pir:l and is available to the designer. Separate analog and
digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic range.
Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum.
The only exception is the DAC sample-and-hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded signal.
The TLC32040C, TLC32041 C, and TLC32042C are characterized for operation from O°C to 70°C and
the TLC320401, TLC320411, and TLC320421 are characterized for operation from - 40°C to 85 DC.

functional block diagram
BANOPASS FILTER
SERIAL
PORT

IN+
INAUX IN +

,-

AUX IN-

I

__

~EI~ S':':TI~

_

_

_

I

_

I

""1,

IL..

-.,

VOLTAGE
REFERENCE
(TLC320401
TlC32042
ONLY)
__

I
I

I
I

I
..J

LOW-PASS FILTER
OUT + _ t - - - - - l

1f

OUT - - t - - - - - l
TRANSMIT SECTION
vcc + Vcc _ ANLG OTGL VOD
GND GND (DIG!

~

TEXAS
INSTRUMENTS
5-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3 2040C, TLC3 20401, TLC3 2041 C, TLC3 20411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION

analog input
Two sets of analog inputs are provided. Normally, the IN + and IN - input set is used; however, the auxiliary
input set, AUX IN + and AUX IN -, can be used if a second input is required. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
The gain for the IN +, IN -, AUX IN +, and AUX IN - inputs can be programmed to be either 1, 2, or 4
(see Table 2). Either input circuit can be selected via software control. It is important to note that a wide
dynamic range is assured by the differential internal analog architecture and by the separate analog and
digital voltage supplies and grounds.

AID bandpass filter. AID bandpass filter clocking, and AID conversion timing
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this
filter is presented in the following pages. This response results when the switched-capacitor filter clock
frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter
clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency-scaled by
the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section
is 300 Hz. However, the high-pass section low-frequency roll-off is less steep for the TLC32042 than for
the TLC32040 and TLC32041.
The Internal Timing Configuration and AIC OX Data Word Format sections of this data sheet indicate the
many options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate
that the RX Counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock
for several Master Clock input frequencies.
The AID conversion rate is then attained by frequency-dividing the 288-kHz bandpass switched-capacitor
filter clock with the RX Counter B. Thus, unwanted aliasing is prevented because the AID conversion rate
is an integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.

AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.

analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.

D/A low-pass filter. DIA low-pass filter clocking, and DIA conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function
of this filter is frequency-scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided
on the output of the DIA low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The DI A conversion rate is then attained by frequency-dividing the 288-kHz switched-capacitor filter clock
with TX Counter B. Thus, unwanted aliasing is prevented because the DIA conversion rate is an integral
submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously
locked.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

5-39

TlC32040C, TlC320401, TlC32041 C, TlC3204 n
TlC32042C. TlC320421
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated a!\ynchronously, the low-pass and band-pass filter clocks are independently generated from
the Master Clock signal. Also, the D/A and A/D conversion rates are independently determined. If the
transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and bandpass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal
to, the D/A conversion timing. (See description of the WORD/BYTE pin in the Pin Functional Description
Section.)

CIA converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
-

system frequency response correction
Sin x/x correction circuitry is performed in digital signal processor software. The system frequency response
can be corrected via DSP software to ± 0.1 dB accuracy to a band-edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of
only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the sin x/x Correction Section
for more details).

serial port
The serial port has four possible modes that are described in detail in the Functional Pin Description Section.
These modes are briefly described below and in the Functional Description for Pin 13, WORD/BYTE.
1. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32011 and TMS320C17.
2. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020 and the TMS320C25.
3.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32011 and TMS320C17.

4.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can
then interface in parallel to the TMS3201 0, TMS320C 15, to any other digital signal processor,
or to external FIFO circuitry.

operation of TLC32040 or TLC32042 with internal voltage reference
The internal reference of the TLC32040 and TLC32042 eliminates the need for an external voltage reference
and provides overall circuit cost reduction. Thus, the internal reference eases the design task and provides
complete control over the performance of the IC. The internal reference is brought out to a pin and is available
to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor
may be connected between REF and ANLG GND.

-II}

TEXAS
INSTRUMENTS
5-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC3 2040C, TLC3 20401, TLC3 2041 C, TLC3 20411
TLC32042C, TLC320421

ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
operation of TLC32040, TLC32041, or TLC32042 with external voltage reference
The REF pin may be driven from an external reference circuit if so desired. This external circuit must be
capable of supplying 250 p.A and must be adequately protected from noise such as crosstalk from the
analog input.

reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function will initialize all AIC registers, including
the control register. After a negative-going pulse on the RESET pin, the AIC will be initialized. This
initialization allows normal serial port communications activity to occur between AIC and DSP (see AIC DX
Data Word Format section).

IOQpback
This feature allows the user to test the circuit remotely. In loopback, the OUT + and OUT - pins are internally
connected to the IN + and IN - pins. Thus, the DAC bits (d15 to d2), which are transmitted to the DX
pin, can be compared with the ADC bits (d15 to d2), which are received from the DR pin. An ideal comparison
would be that the bits on the DR pin equal the bits on the DX pin. However, in practice there will be some
difference in these bits due to the ADC and DAC output offsets.
In loop back, if the IN + and IN - pins are enabled, the external signals on the IN + and IN - pins are ignored.
If the AUX IN + and AUX IN - pins are enabled, the external signals on these pins are added to the OUT +
and OUT - signals in loopback operation.
The loopback feature is implemented with digital signal processor control by transmitting the appropriate
serial port bit to the control register (see AIC Data Word Format section).

PIN
NAME

NO.

ANLG GND

17,18

AUX IN+

24

DESCRIPTION

I/O

Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.

I

Noninverting auxiliary analog input stage. This input can be switched into the bandpass filter and AID converter
path via software control. If the appropriate bit in the Control register is a 1, the auxiliary inputs will replace
the IN + and IN - inputs. If the bit is a 0, the IN + and IN - inputs will be used Isee the AIC DX Data Word
Format section).

AUX IN-

23

I

Inverting auxiliary analog input Isee the above AUX IN + pin description!.

DGTL GND
DR

9
5

0

This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission

DX

12

I

Digital ground for all internal logic circuits. Not internally connected to ANlG GND.
of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.
This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.

EODR

3

0

End of Data Receive. See the WORD/BYTE pin description and the Serial Port Timing diagram. During the wordmode timing, this signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have
been transmitted from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor
upon completion of serial communications. Also, this signal can be used to strobe and enable external serialto-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications
between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low
after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the
second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going signal to differentiate
between the two bytes as to which is first and which, is second. EODR does not occur after secondary
communication.

TEXAS

~

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-41

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
PIN
NAME
EODX

NO.
11

I/O

DESCRIPTION

0

End of Data Transmit. See the WORD/BYTE pin description and the Serial Port Timing diagram. During the

word-mode timing. this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 serial port to the AIC. This signal
can be used to interrupt a microprocessor upon the completion of serial communications. Also, this signal

can be used to strobe and enable external serial-ta-parallel shift registers, latches, or an external FIFO RAM,
and to facilitate parallel data-bus communications between the AIC and the serial-ta-parallel shift registers.
During the byte--mode timing, this signal goes low after the first byte has been transmitted from the TMS320

serial port to the AIC and is kept low until the second byte has been transmitted. The TMS32011 or TMS320C17
can use this low-going signal to differentiate between the two bytes as to which is first and which is second.
FSR

4

0

Frame Sync Receive. In the serial transmission modes, which are described in the WORD/BYTE pin description,
the FSR pin is held low during bit transmission. When the FSR pin goes low, the TMS320 serial port will begin
receiving bits from the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR
pin before FSR goes low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not
occur after secondary communication.

FSX

14

0

Frame Sync Transmit. When this pin goes low, the TMS320 serial port will begin transmitting bits to the AIC
via the DX pin of the AIC. In all serial transmission modes, which are described in the WORD/BYTE pin description,
the FSX pin is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration
diagrams).

IN+

26

I

Noninverting input to analog input amplifier stage

IN-

25

I

Inverting input to analog input amplifier stage

6

I

The Master Clock signal is used to derive all the key logic signals of the AIC, such as the Shift Clock, the

MSTR ClK

switched-capacitor filter clocks, and the AID and D/A timing signals. The Internal Timing Configuration diagram
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples
of the Master Clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred
between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configuration).
OUT+

22

0

OUT-

21

0

Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a single-ended configuration.

REF

8

RESET

2

Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT +.

I/O For the TlC32040 and TlC32042, the internal voltage reference is brought out on this pin. For the TlC32040,
TlC32041, and TlC32042. an external voltage reference can be applied to this pin.
I

A reset function is provided to initialize the T A. TA', TB. RA. RA', RB, and control registers. This reset function
initiates serial communications between the Ale and DSP. The reset function will initialize all AIC registers
including the control register. After a negative-going pulse on the RESET pin. the AIC registers will be initialized
to provide an a-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust
registers, TA' and RA', will be reset to 1. The CONTROL register bits will be reset as follows (see AIC DX
Data Word Format section).
d7

=

1, d6

=

1. d5

=

1. d4

= 0,

d3

= 0,

d2

=

1

This initialization allows normal serial-port communication to occur between Ale and DSP.
SHIFT ClK

10

0

The Shift Clock signal is obtained by dividing the Master Clock signal frequency by four. This signal is used
to

clock the

serial

data transfers of the

AIC,

described in the WORD/BYTE pin description

below (see the Serial Port Timing and Internal Timing Configuration diagram).
VDD

7

Digital supply voltage, 5 V ± 5%

VCC+

20

Positive analog supply voltage. '5 V ± 5%

VCC-

19

Negative analog supply voltage - 5 V ± 5%

~

TEXAS
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POST OFFiCE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
PIN
NAME

NO.

WORD/BYTE 13

1/0

DESCRIPTION

I

This pin. in conjunction with a bit in the CONTROL register, is used to establish one of four serial
modes. These four serial modes are described below.
Ale transmit and receive sections are operated asynchronously.
The following description applies when the Ale is configured to have asynchronous transmit and receive sections.

If the appropriate data bit in the Control register is a 0 (see the AIC DX Data Word Format), the transmit and
receive sections will be asynchronous.
Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and communicates
L
in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
1. The FSX or FSR pin is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. The EODX or EODR pin is brought low.
4. The FSX or FSR pin emits a positive frame-sync pulse that is
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. The EODX or EODR pin is brought high.
7. The FSX or FSR pin is brought high.
Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
H
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing
diagrams):
1. The FSX or FSR pin is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. The FSX or FSR pin is brought high.
4. The EODX or EO DR pin emits a low-going pulse.
Ale transmit and receive sections are operated synchronously.
If the appropriate data bit in the Control register is a 1 the transmit and receive sections will be configured
to be synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing will
be derived from the TX Counter A, TX Counter B, and TA, TA', and TB registers, rather than the RX Counter
A, RX Counter B, and RA, RA', and RS registers. In this case, the AIC FSX and FSR timing will be identical
during primary data communication; however, FSR will not be asserted during secondary data communication
since there is no new AID conversion result. The synchronous operation sequences are as follows (see Serial
Port Timing diagrams).
L
Serial port directly interfaces with the serial port of the TMS320 11 or TMS320C 17 and communicates
in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams):
1. The FSX and FSR pins are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is received.
3. The EODX and EODR pins are brought low.
4. The FSX and FSR pins emit positive frame-sync pulses that are
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The EODX and EODR pins are brought high.
7. The FSX and FSR pins are brought high.
H
Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing
diagrams):
1. The FSX and FSR pins are brought low.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. The FSX and FSR pins are brought high.
4. The EODX or EODR pins emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional
NOR and AND gates, will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to
the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel, data
bus communications between the AIC and the digital signal processor. The operation sequence is the same
as the above sequence (see Serial Port Timing diagrams).
I

-Ij}

TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-43

TLC32040C, TLC320401, TLC32041 C, TLC32041I
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
INTERNAL TIMING CONFIGURATION

r - - - - - - - - - - - -,

MASTER CLOCK
5.184 MHz (11
10.368 MHz (21

SHIFT CLOCK

1---ll.!:D~IV~ID~E:2:B~Y,,:4:J-------t----. 1.296 MHz (11

_ _ _ _ _ _ _ _ _ _ _ _ .J

2.592 MHz (21

----------,

OPTIONAL EXTERNAL CIRCUITRY
FOR FULL- OUPLEX MODEMS
--; 53.6 ';;Hz -- CLOCK (11

DIVIDE BY 2
,

COMMERCIAL

I

EXTERNAL
FRONT-END

I

I

F~~~~~=~~X
FILTERS!

LOW-PASS
SWITCHED
CAP FILTER
CLK - 288 kHz
SQUARE WAVE

I
I

_______ :..J

dO.dl- 0 .l
dO.dl-l.0 t

dO,dl - 0,0
dO.dl -1.1 t

TX COUNTER A
ITA = 9 (111
ITA - 18 (211
576-kHz
&...:;16;...::;BI;.;.T;:.SI"-_~ PULSES

TX COUNTER
TB-40; 7.2
TB - 36; 8.0
TB - 30; 9.6
TB-20; 14.4
TB-15; 19.2

B
kHz
kHz
kHz
kHz
kHz

BANDPASS
SWITCHED
CAP FILTER
CLK - 288 kHz
SQUARE WAVE

DIVIDE BY 2

dO,dl- 0 •0
dO.dl = 1.1 t

dO.dl -0.1
dO.dl=1.0 t

RX COUNTER A
IRA = 9 (111
IRA = 18 (211
(6 BITSI
~~~~----~

SCF Clock Frequency

=

576-kHz
PULSES

RX COUNTER
RB=40; 7.2
RB = 36; 8.0
RB = 30; 9.6
RB = 20; 14.4
RB= 15; 19.2

DIA
CONVERSION
FREQUENCY

B
kHz
kHz
kHz
kHz
kHz

AID
CONVERSION
FREQUENCY

Master Clock Frequency
2 x Contents of Counter A

NOTE; Frequency 1. 20.736 MHz. is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular
speech and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously
and as submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal
frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
stages. Frequency 2. 41.472 MHz. is used to show that the AIC can work with high-frequency signals. which are used by highspeed digital signal processors.
t Split-band filtering can alternatively be performed after the analog input function via software in the TMS320.
tThese control bits are described in the AIC DX Data Word Format section.

TEXAS

'iii

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TLC32040C. TLC320401. TLC32041 C. TLC320411
TLC32042C. TLC320421
ANALOG INTERFACE CIRCUITS
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the AIC and DSP, is
derived by dividing the Master Clock input signal frequency by four.
SCF Clock Frequency

=

Conversion Frequency

Shift Clock Frequency =

Master Clock Frequency
2 x Contents of Counter A
SCF Clock Frequency
Contents of Counter B
Master Clock Frequency
4

TX Counter A and TX Counter B, which are driven by the MasterCiock signal, determine the D/A conversion
timing. Similarly, RX Counter A and RX Counter B determine the AID conversion timing. In order for the
switched-capacitor low-pass and bandpass filters to meet their transfer function specifications, the
frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the
clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock
frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of Master Clock
frequency and TX Counter A and RX Counter A values must yield 2BB-kHz switched-capacitor clock signals.
These 288-kHz clock signals can then be divided by the TX Counter Band RX Counter B to establish the
D/A and AID conversion timings.
TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX
Counter B are reloaded every AID conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers, respectively. Via software control, the TX Counter A can be loaded
with either the TA Register, the T A Register less the T A' Register, or the T A Register plus the T A' Register.
By selecting the TA Register less the TA' Register option, the upcoming conversion timing will occur earlier
by an amount of time that equals T A' times the signal period of the Master Clock. By selecting the T A
Register plus the T A' Register option, the upcoming conversion timing will occur later by an amount of
time that equals TA' times the signal period of the Master Clock. Thus, the DI A conversion timing can
be advanced or retarded. An identical ability to alter the AID conversion timing is provided. In this case,
however, the RX Counter A can be programmed via software control with the RA Register, the RA Register
less the RA' Register, or the RA Register plus the RA' Register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description),
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and AID conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA
Register, RA' Register, and RB Registers are not used.

-I.!}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5--45

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
AIC OR or OX word bit pattern
AID or D/A MSB,
1 st bit sent

1st bit sent of 2nd byte

AID or D/A LSB

AIC OX data word format section
COMMENTS

d15Id14Id13Id12Idllldl0!d9!dS!d7!dS!d5!d4!d2!dl!dO
primary OX serial communication protocol
_ d15 (MSB) through d2 go to the D/A

-+!

0

0

The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with TB and RB

converter register

register values.

_ d15 (MSB) through d2 go to the D/A

-+!

0

1

The TX and RX Counter A's are loaded with the TA+TA' and
RA + RA' register values. The TX and RX Counter B's are loaded

converter register

with the TB and RB register values. NOTE: dl =0, dO = 1 will cause
the next D/A and AID conversion periods to be changed by the
addition of TA' and RA' Master Clock cycles, in which TA' and
RA' can be positive or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
_

d15 (MSB) through d2 go to the D/A

-+!

1

0

The TX and RX Counter A's are loaded with the TA-TA' and
RA - RA' register values. The TX and RX Counter B's are loaded

converter register

with the TB and RB register values. NOTE: d 1 = 1, dO = 0 will cause
the next D/A and AID conversion periods to be changed by the
subtraction of TA' and RA' Master Clock cycles, in which TA' and
RA' can be positive or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
_ d15 (MSB) through d2 go to the D/A
converter register

-+!

1

1

The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with the TB and
RB register values. After a delay of four Shift Clock cycles, a
secondary transmission will immediately follow to program the AIC
to operate in the desired config'uration.

NOTE: Setting the two least significant bits to 1 in the normal trans'Dission of DAC information (Primary Communications) to the AIC
will initiate Secondary Communications upon completion of th~ Primary Communications.
Upon completion of the Primary Communication, FSX will remain high for four SHIFT CLOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner,
the Secondary Communication, if initiated, is interleaved between successive Primary Commun(cations. This interleaving prevents
the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from

skipping a DAC output. It is important to note that in the synchronous mode, FSR will not be asserted during Secondary
Communications.

~

TEXAS
INSTRUMENTS
5-46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
secondary OX serial communication protocol
x x I +- to TA register ~I x
x I +- to RA register ~ I
~I
x 1<- to TA' register ~ I x I <- to RA' register
~I
x 1<- to TB register -+ I x I +- to RB register
x x x x x x x x
d7 d6 d5 d4 d3 d2

0

0

d 13 and d6 are MSBs (unsigned binary)

0

1

d14 and d7 are 2's complement sign bits

1

0

d 14 and d7 are MSBs (unsigned binary)

1

1

1..-- CONTROL --.1
REGISTER

d2

~

0/1 deleteslinserts the bandpass filter

d3 ~ 0/1 disableslenables the loopback function
d4

~

d5

= 0/1

011 disableslenables the AUX IN

+ and AUX IN - pins

asynchronous/synchronous transmit and receive sections

d6

~

0/1 gain control bits (see Gain Control Section)

d7

~

011 gain control bits (see Gain Control Section)

reset function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
will initialize all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on the RESET pin will initialize the AIC registers to provide an 8-kHz AID and
D/A conversion rate for a 5.184 MHz master clock input signal. The AIC, excepting the CONTROL register,
will be initialized as follows (see AIC DX Data Word Format section):

REGISTER

INITIALIZED
REGISTER
VALUE (HEX)

TA
TA'
TB
RA
RA'
RB

9
1
24

9
1
24

The CONTROL register bits will be reset as follows (see AIC DX Data Word Format section):
d7

=

1, d6

=

1, d5

=

1, d4 = 0, d3 = 0, d2 = 1

This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the Pin Descriptions and AIC DX Word Format
sections).
The circuit shown below will provide a reset on power-up when power is applied in the sequence given
under Power-Up Sequence. The circuit depends on the power supplies' reaching their recommended values
a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC320401
TlC32041I
TLC32042

rvv';:c';:c:+1--+--+ 5 v
200 krl

0.5 J'F

L~v~C~C':-J-""'--

-5 V

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-47

TLC32040C, TLC320401, TLC32041C, TLC320411
TlC32042C, TlC320421
ANALOG INTERFACE CIRCUITS
power-up sequence
To ensure proper operation of the Ale, and as a safeguard against latch-up, it is recommmended that a
Schottky diode with a forward voltage less than or equal to 0.4 V be connected from Vee _ to ANLG
GND (see Figure 17). In the absence of such a diode, power should be applied in the following sequence:
ANLG GND and DGTL GND, Vee _, then Vee + and VDD. Also, no input signal should be applied until
after power-up.

AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 1 below.

AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1. TA register must be ~ 4 in word mode (WORD/BYTE =
2. TA register must be ~ 5 in byte mode (WORD/BYTE =
3. TA' register can be either positive, negative, or zero.
4. RA register must be ~ 4 in word mode (WORD/BYTE =
5. RA register must be ~ 5 in byte mode (WORD/BYTE =
6. RA' register can be either positive, negative, or zero.
7. (T A register ± T A' register) "must be > 1.
8. (RA register ± RA' register) must be > 1.
9. TB register must be > 1.

High).
Low).
High).
Low).

TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
IMPROPER CONDITION
T A register

+ TA' register

T A register - TA' register
TA register

+ TA' register

a or
~ a or
< a
~

Ale RESPONSE
1

Reprogram TX Counter A with T A register value

1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter
i.e., TA register

+ RA' register

~

RA register - RA' register

~

RA register

+ RA' register

~

T A register

~

RA register

a or
a or
a or

1

Reprogram RX Counter A with RA register value

1
1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A,
i.e., RA register

a or
a or

RA register

~

T A register

< 4

TA register
RA register

<
<
<

TB register

~

RB register

~

RA register

1

A.

+ TA' register + 40 HEX is loaded into TX Counter A.

+ RA'register + 40 HEX is loaded into RX Counter A.

AIC is shut down.

1

in word mode

The AIC serial port no longer operates.

5 in byte mode
4 in word mode
5 in. byte mode

a or
a or

1

Reprogram TB register with 24 HEX

1

Reprogram RB register with 24 HEX

AIC and DSP cannot communicate

Hold last DAC output

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed, This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see following diagram).

TEXAS •

INSTRUMENTS
5-48

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS

~~~~ELr~

FSX

I

~

i4-0NGOING

FSR

I

CONVERSION~

t2 - t1 "" 1/19.2 kHz

asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the. adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

u

FSX

U

I

I

Mj4f------TRANSMIT CONVERSION PERIOD------.~I

I

I

I

!4-RECEIVE CONV.~RECEIVE CONV.~
PERIOD A
PERIOD B

asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the following figure. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-49

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS

u

U
I

U

I

Lf

I

I

I+-TRANSMIT CONV.-+M-TRANSMIT CONV.-+!f-TRANSMIT CONV.~
PERIOD A
PERIOD B
PERIOD C

12

U

FSRU

I

I

14

~

RECEIVE CONVERSION PERIOD A

Lf

I
RECEIVE CONVERSION PERIOD B----I.~I

asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
The T A, TA', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).

11

n .-----, n

PRIMARY

"'l
I

SECONDARY

PRIMARY

SECONDARY

PRIMARY

SECONDARY

'-------"Lfl "'----'L

TRANSMIT
I
TRANSMIT
I
TRANSMIT
I
14~---CONVERSION----I~.----CONVERSION----t~"'----CONVERSION---~.I
PERIOD A
PERIOD B
PERIOD C

FSR

I

I

.--RECEIVE CONVERSION_-+hk~_ _ _ _ _ _ RECEIVE CONVERSION PERIOD B - - - - - -..
~
PERIOD A
.,..
.,

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V t015 V
Output voltage range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V
Digital ground voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Operating free-air temperature range:TLC32040C, TLC32041 C, TLC32042C . . . . . . . . 0 °C to 70°C
TLC320401, TLC32041I, TLC320421 . . . . . .. - 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 125°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260°C
NOTE 1: Voltage values for maximum ratings are with respect to

vee -.

TEXAS

~

INSTRUMENTS
5-50

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, Vcc + Isee Note 2)

PARAMETER

4.75

5

5.25

V

Supply voltage, V CC _ Isee Note 2)

-4.75

-5

- 5.25

V

4.75

5

5.25

V

Digital supply voltage, VDD Isee Note 2)

a

Digital ground voltage with respect to ANLG GND, DGTL GND

V

Reference input voltage, VrefLextl Isee Note 2)

2

4

V

High-level input voltage, VIH

2

VDD+O.3

V

-0.3

0.8

V

100

pF

Low-level input voltage, VIL Isee Note 3)
Load resistance at OUT + and/or OUT -, RL

(J

300

Load capacitance at OUT + and/or OUT -, CL
MSTR CLK frequency Isee Note 41

0.075

AID or D/A conversion rate
Operating free-air temperature, T A

5

10.368
± 1.5

Analog input amplifier common mode input voltage (see Note 6)

20

I TLC32040C, TLC32041 C, TLC32042C
I TLC320401, TLC320411, TLC320421

a

70

-40

85

MHz
V
kHz
°c

NOTES: 2. Voltages at analog inputs and outputs, REF, VCC +, and VCC _, are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.
4. The bandpass and low-pass switched-capacitor filter response specifications apply only when the switched-capacitor dock

frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted
by the ratio of switched-capacitor filter clock frequency to 288 kHz.
5. This range applies when (IN + - IN -lor IAUX IN + - AUX IN -) equals ± 6 V.

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-51

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range.
= - 5 V. voo = 5 V (unless otherwise noted)

vee -

vee + -

5 V.

total device. MSTR eLK frequency - 5.184 MHz. outputs not loaded
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VOO = 4.75 V, IOH = -3OOI'A

VOL

Low-level output voltage

VOO = 4.75 V, IOL= 2 mA

ICC+

Supply current from V CC +

ICC-

Supply current from VCC-

100

Supply current from VOO

Vref

Internal reference output voltage

MIN

ro

MAX

TLC3204-C

35

TLC3204_1

40

TLC3204-C

-35

TLC3204-1

-40
7

fMSTR CLK = 5.184 MHz

3.3

3

reference voltage
Output resistance at REF

UNIT
V

0.4

Temperature coefficient of internal
"'Vref

Typt

2.4

V
mA
mA
mA
V

200

ppm/·C

100

kO

receive amplifier input
Typt

MAX

AID converter offset error (filters bypassed)

25

65

mV

AID converter offset error (filters in)

25

65

mV

PARAMETER

CMRR

TEST CONDITIONS

Common-mode rejection ratio at IN +, IN -,

MIN

See Note 6

or AUX IN+, AUX INInput resistance at IN +, IN-

'I

or AUX IN+, AUX IN-, REF

UNIT

55

d8

100

kO

transmit filter output
PARAMETER

TEST CONDITIONS

MIN

Output offset voltage at OUT + or OUT VOO

(single-ended relative to ANLG GNO)
Maximum peak output voltage swing across

YOM

RL 2: 3000,

RL at OUT + or OUT - (single-ended)

Offset voltage = 0

Maximum peak output voltage swing between
YOM

OUT + and OUT - (differential output)

RL 2: 6000

t All typical values are at T A = 25 ·C.
NOTE 6: The test condition is a 0-d8m, l-kHz input signal with an 8-kHz conversion rate.

TEXAS .."
INSTRUMENTS
5-52

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Typt

MAX

15

75

UNIT
mV

±3

V

±6

V

TlC32040C, TlC320401, TlC32041C, TlC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range,
Vee - = - 5 V, voo = 5 V (unless otherwise noted) (continued)

vee +

5 V,

system distortion specifications, SCF clock frequency = 288 kHz
PARAMETER

TEST CONDITIONS

MIN

Attenuation of second harmonic of

single-ended

AID input signal

differential

Vin = -0.5dBto - 24 dB referred to V ref.
See Note 7

Attenuation of third and higher

single-ended

Yin :::: -0.5dBto - 24 dB referred to V ref,

harmonics of AID input signal

differential

See Note 7

single-ended

Vin =

DIA input signal

differential

See Note 7

Attenuation of third and higher

single-ended

harmonics of Of A input signal

differential

dB to - 24 dB referred to V ref,
Vin =
See Note 7

MAX

70
62

dB

65
70

- 0 dB to - 24 dB referred to Vref,
62

-a

dB

70
65

57

UNIT
dB

70
65

57

Attenuation of second harmonic of

Typt

dB

65

AID channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER

Av = 1*

Isee Note 7)

Ay = 2*
MIN

MAX

Ay = 4*
MIN

Vin =

- 6 dB to - O. 1 dB

58

>58§

>58§

Vin

=

-12 dB to -6 dB

58

58

>58§

Yin

=
=
=

- 18 dB to -12 dB

56

58

58

- 24 d8 to -18 dB

50

56

58

- 30 dB to -24 dB

44

50

56

- 36 dB to -30 dB

38

44

50

-42 dB to -36 dB

32

38

44

- 48 dB to -42 dB

26

32

38

- 54 dB to -48 dB

20

26

32

Vin

AID channel signal-to-distortion ratio

MAX

MIN

Vin

Yin =
Yin
Vin
Yin

=
=
=

MAX

UNIT

dB

DIA channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER

Isee Note 7)
Yin =
Yin
Yin
Yin

OJ A channel signal-to-distortion ratio

Yin
Yin

=
=
=
=
=

Yin =
Yin
Yin

t All typical values are at T A

=
=

- 6 dB to

a

dB

MIN

MAX

UNIT

58

- 12 dB to -- 6 dB

58

- 18 dB to - 12 dB

56

- 24 dB to - 18 dB

50

- 30 dB to - 24 dB

44

-36 dB to -30 dB

38

-42 dB to -36 dB

32

-48 dB to -42 dB

26

- 54 dB to - 48 dB

20

dB

=

25 DC.
+AV is the programmable gain of the input amplifier.
§A value> 58 is overrange and signal clipping occurs.
NOTE 7: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ref). The load impedance for the DAC
is 600 n.

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-53

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit gain tracking error while transmitting

- 48 dB to 0 dB signal range,

into 600!l

MIN

See Note 8
- 48 dB to 0 dB signal range,

Absolute receive gain tracking error

See Note 8
Signal input is a -0.5-dB,

Absolute gain of the AiD channel

l-kHz sinew ave
Signal input is a O-dB,

Absolute gain of the DiA channel

l-kHz sinew ave

Typt

MAX

UNIT

±0.05 ±0.15

dB

±0.05 ±0.15

dB

0.2

dB

-0.3

dB

t All typical values are at T A = 25 DC.
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).

power supply rejection and crosstalk attenuation
PARAMETER

TEST CONDITIONS
Idle channel, supply signal

VCC + or VCC _ supply voltage

f

=

0 to 30 kHz

rejection ratio, receive channel

f

=

30 kHz to 50 kHz

VCC + or Vec _ supply voltage

f

=

0 to 30 kHz

=

30 kHz to 50 kHz

f

at DR (ADC output)
Idle channel, supply signal
at OUT +

TEXAS •

POST, OFFICE BOX 655303 • DALLAS. TEXAS 75285

UNIT
dB

45
30
dB
45
80

INSTRUMENTS

MAX

30

at 200 mV p-p measured

Crosstalk attenuation, transmit-to-receive (single-ended)

5-54

Typt

at 200 mV p-p measured

rejection ratio, transmit channel

(single-ended)

MIN

dB

TLC32040C, TLC320401, TLC32041C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
delay distortion. SCF clock frequency = 288 kHz ± 2%. input (IN + - IN -) is ± 3-V sinewave
Please refer to filter response graphs for delay distortion specifications.

TLC32040 and TLC32041 bandpass filter transfer function (see curves). SCF clock
frequency = 288 kHz ± 2%. input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
PARAMETER

TEST CONDITIONS
I

Filter Gain
(see Note 10)

I

Input signal relerence is 0 dB

=
=

MIN

=

-25
-0.5

0.5
-58

TLC32042 bandpass filter transfer function (see curves!. SCF clock frequency
input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
TEST CONDITIONS
I

Filter Gain
(see Note 10)

I

Input signal relerence is 0 dB

=
=

f

=

288 kHz ±2%.
MAX

MIN

-2

170 Hz
-0.5

0.5

4 kHz

PARAMETER
Filter Gain

TEST CONDITIONS

Output signal relerence is 0 dB

-58

288 kHz ± 2% (see Note 9)

f :5 3.4 kHz
(see Note 10)

dB

-16

f 2:: 4.6 kHz

low-pass filter transfer function. SCF clock frequency

UNIT

-27

100 Hz

300 Hz :5 I :5 3.4 kHz

dB

-16

4 kHz

I 2:: 4.6 kHz

PARAMETER

UNIT

-42

170 Hz

300 Hz :5 I :5 3.4 kHz
I

MAX

100 Hz

MIN

MAX

-0.5

0.5

f = 3.6 kHz

-4

f = 4 kHz

-30

f 2:: 4.4 kHz

-5B

UNIT

dB

serial port
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH

VOL

Low-level output voltage

IOL

II

Input current

CI

Input capacitance

Co

Output capacitance

= - 3OO I'A
= 2 rnA

MIN

Typt

MAX

2.4

UNIT
V

0.4

V

±10
15

I'A
pF

15

pF

t All typical values are at T A = 25°C.
NOTES: 9. The above lilter specifications are for a switched-capacitor filter clock range of 288 kHz ± 2%. For switched-capacitor filter
clocks at frequencies other than 288 kHz ± 2 %, the filter response is shifted by the ratio of switched-capacitor lilter clock
frequency to 288 kHz.
10. The lilter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband
is measured with respect to the average gain within the passband. The passbands are 300 to 3400 Hz and 0 to 3400 Hz
lor the bandpass and lowpass lilters respectively.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-55

TLC32040C, TLC32040l. TLC32041 C, TLC32041 I
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range. Vee + = 5 V.

Vee- = -5 V. Voo = 5 V
noise (measurement includes low-pass and bandpass switched-capacitor filters)
Typt

TEST CONDITIONS

PARAMETER

single-ended
Transmit noise

MAX

200
OX input = 00000000000000, constant input code

differential

300

500

p.V rms

475

p,V rms

20

Receive noise Isee Note 11)

300

Inputs grounded, gain = 1

UNIT

p.V rms
dBrncO

20

dBrncO

timing requirements
serial port recommended input signals
PARAMETER

MAX

MIN

95

UNIT

tcIMCLK)

Master clock cycle time

trIMCLK)

Master clock rise time

10

ns

tIlMCLK)

Master clock fall time

10

ns

Master clock duty cycle

42%

RESET pulse duration Isee Note 12)
tsu[QXl

DX setup time before SCLK.

thJDXJ

DX hold time after SCLK.

NOTES:

ns

58%

800

ns

20

ns

t cLSCLI<:1I4

ns

11. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be
correspondingly reduced. The noise is computed by statistically evaluating the digital output of the AID converter.
12. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached
their recommended values.

serial port-AIC output signals. CL

30 pF for SHIFT CLK output. CL

1 5 pF for all other outputs
Typt

MAX

Shift clock ISCLK) fall time

(3

8

ns

Shift clock ISCLK) rise time

3

8

ns

PARAMETER

tclSCLKl

Shift clock ISCLK) cycle time

tflSCLKl
trlSCLKl

MIN

380

Shift clock ISCLK) duty cycle

UNIT

ns

45

55

tdICH-FLl

Delay from SCLKI to FSR/FSX/FSDf

30

tdICH-FHl

Delay from SCLKI to FSR/FSX/FSDI

35

tdICH-DRl

DR valid after SCLKI

tdwICH-ELl

%
ns

90

ns
ns

Delay from SCLKI to EODX/EODR> in word mode

90
gO

tdwiCH-EHl

Delay from SCLKI to EODX/EODRI in word mode

90

ns

tflEODXl

EODX fall time

2

8

ns

tIlEODR)

EODR fall time

2

8

ns

tdbICH-ELI

Delay from SCLKI to EODX/EODR> in byte mode

90

ns

tdbICH-EH)

Delay from SCLKI to EODX/EODRt in byte mode

90

ns

td'MH-SLI

Delay from MSTR CLKI to SCLKf

65

170

ns

tdIMH-SHI

Delay from MSTR CLKt to SCLKI

65

170

ns

tTypical values are at T A

=

25°C.

TEXAS

~

INSTRUMENTS
5-56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ns

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range.
Vee - = - 5 V. Vee = 5 V (continued)
serial port -

Vee + = 5 V.

AIC output signals
PARAMETER

TEST CONDITIONS

MIN

Typt

MAX

UNIT

tcISCLK)

Shift clock ISCLK) cycle time

tf(SCLK)

Shift clock ISCLK) fall time

50

ns

trISCLK)

Shift clock ISCLK) rise time

50

ns

380

Shift clock ISCLK) duty cycle

ns

45

=
=

55

%

50 pF

52

ns

50 pF

tdICH-FL)

Delay from SCLKt to FSR/FSXI

CL

tdICH-FH)

Delay from SCLKt to FSR/FSXt

CL

52

ns

tdICH-DR)

DR valid after SCLK t

90

ns

tdw(CH-EL)

Delay from SCLKt to EODX/EODRI in word mode

90

ns

tdwICH-EH)

Delay from SCLKt to EODX/EODRt in word mode

90

ns

tf(EODX)

EODX fall time

15

ns

tf(EODR)

EODR fall time

15

ns

tdbICH-EL)

Delay from SCLKt to EODX/EODRI in byte mode

100

ns

tdbICH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

100

td(MH-SL)

Delay from MSTR CLKt to SCLKI

65

ns

tdIMH-SH)

Delay from MSTR CLKt to SCLKt

65

ns

tTypieal values are at T A

=

ns

25°C.

TABLE 2. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL-SCALE AID CONVERSION)
CONTROL REGISTER BITS

INPUT CONFIGURATIONS
Differential configuration
Analog input = IN + - IN= AUX IN + - AUX IN Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN + - ANLG GND

d6

d7

1
0
1
0
1
0
1
0

1
0
0
1
1
0
0
1

ANALOG INPUTt

AID CONVERSION
RESULT

±6 V

full-scale

+3 V
+ 1.5 V
±3 V

full-scale
full-scale
half-scale

±3 V
± 1.5 V

full-scale
full-scale

:t In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input
not exceed 0.1 dB below full scale.
RIb

R
IN+---v.._ _-I

h-..--

R

IN - -JV\~'--f

~

R
AUX IN + ---v.._e--f
TO MUX

1-:-"-_

R

AUX IN--JV\_ _-t

~

TO MUX

Rib

Rfb

RIb = R for d6 = 1, d7 = 1
d6 = 0, d7 = 0
Rib = 2R for d6 = 1, d7 =
Rib = 4R lor d6 = 0, d7 = 1

RIb = R lor d6 = 1, d7 = 1
d6 = 0, d7 = 0
Rib = 2R lor d6 = 1, d7 = 0
Rib = 4R lor d6 = 0, d7 = 1

°

FIGURE 1. IN + AND IN - GAIN
CONTROL CIRCUITRY

FIGURE 2. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-57

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
sin xIx correction section
The AIC does not have sin xIx correction circuitry after the digital-to-analog converter. Sin xIx correction
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The
results, which are shown below, are typical of the numerical correction accuracy that can be achieved
for sample rates of interest. The filter requires only seven instruction cycles per sample on the
TMS320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor
of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction will add a
slight amount of group delay at the upper edge of the 300-3000-Hz band.

sin xIx roll-off for a zero-order hold function
The sin xIx roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.

TABLE 3. sin xIx ROLL-OFF

ts (Hz)

sin" t/fs
20 109 - - " tIts
(t = 3000 Hz)
(dB)

-2.64

7200
8000

-2.11
-1.44
-0.63
-0.35

9600
14400
19200

Note that the actual AIC sin xIx roll-off will be slightly less than the above figures, because the AIC has
less than a 100-% duty cycle hold interval.

correction filter
To compensate for the sin xIx roll-off of the AIC, a first-order correction filter shown below, is recommended.

U{i+

11

} - - - - - - - - - - _ . - - + Y { i + 11

p1

The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =

p22 (1-p1)2
1 - 2p1 cos(2 7r f/fs) + p1 2

TEXAS

-III

INSTRUMENTS
5-58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
correction results
Table 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and
9600-Hz sampling rates.

TABLE 4

t (Hz)

300
600

ERROR (dB)

ERROR (dB)

ts = 8000 Hz
p1 - -0.14813
p2 = 0.9888
-0.099
-0.089

ts - 9600 Hz
p1 = -0.1307
p2 = 0.9951
-0.043
-0.043

900
1200
1500
1800

-0.054
-0.002
0.041
0.079

0
0
0
0.043

2100
2400
2700
3000

0.100
0.091
-0.043
-0.102

0.043
0.043
0
-0.043

TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = klY +k2U
where k 1 equals p 1 (from the preceding page), k2 equals (1 - p 1 )p2 (from the preceding page), Y is the
filter state, and U is the next I/O sample. The coefficients k 1 and k2 must be represented as 16-bit integers.
The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the
TMS320 processor page pointer and memory configuration are properly initialized, the equation can be
executed in seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dma), (shift)

TEXAS

"'!1

INSTRUMENTS
POST OFFlCE BOX 655303 • DALLAS, TEXAS 75265

5-59

TLC32040C, TLC320401, TLC32041 C, TLC320411
TlC32042C, TlC320421
ANALOG INTERFACE CIRCUITS
byte-mode timing
~re-tr(SClK)

-4trt- t f(SClK)
SHIFT ClK

1

I OB v
td(CH-Fl)~ ~
_ _---.

FSR,

1
1

I

I

1 4i

DR _ _

I

1
td(CH-FHf-toI 14-

I'

08V,"",1---1/.1-'_ _ _ _ _ _

I
:

~ ~d(CH-DR)

~

I

I

~h(~~~~I~
_ _O~O~N~'~T~C~A~R~E_ _~~J(~~
~~
08
07
06~
1

______-I
__I.-_t-;h(DX)
~ ~tdb(CH-El)
tdb(CH-EH~ ItEOOX
,·~----~t~~O~.B~V~_____________-7,r.____________J~

word-mode timing
I4---*tc (SClK)
SHIFT ClK

1I

-+i

OB vI

r-td(CH-Fl)

:

l

I
I

-------.t
FSX, FSR
v
DR _ _

,

1

1

1

OB v

O.B v

2V

'

:

td(CH-FH)-+\

~

r __________~'ll~·2~v~------

i,
f1
: --+I ~td(CH-DR)

0.8

:

~D~'~5_~~~~D_'_ _D_0_l:--+_-----

i

tsu(DX)~ I+-1

DX----~D).,~5iY~41"D~,~31r~~iD1
1

-+i

DON'T CARE

I

1

1

14- th(DX)

I

tdw(CH-El~ 14- -+I I4-tdw(CH-EH)
------------------~~~'--------~LJ'

EODX, EODR

O.B v

2V

shift-clock timing
MSTR ClK

I

td(MH-SH)

-l4-"i

14--+1- td(MH-Sl)

SHIFT ClK _ _ _ _ _ _ _- J t : - - - - - - - - - - . . . . , X " ' I_ _ _ _ _ _ __

FIGURE 3. SERIAL PORT TIMING

~

TEXAS
INSTRUMENTS
5-60

~I~

~0~'~5___~~~~---D-8-------~~~0-'--0-0-1~--~
1
I
tsu(DX)~

EOOR,

I

v I I
-41i4-td(CH-FH)
~ IHd(CH-Fl)
I",':-:-:-_ _ _ _ _ _ _"'\1

~<.:~O;;.::.B,-,v_-II_j...:--j:~:_ _ _ _-ft2V

FSX

OX

0.8

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TlC32040C, TlC320401, TlC32041 C, TlC320411
TlC32042C, TlC320421
ANALOG INTERFACE CIRCUITS
TMS32010
SN74LS299

r

I

OEN

L

QH

G1
A

A1/PA1

B

A2/PA2

C

so

Y1 YO

\

A-H
\

00-015

Sl
'----

QH

G2
SO CLK
G1

00-07

00-015

A-H
\

-----f----Lt--

SR

TLC32040/
TLC32041/
TLC32042
SHIFTCLK

SN74LS299

D-U
CLKOUT
INT

ox

CLK< -

G1

08-015

SN74LS138

~

G-

G2

AO/PAD

WE

Sl

FSX

C2

\

SR

"--1>=0
--

-

~
Q

C1
10

r~

DR

MSTR CLK
EO OX

FIGURE 4. TMS32010-TLC32040/TLC32041/TLC32042 INTERFACE CIRCUIT

in instruction timing
ClK OUT

50, G1
00-015

(
VAllO
)
----------------------(~~~~!~------------------------------------

out instruction timing
ClKOUT _ _ _~

SN74l5138 Y1

5N74l5299 ClK
00·015

--------------------~{=~V~A~LI~O:::)>-------------------------------­
FIGURE 5. TMS32010-TLC32040/TLC32041!TLC32042 INTERFACE TIMING

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-61

TLC32040C, TLC320401, TLC32041 C, TLC32041I
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC TRANSMIT CHANNEL FILTER
10

0.3

~ag~itud~

0
-10
-20
a:I

"0

.,I
a
'c
"0

..

01

:!

Group Delay

-30

(\

-50

-70

j
~

-80

-90

o

\~
r-

::-::~

/
1 \./

E
I

Qj

0

\

0

c.

'0"

~

.,

..

0.05 .~

Qj

-f-S~e N~te

d

2

3

0.1

V

a::

0.15
0.2

4

5

SCF clock frequency
288 kHz

Maximum relative delay (0 Hz to 600 Hz) = 125 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
Absolute delay (600 Hz to 3000 Hz) = 700 !'s.
Test conditions are Vee +, Vee _, and Voo within recommended operating conditions, SeF clock f
input = ± 3-V sinewave, and T A = 25°C.

FIGURE 6

-1.!1

TEXAS
INSTRUMENTS
5-62

..

0.05

--;--See Note A

Normalized Frequency-kHz x
NOTES: A.
B.
C.
O.

.,

0.15
0.1

\

~

0.2

>

\

See Note B,

-40

-60

0.25

\

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=

288 kHz ± 2%,

TLC32040C. TLC320401. TLC32041 C. TLC320411
TLC32042C. TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
TLC32040 and TLC32041
RECEIVE CHANNEL FILTER
10

See Note A

M

0

0.35

. I

agnltude

0.3
0.25

-10

\

-20
IXI
't:l

..
E
..'"
I

't:l

-30
-40

~

\ / \ 1\
V /\ V

-70

L S,ee

-80

Note B

0

2

Normalized Frequency-kHz x

0.1
0.05
0

\~
y

1\

0.05

3

'"
E

.

I
>-

0;

0

c-

:I
0

c:;
.,

.,

.::

0;

a:

0.1

\

See Note C-

-90

0.15

\
\

Group Delay

-50
-60

NOTES: A.
B.
C.
O.

\

,

'2

0.2

0.15
4

5

SCF clock frequency
288 kHz

Maximum relative delay 1200 Hz to 600 Hz) = 3350 p.s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 p.S.
Absolute delay (600 Hz to 3000 Hz) = 1230 P.s
Test conditions are VCC +, VCC _. and VOO within recommended operating conditions, SCF clock f
input = ± 3-V sinewave, and T A = 25°C.

=

288 kHz ± 2%,

FIGURE 7

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

5-63

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
TLC32042
RECEIVE CHANNEL FILTER
10

0.3

Ma~nitu~e
Se~ No~e A

0
-10

0.25
0.2

\

-20
tel
"0

I

-30

\

Q)

"0

a

-40

Group Delay

Cl

-50

J

'",

:2:'"

\

T

.., 1. J

-60 --See Nr e

i

0.15
0.1

.\

0.05

\

'\~

0

\

"\

-70

0.05
0.1

'"
E
I
>
co

Qj

Cl
c.
::l
0

c:;
.:::'"

"'

Qj

a:

See Note C

0.15

-80
-90
0

2

Normalized Frequency-kHz x
NOTES:

A.
B.
C.
D.

4

3

0.2

SCF clock frequency
288 kHz

Maximum relative delay (200 Hz. to 600 Hz) = 3350 p.S.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ps.
Absolute delay (600 Hz to 3000 Hz) = 1080 ps.
Test conditions are VCC +. Vec _. and VDD within recommended operating conditions. SCF clock f
input = .± 3-V sinewave, and T A = 25°C.

FIGURE 8

~

TEXAS
INSTRUMENTS
5--64

5

POST oFFice BOX 655303 • DALLAS, TeXAS 75265

=

288 kHz ± 2%,

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)

AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL

80
70

GAIN 1- 4X

III
"'C

I 60
.9
1;j

lC

0.5

l-kHz input signal with an
8-kHz conversion rate

f--...

i/'

0.3

GAIN - lX-

/' V

50

~ 40

0.2

III
"'C

I

/'

c:
.9

l-kHz input signal

0.4 8-kHz conversion rate

CI>

0.1

:i
..,

0

c:

~

1ii

- -

..-

c: -0.1

is 30

$

'0;
(!1

OJ

-0.2

§, 20
-0.3

iii
10

-0.4

o

- 50

- 40

- 30

- 20

- 10

o

-0.5
-50

10

-40

Input Signal Relative to Vref-dB

FIGURE 9

DIA GAIN TRACKING

vs
INPUT SIGNAL

vs
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)

l-kHz input signal into 600

{J

80

1.0

-

70

V

lC

c: 60

/

0

"f 50
B

is 40

"'---~-~--~:-::-::--::T--~-,

l-kHz input signal into 600

{J

0.4

,1"

0.2 I---+---+---I----+---+--~

c:

..,

Ol---+----~----r_--_+----~-~

~

~

I-~-+---+---I---+---+--~

III
"'C

:i

~ - 0.2 I---+---+---I----+---+--~

OJ 30
c:
CI>
iii 20

'0;
(!1

10

o

10

0.6~---+----+---_+----+----+--~

,//

III

-50

o

0.8 8-kHz conversion rate

I

0

-10

FIGURE 10

90 8-kHz conversion rate

...

-20

DIA CONVERTER SIGNAL-TO-DISTORTION RATIO

100

III
"'C

-30

Input Signal Relative to Vref-dB

-40

-30

-20

-10

0

10

0.4

1----+----+----+----+----+---1

- 0.6

~--+----+----+---+----+--~

- 0.8

I---+---f---+---+--+---J

_

-1

Input Signal Relative to Vref-dB

L-_-L_~

-50

-40

_ _~_~_ _~_~

-30

-20

-10

o

10

Input Signal Relative to V ref - dB

FIGURE 11

FIGURE 12
NOTE: Test conditions are Vee +. Vee _. and VOO within recommended operating conditions set clock f = 288 kHz ± 2%. and T A = 25°e.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-65

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
ATTENUATION OF SECOND HARMONIC OF AID INPUT
vs
INPUT SIGNAL
100
al

90

'c"0

80

"I

100

f\

70

E
iii
:r:

V--

I
II

~

'-

/'

I:
0

1-kHz input signal
90 8-kHz conversion rate

"I

80

o

70

E

:r:'" 60
"E

50

f0-

:c

50

40

e

40

fJ)

'0

al

'c"

60

"
"'"

ATTENUATION OF THIRD HARMONIC OF AID INPUT
vs
INPUT SIGNAL

o

30

'g

30

20

~

"

20

III

I:

:J

I:

~

;(

10

o

~ ~

"

I:

I:

.g

./rv

;(
10

1-kHz input signal
8-kHz conversion rate

o

Input Signal Relative to V ref - dB

- 40
- 30
- 20
- 10
o
Input Signal Relative to V ref - dB

FIGURE 13

FIGURE 14

ATTENUATION OF SECOND HARMONIC OF DIA INPUT

ATTENUATION OF THIRD HARMONIC OF DIA INPUT
vs
INPUT SIGNAL

-50

-40

-30

-20

-10

o

vs

INPUT SIGNAL
._-

100
al

"I

'c"0

E

1-kHz input signal into 600
90 B-kHz conversion rate

"0
"'"

al

----

70

,/'"

"I

--

'c"0

E

:cf0-

50

fJ)

0
I:

e

40

c:

0
.;;

.2 30

"'c:"
'"
~

10

"
~
I:

;(

20

i

10

o

- 50

- 40

- 30

- 20

- 10

o

1-kHz input signal into 600
90 8-kHz conversion rate

10

10

n

80
70

./

:r:'" 60
"E

I:

-

100

n

80

:r:'" 60

- 50

10

----

I

50

40
30

'-

20
10

o

- 50

- 40

- 30

- 20

- 10

o

Input Signal Relative to V ref - dB

Input Signal Relative to V ref - dB

FIGURE 15

FIGURE 16

NOTE: Test conditions are VCC +, VCC _, and VDD within recommended operating conditions set clock f = 288 kHz ± 2%, and TA

~

TEXAS
INSTRUMENTS
5-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

= 25 cc.

TLC32040C, TLC320401, TLC32041 C, TLC320411
TLC32042C, TLC320421
ANALOG INTERFACE CIRCUITS
TYPICAL APPLICATION INFORMATION
TMS32020/C25

TLC32040/TlC32041/TlC32042

ClKOUT t--f----i MSTR ClK
FSX I - - - f - - I FSX
OX 1----1_-1 OX
FSR t--f----i FSR
ORI--_f--I DR

+5 V

VCC+
REF
ANlG GNO

C

VCC-

ClKR t -....----i SHIFT ClK

VOO

ClKX
OGTL GNO

C = 0.2

~F,

CERAMIC

FIGURE 17, AIC INTERFACE TO THE TMS32020/C25 SHOWING DECOUPLING CAPACITORS
AND SCHOTTKY DIODEt
VCC

R

. - - - . - - - - - . . - -......-

Tl431'A--......

FOR:

VCC
VCC
VCC

=
=

=

3.0 V OUTPUT

0.1

~F

CERAMIC

12 V, R = 7200 \l
10 V, R = 5600 n
5 V, R = 1600 n

FIGURE 18, EXTERNAL REFERENCE CIRCUIT FOR TLC32041
tThomson Semiconductors

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 - DALLAS, TEXAS 75265

5-67

TLC32044C, TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS
D3098, MARCH 1988-REVISED MAY 1991

•

Advanced linCMOS'" Silicon-Gate Process
Technology

•

14-Bit Dynamic Range ADC and DAC

•

16-Bit Dynamic Range Input with
Programmable Gain

•

Variable ADC and DAC Sampling Rate Up to
19,200 Samples per Second

•

Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter

•

Serial Port for Direct Interface to
TMS320C17, TMS32020, TMS320C25,
and TMS320C30 Digital Processors

•

Synchronous or Asynchronous ADC and
DAC Conversion Rates with Programmable
Incremental ADC and DAC Conversion
Timing Adjustments

•

•

•

N PACKAGE
(TOP VIEW)

NU
RESET
EODR
FSR
DR
MSTR ClK
VDD
REF
DGTL GND
SHIFT ClK
EODX
DX
WORD/BYTE
FSX

'-i..._ _...r-'

Vcc +
VCC
ANlG GND
ANlG GND
NU
NU

FN PACKAGE
(TOP VIEW)

I~ I§ Ii ~ ~ ~ ~

Serial Port Interface to SN74299 Serial-toParallel Shift Register for Parallel Interface
to TMS32010, TMS320C15, or Other
Digital Processors

432

DR
MSTR ClK

Internal Reference for Normal Operation and
External Purposes, or Can Be Overridden by
External Reference

VDD
REF
DGTl GND
SHIFT ClK
EODX

600-mil Wide N Package (CL to CLI

description
The TLC32044 is a complete analog-to-digital
and digital-to-analog input/output system on a
single monolithic CMOS chip. This device
integrates a bandpass switched-capacitor
antialiasing input filter, a 14-bit-resolution A/D
converter, four microprocessor-compatible serial
port modes, a 14-bit-resolution D/A converter,
and a low-pass switched-capacitor outputreconstruction filter. The device offers numerous
combinations of Master Clock input frequencies
and conversion/sampling rates, which can be
changed via digital processor control.

NU
NU
IN +
IN·
AUX IN +
AUX IN
OUT+
OUT··

1 282726
25
24
23
22
21
20
11
19
12131415161718

5
6
7
8
9
10

XI~IX
Cl>-~ z

INAUX IN +
AUX INOUT+
OUTVcc+
Vcc-

::> ::>ClCl

ZZZ

(3

CJCJ
CJCJ
-' -'

0

 1.
(RA register ± RA' register) must be > 1.
TB register must be > 1.

High).
Low).
High).
Low).

TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
IMPROPER CONDITION
T A register

+ T A' register = 0 or 1

T A register - T A' register

=

AIC RESPONSE
Reprogram TX Counter A with TA register value

0 or 1

T A register

+ T A' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A.

RA register

+ RA' register = 0 or 1

Reprogram RX Counter A with RA register value

i.e., TA register
RA register - RA' register

=

0 or 1

RA register

+ RA' register = 0 or 1

TA register

=
=

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A.
i.e .. RA register

RA register

+ TA' register + 40 HEX is loaded into TX Counter A.

0 or 1

+ RA' register + 40 HEX is loaded into RX Counter A.

AIC is shut down.

0 or 1

T A register < 4 in word mode

The AIC serial port no longer operates.

T A register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
TB register
RB register

=
=

0 or 1

Reprogram TB register with 24 HEX

0 or 1

Reprogram RB register with 24 HEX

Ale and DSP cannot communicate

Hold last DAC output

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see following diagram).

TEXAS •

INSTRUMENTS
POST OfFICE BOX 655303 • DALLAS. TEXAS 75265

5-81

TLC32044C. TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

~~~~ELr~
FSX

I

~:R

If-ONGOING CONVERSION-.!

I

t2 - t1 ;,: 1/19.2 kHz

asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

u

FSX

U

I

I

MIIII-----TRANSMIT CONVERSION PERIOD-----...,.~I

FSR

I

I

I

!f--RECEIVE CONV.~RECEIVE CONV.~
PERIOD A
PERIOD B

asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the following figure. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.

~

TEXAS
INSTRUMENTS
5-82

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

FSX

u

J

u
I

Lf

U

I

I

I

i+-TRANSMIT CONV ...... TRANSMIT CONV.-+j4-TRANSMIT CONV.~
PERIOD A
PERIOD B
PERIOD C

'2

U

FSRU

I

I

14

~

RECEIVE CONVERSION PERIOD A

Lf

I
RECEIVE CONVERSION PERIOD B----J~~I

asynchronous operation - more than one set of primary and secondary OX serial communication
occurring between two receive frame sync (see Ale OX Data Word Format section)
The T A, T A', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).
'1
PRIMARY

SECONDARY

PRIMARY

FSXl----...n~
I

I

TRANSMIT

n

SECONDARY

TRANSMIT
1414----CONVERSION----~---­
CONVERSION
~~
PERIOD A
PERIOD B

PRIMARY

SECONDARY

Ul
I

~III

TRANSMIT
CONVERSION
PERIOD C

L

I
~

'2
FSR

""--- RECEIVE CONVERSION
...-PERIOD A
-

I

I

......
~M------- RECEIVE CONVERSION PERIOD B - - - - - -..
~I

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-83

TLC32044C. TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS
test modest
The following paragraph provides information that allows the TLC32044 to be operated in special test
modes. These test modes are used by Texas Instruments to facilitate testing of the device during
manufacturing. They are not intended to be used in real applications, however, they allow the filters in
the AID and DIA paths to be used without using the AID and DIA converters.
In normal operation, the non usable (NU) pins are left unconnected. These NU pins are used by the factory
to speed up testing of the TLC32044 Analog Interface Circuit (AIC). When the device is used in normal
(non-test-mode) operation, the NU pin (pin 1) has an internal pull-down to - 5 V. Externally connecting
o V or 5 V to pin 1 puts the device in test-mode operation. Selecting one of the possible test modes is
accomplished by placing a particular voltage on certain pins. A description of these modes is provided
in Table 2 and Figures 1 and 2.
TABLE 2. LIST OF TEST MODES
TEST

DIA PATH TEST (PIN 1 to 5 V)

PINS

TEST FUNCTION

5
11
3
27 and 28

AID PATH TEST (PIN 1 to 0)
TEST FUNCTION

The low-pass switched-capacitor filter clock is brought

The bandpass switched-capacitor filter clock is brought

out to pin 5. This clock signal is normally internal.

out to pin 5. This clock Signal is normally internal.

No change from normal operation. The EODX signal is

The pulse that initiates the AID conversion is brought

brought out to pin 11.

out here. This signal is normally internal.

The pulse that initiates the 01 A conversion is brought

No change from normal operation. The EODR signal is

out here.

brought out.

There are no test output signals provided on these pins.

The outputs of the AID path low-pass or bandpass filter
(depending upon control bit d2 -

see AIC DX Data

Word Format section) are brought out to these pins. If
the high-pass section is inserted, the output will have a
(sinx)/x droop. The slope of the droop will be determined

by the ADC sampling frequency, which is the high-pass
section clock frequency (see diagram of bandpass or
low-pass filter test for receive section). These outputs
will drive small (30-pF) loads.
DIA PATH LOW-PASS FILTER TEST; PIN 13 (WORD/BYTE) to -5 V
TEST FUNCTION
15 and 16

The inputs of the DIA path low-pass filter are brought out to pins 15 and 16. The D/A input to this filter is removed.
If the (sin xl/x correction filter is inserted, the OUT + and OUT - signals will have a flat response (see Figure 2). The
common-mode range of these inputs must not exceed ± 0.5 V.

t In the test mode, the AIC responds to the setting of Pin 13 to - 5 V, as if Pin 13 were set to 0 V. Thus, the byte mode is selected
for communicating between DSP and AIC. Either of the path tests (D/A or AID) can be performed simultaneously with the DIA low-pass
filter test. In this situation, Pin 13 must be connected to - 5 V, which initiates byte-mode communications.

TEXAS

~

INSTRUMENTS
5-84

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

PIN 27 (POSITIVE)'
PIN 28 (NEGATlVE)t

I+ +

TEST CONTROL
(PIN 1 AT 0 V)

TEST

FILTER

r--

1
~

~

v

.~

M
U

AID

X

r--

~

'--

~

t---

•

FIGURE 1. BANDPASS OR LOW-PASS FILTER TEST FOR RECEIVER SECTION
FILTER

M

M
U
X

(Sin xlix
CORRECTION

U
X

TEST CONTROL
13 at -5 V)

.....,r-,-..... - - (PIN
PIN 16 (POSITIVEI.
PIN 15 (NEGATIVE)t

FIGURE 2. LOW-PASS FILTER TEST FOR TRANSMIT SECTION
t All analog signal paths have differential architecture and hence have positive and negative components.

..Jj}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5--85

TLC32044C, TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vcc+ (see Note 1)
-0.3 V to 15 V
Supply voltage range, VDD
- 0.3 V to 15 V
Output voltage range, Vo ..
-0.3 V to 15 V
Input voltage range, VI ....
- 0.3 V to 15 V
Digital ground voltage range.
- 0.3 V to 15 V
Operating free-air temperature range: TLC32044C ...................... . . . .. ooC to 70°C
TLC320441
- 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 125°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . .
260°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: N package ............ 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC - .

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, VCC + Isee Note 2)

PARAMETER

4.75

5

5.25

V

Supply voltage, VCC- (see Note 2)

-4.75

-5

-5.25

V

4.75

5

5.25

V

2

4

V

2

VOO+O.3

V

-0.3

0.8

V

100

pF

Digital supply voltage, VDD Isee Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GNO
Reference input voltage, V reflext) Isee Note 2)
High-level input voltage, VIH
Low-level input voltage, VIL (see Note 3)
Load resistance at OUT + and/or OUT -, RL

300

!l

Load capacitance at OUT + and/or OUT -, CL
MSTR CLK frequency Isee Note 4)

0.075

Analog input amplifier common mode. input voltage (see Note 5)

10.368
20

I TLC32044C
I TLC320441

Operating free-air temperature, T A

0

70

-40

85

MHz
V
kHz
DC

2. Voltages at analog inputs and outputs, REF, VCC +, and VCC _, are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.
4. The bandpass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and
the high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the low-pass roll-off frequency
will shift by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF clock is shifted from 8 kHz, the high-pass
roll-off frequency will shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter
ISCF) specifications apply only when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off
frequency will shift by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN + - IN -) or (AUX IN + - AUX IN -) equals ± 6 V.

TEXAS •
INSTRUMENTS
5-86

5

± 1.5

A/D or O/A conversion rate

NDTES:

V

0

POST OFFICE BOX 655303 • DALLAS. TI,:XAS 75265

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

electrical characteristics over recommended operating free-air temperature range. Vee +
Vee- = -5 V. Voo = 5 V (unless otherwise noted)
total device. MSTR elK frequency

5.184 MHz. outputs not loaded

=

PARAMETER
VOH

High·level output voltage

VOL

Low·level output voltage

ICC+ Supply current from Vce +
ICC- Supply current from V CC _

TEST CONDITIONS
VOO
VOO

~

4.75 V, IOH

~

~

4.75 V, IOL

~

-300 JlA

MIN

35
40
-35

TLC320441

Internal reference output voltage

-40
fMSTR CLK ~ 5.184 MHz

7

ro

3.3

3

Temperature coefficient of
internal reference voltage

Output resistance at REF

UNIT
V

TLC32044C

Vref

MAX
0.4

2 mA

TLC320441

Supply current from VOD

aYref

Typt

2.4

TLC32044C

100

5 V.

V
mA
mA
mA
V

200

ppm/DC

100

kn

receive amplifier input
PARAMETER

TEST CONDITIONS

MIN

AID converter offset error (filters in)

CMRR
ri

Common-mode rejection ratio at IN +, IN - ,

See Note 6

or AUX IN+, AUX INInput resistance at IN +, INor AUX IN+, AUX IN-, REF

Typt

MAX

10

70

UNIT
mY

55

dB

100

kn

transmit filter output
PARAMETER

TEST CONDITIONS

MIN

Output offset voltage at OUT + or OUT VOO

(single·ended relative to ANLG GND)
Maximum peak output voltage swing across

YOM

RL'2: 300 n,

RL at OUT + or OUT - (single'ended)

Offset voltage

Maximum peak output voltage swing between
YOM

RL '2: 600

OUT + and OUT - (differential output)

~

0

n

Typt

MAX

15

80

UNIT
mV

±3

V

±6

V

t All typical values are at TA ~ 25°C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with an 8-kHz conversion rate.

TEXAS

-'!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-87

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

electrical characteristics over recommended operating free-air temperature range,
Vee - = - 5 V, voo = 5 V (unless otherwise noted)

Vee +

5

V,

system distortion specifications, SCF clock frequency = 288 kHz
PARAMETER

TEST CONDITIONS

Attenuation of second harmonic of

single-ended

AID input signal

differential

Attenuation of third and higher

single-ended

harmonics of AID input signal

differential

Attenuation of second harmonic of

single-ended

DIA input signal

differential

Attenuation of third and higher

single-ended

harmonics of D/A input signal

differential

MIN

Vin = -0.5 dB to - 24 dB referred to Vref,
See Note 7

Typt

MAX

70
62

Vin = -0.5 dB to -24 dB referred to Vref,
See Note 7

57

Vin = - 0 dB to - 24 dB referred to Vref,
See Note 7

62

Vin = -0 dB to -24 dB referred to Vref,
See Note 7

57

UNIT
dB

70
65

dB

65
70

dB

70
65

dB

65

AID channel signal-to-distortion ratio
PARAMETER

(see Note 7)
-6 dBto -0.1 dB

Vin =

AID channel signal-to-distortion ratio

Ay - 1~
MIN
MAX

TEST CONDITIONS

58

Ay - 2~
MIN MAX
>58§

Ay - 4~
MIN
MAX
>58§

Vin = -12 dB to - 6 dB
Vin = -18 dB to -12 dB

58

58

>58§

56

58

58

Vin = - 24 dB to - 18 dB
Vin = - 30 dB to - 24 dB

50

56

58

44

50

56

Vin = - 36 dB to - 30 dB
Vin = - 42 dB to - 36 dB

38

44

50

32

38

44

Vin = -48 dB to -42 dB
Vin = - 54 dB to - 4B dB

26

32

38

20

26

32

UNIT

dB

t All typical values are at T A = 25°C.
*Av is the programmable gain of the input amplifier.
§A value >60 is over range and signal clipping occurs.

DIA channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER

(see Note 7)
Vin = -6 dB to 0 dB
Vin = -12 dB to - 6 dB
Vin = - 18 dB to -12 dB

MAX

UNIT

58
58
56

- 24 dB to - 18 dB

50

Vin = - 30 dB to - 24 dB
Vin = -36dBto -30dB

44

Vin = -42 dB to -36 dB
Vin = -48 dB to -42 dB

32

Vin = - 54 dB to - 48 dB

20

Vin

DIA channel signal-to-distortion ratio

=

MIN

dB

38
26

NOTE 7: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC
is 600 Il.

TEXAS

~

INSTRUMENTS
5-88

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS

electrical characteristics over recommended operating free-air temperature range, Vee +
vee- = -5 V, voo = 5 V (unless otherwise noted) (continued)

5 V,

gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit gain tracking error while transmitting

- 48 dB to 0 dB signal range,

into 600

n

MIN

See Note 8
- 48 dB to 0 dB signal range,

Absolute receive gain tracking error

See Note 8
Signal input is a - O. 5-dB,

Absolute gain 01 the AID channel

1-kHz sinew ave
Signal input is a O-dB,

Absolute gain 01 the DIA channel

1 ~kHz sinew ave

Typt

MAX

UNIT

±0.05 ±0.15

dB

±0.05 ±0.15

dB

0.2

dB

-0.3

dB

power supply rejection and crosstalk attenuation
PARAMETER

TEST CONDITIONS
Idle channel, supply signal

VCC+ or VCC- supply voltage

I

=

0 to 30 kHz

rejection ratio, receive channel

I

=

30 kHz to 50 kHz

I

=

0 to 30 kHz

VCC + or VCC _ supply voltage

Typt

at DR IADC output)
Idle channel, supply signal

=

30 kHz to 50 kHz

at OUT +

Crosstalk attenuation, transmit-to-receive Isingle-ended)

UNIT
dB

45
30

at 200 m V POp measured

I

MAX

30

at 200 mV POp measured

rejection ratio, transmit channel
Isingle-ended)

MIN

dB
45
80

dB

t All typical values are at T A = 25°C.
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB 10 db relative to V rei).

TEXAS •

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5-89

TLC32044C. TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

delay distortion
bandpass filter transfer function, SCF fclock
PARAMETER

TEST CONDITION

288 kHz IN +

FREQUENCY RANGE
I ,,; 50 Hz
I
I

Input signal

Filter gain

relerence to 0 dB

I
I
I
I

=
=
=
=
=
=

MAX

-29

-25

100 Hz

Kl x - 0.26 dB

-4

-2

-1

1 50 Hz to 3100 Hz

Kl x 0 dB

-0.25

0

0.25

3100 Hz to 3300 Hz

Kl x 0 dB

-0.3

0

0.3

3300 Hz to 3650 Hz

K1 x 0 dB

-0.5

0

0.5

3BOO Hz

K1 x 2.3 dB

-5

-3

-1

-20

-17

-16

Kl x 2.7 dB
Kl x 3.2dB

-40

I ;,: 5000 Hz

K1 x 0 dB

-65

MIN

TYP§

MAX

Kl x 0 dB

-0.25

0

0.25

3100 Hz to 3300 Hz

K1 x 0 dB

-0.3

0

0.3

3300 Hz to 3650 Hz

K1 x 0 dB

-0.5

0

0.5

3800 Hz'

Kl x 2.3 dB

-5

-3

-1

4000 Hz

Kl x 2.7 dB

-20

-17

-16

f ;,: 4400 Hz

Kl x 3.2 dB

-40

I ;,: 5000 Hz

Kl x 0 dB

-65

I
I

f

=
=
=
=
=

UNIT

dB

288 kHz (see Note 9)

0 Hz to 3100 Hz

FREQUENCY RANGE
I

reference is 0 dB

TYP§

4000 Hz

TEST CONDITION

Input signal

MIN
-33

I ;,: 4400 Hz

I

Filter gain

IN - is a ± 3 V sinew ave t (see Note 9)

K1 x 0 dB

low-pass filter transfer function (see curves), SCF fclock
PARAMETER

-

ADJUSTMENT ADDEND*

ADJUSTMENT ADDEND*

UNIT

dB

serial port
PARAMETER

TEST CONDITIONS

MIN

= -300
= 2 mA

2.4

VOH

High-level output voltage

IOH

VOL

low-level output voltage

IOL

II

Input cllrrent

~A

TYP§

MAX

UNIT
V

0.4

V

±10

~A

Ci

Input capacitance

15

pF

Co

Output capacitance

15

pF

t See filter curves in typical characteristics.
* The MIN, TYP, and MAX specilications are given lor a 288-kHz SCF clock Irequency. A slight error in the 288-kHz SCF may result Irom
inaccuracies in the MSTR ClK Irequency, resulting from crystal Irequency tolerances. II this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specilications, where K 1 = 100 • I(SCF Irequency - 288 kHz)/
288 kHz]. For errors greater than 0.25%, see Note 10.
§ All typical values are at T A = 25 DC.
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband ;s measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz lor the bandpass and low-pass
lilters respectively. For switched-capacitor Ii Iter clocks at Irequencies other than 288 kHz, the lilter response is shilted by the ratio of
switched-capacitor Iilter clock frequency to 288 kHz.

TEXAS •

INSTRUMENTS .
5-90

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUiTS

operating characteristics over recommended operating free-air temperature range, VCC+
VCC- = -5 V, VOO = 5 V

5 V,

noise (measurement includes low-pass and bandpass switched-capacitor filters)
Typt

TEST CONDITIONS

PARAMETER

with (sin xlix
Transmit noise

DX input

without (sin xlix

= 00000000000000,

Inputs grounded, gain

Receive noise (see Note 101

=

constant input code

1

325
18
300
18

UNIT

MAX

550
425

~V

rms

~V

rms

dBrncO

500

~V

rms

dBrncO

timing requirements
serial port recommended input signals
MIN

PARAMETER

MAX

95

UNIT

ns

tc(MCLKI

Master clock cycle time

tr(MCLKI

Master clock rise time

10

ns

tf(MCLKI

Master clock fall time

10

ns

RESET pulse duration (see Note 11 I

tsu(DXI

DX setup time before SCLKt

th(DX)

DX hold time after SCLKt

75%

25%
800
20

Master clock duty cycle

ns
ns
ns

t c(SCLK)/4

NOTES: 10. The noise is computed by statistically evaluating the digital output of the AID converter.
11. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their
recommended values.

serial port-AIC output signals, Cl = 30 pF for SHIFT ClK output, Cl

MIN

PARAMETER

tc(SCLK)

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

tr(SCLK)

Shift clock (SCLK) rise time

Typt

MAX

3
3

8
8
55

380

30
35

td(CH-FL)

Delay from SCLKt to FSR/FSX/FSDt

td(CH-FH)

Delay from SCLKt to FSR/FSX/FSDt

td(CH-DR)

DR valid after SCLKt

tdw(CH-EL)

Delay from SCLKt to EODX/EODRt in word mode

tdw(CH-EHl

Delay from SCLKt to EODX/EODRt in word mode

tf(EODX)

EODX fall time

tf(EODR)

EODR fall time

tdb(CH-EL)

Delay from SCLKt to EODX/EODRt in byte mode

tdb(CH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

td(MH-SL)

Delay from MSTR CLKt to SCLKt

tdIMH-SHI

Delay from MSTR CLK! to SCLK!

UNIT

ns

45

Shift clock (SCLK) duty cycle

tTypical values are at T A

15 pF for all other outputs

2
2

65
65

ns
ns

%
ns

90
90
90
90
8
8
90
90
170
170

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

= 25 ac.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-91

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range. V cc +
VCC- = -5 V. VOO = 5 V (continued)

...

5 V.

serial port - AIC output signals
PARAMETER

TEST CONDITIONS

MIN

Typt

MAX

UNIT

tc(SCLK)

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

50

ns

tr(SCLK)

Shift clock (SCLK) rise time

50

ns

380

Shift clock (SCLK) duty cycle

ns

45

=
=

55

%

50 pF

52

ns

50 pF

td(CH-Fl)

Delay from SCLKt to FSR/FSXt

CL

td(CH-FH)

Delay from SCLKt to FSR/FSXt

CL

52

ns

td(CH-DR)

DR valid after SCLKt

90

ns

tdw(CH-El)

Delay from SCLKt to EODX/EODRt in word mode

90

ns

tdw(CH-EH)

Delay from SCLKt to EODX/EODRt in word mode

90

ns

tf(EODX)

EODX fall time

15

ns

tf(EODR)

EODR fall time

15

ns

tdb(CH-El)

Delay from SCLKt to EODX/EODRt in byte mode

100

ns

tdb(CH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

100

ns

td(MH-SL)

Delay from MSTR CLKt to SCLKt

65

ns

tdIMH-SH)

Delay from MSTR CLKt to SCLKt

65

ns

tTypical values are at T A

=

25 DC.

TABLE 3. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL·SCALE AID CONVERSION)
CONTROL REGISTER BITS

INPUT CONFIGURATIONS
Differential configuration

d6

d7

1

1

ANALOGINPUT~

AID CONVERSION
RESULT

0

0

±6 V

full-scale

1

0

±3 V

full-scale

0

1

±1.5 V

full-scale

Single-ended configuration

1

1

Analog input = IN + - ANLG GND

0

0

1

0

Analog input = IN + - IN= AUX IN+ -

= AUX IN + -

AUX IN-

ANLG GND

±3 V

half-scale

0

±3 V

full-scale

1

±1.5 V

full-scale

tin this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.

R
IN + - " " '.....--1

~

R

IN - -'VV'....- t

R
AUX IN + ~""''''''--I
TO MUX

Rib

TO MUX

Rib

Rib - R lor d6 - " d7 - ,
d6 - 0, d7 = 0
Rib = 2R lor d6 = ' . d7 - 0
Rib = 4R lor d6 = 0, d7 = ,

Rib - R lor d6 - " d7 = ,
d6 - 0, d7 = 0
Rib - 2R lor d6 = " d7 - 0
Rib = 4R lor d6 - 0, d7 - ,

FIGURE 3. IN + AND IN - GAIN
CONTROL CIRCUITRY

FIGURE 4. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

TEXAS •
INSTRUMENTS
5-92

~

R

AUX IN - -'VV'....- t

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

(sin xlIx correction section
If the designer does not wish to use the on-board second-order (sin x)/x correction filter. correction can
be accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily
and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved
to a band edge of 3000 Hz by using a first-order digital correction filter. The results. which are shown
below. are typical of the numerical correction accuracy that can be achieved for sample rates of interest.
The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns instruction
cycle. nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates
of 8000 Hz and 9600 Hz. respectively. This correction will add a slight amount of group delay at the upper
edge of the 300-3000-Hz band.

(sin xlIx roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.
TABLE 4. (sin xlix ROLL-OFF

fs (Hz)

sin .. flfs
20109 - - .. flfs
(f - 3000 Hz)
(dB)

-2.64

7200
8000

-2.11

9600

-1.44

14400

-0.63
-0.35

19200

Note that the actual AIC (sin x)/x roll-off will be slightly less than the above figures. because the AIC has
less than a 100% duty cycle hold interval.

correction filter
To compensate for the (sin x)/x roll-off of the AIC. a first-order correction filter shown below. is
recommended.
U(i

+ 1)

I - - - - - - - - - - - _ . - - + V ( i + 1)

p1

The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
jH(f)j2=

p22(1-p1)2
1 - 2p1 cos(2 7r f/fs) + p1 2

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

5-93

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS
correction results
Table 5 below shows the optimum p values and the corresponding correction results for BOOO-Hz and
9600-Hz sampling rates.
TABLE 5

t (Hz)

300
600
900
1200
1500
1800
2100
2400
2700
3000

ERROR (dB)

ERROR (dB)

= 8000 Hz
p1 = -0.14813

ts

ts

p2 = 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

= 9600 Hz
p1 = -0.1307
p2 = 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1Y +k2U
where k 1 equals p 1 (from the preceding page). k2 equals (1 - p 1 )p2 (from the preceding page). Y is the
filter state, and U is the next 1/0 sample. The coefficients k 1 and k2 must be represented as 16-bit integers.
The SACH instruction (with. the proper shift) will yield the correct result. With the assumption that the
TMS320 processor page pointer and memory configuration are properly initialized, the equation can be
executed in seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U
LTA K1
MPY Y
APAC
SACH (dma), (shift)

.TEXAS •

INSTRUMENTS
5-94

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS
byte-mode timing
~,..tfISClK)

I
I
I 0.8 V
tdICH-Fl~ 14I
' I

FSR. FSX

0.8

I
I
I
~ !4-tdICH-Fl)
tdICH-FH~ ifII
I
I'
_ _ _-1fr;"2""V"'-------0-8 1 _ _---->/.}-'_ _ _ _ _ _
I

V

--+I !.-tdICH-FH)

---"'\~",~0"".8..;V_-+I--I:_~' ~
I

~tcISClK)

~,..trISClK)

SHIFT ClK

~IIr-

'vX-..

I

I"" ~~dICH-DR)

DR

__

~D~15~__~~~~---D-8-------~~~D-1--D-0_TI--~
I
I
tsuIDX)~

OX

:

~

I

~

I

I

~

08

~

DON'T CARE

D6~

07

1

-.t l.- thlDX)
--I 14- tdbICH-El)
tdbICH-EH)~ ~
----------------~r~:------~'
EODR.EODX
t~~0~.8~V~_ _ _ _ _ _ _ _ _ _~rrl____________~~
word-mode timing
~tcISCLKI

,

II
---+(
FSX,

I

I

SHIFT CLK
0.8 v)

I4- t d(CH-FL)

08

I
V

I

2V

0.• V

'

:

tdICH-FH)--'"'

14-

' I
"1
I
1-__________~'llro2~v-r-----I
"
I I
1I
I
: 4j !--tdlcH-DR)
I

---~~
FSR
o. v+
DR ___

~D~1~5___~~~D_1__D_O~:r-_~_ ____
tsuIDX)~ I.--

:

I

Dx------~DDv155Y~41~13YO~lrD1

DON'T CARE
I

I

I

I

I+-thIDX)

tdwICH-EL)-+j14- -.j !--tdwICH-EH)

-------------------------1, }-,--------O-.•--.}

+2 v

~

EODX, EODR

shift-clock timing

I+- td(MH-SH)

14-- tdIMH-SL)

--J"
I

\-

SHIFT CLK_ _ _ _ _ _

FIGURE 5, SERIAL PORT TIMING

...tf

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-95

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

TMS32010
SN74lS299
10-

I

DEN

L

Gl
A

Al/PAl

B

Yl

YO I-

Gl

08·015

A·H

C

\

Sl

SO ClK
61

00·015

CLKOUT
INT

,/-

00·07
A·H

\

\

TlC32040/
TlC32041/
TlC32042
SHIFTClK

QH

' - - 62

\

~

ox

r-n
-

SR

SN74lS299

~
WE

G-

SO ClK< !---

t--

SN74lS138

00·015

QH

G2

AO/PAO
A2/PA2

Sl

FSX

C2

SR

...-

~
Q

Cl
10

->;=0

DR

MSTR ClK
EOOX

FIGURE 6. TMS32010/TMS320C15·TLC32044 INTERFACE CIRCUIT
in instruction timing
ClK OUT

SO. Gl
00-015

_________________________________________-<::~~~I>---------------------------------------------------------------------(
VALID
)

out instruction timing
ClKOUT _ _~

. ___~:~I------------------I

i

I

SN74lS 138 Yl

I

SN74lS299 elK
I

00-015

{

I

VALID

)

FIGURE 7. TMS32010/TMS320C15·TLC32044 INTERFACE TIMING

~

TEXAS
INSTRUMENTS
5-96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75266

TLC32044C, TLC320441
VOICE-BAND ANALOG INTERFACE CIRCUITS

TYPICAL CHARACTERISTICS
AIC TRANSMIT AND RECEIVE LOW-PASS FILTER

AIC TRANSMIT AND RECEIVE LOW-PASS FILTER
3

20

SCF clock f

10

TA

cc

..
I

"0

E

CI
to

-40

\

'"

~ 1.5
c.

\

::I

o

\

-50

2

I
>-

-20
-30

:!

\

-10

a
';:

288 kHz

25°C
2.5 Input = ± 3-V sinewave

0

"0

=

=

t5

'/

I

-60

SCF clock f = 288 kHz

TA = 25°C

-70
-80

"

Input = ±3-V sinewave

o

0.5

1

1.5

2

2.5

-

0.5

If
3

3.5

4

4.5

o

5

0.5

1

1.5

2

/

I~ r--

.-/

2.5

3

\

3.5

4

4.5

5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

FIGURE 9

FIGURE 8
AIC RECEIVE-CHANNEL BANDPASS FILTER

AIC RECEIVE-CHANNEL HIGH-PASS FILTER
20

20

SCF clock f = 8 kHz
10

Input = ± 3-V sinewave

0

\

-10

.,

cc

"0

I

0

\

..

a -30
-50
Low-pass SCF clock f = 288 kHz
High-pass SCF clock f - 8 kHz
TA = 25°C
Input - ± 3-V sinewave

-60
-70
-80

'0

a

\
\

-40

o

0.5

1

1.5

2

2.5

3

3.5

Frequency - kHz

FIGURE 10

4

/

/

-10

f

I

\

"0

CI

cc

'0

-20

';:

:!'"

TA = 25°C

10

-20

';:

CI

/"

'"

:2 -30

L

-40
-50

If

4.5

5

-60

o

50 100 150 200250 300 350400450500

Normalized Frequency _ kHz x AID Conversion Rate
8 k samplesls

FIGURE 11

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-97

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL BANDPASS FILTER

AIC (SIN XliX CORRECTION FILTER
5

2.5

Low-pass SCF clock f = 288 kHz
High-pass SCF clock f = 8 kHz

I-'-

TA = 25°C
Input = ±3-V sinewave

If---

SCF clock f = 288 kHz
4.5 I-TA = 25°C
4 I-Input = ± 3-V sinewave
I

l"-

II
/

3.5

'" 2.0

E

if

II]

I

"".,I
""E

n

>

~ 1.5

c

."

Co

Cl

::l

e

ca

1.0

C!l

0.5

\

r-

0.5

1

1.5 2 2.5 3 3.5
Frequency-kHz

V

2

/

1.5

/

1"'-r--

0.0

J

2.5

::i!

k.-I \

-

r--......

3

4

4.5

0.5

V

.I.---"

0

5

/

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

FIGURE 12

FIGURE 13
(SIN XliX CORRECTION FILTER

AID SIGNAL-TO-DISTORTION RATIO

vs

6
IsL x)x

4

correcti/"
filter

2

II]

--r---.

"".,I

E
.'c

V

0

Cl

::i!'" -2

V

-6

~ listorn
o

0.5

1

90

f"'.-

--...

i r i '"

1.5

reristei

2

2.5

100

II]

error

f"-- c::::."

or

INPUT SIGNAL

V

V

I·
I
DIA converter (sin xlix

-4

~

r

3

=

.9

70

'iU

1\

I:

of0

E

'"
is
~
"iii

6

4

80

a;

~

3.5

""I

I:
Cl

iii

[\

4.5

5

1-kHz input signal
8-kHz conversion rate

I
GAIN

60
50
40

=

V /

~/

1X-

,.

30
20

~50

FIGURE 14

o

-40
-30
-20
-10
Input Signal Relative to Vref-d8

FIGURE 15

TEXAS

~

INSTRUMENTS
5-98

=

10

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

.

-

GAIN

4X

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

TLC32044C. TLC320441

VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT 0 dB INPUT SIGNAl)
0.5
0.4

1-kHz input signal
8-kHz conversion rate

0.3
0.2

III
'0

I

0.1

Cl

I:

:.;;;

0

.::"'"

-

-0.1

I:

'iii

CJ -0.2

-0.3
-0.4
-0.5
- 50

- 40

- 30

- 20

o

- 10

10

Input Signal Relative to V ref - dB

FIGURE 16
D/A CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL LEVEL
100 , - - , - - , 1-kHz input signal into 600 ()
90 8-kHz conversion rate
III
'0

80

I

I

.g

70

cc'"

60

I:

I

0

'f 50
0
t;

,./

C 40

~

'\

/
/

/

c;; 30
I:

Cl

iii 20
10

o

- 50

I
- 40
- 30
- 20
- 10
o
Input Signal Relative to V ref - dB

10

FIGURE 17

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-99

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

TYPICAL CHARACTERISTICS
DIA GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL LEVEl)
0.5
0.4

AID SECOND HARMONIC DISTORTION
vs

INPUT SIGNAL
-100

1-kHz input signal
-90 8-kHz conversion rate

1-kHz input signal into 600 {)
8-kHz conversion rate
/Xl

I'

0.3

-80

c

~ -70
o
ti -60
is
-50
o

0.2

/Xl
""0

b.

0.1

c
:;;

~
0
~
c -0.1

- r--

-~

/

-------

r"-

'E

.......... . /

§

-40

""0

-30

ca
J:

'0;

CI -0.2

c

o

"

-0.3

Q)

-20

C/)

-0.4
-0.5
- 50

-10
- 40
- 30
- 20
- 10
o
Input Signal Relative to V ref - d8

o

10

- 50

o
- 40
- 30
- 20
- 10
Input Signal Relative to Vref-dB

FIGURE 18

FIGURE 19
DIA SECOND HARMONIC DISTORTION
vs

INPUT SIGNAL
-100
1-kHz input signal into 600 {)
-90 8-kHz conversion rate
/Xl

"tl

I

c

-80

0

-70

II>

-60

.~

is

V

V

""""--....

<> -50

'c0
§

-40

"tl

-30

ca
J:

c
0

"
Q)

-20

C/)

-10

o

- 50

o
- 40
- 30
- 20
- 10
Input Signal Relative to Vref-d8
FIGURE 20

TEXAS .."
INSTRUMENTS
5-100

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

10

10

TLC32044C, TLC320441
VOICE·BAND ANALOG INTERFACE CIRCUITS

TYPICAL CHARACTERISTICS
AID THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
1· kHz input signal

-90 8-kHz conversion rate .

~ -80

~

I

g

-70

V
./

'f
~ -60

I-"

is
" - 50
·2
o
E -40

'"

ca

::t:

"E

:c

~

-30
-20
-10

o

- 50

- 40

- 30

- 20

o

- 10

10

Input Signal Relative to Vret-dB

FIGURE 21
DiA THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
1-kHz input signal into 600 11

-90 8-kHz conversion rate
~ -80
I

g -70

10-

.~

./

t; - 60

is
 75265

5-113

TLC32044M
VOICE·BAND ANALOG INTERFACE CIRCUIT

~:~ELr~

FSX

~:R

'I

I

i4-0NGOING CONVERSION-.t

12 - 11 "

1/19.2 kHz

asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

u

FSX

U

1

I

Mj4------TRANSMIT CONVERSION PERIOD-----...,.HI

FSR

I

I

I

~RECEIVE CONV.--.w-RECEIVE CONV.~
PERIOD A
PERIOD B

asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the following figure. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already' will be adjusted via the Transmit Conversion Period B
adjustment command.

~

TEXAS
INSTRUMENTS
5-114

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044M
VOICE-BAND ANALOG INTERFACE CIRCUIT

u

U

Lr

U

I
I
I
I
I4-TRANSMIT CONV.~TRANSMIT CONV.""*TRANSMIT CONV.'"*i
PERIOO A
PERIOD B
PERIOD C

t2

U

FSRU

I

I

14

~

RECEIVE CONVERSION PERIOD A

Lr

I
RECEIVE CONVERSION PERIOD B-----I.~I

asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
The T A, T A', TS, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RS register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period S. If RA, RA', and RS register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RS information that is
received during this receive conversion period will be disregarded (see diagram below).

t,

PRIMARY

"xl

SECONDARY

PRIMARY

n-------..~

I

n

SECONDARY

PRIMARY

SECONDARY

r--------ILJl

r------"IL

TRANSMIT
I
TRANSMIT
I
TRANSMIT
I
MI4f-----CONVERSION----••"If-----CONVERSION-----I.~"If-----CONVERSION----+!.I
PERIOD A
PERIOD B
PERIOD C

FSR

~I

"""- RECEIVE CONVERSION __
f-------I
.....PERIOD A
.,..
RECEIVE CONVERSION PERIOD B------~~

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-115

nC32044M

VOICE-BAND ANALOG INTERFACE CIRCUIT
test modest
The following paragraph provides information that allows the TLC32044M to be operated in special test
modes. These test modes are used by Texas Instruments to facilitate testing of the device during
manufacturing. They are not intended to be used in real applications, however, they allow the filters in
the AID and DIA paths to be used without using the AID and DIA converters.
In normal operation, the nonusable (NU) pins are left unconnected. These NU pins are used by the factory
to speed up testing of the TLC32044M Analog Interface Circuit (AI C) . When the device is used in normal
(non-test-mode) operation, the NU pin (pin 1) has an internal pull-down to - 5 V. Externally connecting
o V or 5 V to pin 1 puts the device in test-mode operation. Selecting one of the possible test modes is
accomplished by placing a particular voltage on certain pins. A description of these modes is provided
in Table 2 and Figures 1 and 2.
TABLE 2. LIST OF TEST MODES
TEST

DIA PATH TEST (PIN 1 to 5 V)

PINS

TEST FUNCTION

5
11
3
27 and 28

AID PATH TEST (PIN 1 to 0)

TEST FUNCTION

The low-pass switched-capacitor filter clock is brought

The bandpass switched-capacitor filter clock is brought

out to pin 5. This clock signal is normally internal.

out to pin 5. This clock signal is normally internal.

No change from normal operation. The EODX signal is

The pulse that initiates the AID conversion is brought

brought out to pin 11.

out here. This signal is normally internal.

The pulse that initiates the D/A conversion is brought

No change from normal operation. The EODR signal is

out here.

brought out.

There are no test output signals provided on these pins.

The outputs of the AID path low-pass or bandpass filter
(depending upon control bit d2 -

see AIC DX Data

Word Format section) are brought out to these pins. If
the high-pass section is inserted. the output will have a
(sinx)/x droop. The slope of the droop will be determined
by the ADC sampling frequency, which is the high-pass
section clock frequency (see diagram of bandpass or
low-pass filter test for receive section). These outputs
will drive small (30-pF) loads.
D/A PATH LOW-PASS FILTER TEST; PIN 13 (WORD/BYTE) to -5 V

TEST FUNCTION
15 and 16

The inputs of the D/A path low-pass filter are brought out to pins 15 and 16. The D/A input to this filter is removed.
If the' (sin x)/x correction filter is inserted, the OUT + and OUT- signals will have a flat response (see Figure 2). The
common·mode range of these inputs must not exceed ± 0.5 V.

t In the test mode, the AIC responds to the setting of Pin 13 to - 5 V, as if Pin .13 were set to 0 V. Thus, the byte mode is selected
for communicating between DSP and Ale. Either of the path tests (D/A or AID) can be performed simultaneously with the D/A low-pass
filter test. In this situation, Pin 13 must be connected to - 5 V, which initiates byte-mode communications.

TEXAS ~

INSTRUMENTS
5-116

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
PIN 27 (POSITIVE).
PIN 28 (NEGATIVElt

I+ +

TEST CONTROL
(PIN 1 AT 0 VI

TEST

FILTER

r--

~

t
-

v

•

-

M
U
X

,-

•

I

AID

~

'---

r---

•

FIGURE 1. BANDPASS OR LOW-PASS FILTER TEST FOR RECEIVER SECTION

FILTER

M
U
X

M

(Sin x}/x
CORRECTION

U
X

L.-,r--,......~....- -

TEST CONTROL
(PIN 13 at - 5 V)

PIN 16 (POSITIVE).
PIN 15 (NEGATIVE}t

FIGURE

2.

LOW-PASS FILTER TEST FOR TRANSMIT SECTION

t All analog signal paths have differential architecture and hence have positive and negative components.

TEXAS

+

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-117

TLC32044M
VOICE-BAND ANALOG INTERFACE CIRCUIT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vcc+ (see Note 1)
-0.3 V to 15 V
Supply voltage range, VDD
-0.3 V to 15 V
Output voltage range, Vo .....
-0.3 V to 15 V
Input voltage range, VI .......
-0.3 V to 15 V
-0.3 V to 15 V
Digital ground voltage range. . . .
Operating free-air temperature range .. . . . . . . .
- 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 60 seconds: FK package. . . . . . . . . . . . . . . . . . . . . . .
260. o C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC -.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage. VCC + (see Note 2)

PARAMETER

4.75

5

5.25

V

Supply voltage. VCC- (see Note 2)

-4.75

-5

- 5.25

V

4.75

5

5.25

V

Digital supply voltage, VDD (see Note 2)

0

Digital ground voltage with respect to ANLG GND. DGTL GND

V

Reference input voltage, Vref(ext) (see Note 2)

2

4

V

High-level input voltage, VIH

2

VOO+O.3

V

-0.3

0.8

V

Low-level input voltage, VIL (see Note 3)
Maximum peak output voltage swing across. RL at OUT + or OUT - (single-ended)
(see Note 4)
Load resistance at OUT + and/or OUT -, RL

±3

V

!l

300

Load capacitance at OUT + and/or OUT -, CL

100

MSTR CLK frequency (see Note 5)

0.075

Analog input amplifier common mode input voltage (see Note 6)

NOTES:

- 55

MHz
V

20

kHz

125

°c

2. Voltages at analog inputs and outputs, REF, VCC +, and VCC _, are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.
4. This applies when RL ;,: 300 !l and offset voltage = O.
5. The bandpass switchedccapacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and
the high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the low-pass roll-off frequency
will shift by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF clock is shifted from 8 kHz, the high-pass
roll-off frequency will shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter
(SCF) specifications apply only when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-oft
frequency will shift by the ratio of the SCF clock to 288 kHz.
6. This range applies when (IN + - IN -) or (AUX IN + - AUX IN -) equals ± 6 V.

TEXAS •
INSTRUMENTS
5-118

10.368
±1.5

A/D or 0/ A conversion rate
Operating free-air temperature, T A

5

pF

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044M
VOICE·BAND ANALOG INTERFACE CIRCUIT

electrical characteristics over recommended operating free-air temperature range.
Vee - = - 5 V. Voo = 5 V (unless otherwise noted)

Vee +

5

V.

total device. MSTR eLK frequency = 5.184 MHz. outputs not loaded
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD

Val

Low-level output voltage

VDD

=
=

4.75 V, IOH
4.75 V, IOl

= -300 pA
= 2 rnA

MIN

Typt

Supply current from VDD

Vref

Internal reference output voltage

fMSTR ClK

=

5.184 MHz
2.9

Temperature coefficient of

UNIT
V

ICC+ Supply current from VCC +
lee- Supply current from VceIDD

MAX

2.4
0.4

V

40

rnA

-40

rnA

8

rnA

3.3

V

"V ref internal reference voltage

200

ppm/oe

Output resistance at REF

100

k{l

ro

receive amplifier input
PARAMETER

TEST CONDITIONS

MIN

A/D converter offset error (filters in)
CMRR

r;

Common-mode rejection ratio at IN +, IN -,

See Note 7

or AUX IN+, AUX IN-

35

Input resistance at IN +, INor AUX IN+, AUX IN-, REF

Typt

MAX

10

85

UNIT
mV

55

dB

100

k{l

transmit filter output
PARAMETER

TEST CONDITIONS

MIN

Output offset voltage at OUT + or OUT VOO

(single-ended relative to ANLG GND)
Maximum peak output voltage swing between

VOM

OUT + and OUT - (differential output)

Rl ;,: 300 {l

±6

Typt

MAX

15

85

UNIT
mV
V

t All typical values are at T A =.25 DC.
NOTE 7: The test condition is a O-dBm, 1-kHz input signal with an 8-kHz conversion rate.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5--119

TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
electrical characteristics over recommended operating free-air temperature range, VCC+
VCC - = - 5 V, VOO, = 5 V (unless otherwise noted)

5 V,

system distortion specifications. SCF clock frequency = 288 kHz
MIN

Typt

Yin = - 0,5 dB to - 24 dB referred to Vref,
Single-ended tested at 25 oe, See Note 8

62

70

6.2

70

57

65

PARAMETER

TEST CONDITIONS

Attenuation of second harmonic of

single-ended

AID input signal

differential

Attenuation of third and higher

single-ended

harmonics of AID input signal

differential

Yin = -0,5 dB to -24 dB referred to Vref,
Single-ended tested at 25 oe, See Note 8

Attenuation of second harmonic of

single-ended

Vin = - 0 dB to - 24 dB referred to Vref,

DI A input signal

differential

See Note 8

Attenuation of third and higher

single-ended

Vin = - 0 dB to - 24 dB referred to Vref,

harmonics of DIA input signal

differential

See Note 8

57

MAX

dB
dB

65
70

62

dB

70
65

57

UNIT

dB

65

AID channel signal-to-distortion ratio
(see Note 8)
Yin
Yin
Yin
Yin
AID channel signal-to-distortion ratio

Ay - 1~

TEST CONDITIONS

PARAMETER

Yin
Yin
Yin
Yin
Yin

MIN

MAX

Ay - 2*
MIN
MAX
>58§

Ay - 4~
MIN
MAX
>58§

=
=
=
=

-6dBto -0,5dB

58

- 12 dB to - 6 dB

58

58

>58§

-18 dB to -12 dB

56

58

58

- 24 dB to - 18 dB

50

56

58

=
=
=
=
=

- 30 dB to - 24 dB

44

50

56

- 36 dB to - 30 dB

38

44

50

-42dBto -36dB

32

38

44

-48dBto -42dB

26

32

38

-54dBto -48 dB

20

26

32

UNIT

dB

t All typical values are at T A = 25°e,
*Av is the programmable gain of the input amplifier,
§A value> 58 is over range and signal clipping occurs,

DIA channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER

(see Note 8)
Yin

=

- 6 dB to 0 dB

58

Yin

=
=
=

- 12 dB to - 6 dB

58

- 1 8 dB to - 1 2 dB

56

Yin
Yin
DIA channel signal-to-distortion ratio

MIN

Yin
Yin
Yin
Yin
Yin

=
=
=
=
=

-24dBto-18dB

50

-30dBto -24dB

44

-36 dB to -30 dB

38

-42 dB to -36 dB

32

-48 dB to -42 dB

26

- 54 dB to - 48 dB

20

MAX

UNIT

dB

NOTE 8: The test condition is a 1-kHz input signal with an 8-kHz conversion rate 10 dB relative to Vref), The load impedance for the DAe
is 300 Q,

TEXAS

~

INSTRUMENTS
5-120

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
electrical characteristics over recommended operating free-air temperature range, Vcc+ = 5 V,
Vcc - = - 5 V, Voo = 5 V (unless otherwise noted) (continued)
gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit gain tracking error while transmitting

- 48 dB to 0 dB signal range,

into 300

n

MIN

See Note 9
- 48 dB to 0 dB signal range,

Absolute receive gain tracking error

See Note 9
Signal input is a - O. 5-dB,

Absolute gain 01 the AID channel

l-kHz sinew ave
Signal input is a O-dB,

Absolute gain 01 the DIA channel

l-kHz sinew ave

Typt

MAX

UNIT

±0.05 ±0.15

dB

±0.05 ±0.15

dB

0.2

dB

-0.3

dB

power supply rejection and crosstalk attenuation
TEST CONDITIONS

PARAMETER
VCC+ or VCC- supply voltage

1

=

0 to 30 kHz

rejection ratio, receive channel

1

=

30 kHz to 50 kHz

1

=

0 to 30 kHz

Vee + or V CC _ supply voltage

Crosstalk attenuation (differential)

Typt

=

30 kHz to 50 kHz

dB

Idle channel, supply signal

30
dB
45

at OUT +

=

Transmit-to-receive

DX

Receive-to-transmit

Inputs grounded

00000000000000

UNIT

45

at DR (ADC output)
at 200 mV p-p measured

1

MAX

30

at 200 mV p-p measured

rejection ratio, transmit channel

(single-ended)

MIN

Idle channel, supply signal

65

80

65

80

dB

t All typical values are at TA = 25°C.
NOTE 9: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 db relative to Vrel).

+

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-121

TLC32044M
VOICE-BAND ANALOG INTERFACE CIRCUIT

delay distortion
bandpass filter transfer function. SCF fclock
PARAMETER

TEST CONDITION

288 kHz IN + - IN - is a

FREQUENCEY RANGE

ADJUSTMENT ADDEND*

I s 50 Hz
I
I
Input signal

Filter gain

reference to 0 dB

I
I
I

=
=
=
=
=
=

Kl x 0 dB

-25

Kl x - 0.26 dB

-4

-2

-1

1 50 Hz to 3100 Hz

Kl x 0 dB

-0.25

0

0.25

3100 Hz to 3300 Hz

Kl x 0 dB

-0.3

0

0.3

3300 Hz to 3600 Hz

Kl x 0 dB

-0.5

0

3BOO Hz

Kl x 2.3 dB

-3
-20

0.5

-'17

Kl x 3.2 dB

-40

I ;,: 5000 Hz

Kl x 0 dB

-65

288 kHz (see Note 10)
MIN

TYP§

MAX

Kl x 0 dB

-0.25

0

0.25

3100 Hz to 3300 Hz

Kl x 0 dB

-0.3

0

0.3

3300 Hz to 3600 Hz

Kl x 0 dB

-0.5

0

3800 Hz

Kl x 2.3 dB

-3

4000 Hz

Kl x 2.7 dB

-20

f ;,: 4400 Hz

Kl x 3.2 dB

-40

I ;,: 5000 Hz

Kl x 0 dB

-65

I
I
I
f

dB

-16

0 Hz to 3100 Hz

FREQUENCY RANGE

=
=
=
=
=

UNIT

-0.5

Kl x 2.7 dB

TEST CONDITION

relerence is O. dB

MAX

-29

4000 Hz

I

Filter gain

TYP§

100 Hz

low-pass filter transfer function (see curves). SCF fclock

Input signal

MIN
-33

I ;,: 4400 Hz

I

PARAMETER

± 3 V sinewave t (see Note 10)

ADJUSTMENT ADDEND*

0.5
-0.5

-17

UNIT

dB

-16

serial port
PARAMETER

TEST CONDITIONS

MIN

= -300
= 2 mA

2.4

VOH

High-level output voltage

IOH

VOL

Low-level output voltage

IOL

II

Input current

Ci

Input capacitance

Co

Output capacitance

"A

TYP§

MAX

UNIT
V

0.4

V

±10
15

"A
pF

15

pF

t See filter curves in typical characteristics.
tThe MIN, TYP, and MAX specifications are given lor a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result Irom
inaccuracies in the MSTR eLK Irequency, resulting from crystal Irequency tolerances. II this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specilications, where Kl = 100· [(SCF Irequency - 288 kHz)!
288 kHz). For errors greater than 0.25%, see Note 10.
§ All typical values are at T A = 25 DC.
NOTE 10: The lilter gain outside 01 the passband is measured with respect to the gain at 1 kHz. The Iilter gain within the passband is
measured with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz lor
the bandpass and low-pass lilters respectively. For switched-capacitor lilter clocks at Irequencies other than 288 kHz, the lilter
response is shifted by the ratio 01 switched-capacitor lilter clock frequency to 288 kHz.

TEXAS •

INSTRUMENTS
5-122

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044M

VOICE-BAND ANALOG INTERFACE CIRCUIT
operating characteristics over recommended operating free-air temperature range. VCC+

VCC-

-5V.VOO

=

=

5 V.

5V

noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

Typt

TEST CONDITIONS

with (sin xlix
Transmit noise

DX input

without (sin xlix

=

00000000000000, constant input code

325

MAX

UNIT

575

/LV rms

450

/LV rms

500

/LV rms

dBrneO

18

Receive noise (see Note 111

Inputs grounded, gain

=

300

1

18

dBrncO

timing requirements
serial port recommended input signals
PARAMETER

MIN

MAX

UNIT

100

192

ns

Master clock rise time

10

ns

Master clock fall time

10

ns

tc(MCLKI

Master clock cycle time

tr(MCLKI
tf(MCLKI

Master clock duty cycle

25%

RESET pulse duration (see Note 121
tsu(DXI

DX setup time before SCLKI

th(DXI

DX hold time after SCLKI

75%

800

ns

28

ns

t c(SCLKI/4

ns

NOTES: 11. The noise is computed by statistically evaluating the digital output of the AiD converter.
12. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their
recommended values.

operating characteristics over recommended operating free-air temperature range. V CC +
VCC- = -5 V. VOO = 5 V (continued)
serial port -

5 V.

Ale output signals
PARAMETER

MIN

Typt

MAX

UNIT

tc(SCLKI

Shift clock (SCLKI cycle time

tf(SCLKI

Shift clock (SCLKI fall time

50

ns

tr(SCLKI

Shift clock (SCLKI rise time

50

ns

Shift clock (SCLKI duty cycle

50

400

td(CH-FLI

Delay from SCLKt to FSR/FSXI

td(CH-FHI
td(CH-DRI

ns

%
260

ns

Delay from SCLKt to FSR/FSXt

260

ns

DR valid after SCLKt

316

ns

tdw(CH-ELI

Delay from SCLKt to EODX/EODRI in word mode

280

ns

tdw(CH-EHI

Delay from SCLKt to EODX/EODRt in word mode

280

ns

tf(EODXI

EODX fall time

15

ns

tf(EODRI

EODR fall time

15

ns

tdb(CH-ELI

Delay from SCLKt to EODX/EODRI in byte mode

100

ns

tdb(CH-EHI

Delay from SCLKt to EODX/EODRt in byte mode

100

td(MH-SLI

Delay from MSTR CLKt to SCLKI

65

td(MH-SHI

Delay from MSTR CLKt to SCLKt

65

ns
105

ns
ns

t All typical values are at T A = 25 DC.

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TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
TABLE 3. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL·SCALE AID CONVERSION)
CONTROL REGISTER BITS

INPUT CONFIGURATIONS

dS

d7

1

1

IN + - IN-

0

AUX IN+ - AUX IN-

1

0
0

0

1

1

1

IN + - ANLG GND

0

AUX IN + - ANLG GND

1

0
0

0

1

Differential configuration
Analog input

=
=

Single-ended configuration

Analog input

=
=

ANALOG INPUTt

AID CONVERSION
RESULT

±S V

full-scale

±3 V

full-scale

±1.5 V

full-scale

±3 V

half-scale

±3 V

full-scale

±1.5 V

full-scale

tin this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.
RIb

RIb

R
IN+-"""....- I

~

R
IN - - " " "....-1

R
AUX IN + -"""....~

TO MUX

~

R
AUX IN - - " " "....- t

TO MUX

RIb

RIb
RIb - R lor d6 = 1, d7 = 1
d6 - 0,d7 = 0
RIb = 2R lor d6 - 1. d7 - 0
RIb - 4R lor d6 = 0, d7 - 1

RIb - R lor d6 - 1, d7 - 1
d6 - 0, d7 - 0
RIb - 2R lor d6 - 1, d7 - 0
RIb - 4R lor d6 - 0, d7 - 1

FIGURE 3. IN + AND IN - GAIN
CONTROL CIRCUITRY

FIGURE 4. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

(sin xlIx correction section
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can
be accomplished in digital signal processor (DSP) software, (Sin xlIx correction can be accomplished easily
and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved
to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are shown
below, are typical of the numerical correction accuracy that can be achieved for sample rates of interest.
The filter requires only seven instruction cycles per sample on the SMJ320 DSPs. With a 200-ns instruction
cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates
of 8000 Hz and '9600 Hz, respectively. This correction will add a slight amount of group delay at the upper
edge of the 300-3000-Hz band.

TEXAS

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INSTRUMENTS
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TLC32044M

VOICE-BAND ANALOG INTERFACE CIRCUIT
(sin xlIx roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.

TABLE 4. (sin x)/x ROLL-OFF
20 log sin .. flfs
.. f/f.

fs (Hz)

(f - 3000 Hzl
(dB)

-2.64
-2.11
-1.44

7200
8000
9600
14400
19200

-0.63
-0.35

Note that the actual AIC (sin x)/x roll-off will be slightly less than the above figures, because the AIC has
less than a 100% duty cycle hold interval.

correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is
recommended.
U(i+ 1)

) - - - - - - - - - -.....--+V(i+ 1)

p1

The difference equation for this correction filter is:
Yi+1 = p2(1-pl) (Ui+l)+pl Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =

p22 (1-p1)2
1 - 2p1 cos(2 7r f/fs) + p1 2

TEXAS •

INSTRUMENTS
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TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
correction results
Table 5 below shqws the optimum p values and the corresponding correction results for BODO-Hz and
9600-Hz sampling rates.
TABLE 5
ERROR (dB)
f (Hz)

300
600
900
1200
1500
1800
2100
2400
2700
3000

fs

= BOOO Hz

p1 - -0.14B13
p2 = 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

ERROR (dB)

= 9600 Hz
p1 - -0.1307
p2 = 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

fs

SMJ320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1Y +k2U
where k 1 equals p 1 (from the preceding page), k2 equals (1 - p 1 )p2 (from the preceding page), Y is the
filter state, and U is the next I/O sample. The coefficients k 1 and k2 must be represented as 16-bit integers.
The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the
SMJ320 processor page pointer and memory configuration are properly initialized, the equation can be
executed in seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U
LTA K1
MPY Y
APAC
SACH (dma), (shift)

TEXAS ~

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75266

TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
byte-mode timing
-.,~tfISCLKI

~j4-trlSCLKI

,

SHIFT CLK

, 08 v ,

tdICH-FLl~
FSR. FSX

r-'
"'-;;';;";--+'--'<'""--1,
,,

---"'\,'
\08
V'

, -.,

DR _ _

,

,

~tcISCLKI

,,

,

-41 ~tdICH-FHI

~ I--tdICH-FLI

,."...-------"'\'
~2 V
08 vt

tdICH-FH~

'..,'

I-r,

L-----1/.I-'_ _ _ _ _ _U_

~---~f

~tdICH-ORI

,

I2V

I

~0~15~__~
014
01~~-.
_ _ _0_B_ _ _ _~~~~0_1_ _0_0_1~_ _
0.8V
,
t sulOXI4f ~

ox

10-

"

,

~.i(~~~~~_~020~N~'T~C~A~R~E~_~~=X~'
~
~~
DB,
07
06~

~ i.-thlOXI
----I ~tdbICH-ELI
tdbICH-EHr-l ~
EOOR.EOOX--------~;~f----~t~~0~.8~V~____________~f.~,------~~
word-mode timing

,,

,,

~tc(SCLKI

SHIFT CLK

,.
It- thlOX)

shift· clock timing
MSTR CLK

,

~tdIMH-SLI

!+-tdIMH-SHI

'\1\------

-l:
---~/j

SHIFT CLK

FIGURE 5. SERIAL PORT TIMING

TEXAS

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INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265

5--127

TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT

SMJ320Cl0

FSX

SN541,.S2!1!1
~

S1

DEN
' - G1

AO/PAO

A

A1/PA1

B

A2/PA2

C

V1

t--

VO f-

SO

\

00-015

A-H

ClK OUT

00-015

00-07

\

\

S1

SHIFT ClK

QH'
ClK

A-H

~

~ SN54lS7~
~

G1
SR

I

\

~

SN54lS299

SO

-

TlC32044M

SR

' - - - G2

\ (

~

-

\

--

~

ClK<

G1

08-015

SN54lS138

WE

ox

QH'

G2

r-Ll

10

f-+-

DR

MSTR ClK
EOOX

INT

FIGURE 6, SMJ320C10/SMJ320C15/SMJ320E15·TLC32044M INTERFACE CIRCUIT

in instruction timing
ClK OUT

---'

I
I

I

I .
SO, G1
00-015

_____________________-<::~~~I~----------------------------------(

VALID

)

out instruction timing
ClK OUT _ _--'

:I
I

r --------------------------------

'--_ _--;j.J

I
SN74lS138 V1

I

SN74lS299 ClK
I

00-015

(

I

VALID

)

FIGURE 7, SMJ320C10/SMJ320C15/SMJ320E15·TLC32044M INTERFACE TIMING

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TLC32044M

VOICE·BAND ANALOG INTERFACE CIRCUIT
TYPICAL CHARACTERISTICS
AIC TRANSMIT AND RECEIVE LOW-PASS FILTER
20

AIC TRANSMIT AND RECEIVE LOW-PASS FILTER

3

SCF clock f = 288 kHz
TA = 25°C
2.5 Input = ± 3-V sinewave

10
0

\

-10

--

E

!Xl
"0

.,I

-20

1\

"0

E -30

'"'"
:2

'"

~ 1.5

\

'c

-40

I

0-

"o
Ci

\

-50

2

I
>

I

-60

SCF clock f = 288 kHz
TA = 25°C
Input = ± 3-V sinewave

-70

-80

o

0.5

1

1.5

2

2.5

-

0.5

If
3

3.5

4

4.5

AIC RECEIVE-CHANNEL HIGH-PASS FILTER
20
SCF clock f = 8 kHz
10 TA = 25°C
Input = ± 3-V sinewave

10

!Xl
-

I

\\

0
!Xl

"0

20

E -30

-60
-70

o

0.5

1

1.5 2 2.5 3 3.5
Frequency - kHz

4

/

-10

'"'"

:2 -30
-40

If

r

(

-50

r.
4.5

--

f

E -20

'c

\

Low-pass SCF clock f = 288 kHz
High-pass SCF clock f = 8 kHz
TA = 25°C
Input = ± 3-V sinewave

V

"0

\

:2

-80

.,I

\

'"

"0

'c
g> -40
-50

---

FIGURE 9

AIC RECEIVE-CHANNEL BANDPASS FILTER
20

"0

~

Normalized Frequency _ kHz x SCF Clock Frequency
288 kHz

FIGURE 8

o

V

\

o 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

-10

/

5

-60

o 50 100 150 200250300 350400450500

Normalized Frequency-kHz x AID Conversion Rate
8 k samplesls

FIGURE 10

FIGURE 11

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nC32044M
VOICE·BAND ANALOG INTERFACE CIRCUIT
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL BANDPASS FILTER

2.5

-

I

(\

~ 1.5

."E'"

c

Co
:l

2'"

~ 1.0

0.5

\ r--.....

\
~

I-- r-

1

/

1.5 2 2.5 3 3.5
Frequency - kHz

2.5

V

2

/

1.5

/

1"-r--

0.0
0.5

3

Q)

"0

4

4.5

0.5

I---""V

0

5

0.5

1

/
1.5

2

2.5

3

3.5

4

4.5

5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

FIGURE 12

FIGURE 13
(SIN XliX CORRECTION FILTER
6

vs

(Si~ x)/~

~

- correction

4

AID SIGNAL-TO-DISTORTION RATIO
INPUT SIGNAL

~
100

filter/

2

00

-

"0

I
Q)

"0

E

0

."'"

V

V

r-- r------

2'" -2

V

V

-6

00

"0

..,
0

error

---..

l"- e:-.."

r ""

~

0.5

1

1.5

2

2.5

3

'"

a:

1\

±±

80

3.5

4

70

GAIN = 4X

c:

60

e

50

is

40

of0
-1'....
SERIAL
PORT

IN - -Ho-ioo'
AUX IN

+ --11-1...,.......

AUX IN - - H......"
RECEIVE SECTION

r-

!

.....,

I

-l

INTERNAL
VOLTAGE
REFERENCE

I

I

FILTER
OUT +
OUT -

u

-t-"",,""'--i

_t-"'"""""......- l
TRANSMIT SECTION

VCC +

VCC _

ANLG
GND

DTGL
GND

VDD
IDIGI

PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN - input set is used; however, the auxiliary
input set, AUX IN + and AUX IN -, can be used if a second input is required. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
The gain for the IN +, IN -, AUX IN +, and AUX IN - inputs can be programmed to be either 1, 2, or 4
(see Table 2). Either input circuit can be selected via software control. It is important to note that a wide
dynamic range is assured by the differential internal analog architecture and by the separate analog and
digital voltage supplies and grounds.

AID bandpass filter, AID bandpass filter clocking. and AID conversion timing
The AID high-pass filter can be selected or bypassed via software control. The frequency response of this
filter is presented in the following pages. This response results when the switched-capacitor filter clock
frequency is 288 kHz and the AID sample rate is 8 kHz. Several possible options can be used to attain
a 288-kHz switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the low-pass
filter transfer function is frequency-scaled by the ratio of the actual clock frequency to 288 kHz. The ripple
bandwidth and 3-d8 low-frequency roll-off points of the high-pass section are 1 50 and 100 Hz, respectively.
However, the high-pass section low-frequency roll-off is frequency-scaled by the ratio of the AID sample
rate to 8 kHz.
The Internal Timing Configuration and AIC DX Data Word Format sections of this data sheet indicate the
many options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate
that the RX Counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock
for several Master Clock input frequencies.

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TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
The AID conversion rate is then attained by frequency-dividing the 288-kHz bandpass switched-capacitor
filter clock with the RX Counter B. Thus, unwanted aliasing is prevented because the AID conversion rate
is an integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.

AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.

analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function
of this filter is frequency-scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided
on the output of the (sin x)/x filter to eliminate the periodic sample data signal information, which occurs
at multiples of the 288-kHz switched-capacitor filter clock. The continuous time filter also greatly attenuates
any switched-capacitor clock feedthrough.
The DIA conversion rate is attained by frequency-dividing the 288-kHz switched-capacitor filter clock with
TX Counter B. Thus, unwanted aliasing is prevented because the DIA conversion rate is an integral
submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously
locked.

asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated asynchronously, the low-pass and bandpass filter clocks are independently generated from
the Master Clo.ck signal. Also, the D/A and AID conversion rates are independently determined. If the
transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and bandpass filters. In synchronous operation, the AID conversion timing is derived from, and is equal
to, the DIA conversion timing. (See description of the WORDIBYTE pin in the Pin Functional Description
Section.)

D/A converter performance specifications
Fundamental performance specifications for the DIA converter circuitry are presented in the DIA converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.

system frequency response correction
(Sin x)/x correction for the DIA converter's zero-order sample-and-hold output can be provided by an onboard second-order (sin x)/x correction filter. This (sin x)/x correction filter can be inserted into or deleted
from the signal path by digital signal processor control. When inserted, the (sin x)/x correction filter follows
the switched-capacitor low-pass filter. When the TB register (see Internal Timing Configuration section)
equals 36, the correction results of Figures 11 and 12 will be obtained.

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TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

PRINCIPLES OF OPERATION (continued)
(Sin x)/x correction can also be accomplished by deleting the on-board second-order correction filter and
performing the (sin x)/x correction in digital signal processor software. The system frequency response
can be corrected via DSP software to ± O. 1 dB accuracy to a band-edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of
only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x Correction Section
for more details).

serial port
The serial port has four possible modes that are described in detail in the Functional Pin Description Section.
These modes are briefly described below and in the Functional Description for Pin 13, WORD/BYTE.
1. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320C 1 7.
2. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and the TMS320C30.
3.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS320C 1 7.

4.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift registers,
which can then interface in parallel to the TMS3201 0, TMS320C15, to any other digital signal
processor, or to external FIFO circuitry.

operation of TLC32045 with internal voltage reference
The internal reference of the TLC32045 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. Thus, the internal reference eases the design task and provides complete
control over the performance of the IC. The internal reference is brought out to a pin and is available to
the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor
may be connected between REF and ANLG GND.

operation of TLC32045 with external voltage reference
The REF pin may be driven from an external reference circuit if so desired. This external circuit must be
capable of supplying 250 /LA and must be adequately protected from noise such as crosstalk from the
analog input.

reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function will initialize all AIC registers, including
the control register. After a negative-going pulse on the RESET pin, the AIC will be initialized. This
initialization allows normal serial port communications activity to occur between AIC and DSP (see AIC DX
Data Word Format section).

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5-139

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

PRINCIPLES OF OPERATION (continued)
loopback
This feature allows the user to test the circuit remotely. In loopback, the OUT + and OUT - pins are internally
connected to the IN + and IN - pins. Thus, the DAC bits (d15 to d2), which are transmitted to the OX
pin, can be compared with the ADC bits (d15 to d2), which are received from the DR pin. An ideal comparison
would be that the bits on the DR pin equal the bits on the OX pin. However, in practice there will be some
difference in these bits due to the ADC and DAC output offsets.
The loop back feature is implemented with digital signal processor control by transmitting the appropriate
serial port bit to the control register (see AIC Data Word Format section).
PIN
NAME
ANlG GND
AUX IN+

NO.

I/O

17,18
24

DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.

I

Noninverting auxiliary analog input stage. This input can be switched into the bandpass filter and A/D converter
path via software control. If the appropriate bit in the Control register is a 1, the auxiliary inputs will replace
the IN + and IN - inputs. If the bit is a 0, the IN + and IN - inputs will be used (see the AIC OX Data Word
Format section).

AUX IN-

23

I

Inverting auxiliary analog input (see the above AUX IN + pin description).
This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission

DGTl GND

9

DR

5

0

OX

12

I

Digital ground for all internal logic circuits. Not internally connected to ANlG GND.
of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.
This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.

EO DR

3

0

End of Data Receive. See the WORD/BYTE pin description and Figure 5. During the word-mode timing. this
signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have been transmitted
from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor upon completion
of serial communications. Also, this signal can be used to strobe and enable external serial-to-parallel shift
registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications between the AIC
and the serial-to-parallel shift registers. During the byte-mode timing. this signal goes low after the first byte
has been transmitted from the Ale to the TMS320 serial port and is kept low until the second byte has been
transmitted. The TMS320C17 can use this low-going signal to differentiate between the two bytes as to which
is first and which is second. EODR does not occur after secondary communication.

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TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

PIN
NAME

EODX

NO.
11

I/O
0

DESCRIPTION

End of Data Transmit. See the WORD/BYTE pin description and Figure 5. During the word-mode timing, this
signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control or register
information have been transmitted from the TMS320 serial port to the AIC. This signal can be used to interrupt
a microprocessor upon the completion of serial communications. Also, this signal can be used to strobe and
enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate parallel data-bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this
signal goes low after the first byte has been transmitted from the TMS320 serial port to the AIC and is kept
low until the second byte has been transmitted. The TMS320C 17 can use this low-going signal to differentiate
between the two bytes as to which is first and which is second.

FSR

4

0

Frame Sync Receive. In the serial transmission modes, which are described in the WORD/BYTE pin description,
the FSR pin is held low during bit transmission. When the FSR pin goes low, the TMS320 serial port will begin
receiving bits from the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR
pin before FSR goes low. See Internal Timing Configuration diagram and Figure 5.

FSR does not occur after

secondary communication.

FSX

14

0

Frame Sync Transmit. When this pin goes low, the TMS320 serial port will begin transmitting bits to the AIC
via the DX pin of the AIC. In all serial transmission modes, which are described in the WORD/BYTE pin description,
the FSX pin is held low during bit transmission. See Internal Timing Configuration diagram and Figure 5.

IN+

26

I

Noninverting input to analog input amplifier stage

IN-

25

I

Inverting input to analog input amplifier stage

6

I

MSTR ClK

The Master Clock signal is used to derive all the key logic signals of the AIC, such as the Shift Clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples
of the Master Clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred
between the switched-capacitor filters and the A/D and D/A converters. See Internal Timing Configuration
diagram.

OUT+

22

0

Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a single-ended configuration.

OUT-

21

REF

8

RESET

2

0

Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT +.

I/O The internal voltage reference is brought out on this pin. An external voltage reference can also be applied
to this pin.
I

A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This reset function
initiates serial communications between the AIC and DSP. The reset function will initialize all AIC registers
including the control register. After a negative-going pulse on the RESET pin, the AIC registers will be initialized
to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust
registers, TA' and RA', will be reset to 1. The CONTROL register bits will be reset as follows (see AIC DX
Data Word Format section).

d9

=

1, d7

=

1, d6

=

1, d5

=

1, d4

=

0, d3

= 0,

d2

=

1

This initialization allows normal serial-port communication to occur between AIC and DSP.
SHIFT ClK

10

0

The Shift Clock signal is obtained by dividing the Master Clock signal frequency by four. This signal is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE pin description. See Internal Timing
Configuration diagram and Figure 5.

VDD

7

Digital supply voltage, 5 V ± 5%

VCC+

20

Positive analog supply voltage, 5 V ± fi%

VCC-

19

Negative analog supply voltage - 5 V ± 5 %

TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-141

· '"·:· ·

.~

I

~

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

PIN
NAME
NO.
WORD/BYTE 13

1/0

DESCRIPTION

I

This pin, in conjunction with a bit in the CONTROL register, is used to establish one of four serial modes.
These four serial modes are described below.
Ale transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive sections.
If the appropriate data bit in the Control register is a (see the AIC DX Data Word Format). the transmit and
receive sections will be asynchronous.
Serial port directly interfaces with the serial port of. the TMS320C 17 and communicates in two
L
a-bit bytes. The operation sequence is as follows (see Figure 5).
1. The FSX or FSR pin is brought low.
2. One S-bit byte is transmitted or one S-bit byte is received.
3. The EODX or EODR pin is brought low.
4. The FSX or FSR pin emits a positive frame-sync pulse that is
four Shift Clock cycles wide.
5. One S-bit byte is transmitted or one S-bit byte is received.
6. The EODX or EODR pin is brought high.
7. The FSX or FSR pin is brought high.
Serial port directly interfaces with the serial ports of the TMS32020, TMS320C25, and TMS320C30,
H
and communicates in one 16-bit word. The operation sequence is as follows (see Figure 5):
1. The FSX or FSR pin is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. The FSX or FSR pin is brought high.
4. The EODX or EO DR pin emits a low-going pulse.
Ale 'transmit and receive sections are operated synchronously.
If the appropriate data bit in the Control register is a 1, the transmit and receive sections will be configured
to be synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing will

°

be derived from the TX Counter A, TX Counter B, and TA, TA', and TB registers, rather than the RX Counter
A, RX Counter B, and RA, RA', and RB registers. In this case, the AIC FSX and FSR timing will be identical
during primary data communication; however, FSR will not be asserted during secondary data communication
since there is no new AID conversion result. The synchronous operation sequences are as follows (see Figure 5).
Serial port directly interfaces with the serial port of the TMS320C 17 and communicates in two
L
S-bit bytes. The operation sequence is as follows (see Figure 5):
1. The FSX and FSR pins are brought low.
2. One S-bit byte is transmitted and one S-bit byte is received.
3. The EODX and EO DR pins are brought low.
4. The FSX and FSR pins emit positive frame-sync pulses that are
four Shift Clock cycles wide.
5. One S-bit byte is transmitted and one S-bit byte is received.
6. The EODX and EO DR pins are brought high.
7. The FSX and FSR pins are brought high.
Serial port directly interfaces with the serial ports of the TMS32020, TMS320C25, and TMS320C30,
H
and communicates in one 16-bit word. The operation sequence is as follows (see Figure 5):
1. The FSX and FSR pins are brought low.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. The FSX and FSR pins are brought high.
4. The EODX or EODR pins emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional
NOR and ANq gates, will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to
the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel, data
bus communications between the AIC and the digital signal processor. The operation sequence is the same
as the above sequence (see Figure 5).

TEXAS

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INSTRUMENTS
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TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

INTERNAL TIMING CONFIGURATION

r - - - - - - - - - - - -,

MASTER CLOCK
5.184 MHz 1111
10.368 MHz 121

SHIFT CLOCK
1.296 MHz III
2.592 MHz 121

DIVIDE 8Y 4
_ _ _ _ _ _ _ _ _ _ _ _ .J

------,

DIVIDE BY 2

- - -~~~~Kk~~
- - - - - --,
I
FOR FULL DUPLEX MODEMS

COMMERCIAL
EXTERNAL
FRONT-END
FULL-DUPLEX
SPLIT-BAND
FILTERSt

LOW-PASSI
ISIN XliX
CORRECTION
SWITCHED
CAP FILTER
CLK - 288 kHz
SQUARE WAVE

I

I

I
dO.dl -0.1
dO.dl = 1,0*

I

________ :J

[TA -

9111[

[TA -

1812)[

576-kHz
L..:;16~BI;,;.T.;;.SI:.-_--, PULSES

TX COUNTER B
TB-40; 7.2 kHz
TB - 36; 8.0 kHz
TB-30; 9,6kHz
TB-20; 14.4 kHz
TB-15; 19.2 kHz

DIVIDE BY 2

dO,dl -0,0
dO.dl -1.1

*

dO.dl- 0 ,1
dO,dl· 1 •0

*

RX COUNTER A
IRA 91111
IRA - 18 (2)[
16 BITSI
576-kHz
L,..;,;;..;;.;.;.;;;.;_ _--' PULSES

RX COUNTER B
RB-40; 7.2 kHz
R8 - 36; 8.0 kHz
RB-30; 9.6kHz
RB-20; 14.4 kHz
RB-15; 19.2 kHz

DIA
CONVERSION
FREQUENCY

LOW-PASS
SWITCHED
CAP FILTER
CLK - 288 kHz
SQUARE WAVE

AID
CONVERSION
FREQUENCYI
HIGH-PASS
SWITCHED
CAP FILTER
CLK

____ J

NOTE; Frequency 1. 20,736 MHz. is used to show how 153.6 kHz Ifor a commercially available modem split-band filter clock). popular
speech and modem sampling signal frequencies. and an internal 288-kHz switched-capacitor filter clock can be derived synchronously
and as submultiples of the crystal oscillator frequency _Since these derived frequencies are synchronous submultiples of the crystal
frequency. aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
stages, Frequency 2. 41.472 MHz. is used to show that the AIC can work with high-frequency signals. which are used by highspeed digital signal processors_
tSplit-band filtering can alternatively be performed after the analog input function via software in the TMS320,
*These control bits are described in the AIC OX Data Word Format section.

TEXAS

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5-143

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the AIC and DSP, is
derived by dividing the Master Clock input signal frequency by four.
Low-pass:
SCF Clock Frequency
(D/A or AID Path)

Master Clock Frequency
2 x Contents of Counter A

Conversion Frequency

SCF Clock Frequency (D/A or AID Path)
Contents of Counter B

High-pass:
SCF Clock Frequency
(AID Path)
Shift Clock Frequency

AID Conversion Frequency
Master Clock Frequency

4

TX Counter A and TX Counter B, which are driven by the Master Clock signal, determine the DIA conversion
timing. Similarly, RX Counter A and RX Counter B determine the AID conversion timing. In order for the
low-pass switched-capacitor filter in the DIA path to meet its transfer function specifications, the frequency
of its clock input must be 288 kHz. If the clock frequency is not 288 kHz, the filter transfer function
frequencies are frequency-scaled by the ratios of the clock frequency to 288 kHz. Thus, to obtain the
specified filter response, the combination of Master Clock frequency and TX Counter A and RX Counter
A values must yield a 288-kHz switched-capacitor clock signal. This 288-kHz clock signal can then be
divided by the TX Counter B to establish the D/A conversion timing.
•
The transfer function of the bandpass switched-capacitor filter in the AID path is a composite of its highpass and low-pass section transfer functions. The high-frequency roll-off of the low-pass section will meet
the bandpass filter transfer function specification when the low-pass section SCF is 288 kHz. Otherwise,
the high-frequency roll-off will be frequency-scaled by the ratio of the high-pass section's SCF clock to
288 kHz. The low-frequency roll-off of the high-pass section will meet the bandpass filter transfer function
specification when the AID conversion rate is 8 kHz. Otherwise, the low-frequency roll-off of the highpass section will be frequency-scaled by the ratio of the AID conversion rate to 8 kHz.
TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX
Counter B are reloaded every AID conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers, respectively. Via software control, the TX Counter A can be loaded
with either the TA Register, the TA Register less the TA' Register, or the TA Register plus the TA' Register.
By selecting the T A Register less the T A' Register option, the upcoming conversion timing will occur earlier
by an amount of time that equals T A' times the signal period of the Master Clock. By selecting the TA
Register plus the TA' Register option, the upcoming conversion timing will occur later by an amount of
time that equals TA' times the signal period of the Master Clock. Thus, the DIA conversion timing can
be adv.mced or retarded. An identical ability to alter the AID conversion timing is provided. In this case,
however, the RX Counter A can be progra~med via software control with the RA Register, the RA Register
less the RA' Register, or the RA Register plus the RA' Register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and DIA conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.

TEXAS . "
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TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description).
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and A/D conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA
Register, RA' Register, and RB Registers are not used.

AIC DR or OX word bit pattern
AID or D/A MSB,
1st bit sent

1st bit sent of 2nd byte
D6

AID or D/A LSB
D5

D4

D3

D2

Dl

DO

AIC OX data word format section
COMMENTS

dlSld141d13ld121dlljdl0ld9jdSld71d61dSld41d31d21dlidO
primary OX serial communication protocol
+- d15 (MSB) through d2 go to the D/A

-+

I0

0

The TX and RX Counter A's are loaded with the TA and RA
register values. The TX and RX Counter B's are loaded with TB

converter register

and RB register values.
+- d15 (MSB) through d2 go to the D/A

-+

I0

1

The TX and RX Counter A's are loaded with the T A

+ T A' and

RA + RA' register values. The TX and RX Counter B's are loaded

converter register

with the TB and RB register values. NOTE: dl

~O,

dO ~ 1 will

cause the next DI A and AID conversion periods to be changed
by the addition of T A' and RA' Master Clock cycles, in which
TA' and RA' can be positive or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
+- d15 (MSB) through d2 go to the D/A

-+

I

1

0

converter register

The TX and RX Counter A's are loaded with the T A - T A' and
RA - RA' register values. The TX and RX Counter B's are loaded
with the TB and RB register values. NOTE: dl

~

1, dO ~O will

cause the next DI A and AID conversion periods to be changed
by the subtraction of TA' and RA' Master Clock cycles, in which
TA' and RA' can be positive or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
+- d15 (MSB) through d2 go to the D/A

converter register

-+

I

1

1

The TX and RX Counter A's are loaded with the TA and RA
register converter register values. The TX and RX Counter B's
are loaded with the TB and RB register values. After a delay of
four Shift Clock cycles,

a secondary transmission will

immediately follow to program the Ale to operate in the desired

configuration.
NOTE: Setting the two least significant bits to 1 ill the normal transmission of DAC information (Primary Communications) to the AIC
will initi_ate Secondary Communications upon completion of the Primary Communications.
Upon completion of the Primary Communication, FSX will remain high for four SHIFT CLOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner,
the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents
the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from
skipping a DAC output. It is important to note that in the synchronous mode, FSR will not be asserted during Secondary
Communications.

TEXAS

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5-145

TlC32045C, TlC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

secondary OX serial communication protocol

I - to T A register - I x x I - to RA register I- to T A' register - I x I - to RA' register
I- to TB register - I x I - to RB register

x x
x
x
x

x

x

x

x

x

d9

x

d7 d6 d5 d4 d3 d2
CONTROL

I"

REGISTER

--

I
I
I

0

0

d 13 and d6 are MSBs (unsigned binary)

0

1

d14 and d7 are 2's complement sign bits

1 0
1

d 14 and d7 are MSBs (unsigned binary)

1
0/1 deletes/inserts the A/D highpass filter

d4

=
=
=

d5

=

0/1 asynchronous/synchronous transmit and receive

d6

=
=
=

0/1 gain control bits (see Gain Control Section)

d2

~

d3

0/1 disables/enables the loopback function
0/1 disables/enables the AUX IN + and AUX IN - pins
sections

d7
d9

0/1 gain control bits (see Gain Control Section)
0/1 delete/insert on-board second-order (sin xlix
correction filter

reset function
A reset function is provided to initiate serial communications between the AIC and DSP, The reset function
will initialize all AIC registers, including the control register, After power has been applied to the AIC, a
negative-going pulse on the RESET pin will initialize the AIC registers to provide an 8-kHz AID and D/A
conversion rate for a 5.184 MHz master clock input signal. The AIC, excepting the CONTROL register,
will be initialized as follows (see AIC DX Data Word Format section):
INITIALIZED
REGISTER
VALUE (HEX)

REGISTER
TA
TA'
TB
RA
RA'
RB

9
1
24

9
1
24

The CONTROL register bits will be reset as follows (see AIC DX Data Word Format section):
d9

=

1, d7

=

1, d6

=

1, d5

=

1, d4

=

0, d3

=

0, d2

=

1

This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the Pin Descriptions and AIC DX Word Format
sections).
The circuit shown below will provide a reset on power-up when power is applied in the sequence given
under Power-Up Sequence. The circuit depends on the power supplies' reaching their recommended values
a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC32045

r'Vv:;:c:;:c:-.:+l--.....-- +5 V
0.5

~F

vcc-...--.....- - - 5 V

-1!1

TEXAS
INSTRUMENTS
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TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
power-up sequence
To ensure proper operation of the Ale, and as a safeguard against latch-up, it is recommmended that
Schottky diodes with forward voltages less than or equal to 0.4 V be connected from Vee _ to ANLG
GND and from Vee _ to DGTL GND (see Figure 21). In the absence of such diodes, power should be applied
in the following sequence: ANLG GND and DGTL GND, Vee _, then Vee + and VDD. Also, no input signal
should be applied until after power-up.

AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 1 below.

AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.

TA register must be 2! 4 in word mode (WORD/BYTE =
TA register must be 2! 5 in byte mode (WORD/BYTE =
T A' register can be either positive, negative, or zero.
RA register must be 2! 4 in word mode (WORD/BYTE =
RA register must be 2! 5 in byte mode (WORD/BYTE =
RA' register can be either positive, negative, or zero.
(T A register ± T A' register) must be > 1.
(RA register ± RA' register) must be > 1.
TB register must be > 1.

High).
Low).
High).
Low).

TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
IMPROPER CONDITION
TA register

T A register - T A' register
T A register

AIC RESPONSE

+ T A' register = 0 or 1

=

Reprogram TX Counter A with T A register value

0 or 1

+ T A' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A,
i.e" TA register

RA register

+ RA' register = 0 or 1

RA register - RA' register
RA register

+ RA' register

T A register

=

RA register

=0

=

0 or 1

=0

or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A,
i.e., RA register

<
T A register <
RA register <
RA register <

T A register

+ TA' register + 40 HEX is loaded into TX Counter A.

Reprogram RX Counter A with RA register value

0 or 1

+ RA' register + 40 HEX is loaded into RX Counter A.

AIC is shut down.

or 1

4 in word mode

The Ale serial port no longer operates.

5 in byte mode
4 in word mode
5 in byte mode

TB register

=0

RB register

=

or 1

Reprogram TB register with 24 HEX

0 Or 1

Reprogram RB register with 24 HEX

AIC and DSP cannot communicate

Hold last DAe output

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see following diagram).

TEXAS

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5-147

TLC32045C, TLC320451'
VOICE·BAND ANALOG INTERFACE CIRCUITS

~~~~ELr~
FSX

I

~:R

14-0NGOING CONVERSION-+!

12 - 11 "

I

1/19.2 kHz

asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).

u

FSX

U

I

I

MI'I~-----TRANSMIT

CONVERSION PERIOO-----..,~~I

FSR

I

I

I

~RECEIVE CONV. _ _ _ RECEIVE CONV.--+!

PERIOD A

PERIOD B

asynchronous operation - more than one transmit frame sync .occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the following figure. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent.
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.

TEXAS ~

INSTRUMENTS
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TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

u

U
I

Lr

U

I

I

I

j4-TRANSMIT CONV.~TRANSMIT CONV.-+j4-TRANSMIT CONV. ~
PERIOD A
PERIOD B
PERIOD C

t2

FSRU

Lr

U

I

I

14

~

RECEIVE CONVERSION PERIOD A

I

RECEIVE CONVERSION PERIOD B----1~~1

asynchronous operation - more than one set of primary and secondary OX serial communication
occurring between two receive frame sync (see Ale OX Data Word Format section)
The TA, T A', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).

t,

n . .- - - -. n

PRIMARY

"'l
I

14

SECONDARY

PRIMARY

SECONDARY

TRANSMIT
I
TRANSMIT
CONVERSION----I~
. .- - - - CONVERSION
PERIOD A
PERIOD B

PRIMARY

SECONDARY

Ln
I

~

TRANSMIT
CONVERSION
PERIOD C

L
I

~

1e------"""--- RECEIVE CONVERSION __+IoI
I
....--PERIOD A
~~
RECEIVE CONVERSION PERIOD B,------~~I

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-149

TLC32045C, TLC320451

VOICE·BAND ANALOG INTERFACE CIRCUITS
test modest
The following paragraph provides information that allows the TLC32045 to be operated in special test
modes. These test modes are used by Texas Instruments to facilitate testing of the device during
manufacturing. They are not intended to be used in real applications, however, they allow the filters in
the AID and DIA paths to be used without using the AID and DIA converters.
In normal operation, the non usable (NU) pins are left unconnected. These NU pins are used by the factory
to speed up testing of the TLC32045 Analog Interface Circuit (AIC). When the device is used in normal
(non-test mode) operation, the NU pin (pin 1) has an internal pull-down to - 5 V. Externally connecting
o V or 5 V to pin 1 puts the device in test-mode operation. Selecting one of the possible test or NU modes
is accomplished by placing a particular voltage on certain pins. A description of these modes is provided
in Table 2 and Figures 1 and 2.
TABLE 2. LIST OF TEST MODES
TEST

D/A PATH TEST (PIN 1 to 5 V)

PINS

TEST FUNCTION

5

11
3
27 and 28

AID PATH TEST (PIN 1 to 0)
TEST FUNCTION

The low-pass switched-capacitor filter clock is brought

The bandpass switched-capacitor filter clock is brought

out to pin 5. This clock signal is normally internal.

out to pin 5. This clock signal is normally internal.

No change from normal operation. The ,EODX signal is

The pulse that initiates the AID conversion is brought

brought out to pin 1 1 .

out here. This signal is normally internal.

The pulse that initiates the D/A conversion is brought

No change from normal operation. The EO DR Signal is

out here.

brought out.

There are no test output signals provided on these pins.

The outputs of the AID path low-pass or bandpass filter
(depending upon control bit d2 -

see AIC DX Data

Word Format section) are brought out to these pins. If
the high-pass section is inserted, the output will have a
(sinx)/x droop. The slope of the droop will be determined
by the ADC sampling frequency, which is the high-pass
section clock frequency (see diagram of bandpass or
low-pass filter test for receive section). These outputs
will drive small (30-pF) loads.
D/A PATH LOW-PASS FILTER TEST; PIN 13 (WORD/BYTE) to -5 V
TEST FUNCTION
15 and 16

The inputs of the D/A path low-pass filter are brought out to pins 15 and 16. The D/A input to this filter is removed.
If the (sin x)/x correction filter is inserted, the OUT + and OUT - signals will have a flat response (see Figure 2). The
common-mode range of these inputs must not exceed ±O.5 V.

t In the test mode, the AIC responds to the setting of Pin 13 to - 5 V, as if Pin 13 were set to 0 V. Thus, the byte mode is selected
for communicating between DSP and AIC. Either of the path tests (D/A or AID) can be performed simultaneously with the D/A low-pass
filter test. In this situation, Pin 13 must be connected to - 5 V, which initiates byte-mode communications.

TEXAS . "
INSTRUMENTS
5-150

POST OFFICE BOX 655303 - OALLAS. TEXAS 75265

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

PIN 27 (POSITIVE),
PIN 28 (NEGATlVE)t

TEST CONTROL
(PIN 1 AT 0 V)

FILTER

M
U
X

t

AIO

FIGURE 1, BANDPASS OR LOW·PASS FILTER TEST FOR RECEIVER SECTION

FILTER

M
U
X

M
U
X

(Sin x)/x
CORRECTION

......__ TEST CONTROL
(PIN 13 at -5 V)

PIN 16 (POSITIVE).
PIN 15 (NEGATIVE)t

FIGURE 2, LOW·PASS FILTER TEST FOR TRANSMIT SECTION
t All analog signal paths have differential architecture and hence have positive and negative components,

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-151

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vcc + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Supply voltage range, VDD .......................................... -0.3 V to 15 V
Output voltage range, Vo ........................................... -0.3 V to 15 V
Input voltage range, VI ............................................. -0.3 V to 15 V
Digital ground voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Operating free-air temperature range: TLC32045C . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
TLC320451 ......................... -40°C to 85°C
Storage temperature range ......................................... - 40°C to 125°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC - .

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, VCC + (see Note 2)

PARAMETER

4.75

5

5.25

V

Supply voltage, VCC _ (see Note 2)

-4.75

-5

-5.25

V

4.75

5

5.25

V

2

4

V

2

VOD+O.3
0.8

V

100

pF

Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND

0

Reference input voltage, V reflext) (see Note 2)
High-level input voltage, VIH
Low-level input voltage, VIL (see Note 3)

-0.3

Load resistance at OUT + andlor OUT -, RL
MSTR CLK frequency (see Note 4)

0.075

5

10.368
±1.5

Analog input amplifier common mode input voltage (see Note 5)
AID or DI A conversion rate

20

I TLC32045C
I TLC320451

V

!l

300

Load capacitance at OUT + and/or OUT -, CL

Operating free-air temperature, T A

V

0

70

-40

85

MHz
V
kHz

°c

NOTES: 2. Voltages at analog inputs and outputs, REF, VCC +, and VCC _, are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.
4. The bandpass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and
. the high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the low-pass roll-off frequency
will shift by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF clock is shifted from 8 kHz, the high-pass
roll-off frequency will shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter
(SCF) specifications apply only when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off
frequency will shift by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN+ - IN-) or (AUX IN+ - AUX IN-) equals ±6 V.

TEXAS ."

INSTRUMENTS
5-152

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32045C. TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

electrical characteristics over recommended operating free-air temperature range,
Vee - = - 5 V, voo = 5 V (unless otherwise noted)

Vee +

5

V,

total device, MSTR eLK frequency = 5.184 MHz, outputs not loaded
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD

~

4.75 V,

IOH ~ -300 ~A

VOL

Low-level output voltage

VDD

~

4.75 V,

IOL

ICC+

Supply current from VCC +

ICC-

Supply. current from VCC-

~

MIN

Typt

MAX

2.4

UNIT
V

0.4

2 mA

TLC32045C

40

TlC320451

45

TLC32045C

-40

TlC320451

-45
fMSTR CLK ~ 5.184 MHz

7

V
mA
mA

IDD

Supply current from VDD

Vref

Internal reference output voltage

"V ref
ro

Temperature coefficient of internal reference voltage

200

V
ppm/oC

Output resistance at REF

100

k!l

3.4

2.9

mA

receive amplifier input
TEST CONDITIONS

PARAMETER

MIN

AID converter offset error (filters inl
CMRR

Common-mode rejection ratio at IN +, IN - ,

or AUX IN +, AUX IN-

See Note 6

Input resistance at IN +, IN-

'I

or AUX IN+, AUX IN-, REF

Typt

MAX

10

75

UNIT
mV

55

dB

100

k!l

transmit filter output
TEST CONDITIONS

PARAMETER

MIN

Output offset voltage at OUT + or OUTVOO

(single-ended relative to ANLG GNDI
Maximum peak output voltage swing across

YOM

RL at OUT + or OUT - (single-ended I
Maximum peak output voltage swing between

YOM

OUT + and OUT - (differential outputl

Typt

MAX

15

80

UNIT
mV

RL '" 300 !l,
Offset voltage ~ 0

±3

V

RL '" 600 !l

±6

V

t All typical values are at TA ~ 25°C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with an 8-kHz conversion rate.

i

I.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

i.

I,
5-153

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range, V cc + == 5 V,
VCC- = -5 V, VOO == 5 V lunlessotherwise noted)
system distortion specifications, SCF clock frequency = 288 kHz
TEST CONDITIONS

PARAMETER
Attenuation of second harmonic of

MIN

Vin = -0.5 dB to -24 dB referred to Vref.
See Note 7

single-ended

AID input signal

differential
single-ended

harmonics of AID input signal

differential

Vin =
See Note 7

Attenuation of second harmonic of

single-ended

Vin

Of A input signal
Attenuation of third and higher
harmonics of 01 A input signal

differential

See Note 7

55

single-ended

Vin = - 0 dB to - 24 dB referred to Vref,
See Note 7

55

55

-0.5 dB to -24 dB referred to Vref,

differential

MAX

UNIT

70 .

Attenuation of third and higher

= -

Typt

dB

70
65

55

dB

65
70

0 dB to - 24 dB referred to V ref,

dB

70
65

dB

65

AID channel signal-to-distortion ratio
TEST CONDITIONS

PARAMETER
Vin
Vin
Vin
Vin

AID channel signal-to-distortion ratio

Ay - 1*
MIN MAX

(see Note 7)

Vin
Vin

=
=
=
=
=
=
=
=

Ay - 2*
MIN
MAX
>55§

Ay - 4*
MIN
MAX
>55§

-6dBto -0.1 dB

55

- 1 2 dB to - 6 dB

55

55

>55§

-18 dB to -12 dB

53

55

55

- 24 dB to - 18 dB

47

53

55

-30dBto -24dB

41

47

53

-36 dB to -30 dB

35

41

47

-42 dB to -36 dB

29

35

41

-48 dB to -42 dB

23

29

35

Vin = -54 dB to -48 dB

17

23

29

Vin
Vin

UNIT

dB

DI A channel signal-to-distortion ratio
PARAMETER

TEST CONDITIONS
(see Note 7)
Vin
Vin
Vin
Vin

01 A channel signal-to-distortion ratio

Vin
Vin
Vin
Vin
Vin

=
=
=
=
=
=
=
=
=

MIN

'-6 dB to 0 dB

55

- 1 2 dB to - 6 dB

55

- 18 dB to - 1 2 dB

5.3

- 24 dB to - 18 dB

47

-30 dB to -24 dB

41

-36 dB to -30 dB

35

-42 dB to -36 dB

29

-48 dB to -42 dB

23

-54dBto -48dB

17

MAX

UNIT

dB

t All typical yalues are at T A = 25°C.
Ay is the programmable gain of the input amplifier.
§ A yalue > 55 is over range and signal clipping occurs.
NOTE 7: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V refl. The load impedance for the DAC
is 600 n.

*

TEXAS

~

INSTRUMENTS
6-154

POST OFFICE SOX 655303 • DALLAS. TEXAS 75265

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

electrical characteristics over recommended operating free-air temperature range,
Vee - = - 5 V, voo = 5 V (unless otherwise noted)

vee + ...

5 V,

gain and dynamic range
PARAMETER

TEST CONDITIONS

Absolute transmit gain tracking error while transmitting

- 42 dB to 0 dB signal range,

into 600!l

MIN

See Note 8
- 42 dB to 0 dB signal range,

Absolute receive gain tracking error

See Note 8
Signal input is a - 0.5-dB,

Absolute gain 01 the AID channel

1-kHz sinew ave
Signal input is a O-dB,

Absolute gain 01 the DIA channel

1-kHz sinew ave

Typt

MAX

UNIT

±0.05 ±0.15

dB

±0.05 ±0.15

dB

0.2

dB

-0.3

dB

power supply rejection and crosstalk attenuation
PARAMETER

TEST CONDITIONS
Idle channel, supply signal

V CC + or V CC _ supply voltage

I

=

0 to 30 kHz

rejection ratio, receive channel

I

=

30 kHz to 50 kHz

I

=

0 to 30 kHz

VCC + or VCC _ supply voltage

Typt

at DR (A DC output)
Idle channel, supply signal

=

30 kHz to 50 kHz

at OUT+

Crosstalk attenuation, transmit-to-receive (single-ended)

UNIT
dB

45
30

at 200 mV p-p measured

I

MAX

30

at 200 mV p-p measured

rejection ratio, transmit channel

(single-ended)

MIN

dB
45
80

dB

t All typical values are at T A = 25 DC.
NOTE B: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to V rei).

TEXAS •

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5-155

TLC32045C. TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

delay distortion
bandpass filter transfer function, SCF fclock
PARAMETER

FREQUENCY RANGE

TEST CONDITION
f

Gain relative to

288 kHz IN + - IN - is a

:5

50 Hz

± 3 V sinewave t (see Note 9)

ADJUSTMENT ADDEND*
IK1 x 0 dB

MIN

TYP§

MAX

-33

-29

-25

f = 100 Hz

K1 x - 0.26 dB

-4

-2

-1

f = 150 Hz to 3100 Hz

K1 x 0 dB

0.25

0

0.25

gain at 1 kHz

Input signal

f = 3100 Hz to 3300 Hz

K1 x 0 dB

-0.3

0

0.3

(except passband

reference is 0 dB

f = 3300 Hz to 3650 Hz

K1 x 0 dB

-0.5

0

0.5

ripple

(see Note 9)

f = 3800 Hz

K1 x 2.3 dB

-5

-3

-1

f = 4000 Hz

K1 x 2.7 dB

-20

-17

-16

f ;,: 4400 Hz

K1 x 3.2 dB

-40

f ;,: 5000 Hz

K1 x 0 dB

-65

specification)

low-pass filter transfer function (see curves), SCF fclock
PARAMETER

TEST CONDITION

MIN

TYP§

MAX

K1 x 0 dB

0.25

0

0.25

ADJUSTMENT ADDEND*

f = 3100 Hz to 3300 Hz

K1 x 0 dB

-0.3

0

0.3

gain at 1 kHz

Input signal

f = 3300 Hz to 3650 Hz

K1 x 0 dB

~0.5

0

(except passband

reference is 0 dB

f = 3800 Hz

K1 x 2.3 dB

-5

-3

0.5
-1

ripple

(see Note 9)

f = 4000 Hz

K1 x 2.7 dB

-20

-17

-16

f ;,: 4400 Hz

K1 x 3.2 dB

-40

f ;,: 5000 Hz

K1 x 0 dB

-65

Gain relative to

specification)

dB

288 kHz (see Note 9)

f = 0 Hz to 3100 Hz

FREQUENCY RANGE

UNIT

UNIT

dB

serial port
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH

VOL

Low-level output voltage

IOL

= -300fiA
= 2 mA

MIN

TYP§

MAX

UNIT

0.4

V'
V

2.4
±10

II

Input current

Ci

Input capacitance

15

fiA
pF

Co

Output capacitance

15

pF

t See filter curves in typical characteristics.
t The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result from
inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. If this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where K1 = 100 • [(SCF frequency - 288 kHz)!
288 kHz]. For errors greater than 0.25%, see Note 10.
§ All typical values are at T A = 25°C.
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz for the bandpass and low-pass
filters respectively. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.

TEXAS ~

INSTRUMENTS
5-156

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

operating characteristics over recommended operating free-air temperature range, Vee + '" 5 V,

Vee- -

-5 V, Voo .. 5 V

noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

Typt

TEST CONDITIONS

with (sin x)/x correction
Transmit noise

DX input

without (sin x)/x correction

= 00000000000000,

constant input code

MAX

UNIT

600
450

"V rms
",V rms

530

",V rms

24

Receive noise (see Note 10)

Inputs grounded, gain

=

1

dBrncO

24

dBrncO

timing requirements
serial port recommended input signals
PARAMETER

MIN

MAX

95

UNIT

tclMCLKI

Master clock cycle time

trlMCLKI

Master clock rise time

10

ns

tflMCLKI

Master clock fall time

10

ns

Master clock duty cycle

25%

RESET pulse duration Isee Note 11)
SCLK~

tsulDXI

DX setup time before

thIDXI

DX hold time after SCLK~

NOTES:

ns

75%

800

ns

20

ns

tC(SCLKI/4

ns

10. The noise is computed by statistically evaluating the digital output of the AID converter.
11. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached
their recommended values.

serial port-AIC output signals. Cl - 30 pF for SHIFT ClK output, Cl

=<

15 pF for all other outputs
Typt

MAX

Shift clock ISCLK) fall time

3

8

ns

trISCLK)

Shift clock ISCLK) rise time

3

8

ns

td(CH-FL)

Delay from SCLKt to FSR/FSX/FSD~

30

td(CH-FH)

Delay from SCLKt to FSR/FSX/FSDt

35

90

ns

td(CH-DR)

DR valid after SCLKt

90

ns

tdw(CH-EL)

Delay from SCLKt to EODX/EODR~ in word mode

90

ns

tdwiCH-EHl

Delay from SCLKt to EODX/EODRt in word mode

90

ns

tf(EODX)

EODX fall time

2

8

ns

tfIEODR)

EODR fall time

2

8

ns

tdbICH-EL)

Delay from SCLKt to EODX/EODR+ in byte mode

90

ns

tdb(CH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

90

ns

tdIMH-SL)

Delay from MSTR CLKt to SCLK+

65

170

ns

tdIMH-SH)

Delay from MSTR CLKt to SCLKt

65

170

ns

MIN

PARAMETER
tc(SCL~)

Shift clock (SCLK) cycle time

tf(SCLK)

380

Shift clock ISCLK) duty cycle

tTypical values are at T A

UNIT
ns

45

55

%
ns

= 25 cC.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-157

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

vee +

operating characteristics over recommended operating free-air temperature range,
= - 5 V, voo = 5 V (continued)

Vee -

5 V,

serial port - AIC output signals
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

tc(SCLK)

Shift clock (SCLK) cycle time

tflSCLK)

Shift clock (SCLK) fall time

50

ns

tr(SCLK)

Shift clock (SCLK) rise time

50

ns

380

Shift clock (SCLK) duty cycle

ns

45

55

%

52

ns

td(CH-FL)

Delay from SCLKt to FSR/FSXI

CL = 50 pF

td(CH-FH)

Delay from SCLKt to FSR/FSXt

CL = 50 pF

52

ns

td(CH-DRI

DR valid after SCLKt

90

ns

tdw(CH-El)

Delay from SCLKt to EODX/EODRI in word mode

90

ns

tdw(CH-EH)

Delay from SCLKt to EODX/EODRt in word mode

90

ns

tf(EODX)

EODX fall time

15

ns

tf(EODR)

EODR fall time

15

ns

tdb(CH-EL)

Delay from SCLKt to EODX/EODRI in byte mode

100

ns

tdb(CH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

100

ns

td(MH-SL)

DelaY,Jrom MSTR CLKt to SCLKI

65

ns

td(MH-SHI

Delay from MSTR CLKt to SCLKt

65

ns

tTypical values are at T A = 25°C.

TABLE 3. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL-SCALE AID CONVERSION)
CONTROL REGISTER BITS

INPUT CONFIGURATIONS

d6

d7

1

1

IN + - IN-

a

AUX IN+ - AUX IN-

1

a
a

a

1

1

1

a

Differential configuration
Analog input

=
=

Single-ended configuration
Analog input'

=
=

IN + - ANLG GND
AUX IN + - ANLG GND

ANALOGINPUT*

AID CONVERSION
RESULT

±6 V

full-scale

±3 V

full-scale

±1.5 V

full-scale
half-scale

1

a
a

±3 V
±3 V

full-scale

a

1

±1.5 V

full-scale

*In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.
Rib

Rib

_""'_"'-1
-""',."...._-1
R

R

IN+-_ _"'-I

~ _~TOMUX

R

....

IN--""',.".......-I

AUX IN +

=

FIGURE 3. IN + AND IN - GAIN
CONTROL CIRCUITRY

Rib

=

Rib
Rib

=
=

TO MUX

R lor d6 = 1, d7 '" 1
d6 = 0, d7 = 0
2R lor d6 = 1, d7 = a
4R lor d6 = 0, d7 = 1

FIGURE 4. AUX IN + AND AUX INGAIN CONTROL CIRCUITRY

TEXAS . "
INSTRUMENTS
5-158

r,......

Rib

Rib
R lor d6 = 1, d7 = 1
d6 = 0, d7 = 0
Rib = 2R lor d6 = 1, d7 = 0,
Rib = 4R lor d6 = 0, d7 = 1
RIb

--~

R

AUX IN -

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS

(sin xlix correction section
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can
be accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily
and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved
to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are shown
below, are typical of the numerical correction accuracy that can be achieved for sample rates of interest.
The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns instruction
cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates
of 8000 Hz and 9600 Hz, respectively. This correction will add a slight amount of group delay at the upper
edge of the 300-3000-Hz band.

(sin xlIx roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.
TABLE 4. (sin xl/x ROLL-OFF
20 log sin

fs (Hz I

7200
8000
9600
14400
19200

7r flfs
.. flfs
(f - 3000 Hzl
(dBI
-2.64
-2.11

-1.44
-0.63
-0.35

Note that the actual AIC (sin x)/x roll-off will be slightly less than the above figures, because the AIC has
less than a 100% duty cycle hold interval.

correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is
recommended.

1----------....---+ V(i+ 11

Uti + 11

p1

The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(fIl 2 =

p22 (1 -p1)2
1 - 2p1 cos(2 11" f/fs) + p1 2

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-159

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS

correction results
Table 5 below shows the optimum p values and the corresponding correction results for SOOO-Hz and
9600-Hz sampling rates.
TABLE 5

f (Hz)

300
600
900
1200
1500
1800
2100
2400
2700
3000

ERROR (dB)

ERROR (dB)

fs = 8000 Hz
p1 = -0.14813
p2 = 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

fs = 9600 Hz
p1 = -0.1307
p2 = 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

TMS320 software requirements
The digital correction filter equation C;D
\

-

~
C1

00·07

\

4

---

~-

5R

50 CLK

00-015

WE

OX

5N74L5299

~
\

G-

G1

5N74L5138

00·015

QH

G2

Y1 I - -

A

A1/PA1

51

F5X

C2

5R

Q

10

OR

M5TRCLK
EOOX

FIGURE 6. TMS32010/TMS320C15·TLC32045 INTERFACE CIRCUIT
in instruction timing
ClK OUT _ _oJ

I
I ~I------------------------------1..------+1....·
I

so.

1
1

G1

00-015

(
VAllO
)
----------------------(~~~:I~----------------------~------------

out instruction timing
ClKOUT _ _.....I
I

,

:I~-------------------------------

L...._ _~I.,.,

I

SN74LS138 V1

I

SN74lS299 ClK
I

00-015

(

I
VAllO

)

FIGURE 7. TMS32010/TMS320C15·TLC32045 INTERFACE TIMING

TEXAS . "
INSTRUMENTS
5--162

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC TRANSMIT AND RECEIVE lOW-PASS FILTER

AIC TRANSMIT AND RECEIVE lOW-PASS FilTER

20

3

10
0

\\

-10
III
'tl

.,I

-20

'tl
::l

-30

..
::!:

-40

.l:

C
Ol

E

..

~ 1.5

\
\

-60

SCF clock f = 288 kHz

-70

TA = 25°C
Input - ± 3-V sinewave

o

0.5

1

1.5

2

2.5

c.
o

::l

c:;

~

If
3.5

4

4.5

o

5

0.5

1

1.5

20

10

cD

0
III
'tl

-20

-50

-80

=

288 kHz
8 kHz

= 25°C
Input = ± 3·V sinewave
j
0.5 1 1.5 2 2.5 3 3.5
Frequency - kHz

f- TA

o

5

4

/

-10

I

E -20

'cOl

..

I'

::!: -30

\

=

4.5

V

'tl

\

-40

-70

.,I

1\

low·pass SCF clock f
-60 - High-pass SCF clock f

'"---

4

I

\\

E -30

::!:

3.5

SCF clock f = 8 kHz
TA = 25°C
Input = ± 3-V sinewave

10

'tl

'c
g>

3

Ale RECEIVE-CHANNEL HIGH-PASS FILTER

AIC RECEIVE-CHANNEL BANDPASS FILTER
20

III
'tl

---

2.5

FIGURE 9

FIGURE 8

o

2

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

Normalized Frequency _ kHz x SCF Clock Frequency
288 kHz

-10

\

/

0.5

,..,
3

2

I
>

1\

-50

-80

SCF clock f - 288 kHz

TA - 25°C
2.5 Input = ± 3-V sinewave

-50

Ir

4.5

f

-40

-

-60

5

o

50100150200250300350400450500

Normalized Frequency _ kHz x AID Conversion Rate
8 k samplesls

FIGURE 10

FIGURE 11

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

5-163

TLC32045C; TLC320451

VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL BANDPASS FILTER

AIC (SIN X)/X CORRECTION FILTER
5

Low-pass SCF clock f = 288 kHz
I-- High-pass SCF clock f = 8 kHz
TA = 25°C
Input = ± 3-V sinewave

2.5

SCF clock f = 288 kHz
4.5 r-TA = 25°(:
4 r- Input = ± 3-V sinewave

-

/

/

3.5

"' 2.0

E
I

/

III
"C

>-

I

{\

~ 1.5
:I

~ 1.0

\

-

r--...

0.0
0.5

1

/

L

1.5

l/

I-""

.L

/

;! 2.5
·2
en
2
co
:2

Co

0.5

3

Q)

"C

c

............

/

1'-I--

1.5 2 2.5 3 3.5
Frequency - kHz

4

4.5

0.5

I..-- V

0

5

0.5

1

/
1.5

2

2.5

3

3.5

4

4.5

5

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

FIGURE 12

FIGURE 13
(SIN X)/X CORRECTION FILTER
6

1/

~

INPUT SIGNAL
100

filteV

---

"C

I
Q)

"C

;!
0
·2
en
co
:2 -2

V

V V

-4

r-----. )'-..

n

I--Ttor r r

o

0.5

1 1.5

V

III
"C

I

0

-....

1'--.

T

2.5

.~

a:

f\

c

3

=

r

3.5

4

I

1-kHz1 input s:gnal
8-kHz conversion rate

80
70

50

a

40

10
6

';'

"\

OJ
c
en

1"\
4.5

Cii
5

=

GAIN

0

-

GAIN - 1 X -

60

0

Of

~~

rertej

2

90

error

D/A converter (sin xlix

-6

Xl)/x

correction

2

III

vs

(~in

4

AID SIGNAL-TO-DISTORTION RATIO

"'

V /

30

.,,/

4X

20
10

Normalized Frequency-kHz x SCF Clock Frequency
288 kHz

o

- 50

FIGURE 14

- 40
- 30
- 20
- 10
o
Input Signal Relative to Vref - dB

FIGURE 15

TEXAS

~

INSTRUMENTS
5-164

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

TLC32045C, TLC320451

VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT 0 dB INPUT SIGNAL)
0.5
I
1-kHz input ~ignal
0.4 - 8·kHz conversion rate
0.3
CD

"J"
c

0.2
0.1

:;;

0

(J

.=c'"

~

-0.1

'iii
CI

-0.2
-0.3
-0.4
-0.5
- 50

- 40

- 30

- 20

o

- 10

10

Input Signal Relative to Vref-dB

FIGURE 16

DIA CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL LEVEL
100
1'kH~ input ~ignal in~o 600
90
r- 8.kHz conversion rate
80

ri

CD

"I
0

70

.~

50

OJ
a: 60
c

~

0
0
';'
1&

/"

40

/

30

"

"'\

L

c

CI

in

20
10

~50

-40

-30

-20

-10

o

10

Input Signal Relative to Vref-dB

FIGURE 17

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-165

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
DIA GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL LEVEL)

AID SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
-100

0.5

1-kHz input signal

1-kHz input signal into 600 {)

0.4 - 8-kHz conversion rate

-90 I- 8-kHz conversion rat:..--

'-....

III

i'

0.3

-80

I::

0.1

:;;;
(J
!!

0

I::

-0.1

l-

·f

0.2

III

"J"
c

·iii
C!I -0.2

-- "'

g

is
'Eo

V

.E

-70

~

-60

/'

-50

-40

J:

"I:: -30
o(J
-20

-0.3

'"

til

-0.4

-0.5
- 50

-10
- 40

- 30

- 20

o

- 10

o

10

- 50

Input Signal Relative to Vref-d8

- 40

- 30

FIGURE 18

FIGURE 19
DIA SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL

-100
1-kHz input signal into 600 {)

-90 8-kHz conversion rate
III

i'

-80

c

o -70

'f

~

-60

.~

-50

is

V

/"" r----

......

o

E -40

i;;
J:

" -30
I::
o
~ -20
til

-10

o

- 50

- 40

- 30

- 20

- 10

o

Input Signal Relative to Vref-dB

FIGURE 20

TEXAS . "
INSTRUMENTS
5-166

- 20

- 10

o

Input Signal Relative to Vref-dB

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

10

10

TLC32045C, TLC320451

VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID THIRD HARMONIC DISTORTION

vs
INPUT SIGNAL
-100

I

1 ·kHz input signal

-90 r- 8-kHz conversion rate

~ -80

~~

I

g

-70

'f
~ -60
is
o

'co

/'

/

~-

-50

E -40

co

J:

"E

:cI-

-30
-20
-10

o

- 50

- 40

- 30

- 20

o

- 10

10

Input Signal Relative to Vref-dB

FIGURE 21
D/A THIRD HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
1- kHz input signal into 600 fl

-90 8-kHz conversion rate
~ -80
I

g -70

.~

ti -60
is
0-

'c

~

/'"

-

~

\

50

~ -40
co

J: - 30

"E

~ -20
-10

o

- 50

- 40

- 30

- 20

- 10

o

10

Input Signal Relative to Vref-dB

FIGURE 22

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

5-167

TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
TYPICAL APPLICATION INFORMATION
TLC32045

TMS32020/C25
ClKOUT "'--'---1 MSTR ClK
FSX
FSX

ox

ox

FSR
DR

FSR
DR

ClKR

VCC+ . . . - - - - - - - - -.....- + 5 V
REF t---1.....".-,
C
ANlG GND . . . - - -.....- - - - -...
VCC-~--~--.....-

SHIFT ClK

VOD~-~----

ClKX
OGTlGND~-~---~

C - 0.2

~F.

CERAMIC

FIGURE 23. AIC INTERFACE TO THE TMS32020/C25 SHOWING DECOUPlING CAPACITORS AND
SCHOTTKY DIODE
VCC

R
..----.~-....- - - - 3-V

OUTPUT

Tl431'A--4

FOR:

VCC - 12 V. R - 7200
VCC - 10 V. R - 5600
VCC - 5 V. R - 1600

n
n
n

FIGURE 24. EXTERNAL REFERENCE CIRCUIT FOR TLC32045
tThomson Semiconductors

TEXAS . "
INSTRUMENTS
5-168

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32046
WIDE·BAND ANALOG INTERFACE CIRCUITS

See the TLC32046 Wide-Sand Analog Interface Circuits Data Manual in Section 9 for
product information.

TEXAS .J.!1

INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-169

5--170

TLC32047
WIDE-BAND ANALOG INTERFACE CIRCUITS

See the TLC32047 Wide-Band Analog Interface Circuits Data Manual in Section 9 for
product information.

TEXAS •

INSTRUMEN1S
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5--171

5-172

TLC32071
HIGH·SPEED a·BIT AID AND DIA CONVERTER
WITH a·CHANNEL MULTIPLEXER
DECEMBER 1991

•
•

a-Bit Analog-to-Digital Converter

•

a-Bit Digital-to-Analog Converter

•

Monotonic Over Entire Analog-to-Digital
and Digital-to-Analog Conversion Range

•

a-Input Analog Multiplexer with Latched
Channel Select

Advanced LinCMOS'" Technology

NPACKAGE
(TOP VIEW)

•

Programmable Input Range on Two Input
Amplifiers

•

Interfaces Directly to Many Digital Signal
Processors Including the TMS320 Family

•
•

Low-Glitch Impulse at DAC Output

ANAOUT
RESET
CSAN
CSCNTRL
OEN

REF
Vcc
A2
ANLG COM
AS

1

A4

07
06
05
04
03
02
01
00

A3
A1
A7
AO
A6

ANLG GNO
OGTL GNO
VDD

Built-In Scaling and Level Shifting on Six of
the Analog Inputs

•

FN CHIP CARRIER PACKAGE
(TOP VIEW)

Designed for Servo-Loop Control Systems
Including Disk Drives

description
The TLC32071 is an analog interface integrated
circuit that converts between the analog and digital
domains. The device includes an 8-bit
voltage-output digital-to-analog converter (DAC),
an a-bit analog-to-digital converter (ADC) , an
analog input multiplexer with eight analog inputs,
an output reference MUX, and a high-speed a-bit
bidirectional data bus that interfaces directly to the
TMS320 family of digital signal processors. The
reset input (RESET) is used to clear the DAC and
control registers. The a-bit DAC converts digital
signals to the equivalent analog values. The DAC
is followed by a level shifter, which adjusts the
center of the DAC output range to the voltage
externally applied to the ANLG COM input. One of
three output ranges can be selected by an internal
register.

5

4

321

2827 26
25

6

06
05
04
03

24

ANLG COM
AS

7

23

A4

8

22

A3
A1
A7
AO

9

21

10

20

11
19
12131415161718
C\J~OOOO«)

OOO_ozz~

:::>C!lC!l
-'C!l
f--,
C!lz
o~

The 8-bit ADC converts anyone of eight analog inputs selected by a programmable internal register through
an input multiplexer. Six of these have inverting inputs with built-in level shifting so that these six output ranges
are centered at the ADC input voltage midpoint. Two of the six inputs have register selectable gains. The first
conversion result after selection of one of the six inverting inputs should be discarded as invalid. The two
remaining inputs are direct inputs to the ADC multiplexer with output ranges centered at the internal 2.5-V
reference (Vref). After reset, this reference is available at the REF output. The REF output can also be
programmed by an internal control register to provide access to other internal references, any of the analog
inputs after scaling and shifting, or the unsealed output of the DAC.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products
eonform to specifications per the terms of Texas Instruments standard

warranty. Production processing does nol necessarily include testing of all

parameters.

TEXAS ~

Copyright © 1991, Texas Instruments Incorporated

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-173

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
functional block diagram
14-7

8

00-07

j

00-07

'---

CSCNTRL
CSAN
WE
OEN
RESET

4
3
6
S

8

Oigltal
I/O
Control

OAC

c-Start
AlO

t

~

~version

rxrl:f

O/A Vreference

1

1

Output
Range
Select

ANAO UT

Enable
Oigital
Loopback

PS,06

2
Range/AOC
MUX
Control
Register

~
00-06

~

1
06

3

~01

8

AO

A3

Input
Range
Select

S
2

2

AS
A6
A7

3

3

02-04

~
~

A4

REF
MUX Control
Register

02-06

~

Al
A2

1

19

I
3

23

REF
MUX

8
00-07

~

'--'---

AOC
MUX

24

Vref(2.S V nom)

~~

AOC

+

18
20

Bandgap

AlO Vreference
100kQ

Reference
Voltage
Generator

r--

r--

100 kQ
To
25
ANLG COM 27
VCC -"15'---

Inp~~

Amplifiers

VOO 17

~~~~ ~~~ -'-1.!..S-All resistor values shown are nominal.

TEXAS •

INSTRUMENTS
5-174

POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

.--.--

~

REF

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
equivalents of analog input circuit
ANALOG INPUT

Vcc

1
Rl

.,.AO

=200 kQ
AS,

"""'---1

A7

l

R

= 100 kQ (Typ)

2.SV
ANLG GNO vrt

t Vr
Vr

ANLG GNO

is an internally generated voltage with the following typical values: at range ~ 1, Vr ~ 3.33 V; at range ~ 1/2, Vr ~ 3.75; at range ~ 1/4.
4.167 V.

~

equivalent of digital input circuit

00-07 and
Control Inputs

OGNO
OGNO

TEXAS •

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-175

TLC32071
HIGH·SPEED a·BIT AID AND DIA CONVERTER
WITH a·CHANNEL MULTIPLEXER
Terminal Functions
PIN
NAME

NO.

DESCRIPTION

I/O

1

a

ANLG COM

25

I

ANLG GND

17

ANAOUT

Analog Output. The DAC output with selectable ranges.
Analog Common. Input for reference voltage for inverting analog inputs.
Analog Ground. Ground connection associated with ADC, DAC, and other analog circuits.

AO

19

I

A1

21

I

A2

26

I

A3

22

I

A4

23

I

A5

24

I

A6

18

I

A7

20

I

as a signal ground.

CSAN

3

I

Chip select for writing to the D/A converter and reading the results of an AID conversion.

CSCNTRL

4

I

Chip select for the control register, which selects DAC and ADC ranges and the analog input channel.

DEN

5

I

Read strobe for the AID converter OUtput. Output buffers are enabled when this signal is held low.

DGTLGND

7-1

RESET

Auxiliary non inverting analog input with input range of 0.5 to 4.5 V. This input uses the internal reference VR2.5

I/O

Bidirectional Data Bus. This bus is used for writing conversion data to the DAC, writing data to the range/ADC
MUX control register or to the REF MUX control register, and for reading the ADC conversion result.

2

I

Reset. This strobe, when low, clears the range/ADC MUX control register, the REF MUX control register, and
the DAC input register. CSCNTRL and CSAN should be held high during a reset operation.

28

a

2.5-V Reference Output. The signal routed to this ~in is determined by the contents of an internal register (see
CSCNTRLdata word description). The internally generated 2.S-V reference may be selected for use in biasing
inputs A6 and A7.

4

REF

Inverting Analog Input. This input uses ANLG COM as a signal ground.

Digital Ground. Ground connection associated with digital data-bus signals and other digital circuits.

16

D7-DO

Inverting Analog input with range programmable to 8, 4, or 2 V. This input uses ANLG COM as a signal ground.

VDD

15

VCC
WE

27
6

5-V (digital) supply

a-v (analog) supply

1
I

Write Enable. This input is a write strobe for the control registers and the DAC input register. Data is latched
on the rising edge of this signal.

TEXAS ~

INSTRUMENTS
5-176

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32071
HIGH·SPEED a·BIT AID AND DIA CONVERTER
WITH a·CHANNEL MULTIPLEXER
PRINCIPLES OF OPERATION
writing control words to the TLC32071
With the CSCNTRL input low, a control word is written to the TLC32071 by placing data on the D7-DO inputs
and applying a low-going pulse to the write enable input (WE). Data is latched on the rising edge of the WE pulse.
The values of DO and D1 of the control word determine whether the data is latched in the range/ADC MUX control
register or the REF MUX register. See Tables 1, 2, 3, and 4 for data-bit formats.

operation of the ADC channel
Analog-to-digital conversion begins when gain-select and channel-select data word is latched in the range/ADC
MUX control register by the rising edge of the WE pulse. This data word controls the state of the range/ADC input
multiplexer. After the conversion time, the conversion result may be read by taking the DEN input low while the
CSAN input is low. Writing of data to the REF MUX control register (using CSCNTRL and WE with DO and D1
both 0) does not start a conversion. Each time one of the AO through A5 signal channels is selected, the first
conversion result after selection should be ignored due to internal input amplifier settling time. If this channel
remains selected, subsequent conversions are valid.

operation of the DAC channel
When the CSAN input is low, digital-to-analog conversion is performed by placing input data on data bus
DB7-DBO and applying a low-going pulse to WE. The data word is latched on the rising edge of the WE pulse
and is decoded to an equivalent analog voltage. The conversion occurs internally in approximately 100 ns with
the D/A conversion result available at the ANAOUT output after a specified settling time.

digital loopback mode
Digital loop back enables the simultaneous testing of the ND and D/A channels. When digital loop back is
enabled, the A/D conversion result is transferred to the D/A input latches on the next rising edge of DEN. The
analog signal from the input pin at the ND converter is transferred through the D/A converter to the analog output
ANAOUT. To enable digital loop back, write to the REF MUX control register (see data word format in Table 3)
to set bit D6. Then, perform ND conversion (as in normal operation) by writing channel select and range select
information to the range/ADC MUX control register. This is done by strobing WE while CSCTRL is low. Read
the conversion result by strobing DEN while holding CSAN low when digital loop back is enabled. The ND
conversion result is transferred to the DAC on the rising edge of DEN (See Tables 1, 2, 3, and 4).

reset operation
CSAN and CSCNTRL should be held high during a reset operation. When the RESET input is taken low, the
internal reset signal clears the range/ADC MUX control register, the REF MUX control register, and the DAC
input register. The following conditions exist after reset:
1. The DAC output is set to the voltage at the ANLG COM input.
2. The DAC range is set to ANLG COM ±4 V.
3. The AO analog channel is selected and the AO and A 1 amplifier ranges are set to ANLG COM ±4 V.
4. The 2.5 V reference is selected at the REF output.
5. Digitalloopback is disabled.

analog inputs
The ANLG COM voltage establishes the operating midpoint of the input amplifiers, AO through A5. When the
input signal voltage equals this voltage, the ADC output is ideally digital count zero. These amplifiers level shift
to the ADC midpoint of 2.5 V and scale the input voltage range to the ADC range of 0.5 to 4.5 V. The A6 and
A7 noninverting inputs are centered at the 2.5 V internally generated voltage reference and are connected
directly to the input MUX. Table 5 gives the full scale input range and the midpoint voltages applicable for the
individual analog inputs.

TEXAS l!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-177

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
Table 1. Data Word Formats (Channel Range Selection)
Dl

DO

L

L

AO/Al CHANNEL
No range selection

L

H

Range is set to 1

H

L

Range is set to 1/2

H

H

Range is set to 1/4

INPUT FULL SCALE RANGE

DATA DESTINATION

PROGRAMMABLE GAIN

(ANLG COM=5)

MIN

Higher-order bits are sent to ADC channel-select register

ANLG COM %4 V

1V

9V

ANLG COM ",2V

3V

7V

ANLGCOM±1 V

4V

6V

Table 2. Data Word Formats (RANGE/ADC-Multiplexer Channel Selection)
(Data chosen from this table is only valid when data bits 01 and DO are not both low)
SELECTED CHANNEL

D7

D6

D5

D4

D3

AO

X

X

X

L

L

D2
L

A1

X

X

X

L

L

H

A2

X

X

X

L

H

L

A3

X

X

X

L

H

H

A4

X

X

X

H

L

L

A5

X

X

X

H

L

H

A6

X

X

X

H

H

L

A7

X

X

X

H

H

H

Table 3. Data Word Formats (DAC Output Range Selection)
(Data chosen from this table is only valid when data bits 01 and DO are not both low)
OUTPUT FULL SCALE RANGE
D6

D5

DAC OUTPUT RANGE

L

X

H
H

(ANLG COM=5)

MIN

Range is set to 1

ANLG COM ",4V

1V

MAX

9.V

L

Range is set to 1/2

ANLG COM ±2V

3V

7V

H

Range is set to 1/4

ANLG COM ±1 V

4V

6V

Table 4. Data Word Formats (REF-Multiplexer Channel Selection)
(Data chosen from this table is valid only when data bits 01 and DO are both low)
D6

D5

D4

D3

Vref (2.5 V nom)
Bandgap (ACOM + 1.25 V)

X

X

L

L

L

X

X

L

L

H

ND reference (approximately 4.6 V)

X

X

L

H

L

D/A reference (ANLG COM -3 V)

X

X

L

H

H

AO amp output t

X

X

H

L

L

A 1 amp output t

X

X

H

L

H

ADC MUX output t

X

X

H

H

L

DAC level shift output*

X

X

H

H

H

Enable digitalloopback

H

X

X

X

X

SELECTED CHANNEL

D2

. .
..
t These signals are outputs of scallng~evel-shlftlng
amplifiers. The range of
these signals is Vref ±2 V.
* The unsealed output of the DAC. This analog output is proportional to the
DAC value with a fixed range of ANLG COM ± 1 V. but inverted relative to
the twos-complement code written to the DAC.

TEXAS

~

INSlRUMENlS
5-178

MAX

Higher·order bits are sent to REF-MUX register

POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CQNVERTER
WITH 8-CHANNEL MULTIPLEXER
Table 5. Analog Input Characteristics
INPUT VOLTAGE RANGE
INPUT
AD, AI§

(I)
(1/2)
(1/4)

A2 thru A5§

NOMINAL
FSR*

Vmid t

(ANLG COM=5)
MIN

MAX

ANLG COM
ANLG COM
ANLG COM

±4 V
±4 V
±4 V

1V
3V
4V

9V
7V
6V

ANLG COM

±4 V

1V

9V

±2V
0.5 V
4.5 V
Vref~
tVmid is (VPI27-VMI27)oI27.5/254+VMI27 where VPI27 is the minimum input
voltage to produce an output code of + 127, and VMI27 is the minimum input voltage
to produce an output code of -127.
t Full-scale range is (VPI27-VMI27)o256/254 where VPI27 is the minimum input
voltage to produce an output code of + 127, and VMI27 is the minimum input voltage
to produce an output code of-127.
§ Inverting inputs
~ V ref is an internally generated reference voltage that can be available at the REF output.
The inputs A6 and A7 are connected to Vrefthrough an on-chip resistor.
A6,A7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (analog supply) (see Note 1) ............................... -0.5 V to 14 V
Supply voltage range, Voo (digital supply) (see Note 2) ................................. -0.5 V to 7 V
Digital ground voltage range, DGTL GND ........................................... -0.5 V to 0.5 V
Analog output voltage range (see Note 1) ..................................... -0.5 V to V1 0 + 0.5 V
Analog input voltage range (see Note 1) ............................................. -0.5 V to 14 V
Digital output voltage range (see Note 2) ........................................ -0.5 V to VS + 0.5 V
Digital input voltage range (see Note 2) ......................................... -0.5 V to VS + 0.5 V
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C
NOTES: I. All voltage values are given with respect to ANLG GND unless otherwise noted.
2. All voltage values are with respect to DGTL GND.

TEXAS

~

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-179

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
recommended operating conditions
MIN

NOM

MAX

Supply voltage, VCC

9

10

12

V

Supply voltage, VDD

4,5

5

5,5

V

High-level input voltage, VIH (digital inputs)

2.4

V
0,5

Low-level input voltage, VIL (digital inputs)
Reference voltage input at ANLG COMt input, Vref

3.5

Setup time, CSCNTRL low before WE low, tsu(CS)
Hold time, CSCNTRL high after WE high, th(CS)

UNIT

5

6

V
V

0

ns

0

ns

Setup time, data bus before CSCNTRL high, tsu(D)

15

ns

Hold time, data bus after CSCNTRL high, th(D)

15

ns

ta;

ns

Pulse duration, DEN, tw(DEN)
Setup time, CSAN low before DEN low, tsu(CS)

0

ns

Hold time, CSAN high after DEN high, tt'llCS)

0

ns

Setup time, CSAN low before WE low, tsu(CS)

0

nS

Hold time, CSAN high after WE high, thICS)

0

ns

Pulse duration, RESET, tw(RE)

25

ns

Pulse duration, WE, tw(WE)

30

ns

0

Operating free-air temperature, T A

70

°c

t For a DAC range of R = (1, 1/2, 1/4), ANLG COM should be chosen so that ANLG COM ±4R IS greater than 0.5 V and less then VCC -0.5 V
or the DAC output may not be able to deliver the specified maximum current without voltage-limiting occurring.
; Access time

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD at 4.5 V,

10H =-360 jlA

VOL

Low-level output voltage

VDD at4.5V,

10L = 1.6 mA

Vref

Reference voltage output (see Note 3)

ANLG COM = 5 V

RO(ref)

Reference output resistance

ANLG COM = 5 V

IIH

High-level input current

VIH = 5 V

IlL

Low-level input current

VIL=O

IDD

Supply current, digital

DO-D7 at VIH or VIL

ICC

Supply current, analog

10Z

Off-state output current (high-impedance state)

MIN

TYP9

2.42

2.5

2.58

0.8

1.2

Co

Va =0
Output capacitance (digital outputs)

TEXAS "!1

INSlRUMENTS
5-180

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

V
kQ

10

jlA
jlA

20

mA

22

mA
jlA

-3
25

40

-45

-60

mA
5

§ All tYPical values are at T A = 25°C.
NOTE 3: This voltage is an internal reference voltage (2.5 V) that is available at the output-multiplexer output.

V

-10

3

Va =5V
Va =5V

Short-circuit output current

UNIT
V

0.4

Va =0
lOS

MAX

2.4

pF

TLC32071
HIGH-SPEED a-BIT AID AND DIA CONVERTER
WITH a-CHANNEL MULTIPLEXER
ADC operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

MAX

Linearity error
VI(FS)t

Input voltage for full-scale output code
(Input channel =A6 or A7)

±1
3.92

=A6 or A7)

Vmid*

ADC input offset voltage (Input channel

tconv

Conversion time

See Figure 2

ta

Access time (delay from falling edge of DEN to data output)

See Figure 3

Disable time (delay from rising edge of DEN to
high-impedance state of data output)

Vref+0.06
2.5

CL

tdis

4.08

Vref-0.06

See Figure 3

=100 pF~

UNIT
LSB
V
V
flS

50

CL = 50 pF§

41

CL

=25 pF~

37

CL

=100 pF

35

ns

ns

t Full-scale range is (VP127-VM127) ° 256/254 where VP127 is the minimum input voltage to produce an output code of + 127, and VM127 is the
minimum input voltage to produce an output code of -127.
* Vmid is (VP127-VM127) ° 127.5/254 + VM127 where VP127 is the minimum input voltage to produce an output code of +127, and VM127 is
the minimum input voltage to produce an output code of-127.
§ CL is in addition to the internal capacitance of the digital output.

DAC operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ts

Settling time (to 1 LSB)

EL

Linearity error

TEST CONDITIONS
Load on ANAOUT
(to ANLG COM)

MIN

B

Code width

0.25

Output voltage swing#,
VO(FS)

full scale

DAC input = -12B to + 127

10M

DAC input

=0

MAX
15

fls
LSB

1.75

LSB

7.B4

B

3.92

4

4.0B

Range = 1/4

1.96

2

2.04

B.16

Range

=1

ANLG
COM-O.OB

ANLG
COM+O.OB

Range

=1/2

ANLG
COM-0.06

ANLG
COM+0.06

Range = 1/4

ANLG
COM-0.05

ANLG
COM+0.05

=30 kHz

Glitch energy

Sample rate

Maximum output current,
ANAOUT

Source from VCC-0.5 V or sink from
0.5V

1.2
1.2

UNIT

±1

=1
Range = 1/2
Range

(VP127-VM12B) ° 256/255

Output bias level#, full scale
(VP127-VM128) ° 128/255+VM128

TYP~

=20 pF + 5 kQ

V

V

mV
mA

~ TYPical values are at TA = 25'C.
#VP127 is the voltage output for an input code of +127. VM128 is the voltage output for an input code of -128.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-181

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
ADC electrical characteristics for inputs AO and A1 ove.r recommended operating free-air
temperature range (unless otherwise noted)
PARAMETER

Avl

Voltage amplification

Av2

Voltage amplification

Ay4

Voltage amplification

VOSl
VOS2
VOS4

r;

TEST CONDITIONS

=1
Range = 1/2
Range = 1/4
Range

Output bias voltage at input of ADC with respect to
Vref
Output bias voltage at input of ADC with respect to
Vref
Output bias voltage at input of ADC with respect to
Vref
Input resistance

MIN

TYP

MAX

UNIT

0.99

1

1.01

VN

1.98

2

2.02

VN

3.96

4

4.04

VN

=1

0

±0.02

V

VI

=V(ANLG COM).

Range

VI

=V(ANLG COM).

Range

= 1/2

0

±0.03

V

VI

=V (ANLG COM).

Range

= 1/4

0

±0.05

V

200

260

kQ

140

ADC electrical characteristics for inputs A2, A3, A4 and AS over recommended operating free-air
temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

Av

Voltage amplification to ADC

VOS

Output bias voltage at the input of the ADC with respect to Vref

r;

Input resistance

VI = VCANLG COM)

MIN

TYP

MAX

-0.495

-0.5

-0.505

-0.02

0

+0.02

.V

140

200

260

kQ

UNIT

VN

ADC electrical characteristics for inputs AS and A7 (direct inputs) over recommended free-air
temperature range (unless otherwise noted)
TEST CONDITIONS

PARAMETER

Av

Voltage amplification to ADC

ri

Input resistance (to REF)

TYP

MAX

1
70

TEXAS

~

INSTRUMENTS
5-182

MIN

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

100

UNIT

VN
130

kQ

TLC32071
HIGH·SPEED a·BIT AID AND D/A CONVERTER
WITH a·CHANNEL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION

*-

---.!
CSCNTRL

th(CS)

50%} ...._ _ _ _ _-fV5o%

--------~I

I~-------------

~50%

00-07

,fSO%

tsu(CS) ~ ~

~

----(

I

.1 tsu(O)
-.t t.- th(O)

J>-----

Figure 1. Write Operation
CSCNTRL

\,----,,1
\,-------,1
\

I

______________

00-07

~ tw(OEN) ---+1

'---" I

1

!:~~::::~t~co~n~v~::::~.:

50%~

1

:

r------

~50%

--------~('------~)~----------------~(~----~~
MUX Address and Gain Control

Analog-to-Digital Conversion

Figure 2. AID Conversion Cycle
---.!

*- tsu(CS)

---------. I 1

50%\1

50 %

1

lr~-o%-O---------

-----------\50%
1

00-07

14- th(CS)
I ,..-----------

------Y:1
1

'-I

ta

---.!

I"

1

.:

-4j ~ tdls

------------~(~I____~)~--------Figure 3. AID Read Operation

TEXAS

-1!1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5--183

TLC32071
HIGH·SPEED 8·BIT AID AND DIA CONVERTER
WITH 8·CHANNEL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
-.I ~
1I

~ I+-- th(CS)
II
I 1,-_ _ _ _ _ __

tsu(cs)

_ _ _ _.... 1 1
50%

V

~

- - - -......

50%

~

tw(WE)

50%\

--l ,..-------/(50%

_

_ ___

:t

t-J-~

_ _ _ _ _ _V...;..(A_N_LG_CO_M....;.)_-_-_......

~ts~

ANAOUT

Figure 4. D/A Conversion Operation
IDEAL AID OUTPUT CODE

vs
INPUT VOLTAGE

F~R =tdv

=

I

127 I- TA 25°C
1 LSB FSR/256
126

-8

<3
'5

.e-

o"
o

~

=

••
•
0

.••

-1

I
/'

-126

-128

I
A

I
•••

I

J

=Vmid -127.5 x (FSR/256)
=Vmid -0.5 x (FSR/256)
= Vmid
0= Vmid + 0.5 x (FSR/256)
E = V rpid +126.5 x (F!1R/25p)

A
B
C

I I I

•••

BCD
VI - Input Voltage - V

Figure 5

TEXAS ~

INSlRUMENlS
5-184

J

1/

1

-127

,"

I

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

E

±1 LSB

TLC32071
HIGH-SPEED 8-BIT AID AND D/A CONVERTER
WITH 8-CHANNEL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
IDEAL DIA OUTPUT VOLTAGE

vs
INPUT CODE
ANLG COM + 127 x (FSR/256)

~SR=12.4.~V I
ANLG COM + 126 x (FSR/256) '-- TA = 25'C
1 LSB = FSR/256

/'

,,>

.
I

01

J!!

~

:;
Co
:;

ANLG COM +1 x (FSR/256)

,-

ACOM

,-,-

,-

,-

ANLG COM -1 x (FSR/256)

,-,-

o

ANLG COM -126 x (FSR/256)

/'

ANLG COM -127 x (FSR/256)

,-

/'

1/

./

,-'-

ANLG COM -128 x (FSR/256)
-128 -127

-1

0

126 127

Input Code

Figure 6

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-185

TLC32071
HIGH-SPEED 8-BIT AID AND DIA CONVERTER
WITH 8-CHANNEL MULTIPLEXER
APPLICATION INFORMATION

To
Host

To/From Disk Heads

Figure 7. Simplified Disk-Drive Controller

TEXAS

.J!1

INSlRUMENlS
5-186

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ge·ne~a.I • •I··6fo..m~ti·Orl··
••
:::::G;::e;:;r';:;e;::ra;:;I;::.p;::
•.u;:;?r;::po;:;?s;:;.e;:;·• ;::[j;:;C;:;.··.~;:;;:;;:;;:;;:;;:;;:;;:;;:;;:;;:;;:;;:;;:;;;::::EI
A:::.·.···
•. · •...•

·.~: :ra: :I:;:. R: :(U:;:· ·.r: :p: :o: :.·.~·=.~·.·: :P: :.A:G::::•· .• ~:;:.•·. :::::::::::::::::::::::::::::::::::::::::::::;::111

:::::G:::.e=n:::
..

'li.~.•~Q·~il~i.f-I.•ig··tl..~p~·~.•~.·•·•·~·g~~<~I'1.~• ·• Q~g~r·

6-1

_.
<

0----1"------1

GREEN
VALUE
BLUE
VALUE

'TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC34058
256 x 24 COLOR PALETTE

Terminal Functions
PIN NAME

DESCRIPTION

110

Composite blank control. This TTL-compatible blanking input is stored in the input latch on the rising edge of lD.

BlK
I

When low, BlK drives the DAC outputs to the blanking level, as shown in Table 6. This causes the PO-P7 [A-E] and
OlO-Oll [A-E] inputs to be ignored.
When high, BlK allows the device to perform in the standard manner.

SYNC

Composite sync control. This TTL-compatible sync control input is stored in the input latch on the rising edge of "["0.
I

When low, SYNC turns off a 40 IRE current source on the lOG output, as shown in Figure 3. This input does not override any
control data input, as shown in Table 6. It should be brought low during the blanking interval only, as shown in Figure 3.
When high, SYNC allows the device to perform in the standard manner.
load control. This TTL-compatible load control input latches the PO-P7 [A-E], OlO-OL1 [A-E], BlK, and SYliIC inputs on its

IlO
I

rising edge. The lD strobe occurs at 1/4 or 115 the clock rate and may be phase independent of the ClK and ClK inputs.
The LO duty cycle limits are specified in the timing requirements table.
Address inputs. These TTL-compatible address inputs for the Palette RAM are stored in the input latch on the rising edge of

POA-P7A

LD. These address inputs (up to 8-bits per pixel) select one of 256 24-bitwords in the palette RAM, which is subsequently input

POB-P7B
POC-P7C
POD-P7D

I

POE-P7E

to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Fouror five addresses are simultaneously input to the
PO-P7 [A-D] or PO-P7 [A-E] ports, respectively (see the description of bit CR7 in the command register section). The word
addressed by POA-P7A is first sent to the DACs, then the word addressed by POB-P7B, and so on. Unused inputs should be
connected to GND.

OlOA-AL1A

Overlay selection inputs. These TTL-compatible selection inputs for the Palette overlay registers are stored in the input latch

OLOB-OL1B

on the rising edge of LD. These inputs (up to 2 bits per pixel), along with bit CR6 of the command register (referlO the command

OlOC-OL1C

register section and Table 5), specify whether the color information is selected from the palette RAM or the overlay registers.

If the color information is selected from the overlay registers, the OlO-OLl [A-E] inputs address a particular overlay register.

OlOD-OL1D
OLOE-OL1E

I

The OlO-OLl [A-D] or OLO-OLl [A-E] inputs are simultaneously input to the device (see the description of bit CR7 in the
command register section). The OLO-OLl [A-E] inputs are simultaneously input to the device (see the description of bit CR7
in the command register section). The OLO-Oll [A] inputs are processed first, then the OlO-Oll [B] inputs, and so on. When
obtaining the color information from the overlay registers, the PO-P7 [A-E] inputs are ignored. Unused inputs should be
connected to GND.

lOR, lOG,
lOB

0

Current outputs, red, green, and blue. High-impedance red, green, and blue video analog current outputs can directly drive
a 75-0 coaxial terminated at each end (see Figure 4).
Supply Voltage. All VDO pins must be connected together.

VDO
GND

Ground. All GND pins must be connected together.

COMP

Compensation. This input is used to compensate the internal reference amplifier (see the video generation section). A
I

0.1-/1F ceramic capacitor is connected between this pin and VDD (see Figure 4). The highest possible supply voltage rejection
ratio is attained by connecting the capacitor to VOD rather than to. GND.

FSADJ

Full-scale adjust control. A resistor Rset' (see Figure 4) which is connected between this pin and GND, controls the magnitude
of the full-scale video signal. Note that the proportional current and voltage relationships in Figure 3 are maintained
I

independent of the full-scale output current.
The relationships between Rset and the lOR, lOG, and lOB full-scale output currents are:
Rset (0) = 11294 x Vref (V) I lOG (mA)
lOR, lOB (mA) = 8067 x V ref (V) I Rset (0)

REF

Reference voltage. 1.235-V is supplied at this input. An external voltage reference circuit, shown in Figure 4, is suggested.
I

Generating the reference voltage with a resistor network is not recommended since low-frequency power supply noise will
directly couple into the OAC output signals. This input must be decoupled by connecting a O.l-I1F ceramic capacitor between
VREF and GND.

CLK
CLK

I
I

Clock. This input provides the pixel clock rate. CLK and CLK inputs are designed to be driven by ECLlogic using a 5-V single
supply.
Clock. This input is the complement of C LK and also provides the pixel clock rate.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655303, DALLAS. TEXAS 75265

6-7

TLC34058
256 x 24 COLOR PALETTE

Terminal Functions (continued)
PIN NAME

DESCRIPTION

I/O

CE

Chip enable. This TIL-compatible input control allows data to be stored and enables data to be written or read (see
Figure 1).

I

When low, CE enables data to be written or read.
When high, CE allows data to be internally latched on the rising edge during write operations. Care should be taken to avoid
transients on this input.

RJW

Readlwrite input. This TIL-compatible control input is latched on the falling edge of CE (see Figure 1).

I

When low, writes data to the device. Data is internally latched on the rising edge of CEo
When high, reads data from the device.

CO,Cl

00-07

I
I

Command control inputs. The inputs specify the type of write or read operation (see Tables 1, 2, 3, and 4).
These TIL-compatible inputs are latched on the falling edge of CEo
Data input bus. This TIL-compatible bus transfers data into or outofthe device. The data bus is an S-bit bidirectional bus where
DO is the least significant bit.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, VOO (see Note 1) ................................................................................................................ 7 V
Voltage range on any digital input (see Note 1) ............................................................ - 0.5 V to VOO + 0.5 V
Analog output short circuit duration to any power supply or common, lOS ......................................... unlimited
Operating free-air temperature. TA ................................................................................................. O°C to 70°C
Storage temperature range ......................................................................................................- 65°C to 150°C
Case temperature for 10 seconds: FN package ...................................................................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: GA package ....................................... 260°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND terminal.

recommended operating conditions
Supply voltage, Voo
ClK,ClK

High-level input voltage, V IH

Other inputs
ClK,ClK

lOW-level input voltage, V 1L

Other inputs

Reference voltage, Vre!
Output load resistance, RL
FS AOJ resistor, Rset
Operating free-air temperature, T A

NOM

5

Vnn~l

2
-0.5
-0.5
1.2

0

TEXAS ",

INSTRUMENTS
6-8

MIN

4.75

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MAX

5.25
Vnn + 0.5
Vnn + 0.5
V DD -1.6
O.B
1.235
1.26
37.5
523
70

UNIT
V
V
V
V
V
V
Q
Q

°c

TLC34058
256 x 24 COLOR PALETIE
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, Rset 523 n, V ref 1.235 V (unless otherwise noted)

=

Iref

PARAMETER
Input reference current

kSVR

Supply voltage rejection ratio

=

TEST CONDITIONS
f _1 kHZ,

MHz
125
MHz
135
MHz

IIH

High-level input current

III

low-level input current

Input capacitance, digital
Ci
Ci(ClK) Input capacitance, ClK, ClK
High-level output voltage, 00-07
VOH

MAX

TA = 20'C

VOO =5 V,
VOO = 5.25 V,

TA = 20'C

VOO -5 V,
VOO - 5.25 V,

TA - 20'C

205

TA - O'C
TA = 20'C

200

Other inQl,Jts
ClK,ClK
Other inputs

ClK,ClK

%aVOO

175

VOO=5 V,
VOO = 5.25 V,

VOO = 5 V,
VOO - 5.25 V,
V =4V
V - 2.4 V

UNIT

JlA
-%-

0.5

C8 = 0.1 fLF (see Figure 4)
MHz
110

Supply current

TYPt
10

80

100

MIN

400

TA =O'C
195

420

TA = O'C

mA

435
435

TA - O'C

1

JlA
uA

VI = 0.4 V

1
-1

~

VI = 0.4 V

-1

JlA

f= 1 MHz,
f= 1 MHz,
10H = - 800 JlA
IOL = 6.4 mA

VI = 2.4V

4

10

pF

VI = 4 V

4

10

pF

0.4

V

2.4

V

VOL

lOW-level output voltage, 00-07

10Z
Zo

Output impedance

50

Co

Output capacitance (f = 1 MHz, 10 = 0)

13

High-impedance-state output current

10

JlA
kQ

20

pF

tAli typical values are allA = 25'C.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-9

TlC34058
256 x 24 COLOR PALETTE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, Rset 523 n, Vref 1.235 V (see Note 2)

=

=

PARAMETER

REFERENCE

VERSION

LIMIT
135 MHz

-

Clock frequency
LD frequency
Setup time, RlW, CO, Cl high before CE t
Hold time, R/W, CO, Cl high after CE

t

Pulse duration, CE low

125 MHz

110 MHz

80 MHz

UNITS

MAX

135

125

110

80

MHz

-

MAX

33.75

31.25

27.5

20

MHz

1

MIN

0

0

0

0

ns

2
3

MIN

15
50

15
50

15
50

15

os

50

ns

25

25

25

25

ns

35

50

ns
ns

Pulse duration, CE high
Setup time, write data before CE i
Hold time, write data after CE t

4

MIN
MIN

8

MIN

35

35

9

0

0

10

MIN
MIN

0

Pixel and control setup time

3

3

3

0
4

Pixel and control hold time

11

2
8

2

12

2
7.4

2

Clock cycle time

MIN
MIN

9.09

12.5

Pulse duration, ClK high
Pulse duration, ClK low

13

MIN

3

3.2

4

5

ns
ns

14

MIN

3

3.2

4

5

ns

lO cycle time

15

MIN

29.6

32

36.36

50

ns

lD pulse duration high time

16

MIN

12

13

15

ns

lD pulse duration low time

17

MIN

12

13

15

20
20

os
ns

ns

NOTE 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECl input signals are VOO -1.8 V
to VDD - 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference
points are at the 50% signal level. Analog output loads are less than 10 pF. DO-07 output loads are less than 40 pF.

operating characteristics over recommended ranges of supply voltage and operating free-air
temperature, Rset 523 n, Vref 1.235 V (unless otherwise noted).

=

=

analog outputs
MIN

10

MAX

UNIT

±1

lSB

Differential linearity error

±1

lSB

Gray scale error

±5

Output current

White level relative to blank

17.69

19.05

White level relative to black

16.74

17.62

20.4
18.5

Black level relative to blank

0.95

1.44

1.9

Blank level on lOR, lOB
Blank level on lOG
Sync level on lOG

0

5

50

J.tA

7.6

8.96

mA

5

50

J.tA
J.tA

69.1

DAC to DAC matching

2%

Output compliance voltage

-1

tAli typical values are at TA; 25°C.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303' DALLAS, TEXAS 75265

mA

6.29
0

lSB size

6-10

TYPt

Integral linearity error (each DAC)

PARAMETER
El
En

5%
1.2

V

TlC34058
256 x 24 COLOR PALETIE

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, Rset 523 n, Vref 1.235 V (see Note 2)

=

PARAMETER

=

REFERENCE

LIMIT

CE low to data bus enabled

5

MIN

CE low to data valid
CE high to data bus disabled

6

MAX

7
18
19
20

MAX

Analog otuput delay time (see Note 3)
Analog output rise or fall time (see Note 4)
Analog output settling time (see Note 5)
Glitch impulse (see Note 6)
Analog output skew
Pipeline delay
NOTES:

VERSION
110 MHz

80 MHz

135 MHz

125 MHz

10
75
15
20
2
8
50
0
2

10
75
15
20
2
9
50
0
2

10
100
15
20

MAX

10
75
15
20
2
8
50
0
2

MIN

6

6

MAX

10

10

TVP
TVP
MAX
TVP
TVP

UNITS
ns
os
ns
ns

3

os

12
50
0
2

ns
pV-s

6

6

10

10

clock
cycles

ns
ns

2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECl input signals are VOO -1.8
to VOO - 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals. timing reference
points are at the 50% signal level. Analog output loads are less than 10 pF. 00-07 output loads are less than 40 pF.
3. Measured from 50% point of rising clock edge to 50% point of full-scale transition.
4. Measured between 10% and 90% of full-scale transition.
5. Measured from 50% point of full-scale transition to output settling within ± 1 LSB. Settling time does not include clock and data
feedthrough.
6. Glitch impulse includes clock and data feedthrough, The - 3-dB test bandwidth is twice the clock rate.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-11

TlC34058
256 x 24 COLOR PALETTE

PARAMETER MEASUREMENT INFORMATION

R/W,

co, C1

@_-,+-:--,~~=XXXX~-"-XXX~XX~XX~X"""""XX~XXXX~7'r?XXr-7<""X"""""X"'""""'"")()
1

CE

3

1

~~--------'~~----------------~~'----4----'~~----:..

6

I..

101

101

101

~

5101:

i

DO - 07 (READ) _ _ _ _ _ _ _I_ _-'OO<~

,

)1-1- - - - - - - -

1
1
1
1

DO - 07 (WRITE)


-I--J:

:

8

I"

1
101

1

9

1

~,

1

Figure 1. Read/Write Timing Waveform
15

I..
1

1

16

I"
1
1

PO - P7 (A· B),
OLO - 0L1 (A - B),
SYNC, BLK

1

17

1
101
1
1

1

1

LD~

~ZZzXX

1
I ..

"

I

10

\

1

DATA

i

.1

1
--+1

,1
lOR, lOG, lOB

.. I

1
.1 ..

\

/

/

¥><>
1
1

11

I~ ..

~

1

1

20.1

1

~I

----------------------------------~I--~.I ~19
1
I I
1
12
101
I ..

~:

13---l
CLK

1

1

1

- - . ,,

1
1

14--14
,

Figure 2. Video Input/Output Timing Waveform

TEXAS ."

INSTRUMENTS
6-12

\'---

POST OFFICE BOX 655303' DALLAS, TEXAS 75265

TLC34058
256 x 24 COLOR PALETIE
PARAMETER MEASUREMENT INFORMATION
GREEN

REo,BLUE
mA
V

mA

V

19.05

0.714

26.67

1.000

.------,.....- - - - - - - - - - - - 7 ' < C - - - -

WHITE LEVEL

1.44

0.054

9.05

0.340

~------~-----+_---------

BLACK LEVEL

7.SIRE
DoDO

0.000

7.62

0.286

0.00

0.000

BLANK LEVEL
40lRE
~-------~-~-----------SYNCLEVEL

NOTE A: The IRE (Institute of Radio Engineers - now IEEE) scale is used for defining the relative voltage levels of the sync. white. black. and
blank levels in a monitor circuit. The reference white level is set at 100 IRE units. The blanking level is set at", IRE units. One IRE unit
is equivalent to 1/100 of the difference between the reference white level and the blanking level.

Figure 3. Composite Video Output Waveforms
COMP

VoO

REF

~C8

FSAoJ
lOR

S V (VOO)

C2-C4 fSO C7

R4

rC9

J~ Z1

r

TLC340S8
GNo

L1

~

r C10

C1
GNO

R2

fR1

R3
TO
VIDEO
CONNECTOR

lOG
lOB

Location

Oescription
O.I-~F

ceramic capacitor

Vendor Part Number

Cl - C4, C8,C9
C5 - C7

O.OI-~F

Cl0

33-~F

Ll
Rl, R2, R3

ferrite bead

Fair-Rite 2743001111

75-0. 1% metal film resistor

Dale CMF-55C

R4

1000-0. 1% metal film resistor

Dale CMF-55C

Rset
ZI

523·0. 1% metal film resistor

Dale CMF-55C

1.2-V diode

National Semiconductor

ceramic chip capacitor

tantalum capacitor

Erie RPE112Z5Ul04M50V
AVX 12t02T903QA 1018
Mallory CSRI3-K336KM

LM385Z-1.2
NOTE A: The above listed vendor numbers are listed only as a guide. Substitution of devices with similar
characteristics will not degrade the performance of the TLC34058.

Figure 4. Circuit Diagram

TEXAS .."

INsrRuMENTS
POST OFFICE BOX 655303' DALLAS, TEXAS 75265

6-13

TLC34058
256 x 24 COLOR PALETTE

PARAMETER MEASUREMENT INFORMATION

i

5V

220n

Y

ClK
5V

14

MONITOR
PRODUCTS
970E

330~1

220n1
ClK
CLOCK
GENERATOR

ClK

ClK

1

TlC34058

3300

J-7
lOA

-

5V

r

lD

0.1 1J F -.L
Vref

1 kO

REF

Figure 5. Generating the Clock, Load, and Voltage Reference Signals

----~~----~------~---VDD

lOG

SYNC
(lOG ONLY)

r-

15PF

Figure 6. Equivalent Circuit of the Current Output (lOG)

TEXAS ~

INSTRUMENTS
6-14

POST OFFICE BOX 655303' DALLAS. TEXAS 75265

C (STRAY + lOAD)

TLC34058
256 x 24 COLOR PALETTE

APPLICATION INFORMATION
device ground plane
Use of a four-layer PC board is recommended. All of the ground pins, voltage reference circuitry, power supply
bypass circuitry, analog output Signals, and digital signals, as well as any output amplifiers, should have a
common ground plane.

device analog power plane (APP)
The device plus associated analog circuitry should have a separate analog power plane (APP) for VOO. The
APP powers the device, voltage reference circuitry, and any output amplifiers. It should be connected to the
overall PCB power plane (Voo) at a single point through a ferrite bead, which should be within 3 inches of
the device. This connection is shown in Figure 4.

PCB power plane and PCB ground plane
The PCB power plane powers the digital circuitry. The PCB power plane and PCB ground planes should not
overlay the APP unless the plane-to-plane noise is common-mode.

supply decoupling
Bypass capacitors should have the shortest possible lead lengths to reduce lead inductance. For best results,
a parallel combination of O.1-~F ceramic and O.01-~F chip capacitors should be connected from each VOO
pin to GNO. If chip capacitors are not feasible, radial-lead ceramic capaCitors may be substituted. These
capacitors should be located as close to the device as possible.
The performance of the internal power supply noise rejection circuitry decreases with noise frequency. If a
switching power supply is used for VOO, close attention must be paid to reducing power supply noise. To
reduce such nOise, the APP could be powered with a three-terminal voltage regulator.

digital interconnect
The digital inputs should be isolated from the analog outputs and other analog circuitry as much as possible.
Shielding the digital inputs will reduce noise on the power and ground lines. The lengths of clock and data
lines should be minimized to prevent high-frequency clock and data information from inducing noise into the
analog part of the video system. Active termination resistors for the digital inputs should be connected to the
PCB power plane, not the APP. These digital inputs should not overlay the device ground plane.

analog signal interconnect
Minimizing the lead lengths between groups of VOO and GNO will minimize inductive ringing. To minimize
noise pickup due to reflections and impedance mismatch, the device should be located as close to the output
connectors as possible. The external voltage reference should also be as close to the device as possible, to
minimize noise pickup.
To maximize high-frequency supply voltage rejection, the video output signals should overlay the device
ground plane and not the APP.
Each analog output should have a 75-Q load resistor connected to GNO for maximum performance. To
minimize reflections, the resistor connections between current output and ground should be as close to the
device as possible.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303· DALLAS. TEXAS 75265

6-15

TLC34058
256 x 24 COLOR PALETIE

APPLICATION INFORMATION
clock interfacing
To facilitate the generation of high-frequency clock signals, the eLK and CLK pins are designed to accept
differential signals that can be generated with 5-V (single supply) EeL logic. Due to noise margins of the
CMOS process, the CLK and CLK inputs must be differential signals. Connecting a single-ended clock signal
to eLK and connecting eLK to GND will not work.
The eLK and eLK pins require termination resistors (220-Q to VDD and 330-Q to GND) that should be as close
to the device as possible.
LD is typically generated by dividing the clock frequency by four (4:1 multiplexing) or five (5:1 multiplexing)
and translating the resulting signal to TTL levels. Since no phase relationship between the LD and elK signals
is required, any propagation delay in LD caused by the divider circuitry will not affect device performance.
The pixel, overlay, sync and blank data are latched on the rising edge of lD. LD may also be used as the
shift clock for the video DRAMs. In short, LD provides the fundamental timing for the video system.
The Bt438 Clock Generator (from Brooktree) is recommended for generating the eLK, elK, lD, and REF
signals. It supports both 4:1 and 5:1 multiplexing. Alternatively, the Bt438 can interface the device to a TTL
clock. Figure 5 illustrates the interconnection between the Bt438 and the device.

~

TEXAS
INSTRUMENTS
6-16

POST OFFICE BOX 655303' DALLAS. TEXAS 75265

TLC34058
256 x 24 COLOR PALETIE

PRINCIPLES OF OPERATION
microprocessor unit (MPU) interface
As shown in the functional block diagram, the MPU has direct access to the internal control registers and color
overlay palettes via a standard MPU interface. Since the palette RAM and overlay registers have dual ports, they
can be updated without affecting the display refresh process. One port is allocated for updating or reading data
and the other for display.

palette RAM write or read
The palette RAM location is addressed by the internalS-bit address register (ADDRO-7). THE MPU can either
write to or read from this register. The register eliminates the need for external address multiplexers. ADDROADDR7 are updated via DO-D7. To address the red, green, and blue part of a particular RAM location, the internal
address register is provided with two additional bits, ADDRa and ADDRb. These address bits count modulo 3
and are reset to 0 when the MPU accesses the internal address register.
After writing to or reading from the internal address register, the M PU executes three write or read cycles (red,
green and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and blue
information is addressed from the correct part of the particular RAM location. During the blue write cycle, the red,
green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular RAM
location. After the blue write/read cycle, the internal address register bits ADDRO-7 are incremented to access
the next RAM location. For an entire palette RAM write or read, the bits ADDRO-7 are reset to 00 after accessing
the FF (256) palette RAM location.
Two additional control bits, CO and C1, are used to differentiate the palette RAM read/write function from other
operations that utilize the internal address register. CO and C 1 are respectively set high and low for writing to or
reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal address register
operations. Note that CO and C1 are each set low for writing to or reading from the internal address register.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303' DALLAS. TEXAS 75265

6-17

TlC34058
256 x 24 COLOR PALETTE
PRINCIPLES OF OPERATION
Table 1. Writing to or Reading from Palette RAM
R/W
L
L
L

C1
L
L
L

CO
L

L

ADDRb

Function

ADDRa

X

X

write ADDRO-7: DO-D7->ADDRO-7; O->ADDRa,b

H
H

L
L

L

write red color: DO-D7->RREG; increment ADDRa,b

H

write green color: DO-D7-->GREG; increment ADDRa,b

L

H

H

L

H
H
H

L
L
L

L

X

X

read ADDRO-7: ADDRO-7->DO-D7; O->ADDRa,b

H
H

L
L

L

read red color: RO-R7-->DO-D7; increment ADDRa,b

H

read green color: GO-G7-->DO-D7; increment ADDRa,b

H

L

H

H

L

write blue color:' DO-D7->BREG; increment ADDRa,b;
increment ADDRO-7; write palette RAM

read blue color: BO-B7 ->DO-D7; increment ADDRa,b;
increment ADDRO-7

X ; irrelevant

overlay register write/read
With a few exceptions, the overlay register operation is identical to the palette RAM write/read operation (refer
to the palette RAM write/read section), Upon writing to or reading from the internal address register, the additional
address register ADDRab is automatically reset to O. ADDRab counts modulo 3 as the red, green, and blue
information is written to or read from a particular overlay register. The four overlay registers are addressed with
internal address register values 00-03. After writing/reading blue information, the internal address register bits
ADDRO-7 are incremented to the next overlay location. After accessing overlay register value 03, the internal
address register does not reset to 00 but is advanced to 04.
Forwriting to or reading from the internal address register, CO and C1 are set low. When accessing the overlay
registers, CO and C1 are set high. Refer to Table 2 for quick reference.

Table 2. Writing to or Reading from Overlay Registers
R/W
L
L

C1
L

CO
L

L

H
H

H
H

L

H

H
H
H
H

Function

ADDRb

ADDRa

X
L

X

write ADDRO-7: DO-D7-->ADDRO-7; O->ADDRa,b

L

write red color: DO-D7->RREG; increment ADDRa,b

L

H

write green color: DO-D7->GREG; increment ADDRa,b

H

H

L

L

L

X

X

read ADDRO-7: ADDRO-7->DO-D7; O->ADDRa,b

H
H

H
H

L

L

read red color: RO-R7->DO-D7; increment ADDRa,b

L

H

H

H

H

L

write blue color: DO-D7 -->BREG; increment ADDRa,b;
increment ADDRO-7; write overlay register

read green color: GO-G7->DO-D7; incrementADDRa,b
read blue color: BO-B7 ->DO-D7; increment ADDRa,b;
increment ADDRO-7

X ; irrelevant

"'!1

TEXAS
INSTRUMENTS
6-18

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TlC34058
256 x 24 COLOR PALETTE

PRINCIPLES OF OPERATION
control register write/read
The four control registers are addressed with internal address register values 04-07. Upon writing to or reading
from the internal address register, the additional address bits ADDRab are automatically reset to O. To
facilitate read-modify-write operations, the internal address register does not increment after writing to or
reading from the control registers. All control registers may be accessed at any time. When accessing the
control registers, CO and C1 are respectively set low and high. Refer to Table 3 for quick reference.

R/W
L
L
H
H

Table 3. Writing to or Reading from Control Registers
Function
co
ADDRba AD DRab

Cl
L
H

L
H

L
L
L

X

X

write ADDRO-7: DO-D7 .... ADDRO-7; O.... ADDRa,b

L
X

L
X

write control register: DO-D7 .... control register

L

L

L

read control register: control register.... DO-D7

read ADDRO-7: ADDRO-7-->DO-D7; O-->ADDRa,b

X : irrelevant

summary of internal address register operations
Table 4 provides a summary of operations that use the internal address register. Figure 1 presents the read!
write timing for the device.
If an invalid address is loaded into the internal address register, the device will ignore subsequent data from
the MPU during a write operation and will send incorrect data to the MPU during a read operation,
Table 4. Internal Address Register Operations
ADDRab

INTERNAL ADDRESS
REGISTER VALUE

Cl

co

COLOR

modulo 3)

(ADDRO·7) (HEX)
OO-FF

(counts

MPUACCESS

L

H

color palette RAM

00-03

H

H

over color 0 to 3

04

H

L

read mask register

05

H
H

07

H

L
L
L

blink mask register

06

00

red value

01

green value

11

blue value

00

red value

01

green value

110

blue value

command register
test register

interruption of display refresh pixel data (via simultaneous pixel data retrieval and MPU write)
If the MPU is writing to a particular palette RAM location or overlay register (during the blue cycle) and the
display refresh process is accessing pixel data from the same RAM location or overlay register, one or more
pixels on the display screen may be disturbed. If the MPU write data is valid during the complete chip enable
period, a maximum of one pixel will be disturbed.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655303· DALLAS, TEXAS 75265

6-19

TLC34058
256 x 24 COLOR PALETIE
PRINCIPLES OF OPERATION
frame buffer interface and timing

An internal latch and multiplexer enables the frame buffer to send the pixel data to the device at TIL rates.
On the rising edges of lD, information for four or five consecutive pixels is latched into the device. This
information includes the palette RAM address (up to 8 bits), the overlay register address (up to 2 bits), and
the s)'nc and blank information for each of the four or five consecutive pixels. The timing diagram for this pixel
data input transfer is shown in Figure 2, along with the video output waveforms (lOR, lOG, and lOB). Note
that with this architecture, the sync and blank timing can only be recognized with four- or-five-pixel resolution.
The display refresh process follows the first-in first-out format. Color data is output from the device in the same
order in which palette RAM and overlay addresses are input. This process continues until all four or five pixels
have been output, at which point the cycle will repeat.
The overlay timing can be controlled by the pixel timing. However, this approach requires that the frame buffer
emit additional bit planes to control the overlay selection on a pixel basis. Alternatively, the overlay timing can
be controlled by external character or cursor generation timing (~ee the color selection section).
No phase relationship between the lD and ClK signals is required (see Figure 2). Therefore, the lD signal
can be derived by externally dividing the ClK signal by four or five. Any propagation delay in lD caused by
the divider circuitry will not render the device nonfunctional. Regardless of the phase relationship between
lD and ClK, the pixel, overlay, sync, and blank data are latched on the rising edge of lD.
The device has an internal load signal (not brought out to a pin), which is synchronous to ClK and will follow
lD by at least one and not more than four clock cycles. This internal load signal transfers the lD-latched data
into a second set of latches, which are then internally multiplexed at the pixel clock or ClK signal frequency.
For 4:1 or 5:1 multiplexing, a rising edge of LD should occur every four or five clock cycles. Otherwise, the
internal load signal generation circuitry cannot lock onto or synchronize with lD.

color selection
The read mask, blink mask, and command registers process eight bits of color information (PO-P7) and two
bits of overlay information (OlO-Ol1) for each pixel every clock cycle. Control registers allow individual bit
planes to be enabled/disabled for display and/or blinked at one of four blink rates and duty cycles (see the
command register section, bits CR4-CR5).
By monitoring the BlK input to determine vertical retrace intervals, the device ensures that a color change
due to blinking occurs only during the nonactive display time. Thus, a color change does not occur in the
middle of the screen. A vertical retrace is sensed when BlK is low for at least 256 lD cycles. The color
information is then selected from the palette RAM or overlay registers, in accordance with the processed input
pixel data. Table 5 presents the effect of the processed input pixel data upon color selection. Note that PO
is the least significant bit (lSB) of the color palette RAM. When CR6 is high and both Ol1 and OlO are low,
color information resides in the color palette RAM. When CR6 is low or either of the overlay inputs is high,
the overlay registers provide the DAC inputs.

TEXAS

~

INSTRUMENTS
6-20

POST OFFICE BOX 655303' DALLAS. TEXAS 75265

TLC34058
256 x 24 COLOR PALETIE
PRINCIPLES OF OPERATION
Table 5. Input Pixel Data versus Color Selection
COMMAND

OVERLAY

COLOR

REGISTER

SELECT

ADDRESS

BIT

INPUT

(HEX)

COLOR
INFORMATION

CA6

OL1

OLO

P7-PO

H

L

L

00

color palette entry 00

H

L

L

01

color palette entry 01

H

L

L

FF

color palette entry FF

L

L

L

overlay register 0

X
X
X

L

H

H

L

H

H

XX
XX
XX
XX

overlay register 1
overlay register 2
overlay register 3

X = irrelevant

video generation
The TLC34058 presents 8 bits of red, green, and blue information from either the palette RAM or overlay
registers to the three 8-bit DACs during every clock cycle. The DAC outputs produce currents that correlate
to their respective color input data. These output currents are translated to voltage levels that drive the color
CRT monitor. The SYNC and BLK signals adjust the DAC analog output currents to generate specific output
levels that are required in video applications. Table 6 shows the effect of SYNC and BLK upon the DAC output
currents. Figure 3 presents the overall composite video output waveforms. Note that only the green output
(lOG) contains sync information.
The DAC architecture ensures monotonicity and reduced switching transients by using identical current
sources and routing their outputs to the DAC current output or GND. Utilizing identical current sources
eliminates the need for precision component ratios within the DAC ladder circuitry. An on-chip operational
amplifier stabilizes the DAC full-scale output current over temperature and power supply variations.
Table 6. Effects of Sync and Blank Upon DAC Output Currents (see Note 7)
DESCRIPTION

lOG

lOR, lOB

(rnA)

(rnA)

SYNC

BlK

DAC
INPUTS

WHITE

26.67

19.05

H

H

FF

DATA

data + 9.05

data + 1.44

H

H

data

DATA w/o SYNC

data + 1.44

data + 1.44

L

9.05

1.44

H

H
H

data

BLACK
BLACK w/o SYNC

1.44

1.44

L

H

00

BLACK

7.62

H

L

SYNC

0

0
0

L

L

xx
xx

00

command register
The MPU can write to or read from the command register at any time. The command register is not initialized.
CRO corresponds to the DO data bus line. Refer to Table 7 for quick reference.

NOTE 7: The data in this table was measured with full-scale lOG current

= 26.67 rnA,

Aset

= 523 n,

Vref

= 1.235 V.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303· DALLAS, TEXAS 75265

6-21

TlC34058
256 x 24 COLOR PALETTE
PRINCIPLES OF OPERATION
TABLE 7. COMMAND REGISTER
COMMAND
REGISTER
BIT

COMMAND REGISTER
BIT FUNCTION
Multiplex Select Bit

CR7

COMMAND REGISTER BIT DESCRIPTION
This bit selects either 4:1 or 5:1 multiplexing for the palette RAM and overlay register address,

low: selects 4:1 multiplexing SYNC, and BD< inputs. If 4:1 multiplexing is selected, the device ignores the 'E' palette RAM
high: selects 5:1 multiplexin\ and overlay register address inputs. These inputs should be connected to GND, and the [IT signal
frequency should be 1/4 of the clock frequency. If 5: 1 is specified, all of the palette RAM and overlay
register address inputs are used and the [IT signal should be 115 of the clock frequency.
CR6

RAM Enable Bit

When the overlay select bits, OLO and OL 1, are both low, this bit causes the DACs color information

low: use overlay register 0

to be selected from overlay register 0 or the palette RAM.

high: use palette RAM
CR5, CR4

Blink Rate Select Bits

These two bits select the blink rate cycle time and duty cycle. The on and off numbers specify the

00: 16 on, 48 off (25/75)

blink rate cycle time as the number of vertical periods.

01: 16 on, 16 off (50/50)

The numbers in parenthesis specify the duty cycle in (on/off) percent.

10: 32 on, 32 off (50/50)
11: 64 on, 64 off (50/50)
CR3

CR2

CRl

aLl Blink Enable Bit

If this bit is a high, the OL 1 [A-E] inputs will toggle between a logic 0 and their input value at the

low: disable blinking

selected blink rate before latching the incoming pixel data. Simultaneously, command registerCRl

high: enable blinking

must be set high. If the CR2 bit is low, the OLO [A-E] inputs will be unaffected.

OLO Blink Enable Bit

If this bit is high, the OLO [A-E] inputs will toggle between a logic 0 and their input value at the

low: disable blinking

selected blink rate before latching the incoming pixel data. Simultaneously, command registerCRO

high: enable blinking

must be set high. If the CR2 bit is low, the OLO [A-E] inputs will be unaffected.

all Display Enable Bit

If this bit is low, the OL 1 [A-E] inputs are forced to a logic 0 before latching the incoming pixel data.
If the CRl bit is high, the OL 1 [A-E] inputs will be affected.

low: disable
high: enable
CRO

OLO Display Enable Bit
low: disable

If this bit is low, the OLO [A-E] inputs are forced to a logic 0 before latching the incoming pixel data.
If the CRO bit is high, the OLO [A-E] inputs will be affected.

high: enable

read mask register
The read mask register is used to enable (high) or disable (low) the eight bit planes (PO-P7) within the palette
RAM addresses. The enabling or disabling is accomplished by logic ANDing the read mask register with the
palette RAM address before addressing the palette RAM. Note that read mask register bit 0 corresponds to
data bus line DO. The MPU can write to or read from this register at any time. This register is not initalized.

blink mask register
The blink mask register is used to enable (high) or disable (low) the blinking of bit planes within the palette
RAM addresses. For example, if blink mask register bit n is set high, the true Pn value will address the palette
RAM during the on portion of the blink cycle. During the off part of the blink cycle, the Pn value will be replaced
with a 0 before the palette RAM is addressed. The blink rate cycle time and duty cycle is specified by command
register bits CR4 and CR5. If blink mask register bit n is set low, the true Pn value will always address the
palette RAM. Note that blink mask register bit 0 corresponds to data bus line DO. This register is not intialized.

TEXAS ."

INSTRUMENTS
6-22

POST OFFICE BOX 655303' DALLAS. TEXAS 75265

TLC34058
256 x 24 COLOR PALETTE

PRINCIPLES OF OPERATION

test register
The test register allows the MPU to read the inputs to the DAC for diagnostic purposes. The MPU can write to
or read from this register at anytime. This register is not initialized. Only the four least significant bits can be written
to. while ailS bits can be read. Note that test register bit 0 corresponds to data bus line DO.
A functional description of this register is presented in Table S.
Table 8. Functional Description of Test Register
TR3-TRO
0100
0010
0001
1100
1010
1001

04-07

FUNCTION

4 MSBs of blue data input
4 MSBs of green data input MPU read or write DO-D3
4 MSBs of red data input
4 LSBs of blue data input
4 LSBs of green data input

MPU read DO -D7

4 LSBs of red data input

To read the DAC inputs. the MPU must first load the test register's four least significant bits. One of the test
register bits. bO (red DAC). b1 (green DAC). or b2 (blue DAC), must be set high and the other two bits low. This
process determines whether the inputs to the red, green, or blue DAC will be read. The test register bit b3 must
be set high for reading the four most significant DAC inputs or low for reading the four least significant inputs.
The MPU then reads the test register while the test register's four least significant bits contain the previously
written information. Note that either the device clock must be slowed down to the MPU cycle time or the same
pixel and overlay data must be continuously presented to the device during the entire MPU read cycle.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303' DALLAS. TEXAS 75265

6-23

6-24

TLC34075
VIDEO INTERFACE PALETTE

See the TLC34075 Video Interface Palette Data Manual in Section 9 for product
information.

TEXAS

-'!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-25

6-26

7-1

»
::J
o-

Q)

to

en

:e-......

(")

:::r
CD

U)

7-2

TL182, TL185, TL188, TL191
BI·MOS SWITCHES
02234, JUNE 1976-REVISEO SEPTEMBER 1986

•

Functionally Interchangeable with Siliconix
OG182, OG185, OG188, OG191 with Same
Terminal Assignments

•

Monolithic Construction

•

Adjustable Reference Voltage

•

JFET Inputs

•

Uniform On-State Resistance for Minimum
Signal Distortion

•

± 10-V Analog Voltage Range

•

TTL, MaS, and CMOS Logic Control
Compatibility
TL 182
N PACKAGE

description

(TOP VIEW)

The TL 182, TL 185, TL 188, and TL 191 are
monolithic high-speed analog switches using BIMOS technology. They comprise JFET-input
buffers, level translators, and output JFET
switches. The TL 182 switches are SPST; the
TL 185 switches are SPOT, The TL 188 is a pair
of complementary SPST switches as is each half
of the TL 1 91 .

NC
NC

2A
VEE
Vre!
TL185
N PACKAGE
(TOP VIEW)

101

1 S1
1A

NC

102
1S2
2S1
201

VEE
Vre!
VLL
Vec

NC

2A
2S2

202
TL 188
N PACKAGE
(TOP VIEW)

The output switches are junction field-effect
transistors featuring low on-state resistance and
high off-state resistance. The monolithic
structure ensures uniform matching.

NC
NC

NC
NC

01
S1
A

02
S2
NC
VEE
Vre!

VCC
VLL

BI-MOS technology is a major breakthrough in
linear integrated circuit processing. BI-MOS can
have ion-implanted JFETs, p-channel MOS-FETs,
plus the usual bipolar components all on the
same chip. BI-MOS provides for monolithic
circuit designs that previously have been
available only as expensive hybrids.

TL191
N PACKAGE
(TOP VIEW)

101
NC

M-suffix devices are characterized for operation
over the full military temperature range of
- 55°C to 125°C. I-suffix devices are
characterized for operation from - 25°C to
85 °C, and C-suffix devices are characterized for
operation from O°C to 70°C.

:~~~~:~~i~air::1~1~ ~~::~~ti:r fI~O::;:~":t::S~S not

NC
NC

1A

The threshold of the input buffer is determined
by the voltage applied to the reference input
(V ref) . The input threshold is related to
the reference input by the equation
Vth = Vref + 1.4 V. Thus, for TTL compatibility, the Vref input is connected to ground. The
JFET input makes the device compatible with
bipolar, MOD, and CMOS logic families.
Threshold compatibility may, again, be
determined by Vth = Vref + 1.4 V.

spacifications pef the terms of Texas Instruments

2S
20

VCC
VLL

A high level at a control input of the TL 182 turns
the associated switch off. A high level at a
control input of the TL 185 turns the associated
switch on. For the TL 188, a high level at the
control input turns the associated switches S 1
on and S2 off.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to

1S
10

1S1
1A

102
1S2
2S2
202

VEE
Vre!
VLL
VCC

NC

2A
2S1

201

NC-No internal connection
Copyright © 1984, Texas Instruments Incorporated

"!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-3

TL 182. TL 185
BI·MOS SWITCHES
TL 182 TWIN SPST SWITCH
schematic (each channel)

symbol

0

1A
1S

S
2A
A_

2S

(5)

(1 )

.---t.

(2)

---t..

(13)

10

(10)
(14)

20

FUNCTION TABLE
(EACH HALF)
INPUT

SWITCH

A

S

L

ON (CLOSED)

H

OFF (OPEN)

TL 185 TWIN DPST SW, rCH
schematic (each channel)

symbol

(15)

1A
01

(16)
1S1
(4)
152
(10)

S1
2A
A-+~-4--~------+-------+-----~~

02

2S1
252

-------...,....,...-

(5)

-

(9)

.../"'"

(1 )
101
(3)
102

(6)
(8)

201
202

S2
FUNCTION TABLE
(EACH HALF)

Vref

~

TEXAS
INSTRUMENTS
7--4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

INPUT

SWITCHES

A

SW1 ANDSW2

L

OFF (OPEN)

H

ON (CLOSED)

TL188, TL191
OI·MOS SWITCHES

TL 188 DUAL COMPLEMENTARY SPST SWITCH
schematic

symbol
vcc

VLL

01

Sl

A

(5)

Sl

(4)

52 (11)

-""'"_

---t...

(3)

01
(12) 02

A
02

52

FUNCTION TABLE
SWITCHES

INPUT

VEE

A

SWl

SW2

L

OFF (OPEN)

ON (CLOSED)

H

ON (CLOSED)

OFF (OPEN)

Vref

TL 191 TWIN DUAL COMPLEMENTARY SPST SWITCH
schematic (each

ch~nnel)

symbol

lA

01

lSl
lS2
Sl
2A
A~+-~~-r------~------~----~~)

2S1

02

(15)
(16)
(4)

(1)

-""'"-

~

(3)

101
102

(10)
(9)

(5)
2S2

-""'"-

(S)

201
(6)

---t..

202

FUNCTION TABLE
SWITCHES

INPUT

}

A

SWl

SW2

L

OFF (OPEN)

ON (CLOSED)

H

ON (CLOSED)

OFF (OPEN)

TO OTHER HALF

Vref

"'!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-5

TL 182, TL 185, TL 188, TL 191
BI-MOS SWITCHES

functional block diagram

OOR 01

A-o-t>-

02

+--r
5 OR 51

S2

See the preceding two pages for operation of the switches.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Positive supply to negative supply voltage, VCC - VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Positive supply voltage to either drain, VCC - VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
Drain to negative supply voltage, VD- VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Drain to source voltage, VD - Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 22 V
Logic supply to negative supply voltage, VLL - VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 V
Logic supply to logic input voltage, VLL - VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Logic supply to reference voltage, VLL - Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
Logic input to reference voltage, VI - Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Reference to negative supply voltage, Vref - VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 V
Reference to logic input voltage, Vref - VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 2 V
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating free-air temperature range: TL 182M, TL 185M, TL 188M, TL 191 M . . .. - 55°C to 125°C
TL1821, TL1851, TL1881, TL1911 ......... -25°C to 85°C
TL182C, TL185C, TL188C, TL191C ......... O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C

TEXAS .."
INSTRUMENTS
7-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics.

vee

15 V. VEE = -15 V. VLL =5 V. Vref

OV
TL1_1

TL1_M
MIN
High-Ievet control

VIH

TA ~ MIN TO MAX

input voltage
Low-level control

VIL

TA ~ MIN to MAX

High-level control

VI

~

5 V

VI

~

0

input current

Low-level control

IlL

Vo - 10V,

Off-state drain current

0

O!-

~

..,

~t:l~

;,8 c:~
~

FfTJ
oZ

~ ~.ct
~

'"~

Vo -

Off-state source Gurrent

ISloft)

~

1010ni + 151 ani

~(J)

~

VIH

."

~z

TA

MIN

MAX

MAX

V

V re f+ 2

V re f+ 2

V re f+ O.8

MIN

V re t+ O.8

V,ef+ 0 .8

TA - 25°C

10

10

20

TA - MAX

20

20

20

-250

-250

-250

5

5

100

100

100

5

5

100

100

100

-10

-10

-200

-200

-200

~

MIN to MAX

V

~A

~A

input current

1010ffi

"1

UNIT

MAX

V re t+ 2

input voltage

IIH

TL1_C

TEST CONOITIONS

PARAMETER

~

VIH

~

On-state channel

Vo

leakage current

VIH

Drain-ta-source

VO~

on-state resistance

VIH

~

2 V,
10 V,
2 V,

Vs -

-10 V,

TA - 25°C

VIL ~ 0.8 V

TA - MAX

Vs - 10V,

TA - 25°C

~

VIL

-10V,

VS~

2 V,

VIL

-10V,

IS

2 V,

VIL

~

0.8 V

TA

~

MAX

-10V,

TA

~

25°C

0.8 V

TA

~

MAX

TL 182,
rDS(on)

~

~

1 mA,
~

0.8 V

TA

TL 185,

~

75

100

100

MAX

100

150

150

MIN to 25°C

125

150

150

MIN to 25°C

TA

TL 188
TA

~

~

TA ~ MAX

250

300

300

ICC

Supply current from

Vee

1.5

1.5

1.5

lEE

Supply current from VEE

-5

-5

-5

ILL

Supply current from VLL

4.5

4.5

4.5

TL 191

Iref

Reference current

ICC

Supply current from

lEE

Supply current from VEE

~

Both control inputs at 0 V

TA

~

25°C

Vee
TA

Both control inputs at 5 V

~

25°C

Supply current from VLL

ILL

~

Reference current

--

switching characteristics.

Vee

PARAMETER

ton

Turn-on time

toft

Turn-off time

----

--

-

10 V. VEE

--

--

CL = 30 pF,

---

-20 V. VLL

TEST CONDITIONS
RL = 300 II,

---

Figure 1

._-

-2

-2

-2

1.5

1.5

1.5

-5

-5

-5

4.5

4.5

4.5

-2

-2

-2

5 V. Vref =0 V. TA

TL1_M

TL1_1

TL1_C

TYP

TYP

TYP

175

175

175

350

350

350

25°e

nA

nA

nA

n

mA

I
mA

-I

....
~

CCI
N

-I
~

UNIT

ns

~~
• en
3:0-1

en r....
enCCl

::e~
::::::j-l

t

n~
:::c
....

m=
en
....

TL182, TL185, TL188, TL191
BI·MOS SWITCHES
PARAMETER MEASUREMENT INFORMATION

VLL=5V

VCC=15V

OUTPUT

o
I

J

_.J

CL =30 PF

VEE=-15V

Vref = 0

CL includes probe and jig capacitance
Vs = 3 V for ton and -3 V for toft
Vo=Vs - - - RL + rOS(on)
TEST CIRCUIT

tf

< 10 ns

t

INP~T-:'\

< 10 ns

1'·------

x = r 3V

,1

1\

I

~n ~

'-----if--'
~I

I

OV

I

- -- --+-----:-:-t----- 0.9VOrj-VOI
I

~___
OU"U,

____

----7'.W
III

~

3V

toft

o

'V

-------.'!...'?-. ---- ----- -3V
NOTE: A. The solid waveform applies for TL185 and SW1 of TL185 and TL191; the dashed waveform applies for TL182 and SW2 of
TL 185 and TL 191.
B. Va is the steady-state output with the switch on. Feed through via the gate capacitance may result in spikes (not shown) at
the leading and trailing edges of the output waveform.
.

FIGURE 1. VOLTAGE WAVEFORMS

TEXAS

.-1!1

INSTRUMENTS
7-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL601, TL604, TL607, TL610
P·MOS ANALOG SWITCHES
02161, JUNE 1976-REVISED OCTOBER 1986

± 10·V

•

Switch

•

TTL Logic Capability

Analog Signals

•

5· to 30-V Supply Ranges

•

Low (100

•

High (10 11

•

8-Pin Functions

JG OR P PACKAGE
(TOP VIEW)

Tl601

m On-State Resistance

G N D [ ] B VCC+
A
2
7
52
B
3
6
51
5
VCC5 4

mOff-State Resistance

Tl604

description
The TL601, TL604, TL607, and TL610 are a
family of monolithic P-MOS analog switches that
provide fast switching speeds with high roft/ron
ratio and no offset voltage, The p-channel
enhancement-type MOS switches accept analog
signals up to ± 10 V and are controlled by TTLcompatible logic inputs. The monolithic structure
is made possible by BI-MOS technology, which
combines p-channel MOS with standard bipolar
transistors.

GND [ ] B VC,C+
A
2
7
51
3
6
52
51
5
VCC52 4
Tl607

G N D [ ] B VCC+
2
7
52
3
6
51
5 4
5 VCC-

A
ENABLE

These switches are particularly useful in military,
industrial, and commercial applications such as
data acquisition, multiplexers, A/O and O/A
converters, MODEMS, sample-and-hold
systems, signal multiplexing, integrators, programmable operational amplifiers, programmable
voltage regulators, crosspoint switching
networks, logic interface, and many other analog
systems.

Tl610

G N D [ ] B VCC+

TYPICAL OF
All INPUTS

The TL601 is an SPOT switch with two logic
control inputs. The TL604 is a dual
complementary SPST switch with a single
control input. The TL607 is an SPOT switch with
one logic control input and one enable input. The
TL610 is an SPST switch with three logic control
inputs. The TL61 0 features a higher roff/ron ratio
than the other members of the family.

specifications per the terms of Texas Instruments
standard warranty. Production processing does not

necessarily include testing of all parameters.

2
3

7
6

C
5

5

4

5

VCC-

TYPICAL OF
All SWITCHES
VCC-

~S

IT'
vCC-

The TL601 M, TL604M, TL607M, and TL61 OM
are characterized for operation over the full
military temperature range of - 55 °e to 125 °e,
the TL601', TL6041, TL6071, and TL6101 are
characterized for operation from - 25 °e to
85°e, and the TL601 e, TL604e, TL607e, and
TL610e are characterized for operation from
ooe to 70 oe.

PRODUCTION DATA documents contain information
current as of publication date. Products conform to

A
B

Copyright © 1979, Texas Instruments Incorporated

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS.

T~XAS

i.•,J.:.•
"

75265

7-9

I

I

,.,1.
i

TL601, TL604, TL607, TL610
P·MOS ANALOG SWITCHES
logic symbols t and switch diagrams
TL601

A

B

8

&

(2)

TL602

8(4)

Xl

(3)

n 1/1

(4)

n
n

1
1

A
(6)
'(7)

81

S1

82

S2

(2)

X1

(4)

(6)

1

S1
S2

FUNCTION TABLE

ANALOG SWITCH

ANALOG SWITCH

LOGIC INPUT

A

B

S1

S2

A

S1

L

X

OFF (OPEN)

ON (CLOSEO)

H

ON (CLOSED)

OFF (OPEN)

X

L

OFF (OPEN)

ON (CLOSED)

L

OFF (OPEN)

ON (CLOSED)

H

H

ON (CLOSED)

OFF (OPEN)

TL607

A (2)

TLS10

3X1

B

C

S

(3)

Xl

(7)

~1

FUNCTION TABLE
INPUTS
A ENABLE

IAI
/(6)
S(4)
~--S

A

n 1/1

8 (4)

S2

&

(2)

ENABLE .;..(3";')_--1 G3

1

n

(6)

S

FUNCTION TABLE
ANALOG SWITCH

INPUTS

ANALOG SWITCH
A

B

C

OFF (OPEN)

L

X

X

OFF (OPEN)

S1

S2

S

L

OFF (OPEN)

L

H

OFF (OPEN)

ON (CLOSED)

X

L

X

OFF (OPEN)

H

H

ON (CLOSED)

OFF (OPEN)

X

x

L

OFF (OPEN)

H

H

H

ON (CLOSED)

X

tThese symbols are in accordance with ANSI/IEEE Std 91 1984,

TL607 logic diagram (positive logic)
ENABLE.;..(3~)--~.-~~,

1-------1

A (2)

S (4)

TEXAS

~

INSTRUMENTS
7-10

(7)

~n

FUNCTION TABLE
LOGIC INPUTS

S2~S2

n

n1
n ,-

(3)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL601, TL604, TL607, TL610
P-MOS ANALOG SWITCHES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 V
Supply voltage, VCC _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 V
VCC + to VCC - supply voltage differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Control input voltage .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC +
Switch off-state voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 V
Switch on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 mA
Operating free-air temperature range: TL601 M, TL604M, TL607M, TL61 OM .... - 55 DC to 125 DC
TL6011, TL6041, TL6071, TL6101 ......... -25°C to 85°C
TL601C, TL604C, TL607C, TL610C ......... ODCto 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
Lead temperature (1,6 mm) 1/16 inch from case for 60 seconds: JG package. . . . . . . . . . .. 300 DC
Lead temperature (1,6 mm) 1/16 inch from case for 10 seconds: P package. . . . . . . . . . . .. 260 DC
NOTE 1: All voltage values are with respect to network ground terminal.

recommended operating conditions
TL601M. TL604M

Tl6011. TL6041

Tl607M, Tl610M

Tl6071. TL6101

MIN

NOM

MAX

MIN

NOM

MAX

TL601C. TL604C
Tl607C, TL610C
MIN

NOM

UNIT

MAX

Supply voltage, Vee + (see Figure 11

5

10

25

5

10

25

5

10

25

Supply voltage, Vee _ (see Figure 11

-5

-20

-25

-5

-20

-25

-5

-20

-25

V

30

15

30

15

30

V

5.5

2

5.5

2

5.5

V

Vee + tD Vee _ supply voltage differential (see Figure 11
High-level control input voltage, VIH
LOW-level control input voltage, VIL
Voltage at any analog switch (SI terminal

15
2

All inputs

0.8
VCC-

Switch on-state current
Operating free-air temperature, T A

+8

vcc+

0.8

Vce +8

10
-55

125

Vce+

0.8

Vee

10
-25

85

V

a

+8

Vce+

V

10

mA

70

°e

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-11

TL601. TL60' TL607. TL610
P-MOS ANALOG SWITCHES
electrical characteristics over recommended operating free-air temperature range, Vee +
Vee - = - 20 V, analog switch test current = 1 mA (unless otherwise noted)
PARAMETER

=

IIH

High-level input current

VI

IlL

Low-level input current

loft

Switch off-state current

VI - 0.4 V
Vl(sw) - -10 V,

MAX

0.5

10

=
=

10 V,

TL604

-1 mA

TL607
TL610

10

I'A
I'A
pA

-500
-10

-20

55

100

75

200

40

80

40

100

220

400

220

600

120
25

300

120

400

TL601
Vllsw)
IOlsw)

=
=

-10 V,

TL604

-1 mA

TL607
TL610

roff

Switch off-state resistance

Can

Switch on-state input capacitance

1 MHz

Coft

Switch off-state input capacitance Vllsw) - 0 V, f - 1 MHz

Vl(sw)

=

0 V, f

=

TL601
Logic inputls)
Enable

AI) switch

input high

terminals

Enable

open

input low

at 5.5 V,

input high
Enable

open

input low

8

pF

5

10

5

10

3

5

3

5

5

10

5

10

-1.2

-2.5

-1.2

-2.5

-2.5

-5

-2.5

-5

-0.05

-0.5

-0.05

-0.5

-1.2

-2.5

-1.2

-2.5

TL607

TL604

All switch

pF

8

10

Enable

terminals

Gil

16

5

TL601
Logic inputls)

TL607

TL610

Il

16

10

TL604

at 5.5 V,

nA

20

5

TL610

ICC _ Supply current from V CC _

0.5

-50 -250

-50 -100

TA - MAX
TL601

Switch on-state resistance

ICC + Supply current from VCC +

MAX

-400

TA - 25°C

UNIT

MIN TYP*

-50 -250

See Note 2

IOlsw)

Tl6 __ C

MIN TYP*
5.5 V

Vl(sw)

ron

Tl6 __ M
Tl6 __ 1

TEST CONDITIONst

10 V,

mA

mA

tMAX is 125°C for M-suffix types, 85°C for I-suffix types, and 70°C for C-suffix types.
*AI) typical values are at TA = 25°C except for loff at TA = MAX.
NOTE 2: The other terminal of the switch under test is at VCC + = 10 V.

switching characteristics, Vee + = 10 V, Vee PARAMETER
toft

Switch turn-off time

ton

Switch turn-on time

=

-

20 V, TA

TEST CONDITIONS
RL

=

1 kll, CL

=

35 pF, See Figure 2

TEXAS . "

INSTRUMENTS
7-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=

25°e
MIN

TYP

MAX

400

500

100

150

UNIT
ns

TL601. TL604. TL607. TL610
P·MOS ANALOG SWITCHES
Figure 1 shows power supply boundary conditions for proper operation of the TL601 Series. The range
of operation for supply Vee+ from +5 V to +25 V is shown on the vertical axis. The range of Veefrom - 5 V to - 25 V is shown on the horizontal axis. A recommended 30-V maximum voltage differential
from Vee+ to Vee- governs the maximum Vee+ for a chosen Vee- (or vice versa). A minimum
recommended difference of 15 V from Vee + to Vee _ and the boundaries shown in Figure 1 allow the
designer to select the proper combinations of the two supplies.
The designer-selected Vee + supply value for a chosen Vee - supply value limits the maximum input
voltage that can be applied to either switch terminal; that is. the input voltage should be between Vee+ 8 V and Vee + to keep the on-state resistance within specified limits.
RECOMMENDED COMBINATIONS
OF SUPPLY VOLTAGES

30

25

>I

8,

...co

20

>
a.

15

'1+

10

g
Q.
:::I

(,,)

~

OL-__
-30

~

-25

__

~

____L -__

-20

-15

~

__- L__~

-10

-5

o

VCC_-Supply Voltage-V

FIGURE 1

"11

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265

7-13

H6Dl, H6D4, H6D7, H61D
P·MOS.ANALOG SWITCHES

PARAMETER MEASUREMENT INFORMATION
+10V

2.4V

OR
-10 V

PULSE
GENERATOR

- -

~:;JfoUTPUT
I
.....J RL =
CL = 35 pF
- 1 kU -=
(See Note B)

'1'

_--5V

I ------' I

ton~
OUTPUT

(Seo Note A)

toff~

OV

T-

/90%
.

"'
Vo
~O%

1kU
VO=(10V) - - 1 kU+'on

TEST CIRCUIT
NOTES:

-'"'

50%
50%
~

INPUT

A. The pulse generator has the following characteristics:
Zout = 50 0, tr :5 15 ns, tf :5 15 ns, tw = 500 ns.
B. CL includes probe and jig capacitance.

VOLTAGE WAVEFORMS

FIGURE 2

TYPICAL CHARACTERISTICS
M·SUFFIX DEVICES
I·SUFFIX DEVICES
SWITCH ON-STATE RESISTANCE
vs
SWITCH ANALOG VOLTAGE

c:I

M-SUFFIX DEVICES
I-SUFFIX DEVICES
SWITCH ON-STATE RESISTANCE
vs
FREE-AIR TEMPERATURE

1000

1000

700

700

.."

400

..

200

t:

.;;;

....

a:

~'"

I:

0
~

100

200

~

100

~'"

70

40

0
I

40

) __ 10 V -t--t---t---t----1

V,(sllll -

I

V ,(sllll) ~-r~--j--_t__:=O!--F--

I:

20
10
-15

~

Vcc+ = 10 V
VCC- = -20 V
TA = 25°C

20

VI(5W)

VI(5W) = 10 VI
VCC+

=0 V

= 10 V

VCC-= -20 V

10(5w) = 1 rnA
10~~-~--~--~--~--~--~~

-10
-5
0
5
VI (5w)-Switch Analog Voltage-V

10

-75 -50 -25
0
25
50 75 100 125
T A - Free-Air Ternperature-° C

FIGURE 3

FIGURE 4

-'!1

TEXAS
INSTRUMENTS
7-14

I

I,:_SV

I:

I

~

I:

70

CJ)

I:

400

t:
.;;;

..c:

·3

c:I

.."
..a:'"

I:

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
D2922, JANUARY 1986-REVISED OCTOBER 1988

•
•
•
•
•
•

TLC4016M , , , J OR N PACKAGE
TLC40161 , , ' D OR N PACKAGE

High Degree of Linearity
High On-Off Output Voltage Ratio

(TOP VIEW)

Low Crosstalk Between Switches
Low On-State Impedance ',' . 50
VCC - 9 V

n Typ

1A
1B
2B
2A
2C
3C

at

Individual Switch Controls
Extremely Low Input Current

GND

VCC
1C
4C
4A
4B
3B
3A

description
The TLC4016 is a silicon-gate CMOS quadruple
analog switch designed to handle both analog
and digital signals. Each switch permits signals
with amplitudes up to 12 V peak to be
transmitted in either direction.

logic symbol t
1C
1A

2C

2A

Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.
Applications include signal gating, chopping,
modulation or demodulation (modem). and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.

3C

3A

4C
4A

(13)
(1)

n

(2)

n

n

(3)

n

n

(9)

n

(10)

n

X1
1

1

(5)
(4)

(6)
(8)

(12)
(11 )

n

1B

2B
3B

4B

t This symbol is in accordance with ANSI/IEEE Std 91 1984 and
lEe Publication 617-12,

The TLC4016M is characterized for operation
from - 55°C to 125°C, and the TLC40161 is
characterized from -40°C to 85°C,

logic diagram (positive logic)
A

B

C

PRODUCTION DATA documenls contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

TEXAS

~

Copyright © 1986, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-15

TLC4016M. TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
absolute maximum ratings over operating free-air temperature ~ange (unless otherwise noted)
Supply voltage range (see Note 1) ..................................... -0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) ............................. "
±20 rnA
1/0 port diode current (VI < 0 or VIIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
On-state switch current (VIIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 rnA
Continuous total dissipation .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. see Dissipation Rating Table
Operating free-air temperature range: TLC4016M ........................ - 55°C to 125°C
TLC40161 .......................... -40°C to 85°C
Storage temperature range .............................. :........... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260°C
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package ............. 300°C
NOTE 1: All voltages are with respect to ground unless otherwise specified.
DISSIPATION RATING TABLE
PACKAGE

TA';; 25°C

DERATING FACTOR

POWER RATING

ABOVE TA - 25°C

TA - 70°C
POWER RATING

TA - 85°C
POWER RATING

TA - 125°C
POWER RATING

D

950 mW

7.6 mW/oe

608mW

494mW

NIA

J

1375 mW

880 mW

715 mW

275 mW

N

1150mW

11.0 mW/oe
9.2 mW/oe

736 mW

598 mW

230 mW

recommended operating conditions
MIN

NOM

MAX

Supply voltage, Vee

2t

5

12

V

1/0 port voltage, VIIO

0

Vee

V

1.5

Vee

3.15

Vee

6.3

Vee

8.4
0

Vee
0.3

0

0.9

0

1.8

High-level input voltage, VIH

Low-level input voltage, VIL

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

Input rise time, tr

Vee
Vee

Input fall time, tf

Operating free-air temperature, T A

Vee
Vee

=2V
= 4.5 V
=9V
= 12V
=2V
= 4.5 V
=9V
= 12 V
=2V
= 4.5 V
=9V
=2V
= 4.5 V
=9V

0

UNIT

V

V

2.4
1000
500

ns

400
1000
500

ns

400

Vee
TLe4016M

-55

125

TLe40161

-40

85

°e

tWith supply voltages at or near 2 V, the analog switch on·state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.

TEXAS

~

INSTRUMENTS
7-16

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC4016M, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH

electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted).
PARAMETER

TEST CONDITIONS
IS

~

~

VA

0 to Vee,

See Figure 1

On-state switch

rSon

1 mA,

IS

resistance

VA

~

1 mA,

~

OorVee,

See Figure 1
~

On-state switch

VA

0 to Vee,

resistance matching

See Figure 1
VI ~ 0 or Vee

II

ISoff

ISon

lee

ei

Control input current

~

0 or Vee,

TA

~

25°e

Off-state switch

Vs

~

±Vee,

leakage current

See Figure 2
~

On-state switch

VA

leakage current

See Figure 3

Supply current

Input capacitance

Feedthrough
ef

VI

capacitance

VI

~

10

~

A to B

t All typical values are at T A

VI

~

0

TLC4016M
Typt
MAX

MIN

TLC40161
Typt
MAX

4.5 V

100

220

100

200

9V

50

120

50

105

12 V

30

100

30

85

2V

120

240

120

215

4.5 V

50

120

50

100

9 V

35

80

35

75

12 V

20

70

20

60

4.5 V

10

20

10

20

9V

5

15

5

15

12 V

5

15

5

15

2V

±1

±1

±0.1

±0.1

to

UNIT

\l

\l

pA

5.5 V

±10

±600

±10

±600

9 V

±15

±800

±15

±BOO

12 V

0 or Vee,
0

A or B

MIN

6 V

OorVee,

e

Vee

± 20 ± 1000

±20 ± 1000

5.5 V

±10

± 150

±10

± 150

9V

±15

±200

±15

±200

12 V

± 20

±300

±20

±300

5.5 V

2

40

2

20

9V

B

160

8

80

12 V

16

320

16

160

2 V to

15

12 V

5

2 V to
12 V

5

15
10

5
5

10

nA

nA

pA

pF
pF

25 De.

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-17

TLC4016M. TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH

= 50 pF (unless

switching characteristics over recommended operating free-air temperature range, CL
otherwise noted)
PARAMETER

TEST CONDITIONS

Propagation delay time,
tpd

ton

toft

Vcc

See Figure 4

A to B or B to A

RL

Switch turn-on time

~

1 k{l,

RL

~

1 k{l,

(channel loss

~

25

75

25

62

5

15

5

13

9V

4

14

4

12

12 V

3

13

3

11

2V

32

150

32

125

4.5 V

8

30

8

25

9V

6

18

6

15

12 V

5

15

5

13

2 V

45

252

45

210

4.5 V

15

54

15

45

9 V

10

48

10

40

12 V

8

45

8

38

4.5 V

100

100

9V

120

120

3 dBI

Control feedthrough voltage
VOCFIPPI

to any switch, peak to peak

TlC40161
Typt
MAX

MIN

2V

See Figures 5 and 6

Switch cutoff frequency
fco

TlC4016M
Typt
MAX

4.5 V

See Figures 5 and 6

Switch turn·off time

MIN

See Figure 7

4.5 V

See Figure 8

4.5 V

350

UNIT

ns

ns

ns

MHz
350

mV

Frequency at which crosstalk

attenuation between any two

1

1

switches equals 50 dB
t All typical values are at T A ~ 25°C.

PARAMETER MEASUREMENT INFORMATION
Vcc

VI = VCC

C Xl
TEST
SWITCH

1 B

-4--IS

FIGURE 1. TEST CIRCUIT FOR ON-STATE RESISTANCE
VCC
VI

=

0

C Xl
TEST
SWITCH

B

VB

Vs = VA - VB
CONDITION 1: VA
CONDITION 2: VA

=

0, VB

= VCC,

=

VCC

VB

=0

FIGURE 2. TEST CIRCUIT FOR OFF-STATE SWITCH LEAKAGE CURRENT

TEXAS

~

INSTRUMENTS
7-18

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MHz

TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC

VI

=

C.-----'---....

VIH--"iX1

TEST
SWITCH

B

t----,

A 1

FIGURE 3. TEST CIRCUIT FOR ON·STATE SWITCH LEAKAGE CURRENT
VCC

I
C X1
B OR A

TEST
SWITCH

-I- Vo
'TSO pF

TEST CIRCUIT

/"

-----..J

I
I

loll

.1

tpd

I
I

B~~A

________

~~'%

VOLTAGE WAVEFORMS

FIGURE 4. PROPAGATION DELAY TIME, SIGNAL INPUT TO SIGNAL OUTPUT

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-19

TlC4016M, TlC40161
SILICON-GATE CMOS OUADRUPLE BILATERAL ANALOG SWITCH

PARAMETER MEASUREMENT INFORMATION
VCC

C Xl
A

1 k\l

TEST
SWlfCH
(1 OF 4)

J-'s'--.....-

t

.....-VO
50PF

TEST CIRCUIT

},..OO-YO---------------"""'~o~
-----' I

14

-------

I
~I

I

ton

=

tpZL

toff

=

tpLZ

Vo------~"o%

14

-Vee
OV

~I

I

!~

-Vee

\\.,________________...;jlo~ __ --V"
VOLTAGE WAVEFORMS

FIGURE 5. SWITCHING TIME (tpZL, tPLZ), CONTROL TO SIGNAL OUTPUT

TEXAS,~

INSTRUMENTS
7-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC4016M. TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH

PARAMETER MEASUREMENT INFORMATION
VCC

C

,.....-_-1-_-..,

VI-+-'-IX1

TEST

A
50 pF

1 kll

TEST CIRCUIT

---'""""\

-

-

~%

-----VCC

"

I

toff ~ tPHZ-1I~4-~

~OV

VOLTAGE WAVEFORMS

FIGURE 6. SWITCHING TIME (tpZH, tPHzL CONTROL TO SIGNAL OUTPUT

'Ii1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-21

TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH

PARAMETER MEASUREMENT INFORMATION
VCC
VI---iX1

TEST
SWITCH
(1 OF 41

I--.....-~.-VO

I 5 0 pF -=600 [J

TEST CIRCUIT

"%1\-_- --------,

jf90%

VI _ _ _ _ _

. . ;.10; . '*~O( i

I,

14--+1- Ir

\

I

.10%

OV

~II

~------i

Vo-------t __________ ~n

_ _ _ _ _ _

VOLTAGE WAVEFORMS

FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC

X1

VI -

----+--1

....

X2

600 [J

2

TEST
SWITCH
11 OF 41

2

V02

=

V02

I

-=

=

n

-=

TEST
SWITCH
(1 OF 41

-=
NOTE: AOJUST I lor ax

V01
600

600

n

50PF
-=

50 dB.

V01

FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES, TEST CIRCUIT

'111

TEXAS
INSTRUMENTS
7-22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~or

TLC4066M, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
02922. JANUARY 1986-REVISEO OCTOBER 1988

TLC4066M ... J OR N PACKAGE
TLC40661 ... 0 OR N PACKAGE

•

High Degree of Linearity

•

High On-Off Output Voltage Ratio

•

Low Crosstalk Between Switches

•

Low On-State Impedance ... 30 fl Typ at
VCC - 12 V

•

Individual Switch Controls

(TOP VIEW)

•

Extremely Low Input Current

•

Functionally Interchangeable with National
Semiconductor MM54/74HC4066, Motorola
MC54/74HC4066, and RCA CD4066A

1A
1B
2B
2A
2C
3C

GND
logic symbol t
1C

description

1A
2C
2A
3C
3A

The TLC4066 is a silicon-gate CMOS quadruple
analog switch designed to handle both analog
and digital signals. Each switch permits signals
with amplitudes up to 12 V peak to be
transmitted in either direction.
Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.

VCC
1C
4C
4A
4B
3B
3A

4C

4A

113)
(1 )

n

12)

n

n

(3)

n

n

19)

n

(10)

n

X1
1

1

15)
14)
16)
18)
112)
111 )

n

1B
2B
3B
4B

t This symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.

Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
The TLC4066M is characterized for operation
from - 55 DC to 125 DC. The TLC40661 is
characterized from - 40 DC to 85 DC.
logic diagram (positive logic)
A

VCC

B

C

PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the ,terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.

~

Copyright © 1986, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-23

TLC4066M, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
1/0 port diode current (VI < 0 or Vila> VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
On-state switch current (Vila = 0 to VCC) . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. ± 25 rnA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ± 50 rnA
Continuol,ls total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. see Dissipation Rating Table
Operating free-air temperature: TLC4066M . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
TLC40661 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
NOTE 1: All voltages are with respect to ground unless otherwise specified.
DISSIPATION RATING TABLE
PACKAGE
D

TA s 25°C

DERATING FACTOR

POWER RAtiNG

ABOVE TA - 25°C

950 mW
1375 mW

N

1150mW

7.6 mW/oe
11.0 mW/oe
9.2 mW/oe

TA - 70°C
POWER RATING

TA - 85°C
POWER RATING

TA - 125°C
POWER RATING

608 mW

494mW

NIA

880 mW

715 mW

275 mW

736 mW

598 mW

230 mW

recommended operating conditions
MIN

NOM

MAX

Supply voltage, Vee

2t

5

12

V

1/0 port voltage, VIIO

0

Vee

V

1.5

Vec

Vee = 2 V
High-level input voltage, VIH

Low-level input voltage, VIL

3.15

Vee

Vee = 9 V

6.3

Vee

Vee=12V

8.4

Vee = 4.5 V

Vee = 2 V

0

Vee
0.3

Vee = 4.5 V

0

0.9

Vee = 9 V

0

1.8

Vee = 12 V

0

2.4

Input fall time, tf

Operating free-air temperature, T A

V

V

1000

Vee = 2 V
Input rise time, tr

UNIT

Vee = 4.5 V

500

Vee = 9 V

400

Vee = 2 V

1000

Vee = 4.5 V

500

Vee = 9 V
TLe4066M

400
-55

125

TLe40661

-40

85

ns

ns

°e

tWith supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.

-1!1

TEXAS
INSTRUMENTS
7-24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC4066M, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER

TEST CONDITIONS
IS = 1 mA,
VA = 0 to Vee,
See Figure 1

On-state switch
rSon

resistance

IS = 1 mA,
VA=OorVee,
See Figure 1

On-state switch

VA = OtoVee,

resistance matching

See Figure 1

Control input current

VI = 0 or Vee

VCC

MIN

4.5 V

TlC4066M
Typt
MAX
100

220

MIN

TlC40661
Typt
MAX
100

200
105

9V

50

110

50

12 V

30

90

30

85

2 V

120

240

120

215

4.5 V

50

120

50

100

9 V

35

SO

35

75

12 V

20

70

20

60

4.5 V

10

20

10

20

9 V

5

15

5

15

12 V

5

15

5

15

UNIT

!l

!l

2V
II

or

±1

±1

fA

6V
Off,state switch
ISoff

ISon

lee

ei
ef

leakage current

Vs = ±Vee,
See Figure 2

On-state switch

VA = 0 or Vee,

leakage current

See Figure 3

Supply current

VI = 0 or Vee,
10 = 0

Input capacitance

Feedthrough

capacitance

A or B
e
A to B

VI = 0

5.5 V

±10

±600

±10

±600

9V

±15

±SOO

±15

±800

12 V

±20 ± 1000

±20 ± 1000

5.5 V

±1O

± 150

±10

± 150

9V

±15

± 200

±15

±200

12 V

±20

±300

±20

±300

5.5 V

2

40

2

20

9V

8

160

8

SO

12 V

16

320

16

160

2 V to

15

12 V

5

2 V to
12 V

5

15
10

5
5

10

nA

nA

fA

pF
pF

t All typical values are at T A = 25 De.

~

TEXAS
INSTRUMENTS
POST OFFICE BOX e55303 • DALLAS, TEXAS 75265

7-25

TLC4066M, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

Propagation delay time,
tpd

ton

toff

See Figure 4

A to B or B to A

Switch

turn~on

Vcc

RL

time

=

1 k(J,

RL

=

1 k(J,

Ichannel loss

=

VOCFIPP)

to any switch, peak to peak

TLC40661
Typt
MAX

25

75

15

5

15

5

13

9 V

4

12

4

10

12 V

3

13

3

11

2V

32

150

32

125

8

30

8

25

9V

6

18

6

15

12 V

5

15

5

13

2 V

45

252

45

210

4.5 V

15

54

15

45

9 V

10

48

10

40

12 V

8

45

8

38

4.5 V

100

100

9V

120

120

See Figure 7

4.5 V

See Figure 8

4.5 V

ns

ns

ns

MHz
350

350

UNIT

30

4.5 V

3 dB)

Control feedthrough voltage

MIN

2V

See Figures 5 and 6

Switch cutoff frequency
fco

TLC4066M
Typt
MAX

4.5 V

See Figures 5 and 6

Switch turn-off time

MIN

rnV

Frequency at which crosstalk

attenuation between any two

1

switches equals 50 dB
t All typical values are at T A

=

25°C.

PARAMETER MEASUREMENT INFORMATION
Vcc

VI

=

VCC

C

Xl
TEST
SWITCH

1

B

+--IS

FIGURE 1. TEST CIRCUIT FOR ON-STATE RESISTANCE
VCC
VI

=

0

C Xl
TEST
SWITCH

Vs =

B

VA - VB

CONDITION 1: VA
CONDITION 2: VA

=
=

=

VCC

Vcc, VB

=0

O. VB

FIGURE 2. TEST CIRCUIT FOR OFF-STATE SWITCH LEAKAGE CURRENT

TEXAS .."
INSTRUMENTS
7-26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

MHz

TLC4066M, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC

VI

=

Cr---...L...---,
VIH---.:::.tXl
TEST
SWITCH

B

t-=--...,

A 1

FIGURE 3. TEST CIRCUIT FOR ON·STATE SWITCH LEAKAGE CURRENT
VCC

I
C
VI

Xl
TEST
SWITCH

A OR B 1

B OR A

I - - -...... VO

t50 pF

TEST CIRCUIT

;,-O-%--------,'i:-.--- --:~'
I

_ _ _ _ _-J

I
I

I

14

.1

tpd

tpd

I..

I
I

B~~A

_______

.1
I
I

-J~O.

~:~"

VOLTAGE WAVEFORMS

FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-27

TlC4066M, TlC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC

VI _ _C
"-!X1
A

1 kr!

TEST
SWITCH
11 OF 4)

t-=B=--.....-+--VO

l'

50 pF

TEST CIRCUIT

f,..oo-Yo---------------"""'\Z,~
----' I

I"
Vo

-------

-'CC

ov

I

.1

1

=

ton

-------,i"\,%

tpZL

toff

=

tpLZ

I..

.1
I

!/'"

----------------~},,~ - - --'0'

\1...

VOLTAGE WAVEFORMS

FIGURE 5. SWITCHING TIME (tPZL, tPLZl. CONTROL TO SIGNAL OUTPUT

~

TEXAS
INSTRUMENTS
7-28

. 'CC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC4066M. TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMetER MEASUREMENT INFORMATION
Vee

e Xl
A

TEST CIRCUIT

- - -........

Vee

VI

----..It. ___"
I

I4-+t- ton

=

-

-

~%

toff

tpZH

=

- - ---Vee

"

I

tpHZ -111+0lil-+1

I

1

VO _ _ _ _ _ _

. I~'-l£!O

VOH

_____

~

0 V
~

0 V

VOLTAGE WAVEFORMS

FIGURE 6. SWITCHING TIME (tPZH, tPHZ), CONTROL TO SIGNAL OUTPUT

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-29

TLC4066M, TLC40661
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
Xl

TEST
SWITCH
(1 OF 4)

Vo

-r

-=

600

n

5OPF

-=

TEST CIRCUIT

V,

90%~ - - -

/:00%
i

!I

_ _ _ _ _....;.10.;";OA;;,,JO(

-

-

-----V

\10%

)~~-------OV

vo-t_____________________
f=-----:L1
14--+1- t,

~tf

VOLTAGE WAVEFORMS

FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC

Xl

TEST
SWITCH
(1 OF 4)

VI
X2

600 n

TEST
SWITCH
(1 OF 4)

2

VOl

-=
2

-::-

NOTE: ADJUST f fo, aX

=

V02

=

V02

I

600 n
50PF

-::-

50 dB.

VOl

FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES, TEST CIRCUIT

TEXAS . "
INSTRUMENTS
7-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-1

_.

-

."

.....
(I)
-or

tJ)

8-2

TLC04/MF4A·50, TLC14/MF4A·100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
02970, NOVEMBER 1986-REVISED NOVEMBER 1988

•

•

D8

D OR P PACKAGE

Low Clock-to-Cutoff-Frequency Ratio Error
TLC04/MF4A-50 , .. ± 0.8%
TLC14/MF4A-100 ... ± 1 %

(TOP VIEWI

ClKIN
CLKR

Filter Cutoff Frequency Dependent Only on
External-Clock Frequency Stability

lS
VCC -

•

Minimum Filter Response Deviation Due to
External Component Variations Over Time
and Temperature

•

Cutoff. Frequency Range from 0.1 Hz to
30 kHz. VCC± - ±2.5 V

•

!i-V to 12-V Operation

•

Self Clocking or TTL-Compatible and CMOSCompatible Clock Inputs

•

Low Supply Voltage Sensitivity

•

Designed to be Interchangeable with
National MF4-50 and MF4-100

2

7

FILTER IN
VCC+

3

6

AGND

4

5

FILTER OUT

description
The TLC04/MF4A-50 and TLC 14/MF4A-1 00 are monolithic Butterworth low-pass switched-capacitor filters.
Each is designed as a low-cost. easy-to-use device providing accurate fourth-order low-pass filter functions
in circuit design configurations.
Each filter features cutoff frequency stability that is dependent only on the external-clock frequency stability.
The cutoff frequency is clock tunable and has a clock-to-cutoff frequency ratio of 50: 1 with less than
± 0.8% error for the TLC04/MF4A-50 and a clock-to-cutoff frequency ratio of 100: 1 with less than ± 1 %
error for the TLC14/MF4A-1 00. The input clock features self-clocking or TTL- or CMOS-compatible options
in conjunction with the level shift (LS) pin.
The TLC04M/M F4A-50M and TLC 14M/MF4A-1 OOM are characterized over the full military temperature
range of - 55°C to 125°C. The TLC041/MF4A-501 and TLC141/MF4A-1 001 an~ characterized for operation
from - 40°C to 85 °C. The TLC04C/MF4A-50C and TLC14C/MF4A-1 DOC are characterized for operation
from DoC to 70°C.

functional block diagram
(7)

Vcc+-(3)

lS------------~~---

-VCC+-

LEVEL

----,

(3)1 LS

I

I

CMos:uI-+_S_V-+__
CLKIN
-5 V

I
I
I
I
I

~1~1)~I~C~LK~IN~

I

12) CLKR

I
I

18)1 FILTER IN

BUTTERWORTH
FOURTH-ORDER
LOW-PASS FILTER

16)1 AGND

I
L ______

~~~

I
FILTER IS)
OUT

I

_______

~

14)
-SV---,~------------------~

FIGURE 3. CMOS-CLOCK-DRIVEN, DUAL-SUPPLY OPERATION
SV-----.~-----------------.

(7)

---,

TTLlJl-SV
CLKR

------~~----------------~

ov

18) JFILTER IN

=~~!~:~~~~~

16)1 AGND

LOW-PASS FILTER

L

---- --·J41 -- -- --VCC-

-S V

FIGURE 4. TTL-CLOCK-DRIVEN, DUAL-SUPPLY OPERATION

~

TEXAS
INSTRUMENTS
8-10

FILTER (5)
OUT I

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I

J

TLC04/MF4A·50, TLC14/MF4A·100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
TYPICAL APPLICATION OAT A

5V--------------------------,

r ---- __ b _____ ---,
VCC+

LEVEL

(3)ILS

I
(1)ICLKIN

1'C
+-__-..:(....;8)..:,.1F_IL_T_ER__IN____________---t

F(L TER __
INPUT

(6)1 AGND

BUTTERWORTH
FOURTH-ORDER
LOW-PASS FILTER

FILTER

(5)

OUT

-= IL ______VCC-_ _ _ _ _ _ _ _ .J
(4)

-5V--~--------------------~

fclock

=

RC x In

For VCC -

f

~(V

)~

LV~~=~~: V~~~
) (V

10 V.

_ _1 _
clock
1_69 RC

FIGURE 5. SELF·CLOCKING THROUGH SCHMITT·TRIGGER OSCILLATOR. DUAL·SUPPLY OPERATION

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

8-11

/1
II

TLC04/MF4A·50, TLC14/MF4A·100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
TYPICAL APPLICATION DATA
+10V--~-----'---------------------,

(7)

r - - - - -

VCC

+-

-

l~E;:- -

-

-

-,

(3)1 lS

- + 10 V

~

CMOS
ClKIN

(SEE NOTE A)

(1)IClKIN

--+-----+---'-'.:..;-:~~-iD :>0---1

I

I

oV

I

TTQfl- - 5 _V-+____

~f---(-2)....:I-c-l-KR-----------------I

I

CLKR

oV
FilTER IN ~ 5 VOC
(SEE NOTE B)

10 kll

I

(8d FILTER IN
---+------+---'-'''-;-'-'=-==-=----------------;
(6) I AGND

I

L _____

~~~

10 kll

BUTTERWORTH
FOURTH-ORDER
LOW-PASS FilTER

_______

(4)

(SEE NOTE C)

NOTES:

A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger.
B. The Filter input signal should be dc-biased to mid-supply or ac-coupled to the terminal.
C. The AGND terminal must be biased to mid-supply.

FIGURE 6. EXTERNAL-CLOCK-DRIVEN SINGLE-SUPPLY OPERATION

TEXAS . "
INSTRUMENTS
8-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FilTER
OUT
~

(5)

TLC04/MF4A·50, TLC 14/MF4A·1 00
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
TYPICAL APPLICATION DATA
+10V------------~------------------------~

r - - - - - - - -

(7)

-;CC+ -

-

-

-

-

-

-

-

.,

lEVEL
(3)

lS

(1)

ClKIN

(2)

ClKR

(8)

FilTER IN

(6)

AGND

10 k!l

0.11'F

BUTTERWORTH
FOURTH-ORDER
LOW-PASS FilTER

L ________

VCC.:.. _ _ _ _ _ _ _ _

10 k!l
(SEE NOTE A)

fclock -

FilTER
OUT

(5)

..J

(4)

RC x In

[(~~~ = ~~:) (~~~)J

For VCC - 10 V,
fclock -

1

1:69iiC

NOTE A: The AGND terminal must be biased to mid-supply.

FIGURE 7. SELF-CLOCKING THROUGH SCHMITT-TRIGGER OSCILLATOR. SINGLE-SUPPLY OPERATION

I

I'
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-13

TLC04/MF4A·50, TLC 14/MF4A·1 00
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
TYPICAL APPLICATION OAT A
5V--~------------------------------~

(7)

r - - - - - - --VCC+----------,
LEVEL
(3)

LS

-r__+-____~(l~)~C~LK~IN~_;

CLOCK __
INPUT

(2)

CLKR

(8)

FILTER IN
AGND

(6)

10kll~-+-"

FOURTH-ORDER
LOW-PASS FILTER

L _________ VCC.:.. _ _ _
0.1 fLF

(4)

-5V--~--~~~----------------------~

FIGURE 8. DC OFFSET ADJUSTMENT

TEXAS

~

INSTRUMENTS
8-14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FILTER
OUT

_____

...l

(5)

TLC1 O/MF1 OAr TLC20/MF10C
UNIVERSAL DUAL SWITCHED-CAPACITOR FILTER
02952. AUGUST 198!)-REVISEO NOVEMBER 1988

•

N DUAL-IN-lINE PACKAGE

Maximum Clock to Center-Frequency Ratio
Error
TLC10 ... ±0.6%
TLC20 ... ± 1.5%

(TOP VIEWI

•

Filter Cutoff Frequency Stability Dependent
Only on External-Clock Frequency Stability

•

Minimum Filter Response Deviation Due to
External Component Variations over Time
and Temperature

•

Critical-Frequency Times Q Factor Range Up
to 200 kHz

•

Critical-Frequency Operation Up to 30 kHz

•

Designed to be Interchangeable with:
National MF10
Maxim MF10
Linear Technology LTC1060

1 LP
lBP
lNAH
l1NlAPIN
SW

2LP
2BP
2NAH
21N2APIN
AGND

VCC+
VDD+
LS
lCLK

VCCVDDCF/CL
2CLK

FN CHIP CARRIER PACKAGE
(TOP VIEW)
I
«Cl.Cl.Cl.Cl.

ZOJ...J...JOJ
...-..-..-NN

3

description
The TLC10/MF10A and TLC20/MF10C are
monolithic general-purpose switched-capacitor
CMOS filters each containing two independent
active-filter sections. Each device facilitates
configuration of Butterworth, Bessel, Cauer, or
Chebyshev filter design.
Filter features include cutoff frequency stability
that is dependent only on the external clock
frequency stability and minimal response
deviation over time and temperature. Features
also include a critical-frequency times filter
quality (QI factor range of up to 200 kHz.
With external clock and resistors, each filter
section can be used independently to produce
various second-order functions or both sections
can be cascaded to produce fourth-order
functions. For functions greater than fourthorder, ICs can be cascaded.

2

I

20 19

18

liN lAPIN
SW

4
5

17

6

16

VCC+
VDD+

8

14

2NAH
21N2APIN

15
9 10 II 1213

AVAILABLE OPTIONS

TA

OOC

MAX
fclocklfc ERROR

±O.6%

to

70°C

±1.5%

PACKAGE
CHIP CARRIER
(FN)

PLASTIC DIP
(N)

TLC10CFN

TLC10CN

or

or

MF10ACFN

MF10ACN

TLC20CFN

TLC20CN

or

or

MF10CCFN

MF10CCN

The TLC10/MF10A and TLC20/MF10C are
characterized for operation from O°C to 70°C.

PRODUCTION DATA documents contain information
current 8S of publication date. Products conform to
specifications per the tarms of Texas Instruments
standard warranty. Production processing dOBS not
necessarily include testing of all parameters.

TEXAS

~

Copyright © 1986, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-15

TLC1 O/MF1 OA, TLC20/MF10C
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

PIN
NAME

NO.

I/O

DESCRIPTION

AGNO

15

I

Analog Ground - The noninverting inputs to the input operational amplifiers of both filter sections. This terminal

lAPIN

5

I

2APIN

16

should be at ground for dual supplies or at mid-supply level for single-supply operation.
All-Pass Inputs - The all-pass input to the summing amplifier of each respective filter section used for all-pass
filter applications in configuration modes 1 a, 4, 5, and 6. Thisc terminal should be driven from a source having
an impedance of less than 1 kO. In all other modes, this terminal is grounded. See Typical Application Data.
lBP

2

2BP

19

CF/CL

12

0

Band-Pass Outputs - The band-pass output of each respective filter section provides the second-order band-

I

Center Frequency/Current Limit - This input terminal provides the option to select the input-clock-to-center-

pass filter functions.
frequency ratio of 50: 1 or 100: 1 or to limit the current of the IC. For a 50: 1 ratio, the CF/CL terminal is set
to VOO +. For a 100: 1 ratio, the CF/CL terminal is set to ground for dual supplies or to mid-supply level for
single· supply operation. For current limiting, the CF/CL terminal is setto VOO _. This aborts filtering and limits
the IC current to 0.5 milliamperes.

lCLK

10

2CLK

11

I

Clock Inputs - The clock input to the two·phase nonoverlapping generator of each respective filter section
is used to generate the center frequency of the complex pole pair second-order function. Both clocks should
be of the same level (TTL or CMOSI and have duty cycles close to 50%, especially when clock frequencies
(fclockl greater than 200 kHz are used. At this duty cycle, the operational amplifiers have the maximum time
to settle while processing analog samples.

IIN-

4

21N-

17

lLP

1

2LP

20

LS

9

I

Inverting Inputs - The inverting input side of the input operational amplifier whose output drives the summing
amplifier of each respective filter section.

0
I

Low-Pass Outputs - The low-pass outputs of the second-order filters.
Level Shift - This terminal accommodates various input clock levels of bipolar (CMOS) or unipolar (TTL or
other clocks) to function with single or dual supplies. For CMOS (± 5~volt) clocks, VOO _ or ground is applied
to the LS terminal. For TTL and other clocks, ground is applied to the LS terminal.

lNAH

3

2NAH

18

SW

6

0

Notch, All-Pass, or High-Pass Outputs - The output of each respective filter section can be used to provide
either a second·order notch, all-pass, or high-pass output filter function, depending on circuit configuration.

I

Switch Input - This input terminal is used to control internal switches to connect either the AGNO input or
the LP output to one of the inputs of the summing amplifier. The terminal controls both independent filter sections
and places them in the same configuration simultaneously. If VCC _ is applied to the SW terminal, the AGNO
input terminal will be connected to one of the inputs of each summing amplifier. If Vec + is applied to the
SW terminal, the LP output will be connected to one of the inputs of the summing amplifier.

VCC+

7

Analog positive supply voltage terminal

VCC-

14

Analog negative supply voltage terminal

VOO+

8

VOO-

13

~igital

positive supply voltage terminal

Digital negative supply voltage terminal

~

TEXAS
INSTRUMENTS
8-16

POST OFFICE BOX 65530~ • DALLAS, TEXAS 75265

TLC1 0/MF1 OA, TLC20/MF1 DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

functional block diagram

....

1CLK 110)
LS
CF/CL

IN-,
AGNO

<1>1

j+

19)

NONOVERLAPPING

112)

CLOCK GENERATOR

<1>2

'--

....

14)

13)

I~

115)

12)

'-- +
1APIN

I--

CONTROL

r---

1:1>

II>

'--

15)

1BP

II>

-

-

1NAH

'-11 )

+

+

r-- -

1LP

~ --4
SW

16)

I
2CLK

-"'-- ....

111 )

<,11

I~
....

NONOVERLAPPING
CONTROL

21N-

I--

CLOCK GENERATOR

-

<1>2

-

....
I:
.....

117)

118)
119)

'-- +
116)

1:1>

II>

'-'--

2APIN

r- ~

2NAH
2BP

II>

'-'---

+

+

120)

2LP

~

r -"'---

'--

TEXAS

-'II

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-17

TLC1 0/MF1 OAr TLC20/MF1 DC
UNIVERSAL DUAL SWITCHED-CAPACITOR FILTER
absolute. maximum ratings over operating free-air temperature range (unless otherwise noted)
Analog supply voltage, Vee ± (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 7 V
Digital supply voltage, VDD ± ................................................ ± 7 V
Operating free-air temperature range .... '.................................. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 1 50 °e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 0 e
NOTE 1: All voltage values are with respect to the AGND terminal.

recommended operating conditions
MIN

NOM

MAX

Analog supply voltage, VCC ±, (see Note 2)

+4

±5

±6

Digital supply voltage, VDD +, (see Note 2)

+4

±5

±6

V

0.008

1.0

MHz

0

70

°c

Clock frequency, f clock, (see Note 3)
Operating free-air temperature, T A
NOTES:

= ± 5 V, Voo ± + = ± 5 V, T A = 25 °e (unless otherwise noted)
TLC10lMF10A
TEST CONDITIONS

PARAMETER
Maximum peak-to-peak output

ICC

RL

voltage swing
Short-circuit output

lOS

V

2. A common supply voltage source should be used for the analog and digital supply voltages. Although each has separate terminals,
they are connected together internally at the substrate. VCC + and VDD + can be connected together at the device terminals
or at the supply voltage source. The same is true for VCC _ and VDD _.
3. Both input clocks should be of the same level type (TTL or CMOSI, and their duty cycles should be at 50% above 200 kHz
to allow the operational amplifiers the maximum time to settle while processing analog samples.

electrical characteristics at Vee ±

VOPP

UNIT

current, Pins 3 and 18

I Source
I Sink

~

3.5 kll at all outputs

MIN

TYP

±4

±4.1

See Note 4

MIN

TYP

±3.8

±3.9

2

2

50

50
10

8

Supply current

TLC20lMF10C

MAX

MAX

UNIT
V
mA

8

10

mA

NOTE 4: The short-circuit output current for pins 1, 2, 19, and 20 will be typically the same as pins 3 and 18.

operating characteristics at Vee ±
PARAMETER
Critical-frequency range

Maximum clock
frequency, f clock
Clock to center-frequency

ratio
Temperature coefficient of
center frequency

Filter Q (quality factor)
deviation from 20
Temperature coefficient of

= ± 5 V, Voo ± = ± 5 V, TA =

TEST CONDITIONS
fa x Q " 200 kHz

MIN

TYP

20

30

R1

from unity gain

Mode 1,

=

R2

=

20

30

MAX

1.5

1

1.5

50.24

49.24

49.94

See Figure 1 Pin 12 at 0 V

98.75

99.35

99.95

97.86

99.35 100.84

~

~

20, Pin 12 at 5 V

±10

+10

See Figure 1 Pin 12 at 0 V

±100

+100

R3/R2

=

±2%
±2%

20, Pin 12 at 5 V

See Figure 1 Pin 12 at 0 V
R3/R2

=

20,

ppm/oC

+2%

+6%

±3%

+2%

+6%
ppm/oC

±500

±2%

±2%

See Figure 1

MHz
50.64

±4%

± 500

10 kll

UNIT
kHz

49.94

R3/R2

Low-pass output deviation

TYP

1

fa " 5 kHz,
Mode 1,

measured filter Q

TLC20lMF10C
MIN

49.64

R31R2

fa " 5 kHz,
Mode 1

MAX

10, Pin 12 at 5 V

See Note 3
fa " 5 kHz,
Mode 1,

fa " 5 kHz,
Mode 1,

25°e (unless otherwise noted)

TlC10lMF10A

Crosstalk attenuation

60

60

as

Clock feedthrough voltage

10

10

mV

2.5

2.5

MHz

7

7

V/~s

Operational amplifier

gain-bandwidth product
Operational amplifier
slew rate

TEXAS

~

INSTRUMENTS
8-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

nct D/MFl DA, nC2D/MFl DC
UNIVERSAL DUAL SWITCHED-CAPACITOR FILTER

TYPICAL APPLICATION OAT A
modes of operation
The TLC 1 0/MF1 OA and TLC20/MF10C are switched-capacitor (sampled-data) filters that closely
approximate continuous filters. Each filter section is designed to approximate the response of a secondorder variable filter. When the sampling frequency is much larger than the frequency band of interest, the
sampled-data filter is a good approximation to its continuous time equivalent. In the case of the
TLC1 0/MF1 OA and TLC20/MF1 OC, the ratio is about 50: 1 or 100:1. To fully describe their transfer function,
a time domain approach would be appropriate. Since this may appear cumbersome, the following application
examples are based on the well known frequency domain. It should be noted that in order to obtain the
actual filter response, the filter's response must be examined in the z-domain.
!clock

r-IClK

VI

- - - - - - - - - - --.
y, TlC10/MF10A TLC20/MF10C

I

I

R1
IIN_
IAGND

*I
APIN

NONOVERlAPPING
CLOCK GENERATOR

.....
I~

I

~
2

I
NAHI

...

NOTCH OUT

I

I

BP I

I

I

'-+

1

+1
I __"- --

Et>

''--

Jt>

Jt>

-

I

'---

lPI
'--- +

lOW-PASS OUT

+

H

I

I

VDD+~

R3

: I~r-

L ___

BAND-PASS OUT

R2

I
I

- - ---- ---- ------

..J

10 = Iclockl100 or Iclock/50
Inotch = 10
HOlP = - R2/Rl (as I - 01
HOBP = -R3/Rl (at I = 101
. {as I approaches 0 - R2/R 1
HON = notch gain as I approaches 0.5 Iclock
Q = 10/BW = R3/R2
Circuit dynamics:

The fol/owing expressions determine the swing at each output as a function of the desired Q of the
HOLP = HOBp/Q or HOLP X Q = HON x Q
HOLP (peakl = Q X HOLP (lor high Qsl

second~order

FIGURE 1. MODE 1 FOR NOTCH, BAND-PASS, AND LOW-PASS OUTPUTS: fnotch

function.

to

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-19

TLC1 O/MF1 OAf TLC20/MF1 DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

TYPICAL APPLICATION DATA
fclock

r-IelK
IIN_
IAGND

~

-- -- - - - - -- --,
'h TLC10/MF10A TLC20/MF10C

I

1/>1
NONOVERlAPPING t--1/>2
CLOCK GENERATOR t--

....

I
NAHI

.....

I

I

I

BPi

I

I

-+
APIN I

);1>

-

JI>

'---

I
I

NON INVERTING
BAND-PASS OUT (BP2)

1+

-__
"-

VDD+~

-

-

JI>

-

I
lPI

!--- +

lOW-PASS OUT

+
I
I

:l~

L ___

BAND-PASS OUT (BP1)

R3
R2

I

------

_

I

_ _ ...1

fO = fclock/l00 or fclock/50
0= R3/R2
HOlP = - 1
HOlP (peak) = 0 x HOlP (for high Os)
HOBPl = - R3/R2
HOBP2 = 1 (noninverting)

Circuit dynamics:
HOBPl = 0

FIGURE 2. MODE 1 a FOR NON INVERTING BAND·PASS AND LOW·PASS OUTPUTS

TEXAS . "
INSTRUMENTS
8-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1 O/MF1 OA, TLC20/MF1 DC
UNIVERSAL DUAL· SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION OATA

,
- - -- - - - -- -,

fclock

'Ii TLC10/MF10A TLC20/MF10C

r-ICLK

VI
R1

IAGND

~

I---

~

I
NAHI

....

I

I

BPi

I

I

..... +

1

EI>

..... JI>
L.....-

~I

I

-

f[:>

L...

I
LPI

r--+

+

........ -~H

:LI~~
___

BAND-PASS OUT

L...-.-

-~

VDD+

NOTCH OUT

1+

I

APIN

CLOCK GENERATOR

...

I,N_

I

<1>1

NONOVERLAPPING

LOW-PASS OUT

I
I

R3

R2

1'14

I
I

--------- ...J

10 ~ Inotch x yR2/R4 + 1
Inotch ~ Iclock/l00 or Iclock/50
Q ~ y'R2/R4 + 1
R2/R3
HOLP las I approaches 01
HOBP lat I

~

101

~

~

-R2/Rl
R2/R4 + 1

- R3/Rl

HON 1 las I approaches 01 ~

-R2/Rl
R2/R4 + 1

HON2 las I approaches 0.5 Iclockl ~ - R2/Rl
Circuit dynamics:

HOBP ~ Q ~"'-O-LP---'-'X--;H"O-N-2 ~ Q t'\"10Nl x HON2

FIGURE 3. MODE 2 FOR NOTCH 2, BAND·PASS, AND LOW·PASS OUTPUTS: fnotch



L-

r-yc;-

I_~~

lPI

1--+

r--

I

'---

'---

+1

Jt>

L-

BAND-PASS OUT

lOW-PASS OUT

+
I

VDD-~

~..,

R3

I
:LI-~~
____________ ....1I
I

R2

I

R4 I

I

..L
"'T"

I

I

I

-'
10

=

(lclock/l00 or Iciock/501

a =~

y'R'27R4

x R3/RZ

HOHP (as I approaches 0.5 Iclockl
HOlP (as I approaches 01
HOBP (at I

=

101

=

= -

= -

RZ/Rl

R4/Rl

-R3/Rl

Circuit dynamics:

RZIR4 = HOHP/HOlp: HOBP = ~HOHP x HOlP x
HOlP (peakl = a x HOlP (lor high Osl

HOHP (peakl

=

a

a

x HOHP (lor high Osl

tin this mode, the leedback loop is closed arou~d the input summing amplilier; the linite GBW product 01 this operational amplifier will
cause a slight enhancement. II this is a problem, connect a low-value capacitor (10 pF to 100 pF) across R4 to provide some phase lead.

a

FIGURE 4. MODE 3 FOR HIGH·PASS, BAND-PASS, AND lOW-PASS OUTPUTS

TEXAS

~

INSTRUMENTS
8-22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1 O/MF1 OA, TLC20/MF10C
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

TYPICAL APPLICATION OATA
fclock

y, TLC10/MF10A, TLC20/MF10C

r--

----

-,

I

1-.::....:.::"-----_ _ _ _ _-1 NONOVERLAPPING
R1

I

CLOCK GENERATOR

BP

I

rl-t--------T,.....- t - l f - - - - - - - - B A N O - P A S S OUT
Ie>
+
VOO-

~>-----1+

,

I

Ri

I

,I

R3

SW

Rh

EXTERNAL
OPERATIONAL
AMPLIFIER
NOTCH OUT

R2
R4
L -_ _ _ _ _ _ LOW-PASS OUT

I

I
L ________ _ ___ ..J
fo

=

Q =

(fciock/lOO or fciock/50) .JR2/R4

.JR2/R4 x R3/R2

HOHP

=

-R2/Rl

HOBP = - R3/Rl
HOlP = -R4/Rl
fnotch = (fciock/100 or fclo c k!50) ,fRh/Ri
HON (at f = fo) = I Q (Rg/Ri x HOlP - Rg/Rh
HON 1 (as f approaches 0)

=

x

HOHP)

I

Rg/Ri x HOlP

HON2 (as f approaches 0.5 fclock)

= -

Rg/Rh

x

HOHP

FIGURE 5. MODE 3a FOR HIGH-PASS, BAND-PASS, LOW-PASS, AND
NOTCH OUTPUTS WITH EXTERNAL OPERATIONAL AMPLIFIER

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-23

TLCl O/MFl OA, TLC20/MF10C
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION OATA
fclock

VI

.-

r--

- - - - - - - - - - --.
y, TLC10lMF10A TLC20/MF10C

1
I NONOVERLAPPING I--2
CLOCK GENERATOR I--

ICLK
IIN_
IAGND

~I

....
I~"
....

I
NAHI

,

BP I

'-+

"--

I

-

- J[>

- J[>

1:[>

APIN I

-

-+

I
LPI

+

- -'----- ~

iLI~~
___

BAND-PASS OUT

I

LOW-PASS OUT

I

ISW

VDD+

ALL-PASS OUT

I

I
I

I

I

I

R1

I

R3

R2

I
I

- - ---- ---- ------ .J

fo ~ fclockl1 00 or fclock/50
fz ~ fa t

o
Oz

~

~

fo/SW

~

R3/R2

R3/R1

HOAP lat 0 oS f oS 0.5 fclock) ~ - R2/R1 ~ - 1
Ifor AP output R1 ~ R2)
HOLP las f approaches 0)
HOSp lat f

~

fo)

~

~

-IR2/R1

- R3/R2 IR2/R1

+ 1) ~ - 2
+ 1) ~ - 2 IR3/R2)

Circuit dynamics:

HOSp ~ HOLP x 0 ~ IHOAP

+ 1) 0

tDue to the sampled-data nature of the filter, a slight mismatch of fz and fo occurs causing a O.4-dS peaking around fo of the all-pass
filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.

FIGURE 6. MODE 4 FOR ALL-PASS, BAND-PASS. AND LOW-PASS OUTPUTS

"'!1

TEXAS
INSTRUMENTS
8-24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLCl O/MFl OAr TLC20/MFl DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION OAT A
fclock

r-IClK
IIN_
...

VI
J--

R1

IAGND

y, TLC10/MF10A TLC20lMF10C

I
I

<1>1
NONOVERlAPPING ~
<1>2
CLOCK GENERATOR f--

NAHI

I~

.....

~I

APIN

-- -- - ,- - - - - --,

COMPLEX ZERO OUT

I

I

BPi

I

I

I

'-+

l:e>

-

I

,..--

I

'--

-

r-yc;:-

+

10 ~ .JR2/R4

+

lPI

LOW-PASS OUT

I

'---

VDD+ ISW

:LI~r___

I

'---

'--- +

-'--- 1-4

Se>

-

BAND-PASS OUT

I

RJ

R2
R4

I
I

---------

-.J

1 X Ilclock/100 or Iclock/501

R1/R4 X Ilclock/100 or Iciock/501
I z ~ ";1
Q ~ ";R2/R4 + 1 X RJ/R2
Qz ~

-J1 -

R1/R4 X RJ/R1

HOZ1 las f approaches 01 ~ R2 IR4 - R11/R1 IR2 + R41
HOZ2 las 1 approaches 0.5 Iclockl ~ R2/R1
HOSp

~

IR2/R1 + 11

HOlP

~

IR2 + R11/1R2 + R4) x R4/R1

X

R3/R2

FIGURE 7. MODE 5 FOR NUMERATOR COMPLEX ZEROS, BAND-PASS, AND LOW-PASS OUTPUTS

-1!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-25

TLCl O/MF1 OA, TLC20/MFl DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION OATA
fclock

r-IClK

VI
R1

'INIAGND

-:!:-I

,

- --- -y,- - - -I NONOVERlAPPING

I

...

CLOCK GENERATOR

01>1

r-01>2

t--

I
I

NAHI

HIGH-PASS OUT

1+/

....

I

,
APIN

..

TlC10/MF10A. TlC20 IMF1 OC

BP I

J:'1>
-+

I

L-

"""'Tc>
-

'---

-:!:-I

I-~H

--

r----

+

J[>

-

lPI

VDD-~

L ___

I
I

------

(INVERTED)

I

+

:,-'-r-

lOW-PASS OUT

I

R3

R2

I
_ __ .JI

fe ~ R2/R3 lfeloek!100 or feloek/50)

HOlP

~

-R3/R1

HOHP

~

-R2/R1

FIGURE 8. MODE 6 FOR SINGLE-POLE HIGH·PASS AND LOW·PASS OUTPUT

TEXAS

~.

INSTRUMENTS
8-26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1 D/MF1 OAf TLC2D/MF1 DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION OAT A
!clock

r--

-- -- - - - - -- -,
'h TLC10/MF10A TLC20/MF10C

IIN_
IAGND

I

1
NONOVERlAPPING
2
CLOCK GENERATOR r-

r--

I ClK

....

I
NAHI

.....

~I

I

I

BP I

I
APIN

'-+

1

EI>

JI>

'--

-

'--

I
I

'-~H

-

-

r--+

JI>
+

:,-'-r-

L ___

=

lOW-PASS OUT
(INVERTED)

I
I
lPI

I
IR1

VDD-~

Ie

lOW-PASS OUT
(NON INVERTED)

1+

R2

I
I

- - - - - - - - - ..J

R2/R3 x (feloek/100 or fcloek/50)

HOLPl
HOLP2

= 1 (noninverting)
= - R3/R2

FIGURE 9. MODE 6a FOR SINGLE-POLE LOW-PASS OUTPUT (INVERTED AND NON INVERTED)

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-27

TLC 1O/MF 1OAr TLC20/MF 1DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

TYPICAL APPLICATION OATA
5V

T
vcc+
(6)

VCC+

(9)
(11)

200·kHz
TTL CLOCK

~
-=

INPUT

TLC10/MF10A, TLC20/MF10C

'2LP

SW
LEVEL SHIFT

2BP

2CLK

2NAH

(4)

.i.!.?2.

(20)

LOW-PASS

(19)

OUTPUT

(lB)

lCLK

CENTER FREOI
CURRENT LIMIT
CONTROL
(5)
lAPIN
(16)

lLP
lBP
lNAH
CF/CL

2APIN
l1N21N-

(1 )

(2)

~

~
R2

VCC-

1

-5 V

I
VOO+

R3

R2'

R3'

VOO-

I

R2 = 100 kU
R2 , = 100 kU
R3 = 53.6 kU
R3 '=130kU

FIGURE 10_ FOURTH-ORDER 2-kHz lOW-PASS BUTTERWORTH FilTER

filter terminology
fc
fclock
fnotch
fo
fz
HOSp
HOHP
HOLP
HON
HONl
HON2
HOZl
HOZ2
Q

The cutoff frequency of the low-pass or high-pass filter output
The input clock frequency to the device
The notch frequency of the notch output
The center frequency of the complex pole pair second-order function
The center frequency of the complex zero pair
The band-pass output voltage gain (VIV) at the band-pass center frequency
The high-pass output voltage gain (VIV) as the frequency approaches 0.5 fclock
The low-pass output voltage gain (VIV) as the frequency approaches 0
The notch output voltage gain (V IV) at the notch frequency
The low-side notch output voltage gain as the frequency approaches 0
The high-side notch output voltage gain as the frequency approaches 0,5 fclock
Gain at complex zero output (as f -+ 0 Hz)
Gain at complex zero output (as f approaches 0.5 fclock)
The quality factor of the complex pole pair second-order function, Q is the ratio of fo to
the 3-dS bandwidth of the band-pass output, The value of Q also affects the possible
peaking of the low~pass and high-pass outputs,
The quality factor of the complex zero pair, if such a complex pair exists, This parameter is
used when an all-pass filter output is desired,

TEXAS

.~

INSTRUMENTS
8-28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1 D/MF1 OAr TLC2D/MF1 DC
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER

:>

Q

= _10_; 10 =

"

0

IH

= 10

HOBP 1 - - - - - - - " " 7 ' 1.....

,:H(~~', ~,~)'. ,)

:>

;- 0.707 HOBP 1 - - - - - - - + - - ; - ;
C(
Cl

ILia

JtLiH

(2~ ~2~Y
+

+ 1)

IH

I (LOG SCALE)

FIGURE 11. BAND-PASS OUTPUT

-- '"

HOp

:>

:>

HOlP

;- 0.707 HOlP
C(
Cl

Ip

'"

Ie

= 10

Ip

=

HOp

10

=

x

J

1-

HOLP x

2~2
--===

2..J1 _
o

Ie

1
40 2

I (lOG SCALE)

FIGURE 12. LOW-PASS OUTPUT

HOp~-----~~

:>

~-----

HOHP

>
;- 0.707 HOHPf------,~
«
52

HOp

=

HOHP

1

x ----

2..) 1
Q

Ie

_

1
4Q2

Ip
I (lOG SCALE)

FIGURE 13. HIGH·PASS OUTPUT

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-29

8-30

Gel'1eral.····.·lnformation

9-1

Contents
Page
TLC32046 Analog Interface ............................................. 9-3
TLC32047 Analog Interface ............................................. 9-55
TLC34075 Video Interface Palette ...................................... 9-109

9-2

TLC32046
Wide-Band Analog Interface Circuit
Data Manual

TEXAS

INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to
or to discontinue any semiconductor product or service
identified in this publication without notice. TI advises its
customers to obtain the latest version of the relevant
information to verify, before placing orders, that the
information being relied upon is current.
TI warrants performance of its semiconductor products to
current specifications in accordance with TI's standard
warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this
warranty. Unless mandated by government requirements,
specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance,
customer product design, software performance, or
infringement of patents or services described herein. Nor
does TI warrant or represent that license, either express or
implied, is granted under any patent right, copyright, mask
work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which
such semi.conductor products or services might be or are
used.
Texas Instruments products are not intended for use in
life-support appliances, devices, or systems. Use of a TI
product in such applications without the written consent of the
appropriate TI officer is prohibited.

Copyright © 1991, Texas Instruments rncorporated
Printed in the U.S.A.

9-4

Contents
Page

Introduction ...................................................................
Features .................................................................
Functional Block Diagrams .................................................
Terminal Assignments .....................................................
Terminal Functions ........................................................
Detailed Description ............................................................
Internal Timing Configuration ...............................................
Analog Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AID Band-Pass Filter, Clocking, and Conversion Timing ........................
AID Converter ............................................................
Analog Output ............................................................
DIA Low-Pass Filter, Clocking, and Conversion Timing .........................
DIA Converter ............................................................
Serial Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Operation ....................................................
One 16-Bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two 8-Bit Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Operating Frequencies ......................................
Asynchronous Operation ...................................................
One 16-Bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two 8-Bit Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Operating Frequencies .....................................
Operation of TLC32046 With Internal Voltage Reference .......................
Operation of TLC32046 With External Voltage Reference . . . . . . . . . . . . . . . . . . . . . . .
Reset....................................................................
Loopback ................................................................
Communications Word Sequence ................................................

9-9
9-10
9-11
9-14
9-15
9-17
9-18
9-20
9-20
9-20
9-20
9-20
9-21
9-21
9-21
9-21
9-21
9-22
9-22
9-22
9-22
9-23
9-23
9-23
9-23
9-23
9-24

DR Serial Data Word Format ....................................................
DR Word Bit Pattern .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OX Serial Data Word Format ....................................................
Primary OX Word Bit Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-24
9-24
9-25
9-25

9-5

Page
Secondary DX Word Bit Pattern ..............................................
Reset Function ......................................................... " . . .
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AIC Register Constraints ....................................................
AIC Responses to Improper Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation With Conversion Times Too Close Together . . . . . . . . . . . . . . . . . . . . . . .
More Than One Receive Frame Sync Occurring Between
Two Transmit Frame Syncs - Asynchronous Operation .................
More than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame
Syncs - Asynchronous Operation ....................................
System Frequency Response Correction .....................................
(sin x)/x Correction ........................................................
(sin x)/x Roll-Off for a Zero-Order Hold Function ............................
Correction Filter ........................................................
Correction Results ......................................................
TMS320 Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
Absolute Maximum Ratings .................................................
Recommended Operating Conditions .........................................
Electrical Characteristics ....................................................
total device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power supply rejection and crosstalk attenuation ............................
serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
receive amplifier input ........................................ ;..........
transmit filter output .....................................................
receive and transmit system distortion .....................................
receive channel signal-to-distortion ratio ...................................
transmit channel signal-to-distortion ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
receive and transmit gain and dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
receive channel band-pass filter transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . .
receive and transmit channel low-pass filter transfer function .................
Operating Characteristics (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Requirements ......................................................

9-26
9-26
9-27
9-27
9-27
9-28
9-28
9-29

9-29
9-30
9-30
9-30
9-31
9-31
9-32
9-33
9-33
9-33
9-34
9-34
9-34
9-34
9-34
9-35
9-35
9-35
9-36
9-36
9-36
9-37
9-37
9-38

Parameter Measurement Information - Timing Diagrams .. . . . . . . . . . . . . . . . . . . . . . . . . . .

9-39

TMS32046 - Processor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-42

Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-44

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-54

9-6

List of Illustrations
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22
23
24
25
26
27

28
29
30
31
32
33
34

Page
Dual-Word (Telephone Interface) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . .
Byte Mode. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . ... . .. . . . . . . . . . .
Asynchronous Internal Timing Configuration ..............................
Primary and Secondary Communications Word Sequence ..................
Reset on Power-Up Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Times Too Close Together ...................................
More Than One Receive Frame Sync Between Two Transmit Frame Syncs ...
More Than One Transmit Frame Sync Between Two Receive Frame Syncs . . .
More Than One Set of Primary and Secondary OX Serial Communications
Between Two Receive Frame Syncs ...................................
First-Order Correction Filter .......... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IN+ and IN- Gain Control Circuitry ......................................
Dual-Word (Telephone Interface) Mode Timing ...........................
Word. Timing .........................................................
Byte-Mode Timing ....................................................
Shift-Clock Timing ....................................................
TMS32010rrMS320C15-TLC32046 Interface Circuit .................. ;...
TMS3201 OrrMS320C15-TLC32046 Interface Timing .....................
D/A and NO Low-Pass Filter Response Simulation .......................
D/A and NO Low-Pass Filter Response .................................
D/A and NO Low-Pass Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AID Band-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NO Band-Pass Filter Response Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NO Band-Pass Filter Group Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NO Channel High-Pass Filter. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . .
D/A (sin x)/x Correction Filter Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D/A (sin x)/x Correction Filter Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D/A (sin x)/x Correction Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NO Band-Pass Group Delay ...........................................
D/A Low-Pass Group Delay............................................
NO Signal-to-Distortion Ratio vs Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AID Gain Tracking ....................................................
D/A Converter Signal-to-Distortion Ratio vs Input Signal ...................
D/A Gain Tracking ....................................................

9-12
9-13
9-13
9-19
9-24
9-27
9-28
9-29
9-29
9-30
9-31
9-39
9-40
9-40
9-41
9-42
9-42
9-43
9-44
9-44
9-45
9-45
9-46
9-46
9-47
9-47
9-48
9-48
9-49
9-49
9-50
9-50
9-51
9-51
9-7

List of Illustrations (continued)
Figure

Page

NO Second Harmonic Distortion vs Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . .
D/A Second Harmonic Distortion vs Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . .
NO Third Harmonic Distortion vs Input Signal .............................
D/A Third Harmonic Distortion vs Input Signal .............................
AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors '
. and Schottky Diode .................................................
40 External Reference Circuit for TLC32046 .................................

35
36
37
38
39

9-52
9-52
9-53
9-53
9-54
9-54

List of Tables
Table
1
2
3
4
5
6
7

9-8

Page
Mode-Selection Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary OX Serial Communication Protocol ...............................
Secondary OX Serial Communication Protocol ............................
AIC Responses to Improper Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(sin x)/x Roll-Off Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(sin x)/x Correction Table for f5 = 8000 Hz and f5 ;::: 9600 Hz . . . . . . . . . . . . . . . . .
Gain Control Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-17
9-25
9-26
9-28
9-31
9-32
9-39

Introduction
The TLC32046 wide-band analog interface circuit (AIC) is a complete analog-to-digital and digital-to-analog
interface system for advanced digital signal processors (DSPs) similar to the TMS32020, TMS320C25, and
TMS320C30. The TLC32046 offers a powerful combination of options under DSP control: three operating
modes (dual-word [telephone interface], word, and byte) combined with two word formats (8 bits and 16 bits)
and synchronous or asynchronous operation. It provides a high level of flexibility in that conversion and
sampling rates, filter bandwidths, input circuitry, receive and transmit gains, and multiplexed analog inputs
are under processor control.
This AIC features a
band-pass switched-capacitor antialiasing input filter
14-bit-resolution AID converter
14-bit-resolution D/A converter
low-pass switched-capacitor output-reconstruction filter.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively. The input filter is implemented in switchedcapacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When low-pass filtering is desired, the high-pass filter can be switched out
ofthe signal path. A selectable auxiliary differential analog input is provided for applications where more than
one analog input is required.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology.
This filter is followed by a continuous-time filter to eliminate images of the sample data signal. The on-board
(sin x)/x correction filter can be switched out of the signal path using digital signal processor control.
The AID and D/A architectures ensure no missing codes and monotonic operation. An internal voltage
reference is provided to ease the design task and to provide complete control over the performance of the
IC. The internal voltage reference is brought out to pin 8. Separate analog and digital voltage supplies and
ground are provided to minimize noise and ensure a wide dynamic range. The analog circuit path contains
only differential circuitry to keep noise to a minimum. The exception is the DAC sample-and-hold, which
utilizes pseudo-differential circuitry.
The TLC32046C is characterized for operation from O°C to 70°C, and the TLC320461 is characterized for
operation from -40°C to 85°C.

9--9

Features
. Advanced LinCMOS'" Silicon-Gate Process Technology
14-Bit Dynamic Range ADC and DAC
16-Bit Dynamic Range Input With Programmable Gain
Synchronous or Asynchronous ADC and DAC Sampling Rates Up to 25,000 Samples Per
Second
Programmable Incremental ADC and DAC Conversion Timing Adjustments
Typical Applications
-

Speech Encryption for Digital Transmission

-

Speech Recognition and Storage Systems

-

Speech Synthesis

-

Modems at 8-kHz, 9.6-kHz, and 16-kHz Sampling Rates

-

Industrial Process Control

-

Biomedicallnstrumentation

-

Acoustical Signal Processing

-

Spectral Analysis

-

Instrumentation Recorders

-

Data Acquisition

Switched-Capacitor Antialiasing Input Filter and Output-Reconstruction Filter
Three Fundamental Modes of Operation: Dual-Word (Telephone Interface), Word, and Byte
600-mil Wide N Package
Digital Output in Twos Complement Format
FUNCTION TABLE
SYNCHRONOUS
(CONTROL
REGISTER
BIT D5 = 1)

ASYNCHRONOUS
(CONTROL
REGISTER
BIT D5 = 0)

16-bit format

Dual-word (telephone
interface) mode

Dual-word (telephone
interface) mode

Pin 13 = 0 to 5 V
Pin 1 = 0 to 5 V

TMS32020,
TMS320C25,
TMS320C30

16-bit format

Word mode

Word mode

Pin 13 = VCC-(-5 V nom)
Pin 1 = VCC+ (+5 V nom)

TMS32020,
TMS320C25,
TMS320C30,
indirect
interface to
TMS320C10.

8-bit format
(2 bytes required)

Byte mode

Byte mode

Pin 13 = VCC- (-5 Vnom)
Pin 1 = VCC- (-5 V nom)

TMS320C17

DATA
COMMUNICATIONS
FORMAT

LinCMOS is a trademark of Texas Instruments Incorporated.
9-10

FORCING CONDITION

DIRECT
INTERFACE

Functional Block Diagrams
WORD OR BYTE MODE
IN + 2:.:.6-1-_......
IN _ 2_5.----..~
AUX IN + 2:.:..41--~'"

M

Low-Pass
Filter

U

x

AUX IN _ 2_3r----1,o~

I----IM

Serial
Port

U . . - - -......... AID
X

5
4

DR
FSR

3

EODR
High-Pass
Filter

Receive Section

6

,-;-- --;,

I
--------------------~
I
Transmit Section

Internal
Voltage
Reference

I
I

1 WORDBYTE
13 CONTROL

l..':---r-_-_
__
.....:.JI

12
14

OUT +

Low-Pass
Filter

OUT-

20
VCC +

DGTL
GND

VCC-

11

DIA

7
VDD
(DIG)

MSTR CLK

10 SHIFTCLK

OX
FSX
EODX

8

DUAL-WORD (TELEPHONE INTERFACE) MODE
IN + 2:.:6-t-----1r-......
IN _ 2:-::5..-_V""
AUX IN + 2_4+-_~
AUX IN _ 2_3-t-_i..o'

Low-Pass
Filter

AID

Serial
Port

5
4

DR
FSR
011 OUT

High-Pass
Filter

,-;-- --;,

MSTRCLK

I
Internal
I
--------------------~
Voltage
I
I Reference I
l..':...._-_--r"-_-_....:.J

SHIFTCLK

Receive Section

FSD
DATA DR
OX
14

OUT+

11

Low-Pass
Filter

OUT-

20

Vce

+

ANLG
GND

DGTL
GND

7
VDO
(DIG)

8
REF

FSX
Dl00UT

2
RESET

9-11

FRAME SYNCHRONIZATION FUNCTIONS
TLC32046 Function

Frame Sync Output

Receiving serial data on OX from processor to internal OAC

FSXlow

Transmitting serial data on DR from internal ADC to processor, primary
communications

FSR low

Transmitting serial data on DR from Data DR (pin 13) to processor, secondary
communications in dual-word (telephone interface) mode only

FSD (pin 1) low

5V
201
26

VCC+

-5V
191
VCCDR

IN+

A nalog In

25

IN-

TLC32046

FSR

Serial Data Out
5
4
3

D110UT

....
A nalog Out

22
21

OUT+

OX

12

Serial Data In....

TMS32020,
TMS320C25,
TMS320C30,
or Equivalent
16·Bit DSP

OUTFSX

14

TIL or CMOS
Logic Levels

11
D100UT

,

1

FSD

Secondary Commu nicatlon (see Table above)
Serial Data Input
13
DATA·DR

16·Bit Format TIL
or CMOS Lo 9 ic Leveis

Figure 1. Dual·Word (Telephone Interface) Mode
When the DATA-DR/CONTROL input (pin 13) is tied to a logic signal source varying between 0 and 5 V, the
TLC32046 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input
to the DSP only when pin 1, data frame synchronization (FSO), outputs a low level. The FSO pulse duration
is 16 shift clock pulses. Also, in this mode, the control register data bits 010 and 011 appear on pins 11 and
3, respectively, as outputs.

9-12

5V

26
A nalog In

.. 25

-5V

201

191

VCC +

VCC-

DR

IN+
IN-

TLC32046

FSR
EO DR

22

~

A nalog Out

....

21

OUT+
OX

EODX

1

Serial Data Out

4
3

...
Serial Data In

12

TMS32020,
TMS320C25,
TMS320C30,
or Equivalent
16-Bit DSP

OUTFSX

VCC+
(5 V nom)

5

WORD-BYTE

CONTROL

14

TTL or CMOS
Logic Levels

11

13

....

VCC(- 5 V nom)

Figure 2. Word Mode
5V

.. 26

An alog In

.. 25
~

-5V

201

191

VCC+

VCC-

DR

IN+
IN-

TLC32046

FSR
EODR

22

~

-~

An alog Out
~

21

~

OUT+

OX

EODX

1

Serial Data Out

4

.
~

3

12

.

WORD-BYTE

CONTROL

TMS320C17
or Equivalent
8-Blt Serial
Interface
(2 Bytes Required)

Serial Data In
TTL or CMOS
Logic Levels

OUTFSX

VCC(-5 V nom)

5

14
r'

11

..
~

13

VCC(-5 V nom)

Figure 3. Byte Mode
The word or byte mode is selected by first connecting the DATA-DR/CONTROL input (pin 13) to VCC-.
FSD/WORD-BYTE (pin 1) becomes an input and can then be used to select either word or byte transmission
formats. The end-of-data transmit (EODX) and the end-of-data receive (EODR) signals on pins 11 and 3,
respectively, are used to signal the end of word or byte communication (see the Terminal Functions section).

9-13

I

Terminal Assignments
FN PACKAGE
(TOP VIEW)

N PACKAGEt
(TOP VIEW)

w.
RESET
:j:0110UT/EOOR
FSR

1

AUXIN+

MSTR ClK

AUXIN-

OGTlGNO
SHIFTClK
:j:0100UT/EOOX
OX
:j:OATA-OR/CONTROl
FSX

OUT+
OUT-

8w
j::::

IN+
IN-

DR
VOO
REF

~

0:

:j:FSO/WORO-BYTE

o

~
0

0:

0

l§

61 fBtu f2:::J:::J
I ~;::
u..£l 0:++ Z Z
5

4 321

+
~

282726
25

IN-

6

24

AUXIN+

7

23

AUXIN-

8
9

22
21

OUT+
OUT-

NU

10

20

NU

11
19
121314 15161718

VCC+
VCC-

VCC+
VCCANlG GNO
ANlG GNO

:::JOO

ZZZ
00

gg
Z

Z

 1.
(RA register ± RA' register) must be > 1.
TB register must be '" 15.
RB register must be '" 15.

Ale Responses to Improper Conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are presented in Table 4.

9-27

Table 4. AIC Responses to Improper Conditions
IMPROPER CONDITION

AIC RESPONSE

= 0 or 1
register = 0 or 1

TA register + TA' register
TA register - TA'

Reprogram TX(A) counter with TA register value

TA register + TA' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is
loaded into TX(A) counter, i.e., TA register + TA' register + 40 HEX
is loaded into TX(A) counter.

RA register + RA' register = 0 or 1
RA register - RA' reg ister = 0 or 1

Reprogram RX(A) counter with RA register value

RA register + RA' reg ister

TA register
RA register

= 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is
loaded into RX(A) counter, i.e., RA register + RA' register + 40 HEX
is loaded into RX(A) counter.

= 0 or 1
= 0 or 1

AIC is shut down. Reprogram TA or RA registers after a reset.

TA register < 4 in word mode

The AIC serial port no longer operates. Reprogram TA or RA
registers after a reset.

TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
TB register < 15

Reprogram TB register with 12 HEX

RB register < 15

Reprogram RB register with 12 HEX

AIC and DSP cannot communicate

Hold last DAC output

Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC operates
improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there is not
enough time for the ongoing conversion to be completed. This situation can occur if the A and B registers
are improperly programmed or if the A + A' register result is too small. When incrementally adjusting the
conversion period via the A + A' register options, the designer should not violate this requirement. See
Figure4.

Frame Sync
(FSX or FSR)

l

t1

...------".'/'1-)_ _...,t2,

~----~

I

~----~

j.-- Ongoing Conversion ~I

t2 - t1

oS

1/25 kHz

Figure 7. Conversion Times Too Close Together

More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the Ale
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B may be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.

9-28

The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 8).
t1

LJ
---I~.

LJ

Transmit Conversion Period -------.l~

Receive Conversion
Period A

Receive Conversion
Period 8

Figure 8. More Than One Receive Frame Sync Between Two Transmit Frame Syncs

More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion'period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 9. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2. If there is not
sufficient time between t1 and t2, receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.

Transmit ~ Transmit ~ Transmit
Conversion I
Conversion I Conversion
Period A
Period 8
Period C
t2

j4--

I

FSR~----------~L-J

k---

Receive Conversion Period A

.1.

-'1
~

Receive Conversion Period 8

---.I

Figure 9. More Than One Transmit Frame Sync Between Two Receive Frame Syncs

More than One Set of Primary and Secondary OX Serial
Communications Occurring Between Two Receive Frame Syncs (See OX
Serial Data Word Format section) - Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time betWeen t1
9-29

· and t2, the TA, RA', and RB register information, sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If
RA, RA', and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RN, or RB information received during this receive conversion period is
disregarded. See Figure 10.
Primary
Fsxl

1

n

!+--

Secondaryt 1

Primary

I

I

1
·1<1

Transmit
Conversion
Preload A

n

Secondary

Primary

I I

Transmit
Conversion
Preload B

1
.1 4

n

Secondary

I L
1
·1

Transmit
Conversion
Preload C

t2

FSR
Receive
. - - Conversion
Period A

I
I

·1"

Receive
Conversion
Period B

I
·1

I

Figure 10. More Than One Set of Primary and Secondary OX Serial Communications
Between Two Receive Frame Syncs

System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
inserted into or omitted from the signal path by digital-signal-processor control (data bit D9 in the DX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 4) equals 15, the correction results of Figures 26,27, and
28 can be obtained.
The (sin x)/x correction [see section (sin xl/x] can also be accomplished by disabling the on-board
second-order correction filter and performing the (sin x)/x correction in digital signal processor software. The
system frequency response can be corrected via DSP software to ± 0.1 dB accuracy to a band edge of
3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, that
requires seven TMS320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an
overhead factor of 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x
Correction Section for more details).

(sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown below are typical of the
numerical correction accuracy that can be achieved for sample rates of interest. The filter requires seven
instruction cycles per sample on the TMS320 DS. With a 200-ns instruction cycle, nine instructions per
sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz,
respectively. This correction adds a slight amount of group delay at the upper edge ofthe 300-Hz to 3000-Hz
band.

(sin x)/x Roll-Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 5 (see Figure 27).
9-30

Table 5. (sin x)/x Roll-Off Error
sin It f/f&
It f/fs
f = 3000 Hz

Error = 20 log
fs (Hz)

(dB)

7200
8000
9600
14400
16000
19200
25000

-2.64
-2.11
-1.44
-0.63
-0.50
-0.35
-0.21

The actual AIC (sin x)/x roll-off is slightly less than the figures above because the AIC has less than 100%
duty cycle hold interval.

Correction Filter
To externally compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter can be implemented
as shown in Figure 11.
U

(I + 1) ---I~

Y(i + 1)

p1

Figure 11. First-Order Correction Filter
The difference equation for this correction filter is:
Y(i + 1) = p2· (1 - p1) . u(i + 1) + p1 . Y(i)

(4)

where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
1 H (f) 12

=

(p2)2. (1-p1)2
1-2 . p1 . cos (2n f/fs) + (p1)2

(5)

Correction Results
Table 5 shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates (see Figures 26, 27, and 28).

9-31

Table 6. (sin x)/x Correction Table for fs

= 8000 Hz and fs =9600 Hz

ROLL-OFF ERROR (dB)

=8000 Hz
p1 =-0.14813
p2 =0.9888
fs

f (Hz)

300
600
900
1200
1500
1800
2100
2400
2700
3000

-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102

ROLL-OFF ERROR (dB)

=9600 Hz
p1 =-0.1301'

fs

p2

=0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043

TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
Y(i+1) = Y(i) . k1 + u(i+1) . k2

where k1 = p1, k2 = (1 - p1 )p2, y(i) is the filter state, and u(i+ 1) is the next I/O sample. The coefficients k1
and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift) yields the correct
result. With the assumption that the TMS320 processor page pOinter and memory configuration are properly
initialized, the equation can be executed in seven instructions or seven cycles with the following program:

ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dma), (shift)

9-32

Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
,
(Unless Otherwise Noted)
Supply voltage range, V CC+ (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, Voo ....................................... -0.3 V to 15 V
Output voltage range, Va ........................................ -0.3 V to 15 V
Input voltage range, VI ........................................... -0.3 V to 15 V
Digital ground voltage range ...................................... --'-0.3 V to 15 V
Operating free-air temperature range: TLC32046C ................... O°C to 70°C
TLC320461 .................. -40°C to 85°C
Storage temperature range ...................................... -40°C to 125°C
Case temperature for 10 seconds: FN package ............................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ... 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.

Recommended Operating Conditions
MIN

NOM

MAX

UNIT

Supply voltage, VCC+ (see Note 2)

4.75

5

5.25

V

Supply voltage, VCC- (see Note 2)

-4.75

-5

-5.25

V

4.75

5

5.25

Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND

0

V
V

Reference input voltage, Vref(ext) (see Note 2)

2

4

High-level input voltage, VIH

2

VDD+0.3

V

-0.3

0.8

V

Low-level input voltage, VIL (see Note 3)
Load resistance at OUT + and/or OUT-, RL

300

Q

Load capacitance at OUT + and/or OUT-, CL

100

MSTR CLK frequency (see Note 4)

5

Analog input amplifier common mode input voltage (see Note 5)

Operating free-air temperature range, T A

10.368
±1.5

AID or D/A conversion rate

25

ITLC32046C
I TLC320461

V

0

70

-40

85

pF
MHz
V
kHz

°c

NOTES: 2. Voltages at analog inputs and outputs, REF, VCC+, and VCC- are with respect to the ANLG GND terminal.
Voltages at digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used
in this data manual for logic vo!tage levels only.
4. The band-pass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock
is 288 kHz and the high-pass section SCF clock is 16 kHz. If the low-pass SCF clock is shifted from 288 kHz,
the low-pass roll-off frequency shifts by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF
clock is shifted from 16 kHz, the high-pass roll-off frequency shifts by the ratio of the high-pass SCF clock
to 16 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply only when the SCF
clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off frequency shifts by the ratio
of the SCF clock to 288 kHz.
5. This range applies when (IN+ - IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.

]',
]'

9-33

I~

it

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ =5 V, VCC- =-5 V, Voo = 5 V (Unless
Otherwise Noted)
total device, MSTR ClK frequency = 5.184 MHz, outputs not loaded
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD = 4.75 V,

IOH = ~300 [!A

VOL

Low-level output voltage

VDD = 4.75 V,

IOL= 2 mA

ICC+
ICCIDD
Vref

MIN

ro

MAX

2.4

Supply current from

TLC32046C

35

VCC+
Supply current from

TLC320461

40

TLC32046C

-35

VCCSupply current from VDD

TLC320461

-40
7

Internal reference output voltage

3.3

3

internal reference voltage
Output resistance at REF

UNIT
V

0.4

Temperature coefficient of
aVref

TYpt

V
mA
mA
mA
V

250

ppmrC

100

kQ

power supply rejection and crosstalk attenuation
PARAMETER
VCC+ or VCC- supply voltage
rejection ratio, receive channel
VCC+ or VCC- supply voltage
rejection ratio, transmit channel
(single-ended)

TEST CONDITIONS

MIN

TYpt

f = 0 to 30 kHz

Idle channel, supply
signal at 200 mV p-p

30

f = 30 kHz to 50 kHz

measured at DR (ADC
output)

45

f = 0 to 30 kHz
f = 30 kHz to 50 kHz

MAX

UNIT

dB

Idle channel, supply

30

signal at 200 mV p-p
measured at OUT +

dB

45

Crosstalk attenuation, transmit-to-receive
(single-ended)

dB

80

serial port
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH = -300 [!A

VOL

Low-level output voltage

IOL = 2 mA

II

Input current

MIN

TYpt

MAX

2.4

UNIT
V

0.4

V

±10

~A

±100

~A

II

Input current, DATA-DR/CONTROL

Ci

Input capacitance

15

pF

Co

Output capacitance

15

pF

t All typical values are at TA = 25°C.
receive amplifier input
PARAMETER'

TEST CONDITIONS

MIN

ND converter offset error (filters in)

TYpt

MAX

10

70

UNIT
mV

Common-mode rejection ratio at IN+, IN-,
CMRR

or AUX IN+, AUX IN-

See Note 6

Input resistance at IN+, IN-

q

or AUX IN+, AUX IN-, REF

..

NOTE 6: The test condition
9-34

IS

a O-dBm, 1-kHz mput signal With a 16-kHz conversion rate .

55

dB

100

kQ

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ = 5 V, VCC- =-5 V, Voo = 5 V (Unless
Otherwise Noted) (Continued)
transmit filter output
PARAMETER
VOO
VOM

TEST CONDITIONS

(single-ended relative to ANLG GND)
Maximum peak output voltage swing across
RL at OUT+ or OUT- (single-ended)

VOM

MIN

Output offset voltage at OUT + or OUTRL:' 300 Q,

TYpt

MAX

15

80

UNIT
mV

±3

V

±6

V

Offset voltage = 0

Maximum peak output voltage swing between

RL:' 600 Q

OUT + and OUT- (differential output)

t All typical values are at T A = 25°C.
receive and transmit channel system distortion, SCF clock frequency
(see Note 7)
PARAMETER

TEST CONDITIONS

Attenuation of second harmonic of

single-ended

AID input Signal

differential

Attenuation of third and higher

single-ended

harmonics of NO input signal

differential

Attenuation of second harmonic of

single-ended

D/A input signal

differential

Attenuation of third and higher

single-ended

harmonics of D/A input signal

differential

MIN

TYpt

= 288kHz

MAX

UNIT

70
Vin

=-0.1

62
dB to -24 dB

dB

70
65

57

dB

65
70

Vin

62

=-0 dB to -24 dB

dB

70
65

57

65

MAX

MIN

dB

t All typical values are at T A = 25°C.
receive channel signal-to-distortion ratio (see Note 7)
Av = 1:1:
PARAMETER

NO channel signal-todistortion ratio

TEST CONDITIONS
Vin

58

Vin

58

58

= -6 dB to -0.1 dB
= -12 dB to-6 dB
Vin = -18 dB to -12 dB
Vin =-24 dB to -18 dB
Vin =-30 dB to -24 dB
Vin =-36 dB to -30 dB
Vin =-42 dB to -36 dB
Vin = -48 dB to -42 dB
Vin =-54 dB to -48 dB

*Av is the programmable gain of the input amplifier.

MAX

A v =2:i:
MIN
§

MIN

A v =4:1:
MAX

UNIT

§
§

56

58

58

50

56

58

44

50

56

38

44

50

32

38

44

26

32

38

20

26

32

dB

§ Measurements under these conditions are unreliable due to overrange and signal clipping.
NOTE 7: The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Q. Input and output voltages are referred to Vref.

9-35

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ =5 V, VCC- =-5 V, VOO =5 V (Unless
Otherwise Noted) (Continued)
transmit channel signal-to-distortion ratio (see Note 7)
PARAMETER

TEST CONDITIONS

MIN

=-6 dB to -0.1 dB
Yin =-12 dB to -6 dB
Yin =-18 dB to -12 dB
Yin =-24 dB to -18 dB
Yin =-30 dB to -24 dB
Yin =-36 dB to -30 dB
Yin =-42 dB to -36 dB
Yin =-48 dB to -42 dB
Yin =-54 dB to -48 dB

. 58

Yin

D/A channel signal-to-distortion ratio

NOTE 7:

MAX

UNIT

58
56
50
44

dB

38
32
26
20

The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Q . .Input and output voltages are referred to Yref.

receive and transmit gain and dynamic range (see Note 8)
PARAMETER

TEST CONDITIONS

TYpt

MAX

UNIT

Transmit gain tracking error

Yout = -48 dB to 0 dB signal range

±0.05

±0.15

dB

Receive gain tracking error

Yin = -48 dB to 0 dB signal range

±0.05

±0.15

dB

MIN

NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Yref).

receive channel band-pass filter transfer function, SCF fclock = 288 kHz, input
(IN+ -IN-) is a ±3-V sine wave* (see Note 9)
PARAMETER

TEST

FREQUENCY

MIN

TYpt

MAX

-33

-29

-25

-4

-2

-1

K1 x 0 dB

-0.25

0

0.25

K1 x 0 dB

-0.3

0

0.3

K1 x 0 dB

-0.5

0

0.5

-2

-0.5

-16

-14

ADJUSTMENT

UNIT

CONDITION

f s 100 Hz

K1 x 0 dB

=200 Hz
f =300 Hz to 6200 Hz
f =6200 Hz to 6600 Hz
f =6600 Hz to 7300 Hz
f =7600 Hz
f =8000 Hz

K1 x -0.26 dB

f
Input signal
Filter gain

reference is 0 dB

K1 x 2.3 dB
K1 x 2.7 dB

-5

f

~

8800 Hz

K1 x 3.2 dB

-40

f

~

10000 Hz

K1 x 0 dB

-65

. dB

t All typical values are at T A = 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF

may result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
K1 = 100 • [(SCF frequency - 288 kHz)/288 kHz). For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 300 Hz
to 7200 Hz and 0 to 7200 Hz for the band-pass and low-pass filters, respectively. For switched-capacitor filter
clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter
clock frequency to 288 kHz.
9-36

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ = 5 V, VCC- = -5 V, Voo =5 V (Unless
Otherwise Noted). (Continued)
receive and transmit channel low-pass filter transfer function,
SCF fclock =288 kHz (see Note 9)
PARAMETER

Filter gain

TEST

FREQUENCY

ADJUSTMENT

CONDITION

RANGE

ADDEND:!:

Input signal
reference is 0 dB

MIN

TYpt

MAX

f = 0 Hz to 6200 Hz

Kl x 0 dB

-0.25

0

0.25

f = 6200 Hz to 6600 Hz

Kl x 0 dB

-0.3

0

0.3

f = 6600 Hz to 7300 Hz

Kl x 0 dB

-0.5

0

0.5

f = 7600 Hz

Kl x 2.3 dB

-5

-2

-0.5

f = 8000 Hz

Kl x 2.7 dB

-16

-14

f;<: 8800 Hz

Kl x 3.2 dB

-40

b 10000 Hz

Kl x 0 dB

-65

UNIT

dB

t All typical values are at TA = 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF

may result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
Kl = 100 • [(SCF frequency - 288 kHz)/288 kHz]. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 300 Hz
to 7200 Hz and 0 to 7200 Hz for the band-pass and low-pass filters, respectively. For switched-capacitor filter
clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter
clock frequency to 288 kHz.

Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ = 5 V, Vcc- = -5 V, Voo = 5 V
receive and transmit noise (measurement includes low-pass and band-pass
switched-capacitor filters)
PARAMETER

TEST CONDITIONS

broadband with (sin x)/x

Transmit noise

TYpt

MAX

250

500

broadband without (sin x)/x

200

450

o to 30 kHz with (sin x)/x
oto 30 kHz without (sin x)/x
o to 3.4 kHz with (sin x)/x
o to 3.4 kHz without (sin x)/x
o to 6.8 kHz with (sin x)/x

200

400

OX input

=00000000000000,

200

400

180

300

160

300

180

350

160

350

300

500

constant input code

[wide-band operation with 7.2 kHz
roll-off]

UNIT

f-IVrms

o

to 6.8 kHz without (sin x)/x
[wide-band operation with 7.2 kHz
roll-off]
Receive noise (see Note 10)

Inputs grounded, gain = 1

18

f-IVrms
dBrncO

t All typical values are at T A = 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the

NO converter.

9-37

l

Ii
I

Timing Requirements
serial port recommended input signals
PARAMETER

tc(MClK)

Master clock cycle time

trlMClK)

Master clock rise time

tf(MClK)

MIN

25%

RESET pulse duration (see Note 11)
OX setup time before

UNIT

ns

Master clock fall time
Master clock duty cycle

tsu(DX)

MAX

95
10

ns

10

ns

75%

800

ns

20

ns

SClK~

OX hold time after SClK~
ns
thlDX)
tcISClK)/4
NOTE 11: RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies
have reached their recommended values.

serial port - AIC output signals, CL = 30 pF for SHIFT ClK output, CL =15 pF
for all other outputs
PARAMETER

MIN

TYpt

MAX

UNIT

tc(SClK)

Shift clock (SClK) cycle time

tf(SClK)

Shift clock (SClK) fall time

3

8

ns

tr(SClK)

Shift clock (SClK) rise time

3

8

ns

td(CH-Fl)

Delay from SClKt to

FSR/FSX/FSD~

30

td(CH-FH)

Delay from SClKt to FSR/FSX/FSDt

35

td(CH-DR)

DR valid after SClKt

td(CH-El)

Delay from SClKt to

380

Shift clock (SClK) duty cycle

EODX/EODR~

ns

45

55

in word mode

%

,",s
90

ns

90

ns

90

ns

td(CH-EH)

Delay from SClKt to EODX/EODRt in word mode

90

ns

tf(EODX)

EODX fall time

2

8

ns

tf(EODR)

EODR fall time

2

8

ns

td(CH-El)

Delay from SClKt to EODX/EODRl in byte mode

90

td(CH-EH)

Delay from SClKt to EODX/EODRt in byte mode

90

ns
ns

td(MH-Sl)

Delay from MSTR ClK t to

SClK~

65

170

ns

Delay from MSTR ClKt to SClKt

65

170

ns

tdIMH-SH)
t Typical values are at TA = 25°C.

9-38

Parameter Measurement Information
Rfb
IN +
or
AUXIN+

R

INor
AUXIN-

R

Rfb
Rfb = R for 06 = 1 and 07 =
06 = 0 and 07 = 0
Rfb = 2R for 06 = 1 and 07 = 0
Rfb = 4R for 06 = 0, and 07 = 1

Figure 12. IN+ and IN- Gain Control Circuitry

Table 7. Gain Control Table (Analog Input Signal Required for
Full-Scale Bipolar AID Conversion Twos Complement)t
INPUT
CONFIGURATIONS
Differential configuration
Analog input = IN+ -IN= AUX IN+ - AUX IN-

Single-ended configuration
Analog input = IN+ - ANLG GNO
= AUX IN+ - ANLG GNO

CONTROL REGISTER BITS
06

07

1

1

0

0

ANALOG
INPUTi§

AJO CONVERSION

V'0=±6V

dull scale

RESULT

1

0

V,O = ±3 V

±full scale

0

1

V'0=±1.5V

±full scale

1

1

0

0

V, = ±3 V

±half scale

1

0

V, = ±3 V

±full scale

0

1

V,=±1.5V

±full scale

t VCC+ = 5 V, VCC- = -5 V, VOO = 5 V

t V,O = Differential Input Voltage, V, = Input voltage referenced to ground with IN- or AUX IN- connected to ground.
§ In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.

9-39

1-+ te (SClK)

SHIFT
ClK

rv'\

_ _ _-+1-\
FSX,I:.SB.
~

DR

8

015

12V

I
--.I

8V
td (CH-Fl)

I
I
I

td (CH-FH)

I

~

"""""1

\';
14- td

tsu (OX) -+j

III 2 V I
I

(CH-DR~ - - - .

~;!JCD2\

I
~~~I____

I

01

DO

I

~

I

I
I

i
I

Don't Care

DO

I

DATA-DR _ _ _D;;.1.;.;;5~_ _~pc-02"\_.;;.D.;.1_D;;.0;;....;.1_ _-r-____

Figure 13. Dual-Word (Telephone Interface) Mode Timing

SHIFT
ClK

t

FSX,FSR
DR

015

DO

,

td (CH-El) -.! j4--

Don't Care

-.I ~

td (CH-EH)

----------------------------~\\------------~~
~2V~--:I: EO OX,
EODR
8 V '----J
fr'

Figure 14. Word Timing
t The time between falling edges of FSR is the ND conversion period and the time between falling edges of FSX is the
D/A conversion period.
:j: In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle

is 20 shift-clocks wide, giving a four-clock period setup time between data words.

9-40

-+I j.SHIFT

C~

2 V.

I

II

td (CH-FL)-, 10FSR,

8V

X

FSX

DR

015
tsu (OX)

t f (SCLK)

2 v.

I

:

I
I
I

...j I+- t r (SCLK)

II
\'J

.~~H~.

~

I
~~

f

V

2V

I

td (CH-FH)

2V

~ I*8

\X

I

'Ji

Y2V
I

08

-1 :-

oX---~015l(~~ro1:lTlC~J

I

td (CH-FH) ~ !r-~---

td (CH-FL)

~_0_1_ _00-+:_ _ __
I

Don't Care

EOOR,
EO OX

Figure 15. Byte-Mode Timing

t The time between falling edges of FSR is the ND conversion period, and the time between faliling edges of FSX is the D/A conversion period,
:j: In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is

transmitted or received, Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.

~

-:~~ii;~;~"-r~;"'~~-:-;-.i

MSTR ClK

SHIFTClK

I
I
41

I

~ - td (MH.SH)

i+- td (MH.Sl)

\{_.--------------

_ _ _...J

Figure 16. Shift·Clock Timing

TMS32046 - Processor Interface
5N74l574

5N74l5299
t- 51

DEN

-

G1
A

A1/PA1

B

A2/PA2

C

Y1

50 ClK<

-

YO

08-015

.'\

A-H
\

~

:E
t-

51
'---

WE
ClK
OUT
INT

~

00-07
\

\

A-H
\

5R

=n
1 -

Figure 17. TMS32010/TMS320C15-TLC32046 Interface Circuit

9-42

5HIFT
ClK

OH

G2
G1

\

~
-

5R

50 ClK

00-015
00-015

~

SN74lS299

pn

0

OX

G1

5N74lS138

0

G-

G2

AO/PAO

N

OH

F5X

C2

Pl

~

tDR

M5TR
ClK
EOOX

IN instruction timing
ClKOUT ~

:

L

1

1----+

~I----------------

....

1

r-----------

1

SO,G1
1

00-015

--------«

)>-----------

Valid

OUT instruction timing
ClKOUT

~

:
1

WE

L
~I-----------------

'--__I......
1

SN74lS138 Y1

....----------

!

SN74lS299 ClK

00-015

--------«

Valid

)>----------

Figure 18. TMS32010tTMS320C15-TLC32046 Interface Timing

9-43

Typical Characteristics
D/A AND AID LOW-PASS FILTER
RESPONSE SIMULATION
0.4

I

I

=

I

I

I

TA 25°C
Input ± 3 V Sine Wave

m

=

0.2

"tI

I
CD
"tI

.a

'ctil
"tI

c

III

m

~ ~ ~V\
/

V

III

::il

1\

.......

0

-0.2

I/)
I/)

III

0..

-0.4

-0.6

o

1

2

3
4
5
6
7
Normalized Frequency

8

9

10

Figure 19
D/A AND AID LOW-PASS FILTER RESPONSE
0
See Figure 2·1
for Pass Band
Detail

-10

T~ = 2~oC

~
I-

I

I

I

Input = ± 3 V Sine Wave

-20

m

-30

"tI

I
CD
"tI

-40

'ctil

-50

:J
III

::il

-60
-70

(

-80

-90

J

~

o

2

4

\ !

6
8
10 12 14
Normalized Frequency

-

."

16

18

20

Figure 20
NOTE: Absolute Frequency (kHz) =

9-44

Normalized Frequency x SCF fc10ck (kHz)
288

D/A AND AID LOW-PASS GROUP DELAY
I

0.9

I

I

I

I

TA = 25°C
Input = ± 3 V Sine Wave

f-

0.8
0.7
1/1

E
I

0.6

>Gi

0.5

1\1

0

c.

::I

...0
Cl

0.4

J

0.3
0.2

---

0.1

o

o

2

V

V

\
i'-

3
4
5
6
7
Normalized Frequency

8

9

10

9

10

Figure 21
AID BAND-PASS RESPONSE
0.4

I
I
I
I
I
I
I
High-Pass SCF fclock = 16 kHz
TA = 25°C
Input = ±3 V Sine Wave

0.2
In

"
"c:
I

CD

::I
:!::

0

r-/

CI

1\1

:!i!

"Inc:
1\1

-0.2

1/1
1/1
1\1

c..

.....

'"

J

/

f\

~V

-0.4

-0.6

o

2

3
4
5
6
7
Normalized Frequency

8

Figure 22

NOTE: Absolute Frequency (kHz) ;::

Normalized Frequency x SCF fcIock (kHz)
288

9-45

AID BAND-PASS FILTER RESPONSE SIMULATION
0
High-Pass SCF
-10
fclock = 16 kHz
TA = 25°C
Input = ± 3 V Sine Wave
-20

\,

m

-30

'tI

I
GI

-40

c:

-50

'tI
:J
:!::
01
ft!

:::E

-60

r\

-70
-80
-100

II

o

2

4

I

....

~l 16

6
8 10 12 14
Normalized Frequency

"'--

18

20

Figure 23
AID BAND-PASS FILTER GROUP DELAY
2

I

I

I

I

I

I

I

High-Pass SCF fclock = 16 kHz
TA = 25°C
Input = ±3 V Sine Wfltve

1.8
1.6

-

1.4
1/1

E
I

1.2

:0-

ft!

Gl

0

c.

1.1

:J

0.8

"

0.6

e

11\

0.4

\
/ \

\

-'"

0.2

o

o

'"

0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
Normalized Frequency

Figure 24

NOTE: Absolute Frequency (kHz) =

9-46

Normalized Frequency X SCF fC\ock (kHz)
288

AID CHANNEL HIGH·PASS FILTER
20

=

TA 25°C
Input ± 3 V Sine Wave

10
0

m
'0

=

I~

-10

I
CII

'0
::I

:t:

-20

C

CI
IG

==

f

-30

I

-40
-50

-60

o

100 200 300 400 500 600 700 800 900 1000
Normalized Frequency

Figure 25

DIA (sin x)/x CORRECTION FILTER RESPONSE
4

2

V

m

'0
I

0

V

/

./

/

~

1\,
\

CII

'0

::I

C
CI
IG

\
\

:t:

-2

==
-4 l- TA = 25°C

\

i\

\

Input = ± 3 V Sine Wave

-6

I I I I I
o

2

4

6

8

10

12

14

16

18

20

Normalized Frequency

Figure 26
NOTE: Absolute Frequency (kHz)

=

Normalized Frequency x SCF fclock (kHz)
288

9-47

D/A (sin x)/x CORRECTION FILTER RESPONSE
500
TA= 25°C
Input = ± 3 V Sine Wave
400

V\

II)

::1.

I

>m

300

/ \

Gi

C
Co
:I

e

200

(!l

100

o

V

o

2

4

'I

/

[\

"
6
8
10 12 14 16
Normalized Frequency

18

20

Figure 27
D/A (sin x)/x CORRECTION ERROR
2

L

1.2
/
0.8
IXI

"i'

0.4

~

o

:I

./

-""
............

'2
~ -0.4

==

/

(sin x) Ix Correction

/

V '"
i'-.

..........

-0.8

Error

r-.....
"-.......

19.2 kHz (sin x)
"\.. Distortion

-1.2

'\

-1.6

-2

)'

TA = 25°C
Input = ± 3 V Sine Wave

1.6

I~

\.

\
o

2

3
4
5
6
7
Normalized Frequency

8

9

10

Figure 28

NOTE: Absolute Frequency (kHz) ::

9-48

Normalized Frequency X SCF fC\ock (kHz)
288

AID BAND-PASS GROUP DELAY
760

I

720 1--1-

=

til

T

680 I--

Qj
0

640

I

I

I

I

I

=
=

-ff-

Low-pass SCF fclock 144 kHz
High-pass SCF fclock 8 kHz
TA 25°C
Input ± 3 V Sine Wave

=

- F-------

>co

0..
:I

0

~

600

til

til
co

560

'"
co

520

co

0

/

0..

:I

0

~

400

CI
til
til

co

360

'"

320

I

0..

r::

co

III

0

:::>+
ILL++
a:++ z z ~
CI)

CI)

4 321

282726
25

OUT-

5

VCC+
VCCANlG GND

6

24

AUX IN+

7

23

AUXIN-

8

22

9
10

21

OUT+
OUT-

ANLG GND
NU

20

NU

x

0

IN-

VCC+
VCC-

-JIX

:::>0 Cl
OCl) :::>
z
a: LL Z zz
(!) (!)
f(!) (!)
Z

0

Q.

a:
0

-Jz -Jz
 OAC Register.
TA+ TA' -> TX(A) , RA+RA' -> RX(A). See Figure 4.
TB -> TX(B), RB -> RX(B). See Figure 4.
The next O/A andA/O conversion period will be changed by the addition ofTA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero. Refer to Table 4, AIC Responses to Improper
Conditions.

0

1

015 (MSB)-02 -> OAC Register.
TA-TA' -> TX(A), RA-RA' -+ RX(A). See Figure 4.
TB -> TX(B), RB -> RX(B). See Figure 4.
The next O/A and A/O conversion period will be changed by the subtraction of TA' and RA' master clock
cycles, in which TA' and RA' can be positive, negative, orzero. Referto Table 4, AIC Responses to Improper
Conditions.

1

0

Table 2. Primary OX Serial Communication Protocol
FUNCTIONS

015 (MSB)-02 -> OAC Register.
TA -> TX(A), RA -> RX(A). See Figure 4.
TB -> TX(B), RB -> RX(B). See Figure 4.

015 (MSB)-02 -> OAC Register.
TA -- TX(A), RA -+ RX(A). See Figure 4.
TB -+ TX(B), RB -+ RX(B). See Figure 4.
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on OATA OR (pin 13) is routed to OR (Serial
Oata Output) during secondary transmission.

1
1
NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (primary communications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four SHIFT CLOCK cycles and then goes low and
initiates the secondary communication. The timing specifications forthe primary and secondary communications
are identical. In this manner, the secondary communication, if initiated, is interleaved between successive primary
communications. This interleaving prevents the secondary communication from interfering with the primary
communications and OAC timing. This prevents the AIC from skipping a DAC output. It is important to note that
FSR is not asserted during secondary communications activity. However, in the dual-word (telephone interface)
mode, FSD is asserted during secondary communications but not during primary communications.

9-79

Secondary OX Word Bit Pattern
O/A MSB

1st bit sent
015

1st bit sent of 2nd byte

I 014 I 013 I 012 I 011 I 010 I

09

I

08

I

07

I

06

I

O/A LSB

05

I

~

04

I

03

I

02

I

01

I

00

Table 3. Secondary OX Serial Communication Protocol
01

DO

013 (MSB)-09 -> TA , 5 bits unsigned binary. See Figure 4.
06 (MSB)-02 -> AA, 5 bits unsigned binary. See Figure 4.
015,014,08, and 07 are unassigned.

0

0

014 (sign bit)-09 -> TA', 6 bits 2s complement. See Figure 4.
07 (sign bit)-02 --- AA', 6 bits 2s complement. See Figure 4.
015 and 08 are unassigned.

0

1

014 (MSB)-09 -> TB, 6 bits unsigned binary. See Figure 4.
07 (MSB)-02 -> AB, 6 bits unsigned binary. See Figure 4.
015 and 08 are unassigned.

1

0

02 = 0/1 deletes/inserts the NO high-pass filter.
03 = 0/1 deletes/inserts the loop back function.
04 = 0/1 disables/enables the AUX IN+ and AUX IN- pins.
05 = 0/1 asynchronous/synchronous transmit and receive sections.
06 = 0/1 gain control bits (see Table 7).
07 = 0/1 gain control bits (see Table 7).
09 = 0/1 delete/insert on-board second-order (sinx)/x correction filter
010= 0/1 output to 01 OOUT (dual-word (telephone interface) mode)
011 = 0/1 output to 011 OUT (dual-word (telephone interface) mode)
08, 012-015 are unassigned.

1

1

FUNCTIONS

Reset Function
A reset function is provided to initiate serial communications between the AIC and OSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on the RESET pin initializes the AIC registers to provide a 16-kHz ND and D/A
conversion rate for a 10.36S-MHz master clock input signal. Also, the pass-bands of the ND and O/A filters
are 300 Hz to 7200 Hzand Hz to 7200 Hz, respectively. Therefore, the filter bandwidths are 66% of those
shown in the filter transfer function speCification section. The AIC, excepting the CONTROL register, is
initialized as follows (see AIC DX Data Word Format section):

°

REGISTER
INITIALIZED VALUE (HEX)

TA
12

TA'
01

TB
12

RA
12

RA'
01

RB
12

The CONTROL register bits are reset as follows (see Table 3):
D11 = 0, D10 = 0, D9 = 1, 07

= 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1

This initialization allows normal serial port communications to occur between the AIC and the OSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA', and TB register need to be programmed. Both transmit and
receive timing are synchronously derived from these re'gisters (see the Terminal Functions and DX Serial
Data Word Format sections).
.
Figure 6 shows a circuit that provides a reset on power-up when power is applied in the sequence given in
the Power-Up Sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of SOO ns before the capacitor charges to O.S V above DGTL GND.
9-80

TLC32047
VCC+

5V

0.5 flF

Vcc-

-5V

Figure 6. Reset on Power-Up Circuit

Power-Up Sequence
To ensure proper operation oftheAIC and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from Vcc- to ANLG GND and from
V cc- to DGTL GND. In the absence of such diodes, power is applied in the following sequence: ANLG GND
and DGTL GND, VCC-, then Vcc+ and Voo. Also, no input signal is applied until after power-up.

AIC Register Constraints
The following constraints are placed on the contents of the AIC registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

TA register must be;,; 4 in word mode (WORD/BYTE: High).
TA register must be;,; 5 in byte mode (WORD/BYTE: Low).
TA' register can be either positive, negative, or zero.
RA register must be ;,; 4 in word mode (WORD/BYTE: High).
RA register must be;,; 5 in byte mode (WORD/BYTE: Low).
RA' register can be either positive, negative, or zero.
(TA register ± TN register) must be > 1.
(RA register ± RA' register) must be > 1.
TB register must be ;,; 15.
RB register must be ;,; 15.

AIC Responses to Improper Conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are presented in Table 4. The general procedure for correcting any improper
operation is to apply a RESET and reprogram the registers to the proper value.

9-81

Table 4. AIC Responses to Improper Conditions
IMPROPER CONDITION
TA register + TA' register = 0 or 1

AIC RESPONSE
Reprogram TX(A) counter with TA register value

TA register - TA' register = 0 or 1
TA register + TA' register < 0
...

RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is
loaded into TX(A) counter, Le., TA register + TA' register + 40 HEX
is loaded into TX(A) counter.
Reprogram RX(A) counter with RA register value

RA register - RA' register = 0 or 1
RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is
loaded into RX(A) counter, Le., RA register + RA' register + 40 HEX
is loaded into RX(A) counter.

TA register = 0 or 1

AIC is shut down. Reprogram TA or RA registers after a reset.

RA register", 0 or 1
TA register < 4 in word mode

The AIC serial port no longer operates. Reprogram TA or RA
registers after a reset.

TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
TB register < 15

ADC no longer operates

AB register < 15

DAC no longer operates

AIC and DSP cannot communicate

Hold last DAC output

Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the Ale operates
improperly. In this situation, the second D/A convE;lrsion frame sync occurs too quickly, and there is not
enough time for the ongoing conversion to be completed. This situation can occur if the A and B registers
are improperly programmed or if the A + A' register result is too small. When incrementally adjusting the
conversion period via the A + A' register options, the designer should not violate this requirement. See
Figure?

I+--

Ongoing Conversion

---+1

Figure 7. Conversion Times Too Close Together

More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the Ale
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B may be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between 11 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.

9-82

The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 8).
t1

LJ

LJ

1 4 - - - - - Transmit Conversion Period - - - - + I

I

I

"I~

Receive Conversion
Period A

Receive Conversion
Period B

Figure 8. More Than One Receive Frame Sync Between Two Transmit Frame Syncs

More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the Ale during an FSX frame sync. The ongoing transmit'
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 9. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2. If there is not
sufficient time between t1 and t2, receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.

~

I

Transmit ~ Transmit - . - Transmit
Conversion I
Conversion I Conversion
Period A
Period B
Period C
t2

FSR1-J~--------~L-J
\ . - - Receive Conversion Period A'

..

I~

-'1
~

Receive Conversion Period B

--.j

Figure 9. More Than One Transmit Frame Sync Between Two Receive Frame Syncs

More than One Set of Primary and Secondary OX Serial
Communications Occurring Between Two Receive Frame Syncs (See OX
Serial Data Word Format section) - Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t1
and t2' the TA, RA', and RB register information, sent during transmit conversion period A, is applied to
9-83

receive conversion period A. Otherwise, this information is applied during receive conversion period B. If
RA, RA', and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information received during this receive conversion period is
disregarded. See Figure 10.
Primary

Fsxl

I

Secondar/ 1

Primary

Secondary

Primary

Secondary

I
_If

Transmit
Conversion
Preload 8

I
_If

Transmit
Conversion
Preload C

nl I n I I n I L

Transmit
j + - - Conversion
Preload A

FSR

I

I
-I

I

Receive
I
Receive
I
j....;

r-

2

8VI
I

td (CH-Fl)

FSX,~
8V"X
I I
FSD~I
I

DR

015

-rJ.

td (CH-FH)
If;

~ td (CH-DRl-.. _

~~
~

tsu(DX) ~

01

DO

--~--~~--~~-------

-

Don't Care

DX----<

DO

I

~--.;;;;D.;.1--;;.DO~I----+------

DATA-DR ____D;;.1.;.;;5;.....___

Figure 13. Dual-Word (Telephone Interface) Mode Timing

SHIFT
ClK

2

8VI
td (CH-Fl)

t

FSX,FSR
DR

015

OX _____-<

I I
I I
If;
I -+I ~ td (CH-DR)

~~D1DO
tsu (OX) ~

~---~--~-~-------

I

r-

Don't Care

DO
I

I

-

th (OX)

td (CH-EL)

~ \4-

-.I ~

td (CH-EH)

I~~--*EOOX,----------------------------~\,\------------~I
EODR
8 V"---.I 2 V
Figure 14. Word Timing

t The time between falling edges of FSR is the ND conversion period and the time between falling edges of FSX is the
D/A conversion period.
:j: In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle

is 20 shift-clocks wide, giving a four-clock period setup.time between data words.

9-94

SHIFT
2Y.
CLK
1
td (CH-FL)-,

--.Jr- tr(SCLK)

'I

1

~

FSR,

8V'

FSX

DR

015
tsu (OX)

OX

EOOR,
EOOX

----

I

2Y.

~~

1

1

:

I"

.~ciH~.
~
~

V

II

f

2V

1

td (CH-FH)

2V

-+i ~

8~"

I

Ii

08

I-

r-

1

td (CH-FL)

td (CH-FH)

~

rr2~V-:---1

~___0_1__00-+:_ _ __
1

Don't Care

(

I'i

'

8V~,

_________________________

,~

Z

____________J

Figure 15. Byte-Mode Timing

t The time between falling edges of FSR is the ND conversion period, and the time between fallling edges of FSX is the D/A conversion period.
:j: In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is

transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.

%
U1

MSTR ClK

I

SHIFTClK

~- td (MH-SH)

~ td (MH-SL)

'i~:______________

------'

Figure 16. Shift-Clock Timing

TMS32047 - Processor Interface
5N74L574

SN74LS299
~

-

DEN
'---

G1
A

A1/PA1

B

A2/PA2

C

YO '---

G1

08-015
\

A·H

\

51

-

'"
Ih
:;:

-

f

QH

G2
50 CLK

I-

G1
00-015
\

00-015

CLK
OUT
INT

it

\

~

A-H

./

-

,...
'-----------

Valid

OUT instruction timing
ClKOUT

~

L

I

:I

WE

SN74lS138 Y1

SN74lS299 ClK

00-015

-----~(

Valid

)>----------

Figure 18. TMS32010rrMS320C15-TLC32047 Interface Timing

9-97

Typical Characteristics
D/A AND AID LOW·PASS FILTER
RESPONSE SIMULATION
0.4

I

=

I

TA 25°C
Input ± 3 V Sine Wave

=

0.2

co

"C

I

-

CI)

"C

.a

·c

0

OJ

<1l

:E

"C

c::

<1l

V

N

o

3

-0.2

1\

V\ V\

co
til
til
<11

Il.

-0.4

-0.6

15

12

9
6
Normalized Frequency

Figure 19

D/A AND AID LOW·PASS FILTER
RESPONSE SIMULATION
0
See Figure 2·1
for Pass Band
Detail

-10

~

_

TA = 25°C
Input = ± 3 V Sine Wave

I

I

-20

co

-30

"C

I
CI)

"C

~

c::

OJ

-40
-50

<1l

:E

-60
-70

(

\

-80

-90

o

II
3

6

9

12

15

18

I

It!

21

~

24

27

30

Figure 20
Normalized Frequency X SCF fclock (kHz)
NOTE: Absolute Frequency (kHz) = - - - - - - - - - - - = - = = = - - -

432

9-98

DIA AND AID LOW-PASS GROUP DELAY
0.6

I

=

I

TA 25°C
Input ±3 V Sine Wave

=

0.5

-

(II

j

Qi
Cl
0-

:s

0

0.3

V

(;

....- /

0.2

o

o

3

i\

.~

6
9
f - Frequency - kHz

12

15

Figure 21
AID BAND-PASS RESPONSE
0.4

I
I
I
High-Pass SCF fclock = 24 kHz
TA = 25°C
Input = ±3 V Sine Wave

0.2

to

"
"2
·c
I

Q)

0

../~

m

(II

:E

"tor::

(II

-0.2

i'v~

f\

II
V

ftI

Gl

c

1\

0.5

'\
) \
--"

Q.

::J
0

...

0.4

Cl

0.2

"

0.1

o

o

1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
f - Frequency - kHz

Figure 24

NOTE: Absolute Frequency (kHz) =

9-100

Normalized Frequency X SCF fclock (kHz)
432

AID CHANNEL HIGH-PASS FILTER
20

=

TA 25°C
Input ± 3 V Sine Wave

10

=

0
!Xl

"C

/"'-10

I
CI)

"C

~

-20

t:

r

01
1'0

:i:

-30

I

-40
-50

-60

o

150 300 450 600 750 900 1050 1200 13501500

Normalized Frequency

Figure 25
D/A (sin x)/x CORRECTION FILTER RESPONSE
4

~

/'

!Xl
"C

I

0

v \
V
/

2

~

/

\

1\

\

CI)

"C

E

\

·c

01

1'0

-2

:i:

-4 e-

-6

=

\

TA 25°C
Input ± 3 V Sine Wave

o

=

I

I

I

I

I

3

6

9

12

15

\

\
18

21

24

27

30

f - Frequency - kHz

Figure 26
NOTE: Absolute Frequency (kHz) =

Normalized Frequency x SCF fclock (kHz)

------=--..:.,----=~---'-

432

9-101

D/A (sin x)/x CORRECTION FILTER RESPONSE
325

=

TA 25°C
Input ± 3 V Sine Wave

=

260

Ifr\

U)

::I.

I

>('0

195

/ 1\

Qi
0

c..

:s

...0
CI

130

65

o

1 - -"'"

o

V

6

3

V

'I

i\
'-....

9

12 15 18 21
f - Frequency - kHz

24

27

30

Figure 27
D/A (sin x)/x CORRECTION ERROR
2

=

J

TA 25°C
Input ± 3 V Sine Wave

1.6

=

/

1.2

(sin x) Ix Correction

/
0.8

m
~

-

0.4

V
.............
i'...

GI

"0

.a

o

.i:
~ -0.4

:E

V

/

/
I

Error

"' ""-

""I~

"-

-0.8
-1.2
-1.6

-2

/

28.8 kHz (sin x)
Distortion

'\!\

\

o

1.5

3

4.5 6 7.5 9 10.5 12 13.5 15
f - Frequency - kHz

Figure 28

NOTE: Absolute Frequency (kHz) =

9-102

Normalized Frequency

X

SCF fclock (kHz)

-----.....:..-~---==-~-..:...

432

AID BAND-PASS GROUP DELAY
760

1/1

r

I

I

I

I

I

I

-f{-

Low-pass SCF fclock = 144 kHz
720 f-- -r- High-pass SCF fclock = 8 kHz
TA = 25°C
r- Input = :!: 3 V Sine Wave
680 f--

-r--

>-

I

<'0

a;

a

"::I

...0
(!)

1/1
1/1
<'0

.

640
600
560

"'tl

c:

<'0

a

~

\\

480

r--.....

440
400

/

1\

520

III

o

0.4

0.8

./

1.2

1.6

/

2.0

/
V

V

/

2.4

2.8

3.2

3.6

f - Frequency - Hz

Figure 29

D/A LOW-PASS GROUP DELAY
560
520 _
1/1

r>-

480

_

I

I

I

I

I

I

=

Low-pass SCF fclock 144 kHz
TA 25°C
Input =:!: 3 V Sine Wave

=

I

<'0

a;

a

"::I

e

(!)
1/1
1/1
<'0

,;"c:

<'0

440

V

400

/

360
320

III

a

~

280
240
200

I

I

_V
o

0.4

0.8

/

/

J

V

1.2 1.6 2.0 2.4
f - Frequency - Hz

2.8

3.2 3.6

Figure 30

9-103

AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100

en

1·kHz Input Signal
90 f- 16.kHz Conversion Rate
TA 25°C
80

=

'C

I

.2

70

c:

60

:e

50

~
II:

Gain

40

4OJ

30

en

20

c:
m

=1

"..-1-

V V
"/
,

0

B
C/I
C

Gain

'= 4

10

o
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 31
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT O-dB INPUT SIGNAL)
0.5
0.4

r-

0.3

en
'C

0.2

I

0.1

U

0.0

m
c:
:i
ItS

~

c:
'iii

<-"

-0.1

1·kHz Input Signal
16.kHz Conversion Rate
TA = 25°C

I

"

......

I

I

-

-0.2
-0.3

-0.4
-0.5
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

Figure 32

9-104

10

D/A CONVERTER SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100
90
In

"C
I
0
:;::

r-

80

1·kHz Input Signal Into 600 Q
16.kHz Conversion Rate
TA = 25°C

70

tV

a::
c

60

1:
0

50

0

40

iii
c

30

en

20

0

!!

~

/

,/

/
,/

""

........

/

CI

10

o

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 33
D/A GAIN TRACKING (GAIN RELATIVE TO GAIN
AT O-dB INPUT SIGNAL)
0.5

I

I

I

I

1·kHz Input Signal Into 600 Q
0.4 f-, 16.kHz Conversion Rate
TA = 25°C
0.3
In

"C
I

CI

c
:;:
U

0.2
0.1
0.0

tV

j!:

c

-0.1

-....

"-/ '

'iij
~

-0.2
-0.3
-0.4
-0.5
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 34

9-105

AID SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
-100
-90

m

"0
I
I:

-70

.Bt/)

-60

"co
E
...C\l

-50

oo

=

-80

o

t:

1-kHz Input Signal
16-kHz Conversion Rate
TA 25°C

-V

V

~ b---

-40

J:
"0

I:

-30

o
o

~

en

-20
-10

o
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 35
D/A SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
-100

.tl

"0

I
I:

1-kHz Input Signal Into 600 Q I
-90 - 16-kHz Conversion Rate
TA = 25°C
......
-80
.........
,/

0

-70

Cii

-60

"c0
E
...
C\l

0

-50

"0
t:

-30

t:0

V

~ -..............

0

-40

J:
0

0

~

en

-20
-10

o
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

Figure 36

9--106

10

AID THIRD HARMONIC DISTORTION
vs

INPUT SIGNAL
-100
-90
to

-80 f-

c:

-70

:e0

-60

C.)

-50

'0
I
0

Cii
i5

·2
0

E

1-Hz Input Signal
16-kHz Conversion Rate
TA = 25°C

f-

./'

./'

.... ~ ~

... /

-40

~

111

J:

':g.r:
~

-30
-20
-10

o
-50

-40
-30
-10
-20
o
Input Signal Relative to Vref - dB

10

Figure 37
D/A THIRD HARMONIC DISTORTION
vs

INPUT SIGNAL
-100
-90 rto

'0

-80

I

I

c:

0

-70

:e0

-60

C.)

-50

Cii
i5

I

I

I

1-kHz Input Signal Into 600 Q
16-kHz Conversion Rate
TA = 25°C

_

/""'\

......... / '

\

·2
0

E
...

-40

J:

-30

111

...

'0

:E
~

-20
-10

o
-50

-40
-30
-10
o
-20
Input Signal Relative to Vref - dB

10

Figure 38

9-107

Application Information
TMS32020/C25
ClKOUT

TlC32047
MSTR ClK

FSX

FSX

OX

OX

FSR
DR
ClKR

+5V

VCC+
REF

C

ANlG GNO

FSR
DR

VCC-

SHIFTCLK

VOO

1-._-+-------4.-- - 5 V
1---f-------4.-- + 5 V

CLKX
OGTlGNO

C

= 0.2

~F,

A

Ceramic

Figure 39. AIC Interface to the TMS32020/C25 Showing Oecoupling Capacitors
and Schottky Oiode t
t Thomson Semiconductors
VCC
R

3 V Output
5000
0.01 IlF

TL431
25000

FOR: VCC = 12 V, R = 7200 0
V CC 10 V, R 5600 0
VCC = 5 V, R = 1600 0

=

=

Figure 40. External Reference Circuit for TLC32047

9-108

TLC34075
Video Interface Palette
Data Manual

TEXAS

INSTRUMENlli
9-109

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to
or to discontinue any semiconductor product or service
identified in this publication without notice. TI advises its
customers to obtain the latest version of the relevant
information to verify, before placing orders, that the
information being relied upon is current.
TI warrants performance of its semiconductor products to
current specifications in accordance with Tl's standard
warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this
warranty. Unless mandated by government requirements,
specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance,
customer product design, software performance, or
infringement of patents or services described herein. Nor
does TI warrant or represent that license, either express or
implied, is granted under any patent right, copyright, mask
work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which
such semiconductor products or services might be or are
used.
Texas Instruments products are not intended for use in
life-support appliances, devices, or systems. Use of a TI
product in such applications without the written consent ofthe
appropriate TI officer is prohibited.

Copyright © 1991, Texas Instruments Incorporated
Printed in the U.S.A.

9-110

Contents
Section

Title

Page

Introduction .................................................................
1.1 Features .............................................................
1.2 Functional Block Diagram ...............................................
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.5 Terminal Functions ....................................................

9-115
9-115
9-116
9-117
9-117
9-118

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2 Color Palette RAM ................................................... .
2.2.1 Writing to the Color Palette RAM ................................. .
2.2.2 Reading From the Color Palette RAM .............................. .
2.2.3 Palette Page Register ........................................... .
2.3 Input/Output Clock Selection and Generation ............................... .
2.3.1 SCLK ....................................................... .
2.3.2 VCLK ....................................................... .
2.4 Multiplixing Scheme .................................................. .
2.4.1 VGA Pass-Through Mode ....................................... .
2.4.2 Multiplexing Modes ............................................ .
2.4.3 True Color Mode .............................................. .
2.4.4 Special Nibble Mode ........................................... .
2.4.5 Multiplex Control Register ...................................... .
2.4.6 Read Masking ................................................. .
2.5 Reset .............................................................. .
2.5.1 Power-On Reset ............................................... .
2.5.2 Hardware Reset ............................................... .
2.5.3 Software Reset ................................................ .
2.5.4 VGA Pass-Through Mode Default Conditions ....................... .
2.6 Frame Buffer Interface ................................................ .
2.7 Analog Output Specifications ........................................... .
2.8 HSYNC, VSYNC, and BLANK ......................................... .
2.9 Split Shift Register Transfer VRAMs and Special Nibble Mode ................ .
2.9.1 Split Shift Register Transfer VRAMs .............................. .
2.9.2 Special Nibble Mode ........................................... .
2.10 MUXOUT Output .................................................... .
2.11 General Control Register ............................................... .
2.11.1 HSYNCOUT and VSYNCOUT (Bits 0 and 1) ....................... .
2.11.2 Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode
Enable (SNM) (Bits 2 and 3) ..................................... .

9-120
9-120
9-120
9-121
9-121
9-121
9-121
9-123
9-124
9-126
9-126
9-127
9-127
9-127
9-127
9-130
9-130
9-130
9-130
9-130
9-130
9-131
9-131
9-133
9-133
9-133
9-134
9-135
9-135
9-136

9-136
9-111

1'1

11

I{

Contents (Continued)
Section

Title

Page

2.11.4 Sync Enable Control (Bit 5) .......................................
2.11.3 Pedestal Enable Control (Bit 4) ....................................
2.11.5 MUXOUT (Bit 7) ...............................................
2.12 Test Register ............. , ...........................................
2.12.1 Frame Buffer Data Flow Test ......................................
2.12.2 Identification Code ..............................................
2.12.3 Ones Accumulation Screen Integrity Test ............................
2.12.4 Analog Test ...................................................

9-136
9-136
9-136
9-137
9-138
9-138
9-138
9-138

Specifications ................................................................
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted) ...............................................
3.2 Recommended Operating Conditions ......................................
3.3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4 Operating Characteristics ...............................................
3.5 Timing Requirements .................-.................................
3.6 Switching Characteristics ...............................................
TL34075-66, TLC34075-85 '" ........................................
TL34075-110,TLC34075-135 .........................................
3.7 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9-140

9-140
9-140
9-141
9-142
9-143
9-144
9-144
9-145
9-146

Appendix A SCLK/VCLK and the TMS340xO .................................. .. 9-149
Appendix B PC Board Layout Considerations ..................... ............. .. 9-151
Appendix C SCLK Frequency <: VCLK Frequency .. ............................ .. 9-155

9-112

List of Illustrations
Figure
1
Functional Block Diagram

Title

Page
9-116

2
3

Terminal Assignments .................................................... 9-117
DOTCLKJVCLK/SCLK Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-122

4

SCLKJVCLK Control Timing

9-124

5

SCLKJVCLK Control Timing

9-125

6

SCLKJVCLK Control Timing

9-125

7

SCLKJVCLK Control Timing .............................................. 9-126

8

Equivalent Circuit of the lOG Current Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-131

9

7.5-IRE, 8-Bit Composite Video Output ...................................... 9-132

10

O-IRE, 8-Bit Composite Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-132

11

Relationship Between SFLAG/NFLAG, BLANK, and SCLK ..................... 9-134

12

SFLAG/NFLAG Timing in Special Nibble Mode ............................... 9-135

13

Test Register Control Word State Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-137

14
15

Internal Comparator Circuitry for Analog Test ................................. 9-139
MPU Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-146

16

Video Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-147

17

SFLAG/NFLAG Timing .................................................. 9-147

18

Typical Connection Diagram and Components ................................. 9-152

19

Typical Component Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-153

20

Typical Split Power Plane ................................................. 9-153

21

VCLK and SCLK Phase Relationship (Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

22

VCLK and SCLK Phase Relationship (Case 2) ................................. 9-155

9~155

List of Tables
Table
Title
Page
1
Internal Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-120
2

Allocation of Palette Page Register Bits ...................................... 9-121

3

Input Clock Selection Register Format ....................................... 9-122

4

Output Clock Selection Register Format ...................................... 9-123

5

VCLK/SCLK Divide Ratio Selection ........................................ 9-123

6

Mode and Bus Width Selection ............................................. 9-128

7

Pixel Data Distribution in Special Nibble Mode ................................ 9-134

8

General Control Register Bit Functions ...................................... , 9-136

9

Test Mode Selection ..................................................... , 9-137

10

Test Register Bit Definitions for Analog Test

9-139

11

D<7:4> Bit Coding for Analog Comparisons

9-139
9--113

9-114

1 Introduction
The TLC34075 Video Interface Palette (VIP) is designed to provide lower system cost with a higher level
of integration by incorporating all the high-speed timing, synchronizing, and multiplexing logic usually
associated with graphics systems into one device, thus greatly reducing chip count. Since all high-speed
signals (excluding the clock source) are contained on-chip, RF noise considerations are simplified.
Maximum flexibility is provided through the pixel multiplexing scheme, which allows for 32-,16-,8-, and 4-bit
pixel buses to be accommodated without any circuit modification. This enables the system to be easily
reconfigured for varying amounts of available video RAM. Data can be split into 1, 2, 4, or 8 bit planes. The
TLC34075 is software-compatible with the INMOS IMSG176/8 and Brooktree BT476/8 color palettes.
The TLC34075 features a separate VGA bus that allows data from the feature connector of most
VGA-supported personal computers to be fed directly into the palette without the need for external data
multiplexing. This allows a replacement graphics board to remain downward compatible by utilizing the
existing graphics circuitry often located on the motherboard. The TLC34075 also provides a true color mode
in which 24 (3 by 8) bits of color information are transferred directly from the pixel port to the DACs. This
mode of operation supplies an overlay function using the 8 remaining bits of the pixel bus.
The TLC34075 has a 256-by-24 color lookup table with triple 8-bit video D/A converters capable of directly
driving a doubly terminated 75-Q line. Sync generation is incorporated on the green output channel. HSYNC
and VSYNC are fed through the device and optionally inverted to indicate screen resolution to the monitor.
A palette page register provides the additional bits of palette address when 1, 2, or 4 bit planes are used.
This allows the screen colors to be changed with only one MPU write cycle.
Clocking is provided through one of four or five inputs (3 TTL- and either 1 ECL- or 2 TTL-compatible) and
is software selectable. The video and shift clock outputs provide a software-selected divide ratio of the
chosen clock input.
The TLC34075 can be connected directly to the serial port of VRAM devices, eliminating the need for any
discrete logic. Support for split shift register transfers is also provided.

1.1 Features
Versatile multiplexing interface allows lower pixel bus rate
High level of integration provides lower system cost and complexity
Direct VGA pass-through capability
Directly interfaces to TMS3401 0/TMS34020 and other graphics processors
Triple 8-bit D/A converters
66-, 85-, 110-, and 135-MHz versions
256-word color palette RAM
Palette page register
On-chip voltage reference
RS-343A-compatible outputs
TTL-compatible inputs
Standard MPU interface
Pixel word mask
On-chip clock selection
True color (direct addressing) mode
Directly interfaces to video RAM
Supports split shift register transfers
Software downward-compatible with INMOS IMSG176/8 and Brooktree BT476/8 color palettes
TIGA ™ -software-standard compatible
LinEPIC ™

1-~m

CMOS process

LinEPIC and TIGA are trademarks of Texas Instruments Incorporated.

9-115

r

"TI

m

32

True Color
Pipeline Delay

24

---"B

~

'"
~

-"

en

I

N

1;~m
~

24/

II

c:
o

"TI

7

~ •

B

COMP

~

:J
Q)

OJ

o
o

'"c

P~
I

VGA

iii'

Input
Latch

~

&.

Read I B/ •
Mask ~

+.-

Color
Palette
RAM

I

•

I

Page
Register

R

D

WR--+

>'--->--- lOR

~'-+-IOG.

B.

By By

~>++-IOB

a

Test
Register
MPU
Registers
& Control

24

I 1".1

I-------,

I

zen

S;S;

G>e

t t

o

r

"o
1\

W
V

§I

Vld
. . MUX
& Control

[

Clock
Control

"TI"T1

.j

en <

o
r

0

r

""

~I

[

[[

enenrG>
::r1;I>
ZZZtD

oO"S;
Z

"
Figure 1. Functional Block Diagram

cc
"'I
Q)

3

I /B • I Output
MUX

7

D~
RS

-o·
:J

~ HSYNCOUT
VSYNCOUT
MUXOUT

1.3 Terminal Assignments
D:X:: :x:: O,....~
-l-l:x::::t:
ZOO -l -l -l
a.. a.. a.. a.. a.. a.. a.. a.. a.. a.. a.. a.. a.. a.. >c::I(I) > 0 ()O

co 0> 0 .... C\JC') '0 ....
C\J C') C')

/'"-CO

C\JC\J

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

C\JC')O .... C\JC')'=>OO

c: c: c:

c::I> 0 0 - 00
ZZ

>->(1)(1)
I>

Figure 2. Terminal Assignments

1.4 Ordering Information
TLC34075 -

oqXX

FN

Pixel clock frequency indicator _ _ _ _ _ _ _ _ _ _ _ _---11

MUST CONTAIN TWO OR THREE CHARACTERS:
-66:
66-MHz pixel clock
-85:
85-MHz pixel clock
-110:
110-MHz pixel clock
-135:
135-MHz pixel clock
Package----------------------~

MUST CONTAIN TWO LETTERS:
FN: plastic, square, leaded chip carrier (formed leads)

9-117

1.5 Terminal Functions
PIN NAME

NO.

I/O

DESCRIPTION

BLANK,
VGABLANK

60,61

I

Blanking inputs. Two blanking inputs are provided in order to remove any
external multiplexing of the signals that may cause data and blank to skew.
When the VGA pass-through mode is set in the mux control register, the
VGABLANK input is used for blanking; otherwise, BLANK is used.

CLK<0:2>

77, 76, 75

I

Dot clock inputs. Any of the three clocks can be used to drive the dot clock
at frequencies up to 85 MHz. When VGA pass-through mode is active, CLKO
is used by default.

CLK3, CLK3

74, 73

I

Dual-mode dot clock input. This input is an ECL-compatible input, but a TTL
clock may be used on either CLK3 or CLK3 if so selected in the input clock
selection register. This input may be selected as the dot clock for any
frequency of operation up to the device limit while in the ECL mode; it may only
be used up to 85 MHz in the TTL mode.

COMP

52

I

Compensation input. This terminal provides compensation for the internal
reference amplifier. A resistor and ceramic capacitor are required between
this terminal and VDD. The resistor and capacitor must be as close to the
device as possible to avoid noise pickup. Referto Appendix B for more details.

0<0:7>

36-43

I/O

MPU interface data bus. Used to transfer data in and out of the register map
and palette/overlay RAM.

FSADJUST

51

I

Full-scale adjustment pin. A resistor connected between this pin and ground
controls the full-scale range of the DACs.

GND

44,54,
56,80

HSYNCOUT,
VSYNCOUT

46,47

0

Horizontal and vertical sync outputs of the true/complement gate mentioned
in the HSYNC, VSYNC description below (see Section 2.8).

HSYNC,VSYNC

58,59

I

Horizontal and vertical sync inputs. These signals are used to generate the
sync level on the green current output. They are active-low inputs for the
normal modes and are passed through a true/complement gate. Forthe VGA
pass-through mode, they are passed through to HSYNCOUT and
VSYNCOUT without polarity change as specified by the control register (see
Section 2.8).

lOR, lOG, lOB

48,49,50

0

Analog current outputs. These outputs can drive a37 .5-Q load directly (doubly
terminated 75-Q line), thus eliminating the need for any external buffering.

MUXOUT

63

0

MUX output control. This output pin is software programmable. It is set low
to indicate to external devices that VGA pass-through mode is being used
when the MUX control register value is setto 2Dh. If bit 7 ofthe general control
register is set high after the mode is set, this output goes high. This pin is only
used for external control; it affects no internal circuitry.

P<0:31>

29-1,
84-82

I

Pixel input port. This port can be used in various modes as shown in the MUX
control register. It is recommended that unused pins be tied to ground to lower
the device's power consumption.

RD

31

I

Read strobe input. A low logic level on this pin initiates a read from the
TLC34075 register map. Reads are performed asynchronously and are
initiated on the falling edge of RD (see Figure 3-1).

RS<0:3>

32-35

I

Register select inputs. These pins specify the location in the register map that
is to be accessed, as shown in Table 2-1.

SCLK

79

0

Shift clock output. This output is selected as a submultiple of the dot clock
input. SCLK is gated off during blanking.

9-118

Ground. All GND pins must be connected. The analog and digital GND pins
are connected internally.

PIN NAME

NO.

I/O

DESCRIPTION

SFLAG/NFLAG

62

I

Split shift register transfer flag or nibble flag input. This pin has two functions.
When the general control register bit 3 = 0 and bit 2 = 1, split shift register
transfer function is enabled and a low-to-high transition on this pin during a
blank sequence initiates an extra SCLK cycle to allow a split shift register
transfer in the VRAMs. When the general control register bit 3 = 1 and
bit2 =0, special nibble mode is enabled and this input is sampled atthefalling
edge of VCLK. A high value sampled indicates that the next SCLK rising edge
should latch the high nibble of each byte of the pixel data bus; a low value
sampled indicates that the low nibble of each byte ofthe pixel data bus should
be latched (see Section 2.9). When the general control register bit 3 =0 and
bit 2 =0, this pin is ignored. The condition of bit 3 =1, bit 2 =1 is not allowed,
and device operation is unpredictable if they are so set.

VCLK

78

0

Video clock output. User-programmable output for synchronization of the
TLC34075 to a graphics processor.

VOO

45,55,
57,81

VGA<0:7>

65-72

VREF

53

WR

30

I

Write strobe input. A low logic level on this pin initiates a write to the TLC34075
register map. Write transfers are asynchronous. The data written to the
register map is latched on the rising edge of WR (see Figure 3-1).

8/6

64

I

OAC resolution selection. This pin is used to select the data bus width (8 or
6 bits) for the OACs and is provided to maintain compatibility with the INMOS
IMSG176/8 color palette. When this pin is at a high logic level, 8-bit bus
transfers are used, with 0<7> being the MSB and 0<0> the LSB. For 6-bit bus
operation, while the color palette still has the 8-bit information, 0<5> shifts to
the bit 7 position, 0<0> shifts to the bit 2 position, and the two LSBs are filled
with zeros at the output MUX to the OAC. When read in the 6-bit mode, the
palette-holding register zeroes out the two MSBs.

Power. All VOO pins must be connected. The analog and digital VOO pins are
connected internally.
I

VGA pass-through bus. This bus can be selected as the pixel bus for VGA
pass-through mode. It does not allow for any multiplexing.
Voltage reference for OACs. An internal voltage reference of nominally
1.235 V is designed in. A 0.1-flf ceramic capacitor between this terminal and
GNO is recommended for noise filtering using either the internal or an external
reference voltage. The internal reference voltage can be overridden by an
externally supplied voltage. The typical connection is shown in Appendix B.

NOTES: 1. Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
2. All digital inputs and outputs are TTL-compatible, unless otherwise noted.

9-119

2 Detailed Description
2.1

MPU Interface

The processor interface is controlled via read and write strobes (RD, WR), four register select pins
(RS<0:3», and the 8i6 select pin. The 8i6 select pin is used to select between 8- or 6-bit operation and is
provided in order to maintain compatibility with the IMSG176/8 color palette. This operation is carried out
in order to utilize the maximum range of the DACs.
The internal register map is shown in Table 1. The MPU interface operates asynchronously, with data
transfers being synchronized by internal logic. All the register locations support read and write operations.

Table 1. Internal Register Map
RS3

RS2

RS1

RSO

L

L

L

L

Palette address register - write mode

L

L

L

H

Color palette holding register

L

L

H

L

Pixel read mask

L

L

H

H

Palette address register - read mode

L

H

L

L

Reserved

L

H

L

H

Reserved

L

H

H

L

Reserved

L

H

H

H

Reserved

H

L

L

L

General control register

H

L

L

H

Input clock selection register

H

L

H

L

Output clock selection register

H

L

H

H

Mux control register

H

H

L

L

Palette page register

H

H

L

H

Reserved

H

H

H

L

Test register

H

H

H

H

Reset state

REGISTER ADDRESSED BY MPU

2.2 Color Palette RAM
The color palette RAM is addressed by two internal 8-bit registers, one for reading from the RAM and one
for writing to the RAM. These registers are automatically incremented following a RAM transfer, allowing the
entire palette to be read/written with only one access of the address register. When the address register
increments beyond the last location in RAM, it is reset to the first location (address 0). Although all read and
write accesses to the RAM are asynchronous to SCLK, VCLK, and the dot clock, they are performed within
one dot clock and so do not cause any noticeable disturbance on the display.
The color palette RAM is 24 bits wide for each location (8 bits each for red, green, and blue). If 6-bit mode
is chosen (8/6 =low), the two MSBs are still written to the color palette RAM. However, if they are read back
in the 6-bit mode, the two MSBs are set to 0 to maintain compatibility with the I MSG 176/8 and BT47618 color
palettes. The output MUX shifts the six LSBs to the six MSB positions, fills the two LSBs with Os, then feeds
the eight bits to the DAC. With the 8/6 pin held low, data on the lowest six bits of the data bus are internally
shifted up by two bits to occupy the upper six bits at the output MUX, and the bottom two bits are then zeroed.
The test register and the ones accumulation register both take data before the output MUX to give the user
the maximum flexibility.
The color palette RAM access methodology is described in the following two sections and is fully compatible
with the IMSG176/8 and BT476/8 color palettes.

9-120

2.2.1

Writing to the Color Palette RAM

To load the color palette RAM, the MPU must first write to the address register (write mode) with the address
where the modification is to start. This action is followed by three successive writes to the palette-holding
register with eight bits each of red, green, and blue data. After the blue data write cycle, the three bytes of
color are concatenated into a 24-bit word and written to the color palette RAM location specified by the
address register. The address register then increments to point to the next color palette RAM location, which
the MPU may modify by simply writing another sequence of red, green, and blue data bytes. A block of color
values in consecutive locations may be written to by writing the start address and performing continuous
red, green, and blue write cycles until the entire block has been written.

2.2.2

Reading From the Color Palette RAM

Reading from the color palette RAM is performed by writing the location to be read to the address register.
This action initiates a transfer from the color palette RAM into the holding register followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (six or eight bits, depending on the 8/6 mode) for the specified location. Following the blue read
cycle, the contents of the color palette RAM at the address specified by the address register are copied into
the holding register and the address register is again incremented. As with writing to the color palette RAM,
a block of color values in consecutive locations may be read by writing the start address and performing
continuous red, green, and blue read cycles until the entire block has been read.

2.2.3

Palette Page Register

The 8-bit palette page register provides high-speed color changing by removing the need for color palette
RAM reloading. When using 1, 2, or 4 bit planes, the additional planes are provided by the palette page
register; e.g., when using four bit planes, the pixel inputs specify the lower four bits of the color palette RAM
address with the upper four bits being specified by the palette register. This provides the capability of
selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed
atthe line frequency. A bit-to-bit correspondence is used; therefore, in the above configuration, palette page
register bits 7 through 4 map onto color palette RAM address bits 7 through 4, respectively. This is illustrated
below.
NOTE: The additional bits from the palette page register are inserted before the read mask and hence, are
subject to masking.

Table 2. Allocation of Palette Page Register Bits
NUMBER OF
BIT PLANES

msb

COLOR PALETTE RAM ADDRESS BITS

8

M

M

4

P7

2
1

isb

M

M

M

M

M

M

P6

P5

P4

M

M

M

M

P7

P6

P5

P4

P3

P2

M

M

P7

P6

P5

P4

P3

P2

P1

M

Pn = nth bit from palette page register
M = bit from pixel port

2.3 Input/Output Clock Selection and Generation
The TlC34075 provides a maximum of five clock inputs. Three are dedicated to TIL inputs; the other two
can be selected as either one ECl input or two extra TIL inputs. The TIL inputs can be used for video rates
up to 85 MHz, above which an ECl clock source must be used (although the ECl clock may also be used
at lower frequencies). The dual-mode clock input (ECl/TTl) is primarily an ECl input but can be used as
a TIL-compatible input if the input clock selection register is so programmed. The clock source used at
power-up is ClKO; an alternative source can be selected by software during normal operation. This chosen
clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). The device does,

I

I

9-121

however, allow foruser programming of the SCLK and VCLK outputs (shift and video clocks) via the output
clock selection register. The input/output clock selection registers are shown in Tables 5,6, and 7.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals such
as BLANK and the SYNCs. WhileSCLK and VCLK are designed as general-purpose shift clock and video
clock, respectively, they also interface directly with the TMS340xO GSP family. While SCLK and VCLK can
be selected independently, there is still a relationship between the two. Internally, both SCLK and VCLK are
generated from a common clock counter that increments on the rising edge of the DOTCLK. When VCLK
is enabled and the VCLK and SCLK frequencies are programmed to be the same submultiple of the DOTCLK
frequency, then VCLK and SCLK are in phase. When VCLK is enabled and the VCLK and SCLK frequencies
are prograrnmed to be different submultiples of the DOTCLK frequency, then there are simultaneous rising
edges on the tWo waveforms at times determined by their frequency ratio (see Figure 3).
Appendix A discusses the SCLK/VCLK relationship specific to the TMS340xO GSP.

DOTCLK
VCLK
(DOTCLK/4
as an exampie)

J

SCLK
(DOTCLK/2
as an example)

Figure 3. DOTCLKNCLKlSCLK Relationship

Table 3. Input Clock Selection Register Format
BITSt

3

2

1

0

FUNCTION;
Select CLKO as clock source§

0

0

0

0

0

0

0

1

Select CLK1 as clock source

0

0

1

0

Select CLK2 as clock source

0

0

1

1

Select CLK3 as TIL clock source

0

1

0

0

Select CLK3 as TIL clock source

1

0

0

0

Select ClK3 and ClK3 as ECl clock sources

t Register bits 4, 5, 6, and 7 are don't care bits.
; When the clock selection is altered, a minimum 30-ns delay is incurred before the
new clocks are stabilized and running.
§ ClKO is chosen at power-up to support the VGA pass-through mode.

9-122

Table 4. Output Clock Selection Register Format
BITSt
5

4

3

2

0

0

0

0

0

1

0

1

0

1

1

FUNCTION

*

1

0

x

x

X

VCLK frequency

X

X

X

VCLK frequency

0

X

X

X

VCLK frequency

1

X

X

X

VCLK frequency

0

0

X

X

X

VCLK frequency

1

0

1

X

X

X

VCLK frequency

1

1

X

X

X

X

VCLK output held at logic high level (default condition)§

X

X

X

0

0

0

SCLK frequency

X

X

X

0

0

1

SCLK frequency

X

X

X

0

1

0

SCLK frequency

X

X

X

0

1

1

SCLK frequency

X

X

X

1

0

0

SCLK frequency

X

X

X

1

0

1

SCLK frequency

X

X

X

1

1

X

SCLK output held at logic level low (default condition)§

= OOTCLK frequency
= OOTCLK frequency/2
= OOTCLK frequency/4
= OOTCLK frequency/8
= OOTCLK frequency/16
= OOTCLK frequency/32
= OOTCLK frequency
= OOTCLK frequency/2
= OOTCLK frequency/4
= OOTCLK frequency/8
= OOTCLK frequency/16
= OOTCLK frequency/32

t Register bits 6 and 7 are don't care bits.
:\: When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks
are stabilized and running.
§ These lines indicate the power-up conditions required to support the VGA pass-through mode.

Table 5. VCLK/SCLK Divide Ratio Selection
(Output Clock Selection Register Value in Hex)

~

VCLK

BITS
5 ... 3 11

000
001
010
011
100
101

BITS
2 ••• 011

000

001

010

011

100

101

~

1

2

4

8

16

32

divide
DOTCLKby

1

00

01

02

03

04

05

2

08

09

OA

OB

OC

00

4

10

11

12

13

14

15

8
16

18

19

1A

1B

1C

10

20

21

22

23

24

25

32

28

29

2A

2B

2C

20

~ Output clock selection register bits

2.3.1

SCLK

The TLC34075 latches data on the rising edge of the LOAD signal (LOAD is the same as SCLK but is not
disabled while the BLANK signal is active). Therefore, SCLK must be set as a function of the pixel bus width
and the number of bit planes. The SCLK frequency can be selected to be the same as the dot clock frequency
or 1/2, 1/4, 1/8, 1/16, or 1/32 of the dot clock frequency. If SCLK is not used, the output is switched off and
held low to protect against VRAM lock-up due to invalid SCLK frequencies. SCLK is also held low during
the BLANK signal active period. The control timing has been designed to bring the first pixel data ready from
the VRAM when BLANK is disabled and ready for the display. When split shift register transfer operation
is used, SCLK is taken care of by working with SSRT input (see Section 2.9).
Refer to Figure 2-2 for the following timing explanation.
,~

9-123

I~

The falling edge of VCLK is used internally by the TLC34075 to sample and latch the BLANK input level.
When BLANK goes low, SCLK is disabled as soon as possible. In other words, if the last SCLK pulse is at
the high level while the sampled BLANK is low, SCLK is allowed to finish its cycle to low level, then SCLK
is held low until the sampled BLANK goes back high to enable it again. The VRAM shift register should be
updated during the BLANK active period, and the first SCLK pulse is used to clock the first valid pixel data
from the VRAM. The internal pipeline delay of the BLANK input is designed to be in phase with data at the
DAC output to the monitors. The logic described above works in situations wherein the SCLK period is
shorter than, equal to, or longer than the VCLK period.
Figure 5 shows the case wherein the SSRT (split shift register transfer) function is enabled. One SCLK pulse
with a minimum width of15 ns is generated from the rising edge at the SFLAG input with specified delay.
This is designed to meet the VRAM timing requirement, and this SCLK pulse replaces the first SCLK in the
regular shift register transfer case as described above. Refer to Section 2.9 for the detailed explaniltion of
the SSRT function.
The SCLK output waveform may vary at the time that the sampled BLANK input is low. Refer to Appendix C
for details.

2.3.2

VCLK

The VCLK frequency can be selected to be 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 of that of the dot clock, or it can
be held at a high logic level. The default condition is for VCLK to be held at a high logic level. VCLK is not
used in VGA pass-through mode.
VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and
VSYNC). As can be seen from Figures 4, 5, 6, and 7, since the control signals are sampled by VCLK, it is
obvious that VCLK has to be enabled.
VCLK

BLANK
at Input Pin

LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal - - - -..........--~
Before DOTCLK
Pipeline Delay)
.....- - - - - - - '
2nd
4th
1st Group 3rd Group 5th
6th
Group
Group
Group
Group
PIXEL DATA ~-L-a-st-G-ro-U-p-O-fP-ix-e-Io - a - t a - v - v - v - v - v - v - - - - - - at Input Pin ---./\......I\_~, ______1\.../\...../\-

SCLK

NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).
'

Figure 4. SCLKNCLK Control Timing (SSRTDisabled,
SCLK Frequency =VCLK Frequency)
9-124

VCLK

BLANK
at Input Pin
SFLAG/NFLAG

LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal ---+---~-"'I
Before DOTCLK
Pipeline Delay)

PIXEL DATA
at Input Pin
SCLK Between Split Shift Register Transfer
and Regular Shift Register Transfer
SCLK
NOTE:The SSRT function is enabled (general control register bit 2 = 1).

Figure 5. SCLKNCLK Control Timing (SSRT Enabled,
SCLK Frequency VCLK Frequency)

=

VCLK

BLANK
at Input Pin

LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal ------....;:.~--"'I
Before DOTCLK
Pipeline Delay)
'--------'"'"'2nd
4th
6th
1st Group. 3rd Group 5th Group
PIXEL DATA
at Input Pin

,--------------,

Group

Group

Group

Last Group of Pixel Data

SCLK

Figure 6. SCLKNCLK Control Timing (SSRT Disabled,
SCLK Frequency 4 x VCLK Frequency)

=

NOTE: Either the SSRT function is disabled (gerieral control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).

9-125

VCLK

BLANK
at Input Pin

SFLAG(NFLAG ----1--1-;....,.'-'

LOAD
(Internal Signal
tor Data Latch)
BLANK
(Internal Signal
Before DOTCLK
Pipeline Delay)

-----+--..;;..0:----,
'---.,....~----'

3rd

5th

2nd Group 4th Group 6th
Group
Group
Group

PIXEL DATA
at Input Pin

15t Group of Pixel Data

SCLK Between Split Shift Register
and Regular Shift Register Transfer
SCLK

Figure 7. SCLKNCLK Control Timing (SSRT Enabled,
SCLK Frequency = 4 x VCLK Frequency)

2.4 Multiplexing Scheme
The TlC34075 offers a highly versatile multiplexing scheme as illustrated in Table 6. The on-chip
multiplexing allows the system to be reconfigured to the amount of RAM available. For example, if only
25BK bytes of memory are available, an 800-by-BOO mode with 4 bit planes (four bits per pixel) could be
implemented using an 8-bit-wide pixel bus. If, at a later date, another 25BK bytes are added to another eight
bits of the pixel bus, the user has the option of using 8 bit planes at the same resolution or 4 bit planes at
a 1024-by-768 resolution. When an additional 512K bytes is added to the remaining 16 bits of the pixel bus,
the user has the option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280 by 1024. All the above can be
achieved without any hardware modification and without any increase in the speed of the pixel bus.

2.4.1

VGA Pass-Through Mode

Mode 0, the VGA pass-through mode, is used to emulate the VGA modes of most personal computers. The
advantage of this mode is that the TlC34075 can take data presented on the feature connectors of most
VGA-compatible PC systems into the device on a separate bus, thus requiring no external multiplexing. This
feature is particularly useful for systems in which the existing graphics circuitry is on the motherboard. In
this instance, it enables implementation of a drop-in graphics card that maintains compatibility with all
existing software by using the on-board VGA circuitry but routing the emerging bit-plane data through the
TlC34075. This is the default mode at power-up. When the VGA pass-through mode is selected after the
device is powered up, the clock selection register, the general control register, and the pixel read mask
register are set to their default states automatically.
Since this mode is designed with the feature connector philosophy, all the timing is referenced to ClKO,
which is used by default for VGA pass-through mode. For all the other normal modes, ClK <0:3> are the
oscillator sources for DOTClK, VClK, and SClK; all the data and control timing is referenced to SClK.

9-126

2.4.2

Multiplexing Modes

In addition to the VGA pass-through mode, there are four multiplexing modes available, all of which are
referred to as normal modes. In each normal mode, a pixel bus width of 8, 16, or 32 bits may be used. Modes
1, 2, and 3 also support a pixel bus width of 4 bits. Data should always be presented on the least significant
bits of the pixel bus. For example, when a 16-bit-wide pixel bus is used and there are 8 bits per pixel, each
8-bit pixel should be presented on P<0:7>. All the unused pixel bus pins should be connected to GND.
Mode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette
address, with the 7 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode has uses in high-resolution monochrome applications such as desktop publishing. This mode
allows the maximum amount of multiplexing (a 32:1 ratio), thus giving a pixel bus rate of only 4 MHz at a
screen resolution of 1280 by 1024. Although only a single bit plane is used, alteration of the palette page
register at the line frequency allows 256 different colors to be displayed simultaneously with 2 colors per line.
Mode 2 uses 2 bit planes to address the color palette. The 2 bits are fed into the low-order address bits of
the palette with the 6 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode allows a maximum divide ratio of 16:1 on the pixel bus and is a 4-color alternative to mode 1.
Mode 3 uses 4 bit planes to address the color palette. The 4 bits are fed into the low-order address bits of
the palette with the 4 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode provides 16 pages of 16 colors and can be used at SCLK divide ratios of 1 to 8,
Mode 4 uses 8 bit planes to address the color palette. Since all 8 bits of palette address are specified from
the pixel port, the page register is not used. This mode allows dot-clock-to-SCLK ratios of 1:1 (8-bit bus),
2: 1 (16-bit bus) or 4: 1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024-by-768 pixel screen can be
implemented with an external data rate of only 16 MHz.

2.4.3

True Color Mode

Mode 5 is true color mode, in which 24 bits of data are transferred from the pixel port directly to the DACs
with the same amount of pipeline delay as the overlay data and the control signals (BLANK and SYNCs).
In this mode, overlay is provided by using the remaining 8 bits of the pixel bus to address the palette RAM,
resulting in a 24-bit RAM output that is then used as overlay information to the DACs. When all the overlay
inputs (P<0:7» are ata low logic level or the pixel read mask register is loaded with the value 0, no overlay
information is displayed; when a nonzero value is input with the pixel read mask enabled, the color palette
RAM is addressed and the resulting data is then fed through to the DACs, receiving priority over the true
color data.
The true-color-mode data input only works in the 8-bit mode. In other words, if only 6 bits are used, the 2
MSB inputs for each color should be tied to GND. However, the palette, which is used by the overlay input,
is still governed by the 8/S input pin, and the output MUX selects 8 bits of data or 6 bits of data accordingly.
In the true color mode, P<15:8> pass red data, P<23:16> pass green data, and P<31 :24> pass blue data.

2.4.4

Special Nibble Mode

Mode 6 is special nibble mode, which is enabled when the general control register SNM bit (bit 3) is set to
1 and the general control register SSRT bit (bit 2) is set to 0 (see Section 2.11). When special nibble mode
is enabled, it takes precedence over the other modes, and the mux control register setup is ignored. The
SFLAG/NFLAG input is then used as a nibble flag to indicate which nibble of each byte holds the pixel data.
Special nibble mode is a variation of the 4-bit pixel mode with a 16-bit pixel width. All 32 inputs (PO through
P31) are connected as 4 bytes, but the 16-bit data bus is composed of either the lower or upper nibble of
each of the 4 bytes. For more detailed information, refer to Section 2.9.2. Since this mode uses 4 bit planes
for each pixel, they are fed into the low-order address bits of the palette, with the 4 high-order address bits
being defined by the palette page register (see Section 2.2.3).

2.4.5

Multiplex Control Register

The multiplexer is controlled via the 8-bit multiplex control register. The bit fields ofthe register are in Table 6.

9-127

Table 6. Mode and Bus Width Selection
MODE

0#

MUX CONTROL REGISTER BITSt

DATA BITS
PER
PIXEL:!:

PIXEL
BUS
WIDTH

SCLK
DIVIDE
RATIO§

PIXEL
LATCHING
SEQUENCE1f

5

4

3

2

1

1

0

1

1

0

1

8

8

1

1) VGA<7:0>

0

1

0

0

0

0

1

4

4

1)
2)
3)
4)

0

1

0

0

0

1

1

8

8

1) P
2) P<1>

0

1

0

0

1

0

1

16

16

0

1

0

0

1

1

1

32

32

0

1

0

1

0

0

2

4

2

1) P<1:0>
2) P<3:2>

0

1

0

1

0

1

2

8

4

1)
2)
3)
4)

0

1

0

1

1

0

2

16

8

1) P<1 :0>
2) P<3:2>

0

1

0

1

1

1

2

32

16

0

1

1

0

0

0

4

4

1

1) P<3:0>

0

1

1

0

0

1

4

8

2

1) P<3:0>
2) P<7:4>

0

1

1

0

1

0

4

16

4

1)
2)
3)
4)

0

1

1

0

1

1

4

32

8

1) P<3:0>
2) P<7:4>

0
P
P<1 >
P<2>
P<3>

8) P<7>
1

1) P
2) P<1>
16) P"<15>
1) P
2) P<1>
32) P"<31>

2

P<1:0>
P<3:2>
P<5:4>
P<7:6>

8) P<"15:14>
1) P<1:0>
2) P<3:2>
16) P"<31 :30>

3

P<3:0>
P<7:4>
P<11:8>
P<15:12>

8) P<"31 :28>

9-128

MODE

MUX CONTROL REGISTER BITSt

DATA BITS
PER
PIXEL*

PIXEL
BUS
WIDTH

SCLK
DIVIDE
RATIO§

5

4

3

2

1

0

0

1

1

1

0

0

8

8

1

1) P<7:0>

0

1

1

1

0

1

8

16

2

1) P<7:0>
2) P<15:8>

0

1

1

1

1

0

8

32

4

1)
2)
3)
4)

0

0

1

1

0

1

24

32

1

1) P<31:8>

0

1

1

1

1

1

4

16

4

4

511

6

PIXEL
LATCHING
SEQUENCE~

P<7:0>
P<15:8>
P<23:16>
P<31:24>

~ELAG

1)
2)
3)
4)

- Q'
P<3:0>
P<11 :8>
P<19:16>
P<27:24>

NFLAG = 1;
1) P<7:4>
2) P<15:12>
3) P<23:20>
4) P<31:28>

*t

Bits 6 and 7 are don't care bits.
This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,
often referred to as the number of bit planes. This may be color palette address data (Modes 0-4 and 6) or DAC data
(mode 5).
§ The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8
bit planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
~ For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P<3:0>, P<7:4>, P<11 :8>, P<15:12>.
# Mode 0 is VGA pass-through mode.
" Mode 5 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the DACs;
overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel port data to the DACs is as
follows: P<31 :24> are passed to the blue DAC, P<23:16> are passed to the green DAC, and P<15:8> are passed to
the red DAC. P<7:0> are used to generate overlay data; this operation can be disabled by either grounding P<7:0> or
by clearing the read mask (see Section 1.4.5).
p Mode 6 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in
bits, of the pixel bus. In this mode, the pixel bus is physically 32 bits wide; depending on the value of SFLAG/NFLAG,
either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal
to four 4-bit pixels).
NOTE: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground lowers
power consumption and, thus, is recommended.

9-129

As an example of how to use Table 6, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible SCLK rate, Table 6 shows that, for non-VGA-pass-through operation, only
mode 4 supports an eight-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set of
conditions is selected by writing the value 1Eh to the mux control register. The pixel latching sequence
column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed
by P<15:8>, P<23:16>, and then P<31 :24> as the last displayed pixel plane. Assuming that VCLK is
programmed as DOTCLK/4, Table 2-5 shows that the 1:4 SCLK ratio is selected by writing the value 12h
to the output clock selection register. The special nibble mode should also be disabled (see Sections 2.9.2
and 2.11.2).
When the mux control register is loaded with 2Dh, the TLC34075 enters the VGA pass-through mode (the
same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.

2.4.6

Read Masking

The read mask register is used to enable or disable a pixel address bit from addressing the color palette
RAM. Each palette address bit is logically ANDed with the corresponding bit from the read mask register
before addressing the palette. This function is performed after the addition of the page register bits and,
therefore, a zeroing of the read mask results in one unique palette location (location 0) and is not affected
by the palette page register contents.

2.5

Reset

There are 3 ways to reset the TLC34075:
1.
2.
3.

2.5.1

Power-on reset
Hardware reset
Software reset

Power-On Reset

The TLC34075 contains a power-on reset circuit. Once the voltage levels have stabilized following power-on
reset, the device is in the VGA pass-through mode.

2.5.2

Hardware Reset

The TLC34075 resets whenever RS<3:0> = HHHH and a rising edge occurs on the WR input. The more
rising WR edges occur, the more reliable theTLC34075 .is reset. This scheme (bursting WR strobes until
the power supply voltage stablizes) is suggested at power-up if a hardware reset approach is used.
The default reset condition is VGA pass-through mode, and the values for each register are shown in
Section 2.5.4.

2.5.3

Software Reset

Whenever the mux control register is set for VGA pass-through mode after power-up, all registers are
initialized accordingly. Since VGA pass-through mode is the default condition at power-up and hardware
reset, the act of selecting the VGA pass-through mode through programming the mux control register is
viewed as a software reset. Therefore, whenever mux control register bits <5:0> are set to 2Dh, the
TLC34075 initiates a software reset.

2.5.4

VGA Pass-Through Mode Default Conditions

. The value contained in each register after hardware or software reset is shown below:
Mux control register:
Input clock selection register:
Output clock selection register:
Palette page register:
General control register:

9-130

2Dh
OOh
3Fh
OOh
03h

Pixel read mask register:
Palette address register:
Palette holding register:
Test register:

2.6

FFh
xxh
xxh
(Pointing to color palette red value)

Frame Buffer Interface

The TLC34075 provides two clock signals for controlling the frame buffer interface: SCLK and VCLK. SCLK
can be used to clock out data directly from the VRAM shift registers. Split shift register transfer functionality
is also supported. VCLK is used to clock and synchronize control inputs like HSYNC, VSYNC, and BLANK.
The pixel data presented atthe inputs is latched at the rising edge of SCLK in normal mode or the rising edge
of CLKO in VGA pass-through mode. Control inputs HSYNC, VSYNC, and BLANK are sampled and latched
at the falling edge ofVCLK in normal mode, while HSYNC, VSYNC, and VGABLANK are latched at the rising
edge of CLKO in VGA pass-through mode. Both data and control signals are lined up at the DAC outputs
to the monitors through the internal pipeline delay, so external glue logic is not required. The outputs of the
DACs are capable of directly driving a 37.5-Q load, as in the case of a doubly terminated 75-Q cable. See
Figures 9 and 10 for nominal output levels.

2.7

Analog Output SpeCifications

The DAC outputs are controlled by current sources (three for lOG and two each for lOR and lOB) as shown
in Figure 8. In the normal case, there is a 7.5-IRE difference between blank and black levels, which is shown
in Figure 9. If a 0-1 RE pedestal is desired, it can be selected by resetting bit 4 of the general control register
(see Section 2.11.3). The video output for a O-IRE pedestal is shown in Figure 10.

lOG

SYNC
(lOG Only)

G <0:7>

r-

15PF

Figure 8. Equivalent Circuit of the lOG Current Output

9-131

Green
mA
V
White - - - " , - - , . - . . , . - - - - - - - - - - - - - - - - - - - - : : : : : : - -

26.67

Red/Blue
mA
V

19.0S

0.714

0.OS4

92.SIRE

Black

7.SIRE
Blank

9.0S

0.34

1.44

7.62

0.286

0

0

0

0

40 IRE
Sync

Figure 9. 7.5-IRE, a-Bit Composite Video Output

White

Green
mA
V

Red/Blue
mA
V

2S.24

17.62

0.9S

0.66

100 IRE

Black/
Blank

-~o-----------'-_,_-._-'----------­ 7.62

0.286

o

o

431RE
Sync -~~-----------'--~-----------

o

o

Figure 10. O-IRE, a-Bit Composite Video Output
NOTE: 75- Q doubly terminated load. VREF = 1.235 V, RSET = 523

Q.

RS-343A levels and tolerances are assumed.

A resistor (RSET) is needed to connect the FS ADJ pin to GND to control the magnitude of the full-scale video
signal. The I RE relationships in Figures 9 and 10 are maintained regardless of the full-scale output current.

9-132

The relationship between RSET and the full-scale output current lOG is:
RSET (Q) = K1 x VREF (V) / lOG (mA)
The full-scale output current on lOR and lOB for a given RSET is:
lOR, lOB (mA) = K2 x VREF

M I RSET (Q)

where K1 and K2 are defined as:
lOG
PEDESTAL

2.8

a-BIT OUTPUT

7.5-IRE

K1

O-IRE

K1

IOR,IOB
6-BIT OUTPUT

= 11,294
= 10,684

K1
K1

= 11,206
= 10,600

a-BIT OUTPUT

= 8,067
K2 =7,462
K2

6·BIT OUTPUT
K2
K2

=7,979
=7,374

HSYNC, VSYNC, and BLANK

For the normal modes, HSYNC and VSYNC are active-low pulses, and they are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general control register. However, for the VGA
pass-through mode, the polarities needed for monitors are already provided at the feature connector from
which HSYNC and VSYNC are sourced, so the TLC34075 just passes HSYNC and VSYNC through to
HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 4 through
5, the BLANK, HSYNC, and VSYNC inputs are sampled and latched on the falling edge of VCLK in the
normal modes, and they are latched on the rising edge of the CLKO input in the VGA pass-through mode.
Refer to Figure 16 for the detailed timing.
The HSYNC and VSYNC inputs are used for both the VGA pass-through and normal modes. If the
application uses both VGA pass-through and normal modes, an external multiplexer is needed to select
HSYNC and VSYNC between VGA pass-through mode and normal mode. The MUXOUT signal is designed
for this purpose (see Sections 2.10 and 2.11).
The HSYNC, VSYNC, and BLANK signals have internal pipeline delays to align the data atthe outputs. Due
to the sample and latch timing delay, it is possible to have active SCLK pulses after the BLANK input
becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay
need to be carefully reviewed and programmed. See Section 2.3 and Figures 4 and 5 for more details.
As shown in Figure 18 forthe lOG DAC output, active HSYNC and VSYNC signals turn off the sync current
source (after the pipeline delay) independent of the BLANK signal level. In real applications, HSYNC and
VSYNC should only be active (low) when BLANK is active (low).
To alter the polarity of the HSYNCOUT and VSYNCOUT outputs in the normal modes, the MPU must set
or clear the corresponding bits in the general control register (see Section 2.11.1). Again, these two bits affect
only the normal modes, not the VGA pass-through mode. These bits default to 1.

2.9

Split Shift Register Transfer VRAMs and Special Nibble Mode

2.9.1

Split Shift Register Transfer VRAMs

The TLC34075 directly supports split shift register transfer (SSRT) VRAMs. In order to allow the VRAMs
to perform a split shift register transfer, an extra SCLK cycle must be inserted during the blank sequence.
This is initiated when the SSRT enable bit (bit 2 in the general control register) is set to 1, the SNM bit (bit 3
in the general control register) is reset to 0 (see Section 2.11), and a rising edge on the SFLAG/NFLAG input
pin is detected. An SCLK pulse is generated within 20 ns of the riSing edge of the SFLAG/NFLAG signal.
A minimum 15-ns high logic level duration is provided to satisfy all of the -15 VRAM requirements. By
controlling the SFLAG/NFLAG rise time, the delay time from the rising edge of the VRAM TRG signal to
SCLK can be satisfied. The relationship between the SCLK, SFLAG/N FLAG , and BLANK signals is as
follows:
9-133

BLANK

~~______________________________________~r----

SSRT Enable
(General Control
Register Bit 2)

SFLAGIN:~: ___________~~~____________________________________
Figure 11. Relationship Between SFLAG/NFLAG, BLANK, and SCLK
If SFLAG/NFLAG is designed as an R-S latch set by split shift register transfer timing and reset by BLANK
going high, the delay from BLANK high to SFLAG/NFLAG low cannot exceed one-half of one SCLK cycle;
otherwise, the SCLK generation logic may fail.
.
If the SSRT function is enabled but SFLAG/NFLAG is held low, SCLK runs as if the SSRT function is
disabled. The SFLAG/NFLAG input is not qualified by the BLANK signal and needs to be held low whenever
an SSRT SCLK pulse is not desired. Refer to Section 2.3.1 and Figures 4 through 10 for more system details.

2.9.2

Special Nibble Mode

Special nibble mode is enabled when the SNM bit (bit 3 in the general control register) is set to 1 and the
SSRT bit (bit 2 in the general control register) is reset to 0 (see Section 2.11). Special nibble mode provides
a variation of the 4-bit pixel mode with a 16-bit bus width. While all 32 inputs (P
P<15:12>
P<23:20>
P<31:28>

P<3:0>
P<11 :8>
P<19:16>
P<27:24>

The SFLAG/NFLAG value is not latched by the TLC34075. Therefore, it should stay at the same level during
the whole active display period, changing levels only during the BLANK signal active time. Refer to
Figure 12, which is similar to Figure 4 except that the BLANK Signal timing reference to SFLAG/NFLAG is
explained. The SFLAG/NFLAG input has to meet the setup time and hold the data long enough to ensure
that no pixel data is missed.
Special nibble mode operates at the line frequency when BLANK is active. However, the typical application
of this mode is double frame buffers with pixel data width of 4 bits. While one frame buffer is being displayed
on the monitor, the other frame buffer can be used to accept new picture information. SFLAG/NFLAG is used
to indicate which frame buffer is being displayed.
SNM and SSRT must be mutually exclusive. Unpredictable operation occurs if both the SNM and SSRT bits
are set to 1. The mux control register should be set up as shown in Table 6 (see Section 2.4.5). However,
the SNM bit takes precedence over the other mux control register selections. In other words, if the mux
control register is set up for another mode but special nibble mode is still enabled in the general control
register, the input multiplex circuit takes whatever SCLK divide ratio the mux control register specifies and
performs the nibble operation, causing operational failure.
9--134

During special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified
nibble. The specified nibble is stored in the 4 LSBs of the next register pipe after the input latch, and the
4 MSBs are zeroed in that register. The register pipe contents are then passed to the read mask block. With
this structure, the palette page register still functions normally, providing good flexibility to users.
If the general control register bit 3 = 0 and bit 2 = 0, both split shift register transfers and special nibble mode
are disabled and the SFLAG/NFLAG input is ignored.
VCLK

BLANK
(at its input pin)

SFLAG/N FLAG
Input _ _-,1--'

Valid

LOAD

Sampled
BLANK

PIXEL DATA

2nd
4th
1st Group 3rd Group 5th
Group
Group
Group

I
=x=:>K--------x=x=xxx=
Last Group of Pixel Data

I
SCLK

t CAUTION:
If the data is not held valid until SCLK and BLANK both go low, the last few pixels could be missed.
:j: Setup time to next VCLK falling edge after BLANK high (must be met, otherwise the first pixel data

could be missed).

Figure 12. SFLAG/NFLAG Timing in Special Nibble Mode

2.10

MUXOUT Output

MUXOUT is a TTL-compatible output. It is software programmable and is used to control external devices.
Its typical application is to select the HSYNC and VSYNC inputs between the VGA pass-through mode and
the normal modes (see Section 2.8). This output is driven low at power-up orwhen VGA pass-through mode
is selected; at any other time it can be programmed to the desired polarity via general control register bit 7.

2.11

General Control Register

The general control register is used to control HSYNC and VSYNC polarity, split shift register transfer
enabling, special nibble mode, sync control, the ones accumulation clock source, and the VGA pass-through
indicator. The bit field definitions are as follows:

9-135

Table 8. General Control Register Bit Functions
GENERAL CONTROL REGISTER BIT

7

2.11.1

6

5

4

3

2

1

FUNCTION

X

X

X

X

X

X

X

0
0

X

X

X

X

X

X

X

1

HSYNCOUT is active-high (default)

X

X

X

X

X

X

0

X

VSYNCOUT is active-low

X

X

X

X

X

X

1

X

VSYNCOUT is active-high (default)

X

X

X

X

X

0

X

X

Disable split shift register transfer (default)

X

X

X

X

1

X

X

Enable split shift register transfer

X

X

X

X

0
0

X

X

X

Disable special nibble mode (default)

HSYNCOUT is active-low

X

X

X

X

1

0

X

X

Enable special nibble mode

X

X

X

0

X

X

X

X

O-IRE pedestal (default)

X

X

X

1

X

X

X

X

7.5-IRE pedestal

X

X

0

X

X

X

X

X

Disable sync (default)

X

X

1

X

X

X

X

X

Enable sync

X

0

X

X

X

X

X

X

Reserved (default)

X

1

X

X

X

X

X

X

Reserved

0

X

X

X

X

X

X

X

MUXOUT is low (default)

1

X

X

X

X

X

X

X

MUXOUT is high

HSYNCOUT and VSYNCOUT (Bits 0 and 1)

HSYNCOUT and VSYNCOUT polarity inversion is provided to allow indication to monitors of the current
screen resolution. Since the polarities for VGA pass-through mode are provided at the feature connector,
the inputs to the TLC34075 will have the right polarities for monitors already, so the TLC34075 just passes
them through with pipeline delay (see Section 2.8). These two bits only work in the normal modes, and the
input horizontal and vertical syncs are assumed to be active-low incoming pulses. These two bits default
to the value 1 but can be changed by software.

2.11.2

Split Shift Register Transfer Enable (SSRn and Special Nibble Mode Enable
(SNM) (Bits 2 and 3)

See Section 2.9.

2.11.3

Pedestal Enable Control (Bit 4)

This bit specifies whether a 0- or 7.5-1 RE blanking pedestal is to be generated on the video outputs. Having
a O-IRE blanking pedestal means that the black and blank levels are the same.
0: O-IRE pedestal (default)
1: 7.5-IRE pedestal

2.11.4

Sync Enable Control (Bit 5)

This bit specifies whether or not SYNC information is to be output onto lOG.
0: Disable sync (default)
1: Enable sync

2.11.5

MUXOUT (Bit 7)

The MUXOUT bit indicates to external circuitry that the device is running in VGA pass-through mode. This
bit does not affect the operation of the device (see Section 2.10).
0: MUXOUT is low (default in VGA pass-through mode)
1: MUXOUT is high
9-136

2.12

Test Register

There are three test functions provided in the TLC34075, and they are all controlled and monitored through
the test register. They are data flow check, DAC analog test, and screen integrity test.
The test register has two ports: one for a control word, accessed by writing to the register location, and one
for the data word, accessed by reading from the register location. Depending on the channel written in the
control word, the data read presents the information for that channel.
The control word is three bits long and occupies 0<2:0>. It specifies which of the eight channels to inspect.
The following table and state machine diagrams show how each channel is addressed:

Table 9. Test Mode Selection
02

01

DO

0
0
0
0

0
0

0

Color palette red value

1

Color palette green value

1

0

Color palette blue value

1

1

Identification code

1

0

Ones accumUlation red value

1

0
0

1

Ones accumUlation green value

1

1

0

Ones accumulation blue value

1

1

1

Analog test

CHANNEL

10 code

RESET

Blue

Data Flow Check

Red

r-<:J

Blue

RO

~

OAC Analog Test
Screen Integrity Test

Figure 13. Test Register Control Word State Diagrams
9-137

2.12.1

Frame Buffer Data Flow Test

The TLC34075 provides a means to check all the data entering the OAC (but before the output multiplexer
sis shift). When accessing these color channels, the data entering the OACs should be kept constant for
the entire MPl1 read cycle. This can be done either by slowing down the dot clock or ensuring that the data
is constant for a suffiCiently long series of pixels. The value read is the one stored in the color palette RAM
location pOinted to by the input multiplexer. The read operation causes a post-increment to point to the next
color channel, and the post-increment of blue wraps back to red as shown in the preceeding state diagram.
For example, if 0<2:0> is written as 001, then three succsessive reads are performed, the values read out
are green, blue, and red in that sequence.

2.12.2

Identification Code

The 10 code can be used for identification of different software versions. The 10 code in the TLC34075 is
static and may be read without consideration of the dot clock or video signals. To be user-friendly, the read
postincrement also applies to the 10 register, but once it falls into the color channel, it will not come back
pointing to the 10 unless the value 011 is written to 0<2:0> again. So, if the test register is written as 011 in
0<2:0>, then six successive reads are performed, the first value read is the 10 and the last value read is
green. The 10 value defined here is 75h.

2.12.3

Ones Accumulation Screen Integrity Test

A technique called ones accumulation canbe used to detect errors in fixed (not animated) screen displays.
This type of error detection is useful for system checkout and field diagnostics.
Each of the 256 24-bit words in the TLC34075 internal color palette RAM is composed of three bytes, one
each for the red, green, and blue components of the word. When 0<2:0> are programmed with the
appropriate binary value (see Table 9), the TLC34075 monitors the corresponding color byte that is output
by the color palette RAM. For example, if 0<2:0> are programmed with the value 100, the TLC34075
monitors the red byte. As the current frame is scanned, for each color palette RAM word accessed, the
designated color byte is checked to see how many "1" bits it contains, and this number is added to a
temporary accumulator (the entire byte is checked, even if 6-bit mode is selected). For example, if the
designated color byte contains the value 41 h (0100 0001), then the value 2 is added to the temporary
accumulator, as 41 h contains two "1" bits. This process is continued until an entire frame has been scanned;
the same color byte is monitored for the entire frame. The temporary accumulator truncates any overflow
above the value 255. Due to circuit speed limitations, the ones accumulation is calculated at a speed of
(OOTCLK frequency)/2. Ouring the vertical retrace activated by a falling edge on the TLC34075 VSYNC
input, the value in the temporary accumulator is transferred into the Ones accumulation register, and then
the temporary accumulator is reset to zero (NOTE: the ones accumulation register is updated only on the
falling edge of VSYNC, not by any vertical sync pulses coded into the composite video signal). Before the
next frame scan begins, the TLC34075 automatically changes the value in 0<2:0> so that the ones
accumulation performed during the next frame scan is for a different color byte (see the screen integrity test
state diagram of Figure 13). As long as the screen display remains fixed, the ones accumulation value for
a particular color byte should not change; if it does, an error has occurred.

2.12.4

Analog Test

Analog test is used to compare the voltage amplitudes of the analog RGB outputs to each other and to a
145-mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog
RGB outputs or not and whether the PACs are functional. To perform an analog test, 0<2:0> must be set
to 111; 0<7:4> are set as shown in Table 11. 0<3> contains the result of the analog test.

9-138

Table 10. Test Register Bit Definitions for Analog Test
BIT DEFINITION

READ/WRITE

07: Red select

RNI

06: Green select

RNI

05: Blue select

RNI

04: 145-mV reference select

RNI

03: Result

R

Table 11. 0<7:4> Bit Coding for Analog Comparisons
D<7:4>

OPERATION

IF D3

=1

IF D3

Don't care

=0

Don't care

0000

Normal operation

1010

Red OAC compared to blue OAC

Red> blue

Red < blue

1001

Red OAC compared to 145-mV reference

Red> 145 mV

Red < 145 mV

0110

Green OAC compared to blue OAC

Green> blue

Green < blue

0101

Green OAC compared to 145-mV reference

Green> 145 mV

Green < 145 mV

NOTE: All the outputs have to be terminated to compare the voltage.

01

10RorIOG~D

lOB or 145 mV

BLANK
(Internal Signal)

-

D3

C
~_--'

Figure 14. Internal Comparator Circuitry for Analog Test
The result of the analog comparison is strobed into 03 at the falling edge of an internal signal derived from
the input BLANK signal. In order to have stable inputs to the comparator, the OAC should be set to a constant
level between syncs. For normal operation, data flow check, and screen integrity test, 0<7:4> must be set
to zero.

9-139

3

Specifications

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
{Unless Otherwise Noted)t
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage range, VI .......................•............. -0.5 V to VOD + 0.5 V
Analog output short-circuit duration to any power supply or common ......... unlimited
Operating free-air temperature range, T A .............................. O°C to 70°C
Storage temperature range ...................................... -65°C to 150°C
Junction temperature ......................... '............................ 175°C
Case temperature for 10 seconds: FN package .............................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal.

3.2 Recommended Operating Conditions
VDD

Supply voltage

VREF

Reference voltage

VIH

High-level input voltage

Vil

low-level input voltage

MIN

NOM

MAX

UNIT

4.75

5

5.25

V

1.2

1.235

1.26

V

TTL inputs

2.4

VDD + 0.5

ECl inputs

VDD-1

VDD + 0.5

TTL inputs
ECl inputs

0.8
-0.5

Output load resistance, Rl

9-140

Q

523

0

V
Q

37.5

FS ADJUST resistor, RSET
Operating free-air temperature

VDD -1.6

V

70

°C

3.3 Electrical Characteristics
PARAMETER
VOH
VOL

IIH
IlL

100

High-level output voltage
Low-level output
voltage

0<0:7>, MUXOUT, VCLK

IOZ
Ci

IOH =-800 f,lA

MIN

TYpt

MAX

2.4
0.4

HSYNCOU~VSYNCOUT

IOL = 15 mA

0.4

IOL = 18 mA

0.4

High-level input

TTL inputs

VI = 2.4 V

1

current

ECL inputs

VI = 4V

1

Low-level input

TTL inputs

VI = 0.8 V

-1

current

ECL inputs

VI = 0.4 V

-1

TLC34075-66

350

Supply current,

TLC34075-85

375

pseudo-color mode

TLC34075-110

400

TLC34075-135

470

See Note 2

450

Supply current,

TLC34075-85

450

true color mode

TLC34075-110

450

TLC34075-135

450

High-impedance-state output currrent
Input capacitance

UNIT
V

IOL = 3.2 mA

SCLK

TLC34075-66
100

TEST CONDITIONS

10

TTL inputs

f = 1 MHz, VI = 2.4 V

4

ECL inputs

f = 1 MHz, VI = 4 V

4

V

f,lA

f,lA

mA

f,lA
pF

t All typical values are at VOO = 5 V, T A = 25°C.
NOTE 2: 100 is measured with OOTCLK running at the maximum specified frequency, SCLK frequency =
OOTCLK frequency/4, and the palette RAM loaded with fUll-range toggling patterns (OOh/OOh/FFh/FFh/OOh/
OOh/FFh/FFh/ ... ). Pseudo-color mode is also known as color indexing mode.

9-141

3.4 Operating Characteristics
PARAMETER
Resolution (each DAC)
EL
ED

TEST CONDITIONS

MIN

TYP

8/6 high

8

8/6 low

6

End-point linearity error

8/6 high

(each DAC)

8/6 low

Differential linearity error

8/6 high

(each DAC)

8/6 low

1/4
1
1/4
17.69

19.05

20.4

White level relative to black (7.5 IRE only)

16.74

17.62

18.5

Black level relative to blank (7.5 IRE only)

0.95

1.44

1.9

0

5

50

fAA

7.6

8.96

mA

Sync level on lOG (with SYNC enabled)

0

5

50

fAA

One LSB (8/6 high)

69.1

One LSB (8/6 low)

276.4
2%
-20
-1

Output compliance
Output impedance

Glitch impulse (see Note 2)

9-142

fAA
5%
dB
1.2

50
f = 1 MHz. lOUT = 0

Clock and data feedthrough

NOTE 2:

mA

6.29

DAC-to-DAC matching

Pipeline delay

LSB

Blank level on lOG (with SYNC enabled)

DAC-to-DAC crosstalk

Output capacitance

LSB

5%
White level relative to blank

Blank level on lOR. lOB

Voc

UNIT
bits

1

Gray scale error

Output current

MAX

Normal mode
VGA pass-through mode

V
kQ

13

pF

-20

dB

50

pV-s

1 SCLK + 9 DOTCLK
7.5 DOTCLK

periods

Glitch impulse does not include clock and data feedthrough. The -3-dB test bandwidth is twice the clock rate.

3.5 Timing Requirements
TLC34075-66 TLC34075-85

PARAMETER

MIN

MAX

MIN

MAX

TLC34075-110

MIN

MAX

TLC34075-135
MIN

MAX

UNIT

OOTCLK frequency

66

85

110

135

MHz

ClKO frequency for VGA
pass-through mode

66

85

85

85

MHz

TTL

15.2

11.8

9.1

7.4

ECl

15.2

11.8

9.1

7.4

10

10

10

10

ns

Hold time, RS<0:3> valid
after RO or WR ~

10

10

10

10

ns

tsu2

Setup time, 0<0:7> valid
before WR T

35

35

35

35

ns

th2

Hold time, 0<0:7> valid
after WR t

0

0

0

0

ns

tsu3

Setup time, VGA<0:7> and
HSYNC, VSYNC, and
VGABLANK valid before
ClKO t

2

2

2

2

ns

th3

Hold time, VGA<0:7> and
HSYNC, VSYNC, and
VGABLANK valid after ClKO

2

2

2

2

ns

tcyc

Clock cycle time

tsul

Setup time, RS<0:3>
valid before RO or WR

th1

~

ns

t

tsu4

Setup time, P<0:31> valid
before SClK t

2

2

2

0

ns

th4

Hold time, P<0:31> valid after
SClK t

5

5

5

5

ns

tsu5

Setup time, HSYNC, VSYNC,
and BLANK valid before
VClK ~

5

5

5

5

ns

th5

Hold time, HSYNC, VSYNC,
and BLANK valid after VClK

2

2

2

2

ns

tw1

Pulse duration, RO or WR loW

50

50

50

50

ns

tw2

Pulse duration, RO or WR high

30

30

30

30

ns

TTL

4.5

4

3.5

3

ECl

5.5

4

3.5

3

TTL

4.5

4

3.5

3

~

tw3

Pulse duration, clock high

tw4

Pulse duration, clock low

ECl

5.5

4

3.5

3

tW5

Pulse duration, SFLAG/NFLAG
high (see Note 4)

30

30

30

30

ns
ns
ns

NOTES: 3. TTL input Signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECl input signals are VOO-1.8 Vto VOO-0.8 Vwith less than 2 ns rise/fall time between
the 20% and 80% levels. For input and output signals, timing reference points are atthe 10% and 90% Signal
levels. Analog output loads are less than 10 pF. 0<0:7> output loads are less than 50 pF. All other output loads
are less than 50 pF unless otherwise specified.
4. This parameter applies when the split sbift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.

9--143

3.6 Switching Characteristics
TL34075-66, TLC34075-85
TLC34075-66
PARAMETER

MIN

TYP

TLC34075-85

MAX

MIN

TYP

MAX

UNIT

SCLK frequency (see Note 5)

66

85

MHz

VCLK frequency

66

85

MHz

ten1

Enable time, RD low to D<0:7> valid

40

40

ns

tdis1

Disable time, RD high to D<0:7> disabled

17

17

ns

tv1

Valid time, D<0:7> valid after RD high

tpLH1

Propagation delay, SFLAG/NFLAG
high (see Note 6)

td1

Delay time, RD low to D<0:7> starting to turn
on

td2

Delay time, selected input clock high/low to
DOTCLK (internal Signal) high/low

7

7

ns

td3

Delay time, DOTCLK high/low to VCLK
high/low

6

6

ns

td4

Delay time, VCLK high/low to SCLK high/low

td5

Delay time, DOTCLK high/low to SCLK
high/low

td6

Delay time, DOTCLK high to lOR/lOG/lOB
active (analog output delay time) (see Note 7)

td7

Analog output settling time (see Note 8)

td8

Delay time, DOTCLK high to HSYNCOUT and
VSYNCOUT valid

r to SCLK

tw6

Pulse duration, SCLK high (see Note 6)

tr

Analog output rise time (see Note 9)
Analog output skew

5

5
20

0
5

ns

0

20

5

5

0

ns

0

5

ns

8

8

ns

20

20

ns

8

8

5
15

5
55

15

2
0

ns

ns
55

2
2

0

ns

ns
ns

2

ns

NOTES: 5. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns.
6. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
7. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
8. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
9. Measured between 10% and 90% of the full-scale transition.

9-144

3.6 Switching Characteristics (Cont'd.)
TL34075-110, TLC34075-135
TLC34075-135

TLC34075-110

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

SCLK frequency (see Note 10)

85

85

MHz

VCLK frequency

85

85

MHz

40

40

ns

17

17

ns

ten1

Enable time, RD low to 0<0:7> valid

tdis1

Disable time, RD high to 0<0:7> disabled

tv1

Valid time, 0<0:7> valid after RD high

5

tpLH1

Propagation delay, SFLAG/NFLAG t to SCLK
high (see Note 11)

0

td1

Delay time, RD low to 0<0:7> starting to turn
on

5

td2

Delay time, selected input clock high/low to
DOTCLK (internal signal) high/low

7

7

ns

td3

Delay time, DOTCLK high/low to VCLK
high/low

6

6

ns

td4

Delay time, VCLK high/low to SCLK high/low

td5

Delay time, DOTCLK high/low to SCLK
high/low

td6

Delay time, DOTCLK high to lOR/lOG/lOB
active (analog output delay time) (see Note 12)

td7

Analog output settling time (see Note 13)

td8

Delay time, DOTCLK high to HSYNCOUT and
VSYNCOUT valid

tW6

Pulse duration, SCLK high (see Note 11)

tr

Analog output rise time (see Note 14)
Analog output skew

..

5
20

ns
20

0
5

5

0

ns

0

5

ns

8

8

ns

20

20

ns

6

6

3
15

55

15

2

0

ns
ns

3

2
0

ns

55

ns
ns

2
2

ns

NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns.
11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
12. Measured from the 90% pOint of the rising edge of DOTCLK to 50% of the full-scale transition.
13. Measured from the 50% pOint of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
14. Measured between 10% and 90% of the full-scale transition.

9-145

3.7 Timing Diagrams
tsu1 -l41.r---~~

I

RS <0:3>

I.
I I

.1
I

th1

Xo::..'_~V_al~id_-'ilX,-__________________
--...1II
-

I ~~----- tw1

RD,WR

.1

Y!IiI

---------~'!I'k

-------+:----ll'\.I!

I 14-1.I I

'--....I- t dis1
I
~

/J------

Data Out, RD Low

I

I

I ~ tv1

I+- td1 ---+i
D<0:7>~

(Input)~
,
tsu2

Data In,
~~~~~~
WRLow ~
'I
,
~
~ th2

--io'.t---.t.'

Figure 15. MPU Interface Timing

9-146

\1

I~---------------------'"'!I

~ ten1 ---JoI
I
I

D <0:7>
(Output)

*-- tw2 -+I

I

ClK <0:3>
td2

ffi

:.-.rI

I I I

DOTClK
(Internal Signal)

I
td3

VClK

I

:fi ~

::
Id4 : :

SClK IdS:
Ih3

:

Id3

:1

IN ,
l:

14

i ~ )
,..1
r I

I

~

!4.1

I

td2

X

-~""""T'I- l d - 4 - - - - '

>C

.....- - - - - '

""'r

: :1-.,.:_t_dS_ _ _ _

X. . .____>C

.J

II
I I

II
I I
II

I
I

114~1I1

I

S
Ui_III
V

I

I

VGA<0:7>,
HSYNC, VSYNC, VGABLANK
(VGA Pass-Through Mode)

1\

Data;
Ih4,

ISU4~~

=x:

P <0:31>

Data

Is~:~
HSYNC,VSYNC, BLANK
(Normal Mode)

======X

14

Data
IdS

IOR,IOG,IOB

14 .14

.1

Id7

1j(V11
I
I

_ _ _ _ _ _ _..J..J

1-': I.- tr

=x

HSYNCOUT
VSYNCOUT

Id~

Valid

X Valid x=

Figure 16. Video Input/Output

BLANK

r--

~

~~,--------------~--~/
~1.------tw5------~~1

II~------------~I\
tPlH1-1,.1.--~.r ~ tw6 -+'

SFLAG/
NFLAG ________~/!

I I

SClK __________~y

~

________________

\'-_______________
1

Figure 17. SFLAG/NFLAG Timing (When SSRT Function is Enabled)

9-147

9-148

Appendix A
SCLKNCLK and the TMS340xO
While the TLC34075 SCLK and VCLK outputs are designed for compatibility with all graphics systems, they
are also tightly coupled with the TMS340xO Graphics System Processors. All the timing requirements of the
TMS340xO have been considered. However, there are a few pOints that need to be explained with regard
to applications.

VCLK
All the video control signals in the TMS340xO (i.e., BLANK, HSYNC, and VSYNC) are triggered and
generated from the falling edge of VCLK. The fact that the TLC34075 uses the falling edge to sample and
latch the BLANK input gives users maximum freedom to choose the frequency of VCLK and interconnect
the TLC34075 with the TMS340xO GSP without glue logic. Needless to say, the VCLK frequency needs to
be selected to be compatible with the minimum VCLK period required by the TMS340xO.
In the TMS340xO, the same VCLK falling edge that generates BLANK requests a screen refresh. If the VCLK
period is longer than 16 TOs (TO is the period of the TMS340xO CLKIN), it is possible that the last SCLK
pulse could be used falsely to transfer the VRAM data from memory to the shift register along with the last
pixel transfer. The first SCLK pulse for the next scan line would then shift the first pixel data out of the pipe
and the screen would then falsely start from the second pixel.

SCLK and SFLAG
The TLC34075 SCLK signal is compatible with current -10 and slower VRAMs. When split shift register
transfers are used, one SCLK pulse has to be generated between the regular shift register transfer and the
split ~hift register transfer to ensure correct operation. The SFLAG input is designed forthis purpose. SFLAG
can be generated from a programmable logic array and triggered by the riSing edge of the TR/OE signal or
the riSing edge of the RAS signal of the regular shift register transfer cycle. TR/OE can be used if the
minimum delay from when the VRAM's TRG signal goes high to SCLK going high can be met by the
programmable logic array delay; otherwise, RAS can be used.

9-149

9-150

Appendix B
PC Board Layout Considerations
PC Board Considerations
A four-layer PC board should be used with the TLC34075: one layer each for 5-V power and GND and two
layers for signals. The layout should be optimized for the lowest-possible noise on the TLC34075 power and
ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups
of VDD and GND pins should be minimized so as to reduce inductive ringing. The terminal assignments for
the TLC34075 P<0:31 > inputs were selected for minimum interconnect lengths between these inputs and
the VRAM pixel data outputs. The TLC34075 should be located as close to the output connectors as possible
to minimize noise pickup and reflections due to impedance mismatching.

Ground Plane
A single ground plane is recommended for both the TLC34075 and the rest of the logic. Separate digital and
analog ground planes are not needed.

Power Plane
Split power planes are recommended for the TLC34075 and the rest of the logic. The TLC34075 and its
associated analog circuitry should have their own power plane (referred to as Avec in Figure 18). The two
power planes should be connected at a single point through a ferrite bead as shown in Figures 18, 19, and
20. This bead should be located within three inches of the TLC34075.

Supply Decoupling
Bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation,
to reduce the lead inductance.
For the best performance, a 0.1-flF ceramic capacitor in parallel with a 0.01-flF chip capacitor should be
used to decouple each ofthe three groups of power pins to GND. These capacitors should be placed as close
as possible to the device as shown in Figure 19.
If a switching power supply is used, the designer should pay close attention to reducing power supply noise
and should consider using a three-terminal voltage regulator for supplying power to Avec.

COMP and VREF Terminals
A 1OO-Q resistor and 0.1-flF ceramic capacitor (approximate values) should be connected in series between
the device's COMP and VDD terminals in order to avoid noise and color-smearing problems. Also, whether
an internal or external voltage reference is used, a 0.1-flF capacitor should be connected between the
device's VREF and GND terminals to further stabilize the video image. These resistor and capacitor values
may vary depending on the board layout; experimentation may be required in order to determine optimum
values.

I

t.·

9-151
.Il.·.:

I~

RS
COMP

L1
VDD

IEE::-----=---

VCC

C11

C10

TLC34075
GND f'=-it---__e_--tt---it---...._

GND

FSADJUST
lOR

J----+---+---j----- }

lOG

To Video Connector

IOBJ-------------~e_-----....._ _ _ _ _ _
...a

DESCRIPTION

LOCATION
C1-C3, C9-C10, C12

0.1-~F

ceramic capacitor

C5-C7

0.01-~F

C11

33-~F

L1

ferrite bead

ceramic chip capacitor

tantalum capacitor

R1

1000-0 1% metal-film resistor

R2

523-0 1% metal-film resistor

R3,R4,R5

75-0 1% metal-film resistor

R6

100-0 5% resistor

D1

1.2-V voltage reference

Figure 18. Typical Connection Diagram and Components (Shaded Area is Optional)

9-152

-1
--[£ZJ-- -1
-{Ei}-

$~
o

-l

f-

9

01
RS

~
I~
~

P1

~~
-l
I~I~I ~

0

CS---+

L1

-l

R1

TLC3407S
(84-Pin PLCC)

U1

C11

R2
R3

~

R4

~

RS

~

...0
'1U

... u

041
11)1:
... 1:

~Edge of
the Board

III 0

cO
en

III
C

Figure 19. Typical Component Placement (Component Side)

...........
•

VCC

o.o

••

••••••••••• 00.

()( ).

VCC

C)

•
·.
•

••••• •
••
••
••
••
:••
o.
•• • 0.
cu· ••
AVCC
.0
•
••
•••
••
••
()O
••
••
••
••
•
••
••
• ••
••
••
••••••••••••••
••••••••••••
~\)

Edge of
the Board

VCC

Figure 20. Typical Split Power Plane (Solder Side)

I

9-153

9-154

Appendix C
SCLK Frequency> VCLK Frequency
The VCLK and SCLK outputs generated by the TLC34075 are both free-running clocks. The video control
signals (i.e., HSYNC, VSYNC, and BLANK) are normally generated from VCLK, and a fixed relationship
between the video control signals and VCLK can therefore be expected. The TLC34075 samples and latches
the BLANK input on the falling edge of VCLK. It then looks at the LOAD signal to determine when to disable
or enable SCLK at its output terminal. The decision is deterministic when the SCLKfrequency is greater than
or equal to the VCLK frequency. However, when the SCLK frequency is less than the VCLK frequency, the
appearance of the SCLK waveform at its output terminal when BLANK is sampled low on the VCLK falling
edge can vary (see Figures C-1 and C-2).
To avoid this variation in the SCLK output waveform, the SCLK and VCLK frequencies should be chosen
so that HTOTAL is evenly divisible by the ratio of (VCLK frequency:SCLK frequency); that is,

remainder of [ (

HTOTAL

)

]

:: O.

VCLK frequency
SCLK frequency

For example, if HTOTAL is even, VCLK frequency:: DOTCLK frequency/8, and SCLK frequency::
DOTCLK frequency/16, then the formula above is satisfied. NOTE: When HTOTAL starts at zero (as in the
TMS340xO GSP), then the formula becomes

remainder of [ (

(HTOTAL + 1)
VCLK frequency
SCLK frequency

)

]

:: O.

VCLK

LOAD
(Internal Signal
for Data Latch)
SCLK at
Output Terminal

Figure 21. VCLK and SCLK Phase Relationship (Case 1)

9-155

VCLK

LOAD
(Internal Signal
for Data Latch)

SCLK at
Output Terminal

Figure 22. VCLK and SCLK Phase Relationship (Case 2)

9-156

10-1

Contents
Page
TLC32040 to TM320 Family ............................................ 10-3
TLC34075 to 1280 x 1024 x 8 Display ................................. 10-53

_.

(')
Q)

....
_.
o

:::J

::D

CD

'"C

o

....
"""l:

tn

10-2

Interfacing the TLC32040
Family to the TMS320 Family
Application Report

TEXAS

INSlRUMENlS

10-3

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
. semiconductor products or services might be or are used.
Specifications contained in this User's Guide supersede all data for
these products published by TI in the United States before
March 1988.

Copyright © 1988, Texas Instruments Incorporated

1D-4

Contents
Page

'lection

Introduction

10-7

~.2.3

TLC32040 Interface to the TMS32010/E15
Hardware ..............................................................................
Parts List ...........................................................................
Hardware Description .................................................................
Software ...............................................................................
Initializing the Digital Signal Processor ...................................................
Communicating with the TLC32040 .....................................................
TLC32040 Secondary Communication ...................................................

10-9
10-9
10-9
10-10
10-10
10-10
10-10
10-11

3.1
3.2
3.2.1
3.2.2
3.2.3

TLC32040 Interface to the TMS32020/C25
Hardware Description ....................................................................
Software ...............................................................................
Initializing the TMS32020/C25 .........................................................
Communicating with the TLC32040 .....................................................
Secondary Communications - Special Considerations .......................................

10-13
10-13
10-13
10-14
10-15
10-15

,
t1
t2
tZ.1
tZ.2
tZ.3

TLC32040 Interface to the TMS320C17
Hardware Description ....................................................................
Software ...............................................................................
Initializing the TMS320C17 ............................................................
AIC Communications and TMS320C17 Interrupt Management ................................
Secondary Communications ............................................................

10-17
10-17
10-18
10-18
10-18
10-19

Summary

10-21

~.1

~.1.1

2.1.2
~.2

U.1
~.2.2

~

'\.1
'\.2

a

TLC32040 and TMS32010 Flowcharts and Communication Program ........................... 10-23
Flowcharts ............................................................................. 10-23
Communication Program List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 10-24

3.1
3.2

TLC32040 and TMS32020 Flowcharts and Communication Program ........................... 10-29
Flowcharts ............................................................................. 10-29
Communication Program List .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-32

:::.1
:::.2

TLC32040 and TMS320C17 Flowcharts and Communication Program. . . . . . . . . . . . . . . . . . . . . . . . .. 10-41
Flowcharts ............................................................................. 10-41
Communication Program List .............................................................. 10-44

10-5

10--6

1

Introduction
The TLC32040 and TLC32041 analog interface circuits are designed to provide a high level of system integration and
performance. The analog interface circuits combine high resolution ND and D/A converters, programmable filters,
digital control and timing circuits as well as programmable input amplifiers and multiplexers. Emphasis is placed on
making the interface to digital signal processors (the TMS320 family) and most microprocessors as simple as possible.
This application report describes the software and circuits necessary to interface to numerous members of the TMS320
family. It presents three circuits for interfacing the TLC32040 Analog Interface Circuit to the TMS320 family of digital
signal processors. Details of the hardware and software necessary for these interfaces are provided.
To facilitate the discussion of the software the following definitions and naming conventions are used:
1. >nnnn - a number represented in hexadecimal.

2. Interrupt service routine - a subroutine called in direct response to a processor interrupt.
3. Interrupt subroutine - any routine called by the interrupt service routine.
4. Application program (application routine) - the user's application dependent software (e.g., digital filtering
routines, signal generation routines, etc.)

10-7

10-8

2

TLC32040 Interface to the TMS32010/E15

2.1

Hardware
Because the TLC32040 (Analog Interface Circuit) is a serial-I/O device, the interface to the TMS32010, which has no
serial port, requires a small amount of glue-logic, The circuit shown in Figure 1 accomplishes the serial-to-parallel
conversion for the AlC operating in synchronous mode.

2.1,1

Parts List
The interface circuit for the TMS32010 uses the following standard logic circuits:

1. One SN74LS138 3-to-8-lineaddress decoder
2. One SN74LS02 Quad NOR-Gate
3. One SN74LSOO Quad NAND-Gate
4. One SN74LS04 Hex Inverter
5. One SN74LS74 Dual D-Flip-Flop
6. Two SN74LS299 8-bit Shift Registers
7415299

TLC32040

TM532010/C15
~

DEN

51

F5X

G2

OX

OH'

7415138
' - - G1

YO

YT

-

U2
50
G1

~

h

••
•

U1
AO/PAO

A

A1/PA1

B

A2/PA2

C

5R

r---

-

,~

a

5HIFT
ClK

......

7415299

DO

WE
ClKOUT

-

8
51
G2
50

---4

/

/

OH'

G1

./

U3

16

016

••
•

~

V

/

h

8

••
•a

./

~ -

-::ll4 "'

----I

-

SR

..J-

D~ DR

0
U4

741574

l5"'

1--'

INT

M5TRCLK
EODX

Figure 1. AIC Interface to TMS32010/E15
10-9

2.1.2

Hardware Description
The SN74LS138 is used to decode the addresses of the ports to which the TLC32040 and the interface logic have been
mapped. If no other ports are needed in the development system, this device may be eliminated and the address lines of
the TMS32010 used directly in place of Y1 and YO (see Figure 1).
Since the interface circuits are only addressed when the TMS32010 executes an IN or an OUT instruction, gates Ll, L2,
L3, L4, and L5 are required to enable reading and writing to the shift registers only on these instructions. The TBLW
instruction is prohibited because it has the same timing as the OUT instruction. Flip-flop U4 ensures that the setup and
hold times of SN74LS299 shift registers are met.
Although not shown in the circuit diagram, it is recommended that the CLR pins of the SN74LS299 shift registers as
well as the RESET pin of the AIC be tied to the power-up reset circuit shown in the AIC data sheet. This ensures that
the registers are clear when the AIC begins to transfer data and decrease the possibility that the AIC will shift in bad data
which could cause the AIC to shut down or behave in an unexpected manner.

2.2

Software
The flowcharts for the communication program along with the TMS32010 program listing are presented in Appendix A.
If this software is to be used, and application program that moves data into and out of the transmit and receive registers
must be supplied.

2.2.1

Initializing the TMS320010/E15
As shown in the flowcharts in Appendix A, the program begins with an initialization routine which clears both the
transmit/receive-end flag and the secondary communication flag, and stores the addresses of the interrupt subroutines.
The program uses the MPYK .. PAC instruction sequence to load data memory locations with the 12-bit address of the
subroutines. This sequence is only necessary if the subroutines are to reside in program memory locations larger than
> OOFF. Otherwise, the instructions LACK and SACL may be used to initialize the subroutine-address storage locations.

2.2.2

Communicating with the TLC32040
After the storage registers and status register have been initialized, the interrupt is enabled and control is passed to the
user's application routine (I.e., the system-dependent software that processes received data and prepares data for
transmission). The program ignores the first interrupt that occurs after interrupts are enabled (page 10-28, line 207,
IOINT routine), allowing the AIC to stabilize after a reset. The application routine should not write to the shift registers
while data is moving into (and out of) them. In addition, it should ensure that no primary data is written to the shift
registers between a primary and secondary data-communication pair. The first objecive can be accomplished by writing
to the SN74LS299 shift registers as quickly as possible after the receive interrupt. The number of instruction cycles
between the data transfers can be calculated from the conversion frequency. By counting instruction cycles in the
application program, it is possible to determine whether the data transfer will conflict with the OUT instruction to the
shift register. The second objective can be accomplished by monitoring SNDFLG in the application program. If
SNDFLG is true (>OOFF), secondary communication has not been completed.
When the processosr receives an interrupt, the program counter is pushed onto the hardware stack and then the program
counter is set to > 0002, the location of the interrupt service routine, INTSVC (page 10-25, line 46). The interrupt service
routine then saves the contents of the accumulator and the status register and calls the interrupt subroutine to which
XVECT points. If secondary communication is to follow the upcoming primary communication, XVECT, is set by the
application program to refer to SINTl, otherwise, XVECT defaults to NINT (I.e., the normal interrupt routine).

10-10

Because the interrupt subroutine makes one subroutine call and uses two levels of the hardware stack, the application
program can only use two levels of nesting (i.e., if stack extension is not used). This means that any subroutine called
by the application program can only call subroutines containing no instructions that use the hardware stack (e.g., TBLW)
and that make no other subroutine calls. In addition, if the application program and communication program are being
implemented on an XDS series emulator, the emulator consumes one level of the hardware stack and allows the
application program only one level of nesting (i.e., one level of subroutine calls).
As shown in the flowcharts in Appendix A, the normal interrupt routine reads the AID data from the shift registers and
then sets the receive/transmit end-flag (RXEFLG). The application program must write the outgoing D/A da:ta word to
the shift registers at a time convenient to the application routine. It should have the restriction that the data be written
before the next data transfer.

2.2.3

TLC32040 Secondary Communication
If it is necessary to write to the control register of the AIC or configure any of the AIC internal counters, the application
program must initiate a primary/secondary communication pair. This can be accomplished by placing a data word in
which bits a and 1 are both high into DXMT, placing the secondary control word (see program listing page 10-25) in
D2ND, and placing the address of the secondary communication subroutine, SINTl, in XVECT. When the next interrupt
occurs, the interrupt subroutine will call routine SINTl. SINTl reads the ND information from the shift registers and
writes the secondary communication word to the shift registers.

10-11

10-12

3

TLC32040 Interface to the TMS32020

3.1

Hardware Description
Because the TLC32040 is designed specifically to interface with the serial port of the TMS32020/C25, the interface
requires no external hardware. Except for CLKR and CLKX, there is a one-to-one correspondence between the serial
port control and data pins ofTMS32020 and TLC32040. CLKR and CLKX are tied together since both the transmit and
the receive operations are synchronized with SHIFT CLK of the TLC32040. The interface circuit, along with the
communication program (page 10-33), allows the AIC to communicate with the TMS32020/C25 in both synchronous
and asynchronous modes. See Figures 2, 3, and 4.

3.2

Software
The program listed in Appendix B allows the AIC to communicate with the TMS32020 in synchronous or asynchronous
mode. Although originally written for the TMS32020, it will work just as well for the TMS320C25.

TLC32040

TMS32020/C25
5V

L

WORD/BYTE
MSTR CLK

CLKOUT

FSX

FSX
OX

OX

FSR

FSR

DR

DR

CLKX
CLKR

---1

SHIFT CLK

Figure 2. AIC Interface to TMS32020/C25

10-13

SHIFT elK

I
I

\

I

I

~--~I----+I--~I~--~II~--------------

oR _____o_1_5____

~~1~--0--1----0-0---------------------I

ox -----(

EOOR. EOOX

,

015

------------------------~II~------------~

L....J~----------

The sequence of operation is:
1. The FSX or FSR pin is brought low.
2. One 16-bit w.ord is transmitted or one 16-bit byte is received.
3. The FSX or FSR pin is brought high.
4. The EODX or EO DR pin emits a low-going pulse as shown.

Figure 3. Operating Sequence for AIC-TMC32020/C25 Interface

Figure 4. Asynchronous Communication AIC-TMS32020/C25 Interface
3.2.1

Initializing the TMS32020/C25
This program starts by calling the initialization routine. The working storage registers for the communication program
and the transmit and receive registers of the DSP are cleared, and the status registers and interrupt mask register of the
TMS32020/C25 are set (see program flow charts in Appendix B). The addresses of the transmit and receive interrupt
subroutines are placed in their storage locations, and the addresses of the routines which ignore the first transmit and
receive interrupts are placed in the transmit and receive subroutine pointers (XVECT and RVECT). The TMS32020/C25
serial port is configured to allow transmission of 16~bit data words (FO), the serial port format bit of the TMS32020/C25
must be set to zero) with an externally generated frame synchronization (FSX and FXR arae inputs, TXM bit is set
to 0).

10-14

3.2.2

Communicating with the TLC32040
After the TMS32020/C25 has been initialized, interrupts are enabled and the program calls subroutine IGR. The
processor is instructed to wait for the first transmit and receive interrupts (XINT and RINT) and ignore them. After the
TMS32020 has received both a receive and a transmit interrupt, the IGR routine will transfer control back to the main
program and IGR will not be called again.
If the transmit interrupt is enabled, the processor branches to location 28 in program memory at the end of a serial
transmission. This is the location of the transmit interrupt service routine. The program context is saved by storing the
status registers and the contents of the accumulator. Then the interrupt service routine calls the interrupt subroutine whose
address is stored in the transmit interrupt pointer (XVECT).

A similar procedure occurs on completion of a serial receive; If the receive interrupt is enabled, the processor branches
to location 26 in program memory. As with the transmit interrupt service routine (XI NT, page 10--36, line 226), the
receive interrupt service routine (page 10--36, line 194) saves context and then calls the interrupt subroutine whose
address is stored in the receive interrupt pointer (RVECT). It is important that during the execution of either the receive
or transmit interrupt service routines, all interrupts are disabled and must be re-enabled when the interrupt service routine
ends.
The main program is the application program. Procedures such as digital filtering, tone-generation and detection, and
secondary communication judgment can be placed in the application program. In the program listing shown in
Appendix B, a subroutine (C2ND) is provided which will prepare for secondary communication. If secondary
communication is required, the user must first write the data with the secondary code to the DXMT register. This data
word should have the two least significant bits set high (e.g., >0003). The first 14 bits transmitted will go to the D/A
converter and the last two bits indicate to the AIC that secondary communication will follow. After writing to the SXMT
register, the secondary communication word should be written to the D2ND register.
This data may be used to program the AIC internal counters or to reconfigure the AlC (e.g., to change from synchronous
to asynchronous mode or to bypass the bandpass filter). After both data words are stored in their respective registers,
the application program can then call the subroutine C2ND which will prepare the TMS32020 to transmit the secondary
communication word immediately after primary communication.

3.2.3

Secondary Communicating - Special Considerations
This communication program disables the receive interrupt (RINT) when secondary communication is requested.
Because of the critical timing between the primary and secondary communication words and because RINT carries a
higher priority than the transmit interrupt, the receive interrupt cannot be allowed to interrupt the processor before the
secondary data word can be written to the data-transmit register. If this situation were to occur, the AIC would not receive
the correct secondary control word and the AIC could be shut down.
In many applications, the AIC internal registers need only be set at the beginning of operation, (i.e., just after
initialization). Thereafter, the DSP only communicates with the AIC using primary Communication. In cases such as
these, the communication program can be greatly simplified.

10-15

10-16

4

Interfacing the TMS32040 to the TMS320C17

4.1

Hardware Description
As shown in Figure 5, the TMS320C17 interfaces directly with the TLC32040. However, because the TMSs320C17
responds more slowly to interrupts than the TMS32010!E15 or the TMS32020/C25, additional circuit connections are
necessary to ensure that the TMS320C17 can respond to the interrupt, accomplish the context-switching that is required
when an interrupt is serviced, and proceed with the interrupt vector. This must all be accomplished within the strict timing
requirements imposed by the TLC32040. To meet these requirements, FSX of the TLC32040 is connected to the EXINT
pin of the TMS320C17. This allows the TMS320C17 to recognize the transmit interrupt before the transmission is
complete. This allows the interrupt service routine to complete its context-switching while the data is being transferred.
The interrupt service routine branches to the interrupt subroutines only after the FSX flag bit has been set. This signals
the end of data transmission.
The other hardware modification involves connecting the EODX pin of the TLC32040 to the BIO pin of the
TMS320C17. Because the TMS320C17 serial port accepts data in 8-bit bytes (see Figure 6) and the TLC32040 controls
the byte sequence (i.e., which byte is transmitted first, the high-order byte or the low-order byte) it is important that the
TMS320C17 be able to distinguish between the two transmitted bytes. The EODX signal is asserted only once during
each transmission pair, making it useful for marking the end of a transmission pair and synchronizing the TMS320C17
with the AIC byte sequence. After synchronism has been established, the BIO line is no longer needed by the interface
program and may be used elsewhere.
Because he TMS320C17 serial port operates only in byte mode, 16-bit transmit data should be separated into two 8-bit
bytes and stored in separate registers before a transmit interrupt is acknowledged. Alternatively, the data can be prepared
inside the interrupt service routine before the interrupt subroutine is called. From the time that the interrupt is recognized
to the end of the data transmission is equivalent to 28 TMS320C17 instruction cycles.
TMS320C17

EXINT
FSX
CLK OUT
DXO
FSR
ORO
SCLK

TLC32040

n

*"

WORD/BYTE
FSX
MSTR CLK
OX
FSR
DR
SHIFT eLK

Figure 5. AIC Interface to TMS320C17

10-17

SHIFT elK
I
I

FSX. FSR - - - ,

,

0~5

DR

,

,

I
I·

I

\,....-~I-.."I....-----....I

~~________0~8~_________~~~0~'__~0~O__-

OX~
EOOR.EOOX

I

II

I
I

08

_____

107'06~

--------------11'~------~\L______________________"j'~--------~I

The sequence of operation is:
1. The FSX or FSR pin is brought low.
2. One 8-bit word is transmitted or one 8-bit byte is received.
3. The EOOX or EOOR pins are brought low.
4. The FSX or FSR emit a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The EO OX and EOOR pins are brought high.
7. The FSX and FSR pins are brought high

Figure 6. Operating Sequence for AIC·TMS320C17

4.2

Software
The software listed in Appendix C only allows the AIC to communicaet with the TMS320C17 in synchronous mode.
This communication program is supplied with an application routine, DLB (Appendix C, program listing line 253),
which returns the most recently received data word back to the AIC (digitalloopback).

4.2.1

Initializing the TMS320C17
The program begins with an initialization routine (INIT, page 10-45, line 120). Interrupts are disabled and all the working
storage registers used by the communication program are cleared. Both transmit registers are cleared, the constants used
by the program are initialized and the addresses of the subroutines called by the program are placed in data memory. This
enables the interrupt service routine to call subroutines located in program-memory addresses higher than 255. After the
initialization is complete, the TMS320C17 monitors the FSX interrupt flag in the control register to establish
synchronization with the Ale.

4.2.2

AIC Communications and Interrupt Management
Because the AIC FSX pin is tied to the EXINT line of the TMS320C17 and the delay through the interrupt multiplexer,
the interrupt service routine is called four instruction cycles after the falling edge ofFSX. The interrupt service routine
(INTSVC, Appendix C, program listing, line 90) completes its context switching and then monitors the lower control
register, polling the FSX flag bit that indicates the end of the 8-bit serial data transfer. If the FSX flag bit is set, the transfer
is complete. After this bit is set, control is transferred to the interrupt subroutine whose address is stored in VECT. The
serial communication must be complete before data is read from the data receive register.
When no secondary communication is to follow, the interrupt subroutines, NINT1 and NINT2, are called. If data has
ben stored in DXMT2 (the low-order eight bits of the transmit data word), which does not indicate that secondary
communication is to follow, the interrupt service routine calls NINT1 when the first 8-bit serial transfer is complete.
NINTl immediately writes the second byte of transmit data, (Le., the contents of DXMTI) to transmit data register 0
(TRO). It then moves the first byte of the received data (i.e., the high-order byte of the ND conversion result) into
DRCVl. NINTl then stores in VECT the address of NINT2. NINT2 is called at the end of the next 8-bit data transfer
and resets the FSX interrupt flag bit by writing a logic high to it. The next interrupt (a falling edge of EXINT) occurs
before the interrupt service routine returns control to the main program. THis is an acceptable situation since the
TMS320C17, on leaving the interrupt service routine, recognizes that an interrupt has occurred and immediately
responds by servicing the interrupt.

10-18

The interrupt subroutine NINT2 is similar in operation to NINTl. It stores the low-order byte of receive data (bits 7
through 0 of the AID conversion result) and stores the address of the next interrupt subroutine in VECT. NINT2 does
not write to the transmit data register, TRO. This task has been left to the application program. After the transmit data
has been prepared by the main program and the data has been stored in DXMTI and DXMT2, the main program stores
the first byte of the transmit data in transmit data register 0 (TRO).

4.2.3

Secondary Communications
The interrupt subroutines SINTI through SINT4 are called when secondary communication is required. For secondary
communication, DXMTl and DXMT2 will hold the primary communication word. DXMT3 and DXMT4 will hold the
secondary communication word. VECT, the subroutine pointer should then be initialized to the address of SINTl. As
with the normal (primary communication only) interrupt subroutines (Le., NINTl and NINT2), the secondary
communication routines will change VECT to point to the succeeding routine (e.g., SINTl will point to SINT2, SINT2
will point to SINT3, etc.).

10-19

10-20

5

Summary
The TLC32040 is an excellent choice for many digital signal processing applications such as speech recognition/storage
systems and industrial process control. The different serial modes ofthe AIC (synchronous, asynchronous, 8- and 16-bit)
allow it to interface easily with all of the serial port members of the TMS320 family as well as other processors.

10-21

10-22

A

A.l

TLC32040 and TMS32010 Flowcharts and
Communication Program
Flowcharts

"" "Modified to call NINT.
a. MAIN

b. PRIMARY INTERRUPT ROUTINE

10---23

***

'Set, if need secondary.
"Modify to call SINT2.
"'Modify to call NINT.
'" 'Must execute before transfer beginning.

c. SECONDARY DATA COMMUNICATIONS 1

A.2

Communication Program List

0001
0002
0003
0004
0005
0006
0007
0008
0009
0002
0010
0011
0003
0012
0004
0013
0005
0006
0014
0007
0015
0016
0008
0009
0017
0018
OOOA
0019
OOOC
OOOD
0020
0021
OOOE
0022
OOOF
0023
OOFF
0024
0001
0025
0026
0027
0028
0029 0000
0030 0000 F900
0001 0000
10-24

d. SECONDARY DATA COMMUNICATION 2

************************************************************

*
*
*
*
*
*

When using this program, the circuit in the TlC32040
data sheet or its equivalent circuit must be used.
TMS32010 port 0 and port 1 are reserved for data
receiving and data transmitting. The TBlW command is
prohibited because it has the same timing as the OUT
command. TlC32040 is used only in synchronous mode.

*

*
*
*

*
*

************************************************************
*
RXEFLG

SNDFlG

DRCV
DXMT
D2ND
XVECT
ACHSTK
AClSTK
SSTSTK
ANINT
ASINTl
ASINT2
TMPO

*

SET
ONE

*

*
*

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

>02

>04
>05
>06
>07
>08
>09
>OA
>OC
>OD
>OE
>OF

EQU
EQU

>FF
>01

>03

receive & xmit end flag.
secondary communication flag.
receive data storage.
data storage.
xmit
secondary data storage.
interrupt address storage.
ACCH stack.
ACCl stack.
Status stack.
interrupt address 1
interrupt address 2
interrupt address 3
temporary register.

=================
Reset vector.
=================
AoRG
B

>0000
EPIL

program start address.
jump to Initialization.

0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084

***********************************************************
==================
*
Interrupt vector.

==================
When secondary communication, modify the content
of XVECT to the address of secondary communication
and store secondry data in D2ND.
ex.
LAC
ASINTl,O modify XVECT.
SACL XVECT,O

**

LAC

D2ND,0

*
*
*
*
*

**

store secondary data.

**************************************************~~***~*~~

0002
0002
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC

7COA
6EOl
5808
5009
2007
7F8C
6508
7A09
7BOA
7F82
7F8D

INTSVC

AORG

>0002

interrupt vector.

SST
LDPK
SACH
SACL
LAC
CALA
ZALH
OR
LST
EINT
RET

SSTSTK
ONE
ACHSTK
ACLSTK
XVECT,O

push status register.
set data pointer one.
push ACCH.
push ACCL.
load interrupt address.
branch to interrupt routine.
pop ACCH
pop ACCL.
pop stack register.
enable interrupt.
return from interrupt routine.

ACHSTK
ACLSTK
SSTSTK

~~~***************************************************

*
*

=============================
Initialization after reset.

*
*

=============================

*
*
*
*

Data RAM locations 82H(130) through 8FH(143),
12 words of Page 1, are reserved for this
program. The user must set the status register
by adding the SST command at the end of the
the initialization routine.

*

*
*
*

***************************************~~*************

OOOD
0000
OOOD
OOOE
OOOE
OOOF
0010
0011
0012
0013
0014
0014
0015
0016

*
*
*

AORG

$

initial program.

LDPK

ONE

set Data page pointer one.

7EOl
500F
6AOF
802C
7F8E
500C

LACK
SACL
LT
MPYK
PAC
SACL

ONE
TMPO
TMPO
NINT

save normal communication address
to its storage.

8030
7F8E
5000

MPYK
PAC
SACL

SINTl

6EOl

EPIL

ANINT
save secondary communication addressl
to its storage.

ASINTl
10-25

0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117

0017
0017
0018
0019
OOlA
OOlA
OOlB
001C
OOlD
001D
OOlE
OOlF
OOlF
0020
0020
0020
0020

8037
7F8E
500E

MPYK
PAC
SACL

803E
7F8E
5007

MPYK
PAC
SACL

XVECT

7F89
5002

ZAC
SACL

RXEFlG,O

5003

SACL

SNDFlG,O

7F82

Oil8
0119
0120
0121 0021
0122 0021 2002
0123 0022 FFOO
0023 0021
0124 0024
0125 0024 2003
0126 0025- FEOO
0026 0028
0127 0027
0128 ,0027 4905
0129 0028
0130 0028 7F89
0131 0029 5002
0132 002A
0133 002A F900
002B 0021

10-26

SINT2

save secondary communication address2
to its storage.

ASINT2
IGINT

ignore interrupt once after master
reset.

clear flags.

EINT

enable interrupt.

l(
l(l(l(l(l(l(**l(*l(****************l(********************************

*

====================

*

Main program.

====================

** This program allows the user two levels of nesting
* since one level is used as stack for the interrupt.
* When the RXEFLG flag is false then no data transfer has
* occurred, if it is true then data transfer has finished.
* User routines such as digital filter, secondary-data* communication judgement etc. must be placed in this
* location. Depending on the sampling rate (conversion
* rate), these user routines must write the xmit data to
* the shift registers within approximately 500 instruction
* cycles. If the user requires secondary communication, it
* will be necessary to delay the OUT instruction until the
* secondary data transfer has finished.

*

*
**

*
*
*
*
**
*
*
*
*
*

***************~********************************************

MAIN

LAC
BZ

LAC

MAINI

RXEFLG,O wait for interrupt.
MAIN

BNZ

SNDFLG,O skip OUT instruction during secondary
MAINI
communication.

OUT

DXMT,PAI write xmit data to shift register.

ZAC
SACL

RXEFlG

B

MAIN

clear flags.

loop.

0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187

**********************************************************

*

*

============================
Normal interrupt routine.

============================
destroy ACC,DP.
Write the contents of DXMT to the 'LS299s, receive
DAC data in DRCV, and set RXEFLG flag.

*

*
002C
002C
002D
002D
002E
002F
002F

4004

NINT

IN

DRCV,PAO Receive data from shift register.

7EFF
5002

LACK
SACL

SET
RXEFlG

7F8D

RET

*
*
*
*
*
**
*
*

set receive and xmit ended flag.

return.

**********************************************************

0030
0030 4004
0031
0031 4906
0032
0033
0034
0034
0035
0036
0036
0037

===============================================
Secondary communication interrupt routine 1.
===============================================
destroy ACC, DP

Write the contents of D2ND to the 'LS299s, receive
data in DRCV, and modify XVECT for secondary communi
-cation interrupt.

*

**********************************************************
IN

DRCV,PAO receive data from shift register.

OUT
LAC
SACL

D2ND,PAl write secondary data to shift
register.
ASINT2,0 modify interrupt location.
XVECT
secondary communication 2

7EFF
5003

LACK
SACL

SET
set secondary communication flag.
SNDFlG,O

7F8D

RET

200E
5007

*
*
*
*
**
*

SINTl

*

return.

**********************************************************

*

===============================================

*

Secondary communication interrupt routine 2.

*

===============================================
destroy ACC,DP

*

*
*
0037
0037 200C
0038 5007
0039

Modify XVECT for normal communication, and set
flag.

*
*
*
RXEFLG*

**********************************************************
SINT2

LAC
SACL

ANINT
XVECT

modify interrupt location
normal communication.

10-27

0188 0039 7EFF
LACK SET
set receive and xmit ended flag.
0189 003A 5002
SACL RXEFLG
0190 003B
0191 003B 7F89
ZAC
Clear secondary communication flag.
SACL SNDFLG,O
0192 003C 5003
0193 003D
0194 003D 7F8D
return.
RET
0195 003E
0196
***********************************************************
0197
*
==========================================
Ignoring the first interrupt after reset.
0198
==========================================
0199
0200
destroy ACC,DP.
0201
0202
Ignore the first interrupt after reset. the TLC32040
0203
receives zero as DAC data but no ADC data in DRCV.
0204
0205
0206 003E
0207 003E 200C IGINT
LAC
modify interrupt location
ANINT
SACL XVECT
normal communication.
0208 003F 5007
0209 0040
0210 0040 7F8D
return.
RET
0211 0041
0212
END
NO ERRORS, NO WARNINGS

*

**
*
*

1(}-28

**
*
*

B

B.1

TLC32040 and TMS32020 Flowcharts and
Communication Program
Flowcharts

PUSH ACC, STO

SET STO STATUS REGISTER

~------~------~
~------~------~
~--------~--------~

2
3
4
5
6

-

2

3

LOAD RINT VECTOR ADDRESS

~------~------~

6

4

Alterable AR pointer and OVM.
Alterable CNF, SXM and XF.
Must clear at least 108 through 127, 19 of internal RAM.
If IMR is changed by user program, INST must be changed.
Their contents will be changed by their routine locations.
IGNRR is executed only once after reset.

a. INITIALIZATION

b. RECEIVE INTERRUPT SERVICE ROUTINE

c. RECEIVE SUBROUTINE

d. IGNORE INTERRUPT

10-29

LOAD XINT VECTOR ADDRESS

CALL NRM, 51, 52, IGNRX

7

7 - IGNRX is executed only once after reset.

e. TRANSMIT INTERRUPT SERVICE ROUTINE

8

f. PRIMARY TRANSMISSION ROUTINE

MODIFY IMR INTERRUPT MASKING REGISTER

8 - Modify to 52 address.
9 - Modify to NRM address.

g. PRIMARY-SECONDARY COMMUNICATIONS 1

10-30

h. PRIMARY-SECONDARY COMMUNICATIONS 2

9

NO

~--------~--------~

10

11

10 - Modify to NRM address.
11 - MOdify to S 1 address.

i. IGNORE TRANSMIT INTERRUPT

j. SECONDARY COMMUNICATION JUDGMENT

NO

NO

k. IGNORE FIRST INTERRUPTS

10-31

8.2

Communication Program List

0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
10-32

•••••••••••••••••••••••••••••••••••••••••••••••••••• *****.**
•
TlC32040 & TMS32020 communication program.

============================================

*

*

*

============================================
by H.Okubo & W.Rowand
version 1.1
7/22/88.
•
•
•
•
•
•
•
•
•

•

This is a TMS32020 - TlC32040 communication program
that can be used in many systems. To use this program,
the TMS32020 and the TlC32040 (AIC) must be connected
as shown in the publication: linear and Interface Circuit Applications, Volume 3. The program reserves
TMS32020 internal data memory 108 through 127 (B2) as
flags and storage. When secondary communication is
needed, every maskable interrupt except XINT is disabled until that communication finishes.

• If you have any questions, please let us know.

*
•
•
•
•
•
•
•
•

•*

•••••••••••••••••••••••••••••••••••••••••••••••••*** ••• *****

••* ==========================
•

Memory mapped register.

• ==========================

0000
0001
0004

•DRR

EQU
EQU
EQU

DXR
IMR

0
1
4

*

data receive register address.
• data xmit
register address.
• interrupt mask register address.

•

• ============================================
•
•

Reserved onchip RAM as flags and storages.
(block B2 108 through 127.)

• ============================================

006C
006D
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F

•FXE

FRE
TMPO
ACCHST
ACClST
SSTST
INTST
RVECT
XVECT
VRCV
VNRM
VSI
VS2
DRCV
DXMT
D2ND
FRCV
FXMT
F2ND

*

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQl:I
EQU
EQU
EQU
EQU

108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

• ignore first XINT flag.
ignore first RINT flag.
• temporary register.
• stack for ACCH.
• stack for ACCl.
• stack for STO register.
• stack for IMR register.
• vector for RINT.
• vector for XINT.
• RINT vector storage.
• XINT vector storage.
• secondary vector storagel.
• secondary vector storage2.
• receive data storage.
• xmit data storage.
• secondary data storage.
• receive flag.
xmit flag.
• secondary communication flag.

*

*

0055
0056
0057
0058 0000
0059 0000 FF80
0001 0020
0060
0061
0062
0063
0064
0065 OOlA
0066 OOlA FF80
OOlB 004A
0067
0068
0069
0070
0071
0072 OOlC
0073 OOlC FF80
OOlD 005A
0074
0075
0076 0020
0077
0078
0079
0080
0081
0082
0083 0020 FE80
0021 0025
0084 0022 CEOO
0085 0023 FE80
0024 008D
0086

************************************************************

*

*

Processor starts at this address after reset.
AORG 0
B STRT

*
*

program start address.
jump to Initialization routine.

*

*

************************************************************

*

************************************************************
Receive interrupt location.
AORG 26
B RINT

*

*

Rint vector.
jump to receive interrupt routine.

*
**

*

************************************************************

*

************************************************************
Transmit interrupt location.
AORG 28
B XINT

*
*

Xint vector.
jump to xmit interrupt routine.

*

*
*
*

************************************************************

*

AORG 32

*

start initial program.

*
* User must initialize DSP with the routine INIT. The
*
* user may modify this routine to suit his system require- *
* ments as he likes.
*
************************************************************
STRT
CALL INIT
*
************************************************************

EINT
CALL IGR

*

enable interrupt.

10-33

0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124 0025 C800
0125 0026 DOOI
0027 OEOO
0126 0028 606F
0127 0029 506F
0128
0129
0130
0131
0132
0133
0134
0135 002A DOOI
002B 03FO
0136 002C 606F
0137 002D 516F
0138 002E
10-34

************************************************************

*
==============
*
User area
==============
*
** This program allows the user two levels of nesting,
* since two levels are used as stack for the interrupt.
* When the FXMT flag is false no data transmit has oc* curred. When the FRCV flag is false, no data has been
* received. As those flags are not reset by any routine in
* this program, the user must reset the flags if he
* chooses to use them and note that >OOff means true,
* >0000 means false. User routines such as digital
* filtering, FFTs etc. must be placed in this location.
* Depending on the sampling rate (conversion rate), these
* user routines must write the xmit data to the DXMT
* registers within approximately 500 instruction cycles.
* If the user requires secondary communication, data
* with the secondary code (xxxx xxxx xxxx xxII) should
* first be written to DXMT and then secondary data should
* be written to D2ND. Next, a call should be made to C2ND
* to set up XVECT and the F2ND flag to perform the sec on* dary communication. Note that all maskable interrupts
* except XINT are disabled until secondary communication
* has completed.

*
*
*
**
*

*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

************************************************************

*
========================
*
Initialization routine.
**
========================
* This routine initializes the status registers, flags,
* vector storage contents and internal data locations
* 96 through 107. Note that the User can modify these
* registers (i.e. STO STI IMR), as long as the contents do
* not conflict with the operation of the AIC.

************************************************************

*
**
*
*
*
*
*

************************************************************
LDPK 0
INIT
* set statusO register.
LALK >OEOO,O
* 0000 1110 0000 OOOOB
SACL TMPO,O
LST TMPO

*
*
*
*
*
*
*

*
*
*
*
*
*

ARP=O AR pointer 0
OV =0 (Overflow reg. clear)
OVM=l (Overflow mode set to
=1 Not affected.
!
INTM=l Not affected
DP 000000000 page 0
set statusl register.

APB=O
CNF=O (Set BO data memory)

LALK

>03FO

*
*
*

SACL
LSTl

TMPO,O
TMPO

*
*

0000 0011 1111 OOOOB

1)

0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165

J£ TC =0
* SXM=l (enable sign extend mode.)
J£ D9-D5=111111 not affected.
* XF=1 (XF pin status.)
J£ FO=O (16bit data transfer mode. )
J£ TXM=O (FSX input)

J£
J£

*
*
J£
J£

*
J£

J£
J£

002E
002F
0030
0031
0032
0033

ZAC
SACl
SACl
lARK
RPTK
SACl

CAOO
6001
6000
C060
CBlF
60AO

DXR,O
DRR,O
ARO,96
31
*+,0

* clear registers
*
*
J£ clear Block B2.
*
J£

J£
J£

Interrupt masking

*
0034 CA30
0035 6004
0036 6073

0037 D001
0038 0067
0166 0039 6077
0167
0168 003A D001
003B 006C
0169 003C 6078
0170
0171 003D D001
003E 0071
0172 003F 6079
0173
0174 0040 D001
0041 0055
0175 0042 6076
0176
0177 0043 D001
0044 0094
0178 0045 6074
0179
0180 0046 D001
0047 0099
0181 0048 6075
0182 0049 CE26
0183 004A

lACK
SACl
SACl

>30
IMR,O
INTST,O

* 0000 0000 0011 OOOOB
I I
I I I I
* XINT
I I
I I I I
I I I I
J£ RINT
I I I I
I I I I
* TINT
I I I I
I I I
* INT2
I I I
I I
I I
* INTI
J£ INTO

lAlK

NRM,O

* normal xint routine address.

SACl

VNRM,O

J£

lAlK

Sl,O

J£

SACl

VS1,0

3(

lAlK

S2,0

* secondary xint routine address 2.

SACl

VS2,0

*

lAlK

RCV,O

* rint routine address.

SACl

VRCV,O

lAlK

IGNRR,O

SACl

RVECT,O

lAlK

IGNRX,O

SACl
RET

XVECT,O

*
J£

*
J£
J£

*

*

secondary xint routine address 1.

J£

J£

* set ignore first rint address.

J£

* set ignore first xint address.

* return.

10-35

0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
10-36

*
*

************************************************************

=================================

*

Receive interrupt routine.

=================================

* This routine stores receive data in its storage
* DRCV (112 pageO) and sets the receive flag FRCV (125
* pageO). As two levels of nesting are used, this routine
* allows the user two levels, without stack extension.
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054

7872
C800
6071
6870
2074
CE24
4171
4870
5072
CEOO
CE26

0055
0056
0057
0058
0059

2000
607A
CAFF
607D
CE26

*

*
*
*
*
*

************************************************************
RINT
SST SSTST
* push STO register.
LDPK 0
SACL ACCLST,O
SACH ACCHST,O
LAC RVECT,O
CALA
ZALS ACCLST
ADDH ACCHST
LST SSTST
EINT

RCV

*
*
*
*
*

data
push
push
load

pointer page O.
ACCL.
ACCH.
ACC vector address.

pop ACC

*

RET

*
*

pop ST register.
enable interrupts.
return.

LAC DRR,O
SACL DRCV,O
LACK >FF
SACL FRCV
RET

* save it to its storage.
* set receive flag.
** return.

*

load data from DRR.

************************************************************
*
===================================
*
*
Xmi t interrupt routine.
*

*
*
*
*
*

OOSA
OOSB
OOSC
OOSD
OOSE
OOSF
0060
0061
0062
0063
0064
0065
0066

7872
C800
6071
6870
207C
6001
2075
CE24
4171
4870
5072
CEOO
CE26

===================================

This routine writes xmit data (the contents of DXMT
(123 pageO» to the DXR register according to the type
of communication, i.e. normal communication or secondary
communication. For normal communication, call the normal
communication routine (NRM). For secondary, call the
secondary communication routines (51 and 52). Because
these routines use two levels of nesting, the user is
allowed two levels of nesting if stack extension is not
used.

*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
************************************************************
XINT

SST SSTST
LDPK 0
SACL ACCLST,O
SACH ACCHST,O
LAC D2ND,O
SACL DXR,O
LAC XVECT,O
CALA
ZALS ACCLST
ADDH ACCHST
LST SSTST
EINT
RET

*
*
*
*
*

*
*
*

*

push ST register.
data pointer page O.
push ACCL.
push ACCH.
preload dxr with secondary
communication data.
load vector address.
call xmit routine.
pop ACC

* pop ST register.
* enable interrupt.
* return.

0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288

************************************************************

*
*
*
*

*

===================================
Normal data write routine.

*
*

===================================
This routine is called when normal communication occurs.*
This routine writes xmit data to DXR, and sets the trans-*
mit flag (126 pageO)'

*

************************************************************
0067
0068
0069
006A
006B

207B
6001
CAFF
607E
CE26

*NRM

LAC DXMT,O
SACL DXR,O
LACK >FF
SACL FXMT
RET

* write DXR data.

*

set flag.

* return.

************************************************************

*
*
*
*
*
*
*
006C
006D
006E
006F
0070

207C
6001
2079
6075
CE26

======================================
Secondary data write routine 1.

======================================

*
*
*
*

This routine is called when secondary communication
occurs. It writes secondary data to DXR, and and modifies*
the content of XVECT(117 pageO) for continuing secondary *
communication.
*

************************************************************
Sl

*
*
*
*
**
*
*
*
*

LAC D2ND,O
SACL DXR,O
LAC VS2,O
SACL XVECT,O
RET

*

write DXR 2nd data.

*

modify for next XINT.

*

return.

************************************************************

0071
0072
0073
0074
0075
0076
0077
0078
0079
007A

CAOO
6001
607F
CAFF
607E
2077
6075
2073
6004
CE26

======================================
Secondary data writing routine 2.

======================================

*
*
*
**

This routine is called when secondary communication
occurs. It writes dummy data to DXR to ensure that
*
secondary communication is not inadvertently initiated
on the next XINT. It also modifies the content of XVECT
for normal communication.
*

*
*

************************************************************
S2

ZAC
SACL
SACL
LACK
SACL
LAC
SACL
LAC
SACL
RET

DXR,O
F2ND
>FF
FXMT,O
VNRM,O
XVECT,O
~NTST,O

*
*

clear data for protection.
of double secondary communication.
* clear secondary flag.
* set xmit end flag.
* set normal communication vector.

*

enable all interrupts.

IMR,O
* return.

10-37

0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308

007B
007C
007D
007E
007F
0080
0081
0082
0309 0083
0310
0311 0084
0312 0085
0313 0086
0314 0087
0315 0088
0316 0089
0317 008A
0318 008B
0319 008C
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331 008D
0332 008E
008F
0333 0090
0334 0091
0092
0335 0093
0336 0094

10-38

*~~~~~*******************************************************
=======================
Check

secondary code.

=======================

C800
CA03
606F
207B
4E6F
106F
F680
0084
CE26

destroy DP pointer.
ACC.

*

*
*
*
pageO)*

* This routine checks whether the data in DXMT (123
* has secondary code or not. If secondary code exists,
*
* then disable maskable interrupts except XINT, modify the *
* contents of XVECT(117 pageO) for secondary communication,*
* and set secondary flag. Note that we recommend calling
*
*
* this routine to send control words to the AIC.
************************************************************
LDPK 0
* data page pointer O.
C2ND
LACK 03
SACL TMPO
LAC DXMT,O
* is this data secondary code ?
AND TMPO
SUB TMPO,O
* if yes, then next.
BZ
C2NDl

*

RET

* else return.

LACK >FF
SACL F2ND,0
LACK >20
SACL IMR,O
LAC VSl,O
SACL XVECT,O
LAC DXMT,O
SACL DXR,O
RET

* set secondary flag.

~

CAFF
607F
CA20
6004
2078
6075
207B
6001
CE26

C2NDl

* enable only XINT.
*modify vector address for secondary
* communication.
* write primary data to DXR.
* return.

************************************************************

*

=======================

*

Check first interrupt

=======================

206D
F680
008D
206C
F680
008D
CE26

*
This routine checks if both first interrupts have
* occurred. If this routine is called after reset, it
* waits for both interrupts then returns.
************************************************************
IGR
LAC FRE,O
* check first interrupt after
BZ
IGR
* master reset.
LAC
BZ
RET

FXE,O
IGR

0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347

*
************************************************************

*
*
**
*
*
*
*
*

==============================
Ignore interrupt routine.

==============================
These routines are used so that the first RINT and XINT
after the DSP reset can be ignored. They set flags and
modify each vector address to the normal interrupt
address but do not read or write to the serial ports.
Note that the first data that the AIC will receive after
the DSP reset is >0000.

*
*
**
*
*
*
*
*

SACL FRE,O
LAC VRCV,O
SACL RVECT,O
RET

0359 009D CE26
0360
0361
NO ERRORS, NO WARNINGS

*

LACK
SACL
LAC
SACL
RET

>FF
FXE,O
VNRM,O
XVECT,O

*

return.

END

10-39

10-40

C

C.1

TLC32040 and TMS320C17 Flowcharts and
Communication Program
Flowcharts

WAIT FOR FIRST EODX PULSE

ENABLE INTERRUPT

WRITE SECONDARY COMMUNICATION

MODIFY INTERRUPT LOCATION. *SINT1

NO
NO

CALL SUBROUTINE REFERENCED
BY VECTOR

YES

a. MAIN

b. INTERRUPT SERVICE ROUTINE

1Q....41

c. PRIMARY COMMUNICATION 1

d. PRIMARY COMMUNICATION 2

e. PRIMARY·SECONDARY COMMUNICATION 1

f. PRIMARY·SECONDARY COMMUNICATION 2

CLEAR TRANSMIT LOW BYTE STORAGE LOCATION

g. PRIMARY·SECONDARY COMMUNICATION 3

10--42

h. PRIMARY·SECONDARY COMMUNICATION 4

NO

TO TRANSMIT HIGH-BYTE

MOVE RECEIVE LOW-BYTE
TO TRANSMIT LOW-BYTE
WRITE TRANSMIT HIGH-BYTE TO
TRANSMIT REGISTER BUFFER

i. DIGITAL LOOPBACK

10-43

C.2 Communication Program List

10-44

0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054

************************************************************
*
*

* ====================================================== *
*
TlC32040 to TMS320C17 Communication Program
*
*
verS10n 1.2
*
*
revised 7/22/88
*
**
**
by Hironori Okubo and Woody Rowand
*
Texas Instruments
*
*
(214) 997-3460
*
* ====================================================== *
** This program uses the circuit published in the Volume **
* 3 of the linear and Interface Circuit Applications book *
* with the following modification:
* 1. INT- of the TMS320Cl7 must be connected to EODXof the TlC32040.

*
*
*
*
*
*
*

**

*
*
*
*
*
*
*
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF

In this configuration, the program will allow the
TlC32040 to communicate with the TlC320C17
with the restriction that all interrupts except INTare prohibited and only synchronous communication
can occur. The program allows the user two levels of
nesting in the main program; the remaining two levels
are reserved for the interrupt vector and subroutines.
If desired, this program may be used with the
TMS320ll Digital Signal Processor with the following
change. Since the TMS320ll has only sixteen words of
data RAM on data page 1, all of the registers used by
this program should be moved to data page 0, except
for SSTSTK (the temporary storage location for the
status register) which must remain on page 1 (since
the SST instruction always addresses page 1).

*
*

*
*
*
*
*

**
*

*
*
*
*
*
*

************************************************************
SSTSTK
ACHSTK
AClSTK
RXEFlG
DRCVl
DRCV2
DXMTl
DXMT2
DXMT3
DXMT4
VECT
ANINTl
ANINT2
ASINTl
ASINT2
ASINT3

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

>00
>01
>02
>03
>04
>05
>06
>07
>08
>09
>OA
>OB
>OC
>OD
>OE
>OF

stack for status (SST) register.
stack for accumulator high (ACCH).
stack for accumulator low (ACCl).
xmit/receive in progress.
storage for high byte receive data.
storage for low byte receive data.
storage for high byte xmit data.
storage for low byte xmit data.
storage for high byte secndry data.
storage for low byte secndry data.
storage for interrupt vector addr.
storage for normal xmit/rcv vect 1.
storage for normal xmit/rcv vect 2.
storage for secndry xmit/rcv vect 1.
storage for secndry xmit/rcv vect 2.
storage for secndry xmit/rcv vect 3.

0055 0000
0056
0010
0057
0011
0058
0012
0013
0059
0014
0060
0061
0015
0062
OOFF
0063
0064
0065
0066 0000
0067 0000 F900
0001 0013
0068 0002
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
00.83
0084
0085
0086
0087
0088
0089 0002
0090 0002 6E01
0091 0003 7COO
0092 0004 5801
0093 0005 5002
0094 0006 4813
0095 0007 4011
0096 0008 2011
0097 0009 7912
0098 OOOA FFOO
OOOB 0007
0099 OOOC
0100
0101 OOOC 200A
0102 OOOD 7F8C
0103 OOOE 6501
0104 OOOF 7A02
0105 0010 7BOO
0106 0011 7F82
0107 0012 7F8D

ASINT4
CNTREG
MXINT
CLRX
CLRX1
TEMP
flAG

EQU
EQU
EQU
EQU
EQU
EQU
EQU

>10
>11
>12
>13
>14
>15
>FF

storage for secndry xmit/rcv vect 4.
storage for control register.
storage for xmit interrupt mask.
storage for xmit interrupt clear.
storage for xmit intrpt clear/mask.
temporary register.
flag set.

=======================================
Branch to initialization routine.

=======================================
AORG
B

>0000
INIT

branch to initialization routine.

************************************************************
* =================================
*

Interrupt service routine.
*
* =================================
** To initiate secondary communication, change the
* contents of VECT to the address of the secondary
* communication subroutine and store the information
* in DXMT3 and DXMT4.
** e.g.
modify VECT.
ASINTl
*
LAC
*
SACL VECT
*
I
store high-byte of secondary
HI
*
LAC
information in DXMT3.
*
SACL DXMT3
store low-byte in DXMT4.
H2
*
LAC
*
SACL DXMT4
*
************************************************************

AORG
INTSVC LDPK
SST
SACH
SACL
OUT
WAITl IN
LAC
AND
BZ

>02
1
SSTSTK
ACHSTK
ACLSTK
CLRX,PAO
CNTREG,PAO
CNTREG,0
MXINT
WAITI

*
LAC
CALA
ZALH
OR
LST
EINT

RET

VECT
ACHSTK
ACLSTK
SSTSTK

push status register.
push accumulator high.
push accumulator low.
make sure FSX-flag is clear.
read control register.
load accumulator with control reg.
mask-off xmit interrupt flag.
loop until xmit interrupt flag is

recognized.
load ace with interrupt vector.
call appropriate xmit/rcv routines.
pop accumulator high.
pop accumulator low.
PoP status register.
enable interrupts.
return to main program.
10-45

0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
10-46

0013

************************************************************

* ====================================
*
Initialization after reset.
* ====================================
** Data RAM locations >80 through >92 are reserved by
* this program. The user must set the status register
* at the end of this program with the SST command or
* a combination of SOVM, LDPK etc.
*

0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
0010
001E
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
0028
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D

7F81
6E01
7F89
6880
7083
50A8
50A8
50A8
50A8
50A8
50A8
50A8
5088
4906
4906
7E04
5012
7EOl
5015
6A15
80Al
7F8E
6713
80A2
7F8E
6714
8090
7F8E
500A
8077
7F8E
500B
8070
7F8E
500C
8084
7F8E
5000
808A
7F8E
500E
8090
7F8E

*
*
*
*

*

*
*

*
*
************************************************************
INIT

DINT
LDPK
ZAC
LARP
LARK
SACL
SACl
SACL
SACL
SACL
SACL
SACL
SACL
OUT
OUT
LACK
SACl
LACK
SACL
LT
MPYK
PAC
TBLR
MPYK
PAC
TBLR
MPYK
PAC
SACL
MPYK
PAC
SACL
MPYK
PAC
SACL
MPYK
PAC
SACL
MPYK
PAC
SACL
MPYK
PAC

1

disable interrupts.
set Data page pointer one.
clear registers.

o
0, RXEFLG+>80
H

*+
*+
*+
*+
*+
*+

*

DXMTl,PAl
DXMTl, PAl
?00000100
MXINT
1

TEMP
TEMP
CLXl
CLRX
CLX2

clear transmit registers.

initialize xmit-int mask.
prepare for serial port initialization and initialization of registers containing 16-bit constants.
initialize interrupt flag clear.

initialize interrupt flag clear
with interrupts disabled.

CLRXI
IGN
VECT
NINTl
ANINTl
NINT2
ANINT2
SINTl
ASINTl
SINT2
ASINT2
SINn

initialize interrupt vector.
save normal communication address
to its storage.
save normal communication address 2
to its storage.
save secondary communication
address 1 to its storage.
save secondary communication
address 2 to its storage.
save secondary communication
address 3 to its storage.

0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188

003E
003F
0040
0041
0042

600F
A095
CE14
6010

SACL
MPYK
PAC
SACL

ASINT3
SINT4

save secondary communication
address 4 to its storage.

ASINT4

************************************************************

* ===========================================
Synchronize high/low byte transmission.
* ===========================================
* The time between FSX- interrupts is approximately
*
*
*
*
*

*

ten microseconds (50 cycles). Wait for first
FSX-, if this is the first interrupt, delay 60
cycles (past the second interrupt). If it is the
second interrupt, no harm done.

*

0042
0043
0044
0045
0046
0047
0048
0048
0049
004A
004B
004C
004C
004D
004D

E014
8011
2011
4E12
F680
0043
C014
5500
FB90
0049

0189
0190
E013
0191
0192
CEOO
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213 004E CAOO
0214 004F 6006
0215 0050 CA03

************************************************************
OUT
CLRXl,PAO clear interrupt flags, disable into
IGNOR IN
CNTREG,PAo read control register.
wait
LAC
CNTREG
AND
for
MXINT
FSX- flag.
BZ
IGNOR

LARK
IGNORI NOP
BANZ

OUT

0,20
IGNORI

wait 60 cycles (20 X 3 cycles) 1n
case FSX- into is first of the pair.
if FSX,- int was the second, delay

CLRX,PAO

anyWay.

enable interrupt.
EINT
************************************************************

* =================================
Main program (user area)
* =================================
*
* This program allows the user two levels
*

*

*
*
*
*
*
*

*

*
*
*
*

*
*

*
*

of nesting,
*
since one level is used as stack for the interrupt and *
the interrupt service routine makes one subroutine call.*
User routines such as digital filtering, FFTs, and
*
secondary communication judgement may be placed here.
*
The number of instruction cycles between interrupts
*
varies with the sampling rate. In the power-up
*
condition this is approximately 500 cycles.
*
In the example below, the first two transmissions send
secondary information to the AIC. The first configures
the TB and RB registers. The second configures the
control register.

MAIN

ZAC
SACL
LACK

*

*
*
*
*

prepare first control word.
DXMTl
>03

10-47

0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229

0051
0052
0053
0054
0055
0056
0057
0057
0058

5007
7E24
5008
7 E92
5009
200D

SACL
LACK
SACL
LACK
SACL
LAC

DXMT2
>24
DXMT3
>92
DXMT4
ASINTl

500A
4906

SACL
OUT

VECT
DXMTl,PAl

communications.
store first transmit byte in
transmit buffer.

0059
005A
005B
005C
005D
005E
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A

7F89
5003
2003
FFOO
005B

RXEFLG
RXEFLG
MAINI

clear xmit/rcv end flag.

0230
0231
7F89
0232
5006
0233
7E03
0234
5007
0235
7EOO
0236
5008
0237
7E67
0238
5009
0239
200D
0240
500A
0241
4906
,0242
7F89
0243
5003
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253 006B 2003
0254 006C FFOO
006D 006B
0255 006E
0256 006E 2004
0257 006F 5006
0258 0070 2005
0259 0071 5007
0260 0072 4906
0261
0262 0073 7F89
0263 0074 5003
0264 0075 F900
0076 006B
0265 0077

10-48

*
MAINI

lAC
SACL
LAC

Bl
lAC
SACL
LACK
SACL
LACK
SACL
LACK
SACL
LAC
SACL
OUT
lAC
SACL

should be xxxx xxII.

set VECr for secondary

wait for data transfer to complete.

prepare second control word.
DXMTl
>03
DXMT2
>00
DXMT3
>67
DXMT4
ASINTl
VECT
DXMTl, PAl
RXEFlG

clear xmit/rcv end flag.

************************************************************

* ==================================
*
*
Digital loop-back program
*
* ==================================
*
** This program serves as an example of what can be done *
*
* in the user area.
*
**************************************************************
DLB

*

RXEFLG
DLB

wait for data transfer to complete.

Bl

LAC

LAC
SACL
LAC
SACL
OUT

DRCVl
DXMTl
DRCV2
DXMT2
DXMTl,PAl

move receive data to transit
registers.

lAC
SACL
B

RXEFlG
DLB

write first transmit byte to
transmit buffer.
clear rcv/xmit-end flag.

0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320

************************************************************

* ===================================
*
Normal interrupt routines.
* ===================================
** These routines destroy the contents of the accumulator* and the data page pointer, making it necessary to save
* these before the routines begin.
** Write the contents of DXMT2 to the transmit buffer and
* read the receive buffer into DRCVl.
*

0077
0077
0078
0079
007A
007B
007C
007D
007E
007F
0080
0081
0082
0083

*

*
*
*
**
*
*

************************************************************
4907
4104
200C
500A
4813
7F8D
4105
200B
500A
4813
7EFF
5003
7F8D

NINTl

NINT2

OUT
IN
LAC
SACL
OUT
RET
IN
LAC
SACL
OUT
LACK
SACL
RET

DXMT2,PAl
DRCVl,PAl
ANINT2
VECT
CLRX,PAO

write xmit-low to xmit register.
read rcv-data-high from rcv reg.
prepare next interrupt vector.

DRCV2,PAl
ANINTl
VECT
CLRX,PAO
FLAG
RXEFlG

read receive-data-low from rcv reg.
prepare next interrupt vector.

clear xmit interrupt flag.

clear xmit interrupt flag.
set xmit/rcv end flag.

************************************************************

* ========================================
*
*
Secondary interrupt routines
*
* ========================================
*
* These routines destroy the contents of the accumulator *
* and the data page pointer.
*
** The following routines write the low byte of the primary**
* data word and the high and low byte of the secondary *
* data word. They also read the A/D information from
* the receive registers.
*
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093

4907
4104
200E
500A
4813
7F8D
4908
4105
200F
500A
4813
7F8D
4909
2010
500A
4813

************************************************************
SINTl

SINT2

SINn

OUT
IN
LAC
SACL
OUT
RET
OUT
IN
LAC
SACL
OUT
RET
OUT
LAC
SACL
OUT

DXMT2,PAl
DRCVl,PAl
ASINT2
VECT
CLRX,PAO

write xmit-data-low to xmit reg.
read receive-data-high from rcv reg.
prepare next interrupt vector.

DXMT3,PAl
DRCV2,PAl
ASINn
VECT
CLRX,PAO

write secondary-dat~-high to xmit.
read receive-data-low from rcv.
prepare next interrupt vector.

DXMT4,PAl
ASINT4
VECT
CLRX,PAO

write secondary-data-low to xmit.
prepare next interrupt vector.

clear xmit interrupt flag.

clear xmit interrupt flag.

clear xmit interrupt flag.
10-49

0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
0350
0351
0352
0353
0354
0355
0356
0357
0358

0094
'0095
0096
0097
0098
0099
009A
009B
009C

7F8D
200B
SODA
4813
7F89
5007
7EFF
5003
7F8D

RET
LAC
SACL
OUT
ZAC
SACL
LACK
SACL

SINT4

clear xmit interrupt flag.

DXMT2
FlAG
RXEFlG

clear DXMT2 immediately to eliminate
unnexpected secondary communications
set xmit/rcv end flag.

prepare next interrupt vector.

RET

************************************************************

* ===========================
* Ignore first interrupt.
* ===========================
*
This routine is used to ignore the first data
* mission and also to synchronize the AIC with the
* processor.
009D
009E
009F
OOAO

200B
500A
4813
7F8D

*

trans-

*
*
*

************************************************************
IGN

LAC
SACL
OUT
RET

ANINTI
VECT
CLRX,O

************************************************************
CONTROL REGISTER INFORMATION
SERIAL-PORT CONFIG.
INT. MASK
INT. FLAG
1 0 0 0 1 1 1 01 0 0 0 11 0 1 0 01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I I 1 lINT
I
I I I __ FSR
I_XF status
I I
FSX
I
FR

**
OOAI 8ElF
00A2 8EOF

(write l"s to clear)

**

************************************************************

CLXl
CLX2

NO ERRORS, NO WARNINGS

10-50

ANINTl
VECT
CLRX,PAO

DATA
DATA
END

>8ElF
>8EOF

0317 009D 200B IGN
LAC
ANINTl
SACL VECT
0318 009E 500A
CLRX,O
0319 009F 4813
OUT
0320 OOAO 7F8D
RET
0321
************************************************************
0322
*
*
0323
CONTROL REGISTER INFORMATION
*
*
0324
*
*
SERIAL-PORT CONFIG.
0325
INT. MASK
INT. FLAG
*
*
0326
1 0 0 0 1 1 1 01 0 0 0 11 0 1 0 01
*
*
0327
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
*
*
• INT
0328
I
*
*
••
'0329
LXF status
•
FSR
J
*
'-- FSX *
0330
*
*
FR
0331
*
*
0332
*
*
(write lis to clear)
0333
*
*
0334
************************************************************
DATA >8ElF
0335 OOAI 8EIF CLXI
DATA >8EOF
0336 00A2 8EOF CLX2
0337
END
NO ERRORS, NO WARNINGS

10--51

10-52

Implementation of a 1280 x 1024 x 8
Display Using the TLC34075
Video Interface Palette

By
Robert Milhaupt, Jeffrey Nye, and John Yin

TEXAS
INSTRUMENTS

10-53

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue any
semiconductor product or service identified in this publication without notice. TI
advises its customers to obtain the latest version of the relevant information to
verify, before placing orders, that the information being relied upon is current.
TI warrants performance of its semiconductor products to current specifications in
accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty.
Unless mandated by government requirements, specific testing of all parameters
of each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor
does TI warrant or representthat license, either express or implied, is granted under
any patent right, copyright, mask work right, or other intellectual property right of
TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Texas Instruments products are not intended for use in life-support appliances,
devices, or systems. Use of a TI product insuch applications without the written
consent of the appropriate TI officer is prohibited.

Copyright © 1991, Texas Instruments Incorporated

10-54

Contents
Section

Title

Page

1

INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-57

2

FEATURE SET DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-57
2.1 TLC34075 Feature Set .................................................. 10-57
2.2 Design Features ............. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-58

3

RELATED DOCUMENTATION ............................................ 10-58

4

DESIGN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1 Memory Map .........................................................
4.1.1 Memory Map Decoding ............................................
4.1.2 Mapping the TLC34075 Into 'fMS34020A Memory Space ................
4.1.3 Address Latching .................................................
4.2 Frame Buffer Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.1 TMS34020A Shift Register Transfer Operation .........................
4.2.2 Packed and Unpacked Frame Buffers .................................
4.2.3 Split Shift Register Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.4 Packed Displays and TMS34020A Screen Refresh Latency ................
4.2.5 Multiplexing the PXD Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3 Video Interface Palette Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.1 Video Interface Palette Control Registers ..............................
4.3.2 Accessing the Video Interface Control Registers. . . . . . . . . . . . . . . . . . . . . . . ..
4.3.3 TLC34075 Dot Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4 Resetting the TMS34020A ...............................................
4.5 Resetting the TLC34075 .................................................

10-58
10-59
10-61
10-62
10-62
10-62
10-63
10-63
10-66
10-69
10-70
10-71
10-71
10-71
10-71
10-72
10-72

5

PROGRAMMING THE TLC34075 REGISTERS ..............................
5.1 General Control Register ................................................
5.2 Input Clock (Dot Clock) Selection . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..
5.3 SCLK and VCLK Divide Ratio Selection ...................................
5.4 Multiplexer Control Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 Accessing the Palette Color Look-Up Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6 Suggested Values for TMS34020A and TLC34075 Registers. . . . . . . . . . . . . . . . . . ..

10-72
10-72
10-73
10-73
10-74
10-74
10-74

Appendix A: Application Circuit Schematic and Parts List . . . . . . . . . . . . . . . . . . . . . . . . .. 10-77
Appendix B: ABEL'· Files for LTCHDCD (U4), RASDCD (US), and
RESET (U38) PALs® .............................................. 10-89

ABEL is a trademark of DATA I/O.
PAL is a registered trademark of Advanced Micro Devices.

10--55

List of Illustrations
Figure

Title

Page

1
2
3

System Block Diagram

4

Packed 1280-by-1024-by-8 Display Memory ................................. 10-66

5

SRT Signals During Horizontal Blanking Without Split Shift Register Transfers ..... 10-67

6

SRT Signals During Horizontal Blanking Using Split Shift Register Transfers ....... 10-68

7

SCLK Pulse Between SRT and SSRT and Related Signals ..................... "

8

Generation of SOEO and SOE1 (Both Previous and Current Display
Line inVRAM Bank 0) ................................................ 10-70
Generation of SOEO and SOEl (Previous Display Line in VRAM Bank 0,
Current Line in VRAM Bank 1) ......................................... 10-71

9

10-56

10-59

Shift Register Transfer Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-64
Unpacked 1280-by-1024-by-8 Display Memory ............................... 10-65

10-69

1 INTRODUCTION
The TLC34075 Video Interface Palette (VIP) achieves a new level of video system integration by
incorporating in a single device logic typically implemented with 20 to 30 integrated circuits. The
TLC34075 contains programmable video shift registers, VGA pass-through logic, VRAM control
circuitry, video sync and blank control, a voltage reference, dot clock multiplexers, monitor detection
circuitry, a true color pipeline with overlay, a 256-entry 24-bit-wide palette RAM, a VGA-compatible
register set, and frame buffer test circuitry. The feature set of the TLC34075 is designed to provide
maximum flexibility to the designer so that the resulting system can support an extremely broad
applications base. The high level of integration enables very low chip count designs and makes large
amounts of board space available for product differentiation.
This application report details a graphics design capable of resolutions up to 1280 by 1024 by 8. The design
utilizes a 110-MHz TLC34075 and a 40-MHz TMS34020A. The discussion herein includes the local-bus
interface and back-end implementation. Since this design is independent of the host bus, the host interface
is left as an exercise to the reader. The hardware described in this application report has been built and tested
in a laboratory environment.

2 FEATURE SET DESCRIPTION
This section briefly outlines the features found in the TLC34075 and those found in the design
implementation.

2.1 TLC34075 Feature Set

•
•

•
•
•
•
•

•
•
•

•
•

•

RS-343A-Compatible Outputs (RGB)
Programmable Sync Pedestal
Sync on Green
Separate TTL-Compatible Sync With Polarity Control
Programmable Pixel Depth:
1, 2, 4, 8, or 24+8 bits per pixel
Programmable Pixel Bus Width:
4, 8, 16, or 32 bits wide
VGA Compatible Register Set
VGA Pass-Through Port
On-Chip Voltage Reference
4/5 Input Dot Clock Multiplexer
Split Shift Register Transfer SCLK Pulse Generation
Monitor Detection
Palette Paging Register

10-57

2.2 Design Features

•

•
•

Supports several programmable resolutions and pixel depths including:
1280 by 1024 (1, 2, 4, or 8 bits per pixel) noninterlaced (discussed)
1024 by 768 (1, 2, 4, or 8 bits per pixel) noninterlaced (not discussed)t
640 by 480 (1, 2, 4, or 8 bits per pixel) noninterlaced (discussed)
512 by 512 (1, 2, 4, 8, or 32 bits per pixel) noninterlaced (not discussed)t
2M bytes ofzero-wait-state VRAM (TMS44C251-1O)
1M bytes ofzero-wait-state DRAM (TMS44C256-10)

t Resolutions not discussed herein will be addressed in future application notes.
3 RELATED DOCUMENTATION
Following is a partial list of literature pertinent to the design described in this article.

•

•
•
•
•
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TMS34020 User's Guide (SPVU019)
TMS34020, TMS34020A Data Sheet (SPUS004B)
TLC34075 Data Manual (SLAS043)
MOS Memory Data Book (SMYD091)
340 Family Graphics Library User's Guide (SPVU027)
340 Family Code Generation Tools User's Guide (SPVU020A)
TIGA Interface User's Guide, Rev 2.0 (SPVU015B)

4 DESIGN DESCRIPTION
The system block diagram is shown in Figure 1. The LAD bus is a 32-bit multiplexed address and data path
used as the local bus in this design. All peripherals accessible to the TMS34020A are linked via this bus.
The LAD bus is also used by the decoder logic to enable access to these peripherals.
The RCA bus is the RAM address bus used directly by the VRAM and DRAM banks. This bus, an important
feature of the TMS34020A, eliminates the need for external row and column address multiplexers.
The three-state PXD bus is a 64-bit pixel data path multiplexed to 32 bits. It is used to bring pixel data into
the TLC34075. Control of the PXD data bus is shared by the TMS34020A, which performs memoryto-shift-register transfer cycles based on VCLK, the TLC34075, which provides the SCLK and the VCLK
signals, and the RASDCD (U5) decoder, which performs the three-state multiplexing function by enabling
the SOE pin of the proper VRAM bank.
VCLK is the synchronizing clock used by the TMS34020A to determine when to assert video sync and
blank signals and when to perform the next memory-to-shift-register transfer cycle for screen refresh. The
frequency of VCLK is adjustable via a register in the TLC34075 and is typically a submultiple of the dot
clock.
SCLK is the VRAM shift clock used to move the next pixel data to the serial output port of the VRAM;
this pixel data is subsequently captured by the input latch of the TLC34075. The frequency of SCLK is
adjustable via a register in the TLC34075 and is always related to the number of pixels available at the pixel
input to the TLC34075. For example, the combination of a 4-bit pixel and a 32-bit-wide PXD bus requires
that the SCLK frequency is one eighth of the dot clock frequency because 8 pixels are obtained with every
SCLKpulse.
Two latches and two decoder devices are used to configure the memory map and control access to the
peripherals on the local bus.
10-58

Memory Control

I
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J

r'
TMS34020A

Video

Control

~
Reset
Logic

I

r-

'--

~

- - , / TLC34075

~

~J

LAD

,

Decode
Logic
Control

h

-

-

DRAM

/'-

"-

Decoded
Control

-

~

fr

VRAM

PXD

VI'-r-

I

Figure 1. System Block Diagram
The RESET (U38) PAL@provides a controlled reset pulse to the TMS34020A and to the TLC34075 reset
generation circuitry.

4.1 Memory Map
The memory map of this design is summarized in the table below.
ADDRESS

DESCRIPTION

ACCESS

00000000

Start of VRAM Bank 0

R/W:32

00800000

Start of VRAM Bank 1

R/W:32

01000000

Start of DRAM Bank 0

R/W:32

017FFFFF

End of DRAM Bank 0

----- ... ---

TMS34020A I/O Registers

-----------

COOOOOOO

VESYNC

R/W:16

COOOO010

HESYNC

R/W:16

COOOOO20

VEBLNK

R/W:16

COOOO030

HEBLNK

R/W:16

PAL is a registered trademark of Advanced Micro Devices, Inc.

Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10-59

ADDRESS

10-60

DESCRIPTION

ACCESS

COOOOO40

VSBLNK

R/W:16

COOOO050

HSBLNK

R/W:16

COOOO060

VTOTAL

R/W:16

COOOOO70

HTOTAL

R/W:16

COOOOO80

DPYCTL

R/W:16

COOOO090

DPYSTRT

R/W:16

COOOOOAO

DPYINT

R/W:16

COOOOOBO

CONTROL

R/W:16

COOOOOCO

HSTDATA

R/W:16

COOOOODO

HSTADRL

R/W:16

COOOOOEO

HSTADRH

R/W:16

COOOOOFO

HSTCTLL

R/W:16

COOOO100

HSTCTLH

R/W:16

COOOO110

INTENB

R/W:16

COOOO120

INTPEND

R/W:16

COOO0130

CONVSP

R/W:16

COOOO140

CONVDP

R/W:16

COOO0150

PSIZE

R/W:16

COOOO160

PMASKL

R/W:16

COOOO170

PMASKH

R/W:16

COOO0180

CONVMP

R/W:16

CQOOO190

CONTROL

R/W:16

COOO01AO

CONFIG

R/W:16

COOO01BO

DPYTAP

R/W:16
R/W:16

COOO01CO

VCOUNT

coooomo

HCOUNT

R/W:16

COOOO1EO

DPYADR

R/W:16

COOOO1FO

REFADR

R/W:16

COOOO200

DPYSTL

R/W:16

C0000210

DPYSTH

R/W:16

COOO0220

DPYNXL

R/W:16

COOOO230

DPYNXH

R/W:16

COOO0240

DINCL

R/W:16

COOO0250

DINCH

R/W:16

COOO0260

Reserved

------

COOOO270

HESERR

R/W:16

COOOO280

Reserved

---- ..-

COOOO290

Reserved

------

COOO02AO

Reserved

------

COOOO2BO

Reserved

.. -_ .. _-

COOOO2CO

SCOUNT

R/W:16

COOOO2DO

BSFLTST

R:16

COOOO2EO

DPYMSK

R/W:16

COOOO2FO

Reserved

_.. _---

ADDRESS

DESCRIPTION

ACCESS

COOO0300

SETVCNT

R/W:16

C0000310

SETHCNT

R/W:16

COOO0320

BSFLTDL

R:16

COOO0330

BSFLTDH

R:16

COOO0340

Reserved

--~~-

COOO0350

Reserved

-----

COOO0360

Reserved

-----

COOO0370

Reserved

-----

COOO0380

IHOST1L

R:16

COOO0390

IHOST1H

R:16

COOO03AO

IHOST2L

R:16

COOO03BO

IHOST2H

R:16

COOO03CO

IHOST3L

R:16

COOO0300

IHOST3H

R:16

COOO03EO

IHOST4L

R:16

COOO03FO

IHOST4H

R:16

----------

End of TMS34020A I/O Register Set

-----

----------

Beginning of TLC34075 Register Set

-----

00000000

Write Mode Address Register

R/W:8

00000020

Palette Holding Register

R/W:8

00000040

Read Mask Register

R/W:8

00000060

Read Mode Address Register

R/W:8

00000080

Reserved

-----

OOOOOOAO

Reserved

-----

OOOOOOCO

Reserved

-----

OOOOOOEO

Reserved

-----

00000100

General Control Register

R/W:8

00000120

Input Clock Register

R/W:8.

00000140

Output Clock Register

R/W:8

00000160

MUX Control Register

R/W:8

00000180

Palette Page Register

R/W:8

000001AO

Reserved

-----

000001 CO

Test Register

R/W:8

000001 EO

Reset State

R/W:8

.. ---------

End of TLC34075 Register Set

------

FF800000

Beginning of shadow of DRAM Bank 0

R/W:32

FFFOOOOO

TMS34020A Interrupt and Trap Vectors

R/W:32

FFFFFFFF

End of Interrupt and Trap Vectors and
shadow of DRAM Bank 0

------

4.1.1 Memory Map Decoding
The memory map previously shown is decoded by the RASDCD (US) PAL. A RAS-banking method is
used. The RASDCD (US) PAL provides bank decoding based on the URAS output from the TMS34020A
and the latched address information provided by the SN74AS841 (U3) address latch. The RASO, RASl,
and RAS2 signals are used to drive the RAS input signals ofVRAM bank 0, VRAM bank 1, and the DRAM
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10-61

bank, respectively. The RAS2 output of the RASDCD (US) PAL is also decoded to map the DRAM into
the address range of the TMS34020A's interrupt and trap vectors. Because the TMS34020A's interrupt and
trap vectors are stored at the end of the shadow of DRAM bank 0, program memory space in DRAM must
not use upper locations of DRAM. The RASDCD (U5) PAL also provides a chip select signal, PALETEN,
which is generated for the TLC34075. Because incomplete address decoding is used, all banks are alia sed
throughout memory space; the memory map only shows the suggested memory usage and the shadowing
of DRAM bank O.
The video RAM RAS signals are not based solely on address. The TMS34020A provides two special bus
cycles during which both banks of video RAM should be activated:
• the load-write-mask cycle: used to write-protect bit planes within the video RAM .
• the load-color-register cycle: copies the color value from the TMS34020A COLOR1 register
into the video RAM color register. The color register data is then used during block-write cycles;
this is useful for bulk initialization of memory or for fast screen clearing.
During either a load-write-mask cycle or a load-color-register cycle, the TMS34020A zeroes the LAD bus
during the address portion of the cycle and zeroes the RCA bus for both the row and column portions of
the cycle. If these cycles were not special-cased, only video RAM bank 0 would act on these cycles, as it
is mapped to address zero. The RAS2 signal is not asserted during these cycles since the TMS44C256
DRAM does not support these cycles.

4.1.2 Mapping the TLC34075 Into TMS34020A Memory Space
The TLC34075 implements a VGA-compatible register set that uses an 8-bit data bus. Since the
TMS34020A's LAD bus is 32 bits wide, it is convenient to map the TLC34075 into the TMS34020A's
memory space as a 32-bit-wide device, ignoring the upper 24 bits of data.
The TLC34075 chip-select signal (PALETEN) generated by the RASDCD (U5) PAL is used by the
LTCHDCD (U4) PAL to generate read and write strobes to the TLC34075. The TLC34075's write signal
(WR) is driven low when PALETEN is low and WE is low. The TLC34075's RD input is driven low when
PALETEN is low, WE is high, and TR/QE is low (TR/QE, while not strictly required, provides symmetrical
timing for RD and WR assertion). The four register select inputs of the TLC34075 are connected to the four
latched address bits: LDAT8, LDATI, LDAT6, and LDAT5. This imposes several constraints on the
software operation of the system. When reading values from the TLC34075's registers, only the lower 8
bits of a 32-bit, long-word-aligned memory access are valid. Similarly, a 32-bit-wide write to a 32-bit
word-aligned address of a TLC34075 register only uses the lower 8 bits of data. It is safest to access the
TLC34075 with 8-bit reads and writes to long-word-aligned addresses as shown in the memory map.

4.1.3 Address Latching
The address latches, the LTCHDCD (U4) PAL, and the SN74AS841 (U3) latch generate latched address
information for the memory decoder PAL and the TLC34075. The memory decoder PAL requires latched
address bits 31-28, 24-23, and status bits 3-0, and the TLC34075 uses latched address bits 8-5. The
LTCHDCD (U4) PAL uses internal feedback to implement a transparent latch. In addition, it forces latched
address bits 8-5 high during reset, as described in Section 4.5.

4.2 Frame Buffer Organization
Frame buffer memory in 1280-by~1024-by-8 systems is typically implemented with either "packed" or
"unpacked" scan lines. While the unpacked scan line method is the simpler hardware implementation, it
causes poor memory utilization, as memory fragments not used for pixel data appear at the end of each scan
line. The packed scan line implementation utilizes frame buffer memory efficiently, as all memory not used
10-62

for pixel data appears in a contiguous block at the end of the frame buffer. Prior to availability of the
TLC34075, implementing a 1280-by-1024 packed frame buffer for a TMS340-based system has been
complex. The architecture of the TLC34075 removes virtually all of that complexity.
The following discussion deals with the tradeoffs associated with unpacked- versus packed-frame buffer
memories in TMS340 designs. As background to the discussion, the first section deals with the operation
of the TMS34020A memory controller regarding shift register transfer cycles.

4.2.1 TMS34020A Shift Register Transfer Operation
When the graphics system is ready to display valid video data, the screen refresh enable bit of the display
control I/O register (SRE [DPYCTL]) is set to one by system software. At this time, the video timing logic
of the TMS34020A begins scheduling VRAM shift register transfer cycles (also called serial register
transfers, memory-to-register transfers, screen refresh cycles, or SRTs). The TMS34020A supports two
types ofSRTs: those that occur during the horizontal blanking interval and those that occur during the active
display time. SRTs that occur during active display time (midline reload cycles) are not required for this
design.
The TMS44C251 video RAM supports two types of shift register transfer: a normal shift register transfer
(SRT) that transfers one whole RAM array row into the VRAM's serial shift register and a split shift register
transfer (SSRT) that transfers one half of a RAM array row to one half of the VRAM's serial shift register.
The TMS34020A supports both types. Unless the SRT bit of the DPYCTL (OxC0000080) register is set
to one, the TMS34020A only performs normal SRTs. If the SRT bit is set, the TMS34020A schedules, at
the beginning of blanking, an SRT immediately followed by a SSRT. Additional SSRTs may be scheduled
by the TMS34020A during the active portion of the scan line if the SCLK input of the TMS34020A is
cycling and the TMS34020A determines that the serial shift register is nearly empty. If split shift register
transfers are not needed during the active portion of the scan line, the TMS34020A's SCLK input should
be tied to ground. Although the application described herein uses split shift register transfers, it does not
require SSRTs during the active portion of the scan line but only during blanking. Therefore, in this
application, the TMS34020A's SCLK input is tied to ground.
At the onset of the horizontal blanking period for a scan line, the TMS34020A memory controller schedules
an SRT cycle to occur during the blanking interval. The SRT cycle instructs the VRAM to copy pixel data
from a row of its RAM array into its serial shift register. An example of an SRT cycle is shown in Figure 2.
For applications in which a pixel data scan line wraps from one RAM row to the next row rather than being
contained in a single RAM row, a split shift register transfer (SSRT) cycle is used to copy the scan line from
the RAM into the serial shift register. As shown in Figure 4, packed scan line implementation results in
numerous instances of scan lines wrapping from one RAM row to the next. Hence, SSRTs are used in
systems that employ packed scan line frame buffers.

4.2.2 Packed and Unpacked Frame Buffers
The amount of memory required for a 1280-by-1024-by-8 frame buffer depends on whether a packed or
unpacked implementation is chosen. In a packed implementation, the scan line pixel data are stored
contiguously in the frame buffer (i.e, the last pixel of a scan line is followed immediately by the first pixel
of the next scan line; there are no unused bits between scan lines). Therefore, the pitch of the pixel
information (the difference in storage addresses for vertically adjacent pixels) equals the amount of
memory required to store one pixel data scan line (in this case, 1280 pixels/line times 8 bits/pixel, or 10240
bits). A minimum of 1.25M bytes of memory is required to implement a 1280-by-1024-by-8 packed frame
buffer (1280 bytes/line x 1024 lines).
In an unpacked frame buffer implementation, the pitch of the pixel data is typically chosen to be the power
of two that is greater than or equal to the amount of memory required to store one pixel data scan line. For
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 Video Interface Palette

10-63

example, a 1280-by-1024-by-8 unpacked frame buffer (one scan line requires 10240 storage bits) would
typically employ a pitch of 16384 bits, which is the first power of two greater than the 10240bits required
for one scan line. Therefore, a minimum of 2.1M bytes of memory is required to implement a
1280-by-1024-by-8 unpacked frame buffer (2048 bytes/line x 1024 lines).
Each system has both advantages and disadvantages:
FRAME BUFFER TYPE

ADVANTAGE

DISADVANTAGE

Unpacked

May not require split shift register transfers

Typically fragments unused frame buffer
memory

Packed

Does not fragment unused frame buffer
memory

Typically requires split shift register
transfers

I"
Memory-to-Register Transfer Cycle --'---+j
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Figure 2. Shift Register Transfer Cycle
10-64

Figures 3 and 4 show the memory organization for unpacked and packed frame buffers, respectively, for
a 1280-by-1024-by-8 display ..
VRAM
Bank

RAM Array
Row

0

0

0

Scan Line 0

Unused

Scan Line 1

Unused

0

2

Scan Line 2

Unused

0

3

Scan Line 3

Unused

0

4

Scan Line 4

Unused

0

5

Scan Line 5

Unused

•
••

•••

0

509

Scan Line 509

Unused

0

510

Scan Line 510

Unused

0

511

Scan Line 511

Unused

0

Scan Line 512

Unused

Scan Line 513

Unused

2

Scan Line 514

Unused

3

Scan Line 515

Unused

•••

••
•

•

••

•

••

509

Scan Line 1021

Unused

510

Scan Line 1022

Unused

511

Scan Line 1023

Unused

Figure 3. Unpacked 1280-by-1024-by-8 Display Memory
In implementing a 1280-by-1024-by-8 unpacked frame buffer, no split shift register transfers are needed,
as no scan line crosses a VRAM array row boundary. The packed frame buffer organization does span scan
line information across VRAM array row boundaries and, therefore, requires split shift register transfers.
Note that, in both the packed and unpacked systems, the first scan line in the second bank of VRAM is
aligned with the beginning of the first row of the bank. This is necessary, as switching between banks of
VRAM during the scan line would be extremely difficult to synchronize. Consider the last SRT in the first
bank of VRAM for the packed frame buffer. If the last SRT in VRAM bank 0 only gets a portion of the data
for the scan line, the SSRTwill address the beginning of the second bank of VRAM. Since the SSRT occurs
during blanking, there is no way to determine when to change from VRAM bank 0 driving the PXD bus
to VRAM bank 1 driving the PXD bus. (There is no method by which data from the RAM array of one bank
of VRAM may be transferred into the serial shift register of the other VRAM bank using SRTs or SSRTs.)
Since the TMS34020A requires that the display pitch must be constant throughout the display, the packed
frame buffer implementation requires that the first scan line in VRAM bank 0 be offset from the beginning
of the bank as shown in Figure 4. The starting point chosen in Figure 4 stores the maximum amount of the
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10--65

frame buffer in VRAM bank 0 while placing the first pixel of a scan line at the beginning ofVRAM bank 1.
For other resolutions and pixel depths in which the frame buffer spans more than one VRAM bank, and
when implementing multiple-page frame buffers, the starting address of the frame buffer must be chosen
similarly.
VRAM
Bank

RAM Array

0

0

Row

Scan line 1b

0
0

Scan line 0

Unused I

0

3

0

4

0

5

••
•

••
•

0

509

0

510

0

511

Scan line
4b

Scan line,
7b

126

•

••

Scan Line 7a

,

Scan line 8

Scan Line
9a

•••
Scan Line 815b
Scan line
816b

Iscan Line
818a
Scan line 819

I

,

Scan line 820
Scan line
821b

Scan line 816a

I
Scan line 817

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Scan llne818b

J

Scan line 821 a
,scan line
823a

Scan line 822

Scan line 823b

Scan line 824a

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Scan line,
1018b

Scan line
1020a

Scan Line ;021

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Scan line 1022
Scan line
1023b

,

Scan line 1019

Scan Line 1020b

127
128

,scan line
6a

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Scan line 4a

Scan Line 5

Scan line 6b

4

••
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Scan line 2
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Scan line 3

2

Scan line
1a

I

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Scan line 1023a

Unused

129

Unused

•
••

••
•

511

Unused

Figure 4. Packed 1280-by-1024-by-8 Display Memory

4.2.3 Split Shift Register Transfers
When using split shift register transfers (for VRAMs that support this feature), the VRAM shift register
is split in half. A split shift register transfer cycle specifies which half of the shift register is to be loaded
from which RAM array row. The data loaded into the shift register half-row comes from the RAM array
row specified at row address time (when RAS is low). The most significant bit of the column address
determines which half of the shift register is loaded, and all other column address bits hold the least
significant bits of the tap address. If the most significant bit of the column address is a zero, then the lower
10-66

(least significant) half of the RAM array row is loaded into the lower half of the shift register; if the most
significant bit of the column address is a one, then the upper (most significant) half of the RAM array row
is loaded into the upper half of the shift register.
In generating screen refresh cycles, the TMS34020A determines whether split shift register transfers should
be used based on the value of the SSV (enable split-serial-register midline reload) bit in its DPYCTL
register. If the SSV bit is set to one, the TMS34020A performs an SRT with a row address and tap point
followed by an SSRT with a full row address and a half-row address during the column address subcycle.
The SSRT replaces one half of the data transferred into the shift register during the SRT. It is important to
note that the VRAM's SCLK input must cycle at least once between the SRT and the SSRT in order to
transfer the tap point sent during the SRT between the VRAM internal tap point latch and the VRAM
internal tap point counter. Since this SCLK loads data into the shift register from the RAM array, it is
effectively the first SCLK pulse for the display line, and the pixel data that the VRAMs present at their serial
outputs must be displayed before the next SCLK pulse. Figures 5 and 6 show the pertinent signals during
horizontal blanking for systems without and with split shift register transfers, respectively. The BLANK
signal shown is the TLC34075's internal blanking signal, which is delayed by an amount equal to the
internal pixel pipeline delay.

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--------~------~------~-----

...

1st

2nd

SCLK

SCLK

Pulse

Pulse

Figure 5. SRT Signals During Horizontal Blanking Without
Split Shift Register Transfers

Implementation of a 1280 x 1024 x 8 Display USing the TLC34075 VIdeo Interface Palette

10-67

... J:

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CAS
SF
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Figure 6. SRT Signals During Horizontal Blanking Using Split Shift Register Transfers
Since the TLC34075 generates the SCLK signal to the VRAMs, it is convenient to allow it to insert the first
SCLK pulse between the SRT and the SSRT. The TLC34075 SFLAG input tells the TLC34075 when the
first SRT has completed. If the split shift register transfer enable bit in the TLC34075 general control
register is set to 1 and the special nibble mode enable bit (also in the general control register) is set to zero,
the TLC34075 relocates the first SCLK pulse to occur just after the rising edge of SFLAG following the
SRT. External circuitry (in the RASDCD (U5) and LTCHDCD (U4) PALs) decodes the SRT cycle and
drives the SFLAG input high after RAS and ALTCH go high. SFLAG is driven low when blanking goes
inactive. Figure 7 shows the signals related to SCLK generation during horizontal blanking with the
TLC34075 SCLK pulse relocation enabled.
For systems that perform SSRTs only during the active display time, there is no need to assert SFLAG. In
this case, the SSRTs occur after SCLK has started clocking pixels out of the VRAM. The tap point of the
SRT is latched by the first SCLK pulse.

10-68

... J:

BLANK " \
I

I

t

ALTCH \
I

AAS

I

U
I

:1

SFLAG
SCLK
Row
A

I
I
I
I
I
I
I
I
I
I

Ii

I
I
I
I
I

11\:
I
I
I

I
I

•••

I
I

:1
Tap
Point
A

r"·

I

I
I
I
I

SF

I
I

I

:\

I
I

CAS

SFLAGEN

I

)'

I

SAT

\

I

:\

r"·

I

Relocated
1st SCLK
Pulse

I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

i \. ...
I
I
I
I
I
I
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Row
B

I
I Half Blt,1
I Tap I
I Point I

•••

•••

•••
I
I

\
\

I
I

... ~

B

I
I
I

2nd
SCLK
Pulse

I
I
I

Figure 7. SCLK Pulse Between SRT and SSRT and Related Signals
4.2.4 Packed Displays and TMS34020A Screen Refresh Latency
In certain display configurations, it is not possible to employ screen organizations that require the use of
SSRTs. This problem stems from the set time between the start of horizontal blanking and the
TMS34020A-generated screen refresh cycles (the scheduling of screen refresh cycles is discussed in the
TMS34020 User 's Guide) and the amount of pixel pipeline delay. In systems for which the minimum screen
refresh latency times two is less than the SCLK period, an SRT may occur while the palette is still pushing
pixels through its pipeline. In this situation, SCLK may be high at the time when the relocated SCLK pulse
should be inserted. Because the VRAM sees no rising edge on SCLK, it does not accept the tap point
presented during the SRT, giving an improper image on the screen. Avoid using packed frame buffers for
displays with low pixel sizes (number of bits per pixel) and low dot clock frequencies. At one and two bits
per pixel, the noninterlaced 640-by-480 SCLK period is greater than two times the screen refresh latency,
suggesting that these configurations should be implemented as unpacked frame buffers. Note that the
situation wherein the SCLK period is greater than two times the TMS34020A's minimum screen refresh
latency corresponds to a display that requires a relatively small frame buffer; this typically eliminates the
need for packed frame buffer implementation.
There may be occasions when, even if two times the minimum screen refresh latency time is less than the
SCLK period, it is necessary to implement a packed display organization. In systems with a set screen
refresh latency, it may be possible to delay the SRT. In TMS34020A-based systems, the SRT can be
wait-stated until SCLK falls. As an example, in a TMS34020A-based system, the SRT cycle could be
wait-stated until SCLK falls using the LRDY signal of the TMS34020A.
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10-69

In systems with a user-defined screen refresh latency, this latency should be set to be greater than the
worst-case pixel pipeline delay but shorter than the horizontal blanking width. Consider all possible factors
when determining the latency setting (e.g., delays due to high-priority bus cycles, delays due to pipelined
memory accesses, etc.).

4.2.5 Multiplexing the PXDBus
During an SRT, the RCA bus carries the address of the VRAM row and the tap point for the display line
data but does not distinguish between VRAM banks. Since the LAD bus carries the address of the first pixel
of a display line during the address subcycle of the SRT, RAS banking is in effect as described in
Section 4.1.1. Only one bank ofVRAM receives a RAS cycle. Because the serial data outputs of both banks
of VRAM are tied to the 32-bit-wide PXD bus, the serial data outputs must be three-stated so that only the
appropriate VRAM bank drives pixel data onto the pixel bus. The VRAMs each provide a serial output
enable pin (SOE) for this purpose. The RASDCD (U5) PAL provides two outputs to drive these enable pins:
SO EO and SOE 1. The address of the screen refresh is decoded and, during the tap point subcycle of the SRT,
the appropriate SOE output is asserted. To assure that both banks of VRAM do not drive the PXD bus
simultaneously when switching from one bank to the other, the RASDCD (U5) PAL forces both SOE
outputs inactive during the row address subcycle of the SRT (see Figures 8 and 9). Internal feedback is used
to latch the SOE outputs. The RASDCD (U5) PAL also signals the beginning of an SRT cycle to the
LTCHDCD (U4) PAL for generation of the SFLAG signal to the TLC34075.
BLANK \

I

RAS

I

SF

I

SOE1

I

I

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I

I

:/i\
I
I
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1
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SOEO

I

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Row
A

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I

Tap
Point
A

I

I

1I

1
'LJ
I
I

/

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I

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\

I

Row
B

I
I Half Bit,1
I T,,:p !
I POint I
I B I

Figure 8. Generation of SOEO and SOE1 (Both Previous and
Current Display Line in VRAM Bank O)

10-70

BLANK \ .

I

RAS

CAS
SF

I

1
I

SOE1

:1
I
I
I
I
I
I
I

Row
A

I

I

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I
I

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:\
I
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Tap

Point
A

I
I
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1

I
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SOEO

I

I
\.J

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Row
B

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I

\

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I
I
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I
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I
I
I
I
I
I
I Half Bit'l
Tap
I Point I
I B I

Figure 9. Generation of SOEO and SOE1 (Previous Display Line in VRAM Bank 0,
Current Line in VRAM Bank 1)

4.3 Video Interface Palette Control
The TLC34075's video output generation is based on sync and blanking signals from the TMS34020A, dot
clock inputs, and TLC34075 control register values. In turn, the TLC34075 provides to the TMS34020A
VCLK and SCLK signals that are used to generate video sync and blank signals (HSYNC, VSYNC,
HBLNK, and VBLNK).

4.3.1 V ideo Interface Palette Control Registers
The TLC34075 implements ten control registers. Four of these registers are used to program the palette
look-up table. The remaining six registers control the pixel data multiplexer, input clock select, VCLK and
SCLK divide ratios, SCLK relocation for SSRTs, and several other aspects of palette operation. These
registers are more thoroughly described in Section 5.
4.3.2 Accessing the Video Interface Control Registers
The RASDCD (U5) PAL maps the TLC34075's control registers into the TMS34020A's local memory
space starting at address DOOOOOOOh. Each register is mapped into 32 bits of the memory space. However,
since the TLC34075 has an 8-bit data bus, only the lower 8 bits of each long-word-aligned group of 32 bits
may be read or written to. Memory accesses with the most significant nibble equal to Dh enable the palette,
and latched address bits 8 through 5 are tied to the TLC34075's register select pins RS3 thru RSO,
respectively. Note that this addressing scheme aliases the palette's registers throughout the range
D0000200h through DFFFFFFFh.
4.3.3 TLC34075 Dot Clock Inputs
The TLC34075 has five possible dot clock inputs. Two of the five may be combined as a single
complementary, ECL-compatible clock input or used as two separate TTL-compatible clock inputs. For
a non interlaced resolution of 1280 by 1024, a dot clock input of about 108 MHz is required. This design
uses a UO-MHz ECL oscillator with complementary outputs running at a 5-V supply voltage for
1280-by-1024 displays. A 25-MHz TTL oscillator is used for 640-x-480 displays.
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10-71

4.4 Resetting the TMS34020A
The RESET (U38) PAL uses a state machine to ensure that the local reset signal (LRESET) meets the
TMS34020A's reset requirements during active operation. Of the 16 states, the first four ensure that a reset
pulse has a minimum length of four LCLKs to prevent reset due to noise on the HRS input. The state
machine starts at state 0 and advances to state 1 if its HRS (hardware reset) input is active when its
LCLK<1> input falls. The state machine progresses through states 2 and 3 to state 4 if the HRS input
remains active (if HRS goes inactive during any of the first 4'states, the state machine returns to state 0
without asserting LRESET). Once the state machine reaches state 4, LRESET is asserted until the state
machine reaches state 15 (12 LCLK cycles). If HRS is still asserted when state 15 is reached, the state
machine remains in state 15, with LRESET asserted, until HRS is released. The state machine then returns
to state O.
This state machine timing exceeds the minimum LRESET active time required by the TMS34020A for
reset after a power-on reset has been performed. The power-on reset, however, must be over 3 times the
reset pulse length attainable using a 4-bit counter as described above. An external circuit must ensure that
HRS is asserted cleanly at power-on for at least the minimum power-on reset time as described in the
TMS34020A data sheet.

4.5 Resetting the TLC34075
Power-on reset of the TLC34075 is accomplished automatically by internal circuitry. An operating reset
of the TLC34075 is effected by writing all ones to the TLC34075 register select (RS<3:0» lines and then
causing a low-to-high transition on the WR input. In this design, these actions occur as follows: when the
RESET (U38) PAL asserts the LRESET signal, the LTCHDCD (U4) PAL drives LDAT<8:5> high and
pulses its PALETWR output low while LCLKl is high. No circuitry is needed to special-case the data inputs
during the hardware reset, as the TLC34075 ignores its data bus when RS<3:0> are all high.

5 PROGRAMMING THE TLC34075 REGISTERS
This section describes several of the TLC34075 's control registers. Included are the general control register,
the input clock selection register, the output clock selection register, the multiplexer control register, and
the palette programming registers. See the TLC34075 data sheet for details on the registers not described
herein.

5.1 General Control Register
The general control register allows selection of several attributes of the outputs to the monitor as well as
the special nibble mode (used in systems with distributed 16-bit-wide pixel buses) and SCLK pulse
relocation. The polarities of the horizontal and vertical sync outputs are programmable; a 7.5-IRE pedestal
and "sync on green" are also selectable. Table 1 describes the bit fields of the general control register. The
general control register appears in the memory map at DOOOOI00h.

10-72

Table 1. TLC34075 General Control Register
GENERAL CONTROL REGISTER BIT

FUNCTION

7

6

5

4

3

2

1

0

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

1

HSYNCOUT active high

X

X

X

X

X

X

0

X

VSYNCOUT acrtive low

X

X

X

X

X

X

1

X

VSYNCOUT active high

X

X

X

X

X

0

X

X

Split shift register transfer disable

X

X

X

X

a

1

X

X

Split shift register transfer enable

X

X

X

X

a

X

X

X

Special nibble mode disable

X

X

X

X

1

a

X

X

Special nibble mode enable

X

X

X

a

X

X

X

X

a-IRE pedestal

X

X

X

1

X

X

X

X

7.S-IRE pedestal

X

X

a

X

X

X

X

X

Sync disable

HSYNCOUT active low

X

X

1

X

X

X

X

X

Sync enable

X

0

X

X

X

X

X

X

Reserved

X

1

X

X

X

X

X

X

Reserved

0
1

X

X

X

X

X

X

X

MUXOUT low (default)

X

X

X

X

X

X

X

MUXOUThigh

5.2 Input Clock (Dot Clock) Selection
Input clock selection is based on the required display resolution and the frequencies of the available
oscillators. The nO-MHz oscillator on the complementary inputs of the TLC34075 is selected by writing
8h to the input clock selection register (at memory location D0000120h). Note that the TLC34075 does not
require an active clock to access the control registers.

5.3 SCLK and VCLK Divide Ratio Selection
SCLK and VCLK divide ratios are selected via the output clock selection register. The SCLK divide ratio
determines how many pixels are available on the TLC34075's pixel inputs for each SCLK pulse. The SCLK
divide ratio depends on the number of input bits used on the pixel bus (this application uses all 32 bits) and
the number of bits per pixel. For a pixel size of 8 bits and a 32-bit-wide pixel bus, the SCLK divide ratio
must be 4. Similarly, for a pixel size of 2 bits and a 32-bit-wide pixel bus, the SCLK divide ratio must be
16. The TLC34075 provides power-of-two SCLK divide ratios between 1 and 32, inclusive. An additional
option holds the TLC34075 SCLK output in the low state regardless of the sync, blank, and clock inputs.
The VCLK divide ratio is used to determine the frequency of the signal that the TMS34020A uses to
generate sync and blank signals. To reduce the RF noise generated by the board, the VCLK divide ratio is
generally chosen to give the lowest possible frequency at which it is possible for the TMS34020A to
produce proper sync and blank timings. The TLC34075 provides power-of-two VCLK divide ratios
between 1 and 32, inclusive. An additional option holds the TLC34075 VCLK output in the high state
regardless of the sync, blank, and clock inputs.
The SCLK and VCLK divide ratio selections are programmed as a six-bit value in the output clock selection
register, which is mapped to memory location D0000140h in this application. The output clock selection
register programming values are listed in Table 2.
Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

10-73

Table 2. TLC34075 Output Clock Selection Register Programming Values
SCLK DIVIDE RATIO

VCLK
DIVIDE
RATIO

1
2
4
8
16 .
32

1
OOh
08h
10h
18h
20h
28h

2
01h
09h
11 h
19h
21h
29h

4
02h
OAh
12h
1Ah
22h
2Ah

8
03h
OSh
13h
1Sh
23h
2Sh

16
04h
OCh
14h
1Ch
24h
2Ch

32
OSh
ODh
15h
1Dh
25h
2Dh

5.4 Multiplexer Control Programming
The multiplexer control register determines how the TLC34075 uses the input data. The number of bits per
pixel and the number of bits physically connected to the pixel inputs of the TLC34075 are specified by this
register. Each valid multiplexer control register value implies an SCLK divide ratio. The valid multiplexer
control register values for this implementation are listed in Table 3. The multiplexer control register appears
in the memory map at D0000160h.

Table 3. Suggested Multiplexer Control Register Values
for This Implementation
NUMBER OF
BITS PER PIXEL

MULTIPLEXER CONTROL
REGISTER VALUE

1
2
4
8

13h
17h
18h
1Eh

5.5 Accessing the Palette Color Look-Up Tables
The TLC34075's palette look-up tables are accessed by writing the address of the look-up table entry to
a palette read address register or palette write address register (D0000060h and DOOOOOOOh, respectively),
then reading or writing the palette data register (D0000020h) three times (once each for red, green, and
blue). After the three reads or writes, the palette read address register or palette write address register is
autoincremented. The TLC34075 also has a pixel mask register (D0000040h) that allows incoming pixel
values to be masked.

5.6 Suggested Values for TMS34020A and TLC34075 Registers
Table 4 shows the suggested TMS34020A and TLC34075 register values to use with a Mitsubishi Diamond
Scan monitor and the hardware described. Video timing registers (addresses COOOOOOOh to C0000070h)
may need to be recalculated for other monitors. Note that the DPYCTL values for a 640-by-480 display
at one or two bits per pixel do not use SSRTs. They implement non packed frame buffers; the remainder
implement packed frame buffers and use SSRTs.

10-74

Table 4. Suggested TMS34020A and TLC34075 Register Values
for Use With a Mitsubishi Diamond Scan Monitor
REGISTER

VESYNC
HESYNC
VEBLNK
HEBLNK
VSBLNK
HSBLNK
VTOTAL
HTOTAL
DPYCTL
CON FIG
PSIZE
DPYSTL
DPYSTH
DINCLO
DINCHI
DPYMSK
GENCTL
INCLK
OUTCLK
MUXCTL
REGISTER

VESYNC
HESYNC
VEBLNK
HEBLNK
VSBLNK
HSBLNK
VTOTAL
HTOTAL
DPYCTL
CON FIG
PSIZE
DPYSTL
DPYSTH
DINCLO
DINCHI
DPYMSK
GENCTL
INCLK
OUTCLK
MUXCTL

ADDRESS

COOOOOOOh
COOOOO10h
COOOOO20h
COOOO030h
COOOO040h
COOOOO50h
COOOOO60h
COOOOO70h
COOOOO80h
COOOO1AOh
COOOO150h
COOOO200h
COOOO210h
COOOO240h
COOOO250h
COOOO2EOh
DOOOO100h
DOOOO120h
DOOOO140h
DOOOO160h
ADDRESS

COOOOOOOh
COOOOO10h
COOOOO20h
COOOOO30h
COOOO040h
COOOOO50h
COOOOO60h
COOOOO70h
COOOOO80h
COOOO1AOh
COOOO150h
COOO0200h
COOO0210h
COOOO240h
COOOO250h
COOOO2EOh
DOOOO100h
DOOOO120h
DOOOO140h
DOOOO160h

1280 x 1024 x 8

0OO2h
0010h
0022h
0033h
0422h
OOD3h
0426h
OOD7h
F047h
ODOAh
0OO8h
0800h
OOOOh
2800h
OOOOh
OOFFh
87h
08h
1Ah
1Eh
640 x 480 x 8

0OO2h
0OO6h
0018h
001Ah
01F8h
OOBAh
01F9h
OOCOh
F047h
OOOAh
0008h
OOOOh
OOOOh
1400h
OOOOh
OOFFh
87h
01h
12h
1Eh

1280 x 1024 x 4

0OO2h
0010h
0022h
0033h
0422h
OOD3h
0426h
OOD7h
F047h
ODOAh
0OO4h
OOOOh
OOOOh
1400h
OOOOh
OOFFh
87h
08h
1Bh
1Bh
640x480x4
0OO2h
0OO6h
0018h
001Ah
01F8h
OOBAh
01F9h
OOC1h
F047h
ODOAh
0OO4h
OOOOh
OOOOh
OAOOh
OOOOh
OOFFh
87h
01h
13h
1Bh

1280 x 1024 x 2

0OO2h
0010h
0022h
0033h
0422h
OOD3h
0426h
OOD7h
F047h
ODOAh
0OO2h
OOOOh
OOOOh
OAOOh
OOOOh
OOFFh
87h
08h
1Ch
17h
640 x 480 x 2

0002h
0OO6h
0018h
001Ah
01F8h
OOBAh
01F9h
OOBFh
FOO7h
ODOAh
0002h
OOOOh
OOOOh
0800h
OOOOh
OOFFh
83h
01h
14h
17h

Implementation of a 1280 x 1024 x 8 Display Using the TLC34075 VIdeo Interface Palette

1280 x 1024 x 1

0OO2h
0010h
0022h
0033h
0422h
OOD3h
0426h
OOD7h
F047h
ODOAh
0OO1h
OOOOh
OOOOh
0500h
OOOOh
OOFFh
87h
08h
1Dh
13h
640 x 480 x 1

0OO2h
0006h
0018h
001Ah
01F8h
OOBAh
01F9h
OOC1h
F007h
ODOAh
0001h
OOOOh
OOOOh
0400h
OOOOh
OOFFh
83h
01h
15h
13h
10-75

· 10-76

APPENDIX A

10-77

PART

REFERENCE

1O-!lF tantalum capacitor

C1, C2, C3, C4

o.1-!lF capacitor

CS, C6, C7, C8, C9, C10, C11, C12, C13, C14,
C1S,C16,C17,C18,C19,C20,C21,C22,C23,
C24, C2S, C26, C27, C28, C29, C30, C31, C32,
C33,C34,C35,C36,C37,C38,C39,C40,C41,
C42,C43,C44,CS3,CS4,CS5,CS6,CS7,CS8

QUANTITY

4
46

0.22-!lF capacitor

C45, C46, C47, C48, C49, CSO, C51

0.33-!lF tantalum capacitor

CS2

1

0.1-!lF capacitor

CS9, C60, C61, C62

4

Ferrite bead Fair Rite Products 3274301112

L1, L2, L3,L4, LS, L6

6

DB9 connector

P1

1

DB 15 connector

P2

1

7

4.7-kQ resistor

R1

1

7S-Q 1% resistor

R2,R3,R4

3

S23-Q 1% resistor

R5

1

220-Q resistor

R6,R9

2

330-Q resistor

R7,R8

2

33-Q resistor

R10,R11

2

100-Q resistor

R12

1

RSIP1, RSIP2, RSIP3, RSIP4

4

U1

1

33-Q

x

5 Isolated Resistor Network

TMS34020AGBL-40
40-MHz TTL oscillator

U2

1

74AS841

U3

1

TIBPAL20L8-7

U4,U5

2

TMS44C256-10SD

U6,U7,U8,U9,U10,U11,U12,U13

8

TMS44C2S1-10SD

U14,U15,U16,U17,U18,U19,U20,U21,U22,
U23,U24,U25,U26,U27,U28,U29

16

TLC3407S-110

U30

1

2S-MHz TTL oscillator

U32

1

110-MHz ECL osCillator GED LM1400E50
series or CTI K1149BA series

U36

1

64-MHz TTL oscillator

U37

1

TIBPAL 16R4-25

U38

1

10-78

Decode Logic
UWE
UTR/OE
USF
URAS
ALTCH
GSPBL
LCLK1
LRESET

RAM Arrays
WE
TR/OE
SF
PALETRD
PALETWR
SFLAG
LDAT(O:31f
MAD(O:8f

ROWCOL(O:8J CAS(O:3f
UCAS(O:3f
RAS(O:2f
SOE1
DAT(O:31f
321
SOEO
32

31

TMS34020A
LRESET

VCLK

ALTCH
URAS
UWE
UTR/OE
USF
GSPHS
GSPVS
GSPBL
DAT(O:31f
ROWCOL(O:8f
LCLK(O:1f
UCAS(O:3f

Reset Control

~

HRS

.I

ILCLK1

LRESET

:

4

~

32.

PXD(O:31f

L--

32
TLC34075
PALETWR
PALETRD
GSPHS
GSPVS
GSPBL
SFLAG

32

Figure A-1. System Block Diagram

(0

-~

WE
SF
SCLK
TR/OE
MAD(O:8f
CAS(O:3f
RAS(O:2f
DAT(O:31f
SOE1
SOEO

I DAT(O:31f
LDATio:31f

PXD(O:31f

VCLK
SCLK

VCC

%
o
C1

IC5

IC6

I C7

_I?S

_IC9

IC10

-r

IC11

IC12

IC13

IC14

IC1S

IC16

IC17

IC18

IC19

.±.. 10!-lF ~.1 !-lF~.1!-lF~.1 !-l'J!.1 !-lF~.1 !-IF_~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~1!-lF

T TANT I

I· I

I

I

I

I

1

I

I

I

I

I· I

I

1

C4

+ 10!-lF

T TANT.
VCC

C2

C20

C21

C22

C23

C24

C25

C27

C26

C28

C29

C31

C30

C32

C34

C33

C35

.±.. 10!-lF ~.1 !-lF~1!-lF~.1 !-lF~.1 !-lF~.1!-lF~.1 !-lF~.1 !-l~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 !-lF~.1 flF~1!-lF J-.0.1!-lF

TTANTI

I

I

I

T I III I

I

I

I

I
Vcc

-=C3

C37

C36

C38

C39

C41

C40

C42

C43

C44

.±.. 10f!F J!.1 f!~.1 f!FJ-.0.1 f!~0.1 f!~.1 f!FJ!.1 fl~0.1 f!~.1 f!'J.!.1 flF

T~I

I I I 1I I I I T
Vce
I

C45

I C46

I C47

I C48

I C49

I

coo

I C51

~.22 f!~.22 f!~.22 f!~.22 f!~.22 f!~.22 f!~.22 f!F

T I

I

+ 5 VDC PULLUP

III I

T

-=-

Vce

~ :;'"

.-----------«

PULLUPO

Figure A-2. Power Conditioning

>

I

I

T

DAT 0:31

Ul

~
-W~
~
~
..m.....:

flOE
HOST

Res~

RWmTE

!=
!=
:ru=
~

~

~
~
""""'ElL-

~
~
~

~

-'pfT,o

iri'6~

T,tRi2

~
..:.;.::::-

.2.!L.
~

/

..ELL
..!!1L
..!:!.!L

~
~

.!LK2

=
ClK40

N3

U2

I

HA31
HA30
HA29
HA2S
HA27

HA26
HA25
HA24
HA23
HA22
HA21
HA20
HA19
HA18
HA17
HA16
HA15
HA14

HA13
HA12
HAll
HAlO
HA9
HAS
HA7
HA6
HAS
H9S3
HBS2
HBSl
HBSO
HROY

REStT

ClKIN

OUT 8

~

40-MHZ TTL OSC
PUlLUPO

~

~
M3

VClK

RmT

K3

A12

{-

Dm"1

LA031
LA030
LA029

SClK

LAD22
LAD21
LAD20
LAD19
LAD1S
LAD17
LAD16
LAD15

LAD14
LA013
LAD12
LADll
LAD10
LAD9
LADS
LAD7
LADS
LAD5
LAD4
LAD3
LAD2
LADl
LADO
RCA12
RCA11
RCA10
RCA9
RCAS

Arn:H

=

CASlj
~
~

O'OOOT
DDIN

WE

!'IT
IW

m

CAMD

llTZrnl

~

--IlL

EMUO

DAT22
DAT21
DAT20
OAT19
DAn 8
OATH
OAT16
OAT15
DAT14
DAT13
DAT12
OAT11
DAT10
DAT9
DATS
DAT7
DATS
OATS
DAT4
DAT3
DAT2
DATl
DATO

Graphics
System

Processor

~

ROWr.Ol O:S

~
69
C9

6USFLT
I'{l'MD
lRDY

RSYIIIC
V'S'i'm:
C9CFJr

ROWCOlS
ROWCOl7

ROWCOl6
ROWCOl5
Rnwr.ClI4
RnWCOl3
ROWCOL2
ROWCOll
ROWCOlO

fM--.
lCLKO

SF

:=.'::

H13
H14
K15
l15
M15
N15
M14
A13
B12
Bl'
615
014
D15
E15
F14
G13
H15
J15
J13
K14
l14
l13
P1S

RCA7 Al0
RCA6 A9
RCAS I RR
RCA4 1;::7
RCA3 A7
RCA2 A6
B7
RCAl
RCAO
lClKl Hl
LCLK2 H3

mm

EMU2
EMU3
EMUl

>

OAT31
OAT30
OAT29

LA02S In" . nAT?R
LAD27 E13 DAT27
LAD26 C15 DAT26
LAD25 E14 DAT25
LAD24 F13 DAT24
LAD23 G15 DAT23

CAST
VClK

Bll
C11
A14

01
Cl
E3
02
91

'Trn

1JRAS

'UCliS1l
'UCAST
lJCAS2
LJCi'\S3

~

'>

URAS

'>

0ClIS 0:3

'>

)

,1

'\.......r

~

OWl':
A5 1J'TI'!l:l't
B2

C6

'>

'J

lClKl

A'

I;::'",T~·

OWl':
~n

USF

USF

~

">

>

~
J2

1*+

J:.
-

~

P ;-;2

A4==
65 "GSl'VS
A3 l!SI'll[

~

GSl"FIS
~

~

'>

>

'>

TMS34020AG6l-40
PUlLUP

Figure A-3. Graphics System Processor Connection
10-81

~

Series Termination

I\)

IROWCOL 0:8
ROWCOLO
ROWCOLl
ROWCOL2
ROWCOL3
ROWCOL4

1~
3
5
7
9

MAD(O:S( ::::::
2

•

6
8
10

MADO
MADl
MAD2
MAD3
MAD4

....:...:..;.. 33Q
ROWCOL5
ROWCOLS
ROWCOL7
ROWCOL8

I

>

0Tl1IQE

<

DAT 0:31

lI-:

DAT24
DAT23

DAT3
DAT2
DAn
DATO

1

=

=

3
5
7
9

2
3
4
5
6
7
8
9
10
11
13

Dl
D2
D3
D4
05
D6
D7
D8
D9
Dl0

2
4
6
8
10

MAD5
MAD6
MA07
MAD8

DAT8 1
DAT7 2
DAT63
DATS 4
=5
=6
WE 7
TRiO!' 8

06
07
08
09
010

23
22
21
20
19
18
17
16
15
14

U4
11
12
13

I.

01
02
03

04

15
05
16
06
17
07
18
08
SIlT 10 19
110
I"AIT'I'WI! 11
111
LCLKl13
112
~ 113
- R 1,.
20L8-7
LTCHDCD.ABL

=9

TRi'OE

TRi'OE

=
=

CAS 0:3

-{

CAST
CAS2

::::::

~

WE

WE

LDAT\0:31j;>

US
01
02
03
04
05

LDAT31
LDAT30
LOAT29
LDAT28
LDAT24
LDAT23
LDAT3
LDAT2

LDATl
LDATO

~gc

lJRAS

LCLK1

~33Q

.....;..;...;.. 33Q

74AS841

1=

2
4
6
8
10

U3
DAT31

DAT30
DAT29
DAT28

<

lJCAST
lJCAS2
0CAS3
UWE

>-

..!!§.!!1

1~

lJCASO

"-

>

OWE

3
5
7
9

Qm/Ot

OCAS 0:3

I

1

22
21
20
19
18
17
16

I'AITTim"

LDAT31 1
LDAT30 2
LDAT29 3
LDAT28 4
LOAT24 5
LDAT23 6
LDAT3 7
LDAT2 8
LDATl 9
LOATO 10

11
12
13

rom(0:2(
01

14

02
15
03
16
O.
17
05
18
06
19
07
110
="
08
111
SF 13
112
rn:ASl)" ,.
lJRAS 23 113
11.
20L8-7
RASDCD.ABL

22
21
20
19
18
17

~:

~

1
3

"""'"

~

'V'

S
7

"""""""
SIlT
PALUEN

~4 2

~bi

II

4
6

~")
-"iF

10

USF

>

SF

>

33Q

1mET

=

LDAT8
LDAT7
LDAT6
LDATS
SFLAG
SFLAGEN
'TWl'I

1mET

::::::

=

>

I'AITTim"

::::::

SFLAG

.• =

I'Al:EiWR

1:RESET

1=

I

>

ro

DRAM BANKO

I RAS(O:3f

DAT(O:31f

DAT(O:31L

I MAD(O:8f

MAD(O:8f

'"

I CAS(O:3f
I WE

RAS(O:3f
CAS(O:3f
WE
VRAM BANKO

ro....

'"

'- -

MAD(O:8f
RAS(O:3f

\..

I
I

TR/OE

I

SCLK

DAT(O:31f

--

SF

SOEO

f---

CAS(O:3f
WE

PXD(O:31f

I'

PXD(O:31r

SF
TR/OE

---

SCLK

~

VRAM BANK 1

......

'-

~

DAT(O:31f
MAD(O:8f

\..

RAS(O:3f

\..

SOE1

l-

CAS(O:3f
'--

WE

PXD(O:31f

SF
TR/OE
SCLK

I
I

SOE1
SOE1
SOEO

SOEO

Figure A-S. RAM Array Block Diagram

10-83

......

l'
00
~

<:DAT 0:31

<

i

MAD 0:8
U6
MADO
MAD1

MAD2
MAD3
MAD4

MADS
MADS
MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
CASO 2
WE
8
1

~...1.L

AO
Al

A2
A3
A4
AS
A6
A7
A8

6
3
4

DATO
DA"
DAT2
DAT3

MADO
MADl
MAD2
MAD3
MAD4
MADS
MAD6
MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
CAST 2

!lAS

CAS
W

-~

G

~...1.L

TF
TMS44C256-10SD

~

Ul0

U8
DOO
DOl
D02
D03

AO
Al

A2
A3
A4
AS
A6
A7
A8

DOO
DOl
D02
003

6
3
4

DAT8
DAT9
DATlO
DAT11

MADO
MADl
MAD2
MAD3
MAD4
MADS
MADS
MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
CAS2 2
WE 8
1

!lAS

CAS
W
G

~...1.L

TF
TMS44C2S6-10SD

AO
Al

A2
A3
A4

12
DOO
DOl
002
003

6 ~AT16
7 DAT17
3 nAT,"
4 DAT19

AS
A6
A7
AS

MADO
MAo1

MAD2
MAD3
MAD4
MADS
MADS
MAD7
MAD8
=
CAS3

!lAS

CAS
W

WE

G

11
12
13
14
16
17
18
19
20

9
2
8
1

~...1.L

TF
TMS44C256-10SD

AO
Al

A2
A3
A4
AS
A6
A7
AS

DOO
DO!
002
003

6
7
3
4

DAT24/
OAT';

DAT26-~

DAT27

!lAS

CAS

w
G

TF
TMS44C2S6-10SD

J

< - """,1"",/ ~

!

I

J7
MADO
MAD1
MAD2
MAD3
MAD4
MADS
MAD6
MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
CASO 2
WE
8
1

~...1.L

AO
Al

A2
A3
A4
A5
A6
A7
AS

DOO
DOl
002
D03

6
7

3
4

!lAS

CAS
W
G
TF
TMS44C2S6-10SD

DAT4
OATS
DAT6
DAT7

MADO
MADl
MAD2
MAD3
MAD4
MADS
MAD6
MAD7
MAD8

11
12
13
14
16

17
18
19
20

=9
=2
8

"""

I~
-"'~

AO
Al

A2
A3
A4

DOO
DOl
D02
D03

6
7

3
4

AS
A6
A7
AS

!lAS

CAS
W
G
TF

DATl2
DATl3
DAT14
-DATl5

MADO
MADl
MAD2
MAD3
MAD4
MADS
MADS
MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
=2
WI="
8
1

~...1.L

TMS44C256-10SD

Figure A-5. Program Memory

AO
Al

A2
A3
A4
AS
A6
A7
AS

i

U13

U11

J9

6
DOC _7
DOl 3
D02 4
D03

!lAS

CAS
W
G
TF
TMS44C256-10SD

DAT20
DAT21
DAT22
DAT23

MADO
MADl
MAD2
MAD3
MA04
MAD5
MADS

MAD7
MAD8

11
12
13
14
16
17
18
19
20

=9
n;"" 2
we 8
1

~...1.L

AO
Al

A2
A3
A4
AS
A6
A7
AS

DOO
DOl
D02
D03

6
7
3
4

!lAS

CAS
W
G
TF
TMS44C256-10SD

OAT"" '

DAT29-~
OJT""
JAT31

I

<

DAl

<
~.
--'#!:l' 25 AD

•

D-~

~

A7

M

M
M
M

)16
DOD I 1? DATO

D01~

D02
D03

AD
MA

AD
Al

~

A2

A

A3

U1S
M
M

DOD
DOl
D02
D03

A
A

~M
AS
A6
A7
AS

M
M

=
=

RASO

M

M

4

=
=

PXDS
PXD9
PXD10
PXDll

AD
Al
A2
A3

OSF

RASO

DOD
DOl
D02
D03

M
AS
A6
A7
AS

W

SDOD
SDOl
51': SD02
SC SD03

TMS44C251-1DSD

A3

AS

OSF

W

~

A2

U2D
DOO
DOl
D02
DQ3

AS
A6
A7

'i:J

1=(0'31>

AD
Al

=
=

OSF

I-zz-

W

TRG SDOO 9
DSF SDOl lD
51': SD02 56
SC SD03

TMS44C25l-l0SD

TMS44C2S1-l0SD

15

U17

U19

AD
Al
A2
A3
A4
AS

2.

AO
Al
A2
A3
A4

.MADl> 18

I~

TRGSDOO
DSF SD01
51': SD02
SC SD03 6

PXD24

PXD2S
PXD26
PXD27

TMS44C251-l0SD

GBiii>---~
~
~

~r

..MAll2

A7

~

M

OSF

I=-

~~"o,
51':
SCLK

AS

_11ASl! 1A

rI

=

OSF

=
W

pyn,

SD02 IlL.PXill'
SC SD03

TMS44C25l-l0SD

MA

M

A7

~ SDOO I 0

4

DOO
DOl
D02
D03

TRG SDOO

SE.....J....:: DSF SDOl
51': SD02
SC SD03

AO
Al
A2
A3
M
AS
AS
A7
AS

=
=

U2l
DOO
DOl
D02
D03

M
OSF

W

TRG SDOO
DSF SDOl
51': SD02
SC SD03

TMS44C25l-l0SD

Figure A-7. Frame Memory Bank 0

b

01

M

AO
Al
A2
A3

DOD
DOl
D02
D03

A4
AS

AS
A7

AS

=
=

OSF

W

TRGSDOO
DSFSDOl

Ja10

PX028

~ ~gg; IB-.l'XD31.
TMS44C25l-10SD

~
0>

OAT(O:31

IfA AO(D:81
 > »>

<3<3<3 <3
»>

P28
P27
P26
P25
P24
P23
P22
P21
P20

~

:"i
III

<3

>

OSCI81~
OlIT

"'I!g

~ '"

25-MHz TTL OSC

"'

P19

1

4

:!.'!.
1

--""-

PXLJ2
pXll

8

PXDO

2a

P18
P17
P16
P15
P14
P13
P12
Pll
Pl0
P9
P8
P7
P6
P5
P4
P3
P2
PI
PO b8(3d8~o8

COMP

~

C')N ..... O

cn(/)(f)(J)

cr:CCCCCC

"" '1 ~ ~

~

~

oa: 
[ PALETWR, PALETRD] )
0 , 0 ] ->
0 , 0 ];
0 , 0 , 0
0
0 ] ->
1
0 ];
0 , 0 , 1
0
0 ] ->
0 , 0 ];
0 , 0 , 0
1
0 ]i
0 , 0 , 1 , 0 , 0 ] ->
0 , 0 ]i
0 ] ->
0 , 0 , 0 , 0
0
0 , 1
0 , 0 ] ->
1 , 0 ]i
TEST VECTORS
"test action of LDAT8 •. 5 during reset
( [ DAT8, DAT7, OAT6, DAT5, ALTCH, !LRESET]
[ LDAT8, LOAT7, LDAT6, LDAT5])
0 , 1 , 0 ] -> [ 1 , 1 , 1
0 , 0 , 0
1 , 1 , 0 ] -> [ 1 , 1 , 1
0 , 0 , 0
0 , 0 , 1 , 0 , 1 , 0 ] -> [ 1 , 1 , 1 ,
0 , 1 , 0 , 0 , 1 , 0 ] -> [ 1 , 1 , 1 ,
0 , 1 , 0 ] -> [ 1 , 1 , 1 ,
1 , 0 , 0
0 , 1 , 1 ] -> [ 0 , 0 , 0
0 , 0 , 0

->

1 ]i
1

1
1
1
0

];
]i
]i
]i
]i

TEST VECTORS
"test action of SFLAG, SFLAGEN
([ SRT, ALTCH, GSPBLNK] -> [ SFLAGEN, SFLAG])
[.x.,.x., 0 ] -> [ 0 , 0 ]i
[ 0 , 1 , 1 ] -> [ 0 , 0 ]i
" Non-SRT cycle, blank active
[ 0 , 0 , 1 ] -> [ 0 , 0 ]i
[ 0 , 1 , 1 ] -> [ 0 , 0 ]i
" SRT cycle, blank active
[ 1 , 1 , 1 ] -> [ 0 , 0 ]i
[ 1 , 0 , 1 ] -> [ 1 , 0 ]i
" SRT cycle, altch low
" Altch high at end of SRT
[1
1
1] -> [ 1 , 1 ]i
[ 0 , 1 , 1 ] -> [ 1 , 1 ]i
" Beginning of next cycle
[ 0 , 0 , 1 ] -> [ 1 , 1 ]i
" Altch falls on next cycle
[0
0, 0 ] -> [ 0 , 0 ]i
" End of blanking

10-91

TEST VECTORS
"check LOAT8 •• 5 when not resetting
( [ OAT8, OAT7, OAT6, OAT5, ALTCH, !LRESET] ->
[ LDAT8, LOAT7, LOAT6, LDAT5] )

, 0 , 0 ,
, 0 , 0 ,
[.x.,.x.,.x.,.x.,
[ 0 , 0 , 0 , 1 ,
[ 0 , 0 , 0 , 1 ,
[ 0
[ 0

,
,

0
0

[.X.,.X.,.X.,.X.,

,

1
0
0

,
,

1
1
1

-> [0,0,0,0]
-> [0,0,0,0]
-> [0,0,0,0]

1
0
0

,
,
,
,
,
,

1
1
1

-> [0,0,0,1)
-> [0,0,0,1)
-> [0,0,0,1)

1
1
1

-> [0,0,1,0)
-> [0,0,1,0)
-> [0,0,1,0]

1
1
1

-> [0,1,0,0)
-> [0,1,0,0)
-> [0,1,0,0)

1

-> [1,0,0,0]
-> [1,0,0,0)
-> [1,0,0,0)

[ 0
[ 0

,
,

0
0

,
,

1
1

,

0
0

,
,

1
0
0

[ 0
[ 0

,

1
1

,

,

0
0

,
,

0
0

,
,

1
0
0

[ 1
[ 1

,

0
0

,

0

,

1
0
0

[.X.,.X.,.X.,.X.,

,

[.X.,.X.,.X.,.X.,

,

0
0

,
,

, 0 ,

[.X.,.X.,.X.,.X.,

END

10-92

- LTCHDCD

,

,

,
,
,

, 1
1

module

"
"
"
"
"
"

- RESET;

title

Part
Reference
Revision
Date
By
Company

TIBPAL16R4-25
U38

*

1/8/91
Bob Milhaupt
Texas Instruments, Inc.

'RESET'

" RESET CONTROL PAL®(RESET)

""

The primary function of RESET is to filter spurious noise from the
HRS (Hardware Reset) input and provide a local reset signal (LRESET) which
meets the TMS34020's reset timing specs. This reset mechanism is
.
implemented using a state machine.
It requires that HRS remain active for
four successive LCLKI edges. Following this condition the state machine
then goes into a closed 11 state loop. The last state waits for HRS to be
removed before returning to state O.
LRESET is held inactive in states 0
through 3, and active during states 4 through 15. The HRS input must be
held active at power-up long enough to satisfy the TMS34020A power-up reset
timing requirements.

RESET device 'P16R4';
"Inputs
CLK
HRS
LCLKI

pin
pin
pin

1
5
9

pin
pin
pin
pin
pin
pin

19
12
17
16
15
14

"Hardware Reset

"Outputs
!LRESET
OCLKI
BITO
BIT 1
BIT2
BIT3

"Local Reset signal to 34020, logic
"Delayed LCLKI
"State Machine LSB
"State Machine MSB

"Declarations and Intermediate Variable Definitions

S11

[BIT3,BIT2,BITl,BITO];
"bOOOO;
"bOOOl;
"bOOlO;
"bOOll;
"bOlOO;
"bOlOl;
"bOllO;
"bOlll;
"blOOO;
"blOOl;
"bl0l0;
"blOll;

S12
513
514
S15

"bllOl;
"blllO;
"bllll;

S

SO
Sl
S2
S3
54
S5
S6
57
58
59
510

"b1100;

EQUATIONS
OCLKI

!LCLKl;

10-93

LRESET

(S == S4 ) # (5
S7 ) # (8
(S
S10) # (S
(S
(S
S13) # (S

STATE_DIAG~ S

STATE
STATE
STATl';
STATE
STATE
STAn
STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE
END _RESET

10-94

SO:
SI:
52:
S3:
S4:
S5:
S6:
S7:
S8:
S9:
S10:
SII:
S12:
S13:
S14:
S15:

IF
IF
IF
IF

(

HRS )
(
H~S )
(
HRS )
( . HRS. )

GOTO S5;
Go':{.'o S6;
GOTO S7;
GOTO S8;
GOTO S9;
GOTO S10;
GOTO S11;
GOTO S12;
GOTO S13;
GOTO S14;
GOTO S15;
IF ( !HRS )

S5 )
S8 )
Sl1)
S14)

#
#
#
#

(S
(S
(S
(S

THEN
THEN
THEN
THEN

Sl
S2
S3
S4

S6 )
S9 )
S12)
S15)
ELSE
ELSE
ELSE
ELSE

:

#
#
#

SO;
SO;
SO;
SO;

THEN SO ELSE S12;

module

_RASDCD;

"
"
"
"
"
"
title

Part
Reference
Revision
Date
By
Company

TIBPAL20L8-7
U5

*

1/8/91
Bob Milhaupt
Texas Instruments, Inc.

'RAS and VRAM Control Decoder'

" RAS DECODE PAL®(RASDCD)

""

RASDCD performs RAS decoding for memory segmentation. Note that there is
, a significant degree of aliasing to reduce complexity and chip count of
the decoder.
LDAT31 •. 28 are used in decoding bank selects for RAM,
shadow ram, and palette memory mapping. LDAT24 and LDAT23 (in addition
to LDAT31 .. 28) are used select between VRAM bank 0, VRAM bank 1, and DRAM
bank 0 via the RASO, RAS1, and RAS2 signals, respectively. One device
select,PALETEN, is decoded to enable reads and writes of the 34075 Video
Interface Palette. status bits LAD<3:0> determine refresh and VRAM cycles.
These are also used in decoding the RAS signals. The SRT output decodes
" Shift Register Transfers. Other logic uses this signal to determine the
" end of the SRT cycle at which time the SFLAG input of the 34075 Video
" Interface Palette should be asserted. This relocates the first SCLK pulse
" as necessary when using Split Shift Register Transfers.

RASDCD device 'P20L8' ;
"Inputs
LDAT31
LDAT30
.LDAT29
LDAT28
LDAT24
LDAT23
LDAT3
LDAT2
LDATl
LDATO
!LRESET
SF
!CASO
JURAS

pin
pin
p~n

pl.n

p~n

pl.n
pin
pin
pin
pin
pin
pin
pin
pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;

13;
14;
23;

"outputs
!PALETEN
!RAS2
!RASl
!RASO
!SOECLR
!SRT
!SOEl
!SOEO

pin
pin
pin
pin
pin
p~n

pl.n
pin

15;
22;
21;
20;
19 ;
18;
17;
16;

Palette select
DRAM RAS
VRAM Bank 1 RAS
" VRAM Bank 0 RAS
" Internal feedback term

"
""
"
"

Serial Output Enable, Bank 1
Serial Output Enable, Bank 0

"Declarations and Intermediate Variable Definitions
REFRESH

!LDAT3

&

!LDAT2

&

LDAT1

&

LDATO

VTRANS

!LDAT3

&

LDAT2

&

!LDAT1

&

!LDATO

CTRANS

!LDAT3

&

LDAT2

&

!LDATl

&

LDATO

10-95

" OTHVTM decodes some other VRAM cycles where both VRAM banks must have
" active RAS signal: Write-Mask Load and color-Register Load
!LDAT3

&

LDAT2

&

LDAT1;

INTAREA

LDAT3

&

!LDAT2

&

LDAT1

&

LDATO

PALET

LDAT31

&

LDAT30

&

!LDAT29

&

LDAT28;

VBNKO

!LDAT31

&

!LDAT30

&

!LDAT24

&

!LDAT23;

VBNK1

!LDAT31

&

!LDAT30

&


(PALETEN,RAS2,RAS1,RASO,SOEO,SOE1,SOECLR,SRT])
II

check RAS decoding
[0,0,0,0,0,0,0,0,0,0,0,0,0,0]
[1,1,0,1,0,0,0,0,0,0,1,0,0,0]
[0,0,0,0,1,0,0,0,0,0,1,0,0,0]
[0,0,0,0,1,1,0,0,0,0,1,0,0,0]
[0,0,0,0,0,0,0,0,0,0,1,0,0,0]

" check assertion of RASO
[0,0,0,0,0,0,0,1,0,0,1,0,0,0]
[0,0,0,0,0,0,0,1,0,1,1,0,0,0]
[0,0,0,0,0,0,0,1,1,0,1,0,0,0]
[0,0,0,0,0,0,0,1,1,1,1,0,0,0]
[0,0,0,0,0,0,1,0,0,0,1,0,0,0]
[O,O,O,O,O,O,l;p,O,l,l,O,O,O]
[0,0,0,0,0,0,1,0,1,0,1,0,0,0]

-> [O,O,O,O,X,X,X,X];

-> [1,O,O,O,X,X,X,X];

-> [O,l,O,O,X,X,X,X];
-> [O,I,O,O,X,X,X,X];
-> [O,O,O,I,X,X,X,X];
->
->
->
->
->
->
->

[O,O,O,I,X,X,X,X];
[O,O,O,I,X,X,X,X];
[O,O,I,I,X,X,X,X];
(O,O,I,I,X,X,X,X];
[O,O,O,I,X,X,X,X];
[O,O,O,l,X,X,X,X];
[O,O,O,I,X,X,X,X];

" check assertion of RAS2 when address is 0 and interrupt fetch is given
[O,0,0,0,0,0,1,0,li1,l,O,O,O] -> [O,I,O,O,X,X,X,X];

10-96

II

II

II

II

II

II

II

check assertion of RAS1
[0,0,0,0,0,1,0,1,0,0,1,a,0,0]
[0,0,0,0,0,1,0,1,0,1,1,0,0,0]
[0,0,0,0,0,1,0,1,1,0,1,0,0,0)
[0,0,0,0,0,1,0,1,1,1,1,0,0,0)
[0,0,0,0,0,1,1,0,0,0,1,0,0,0)
[0,0,0,0,0,1,1,0,0,1,1,0,0,0]
[0,0,0,0,0,1,1,0,1,0,1,0,0,0]

-> [0,0,1,0,X,X,X,X];
-> [0,0,1,0,X,X,X,X);

-> [O,O,l,l,X~X,X,X];
-> [O,O,l,l,X,X,X,X);
-> [0,0,1,0,X,X,X,X);
-> [0,0,1,0,X,X,X,X];
-> [0,0,1,0,X,X,X,X];

°

check assertion of RAS2 when address is
and interrupt fetch is given
[0,0,0,0,0,1,1,0,1,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];
check assertion of RAS2
[0,0,0,0,1,0,0,1,0,0,1,0,0,0]
[0,0,0,0,1,0,0,1,0,1,1,0,0,0]
[0,0,0,0,1,0,0,1,1,0,1,0,0,0]
[0,0,0,0,1,0,0,1,1,1,1,0,0,0]
[0,0,0,0,1,0,1,0,0,0,1,0,0,0]
[0,0,0,0,1,0,1,0,0,1,1,0,0,0]
[0,0,0,0,1,0,1,0,1,0,1,0,0,0]
[0,0,0,0,1,0,1,0,1,1,1,0,0,0]

-> [O,l,O,O,X,X,X,X);
-> [0,1,0,0,X,X,X,X];
-> [O,l,X,X,X,X,X,X];
-> [0,1,X,X,X,X,X,X];
-> [O,l,O,O,X,X,X,X];
-> [0,1,0,0,X,X,X,X];
-> [O,l,O,O,X,X,X,X];
-> [0,1,0,0,X,X,X,X);

check assertion of RAS2 for a shadow of dram
[0,0,0,0,1,1,0,1,0,0,1,0,0,0] -> [0,1,0,0,X,X,X,X);
[0,0,0,0,1,1,0,1,0,1,1,0,0,0) -> [O,l,O,O,X,X,X,X];
[0,0,0,0,1,1,0,1,1,0,1,0,0,0] -> [O,l,X,X,X,X,X,X];
[0,0,0,0,1,1,0,1,1,1,1,0,0,0] -> [O,l,X,X,X,X,X,X];
[0,0,0,0,1,1,1,0,0,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[0,0,0,0,1,1,1,0,0,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[0,0,0,0,1,1,1,0,1,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[0,0,0,0,1,1,1,0,1,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];
check assertion of RAS2 for another shadow of dram
[1,1,1,1,1,1,0,1,0,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,1,0,1,0,1,1,0,0,0] -> [0,1,0,0,X,X,X,X];
[1,1,1,1,1,1,0,1,1,0,1,0,0,0] -> [0,1,X,X,X,X,X,X];
[1,1,1,1,1,1,0,1,1,1,1,0,0,0] -> [O,l,X,X,X,X,X,X];
[1,1,1,1,1,1,1,0,0,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,1,1,0,0,1,1,0,0,0] -> [0,1,0,0,X,X,X,X];
[1,1,1,1,1,1,1,0,1,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,1,1,0,1,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];
check assertion of RAS2 for another shadow of dram
[1,1,1,1,1,0,0,1,0,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,0,0,1,0,1,1,0,0,0] -> [O,l,O,O,X,X,X,X);
[1,1,1,1,1,0,0,1,1,0,1,0,0,0) -> [O,l,X,X,X,X,X,X);
[1,1,1,1,1,0,0,1,1,1,1,0,0,0] -> [O,l,X,X,X,X,X,X];
[1,1,1,1,1,0,1,0,0,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,0,1,0,0,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,0,1,0,1,0,1,0,0,0] -> [O,l,O,O,X,X,X,X];
[1,1,1,1,1,0,1,0,1,1,1,0,0,0] -> [O,l,O,O,X,X,X,X];

-

check assertion of SOEO, SOE1
[0,0,0,0,0,0,0,1,0,0,0,0,0,0)
[0,0,0,0,0,0,0,1,0,0,1,0,0,0]
[0,0,0,0,0,0,0,1,0,0,1,0,1,0)
[0,0,0,0,0,0,0,1,0,0,0,0,0,0)
[0,0,0,0,0,0,0,1,0,0,0,0,0,1]
[0,0,0,0,0,0,0,1,0,0,1,0,0,1]
[0,0,0,0,0,0,0,1,0,0,1,0,1,1]
[0,0,0,0,0,0,0,1,0,0,0,0,0,1]
[0,0,0,0,0,0,1,0,0,0,0,0,0,0]
[0,0,0,0,0,0,1,0,0,0,1,0,0,0]
[0,0,0,0,0,0,1,0,0,0,1,0,1,0]

simulate the sequence of the SRT, SSRT
II
"'"> [O,O,O,O,X,X,X,X];
Begin of SRT
-> [O,O,O,l,O,O,X,X];
-> [O,O,O,l,l,O,X,l);
-> [O,O,O,D,l,O,X,l];
II
-> [0,0,0,0,1,0,0,1];
Begin of SSRT
-> [0,0,0,1,1,0,0,0];
-> [0,0,0,1,1,0,0,0];
-> [0,0,0,0,1,0,0,0];
II
-> [0,0,0,0,1,0,X,0];
Data cycle
-> [O,O,O,l,l,O,X,O] ;
-> [O,O,O,l,l,O,X,O] ;

10-97

[0,0,0,0,0,0,1,0,0,0,0,0,0,0]
[0,0,0,0,0,1,0,1,0,0,0,0,0,0]
[0,0,0,0,0,1,0,1,0,0,1,0,0,0]
[0,0,0,0,0,1,0,1,0,0,1,0,1,0]
[0,0,0,0,0,1,0,1,0,0,0,0,0,0]
[0,0,0,0,0,1,0,1,0,0,0,0,0,1]
[0,0,0,0,0,1,0,1,0,0,1,0,0,1]
[0,0,0,0,0,1,0,1,0,0,1,0,1,1]
[0,0,0,0,0,1,0,1,0,0,0,0,0,1]
[0,0,0,0,0,0,0,0,0,0,0,0,0,0]
[0,0,0,0,0,0,0,0,0,0,1,0,0,0]
[0,0,0,0,0,0,0,0,0,0,1,0,1,0]
[O,O,O,O,O~O,O,O,O,O,O,O,O,O]

END _RASDCD

10-98

->
->
->
->
->
->
->
->
->
->
->
->
->

[O,O,O,O,l,O,X,O]:
[O,O,O,O,l,O,X,O]:
[0,0,1,0,0,0,1,0]:

" Begin of SRT

[O,O,l,O,O~l,X,l]:

[O,O,O,O,O,l,X,l]:
[O,O,O,O,O,l,X,l]:
[O,O,l,O,O,l,X,O]:
[O,O,l,O,O,l,X,O]:
[O,O,O,O,O,l,X,O]:
[O,O,O,O,O,l,X,O]:
[O,O,O,l,O,l,X,O]:
[O,O,O,l,O,l,X,O]:
[O,O,O,O,O,l,X,O]:

"

Begin of SSRT

" Data cycle

11-1

Contents
Page
Ordering Information ..................................................... 11-3
Mechanical Data .......................................................... 11-5

-

11-2

ORDERING INSTRUCTIONS

ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the
page heading regardless of package. The availability of a circuit function in a particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical
outline drawings shown in this section.
Factory orders for circuits described in this data book should include a four-part type number as shown in the following
example.

Example:

TL

598M

J

/8838

Prefix _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'
MUST CONTAIN TWO OR THREE LETTERS
SN .......... TI Special Functions or Interface Products
TL, TLE .......................... TI Linear Products
TLC ........... TI Linear Silicon-Gate CMOS Products
STANDARD SECOND-SOURCE PREFIXES
AD ................................. Analog Devices
ADC, LF, LM, LP, or MP ..................... National
LT or LTC .......................... Linear Technology
MC ....................................... Motorola
NE, SA, or SE .............................. Signetics
OP ........................................... PMI
RC, RM, or RV ............................ Raytheon
uA ................................ Fairchild/National
UC ....................................... Unitrode

Unique Circuit Description Including Temperature Range
MUST CONTAIN TWO OR MORE CHARACTERS
(From Individual Data Sheets)
Examples:

10
592
7757

34070
1451AC
2217-285

Package _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
MUST CONTAIN ONE OR TWO LETTERS
0, DB, OW, FK, FN, J, JD, JG, KC, KK, KV, LP, N, NS, NT, NW, P, PK, PW, U
(From Pin-Connection Diagrams on Individual Data Sheet)

MIL-STD-8838, Method 5004, Class 8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---<
Omit /883B When Not Applicable

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

11-3

ORDERING INSTRUCTIONS

Circuits are shipped in one of the carriers below. Unless a specific method of shipment is specified by the customer
(with possible additional costs), circuits will be shipped via the most practical carrier.
Dual-In-Line (J, JD, JG, N, NT, NS, NW, P)
- A-Channel Antistatic or
Conductive Plastic Tubing

Shrink Small Outline (DB)
- Tape and Reel
Thin Shrink Small Outline (PW)
- Tape and Reel

Plug-In (LP)
Plastic Bag
- Tape and Reel

Small Outline (0, OW)
- Tape and Reel
- Antistatic or Conductive
Plastic Tubing

Chip Carriers (FK, FN)
- Antistatic or Conductive
Plastic Tubing

Power Tab (KC, KK, KV)
- A-Channel Antistatic or
Conductive Plastic Tubing

Flat (U)
- Milton Ross Carriers

TEXAS

-'!1

INS1RUMENTS
11-4

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

0008, 0014, and 0016
plastic small-outline packages
Each of these small-outline packages consists of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
0008, 0014, and 0016
(16-pin package used for illustration)

Designation per JEOEC Std 30:
POSO-G8
POSO-G14
POSO-G16

4,00 (0.157)
3,81 (0.150)

9

8

5,21 (0.205) -j'4f------J>\
4,60 (0.181)
0,50 (0.020) x 45' NOM
0,25 (0.010)

I I
,

,

:r~

--,.I I.r

0,51 (0.020)
0,36 (0.014)
7' NOM
4 Places

Pin Spacing
1,27 (0.050)
(see Note A)
DIM
~

8

14

16

AMIN

4,80

8,55

9,80

(0.189)

(0.337)

(0.386)

A MAX

5,00
(0.197)

8,74

10,00
(0.394)

(0.344)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: C.
D.
E.
F.

Leads are within 0,25 (0.010) radius of true position at maximum material condition.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Lead tips to be planar within ±0,051 (0.002) exclusive of solder.

TEXAS

.J!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

11-5

MECHANICAL DATA

08008,08014,08016,08020, and 08024
shrink small-outline packages
These shrink small-outline packages consist of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
Designation per JEOEC Std 30:
POSO-G8
POSO-G14
POSO-G16
POSO-G20
POSO-G24

OB008, OB014, OB016, OB020, and OB024
(24-pin package used for illustration)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS
NOTES: A.
B.
C.
D.
E.

Leads are within 0,25 mm radius of true position at maximum material condition.
Body dimensions do not include mold flash or protrusion.
Mold or flash end protrusion shall not exceed 0,15 mm.
Interlead flash shall be controlled by TI statistical process control (additional information available through TI field office).
Lead tips to be planar within ±0,05 mm exclusive of solder.

~
DIM

8

14

16

AMIN

2,70

5,90

5,90

A MAX

3,30

6,50

6,50

BMAX

0,68

1,30

0,98

TEXAS .J!1

INSlRUMENTS
11-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

20

24

6,90

7,90

7,50

8,50

0,83

0,68

MECHANICAL DATA

DW016, DW020, DW024, and DW028
plastic small-outline packages
Each of these small-outline packages consists of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
DW016, DW020, DW024, and DW028
(20-pin package used for illustration)

i
10,65 (0.419)
10,15 (0,400)

r-

1'8888 f

Designation per JEDEC Std 30:
PDSO-G16
PDSO-G20
PDSO-G24
PDSO-G28

A11

20

I

7,55 (0.297)
7,45 (0.293)

~~~~1~~~~~~1~0

-1 t

~op7~~s

H

t - - - - I_ _

-r

2,65 (0.104)
2,35 (0.093)

t

0,30 (0.012)
0,10 (0.004)

_ _

I' 'I

J

0,785 (0.031)...
0,585 (0.023)

j

0.' ,0.""

< ".

~

~cD(
-or
~ \~

L

40

±4

\

0,490 (0.019)
0,350 (0.014)

0

0,320 (0.013)
0,230 (0.009)

'~'

9,0 (0.354)
,.,

,0''', ~

~I

r-.;

7 0 NOM
4 Places

/

1,:>7 (0.050)
0,40 (0.016)

1,27 (0.050) TP (see Note A)

~

24

28

16

20

AMIN

10,16
(DADO)

12,70

15,29

17,68

(0.500)

(0.602)

(0.696)

A MAX'

10,36
(00408)

12,90
(0.508)

15,49
(0.610)

17,88
(0.704)

DIM

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.

Leads are within 0,25 (0.010) radius of true position at maximum material condition.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed, 0,15 (0.006).
Lead tips to be planar within ±0,051 (0.002) exclusive of solder.

TEXAS

.JJ1

INSlRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

11-7

MECHANICAL DATA

FK020, FK028, FK044, FK052, FK068, and FK084
ceramic chip carrier
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid and
braze seal. These packages are intended for surface mounting on solder leads on 1,27 (0.050) centers.
Terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1 and 2.
FK020, FK028, FK044, FK052, FK068, AND FK084
(28-pln used for illustration)

Designation per JEDEC Std 30:
.
CQCC-N20
CQCC-N28
CQCC-N44
CQCC-N52
CQCC-N68
CQCC-N84

19

25

5

26

4
0,51 (0.020)
0,25 (0.010)

1r

Index Corner

~~~U

~ 0,51 (0.020)
0,25 (0.010)

1,14 (0.045)
~ 0,89 (0,035)

j

-I.. t

1,14 (0.045)
0,89 (0.035)
2,03 (0.080)
1,63 (0.064)

1,27 (0.050) T.P.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. See next page for A and B dimensions.

TEXAS ~

INSTRUMENTS
11-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

FK020, FK028, FK044, FK052, FK068, and FK084
ceramic chip carrier (continued)
JEDEC OUTLINE

NUMBER OF

DESIGNATIO Nt

TERMINALS

MIN

MAX

MIN

MAX

MS-004-CB

20

8,69 (0.342)

9,09 (0.358)

7,80 (0.307)

9,09 (0.358)

MS-004-CC

28

11,23 (0,442)

11,63 (0,458)

10,31 (0,406)

11,63 (0,458)

MS-004,CD •.

44

16,26(0.640)

16,76 (0.660)

12;58(0.495)

14,22(0.560)

,

."

MS-OQ4,CE
MS·004-CF

I

MS-004-CG

I

52

'.

68 .
···· •. 84

.....

B

A

18,78 (0.740)

19,32(0.760)

12,58 (0.495)

14,22 (0.560)

23,83 (0.938)

24,43 (0.962)

21,60 (0.850)

.21,80 (0.858)

28,99 (1,141)

29,59(1.164)

26,60 (1.047)

27,00 (1,063)

.. JEDEC outline apply.
t All dimensions and notes for the speCified

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 65$303 • DALLAS. TEXAS 75265

11-9

MECHANICAL DATA

FN020, FN028, FN044, FN052, FN068, and FN084
plastic J-Ieaded chip carrier
Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an
electrically nonconductive plastic compound. The compound withstands soldering temperatures with no
deformation, and circuit performance characteristics remain stable when the devices are operated in
high-humidity conditions. The package is intended for surface mounting on 1,27 (0.050) centers. Leads require
no additional cleaning or processing when used in soldered assembly.
FN020, FN028, FN044, FN052, FN068, and FN084
(20-PIN package used for illustration)

Designation per JEDEC Std 30:
S-PLCC-J20
S-PLCC-J28
S-PLCC-J44
S-PLCC-J52
S-PLCC-J68
S-PLCC-J84

0
1.10.18 (000?]®1 s®1 D-E®I

:....-IB

Gi±J (see Note 0)

~

D1 (see Nole B) - I t -

1.1018 (0.007)®1 s® 1 D-E®I

1.11 (0.002 IN./IN·ll s I

I

1 22 (0.048) 2 Places ......
1,07 (0.042)

@
j@
~ - ~

; [n

016--

z

•

l

0

•

.

r:l

/
[

~ iicg~
~~ L[J
UJ~
T
GIG
~GJ ~d
*:
o

t 1f;:C±J

-

z

-I

ri

(see Note C)

r:l.r1

3

2

1

ees

20

19

16

15 ]
14 ]

8
11

12

1

I:±l

A

-------f"

I \.:=:

TYP.

2 Sides (see Note E)

J

6
7

10

~,~~ :~~~~l

fi'

Seating Plane
(see Note B)

A

18 ]
17 ]

5

9

1 42 (0.056)
1,07 (0.042)

I

0
4

v

0.51 (0.020) R. Max

1

R.TYP

~

02, E2
(see Note F)

(see Note F)

1.27 (0.050) T.P

. I

4 Sides

BfJ

1r,."1::-0.:::38:--:(-;:-0.0:::'--::5)"@"'Ir:D~_E;:-;@=I

--±-I.10.38(0.015)®IF-G®1

(see Note C)

13

LW

."--' "--' "--' "--' "--'

-----.lI

0.51 (0.020) MIN.

(see Note C)

~,~~ :~:~6~l

*

'1Sh

(Includes Lead Finish)

SUM OF DAM BAR PROTRUSIONS
TO BEO,1S (0.007) MAXIMUM
PER LEAD

,

(see table on following page for additional dimensions)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: B. All dimensions conform to JEDEC Specification MO-047ANAF. Dimensions and tolerancing are per ANSI Y14.5M -1982.
C. Dimensio~s D, and E, do not include mold flash protrUSion. Protrusion shall not exceed 0,25 (0.010) on any side. Centerline of center
pin each side is within 0,10 (0.004) of package centerline by dimension B. The lead contact points are planar within 0,10 (0.004).
D. Datums ~ and ~ for center leads are determined at datum

I- H -I·

E. Datum ~ is located at top of leads where they exit plastic body.
F. Location of datums

I - A -I and ~ to be determined at datum ~.
I - C -I.

G. Determined at seating plane

TEXAS

-IJI

INSlRUMENlS
11-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

FN020, FN028, FN044, FN052, FN068, and FN084
plastic J-Ieaded chip carrier (continued)
JEDEC
OUTLINE

PINS

MO·047AA

20

MO·047AB

28

MO·047AF

84

NOTES A: All dimensions conform to JEDEC Specification MO-047ANAF. Dimensions and tolerancing are per ANSI Y14.5M -1982.
F: Determined at seating plane
C

1- -I·

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-11

MECHANICAL DATA

J014
ceramic dual·in·line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and lead frame. Hermetic
sealing is accomplished with glass. The package is intended for insertion in mounting hole rows on 7 ,62 (0.300)
centers. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in
the board during soldering. Tin~plated ("bright-dipped") leads require no additional cleaning or processing when
used in soldered assembly.
J014

Designation per JEDEC Std 30:
GDlp·T14

0,63 (0.025) R NOM

i+------1of- 7,87 (0.310)
7,37 (0.290)

~--.rr- 7,11 (0.280)

6,22 (0.245)

-1

~ I- 1 ,2~~~50)

~
.

105
90
0

0

0,51 (0.020) MIN

l

t

~--~~----~
Glass
............................r----:Sealant

5,08 (0.200) MAX

-Seating---------+---.t-,
Plane

14 Places ~~
0,36 (0.014)
0,20 (0.008)
14 Places

-.I

~

II

3,30 (0.130)
MIN

0,69 (0.027) MIN
14 Places

_J

~~ 0,58 (0.023)

0,38 (0.015)
14 Places
(see Notes B & C)

2,54 (0.100)
1,78 (0.070)
4 Places

Pin Spacing 2,54 (0.100) T.P.
(see Note A)

Falls within JEDEC TO-116 and EIA MO-001M dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
' - - - - - - - - - - NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area olthe lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS

~

INSTRUMENTS
11-12

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

J016, J018, J020, and J022
ceramic dual-in-line
These hermetically sealed dual-in-Iine packages consist of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. These packages are intended for insertion in mounting-hole rows
of 7,62 (0.300) centers for the J016, J018, J020, and 10,16 (0.400) centers for the J022, respectively. Once the
leads are compressed and inserted, sufficient tension is provided to secure the package in the board during
soldering. Tin-plated (bright-dipped) leads require no additional cleaning or processing when used in solder
assembly.
.
J016, J018, J020, and J022
(22-pin package used for illustration)

Designation per JEDEC Std 30:
GDIP-T16
GDIP-T18
GDIP-T20
GDIP-T22

M
~
,
.
"
.
".
"'
"
~.
(O':'::J~;~O) i 5'0I~"4~-x-20-0-)l,-1

~

~

~
105'
90'

1,27

- ....- - - - - - - - - - - - - - . - - . . . - - - -

'*

- - Seatlng__
Plane

-

...

22 Places
o 36 (0 014)
0,20
(0.008)
22 Places

4 Places
. .
Pin Spacing
2,54 (0.100) T. P.
(see Note A)

S~~I~~t

I

-U'

. ,
18 Places

l'.

0,584 (0.023)

22 Places
(see Notes B & C)

1,27 (0.050)
0,38 (0.015)
4 Places

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

~
PINS

16

22

C

MAX

MIN

MAX

MIN

MAX

19,18 (0.755)

19,94 (0.785)

7,37 (0.290)

7,87 (0.310)

6,22 (0.245)

7,62 (0.300)

23,1(0.910)

7,37(0.290)

7,87 (0.310)

6,22 (0.245)

7,62 (MOO)

24,76 (0.975)

7,37 (0.290)

7,87 (0.310)

6,22 (0.245)

7,62 (0.300)

28,0 (1.100)

9,91 (0.390)

10,41 (00410)

18
20

B

A
MIN

23,62 (0.930)

9,65 (0.388)

NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the seating
plane.

TEXAS ~

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-13

MECHANICAL DATA

J028
ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and lead frame. Hermetic
sealing is accomplished with glass. The package is intended for insertion in mounting hole rows on 15,24 (0.600)
centers. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in
the board during soldering. Tin-plated ("bright-dipped") leads require no additional cleaning or processing when
used in soldered assembly.
J028

Designation per JEDEC Std 30:
GDIP-T8
GDIP-T14
GDIP-T16

1 4 - - - - - - - 37,1 (1.460) MAX

0,63 (0.025) R
NOM

r----~+-

I

j

14,2 (0.560)

~

:~~: ::::::: NOM

Glass Sea lent
1,78 (0.070) MAX 28 Places

~-s.""'

f~~

J\

28 Places
0,36 (0.014)
0,20 (0.008)
14 Places

Plane

~\.--

"

0,71 (0.028) MIN
28 Piaces

4,06 (0.160)
3,17 (0.125)
28 Places
2,54 (0.100)
1,52 (0.060)
4 Places

0,51 (0.020)
0,41 (0.016)
28 Places
Pin Spacing 2,54 (0.100) T.P.
(see Note A)

ALL LINEAR DIMENSIONS ARE!N MILLIMETERS AND PARENTHETICAllY IN INCHES
NOTES: D. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
E. This dimension does net apply for solder-dipped leads.
F. When solder-dipped leads are specified, dipped area ofthe lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS •

INSlRUMENlS
11-14

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

JD024 and JD028
ceramic side-braze dual-in-line packages
These hermetically sealed dual-in-line packages consist of a ceramic base, metal cap, and side-brazed
tin-plated leads. These packages are intended for insertion in mounting-hole rows of 15,24 (0.600) centers.
Leads require no additional cleaning or processing when used in solder assembly.
JD024 and JD02B
(2B-pln package used for illustration)

Designation per JEDEC Std 30:
GDIP-T24
GDIP-T2B

L'MAX~

Index Mark

1-- =I
ct.

ct.

A

~ ~!E':f

Il

__

~[:: [~J::: ]j

'r '~,~~~,

900
0,36 (0.015)
0,25 (0.008)

~II- ~:~: :~:~~~:

0,51 (0.020) MIN

5,08 (0.200) MAX

+-JIT'"TI"~~~;:;;=;;:;;=;;:;t,;:;;:;;:;;::;;:;;:;;:;;::;;:;---t

JL

I-I

1,91 (0.075) MAX
4 Places

.1

Pin Spacing 2,54 (0.100) T.P. ~
(see Note A)

~

I.

r-24

2B

15.24 (0.600)

15,24 (0.600)

B (MAX)

31,8 (1.250)

36,8 (1.450)

C(NOM)

15,0 (0.590)

15,0 (0.590)

DIM
A

+0.51 (+0.020)
-0,25 (-0.010)

3,18 (0.125) MIN

0,53 (0.021)
0,38 (0.015)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

TEXAS

-'!1

INSTRUMENlS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

11-15

MECHANICAL DATA

JG008
ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and lead frame. Hermetic
sealing is accomplished with glass. The package is intended for insertion in mounting hole rows on 7,62 (0.300)
centers. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in
the board during soldering. Tin-plated ("bright-dipped") leads require no additional cleaning or processing when
used in soldered assembly.
JG08

Designation per JEDEC Std 30:
GDIP-T8

0,63 (0.025) R NOM

~---4>f- 7,87 (0.310)

7,37 (0.290)

~_ _--I*+_

7,11 (0.280)
6,22 (0.245)

~-H-1 ,27

5,08 (0.200)

(0.050) NOM

MAX

1,78 (0.070) 8 Places

--r--------

1 rI

Glass

.............IIIIJIIII.r

Seating
Plane

-..j

Sealant

f.- 0,76 (0.030) MIN
8 Places

..l~
~ \'

0,36 (0.014)
0,20 (0.008)
8 Places

3,30 (0.130) MIN
1,6 (0.065)
0,4 (0.015)
4 Places

r-

. tt _

-.!

••

U

~

Pin Spacing
2,54 (0.100) T.P.
(see Note A)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.

TEXAS ~

INSTRUMENTS
11-t6

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

0,58 (0.023)
0,38 (0.015)
8 Places

MECHANICAL DATA

KC003
plastic flange-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when the package is operated under high-humidity conditions.
Ke003

Designation per JEDEC Std 30:
R-PSFM-T3

0,81", 0,08
(0.032 '" 0.003)
3 Places 1 ,78 (0.070)
2,79 (0.110)
2,29 (0.090)
1,14 (0.045)

0,64 (0.025) R NOM
2 Places
(see Note A)

1[

5,34 (0.210)
4,82 (0.190)

n=

L ".v~
12'70~ ~

Pin Spacing
2,79 (0.110)
2,29 (0.090)
(see Note B)

6,35 (0.250)
MAX

~~:~~!~::~2~1
0,64 (0.025)
0,30 (0.012)

450
(see Note A)

~
+

6,86 (0.270)
5,84 (0.230)

j--E--~

g ; I 4 , 8 3 (0.190)
--1..
3,56 (0.140)

+-------

2,92 (0.115)
2,03 (0.080)

1,40 (0.055)
0,51 (0.020)

3,56 (0.140)
3,05 (0.120)

The center terminal is in electrical contact with the mounting tab.
Falls within JEDEC TO-220AB dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Notches and/or mold chamfer mayor may not be present.
B. Leads are within 0,13 (0.005) radius of true position (T.P.) at maximum material conditions.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-17

MECHANICAL DATA

KC005
plastic flange-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when the package is operated under high-humidity conditions.
KC005
4,83(0.190)
3,56 (0.140)
3,96 (0.156)
3,71 (0.146)

E

10,67 (0.420)
14------~1- 9,65 (0.380)

t

3,56 (0.140)
3,05 (0.120)
1,40 (0.055)
0,51 (0.020)

1
6,86 (0.270)
5,84 (0.230)

0,64 (0.025) R NOM
2 Places
(see Note A)

Designation per JEDEC Std 30:
R-PSFM-T5

=-r
.

-

- -

-*---- -

15,88 (0.625)
14,22 (0.560)

J

45°
(see Note A)

14,27 (0.562)
12,70 (0.500)

L
Pin Spacing _
1,70 (O.067)

(see Note B)

~II~ 1,02 (0.040)
II

0,76 (0.030)
5 Places

2,92 (0.115)
2,03 (0.080)
0,64 (0.025)
0,30 (0.012)
5 Places

ALL LINEAR DiMENSiONS ARE iN MILLIMETERS AND PARENTHETiCAllY IN INCHES
NOTES: A. Notches and chamfer mayor may not be present.
B. leads are with 0,13 (0.005) radius of true position (T.P.) at maximum material conditions.

TEXAS ."

INSlRUMENTS
11-18

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

KK003
plastic flange-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when the package is operated under high-humidity conditions.
KK003

Designation per JEDEC Std 30:
X-PSFM-T3

.1

..
I

r

16,26 (0.640)
15,75 (0.620)

I.11 I'
5,08 (0.200)
~====1'1 = £ ; , 7 5 (0.180)
~
4,57(0.180)
I
4,06 (0.160)

1,78 (0.070)
1,52 (0.060)

~

5,33 (0.210)
4,83 (0.190)

2 Places

22,35 (0.880)
21,84 (0.860)

~

_

=t
[

20,83 (0.820)
19,81 (0.780)

L

1,52 (0.060)
1,02 (0.040)

Lead Spacing
5,08 (0.200)
TP

Mounting Hole
3,18 (0.125)

1b--=:r--=:r0-2:J

l

6,35 (0.2::: NOM

7' NOM

MAX

2,29 (0.090)
1,78 (0.070)

2,29 (0.090)
1,78 (0.070)

--+I
Jl

3,30 (0.130)
2,79 (0.110)

~

0,89 (0.035)
0,64 (0.025)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

TEXAS

~

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

11-19

MECHANICAL DATA

KV005
plastic flange-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when the package is operated under high-humidity conditions.

ra

Designation per JEDEC Sid 30:
R·PSFM·T5

KV005

10,67 (0.420)
9,65 (0.380)

0,64 (0.025) NOM
2 Places
(see Nole A)

~:~~ !g:~:gl

1

I

l-.I
1 'I

3,05 (0.120)

cf''''

3,56 (0.140)
3,05 (0.120)
1,40 (0.055)
0,51 (0.020)

~------~--------

6,86 (0.270)
5,84 (0.230)

:L...

£

15,88 (0.625)
14,22 (0.560)

t--

J1
15,77 (0.621)
NOM

18,03 (0.710)

21,920 (0.863)
MIN·

I

." L

25,4 (1.00)

Lead Spacing
1,70 (0.067)
(see NOie B)

45''/

I

(see Note A)

~

0,64 (0.025)
0,30 (0.012)
1,02 (0.040)
0,76 (0.030)
5 Places

NOM

.....,.,............

1

2,92 (0.115)
2,03 (0.080)

~-

r

~_*_

4,67 (0.184)
4,29 (0.169)

0 .338) --+I~+-----~~I
!l-2lU
8,20 (0.323)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Notches and chamfer mayor may not be present
B. Leads are with 0.13 (0.005) radius of true position (T.P.) at maximum material conditions.

TEXAS l!1

INSlRUMENTS
11-20

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

KV007 plastic flange-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when the package is operated under high-humidity conditions.

(O'lBl)tr.j

KV007

4,597
4,547 (0.179)

Designation per JEDEC Sid 30:
R-PSFM-T7

I
3,43 (0.135)
3,17 (0.125)

1,40 (0.055)
1,14 (0.045)

3,96(0.1~

14I

3,71 (0.146) DIA

i

1

I

20,88 (0.822)
20,62 (0.812)

5'
I

I

I
1,40 (0.055)
1,14 (0.045)

0,7~~

0,660 (0.026)

---_1-

1. . . .

2,79 (0.110)
2,54 (0.100)

7,75 (0.305)
7,49 (0.295)

7,75 (0.305) -~-----toI
7,49 (0.295)

9,52 (0.375)
9,27 (0.365) NOM

0,63 (0.025)
0,38 (0.015) R

2

PI~~es

---.. n

f-

In

-n

J~-----"".~
[

0,51 (0.020)
0,25 (0.010)

10,211 (0.4020)
10,109 (0.3980)

ALL LINEAR DIMENSIONS ARE IN MILLILMETERS AND PARENTHETICALLY IN INCHES.

TEXAS

-1/1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

11-21

MECHANICAL DATA

LP003
plastic cylindrical package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation and circuit performance characteristics
remain stable when operated in high-humidity conditions. Leads require no additional cleaning or processing
when used in soldered assembly.
LP003

Designation per JEDEC Std 30:
PBCY-W3
1,27 ± 0,13
(0.050 ± 0.005)

dt
'." ~E ' Ff==-=====~=====~: Seating Plane

5,21 (0.205)
4,44 (0.175)

DIA

2,54 ± 0,13
(0.100 ± 0.005)

1,27 (0.050)
(see Note A)

-x------

I~

~~5,34(0.210)

4,32 (0.170)
12,7 (0.500) MIN

4.19 (0.165)
3,17(0.125)

J

2.67 (0.105)
2,03 (0.080)

---.+----7"-........

.

2,67 10.105)
2,03 (0.080)

3 Leads
0,43 + 0,13, - 0,03 WIDE
0,38 ± 0,03 THICK
(0.017 + 0.005, - 0.001 WIDE
0.015 ± 0.001 THICK)

Falls within JEDEC TO-226AA dimensions
(TO-226AA replaces TO-92)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Lead dimensions are not controlled within this area.

TEXAS

~

INSlRUMENTS
11-22

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

N014, N016, N018, and N020
300-mil plastic dual-in-line packages
These dual-in-line packages consist of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation and circuit performance
characteristics will remain stable when operated in high-humidity conditions. These packages are intended for
insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient
tension is provided to secure the package in the board during soldering. Leads require no additional cleaning
or processing when used in soldered assembly.
Designation per JEDEC Std 30:
PDlp·T14
PDlp·T18
PDIP·T16
PDlp·T20
11

N014, N016, N018, AND N020
(20·pin package used for illustration)
20

1

~-+i

g.:1

E1
~

.

0,25 (0.010) NOM
E

t
t

5,08 (0.200) MAX

~ h-rr--nr-1-,-....,--,--,-...,.--rr-'-"-TT--r-rrl

- - Seating ---1----a--+I
1050
Plane
0
90
20 Places ~~ 0,36 (0.014)
0,25 (0.010)
,
20 Places
3,17 (0.125,
G
(see Notes B and C)
4 Places

J~I~

10

I~------ Al - - - - - - - - . 1
~ ~ 1,78 (0.070) MAX 18 Places
r--I-r---;.....;.-,-----;
0,51 (0.020)
MIN

Pin Spacing 2,54 (0.100) T.P.
(see Note A)

~--------

A2

0,533 (0.021)
0,381 (0.015)
20 Places
(see Notes Band C)

-------------~

1,91 (0.075)
~ 1,02 (0.040)
4 Places

VIEW A

H
4 Places

~

Pin Spacing 2,54 (0.100) T.P.
(see Note A)

0,533 (0.021)
0,381 (0.015)
20 Places
(see Notes B and C)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS

.JJ1

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

11-23

MECHANICAL DATA

N014, N016, N018, and N020
300-mil plastic dual-in-line package (continued)

~N
DIM
A1

A2
B
C

14

16

18

19,5 (0.7S0)

23,4 (0.920)

20

MIN

18,0 (0.710)

MAX

19,8 (0.7S0)

MIN

18,0 (0.710)

MAX

19,8 (0.7S0)

NOM

2,8 (0.110)

2,S (0.110)

4,06 (0.160)

2,80 (0.110)

MIN

7,37 (0.290)

7,37 (0.290)

7,37 (0.290)

7,37(0.290)

7,S7 (0.310)

7,S7 (0.310)

23,22 (0.914)
24,77 (0.975)
23,62 (0.930)
25,4 (1.000)

MAX

7,87 (0.310)

7,87 (0.310)

MIN

6,10 (0.240)

6,10 (0.240)

MAX

6,60 (0.260)

6,60 (0.260)

6,99 (0.275)

E

NOM

2,0 (O.OSO)

2,0 (O.OSO)

2,03 (O.OSO)

2,0 (O.OSO)

F

MIN

0,S4 (0.033)

0,S4 (0.033)

0,S9 (0.035)

0,S4 (0.033)

D

G

H

6,60 (0.240)
7,11 (0.2S0)

MIN

(see Note A)

0,3S (0.015)

(See Note A)

1,6S (0.066)

MAX

(see Note A)

1,65 (0.065)

(see Note A)

0,22 (M09)

MIN

2,54 (0.100)

1,02 (0.040)

0,23 (0.009)

0,3S (0.015)

MAX

1,52 (0.060)

2,41 (0.095)

1,91 (0.075)

1,27 (0.050)

NOTES: A. The 14-pin and 1S-pin plastic dual-in-Iine package is only offered with the external pins shaped
in their entirety, and do not have alternate side view dimensions.

TEXAS .JJ1

INSlRUMENTS
11-24

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

N022
400-mil plastic dual-in-line package
This dual-in-line package consist of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation and circuit performance
characteristics will remain stable when operated in high-humidity conditions. This package is intended for
insertion in mounting-hole rows on 10,16 (00400) centers. Once the leads are compressed and inserted,
sufficient tension is provided to secure the package in the board during soldering. Leads require no additional
cleaning or processing when used in soldered assembly.
N022

Designation per JEDEC Std 30:
PDIP-T22

12

22

9

11

10,41 (0.410)
9,91 (0.390)

I

0,51 (0.020) 1__

9,02 (0.355)

~I

28,5(1.120) MAX

MIN

·1-

Max

-~;;("oo)f~- h--r-r---rVVV\lVVM\XN\?~~
II-,----,,---rl
"'--'----'-'--ll

~ \"

0'35~.~~:0,203 (0.008)
22 Places
(see Notes B and C)

t

~III---

I.. J

3,17 (0.125)

MI~in Spacing ~O) T.P.

1,78 (0.070) MAX

(see Note A)

22 Places

-.j ~

0,84 (0.033) MIN
22 Places

0,533 (0.021)
0,381 (0.015)
22 Places
(see Notes B and C)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: B. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
C. This dimension does not apply for solder-dipped leads.
D. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS . .

INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-25

II
Ii
I

MECHANICAL DATA

N028
600-mil plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation and circuit performance
characteristics will remain stable when operated in high-humidity conditions. This package is intended for
insertion in mounting-hole rows on 15,24 (0.600) centers (see Note A). Once the leads are compressed and
inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no
additional cleaning or processing when used in soldered assembly.
.
N028

Designation per JEDEC Std 30:
PDlp·T28

14

36,6 (1.441) MAX
28

15

-I

,"~*: .:E:::::::::::::I~~I
ru
t
14

"}

2,8 (0.110) NOM
12

;-j

SPlane
......

0,36 (0.014)
0,20 (0.008)
24 Places
(see Notes Band C)

11,78 (0.070) MAX

~~~
"""f"")
L
t3,17 (0.125) MIN
24 Places
2,42 (0.095) MAX

JLJ l

4 Pla~es
Pin Spacing 2,54 (0.100) T. P.
(see Note A)

-.jj.-J

0,533 (0.021)
0,381 (0.015)
24 Places
(see Notes B and C)

l

0,83 (0.095) MAX
24 Places

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS

..If

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-29

MECHANICAL DATA

P008
plastic dual-in-Iine package
This package consists of a circuit mounted on an a-pin lead frame and encapsulated within a plastic
compound.The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high-humidity conditions. The package is intended for
insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient
tension is provided to secure the package in the board during soldering. Solder-plated lead require no additional
cleaning or processing when used in soldered assembly.
P008

I.

Designation per JEDEC Std 30:
PDIP-T8
10,2 (0,400) MAX

j
5

B
Index Dot

It.

14-------.>1----

7,87 (0.310)
7,37 (0.290)

14----+t-i-

6,60 (0.260)
6,10 (0.240)

1,78 (0.070) MAX
8 Places

...
5,08 (0.200)
MAX

jl.[

~

L

Seating Plane
Gauge Plane

9g~:~~ 19:9ggl

--.II.--

3,17 (0.125)
MIN

0,36 (0.014)
0,20 (0.008)
(see Note B and C)

2,54 (0.100) T. P.
6 Places
(see Note A)

0,533 (0.021)
0,381 (0.015)

(see Note B and C)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area olthe lead extends from the.lead tip to at least 0,51 (0.020) above seating plane.

TEXAS

-IJ1

INSTRUMENTS
11-30

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

PK003
plastic lead-mount package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation, and circuit performance characteristics will
remain stable when operated in high-humidity conditions.
PK003

Designation per JEDEC Std 30:
PSSO·F3

1

~8::!~0~;:~~~

0,40 (0.016) NOM

LL

_~_I

".,1,,,, t
2,40 (0.095)

1,60 (0.063)
1,40 (0.055)

r

I ~

--l'

4,25 (0.167) MAX

1
.,... ('.'''' MAX . .

II ~

I -'11
1,50 (0.059) NOM

L

~
0,80 (0.032) MIN

0,44 (0.017) MAX

~~

0,53 (0.021) MAX

--f.---.I

The center lead is in electrical contact with the tab
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

TEXAS

.1!1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-31

MECHANICAL DATA

PVV008,PVV014,PVV016,PVV020
shrink small-outline packages
These shrink small-outline packages consist of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
PWOOB. PW014, PW016, PW020
(14-pin package used for illustration)

Designation per JEDEC Std 30:
PDSO-G8
PDSO-G14
PDSO-G16
PDSO-G20

DETAIL A

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS
NOTES: A.
S.
C.
D.

Leads are within 0.25 mm radius of true position at maximum material condition.
Body dimensions include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 mm.
Lead tips to be planar within ±0,051 mm exclusive of solder.

DIM
~

B

14

16

20

AMIN

2,99

4,99

4.99

6,40

A MAX

3,03

5,30

5,30

6,80

SMAX

0,65

0,70

0,38

0,48

TEXAS

-III

INSlRUMENTS
11-32

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL DATA

U010
ceramic flat package
This flat package consists of a ceramic base, ceramic cap, and lead frame. Circuit bars are alloy mounted.
Hermetic sealing is accomplished with glass. Leads require no additional cleaning or processing when used in
soldered assembly.
U010

0,153 (0.006)
0,076 (0.003)
10 Leads

1r

0,483 (0.019)
0,381 (0.015)
10 Leads

1r

Designation per JEDEC Std 30:
GDFP·F10

~ 1,27 (0.050) NOM

(see Note A)

8,89 (0.350)
5,08 (0.200)

25,4

(1~:)- -1----Tm

19,0 (0.750)

L"":;;;10;;:......:;;;I-:""':;;;;-""";;;::"""6:;;;:""

1

6,35 (0.250)
5,97 (0.235)

7,62 (0.300)
(see Note B)

2,03 (0.080)
1,27 (0.050)

-

Alternate
Index Points . ~ ~

~- ---l------------r-

I-

5
-

"MI
8,89 (0.350)

--.\

1,27 (0.050)
0,13 (0.005)

+--

i...L.. 0,64 (0.025)

ro- 0,00 (0.000)

6,35 (0.250) ----.

Falls within JEDEC MO-004AA dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A Leads are within 0,13 (0.005) radius of true position (T.P.) at maximum material conditions.
B. This dimension determines a zone within which all body and lead irregularities lie.

TEXAS .Jf

INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11-33

MECHANICAL DATA

W014
ceramic flat package
This hermetically sealed flat package consists of an electrically nonconductive ceramic base and cap and a lead
frame. Hermetic sealing is accomplished with glass. Leads require no additional cleaning or processing when
used in soldered assembly.
W014
0,152 (0.006)
0,076 (0.003)
14 Leads

1r

0,483 (0.019)
0,381 (0.015)
14 Leads

.",1:

---,.-

_________ ~'I~_

Base And
Seating
Plane

1

Designation per JEDEC Std 30:
GDFp·F14

~

~ 1,27 (0.050) NOM

12 Places
(see Note A)

1

1- '-

-

i-8

14

_;::~~L~~£~T~L.~" l" _'" 't"'. .,. _~_.~. ,. =~ _~7~
(

2,03 (0.080)
1,27 (0.050)

7,oJ27S)
N t B)

1r

(see Note C)

8,00 (0.315)

1,02 (0.040)
0,51 (0.020)

-J I.-

""T"

L

-..J
8,89 (0.350) - - - - .
8,56 (0.337)

~ 0,64 (0.025)

r--- 0,25 (0.010)

Fall within JEDEC MO-004AA dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) at maximum material condition.
B. This dimension determines a zone within which all body and lead irregularities lie.
C. Index point is provided on cap for terminal identification only.

TEXAS

-1!1

INSTRUMENTS
11-34

POST OFFICE BOx 655303 • DALLAS, TEXAS 75265

4 Places

TI North
TI Authorized
American Sales North American
Offices
Distributors
ALABAMA: Huntsville: (205) 837-7530
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Customer
Response Center
TOLL FREE:
OUTSIDE USA:

(800)336-5236
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(8:00 a.m. - 5:00 p.m. CST)

©1991 Texas Instruments Incorporated

Alliance Electronics, Inc. (military product only)
Almae Electronics
Anthem Electronics
Arrow {Canada}
Arrow/Kierulff Electronics Group
Future Electronics (Canada)
GRS Electronics Co., Inc.
Hall·Mark Electronics
Lex Electronics
Marshall Industries
Newark Electronics
Rochester Electronics, Inc.
(obsolete product only (S08) 462-9332)
Wyle Laboratories
Zeus Components

TI Distributors
ALABAMA: Arrow/Kierulff (205) 837-6955; Hall-Mark (205)
837-8700; Marshall (205) 881·9235; Lex (20S) 895-0480.
ARIZONA: Anthem (602) 966-6600; Arrow/Kierulff (602)
437-0750; Hall-Mark (602) 437-1200; Marshall (602)
496-0290; Lex (602) 431-0030; Wyle (602) 437-2088.
CALIFORNIA: Los Angeles/Orange County: Anthem
(818) 775-1333, (714) 768-4444; Arrow!Kierulff (818)
701-7500, (714) 838-5422; Hall·Mark (818) 773-4500,
(714) 727-6000: Marshall (818) 407-4100, (714) 458-5301;
Lex (818) 880-9686, (714) 587·0404: Wyle (818) 880·9000,
(714) 863-9953: Zeus (714) 921-9000, (818) 889-3838;
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638-5282:
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565-4800; Hall-Mark (619) 268-1201; Marshall (619)
578-9600; Lex (619) 495-0015: Wyle (619) 565-9171: Zeus
(619) 277-9681:
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727·2500; Zeus (408) 629-4789.
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373-5616; Hall·Mark (303) 790-1662; Marshall (303)
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265-3822: Lex (203) 264-4700.
FLORIDA: Fort Lauderdale: Arrow/Kierulff (305) 429-8200;
Halil-Mark (305) 971-9280; Marshall (305) 977-4880; Lex
(305) 421-6633:
Orlando: Arrow/Kierulff (407) 333-9300; Hall-Mark (407)
830·5855; Marshall (407) 767-8585; Lex (407) 331-7555;
Zeus (407) 365-3000:
Tampa: Hall-Mark (813) 541·7440; Marshall (813)
573-1399; Lex (813) 541-5100.
GEORGIA: Arrow/Kierulff (404) 497-1300; Hall-Mark (404)
623·4400; Marshall (404) 923·5750; Lex (404) 449-9170.
ILl.INOIS: Anthem (708) 884-0200; Arrow/Kierulff (708)
250-0500; Hall·Mark (708) 860-3800; Marshall (312)
490-0155; Newark (312)784-5100; Lex (708) 330-2888.
INDIANA: Arrow/Kierulff (317) 299-2071; Hall-Mark (317)
872-8875; Marshall (317) 297-0483; Lex (317) 843-1050.
IOWA: Arrow/Kierulff (319) 395-7230; Lex (319) 373-1417.
KANSAS: Arrow/Kierulff (913) 541·9542; Hall-Mark (913)
888-4747; Marshall (913) 492-3121; Lex (913) 492·2922.
MARYLAND: Anthem (301) 995-6640; Arrow/Kierulff (301)
995-6002; Hall-Mark (30t) 988-9800; Marshall (301)
622-1118; Lex (301) 596-7800: Zeus (301) 997-1118.
MASSACHUSETTS: Anthem (508) 657·5170:
Arrow/Kierulff (508) 658-0900; Hall-Mark (508) 667-0902;
Marshall (508) 658-0810: Lex (508) 694-9100: Wyle (617)
272-7300; Zeus (617) 246-8200.

MICHIGAN: Detroit: Arrow/Kierulff (313) 462-2290;
Hall-Mark (313) 462-1205; Marshall (313) 525·5850;
Newark (313) 967-0600; Lex (313) 525-8100;
Grand Rapids: Arrow/Kierulff (616) 243-0912.
MINNESOTA: Anthem (612) 944-5454; Arrow/Kierulff (612)
829-5588; Hall-Mark (612) 941-2600; Marshall (612)
559-221'; Lex (612) 941-5280.
MISSOURI: Arrow/Kierulff (314) 567-6688; Hall-Mark (314)
291-5350; Marshall (314) 291-4650; Lex (314) 739-0526.
NEW JERSEY: Anthem (201) 227-7960; Arrow/Kierulff
(201) 538-0900, (609) 596-8000; GRS (609) 964-8560;
Hall-Mark (201) 515-3000, (609) 235-1900; Marshall (201)
882-0320, (609) 234-9100; Lex (201) 227-7880, (609)

273-7900.
NEW MEXICO: Alliance (505) 292-3360.

~~~iK?e~~~ ~gln6~ ~J~~1~o~7~:~J~~~)(:~~;~~~~b600;

Marshall (516) 273-2424: Lex (516) 231-2500;
Zeus (914) 937.7400;
Rochester: Arrow/Kierulff (716) 427-0300; Hall-Mark (716)
425-3300; Marshall (716) 235-7620; Lex (716) 383-8020; .
Syracuse: Marshall (607) 785-2345.
NORTH CAROLINA: Arrow/Kierulff (919) 876-3132;:
Hall-Mark (919) 872-0712: Marshall (919) 878-9882; Lex
(919) 876·0000.
OHIO: Cleveland: Arrow/Kierulff (216) 248-3990;
~~I~)M4~~_~d:J;349-4632; Marshall (216) 248-1788; Lex

Columbus: Hall-Mark (614) 888-3313;
Dayton: Arrow/Kierulff (513) 435-5563;
Marshall (513) 898-4480: Lex (513) 439-1800;
Zeus (513) 293-6162
OKLAHOMA: Hall·Mark (918) 254-6110: Lex (918)
622-8000.
OREGON: Almae (503) 629-8090: Anlhem (503) 643-1114;
Arrow/Klerulff (503) 627-7667; Marshall (503) 644-5050;
Wyle (503) 643-7900.
PENNSYLVANIA: Anthem (215) 443-5150; Arrow/Klerulff
(215) 928-1800; GRS (215) 922-7037;
Mershall (412) 788-0441; Lex (412) 963-6804.
TEXAS: Austin: Arrow/Kierulff (512) 835-4180;
Hall-Mark (512) 258-8848; Lex (512) 339-0088; Wyle (512)
345-8853;
Dallas: Anthem (214) 238-7100; Arrow/Klerulff (214)
380-6464; Hall-Mark (214) 553-4300; Marshall (214)
233·5200; Lex (214) 247-6300; Wyle (214) 235-9953:
Zeus (214) 783-7010;
Houston: Arrow/Kierulff (713) 530-4700; Hall-Mark
781-6100; Marshall (713) 895-9200; Lex
1713)
713) 784-3600; Wyle (713) 879-9953.
UTAH: Anlhem (801) 973-8555; Arrow!Kierulff (801)
973-6913; Marshall (801) 485-1551: Wyle (801) 974-9953.
WASHINGTON: Aimee (206) 643-9992, (509) 924-9500;
anthem (206) 483-1700; Arrow/Kisrulff (206) 643-4800:
Marshall (206) 486-5747; Wyle (206) 881-1150.
WISCONSIN: Arrow/Kierulff (414) 792-0150; Hall·Mark
(414) 797-7844; Marshall (414) 797-8400:
Lex (414) 784-9451.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow Canada (514) 421-7411;
Future (514) 694·7710; Marshall (514) 694-8142
Ottawa: Arrow Canada (61-3) 226-6903; Future (613)
820-8313; Quebec City: Arrow Canada (418) 871-7500:
Toronto: Arrow Canada (416) 670-7769;
Future (416) 612-9200; Marshall (416)458-8046;
Vancouver: Arrow Canada (604) 421-2333;
Future (604) 294-1166.

TI Die Processors
Chip Supply
Elmo Semiconductor
Minco Technology Labs

(407) 298-71 00
(818) 768-7400
(512) 834-2022

TEXAS

INSTRUMENTS

00691

TI Worldwide
Sales Offices
ALABAMA: Huntsville: 4960 Corporate Drive,
Suite N-150, Huntsville, AL 35805-6202, (205) 837-7530.
ARIZONA: Phoenix: 8825 N. 23rd Avenue, Suite 100,
Phoenix, AZ 85021, (6D2) 995-1007.
CALIFORNIA: Irvine: 1920 Main Street, Suite 900,
Irvine, CA 92714, (714) 660-1200; Roseville: 1 Sierra Gale
Plaza, Suite 2558, Roseville, CA 95678, (916) 786-9206;
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COLORADO: Aurora: 1400 S. Potomac Street, Suite 101,
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CONNECTICUT: Wallingford: 9 Barnes Industrial Park
So., Wallingford, CT 06492, (203) 269-0074.
FLORIDA: Altamonte Springs: 370 S. North Lake
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(407) 260·2116;
Fort Lauderdale: 2950 N.W. 62nd Street,
Suite 100, Fort Lauderdale, FL 33309,
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GEORGIA: Norcross: 5515 Spalding Drive,
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ILLINOIS: Arlington Heights: 515 W. Algonquin,
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IOWA: Cedar Rapids: 373 Collins Road N.E., Suite 201,
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KANSAS: Overland Park: 7300 College Boulevard,
Lighton Plaza, Suite 150, Overland Park, KS 66210,
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MARYLAND: Columbia: 8815 Centre Park Drive,
Suite 100, Columbia, MO 21045, (301) 964-2003.
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Suite 2800, Waltham, MA02154, (617) 895-9100.
MICHIGAN: Farmington Hills: 33737 W. 12 Mile Road,
Farmington Hills, M148331, (313) 553-1500.
MINNESOTA: Eden Prairie: 11000 W. '78th Street,
Suite 100, Eden Prairie, MN 55344, (612) 828-9300.
MISSOURI: SI. Louis: 12412 Powerscourt Drive,
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NEW JERSEY: Iselin; Parkway Towers,
485 E. Route 1 South, Iselin, NJ 08830, (201) 750-1050.
NEW MEXICO: Albuquerque: 2709 Pan American
Freeway, N.E., Albuquerque, NM 87107, (505) 345-2555.
NEW YORK: East Syracuse: 6365 Collamer Drive,
East Syracuse, NY 13057, (315) 463-9291;
Fishkill: 300 Westage Business Center, Suite 140,
Fishkill, NY 12524, (914) 897-2900; Melville: 1895 Walt
Whitme.r! Rced, Me!l/i!!e, NY 11747, (516} 454-6600;
Pittsford: 2851 Clover Street, Pittsford, NY 14534,

(716) 385·6770.
NORTH CAROLINA: Charlotte: 8 Woodlawn Green,
Suite 100, Charlotte, NC 28217, (704) 527-0930;
Raleigh: 2809 Highwoods Boulevard, Suite 100,
Raleigh, NC 27625, (919) 876-2725.
OHIO: Beachwood: 23775 Commerce Park Road,
Beachwood, OH 44122, (216) 464-6100;
Beavercreek: 4200 Colonel Glenn Highway, Suite 600,
Beavercreek, OH 45431, (513) 427-6200.
OREGON: Beaverton: 6700 SW. 105th Street,
Suite 110, Beaverton, 01-1 97005, (503) 643-6758.
PENNSYLVANIA: Blue Bell: 670 Sentry Parkway, Blue
Bell, PA 19422, (215) 825-9500.
PUERTO RICO: Halo Rey: 615 Mercantile Plaza Building,
Suite 505, Hato Rey, PR 00918, (809) 753-8700.
TEXAS: Austin: 12501 Research Boulevard,
Austin, TX 78759, (512) 250-6769; Dallas: 7839 Churchill
Way, Dallas, TX 75251, (214) 917-12.64;
Houston: 9301 Southwest Freewa/, Suite 360, Houston,
TX 77074, (713) 778·6592

UTAH: Salt Lake City: 1800 S. West Temple Street,
Suite 201, Salt Lake City, UT 84115, (801) 466-8973.
WASHINGTON: Redmond: 5010 148th Avenue N.E.,
Building S, Suite 107, Redmond, WA 98052,

(206) 881 ·3080.
WISCONSIN: Waukesha: 20825 Swenson Drive,
Suite 900, Waukesha WI 53186, (414) 798-1001.
CANADA: Nepean: 301 Moodie Drive, Mallom Center,
Suite 102, Nepean, OntariO, Canada K2H 9C4,
(613) 726-1970; Richmond Hill: 280 Centre Street
East, Richmond Hill, Ontario, Canada L4C 1 Bl,
(416) 884-9181; St. Laurent: 9460 Trans Canada
Highway, S1. Laurent, Quebec, Canada H4S 1 R7,

(514) 335·8392.
ARGENTINA: Texas Instruments Argentina Viamonte
1119,1053 Capital Federal,
Buenos Aires, Argentina, 11748-3699.
AUSTRALIA (& NEW ZEALAND): Texas Instruments
Australia Ltd., 6-10 Talavera Road, North Ryde (Sydney),
New South Wales, Australia 2113,2-878-9000; 14th Floor,
380 Street, Kilda Road, Melbourne, Victoria, Australia
3004,3-696-1211; 171 Philip Highway, Elizabeth, South
Australia 5112, 8 255-2066.
BEL.GIUM: SA Texas Instruments Belgium N.V" 11,
Avenue Jules Bordetlaan 11, 1140 Brussels, Belgium,

(02) 242 30 80.
BRAZIL: Texas Instruments Electronicos do Brasil Ltda ..
Rua Paes Leme, 524-70 andar, 05424 Sao Paulo, Brazil,
11-815-6166.
DENMARK: Texas Instruments !VS, Borupvang 20,
DK-2750 Ballerup, Denmark, (45) 44687400.
FINLAND: Texas Inslruments OY, P.O. Box 86, 02321
Espoo, Finland, (0) 802 6517.
FRANCE: Texas Instruments France, 8-10 Avenue
Morane Saulnier-B.P. 67, 78141 Velizy Villacoublay cedex,
France, (1) 30 70 1003.
GERMANY: Texas Instruments Deutschland GmbH.,
Haggertystrasse 1, 8050 Freising, (08161) 80·0 od. Nbs!;
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65; Dusseldorfer Strasse 40, 6236 Eschborn " (06196) 80
70; Kirchhorster Strasse 2, 3000 Hannover 51, (0511) 64
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Essen " (201) 24 25-0.
HOLLAND: Texas Instruments Holland B.V., Hogehilweg
19, Postbus 12995,1100 A2 Amsterdam-Zuidoost, Holland,

(020) 5602911.
HONG KONG: Texas Instruments Hong Kong Ltd., 8th
Floor, World Shipping Center, 7 Canton Road, Kowloon,
Hong Kong, 7351223.
HUNGARY:' Texas Instruments International, Budaorsi
u.42, H-1112 Budapest, Hungary, (1) 1 666617.
IRELAND: Texas Instruments Ireland Ltd., 7/8 Harcourt
Street, Dublin 2, Ireland, (01) 481677.
ITALY: Texas Instruments !Ialia S.p.A, Centro Direzionale
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38,00148 Rome, Italy (06) 6572651; Via Amendola, 17,
40100 Bologna, Italy (051) 554004.
JAPAN: Texas Instruments Japan Ltd" Aoyama Fuji

~~~~J~~_~-16,-~;2~~aS~i~~~~~a B~ji~~~~~F, 1~~~~2~a$~~~u~~',
Minato-ku, Tokyo, Japan 108, 03-3769-8700; Nissho-iwai
Building 5F, 2-5-8 Imabashi, Chuou-ku, Osaka, Japan 541,
06-204-1881: Dai-ni Toyota Building Nishi-kan 7F, 4-10-27
Meieki, Nakamura-ku, Nagoya, Japan 45~, ~52-583-8691;
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Daiichi Olympic Tachikawa Building 6F, 1-25-12,
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134 Gondo-cho Hodogaya-ku, Yokohama, Kanagawa 240,
Japan, 045-338-1220; Nihon Seimei Kyoto Yasaka
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600,075-341-7713; Sumitorno Seime! Kumagaya Building
SF, 2-44 Yayoi, Kumagaya, Saitama, Japan 360,
0485-22-2440; 2587-1, Aza Harudai, Oaza Yasaka, Kitsuki,
Oita, Japan 873, 09786-3-3211.
KOREA: Texas Instruments Korea Ltd., 28th Floor, Trade
Tower, 159-1, Samsung-Dong, Kangnam-ku Seoul, Korea.
2551 2800.

MALAYSIA: Texas Instruments MalaYSia, Sdn. Bhd., Asia
Pacific, Lot 36.1 #Box 93, Menara, Maybank, 100 Jalan Tun
Perak, 50050 Kuala Llumpur, Malaysia, 2306001.
MEXICO: Texas Instruments de Mexico S.A, de C.v.,
Alfonso Reyes 115, Col. Hipodromo Condesa, Mexico,
D.F" Mexico 06170, 5-515-6081,
NORWAY: Texas Instruments Norge !VS, P8 106, Refstad
(Sinsenveien 53), 0513 Oslo 5, Norway, (02) 155090.
PEOPLE'S REPUBL.IC OF CHINA: Texas Instruments
China Inc., Beijing Representative Office, 7-05 CITIC
Building, 19 Jianguomenwai Dajje, Beijing, China,
500-2255, Ext. 3750.
PHILIPPINES: Texas Instruments Asia Ltd.,
Philippines BranCh, 14th Floor, Ba-Lepanto BUilding,
Paseo de Roxas, Makati, Metro Manila, Philippines,
28176031.
POATUGAL: Texas Instruments Equipamento Electronico
(Portugal) Ltda., Eng. Frederico Ulricho, 2650 Moreira Da
Maia, 4470 Maia, Portugal (2) 948 1003.
SINGAPORE ~& INDIA, INDONESIA, MALAYSIA,

r~~I~C~f~)~iv~~6~, 1~6yu,.~~~~os~n~6~d,r~J~:0~), Ltd.,
United Square, Singapore 1130,3508100.
SPAIN: Texas Instruments Espana SA, c/Gobelas 43,
Ctra de la Coruna km 14, La Florida, 28023, Madrid, Spain,
(1) 372 8051; c/Diputacion, 279-3-5, 08007 Barcelona,

Spain, (3) 317 91 80.
SWEDEN: Texas Instruments International Trade
Corporation (Sverigefilialen), Box 30, S-164 93 Kista,
Sweden, (08) 752 58 00.
SWITZERLAND: Texas Instruments Switzerland AG,
Riedstrass:e 6, CH-8953 oietikon, Switzerland,
(01) 7442811.
TAIWAN: Texas Instruments Taiwan Limited, Taipei
Branch, 10th Floor Bank Tower, No. 205 Tun Hwa N. Road,
Taipei, Taiwan, Republic of China, 2-7139311.
UNITED KINGDOM: Texas Instruments Ltd., Manton
Lane, 8eqford, England, MK41 7PA, (0234) 270 111.

TI Authorized
North American
Distributors
Alliance E)ectronics, Inc. (military product only)
Almac Electronics
Anthem Electronics
Arrow/Kierulff Electronics Group
Arrow (Canada)
Future Electronics (Canada)
GRS Electronics Co., Inc.
Hall-Mark Electronics
Lex Electronics
Marshall Industries
Newark Electronics
Wyle Laboratories
leus Components
Rochester Electronics, Inc. (obsolete product only)

TEXAS

INSTRUMENTS
©1991 Texas Instruments Incorporated

60691

."

TEXAS

INSTRUMENTS
Other Linear Product Lines from TI
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Data Acquisition
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Thank you for your interest in TI Linear Products. On the last
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American authorized distributors. Our sales representatives
will be happy to answer your questions about pricing, device
availability and technical product information. For information
on how to order technical literature, please contact our
Literature Center at the following address:
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LITERATURE CENTER
P.O. Box 809066
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TEXAS
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Pri nted in U.S.A.
0192- 140

SLYD004A



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