1992_Teledyne_Data_Book 1992 Teledyne Data Book
User Manual: 1992_Teledyne_Data_Book
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~"'TELEDYNE
COMPONENTS
1992 DATA BOOK
ANALOG SIGNAL PROCESSING
DRIVERS
DMOS
POWER ICs
SENSORS
Teledyne Components reserves the right to make changes in the circuitry or specification detailed in this manuaI at any time
without notice. Minimums and maximums are guaranteed. All other specifications are intended as guidelines only. Teledyne
Components assumes no responsibility for the use of any circuits described herein and makes no representations that they are free
from patent infringement.
© TELEDYNE COMPONENTS 1991
TELEDYNE COMPONENTS makes no representation that use of its modules in the circuits described herein, or use of other
technical information contained herein will not infringe on existing or future patent rights nor do the descriptions contained h(:rein
imply the granting of licenses to make use or sell equipment constructed in accordance therewith. Device specifications as
contained on the data sheet are current as of the publication date shown. TELEDYNE COMPONENTS maintains the right to make
changes in the circuitry andlor specifications contained on this data sheet at any time, without notice and assumes no responsibility
for the use of any circuits d.escribed therein.
Display AID Converters
Binary AID Converters
Voltage-to-Frequency/Frequency-to-Voltage Converters
Sensor Products
Power Supply Control ICs
Power MOSFET, Motor and PIN Drivers
References
Chopper-Stabilized Operational Amplifiers
High Performance Amplifiers/Buffers
Video Display Drivers
Display Drivers
IDI
III
Analog Switches and Multiplexers
lEI
Data Communications
IDI
Discrete DMOS Products
Reliability and Quality Assurance
Ordering Information
III
l1li
BI
Package Information
III
Sales Offices
IDI
TABLE OF CONTENTS
SECTION 1
Display AID Converters
1-1
TCS07
2-1/2 Digit Analog-to-Digital Converter
TCSll
3-1/2 Digit NO Converter with Hold and Differential Reference Inputs
1-13
TCS1S
Auto-Ranging Analog-to-Digital Converter with 3-1/2 Digit and Bar-Graph Displays
1-27
TCS20/1
Display NO Converters with Frequency Counter and Logic Probe
1-49
TCS2213
3-3/4 Digit LCD Analog-to-Digital Converter
1-73
TCS26
NO Converter with Bar Graph Display Output
1-87
TCS35
Personal Computer Data Acquisition ADC
TC7106n
3-1/2 Digit NO Converter
1-115
1-99
TC7106A17A
3-1/2 Digit NO Converter
1-115
TC7116n
3-1/2 Digit Analog-to-Digital Converters with Hold
1-135
TC7116A17A
3-1/2 Digit Analog-to-Digital Converters with Hold
1-135
TC7126/6A
3-1/2 Digital Analog-to-Digital Converter
1-149
TC7129
4-1/2 Digit Analog-to-Digital Converter with On-Chip LCD Drivers
1-163
TC7135
4-1/2 Digit Analog-to-Digital Converter
1-177
TC713616A
Low Power, 3-1/2 Digit Analog-to-Digital Converters
1-191
TCS750
3-1/2 Digit Analog-to-Digital Converter with Parallel BDC Output
1-205
TC14433/A1B
3-1/2 Digit ADC
1-213
SECTION 2
Binary AID Converters
TC500/A
Integrating Converter Analog Processors
TCSOO
15-Bit Plus Sign, Integrating Analog-to-Digital Converter
2-13
2-1
2-31
TCS04
12-Bit ~P-Compatible Multiplexed NO Converter
TCS50
15-Bit, Fast-Integrating CMOS Analog-to-Digital Converter
2-51
TC710919A
12-Bit ~P-Compatible Analog-to-Digital Converters
2-65
TCS702
Binary Output Analog-to-Digital Converters
2-87
TCS704105
Binary Output Analog-to-Digital Converters
2-87
SECTION 3
Voltage-to-Frequency/Frequency-to-Voltage Converters
4731133
High Reliability Hybrid Voltage-to-Frequency Converters
3-1
4736
High-Reliability Hybrid Frequency-to-Voltage Converter
3-11
4743
High Frequency, Hybrid Voltage-to-Frequency Converter
3-19
TC9400/112
VOltage-to-Frequency/Frequency-to-Voltage Converters
3-23
iii
TABLE OF CONTENTS
SECTION 4
Sensor Products
TC620/1
Solid State Temperature Sensor
4-1
TC626
Solid-State Temperature Sensor
4-7
TC67516
Fast NiCAD/Ni-Hydride Battery Charger
4-9
SECTION 5
Power Supply ControllCs
TC170
CMOS Current-Mode PWM Controller
5-1
TC17213
BiCMOS Current-Mode PWM Controller
5-9
TC15C2517
BiCMOS PWM Controllers
5-13
TC25C2517
BiCMOS PWM Controllers
5-13
TC35C2517
BiCMOS PWM Controllers
5-13
TC18C42131415
BiCMOS Current Mode PWM Controller
5-19
TC28C42131415
BiCMOS Current Mode PWM Controller
5-19
TC38C4213/415
BiCMOS Current Mode PWM Controller
5-19
TC18C4617
CMOS Current Mode PWM Controller
5-25
TC28C4617
CMOS Current Mode PWM Controller
5-25
TC38C4617
CMOS Current Mode PWM Controller
5-25
TC76S0
DC-to-DC Voltage Converter
5-31
TC7662A
DC-to-DC Converter
5-43
TC962
High Current DC-to-DC Converter
5-49
SECTION 6
Power MOSFET, Motor and PIN Drivers
1120
High-Speed Pin Driver
6-1
TC14261718
1.2A Dual High-Speed MOSFET Drivers
6-3
TC4261718
Dual High-Speed Power MOSFET Drivers
TC429
Single High-Speed, CMOS Power MOSFET Driver
6-17
TC430
Fast CMOS CCD Driver
6-25
TC4401
6A Open-Drain MOSFET Driver
6-33
TC4403
1.5A High-Speed, Floating Load Driver
6-41
TC4404/5
1.5A Dual Open-Drain MOSFET Drivers
6-47
TC440617
3A Dual Open-Drain MOSFET Drivers
6-55
TC442019
6A High-Speed MOSFET Drivers
6-63
TC442112
9A High-Speed FET Driver
6-69
TC44231415
3A Dual High-speed MOSFET Drivers
6-77
TC44261718
1.5A Dual High-Speed FET Drivers
6-85
TC4437/819
Power Logic CMOS Quad Drivers
6-93
TC4457/819
Power Logic CMOS Quad Drivers
6-93
iv
6-9
TABLE OF CONTENTS
Power MOSFET, Motor and PIN Drivers (Continued)
TC4467/819
Power Logic CMOS Quad Drivers
TC4487/819
Power Logic CMOS Quad Drivers
TC4460/61 162/63
Current-Sensing, 6 Amp Power MOSFET Driver
6-105
TC462617
Power CMOS Drivers with VDD Tripier
6-111
6-93
6-93
SECTION 7
References
TC04105
Low Power, Band-Gap Voaage References
7-1
SECTION 8
Chopper-Stabilized Operational Amplifiers
TC900
Low Power, Chopper-Stabilized Operational Amplifier
TC901
Monoltthic, Auto-Zeroed Operational Amplifier
8-9
TC911
Auto-Zeroed Monolithic Operational Amplifier
8-15
8-1
TC913
Dual Auto-Zeroed Operational Amplifier
8-21
TC914
Quad Auto-Zeroed Operational Amplifier
8-27
TC915
High-Voltage, Auto-Zeroed Operational Amplifier
8-33
TC918
Low-Cost CMOS Operational Amplifier
8-41
TC7650
Chopper-Stabilized Operational Amplifiers
8-47
TC7652
Low Noise, Chopper-Stabilized Operational Amplifier
8-55
TC9420/1
High-Voltage, Auto-Zeroed Operational Amplifiers
8-63
SECTION 9
High Performance Amplifiers/Buffers
1321
Wideband, High Slew Rate Operational Amplifier
1322
Wideband, High Slew Rate Operational Amplifier
9-5
1332
High Performance Operational Amplifier
9-9
9-1
1344
Monolithic Wideband, JFET Input Operational Amplifier
9-13
1346
Monoltthic Low Bias Current Operational Amplifier
9-17
1430
Fast Settling, FET Input Operational Amplifier
9-21
1435
Operational Amplifier-High-Frequency, Fast-Settling
9-27
1437
Operational Amplifier-Wideband, Fast-Settling
9-35
1438
Operational Amplifier-Wideband, Fast-Settling
9-45
1443
Operational Amplifier-Wideband, Fast-Settling, Fully-Differential, FET-Input
9-47
1460
Operational Amplifier-High-Speed, VMOS Output
9-55
1461
Operational Amplifier-High-Speed, High-Power, VMOS Output
9-61
1468 (TCPA12)
Operational Amplifier-High-voltage, Very-High-Power
9-69
1480
Operational Amplifier-Fast-Settling,
1481
Operational
Amplifier-High-Vo~age
v
High-Vo~age
9-73
9-77
TABLE OF CONTENTS
High Performance Amplifiers/Buffers (Continued)
1482
Operational Amplifier-High-Voltage
4856
Low Cost Microcircuit Sample/Hold Amplifier
9-81
4860
Fast, 12-Bit Sample/Hold Amplifier
9-85
9-91
9-79
TP0032
Operational Amplifier-High-Speed, FET-Input
TP0033
High-Speed, Unity-Gain Buffer/Driver Amplifier
9-97
TP3554
Operational Amplifier-High-Speed, Wideband
9-103
SECTION 10
Video Display Drivers
1900
Monolithic, High-Voltage Video Driver for CRT Monitors
10-1
1902
High-Voltage Video Driver for CRT Monitors
10-7
1903
High-Negative-Voltage Video Driver for CRT Monitors
10-13
SECTION 11
Display Drivers
TC7211/12A
4-Digit CMOS Display Decoder/Driver
TC7211/12AM
Bus Compatible
TC9404
Serial Inputl16-Bit Parallel Output Peripheral Driver
11-25
TC9405
16-Bit Parallel-Latched Output Peripheral Driver
11-31
4-Dig~
11-1
CMOS Decoder/Driver
11-15
SECTION 12
Analog Switches and Multiplexers
CDG201
Monol~hic
CMOS/DMOS, Quad SPST Analog Switch
12-1
CDG211
Quad Monolithic, SPST CMOS/DMOS Analog Switch
12-7
CDG2214
High-speed Analog Switch
12-13
CDG2269
Dual SPDT CMOS/DMOS Analog Switch With Data Latch
12-17
CDG30819
Quad Monolithic, SPST CMOS/DMOS Anaiog Switches
12-23
CDG430819
Quad Monolithic, SPST CMOS/DMOS Analog Switches
12-23
CDG4500
4-Channel CMOS/DMOS High-Frequency Multiplexer
12-31
CDG5341
Dual Monolithic, SPST CMOS/DMOS "T' Configuration Analog Switch
12-35
TC42011213
Quad Single-Pole CMOS Analog
TC4411213
Microprocessor Compatible CMOS Analog Sw~ches
12-45
TC4441516n
Microprocessor Compatible CMOS Analog
Sw~ches
12-51
Sw~ches
12-39
SECTION 13
Data Communications
TC232
Dual RS-232
Transm~ter/Receiver
and Power Supply
vi
13-1
TABLE OF CONTENTS
SEcnON 14
Discrete OM05 Products
2N7000fl
Power FETs-N-Channel, Enhancement-Mode DMOS
85170
N-Channel Enhancement-Mode DMOS Power FET
14-3
501106
N-Channel Enhancement-Mode DMOS Power FETs
14-5
50210-215
N-Channel Enhancement-Mode DMOS FET Switches
14-7
50211A-215A
N-Channel Enhancement-Mode DMOS FET Switches
14-9
50304-6
N-Channel Enhancement-Mode Dual Gate DMOS FET
14-11
5050001112
N-Channel Enhancement-Mode Quad DMOS FET Analog Switch Arrays
14-15
50510011
N-Channel, Enhancement-Mode Quad DMOS FET Analog Switch Arrays
14-19
505200
N-Channel Enhancement-Mode Quad DMOS FET Driver Array
14-21
5054001112
Quad DMOS FET Analog Switch Arrays
14-23
VN0610LU2222LL
N-Channel Enhancement-Mode DMOS Power FETs
14-27
VN10KN3
N-Channel Enhancement-Mode DMOS Power FETs
14-29
VN10LMfl222LM
N-Channel Enhancement-Mode DMOS Power FETs
14-31
VQ1000
N-Channel Enhancement-Mode Quad DMOS Power FET Array
14-33
14-1
SECTION 15
15-1
Reliability and Quality Assurance
SECTION 16
16-1
Ordering Information
SECTION 17
17-1
Package Information
SEcnON 18
18-1
5ales Offices
vii
viii
ALPHANUMERIC PRODUCT LIST
1120
High-Speed Pin Driver
1321
Wideband, High Slew Rate Operational Amplifier
9-1
1322
Wideband, High Slew Rate Operational Amplifier
9-5
1332
High Performance Operational Amplijier
1344
Monolithic Wideband, JFET Input Operational Amplijier
9-13
1346
Monolithic Low Bias Current Operational Amplifier
9-17
1430
Fast Settling, FET Input Operational Amplifier
9-21
1435
Operational Amplijier-High-Frequency, Fast-Settling
9-27
1437
Operational Amplifier-Wideband, Fast-Settling
9-35
1438
Operational Amplijier-Wideband, Fast-Settling
9-45
1443
Operational Amplifier-Wideband, Fast-Settling, Fully-Differential, FET-Input
9-47
1460
Operational Amplifier-High-Speed, VMOS Output
9-55
1461
Operational Amplifier-High-Speed, High-Power, VMOS Output
9-61
1468 (TCPA12)
Operational Amplifier-High-voltage, Very-High-Power
9-69
1480
Operational Amplffier-Fast-Settling, High-Voltage
9-73
1481
Operational
Amplifier-High-Vo~age
9-77
1482
Operational Amplifier-High-Voltage
9-79
1900
Monolithic, High-Voltage Video Driver for CRT Monitors
10-1
1902
High-Voltage Video Driver for CRT Monitors
10-7
6·1
9-9
1903
High-Negative-Voltage Video Driver for CRT Monitors
4736
High-Reliability Hybrid
4743
High Frequency, Hybrid Voltage-to-Frequency Converter
3-19
4856
Low Cost Microcircu~ Sample/Hold Amplifier
9-81
4860
Fast, 12-Bit Sample/Hold Amplifier
9-85
2N700012
Power FETs-N-Channel, Enhancement-Mode DMOS
14-1
4731133
High Reliability Hybrid Voltage-to-Frequency Converters
8S170
N-Channel Enhancement-Mode DMOS Power FET
Frequency-to-Vo~age
Converter
10-13
3-11
3-1
14-3
COG201
Monolithic CMOS/DMOS, Quad SPST Analog Switch
12-1
COG211
Quad Monolithic, SPST CMOS/DMOS Analog Switch
12-7
COG2214
High-speed Analog Switch
12-13
COG2269
Dual SPOT CMOS/DMOS Analog Switch With Data Latch
12-17
COG30819
Quad Monolithic, SPST CMOSIDMOS Analog Switches
12-23
COG430819
Quad Monolithic, SPST CMOS/DMOS Analog Switches
12-23
COG4500
4-Channel CMOS/DMOS High-Frequency Mu~iplexer
12-31
COG5341
Dual Monolithic, SPST CMOSIDMOS ''T" Configuration Analog Switch
12-35
S01106
N-Channel Enhancement-Mode DMOS Power FETs
14-5
S0210·215
N-Channel Enhancement-Mode DMOS FET Switches
14-7
S0211 A·215A
N-Channel Enhancement-Mode DMOS FET Switches
S0304·6
N-Channel Enhancement-Mode Dual Gate DMOS FET
14-9
14-11
S05000/112
N-Channel Enhancement-Mode Quad DMOS FET Analog Switch Arrays
14-15
S051 00/1
N-Channel Enhancement-Mode Quad DMOS FET Analog Sw~ch Arrays
14-19
ix
ALPHANUMERIC PRODUCT LIST
S05200
N-Channel Enhancement-Mode Quad DMOS FET Driver Array
14-21
S05400/112
Quad DMOS FET Analog Switch Arrays
14-23
TC04105
Low Power, Band-Gap Voltage References
TC14261718
1.2A Dual High-Speed MOSFET Drivers
TC14433/AIB
3-1/2 DigitADC
7-1
6-3
1-213
TC15C2517
BiCMOS PWM Controllers
TC170
CMOS Current-Mode PWM Controller
TC17213
BiCMOS Current-Mode PWM Controller
5-9
TC18C4213/415
BiCMOS Current Mode PWM Controller
5-19
TC18C4617
CMOS Current Mode PWM Controller
5-25
TC232
Dual RS-232 Transmitter/Receiver and Power Supply
13-1
TC25C2517
BiCMOS PWM Controllers
5-13
TC28C42131415
BiCMOS Current Mode PWM Controller
5-19
TC28C4617
CMOS Current Mode PWM Controller
5-25
TC35C2517
BiCMOS PWM Controllers
5-13
TC38C4213/415
BiCMOS Current Mode PWM Controller
5-19
TC38C4617
CMOS Current Mode PWM Controller
5-25
TC42011213
Quad Single-Pole CMOS Analog Switches
TC4261718
Dual High-Speed Power MOSFET Drivers
TC429
5-13
5-1
12-39
6-9
----~~----------------------------------------------
Single High-Speed, CMOS Power MOSFET Driver
6-17
TC430
Fast CMOS CCD Driver
TC44112J3
Microprocessor Compatible CMOS Analog Switches.
12-45
6-25
TC444151617
Microprocessor Compatible CMOS Analog Switches
12-51
TC4401
6A Open-Drain MOSFET Driver
TC4403
1.5A High-Speed, Floating Load Driver
6-41
TC4404/5
1.5A Dual Open-Drain MOSFET Drivers
6-47
6-33
TC440617
3A Dual Open-Drain MOSFET Drivers
6-55
TC4420J9
6A High-Speed MOSFET Drivers
6-63
TC4421 12
9A High-Speed FET Driver
6-69
TC4423J415
3A Dual High-speed MOSFET Drivers
6-77
TC44261718
1.5A Dual High-Speed FET Drivers
6-85
TC4437/8J9
Power Logic CMOS Quad Drivers
6-93
TC4457/8J9
Power Logic CMOS Quad Drivers
6-93
TC4460161162163
Current-Sensing, 6 Amp Power MOSFET Driver
TC4467/8J9
Power Logic CMOS Quad Drivers
TC4487/8J9
Power Logic CMOS Quad Drivers
TC462617
Power CMOS Drivers with VDD Tripier
6-105
6-93
6-93
6-111
TC500/A
Integrating Converter Analog Processors
TC620/1
Solid State Temperature Sensor
2-1
4-1
TC626
Solid-State Temperature Sensor
. 4-7
TC67516
Fast NiCAD/Ni-Hydride Battery Charger
4-9
x
ALPHANUMERIC PRODUCT LIST
TC7106n
3-1/2 Digit AID Converter
1-115
TC7106A17A
3-1/2 Digit AID Converter
1-115
TC710919A
12-Bit ~P-Compatible Analog-to-Digital Converters
TC7116n
3-1/2 Digit Analog-to-Digital Converters with Hold
1-135
2-65
TC7116A17A
3-1/2 Digit Analog-to-Digital Converters with Hold
1-135
TC7126/6A
3-1/2 Digital Analog-to-Digital Converter
1-149
TC7129
4-1/2 Digit Analog-to-Digital Converter with On-Chip LCD Drivers
1-163
TC7135
4-1/2 Digit Analog-to-Digital Converter
1-177
TC7136/SA
Low Power, 3-1/2 Digit Analog-to-Digital Converters
1-191
TC7211112A
4-Digit CMOS Display Decoder/Driver
TC7211/12AM
Bus Compatible 4-Digit CMOS Decoder/Driver
11-1
11-15
TC7650
Chopper-Stabilized Operational Amplifiers
8-47
TC7652
Low Noise, Chopper-Stabilized Operational Amplifier
8-55
TC7660
DC-to-DC Voltage Converter
5-31
TC7662A
DC-to-DC Converter
5-43
TC800
15-Bit Plus Sign, Integrating Analog-to-Digital Converter
2-13
TC804
12-Bit ~P-Compatible MuHiplexed AID Converter
2-31
TCB07
2-1/2 Digit Analog-to-Digital Converter
TC811
3-1/2 Digit AID Converter with Hold and Differential Reference Inputs
1-13
TCB18
Auto-Ranging Analog-to-Digital Converter with 3-1/2 Digit and Bar-Graph Displays
1-27
TC820/1
Display AID Converters with Frequency Counter and Logic Probe
1-49
TC82213
3-3/4 Digit LCD Analog-to-Digital Converter
1-73
1-87
1-1
TC826
AID Converter with Bar Graph Display Output
TC835
Personal Computer Data Acquisition ADC
1-99
Te850
15-Bit, Fast-Integrating CMOS Analog-to-Digital Converter
2-51
TC8702
Binary Output Analog-to-Digital Converters
2-87
TC8704105
Binary Output Analog-to-Digital Converters
TC8750
3-1/2 Digit Analog-to-Digital Converter with Parallel BDC Output
TC900
Low Power, Chopper-Stabilized Operational Amplifier
8-1
TC901
Monolithic, Auto-Zeroed Operational Amplifier
8-9
TC911
Auto-Zeroed Monolithic Operational Amplifier
8-15
TC913
Dual Auto-Zeroed Operational Amplifier
8-21
TC914
Quad Auto-Zeroed Operational Amplifier
8-27
2-87
1-205
TC915
High-VoHage, Auto-Zeroed Operational Amplifier
8-33
TC918
Low-Cost CMOS Operational Amplifier
8-41
TC9400/112
Voltage-to-Frequency/Frequency-to-Voltage Converters
TC9404
Serial Input/16-Bit Parallel Output Peripheral Driver
11-25
3-23
11-31
TC9405
16-Bit Parallel-Latched Output Peripheral Driver
TC9420/1
High-VoHage, Auto-Zeroed Operational Amplifiers
8-63
TC962
High Current DC-to-DC Converter
5-49
TPO032
Operational Amplifier-High-Speed, FET-Input
9-91
xi
ALPHANUMERIC PRODUCT LIST
TP0033
High-Speed, Unity-Gain Buffer/Driver Amplifier
9-97
TP3554
Operational Amplifier-High-Speed, Wideband
9-103
14-27
VN0610LU2222LL
N-Channel Enhancement-Mode DMOS Power FETs
VN10KN3
N-Channel Enhancement-Mode DMOS Power FETs
14-29
VN10LMI2222LM
N-Channel Enhancement-Mode DMOS Power FETs
14-31
VQ1000
N-Channel Enhancement-Mode Quad DMOS Power FET Array
14-33
xii
Section 1
Display AID Converters
Display AID Converters
1
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
~~TELEDYNE
COMPONENTS
TC807
2-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Drives 2-1/2 Digit LED Displays
Internal Voltage Reference ........... 150 pprnl°C Max
Low Supply Current ••....•..•••.....•.••....•.•...•• 2 mA Max
Ratiometric Measurements
Auto-Zero Cycle Eliminates External Trimmers
Dynamic Range •.•..•..•..••••....•..•.•....••.•... ±200 Counts
Multiple Package Options
- Low-Cost 40-Pin Package
- 44-Pin Plastic Flat Package
- 44-Pin PLCC Package
The TCB07 is a 2-1/2 digit analog-to-digital converter
(ADC) designed to drive standard 7-segment LED displays
without external drive electronics.
This 0.5% resolution converter is ideal for low-cost
pressure, temperature, pH or flow-rate indicators.
The TCB07 features differential inputs and references
for ratio metric readings. An auto-zero cycle eliminates external offset adjustment potentiometers.
This dual-slope converter automatically rejects 50-,
60- and 400-Hz line frequency interference signals. Polarity information is displayed, giving the device a ±200 count
dynamic range.
Overall system cost is reduced by incorporating a lowtemperature coefficient voltage reference on-chip.
O.lI-1F
COMMON
ANODE
LED
34
+
ANALOG
INPUT
1 Mn
31
C~EF
CiiEF
v~
9-19
22-25
30 ViN
POL
O.OlI-1F
32
BP
COMMON
SEGMENT
DRIVE
20
21
1
v+ 1-!---_4I----Q
+5V
.,~
VBUFF TeaO?
47k!l
V~EF
CAZ
0.2211F
36
VREF
V-
1 k!l
--5V
TO ANALOG
COMMON (PIN 32)
39
3 CONVERSIONS/SEC
200 mV FULL SCALE
100 k!l
Figure 1. Typical Operating Circuit
1088-1
1-1
2-1/2 DIGIT
ANALOG-TO-DIGITAL·CONVERTER
TC807
PIN CONFIGURATIONS
I
C2
I
l'~S
82
""
TC807CPL
A2
F2
E2
D3
L
10'S
83
F3
E3
100's- AB4
POL -
......_ _ _.....1.--
NC = NO INTERNAL CONNECTION
""
""
TC807CKW
TC807CLW
(FLAT PACKAGE)
(PLCC)
1-2
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
ORDERING INFORMATION
Part No.
Package
TCS07CPL
40-Pin Plastic DIP
Temperature Range
O·Cto +70·C
TCS07CKW
44-Pin Plastic Flat
O·Cto +70·C
TCS07CLW
44-Pin PLCC
O·Cto +70·C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
V+ .......................................................................... +6V
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 60 Sec) ................. +300°C
V- ..........................................................................-9V
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under 'Absolute Maximum Ratings' may cause pennanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
effect device reliability.
Analog Input Voltage (Either Input) (Note 1) ........ V+ to VReference Input Voltage (Either Input) ................. V+ to VClock Input ........................................................ GND to V+
Power Dissipation (Note 2) .................................. 800 mW
Operating Temperature Range .................... O°C to +70°C
ELECTRICAL CHARACTERISTICS: TA =+25°C, fClK =48 kHz, unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Zero Input Reading
Max
VIN= OV
Full Scale = 200 mV
-0
±o
+0
Digital
Reading
Ratiometric Reading
VIN= VREF
VREF= 100 mV
99
991100
100
Digital
Reading
Roll-Over Error (Difference in
Reading for Equal Positive and
Negative Reading Near Full Scale)
-VIN = +VIN = 200 mV
-1
±0.2
+1
Counts
Linearity (Max Deviation from
Best Straight Line Fit)
Full Scale = 200 mV
or Full Scale = 2V
-1
±0.2
+1
Counts
Common-Mode Rejection
Ratio (Note 3)
VCM = ±lV, VIN = OV
Full Scale = 200 mV
INN
Noise (Peak-Peak Value Not
Exceeded 95% of Time)
VIN = OV, Full Scale = 200 mV
15
-
Leakage Current at Input
VIN=OV
Zero Reading Drift
VIN= OV
Supply Current (Does Not Include
LED Current)
VIN= OV
Internal Voltage Reference
(Analog Common Potential
wnh Respect to Positive Supply)
25 kW Between Common
and Posnive Supply
Temperature Coefficient of
Analog Common (With Respect
to Positive Supply)
25 kW Between Common
and Posnive Supply
O·C S; T A S; 70·C
-
50
1
25
0.2
5
Ilvrc
O.S
2
rnA
2.7
3.05
3.35
V
-
20
150
ppml·C
-
rnA
rnA
V+ = 5V, Segment Voltage = 3V
4
S
Segment Sinking Current, Pin 19
V+ = 5V, Segment Voltage
=3V
S
16
1-3
IlV
-
Segment Sinking Current (Except Pin 19)
NOTES: 1. Input voltages may exceed supply voltages, provided input current is limited to ±loo !lA.
2. Dissipation rating assumes device is mounted with all leads soldered to PC board.
3. Refer to 'Differential Input' discussion.
Unit
pA
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
PIN DESCRIPTION
40-Pin DIP
Pin Number
Name
Description
V+
Pos~ive
2
NC
No connection.
3
NC
No connection.
4
NC
No connection.
5
NC
No connection.
6
NC
7
NC
No connection.
No connection.
8
NC
No connection.
9
Activates the D section of the un~s display.
10
D1
C1
Activates the C section of the un~s display.
11
91
Activates the 9 section of the units display.
12
A1
Activates the A section of the units display.
13
F1
Activates the F section of the un~s display.
14
E1
Activates the E section of the units display.
15
D2
Activates the D section of the tens display.
16
92
Activates the 9 section of the tens display.
17
F2
18
E2
Activates the F section of the tens display.
Activates the E section of the tens display.
supply voltage.
19
A93
Activates both halves of the "1" in the hundreds display.
20
POL
Activates the negative polarity display.
21
GND
22
G2
Activates the G section of the tens display.
23
A2
C2
Activates the A section of the tens display.
24
25
G1
Activates the G section of the ones display.
Negative power supply voltage.
Digital ground.
Activates the C section of the tens display.
26
V-
27
VINT
Integrator output. Connection point for integration capacitor. See "Integrating Capacitor" for additional
details.
28
VBUFF
Integration resistor connection. Use a 47 k.Q resistor for 200 mV full-scale range and a 470 k.Q resistor
for 2V full-scale range.
29
CAZ
30
31
VIN
VIN+
32
COMMON
33
CREF
CREF+
34
35
36
VREF
VREF+
The size of the auto-zero capacitor influences the system noise. Use a 0.471lF capacitor for 200 mV
full scale, and a 0.47 IlF capacitor for 2V full scale. See "Auto-Zero Capacitor" for more details.
The analog low input is connected to this pin.
The analog high input is connected to this pin.
This pin is primarily used to set the analog common-mode voltage for battery operation or in systems
where the input signal is referenced to the power supply. See "Analog Common" for more details. It
also acts as a reference voltage source.
See pin 34.
A 0.1 IlF capacitor is used in most applications. If a large common-mode voltage exists (for example
the VIN- pin is not at analog common), and a 200 mV scale is used, a 1 IlF capacitor is recommended
and will hold the roll-over error to 0.5 count.
See pin 36.
The analog input required to generate a full-scale output (199 counts). Place 100 mV between pins
35 and 36 for 200 mV full scale. Place 1V between pins 35 and 36 for 2V full sell Ie. See "Reference
Voltage."
1-4
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
PIN DESCRIPTION (Cont.)
40-Pin DIP
Pin Number
Name
37
TEST
Description
Lamp test. When pulled high (to V+), all segments will be turned on and the display should read
"-188". It may also be used as a negative supply for externally-generated decimal points. See "Test"
for
38
39
40
add~ional
information.
OSC3
See pin 40.
OSC2
See pin 40.
OSC1
Pins 40, 39, and 38 make up the oscillator section. For a 48 kHz clock (three readings per second),
connect pin 40 to the junction of a 100 kn resistor and a 100 pF capacitor.The 100 kn resistor is held
to pin 39 and the 100 pF capac~or is tied to pin 38.
ANALOG SECTION
Figure 2 is a block diagram of the TC80? Each
measurement cycle is divided into three phases: (1) autozero (A-Z) , (2) signal integration (51), and (3) reference
integration (RI). The conversion rate is set by the clock
oscillator frequency and is independent of the analog input
amplitude.
Polarity is determined at the end of the signal integrate
phase. The sign bit is a true polarity indication, in that signals
less than 1 L5B are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
Reference-Integrate Cycle
Auto-Zero Cycle
The final phase is reference integrate or deintegrate.
VIN- is internally connected to analog common and VIN+ is
During the auto-zero cycle, the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero-input condition. Additional analog gates close a feedback loop around the integrator and
comparator. This loop permits comparator offset voltage
error compensation. The voltage level established on CAZ
compensates for device offset voltages. The offset error
referred to the input is less than 10 ltV.
The auto-zero cycle length is 4000 to 12,000 clock
cycles.
connected across the previously charged reference capacitor. Circuitry within the chip ensures the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal, and is
between 0 and 8000 clock cycles. The digital reading
displayed is:
100
x~.
VREF
DIGITAL SECTION
Signal-Integrate Cycle
The TC80? contains all the segment drivers necessary
to directly drive a 2-1/2 digit LED display. The segment is
typically 8 rnA. The 1OO's output (pin 19) sinks current from
two LED segments, and has a 16-rnA drive capability. The
TC80? is designed to drive common anode LED displays.
(See Figure 2.)
The polarity indication is "ON" for negative analog
inputs. If VIN- and VIN+ are reversed, this indication can be
reversed also, if desired.
The display font is shown in Figure 3.
The auto-zero loop is opened, the internal short removed, and the internal differential inputs connect to VIN+
and VIN-. The differential input signal is integrated for a fixed
time period. The signal integration period is 4000 cycles.
The integration time period is:
4
tSI = f-- X 1000,
osc
where fasc = external clock frequency.
The differential input voltage must be within the device's
common-mode range (1 V of either supply) when the converter and measured system share the same power supply
common (ground). 1fthe converter and measured system do
not share the same power supply common, VIN- should be
tied to analog common.
System Timing
The oscillator frequency is +4 prior to clocking the internal decade counters. The three-phase measurement
cycle takes a total of 16,000 clock pulses.
1-5
2-1/2 DIGIT
ANALOG-TO-DiGITAL CONVERTER
TC807
LED DISPLAY
B B
TYPICAL SEGMENT OUTPUT y+
y+
IN
31
y~o--+~DO~~---+---------~--;
All
~'"
TC807
L_t-:L_+-_~=~
26
y-
Figure 2. Block Diagram
Hi
TO
DIGITAL
SECTION
__~=~~=-
_____
~2t101 DIGITAL
GND
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
Each phase ofthe measurement cycle has the following
length:
0123'156789
where fose is the externally set clock frequency.
Component Value Selection
Auto-Zero Capacitor (CAZ)
The CAZ size has some influence on system noise. A
0.471lF capacitor is recommended for 200 mV full scale. A
0.047IlF capacitor is adequate for 2V full-scale applications.
A Mylar-type dielectric capacitor is adequate.
Nominal Full-Scale VoHage
2V
200 mV
Component
Value
CAZ
Reference Voltage Capacitor (CREF)
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
cycle is stored on CREF. A 0.1 IlF capacitor is acceptable
when VIN- is tied to analog common. If a large commonmode voltage exists (VREF- ~ analog common) and the
application requires a 200-mV full scale. increase CREF to
1 IlF. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
0.4711F
0.047 11F
471<0
4701<0
0.2211F
0.2211F
NOTE: lose = 48 kHz (3 readings/second)
Oscillator Components
Rose (pin 40 to pin 38) should be 1 00 kn. Case is selected from the equation:
fose = 0.45
RC .
Integrating Capacitor (CINT)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage reference. For this case. a ±2V full-scale integrator output swing
is satisfactory. For 3 readings/second (fose = 48 kHz). a
0.22llFvalue is suggested. If a different oscillator frequency
is used. CINT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
An exact expression for CINT is:
INT=
81
Integrating Resistor (RINT)
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling current is
100 JJA. The integrator and buffer can supply 20 JJA drive
currents with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region but not so large
that printed circuit board leakage currents induce errors. For
a 200 mV full scale. RINT is 471<.0. A 2V full scale requires
4701<.0.
[to:e] .
(3) Reference Integrate: 0 to 8000 clock pulses.
C
I-I 8
Figure 3. Display Font and Segment Assignment
(2) Signal Integrate: 4000 clock pulses - This time
period is fixed. The integration period is:
tSI = 4000
r1oo·sT10·sT1·s-,
DISPLAY FONT
(1) Auto-Zero Phase: 4000 to 12.000 clock pulsesFor signals less than full-scale. the auto-z!"ro phase
is assigned the unused reference integrate time
period.
For fosc of 48 kHz. Case is 100 pF. nominally.
Note that fose is +4 to generate the TC807 internal
control clock.
To achieve maximum rejection of 60 Hz noise pickup.
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz. 120 kHz. 80 kHz. 60 kHz.
40 kHz. 33-1/3 kHz. etc .• should be selected. For 50 Hz
rejection. oscillator frequencies of 200 kHz. 100 kHz. 66-21
3 kHz. 50 kHz. 40 kHz. etc .• would be suitable. Note that
40 kHz (2.5 readings/second) will reject both 50 and 60 Hz
(also 400 and 440 Hz).
(4000) (-f1)(VFS)
ose RINT
Reference Voltage Selection
A full-scale reading (280 counts) requires the input
signal be twice the reference voltage.
where: fose = Clock frequency at pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing.
CINT must have low dielectric absOlption to minimize
roll-over error. An inexpensive polypropylene capacitor is
recommended.
1·7
Required Full-Scale VoHage*
VREF
200mV
100mV
2V
1V
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVEftTER
TC807
In some applications, a scale factor other than unity
may exist between a transducer output voltage and the
required digital reading. For example, assume a pressure
transducer output for 200 Iblin.2 is 400 mY. Rather than
dividing the input voltage by two, the reference voltage
should be set to 200 mY. This permits the transducer input
to be used directly.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to
zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied
between analog common and VIN- . The transducer output
is connected between VIN+ and analog common.
The internal voltage reference potential available at
analog common is normally used to supply the converter's
reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
where an externally-generated reference voltage is desired, refer to Figure 4.
y+
I
y+
Y~EF
Y~~ REF
~:>
'l~
6.8Y
A ZE NER
Iz
•
TCB07
(a)
y+
I
y+
~~
DEVICE PIN FUNCTIONAL DESCRIPTION
Differential Signal Inputs
6.8kn
...
4~
Y~EF ~$20 kO '.l (
?
TCB07
"iiEF
,. ...
TC04
1.2Y REF
COMMON
VIN+ (Pin 31), VIN- (Pin 30)
The TC807 is designed with true differential inputs
and accepts input signals within the input stage commonmode voltage range (VCM). The typical range is V+ -1V to V+1V. Common-mode voltages are removed from the system
when the TC807 operates from a floating power source
(isolated from measured system) and VIN- is connected to
analog common.
In systems where common-mode voltages exist,
the 86 dB common-mode rejection ratio minimizes error.
Common-mode voltages do, however, affect the integrator
output level. Integrator output saturation must be prevented.
A worst-case condition exists if a large positive VCM exists in
conjunction with a full-scale negative differential signal. The
negative signal drives the integrator output positive along
with VCM (Figure 5). For such applications, the integrator
output swing can be reduced below the recommended 2V
full-scale swing. The integrator output will swing within 0.3V
of V+ or V- without increasing linearity errors.
(b)
Figure 4. External Reference
+
~
YI =
[YCM =YIN!
Where:
I
tl = Integration Time = 4
f 000
asc
CI = Integration Capacitor
RI = Integration Resistor
Differential Reference
Figure 5. Common-Mode Yoltage Reduces Available Intagrator
Swing (YCDII Y!N)
*
VREF+ (Pin 36), VREF-(Pln 39)
The reference voltage can be generated anywhere
within the V+ to V- power supply range.
To pr.event roll-over errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
1·8
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
Analog Common
(2) The signal is less than ±1.SV.
Analog COMMON (pin 32) is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.3SV below V+. Analog common is
tied internally to an N-channel FET capable of sinking 30
mAo This FET will hold the common line at 3V should an
external load attempt to pull the common line toward V+.
Analog common source current is limited to 10 !lA.
Therefore, analog common is easily pulled to a more
negative voltage (i.e., below V+ -3V).
The TC807 connects the internal VIN+ and VIN- inputs
to analog common during the auto-zero cycle. During the
reference-integrate phase, VIN- is connected to analog
common. If VIN- is not externally connected to analog common, a common-mode voltage exists. This is rejected by
the converter's 86-dB common-mode rejection ratio. In
systems where VIN- is connected to the power supply
ground or to a given voltage, analog common should be
connected to VIN-.
Analog common serves to set the analog section reference or common point. The common potential has a
0.001%/% voltage coefficient and 1S0 output impedance.
With sufficiently high total supply voltage (V+ -V->7V),
analog common is a very stable potential with excellent
temperature stability (typically 20 pprn/°C). This potential
can be used to generate reference voltage.
If analog common is connected to power ground, the
internal reference is disabled. An external reference is
required when analog common is connected to power
ground.
(3) An external reference is used.
(4) The TC7660 DC-to-DC converter may also be used
to generate -SV from +SV (Figure 7).
Ratiometric Resistance Measurements
True differential input and differential reference make
ratiometric readings possible. Typically, in a ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display
will read 100. The displayed reading can be determined from
.
the following expression:
Displayed reading = RUNKNOWN x 100.
RSTANDARD
The display will overrangefor RUNKNOWN;;.2
x RSTANDARD.
V+=5V
Test
TEST (pin 37) potential is SV less than V+. Iflest is pulled
high (to V+), all segments plus the minus sign will be activated.
The test pin will sink about 10 mA when pulled to V+.
V+
OSC l
osc2
OSC3
~~
POWER SUPPLIES
TC807
The TC807 is designed to work from ±SV supplies.
However, if a negative supply is not available, it can be
generated from the clock output with two diodes, two capacitors, and an inexpensive IC. (See Figure 6.)
In selected applications, a negative supply is not required. The conditions to use a single +5V supply are:
GND 1------+
VV-=-3.3V
(1) The input signal can be referenced to the center of
the common-mode range of the converter.
Figure 6. Generating Negative Supply From +5V
1·9
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
.•..:..::...:....::..:'-'-----.......----o..sv
..sV
VREF 35
...
COM 32
~""
le807
1 Mn
~
le807
+
0.0111F IN
+
V~ J.:3"'1_.....""'rv-.a
VIN
VjNI-'3;.:;0-+---o
[J---------r---o~V
GND 21
V26
8
Figure 9. Internal Reference (200 mV Full Scale, 3 RPS,
VIN- Tied to Ground for Single· Ended Inputs)
Figure 7. Negative Power Supply Generation With TC7660
~T~O~PI~N~1_ _ _ _ _~_ _ _ _OV+
24kn
[J-~~--~~25kn
RSTANDARD
Q-+-+---I vj'N
RUNKNOWN
~'"
le807
~""
le807
1 Mn
+
0.011'F IN
o--......-IVjN
COMMON
rJ------------oV-
Figure 8. Low Parts Count Ratiometric Resistance Measurement
Figure 10. Recommended Component Values for 2VFull Scale
1010
2-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC807
~~~~--------~---------ov+
..,,,
TC807
1 MQ
~~~~--------~--------_ov+
..,,,
..,,,
TC04
TC04
..,,,
+
O.OlI1F IN
TC807
1 MQ
+
O.OlI1F IN
[J---------------------ov-
Rgure 11. TCB07 With a 1.25V External Band-Gap Reference
(V'N- Tied to Common)
Figure 12. TCS07 Operated From Single +5V Supply (An External
Reference Must Be Used in This Application)
1-11
NOTES
1-12
"~TELEDYNE
COMPONENTS
TC811
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
FEATURES
TYPICAL APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Differential Reference Input
Display Hold Function
Fast Over-Range Recovery, Guaranteed Next
Reading Accuracy
Low Temperature Drift Internal Reference
35 ppm/°C (Typ)
Guaranteed Zero Reading With Zero Input
Low Noise .................................................... 15 I1Vp-p
High Resolution (0.05%) and Wide Dynamic
Range (72 dB)
High Impedance Differential Input
Low Input Leakage Current ....................... 1 pA Typ
10 pA Max
Direct LCD Drive-No External Components
Precision Null Detection with True Polarity at Zero
Crystal Clock Oscillator
Available in DIP, Compact Flat Package or PLCC
Convenient 9V Battery Operation with
Low Power Dissipation (60011A Typical, 1mW
Maximum)
•
•
•
•
•
•
•
Thermometry
Digital Meters
- VoltagelCurrentIPower
- pH Measurement
- Capacitancennductance
- Fluid Flow Rate/Viscosity
-Humidity
-Position
Panel Meters
LVDT Indicators
Portable Instrumentation
Digital Scales
Process Monitors
Gaussometers
Photometers
FUNCTIONAL DIAGRAM
TYPICAL SEGMENT OUTPUT
--~--v·
LCD DISPlAY
""
TC811
,,i---,,
,,,
,
CtiEF
i"'~'~~+'~",,+-_~~~~~~~CcW~lTo.~
v;'r
,,
,,,
t~~~'u~_~r-~~
ViN ::JO
4348 III F01
1089-1 (4348)
1-13
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
GENERAL DESCRIPTION
The TC811 is a low power, 3-1/2 digit, LCD display
analog-to-digital converter. This device incorporates both a
display hold feature and differential reference inputs. A
crystal oscillator, which only requires two pins, permits
added features while retaining a 40-pin package. An additional feature is an "Integrator Output Zero" phase which
guarantees rapid input overrange recovery.
The TC811 display hold (HLDR) function can be used to
"freeze' the LCD display. The displayed reading will remain
indefinitely as long as HLDR is held high. Conversions
continue but the output data display latches are not updated.
The TC811 also includes a differential reference for easy
ratiometric measurements. Circuits which use the
7106/26/36 can easily be upgraded to include the hold
function with the TC811.
The TC811 has an improved internal zener reference
voltage circuit which maintains the Analog Common temperature drift to 35ppml°C (typical) and 75ppml°C (maximum). This represents an improvement of two to four times
over similar 3-1/2 digit converters, eliminating the need for
a costly, space consuming external reference source.
The TC811 limits linearity errorto less than one count on
both the 200mV and the 2.00V full-scale ranges. Rollover
error-the difference in readings for equal magnitude but
opposite polarity input signals-is below ±1 count. High
impedance differential inputs offer 1pA leakage currents
and a 1012.0 input impedance. The 15/lVp-p noise performance guarantees a "rock solid" reading. The Auto Zero
cycle guarantees a zero display readout for a zero voH input.
ThesingiechipCMOSTC811 incorporates all the active
devices for a 3-1/2 digit analog to digital converter to directly
drive an LCD display. Onboard oscillator, precision voltage
reference and display segment and backplane drivers simplify system integration, reduce board space requirements
and lower total cost. A low cost, high resolution (0.05%)
indicating meter requires only a TC811, an LCD display, five
resistors, six capacitors, a crystal, and a 9V battery. Compact, hand held multimeterdesigns benefit from the Teledyne
Semiconductor small footprint package option.
The TC811 uses a dual slope conversion technique
which will reject interference signals if the converters integration time is set to a muHiple of the interference signal
period. This is especially useful in industrial measurement
environments where 50, 60 and 400Hz line frequency signals are present.
ORDERING INFORMATION
Part No.
TC811CPL
TC811 RCPLI
TC8111JL
TC811CKW
TC811CLW
Package
40-Pin
40-Pin
40-Pin
44-Pin
44-Pin
Temperature Range
Plastic
Plastic
CerDIP
Flat
PLCC
0° to 70°C
0° to 70°C
-25° to 85°C
0° to +70°C
0° to +70°C
NOTES: 1. Reversed pin-out
1-14
VREFTempCo
75 ppml°C Max
75 ppml°C Max
100 ppml°C Max
75 ppml°C Max
75 ppml°C Max
3·1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
PIN CONFIGURATIONS
..
w
!
HLDR
1
esc1
esc1
12
OSC2
y+
OSC2
y+
TEST
TEST
1°
1'.
~
10's
~
100'.
L
CAZ
CAZ
VaUFF
VaUFF
YINT
Y-
I_1:
G2l
C3
A3
G3
2
J
100'.
A:
G3
BP
BP
(BACKPLANE)
(BACKPLANE)
POL
(MINUS SIGN)
Ne = NO INTERNAL CONNECTION
4348 ILL F02
1-15
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Commercial Package (C) ....................... O°C to +70°C
Industrial Package (I) ......................... -25°C to +85°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (soldering, 60 sec) .................. +300°C
Supply Voltage (V+ to V-) ........................................... 15V
Analog Input voltage {Either Input)1 .................... V+ to VReference Input Voltage ...................................... V+ to VClock Input ...................................................... TEST to V+
Power Dissipation2
CerDIP Package (J) ..................................... 1000 mW
Plastic Package (P, K) ................................... 800 mW
Plastic Leaded Chip Carrier (L) ..................... 800 mW
ELECTRICAL CHARACTERISTICS:
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Vsuppl y = 9V, fCLOCK= 32.768kHz, and TA = 25·C, unless otherwise noted.
Min
Typ
Max
-000.0
±OOO.O
+000.0
Unit
Parameter
Test Conditions
-
Zero Input Reading
VIN= OV
VFS= 200mV
-
Zero Reading Drift
VIN = OV, O·C s T AS 70·C
-
0.2
1
Ratiometric Reading
VIN = VREF, VREF = 100mV
999
999/1000
1000
NL
Linearity Error
VFS = 200mV or 2.000V
-1
±0.2
+1
ER
Roll Over Error
VIN- = VIN+
-1
±0.2
+1
Counts
eN
Noise
VIN = OV, VFS = 200mV
-
15
-
ILVp-p
10
pA
50
-
ILVN
-
1
5
ppml·C
-
Symbol
Input
Z
200mV
IL
Input Leakage Current
VIN= OV
CMRR
Common-Mode Rejection
VCM = ±1 V, VIN = OV,
VFS= 200mV
TCSF
Scale Factor Temperature
Coefficient
VIN = 199mV, O·C S TAS 70·C
(ext. VREF tc = Oppm)
1
Digital
Reading
ILV/·C
Digital
Reading
Counts
Analog Common Section
VCTC
Vc
Analog Common
Temperature Coefficient
Analog Common Voltage
250Kn from V + to Analog Common
O·C S TA S 70·C
"C" Commercial
"I" Industrial
-
35
35
75
100
ppml·C
ppml·C
250Kn from V+ to Analog Common
2.7
3.05
3.35
Volts
-
Hold Pm Input Section
Input Resistance
Pin 1 to Pin 37
VIL
Input Low Voltage
Pin 1
VIH
Input High Voltage
Pin 1
V+ -1.5
70
-
-
kQ
Test +1.5
V
-
V
LCD Drive Section 3
VSD
LCD Segment Drive VoHage
V+toV-=9V
4
5
6
Vp_p
VSD
LCD "Backplane Drive Voltage V+to V-= 9V
4
5
6
Vp_p
-
70
100
ILA
90
125
IJ.A
Power Supply
Isup
Power Supply Current
VIN = OV, V+to V-= 9V
fosc= 16kHz
fosc = 48kHz
NOTES: 1. Input voltages may exceed supply voltages when Input current IS limited tol OO~.
2. Dissipation rating assumes device is mounted with all leads soldered to a printed circuit board.
3. Backplane drive is in phase with the segment drive for 'segment off' 180° out of phase for 'segment on.' Frequency is 20 times the
conversion rate. Average DC component is less than 5OmV.
1-16
3·1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
PIN DESCRIPTION
40-Pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
44-Pin
PLCC
Name
2
3
4
5
6
7
8
9
10
11
13
14
15
16
HLDR
Function
Hold pin, logic 1 holds present display reading
D1
Activates the D section of the units display
C1
Activates the C section of the units display
B1
A1
Activates the B section of the units display
Activates the A section of the units display
F1
Activates the F section of the units display
G1
Activates the G section of the units display
E1
Activates the E section of the units display
D2
Activates the D section of the tens display
~
B2
Activates the C section of the tens display
A2
Activates the A section of the tens display
F2
Activates the F section of the tens display
E2
Activates the E section of the tens display
17
Da
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
Ba
Activates the D section of the hundreds display
Activates the B section of the hundreds display
Fa
Activates the F section of the hundreds display
Ea
AB4
Activates the E section of the hundreds display
POL
Activates the negative polarity display
Activates the B section of the tens display
Activates both halves of the 1 in the thousands display
BP
Backplane drive output
Ga
Activates the G section of the hundreds display
As
Activates the A section of the hundreds display
Ca
Activtes the C section of the hundreds display
G2
V-
Negative power supply voltage
VINT
VSUFF
Activates the G section of the tens display
Integrator output, connection for CINT
Buffer output, connection for RINT
CAZ
Integrator input, connection for CAZ
VIN-"
Analog input low
VIN+
COM
Analog input high
Analog Common: Internal zero reference
VREF-
Reference input low
CRE~
Negative connection for reference capacitor
CREF+
Positive connection for reference capacitor
VREF+
TEST
All LCD segment test when pulled high (V+)
V+
Reference input high
Positive power supply voltage
OSC2
Crystal oscillator output
OSC1
Crystal oscillator input
1-17
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
ANALOG
INPUT
SIGNAL
3.
ANALOG
INPUT
0--0
C~EF
1 Mn
31
+
V~
O.01IJF
30 ViN
32
POL
BP
~~~~~~
v+
REF
VOLTAGE
'11~
Teall
HLDR
180 kfl
V~EF
c",
O.068IJF
TO ANALOG COMMON
",.0
~~
(PIN 32)
w~
v'----ll---+---j I----'+--lr----- v'
4348 ILL F03
4346 ILL F04
Figure 1 Typical Operating Circuit
Figure 2 Basic Dual Slope Converter
GENERAL THEORY OF OPERATION
30
Dual-Slope Conversion Principles
~
The TC811 is a dual slope, integrating analog-to-digital
converter. An understanding of the dual slope conversion
technique will aid the user in following the detailed TC811
theory of operation following this section. A conventional
dual slope converter measurement cycle has two distinct
phases:
1) Input Signal Integration
2) Reference Voltage Integration (Deintegration)
Referring to Fig 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(TINT), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (de integration) time (TDEINT) is then
directly proportional to the unknown input voltage (VIN).
In a simple dual slope converter, a complete conversion
requires the integrator output to "ramp-up" from zero and
"ramp-down" back to zero. A simple mathematical equation
relates the input signal, reference voltage and integration
time:
I"
V
I V
y/
z
o
tw
v/
20
~
w
a:
w
o
o
/
/
:E 10
I
.J
~
a:
oz
o
--
1/
V
V
O.lfT
Rgure 3
IIII
I I I 1111
INPUT FREQUENCY
Normal-Mode Rejection of
Dual Slope Converter
tDEINT]
VIN=VREF [ tiNT
1-18
T =MEASUREMENT PERIOD
1fT
For a constant VINT:
where:
VREF = Reference voltage
tiNT = Integration Time
tDEINT = Deintegration Time
/
10fT
4346 ILL F05
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
Accuracy in a dual slope converter is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit of
the dual slope technique is noise immunity. Noise spikes are
integrated or averaged to zero during the integration periods, making integration ADCs immune to the large conversion errors that plague successive approximation converters in high noise environments. Interfering signals, with
frequency components at multiples of the averaging (integrating) period, will be attenuated. (see Fig 3). Integrating
ADCs commonly operate with the signal integration period
set to a multiple of the SO/60Hz power line period.
INT
y
DE-I NT
II
r
1000 +J
1+1-20oo+J
-
-
--ft--11-140
ZI-+I---------------------~
AZl!-_________________________
I"
I
I
::;l
~~ 910-2900
~I
4000
4348 III f06
THEORY OF OPERATION
Analog Section
Figure 4a
In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC811 design incorporates an "Integrator Output Zero" cycle and an "Auto Zero"
cycle. These additional cycles ensure the integrator starts
at OV (even after a severe over-range conversion) and that
all offset voltage errors (buffer amplifier, integrator and
comparator) are removed from the conversion. A true digital
zero reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
(1)
(2)
(3)
(4)
Integrator Output Zero Cycle
Auto Zero Cycle
Signal Integrate Cycle
Reference Deintegrate Cycle
Conversion Timing During Normal Operation
F10oo+Jr..._ _ _ _ _ _~r
~2oo1-2090:=:::;J
I
INT
DE-I NT ....;.---------.....
ZI
I
.
31-640~
I
30~10--rl-
AZ . ,
/..
4000
=.·r
4349 ILL f07
Figure 4b
Integrator Output Zero Cycle
Conversion Timing During Overrange Operation
during the measurement cycle. The Auto Zero cycle residual is typically 10 to 15JlV.
The Auto Zero duration is from 910 to 2,900 counts for
non-over-range conversions and from 300 to 91 0 counts for
over-range conversions.
This phase guarantees that the integrator output is at
zero volts before the system zero phase is entered, ensuring
that the true system offset voltages will be compensated for
even after an over-range conversion. The duration of this
phase is variable, being a function of the number of counts
(clock cycles) required for deintegration.
The Integrator Output Zero cycle will last from 11 to 140
counts for non-over-range conversions and from 31 to 640
counts for over-range conversions.
Signal Integration Cycle
Upon completion of the Auto Zero cycle, the Auto Zero
loop is opened and the internal differential inputs connect to
VIN+ and VIN-. The differential input signal is then integrated
for a fixed time period which, in the TC811 is 1000 counts
(4000 clock periods). The externally set clock frequency is
divided by four before clocking the internal counters. The
integration time period is:
Auto Zero Cycle
During the Auto Zero cycle, the differential input signal
is disconnected from the measurement circuit by opening
internal analog switches and the internal nodes are shorted
to Analog Common (OV ref.) to establish a zero input
condition. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
CAZ then compensates for internal device offset voltages
TINT =
4000
fose
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground).
1·19
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
If the converter and measured system do not share the same
power supply common, as in battery powered applications,
VIN- should be tied to Analog Common.
Polarity is determined at the end of signal integration
phase. The sign bit is a 'true polarity" indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection which is limited only by device
noise and Auto Zero residual offsets.
the need for an external reference. Some minor component
changes are required to upgrade existing designs, reduce
power dissipation, and improve the overall performance.
(see Oscillator Components)
Digital Section
The TC811 contains all the segment drivers necessary
to directly drive a 3-1/2 digit liquid crystal display (LCD). An
LCD backplane driver is included. The backplane frequency
is the external clock frequency divided by 800. For three
conversions/second the backplane frequency is 60Hz with
a 5V nominal amplitude. When a segment driver is in phase
with the backplane signal the segment ot':bFP'. An out of
phase segment drive signal causes the segment to be "ON"
or visible. This AC drive configuration results in negligible
DC voltage across each LCD segment. This insures long
LCD display life. The polarity segment driver is "ON" for
negative analog inputs. If VIN+ and VIN- are reversed then
this indicator would reverse.
Reference Integrate (Deintegrate) Cycle
The reference capacitor, which was charged during the
Auto Zero cycle, is connected to the input of the integrating
amplifier. The internal sign logic insures that the polarity of
the reference voltage is always connected in the phase
which is opposite to that of the input voltage. This causes the
integrator to ramp back to zero at a constant rate which is
determined by the reference potential.
The amount of time required (TDEINT) for the integrating
amplifier to reach zero is directly proportional to the amplitude of the voltage that was put on the integrating capacitor
(VINT) during the integration cycle:
TDEINT
=
TEST Function (TEST)
RINT CINT VINT
V
REF
On the TC811, when TEST is pulled to a logical "HIGH",
all segments are turned "ON". The display will read "-1SSS".
During this mode the LCD segments have a constant DC
voltage impressed. Do not leave the display in this mode for
more than several minutes. LCD displays may be destroyed
if operated with DC levels for extended periods.
The display FONT and segment drive assignment are
shown in Figure 5.
The digital reading displayed Is:
Digital Count
=1000
VIN+-VIN-"'-V:-:---"-'REF
The oscillator frequency is divided by 4 priorto clocking
the internal decade counters. The four phase measurement
cycle takesa total of 4000 counts or 16000 clock pulses. The
4000 count cycle is independent of input signal magnitude
or polarity.
Each phase ofthe measurement cycle has the following
length:
DISPLAY FONT
0123'156789
il000'ST100'ST10'sTl'Sl
1) Auto Zero: 300 to 2900 Counts
2) Signal Integrate: 1000 Counts
1--1 8 8 81
This time period is fixed. The integration period is:
4000
fosc
= 1000 Counts
4348 ILL
Figure 5
Where fosc is the crystal oscillator frequency.
Foe
Display FONT and Segment Assignment
HOLD Reading Input (HLDR)
3) Reference Integrate: 0 to 2000 Counts
4) Integrator Output Zero: 11 to 640 Counts
When HLDR is at a logic "HI" the latch will not be
updated. Conversions will continue but will not be updated
until HLDR is returned to "LOW'. To continuously update the
display, connect HLDR to ground or leave it open. This input
is CMOS compatible and has an internal resistance of 70Kn
(typical) tied to TEST.
The TC811 can replace the ICL71 06/26136 in circuits
which require both the hold function and a differential
reference. The TC811 offers a greatly improved intemal
reference temperature coefficient, which can often eliminate
1-20
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
COMPONENT VALUE SELECTION
Oscillator Components
Auto Zero Capacitor - CAZ
The internal oscillator has been designed to operate
witha quartzcrystal,such astheStatekCX-1 V series. Such
crystals are very small and are available in a variety of
standard frequencies. Note that fose is divided by four to
generate the TCS11 internal control clock. The backplane
drive signal is derived by dividing fose by SOo.
To achieve maximum rejection of ac-line noise pickup,
a 40kHz crystal should be used. This frequency will yield an
integration period of 1OOms and will reject both 50Hz and
60Hz noise. For prototyping or cost-sensitive applications a
32.76SkHz watch crystal can be used, and will produce
about 25dB of line-noise rejection. Other crystal frequencies, from 16kHz to 4SkHz, can also be used.
Pins 39 and 40 make up the oscillator section of the
TCS11. Figures 6a and 6b show some typical conversion
rate component values.
The LCD backplane frequency is derived by dividing the
oscillator frequency by SOo. Capacitive loading of the LCD
may compromise display performance if the oscillator is run
much over 4SKHz.
The value of the Auto Zero capacitor (CAz) has some
influence on system noise. A 0.471-1F capacitor is recommended for 200mV full-scale applications where 1LSB is
lO0I-1V. A 0.10I-1F capacitor should be used for 2.0V fullscale applications. A capacitor with low dielectric absorption
(Mylar) is required.
Reference Voltage Capacitor -CREF
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
cycle is stored on CREF. A 0.11-1F capacitor is typical. If the
application requires a sensitivity of 200mV full-scale, increase CREF to 1.0I-1F. Rollover error will be held to less than
1/2 count. A good quality, low leakage capacitor, such as
Mylar, should be used.
Integrating Capacitor - CINT
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage reference. For this case a ±2V integrator output swing is
optimum when the analog input is near full-scale. For 2 or
2.5 reading/second (fose = 32kHz or 40kHz) and VFS =
200mV, a .06SI-1F value is suggested. If a different oscillator
frequency is used, CINT must be changed in inverse proportion to maintain the nominal ±2V integrator swing. An exact
expression for CINT is :
4000 VFS
CINT = VINT RINT fose
where:
fose =Clock frequency at Pin 39
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing
Reference Voltage (VREF)
A full-scale reading (2000 counts) requires the input
signal be twice the reference Voltage.
In some applications a scale factor other than unity may
exist, such as between a transducer output voltage and the
required digital reading. Assume, for example, a pressure
transducer output is 400mV for 20001b/in 2. Rather than
dividing the input voltage by two, the reference voltage
should be set to 200mV. This permits the transducer input
to be used directly.
"'''
TC811
OSCl
40
22Mn
CINT must have low dielectric absorption to minimize
roll-over error. A polypropylene capacitor is recommended.
Integrating Resistor -RINT
40.0 kHz
The input buffer amplifier and integrator are designed
with class A output stages which have idling currents of 6i!A.
The integrator and buffer can supply 1i!A drive currents with
negligible linearity errors. RINT is chosen to remain in the
output stage linear drive region but not so large that printed
circuit board leakage currents induce errors. For a 200mV
full-scale, RINT should be about 1S0kQ. A 2.0V full-scale
requires abut 1 .SMil.
OSC2
39
V+
38
470k
9V
L.....------+---+---.-l+ III
4348 ILL Fog
Figure 6a TC8ll Oscillator
1-21
3-112 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
Oscillator
Freq. (kHz)
ence inputs permit ratiometric measurements and simplify
interfacing with sensors such as load cells and temperature
sensors. The TC811 is ideally suited to applications in handheld multi meters, panel meters, and portable instrumentation. The reference voltage can be generated anywhere
within the V+ to V- power supply range.
To prevent rollover type errors from being induced by
large common-mode voltages, CREF should be large compared to stray node capacitance. A 0.1!!F capacitor is a
typical value.
The TC811 offers a significantly improved Analog Common temperature coefficient. This provides a very stable
voltage suitable for use as a voltage reference. The temperature coefficient of Analog Common is typically 35ppm/
Full-Scale Voltage (VFS)
2.0V
200mV
CINT
RINT
CINT
RINT
32.768
180k
0.0681lF
1.8M
0.0681lF
40
150k
0.0681lF
1.5M
0.0681lF
Figure6b
DEVICE PIN FUNCTIONAL DESCRIPTION
Differential Signal Inputs (VIN+ (Pin 31),
VIN- (Pin 30»
The TC811 is designed with true differential inputs and
accepts input signals within the input stage common mode
voltage range (VCM). The typical range is V+ - 1.0 to V- +
1.5V. Common-mode voltages are removed from the system when the TC811 operates from a battery or floating
power source (isolated from measured system) and VIN- is
connected to Analog Common. (see Fig 8)
In systems where common-mode voltages exist, the
86dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worse case condition exists if a large positive
VCM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output
positive along with VCM (Figure 8). For such applications the
integrator output swing can be reduced below the recommended 2.0V full-scale swing. The integrator output will
swing within 0.3V of V+ or V- without increased linearity
error.
CC.
VCM
I
:h
VI
Where:
TI
CI
RI
= ~I
[VCM -VIN]
I
= INTEGRATION TIME
= f4000
osc
= INTEGRATION CAPACITOR
=INTEGRATION RESISTOR
4348 ILL Fl1
Figure 8
Common-Mode Voltage Reduces Available
Integrator Swing. (VCOM '" VIN)
Reference (VREF+ (Pin 3S), VREF- (Pin 33»
Unlike the ICL7116, the TC811 has a differential reference as well as the "hold" function. The differential refer-
MEASURED
SYSTEM
10pF
~-~-~-~~V+
VBUF
~---IV+
20MQ
"'-_--1 V-
20 pF
1-----+.JVw......----l ~ V +
470 k
9V
4348 ILL FlO
Figure 7
Common-Mode Voltage Removed in Battery Operation With VIN""
1-22
=Analog Common
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
Analog Common (Pin 32)
APPLICATIONS INFORMATION
The Analog Common pin is set at a voltage potential
approximately 3.0V below V+. This potential is guaranteed
to be between 2.70Vand 3.35V below V+. Analog common
is tied internally to an N channel FET capable of sinking
1OO~. This FET will hold the common line at 3.0V below
V+ should an eX1ernalload attempt to pull the common line
toward V+. Analog common source current is limited to 1~.
Analog common is therefore easily pulled to a more negative
voltage (Le. below V+ - 3.0V).
The TCB11 connects the internal VIN+ and VIN- inputs
to Analog Common during the Auto Zero cycle. During the
reference integrate phase VIN- is connected to Analog
Common. If VIN- is not eX1ernally connected to Analog
Common, a common-mode voltage exists. This is rejected
by the converter's B6dB common-mode rejection ratio. In
battery powered applications, Analog Common and VINare usually connected, removing common-mode voltage
concerns. In systems where VIN- is connected to the power
supply ground or to a given voltage, Analog Common should
be connected to VIN-.
The Analog Common pin serves to set the analog
section reference or common point. The TCB11 is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float)
with respect to the TCB11 power source. The Analog
Common potential of V+ - 3.0V gives a 7V end of battery life
voltage. The analog common potential has a voltage
coefficient of 0.001 %1%.
With a sufficiently high total supply voltage (V+ - V- >
7.0V), Analog Common is a very stable potential with
excellent temperature stability (typically 35ppm'°C). This
potential can be used to generate the TCB11 reference
voltage. An external voltage reference will be unnecessary
in most cases because of the 35ppm'°C temperature coefficient. See TCB11 Internal Voltage Reference discussion.
Decimal Point and Annunciator Drive
TEST (Pin 37)
The TEST pin is connected to the internally generated
digital logic supply ground through a 500n resistor. The
TEST pin may be used as the negative supply for eX1emal
CMOS gate segment drivers. LCD display annunciators for
decimal points, low battery indication, or function indication
may be added without adding an additional supply. No more
than 1 rnA should be supplied by the TEST pin. The TEST
pin potential is approximately 5V below V+.
Internal Voltage Reference
The TCBll Analog Common voltage temperature stability has been significantly improved. This improved device
can be used to upgrade old systems and design new
systems without eX1ernal voltage references. EX1ernal R
and C values do not need to be changed, however, noise
performance will be improved by increasing CAZ (See Auto
Zero Capacitor section). Fig 10 shows Analog Common
su I in the necessa volta e reference for the TCB".
'L. _
v·
BPI--_--'---t
I
TOlCD
DECIMAL
POINT
TESTI--+-----'
TOlCD
L - - - - - - o BACK.
PLANE
v·
The TEST pin potential is 5V less the V+. TEST may be
used as the negative power supply connection when interfacing the TCB11 to eX1ernal CMOS logic. The TEST pin is
tied to the internally generated negative logic supply through
a 500n resistor. The TEST pin may be used to sink up to
1rnA. See the applications section for additional information
on using TEST as a negative digital logic supply.
If TEST is pulled "HIGH" (V+) , all segments plus the
minus sign will be activated. Do not operate in this mode for
more than several minutes, because when TEST is pulled to
V+, the LCD Segments are impressed with a DC voltage
which may cause damage to the LCD.
4049
~"
Tce11
~"
Tee11
HDlR
BPt----:-......-\
'~~l
TEST
4348 ILL F12
Figure 9 Display Annunciator Drivers
1·23
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
Liquid Crystal Display Sources
Several LCD manufactures supply standard LCD displays to interface with the TC811 3-1/2 digit analog-to-digital
converter.
38
Manufacturer
Address/Phone
Crystaloid
Electronics
5282 Hudson Dr.,
Hudson, OH 44236
216-655-2429
770 Airport Blvd.,
Burlingame, CA 94010
415-347-9916
3415 Kashikawa St.,
Torrence, CA 90505
212-534-0360
612 E. Lake St.,
Lake Mills, WI 53551
414-648-2361
AND
EPSON
Hamlin, Inc.
Representativ!
Part Numbers
240kQ
~~
TC811
C5335, H5535,
T5135, SX440
VREF
FE 0801,
FE 0203
"REF
36
t=.....-.< 10 kQ
VREF
33
ANALOG 32
COMMON
LD-B709BZ
LD-H7992AZ
SET VREF
=1/2 VFULL SCALE
4348 ILL F13
3902,3933,3903
Figure 10
TC811 Internal Voltage Reference Connection
'NOTE: Contact LCD manufacturer for full product listing/specifications.
Oscillator Crystal Source
Manufacturer
Address/Phone
STATEK
512 N-Main
Orange, CA 92668
714-639-7810
Representative
Part Numbers
CX-1V 40.0
Q-~_-IV~
RUNKNOWN
Ratiometric Resistance Measurements
o--_-IV 1N
ANALOG
COMMON
The TC811 true differential input and differential reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current is passed through the pair (Figure
11). The voltage developed across the unknown is applied
to the input and the voltage across the known resistor
applied to the reference input. If the unknown equals the
standard, the input voltage will equal the reference voltage
and the display will read 1000. The displayed reading can
be determined from the following expression:
Displayed reading =
RUNKNOWN
RSTANDARD
The display will overrange for
4348 ILL F14
Figure 11
x 1000
RUNKNOWN ;::>:
~~
TC811
2 X
RSTANDARD.
1-24
Low Parts Count Ratio Metric Resistance Measurement
3-1/2 DIGIT AID CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
..,~
..,~
~-------+-----;Vm
TCSll
TCBII
VFS = 200 MV
O.7%1°C
PTC
'--------_---+~ VREF
COMMON
HLDR
COMMON
' - - V+
HLDR
v·
4346 ILL F16
4348 FHD F15
Figure 12
'--
Figure 13
Temperature Sensor
1-25
Positive Temperature Coefficient
Resistor Temperature Sensor
NOTES
1-26
.,"'TELEDYNE
COMPONENTS
TC818
AUTO-RANGING ANALOG-TO-DIGITAL CONVERTER
WITH 3-1/2 DIGIT AND BAR-GRAPH DISPLAYS
FEATURES
•
•
•
•
•
•
3-112 Digit Numeric Plus 4O-Segment Bar-Graph
•
Display Hold Function
LCD Drivers
Annunciator Outputs Permit Customizing of LCD
2-Chip Set, Surface-Mounted
- 50-Pin Flat Package
- 20-Pin Small Outline (SO)
Auto-Range Operation for AC and DC Voltage
and Resistance Measurements
Two User-Selected ACIDC
Current Ranges ........................... 20 mA and 200 mA
22 Operating Ranges
- 9 DC/AC Voltage
- 4 ACIDC Current
- 9 Resistance and Low-Power Ohms
•
3-112 Digit Resolution in Auto-Range Mode ... 112000
•
Extended Resolution in Manual
Range Mode ..................................................... 113000
Memory Mode for Relative
Measurements .............................................. ±5% F.S.
Internal AC-to-DC Conversion Op Amp
Triplex LCD Drive for Decimal Points, Digits,
Bar-Graphs, and Annunciators
Continuity Detection and Piezoelectric Transducer
Driver
Low-Drift Internal Reference ........•............ 75 ppm/°C
9V Battery Operation ....................................... 10 mW
Low Battery Detection and LCD Annunciator
•
•
•
•
•
•
•
FUNCTIONAL DIAGRAM
IF LCD BIAS CONNECTED TO DIGITAL
GROUND, PEAK DRIVE SIGNAL - 5V.
.,,,
TC818A
*NOT REQUIRED WHEN RESISTOR NETWORK IS USED.
SEE APPLICATIONS SECTION FOR DETAILS.
1
YRt(·1)
....--II/Ii'l.-...::Jv R2(+1Q)
R111101 kO 3
VR3(+100)
:~~~iT~~NGE
R1W10kCl 41
Y R4(+1.000)
+---'II\IIr--'-'I
v RS(+1O,OODt
J
ADI
~~_~R~w~1~.n~~~~~~~~·;---=r~::~--=r~rrr~~F-4fr-~~~ltrj~~r:~Ffu~f3~2-113.15mV
COMe
A11/'SkO
HOLD
1090-1
1·27
~
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
GENERAL DESCRIPTION
ORDERING INFORMATION
The TC818 is a 2-chip integrating analog-to-digital converter (ADC) with 3-1/2 digit numeric and 40-segment bargraph LCD drivers, automatic ranging, and single 9V battery
operation. The TC818 chip set (consisting of the TC818A
and TC818D), combines the precision of a numeric display
with the quick recognition of a barilraph. The numeric
display is driven by the TC818A, which also includes the
ADC. The bar-graph display is driven by the TC818D.
The 40-segment bar-graph display provides "quicklook" perception of amplitude. Recognizing trends is also
easier with a bar-graph, making TC818-based instruments
valuable in nulling, tuning, calibration, and similar applications. On the other hand, the numeric display provides
0.05% resolution and a full set of annunciators that spell out
the TC818's many operating modes.
.
Automatic range selection is provided for both voltage
(DC and AC) and ohms (high and low power) measurements. Expensive and bulky mechanical range switches are
not required. Five full-scale ranges are available, with automatic selection of external volt/ohm attenuators over a 1 to
10,000 range. Two current ranges, 20 mA and 200 mA, can
be manually selected. The auto-range feature can be bypassed, allowing input attenuator selection through a single
line input.
During manual mode operation, resolution is extended
to 3000 counts full-scale. Extended resolution is also available during 2000 kQ and 2000V full-scale auto-range operation. The extended range operation is indicated by a flashing
1 MSD and by the fully~extended bar-graph.
The TC818 includes an AC-to-DC converter for AC
voltage and current measurements. Only external diodes/
reSistors/capacitors are required. Other features include a
memory mode, low-battery detection, display HOLD input,
and continuity buzzer driver.
The 3-1/2 digit numeric display includes a full set of
annunciators. Decimal points are adjusted as automatic or
manual range changes occur, and voltage, current, and
ohms operating modes are displayed. Additional annunciators are activated for manual, auto, memory, HOLD, AC,
low-power ohms, and low-battery conditions.
The TC818 is available in a surface-mounted chip set,
with the TC818A in a 50-pin flat package and the TC818D in
a 20-pin small outline (SO) package. Combining numeric
and bar-graph display drivers, single 9V battery operation,
internal range switching, and compact surface mounting,
the TC818 is ideal for advanced portable instruments.
Pan No.
Temperature
Range
Package
TC818ACBQ
50-Pin Plastic
Flat
o·Ctc +70·C
TC818DCOP
20-Pin SO
O·Ctc +70·C
PIN CONFIGURATIONS
Vee
1 21,22,23
1 24,25,26
1 27,28,29
1 30,31,32
1 ........
1 36,37,38
1 3.,40,OR
DATA
QND -.....
1
_ _r-
1-28
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
ABSOLUTE MAXIMUM RATINGS
Both Devices
Operating Temperature Range .................... O°C to +70°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................. +300°C
TC818A
Supply Voltage .......................................................... + 15V
Analog Input Voltage ........................................ Vee to Vss
Reference Input Voltage .................................. Vee to Vss
Voltage at Pin 43 ...................................... Common ±0.7V
Power Dissipation ................................................ 800 mW
Slatie-sensitive device. Unused devices must be stored in conductive
material. Protect devices from slatic discharge and slatic fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage. to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
TC818D
Supply Voltage ............................................................ +6V
Digital Input Voltage ....................................... Vee to GND
Power Dissipation ................................................ 500 mW
ELECTRICAL CHARACTERISTICS: VS = 9V, TA = +25°C, Figure 1 Test Circuit
Symbol
RE
Parameter
Test Conditions
Zero Input Reading
200 mV Range Without 10 MO Resistor
200 mV Range With 10 MO Resistor
20 rnA and 200 rnA Range
200 mV Range Without 10 MO Resistor
200 mV Range With 10 MO Resistor
20 rnA and 200 rnA Range
Best Case Straight Line
Roll-Over Error
NL
Linearity Error
liN
eN
Input Leakage Current
Input Noise
AC Frequency Response
Min
BW=0.ltol0Hz
±l%Error
±5% Error
Excludes 2000 Range
QQen Circuit Vokage for
LO Ohm Measurements
VeoM
VCTe
VIL
-
-
-
-
0000
0000
-
-
Max
+0000
+0001
+0000
±1
±3
±1
±1
10
-
Unit
Digital
Reading
Counts
Count
pA
-
!LVp-p
Hz
-
20
40 to 500
40 to 2000
570
660
mV
Excludes 2000 Range
-
285
350
mV
Analog Common Voltage
Common Voltage
Temperature Coefficient
(Vee- VCOM)
2.8
3
-
-
3.3
50
V
ppml"C
-
Hz
20mA, AC, I, LOO, HOLD Range, -MEM,
Ohms (Relative to DIGITAL GND, Pin 55)
-
100
Low Logic Input
Logic 1 Pull-Up
20 mA, AC, I, LOO, HOLD Range, -MEM,
Ohms (Relative to DIGITAL GND, Pin 55)
ANNUNC, DEINT; IL = 100 ILA
ANNUNC, DEI NT; IL = 100 !LA
-
25
-
DGND+O.l
-
Vcc-Q.l
4
-
kHz
Vee to Vss
6.3
-
6.6
0.8
7
1.5
V
--.---mA
Min
TC818D
Typ
Max
Unit
-
-
V
1
10
V
nA
Open Circuit Vokage for
Ohm Measurements
Display Multiplex Rate
VOL
VOH
-0000
-0001
-0000
TC818A
Typ
Low Logic Output
High Logic Output
Buzzer Driver Frequency
Low Battery Flag Vokage
Operating Supply Current
-
-
-
1
V
_._--_._.
-
-- -
!LA
-"---'-
V
r-v---
ELECTRICAL CHARACTERISTICS: Vce = 5V, GND = OV, T A = +25°C
Symbol
Parameter
VIH
High Logic Input
2.5
VIL
Low Logic Input
Logic Input Current
-
IlL
Test Conditions
-
Vec - VIN - GND
Display Multiplex Rate
Operating Supply Current
1-29
-
0.01
100
40
-
Hz
100
ILA
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
TC818A PIN DESCRIPTION
Pin No.
(Quad Flat
Package)
Symbol
Description
OHM
Logic input. "0" (dig~al ground) for resistance measurement.
2
20mA
Logic Input. "0" (dig~al ground) for 20 mA full-scale current measurement.
3
BUZ
Buzzer. Audio frequency, 4 kHz, output for continuity indication during resistance measurement.
A noncontinuous 4 kHz signal is output to indicate an input overrange during voltage or current
measurements.
4
XTAl1
32.768 kHz crystal connection and clock output to drive TC818D.
5
XTAL2
32.768 kHz crystal connection.
6
VOISP
7
8
BPl
LCD backplane #1.
BP2
LCD backplane #2.
9
BP3
LOQlA
10
Sets peak LCD drive signal: Vp =Vcc = VOISP. VOISP may also be used to compensate for
temperature variation of LCD crystal threshold voltage.
LCD backplane #3.
LCD annunciator segment drive for low ohms resistance measurement and current
measurement.
11
QlA
LCD annunciator segment drive for resistance measurement and current measurement.
12
klm/HOLD
LCD annunciator segment drive for k ("kilo-Ohms"), m ("mil Ii-Amps" and "milli-Votts") and
HOLD mode.
13
BCPO
(Ones Dig~)
LCD segment drive for "b," "c" segments and decimal point of least signfficant digit (LSD).
14
ADGO
LCD segment drive for "a," "g," "d" segments of LSD.
15
FEO
LCD segment drive for "I" and "e" segments of LSD.
16
17
BCP1
ADG1
LCD segment drive for "b," "c" segments and decimal point of second LSD.
LCD segment drive for "a," "g," "d" segments of second LSD.
LCD segment drive for "f" and "e" segments of second LSD.
18
FE1
19
BCP2
LCD segment drive for "b," "c" segments and decimal point of third LSD (hundreds digit).
20
ADG2
LCD segment drive for "a," "g," "d" segments of third LSD.
21
FE2
BCP3
LCD segment drive for "b," "c" segments and decimal point of MSD (thousands digit).
22
23
ACI-IAUTO
24
25
-MEM/BATT
ANNUNC
26
Vee
27
COM
LCD segment drive for '1" and "e" segments of third LSD.
LCD annunciator segment drive for AC measurements, polar~y, and auto-range operation.
LCD annunciator segment drive for low-battery indication and memory (relative measurement).
Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC can be used to
control display annunciators. Connecting an LCD segment to ANNUNC turns it on; connecting it
to ~s backplane turns ~ off. AN NUNC is also used to synchronize the TC818A and TC818D
backplanes.
Pos~ive
battery supply connection.
Analog circuit ground reference point. Nominally 3V below Vcc.
28
DEINT
Deintegrate output. Transmits the AID conversion resutt to the bar-graph LCD driver. (See text.)
29
RMREFL
Ratiometric (resistance measurement) reference low vottage.
30
CREFL
Reference capacitor negative terminal, CREF = 0.1 IJ.F.
31
Reference capacitor positive terminal, CREF = 0.1 IJ.F.
32
CREFH
REFHI
33
OR1
Standard resistor connection for 2000 full-scale.
34
OR2
Standard resistor connection for 20000 full-scale.
35
OR3
Standard resistor connection for 20 kG full-scale.
36
OR4
Standard resistor connection for 200 kO full-scale.
=--------:=-=::::-':':---:::--:-----:----,-'---;:---,....--'--'=---'--.,-:-,....--:--::--:-::-::-::-:::--:-:-- .._ - - - _ . _ -
Reference vottage for vottage and current measurement. Nominally 163.85 mV.
1-30
AUTO· RANGING ANALOG·TO·DIGITAL
CONVERTER WITH 3·1/2 DIGIT AND
BAR·GRAPH DISPLAYS
TC818
TC818A PIN DESCRIPTION (Cont.)
Pin NO.
(Quad Flat
Package)
Symbol
Description
37
OR5
Standard resistor connection for 2000 kO full-scale.
38
VR3
Voltage measurement + 100 attenuator.
39
VR2
Voltage measurement +1 0 attenuator.
40
VR5
Voltage measurement + 10,000 attenuator.
41
VR4
Voltage measurement + 1000 attenuator.
42
43
VI
Unknown voltage input + attenuator.
Ii
Unknown current input.
44
ACVL
45
CI
46
Auto-zero capacitor connection. Nominally 0.1 IlF.
48
CAZ
Rx
CFI
49
ADI
Negative input of internal AC-to-DC operational amplifier.
47
Low output of AC-to-DC converter.
Integrator capacitor connection. Nominally 0.1 IlF. (Must have low dielectric absorption.
Polypropylene dielectric suggested.)
Unknown resistance input.
Input fi~er connection.
Output of internal AC-to-DC operational amplifier.
50
ADO
51
ROBUF
52
RVIBUF
53
ACVH
Positive output of AC-to-DC converter.
54
Negative supply connection. Connect to negative terminal of 9V battery.
55
Vss
DGND
56
RANGE
57
HOLD
Input to hold display. Connect to DGND to '1reeze" display.
58
-MEM
59
DC (0)/
AC(LOO)
Input to enter memory measurement mode for relative measurements. The two LSDs are stored
and subtracted from future measurements.
Input that selects AC or DC option during vo~age/current measurements. For resistance
measurements, the ohms or low power (voltage) ohms option can be selected.
60
T
Active buffer output for resistance measurement. Integration resistor connection.
Nominally 220 kO.
Active buffer output for voltage and current measurement. Integration resistor connection.
Nominally 150 kO.
Internal logic digital ground. Ground connection for the TC818D, and the logic "0" level.
Nominally 4.7V below Vcc.
Input to set manual operation and change ranges.
Input to select measurement. Connect to logic "0" (digital ground) for current measurement.
1-31
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
TC818D PIN DESCRIPTION
PinNa.
(20-Pin SO)
1
2
3
4
Symbol
Description
18,19,20
15,16,17
Segments 18,19,20 of LCD.
Segments 15, 16, 17 of LCD.
12,13,14
9,10,11
Segments 12, 13, 14 of LCD.
Segments 9, 10, 11 of LCD.
5
6
7
6,7,8
3,4,5
Segments 6, 7, 8 of LCD.
Segments 3, 4, 5 of LCD.
0,1,2
Segments 0, 1, 2 of LCD.
8
Sets peak LCD vokage drive level. Connect to VDISP of TC818A, or to GND of TC818D.
Clock input. Connect to XTALl output of TC818A.
11
VDISP
CLK
GND
SYNC
12
DATA
13
39,40, OR
Data input. Pulses at the CLK input are counted while DATA is logic high. Connect to DEINT
output of TC818A.
Segments 39, 40 and overrange of LCD.
14
15
16
36,37,38
Segments 36, 37, 38 of LCD.
33,34,35
30,31,32
Segments 33, 34, 35 of LCD.
Segments 30, 31,32 of LCD.
17
27,28,29
Segments 27, 28, 29 of LCD.
18
19
24,25,26
21,22,23
Segments 24, 25, 26 of LCD.
Segments 21, 22, 23 of LCD.
20
Vee
9
10
Digital ground. Connect to DGND of TC818A.
Display SYNC input. Synchronizes backplanes of the TC818A and TC818D. Connect to
ANNUNC output of TC818A.
Power supply input. Connect to Vee of TC818A.
THEORY OF OPERATION·
The TC818 consists of two CMOS integrated circuits.
The TC818A incorporates an auto-ranging ADC and drivers
for a 3-1/2 digit LCD, while the TC818D provides data
formatting and drivers for a 40-segment bar-graph display.
Both integrated circuits are required to form a complete
measurement system.
During each AID conversion cycle, data is transferred
from the TC818A to the TC818D. Therefore, the bar-graph
display will track the numeric (3-1/2 digit) display. The exact
relationship between numeric display counts and bar-graph
segments displayed is shown in Table I. Both displays are
updated at the same rate. When the TC818A is in its
extended resolution mode (3000 counts, maximum), the
bar-graph will display all 40 bars continuously.
will adjust the input voltage or ohms attenuators so that
measurements will always be made in the appropriate
range. Measurement ranges, logic control inputs, 3-1/2 digit
LCD formatting, and other features are identical to the
TC815 auto-ranging AID converter. However, the TC818A
is not pin-compatible with, and is not a replacement for, the
TC815.
A display annunciator output (ANNUNC) can be used to
customize the LCD. AN NUNC is a square wave at the
backplane frequency. Connecting an annunciator segment
to the ANNUNC driver turns the segment on; connecting the
segment to its backplane turns it off.
Analog-to-Digital Converter (ADC)
The TC818D includes a counter and data latch, clock
divider, and triplex LCD bar-graph formatting and display
functions. A block diagram of the TC818D and connections
between the TC818A and TC818D is shown in Figure 2. The
TC818D does not require a separate power supply, since it
is powered from Vee and digital ground of the TC818A.
Bar-Graph Driver
The TC818A includes an integrating ADC with autoranging resolution of 2000 counts and manual range resolution of 3000 counts. Figure 1 shows a simplified schematic
of the analog section. In auto-ranging mode, internal logic
1-32
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
.q. .
. ,.,. . ,~F:i1 R711ookO
- - - O.
1
ORX47
----------------~.-:,~~--------~;------
TC818A
OHMS
INPUT
v-
R6I2200
R6I1oo kO RMREFL29
/.521 iiE.O
:
R5Il.638 MO
VCC
/.S240·'110k
U--
,/.
O·
/(1-525 ll1k
R4I163.85 kO
5440':';110
1.5kO
o·
._?.
R2I1638.50
")6.2V
R1I163.85O
m>-.,........
CURRE~A
O·
/~1/10
OR , 33
~2.8V REF.~:
+
528 0 - 111
COM
~
32 REF HI
~~~ ~~~1~1403--~~~~C~C------~5~10~,~0~+~I~
...i.!'3,D4
~...
RI9/5 kO
27
OAI::-:N""'A".L""'OG~
RI5190
...163.B5mV
V-
~'"
RI6110
RI6124 kO <;
VCC+~fn
.~ 1/100
.( ZI
o-JVI!v:
10kO
-.0
VOLTAGE
INPUT RI419.9 MO .J_VI42
51/. V.l/1
V' V'
1110 1110
R13/5oo kO*
"NOT REQUIRED
WHEN RE51STOR
NETWORK 15 U5ED.
V' V' V111 1110k
k
~6~p~8~9
R~2I1.11 MO VR239
5L-.1I.,/,0
v-
31 CREFH
~ODE
S3 .....1I.,1100
CREFH+O.,
30CREFL
54. .....V·,/,k
COMMONo-~r-.RJ~vvk~0_ _V~R~20~~__~~_~~550/r,V"·oll~"~/'~0~k~
.l
V
AC·To-DC-
~F
50
IIR22
ADO
4.7
..------1~--_I
~
01
<:lC3
10kO+'~F
02
1 J~
R23T~4
10kO
1 ~F
g~~ri~TER
~F
I
S18DE
¢519DE+li"
+1-------..
511 I" h+AC
i.io
C2 IADI 49
~-+--1---~-H~~+---------~
0.22~F
R26
3kO
514
ACVH 53
5131INToI.0+DC)
J
Cl/1~F
r
ACVH44
RBum
Figure 1
TCB1BA Analog Section
1-33
~F
AUTO-RANGINGANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
ANALOG
SEC110N
DIGITAL
SEC110N
DEINT 28
CLEAR
BAR-GRAPH
COUNTER
12 DATA
DISPLAY
lATCH
~~=r;>~:3~~~::~t------t--~~---------=~COUNT
CLOCK
11
9
SYNC
ClK
BARS
0,1,2
DIVIDER
TRIPLEX
DRIVERS
BARS
39,40,OR
~'"
TC818D
GND
20
VDISP
..1;,.;:0______..... 8
-----1
Figure 2
Interface Between TC818A and TC818D
When the TC818D DATA input goes to a logic high,
pulses are counted at the CLK input. A clock divider scales
clock pulses so that the number of LCD bar-graph segments
is proportional to the numeric display (see Table I).
When the DATA input goes low, the counter contents
are transferred toa display latch. Thenthe bar-graph counter
is reset to zero in preparation for the next AJD conversion
cycle.
The CLK input is also divided to produce the triplex LCD
drivers. The backplane and segment driver waveforms are
the same voltage levels as the TC818A. However, the
TC818D segment driver waveforms are less complicated
than those of the TC818A, because adjacent bar-graph
segments are either on or off.
The SYNC input permits synchronizing display backplanes. By connecting the ANNUNC output of the TC818A
to the SYNC input of the TC818D, the two sets of LCD
drivers will be synchronized. This feature permits the use of
an LCD with only one set of backplane drivers and saves
three pin connections to the display.
LCD backplane and segment drive voltages are set by
the voltage between Vcc and VOISP pins. In most cases,
VDlSP will be connected to GND and the LCD drive voltage
willbeabout5V.lfVolsP is not connected to GND, thenVolsP
of the TC818D must be connected to VOISP of the TC818A.
Data Transfer
Analog conversion results are transferred from the
TC818A to the TC818D via two pins, DEINT and XTAL1.
DEINT is a TC818A output with a pulse width proportional to
the analog voltage being measured. DEINT goes to a logic
high at the beginning of the TC818A deintegrate cycle, and
goes low atthecomparatorzero-crossing (end of conversion).
1-34
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
Timing of the DEINT pulse width is derived from the
TC818A's XTAL 1 output, which provides a 32.768 kHz
clock. The number of clock pulses occurring while DEINT is
high determines the number of bar-graph segments displayed. The relationship between numeric display counts
and bar-graph segments is shown in Table I.
Resistance, Voltage, Current
Measurement Selection
The TC818 is designed to measure voltage, current,
and resistance. Auto-ranging is available for resistance and
voltage measurements. The OHM (pin 1) and T(pin SO) input
controls are normally pulled internally to Vcc.
By tying these pins to DGND (pin 55). the TC818 is
configured internally to measure resistance, voltage, or
current. The required signal combinations are shown in
Table II.
Table I. TC8l8A Numeric Display vs TC8l8D
Bar-Graph Segments
Numeric Reading
Bar-Graph Segments
0-24
25-74
75-124
0
1
2
•
•
•
•
•
«50'N)-25) to «50'N)+24)
(where 1 :s; N :s; 40)
N
•
•
•
•
•
•
Full-Scale
Range
200Q
2000Q
20kQ
200kQ
2000kQ
Selected Measurement
o
o
o
o = Digital Ground
,
=
Standard
Resistance
163.85Q(Rl)
1638.5Q (R2)
16,385Q (R3)
163,850Q (R4)
1,638,500Q (R5)
Low-Power
Ohms Mode
No
Yes
Yes
Yes
Yes
A8, a positive temperature coefficient reSistor, and the
S.2V zener, Z1, provide input voltage protection during
ohms measurement.
Table II. TC8l8 Measurement Selection Logic
o
The TC818 can be configured to reliably measure incircuit resistances shunted by semiconductor junctions. The
TCB1810w-powerohms measurement mode limits the probe
open circuit voltage. This prevents semiconductor junctions
in the measured system from turning on.
In the resistance measurement mode, the Q/LOn (pin
59) input selects the low-power ohms measurement mode.
For low-power ohms measurements, Q/LOn (pin 59) is
momentarily brought low to digital ground potential. The
TC81B sets up for a low-power ohms measurement with a
maximum open circuit probe voltage of 0.35V above analog
common. In the low-power ohms mode, an LCD annunciator, LOn, will be activated. On power-up, the low-power
ohms mode is not active.
If the manual operating mode has been selected, toggling
Q/LOn resets the TC818 back to auto-range mode. In
manual mode, the decision to make a normal or low-power
ohms measurement should be made before selecting the
desired range.
The low-power ohms measurement is not available on
the 200n full-scale range. Open-circuit voltage on this range
is below 2.BV.
The standard resistance values are listed in Table III.
Table III. Ohms Range Ladder Network
1975-2024'
40
OVR
>2024'
• Readings> '999 will only occur in manual or expanded resolution
modes.
Function Select Pin
OHM (Pin 1)
T(Pin 60)
Resistance Measurements - Ohms
and Low Power Ohms
Ratiometric Resistance Measurements
Vottage
Resistance
Current
Vottage
The TC818 measures resistance ratiometrically. Accuracy is set by the external standard resistors connected to
pins 33 through 37. A low-power ohms mode may be
selected on all but the 200n full-scale range. The low-power
ohms mode limits the voltage applied to the measured
system. This allows accurate "in-circuit" measurements
when a resistor is shunted by semiconductor junctions.
Full auto-ranging is provided. External precision standard resistors are automatically switched to provide the
proper range.
Floating or Tied to Vee
NOTES: ,. OHM and Tare normally pulled internally high to Vee
(pin 26). This is considered a logic "'''.
2. Logic "0" is the potential at digital ground (pin 55).
'-35
AUTO-RANGING ANALOG-TO-DIGfTAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
Figure 3 is a detailed block diagram of the TC818
configured for ratiometric resistance measurements. During
the signal integrate phase the reference capacitor charges
toa voltage inversely proportional to the measured resistance,
Rx. Figure 4 shows that the conversion accuracy relies only
on the accuracy of the external standard resistors.
Normally, the required accuracy of the standard resistances will be dictated by the accuracy specifications of the
user's end product. Table IV gives the equivalent ohms per
count for various full-scale ranges to allow users to judge the
required resistor accuracy.
Table IV. Reference Resistors
Full-Scale
Range(Q)
Reference
Resistor
200
2k
20k
200k
2M
163.85
1638.5
16385
163,850
1,638,500
.QJCount
0.1
10
100
1000
9V
II
R5I1638500a
R4Il638500
37
529
36
530
10ka
OHM5
VCC
26
-1.5 kQ
-1.5 kQ
+
R18
24kQ
32
5ka
27
R8
220fl
(PTC)
DE-a
523
'" ~ODT'o-~"
31
~__~~_+-_~51~8~
521
~'V\J\r---1--+---=.:..o....
DE
DE-a
VC C -2·6V
~'"
TC818A
BUFFER
_ _ _RA7I100 kQ 47
>--....--,
~ -{>--[>
INTEGRATOR COMPARATOR
534
a
RClBUF 51
Figure 3
Ratiometric Resistance Measurement Functional Diagram
1·36
ANALOG
COMMON
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
Example: 200 kQ Full-Scale Measurement
VA
o
--I
(a) VR =
0.64V FOR OHMS
}
0.32V FOR LO OHMS
163.85 kQ
30.64
163.85 + 220 + Rx
Rx
(b) Vx = 163.85 kQ + 220Q + Rx 30.64
RS~
CREFJl!+ IVR
100 kn
163.85 kn ~
>
:wv-
(c) "Ramp-Up Voltage" = "Ramp-Down Voltage"
220n
~
t - - - - -.... VX
>
UNKNOWN~RX
where:
RI = Integrating Resistor, tl = Integrate Time
CI = Integrating Capacitor, toe = Deintegrate Time
TO ANALOG
BUFFER
(d) Rx = 163.85 (
t~leJ
Independent of RI, CI or intemal voltage reference.
Figure 4
Resistance Measurement Accuracy Set by External Standard Resistor
Voltage Measurement
Resistive dividers are automatically changed to provide
in-range readings for 200 mV to 2000V full-scale readings
(Figure 1). The input resistance is set by external resistors
R14/R13. The divider leg resistors are R9-R12. The divider
leg resistors give a 200 mV signal at VI (pin 42) for full-scale
voltages from 200 mV to 2000V.
For applications that do not require a 10 MW input
impedance, the divider network impedances may be lowered. This will reduce voltage offset errors induced by switch
leakage currents.
Current Measurement
at the current input (h, pin 43). For 20 mA measurements, a
10Q resistor is used. The 200 mA range requires a 1Q
resistor. Full scale is 200 mV
Printed circuit board trace resistance between analog
common and R16 must be minimized. In the 200 mA range,
for example, a 0.05Q trace resistance causes a 5% currentto-voltage conversion error at II (pin 43).
The extended resolution measurement option operates
during current measurements.
To minimize roll-over error, the potential difference
between ANALOG COM (pin 27) and system common must
be minimized.
AC-to-DC Measurements
The TC818 measures current only under manual range
operation. The two user-selectable, full-scale ranges are
20 mA and 200 mAo Select the current measurement mode
by holding the I input (pin 60) low at digital ground potential.
The OHM input (pin 1) is left floating or tied to the positive
supply.
Two ranges are possible. The 200 mA full-scale range
is selected by connecting the 20 mA input (pin 2) to digital
ground. If left floating, the 200 rnA full-scale range is selected.
External current-to-voltage conversion resistors are used
In voltage and current measurements, the TC818 can
be configured for AC measurements. An on-Chip operational
amplifier and external rectifier components perform the ACto-DC conversion.
When power is first applied, the TC818 enters the DC
measurement mode. For AC measurements (current or
voltage), AC/DC (pin 59) is momentarily brought low to
digital ground potential; the TC818 sets-up for AC measurements and the AC liquid crystal display annunciator activates. Toggling AC/DC low again returns the TC818 to DC
operation.
1-37
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
The maximum reference deintegratetime, representing
a full-scale analog input, is 3000 clock periods (or 183.1 ms)
during manual extended resolution operation. The 3000
counts are available in manual mode, extended resolution
operation only. In auto-ranging mode, the maximum deintegrate time is 2000 clock periods. The 1000 clock periods
are added to the auto-zero phase. An auto-ranging or
manual conversion takes 8000 clock periods. After a zero
crossing is detected in the reference deintegrate mode, the
auto-zero phase is entered.
Figure 5 shows the basic TC818 timing relationships.
If manual operating mode has been selected, toggling
AC/DC resets the TC818 back to auto-range mode. In
manual mode operation, AC or DC should be selected first,
then the desired range.
The minimum AC full-scale voltage range is 2V. The DC
full-scale minimum voHage is 200 mV.
AC current measurements are available on the 20 mA
and 200 mA full-scale ranges.
Conversion Timing
The TC818 uses the conventional dual-slope integrating conversion technique with an added phase that automatically eliminates zero offset errors. The TC818 gives a
zero reading with a OV input.
This device is designed to operate with a low-cost,
readily-available 32.768 kHz crystal. It serves as a timebase oscillator crystal in many digital clocks. (See extemal
crystal sources, page 18.)
The external clock is divided by two. The internal clock
frequency is 16.348 kHz, giving a clock period of 61.04 j.lS.
The total conversion - auto-zero phase, signal integrate,
and reference deintegrate - requires 8000 clock periods (or
488.3 ms). There are approximately two complete conversions per second.
The integration time is fixed at 1638.5 clock periods (or
100 ms), giving a rejection of 50/60 Hz AC line noise.
Manual Range Selection
The TC818's voHage and resistance auto-ranging feature can be disabled by momentarily bringing RANGE (pin
56) to digital ground potential (pin 55). When the change
from auto to manual ranging occurs, the first manual range
selected is the last range in the auto-ranging mode.
The TC818's power-up circuit initially selects autorange operation. Once the manual-range option is entered,
range changes are made by momentarily grounding the
RANGE control input. The TC818 remains in the manualrange mode until the measurement function (volta~r
resistance) or measurement option (ACIDC, ntLOQ)
changes, causing the TC818 to return to auto-ranging
operation.
External Crystal = 32.768 kHz
~~
TC818
•
AUpTHo-AZsEERO...
SIGNAL
INT
PHASE
REF
DEINT
PHASE
Internal Clock Period
_
NEXT CONYERSION
AUTO-ZERO CYCLE
EXTENDED
RESOLUTION
ZERO
/CROSSING
= tp = 2/32.768 = 61.04 ~s
Total Conversion Time = tCONV = 8000 (tp)
= 488.3 ms = 2 conv/sec
Integration Time
= tl = 1638.5 (tp) = 100 ms
Maximum Reference Deintegrate Time
= tOE = 3000 (tp) =
183.1 ms (manual,
extended resolution)
= 2000 (tp) = 122.1 ms (auto-range)
ocTO
INPUT
SIGNAL
1<4--- looNY= 8000 Ip - - - . .
Minimum Auto-Zero Time
= (8000-3000-1638.5)
(tp) = 205.1 ms (manual,
extended resolution)
"IN AUTO-RANGE OPERATION,
MAXIMUM IS 2000 IpAND
MINIMUM AUTO-ZERO TIME
IS 4361.5 I p •
=
Figure 5
(8000-2000-1638.5)
(tp) = 266.2 ms (auto-range)
Basic TC818 Conversion TIming
1-38
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
The "Auto" LCD annunciator driver is active only in the
auto-range mode.
Figure 6 shows typical operation where the manual
range selection option is used. Also shown is the extended
resolution display formal.
Extended Resolution Manual Operation
When operated in the manual-range mode, the TC818
extends resolution by 50% for current, voltage, and resistance measurements. Resolution increases to 3000 counts
from 2000 counts. The extended resolution feature operates
only in the 2000 kQ and 2000V ranges during auto-range
operation.
In the extended resolution operating mode, readings
above 1999 are displayed with a blinking" 1" most significant
digit. The blinking "1" should be interpreted as the digit 2.
The three least significant digits display data normally. The
bar-graph LCD will be fully extended.
An input overrange condition causes the most significant digit (MSD) to blink and sets the three least significant
digits (LSDs) to display "000." The buzzer output is enabled
for input voltage and current signals with readings greater
than 2000 counts in both manual- and auto-range operations.
"''''
TC818
Figure 7
Manual Range Selection; Current Measurement
"''''
TC818
OUTPUT NON-
.---_--1 ~~~~~~~~
FREQUENCY
OVERRANGE
INDICATOR
• MODE ALSO OPERATES WHEN AUTO-RANGING
OPERATION IS SELECTED AND 2 Mil < RX < 2.999 Mil.
Figure 6
Figure 8
Manual Range Selection; Resistance Measurement
1-39
Manual Range Selection; Voltage Measurement
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
For resistance measurements, the buzzer signal does
not indicate an overrange condition. The buzzer is used to
indicate continuity. Continuity is defined as a resistance
reading less than 19 counts.
The -MEM mode is also cancelled whenever the measurement type (resistance, voltage, current, ACIDC,
WLOO) or range is changed. The LCD -MEM annunciator
will be off in normal operation.
In auto-range operation, if the following input signal
cannot be converted on the same range as the stored value,
the -MEM mode is cancelled. The LCD annunciator is
turned off.
The -MEM operating mode can be very useful in resistance measurements where lead length resistance would
cause measurement errors.
-MEM Operating Mode
Bringing-MEM (Pin 58) momentarily lowconfiguresthe
"-MEM" operating mode. The -MEM LCD annunciator
becomes active. In this operating mode subsequent measurements are made relative to the last two digits (:$; 99)
displayed at the time M EM is low. This represents 5% of fullscale. The last two significant digits are stored and subtracted from all the following input conversions.
A few examples clarify operation:
Automatic Range Selection Operation
When power is first applied, the TC818 enters the autorange operating state. The auto-range mode may be en'
tered from manual mode by changing the measurement
function (resistance or voltage) orby changing the measurement option (ACIDC, WLOO).
The automatic voltage range selection begins on the
most sensitive scale first: 200 mV for DC or 2V for AC
measurements. The voltage range selection flow chart is
given in Figure 9.
Internal input protection diodes to Vcc (pin 26) and Vss
(pin 54) clamp the input voltage. The external 10 MO input
resistance (see R14 and R13, Functional Diagram) limits
current safely in an overrange condition.
The voltage range selection is designed to maximize
resolution. For input signals less than 9% of full scale (count
reading <180), the next most sensitive range is selected.
An overrange voltage input condition is flagged, whenever the internal count exceeds 2000, by activating the
buzzer output (pin 3). This 4 kHz signal can directly drive a
piezoelectric acoustic transducer. An out-of-range input
signal causes the 4 kHz signal to be on for 122 ms, off for 122
ms, on for 122 ms, and off for 610 ms (see Figure 15).
Duringvoltage auto-range operation, the extended resolution feature operates on the 2000V range only. (See
extended resolution operating mode discussion.)
The resistance auto-range selection procedure is shown
in Figure 10. The 2000 range is the first range selected
unless the low ohms resistance measurement option is
selected. In low ohms operation, the first full-scale range
tried is 2 ill.
The resistance range selected maximizes sensitivity. If
the conversion results in a reading less than 180, the next
most sensitive full-scale range is tried.
lithe conversion is less than 19 in auto-range operation,
a continuous 4 kHz signal is output at BUZ (pin 3). An
overrange input does not activate the buzzer.
Example 1: In Auto-Ranging
RI (N) = 18.21 ill (20 kO Range);:: Display 18.21 kO
MEM ;:: Store 0.21 kO
RI (N + 1) = 19.87 kO (20 ill Range)
;:: Display 19.87 - 0.21 = 19.66 kO
RI (N + 2) = 22.65 ill (200 ill Range)
;:: Display 22.7 kO and MEM Disappears
Example 2: In Fixed Range 200n Full Scale
RI (N) = 18.20;:: Display 18.20
MEM ;:: Store 8.20
RI (N + 1) = 36.70
;:: Display 36.7 - 8.2 = 28.50
RI (N + 2) = 5.80
;:: Display 5.8 - 8.2 = -2.40*
'WiII display minus resistance if following input is less than offset stored
at fixed range.
Example 3: In Fixed Range 20V Full Scale
VI (N) = 0.51V;:: Display 0.51V
MEM ;:: Store 0.51 V
VI (N + 1) = 3.68V
;:: Display 3.68
~
0.51 = 3.17V
VI (N + 2) = 0.23V
;:: Display 0.23 - 0.51
=-0.28V
VI (N + 3) = -5.21V
;:: Display -5.21 - 0.51 = -5.72V
On power-up the, -M EM mode is not active. Once the MEM is entered, bringing MEM low again returns the TC818
to normal operation.
1-40
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
"''''
"''' re818
N • 0: :zoon FULL-scALE RANGE
Te8l8
...._""1"'_....
....- t -...... N =1: 2 kG FULL-SCALE RANGE
N = 0; 200 mV FULL-SCALE
RANGE
N .. U1JJ~LL.SCALE
(REIIAIN IN RANGE
SELECTED DURING
THE Klh CONVERSION)
N=NK
,...--'--...., (REMAIN IN RANGE
SELECTED
DURING THE Kill
L...--r--"" CONVERSION)
START: POWER ON, FUNTION OR MEASUREMENT OPTION CHANGE
Agura 10
Out·of-range input conditions are displayed by a blink·
ing MSD with the three LSDs set to "000," and by the fully
extended bar·graph.
The extended resolution feature operates only on the
200 kn and 2000V full·scale ranges during auto·range
operation. A blinking "1" most significant digit is interpreted
as the digit 2. The three LSDs display data normally.
START: POWER ON, FUNCTION OR
MEASUREMENT OPTION CHANGE
Figure 9
Auto-Range Operation; Resistance Measurement
Auto·Range Operation; Voltage Measurement
1-41
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH. DISPLAYS
TC818
Low-Battery Detection Circuit
The TC8t8 contains a low-battery detector. When the
9V battery supply has been depleted to a 7V nominal value,
the LCD low-battery annunciator is activated.
The low-battery detector is shown in Figure 11. The lowbattery annunciator is guaranteed to remain OFF with the
battery supply greater than 7V. The annunciator is guaranteed to be ON before the supply battery has reached 6.3V.
Triplex Liquid Crystal Display (LCD) Drive
The TC818 directly drives a triplexed LCD using 1/3 bias
drive. All numeric data, decimal point, polarity, and function
annunciator drive signals are developed by the TC818A.
The bar-graph data are developed to the TC818D. A direct
connection to a triplex LCD is possible 'without external drive
electronics. Standard and custom LCDs are readily available from LCD manufacturers.
The LCDs must be driven with an AC signal having a
zero DC componEmt, for long display life. The liquid crystal
polarization is a function of the RMS voltage appearing
across the backplane and segment driver. The peak drive
signal applied to the LCD i,s:
An "OFF" LCD segment has an RMS voltage of Vp/3
acrossitor1V.An "ON" segment hasa 0.63 Vpsignal across
it or 1.92V for Vcc - VOISP = 3V.
Since the VOISP pin is available, the user may adjust the
"ON" and "OFF" LCD levels for various manufacturer's
displays by changipg Vp signal across it or 1.92V for VCCVOISP =3V.
"OFF" segments may become visible at high LCD
operating temperatures. A voltage with a -5 to -20 mV/oC
temperature coefficient can be applied to VOISP to accommodate the liquid crystal temperature operating characteristics, if necessary.
The TC818A and TC818D internally generate two intermediate LCD drive potentials (VH and VLl from resistive
dividers (FigurE! 12) between Vcc and VDlSP. The ladder
impedance is approximately 150 kil. This drive method is
commonly known as 1/3 bias. With VOISP connected to
, digital ground, Vp ~ 5V.
The intermediate levels are needed so that drive signals
giving RMS "ON" and "OFF" levels can be generated. Figure
13 shows a typical drive signal and the resulting waveforms
for "ON" and "OFF" RMS voltage levels across a selected
numeric LCD element.
Vcc - VOISP
For,example, if VOISP is set at a potential3V below Vcc,
the peak drive signal is:
VCC
Vp = Vcc - VOISP = 3V
VCC
0-+-.---.
s~~~
LOW-BATTERY DETECTOR
DRIVE
LOGIC
TO LCD
ANNUNCIATOR
SELECTION
LOGIC
I
SOk
VH
SOk
VL ...-
.....
SETVDISP
FOR PROPER Vp
WITH RESISTIVE
DIVIDER
L..-----":r----o VDISP
~'"
50k
TC8t8A
TC8t8D
---(1-----'
~'"
TC8t8
"OFF"
VSS
"ON" =
LOW-BATTERY ANNUNCIATOR DISPLAYED FORVS < TV.
Figure 11
=vpf3 RMS
Low-Battery Detector
v'11 '"
30
P
Figure 12
1-42
RMS
1/3 Bias LCD Drive
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
SEGMENTS
BACKPLANES
I
I
I
I
SEGMENTS
I
2
3
4
5
APPLIED
RMS VOLTAGE
6
2:3:4:5:6:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~::3V) D--J--U--~--l
I
I
I
Vp :
BP2
I
I
I
:
I
I
I
I
I
I
:
:
I
I
I
I
I
VL~: !
BP3
0 f--------~---I
I
!
!
Waveforms to Generate
I
I
I
I
I
I
I
:
Vp :
I
I
I
I
I
~~ bCYu=i
VH
a (FE -BP1)
"ON"
I
- .... VRMS =
b(BCP-BP1)
"ON"
iII
Vp
3"3
I
--------~ VRMS = iII V
c(BCP-BP2)
"ON"
!
3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
:
:
I
I
I
I
I
I
I
I
:
VL
-V L
-V p
-~---j--tlJ--l---F1
:
:
:
Vp:
:
:
VH
VL
:
:
:
-V o
L
-V H
-V p
:
:
-t--------i
Triplex LCD Drive Waveforms
1-43
---------1I
Vp:
VH
Figure 13
I
I
VRMS=
~
V
3"3 P
·-~--+----t---J----~ VRMS = Vp3
e (FE -BP2
"OFF"
g(AGD-BP2)
"ON"
3"3 P
I
I
._L ________
d(AGD-BP3)
"ON"
f(FE-BP1)
"OFF"
:
I
I
I
I
I
I
I
I
I
I
I
VRMS =Vp
3
I
--------1I VRMS=.::..L.L
~
:
I
I
3"3
Vp
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
Liquid Crystal Displays (LCDs)
The 32 kHz quartz crystal is readily available and
inexpensive. The 32 kHz crystal is commonly used in digital
clocks and counters.
Several crystal sources exist. A partial listing is:
Most users design their own custom LCD. However, for
prototyping purposes, a standard display is available from
Varitronix, Ltd. The prototype display configuration is shown
in Figure 14.
• Statek Corporation
512 N. Main
Orange, CA 92668
(714) 639-7810
TWX: 910-593-1355
Telex: 67-8394
• Varitronix Ltd.
9/F Liven House, 61-63, King Yip Street
Kwun Tjong, Hong Kong
Tel: 3-410286
Telex: 36643 VTRAX HX
FAX: 852-3-439555
• Daiwa Sinku Corporation
1389, Shinzaike - AZA-Kono
Hirakacho, Kakogawa Hyogo, Japan
Tel: 0794-26-3211
Part No. VIM-328-DP
• USA Office:
VL Electronics Inc.
3171 Los Feliz Blvd, #303
Los Angeles, CA 0039
Tel: (213) 738-8700
• International Piezo LTD
24-26 Sze Shan Street
Yau Ton, Hong Kong
TLX: 35454 XTAL HZ
Tel: 3-3501151
External Crystal
Contact manufacturer for full specifications.
The TC818 is designed to operate with a 32,768 Hz
crystal. This frequency is internally divided by two to give a
61.04 I1s clock period. One conversion takes 8000 clock
periods or 488.3 ms (=2 conversions/second). Integration
time is 1638.5 clock periods or 100 ms.
PAD BP1
r-iiiMliMIi--I~-il-jj~li~I--iii;iiii-l
I
"J 0
: M;.
I.'
! *4Iil•• t. O. O. 0
:
0
5
10
15
I
kQ
mVA
!
:
20 :
l 00000000000000000000000000000000000000000 !
------------------------------------~
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
BP2
BP3
PAD BP1
-
-
XO
X5
X6
X11
X12
X17
X16
X23
X24
X29
X30
X35
X36
X1
X4
SCALE
X2
X3
X6
X9
X14
X15
X20
X21
X26
X27
X32
X33
X36
X39
19
20
21
BP1
-
Xl
X10
X13
X16
X19
X22
X25
X26
X31
X34
X37
X40
-
-
34
BP2
-
-
BP3
35
36
Figure 14 Typical LCD Ccnfiguration, TC818 Triplex
1-44
22
23
24
25
26
27
26
29
30
31
32
33
BP2
-
-
BP1
-
-
-
BP2
Lon
n
HOLD k
4B
4C
4A
4G
4F
4E
3B
3C
3A
3G
3F
3E
2B
2C
2A
2G
2A
2G
1B
1C
Z
-MEM
AC
Y
BP3
BP3
-
A
v
m
4D
-
3P
3D
-
2P
2D
2D
1P
-
AUTO
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
"Buzzer" Drive Signal
The BUZ output (pin 3) will drive a piezoelectric audio
transducer. The signal is activated to indicate, an input
overrange condition for current and voltage measu rements
or continuity during resistance measurements.
During a resistance measurement, a reading less than
19 on any full-scale range causes a continuous 4 kHz signal
to be output. This is used as a continuity indication.
. . A voltage or current input measurement overrange is
Indicated by a noncontinuous 4 kHz signal at the BUZ
output. The LCD most significant digit also flashes and the
three least significant digits are set to display zero. The
buzzer drive signal for overrange is shown in Figure 15, The
!,
BUZ output is active for any reading over 2000 counts in both
manual and auto-range operation. The buzzer is activated
during an extended resolution measurement.
The B~Z si~nal swings from Vee (pin 26) to DGND (pin
55). The Signal IS at Vcc when not active.
The BUZ output is also activated for 15 ms whenever a
range change is made in auto-range or manual operation.
Ch~nging the type of measurement (voltage, current, or
resistance), or measurement option (AC/DC, WLOQ), also
acti.vates the buzzer output for 15 ms. A range change
dunng a current measurement will not activate the buzzer
output.
-----
DIGITAL
GROUND
4 kHz SIGNAL
NONCONTINUOUS BUZZER SIGNAL INDICATES INPUT OVERRANGE
POWER UP
VIN=250mv
4000 SOOO 12000
l
INTEGRATE
TSC818A
SIGNALS
,
,
iNT :
1
t~
~ t
, 1000 CLOCK,
'PULSES'
:
n
lffihr-
'
DEINT '",_ _.ld:.......!
,
:
,
CHANGE INPUT
VIN=3.2V
'
:
nL...-~..JnL...---!---InL..........I.......InL.---'L...-rt.........:
!:::r!!--:::::~':::=--~,..,J~::--~=
r---'"
AZ '",- - - - .
,
,
:..
--t~I-----~-MANUAL RANGE:--'-----~
"
200mV
'
,
200 mV
'
RANGE
'
,,
RANGE:
OVER RANGE ,
EXTENDED ,'
BUZZ
,
(PIN
3) :;-_-t-'IIIIIIIr-IIInIIIIt-;:,;",,;,;,;,;,;,;,:::,r..:.:.:..:.:::.::::.,,!-.:.R:::A:::N:G:E.., t-""1llllll1r-,lllIIInlll-,;.;:.;:.:.:;:......J,!-..
III1""J
4 kHz 4 kHz 15 ms
ONE CYCLE OF
~
4 kHz 4 kHz.
:
I I I
_610ms'
N
~I
! OVERRANcrEBUZZ~
t
BUZZER ACTIVATED DUE
TO POWER UP
Figure 15
~8
122
BUZZER ACTIVATED DUE TO
PREVIOUS CONVERSION OVERRANGE
TC618 Timing Waveform for Buzzer Output
1-45
hUZZER
ACTIVATED
DUE TO
PREVIOUS
CONVERSION
OVERANGE
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
Vendors for piezoelectric audio transducers are:
Component Selection
• Gulton Industries
Piezo Products Division
212 Durham Avenue
Metuchen, New Jersey 08840
(201) 548-2800
Typical PINs: 102-95NS, 101-FB-00
Integration Resistor Selection
The TC818 automatically selects one of two extemal
integration resistors. RVI BU F (pin 52) is selected for voltage
and current measurement. RWBUF (pin 51) is selected for
resistance measurements.
• Taiyo Yuden (USA) Inc.
Arlington Center
714 West Algonquin Road
Arlington Heights, Illinois 60005
Typical PINs: CB27BB, CB20BB, CB355BB
RVIBUF Selection (Pin 52)
In auto-range operation, the TC818 operates with a 200
mV maximum full-scale potential at VI (pin 42). Resistive
dividers at VR2 (pin 39), VR3(pin38), VR4(pin41), andVR5
(pin 40) are automatically switched to maintain the 200 mV
full-scale potential.
In manual mode, the extended operating mode is activated giving a 300 mV full-scale potential at VI (pin 42).
The integrator output swing should be maximized, but
saturations must be avoided. The integrator will swing within
0.45V of Vce (pin 26) and 0.5V of Vss (pin 54) without
saturating. A ±2V swing is suggested. The value of RVIBUF
is easily calculated, assuming a worst-case extended resolution input signal:
Display Decimal Point Selection
The TC818 provides a decimal point LCD drive signal.
The decimal point position is a function of the selected fullscale range, as shown in Table V.
Table V. Decimal Point Selection
1
9
*
9
9
Full-Scale Range
DP3
DP2
DP1
2000V, 2000 k.Q
200V, 200 kO
20V, 20 k.Q
2V, 2 k.Q
200V, 2000
200 mY, 2000
20mA
200mA
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
RVIBUF = VMAX (tl)
ON
OFF
OFF
ON
ON
OFF
ON
where:
.VINT = Integrator swing = ±2V
tl
= Integration time = 100 ms
CI
= Integration capacitor = 0.1 IlF
VMAX= Maximum input at VI = 300 mV
RWBUF Selection (Pin 51)
In ratiometric resistance measurements, the signal at
Rx (pin 47) is always positive with respect to analog common. The integrator swings negative.
The worst-case integrator swing is for the 200Q range
with the manual, extended resolution option.
The input voltage, Vx (pin 47) is easily calculated
(Figure 16):
AC-to-DC Converter Operational Amplifier
The TC818 contains an on-chip operational amplifier
that may be connected as a rectifier for AC-to-DC voltage
and current measurements. Typical operational amplifier
characteristics are:
•
•
•
•
= 150 kn
Slew Rate: 1 V/IlS
Unity-Gain Bandwidth: 0.4 MHz
Open-Loop Gain: 44 dB
Output Voltage Swing (Load = 10 kn) ±1.5V
(Referenced to Analog Common)
RQBUF = (Vee - VANeoM) Rx
(Rx + Rs + R1 + Rs)
where:
VANCOM
Rs
RI
Rx
Rs
When the AC measurement option is selected, the input
buffer receives an input signal through switch S14 rather
than switch S11 (see Figure 1). With external circuits, the AC
operating mode can be used to perform other types of
functions within the constraints of the internal operational
amplifier. External circuits that perform true RMS conversion or a peak hold function are typical examples.
1-46
= 0.63V
= Potential at analog common = 2.7V
= 220Q
= 163.85Q
=300Q
= Internal switch 33 resistance = 600Q
AUTO-RANGING ANALOG-TO-DIGITAL
CONVERTER WITH 3-1/2 DIGIT AND
BAR-GRAPH DISPLAYS
TC818
For a 3.1 V integrator swing, the value of ROBUF is
easily calculated:
ROBUF =
(Vx Max) (tl)
~ 220 k.Q
where:
VINT
tl
CI
Rx Max
Vx Max
= Integrator swing = 3.1V
= Integration time = 100 ms
= Integration capacitor = 0.1 llF
=3000
= 700 mV
Reference Voltage Adjustment
The TC818 contains a low temperature drift internal
voltage reference. The analog common potential (pin 27) is
established by this reference. Maximum drift is a low 75
ppm/oC. Analog common is designed to be approximately
2.6V below Vcc (pin 26). A resistive divider (R18/R19.
Functional Diagram) sets the TC818 reference input voltage
(REFHI, pin 32) to approximately 163.85 mY.
With an input voltage near full scale on the 200 mV
range. R19 is adjusted for the proper reading.
Display Hold Feature
With a low battery voltage of 6.6V, analog common will
be approximately 3.6V above the negative supply terminal.
With the integrator swinging down from analog common
toward the negative supply, a 3.1 V swing will setthe integrator output to 0.5V above the negative supply.
Capacitors -
The LCD will not be updated when HOLD (pin 57) is
connected to GND (pin 55). Conversions are made. but the
display is not updated. A HOLD mode LCD annunciator is
activated when HOLD is low.
The LCD HOLD annunciator is activated through the
triplex LCD driver signal at pin 12.
CINT, CAZ and CREF
Flat Package Socket
The integration capacitor, CINT, must have low dielectric
absorption. A 0.1 llF polypropylene capacitor is suggested.
The auto-zero capacitor, CAZ, and reference capacitor.
CREF, should be selected for low leakage and dielectric
absorption. Polystyrene capacitors are good choices.
Sockets suitable for prototype work are available. A
USA source is:
• Nepenthe Distribution
2471 East Bayshore. Suite 520
Palo Alto. CA 94303
(415) 856-9332
TWX: 910-373-2060
"CBO" Socket. Part No. IC51-064-042
VCC=9V
SW3~
Rs =6000
Resistive Ladder Networks
Resistor attenuator networks for voltage and resistance
measurements are available from:
• Caddock Electronics
1717 Chicago Avenue
Riverside. CA 92507
Tel: (714) 788-1700
TWX: 910-332-6108
AHenuator
Accuracy
ANALOG COMMON
Figure 16
=Vee -
0.1%
0.25%
0.25%
3V
ROBUF Calculation (2000 Manual Operation)
1-47
AHenuator
Type
Voltage
Vottage
Resistance
Caddock
Pan Number
1776-C441
1776-C44
TI794-204-1
NOTES
1-48
.,"'TELEDYNE
COMPONENTS
(3-3/4 DIGIT) TC820
(3-1/2 DIGIT) TC821
DISPLAY AID CONVERTERS WITH FREQUENCY
COUNTER AND LOGIC PROBE
FEATURES
•
Multiple-Function Measurement System
- Analog-to-Digital Converter
- Frequency Counter
- Logic Probe
• Frequency Counter
- Measures Input Frequency to 4 MHz
- Auto-Ranging Over Four-Decade Range
• Logic Probe Inputs
- Two LCD Annunciators
- Buzzer Drive
• Peak Reading Hold With LCD Annunciator
• 3-3/4 Digit (3999 Maximum) Resolution (TC820)
• 3-112 Digit (1999 Maximum) Resolution (TC821)
• Low Noise AID Converter
- Differential Inputs, 1 pA Bias Current
- Differential Reference for Ratiometric Ohms
- On-Chip Voltage Reference, 50 ppm/DC Drift
•
•
•
•
•
•
•
No External LCD Drivers Required
- Full 3-3/4 Digit Display
- Displays "OL" for Input Overrange
- Three Decimal Point and Polarity Drivers
- LCD Annunciator Drive
- Adjustable LCD Drive Voltage
Low Battery Detect With LCD Annunciator
On-Chip Buzzer Driver and Control Input
Control Input Changes Full Scale Range by 10:1
Data Hold Input
Underrange and Overrange Outputs
Multiple Package Options
-40-Pin DIP
- 44-Pin Flat Package or PLCC
SIMPLIFIED BLOCK DIAGRAM
TRIPLEX LCD
I LOGIC HIGH I I OVERRANGE IlpKHOLDI
I LOGIC LOW I
rL'OW'iiAiTJ
3. 9.9.9
O:~~====;===;....1
EOC 0
UNDERRANGE
OVERRANGE
O--;r==:1..-_...L...L...,
ANALOG
INPUT
r;~~;'"if-l----o "'- DECIMAL
"----',
H----o
POINT
SELECT
FULLS~~:~ o - - t - - - - - '
FREQUENCY
INPUT
LOGIC 0-1-+--1
PROBE
INPUT
TO LCD
AND BUZZER
t+.:..:::.;=~o
+
*TC821 IS 3-112 DIGITS.
PEAK
HOLD
1091·1
1-49
-=-
9V
" ' - FUNCTION
SELECT
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
GENERAL DESCRIPTION
The TC820 is a 3-3/4 digit measurement system combining an integrating analog-to-digital converter, frequency
counter, and logic level tester in a single 40-pin package.
The TC820 supersedes the TC7106 in new designs by
improving performance and reducing system cost. The
TC820 adds features that are difficult, expensive, or impossible to provide with older AID converters (see the competitive evaluation). The high level of integration permits TC820based instruments to deliver higher performance and more
features, while actually reducing parts count.
Fabricated in low-power CMOS, the TC820 directly
drives a 3-3/4 digit (3999 maximum) LCD. The TC821
includes all features of the TC820, but with a resolution of
3-1/2 digits (1999 maximum).
With a maximum range of 3999 counts, the TC820
provides 10 times greater resolution in the 200 mV to 400
mV range than traditional 3-1/2 digit meters. An auto-zero
cycle guarantees a zero reading with a OV input. CMOS
processing reduces analog input bias current to only 1 pA.
Rollover error, the difference in readings for equal magn~ude
but opposite polarity input signals, is less than ±1 count.
Differential reference inputs permit ratiometric measurements for ohms or bridge transducer applications.
The TC820's frequency counter option simplifies design of an instrument well-suited to both analog and digital
troubleshooting: voltage, current, and resistance measurements, plus precise frequency measurements to 4 MHz
(higher frequencies can be measured with an extemal
prescaler), and a simple logic probe. The frequency counter
will automatically adjust its range to match the input frequency, over a four-decade range.
Two logic level measurement inputs permit a TC820based meter to function as a logic probe. When combined
with external level shifters, the TC820 will display logic
levels on the LCD and also turn on a piezoelectric buzzer
when the measured logic level is low.
Other TC 820 features simplify instrument design and
reduce parts count. On-chip decimal point drivers are included, as is a low battery detection annunciator. A piezoelectric buzzer can be controlled with an external switch or
by the logic probe inputs. Two oscillator options are provided: A crystal can be used if high accuracy frequency
measurements are desired, or a simple RC option can be
used for low-end instruments.
A "peak reading hold" input allows the TC820 to retain
the highest AID or frequency reading. This feature is useful
in measuring motor starting current, maximum temperature, and similar applications.
A family of instruments can be created with the TC821
and TC820. No additional design effort is required to create
instruments with 3-1/2 and 3-3/4 digit resolution. The TC821
can also reduce parts count in existing high-end 71 06-type
designs.
The TC820 and TC821 operate from a single 9V battery,
with typical power of 10 mW. Packages include a 40-pin
DIP, 44-pin plastic flat package, and 44-pin PLCC.
COMPETITIVE EVALUATION
TC820
7106
3-3/4 Digit Resolution
Yes
No
Auto-Rangin9 Frequency Counter
Yes
No
Logic Probe
Yes
No
Decimal Point Drive
Yes
No
Peak Reading Hold
(Frequency or Voltage)
Yes
No
Display Hold
Yes
No
Simple 10:1 Range Change
Yes
No
Buzzer Drive
Yes
No
Low Battery Detection
With Annunciator
Yes
No
Overrange Detection
With Annunciator
Yes
No
Features
Low Drift Reference
Yes
No
Underrange/Overrange
Logic Output
Yes
No
Input Overload Display
"OL"
"1"
LCD Annunciator Driver
Yes
No
Triplexed
Direct
LCD Pin Connections
15
24
LCD Elements
36
23
LCD Drive Type
1-50
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
PIN CONFIGURATIONS
0
.,
0
~
0
CI
CI
0(
BC3P2
.,
0(
0
~
II;'
..J
"'::'
III
0
..J
0
:>:
N
(j
III
III
I~
;!!;
I~
0
:>:
0
0
0
7
BC2Pl 1
..,r-
PKFEl
AGDl
TC820CLW
TC821CLW
BP1BT
SEGMENTS L-E4
1
SEGMENTS AGD4
SEGMENTS BC4P3
3
SEGMENTS AGD3
SEGMENTS BCPl
BP2
OSC2
8
CAZ
0
Z
V BUFF
CI
0
YiN
YiN
SEGMENTS PKFEl
VREF
SEGMENTS AGDl
VAEF
CREF
SEGMENTS BCl BT
BP3
CAEF
BP2
COM
BPl
DGND
ANNUNC
LOGIC
RANGElFREQ
DPOILO
BPl
VDISP
VINT
6
SEGMENTS OFE2
SEGMENTS AGD2
BP3
OSC3
OSCl
SEGMENTS HFE3
SEGMENTS BC3P2
V~
Vii
0
~
z0 o a ..J
Cs ii:
~ IL
z ..J Mi
0
z0(
0
::;)
8
CI
Z
0(
I::J
0
N
::J
N
::J
'" '"
II:
~w
0
...J
II:
::;)
~
IL
II:
lL
0
.,
~
0
0
CI
~
0(
.,
~
j",::,
0
III
0
..J
0
N
0
III
0
o&l
5w
10
BC3P2 1
PKHOLD
FREOIVOLTS
BUZIN
BUZOUT
BCP2Pl 4
..,r-
DP11H1
TC820CKW
TC821CKW
BP1BT 7
0
Z
CI
0
0
0
Z
(3
z
...J
::J
Z
0(
0
aw
II:
iii
CI
Z
0(
II:
1-51
~
I::J
0
N
::J
ii:
0
'"
;!!;
N
::J
'"
I~~
W
II:
lL
0
...J
0
:>:
~
IL
II:
::J
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
ABSOLUTE MAXIMUM RATINGS (Note 3)
Supply Voltage (Vs+ to GND) ...................................... 15V
Analog Input Voltage (Either Input) (Note 1) ..... Vs+ to VsReference Input Voltage (Either Input) .............. Vs+ to VsDigital Inputs ................................................ Vs+ to DGND
VDISP .................................................. Vs+ to DGND -0.3V
Power Dissipation, Plastic Package (Note 2) ....... SOO mW
Operating Temperature Range
"C" Devices ............................................ O°C to +70°C
"E" Devices ........................................ -40°C to +S5°C
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................... 300°C
NOTES: 1. Input voltages may exceed the supply voltages provided
that input current is limited to ±100 ~A Current above this
value may result in invalid display readings but will not
destroy the device if limited to ±1 mA
2. Dissipation ratings assume device is mounted with all leads
soldered to printed circuit board.
3. Stresses above those listed under Absolute Maximum
Ratings may cause pennanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Static-sensitive devices. Unused devices should be stored in conductive
material to protect against static discharge and static fields
ELECTRICAL CHARACTERISTICS: Vs
= 9V, TA = 25°C
Parameter
Test Conditions
Min
Typ
Max
Units
Zero Input Reading
VIN = OV
Full Scale = 200 mV
(VFS = 200 mV for TC821)
-000
±OOO
+000
Digital
Reading
RE
Roll-Over Error
VIN =±390 mV
Full-Scale = 400 mV
(VIN = ±190 mV,
VFS = 200 mV for TC821)
-1
±0.2
+1
Counts
NL
Nonlinearity (Maximum
Deviation From Best
Straight Line Fit)
Full-Scale = 400 mV
(VFS = 200 mV for TC821)
-1
±0.2
+1
Count
Ratiometric Reading
VIN - VREF, TC820
VIN = VREF, TC821
1999
999
1999/2000
999/1000
2000
1000
CMRR
Common-Mode Rejection
Ratio
VCM = ±IV, VIN = OV
Full-Scale = 400 mV
(VFS = 200 mV for TC820)
VCMR
Common-Mode Voltage
Range
Noise (P-P Value Not
Exceeded 95% of Time)
Input High, Input Low
Symbol
eN
liN
Input Leakage Current
VCOM
Analog Common Voltage
VCTC
Common Voltage
Temperature Coefficient
TCzs
TCFS
Zero Reading Drift
Scale Factor
Temperature Coefficient
VIN = OV
Full-Scale = 400 mV
(VFS = 200 mV for TC820)
VIN = OV
TA = 25°C
O'C"; TA"; +70'C
-40'C ,,; T A ,,; +85'C
25 kO Between Common and Vs+
(VS+-VCOM)
25 kO Between Common and Vs+
O'C,,; TA"; +70'C
-40'C ,,; T A ,,; +85'C
Vs +1.5
50
-
Vs+-1
fl VN
V
-
15
-
flV
-
1
20
100
10
pA
-
3.15
3.3
-
35
50
VIN = OV
O'C,,; TA"; +70'C
-40'C ,,; T A ,,; +85°C
-
0.2
1
VIN = 399 mV
(VIN = 199 mV for TC821)
O°C,,; TA"; +70°C
-40°C,,; T A ,,; +85°C
Ex1 Ref = 0 ppml°C
-
1
5
1-52
-
Digital
Reading
-
3.45
50
V
ppml'C
-
5
-
flV/'C
ppml°C
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Is
VIL
VIH
VOL
VOL
Parameter
Test Conditions
Supply Current
Peak-to-Peak Backplane
Drive Vottage
Buzzer Frequency
Counter Timebase Period
Low 'Battery Flag Voltage
Input Low VoHage
Input High Vottage
Output Low Voltage,
UR, OR Outputs
Output High Vottage,
UR, OR Outputs
Control Pin
Pull-Down Current
VIN = OV'
Vs=9V
VOISP= DGND
lose = 40 kHz
lose = 40 kHz
Vs+to Vs
Units
Min
Typ
Max
-
1
4.7
1.5
5.3
mA
V
-
kHz
Second
V
V
V
V
4.5
-
6.7
-
5
1
7
IL=50IlA
-
IL = 50 IlA
Vs+-1.5
-
VIN= Vs+
-
5
Vs+-1.5
7.3
DGND+1.5
DGND+O.4
-
V
-
IlA
PIN DESCRIPTION
Pin No.
Pin No.
(40-Pin
Packagel)
(44-Pin Flat
Package)
Symbol
40
L-E4
41
42
43
44
1
2
3
4
5
6
7
AGD4
BC4P3
HFE3
AGD3
BC3P2
OFE2
AGD2
BC2P1
PKFE1
AGD1
BC1BT
BP3
BP2
BP1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
8
9
10
11
12
13
VOISP
DGND
ANNUNC
Description
LCD segment driver lor L ("logic low'), polarity, and "e" segment of most
signfficant digit (MSD).
LCD segment drive for "a," 'g," and "d" segments of MSD.
LCD segment drive for "b" and "c" segments of MSD and decimal point 3.
LCD segment drive for H ("logic high"), and "t" and "e" segments of third LSD.
LCD segment drive for "a,' "g," and "d' segments of third LSD.
LCD segment drive lor "b" and "c" segments of third LSD and decimal point 2.
LCD segment drive for "overrange," and "f' and "e" segments of second LSD.
LCD segment drive for "a,' "g," and "d" segments of second LSD.
LCD segment drive for 'b " and "c" segments of second LSD and decimal point 1.
LCD segment drive for "hold peak reading,' and '1" and "eu segments of LSD.
LCD segment drive for 'a," 'g,' and "d" segments of LSD.
LCD segment drive for "b' and "c" segments of LSD and 'low battery."
LCD backplane #3.
LCD backplane #2.
LCD backplane #1.
Sets peak LCD drive signal: VPEAK = (Vs+) -VDISP. VOISP may also be used to
compensate for temperature variation of LCD crystal threshold voltage.
Intemallogic digital ground, the logic "0" level. Nominally 4.7V below Vs+.
Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC
can be used to control display annunciators. Connecting an LCD segment to
ANNUNC turns it on; connecting it to its backplane turns it off.
1-53
DISPLAY AID CONVERTERS
WITH FREQUENCY.COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
PIN DESCRIPTION (Cant.)
Pin No.
(40-Pin
Packagel)
Pin No.
(44-Pin Flat
Package)
Symbol
18
14
LOGIC
19
15
RANGE/
FREQ
20
16
DPO/LO
Description
Logic mode control input. When connected to Vs+, the converter is in logic mode.
The LCD displays "OL" and the decimal point inputs control the "high" and "low"
annunciators. When the "low" annunciator is on, the buzzer will also be on. When
unconnected or connected to DGND, the TC820 is in the voltage/frequency
measurement mode. This pin has a 5liA internal pull-down to DGND.
Dual-purpose input. In range mode, when connected to Vs+, the integration time
will be 200 counts instead of 2000 counts (100 instead of 1000 counts for TC821),
and the LCD will display the analog input divided by 10. (See text for limitation with
TC820.) In frequency mode, this pin is the frequency input. A digital signal applied
to this pin will be measured with a 1-second time base. There is an internal
5 IiA pull-down to DGND.
Dual-purpose input. Decimal point select input for voltage measurements. In logic
mode, connecting this pin to Vs+ will turn on the "low" LCD segment. There is an
internal 5 IiA pull-down to DGND in volts mode only. Decimal point logic:
DP1
DPO
Decimal Point Selected
0
0
0
1
0
None
DP1
DP2
DP3
21
17
DP1/HI
Dual-purpose input. Decimal point select input for voltage measurements. In logic
mode, connecting this pin to Vs+ will turn on the "high" LCD segment. There is an
internal 5 IiA pull-down to DGND in volts mode only.
22
18
BUlOUT
Buzzer output. Audio frequency, 5 kHz, output which drives a piezoelectric buzzer.
23
19
BUliN
Buzzer control input. Connecting BUliN to Vs+ turns the buzzer on. BUliN is
logically ORed (internally) with the "logic level low" input. There is an internal 5 IiA
pull-down to DGND.
24
20
FREQ/
VOLTS
Voltage or frequency measurement select input. When unconnected, or connected
to DGND, the AID converter function is active. When connected to Vs+, the
frequency counter function is active. This pin has an internal 5 IiA pull-down
to DGND.
25
21
PKHOLD
Peak hold input. When connected to Vs+, the converter will only update the display
if a new conversion value is greater than the preceding value. Thus, the peak
reading will be stored and held indefinitely. When unconnected, or connected to
DGND, the converter will operate normally. This pin has an internal 5 IiA pull-down
to DGND.
22
UR
Underrange output. This output will be high when the digital reading is 380 counts
or less (,,;:180 counts for TC821).
23
OR
Overrange output. This output will be high when the analog signal input is greater
than full scale. The LCD will display "OL" when the input is overranged.
26
24
27
25
Vs
COM
28
26
CREF+
Positive connection for reference capacitor.
29
27
Negative connection for reference capacitor.
Low differential reference input connection.
30
28
CREF
VREF+
31
29
VREF-
32
30
VIN
Negative supply connection. Connect to negative terminal of 9V battery.
Analog circuit ground reference point. Nominally 3.3V below Vs+.
High differential reference input connection.
Low analog input signal connection.
1-54
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
PIN DESCRIPTION (Cont.)
Pin No.
(40-Pin
Packagel)
Pin No.
(44-Pin Flat
Package)
Symbol
33
31
VIN·
34
32
VBUFF
35
33
CAZ
36
34
35
VINT
EOC/
HOLD
37
36
OSC1
Crystal oscillator (input) connection.
38
37
OSC2
Crystal oscillator (output) connection.
39
38
OSC3
RC oscillator connection.
40
39
Vs·
Description
High analog input signal connection.
Buffer output. Connect to integration resistor.
Auto-zero capacitor connection.
Integrator output. Connect to integration capacitor.
Bidirectional pin. Pulses low (i.e .• from Vs· to DGND) at the end of each
conversion. If connected to Vs+' conversions will continue, but the display is not
updated.
Positive power supply connection, typically 9V.
ORDERING INFORMATION
Surface-Mount Devices
Part No.
Resolution
Package
TC820CKW
3-3/4 Digits
44-Pin Plastic
Flat Package
TC820CLW
3-3/4 Digits
TC820EKW
3-3/4 Digits
44-Pin Plastic
Leaded Chip
Carrier (PLCC)
44-Pin Plastic
Flat Package
TC820ELW
3-3/4 Digits
TC821CKW
3-1/2 Digits
TC821CLW
3-1/2 Digits
TC821EKW
3-1/2 Digits
TC821ELW
3-1/2 Digits
40-Pin DIPs
Part No.
Resolution
TC820CPL
3-3/4 Digits
O·C to+70·C
O·Cta +70·C
TC820EPL
TC821CPL
3-3/4 Digits
3-1/2 Digits
-40·C to +85·C
O·Cto +70·C
O·C to +70·C
TC821EPL
3-1/2 Digits
-40·C to +85·C
Temperature
Range
-40·C to +85·C
44-Pin Plastic
Leaded Chip
Carrier (PLCC)
-40·C to +85·C
44-Pin Plastic
Flat Package
44-Pin Plastic
Leaded Chip
Carrier (PLCC)
44-Pin Plastic
Flat Package
44-Pin Plastic
Leaded Chip
Carrier (PLCC)
O·C to +70·C
Temperature Range
TC820ITC821 Comparison
Device
Feature
Resolution
All Other Features
(Counter, Logic, etc.)
O·Cta +70·C
-40·C to +85·C
-40·C to +85·C
1-55
TC820
TC821
3-3/4 Digits
3-1/2 Digits
Yes
Yes
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3 ..3/4 DIGIT)
TC821 (3-1/2 DIGIT)
FUNCTIONAL DIAGRAM
BUZZER
DRIVER
YiN
Vj"N
RANGEl
FREQ
Vi'iEF
FREQ/
VOLTS
VREF
COMMON
Vs
r----+-t-i
LOGIC
.-----r~;u~.,_--.!_I DPOILO
l::l==~ds~--I DP11H1
Vii
DGND UR OR
EOc/
HOLD
PEAK
HOLD
1-56
ANNUNC
VDISP
SEGO' •• BP3
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
I LOGIC HIGH I
I LOGIC LOW I
V+
S
22 Jill
I
24
V+~TOSWITCH
S
I
S2
FREQI
VOLTS
18
I
100 k.Q
l--_-+_--'V\(\,..._~33'_1
I
32
16
VREF =200 mV
LOGIC
VREF
YiN
COM
YiN
V; 1-4~0!...-.-_--._-. V;
~'"
DGND
TC820
TC821
RANGEIFREQ
BUZOUT
PIEZO
BUZZER
DPO/LO
BUZ IN L2::3:.........___.. 0 - - - Vs
PK HOLD 25
DP11H1
0 - - - V;
VINT CREF CREF
OSCl
37
36
0.2
!IF
28
29
0.1
!IF
NOTE:
Pin numbers are for
40'pin package.
22M!l
Rgure 1. Typical Operating Circuit
FEATURES
GENERAL THEORY OF OPERATION
The TC820 and TC821 combine the features of an
analog-to-digital converter (ADC). frequen~y c?unter. and
logic probe. in a single CMOS-integrated circuIt. All of the
TC820 features are shown graphically in the functional
diagram. With on-chip voltage reference and LCD drive
circuitry. the TC820 simplifies the design of multi-mode
measurement instruments.
The TC820 has a resolution of 3-3/4 digits (3999
maximum). while the TC821 has a resolution of 3-1/2 digits
(1999 maximum). The features of both co~~erter~ are the
same. so that both 3-314 digit and 3-1/2 digit deSigns can
be produced with only one PC board design. The differences between the TC820 and the TC821 primarily affect
system timing. and are noted in the appropriate sections of
the data sheet.
Dual-Slope conversion Principles
The TC820 analog-to-digital converter operates on the
principle of dual-slope integration. An understanding of the
dual-slope conversion technique will aid the user in following
the detailed TC820 theory of operation following this section.
A conventional dual-slope converter measurement cycle
has two distinct phases:
(1) Input Signal Integration
(2) Reference Voltage Integration (Deintegration)
Referring to Figure 2. the unknown input signal to be
converted is integrated from zero for a fixed time period
(tiNT). measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
1-57
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
conversion errors that plague successive approximation
converters in high-noise environments. Interfering signals,
with frequency components at multiples of the averaging
(integrating) period, will be attenuated (Figure 3). Integrating ADCs commonly operate with the signal integration
period set to a multiple of the 50/60 Hz power line period.
ANALOG
INPUT
SIGNAL
0-0
iii"
:!!.
z
o
REF
VOLTAGE
POLARITY CONTROL
30
T
= MEASUREMENT
I
}f
V
i3
a:
w
c
§l
I~V
PERIOD
i=
(.) 20
w
/
/
10
/
«--'
:;:
a:
o
Z
f
1fT
INPUT FREQUENCY
10fT
Analog Section
In addition to the basic integrate and deintegrate dualslope phases discussed above, the TC820 design incorporates a "zero integrator output" phase and an "auto-zero"
phase. These additional phases ensure that the integrator
starts at OV (even after a severe overrange conversion),
and that all offset voltage errors (buffer amplifier, integrator
and comparator) are removed from the conversion. A true
digital zero reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
tiNT
0
where: VREF = Reference voltage
tiNT
= Integration time
tOEINT = Deintegration time
(1)
(2)
(3)
(4)
For a constant tiNT:
VIN = VREF X
V~
TSC820 THEORY OF OPERATION
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (T OEINT) is then
directly proportional to the unknown input voltage (VIN).
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" from zero and
"ramp-down" back to zero. A simple mathematical equation
relates the input signal, reference voltage, and integration
time:
1
'--
Figure 3. Normal-Mode Rejection of Dual-Slope Converter
Figure 2. Basic Dual-Slope Converter
RINT CINT
0
O.lfT
tOEINT
Zero Integrator Output
Auto-Zero
Signal Integrate
Reference Deintegrate
Zero Integrator Output Phase
This phase guarantees that the integrator output is at
OV before the system zero phase is entered, ensuring that
the true system offset voltages will be compensated for
even after an overrange conversion. The duration of this
phase is 500 counts plus the unused deintegrate counts,
for both the TC820 and TC821.
tiNT
Accuracy in a dual-slope converter is unrelated to the
integrating resistor and capacitor values as long as they
are stable during a measurement cycle. An inherent benefit
of the dual-slope technique is noise immunity. Noise spikes
are integrated or averaged to zero during the integration
periods, making integrating ADCs immune to the large
1-58
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by opening
internal analog switches, and the internal nodes ate shorted
to Analog Common (OV ref) to establish a zero input condition. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established
on CAZ then compensates for intemal device offset voltages
during the measurement cycle. The auto-zero phase residual is typically 10 fJ.V to 15 fJ.V. The auto-zero duration is
1500 counts (750 counts for TC821).
Signal Integration Phase
Upon completion of the auto-zero phase, the auto-zero
loop is opened and the internal differential inputs connect
to VIN+ and VIN-. The differential input signal is then
integrated for a fixed time period, which is 2000 counts
(4000 clock periods) in the TC820, and 1000 counts (4000
clock periods) in the TC821. The externally-set clock
frequency is divided by two (TC820) or four (TC821) before
clocking the internal counters. The integration time period
is:
4000
tiNT = fosc
Note that for the same clock frequency, the TC820 and
TC821 have the same signal integration time. Therefore,
the noise rejection performance of the two converters will
be the same.
The differential input voltage must be within the device's
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, as in battery-powered applications,
VIN- should be tied to analog common.
Polarity is determined at the end of signal integration
phase. The sign bit is a "true polarity" indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection that is limited only by device
noise and auto-zero residual offsets.
Reference Integrate (Deintegrate) Phase
The reference capacitor, which was charged during the
auto-zero phase, is connected to the input of the integrating amplifier. The internal sign logic ensures the polarity of
the reference voltage is always connected in the phase
opposite to that of the input Voltage. This causes the integrator to ramp back to zero at a constant rate determined
by the reference potential.
The amount of time required (TDEINT) for the integrating amplifier to reach zero is directly proportional to the
1-59
amplitude of the voltage that was put on the integrating
capacitor (VINT) during the integration phase:
The digital reading displayed by the TC820 is:
Digital Count
=2000
VIN+- VINV
REF
For the TC821 , the digital reading displayed is:
VIN+- VINDigital Count = 1000 -,..,,--VREF
System Timing
The oscillator frequency is divided by 2 (4 for TC821)
prior to clocking the internal decade counters. The fourphase measurement cycle takes a total of 8000 (4000)
counts or 16000 (16000) clock pulses. The 8000 (4000)
count phase is independent of input signal magnitude or
polarity.
Each phase of the measurement cycle has the following length:
Conversion Phase
1)
2)
3)
4)
TC820
Auto-Zero:
1500
2000
Signallntegrate: 1 •2
Reference Integrate:
1 to 4001
Integrator Output Zero: 499 to 4499
TC821
Units
500
1000
1 to 2001
499 to 2499
Counts
Counts
Counts
Counts
NOTES: 1. This time period is fixed. The integration period for the
TCB20 is:
tiNT (TC820) = 4f Ooo = 2000 counts
esc
For the TCB21 , the integration period is:
=
=
40
1000 counts
tiNT (TC821)
f 00
esc
where fose is the clock oscillator frequency.
2. Times shown are the RANGE/FREO at logic low (normal
operation). When RANGE/FREO is logic high, signal
integrate times are 200 counts for TCB20 and 100 counts
forTCB21. See "10:1 Range Change" section.
Input Overrange
When the analog input is greater than full scale, the
LCD will display "OL" and the "OVER RANGE" LCD annunciator will be on.
Peak Reading Hold
The TC820 provides the capability of holding the highest (or peak) reading. Connecting the PK HOLD input
to Vs+ enables the peak hold feature. At the end of each
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
conversion the contents of the TC820 counter is compared
to the contents of the display register. If the new reading is
higher than the reading being displayed, the higher reading
is transferred to the display register. A "higher" reading is
defined as the reading with the higher absolute value.
The peak reading is held in the display register so the
reading will not 'droop" or slowly decay with time. The held
reading will be retained until a higher reading occurs, the
PK HOLD input is disconnected from Vs+, or power is removed.
The peak signal to be measured must be present
during the TC820 signal integrate period. The TC820 does
not perform transient peak detection of the analog input
signal. However, in many cases, such as measuring temperature or electric motor starting current, the TC820
"acquisition time' will not be a limitation. If true peak detection is required, a simple circuit will suffice. See the applications section for details.
The peak reading function is also available when the
TC820 is in the frequency counter mode. The counter auto~
ranging feature is disabled when peak reading hold is
selected.
10:1 Range Change
The analog input full-scale range can be changed with
the RANGEIFREQ input. Normally, RANGEIFREQ is held
low by an internal pulldown. Connecting this pin to Vs+ will
increase the full-scale voltage by a factor of 10. No extemal
component changes are required.
The RANGEIFREQ input operates by changing the
integrate period. When RANGEIFREQ is connected to
Vs+, the signal integration phase of the conversion is reduced by a factor of 10 (Le., from 2000 counts to 200
counts).
For the TC821 (3-1/2 digit) ADC, the RANGEIFREQ
input can be used to select between 200 mV and 2V full
scale. For the TC820, however, the 10:1 range change will
result in ±4V full scale. This full-scale range will exceed the
common-mode range of the input buffer when operating
from a 9V battery. If range changing is required for the
TC820, a higher supply voltage can be provided or the
input voltage can be divided by 2 externally.
The frequency counter derives its time base from the
clock oscillator. The counter time base is:
fosc
tCOUNT = 40 000
Thus, the counter will operate with a 1-second time
base when a 40 kHz oscillator is used. The frequency
counter accuracy is determined by the oscillator accuracy.
For accurate frequency measurements, a crystal oscillator
is recommended.
The frequency counter will automatically select the
proper range. Auto-range operation extends over four
decades, from 3.999 kHz to 3.999 MHz (1.999 kHz to 1.999
MHz for TC821). Decimal points are set automatically in
the frequency mode (Figure 5).
The logic switching levels of the RANGEIFREQ input
are CMOS levels. For best counter operation, an extemal
buffer is recommended. See the applications section for
details.
LogiC Probe
The TC820 can also function as a simple logic probe
(Figure 6). This mode is selected when the LOGIC input is
high. Two dual-purpose pins, which normally control the
decimal points, are used as logic inputs. Connecting either
input to a logic high level will turn on the corresponding
LCD annunciator. When the "low" annunciator is on the
buzzer will be on. As with· the frequency counter input,
external level shifters/buffers are recommended for the
logic probe inputs.
When the logic probe function is selected while FREQ/
VOLTS is low (AID mode), the ADC will remain in the autozero mode. The LCD will read "OL" and all decimal points
__
will be off (Figure 7).
If the logic probe is active while FREQ/VOLTS is high
(counter mode), the frequency counter will continue to
operate. 'rhe display will read "OL" but the decimal points
will be visible. If the logic probe input is also connected to
the RANGEIFREQ input, bringing the LOGIC input low will
immediately display the frequency at the logic probe input.
Analog Pin Functional Description
Differential Signal Inputs (VIN+), (VIN-)
The TC820 is designed with true differential inputs,
and accepts input signals within the input stage commonmode voltage (VCM) range. The typical range is Vs+ -1V to
Vs- +1.5V. Common-mode voltages are removed from the
system when the TC820 operates from a battery or floating
power source (isolated from measured system) and Vs- is
connected to analog common. (See Figure 8.)
Frequency Counter
In addition to serving as an analog-to-digital converter,
the TC820 internal counter can also function as a frequency counter (Figure 4). In the counter mode, pulses at
the RANGEIFREQ input will be counted and displayed.
1-60
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
LCD
I!
h
3.9.9.9
~~_ID_J~~~__________~{~~_ __ _
+
~
r:7I
CLOCK
~
OSQUAroR
I I
COMPARATOR
FROMINTEGRATOR~
OF AID CONVERTER
DATA LATCH, PEAK
HOLD REGISTER,
,~DOEf~ONE~
n
I
I4 -
+ 20,000
ENABLE
3-314 DIGIT COUNTER
AID CONVERTER:
FREQUENCY COUNTER
FREQI
AID CONVERTERIFREQUENCY
VOLTS ~~__~CO~U~N~TE=R~S=E=~~CT~______________
COUNT
~:
+-__~I
~""
TO DECIMAL
POINT DRIVERS
TC820
TC821
FREQUENCY
t
PROGRAMMABLE
--:;UT
DIVIDER
I'.A------I A
~__
(+_l,_1_0,_1_oo_,l_000
__) __~,~~r_--~
RA~~~ ~I-::-IN:::P""'U:::T-----I
RAN E
cJlNmoE
f--+ °"8~rE~GE
OVERFLOW
u
UNDERRANGE
DETECT
I
1+____________________----'
______~
Rgure 4. TC820 Counter Operation
In systems where common-mode voltages exist, the
86 dB common-mode rejection ratio minimizes error.
Common-mode voltages do, however, affect the integrator
output level. A worst-case condition exists if a large, positive VCM exists in conjunction with a full-scale, negative
differential signal. The negative signal drives the integrator
output positive along with VCM (Figure 9). For such applications, the integrator output swing can be reduced below
the recommended 2V full-scale swing. The integrator output will swing within O.3V of Vs+ or Vs- without increased
Ii nearity error.
~,~oo
J.J.~._'
DP3
DP2
DP1
'IN
DECIMAL POINT
o Hz-3999 Hz
4 kHz - 39.99 kHz
40 kHz - 399.9 kHz
:2: 400kHz
DP3
DP2
DP1
NONE
Reference (Vs+, Vs-)
The TC820 reference, like the analog signal input, has
true differential inputs. In addition, the reference voltage
can be generated anywhere within the power supply voltage
of the converter. The differential reference inputs permit
ratiometric measurements and simplify interfacing with
sensors, such as load cells and temperature sensors.
Rgure 5. TC820 Auto-Range Decimal Point Selection
VB Frequency Counter Input
1-61
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-314 DIGIT)
TC821 (3-1/2 DIGIT)
LCD
r--1
HIGH
rl
E~~~~~ELI
LOGIC
PROBE
INPUT
~
DETECTION
AND PULSE
STRETCHING
.
CMOS
LOGIC
LEVELS
•
0'
'L
LOW 1
~~
DPOILO
TC820
TC821
LCD
DRIVERS
DP11H1
Vs
J
LOGIC
Ln
t
DISABLE AID CONVERTER
~
-
~~ZZER
0
NC
Figure 6. Logic Probe Simplified Schematic
HIGH
1*
LOW
1**
OL
* "HIGH" ANNUNCIATOR WILL BE ON WHEN DP11H1 =
LOGIC HIGH
** ·LOW" ANNUNCIATOR AND BUZZER WILL BE ON
WHEN DPOILO
=LOGIC HIGH
Figure 7. LCD During Logic Probe Operation
To prevent roll-over-type errors from being induced by
large common-mode voltages, CREF should be large compared to stray node capacitance. A 0.1 JlF capacitor is
typical.
The TC820 offers a significantly improved analog
common temperature coeffICient, providing a very stable
voltage suitable for use as a voltage· reference. The
temperature coefficient of analog common is typically
35 ppml°C.
Analog Common
The analog common pin is set at a voltage potential
approximately 3.3V below Vs+. This potential is guaranteed to be between 3.15V and 3.45V below Vs+. Analog
common is tied internally to an N-channel FET capable of
sinking 3 rnA. This FET will hold the common line at 3.3V
below Vs+ should be an external load attempt to pull the
common line toward Vs+. Analog common source current
is limited to 12 1lA, and is therefore easily pulled to a more
negative voltage (Le., below Vs+ -3.3V).
The TC820 connects the internal VIN+ and VIN- inputs
to analog common during the auto-zero cycle. During the
reference. integrate phase, VIN- is connected to analog
common. If VIN- is not externally connected to analog
common, a common-mode voltage exists. This is rejected
by the converter's 86 dB common-mode rejection ratio. In
battery-powered applications, analog. common and VINare usually connected, removing common-mode voltage
concerns. In systems where VIN- is connected to the power
supply ground or to a given voltage, analog common should
be connected to VIN-.
The analog common pin serves to set the analog section
reference or common point. The TC820 is specifically
designed to operate from a battery or in any measurement
1-62
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
MEASURED
SYSTEM
OSC2t-'V'"'v-----'
OSC3 NC
9V
Figure 8. Common-Mode Voltage Removed in Battery Operation With VIN- = Analog Common
Table I. TC820 Control Input Truth Table
Logic Input
t
J
FREQI
VOLTS
RANGEl
FREQ
X
X
1
0
0
0
0
Where:
11= Integration Time = 4000
'OSC
CI= Integration Capacitor
RI= Integration Resistor
LOGIC
0
Frequency
Counter Input
0
TC820/821
Function
Logic Probe
AID Converter,
VFULL SCALE = 2 X VREF
AID Converter,
VFULL SCALE = 20 X VREF
Frequency Counter
NOTES: 1. Logic '0' = DGND
2. Logic '1' = Vs'
Figure 9. Common-Mode Voltage Reduces Available
Integrator Swing (VCOM '" V,N)
FREQNOLTS
This input determines whether the TC820 is in the
analog-to-digital conversion mode or in the frequency
counter mode. When FREONOLTS is connected to Vs+, the
TC820 will measure frequency at the RANGE/FREQ input.
When unconnected, or connected to DGND, the TC820 will
operate as an analog-to-digital converter. This input has an
internalS !JA pull-down to DGND.
system where input signals are not referenced (float) with
respect to the TC820 power source. The analog common
potential of Vs+ -3.3V gives a 7V end-of-battery-life voltage.
The analog common potential has a voltage coefficient of
0.001%/%.
With a sufficiently high total supply voltage (Vs+ - Vs> 7V), analog common is a very stable potential with
excellent temperature stability (typically 35 ppm/°C). This
potential can be used to generate the TC820 reference
Voltage. An external voltage reference will be unnecessary
in most cases, because of the 35 ppm/°C temperature
coefficient. See the applications section for details.
LOGIC
The LOGIC input is used to activate the logic probe
function. When connected to Vs+, the TC820 will enter the
logic probe mode. The LCD will show 'OL" and all decimal
points will be off. The decimal point inputs directly control
"high" and "low" display annunciators. When LOGIC is
unconnected, or connected to DGND, the TC820 will perform analog-to-digital or frequency measurements as selected by the FREONOLTS input. The LOGIC input has an
internal 5 !JA pull-down to DGND.
Function Control Input Pin
Functional Description
The TC820 operating modes are selected with the
function control inputs. The control input truth table is
shown in Table I. The high logicthreshoid is ;;;>Vs+-1.5Vand
the low logic level is ""DGND + 1.5V.
1-63
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
RANGEIFREQ
The function of this dual-purpose pin is determined by
the FREQ/VOLTS input. When FREQJVOLTS is connected
to Vs+, RANGEIFREQ is the input for the frequency counter
function. Pulses at this input are counted with a time base
equal to foscl40,OOO. Since this input has CMOS input
levels (Vs+ -1.5V and DGND +1.5V), an external buffer is
recommended.
When the TC820 analog-to-digital converter function is
selected, connecting RANGEIFREQ to Vs+ will divid~ the
integration time by 10. Therefore, the RANGE/FREQ Input
can be used to perform a 10:1 range change without
changing external components.
DPOILO, DP11H1
The function of these dual-purpose pins is determined
by the LOGIC input. When the TC820 is in the analog-t~
digital converter mode, these inputs control the LCD decImal points. The decimal point truth table is shown in Table II.
These inputs have internal 5 ~ pull-downs to DGND when
the voltagelfrequency measurement mode is active.
Table II. TC820 Decimal Point Truth Table
Decimal Point Inputs
DP1
DPO
0
0
0
0
1
Additional Features
The TC820 and TC821 are available in 40-pin and 44pin packages. Several additional features are available in
the 44-pin package.
EOC/HOLD
EOC/HOLD is a dual-purpose, bidirectional pin. As an
output, this pin goes low for 10 clock cycles at th~ end of
each conversion. This pulse latches the conversion data
into the display driver section of the TC820.
EOC/HOLD can be used to hold (or "freeze") the display. Connecting this pin to Vs+ inhibits the display u~date
process. Conversions will continue, but the display will not
change. EOC/HOLD will hold the display reading for either
analog-to-digital or frequency measurements.
..
The input/output structure of the EOC/HOLD pin IS
shown in Figure 10. The output drive current is only a few
microamps, so EOC/HOLD can easily be overdriven by an
open-collector logic gate, as well as a FET, bipolar transistor or mechanical switch. When used as an output, EOC/
HOLD will have a slow rise and fall time due to the limited
output current drive. A CMOS Schmitt trigger buffer is
recommended.
LCD
3999
399.9
39.99
3.999
EO~OLDo-~4t-----'------1
DISPLAY
UPDATE
-SOOk!}
Connecting the LOGIC input to Vs+ places the TC820
in the logic probe mode. In this mode, the DPO/LO and
DP1/HI inputs control the LCD "low" and "high" annunciators directly. When DP1/HI is connected to Vs+, the "high"
annunciator will turn on. When DPO/LO is connected to
Vs+, the "low" annunciator and the buzzer will turn on. The
internal pull-downs on these pins are disabled when the
logic probe function is selected.
.
These inputs have CMOS logic switching thresholds.
For optimum performance as a logic probe, external level
shifters are recommended. See the applications section for
details.
"r-
EOC
TC820
TC821
Figure 10. EOClHOLD Pin Schematic
Overrange (OR), Underrange (UR)
The OR output will be high when the analog input
signal is greater than full scale (3999 counts for TC820 and
1999 counts for TC821). The UR output will be high when
the display reading is 380 counts or less (.;;180 counts for
TC821).
The OR and UR outputs can be used to provide an
auto-ranging meter function. By logically ANDing these
outputs with the inverted EOC/HOLD output, a single pulse
will be generated each time an underranged or overranged
conversion occurs (Figure 11):
BUZIN
This input controls the TC820 on-chip buzzer drive.r.
Connecting BUZ IN to Vs+ will turn the buzzer on. There IS
an extemal pull-down to DGND. BUZ IN can be used with
external circuitry to provide additional fUr;lctions, such as a
fast, audible continuity indication.
1-64
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
A battery with voltage between 3.5V and 7V can be
used to power the TC820, when used with a voltage doubler,
as shown in Figure 13. The voltage doubler uses the
TC7660 and two external capacitors. With this configuration measurements can be referenced either to Analog
Common or to battery ground.
EOClHOLD
.,'"
'-.../
TC820 UR
TCB21
'-.../
OR
Digital Ground (DGND)
*74HC132
Figure 11. Generating Underrange and Overrange Pulses
VOISP
The VOISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VOISP is connected internally to
DGND, providing a typical LCD drive voltage of 5 Vp.p. The
44-pin package includes a separate VOISP input for applications requiring a variable or temperature-compensated
LCD drive voltage. See the applications information for
suggested circuits.
APPLICATIONS INFORMATION
Power Supplies
Digital ground is generated from an internal zener diode
(Figure 14). The voltage between Vs+ and DGND is the internal supply voltage for the digital section of the TC820.
DGND will sink a minimum of 3 mAo
DGND establishes the low logic level reference for the
TC820 mode select inputs, and for the frequency and logic
probe inputs. The DGND pin can be used as the negative
supply for external logic gates, such as the logic probe
buffers. To ensure correct counter operation at high frequency, connect a 1 JiF capacitor from DGND to Vs+.
DGND also provides the drive voltage for the LCD. The
TC820 40-pin package internally connects the LCD VDISP
pin to DGND, and provides an LCD drive voltage of about
5 Vp.p. In the 44-pin package, connecting the VDISP pin to
DGND will provide a 5V LCD drive Voltage.
Digital Input LogiC Levels
The TC820 is designed to operate from a single power
supply such as a 9V battery (Figure 12). The converter will
operate over a range of 7V to 15V. For battery operation,
analog common (COM) provides a common-mode bias
voltage (see analog common discussion in the theory of
operation section). However, measurements cannot be
referenced to battery ground. To do so will exceed the
negative common-mode voltage limit.
Logic levels for the TC820 digital inputs are referenced
to Vs+ and DGND. The high-level threshold is Vs+ -1.5V
and the low logic level is DGND +1.5V. In most cases,
+
..=.. 3.5V to 6V
.,'"
v+
5
VREF
+
VREF
..=.. 9V
TC820
TC821
.,'"
TC820
TC821
VIN +
VB
8
COM
2
+
+
10llF
4
VIN-
.,'"
5
TC7660
Vi
Figure 12. Powering the TC8201821 From a Single 9V Battery
Figure 13. Powering the TC8201821 From a Low-Voltage Battery
1·65
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
vii
3.2V
COM
5V
1 ____
P
1
DGND
Figure IS. R-C Oscillater Circuit
L---------~~-4----~~------O~
Figure 14•. DGND and COM Outputs
digital inputs will be connected directly to Vs+ with a
mechanical switch. CMOS gates can also be used to
control the logic inputs, as shown in the logic probe inputs
section.
Clock Oscillator
The TC820 oscillator can be controlled with either a
crystal or with an inexpensive resistor-capacitor combination. The crystal circuit, shown in Figure 15, is recommended when high accuracy is required in the frequency
counter mode. The 40 kHz crystal is a standard frequency
for ultrasonic alarms, and will provide a 1-second time
base for the counter or 2.5 analog-to-digital conversions
per second. Consult the crystal manufacturer for detailed
applications information.
Where low cost is important, the R-C circuit of Figure
16 can be used. The frequency of this circuit will be approximately:
fose
l
••
Typical values are R = 10 kn and C = 68 pF. The resistor value should be ;;;.100 kn. For accurate frequency
measurement, an R-C oscillator frequency of 40 kHz is
required.
System Timing
All system timing is derived from the clock oscillator.
The clock oscillator is divided by 2 (4 for TC821) prior to
clocking the AID counters. The clock is also divided by 8 to
drive the buzzer, by 240 to generate the LCD backplane
freqUency, and by 40,000 for the frequency counter time
base. A simplified diagram of the system clock is shown in
Figure 17.
Component Value Selection
Auto Zero Capacitor - CAZ
The value of the auto-zero capacitor (CAz) has some
infl~ence on system noise. A 0.47 IlF capacitor is recommended; a low dielectric absorption capacitor (Mylar) is
required.
Reference Voltage Capacitor - CREF
The reference voltage capacitor used to ramp the integrator output voltage back to zero during the reference
integrate cycle is stored on CREF. A 0.1 IlF capacitor is
typical. A good quality, low leakage capacitor (such as
Mylar) should be used .
= 0.3
RC
g 5 PF
~10PF
Integrating Capacitor - CINT
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage
reference. For this case, a ±2V integrator output swing is
optimum when the analog input is near full scale. For 2.5
readings/second (fose = 40 kHz) and VFS = 400 mV, a
0.221lF value is suggested. If a different oscillator frequency
is used, CINT must be changed in inverse proportion to
I
I
I
470k!l
22M!l
Figure 15. Suggeeted Crystal Oscillator Circuit
HIS
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
WC~
OSCILLATOR
COMPONENTS
11
Reference Voltage Selection
A full-scale reading (4000 counts for TC820 and 2000
counts for TC821) requires the input signal be twice the
reference Voltage.
XTAL~
OSCILLATOR
COMPONENTS
"''"
TC820
TC821
Table III. Reference Voltage Selection
D
Full-Scale
Input Voltage
(VFS) (Note 1)
200 mV
400 mV
IV
2V
(Notes 3,4)
AID
COUNTER
TC820
VREF
Note 2
200 mV
500mV
IV
Resolution
100J.lV
250J.lV
500J.lV
TC821
VREF
Resolution
100mV
200 mV
500mV
100J.lV
200J.lV
500J.lV
1 mV
tV
NOTES: 1. TC820/821 in AID converter mode, RANGE/FREQ = logic
low.
2. Not recommended.
3. VFS > 2V may exceed the input common mode range.
See "10: 1 Range Change" section.
4. Full-scale voltage values are not limiled 10 the values
shown. For example, TC820 VFS can be any value from
400 mVt02V.
BUZZER
LCD
BACKPLANE
DRIVER
In some applications, a scale factor other than unity
may exist between a transducer output voltage and the
required digital reading. Assume, for example, that a pressure transducer output is 800 mV for 4000 Ib/in2 . Rather than
dividing the input voltage by two, the reference voltage
should be set to 400 mV. This permits the transducer input
to be used directly.
The internal voltage reference potential available at
analog common will normally be used to supply the
converter's reference Voltage. This potential is stable
whenever the supply potential is greater than approximately
7V. The low-battery detection circuit and analog common
operate from the same internal reference. This ensures
that the low-battery annunciator will turn on at the time the
internal reference begins to lose regulation.
The TC820 can also operate with an external reference. Figure 18 shows internal and external reference
applications.
COUNTER
TIME BASE
Figure 17. System Clock Generation
maintain the nominal ±2V integrator swing. An exact
expression for CINT is:
4000 VFS
CINT = ------'-=-VINT RINT fose
where: fosc = Clock frequency
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing
CINT must have low dielectric absorption to minimize
roll-over error. A polypropylene capacitor is recommended.
Ratiometric Resistance Measurements
The TC820 true differential input and differential reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect to a known standard resistance. No accurately defined reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current is passed through the pair (Figure 19). The voltage developed across the unknown is
applied to the input and voltages across the known resistor
Integrating Resistor - RINT
The input buffer amplifier and integrator are designed
with class A output stages. The integrator and buffer can
supply 40 j.iA drive currents with negligible linearity errors.
RINT is chosen to remain in the output stage linear drive
region but not so large that printed circuit board leakage
currents induce errors. For a 400 mV full scale, RINT should
be about 100 kn.
1-67
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
~f'
+9V
+
T11'F
~f'
TC04A
t - -.....--IV;
FREQNOLTS
DGND
12V
REF
TC820
TC821
FREQUENCY
INPUT
.Xl~--t
RANGE/FREQ
COMMON
GNDQ----.-----tDGND
SET "REF" 1/2 VFULL SCALE
(a) Internal Reference
(b) External Reference
Figure 20. Frequency Counter External Buffer
Figure 1B. Reference Voltage Connections
Logic Probe Inputs
V+
VREF S
~EF4'"
o-+~-IvIN
RUNKNOWN
" ..
TC820
TC821
o-------1V;
Buffering the FREQ Input
TC820
TC821
LOGIC
When the FREOIVOLTS input is high and the LOGIC
input is low, the TCB20 will count pulses at the RANGEl
FREQ input. The time base will be foscl40,000, or 1 second with a 40 kHz clock. The signal to be measured should
swing from Vs+ to DGND. The RANGEIFREQ input has
CMOS input levels without hysteresis. For best results,
especially with low-frequency sine-wave inputs, an external
buffer with hY$teresis should be added. A typical circuit is
shown in Figure 20.
LOGIC
PROBE
INPUT
~HI>--I ~)--t
DP11H1
L-----tDPOILO
L - - - - - - - t DGND
*74HC14
Figure 21. Simple External Logic Probe Buffer
1-68
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
+9V
~---------'--~VS
r -......- - - -..
10kn
LOGIC
PKHOLD
......_IDP1/HI
>----1~~~
1 Mn
~'"
PROBEo-t--+~H
INPUT
TC820
TC821
0.01 "F~
OFFSET
NULL
TC820
TC821
LOGIC
~'"
1N4148
.~--~--~--4-"""--~vm
>---1M-~~"""--IDPO/LO
1 Mn
OV
Figure 23. External Peak Detector
~-------------IDGND
NOTE: Select Rl, R2, R3 for desired logic thresholds.
Backplane waveforms are shown in Figure 24. These
appear on outputs BP1, BP2, and BP3. They remain the
same regardless of the segments being driven.
Other display output lines have waveforms that vary
depending on the displays values. Figure 25 shows a set of
waveforms for the a, g, d outputs of one digit for several
combinations of "on" segments.
Figure 22. Window Comparator Logic Probe
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or impossible to see. To display short pulses properly, the input
pulse should be "stretched." The circuit of Figure 22 shows
capacitors added across the input pull-down resistors to
stretch the input pulse and permit viewing short-duration
input pulses.
Table IV. LCD Backplane and Segment Assignments
External Peak Detection
44-Pin
Flat Pkg
Pin No.
LCD
Display
Pin No.
BP1
BP2
40
3
LOW
" "
E4
2
3
41
42
4
5
A4
G4
C4
04
OP3
4
43
6
HIGH
F3
E3
5
44
7
A3
G3
03
OP2
40-Pin DIP
Pin No.
The TC820 will hold the highest AJD conversion or
frequency reading indefinitely when the PK HOLD input is
connected to Vs+. However, the analog peak input must be
present during the AJD converter's signal integrate period.
For slowly changing signals, such as temperature, the
peak reading will be properly converted and held.
If rapidly changing analog signals must be held, an
external peak detector should be added. An inexpensive
circuit can be made from an op-amp and a few discrete
components, as shown in Figure 23. The droop rate of the
external peak detector should be adjusted so that the held
voltage will not decay below the desired accuracy level
during the converter's 400 ms conversion time.
8
B3
C3
7
2
9
OVER
F2
E2
8
3
10
A2
G2
02
OP1
6
Liquid Crystal Display (LCD)
The TC820 drives a triplex (multiplexed 3:1) LCD with
three backplanes. The LCD can include decimal points,
polarity sign, and annunciators for overrange, peak hold,
high and low logic levels, and low battery. Table IV shows
the assignment of the display segments to the backplanes
and segment drive lines. The backplane drive frequency is
obtained by dividing the oscillator frequency by 240.
B4
9
4
11
B2
C2
10
5
12
PEAK
F1
E1
11
12
6
7
13
14
A1
B1
G1
C1
01
BATT
13
8
2,16"
14
9
15
10
BP3
BP2
15
BP1
"Connect both pins 2 and 16 of LCD to TC820 BP3 output.
1-69
BP3
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-3/4 DIGIT)
TC821 (3-1/2 DIGIT)
LCD Source
BP2 ...
n
......
-
~
Although most users will design their own custom LCD,
a standard display for the TC820 (Figure 26), Part No. ST1355-M1, is available from:
~
r-1
u~"""LJ"'-""""
Crystaloid (USA)
Crystaloid Electronics
P.O. Box 628
5282 Hudson Dr.
Hudson, OH 44238
Phone: (216) 655-2429
Fax: (216) 655-2176
BP3
Figure 24. Backplane Waveforms
SEGMG~~
ALL OFF
I ----------F-
---------
SEGME~~ ====-------"Cj=========
' :ci_________
d gOFF
Annunciator Output
-- VL
-------------------------- "oISP
a
This display can also be used with the TC821.
-------------------------- ~D
±
n
L
t-
-- VL
-- ---------__ n
___
"oISP
The annunciator output is a square wave running
at the backplane frequency (for example, 167 Hz when
fose = 40 kHz). The peak-to-peak amplitude is equal to
(Vs+ - VOISP). Connecting an annunciatorofthe LCD to the
annunciator output turns it on; connecting it to its backplane
turns it off.
LCD Drive Voltage (VOISP)
','o~ ::::::::~------§ t-
The peak-to-peak LCD drive voltage is equal to (Vs+
- VOISP). In the 40-pin dual-in-line package (DIP), VOISP is
internally connected to DGND, providing a typical LCD
drive voltage of 5 Vp.p.
For applications with a wide temperature range, some
LCDs require that the drive levels vary with temperature to
maintain good viewing angle and display contrast. In this
case, the TC820 44-pin package provides a pin connection
for VOISP. Figure 27 shows TC820 circuits that can be
adjusted to give a temperature compensation of about
10 mVfOC between Vs+ and VOISP. The diode between GND
and V OISP should have a low turn-on voltage because V OISP
cannot exceed 0.3V below GND.
r------ ==========nn -- ~ISP
i-----------i---------nE
~ -------- ----------- -- ~
-n
---
ALL ON
--
--
-----------
Crystaloid (Europe)
Rep France
102, rue des Nouvelles
F92150 Suresnes
France
Phone: 33-1-42 04 29 25
Fax: 33-1-45 06 46 99
""
~
"oISP
Figure 25. Typical Display Output Waveforms
Crystal Source
Two sources of the 40 kHz crystal are:
IHIGH I IOVERI IPEAKI raAfiJ
ILOwl ,
"
"
Statek Corp
512 N. Main St
Orange, CA 92668
Phone: (714) 639-7810
Fax: (714) 997-1256
Part #: CX-1V-40.0
"
--0.0.0.0
Figure 26. Typical TC82(}1821 LCD
1·70
SPK Electronics
2F-l, No. 312, Sec 4,
Jen Ai Rd
Taipei, Taiwan R.O.C.
Phone: (02) 754-2677
Fax: 886-2-708-4124
Part#: QRT-38-40.0 kHz
DISPLAY AID CONVERTERS
WITH FREQUENCY COUNTER
AND LOGIC PROBE
TC820 (3-314 DIGIT)
TC821 (3-1/2 DIGIT)
y+
y+
1N4148
39
39
~'"
11
20kQ
TC820
TC821
L..-_. . . .
YOISP
12
75kQ
~'"
TC820
TC821
-_..:..11!.1YOISP
OGNO
24
24
NOTE: Pin numbers shown are for 44-pin flat package.
Figure 27. Temperature-Compensating Circuits
1-71
NOTES
1·72
.,"'TELEDYNE
COMPONENTS
TC822
TC823
3-3/4 DIGIT LCD ANALOG TO DIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
3-314 Digit (3999 maximum) Resolution
3V Battery Operation
- On-Chip DC-to-DC Converter
Low Power Operation
- Supply Current 400 r.tA Typical
Differential Signal Inputs
Differential Reference Inputs
LCD with Triplexed drive
- 3-3/4 Digit Resolution
- 3 Decimal Points
- LCD Annunciator Driver Output
- Low-battery and Hold Annunciators
•
•
•
•
•
•
Op-amp for AC-to-DC Converter
Display HOLD with LCD Annunciator
Low-battery Detect with LCD Annunciator
On-chip Band-gap Reference
Crystal Oscillator
40-Pin DIP or 44-Pin Flat Package
FUNCTIONAL DIAGRAM
c+
BUFOSC
c-
IN+
INVi'iEF
VREF
COMMON
BUFFER
LOW BATTERY DETECT
t-----I
HOLD
'-------f"""';;;;~~;-l-----l DP1
L,.....!:~~-,..J--------j
14
ANNUNC
SEGO-BP3
IHOLDI
~
-3.9.9.9
1-73
DP2
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
GENERAL DESCRIPTION
The TC822 is a 3-314 digit LCD analog-to-digital converter ADC which operates from a single 3V battery. Product
designs utilizing the TC822 offer higher performance, lower
parts count and smaller size than 7106-based designs,
while the 3V battery permits a wide variety of packaging
options.
All active components necessary to construct a 0.025%
resolution measurement system are included on the TC822.
Only external resistors and capacitors, an LCD and a battery
are required.
The TC822 includes features which must be added
externally with ADCs such as the 7106. LCD decimal point
drivers, low-battery detection, and data hold function with
LCD annunciator are all on chip. No extemal exclusive-OR
gates are required. An operational amplifier, which can be
used for an AC-to-DC converter or resistance measurement
current source, is also included.
Differential signal inputs with 1 pA leakage simplify
system design. Differential reference inputs permit ratiometric
measurements, while retaining the data HOLD function.
Either the internal 1.3V band-gap reference or an external
reference can be used.
The TC822 LCD drive includes 3-3/4 digits, decimal
points, and HOLD and lOW-battery annunciators. Thetriplexed
LCD requires only 14 interconnects, which increases reliability and simplifies mechanical design.
Package options include a 40-pin 01 P and 44-pin plastic
leaded chip carrier (PLCC), and compact flat packages. The
many on-chip features of the TC822, combined with the
compact flat package and 3V battery, permit the design of
very small, high quality, economical instruments.
The TC823 offers all the features of the TC822, but with
a resolution of 3-1/2 digits.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Vs+ to GND) ................................... +4.7V
Analog Input Voltage (either input) .................... Vs+ to Vs(Note 1)
Reference Input Voltage (either input) .............. Vs+ to VsOp Amp Input Voltage (either input) .................. Vs+ to VsDigital Inputs ................................................... Vs+ to GND
Power Dissipation, Plastic Package ..................... 800 mW
Operating Temperature Range
C Devices .............................................. O°C to + 70°C
E Devices ............................................ -40°C to +85°C
Storage Temperature Range .................. -65°C to + 150°C
Lead Soldering Temperature (10 sec) ................... +300°C
NOTES: 1. Input voltages may exceed the supply voltages provided
that input current is limited to ±1 00 ~A. Current above this
value may result in invalid display readings but will not
destroy the device if limited to ±1 mAo
2. Dissipation ratings assume device is mounted with all
leads soldered to printed circuit board.
3. Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of the specifications is
not implied. Exposure to Absolute Maximum Rating
Conditions for extended periods may affect device
reliability.
4. Static-sensitive device. Unused devices must be stored in
conductive material. Protect devices from static discharge
and static fields.
ORDERING INFORMATION
Part No.
TC822CKW
TC822CLW
TC822CPL
TC822EKW
TC822ELW
TC822EPL
TC823CKW
TC823CLW
TC823CPL
TC823EKW
TC823ELW
TC823EPL
Resolution
Digits
44-Pin Plastic
Flat Package
3-314
3-314
3-314
3-314
3-314
3-314
3-1/2
3-1/2
3-1/2
3-1/2
3-1/2
3-1/2
X
44-Pin Plastic
Leaded Chip (PLCC)
40-Pin Plastic
DIP
X
X
X
X
X
X
X
X
X
X
X
1-74
Temperature
Range
O°C to +70°C
O°C to +70°C
O°C to +70°C
--40°C to +85°C
--40°C to +85°C
--40°C to +85°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
--40°C to + 85°C
--40°C to +85°C
--40°C to + 85°C
3·3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
ELECTRICAL CHARACTERISTICS: VS = 3.0 V, TA =25° C, Figure 1 Test Circuit
Parameter
Test Conditions
Min
Typ
Max
Zero Input
Reading
VIN=O.OV
Full-Scale = 400 mV
-0000
0000
+0000
RE
Roll-Over
Error
VIN=±390 mV
Full-Scale = 400 mV
-1
±0.2
+1
Counts
NL
Non-Linearity
(Max Deviation from
Best Straight Line Fit)
Full-Scale = 400 mV
-1
±0.2
+1
Count
VIN= VREF
1999
19991
2000
2000
EN
Ratiometric
Reading
Noise
(p-p value not
exceeded 95% of time)
liN
Input Leakage Current
Symbol
Units
Input
CMRR
VIN= O.OV
Full-Scale = 400 mV
VIN= 0.0 V
TA= 25°C
O°C ~ TA ~ +70°C
-40°C ~ TA ~ +85°C
Common-Mode
Rejection Ratio
Common-Mode
Voltage Range
VCM = ±0.2V, VIN = 0.0 V
Full-Scale= 400 mV
Input High, Input Low
VIN = O.OV, Full-Scale = 400 mV
Zero Reading Drfft
-
15
-
-
ILV
-
10
100
250
pA
20
100
-
50
-
-
GND +0.5
VIN=O.OV
O°C ~ TA ~ +70°C
-40°C ~ TA ~ +85°C
Ext. ReI. 0 ppml°C
-
0.2
1
-
Scale Factor
Temperature
Coefficient
VIN=399 mV
O°C ~ TA ~+70°C
-40°C ~ TA ~ +85°C
Ext. ReI. 0 ppml°C
-
±1
±5
±5
±25
Input Voltage Range
VIN+. VIN
Normal Mode +
Common-Mode Voltage
GND-o.5
-
GND +0.5
VREF
Reference
Voltage
IL= 25ILA
(VREF-GND)
1.25
1.3
1.45
TCVREF
Reference Voltage
Temperature
Coefficient
O°C ~ TA ~ +70°C
-
50
Op-Amp Input
Offset Voltage
Vs=3V
-
±10
-
±2
0.6
TCzs
TCFS
Digital
Reading
-
GND-0.5
VCMR
Digital
Reading
ILVN
V
ILV/0 C
ppml"C
V
Reference
-
V
ppml°C
Op-Amp
VIOA
Op-Amp Input
Voltage Range
Op-Amp Unity
Gain Frequency
Op-Amp Output
Voltage Swing
RL = 100 k.Q to GND
-
±2.5
Op-Amp Slew Rate
RL = 100 k.Q to GND. CL = 50 pF
-
1
1-75
-
-
mV
V
MHz
V
VlJIS
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
ELECTRICAL CHARACTERISTICS (Cont.): Vs= 3.0 V,
Symbol
TA= 25° C, Figure 1 Test Circuit
Parameter
Test Conditions
Min
Typ
Max
VIL
Input Low Voltage
DP1, DP2, HOLD
VIH
Input High VoHage
DP1, DP2, HOLD
-
-
GND+0.5
Vs+-O.5
-
-
V
V
Control Pin
Pulldown Current
VIN=VS+
-
3
-
).IA
LCD Drive Voltage
2V5. Vs+5. 4V
3.1
3.2
3.3
Vp-p
Supply Current
VIN=O.OV
Vs+=3.0 V
Vs+to GND
-
400
600
).IA
2
-
4
V
Vs+to GND
2.15
2.25
2.45
V
Units
Digital
Power Supply
Is
Supply Operating
Voltage Range
Low-Battery
Flag Voltage
iHOLOi
m § ~ m a :D
!;l
!;l
.
~
I
.."
+
-- ""'"
_,
__J __J __J
~
~
1k
~
§!
Iii
!;l
c
.."
0:
D
.:z
Ii
.." .. .. ..
m8
!;l
~
18
:
DP1
DP2
}--....-....:.:..tViN
"'"
COMMON
HOLD
TC822
C+
.0
C.
10_
C-
3.
V~EF
26
VREF
aND
33
R3
68k
R2
20k
Figure 1
Test Circuit
1-76
V+
+
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
PIN CONFIGURATIONS
Ii
B
ACEO
1
BATFCIDP1
2
BAlRDP1
+.
>
u
•
•
"''''
TC8:l2CKW
TC8Z3CKW
(44-P1N PLASTIC)
(FlATPACKAGEI
PRELIMINARY PIN DESCRIPTION AND FUNCTION,
TC822 3-3/4 DIGIT A-D CONVERTER, 3V OPERATION
Pin No.
(40-Pin
Package)
Symbol
Description
Vs+
2
OSCl
3
4
OSC2
Positive battery supply connection. Typically 3V.
Oscillator connection.
Oscillatorconnection-.----·-------------------
BUFOSC
Buffered oscillator output.
5
BCDO
LCD segment drive for 'b', 'c', and 'd' segments of least significant digit (LSD).
AGEO
BATFODPl
LCD segment drive for 'a', 'g', and 'e' segments of LSD.
LCD segment drive for LOW-BATTERY, 'f' segment of LSD, and decimal point 1.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
BCDl
LCD segment drive for 'b', 'c', and 'd' segments of 2nd LSD.
AGEl
HOLDF1DP2
LCD segment drive for 'a', 'g', and 'e' segments of 2nd LSD.
LCD segment drive for 'data hold', 'f' segment of 2nd LSD, and decimal point 2.
BCD2
AGE2
-F2DP3
LCD segment drive for 'b', 'c', and 'd' segments of 3rd LSD.
LCD segment drive for 'a', 'g', and 'e' segments of 3rd LSD.
LCD segment drive for 'polarity', l' segment of 3rd LSD, and decimal point 3.
BCD3
AGE3
LCD segment drive for 'a', 'g', and 'e' segments of MSD.
LCD segment drive for 'b', 'c', and 'd' segments of most significant
dig~
(MSD).
BP3
LCD backplane #3.
BP2
BPl
LCD backplane #2.
LCD backplane #1.
ANNUNC
Square wave output at the backplane frequency, synchronized to BP1. ANNUNC can be used
to control display annunciators. Connecting an LCD segment to ANNUNC turns it on; connecting it to its backplane turns it off.
20
DPl
Decimal Point select input.
21
22
DP2
HOLD
Decimal Point select input.
Hold input. Connecting this pin to Vs+ will1reeze' the LCD.
1-77
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
PRELIMINARY PIN DESCRIPTION AND FUNCTION,
TC822 3-3/4 DIGIT A-D CONVERTER, 3V OPERATION (Cont.)
Pin No.
(40-Pin
Package)
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
Description
CINT
BUF
Buffer output. Connect to integration resistor.
Integrator output. Connect to integration capacitor.
CAZ
VREF+
CREF+
ALitozero capacitor connection.
High differential reference input connection.
CREF
VREF
VIN+
Negative connection for reference capacitor.
VIN
COM
REFOUT
Positive connection for reference capacitor.
Low differential reference input connection.
High analog input signal connection.
Low analog input signal connection.
Analog circuit ground reference point.
Output of 1.3V voltage reference.
OAOUT
OA-
Output of uncommitted operational amplifier.
OA+
Vs
CGND
C+
Noninverting input of uncommitted operational amplifier.
Output of DC-to-DC converter. Connect a 1 ILF capacitor from this pin to power ground.
Inverting input of uncommitted operational amplHier.
Capacitor connection for DC-to-DC converter.
Power ground.
Capacitor connection for DC-to-DC converter.
FEATURES
GENERAL THEORY OF OPERATION
The TC822 and TC823 are high-resolution analog-todigital converters which include all ofthe active components
required to build a typical digital multi meter or other measurement instrument. The on-chip op-amp can be configured asa sensor amplifier, AC-to-DC converter, or resistance
measurement current source. The LCD includes decimal
points, low-battery detection, and data hold annunciators. A
DC-to-DC converter permits operation from a single 3V
battery. With on-chip voltage reference and LCD drive
circuitry, the TC822 simplifies the design of multi-mode
measurement instruments.
The TC822 has a resolution of 3-3/4 digits (3999,
maximum) while the TC823 has a resolution of 3-1/2 digits
(1999, maximum). The features of both converters are the
same, so that both 3-3/4 digit and 3-1/2 digit designs can be
produced with only one basic design. The differences between the TC822 and the TC823 primarily affect system
timing, and are noted in the ADC System Timing section of
the data sheet.
Dual-Slope Conversion Principles
The TC822 ADC operates on the principle of dual-slope
integration. An understanding of the dual-slope conversion
technique will aid the user in following the detailed TC822
theory of operation following this section. A conventional
dual-slope converter measurement cycle has two distinct
phases:
1) Input Signal Integration
2) Reference Voltage Integration (Deintegration)
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(tiNT), measured by counting clock pulses. A constant reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (tOEINT) is then
directly proportional to the unknown input voltage (VIN).
1-78
3·3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
iii'
30
T
~
t3
..,w
20
~,
w
,
,,
a:
w
c
, "
~ 10
-'
~
a:
o
Z
~
=MEASUREMENT
PERIOD
z
o
0
0.1fT
J.,.....-
+--,1-'
1fT
INPUT FREQUENCY
10fT
Figure 3 Normal-Mode Rejection of Dual-Slope Converter
' \ + - - - VIN
112 FULL SCALE
TC822 ADC THEORY OF OPERATION
VIN 1/4 FULL SCAlE
Analog Section
In addition to the basic integrate and deintegrate dualslope phases discussed above, the TC822 design incorporates a 'Zero Integrator Output' phase and an 'Auto Zero'
phase. These additional phases ensure that the integrator
starts at zero volts (even after a severe over-range conversion) and that all offset voltage errors (buffer amplifier,
integrator and comparator) are removed from the conversion. A true digital zero reading is assured without any
external adjustments.
A complete conversion consists of four distinct phases:
FIXED
SIGNAL
INTEGRATE
TIME
Figure 2
Basic Dual-Slope Converter
In a simple dual-slope converter, a complete conversion
requires the integrator output to 'ramp-up' from zero and
'ramp-down' back to zero. A simple mathematical equation
relates the input signal, reference voltage and integration
time:
r
tINT
__1__
RINT CINT 1,
where:
VREF
tiNT
tOEINT
VIN (t)dt
1)
2)
3)
4)
VREFtOEINT
RINT CINT
= Reference Voltage
Zero Integrator Output Phase
Auto Zero Phase
Signal Integrate Phase
Reference Deintegrate Phase
= Integration Time
= Deintegration Time
Zero Integrator Output Phase
This phase guarantees that the integrator output is at
zero volts after an overrange input occurs. Thus, the next
reading after an overranged reading will be correct. The ZI
phase duration varies from 0 to 600 counts.
For a constant TINT:
VIN =V REF' toEINT
~NT
Accuracy in a dual-slope converter is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. An inherent benefit of
the dual-slope technique is noise immunity. Noise spikes
are integrated, or averaged, to zero during the integration
periods, making integrating ADCs immune to the large
conversion errors that plague successive approximation
converters in high-noise environments. Interfering signals,
with frequency components at multiples of the averaging
(integrating) period, will be attenuated (see Figure 3). Integrating ADCs commonly operate with the signal integration
period set to a multiple of the 50/60 Hz power line period.
Auto Zero Phase
During the Auto Zero phase, the differential input signal
is disconnected from the measurement circuit by opening
internal analog switches and the internal nodes are shorted
to Analog Common (0 volt ref) to establish a zero input
condition. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
CAZ then compensates for internal device offset voltages
during the measurement cycle. The Auto Zero phase residual is typically 10 to 15 ~V. The Auto Zero duration is 1600
counts, plus the ZI counts if an overrange did not occur, plus
1-79
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
unused deintegration counts. Thus, the AZ phase can
occupy from 1600 to 6000 counts (600 to 3000 counts for
TC823).
count phase is independent of input signal magnitude or
polarity.
Each phase of the measurement cycle has the following
length:
Signal Integration Phase
Conversion Phase
Upon completion of the Auto Zero phase, the Auto Zero
loop is opened and the internal differential inputs connect to
VIN+ and VIN-. The differential input signal is then integrated
for a fixed time period, which in the TC822 is 2000 counts
(4000 clock periods) and in the TC823 is 1000 counts (4000
clock periods). The externally set clock frequency is divided
by two (TC822) or four (TC823) before clocking the internal
counters. The integration time period is:
1)
2)
3)
4)
TC822
TC823
Auto Zero
1600 to 5999
Signallntegrate*
2000
Reference Integrate
1 to 4000
Integrator Output Zero
0 to 400
600 to 2999
1000
1 to 2000
0 to 400
Counts
Counts
Counts
Counts
• This time period is fixed. The integration period for the
TC822 is:
'NT =4000
fosc
Note that, for the same clock frequency, the TC822 and
TC823 will have the same signal integration time. Therefore,
the noise rejection performance of the two converters will be
the same.
Polarity is determined at the end of signal integration
phase. The sign bit is a 'true polarity' indication inthatsignals
less than 1 LSB are correctly determined. This allows
precision null detection which is limited only by device noise
and Auto Zero residual offsets.
'NT (TC822) = 4000 = 2000 Counts
fose
For the TC823, the integration period is:
'NT (TC823) = 4000 = 1000 Counts
fose
where fosc is the clock oscillator frequency.
ANALOG PIN FUNCTIONAL DESCRIPTION
Differential Signal Inputs (VIN+' VIN-)
The TC822 is designed with true differential inputs and
accepts input signals within the input stage common mode
voltage range (VCM). The maximum input voltage range,
which includes normal-mode + common-mode signals, is
±0.5V.
Reference Integrate (Deintegrate) Phase
The reference capacitor, which was charged during the
Auto Zero phase, is connected to the input of the integrating
amplifier. The internal sign logic insures that the polarity of
the reference voltage is always connected in the phase
which is opposite to that of the input voltage. This causes the
integrator to ramp back to zero at a constant rate which is
determined by the reference potential.
The amount of time required (tOEINT) for the integrating
amplifier to reach zero is directly proportional to the amplitude of the voltage that was put on the integrating capacitor
(VINT) during the integration phase:
Common-mode voltages are removed from the system
when VIN- is connected to Analog Common. The TC822's
on-chip DC-to-DC converter eliminates most common-mode
difficulties and permits measurements where measurement
and power grounds cannot be isolated. (see Figure 4)
1- 3.9.9.91
!oINT = RINT • CINT • VINT
VREF
The digital reading displayed by the TC822 is:
{i1If"
V+
TC822
~~ -.8V
Digital Count = 2000. ViN- ViN
VREF
For the TC823, the digital reading displayed is:
MEASURED
SYSTEM
GND
Digital Count = 1000. vtN- ViN
VREF
Figure 4
ADC System Timing
-
Vi~
->->--
COMMON
YiN
Vs
C+
-
:!:
71
C-
-=r " l-- 3V
vS
DC-to-DC Converter Permits
Ground Referenced Measurements
Common-mode voltages with respect to powerG ND do,
however, affect the integrator output level. The user must be
particularly careful that the integrator does not saturate
when at minimum battery voltage. A worse case condition
The oscillator frequency is divided by 2 (4 for TC823)
prior to clocking the internal decade counters. The four
phase measurement cycle takes a total of 8000 (4000)
counts Or 16000 (16000) clock pulses. The 8000 (4000)
1-60
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
exists if a large positive VCM exists in conjunction with a fullscale negative differential signal. The negative signal drives
the integrator output positive along with VCM (Figure 5). For
such applications the integrator output swing can be reduced below the recommended 1.5V full-scale swing. The
integrator output will swing within 0.3V of Vs+ orVs-without
increased linearity error.
systems where VIN- is connected to the power supply ground
or to a given voltage, Analog Common should be connecled
to VIN-.
The Analog Common pin serves to set the analog
section reference or common point. The TC822 is specifically designed to operate from a battery or in any measurement system where input signals are referenced to the
TC822 power source, so Analog Common is normally connected to power GND.
DIGITAL PIN FUNCTIONAL DESCRIPTION
DP1, DP2
These inputs control the LCD decimal points. The decimal point truth table is shown in Table 1. These inputs have
internal 3 !lA pulldowns to DGND.
Table 1 TC822 Decimal Point Truth Table
Decimal Point
DP2
where:
VI
=INTEGRATION TIME = 4000
0
0
'OSC
=INTEGRATING CAPACITOR
RI =INTEGRATING RESISTOR
0
0
CI
Figure 5
Inputs
DP1
LCD
3999
399.9
39.99
3.999
Hold
Common-Mode Voltage Reduces Available
Integrator Swing. (VCOM'" VIN)
HOLD can be used to hold or 'freeze' the display.
Connecting this pin to Vs+ inhibits the display update process. Conversions will continue, but the display will not
change.
Reference Inputs (VREF+' VREF-)
The TC822 reference, like the analog signal input, has
true differential inputs. In addition, the reference voltage can
be generated anywhere within the power supply voltage of
the converter. The differential reference inputs permit
ratiometric measurements and simplify interfacing with sensors sljch as load cells and temperature sensors.
APPLICATIONS INFORMATION
Power Supplies
This pin is the buffered output of the internal CMOS
band-gap reference. The output voltage is typically 1.3V
above power GND, with a load current of 25 (.IA. The
temperature coefficient of REFOUT is typically 50 ppm/°C.
The TC822 is designed to operate from a 3V battery, but
will operate over a range of 2.0 to 4.0V. An on-chip DC-toDC converter converts the +3V supply to -3V, which permits
bipolar input voltages to be converted. Measurements are
referenced to battery ground, so that the TC822/823 are
ideal for applications such as measuring battery voltage,
battery charging current, etc.
Analog Common
Op-Amp Power Supply Current
The TC822 connects the internal VIN+ and VIN- inputs to
Analog Common during the Auto Zero cycle. During the
reference integrate phase VIN- is connected to Analog
Common. If VIN- is not externally connected to Analog Common, a common-mode voltage exists. This is rejected by the
converter's 86 dB common-mode rejection ratio. In battery
powered applications, Analog Common and VIN- are usually
connected, removing common-mode voltage concems. In
The op-amp of the TC822 has a low-distortion class A
output, which is biased at 100!lA. To reduce supply current
when the op-amp is not being used, connect the noninverting input to Vs-, as shown in Figures 6 and 11. When
the op-amp is used, supply current will increase by about
200!lA.
Reference Output (REFOUT)
1-81
•
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
Vs
XTAL OSCILLATOR
COMPONENTS
36
35
34
OA+
OA-
O~~;-:
...J...r--....--IID11--.'--'1
7
I
I
I
I
I
7
OSC1
OSC2
BUFOSC
..,rFigure 6
TC822
TC823
Simplified Op-Amp Output Schematic
Clock Oscillator
The crystal oscillator circuit is shown in Figure 7. An
inexpensive 32.768 kHz watch crystal gives about 27 dB
noise rejection at 60 Hz, while a 40 kHz crystal (used in
ultrasonic alarms) will almost totally reject 50 and 60 Hz
noise.
15M
Figure 8
,
I
I
I
I
I
I
Integrating Capacitor - CINT
I
I
2
32.768 kHz
40kHz
...---tD
5PF~
Figure 7
3
~
---------
System Clock Generation
cycle is stored on CREF. A 0.22 j.lF capacitor is typical. A good
quality, low leakage capacitor, such as polyester, should be
used.
I
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage reference. For this case a ±1.5 V integrator output swing is
optimum when the analog input is near full-scale. For 2.5
readings/second (fosc=40 kHz) and VFS =400 mV, aO.27 j.lF
value is suggested. For a 32.768 kHz crystal, use 0.22 j.lF.
If a different oscillator frequency is used, CINT must be
changed in inverse proportion to maintain the nominal ±1.5V
integrator swing. An exact expression for CINT is:
4
5pF
Crystal Oscillator Circuit
System Clock
All system timing is derived from the clock oscillator. The
clock oscillator is divided by two (four for TC823) prior to
clocking the AID counters. The clock is also divided by 4 to
drive the DC-to-DC converter, and by 768 to generate the
LCD backplane frequency. A simplified diagram of the
system clock is shown in Figure 8.
where:
COMPONENT VALUE SELECTION
Auto Zero Capacitor - CAZ
CINT = _....:4",0",0.::.0-,V,-,F.."S_
VINT • R'NT • fosc
fosc = Clock frequency
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator
output swing
C'NT must have low dielectric absorption to minimize
roll-over error. A polypropylene capacitor is recommended.
The size oft he Auto Zero capacitor (CAZ) has some effect
on system noise. A 0.22 j.lF capacitor is recommended. A
capacitor with low dielectric absorption (polyester) is required.
Integrating Resistor - RINT
The input buffer amplifier and integrator are designed
with class A output stages. The integrator and buffer can
supply 5 j.tA drive currents with negligible linearity errors.
RINT is chosen to remain in the output stage linear drive
Reference Voltage Capacitor - CREF
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
1-82
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
region but not so large that printed circuit board leakage
currents induce errors. For a 400 mV full-scale, RINT should
be about 100 kil.
Reference Voltage Selection
A full scale reading (4000 counts for TC822 and 2000
counts for TC823) requires that the input signal be twice the
reference voltage. For example, a 400 mV full scale TC822
requires a reference voltage of 200 mV.
In some applications a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, that a pressure transducer output is 500 mV for 4000 Ib/in2 . Rather than dividing
the input voltage by 1.25, the reference voltage should be
set to 250 mV. This permits the transducer input to be used
directly. For best results, full scale voltage should be limited
to 500 mV.
The TC822 can also operate with an external reference.
Figure 9 shows internal and external reference applications.
Ratiometric Resistance Measurements
The unknown resistance is put in series with a known
standard and a current is passed through the pair (Figure
10). The voltage developed across the unknown is applied
to the input and the voltage across the known resistor
applied to the reference input. If the unknown equals the
standard, the input voltage will equal the reference voltage
and the display will read 2000 (1000 for TC823). The
displayed reading can be determined from the following
expression:
Displayed Reading
= RUNKNOWN • 2000
RSTANDARD
The display will overrange for RUNKNOWN ~ X RSTANDARD
RSTANDARD
VREF
9----4--'>--; YIN
6---~r---f
The TC822 true differential input and differential reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
..,,,
TC822
RUNKNOWN
YiN
ANALOG
COMMON
Figure 10 Low Parts Count Ratiometric Resistance Measurement
V+
I
Vs
V+
S
REF OUT
-=-
AJ,"
-'-
3V
~ SOK
~
~ SOK
VREF
TCB22
TCB23
AJ,"
AJ,"
TCB22
TC823
TC04
VtEF
I
VREF
COMMON 1 - - -....
COMMON
GND
1
SET VREF
=1/2 FULL SCALE
(a) INTERNAL REFERENCE
Figure 9
(b) EXTERNAL REFERENCE
Internal and External Reference Applications
1-83
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
AC-to-DC Converter
Table 2
LCD Pin Assignment, TC822
The on-chip op amp of the TC8221823 can be combined
with external components to convert an AC voltage into a DC
voltage. Figure 11 shows a typical circuit.
Pin
COM1
COM2
COM3
COM 1
2
3
4
5
6
7
8
LCD
The TC822 drives a triplex (multiplexed 3:1) liquid
crystal display with three backplanes. The LCD includes
decimal points, polarity sign, and annunciators for data hold
and low-battery. Table 2 shows the assignment of the
display segments to the backplanes and segment drive
lines. The backplane drive frequency is obtained by dividing
the oscillator frequency by 768.
9
10
11
12
13
14
15
16
17
18
COM2
BO
AO
BATTERY
B1
A1
HOLD
B2
A2
Y
B3
A3
CO
GO
FO
C1
G1
F1
C2
G2
F2
C3
G3
30
"''"
TC822
AC
30
ViN
37
Vs
31
viN
COMMON
Figure 11 Low Cost AC-to-DC Converter
1-84
COM3
DO
EO
P1
D1
E1
P2
D2
E2
P3
D3
E3
3-3/4 DIGIT LCD
ANALOG TO DIGITAL CONVERTER
TC822
TC823
Backplanes waveforms are shown in Figure 12. These
appear on outputs BP1, BP2, and BP3. They remain the
same regardless of the segments being driven.
BP2 -'
...--.
LJ
n
=
....................
=
LJ
n=
..........
c
Other display output lines have waveforms that vary
depending on the displays values. Figure 13 shows a set of
waveforms for the AGE outputs of one digit for several
combinations of 'on' segments.
- - - - - - - - - - - - - - - - - - - - - - - - - - Voo
J
I
ALLOFF-----------
---------r ::
------------q---------
d,gOFF
Varitronix
9/F Liven House
61-63 King Yip Sireel
Kwun Tjong
Hong Kong
Tel: 3-410286
FAX: 3-439555
.....,.,.,.,:
___,1
~
lOVER
I I
PEAK
I CBATIJ :
~
- - - - - - - - - - - - - - - - - - - - - - - - - - V OISP
.SEQME~~ - - - - - - -
Although most users will design their own custom LCD,
a standard display for the TC822 is available. Figure 14
shows a display, part No. VIM428-DP, available from
Varitronix.
Varitronix (USA)
VL Electronics
3171 Los Feliz Blvd
Suite 303
Los Angeles, CA 90039
Tel: (312) 661-8883
FAX: (213) 663-3711
Part No.:jg VIM428-DP
Figure 12 Backplane Waveforms
SEGMc.~~
LCD Source
I
I
. .' . . .' . . .' ______
...
1----------------1:
Voo
- - - - - - - - - YH
0=========== ________ 1 :~sP
~.~ ::::::::Fu-----~::
Figure 14 Typical TC8221823 LCD
]------- --=========---- -:~ISP
Annunciator Output
~~ f:::::::::-tu--------f:
-----------
-----------
----------
The annunciator output is a square wave running at the
backplane frequency (for example, 52 Hz when
fosc = 40 kHZ). The peak-to-peak amplitude is the same as
the backplane and segment driver outputs. Connecting an
annunciator of the LCD to the annunciator outputturns it on;
connecting it to its backplane turns it off.
-VL
V 01SP
Figure 13 Typical Display Output Waveforms
LCD Drive Voltage
The peak-to-peak LCD drive voltage is typically 3.2 Vpp.
This voltage will remain stable until the battery voltage falls
below the point where the low-battery flag turns on
(about 2.1V).
1-85
NOTES
1-86
"~TELEDYNE
COMPONENTS
TC826
AID CONVERTER WITH BAR GRAPH DISPLAY OUTPUT
FEATURES
GENERAL DESCRIPTION
•
•
..
•
•
•
•
•
•
•
•
•
In many applications a graphical display is preferred
over a digital display. Knowing a processor system operates,
for example, within design limits is more valuable than a
direct system variable readout. A bar or moving dot display
supplies information precisely without requiring further interpretation by the viewer.
The TC826 is a complete analog-to-digital converter
with direct liquid crystal (LCD) display drive. The 40 LCD
data segments plus zero driver give a 2.5% resolution bar
display. Full-scale differential input voltage range extends
from20mV t02V. The TC826 sensitivity is 500 I1v. A low drift
35 ppm'°C internal reference, LCD backplane oscillator and
driver, input polarity LCD driver, and overrange LCD driver
make designs Simple and low cost. The CMOS design
required only 12511A from a 9V battery. In +5V systems a
TC7660 DC to DC converter can supply the -5V supply. The
differential analog input leakage is a low 10 pA.
Two display formats are possible. The BAR mode
display is like a 'thermometer' scale. The LCD segment
driver that equals the input plus all below it are on. The DOT
mode activates only the segment equal to the input. In either
mode the polarity signal is active for negative input signals.
An overrange input signal causes the display to flash and
activates the overrange annunciator. A hold mode can be
selected that freezes the display and prevents updating.
The dual slope integrating conversion method with
auto-zero phase maximizes noise immunity and eliminates
zero-scale adjustment potentiometers. Zero-scale drift is a
low 511V/oC. Conversion rate is typically 5 per second and
is adjustable by a single external resistor.
A compact, 0.5" square, flat package minimizes PC
board area. The high pin count LSI package makes multiplexed LCD displays unnecessary. Low cost, direct drive
LCD displays offer the widest viewing angle and are readily
available. A standard display is available now for TC826
prototyping work.
Bipolar AID Conversion
2.5% Resolution
Direct LCD Display Drive
'Thermometer' Bar or Dot Display
40 Data Segments Plus Zero
Overrange Plus Polarity Indication
Precision On-Chip Reference •............... 35 ppm/DC
Differential Analog Input
Low Input Leakage .......................................... 10 pA
Display Flashes on Overrange
Display Hold Mode
Auto-Zero Cycle Eliminates Zero Adjust
Potentiometer
• 9V Battery Operation
.. Low Power consumption ••••.••.•...•.....•.....•..• 1.1 mW
• 20 mV to 2.0 V Full-Scale Operation
• Non-Multiplexed LCD Drive for Maximum Viewing
Angle
PIN CONFIGURATION
1093-1
1-87
AID CONVERTER WITH
BAR GRAPHDISPLAV OUTPUT
TC826
ORDERING INFORMATION
Package
Part No.
TC826CBQ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to \f) .......... ,................................. 15V
Analog Input Voltage (either input)(l) ................... V+ to VPackage Power Dissipation
'
Flat Package .................................................. 500 mW
Operating Temperature
'C' Devices ..........................•.................. O°C to +70°C
Storage Temperature ................. ,........... -65°C to +150°C
Lead Temperature (Soldering. 60 sec) .................... 300°C
Temperature
60-Pin Plastic
Quad Flat Package
Formed Leads
Static·sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings,may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended'
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS:
unless otherwise stated Vs
Parameter
Test Conditions
Zero Input
VIN= O.OV
2
-
Zero Reading Drift
VIN= O.OV
DoC ~ TA ~ 70°C
3
NL
Linearity Errpr
No.
1
Symbol
= 9V; ROSC =430 kn; TA = 25°C; Full-Scale = 20 mV.
Min
Typ
Max
Unit
-0
±o
+0
Display
-
0.2
1
fJ.V/oC
Max Deviation From
Best Straight Line
-1
0.5
+1
Count
-1
0
+1
Count
60
-
fJ.VP-P
4
-
Rollover Error
-VIN = +VIN
5
EN
Noise
V IN = OV
Input Leakage Current
VIN =OV
Common-Mode
Rejection Ratio
VCM=±,1V
6
ILK
7
CMRR
8
9
10
VCTC
-
VIN
-
=OV
10
20
-
50
-
fJ. VN
pA
-
ppm/°G
Scale Factor
Temperature Coefficient
o ~TA ~ 70°C
External Ref. Temperature
Coefficient 0 ppm/°C
-
1
Analog Common
Temperature Coefficient
250 k.Q Between
Common and V+
O°C ~ T A ~ 70°C
-
35
100
ppm/°C
Analog Common
Voltage
250 k.Q Between
Common and Vs+
2.7
2.9
3.35
V
=
11
VSD
LCD Segment
Drive VoHage
4
5
6
Vp_p
12
VBD
LCD Backplane
Drive Voltage
4
5
6
Vp_p
-
125
175
fJ.A
13
-
Power Supply Current
NOTES: 1. Input voltages may exceed the supply voltages when
3. Backplane drive is in phase with segment drive for 'off'
segment and 180°C out of phase for 'on' segment.
Frequency is 10 times conversion rate.
4. Logic input pins 58, 59, and 60 should be connected
through 1 Mn series resistors to Vs- for logic O.
the input current is limited to 100 /lA.
2. Static sensitive device. Unused devices should be
stored in conductive material to protect devices from
static discharge and static fields.
1·88
AID CONVERTER WITH
BAR GRAPH DISPLAY OUTPUT
TC826
PIN DESCRIPTION AND FUNCTION
Pin No.
Name
Analog
Common
3
4
+IN
-In
REFIN
Establishes the internal analog ground point. Analog common is set to 2.9V below the positive supply
by an internal zener reference circuit. The vo~age difference beween Vs+ and analog-common can be
used to supply the TC826 vo~age reference input at REF IN (Pin 4).
Positive analog signal input.
Negative analog signal input.
Reference vo~age posttive input. Measured relative ato analog-common. REF IN '" Full-Scale/2.
Reference capacitor connection.
5
6
7
8
9
10
11
Description
CREF-
Reference capacitor connection.
VBUF
Buffer output. Integration resistor connection.
Positive supply terminal.
CAZ
Negative comparator input. Auto-zero capacttor connection.
VI NT
VS-
Negative supply terminal.
Integrator output. Integration capacitor connection.
12
OSCl
Oscillator resistor (Rose) connection.
13
OSC2
Oscillator resistor (Rose) connection.
14
BP
15
BAR 0
16
17
18
19
20
21
22
23
24
25
2
3
4
5
6
7
8
9
10
11
LCD Backplane driver.
LCD Segment driver: Bar 0
2
3
4
5
6
7
27
12
28
13
8
9
10
11
12
13
14
26
29
14
30
15
15
31
34
16
17
18
19
16
17
18
19
20
32
33
35
20
36
21
21
37
38
22
23
22
39
40
24
25
24
25
41
26
26
42
43
27
27
28
28
23
1-89
AID CONVERTER WITH
BAR GRAPH DISPLAY OUTPUT
TC826
PIN DESCRIPTION AND FUNCTION (Cont.)
Pin No.
Name
Description
44
BAR 29
LCD Segment driver: Bar 29
30
45
30
46
31
31
47
32
32
48
33
33
49
34
34
50
35
35
51
36
36
52
37
37
53
38
38
54
39
55
40
39
40
LCD segment driver that indicated input out-of-range condition.
56
OR
57
POL-
58
BARIDOT
59
HOLD
Input logic signal that prevents display from changing. Pulled high internally to inactive state.
Connect to Vs- through 1Mn series resistor for HOLD mode operation.
60
TEST
Input logic signal. Sets TCa05 to BAR display mode. Bar 0 to 40, plus OR flash on and off. The POLLCD driver is on. Pulled high internally to inactive state. Connect to Vs- with 1 Mn series resistor to
activate.
LCD segment driver that indicates input signal is negative.
Input logic signal that selects bar or dot display format. Normally in bar mode. Connect to Vs- through
1Mn resistor for Dotformat.
C INT
RINT
CREF
CREF
1.0 J.lf
BARfOOT
ase1 12
..,~
HOLD
ROSC
430 kO.
TC826
1 Mfl
60
11
OSC2
TEST
BP
Vg
OR
BARaBAR40 POL-
w
2:
13
14
56
57
a:
c
R,
9V
...z
R2
BACKPLANE
w
:IE
-IN +IN
"w
VI
COMPONENT
20mV
2V
200mV
FULL-SCALE FULL-SCALE FULL-SCALE
RINT
2 Mfl
200 kQ
23 kQ
CINT
0.033 J.l-f
0.033 J,lf
0.03311'
CREF
1 ~f
1 ~f
1 ~f
0.068 11'
0.068/1'
0.014 11'
CAZ
OR
DDDDDD
R, + R2 = 250 kO
Figure 1 Typical TC826 Circuit Connection
1-90
41 SEGMENT
LCD BAR GRAPH
AID CONVERTER WITH
BAR GRAPH DISPLAY OUTPUT
D
TC826
DUAL SLOPE CONVERSION PRINCIPLES
The TC826 is a dual slope, integrating analog-to--digital
converter. The conventional dual slope converter measurement cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (Deintegration)
The input signal being converted is integrated for a fixed
time period (TSI). Time is measured by counting clock
pulses. An opposite polarity constant reference voltage is
then integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional
to the input signal (TRI). (Figure 2).
In a simple dual slope converter a complete conversion
requires the integrator output to 'ramp-up' and 'rampdown'.
A simple mathematical equation relates the input signal
reference voltage and integration time:
r
Jo
RC
~
m
:!!.
z
l-oQ
...,
TSI
...L
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high noise environments.
Interfering signals with frequency components at mUltiples
of the averaging period will be attenuated. (Figure 3.)
The TC826 converter improves the conventional dual
slope conversion technique by incorporating an auto-zero
phase. This phase eliminates zero-scale offset errors and
drift. A potentiometer is not required to obtain a zero output
for zero input.
w
w
VIN(t) dt =VRTRI
RC
30
T
20
Z
0
I
~
VIN ~ 112 vFULL-SCALE
VIN
~
)1
lIT
101T
INPUT FREQUENCY
Normal-Mode Rejection 01 Dual Slope Converter
CLOCK
POLARITY CONTROL
~ 8 ~,\"
,..
..,.
..,
-
~
O.llT
REF
VOL'tAGE
I
,,
-'
Figure 3
cC ~
,'f
~ 10
TSI
gl-
V
l!:l
~
a:
o
y~
PERIOD
a:
Where:
Vii = Reference Voltage
VSI'" Signal Integration Time (Fixed)
TRI = Reference Voltage Integration Time (Variable)
For a constant VIN: VIN =VA TAl
II:lA
= MEASUREMENT
1/4 vFULL-SCALE
FIXED SIGNAL VARIABLE
INTEGRATE REFERENCE
TIME
INTEGRATE
TIME
Figure 2 Basic Dual Slope Converter
1-91
AID CONVERTER WitH
BAR GRAPH DISPLAY OUTPUt
TC826
THEORY OF OPERATION
Analog Section
offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages.
The auto-zero cycle length is 19 counts minimum.
Unused time in the deintegrate cycle is added to the autozero cycle.
In addition to the basic signal integrate and deintegrate
cycles discussed above, the TC826 incorporates an autozero cycle. This cycle removes buffer amplifier, integrator,
and comparator offset voltage error terms from the conversion. A true digital zero reading results without extemal
adjusting potentiometers. A complete conversion consists
of three cycles: an auto-zero, signal integrate and reference
cycle. (Figures 4 and 5.)
Signal Integration Cycle
The auto-zero loop is opened and the internal differential inputs connect to +IN and -IN. The differential input
signal is integrated for a fixed time period. The TC826 signal
integration period is 20 clock periods or counts. The externally set clock frequency is divided by 32 before clOCking the
internal counters. The integration time period is:
Auto-Zero Cycle
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(internal analog ground) to establish a zero input condition.
Additional analog gates close a feedback loop around the
integrator and comparator. This loop permits comparator
TSI .. ~x20
Fosc
Where:
Fosc = External Clock Frequency
v~
REF IN
r--r4~--~r----------r------r---~----~----------~7--Tr-AZ
Ccii.iP
• INPUT
to DIGitAL
secnON
INT
AZ
~.3V
-~PUT~~----------------4-------------~
FROM
{_
DIGITAL
_ AZ
INT
DE.
CONTROL
_
SECTION
_
DE-
o
ANALOG SWITCH
~VS-2.9V
~"
TC826
11
~Vs
Figure 4
TC826 Analog Section
1-92
AID CONVERTER WITH
BAR GRAPH DISPl..AY OUTPUT
D
TC826
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share-lhe same
power supply CQmmon, -IN should be tied to analog-commono This is the usual connection for battery operated
systems. Polarity is determined at the end of signal integrate
signal phase. The sign bit is a true polarity indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection limited only by device noise
and system nQise.
cycle takes a total of 80 clock pulses. The 80 count cycle is
independent of input signal magnitude.
Each phase ofthe measurement cycle has the following
length:
• Auto-Zero Phase: 19 to 59 Counts
For signals less than full-scale the auto-zero is assigned the unused reference integrate time period.
• Signal Integrate: 20 Counts
This time period is fixed. The integration period is:
Reference InteQ/lIte Cycle
The final phase is reference integrate or deintegrate. IN is intemally CQnnected to analog common and +IN is
connected with the CQrrect polarity to cause the integrator
output to retum to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 40 counts. The digital reading displayed is:
20=
=20[
32J
FosJ
Where Fosc is the extemally set clock frequency.
TSI
• Reference Integrate: 0 to 41 Counts
Reference Voltage Selection
A full-scale reading requires the input signal be twice the
reference voltage. The reference potential is measured
between REF IN (Pin 4) and Analog-Common (Pin 1).
VIN
VREF
Required Full-Scale Voltage
System Timing
20mV
2V
The oscilll;llQr frequency is divided by 32 propr to clocking the internal counters. The three phase measurement
SIGNAL
INTeGRATE
PHASE (Sl)
AUTOo-lERO
PHASE(~
10 mV
1V
REFERENCE INTEGRATE
PHASE (RI)
(DEINTEGRATE)
SIGN BIT
DETeRMINED
INTeGRATOR
OUTPUT
ANALOG
COMMON
POTeNTIAL
ZERO CROSSING
DETECTED
INTeRNAL
SYSTEM CLOCK
(FSYS)
~ ~ tul.j-u--(
~ 6
o
~
I'-
4
2
o
~
18
o
o
Figure 8
2
4
I...... i"oo..
6 8 10 12 14 16 18 20
Rose (X 100 kO)
Oscillator Freqllency VB, ROSC
FOSC is divided by 32 to provide an internal system
clock, FYSY. Each conversion requires SO internal clock
cycles. The internal system clock is divided by 8 to provide
the LCD backplane drive frequency. The display flash rate
during an input out-of-range signal is set by dividing FSYS
by 320. (See Figure 9.)
The internal oscillator may be bypassed by driving OSCI
(Pin 12) with an external signal generator. OSC2 (Pin 13)
should be left unconnected.
The oscillator should swing from Vs+ to Vs- in single
supply operation (Figure 10A). In dual supply operation the
signal should swing from power supply ground to Vs+.
AID CONVERTER WITH
BAR GRAPH DISPLAY OUTPUT
TC826
A. BAR MODE
7
J-
"""
1.INPUT,,0
TC826
r
9V
12
OSC1
1
-.....
BAR 4 c::::::J
BAR 3
BAR 2 c::::::J
BAR 1 c::::::J
BAR 0 tzZZ:a
r
2. INPUT = 5%
OF FULL-SCALE
OFF
c::::J OFF
3
OSC2
;;1"0.1 II'
OFF
OFF
ON
c:::::::J OFF
c::::::J OFF
tzZZ:a ON
iZZZaON
iZZZaON
B.DOTMODE
I--
EXTERNAL
OSCILLATOR
2. INPUT = 5%
OF FULL-SCALE
1.INPUT=0
BAR 4 c::::::J
BAR 3 c::::::J
BAR 2 c::::::J
BAR 1
BAR 0 tzZZ:a
A. SINGLE 9V SUPPLY
c::::J
VS"SV
Vs 7
OFF
OFF
OFF
OFF
ON
c::::::J OFF
c::::::J OFF
IZZZ2I ON
c::::::J OFF
c::::::J OFF
Figur. 11 Dillp;ay Option Formats
POWER
SUPPLY
OSCILLATOR
BAR Format
0.111'
Vi
The TC826 power-ups in the BAR mode. BAR / DOT is
pulled high internally. This display format is similar to a
thermometer display. All bars/LCD segments, including
zero, below the bar/LCD segment equaling the input signal
level are on. A half-scale input signal, for example, would be
displayed with BAR 0 to BAR 20 on.
11
B. DUAL SUPPLY
Vs .. SV
Figure 10 Exlllrnal Olc;illator Connoc;tion
DOT Format
LCD Display Format
By connecting BAR / DOT to Vs- through a 1 Mn resistor the DOT mode is selected. Only the BAR LCD segment
equaling the input signal is on. The zero segment is on for
zero input.
This mode is useful for moving cursor or 'needle'
applications.
The input signal can be displayed in two formats (Rgure
11). The BAR / DOT input (Pin 58) selects the format. The
TC826 measurement cycle operates indentically for either
mode.
1·96
AID CONVERTER WITH
BAR GRAPH DISPLAY OUTPUT
II
TC826
LCD DISPLAYS
LCD BACKPLANE DRIVER (PIN 14)
Most end products will use a custom LCD display for
final production. Custom LCD displays are low cost and
available from all manufacturers. The TC826 interfaces to
non-multiplexed LCD displays. A backplane driver is included
on chip.
To speed initial evaluation and prototype work a standard TC826 LCD display is available from Varitronix.
Additional drive electronics is not required to interface
the TC826 to an LCD display. The TC826 has an on-chip
backplane generator and driver. The backplane frequency
is:
FBP = FOSC/256
Varitronix Ltd.
9/F Linen House, 61-63, King Yip Street
Kwun Tjong, Hong Kong
Telex: 36643 VTRAX HX
Figure 12 gives typical backplane driver rise/fall time v.
backplane capacitance.
10
9
"'8
5
I
TA = 25°C
Vs =9V
j
~ 7
USA Office:
VL Electronics Inc.
3161 Los Feliz Blvd., Suite 303
Los Angeles, CA 90039
Tel: 213/661-8883
Telex: 821554
~6
w
~
5
::l
4
'"
/
!:!:3
w
~2
• Part No.: VBG412-1 (Pin Connectors)
• Part No.: VBG412-2 (Elastomer Connectors)
1
o
Other standard LCD displays suitable for development
work are available in both linear and circular formats. One
manufacturer is:
II
V
/
V
L
1 2 3 4 5 6 7 8 0 10
BACKPLANE CAPACITANCE (X lOOp!)
Figure 12 Backplane Driver Rise/Fall Time vs. Capacitance
FLAT PACKAGE SOCKET
UCE Inc.
24 Fitch Street
Norwalk, CT 06855
Tel: 2031838-7509
Sockets suitable for prototype work are available. A
USA source is:
Nepenthe Distribution
2471 East Bayshore, Suite 520
Palo Alto, CA 94303
Tel: 415/856-9332
Telex: 910/373-2060
• Part No. 5040: 50 segment circular display with
3 didgit numeric scale.
• Part No. 5020: 50 segment linear display.
'BO' Socket Part No.: ICS1-064-042 BO
1-97
NOTES
1-98
"~TELEDYNE
COMPONENTS
TC835
PERSONAL COMPUTER DATA ACQUISITION ADC
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Guaranteed 200 kHz Operation
Guaranteed Zero Reading for OV Input
Input Sensitivity ............................................. 100 IlV
Multiplexed BCD Data Output
No Sample and Hold Required
UART and Microprocessor Interface
Blinking Display Indicates Overrange
Control Outputs for Auto-Ranging
Available in PLCC and Surface-Mount Packages
Low-Power CMOS Technology
Pin Compatible With TC7135, ICL7135, MAX7135
and SI7135
Single 5V Operation With TC7660
DC-to-DC Converter
Extended Temperature Range
Operation •...••••••..•..•••..•••..••.•...•.•...••.. -40°C to +85°C
•
•
•
•
•
Personal Computer Data Acquisition
Scales
Panel Meters
Digital Pressure Meters
Chemical Concentration
Temperature
Process Variable Measurement
-Flow Rate
- Temperature
-Speed
- Concentration
Electrostatic Field Measurement
Voltage, Resistance, Current Measurements
Light Intensity
Toxic Level Measurement
HP-IL Bus Instrumentation
TYPICAL APPLICATION
ADDRESS BUS
-----.1 I
+5V
V+ REF
CAP
BUF
PAO
PA1
PA2
1Y
2Y
3Y
157
6522
·VIA-
AZ
POL
OR
INTI----'
UR
05
B8 TC835
B4
+INPUT _ .....-'\/"".....<
B2
..,,,
1B
2B
3B
SEL
1A
2A
3A
VR
-INPUT
ANALOG
COMMON
GAIN SELECTION
'IN
CHANNEL SELECTION
1095-1
+15V -15V
CHANNEL 1
CHANNEL 2
CHANNEL 3
PA3
PA4
PAS
PA6
PA7
CA1
CA2
PBS
PB4
PB3
GAIN: 10, 20,50,100
.....,'''''\~
1-99
REF
VOLTAGE
CHANNEL 4
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
PIN CONFIGURATIONS
UNDERRANGE
OVERRANGE
STROBE
RUNIHOLD
DIGTALGND
REF CAP-
31 RUNIHOLD
POLARITY
"'f-
CLOCK IN
TCB35CPI
TC835EJI
TCB35EPI
BUSY
01 (LSD)
D2
BUFFOUT 4
REF CAP- 5
"'f-
REFCAP+ 6
TC835CKW
TCB35EKW
-INPUT 7
D3
(MSD)D5
D4
(LSB)B1
B8(MSD)
NC
B4
NC
B2
25 RUNIHOLD
BUFF OUT 6
2
DIGITALGND
2
CLOCK IN
REFCAP+
REF CAP- 7
REFCAP+ 8
SUB
NC
REF CAPBUFF OUT
NC
AZIN
NC
~~~~~n7~Tr-~~~~~~~~~~INTOUT
NC = NO INTERNAL CONNECTION
1-100
U
(.)
0
(.)
(J
W W
Z
Z
Z
Z
Z
"
"
:i ~
~
~ ~
!5
-
PERSONAL COMPUTER
II
DATA ACQUISITION ADC
TC835
GENERAL DESCRIPTION
ORDERING INFORMATION
The TC835 is a low-power. 4-1/2 digit (0.005% resolution). BCD analog-to-digital converter (ADC) that has been
characterized for 200 kHz clock rate operation. The five
conversions per second rate is nearly twice as fast as the
ICL7135 or TC7135.
The multiplexed BCD data output is perfect for interfacing to personal computers. The lOW-COst. greater than 14bit high-resolution. and 100 !LV sensitivity makes the TC835
the most cost-effective data converter available today.
The TC835 (like the TC7135) does not use the extemal
diode-resistor roll-over error compensation circuits required
by the ICL7135. This improves circuit density and simplifies circuit board layout.
The device incorporates "integrator output zero" and
"auto-zero" phases on each conversion cycle. guaranteeing a stable zero output for OV input. even when operated
at the higher clock rate.
Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE outputs. along with
the RUN/HOLD input of the TC835. The overrange. underrange. busy. and run/hold control functions and multiplexed
BCD data outputs make the TC835 the ideal converter for
!LP-based scales and measurement systems and intelligent panel meters. (See Application Notes 16 and 17 for
microprocessor interface techniques.)
The TC835 interfaces with full-function LCD and LED
display decoder/drivers (TC7211A or TC7212A). The
UNDERRANGE and OVER RANGE outputs may be used
to implement an auto-ranging scheme or special display
functions.
This device is pin compatible with. and incorporates all
the features of. the popular TC7135 and ICL7135. The
performance of existing designs may be upgraded to faster
conversion rates by lowering the value of the integrating
capacitor and increasing the clock frequency (see "Component Selection").
1-101
Part No.
TC83SCPI
TC83SCKW
TC83SCLI
TC83SCBQ
TC83SEJI
TC83SEPI
TC835EKW
TC835ELI
Package
Temperature
Range
28-Pin Plastic
44-Pin Flat
28-Pin PLCC
50-Pin Flat
28-Pin CerDIP
28-Pin Plastic
44-Pin Flat
28-Pin PLCC
O·Cto+70·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70·C
-40·C to +8S·C
-40·C to +8S·C
-40·C to +8S·C
-40·C to +8S·C
NOTE: Tape and reel available for 44-pin flal and 28-pin PLCC
packages.
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
ABSOLUTE MAXIMUM RATINGS (Note 1)
Package Power Dissipation
CerDIP (J) .............................................................. 1W
Plastic (P) ;.......................................................... 0.8W
Positive Supply Voltage .............................................. +6V
Negative Supply Voltage .............................................. -9V
AnalOg Input Voltage (Pin 9 or 10) ......... V+ to V- (Note 2)
Reference Input Voltage (Pin 2) ........................... V+ to VClock Input Voltage .............................................. OV to V+
Operating Temperature Range .................... O°C to +70°C
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reiiability.
ELECTRICAL CHARACTERISTICS: TA = +25°C, hOCK = 200 kHz, V+ = +5V, V- =-5V
Parameter
Test Conditions
Display Reading With
Zero Volt Input
Notes 3 and 4
TCz
Zero Reading
Temperature Coefficient
TCFS
Symbol
Min
Typ
Max
Unit
-0.0000
to.oooo
+0.0000
VIN= OV
Note 5
-
0.5
2
IlV/·C
Full-Scale
Temperature Coefficient
VIN=2V
Notes 5 and 6
-
-
5
ppm/·C
NL
Nonlinearity Error
Note 7
-
0.5
1
Count
DNL
Differential Linearity Error
Note 7
-
0.01
-
Display Reading in
Ratiometric Operation
VIN = VREF
Note 3
+0.9997
+0.9998
+1.0000
± Full-Scale Symmetry
Error (Roll-Over Error)
-VIN = +VIN
Note 8
-
0.5
1
liN
Input Leakage Current
Note 4
eN
Noise
Peak-to-Peak Value Not
Exceeded 95% of Time
Analog
±FSE
Display
Reading
LSB
Display
Reading
Count
-
1
10
pA
-
15
-
IlVp.p
Digital
III
Input Low Current
VIN = OV
IIH
Input High Current
VIN= +5V
VOL
Output Low VoHage
VOH
Output High VoHage
B1, B 2, B4, Ba, 01-05
Busy, Polarity, OVerrange,
Underrange, Strobe
Clock Frequency
Note 10
felK
-
10
100
0.08
10
IOl= 1.6 mA
-
0.2
0.4
IOH=lmA
IOH= lOIlA
2.4
4.9
4.4
4.99
5
5
0
200
1200
Il A
IlA
V
V
V
kHz
Power Supply
V+
Pos~ive Supply Voltage
4
5
6
V
V-
Negative Supply VoHage
-3
-5
-8
V
1+
Positive Supply Current
felK = 0 Hz
-
1
3
mA
I
Negative Supply Current
felK= 0 Hz
-
0.7
3
mA
PO
Power Dissipation
felK = 0 Hz
-
8.5
30
mW
NOTES:
1. Functional operation is not implied.
2. Limit input current to undar 100 I1A if input voltages exceed supply
voltage.
3. Full-scale voltage = 2V.
4. VIN= OV.
5. O·C s; TA s; +70·C.
6. Extemal reference temperature coefficient less than 0.Q1 ppml"C.
1-102
7. -2V s; VIN s; +2V. Error of reading from best fit straight
line.
a. IVINI = 1.9959.
9. Test circuit shown in Figure 1.
10. Specification related to clock frequency range over which
the TCa35 correctly performs its various functions.
Increased errors result at higher operating frequencies.
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
Figure 1
Test Circuit
V+
REF
IN
ANALOG
0 - -...-
COM
.....--+--'
SW,
~~~¥ O-.....-~Nv--......--+---t
-IN
~.---__- - - - - - - '
Figure 3C
Figure 2
o SWITCH OPEN
•
SWITCH CLOSED
Input Signal Integration Phase
ANALOO
Digital Logic Input
INPUT BUFF
+IN
REF
IN
-IN
Figure 3D
Figure 3A
Analog Circuit Function Diagram
1-103
o
SWITCH OPEN
•
swrrCH CLOSED
Reference Voltage Integration Cycle
•
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated; or averaged, to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
(See Figure 4.)
ANALOQ
INPUT BUFF
+IN
REF
IN
TC83S Operational Theory
-IN
Figure 3E
o
SWITCH OPEN
•
swrrCH CLoseD
The TCB35 incorporates a system zero phase and
integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
The TCB35 measurement cycle contains four phases:
Integrator Output Zero Phase
GENERAL THEORY OF OPERATION
(1) System zero
Dual·Slope Conversion Principles
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
The TCB35 is a dual-slope, integrating analog-to-digital
converter. An understanding of the dual-slope conversion
technique will aid in following the detailed TCB35 operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
Intemal analog gate status for each phase is shown in
Table I.
C
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period. Time is measured by counting clock pulses. An
opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC
f
tSI
0
VIN(t) dt
=
REF
VOLTAGE
POLARITY CONTROL
VR tAl
RC
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
For a constant VIN:
Figure 4
VIN=VR [ -tRI ] .
tSI
1-104
Basic Dual-Slope Converter
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
Table I. Internal Analog Gate Status
Conversion
Cycle Phase
System Zero
Input Signal
Integration
Reference Voltage
Integration
Integrator
Output Zero
SWI
SW~I
Internal Analog Gate Status
SWz
SWR
SWRI
SW1
Closed
Closed
3A
38
Closed
3C
Closed
SWIZ
Reference
Schematic
Closed
Closed'
Closed
Closed
3D
'NOTE: Assumes a positive polarity input signal. SWAI would be closed for a negative input signal.
System Zero (Figure 3B)
During this phase, errors due to buffer, integrator, and
~omparator offset voltages are compensated for by chargIng CAZ (auto-zero capacitor) with a compensating error
voltage. With a zero input voltage the integrator output will
remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to ANALOG COMMON. The
reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the
integrator and comparator, charges the CAzcapacitor with a
voltage to compensate for buffer amplifier, integrator, and
comparator offset voltages.
Analog Input Signal Integration (Figure 3C)
The TC835 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage must
be within the device common-mode range; -1 V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase.
Reference Voltage Integration (Figure 3D)
The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output
back to zero. The digital reading displayed is:
Reading
=10,000
[ Differentiallnput~ .
VREF
J
Integrator Output iero (Figure 3E)
This phase guarantees the integrator output is at OV
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
condition exists, the phase is extended to 6200 clock cycles.
Analog Section Functional Description
Differential Inputs
(+INPUT, Pin 10 and -INPUT, Pin 9)
The TC835 operates with differential voltages within the
input amplifier common-mode range. The input amplifier
common-mode range extends from 0.5V below the positive
supply to lV above the negative supply. Within this common-mode voltage range, an 86 dB common-mode rejection ratio is typical.
The integrator output also follows the common-mode
voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a
large positive common-mode voltage with a near full-scale
~egati~e differ~ntial input voltage is applied. The negative
Input Signal drives the integrator positive when most of its
swing has been used up by the positive common-mode
Voltage. For these critical applications the integrator swing
can be reduced to less than the recommended 4V full-scale
swing, with some loss of accuracy. The integrator output can
swing within 0.3V of either supply without loss of linearity.
ANALOG COMMON Input (Pin 3)
ANALOG COMMON is used as the -INPUT return
during auto-zero and deintegrate. If-INPUT is differentfrorn
ANALOG COMMON, a common-mode voltage exists in the
system. This signal is rejected by the excellent CMRR of the
converter. In most applications, -INPUT will be set at a fixed,
kno~n v,oltage (power supply common, for instance). In this
appllcallon, ANALOG COMMON should be tied to the same
point, thus removing the common-mode voltage from the
converter. The reference voltage is referenced to ANALOG
COMMON.
REFERENCE Voltage Input (REF IN, Pin 2)
The REF IN input must be a positive voltage with respect
to ANALOG COMMON. Two reference voltage circuits are
shown in Figure 5.
1-105
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
~------------.-~y+
y+
REF
~~
IN
TC835
C~:~~ 1---....--..
~IZ
DIGITAL CLOCK
GND
~------------.-~y+
HOI,.D
Figure 6
6.8 k.Q
y+
OYERRANGE
RUW
IN
UNDERRANGE
, BUSY
Digital Section Functional Diagram
~~
~~ R~~
TC835
TCD4
INTEGRATOR
OUTPUT
UY REF
SIGNAL
SYSTEM IINTE
REFERENC~
f~~'?' c1:fuO~
INr:oG~TE
---_....,
COUNTS (FIXED)
COUNTS (MAX)
..... FULL MEASUREMENT CYCLE
40,002 COUNTS
ANALOG
GROUND
Figure 5
BUSY
OVERRANGE
WHEN 'l'//////////.,-I
APPLICABLE ~
Using an External Reference
UNDERRANGE ~
WHEN -'l'////,I
APPLICABLE ,~~.....- -..
EXPANDED SCALE
BELOW
Digital Section Functional Description
L
I
The major digital subsystems within the TC835 are
illustrated in Figure 6, with timing relationships shown in
Figure 7. The multiplexed BC D output data can be displayed
on LCD or LED display with the TC7211A (LCD) orTC7212A
(LED) 4-digit display drivers.
The digital section is best described through a discussion of the control Signals and data outputs.
DIGITSCAN
n.......Il..-J1 05
..rL-..S'1..-l' 04
....Il-n-.J1.. 03
--"---ll..-ID2
I
.
- - " - - - - " - 01
FIRST 05 OF SYSTEM ZERO
C010UON1TS
AND REFERENCE INTEGRATE
STROBE '\'j*lj*lj...j ...j,...._ _ _ _.;:O:;.::N;.E;.CO::;U;:;NT;,:,.::.LO::;N.:;;G;::E;.;R.:...._
I
RUN/HOLD tnput (Pin 25)
When left open, this pin assumes a logic "1" level. With
a R/H = 1, the TC835 performs conversions continuously,
with a new measurement cycle beginning every 40,002
clock pulses.
When R/H changes to a logic "0," the measurement
cycle in progress will be completed, and data held and
displayed as long as the logic "0" condition exists.
A positive pulse (>300 ns) at R/H initiates a new measurement cycle. The measurement cycle in progress when
R/H initially assumed the logic "0" state must be completed
before the positive pulse can be recognized as a single
conversion run command.
DIGITS~~~
SIGNAL
1- . AUTO ZERO
INTEGRATE
n-.;D_5_ _ _ _ _
o{l,f-__
~
OVERRANGE
In_~~-----~lf-----~
-J1_D~3
Figure 7
1-106
_____
~l~I
_____
~~
TIming Diagrams for Outputs
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
The new measurement cycle begins with a 10,001count auto-zero phase. At the end of this phase the busy
signal goes high.
TC83S
OUTPUlS
BUSY ~ENO OF CONVERSION
7-il---------------------------------
STROBE Output (Pin 26)
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur in the
center of the digit drive signals (0" 02, 03, Os, Figure 8).
Os (MSO) goes high for 201 counts when the measurement cycles end. In the center of the Os pulse, 101 clock
pulses after the end of the measurement cycle, the first
STROBE occurs for one-half clock pulse. After the Os digit
strobe, 04 goes high for 200 clock pulses. The STROBE
goes low 100 clock pulses after 04 goes high. This continues
through the 0, digit drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
The active low STROBE pulses aid BCD data transferto
UARTs, processors and external latches. (See Application
Note 16.)
BUSY Output (Pin 21)
At the beginning of the signal-integration phase, BUSY
goes high and remains high until the first clock pulse afterthe
integrator zero crossing. BUSY returns to the logic "0" state
after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first
clock pulse after BUSY, and are latched at the clock pulse
end. The BUSY Signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
cycle.
OVERRANGE Output (Pin 27)
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE
output is set to a logic "1." The overrange output register is
set when BUSY goes low, and is reset althe beginning olthe
next reference-integration phase.
UNDERRANGE Output (Pin 28)
If the output count is 9% of full scale or less (!>1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low althe next signal-integration phase.
STROBE
---..."r----..----......---...,'......--....r---------
os
~------~c::::J~----------------------COUNlS
---Jc::-Jt...___________________
D3 __________
COUN.lS
~----------------~c::::J..-----------COUNTS
D'----------~~~------
COUNlS
"DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
Figure 8
Strobe Signal Pulses Low Five Times per Conversion
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal polarity
determined correctly. This is useful in null applications.
DIGIT Drive Outputs (Pins 12, 17, 18, 19 and 20)
Oigit drive signals are positive-going signals. The scan
sequence is Os to 0,. All positive pulses are 200 clock pulses
wide, except Os, which is 201 clock pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated. This provides a blinking visual display indication.
BCD Data Outputs (Pins 13, 14,15 and 16)
The binary coded decimal (BCD) bits Ba, B4, B2, B" are
positive-true logic signals. The data bits become active
simultaneously with the digit drive signals. In an overrange
condition, all data bits are at a logic "0" state.
POLARITY Output (Pin 23)
A positive input is registered by a logic "1" polarity signal.
The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next
conversion.
1-107
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
APPUCATIONS INFORMATION
Component Value Selection
The integrating resistor is determined by the full-scale
input voltage and the output current of the buffer used to
charge the integrator capacitor. Both the buffer amplifier and
the integrator have a class A output stage, with 100 IJA of
quiescent current. A 20 IJA drive current gives negligible
linearity errors. Values of 5 IJA to 40 IJA give good results.
The exact value of an integrating resistor for a 20 IJA current
is easily calculated.
Manufacturer
Part Type
TC04A
TC8069
Teledyne Components
Conversion Timing
R
_ full-scale voltage
INT20 IJA
Line Frequency Rejection
A signal integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 200 kHz clock frequency will reject 60 Hz and 400 Hz
noise. This corresponds to five readings per second.
Integrating Capacitor
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that ensures
the tolerance build-up will not saturate the integrator swing
(approximately 0.3V from either supply). For ±5V supplies
and ANALOG COMMON tied to supply ground, a ±3.5V to
±4Vfull-scale integrator swing isadequate. A 0.1 0 ILFto 0.47
ILF is recommended. In general, the value of CINT is given by:
CINT
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference be
used where high-accuracy absolute measurements are
being made. Suitable references are:
Conversion Rate vs Clock Frequency
[10,000 x clock period) x liNT
Integrator output voltage swing
(10,000) (clock period) (20 IJA)
Integrator output voltage swing
A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent rollover
or ratiometric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference. This
ratiometric condition should read half-scale 0.9999. any
deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable
cost. Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor has some influence
on the noise of the system. A large capacitor reduces the
noise. The reference capacitor should be large enough such
that stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference capacitor and
auto-zero capacitor are only important at power-on, or when
the circuit is recovering from an overload. Smaller or cheaper
capacitors can be used if accurate readings are not required
for the first few seconds of recovery.
Reference Voltage
The analog input required to generate a full-scale output
is VIN = 2 VREF.
1-108
Oscillator Frequency
(kHz)
Conversion Rate
(Conv/Sec)
100
120
200
300
400
800
1200
2.5
3
5
7.5
10
20
30
Line Frequency Rejection
60 Hz
50 Hz
400 Hz
Oscillator Frequency
(kHz)
50.000
53.333
66.667
80.000
83.333
100.000
125.000
133.333
166.667
200.000
250.000
The conversion rate is easily calculated:
Conversi?n Rate
(Readings 1/sec)
=
Clock Frequency (Hz)
4000
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
Power Supplies and Grounds
Power Supplies
The TC835 is designed to work from ±5V supplies. For
single +5V operation, a TC7660 can provide a -5V supply.
Grounding
Systems should use separate digital and analog ground
systems to avoid loss of accuracy.
Displays and Driver Circuits
Teledyne Components manufactures two display decoder/driver circuitsto interface the TC835 to an LCD or LED
display. Each drive has 28 outputs for driving four 7-segment
digit displays.
Device
Package
Description
TC7211AIPL
40-Pin Epoxy
4-Digit LCD Driver/Decoder
TC7212AIPL
40-Pin Epoxy
4-Digit LED DriverlDecoder
Several sources exist for LCD and LED display:
Display
Type
Manufacturer
Address
Hewlett Packard
Components
640 Page Mill Rd.
Palo Alto, CA 94304
LED
Litronix, Inc.
19000 Homestead Rd.
Cupertino, CA 94010
LED
AND
770 Airport Blvd.
Burlingame, CA 94010
LCD and
LED
Epson America, Inc.
3415 Kanhi Kawa SI.
Torrence, CA 90505
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator need
not be a limitation. Since the nonlinearity and noise do not
increase substantially with frequency, clock rates of up to
-1 MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be a
constant and can be subtracted out digitally.
The clock frequency may be extended above 200 kHz
without this error, however, by using a low-value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage on to the
integrator output at the beginning of the reference integrate
phase. By careful selection of the ratio between this resistor
and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by
approximately a factor of 3. At higher frequencies, ringing
and second-order breaks will cause significant nonlinearities
in the first few counts of the instrument.
The minimum clock frequency is established by leakage
on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no
measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.
Zero-Crossing Flip-Flop
LCD
High-Speed Operation
The maximum conversion rate of most dual-slope AID
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the integrator ramp with a 31J-S delay, and at a clock frequency of
200 kHz (5 IJ-S period), half of the first reference integrate
clock period is lost in delay. This means that the meter
reading will change from Oto 1 with a50l1Vinput, 1 t02 with
150 I1V, 2 to 3 at 250 I1V, etc. This transition at mid-point is
considered desirable by most users; however, if the clock
frequency is increased appreciably above 200 kHz, the
instrument will flash "1" on noise peaks even when the input
is shorted.
The flip-flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half-clockpulse have died down. False zero-crossingscaused
by clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flipflop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zero gives an overload display of 0000 instead of 0001.
No delay occurs during signal integrate, sothat true ratiometric
readings result.
1-109
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
TYPICAL APPLICATION DIAGRAMS
RC Oscillator Circuit
Comparator Clock Circuits
+SV
R2
R1
~fct?l'o
-
-
16kn
--
O.2211F
GATES ARE 74C04
16kn
1. fo =
1
, Rp = R1 R2
2 C(0.41 Rp + 0.7 R1)
R1 + R2
a. If R1 = R2 = R1, f;: 0.55/RC
+SV
b. If R2 » R1, f;: 0.45/R1C
C.
2.
R2
100kn
If R2» R1, f;: 0.721R1C
R4
2kn
Examples:
a. f = 120 kHz, C = 420 pF
R2
100kn
R1 = R2 ~ 10.9 kn
1>----+--OVOUT
R3
b. f = 120 kHz, C = 420 pF, R2 = 50 kn
R1 =8.93 kn
SOkn
c. f = 120 kHz, C = 220 pF, R2 = 5 kn
R1 =27.3 kn
,.,10
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
TYPICAL APPLICATIONS DIAGRAMS (Cont.)
4-1/2 Digit ADC With Multiplexed Common Anode LED Display
+5V
20
19
18
01 D2 03
r----4-'i INT OUT
17
04
12
05
O.3311 F
AZIN
100 110
200 kH~
100 110
POL
6 BUFF
OUT
22
10
fiN
+INPUT
"''''
TC835
1 IIF 9
-INPUT
3 ANALOG
COMMON
23
4.7 kfi
REF 7
CAP""
REF 8
CAP+
BLANK MSO ON ZERO
16
15
B4 14
B2
13
B1
6
2
1
7
B8
"''''
TC04
1-111
0
C
B
A
RBI
7447
16
+5V
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
TYPICAL APPLICATIONS DIAGRAMS (Cont.)
4-112 Digit ADC Interfaced to LCD With Digit Blanking on Overrange
4-112 DIGIT lCO
SEGMENT
DRIVE
112C04030
-5V
23
1
v4
POL
01
INTOUT
02
AZIN
03
BUFF OUT
04
lj1F
6
20
01
19
200 kHz
'IN
",r-
B8
TC835
1001<0
+INPUT
B2
Bl
05
3 ANALOG
COMMON
33
17
34
IL ____________
B4
+
32
18
100 kD.
22
...''''--''''------'''
...
C04081
I
STROBE
OR
16
30
15
29
14
28
13
12
27
!.., ........ -----"'--
27
0
Q
112
C04013
ClK
26
+5V
1/4 C04030
+5V
1-112
03
04
",r-
C04071
I
02
TC7211A
B3
B2
v+
Bl
GNO
BO
e"'tl
~
~m
g"r
»~
»0
OZ
0»
l>
""
r:
o
4-112 Digit ADC with Multiplexed Common Cathode LED Display
+5Y
+5Y
/'t-S
~6.8Y
>
~ .....
Teo
1
t----
Y
~
-:~ 10~
>
2;'"
kn ~
UR
1 Y2
REFIN
D33 F-'- 1 "F
4
. ""1=-H-.2
~
OR
- - 26
STROBE F
AZIN
_>
oo~
m~
S
...L 100kn 7 REFCAp.
-,-1 "F
8
T~
-'-0.1
"F
ClKIN
REF CAP-
9 -INPUT
10
~
21
~
l
~ S
: !~»>•
••
9
~
J\
,/\
8
r!-ft4-
12
...A::
-vvv
AA
...A:
TC83S
B1 (LSB)
B2
.J\
A
,/\
vvv
0:xJ
-1
en
m
'0
o
fa.
-
4
I,l
16
2
17
r--
181
rl
-+-___+-_
-.
I ....... -
D4 t 1
::..:7
Zc:
r-
15
'VVV
D3 18
»-1
em
l>
3:
::VV 13 CD4S13
v
14
BE
5
...A
D2 19
U)
Q
::D
>kn
roY' .....Y' ,....r' ,..r' ,....y'
"I I 'J. I ') I "'"'l
~s::
0"tJ
c
t-
.>
; "'"'l
~
);
I--
(LSD)Ol 20
.--_...!1~2 05 (MSO)
~
+' aD 8 8 8:=-
<:>!-7
~ rh
-0
~O
o
z
t----
BUSY!-=-!
.INPUT
11
".....
+5Y0..!2 y+
.-----E
vvv
.l-Vl'v
OGNO 24
POLARITY
J\AA
~
,
1500 '--,-
RUNM-O-LO~
~ 6 g~F
;;;
~
~
' - - _......._~3 ANALOG
ANALOG
GND
GND
~
I
c ...
I"'-
+1
,Y
~
......
T
m
B4tl~6it-----t------------------~+J
(MSB)B8t,l:..:5,-----t--------------------iJ
OSC
-I
o
~
en
PERSONAL COMPUTER
DATA ACQUISITION ADC
TC835
TYPICAL APPLICATIONS DIAGRAMS (Cont.)
Negative Supply Voltage Generator
+5V
v+
11
8
v..,~
TC835
1
(~V)
5
""1
-=
24J.-
10114
..,~
TC7660
4ycJ 213
10llF
-=
"'f'TELEDYNE
COMPONENTS
TC71 osn1 OSA
TC7107n107A
3..1/2 DIGIT AID CONVERTER
FEATURES
•
•
•
•
•
•
Internal Referenc;e with
Low Temperature Drift ...•........•... 20 ppml°C Typic;al
50 ppml°C Maximum
Drives LCD (TC71 06) or LED (TC7107) Display
Ditec;tly
Guaranteed Zero Reading With Zero Input
Low Noise for Stable Display
Auto-Zero Cyc;le Eliminates Need for Zero
Adjustment
•
•
•
•
•
True Polarity Indic;ation for Prec;ision Null
Applic;ations
Convenient 9 V Battery Operation (TC7106A)
High Impedanc;e CMOS Differential Inputs .... 10'20
Differential Referenc;e Inputs Simplify Ratiometric;
Measurements
Low Power Operation ..................................... 10 mW
Available In 6O-Pin Plastic; Flat Pac;kage
0.1 pi'
34
1 MIl
31
V~
A"f'rJp?H 0.01 pi'
30 YiN
AtjALOG
..,....
COMMON
28
TC7106A
VeuFF
47 kll
TOANAl..OG
COMMON (PIN 32)
39
3 CONVERSION$lSEC
200 mV FU~L SCAI..E
100 kll
4350 ILL F01
Figllro 1 TC7106A Typie !!l ~
~
0
..
~
~ m
Z
It;
!E
...w
a:
a:
...9 ...w ...w
:Ii
II! If If 8
:I! 9
iiE
!!
II:
~ iii
Ii
>
REFLO
NC
CAEF
O2
ChEF
C3
~
COMMON
A.
C2
IN HI
G.
"'t-
NC
e,
...,
.,t-
NC
TC7106ACLW
Tt7107ACLW
(PLCC)
INLO
F2
BP/OND
TC7106ACKW
TC7107ACKW
(FLAT PACKAClE)
POL
All
AB4
BUFF
E3
E2
INT
C,
F.
0,
V-
B,
B3
.r
,['
,g J
C
6 !i!
Go
Q
z
~
..
"
~
J'
.r .r ,;
N
"
~
8 rr·,r
~
oJ:'
~
8
'"
4350 ILL F03
1-111
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC7107n107A
PIN CONFIGURATIONS (Cont.)
-'NT
VeUFF
NO
OAt
NO
SUB
SUB
NO
NO
COMMoN
CfiEF
O~EF
VREF
NOTES:
1. Ne _ NO IN"tI:~NAL CONNECtiON
2. PINS I, 23, 3. ANO 53 ARE CONNEctED to tHE DIE SUBSTRATE. THE
POTI:NllAL AT THESE PINS IS APPROXIMATELY Y+. NO EXTERNAL
NOTES;
1. Ne • NO INTERNAL CONNECTION
2. PINS 8,23, 3. AND 53 ARE CONNECTeD TO THE
OIi:SUI3STRATE. 'tHE
POTENTlAL ATTHESE PINS IS APPROXIMATELY Y·. NO ErtERNAL
CONNEC11ONS SHOULD BE MADE.
CONNECTIONS SHOUtJ) BE MADE.
4350 III F04
ABSOLUTE MAXIMUM RATINGS·
TC7106A
TC1107A
Supply Voltage (V+ to V-) ........................................... 15 V
Analog Input Voltage (either input) (Note 1) ......... V+ to VReference Input Voltage (either input) .................. V+ to VClock Input ......................................................... Test to V+
Power Dissipation (Note 2)
CerDIP Package .......................................... 1000 mW
Plastic Package ............................................. SOO mW
Operating Temperature
"C" Devices ............................................ O°C to +70°C
"I" Devices .......................................... -25°C to +85°C
Storage Temperature ............................. --65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................... 300°C
Supply Voltage
V+ ........................................................................ +6 V
V- ........................................................................ -9 V
Analog Input Voltage (either input) (Note 1) ......... V+ to VReference Input Voltage (either input) .................. V+ to VClock Input ....................................................... GND to V+
Power Dissipation (Note 2)
CerDIP PAckage ......................................... 1000 mW
Plastic Package ............................................. 800 mW
Operating Temperature
"C" Devices ............................................ O°C to +70°C
"I" Devices .......................................... -25°C to +S5°C
Storage Temperature ............................. --65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................... 300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
1-118
3 1/2 DIGIT AID CONVERTER
TC71 OSn1 06A
TC71 07n1 07A
ELECtRICAL CHARACTERISTICS
(Note 3)
Min
TC811
Typ
Max
VIN= 0.0 V
Full-Scale = 200.0 mV
-000.0
±ooo.o
+000.0
VIN= VREF
VREF= 100 mV
-VIN = +VIN:; 200 mV
999
999/1000
1000
-1
±0.2
+1
Digital
Reading
Digital
Reading
Counts
Full-Scale = 200 mV
or Full-Scale = 2.000 V
VCM =±1V, VIN= OV,
Full Scale = 200.0 mV
VIN= OV
Full-Scale = 200.0 mV
-1
±0.2
+1
Counts
-
50
-
fl VN
-
15
-
flY
Characteristics
Conditions
Zero Input Reading
Ratiometric Reading
Roll-Over Error (Difference in
Reading for E:qual Positive and
Negative Reading Near Full-Scale)
Linearity (Max. Deviation From
Best Straight Line fOit)
Common-Mode
Rejection Ratio (Note 4)
Noise (Pk - Pk Value Not
Exceeded 95% of Time)
Leakage Current @ Input
Zero Reading DrHt
Scale Factor
Temperature Coefficient
VIN= OV
VIN= OV
"C' Device = O·C to 70°C
VIN=OV
"I" Device = -25°C to +85°C
VIN = 199.0 mV,
"C" Device = O°C to 70°C
(Ext. Ref = 0 ppmOC)
VIN" 199.0 mV
"I" Device = -25°C to +85°C
Unit
-
1
10
pA
0.2
1
flV/oC
-
1.0
2
flVloC
-
1
5
ppml°C
-
-
20
ppml°C
-
0.8
1.8
mA
Supply Current (Does Not
VIN=O
Include LE:D Current fOor TC71 07A)
25k.Q Between Common
Analog Common Vo~age
2.7
3.05
3.35
V
and Pos. Supply
(With Respect to Pos. Supply)
25k.Q Between Common
Temp. Coell. of
and Pos. Supply
Analog Common
(With Respect
O°C ~ TA ~ 70·C
20
50
ppml°C
to Pos. Supply)
''Co" Industrial Temp. Range Devices
25k.Q Between Common
Temp. Coell. of
and Pos. Supply
Analog Common
(With Respect
ppml·C
O°C ~ TA S 85°C
75
to Pos. Supply)
"I," Industrial Temp. Range Devices
V+to V-= 9 V
TC710BA ONLY Pk - Pk
4
5
6
V
Segment Drive Voltage (Note 5)
V+to V-= 9 V
TC7106A ONLY Pk - Pk
4
5
6
V
Backplane Drive Voltage (Note 5)
8.0
TC7107AONLY
v+" 5.0V
5
mA
Segment Sinking Current (Except Pin 19)
Segment Vo~age = 3 V
V+= 5.0 V
TC71 07A ONLY
16
10
mA
Segment Voltage = 3 V
Segment Sinking Current (Pin 19)
.
.
NOTES: 1. Input voltages may exceed the supply voltages provided the Input current IS limited to ±100 !lA.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, speCifications apply to both the TC7106A and TC7107A at TA s 25°, 'CLOCK" 48 kHz. TC7106A is tested in the
circuit of Figure 1. TC71 07 A is tested in the circuit of Figura 2.
4. Refer to "Differentiallnpuf' discussion.
S. Backplane drive is in phase with segment drive for "off" segment, 180° out of phase for ·on" segment. Frequency is 20 times conversion
rate. Average DC component is less than 50 mY.
-
-
-
-
-
1-119
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC71 07n1 07A
PIN DESCRIPTION
40-Pin DIP
Pin Number
(Normal)
(Reverse)
60-Pin
Flat Package
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
13
14
15
16
17
18
19
20
21
25
26
27
28
29
30
31
32
33
34
35
36
22
23
24
25
26
27
(19)
(18)
(17)
(16)
(15)
(14)
37
40
41
43
45
46
VINT
28
(13)
47
VBUFF
29
(12)
49
CAZ
30
31
32
(11)
(10)
(9)
51
55
57
VIN
VfN
Analog
Common
33
(8)
58
CFiEF
Name
V+
D1
C1
61
A1
F1
G1
E1
02
~
62
A2
F2
E2
D3
63
Fa
E3
A6 4
POL
6P
GND
G3
~
C3
G2
V-
Description
Positive supply voltage.
Activates the 0 section of the units display.
Activates the C section of the units display.
Activates the 6 section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the 6 section of the tens display.
Activates the A section of the tens display.
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the 0 section of the hundreds display.
Activates the 6 section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
LCD Backplane drive output (TC7106A).
Digital ground (TC7107A).
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
Integrator output. Connection point for integration capacitor. See
INTEGRATING CAPACITOR section for more details
Integration resistor connection. Use a 47 k.n resistor for a 200 mV!lJIIscale range and a 470 k.n resistor for 2V full-scale range.
The size of the auto-zero capacitor influences system noise. Use a
0.47-I1F capacitor for 200 mV full scale, and a 0.0471lF capacitor for
2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more
details.
The analog low input is connected to this pin.
The analog high input signal is connected to this pin.
This pin is primarily used to set the analog common-mode voHage
for battery operation or in systems where the input signal is
referenced to the power supply. It also acts as a reference voHage
source. See paragraph on ANALOG COMMON for more details.
See pin 34.
1-120
3 1/2 DIGIT AID CONVERTER
TC71 OSn1 OSA
TC7107n107A
PIN DESCRIPTION (Cont.)
(Reverse)
SO-Pin
Flat Package
Pin Number
Name
Description
(7)
59
CREF
35
36
(6)
(5)
60
1
VREF
VREF
37
(4)
3
Test
38
39
40
(3)
(2)
(1)
4
6
10
OSC3
OSC2
OSC1
A O.l-ILF capacitor is used in most applications. If a large commonmode voltage exists (for example, the ViN pin is not at analog
common), and a 200-mV scale is used, a l-IJ.F capacitor is recommended and will hold the roll-ovar error to 0.5 count.
See pin 36.
The analog input required to generate a full-scale output (1999
counts). Place 100 mV between pins 35 and 36 for 199.9 mV
full-scale. Place 1 V between pins 35 and 36 for 2V full scale. See
paragraph on REFERENCE VOLTAGE.
Lamp test. When pulled high (to V+) all segments will be turned on
and the display should read -1888. It may also be used as a negative
supply for externally-generated decimal points. See paragraph under
TEST for additional information.
See pin 40.
See pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48-kHz clock
(3 readings per section), connect pin 40 to the junction of a 100-kn
resistor and a 1OO-pF capacitor. The 100-kn resistor is tied to pin 39
and the 1OO-pF capacitor is tied to pin 38.
4o-Pin DIP
Pin Number
(Normal)
34
General Theory of Operation
Dual Slope Conversion PrinCiples
where:
The TC71 06A and TC71 07A are dual slope, integrating
analog-to-digital converters. An understanding of the dual
slope conversion technique will aid in following the detailed
operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
VA = Reference Voltage
T SI = Signal Integration Time (Fixed)
TAl = Reference Voltage Integration Time (Variable)
For a constant V,N:
TAl
V,N=VA TSI
Input Signal Integration
Reference Voltage Integration (Deintegration)
The input signal being converted is integrated for a fixed
time period (Tsl). Time is measured by counting clock
pulses. An opposite polarity constant reference voltage is
then integrated until the integrator output voltage retums to
zero. The reference integration time is directly proportional
to the input signal (TAl). (Figure 3A).
In a simple dual slope converter a complete conversion
requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage and integration time:
_1_
RC
f
T 51 VIN(t)dt =
o
VATAI
RC
Figure SA Basic Dual Slope Converter
1-121
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC7107n107A
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high noise environment.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
muHiple of the 50/60 Hz power line period. (Figure 3B)
Signal Integrate Cycle
The auto-zero loop in opened, the internal differential
inputs connect to YiN and YiN. The differential input signal is
integrated for a fixed time period. The signal integration
period is 1000 counts. The externally set clock frequency is
divided by four before clocking the internal counters. The
integration time period is:
TSI
30
.v' "
,
,,
If
[,
o
Ii liEASUjEMrTI Piilll
lIT
0.11T
Figure 3B
I
INPUT FREQUENCY
=External Clock Frequency
"the differential input voltage must be within the device
common-mode range (1 V of either supply) when the converter and measured system share the same power supply
common (ground). If the converter and measured system do
not share the same power supply common, YiN should be
tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
lV~
I-- ~
_4_ x 1000
fose
where:
fosc
\)'
=
Reference Integrate Cycle
101T
4350 ILL F06
Normal-Mode Rejection of Dual Slope Converter
Analog Section
In addition to the basic signal integrate and deintegrate
cycles discussed, the circuit incorporates an auto-zero
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without external adjusting
potentiometers. A complete conversion consists of three
cycles: an auto zero, signal integrate and reference integrate cycle.
Auto-Zero Cycle
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening· internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on
CAZ compensates for device offset Voltages. The offset error
referred to the input is less than 10 ~V.
The auto-zero cycle length is 1000 to 3000 counts.
The final phase is reference integrate or de-integrate.
YiN is internally connected to analog common and Vi\iJ is
connected across the previously charged reference capacitor. Circuitry within the chip ensures thatthe capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 counts. The digital reading displayed is:
1000x VVIN
REF
Digital Section (TC7106A)
The TC71 06A (Figure 5) contains all the segment drivers necessary to directly drive a 3 1/2 digit liquid crystal
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane frequency is 60 Hz with a 5 V nominal amplitude. When a
segment driver is in phase with the backplane signal the
segment is "OFF." An out of phase segment drive signal
causes the segment to be "ON" or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment. This insures long LCD display life. The
polarity segment driver is "ON" for negative analog inputs. If
Vi\iJ and YiN are reversed this indicator would reverse.
1-122
Co)
......
i\3
c
C5
=i
~
TYPICAL SEGMENT OUTPUT
--------~------v+
o
o
z
<
m
~
m
LCD DISPLAY
~'"
TC7106A
::D
!!
~
iil
UI
_ ~0
~
;
f
f
tC:~¢
,
hy+
. ·1
____
Vm~ --SI~~~~t;==::::::
INT
26
I.. ~
l
V-
-
40
osc,
39
osc;Rose
......!!
1,
I ..,..,.A
TEST
5000
!!ov-
OSC3
-1-1
00
............
""""""""
00
i
F
?l
~~
............
00
~~
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC71 07n1 07A
On the TC7106A when the test pin is pulled to V+ all
segments are turned "ON." The display reads -1888. During
this mode the LCD segments have a constant DC voltage
impressed. Do not leave the display in this mode for more
than several rninutes. LCD displays may be destroyed if
operated with DC levels for extended periods.
The display FONT and the segment drive assignment
are shown in Figure 6.
•
Signal Integrate: 1000 Counts
(4000 Clock Pulses)
This time period is fixed. The integration period is:
TSI
= 4000
[ fo:c ]
Where fosc is the externally set clock frequency.
•
Reference Integrate: 0 to 2000 Counts
(0 to 8000 Clock Pulses)
DISPLAY FONT
The TC71 06A171 07A are drop in replacements for the
Ol23LfS6789
710617107 parts. External component value changes are
not required to benefit from the low drift internal reference.
rlOOO'ST100'sT10'sTl'sl
Clock Circuit
1--1 8 8 81
Three clocking methods may be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
4350 ILL Fog
Figure 6
Display FONT and Segment Assignment
I
I
I
I
I
I
I
IL _ _ _ _
Digital Section (TC71 07A)
System Timing
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The three phase measurement cycle takes a total of 4000 counts or 16000 clock
pulses. The 4000 count cycle is independent of input signal
magnitude.
Each phase ofthe measurement cycle has the following
length:
Auto-Zero Phase:
1000 to 3000 Counts
(4000 to 12000 Clock Pulses)
For signals less than full-scale the auto-zero phase is
assigned the unused reference integrate time. period.
I
39
I
I
I
38
------.1I
~"
EXT
Figure 7 shows the TC7107A. It is identical to the
TC7106A except that the regulated supply and back plane
drive have been eliminated and the segment drive is typically 8 mAo The 1000 output (pin 19) sinks current frorn two
LED segments, and has a 16 mA drive capability. The
TC7107A is designed to drive common anode LEOs.
In both devices, the polarity indication is "on" for negative analog inputs. If ViN and ViN are reversed, this indication
can be reversed also, if desired.
The display font is the same as the TC71 06A.
•
I
TO
COUNTER
I
In the TC71 06A an internal digital ground is generated
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
capacitive currents when the backplane voltage is switched.
osc
TC7106A
TC7107A
4350 ILL F10
Figure B Clock Circuits
Component Value Selection
Auto-Zero Capacitor - CAZ.
The CAZ capacitor size has some influence on system
noise. A 0.47 JJ.F capacitor is recommended for 200 mV fullscale applications where 1 LSB is 100 JJ.V. A 0.047 JJ.F
capacitor is adequate for 2.0 V full-scale applications. A
mylar iype dielectric capacitor is adequate.
Reference Voltage Capacitor -
CREF
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
cycle is stored on CREF. A 0.1 JJ.F capacitor is acceptable
when ViN is tied to analog common. If a large common-mode
voltage exists (VREF oF- analog common) and the application
requires a 200 mV full-scale increase CREF to 1.0 JJ.F.
Rollover error will be held to less than 0.5 count. A mylar type
dielectric capacitor is adequate.
1-124
....w
i\5
c
C5
=i
~
TYPICAL SEGMENT OUTPUT
,
v+
o
oz
LED DISPLAY
<
m
~
m
II
FROM COMPARATOR OUTPUT
I
~
T
,
'r
'A y+
1
2'1
L......J
DIGITAL
GROUND
40
OSC,
TEST
Rose
Cose
-t-t
!l!l
........
00
i
F
ii
~~
........
00
~~
3 1/2 DIGIT AID CONVERTER
TC71 OSn1 OSA
TC71 07n1 07A
Integrating Capacitor - CINT
Oscillator Components
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Due to the
TC71 06A171 07A superior analog common temperature
coefficient specification, analog common will normally supply the differential voltage reference. For this case a±2 V fullscale integrator output swing is satisfactory. For3 readings/
second (fosc = 48 kHz) a 0.22 f.1F value is suggested. If a
different oscillator frequency is used CINT must be changed
in inverse proportion to maintain the nominal ±2 V integrator
swing.
An exact expression for CINT is:
Rosc (Pin 40 to Pin 39) should be 100 kil. Cosc is
selected from the equation:
(4000) (_1_)( VFS )
CINT = _ _ _ _fo_s_C__R_I_NT_
VINT
Where:
fosc = Clock frequency at Pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current is
100 f.1A. The integrator and buffer can supply 20 f.1A drive
currents with negligible linearity errors. RINT is chosen to
remain in the output stage linear drive regionbut not so large
that printed circuit board leakage currents induce errors. For
a 200 mV full-scale RINT is 47 kil. A 2.0 V full-scale requires
470 kil.
CAZ
RINT
CINT
Note:
1. fose
200.0 mV
,2.000V
0.471LF
47kn
0.221LF
0.047 1LF
470 kn
=48 kHz (3 readings/sec)
For fosc of 48 kHz, Cosc is 100 pF nominally.
Notethatfosc is divided byfourto generate the TC71 06A
internal control clock. The backplane drive signal is derived
by dividing fosc by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz,
40 kHz, 33 1/3 kHz, etc. should be selected. For 50 Hz
rejection, oscillator frequencies of 200 kHz, 100 Khz,
66213 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that
40 kHz (2.5 readings/second) will reject both 50 and 60 Hz
(also 400 and 440 Hz).
Required Full-Scale Voltage·
200.0 mV
2.000 V
Nominal Full-Scale Voltage
0.221LF
0.45
RC
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
INTEGRATING RESISTOR - RINT
Component
osc =
Reference Voltage Selection
CINT must have low dielectric absorption to minimize
rollover error. An inexpensive polypropylene capacitor is
recommended.
Value
f
100.0 mV
1.000V
In some applications a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, a pressure transducer
output is 400 mV for 2000 Iblin2 . Rather than dividing the
input voltage by two the reference voltage should be set to
200 mY. This permits the transducer input to be used
directly.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analog common and YiN. The transducer output is connected between YiN and analog common.
The internal voltage reference potential available at
analog common will normally be used to supply the converters reference. This potential is stable whenever the supply
potential is greater than approximately 7 V. In applications
where' externally generated reference voltage is desired
refer to Figure 9.
1-126
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC7107n107A
v+
output swing can be reduced below the recommended
2.0 Vfull-scale swing. The integrator output will swing within
0.3 V of V+ or V- without increasing linearity errors.
y+
v+
v+
"'"
VREF
"'' '
TC7106A
TC7107A
TC7106A
TC7107A
+IZ
V~EF
VREF
"'"
TC04
1.2V
REF
COMMON
VI
(b)
(a)
Where'
.
4350 ILL F11
Figure 9
=~
[VCM -VIN]
I
4000
TI = INTEGRATION TIME = fosc
External Reference
CI = INTEGRATION CAPACITOR
RI = INTEGRATION RESISTOR
Device Pin Functional Description
Differential Signal Inputs
(ViN (Pin 31), VjN (Pin 30))
4350 ILL F13
Figure 11
The TC7106A17017A is designed with true differential
inputs and accepts input signals within the input stage
common mode voltage range (VCM). The typical range is V+
-1.0 to V- + 1 V. Common-mode voltages are removed from
the system when the TC71 06A1TC71 07A operates from a
battery or floating power source (isolated from measured
system) and VjN is connected to analog common (VCOM):
See Figure 10.
In systems where common-mode voltages exist in
86 dB common-mode rejection ratio minimizes error. Common-mode voHages do, however, affect the integrator output level. Integrator output saturation must be prevented. A
worse case condition exists if a large positive VCM exists in
conjunction with a full-scale negative differential signal. The
negative signal drives the integrator output positive along
with VCM (Figure 11). For such applications the integrator
Common-Mode Voltage Reduces Available Integrator
Swing. (VCOM VIN)
*
Differential Reference
(VREF (Pin 36), VREF (Pin 35))
The reference voHage can be generated anywhere
within the V+ to V- power supply range.
To prevent rollover type errors being induced by large
common-mode voltages CREF should be large compared to
stray node capacitance.
The TC71 06A1TC71 07A circuits have significantly lower
analog common temperature coefficient. This potential gives
a very stable voHage suitable for use as a voHage reference.
The temperature coefficient of analog common is 20 ppm/DC
typically.
MEASURED
SYSTEM
9V
43S01LL F12
Figure 10
Common-Mode Voltage Removed in Battery Operation with ViN =Analog Common
1-127
3 1/2 DIGIT AID CONVERTER
TC71 OGn1 OGA
TC71 07n1 07A
Analog Common (Pin 32)
The analog common pin is set at a voltage potential
approximately 3.0 V below V+. The potential is guaranteed
to be between 2.7 V and 3.35 V below V+ Analog common
is tied internally to the N channel FET capable of sinking 20
mAo This FET will hold the common line at 3.0 V should an
external load attempt to pull the common line toward V+
Analog common source current is limited to 10 j..LA. Analog
common is therefore easily pulled to a more negative
voltage (i.e., below V+ -3.0 V).
The TC71 06A connects the internal YiN and YiN inputs
to analog comrnon during the auto-zero cycle. During the
reference integrate phase YiN is connected to analog common. If YiN is not externally connected to analog common,
a common-mode voltage exists. This is rejected by 'the
converters 86 dB common-mode rejection ratio. In battery
operation analog common and YiN are usually connected
removing common-rnode voltage concerns. In systems where
YiN is connected to the power supply ground or to a given
voltage, analog common should be connected to YiN.
The analog common pin serves to set the analog section
reference or common point. The TC7106A is specifically
designed to operate from a battery or in any measurement
system where input signals are not referenced (float) with
respect to the TC71 06A power source. The analog common
potential of V+ -3.0 V gives a 6 Vend of battery life Voltage.
The common potential has a 0.001 %/% voltage coefficient
and a 15 12 output impedance.
With sufficiently high total supply voltage (V+ -V- >
7.0 V) analog cornmon is a very stable potential with excel-
lent temperature stability-typically 20 ppm/°C. This potential can be used to generate the reference voltage. An
external voltage reference will be unnecessary in most
cases because of the 50 ppm/°C maximum temperature
coefficient. See Internal Voltage Reference discussion.
Test (Pin 37)
The test pin potential is 5 V less than V+. Test may be
used as the negative power supply connection for external
CMOS logic. The test pin is tied to the internally generated
negative logic supply (Internal Logic Ground) through a
50012 resistor in the TC71 06A. The test pin load should be
no more than 1mA .
Iftest is pulled to V+ all segments plus the minus sign will
be activated. Do not operate in this mode for more than
several minutes with the TC71 06A. With Test = V+ the LCD
Segments are impressed with a DC voltage which will
destroy the LCD.
The test pin will sink about 10 rnA when pulled to V+.
Internal Voltage Reference Stability
The analog common voltage temperature stability has
been significantly improved (Figure 12). The "A" version of
the industry standard circuits allow users to upgrade old
systems and design new systems without external voltage
references. External Rand C values do not need to be
changed. Figure 13 shows analog common supplying the
necessary voltage reference for the TC71 06A1TC71 07 A.
200
U 180
~0-
l-
a
160 I-
zw
140 I-
I-
Na
MAXIMUM
SPECIFIED
NO MAXIMUM
SPECIFIED
TYPICAL
V-
TC7106A
TC7107A
U
u:u.. 120
w
0 100 l(.)
w
a: 80 l-
t
MAXIMUM
:J
I-
....--+---IVREF
0.7%I"C
PTC
COMMON
4350 ILL F23
Figure 21
4350 ILL F24
Temperature Sensor
Figure 22
Positive Temperature Coefficient Resistor
Temperature Sensor
9Y
y
12
Y+
""
11
CONSTANTSY
v+
/
REF02
YOUT
Y+REF
1
6
S1kn
Ii;
Rs
5
2
ADJ ! - - - N C
TEMP
0---
"""
TC911
TEMPERATURE
DEPENDENT
OUTPUT
V-REF
YFS =2.00 Y
r"
V-IN
YOUT=
2S·C
1.3k
Y+IN
SOkoL
R1
GND
14
~""
TC7106A
SOkO
R2
~'1
3~~
3
/
5.1 kn
COMMON
v1
26
1
43S0ILL F25
Figure 23
Integrated Circuit Temperature Sensor
1-132
3 1/2 DIGIT AID CONVERTER
TC71 06n1 06A
TC7107n107A
TO PIN 1
TOPINI
+5V
+
~"
TC7106A
+
+
~"
IN
IN
TC7107A
=
9V
cr~~~------------~--O~V
4350 III F26
Figure 24
4350 ILL F27
TC7106A Using the Internal Reference.
(200 mV Full-Scale, 3 RPS).
Figure 25
TC7107A Internal Reference (200 mV Full-Scale,
3 RPS, YiN Tied to GND for Single Ended Inpuls).
TO PIN 1
~"
TC7106A
TC7107A
lMQ
+
IN
~==~~-------------oV-
CD4077
OIR = OVERRANGE
WR = UNDERRANGE
4350 III F28
Figure 26
4350 ILL F29
Circuit for Developing Underrange and Overrange
Signals from TC7106A Oulpuls.
Figure27
1-133
TC7106A1TC7107A: Recommended Component
Values for 2.00 V Full-Scale
3 1/2 DIGIT AID CONVERTER
TC71 OSn1 OSA
TC71 07n1 07A.
TO PIN 1
10110
"II"'TC04
1MO
10kO
y.
""TC04
•
.,""
IN
TC7107A
"'''"
TC7107A
1MO
y.
•
IN
y-
4350 III F31
4350 ILL F30
Figure 28
TC71 07A With a 1.2 Y External Band-Gap Reference.
(Y-IN Tied to Common.)
Figure 29
1-134
TC7107A Operated from Single.5 Y Supply An
External Reference Must Be Used in This Application.
"~TELEDYNE
COMPONENTS
TC7116
TC7116A
TC7117
TC7117A
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
FEATURES
•
•
•
•
•
Low Temperature Drift Internal Reference
TC71161TC7117 ............................. 80 ppml°C Typ
TC7116A1TC7117A ........................ 20 ppml°C Typ
Display Hold Function
Directly Drives LCD or LED Display
Guaranteed Zero Reading With Zero Input
Low Noise for Stable
Display ..•.....• 2V or 200 mV FUll-Scale Range (FSR)
•
Auto-Zero Cycle Eliminates Need for tero
Adjustment Potentiometer
True POlarity Indication for Precision Null
Applications
Convenient 9V Battery Operation
(TC71161TC7116A)
High Impedance CMOS Differential Inputs ... 10120
Low Power Operation ..................................... 10 mW
•
•
•
•
1 Mil
3
YiN
32 ANALOG
COMMON
28 VBUFF
+
V
.,~
1---_-..,
24 kll
iC~l~
47kn
V~EF
0.22~F
VREF
36
l00I'l1V
1 kll
y- 26
TO ANALOG
COMMON (PIN 32)
39
3 CONVERSIONSISEC
Figure 1
Typical TC71161TC7116A Operating Circuit
DISPLAY
1 HOLD
lMn
32 ANALOG
COMMON
28 VBUFF
.,~
+ ..- -....._.....0 +5V
V
trg,~r:A
0.22 pF
y-I----tl----o ~V
to ANAlOG
COMMON (PIN 32)
39
3 CONVERSIONSISEC
Figure 2
Typical TC7117ITC7117A Operating Circuit
1-135
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
GENERAL DESCRIPTION
The TC7116A and TC7117A feature a precision, lowdrift internal reference, and are functionally identical to the
TC71161TC7117. A low-drift external reference is not
normally required with the TC7116A!TC7117A.
The TC7116A!TC7117A are 3-1/2 digit CMOS analogto-digital converters (AOCs) containing all the active
components necessary to construct a 0.05% resolution
measurement system. Seven-segment decoders, polarity
and digit drivers, voltage reference, and clock circuit are
integrated on-chip. The TC7116A drives liquid crystal
displays (LCOs) and includes a backplane driver. The
TC7117A drives common anode light emitting diode (LED)
displays directly with an S-mA drive current per segment.
These devices incorporate a display hold (HLDR)
function. The displayed reading remains indefinitely, as
long as HLDR is held high. Conversions continue, but
output data display latches are not updated. The reference
low input (VREF) is not available as it is with the TC71 061
7107. VREF is tied internally to analog common in the
TC7116A17117A devices.
The TC7116A17117A reduces linearity error to less
than 1 count. Roll-over error (the difference in readings for
equal magnitude but opposite polarity input signals) is
below ±1 count. High-impedance differential inputs offer 1
pA leakage current and a 10120 input impedance. The 15
~Vp_p noise performance guarantees a "rock solid" reading.
The auto-zero cycle guarantees a zero display reading with
aOVinput.
The TC7116A17117A dual-slope conversion technique
automatically rejects interference signals if the converter's
integration time is set to a multiple 'of the interference
period. This is especially useful in industrial measurement
environments where 50-Hz, 60-Hz, and 400-Hz line
frequency signals are present.
The TC7116A17117A are available in a small, 60-pin
flat package for compact designs. Standard devices are
offered in an industrial temperature range and with 160hour burn-in at +125°C.
ORDERING INFORMATION
Part No.
TC7116CPL
TC7116ACPL
TC71161PL
TC7116CJL
TC71161JL
TC7116AIJL
TC7116CBQ
TC7116ACBQ
TC7116CKW
TC7116ACKW
TC7116CLW
TC7116ACLW
TC7117CPL
TC7117ACPL
TC71171PL
TC7117CJL
TC71171JL
TC7117AIJL
TC7117CBQ
TC7117ACBQ
TC7117CKW
TC7117ACKW
TC7117CLW
TC7117ACLW
Package
Temperature Range
Reference Temperature
Coefficient
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin CerDIP
40-Pin CerDIP
40-Pin CerDlP
60-Pin Plastic Flat
60-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin PLCC
44-Pin PLCC
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin CerDlP
40-Pin CerOIP
40-Pin CerDIP
60-Pin Plastic Flat
60-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin PLCC
44-Pin PLCC
DOC to +70°C
DOC to +70°C
-25°C to +S5°C
DoC to +70°C
-25°C to +85°C
-25°C to +85°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
O°C to +70°C
O°Cto +70°C
-25°C to +S5°C
O°Cto +70°C
-25°C to +S5°C
-25°C to +85°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
DoC to +70°C
O°C to +70°C
O°C to +70°C
SO ppm/°C
35 ppm/°C
SO ppm/°C
SO ppm/°C
80 ppm/°C
35 ppm/°C
SO ppm/°C
35 ppm/°C
SO ppm/°C
35 ppm/°C
SO ppm/°C
35 ppm/°C
80 ppm/°C
35 ppm/°C
SO ppm/°C
80 ppm/°C
80 ppm/°C
35 ppm/°C
SO ppm/°C
35 ppm/°C
80 ppm/°C
35 ppm/°C
SO ppm/°C
35 ppm/°C
1-136
Display
Drive
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
3·1/2 DIGIT ANALOG ..TO..DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
PIN CONFIGURATIONS
F2
E2
03
B3
F3
E3
l000'8--... AB 4
...
w u
+a: z
>
POL
(MINUS SIGN)
...s:w
.
c
l-
HI
f>
u
III
I- 0
U
...
u
z III
0
U
Z
/II
:l
III
U
Z
.. U u
&! z z !!i...
0
%
...
!f 0
i!!: i!!: ~
a:
..
o u
......
:l
/II
1~
TC7116CKW
TC7116ACKW
TC7117CKW
TC7117ACKW
(FLAT PACKAGE)
TC7116CLW
TC7116ACLW
TC7117CLW
TC7117ACLW
(PLCC)
NOles:
=
1. NC No internal connection.
2. Pins 8, 23, 38, and 53 are connected to the die substrate. The potential at these pins is approximately V~ No external connections
should be made.
1-137
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
ABSOLUTE MAXIMUM RATINGS·
Supply Voltage
TC7116/TC7116A: V+ to V- ............................... ±15V
TC7117/TC1117A: V+to GND .............................. +6V
V-to GND ............................. -9V
Analo'g Input Voltage (Either Input) (Note 1) ......... V+ to VReference Input VoHage (Either Input) ................. V+ to VClock Input
TC7116/TC7116A ..................................... TEST to V+
TC7117/TC7117A ...................................... GND to V+
Power Dissipation (Note 2)
CerDIP ......................................................... 1000 mW
Plastic ............................................................ 800 mW
Operating Temperature
"C" Device .............................................. O°C to +70°C
"I" Device ............................................ -25°C to +85°C
Storage Temperature .............. ,.............. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................... 300·C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratin9s only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS (Note 3)
Parameter
Test Conditions
Zero Input Reading
VIN= OV
Full Scale = 200 mV
VIN = VREF
VREF= 100 mV
-VIN = +VIN '" 200 mV or
Ratiometric Reading
Roll-Over Error (Difference in
Reading for l:qual Positive and
Negative Readings Near Full Scale)
Linearily (Maximum Deviation From
Best Straight Line F~)
Common-Mode Rejection Ratio (Note 4)
Noise (Peak-to-Peak Value Not
E:xceeded 95% of Time)
Leakage Current at Input
Zero Reading Drift
Scale Factor Temperature Coefficient
Input Resistance, Pin 1
VIL. Pin 1
VIL, Pin 1
VIH. Pin 1
Supply Current (Does Not Include
LEO Current for ll17A)
Analog Common Voltage
(W~h Respect to Pos~ive Supply)
Temperature Coefficient of Analog Common
(With Respect to Pos~ive Supply)
Temperature Coefficient of Analog Common
(W~h Respect to PoMive Supply)
Min
Typ
-
±o
999
999/1000
Max
1000
Unit
Digital
Reading
Dig~al
-1
±0.2
+1
Reading
Counts
=200 mV or 2V
-1
±0.2
+1
Counts
VCM =±lV, VIN = OV
Full Scale = 200 mV
VIN= OV
Full Scale = 200 mV
VIN =OV
VIN =OV
"C" Device: O·C to +70·C
"I" Device: -25·C to +S5·C
VIN = 199 mV
"C" Device: O·C to +70°C
(EX! Ref = 0 ppm/DC)
"I" Device: -25°C to +S5°C
Note 6
TC7116A Only
TC7117A Only
Both
VIN = OV
-
50
-
15
-
-
1
10
pA
0.2
1
1
2
fJ,V,·C
fJ,V,·C
1
5
ppm/°C
20
ppm/°C
kO
V
V
V
Full Scale
~
2V
25 kO Between Common
and Positive Supply
"C" Device: O°C to +70°C
TC7116A1TC7117A
TC7116ITC7117
"I" Device: -25°C to +S5°C
25 kQ Between Common and
Pos~ive Supply (TC7116A1TC7117A)
1-138
-
-
-
30
70
-
-
-
Test +1.5
GND +1.5
-
0.8
1.8
2.4
3.05
3.35
-
20
SO
-
-
V+-l.5
-
-
-
-
50
75
fJ,VN
fJ,V
rnA
V
ppm/°C
ppm/°C
ppm/°C
3.. 1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7117
TC7117A
TC7116A
ELECTRICAL CHARACTERISTICS (Cont.)
Parameter
Test Conditions
Min
Typ
Max
TC7116ITC7116A ONLY Peak-to-Peak
Segment Drive Vottage
V+to V-= 9V
(Note 5)
4
5
6
V
TC7116ITC7116A ONLY Peak-to-Peak
Backplane Drive Voltage
V+to V = 9V
(Note 5)
4
5
6
V
TC7117ITC7117A ONLY Segment
Sinking Current (Except Pin 19)
V+=5V
Segment Voltage = 3V
5
8
-
mA
TC7117ITC7117A ONLY Segment
Sinking Current (Pin 19 Only)
V+=5V
Segment Voltage = 3V
10
16
-
mA
Unit
NOTES: 1. Input voltages may exceed supply voltages, provided input current is limited to ±1 00 ~.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply at TA = +25°C, fCLOCK = 48 kHz. TC7116fTC7116A are tested in the circuit of Figure 1.
TC7117rrC7117A are tested in the circuit of Figure 2.
4. Refer to 'Differential Input' discussion.
5. Backplane drive is in-phase with segment drive for "off' segment, 180° out-of-phase for "on" segment. Frequency is 20 times conversion.
rate. Average DC component is less than 50 mY.
6. The TC71161TC7116A logic inputs have an intemal pull-down resistor connected from HLDR, pin 1 to TEST, pin 37.
The TC7117rrC7117A logic inputs have an intemal pull-down resistor connected from HLDR, pin 1 to GND, pin 21.
PIN DESCRIPTION
60-Pin
Flat Package
Pin Number
Name
1
13
HLOR
2
14
01
Activates the 0 section of the units display.
3
15
C1
Activates the C section of the units display.
4
16
Bl
Activates the 8 section of the units display.
5
6
17
AI
Activates the A section of the units display.
18
Fl
Activates the F section of the units display.
7
19
G1
Activates the G section of the units display.
8
20
Activates the E section of the units display.
9
21
El
O2
10
25
C2
Activates the C section of the tens display.
4o-Pin DIP
Pin Number
Normal
Description
Hold pin, Logic 1 holds present display reading.
Activates the
0 section of the tens display.
11
26
B2
Activates the 8 section of the tens display.
12
27
A2
Activates the A section of the tens display.
13
28
F2
Activates the F section of the tens display.
14
29
E2
Activates the E section of the tens display.
15
30
03
Activates the
16
31
83
Activates the 8 section of the hundreds display.
17
32
F3
Activates the F section of the hundreds display.
18
33
Activates the E section of the hundreds display.
19
34
E3
A8 4
20
35
POL
Activates the negative polarity display.
21
36
BP
GNO
LCD backplane drive output (TC7116ITC7116A).
Digital ground (TC7117ITC7117 A).
22
37
G3
Activates the G section of the hundreds display.
23
40
AJ
Activates the A section of the hundreds display.
0 section of the hundreds display.
Activates both halves of the 1 in the thousands display.
1-139
3..1/2 DIGIT ANALOG·TO..DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
PIN DESCRIPnON (Cont.)
4O-Pin DIP
Pin Number
Normal
6O-Pin
Flat Package
Pin Number
Name
Description
24
25
26
27
13
41
43
45
46
HLDR
Ca
G2
VVINT
28
47
VSUFF
29
49
CAZ
30
31
32
51
55
57
VIN
V1N
ANALOG
33
34
58
59
CREF
C+REF
35
36
60
Hold pin, Logic 1 holds present display reading.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
Integrator output. Connection point for integration
capacitor. See Integration Capacnor section for
add~ional details.
Integration resistor connection. Use a 47 kn resistor for
200 trW full-scale range and a 41'0 kn resistor fot 2V
full-scale range.
The size of the auto-zero capacitor influences system
nOise. Use a 0.4711F capacitor for 200.mV full scale illid
a 0.04711F capacitor for 2V full scale. See Auto-Zero
Capacitor paragraph for more details ..
The analog low input is connected to this pin.
The analog high input is connected to this pin.
This pin is primarily used to set the analog commonmode COMMON vo~age for battery operation or in
systems where the input signal is referenced to the
power supply. See Analog Common paragraph for more
details. It also acts as a reference VOltage source.
See pin 34.
A 0.1 I1F capaCitor is used in most applications. If a
large, common-mode voltage exists (e.g., the "iN pin is
hOt at analog common), and a 200 mV scale is used, a 1
I1F capacitor is recommended and will hold the roll-over
error to 0.5 count.
Positive power supply voltage.
The analog input required to generate a full-scale output
(1999 counts). Place 100 mV between pins 32 atid 36
for 199.9 mV full scale. Place 1V between pilis 32 atid
36 for 2V full scale. See paragraph on Referelieii
37
3
TEST
38
39
40
4
6
10
OSCa
V+
V+REF
Vo~age.
Lamp test. When pulled high (to V+), all segments will
be turned on and the display should read ~ 18S8. It may
also be used as a negative supply for extemallygenerated decimal points. See Test paragraph for more
details.
See pin 40.
See pin 40.
Pins 40, 39 and 38 makii up the oscillator section. Fot a
48 kHz clock (3 readings per sec), connect pin 40 to the
junction of a 100 kn resistor and a 100 pF capacitor. The
100 kn resistor is tied to pin 39 and the 100 pF capacitor
is tied to pin 38.
OS~
OSCl
1-140
3..1/2 DIGIT ANALOG ..TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
C REF
".,.. ... "'.
: v+
,,
,,
'31
YiN O,4--coO-.....--I-::c=-'.---+--...J
,,
TO
DIGITAL
SECTION
r-.----,
,
,,
I
COMPARATOR
..,'"
ANALOG ,3;!
CO~~ONO,-+---~--""'~~----~
TC7116
TC7116A
TC7117
TC7117A
130
V-INo-~~~--~----------~~------------...l
: .. __ I!:IT_ .. ____ .. _________ .. 26
Figure 3
Analog $e~1ion ofTC71161TC7116A and TC7117ITC7117A
ANALOG seCTION
Reference Integrate Phase
Figure 3 shows the block diagram of the analog section
for the TC7116/TC7116A and TC71171TC7117A. Each
measurement !::y<:le j~ diVideg into three phases: (1) auto;zero (A·Z) , (2) signal integrate (IND, and (3) reference
integrate (REF) or deintegrate (DE).
The final phase is reference integrate, or deintegrate.
Input low is internally connected to analog common and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time
required for the output to return to zero is proportional to
the input signal. The digital reading displayed is:
Auto-Zero Phase
High and low inputs are disconnected from the pins
and internally shorted to analog common. The reference
capacitor is charged to the reference voltage. A feedback
loop is closed around the system to charge the auto-zero
capacitor (CA;z) to compenSllte for offset voltages in the
buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, A-Z accuracy is limited only
by system noise. The offset referred to the input is less
than 10 ltV.
1000x
~
VREF
Reference
The positive reference voltage (V+REF) is referenced to
analog common.
Differential Input
Signal-Integrate Phase
The auto-zero loop is opened, the internal short is
removed, and the internal high and low inputs are connected to the external pins. The converter then integrates
the differential voltages between V'iN and VIN for a fixed
time. This differential voltage can be within a wide common-mode range; 1Vof either supply. However, if the input
signal has no return with respect to the converter power
supply, VIN can be tied to analog common to establish the
correct common-mode voltage. At the end of this phase,
the polarity of the integrated signal is determined.
1-141
This input can accept differential voltages anywhere
within the common-mode range of the input amplifier or,
specifically, from 1V below the positive supply to 1V above
the negative supply. In this range, the system has a CMRR
of 86 dB, typical. However, since the integrator also swings
with the common-mode voltage, care must be exercised to
ensure the integrator output does not saturate. A worstcase condition would be a large, positive common-mode
voltage with a near full-scale negative differential input
voltage. The negative-input signal drives the integrator
positive when most of its swing has been used up by the
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
v+
.......
v+
v+
I
I
.,
v+
,
,
"'''
TC7116
TC7116A
"'''
TC7116
TC7116A
TC7117
TC7117A
20 kQ
1---<
V+REF
I
I
4049
~---1----~'~
BP 21
"'''
TC9491CJ
TESTi-:3C=7---+---..-J
'
,,
I
,
TOLCt)
DECIMAL
POINT
TO LCD
1 . . - - - - - - - 0 BACKPLANE
COMMON
Figure 4
Figure 5
Using an External Reference
positive common-mode voltage. For these critical applications, the integrator swing can be reduced to less than
the recommended 2V full-scale swing with little loss of
accuracy. The integrator output can swing within 0.3V of
either supply without loss of linearity.
Simple Inverter for Fixed Decimal Point
BP ........-------...;....\·
"'''
Analog Common
TC7116
TC7116A
This pin is included primarily to set the common-mode
voltage for battery operation (TC7116ITC7116A) or for any
system where the input signals are floating with respect to
the power supply. The analog common pin sets a voltage
approximately 2.SV more negative than the positive supply.
This is selected to give a minimum end-of-life battery voltage
of about 6V. However, analog common has some attributes
of a reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (>7V), the analog
common voltage will have a low voltage coefficient (0.001 %/
%), low output impedance (=150.), and a temperature
coefficient of less than 20 ppm/°C, typically, and 50 ppm
maximum. The TC7116ITC7117 temperature coefficients
are typically so ppm/°C.
An external reference may be used, if necessary, as
shown in Figure 4.
Analog common is also used as VIN return during autozero and deintegrate. If VjN is different from analog common,
a common-mode voltage exists in the system and is taken
care of by the excellent CMRR of the converter. However, in
some applications, VjN will be set at a fixed, known voltage
(power supply common for instance). In this application,
analog common should be tied to the same point, thus
removing the common-mode voltage from the converter.
The same holds true for the reference voltage; if it can be
conveniently referenced to analog common it should be,
since this removes the common-mode voltage from the
reference system.
Within the IC, analog common is tied to an N-channel
FET that can sink 30 mA or more of current to hold the
voltage 3V below the positive supply (when a load is trying
TEST
Figure 6
Exclusive "OR" Gate for Decimal Point Drive
4~ TC7116ITC7116A
''11
TC7117ITC7117A
Figure 7
Clock Circuits
to pull the analog common line positive). However, there is
only 10 ~ of source current, so analog common may easily
be tied to a more negative voltage, thus overriding the
internal reference.
Test
The test pin serves two functions. On the TC7117!
TC7117A, it is coupled to the internally-generated digital
supply through a 5000. resistor. Thus, it can be used as a
1-142
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
negative supply for extemally-generated segment drivers,
such as decimal points or any other presentation the user
may want to include on the LCD. (Figures 5 and 6 show
such an application.) No more than a 1 mA load should be
applied.
The second function is a "lamp test." When test is pulled
high (to V+), all segments will be tumed on and the display
should read -1888. The test pin will sink about 10 mA under
these conditions.
DIGITAL SECTION
Figures 8 and 9 show the digital section for TC71161
TC7116A and TC7117ITC7117A, respectively. For the
TC7116ITC7116A (Figure 8), an intemal digital ground is
generated from a 6V zener diode and a large P-channel
source follower. This supply is made stiff to absorb the
-/
"''''
TC7116
TC7116A
TC7117
TC7117A
relative large capacitive currents when the backplane (BP)
voltage is switched. The BP frequency is the clock frequency +800. For 3 readings per second, this is a 60-Hz
square wave with a nominal amplitude of 5V. The segments
are driven at the same frequency and amplitude, and are inphase with 8P when OFF, but out-of-phase when ON. In all
cases, negligible DC voltage exists across the segments.
Figure 9 is the digital section of the TC7117ITC7117A. It
is identical to the TC71161TC7116A, except the regulated
supply and BP drive have been eliminated, and the segment
drive is typically 8 rnA. The 1OOO'soutput (pin 19) sinks current
from two LED segments, and has a 16-rnA drive capability.
The TC7117ITC7117A are designed to drive common anode
LED displays.
In both devices, the polarity indication is ON for analog
inputs. If VjN and VtN are reversed, this indication can be
reversed also, if desired.
B B B
BACKPLANE
~------.----~--------------
21
TYPICAL SEGMENT OUTPUT
--------~------v+
SEGMENT
OUTPUT
INTERNAL DIGITAL GROUND
Figure 8
TC71161TC7116A Digital Section
1-143
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
System Timing
The clocking method used for the TC7116/TC7116A
and TC7117ITC7117A is shown in Figure 9. Three clocking
methods may be used:
(1) An external ()l;cillator connected to pin 40.
(2) A crystal between pins 39 and 40.
(3) An RC network using all three pins.
The oscillator frequency is +4 before it clocks the
decade counters. It is then further divided to form the three
convert-.cycle phases: signal integrate (1000 counts). reference delntegrate (0 to 2000 counts). and auto-zero (1 000 to
3000 counts). For signals less than full scale. auto-zero gets
the unused portion of reference deintegrate. This makes a
~omplete mea~ure cycle of 4000 (16.000 clock pulses)
Independent of Input voltage. For 3 readings per second an
oscillator frequency of 48 kHz would be used.
•
..,~
. To. achieve maximum rejection of 60-Hz pickup. the
Signal-Integrate cycle should be a multiple of 60 Hz. Oscillator frequencies of 240 kHz. 120 kHz. 80 kHz. 60 kHz. 48
kHz. 40 kHz. 33-1/3 kHz. etc. should be selected. For 50 Hz
rejection. oscillator frequencies of 200 kHz. 100 kHz. 66-213
kHz. 50 kHz. 40 kHz. etc. would be $uitable. Notetht;lt 40 kHz
(2.5 readings per second) will reject both 50 Hz and 60 Hz
(also 400 Hz t;lnd 440 Hz).
HOLD Reading Input
When HLDR is at a logic HIGH the latch will not be
updated. Analog-to-digital conversions will continue but will
not be updated until HLDR is returned to LOW. To continuously update the display. connectto test (TC7116/TC7116A)
or ground (TC7117ITC7117A). or disconnect. This input is
CMOS compatible with 70 kO typical re$istance to test
(TC7116/TC7116A) or ground (TC71171TC7117A) .
-/
TC7117
TC7117A
8
TYPICAL SEGMENT OUTPUT
--------v+
TO
SEGMENT
DIGITAL GROUND
39
·-·-OSc~
38
...........
OSC3
Figure 9
TC7117/TC7117A Digital Seetlon
1-144
8
8
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7117
TC7117A
TC7116
TC7116A
Reference Voltage
COMPONENT VALUE SELECTION
Auto-Zero Capacitor
The size of the auto-zero capacitor has some. influence
on system noise. For200 mV full scale, where noise is very
important, a 0.47 IlF capacitor is recommended. On the 2V
scale, a 0.047 IlF capacitor increases the speed of recovery
from overload and is adequate for noise on this scale.
Reference capacitor
A 0.1 IlF capacitor is acceptable in most applications.
However, where a large common-mode voltage exists (i.e.,
the ViN pin is not at analog common), and a 200-mV scale is
used, a larger value is required to prevent roll-over error.
Generally, 1 IlF will hold the roll-over error to 0.5 count in this
instance.
Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approximately 0.3V from
either supply). In the TC7116fTC7116A or the TC7117/
TC7117A, when the analog common is used as a reference,
a nominal ±2.V full- scale integrator swing is acceptable. For
the TC7117ITC7117A, with ±5V supplies and analog common tied to supply ground, a ±3.5V to ±4V swing is nominal.
For 3 readings per second (48 kHz clock), nominal values for
CINT are 0.22 1l1F and 0.10 IlF, respectively. If different
oscillator frequencies are used, these values should be
changed in inverse proportion to maintain the output swing.
The integrating capacitor must have low dielectric absorption to prevent roll-over errors. Polypropylene capacitors
are recommended for this application.
Integrating Resistor
To generate full-scale output (2000 counts), the analog
input required is VIN = 2 VREF. Thus, for the 200 mV and 2V
scale, VREF should equal 100 mV and 1V, respectively. In
many applications, where the ADC is connected to a transducer, a scale factor exists between the input voltage and
the digital reading. For instance, in a measuring system the
designer might like to have a full-scale reading when the
voltage from the transducer is 700 mV. Instead of dividing
the input down to 200 mV, the designer should use the input
voltage directly and select VREF =350 mV. Suitable values
for integrating resistor and capacitor would be 120 kn and
0.22 IlF. This makes the system slightly quieter and also
avoids a divider network on the input. The TC7117ITC7117A,
with ±5V supplies, can accept input signals up to ±4V.
Another advantage of this system is when a digital reading
of zero is desired for VIN O. Temperature and weighing
systems with a variable tare are examples. This offset
reading can be conveniently generated by connecting the
voltage transducer between ViN and analog common, and
the variable (or fixed) offset voltage between analog common andVjN.
*
TC7117rrC7117A POWER SUPPLIES
The TC7117ITC7117Aaredesignedtooperatefrom±5V
supplies. However, if a negative supply is not available, it can
be generated with a TC7660 DC-to-DC converter and two
capacitors. Figure 10 shows this application.
In selected applications, negative supply is not required.
The conditions to use a single +5V supply are:
(1) The input signal can be referenced to the center of
the common-mode range of the converter.
(2) The signal is less than ±1.5V.
(3) An extemal reference is used.
Both the buffer amplifier and the integrator have a class
A output stage with 100 !!A of quiescent current. They can
supply 20 !!A of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 470 kn is near optimum and,
similarly, 47 kn for 200 mV full scale.
"''''
TC04
TC7117
TC7117A
Oscillator Components
8
For all frequency ranges, a 100-kn resistor is recommended; the capacitor is selected from the equation:
YiN
31
YiN
30
V- GND
"''''
f=~.
26
'""
+
YIN
21
'""
RC
For 48 kHz clock (3 readings per second), C
= 100 pF.
Figure 10
1-145
Negative Power Supply Generation With TC7660
3~1/2
TC7116
TC7116A
DIGIT ANALOG·TO·DIGITAL
CONVERTERS WITH HOLD
TC7117
TC7117A
TYPICAl,. APPLICATIONS
+
IN
CD4077
Figure 11
TC71161TC7116A Using the Internal Ref.....em:/il
(200 mV Full Scale, 3 RPS)
Figure 13
OIR ~ OVERRANGE
ll'R' =UNDERRANGE
Circuit for Developing Underrange and Overrange
Signals from TC71161TC7116A Outputs
+
IN
IN
o-=:.e:...:...:....-----...;.-o -SV
Figure 12
~~~-----------oy-
TC71171TC7117A Internal Referenc:e (200 mV Full
Scale, 3 RPS, Vj"N Tied to GND lor Single-Ended Inputs.)
Figure 14
1-146
TC71171TC7117A With a 1.2Y External Band-Gap
Referenca (Vj"N Tied to Common)
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
10kil
v+
""TC9491CJ
+
v+
+
"''''
TC7116
TC7116A
TC7117
TC7117A
TC7117
TC7117A
"''''
IN
TC7117
TC7117A
1 Mil
IN
V-
Figure 15
Recommended Component Values for 2V Full Scale
(TC71161TC7116A and TC71171TC7117A)
Figure 16
TC7117ITC7117AOperated from Single+5V Supply
(An External Reference Must Be Used in This
Application.)
APPLICATIONS INFORMATION
The TC7117fTC7117A sink the LED display current,
causing heat to build up in the IC package. If the internal
voltage reference is used, the changing chip temperature
can cause the display to change reading. By reducing
package power dissipation, such variations can be reduced.
By reducing the LED common anode voltage, the TC7117/
TC7117A package power dissipation is reduced.
Figure 17 is a curve-tracer display showing the relationship between output current and output voltage for typical
TC7117CPLlTC7117ACPL devices. Since a typical LED
has 1.8V across it at 8 mA and its common anode is
connected to +5V, the TC7117fTC7117A output is at 3.2V
(Point A, Figurel?). Maximum power dissipation is 8.1 mA
x 3.2V x 24 segments = 622 mW.
However, notice that once the TC7117fTC7117A's output voltage is above 2V, the LED current is essentially
constant as output voltage increases. Reducing the output
voltage by 0.7V (Point B Figure 17) results in 7.7 mA of LED
current, only a 5% reduction. Maximum power dissipation is
now only 7.7 mAx 2.5Vx24 =462 mW, a reduction of 26%.
An output voltage reduction of 1V (Point C) reduces LED
current by 10% (7.3 mA), but power dissipation by 38% (7.3
mA x 2.2V x 24 = 385 mW).
Reduced power dissipation is very easy to obtain.
Figure 18 shows two ways: Either a 5.1 n, 1/4W resistor, or
a 1A diode placed in series with the display (but not in series
with the TC7117fTC7117A). The resistor reduces the
TC7117fTC7117A's output voltage (when all 24 segments
are ON) to Point C of Figure 17. When segments turn off, the
output voltage will increase. The diode, however, will result
in a relatively steady output voltage, around Point B.
In addition to limiting maximum power dissipation, the
resistor reduces change in power dissipation as the display
changes. The effect is caused by the fact that, as fewer
segments are ON, each ON output drops more voltage and
current. Forthe best case of six segments (a "111" display)
to worst case (a "1888" display), the resistor circuit will
change about 230 mW, while a circuit without the resistor will
change about 470 mW. Therefore, the resistor will reduce
the effect of display dissipation on reference voltage drift by
about 50%.
The change in LED brightness caused by the resistor is
almost unnoticeable as more segments turn off. If display
brightness remaining steady is very important to the designer, a diode may be used instead of the resistor.
1-147
3-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTERS WITH HOLD
TC7116
TC7116A
TC7117
TC7117A
1.50,l/4W
,-'VV'v-,
lN4OO1
'_~-_I
Figure 17
Figure 18
TC7117ITC7117 A Output Current vs Output Voltage
1-148
Diode or Resistor Limits Package Power Dissipation
"~TELEDYNE
COMPONENTS
TC7126
TC7126A
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
TYPICAL APPUCATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Temperature Drift Internal Reference
TC7126 •.........•..•.....•.•..•..•..........•. 80 ppmf'C Typ
TC7126A ..................................... 35 ppmf'C Typ
Guaranteed Zero Reading With Zero Input
Low Noise'.................................................... 15~Vp.p
High Resolution ....•......•....•.•...•............•..•....... 0.050/0
Wide Dynamic Range ......................................72 dB
Low Input Leakage Current ....................... 1 pA Typ
10 pA Max
Direct LCD Drive - No External Components
Precision Null Detectors With True Polarity at Zero
High-Impedance Differential Input
Convenient 9V Battery Operation With
Low Power Dissipation ......................... 500 J.LO Typ
900 J.LO Max
Internal Clock Circuit
Improved Drop-In Replacement for ICL7126 That
Offers Low Analog Common Voltage Drift
Available in Compact Flat Package
Industrial Temperature Range Device Available
Thermometry
Bridge Readouts
- Strain Gauges
-Load Cells
- Null Detectors
Digital Meters
- VoltagelCurrent/OhmsIPower
-pH
- CapacitanceJInductance
- Fluid Flow RateNiscositylLevel
-Humidity
-Position
Digital Scales
Panel Meters
LVDT Indicators
Portable Instrumentation
Power Supply Readouts
Process Monitors
Gaussometers
Photometers
•
•
•
•
•
•
•
•
•
TYPICAL OPERATING CIRCUIT
34
31
v~
30
viN
9-19 SEGMENT
22-25 DRIVE
POL
BP
32 ANALOG
COMMON
..--_2""B'i VBUFF
180kn
0.15 11F
v+
1
.,'"
TC7126
TC7126A
36
V~EF I-='---to<
VREF 1-'3~5_ _..
V- 26
L-_2
__7... V1NT
1 CONVERSION/SEC
OSC2
39
TO ANALOG COMMON
(PIN 32)
NOTE: Pin numbers refer to 4O-pin DIP.
560kn
1078-1
1-149
3-112 DIGIT
ANALOG-TO-DIGITAL CONV.ERTER
TC7126
TC7126A
GENERAL DESCRIPTION
The TC7126A features a precision, low-drift intemal
voltage reference and is functionally identical to the TC7126.
A low-drift extemal reference is not normally required with the
TC7126A.
The TC7126A is a 3-1/2 digit CMOSanalog-tb-digital
converter (ADC) containing all the active components necessary to construct a 0.05% resolution measurement system.
Seven-segment decoders, digit and polarity drivers, voltage
reference, and clock circuit are integrated on-chip. The
TC7126A directly drives a liquid crystal display (LCD), and
includes a backplane driver.
A loW-COst, high-resolution indicating meter requires only
a display, four resistors, and four capacitors. The TC7126A's
extremely low power drain and 9V battery operation make it
ideal for portable applications.
The TC7126A reduces linearity error to less than 1 count.
Roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below ±1 count.
High-impedance differential inputs offer 1·pA leakage current
and a 10120 input impedance. The 15 IlVp-p noise performance guarantees a "rock solid' reading, and the auto-zero
cycle guarantees a zero display reading with a OV input.
The TC7126A's dual-slope conversion technique automatically rejects interference signals if the converter's integration time is setto a multiple oftheinterference period. This
is especially useful in industrial measurement environments
where 50-Hz, 60-Hz, and 400-Hz line frequency signals are
present.
ORDERING INFORMATION
Part No.
TC7126CPL
TC7126ACPL
TC7126RCPL
TC7126ARCPL
TC71261PL
TC7126CJL
TC71261JL
TC7126AIJL
TC7126C80
TC7126AC80
TC7126CKW
TC7126ACKW
TC7126CLW
TC7126ACLW
Package
Pin Layout
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-CerDIP
40-CerDIP
40-CerDIP
60-Pin Plastic Flat
60-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin Plastic Flat
44-Pin PLCC
44-Pin PLCC
Normal
Normal
Reversed
Reversed
Temp Range
O·C to +70·C
O·C to +70·C
O·C to +70·C
O·Cto +70·C
25·Cto +85·C
O·C to +70·C
25·C to +85·C
25·C to +85·C
O·C to +70·C
O·C to +70·C
O·C to +70·C
O·C to +70·C
O·Cto +70·C
O·C to +70·C
PIN CONFIGURATIONS
.,,,
.,,,
3 COMMON
TC7126CKW
TC7126ACKW
(FLAT PACKAGE)
TC7126ClW
TC7126AClW
. (PlCC)
1 VeUFF
1-150
Ref Tempco (Max)
80ppm/·C
35 ppm/·C
80 ppm/·C
35 ppm/·C
80 ppm/·C
80 ppm/·C
80 ppm/·C
35 ppm/·C
80 ppm/·C
35 ppm/·C
80 ppm/·C
35 ppm/DC
80 ppm/·C
35 ppm/·C
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
PIN CONFIGURATIONS (Cont.)
I"'
OSC1
OSC1
OSC2
OSC2
OSC3
OSC3
V~EF
V~EF 5
A1
ViiEF
ViiEF
6
F1
7
G1
8
E1
C~EF
C~EF
C2
CiiEF
ANALOG
COMMON
~
100's
L
VIN
VIN
A2
CAZ
CAZ
F2
VBUFF
E2
VINT
V-
03
F3
3
E3
A3
G3
1000's_ AB4
POL
(MINUS SIGN)
O2
1
J
V-
I
G2
B3
C3
F3
L
A3
E3
100's
E2
03
JOO'S
AB4 .... 1000·s
G3
BP
(BACKPLANE)
BP
(BACKPLANE)
10's
F2
VINT
100's
B2
~~
VBUFF
~2l
B3
1's
C2
vtN
vtN
1
~l
C1
B1
CiiEF
ANALOG
COMMON
B2
3
TEST
1's
10's
v+
POL
(MINUS SIGN)
NC = NO INTERNAL CONNECTION
I
>
0
z
o
ID
...J
;:) CO) a.. 0
Z0CJtDa..
.,,,
TC7126CBQ
TC7126ACBQ
NOTES:
1. NC = No inlernal connection.
2. Pins 8. 23, 38 and 63 are connected to the
die substrate. The potential at these pins is
approXimately V+. No external connections
should be made.
~g~~>ocr
o
1-151
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to V-) ......................................... +15V
Analog Input Voltage (Either Input) (Note 1) ........ V+ to VReference Input Voltage (Either Input) ................. V+ to VClock Input .................... : ................................. TEST to V+
Operating Temperature Range
C Devices .............................................. O°C to + 70°C
I Devices ............................................ -25°C to +85°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................. +300°C
ELECTRICAL CHARACTERISTICS:
Symbol
Power Dissipation (Note 2)
CerDIP (J) .................................................... 1000 mW
Plastic DIP (P) ............................................... 800 mW
Plastic Flat Package, PLCC (B, K, L) ............ 500 mW
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions jlbove those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
VS = +9V, fCLK = 16 kHz, and TA= +25°C, unless otherwise noted.
Parameter
Test Conditions
Zero Input Reading
VIN= OV
Full Scale = 200 mV
Zero Reading Drift
Min
Typ
Max
-000.0
±OOO.O
+000.0
Unit
Input
VIN = OV, O·C ~ TA ~ +70·C
-
0.2
1
Ratiometric Reading
VIN = VREF, VREF = 100 mV
999
999/1000
1000
NL
Linearity Error
Full Scale 200 mV or 2V
Max Deviation From Best Fit
Straight Line
-1
±0.2
1
Roll-Over Error
-VIN
-1
±0.2
eN
IL
CMRR
Noise
Input Leakage Current
VIN
-
15
VIN= OV
-
1
Common-Mode Rejection
Ratio
VCM = ±1 V, VIN OV,
Full Scale 200 mV
-
50
Scale Factor Temperature
Coefficient
VIN 199 mV, O·C ~ TA ~+70·C
Ext Ref Temp Coeff 0 ppm/°C
-
=
=+VIN = 200 mV
=OV, Full Scale =200 mV
=
=
=
=
1
-
Digttal
Reading
IJ.V/·C
Digttal
Reading
Count
Count
IJ.Vp.p
10
pA
-
IJ.VN
1
5
ppm/·C
-
SO
35
75
ppm/·C
ppm/°C
35
100
ppm/·C
2.7
3.05
3.35
V
Analog Common
Analog Common Vokage
250 k.Q Between Common and V+
O·C ~ TA ~ +70·C ("C' Devices):
TC7126
TC7126A
-25·C ~ TA ~ +S5·C ("I" Device):
TC7126A
250 k.Q Between Common and V+
LCD Segment Drive Voltage
V+to V = 9V
Vp.p
LCD Backplane Drive Voltage
V+ to V- = 9V
Vp.p
Analog Common
Temperature Coefficient
VCTC
Vc
LCD Drive
VSO
VBO
Power Supply
Power Supply Current
VIN = OV, V+ to V = 9V (Note 6)
55
100
IJ.A
Input voltage may axceed supply voltages when input current is limited to 100 IJ.A.
Dissipation rating assumes device is mounted with all leads soldered to PC board.
Refer to 'Differential Input' discussion.
Backplane drive is in·phase with segment drive for 'off' segment and 180° out-of·phase for 'on' segment. Frequency is 20 times
conversion rate. Average DC component is less than 50 mY.
5. See 'Typical Operating Circuit.'
6. During auto-zero phase, current is 10-20 IJ.A higher. A 48 kHz oscillator increases current by 81J.A (typical). Common current not
included.
Is
NOTES: 1.
2.
3.
4.
1·152
3·1/2 DIGIT
ANALOG·TO·DIGITAL CONVERTER
TC7126
TC7126A
PIN DESCRIPTION
4o-Pin DIP
Pin Number
(Reverse)
Normal
6O-Pin
Flat Package
Pin Number
Name
Positive supply voltage.
Description
(40)
13
V+
2
(39)
14
01
Activates the 0 section of the units display.
3
(38)
15
C1
Activates the C section of the units display.
4
(37)
16
B1
Activates the B section of the units display.
5
(36)
17
A1
Activates the A section of the units display.
6
(35)
18
Activates the F section of the units display.
7
(34)
19
F1
G1
8
(33)
20
Activates the E section of the units display.
Activates the G section of the units display.
9
(32)
21
E1
O2
10
(31)
(30)
C2
B2
Activates the C section of the tens display.
11
25
26
12
(29)
27
A2
Activates the A section of the tens display.
13
(28)
28
F2
Activates the F section of the tens display.
14
(27)
29
E2
Activates the E section of the tens display.
15
(26)
30
03
Activates the D section of the hundreds display.
16
(25)
31
B3
Activates the B section of the hundreds display.
17
(24)
32
F3
Activates the F section of the hundreds display.
18
(23)
33
E3
Activates the E section of the hundreds display.
19
(22)
34
20
(21)
35
AB4
POL
Activates the 0 section of the tens display.
Activates the B section of the tens display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
21
(20)
36
BP
Backplane drive output.
22
(19)
37
G3
Activates the G section of the hundreds display.
23
(18)
40
(17)
41
A3
C3
Activates the A section of the hundreds display.
24
25
(16)
43
G2
Activates the G section of the tens display.
26
(15)
45
V-
27
(14)
46
VINT
28
(13)
47
VBUFF
29
(12)
49
CAZ
The size of the auto-zero capacitor influences system noise. Use a
0.33 IlF capacitor for 200 mV full scale, and a 0.033 IlF capacitor for 2V
full scale. See paragraph on auto-zero capacitor for more details.
VIN
VIN+
The low input signal is connected to this pin.
30
(11 )
51
31
(10)
55
32
(9)
57
ANALOG
COMMON
33
(8)
58
CREF
Activates the C section of the hundreds display.
Negative power supply voltage.
The integrating capacitor should be selected to give the maximum
voltage swing that ensures component tolerance build-up will not allow
the integrator output to saturate. When analog common is used as a
reference and the conversion rate is 3 readings per second, a 0.047 IlF
capacitor may be used. The capacitor must have a low dielectric
constant to prevent roll-over errors. See "Integrating Capacitor" section
for additional details.
Integration resistor connection. Use a 180 kO resistor for a 200 mV fullscale range and a 1.8 MO resistor for a 2V fUll-scale range.
The high input signal is connected to this pin.
This pin is primarily used to set the analog common-mode voltage for
battery operation or in systems where the input signal is referenced to
the power supply. See paragraph on analog common for more details. It
also acts as a reference voltage source.
See pin 34.
1-153
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
PIN DESCRIPTION (Cont.)
40-Pin DIP
Pin Number
(Reverse)
Normal
60-Pin
Flat Package
Pin Number
Name
(7)
59
35
(6)
60
36
(5)
37
(4)
3
TEST
38
(3)
39
(2)
(1)
4
6
OSC:z
34
40
Description
A 0.1 J.1F capacitor is used in most applications. If a large common-mode
vottage exists (for example, the VIN- pin is not at analog common), and a
200 mV scale is used, a 1 J.1F capacitor is recommended and will hold
the roll-over error to 0.5 count.
See pin 36.
The analog input required to generate a full-scale output (1999 counts).
Place 100 mV between pins 35 and 36 for 199.9 mV full scale. Place 1 V
between pins 35 and 36 for 2V full scale. See paragraph on reference
voltage.
Lamp test. When pulled high (to V+), all segments will be turned on and
the display should read -188S. It may also be used as a negative supply
for externally-generated decimal points. See paragraph under test for
additional information.
See pin 40.
10
See pin 40.
Pins 40, 39 and 38 make up the oscillator section. For a 4S kHz clock (3
readings per second), connect pin 40 to the junction of a 1SO k.Q resistor
and a 50 pF capacitor. The 180 k.Q resistor is tied to pin 39 and the
50 pF capacitor is tied to pin 38.
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
The TC7126A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7126A
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
REF
VOLTAGE
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period (tSI), measured by counting clock pulses. An
opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal (tAl).
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "ramp-down."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
Figure 1
_
1
RC
f
tsl
0
VIN(t) dt
~lIic
Dual-Slope Converter
where:
= V R t RI
VR = Reference voltage
tSI = Signal integration time (fixed)
tAl = Reference voltage integration time (variable).
RC'
1-154
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
30
\
V,
\
~
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on
CAZ compensates for device offset voHages. The auto-zero
phase residual is typically 10 11V to 15 11V.
The auto-zero cycle length is 1000 to 3000 clock
periods.
\jP
,y'
,,
Signal Integration Phase
The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN-. The differential input
signal is integrated for a fixed time period. The TC7126A
signal integration period is 1000 clock periods, or counts.
The externally-set clock frequency is +4 before clocking the
internal counters. The integration time period is:
IJ
o
~~
~
II
li
ITEASUjEMjNTtiRlll1
lit
0.11t
1011
INPUT FREQUENCY
Figure 2
tSI = _4_ X 1000,
fose
Normal-Mode Rejection of Dual-Slope Converter
For a constant VIN:
where fose = external clock frequency.
tRI]
VIN = VR [ tSI·
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
Interfering signals with frequency components at mUHiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
ANALOG SECTION
In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC7126A design incorporates an auto-zero cycle. This cycle removes buffer
amplifier, integrator, and comparator offset voltage error
terms from the conversion. A true digital zero reading results
without external adjusting potentiometers. A complete conversion consists of three phases:
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, VIN- should be tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that signals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
Reference Integrate Phase
The third phase is reference integrate, or deintegrate.
VIN- is internally connected to analog common and VIN+ is
connected across the previously-charged reference capacitor. Circuitry within the chip ensures the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
(1) Auto-zero phase
1000~
(2) Signal integrate phase
VREF
(3) Reference integrate phase
DIGITAL SECTION
Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
The TC7126A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency +800. For 3 conversions per second the
backplane frequency is 60 Hz with a 5V nominal amplitude.
1-155
-t-t
(")(")
...........
........
NN
cncn
~
TYPICAL SEGMENT OUTPUT
,
y+
LCD
~'"
TC7126A
!1
'l!
iii
Co>
§
~
'"
8l ~
III
...g
C REF
+
RINT
CREF
VREF
VREF
f----~-?36------'?35
:~~_~~U.!'~+
V·
I'
I
I
I
I
I
I
I
I
viN~
I
I
~
I
I
I
f t6':~~~
Z
I
I
;6;'"
"1
~
~
r
I
ViN9----®___"?'~AZ-&-D-E-(·-)-t~-----------'
'- __I!!!. _____________ _
1" I
r
26
;~---------------,I
"
~TEST
oQ
~
o
I
C
I
1_--- '----O'si:;
I
L-I
i
40
C5
39
OSC1
Rosc
Cose
.-(')~
OW
Z'
<~
mN
:::DC
-t-
me
:::D-t
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
The TC7126A is a drop-in replacement for the TC7126
and ICL7126 that offers a greatly improved internal reference temperature coefficient. No external component value
changes are required to upgrade existing designs.
When a segment driver is in-phase with the backplane
signal, the segment is "OFF." An out-ot-phase segment
drive signal causes the segment to be "ON," or visible. This
AC drive configuration results in negligible DC voltage
across each LCD segment, ensuring long LCD life. The
polarity segment driver is "ON" for negative analog inputs. If
VIN+ and VIN- are reversed, this indicator would reverse.
On the TC7126A, when the test pin is pulled to V+, all
segments are turned "ON." The display reads -1888. During this mode, LCD segments have a constant DC voltage
impressed. Do not leave the display in this mode for more
than several minutes; LCDs may be destroyed if operated
with DC levels for extended periods.
The display font and segment drive assignment are
shown in Figure 4.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor (CAl)
The CAZ size has some influence on system noise. A
0.33 !J.F capacitor is recommended for 200 mV full-scale
applications where 1 LSB is 100 !J.V. A 0.033!J.F capacitor is
adequate for 2V full-scale applications. A Mylar-type dielectric capacitor is adequate.
Reference Voltage Capacitor (CREF)
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
phase is stored on CREF. A 0.1 !J.F capacitor is acceptable
when VREF- is tied to analog common. If a large commonmode voltage exists (VREF- ~ analog common) and the application requires a 200 mV full scale, increase CREF to
1 !J.F. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
System Timing
The oscillator frequency is +4 prior to clocking the internal decade counters. The three-phase measurement cycle
takes a total of 4000 counts (16,000 clock pulses). The 4000count cycle is independent of input signal magnitude.
Each phase of the measurement cycle has the following
length:
(1) Auto-zero phase: 1000 to 3000 counts
(4000 to 12,000 clock pulses)
For signals less than full scale, the auto-zero phase
is assigned the unused reference integrate time
period.
(2) Signal integrate:
1000 counts
(4000 clock pulses)
This time period is fixed. The integration period is:
tSI = 4000 [fo:cJ '
where fosc is the externally-set clock frequency.
(3) Reference integrate: 0 to 2000 counts
(0 to 8000 clock pulses)
Integrating Capacitor (CINT)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Due to the
TC7126A's superior analog common temperature coefficient specification, analog common will normally supply the
differential vo~age reference. For this case, a ±2V full-scale
integrator output swing is satisfactory. For 3 readings per
second (fosc = 48 kHz), a 0.047 !J.F value is suggested.
For 1 reading per second, 0.15 !J.F is recommended. If a
different oscillator frequency is used, CINT must be changed
in inverse proportion to maintain the nominal ±2V integrator
swing.
An exact expression for CINT is:
(4000) (
C INT=
DISPLAY FONT
i1000'ST100'ST10'sT1'Sl
I
Figure 4
0
0
01
'-'
'-'
'-' 1
(VFS \
~)
VINT
where: fosc = Clock frequency at pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing.
0123Lf56789
1__ I
1 )
fosc
At 3 readings per second, a 7500 resistor should be
placed in series with CINT. This increases accuracy by compensating for comparator delay. CINT must have low dielectric absorption to minimize roll-over error. An inexpensive
polypropylene capacitor is recommended.
Display Font and Segment Assignment
1-157
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
Integrating Resistor
(RINT)
The input buffer amplifier and integrator are designed
wijh Class A output stages. The output stage idling current
is 6 J.IA. The integrator and buffer can supply 1 J.IA drive
current with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region, but not so large
that PC board leakage currents induce errors. For a 200 mV
full scale, RINT is 180 1<0. A 2V full scale requires 1.8 Mil.
Component
Value
CAZ
RINT
CINT
NOTE:
DEVICE PIN FUNCTIONAL DESCRIPTION
Nominal Full-Scale Voltage
200mV
2V
0.331lF
180 kO
0.0331lF
1.8MO
0.047 J.lF
0.047 1lF
(Pin Numbers Refer to 40-Pin DIP)
Differential Signal Inputs
lose = 48 kHz (3 readings Pl'r sec).
Oscillator Components
Cosc should be 50 pF; Rosc is selected from the equation:
0.45
fosc=R"C.
For a 48 kHz clock (3 conversions per second), R = 180 1<0.
Note that fosc is +4 to generate the TC7126A's internal clock. The backplane drive signal is derived by dividing
fosc by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz,
40 kHz, 33-1/3 kHz, etc. should be selected. For 50 Hz
rejection, oscillator frequencies of 200 kHz, 100 kHz, 66-2/
3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that
40 kHz (2.5 readings per second) will reject both 50 Hz and
60 Hz (also 400 Hz and 440 Hz).
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Required Full-Scale Voltage"
200mV
2V
input voltage by two, the reference voltage should be set to
200 mY. This permits the transducer input to be used
directly.
The differential reference can also be used where a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature-measuring instrumentation.
A compensating. offset voltage can be applied between
analog common and VIN-. The transducer output is connected between VIN+ and analog common.
lOOmV
lV
In some applications, a scale factor other than unity may
exist between a transducer output voltage and the required
digijal reading. Assume, for example, a pressure transducer
output for 2000 Iblin. 2 is 400 mY. Rather than dividing the
VIN+ (Pin 31), VIN- (Pin 30)
The TC7126A is designed with true differential inputs
and accepts input signals within the input stage commonmode voltage range (VCM). Typical range is V+ -lV to V+1V. Common-mode voltages are removed from the system
when the TC7126A operates from a battery orfloating power
source (isolated from measured system), and VIN- is connected to analog common (VCOM). (See Figure 5.)
In systems where common-mode voltages exist, the
TC7126A's 86 dB common-mode rejection ratio minimizes
error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large
positive VCM exists in conjunction with a full-scale negative
differential signal. The negative signal drives the integrator
output positive along with VCM (see Figure 6.) For such
applications, the integrator output swing can be reduced
below the recommended 2V fUll-scale swing. The integrator
output will swing within 0.3V of V+ or V- without increased
linearity error.
Differential Reference
VREF+ (Pin 36), VREF- (Pin 35)
The reference voltage can be generated anywhere
within the V+ to V- power supply range.
To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
The TC7126A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable voltage, suitable for use as a voltage reference.
The temperature coefficient of analog common is typically
35 ppm/°C forthe TC7126A and 80 ppm/°Cforthe TC7126.
ANALOG COMMON (Pin 32)
The analog common pin is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.35V below V+. Analog common is
tied internally to an N-channel FET capable of sinking
100 J.IA. This FET will hold the common line at 3V should an
1-158
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7126
TC7126A
MEASURED
SYSTEM
9V
Figure 5
Common-Mode Voltage Removed in Battery Operation Wilh V,N
external load attempt to pull the common line toward V+.
Analog common source current is limited to 1 ~. Therefore,
analog common is easily pulled to a more negative voltage
(Le., below V+ -3V).
The TC7126A connects the internal VIN+ and VIN- inputs to analog common during the auto-zero phase. During
the reference-integrate phase, VIN- is connected to analog
common. If VIN- is not externally connected to analog common, a common-mode voltage exists, but is rejected by the
converter's 86 dB common-mode rejection ratio. In battery
operation, analog common and VIN- are usually connected,
removing common-mode voltage concems. In systems where
VIN- is connected to power supply ground or to a given
voltage, analog common should be connected to VIN-.
The analog common pin serves to set the analog section reference, or common point. The TC7126A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float)
with respect to the TC7126A's power source. The analog
=Analog Common
common potential of V+ -3V gives a 7V end of battery life
voltage. The common potential has a 0.001 %/% voltage
coefficient and a 15n output impedance.
With sufficiently high total supply voltage (V+-V- >7V),
analog common is a very stable potential with excellent
temperature stability (typically 35 ppm/°c). This potential
can be used to generate the TC7126A's reference voltage.
An external voltage reference will be unnecessary in most
cases because of the 35 pprnl°C temperature coefficient.
See "TC7126A Internal Voltage Reference" discussion.
TEST (Pin 37)
The test pin potential is 5V less than V+. Test may be
used as the negative power supply connection for external
CMOS logic. The test pin is tied to the internally-generated
negative logic supply through a soon resistor. The test pin
load should not be more than 1 mAo See "Digital Section" for
additional information on using test as a negative digital logic
supply.
If test is pulled high (to V+), all segments plus the minus
sign will be activated. Do not operate in this mode for more
than several minutes. With TEST= V+, the LCD segments
are impressed with a DC voltage which will destroy the LCD.
TC7126A Internal Voltage Reference
~
VI =
[VCM = VIN]
Where:
I
II = Integration lime = 4
f 000
osc
CI = Integration capacitor
RI
Integration resistor
=
Figure 6
Common-Mode Voltage Reduces Available Integrator
Swing (VCOM V,N)
*
The TC7126A's analog common voltage temperature
stability has been significantly improved (Figure 7). The "A"
version of the industry-standard TC7126 device allows
users to upgrade old systems and design new systems
without external voltage references. External Rand C values do not need to be changed. Figure 10 shows analog
common supplying necessary voltage reference for the
TC7126A.
1-159
3·1/2 DIGIT
ANALOG·TO·DIGITAL CONVERTER
TC7126
TC7126A
200
() 180 IE
Q.
...
NO
MAXIMUM
SPECIFIED
I.!!:: 160
Zloal 140 I-
::;;2
.,,,
TYPICAL
::;;-
120 l-
ott
UW
100
88
..Jw
«a:
80
Z::>
«~
I-
a:
w
60 l-
::;;
40 l-
0-
W
I-
20
,----1
I- GUARANTEED
-
MAXIMUM
TC7126A
NO
MAXIMUM
SPECIFIED
vREF
TYPICAL
I
I
I TYPICAL I
-'f'
I
10 k!l
VRl:F
ANALOG 32
COMMON
ICL7126
SET VREF = 1/2 VFULL SCALE
ICL7136
0
Figure 7
36
VREF
35
I
TC7126A
240 kn
Figure 8
Analog Common Temperature Coefficient
TC7126A Internal Voltage Reference Connection
APPLICATIONS INFORMATION
Flat Package
Liquid Crystal Display Sources
The TC7126A is available in an epoxy 60-pin formed
leads flat package. A test socket for the TC7126ACBQ
device is available:
Several manufacturers supply standard LCDs to interface with the TC7126A 3-1/2 digit analog-to-digital converter.
Part No.
IC 51·42
Manufacturer: Yamaichi
Distribution: Nepenthe Distribution
2471 East Bayshore
Suite 520
Palo Alto, CA 94043
(415) 856-9332
Representativ:
Part Numbers
Manufacturer
AddressIPhone
Crystaloid
Electronics
5282 Hudson Dr.,
Hudson, OH 44236
216-655-2429
C5335, H5535,
T5135, SX440
AND
770 Airport Blvd.,
Burlingame, CA 94010
415-347-9916
FE 0801,
FE 0203
VGI, Inc.
1800 Vernon St., Ste. 2
Roseville, CA 95678
916-783-7878
11048, 11126
Hamlin, Inc.
612 E. Lake St.,
Lake Mills, WI 53551
414-648-2361
3902,3933,3903
Ratiometric Resistance Measurements
'NOTE: Contact LCD manufacturer for full product listing/specifications.
Decimal Point and Annunciator Drive
The test pin is connected to the internally-generated
digital logic supply ground through a 5000 resistor. The test
pin may be used as the negative supply for external CMOS
gate segment drivers. LCD annunciators for decimal points,
low battery indication, or function indication may be added
without adding an additional supply. No more than 1 mA
should be supplied by the test pin. The test pin potential is
approximately 5Y below Y+.
The TC7126A's true differential input and differential
reference make ratiometric readings possible. In ratio metric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately-defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display
will read 1000. The displayed reading can be determined
from the following expression:
1-160
Displayed reading
=
RUNKNOWN
RSTANDARD
The display will overrange for
x 1000.
RUNKNOWN ;;.
2X
RSTANDARD.
3·1/2 DIGIT
ANALOG·TO-DIGITAL CONVERTER
TC7126
TC7126A
Simple Inverter fOf Filled De"imal Point
or DisplayAnnunciator
Y+
1-
y+
"C"
RSTANDARD
... - .
9-+-...--t yiN
4049
TC7126A
BP 21
RUNKNOWN
TO LCD
DECIMAL
POINT
TC7126A
o--_-IYit.i
l ____~TE~S!T~3~7--t:::::::~___oTO
ANALOG
COMMON
BACKPLANE
Multiple Decimal Point or
Annunciator Driver
Figllre 10
y+
y+
BP~------~~~
~
.,,,
Low Parta Count Ratiometric Resistance Measurement
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
TEST
Figure 9
YIN
Decimal Point and Annunciator Drives
27
o--"'-K>+-o-,
"C"
9Mn
TC7126A
YREF
YREF
ANALOG
COMMON
900 k.Q
YiN
90kn
YOUT
26
10 kn
COM
C1
C2
=3 pF TO 10 pF, YARIABLE
=
132 pF, YARIABLE
Figure 11
3-112 Digit True RMS AC DMM
1·161
Y-
40
3·1/2 DIGIT
ANALOG ..TO..DIGITAL CONVERTER
TC7126
TC7126A
300 k,Q
160k,Q
300kQ
y-
V+·
YiN
YiN
R1
SOk,Q
1N4148
SENSOR
R2
SOkQ
VREF
"'''
O.7%/"C
PTC
TC7126A
~--------~---,~VREF
"REF
COMMON
COMMON
Figure 12 Temperature Sen$or
Figur.13
Po.illv. Temp"rature Coefficient Reshltor
Temperature Sensor
9V
y
h
I
CONSTANTSV
+
V+
VOUT
ADJ
"''''
V+
VAEF
6111~ J1A~
...... YR Y
rL-NC 4
1
YRY
S
>SOIdl
3
REF02 TEMP 3
TEMPERATURE
DEPENDENT OUTPUT
R2
2~8
1/2
LM3S8
~
1
·'O~'I
1.86V @
+2SoC
GND
VREF
>
YiN
"'f'
TC712(;A
R1
< SOIdl
;>
1
YiN
COMMON
v-
J
14
1
Figure 14 Integrated Circuit T.mperature Sen,or
.,"TELEDYNE
COMPONENTS
TC7129
4..1/2 DIGIT ANALOG ..TO..DIGITAL CONVERTER
WITH ON ..CHIP LCD DRIVERS
FEATURES
•
•
•
•
•
Coynt Rese>lution ......................................... ±19,999
Rese>iution on 200 mV Scale ........................... 10 IlV
True Differential Input and Reference
Low Power Consumption .................... 500 J.LA at 9V
Direct LCD Driver for:
- 4-1/2 Digits
- Decimal Points
- Low-Battery Indicator
- Continuity Indicator
•
•
•
•
Overrange and Underrange Outputs
Range Select Input ............................................. 10:1
High Common-Mode Rejection Ratio .......... 110 dB
External Phase Compensation Not Required
TYPICAL OPERATING CIRCUIT
LOW BATTERY
CONTINUITY
-1.9.9.9.9
y+
.1 5pF
I
y+
+
-=-
9Y
* NOTE:
1079-1
RC network between pins 26 and 28 is not required.
1-163
10PF
4..1/2 DIGIT ANALOQ;.TO·DfGITAL
CONVERTER WITH ON·CHIP LCD DRIVERS
TC7129
latch-and-hold input to freeze the present reading. This
combination of features makes the TC7129 the ideal
choice for full-featured multimeter and digital measurement
applications.
GENERAL DESCRIPTION
The TC7129 is a 4·112 digit analog-to-digital converter
(ADC) that directly drives iii multiplexed liquid crystal display (LCD). Fabricated in high-performance. low-power
CMOS. the TC7129 ADC is designed specifically for highresolution. battery-powered digital multi meter applications.
A complete analog measurement instrument requires only
the TC7129. a few passive components. a reference. an
LCD. and a battery. Power consumption is low. only 500
f.IA from a 9V battery. The traditional dual-slope method of
AID conversion has been enhanced with a successive
integration technique to produce readings accurate to bet.
ter than 0.005% of full scale. and resolution down to 10 ~V
per count.
The TC7129 includes featureS important to multimeter
applications. It detects and indicates low-battery condition.
A continuity output drives an annunciator on the display. and
can be used with an external driver to sound an audible
alarm. Overrange and underrange outputs and a rangechange input provide the ability to create auto-ranging
instruments. For snapshot readings. the TC7129 includes a
ORDERING INFORMATION
T,mp,rature
Pin
Part No.
Layout
Package
Range
TC7129CPL
Normal
O·Cto +70·C
TC7129RCPL
Reversed
TC7129CJL
Normal
TC7129CKW
Formed
40-Pin
Plastic DIP
40-Pin
Plastic DIP
40-Pin
CerOlP
44-Pin
Plastic Flat
44-Pin
PLCC
60-Pin
Plastic Flat
TC7129CLW
TC7129CBQ
Formed
O·Cto +70·C
O·C to +70·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70·C
PIN CONFIGURATIONS
"2fCJo BATT 2
",Q•••• 3
F.. ~. DP, '
,,.c;:,,.,INUS 5
.,,,
TC7'2~KW
... ~••• 7
F", ..,DP:J •
' .. C"BCs
ANN~UN",:'~:.::~ 4
A,.G,.D, •
F,. e,. DP, •
~ ••
~~~"
Q~
3m~
~$~{!d'~~j~
'r.;rr==n;;n;;rr;;;n;;;n;;r-r;;(
C•• LO eATT
A•• 0 •• D.
•
e•. DP,
•
F••
Ca. MINUS ,.
Fz,EzoDPZ 1
A,. o~. Da 11
F•• E•• DP. ,.
lilaoC"MlNUS 11
~~.
gl~;ru~
LINes
•
.... 0.".10
A30Q~
B4' C" Be, 13
A,.G,. DC 14
NC'
DJ 1
F:Jo 13, PP3
1
a. (;4, It,
1
A",a. D4 1
F.. E. DP 4
1-164
.'7'l,::,rr.:nr::rr.::n::n:::rr.:rr::rr.:::n::=n::r,.... INT QUT
4·1/2 DIGIT ANALOG·TO~DIGITAL
CONVERtER WITH ON·CHIP LCD DRIVI:RS
TC7129
ABSOLUTt: MAXIMUM RAtINGS
Notes: Input voltages may exceed supply voltages, provided input current
is limited 1o±400 IIA. Currents above this value may result in invalid display
readings but wUl not destroy the device if limited to ±1 mAo
DiSSipation ratings assume device is mouhtad with all leads soldered to
printed circuit board.
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
abovEl thOse listed under Absolute Maximum Ratings may cause permanent demage to the device. These are stress ratings only and functional
operation of ths device at these or any other conditions above those
indicatad in the operational sections 01 the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
Supply Voltage (V+ to V-) ........ ,..... ,........................... +15V
Reference Voltage (REF HI or REF LO) ............... V+ to VInput Voltage (IN HI or IN LO) (Note 1) ................ V+ to VVOISP ................................................... V+ to DGND -().3V
Digital Input. Pins
1.2.19.20.21.22.27.37.39.40 .......... DGNO to V+
Analog Input. Pins 25. 29, 30 ............................... V+ to VPower Dissipation Plastic Package (Note 2) ..... ,.. 800 mW
Operating Temperature Range .................... o·C to +70"C
Storage Temperature Range .................. --65°C to +150°C
Lead Temperature (Soldering. 10 sec) .................. +300·0
ELECTRICAL CHARACTERISTICS:
Symbol
V+ to V- =: 9V. VREF = 1V. TA '" +25°C. felK;: 120 kHz. unless otherwise
indicated. Pin numbers refer to 40-pin DIP.
I Min
Parameter
test Conditions
Zero Input Reading
Zero REladin9 Drift
Ratiometrie Reading
Range ChangEl Accuracy
VIN " OV. 200 mV Scale
VIN =OV, O°C < TA < +70°C
VIN: VREF '" 1000 mV, Range =2V
VIN =0.1 V on Low Range
+VIN =1V on High Range
-VIN = +VIN = 199 mV
~OO mVScale
VCM =1V. VIN = OV. 200 mV Scale
VIN: OV
200mVSeale
V,N" ov
200mV Scale
VIN " OV, Pins 32, 33
VIN'" 199 mY. O°C < TA < +70°C
External VREF =0 ppml"C
Typ
Max
IUnit
Input
RE
NL
CMRR
CMVR
eN
11/.
POYler
VCOM
DGND
Is
lCLK
Roll-Over Error
Linearity Error
Common-Mode Rejection Ratio
Common-Mode Voltage Range
Noise (Peak-to-Peak Value Not
Exceeded 95% 01 Time)
Input Leakage Current
Scale Factor Temperature
Coefficient
Common Voltage
Common Sink Current
Cornman Source Current
Dignal Ground Voltage
Sink Current
Supply Voltage Range
Supply Current Excluding Common Current
Clock Frequency
VOISP Resistancs
Low-Battery Flag Activation Voltage
V+to Pin ~8
AComrnon '" +0.1 V
AGornmon " -0.1 V
V+ to Pili 36, V+ to VADGND =+0.5V
V+toV
V+to V 9V
Continuity Comparator
Threshold Voltages
Pull-Down Current
"Weak Output" Current
Sink/Source
Pin 22 Source Current
Pin 22 Sink Current
Your Pin 27 =High
VOUT Pin 27 '" Low
Pins 37. 38. 39
Pins 20. 21 Sink/Source
Pin 27 Sink/Source
-0000
OOM
±D.5
9997
9999
0.9999 1.0000
-
-
-
-~
-
-
=
VOISPtoV+
V+to V-
2
-
-~
Counts
Counts
dB
V
V
IJ.Vp-p
10
7
pA
ppml°C
-
3.2
0.6
3.5
V
mA
4.5
5.3
-6
--
6.3
10
1.2
9
0.5
120
60
7.2
Digital
100
---
~
1-165
-
1
2
-
2.8
=9V
1
1
110
(V-) +1.5
(V+)-l
14
+0000 Counts
IJ.V/oC
10000 Counts
1.0001 Ratio
200
200
2
3/3
3/9
40
3
-
-
5.8
JJ.A
1
360
V
mA
V
mA
kHz
7.7
V
-12
-
400
10
---
kQ
mV
mV
I!A
IJ.A
IJ.A
IJ.A
IJ.A
4;01/2 DIGIT ANALOG ..TO-DIGITAL
CONVERTER WITH ON"CHIP LCD DRIVERS
TC7129
PIN DESCRIPTIONS (Pin Numbers Refer to 40-Pin DIP)
Name
Function
Pin
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSC,
OSes
AUNUNCIATOR
DRIVE
B,.C,.CONT
A,.G,.D,
B2• C2. LO BATT
A2. G2. D2
F2. E2. DP2
B3. C3. MINUS
Aa. G3. D3
Fa. Ea. DPa
B4. C4. BCs
~.D4.G4
F4• E4• DP4
BP3
BP2
BP, .
VDlSP
DP.v0R
21
DPa/UR
22
LATCHIHOLD
23
24
25
26
27
VV+
INTIN
INTOUT
CONTINUITY
28
COMMON
29
30
31
32
33
34
35
36
37
38
39
40
CREF+
CREFBUFFER
INLO
IN HI
REFHI
REFLO
DGND
RANGE
DP2
DP,
OSC2
Input to first clock inverter.
Output of second clock inverter.
Backplane square-wave output for driving annunciators.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Backplane #3 output to display.
Backplane #2 output to display.
Backplane #1 output to display.
Negative rail for display drivers.
Input: When HI. turns on most significant decimal point.
Output: Pulled HI when result count exceeds ±19.999.
Input: Second most significant decimal point on when HI.
Output: Pulled HI when result count is less than ±l 000.
Input: When floating. ADC operates in the free-run mode. When pulled HI. the last displayed
reading is held. When pulled LO. the result counter contents are shown incrememing during the
deintegrate phase of cycle.
Output: Negative-going edge occurs when the data latches are updated. Can be used tor
converter status signal.
Negative power supply terminal.
Positive power supply terminal and positive rail for display drivers.
Input to integrator amplnier.
Output of integrator amplnier.
Input: When LO. continuity flag on the display is off. When HI. continuity flag is on.
Output: HI when voltage between inputs is less than +200 mY. LO when voltage between inputs
is more than +200 mY.
Sets common-mode voltage of 3.2V below V+ for DE. lOX. etc. Can be used as preregulator for
external reference.
Positive side of external reference capacitor.
Negative side of external reference capacitor.
Output of buffer amplifier.
Negative input voltage terminal.
Positive input voltage terminal.
Positive reference voltage input terminal.
Negative reference voltage input terminal.
Internal ground reference for digital section. See "±5V Power Supply· paragraph.
3!lA pull-down for 200 mV scale. Pulled HI externally for 2V scale.
Internal31lA pull-down. When HI. decimal point 2 will be on.
Internal 3 !lA pull-down. When HI. decimal point 1 will be on.
Output of first clock inverter. Input of second clock inverter.
1-166
4·1/2 DIGIT ANALOG"TO·DIGITAL
CONVERTER WITH ON·CHIP LCD DRIVERS
TC7129
COMPONENT SELECTION
The TC7129 is designed to be the heart of a highresolution analog measurement instrument. The only additional components required are a few passive elements, a
voltage reference, an LCD, and a power source. Most
component values are not critical; sUbstitutes can be chosen
based on the information given below.
The basic circuit for a digital multimeter application is
shown in Figure 1 . See "Special Applications" for variations.
Typical values for each component are shown. The sections
below give component selection criteria.
Oscillator (Xosc.
COl. C02. Ro)
The primary criterion for selecting the crystal oscillator
is to chose a frequency that achieves maximum rejection of
line-frequency noise. To do this, the integration phase
should last an integral number of line cycles. The integration
phase of the TC7129 is 10,000 clock cycles on the 200 mV
range and 1000 clock cycles on the 2V range. One clock
cycle is equalto two oscillator cycles. For 60 Hz rejection, the
oscillator frequency should be chosen so the period of one
line cycle equals the integration time for the 2V range:
1/60 second", 16.7 ms
giving an oscillator frequency of 120 kHz. A similar calculation gives an optimum frequency of 1 00 kHz for 50 Hz
rejection.
The resistor and capacitor values are not critical; those
shown work for most applications. In some situations the
capacitor values may have to be adjusted to compensat~ for
parasitic capacitance in the circuit. The capacitors can be
low-cost ceramic devices.
LOW BATTERY
10kn
+
-=-
9V
RBIAS
Figure 1
Standard Circuit
1·167
=
1000 clock cycles * 2 osc cycles/clock cycle
oscillator frequency
4·1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON·CHIP LCD DRIVERS
TC7129
Some applications can use a simple RC network instead
of a crystal oscillator. The RC oscillator has more potential
for jitter, especially in the least significant digit. See "RC
Oscillator."
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptable high dielectric ab<'sorption.
Reference Capacitor (CREF)
Integrating Resistor (RINT)
The integrating resistor sets the charging current for the
integrating capacitor. Choose a value that provides a current
between 5 !lA and 20 !lA at 2V, the maximum full-scale
input. The typical value chosen gives a charging current of
13.3 !lA:
2V
ICHARGE = - - 13.3 !lA
150
kn
Too high a value for RINT increases the sensitivity to
noise pickup and increases errors due to leakage current.
Too Iowa value degrades the linearity of the integration,
leading to inaccurate readings.
.
Integrating Capacitor (CINT)
The charge stored in the integrating capacitor during
integrate phase is directly proportional to the input voltage.
The primary selection criterion for CINT is to choose a value
that gives the highest voltage swing while remaining within
the high-linearity portion of the integrator output range. An
integrator swing of 2V is the recommended value. The
capacitor value can be calculated from the equation:
CINT = tiNT * liNT,
VSWING
Voltage Reference (DREF. RREF. RaiAs. CRF)
A TC04 band-gap reference provides a high-stability
voltage reference of 1.25V. The reference potentiometer
(RREF) provides an adjustment for adjusting the reference
voltage; any value above 20 kW is adequate. The bias
resistor (RBlAs) limits the current through DREF to less than
150!lA. The reference filter capacitor (CRF) forms an RC
filter with RBIAS to help eliminate noise.
Input filter (RIF. CIF)
For added stability, an RC input noise filter is usually
included in the circuit. The input filter resistor value should
not exceed 100 kW. A typical RC time constant value is
16.7 ms to help reject line-frequency noise. The input filter
capacitor should have low leakage for high-impedance
input.
Battery
The typical circuit uses a 9V battery as a power source.
Any value between 6V and 12V can be used. For operation
from batteries with voltages lower than 6V and for operation
from power supplies. see "Powering the TC7129."
where tiNT is the integration time.
USing the values derived above (assuming 60 Hz
operation), the equation becomM:
SPECIAL APPLICATIONS
The TC7129 as a Replacement Part
C - 16.7ms *13.3!lA -01 F
INT 2V
- . I.J. .
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and Teflon
capacitors are usually suitable. A good measurement of the
dielectric absorption is to connect the reference capacitor
across the inputs by connecting:
Pinto Pin
20 -t33 (CREF+ to IN HI)
30-t 32 (CREF- to IN LO)
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion forthis component.
The value must be high enough to offset the effect of stray
capacitance at the capacitor terminals. A value of at least
1 I.J.F is recommended.
The TC7129 is a direct pin-for-pin replacement part for
the Intersil ICL7129. Note, however, that the Intersil part
requires a capacitor and resistor between pins 26 and 28 for
phase compensation. Since the TC7129 uses internal phase
compensation. these parts are not required and. in fact.
must be removed from the circuit for stable operation.
Powering the TC7129
While the most common power source for the TC7129
is a 9V battery. there are other possibilities. Some of the
more common ones are explained below.
1-168
4~1/2
DIGIT ANALOG·TO·DIGITAL
CONVERTER WITH ON·CHIP LCD DRIVERS
TC7129
±5V Power Supply
Measurements are made with respect to power supply
ground. DGND (pin 36) is set internally to about 5V less than
v+ (pin 24); it is not intended as a power supply input and
must not be tied directly to power supply ground. (It can be
used as a reference for external logic, as explained in
"Connecting to External Logic." (See Figure 2.)
~""
TC04
36
+_
3.8V
-TO
6V
REFLO
+5V
~"COM
28
TC7129
IN HI
33
8
INLO
V-
2
~"
~"
TC04
TC7660
.....-...J
REF LO 1-'3;.;:.5.....
35
+
32
23
4
5
36 DGND
0.11JF
~""
TC7129
0.1 IJF
IN HI ,",3;.;:.3_>-J\.AI"~ +
32
IN LO r----1~--O
Figure 3
Powering the TC7129 From a Low-Voltage Battery
+5V
-5V
Figure 2
Powering the TC7129 From
a ±5V Power Supply
~""
0.111F
Low-Voltage Battery Source
A battery with voltage between 3.8V and 6V can be used
to power the TC7129 when used with a voltage-doubler
circuit as shown in Figure 3. The voltage doubler uses the
TC7660 DC-to-DC voltage converter and two external capacitors.
36 DGND
0.111F
"'''
Measurements are made with respect to power supply
ground. COMMON (pin 28) is connected to REF LO (pin 35).
A voltage doubler is needed, since the supply voltage is less
than 6V minimum needed by the TC7129. DGND (pin 36)
must be isolated from power supply ground. (See Figure 4.)
33
+
TC7129
8
+5V Power Supply
TC04
V+
2
.,""
4
TC7MO
32
V23
10llF
5
Connecting to· External Logic
External logic can be directly referenced to DGND (pin
36), provided the supply current of the external logic does not
exceed the sink current of DGND (Figure 5). A safe value for
DGND sink current is 1.2 rnA. If the sink current is expected
to exceed this value, a buffer is recommended. (See Figure 6.)
1-169
Figure 4
Powering the TC7129 From a +5V Power Supply
4~1/2 DIGIT ANALOG~TO~DIGITAL
CONVERTER WITH ON~CHIP LCD DRIVERS
TC7129
y+
y+
24
24
EXTERNAL
LOGIC
"'''
TC7129
"'''
TC7129
'--_ _...........:..36, DGND
23
yFigure 5
External Logic Referenced Directly to DGND
Figure 6
External Logic Referenced to DCND With Buffer
Temperature Compensation
For most applications, VDlSP (pin 19) can be connected
directly to DGND (pin 36). For applications with a wide
temperature range, some LeOs require the drive levels vary
with temperature to maintain good viewing angle and display contrast. Figure 7 shows two circuits that can be
adjusted to give temperature compensation of about 10
mV/oC between V+ (pin 24) and VOISP. The diode between
OGNO and VOISP should have a low turn-on voltage because
VOISP cannot exceed 0.3V below OGND.
Y+
1N4148
y+
39k!l
24
200 k!l
24
"'''
"'''
TC7129
5k!l>-_--I
>-_+-..;.19~
TC7129
YDISP
' - - - -..........---1 YDISP
3& DCND
DGND
75 k!l
23
Figure 7
23
TeMperature Compensating Circuits
1-170
4-1/2 DIGIT ANALOG-TO-OIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
RC Oscillator
For applications in which 3-1/2 digit (100 I!V) resolution
is sufficient, an RC oscillator is adequate. A recommended
value for the capacitor is 51 pF. Other values can be used as
long as they are sufficiently larger than the circuit parasitic
capacitance. The resistor value is calculated from:
R = 0.45
freq *C
For 120 kHz frequency and C = 51 pF, the calculated
value of R is 75 kW. The RC oscillator and the crystal
oscillator circuits are shown in Figure 8.
measurement of the time to ramp the integrated voltage to
zero, and is therefore proportional to the input voltage being
measured. This count can then be scaled and displayed as
a measurement of the input Voltage. Figure g shows the
phases of the dual-slope conversion.
The dual-slope method has a fundamental limitation.
The count can only stop on a clock cycle, so that measurement accuracy is limited to the clock frequency. In addition,
a delay in the zero-crossing comparator can add to the
inaccuracy. Figure 10 shows these errors in an actual
measurement.
I
INTEGRATE
Measuring Techniques
I
~DEINTEGRATE~
Two important techniques are used in the TC7129:
successive integration and digital auto-zeroing. Successive
integration is a refinement to the traditional dual-slope
conversion technique.
Dual-Slope Conversion
A dual-slope conversion has two basic phases: integrate and deintegrate. During the integrate phase, the input
signal is integrated for a fixed period of time; the integrated
voltage level is thus proportional to the input voltage. During
the deintegrate phase, the integrated voltage is ramped
down at a fixed slope, and a counter counts the clock cycles
until the integrator voltage crosses zero. The count is a
"""'------ 40------
1
270 k.Q
5 pF
120 kHz
10 pF
v+o-j t--- ...
II:
0
II:
0
z
;:)
m
;:)
UI
I
2!:
> Ii.
...
II:
:;; u
0 z
U
CI
u u u
z z z
BUFF OUT 6
REF CAP- 7
0
...I
c(
REFCAP+ 8
z
c(
+INPUT 1
NOTES: 1. Ne = No internal connection.
2. Pins 6, 23, 38 and 53 are connected to the die substrate.
The potential at these pins is approximately V+. No external
connection should be made.
1-176
c(u II:
3
II:
;:)
2
..,,,
TC7135CLI
II:
0
I~t;
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Positive Supply Voltage .............................................. +6V
Negative Supply Voltage ............................................. -9V
Analog Input Voltage (Pin 9 or 10) .......... V+ to V- (Note 2)
Reference Input Voltage (Pin 2) ........................... V+ to VClock Input Voltage .............................................. OV to V+
Operating Temperature Range .................... O°C to +70°C
Storage Temperature Range .................. -65°C to +160°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
ELECTRICAL CHARACTERISTICS:
Package Power Dissipation
CerDIP (J) .............................................................. 1W
Plastic (P) ........................................................... O.BW
Static-sensitive device. Unused devices must be stored in conductive
material to protect them from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause permanent
damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
TA = +25°C, fCLocK = 120 kHz, V+ = +5V, V- = -5V (Figure 1)
Parameter
Test Conditions
Display Reading With
Zero Volt Input
Notes 2 and 3
NL
Zero Reading Temperature
Coefficient
Full-Scale Temperature
Coefficient
Nonlinearity Error
DNL
Differential Linearity Error
Note 6
Display Reading in
Ratiometric Operation
± Full-Scale Symmetry
Error (Roll-Over Error)
Y'N = VREF
Note 2
Symbol
Min
Typ
Max
-0.0000
±o.oooo
+0.0000
Y'N = OV
Note 4
-
0.5
2
~V/oC
Y'N = 2V
Notes 4 and 5
Note 6
-
-
5
ppml°C
-
0.5
1
Count
0.01
-
+0.9999
+1.0000
0.5
1
LSB
Display
Reading
Count
Unit
Analog
TCz
TCFS
±FSE
Input Leakage Current
Noise
liN
VN
+0.9998
-Y'N = +V'N
Note 7
-
Note 3
Peak-to-Peak Value Not
Exceeded 95% of Time
-
Display
Reading
1
10
pA
15
-
~Vp_p
-
-
..
-
Digital
I'l
hH
VOL
Input Low Current
Y'N = OV
10
100
~A
Input High Current
V'N=+5V
IOl= 1.6 mA
-
0.08
10
~A
-
0.2
0.4
V
IOH = 1 mA
IOH = 10~A
2.4
4.9
4.4
4.99
5
5
V
V
0
120
1200
4
5
-5
6
-8
1
0.7
8.5
3
mA
3
30
mA
mW
Output Low Voltage
Output High Voltage
B 1, B2, B4 , Be, 0 1-0 5
Busy, Polarity, Overrange,
Underrange, Strobe
VOH
Clock Frequency
felK
Power Supply
V+
Positive Supply Voltage
VNegative Supply Voltage
1+
1-
PO
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
Note 8
-3
Positive Supply Current
felK = 0 Hz
-
Negative Supply Current
Power Dissipation
felK = 0 Hz
felK = 0 Hz
-
-
kHz
V
V
_..
Limit input current to under 100 JlA if input voltages exceed supply voltage.
Full-scale voltage = 2V.
Y,N =OV.
O°C"" TA "" +70°C.
External reference temperature coefficient less than 0.01 ppmfOC.
-2V "" Y,N "" +2V. Error of reading from best fit straight line.
IV,NI = 1.9959.
Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at
higher operating frequencies.
1-179
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
ANALOG
INPUT BUFFER
"N
UNOERRANGE 28
< ...1--""""""1 REF IN
OVERRANGE 27
STROBE 26
25
RUN/HOLD
INTOUT
AZIN
BUFF OUT
+5V
OIGTALGNO
REF
IN
24
23
POLARITY
22
CLOCK IN
CiiEF
21
BUSY
C~EF
20
(LSD) 01
-INPUT
19
02
+INPUT
TC7135
18
03
V+
12 05 (MSO)
17
04
-=
CLOCK
INPUT
120 kHz
~'"
13 B1 (LSB)
14 B2
(MSB) B8
B4
-IN
o
SWITCH OPEN
•
SWITCH CLOSED
Figure 3B. System Zero Phase
16
15
ANALOG
INPUT BUFFER
Figure 1. Test Circuit
"N o-t"~-~-~H
REF
IN
-IN
o-t..---4-------..J
o
SWITCH OPEN
•
SWITCH CLOSED
Figure 3C. Input Signal Integration Phase
Figure 2. Digital Logic Input
ANALOG
INPUT BUFFER
ANALOG
INpUT BUFFER
"N
"N
REF
IN
REF
IN
-IN
-IN
o
SWITCH OPEN
•
SWITCH CLOSED
Figure 3D. Reference Voltage Integration Phase
Figure 3A. Internal Analog Switches
1-180
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
For a constant V,N:
ANALOG
INPUT BU FFER
VIN
-IN
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
(See Figure 4.)
REF
IN
-IN
o
SWITCH OPEN
•
SWITCH CLOSED
=VR [~l.
tSI]
TC7135 Operational Theory
Figure 3E. Integrator Output Zero Phase
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
The TC7135 measurement cycle contains four phases:
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7135
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
(1) System zero
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
Intemal analog gate status for each phase is shown in
Table I.
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated
until the integrator output voltage retums to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC
f
tsl
0
V,N(t) dt
ANALOG
INPUT
SIGNAL
0--<)
REF
VOLTAGE
POLARITY CONTROL
= VRRCtAl ,
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
Figure 4. Basic Dual-Slope Converter
H81
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Table I. Internal Analog Gate Status
Conversion
Cycle Phase
System Zero
Input Signal
Integration
Reference Vottage
Integration
Integrator
Output Zero
SWI
SWRI+
Internal Analog Gate Status
SWRISWz
SWR
SW1
Closed
Closed
3B
3C
Closed
3D
Closed
SWIZ
Reference
Schematic
Closed
Closed'
Closed
Closed
3E
'NOTE: Assumes a positive polarity input signal. SWAI- would be closed for a negative input signal.
System Zero Phase
During this phase, errors due to buffer, integrator, and
~omparator offset voltages are compensated for by chargIng CAl (auto-zero capacitor) with a compensating error
Voltage. W~h zero input voltage, the integrator output remains
at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The internal input pointsconnectto analog common. The reference
capacitor charges to the reference voltage potential through
SWR. A feedback loop, closed around the integrator and
comparator, charges the CAl with a voltage to compensate
forbufferamplifier, integrator, and comparator offset voltages.
(See Figure 3B.)
Analog Input Signal Integration Phase
The TC7135 integrates the differential voltage between
the +INPUT and -INPUT. The differential voltage must be
within the device's common-mode range; -1V from either
supply rail, typically.
The input signal polar~y is determined at the end of this
phase. (See Figure 3C)
Reference Voltage Integration Phase
The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator
output back to zero. (See Figure 3D.) The digital reading
displayed is:
Reading = 10,000 [Differential Input ] .
VREF
Analog Section Functional Description
Differential Inputs
Th~ TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin g) within the input amplifier
common-mode range which extends from 1V below the
pos~ive supply to 1V above the negative supply. Within this
common-mode voltage range, an 86 dB common-mode
rejection ratio is typical.
The integrator output also follows the common-mode
voltage and must not be allowed to saturate. A worst-case
condition exists, for example, when a large positive commonmode voltage with a near full-scale negative differential
input voltage is applied. The negative input signal drives the
integrator p~.sitive when most of ~s swing has been used up
by the positive common-mode voltage. For these critical
applications, the integrator swing can be reduced to less
than the recommended 4V full-scale swing, w~h some loss
of accuracy. The integrator output can swing w~hin 0.3V of
either supply without loss of linear~y.
Analog Common
ANALOG COMMON (pin 3) is used asthe-INPUT return
during the auto-zero and de integrate phases. If -INPUT is
di~ere~t from analog common, a common-mode voltage
eXists In the system. This signal is rejected by the excellent
CMRR of the converter. In most applications, -INPUT will be
~et at a fixed known voltage (power supply common, for
Instance). In this application, analog common should be tied
to the same point, thus removing the common-mode voltage
from the converter. The reference voltage is referenced to
analog common.
Integrator Output Zero Phase
Reference Voltage
This phase guarantees the integrator output is at OV
The reference voltage input (REF IN, pin 2) must be a
when the system zero phase is entered and that the true
pos~ive voltage with respect to analog common. Two refersystem offset voltages are compensated for. This phase
ence voltage circuits are shown in Figure 5.
norm.~lIy la~ts 100 to 200 clock cycles. If an overrange
condition eXists, the phase is extended to 6200 clock cycles.
(See Figure 3E.)
1·182
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Digital Section Functional Description
r-------------.---oV+
The major digital subsystems within the TC7135 are
illustrated in Figure 6, with timing relationships shown in
Figure 7. The multiplexed BCD output data can be displayed
on an LCD or LED display with the TC7211A (LCD) or
TC7212A (LED) 4-digit display drivers.
The digital section is best described through a discussion of the control signals and data outputs.
V+
~f'
REF
IN
TC7135
~IZ
RUN/HOLD Input
When left open, the RUNIHOLD (RIA) input (pin 25)
assumes a logic "1" level. With RIA = 1 , the TC7135 performs conversions continuously, with a new measurement
cycle beginning every 40,002 clock pulses.
When R/Hchanges to logic "0," the measurement cycle
in progress will be completed, and data held and displayed,
as long as the logic "0" condition exists.
A positive pulse (>300 ns) at RIA initiates a new measurement cycle. The measurement cycle in progress when
RIA initially assumed logic "0" must be completed before the
positive pulse can be recognized as a single conversion run
command.
The new measurement cycle begins with a 10,001count auto-zero phase. At the end of this phase, the busy
signal goes high.
VV+
6.8
V+
k.Q
~f'
TC04
~f' R~~
1.25V REF
TC7135
ANALOG
GROUND
Figure 5. Using an External Reference Voltage
POLARITY
MSB ~ DIGIT
DRIVE
MULTIPLEXER
FROM
ANALOG
SECTION
DIGITAL CLOCK
GND
IN
RUNI
HOLD
OVERRANGE
UNDERRANGE
Figure 6. Digital Section Functional Diagram
'-'83
BUSY
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
TC7135
OUTPUTS
INTEGRATOR
OUTPUT
SIGNAl
SYSTEM
ZERO IINTE
10,000
10,001 COUNTS
COUNTS (FIXED)
BUSY ~END OF CONVERSION
REFERENC~
INTEGRATE
~l'-------------------------------
20,001
B1-88 ""::;-:=::V-~:--II-;::--V--;:::--v.:~:::::1'-;::;-""'-
COUNTS (MAX)
~FULLM~~~~0~~1CYCLE
BUSY
--.J
1...._ _...,
OVERRANGE
APPlIC'l~~~ ~
os
UNDERRANGE ~
WHEN 'l'////....
APPLICABLE ."""",,;,Q,..-_..1
EXPANDEO SCALE
BELOW
L
I
DIGIT SCAN
~ ______j~L_____________________
COUNTS
OO __________~~L_________________
r1-....l'1...-. 05
.rL.-l'1...-.J" 04
--"-"--J"L 03
--IL......IL-1" 02
~
-l"L..-..I"L-
Dl--------------------~~~------
I
I
COUNTS
COUNTS-
01
COUNTS
'FIRST 05 OF SYSTEM ZERO
ANO REFERENCE INTEGRATE
STROBE ~i~i~i'i'i~~______~O~NE~C~O~U~N~T~LO~N~G=ER~.____
100
COUNTS
'DELAY BETWEEN BUSY GOING LOW ANO FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
SIGNAL
1- . AUTO ZERO
INTEGRATE
DIGIT S~~~ nL:0~5~________~ltLOVERRANGE
-l1~0~3______~t~
Figure 8. Strobe Signal Pulses Low FiYe Times per Conversion
____~
__
______
Jn~0~4_ _ _ _~l~
________________-J~1...___________
The active-low STROBE pulses aid BCD data transfer
to UARTs, microprocessors, and external latches. (See
Application Note AN-16.)
~
+-~
Figure 7. Timing Diagrams for Outputs
STROBE Output
During the measurement cycle, the STROBE output
(pin 26) control line is pulsed low five times. The five low
pulses occur in the center of the digit drive signals (D1, D2,
D3, D4 and D5; see Figure 8).
D5 goes high for 201 counts when the measurement
cycles end. In the center of D5 pulse, 101 clock pulses after
the end of the measurement cycle, the first STROBE occurs
for one-half clock pulse. After D5 strobe, D4 goes high for 200
clock pulses. STROBE goes low 100 clock pulses after D4
goes high. This continues through the D1 drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
BUSY Output
At the beginning of the signal-integration phase, BUSY
(pin 21) goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to logic "0"
after the measurement cycle ends in an overrange condition.
The internal display latches are loaded during the first clock
pulse after BUSY and are latched at the clock pulse end. The
BUSY signal does not go high at the beginning of the
measurement cycle, which starts with the auto-zero phase.
OVERRANGE Output
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVER RANGE
output (pin 27) is set to logic "1." The OVERRANGE output
register is set when BUSY goes low and reset at the
beginning of the next reference-integration phase.
UNDERRANGE Output
If the output count is 9% of full scale or less (,.;;1800
counts), the UNDERRANGE output (pin 28) register bit is
set at the end of BUSY. The bit is set low at the next signalintegration phase.
1-184
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
adequate. A 0.10~FtoO.47~F is recommended. In general,
the value of CINT is given by:
POLARITY Output
A positive input is registered by a logic "1" polarity signal.
The POLARITY output (pin 23) is valid at the beginning of
reference integrate and remains valid until determined during the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null applications.
CINT =
(10,000) (clock period) (20 ~)
Integrator output voltage swing·
A very important characteristic of the CINT is that it has
low dielectric absorption to prevent roll-over or ratio metric
errors. A good test for dielectric absorption is to use the
capacitor with the input tied to the reference. This ratio metric
condition should read half-scale 0.9999. Any deviation is
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Digit Drive Outputs
Oigit drive outputs are positive-going signals. Their scan
sequence is Os, 04, 03, 02 and 01 (pins 12, 17, 18, 19 and
20, respectively). All positive signals are 200 clock pulses
wide, except Os, which is 201 clock pulses.
All five digits are continuously scanned, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated, providing a blinking
visual display.
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor (CAz) has some influence on system noise. A large capacitor reduces noise.
The reference capacitor (CAEF) should be large enough such
that stray capacitance from its nodes to ground is negligible.
The dielectric absorption of CAEF and CAl is only important at power-on, or when the circuit is recovering from an
overload. Smaller or cheaper capacitors can be used if
accurate readings are not required during the first few
seconds of recovery.
BCD Data Outputs
The binary coded decimal (BCO) outputs, Ba, B4, B2 and
B1 (pins 16, 15, 14 and 13, respectively) are positive truelogic signals. They become active simultaneously with digit
drive signals. In an overrange condition, all data bits are
logic "0".
APPLICATIONS INFORMATION
Reference Voltage
Component Value Selection
The analog input required to generate a full-scale output
is VIN =2 VAEF.
The stability of the reference voltage is a major factor in
overall absolute accuracy of the converter. Therefore, it is
recommended that high-quality references be used where
high-accuracy, absolute measurements are being made.
Suitable references are:
Integrating Resistor
The integrating resistor (RINT) is determined by the fullscale input voltage and output current of the buffer used to
charge the integrator capacitor (CINT). Both the buffer amplifier and the integrator have a Class A output stage, with
100 ~ of quiescent current. A 20 ~ drive current gives
negligible linearity errors. Values of 5 ~ to 40 ~ give good
results. The exact value of RINT for a 20 ~ current is easily
calculated:
R
[10,000 x clock period] x hNT
Integrator output voltage swing
Part Type
TC04
MP5010
_ Full-scale voltage
INT20~
Manufacturer
Teledyne Components
Teledyne Components
Conversion Timing
Integrating Capacitor
The product of RINT and CINT should be selected to give
the maximum voltage swing to ensure tolerance build-up will
not saturate integrator swing (approximately 0.3V from
either supply). For±5V supplies, and analog common tied to
supply ground, a ±3.5V to ±4V full-scale integrator swing is
Line Frequency Rejection
A signal-integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 100 kHz clock frequency will reject 50 Hz, 60 Hz and
400 Hz noise, corresponding to 2.5 readings per second.
1-185
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Table II. Line Frequency Rejection
High-Speed Operation
Oscillator Frequency
(kHz)
Frequency Rejected
(Hz)
300,200,150,120,
100,40,33-1/3
60
250, 166-213,
50
125,100
100
50,60,400
Table III. Conversion Rate vs Clock Frequency
Conversion Rate
(Conv/Sec)
Clock
Frequency (kHz)
100
120
200
300
400
800
1200
2.5
3.0
5.0
7.5
10.0
20.0
30.0
Displays and Driver Circuits
Teledyne Components manufactures three display decoder/driver circuits to interlace the TC7135 to LCOs or LEO
displays. Each driver has 28 outputs for driving four 7segment digit displays. The TC700A features increased
LEO segment drive current for greater display brightness.
Device
Package
Description
TC7211AIPL
TC7212AIPL
40-Pin Epoxy
40-Pin Epoxy
4-Digh LCD Driver/Encoder
4-Digit LED Driver/Encoder
The maximum conversion rate of most dual-slope AOCs
is limited by frequency response of the comparator. The
comparator in this circuit follows the integrator ramp with a
3 !lsdelay, and at a clock frequency of 160 kHz (6!ls period),
half of the first reference integrate clock period is lost in
delay. This means the meter reading will change from 0 to
1 with a 50!lV input, 1 to 2 with 150 !lV, 2 to 3 with 250 !lV,
etc. This transition at mid-point is considered desirable by
most users; however, if clock frequency is increased appreciablyabove 160 kHz, the instrument will flash "1" on
noise peaks even when the input is shorted.
For many dedicated applications, where the input signal
is always of one polarity, comparator delay need not be a
limitation. Since nonlinearity and noise do not increase
substantially with frequency, clock rates up to -1 MHz may
be used. For a fixed clock frequency, the extra count (or
counts) caused by comparator delay will be constant and
can be digitally subtracted.
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage onto the
integrator output at the beginning of reference-integrate
phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be compensated for and maximum clock frequency extended
by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant
nonlinearities during the first few counts of the instrument.
The minimum clock frequency is established by leakage
on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no
measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means if the display takes significant current from the logic
supply, the clock should have good PSRR.
Several sources exist for LCOs and LEO displays.
Manufacturer
Address
Hewlett Packard
Components
AND
640 Page Mill Road
Palo Alto, CA 94304
770 Airport Blvd.
Burlingame, CA 94010
3415 Kanhi Kawa SI.
Torrance, CA 90505
Epson America, Inc.
Display
Type
LED
LCD and
LED
LCD
Zero-Crossing Flip-Flop
The flip-flop interrogates data once every clock pulse
after transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by
clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
1-186
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flipflop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zero gives an overload display of 0000 instead of 0001.
No delay occurs during signal integrate, so true ratio metric
readings result.
+5Y
y+
8
Y-
.,rTC7135
Generating a Negative Supply
11
1
(-6V)
.,r-
5
1
TC7660
10 ll F
4
24
A negative voltage can be generated from the positive
supply by using a TC7660. (See Figure 9.)
-=
10llF
Figure 9. Negative Supply Yoltage Generator
TYPICAL APPUCATIONS DIAGRAMS
RC Oscillator Circuit
Comparator Clock Circuit
+5Y
GATES ARE 74C04
O.22I1F
1. fo =
2 C[0.41 Rp + 0.70 R11
, Rp =
R1 R2
R1 + R2
a. If R = R1 = R2, f ;:; 0.55/RC
b. If R2 » R1, f;:; 0.45/R1C
c. If R2« R1, f;:; 0.721R1C
2. Examples:
a. f = 120 kHz, C = 420 pF
R1 = R2 = 10.9 kn
b. f = 120 kHz, C =420 pF, R2
R1 = 8.93 kn
=50 kn
c. f = 120 kHz, C =220 pF, R2
R1 =27.3kn
=5 kn
R2
100Jen
1-187
-=
4..1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
TYPICAL APPLICATIONS DIAGRAMS (Cont.)
4-112 Digit ADC With Multiplexed Common Anode LED Display
4
OA7pF
AZIN
100110
•• 'IN
1.0 kHz
100110
+
ANALOG
INpUT
10
..,,,
CHEF 7
TC7135
1 pF
CREF •
BLANK MSD ON ZERO
+INPUT
1 pF.
-INpUT
•
4.7110
POL 23
ANALOG
COMMON
B8
B4
B•
Bl
1&
• D
15
14
13
•1 C
B
7 A
4-112 Digit ADC Interfaced to LCD With Digit Blanking on Overrange
v
1I2CD4030
c::::...---=+:::::;:r-'
.2 D2
I
33 D3
•
3404
.:
120 kHz
..,,,
rr::::jI-t:·r··"'::·>-··...:C:::D40::·:.7r:.j:______+...l30~ alC7211A
:
1-188
29 B2
+5V
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
TYPICAL APPLICATIONS DIAGRAMS (Cont.)
4-112 Digit ADC With Multiplexed Common Cathode LED Display
oSV
oSV
~"
TC04
4 INT
-=-:--::--, OUT
5 AZIN
elK IN 22
BUSY 21
+_+_+_+_..J
oSV
(LSD)Dll'20~-_ _
-INPUT
10 +INPUT
~"
11 y+
TC713S
12 D5(MSD)
D2
D3
D4
1.
1.
17
(MS.) •• 16
15
••
' - - - - - O O fO ·120kHz
4-Channel Data Acquisition System
ADORESSBUS
I
I
CONTROL
~III
PAO
PAl
PA2
oSV
lY
2Y
3Y
157
6522
-VlA-
1.
2.
3B
SEL
lA
2A
3A
+INPUT
CHANNEL 2
CHANNEL 3
PA3
PM
PAS
PA6
PA7
CAl
CA2
Bl
01
VR
02
-INPUT
03
D4
ANALDO
STB COMMON
RIH
liN
GAIN SELECTION fiN
PBS
PB4
PB3
1-189
DIFFERENTIAL
MULTIPLEXER
NOTES
1-190
~"'TELEDYNE
COMPONENTS
TC7136
TC7136A
LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
FEATURES
TYPICAL APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast Overrange Recovery, Guaranteed First
Reading Accuracy
Low Temperature Drift Internal Reference
TC7136 ........................................ 70 ppmf'C Typ
TC7136A ........•........•................... 35 ppmf'C Typ
Guaranteed Zero Reading With Zero Input
Low Noise .................................................... 15 ~Vp_P
High Resolution ..•........•.................................. 0.05%
Wide Dynamic Range ...................................... 72 dB
Low Input Leakage Current ......................• 1 pA Typ
10 pA Max
Direct LCD Drive - No External Components
Precision Null Detectors With True Polarity at Zero
High-Impedance Differential Input
Convenient 9V Battery Operation With
Low Power Dissipation ......................... 500 ~W Typ
900~WMax
•
•
•
Internal Clock Circuit
Available in Compact Flat Package or PLCC
Industrial Temperature Range Device Available
•
•
•
•
•
•
•
•
•
Thermometry
Bridge Readouts
- Strain Gauges
-Load Cells
- Null Detectors
Digital Meters
- VoltagelCurrenUOhmslPower
-pH
- Capacitance/lnductance
- Fluid Flow Rate/ViscositylLevel
-Humidity
-Position
Digital Scales
Panel Meters
LVDT Indicators
Portable Instrumentation
Power Supply Readouts
Process Monitors
Gaussometers
Photometers
TYPICAL OPERATING CIRCUIT
34
1 M!l
+
ANALOG
INPUT
9-19 SEGMENT
22-25 DRIVE
viN
0.01 "F
yiN
POL
BP
ANALOG
COMMON
r----=2,8 VBUFF
180 k.Q
0.47
20
21
y+
4~
,. ..
TC7136
TC7136A
36
V~EF F:.............~
"F 29
CAZ
ViiEFI-:3:=5_ _..
O.lS"F
v-
,--......::2"-17 V1NT
OSC2
26
1 CONVERSIONISEC
39
ROSC SOpF
560 k.Q
1081-1
1·191
TO ANALOG COMMON
(PIN 32)
LOW POWER, 3·1/2 DIGIT
ANALOG·TO·DlGITAL CONVERTERS
TC7136
TC7136A
GENERAL DESCRIPTION
The TC7136 and TC7136A are low-power, 3-1/2 digit,
liquid crystal display (LCD), analog-to-digital converters
(ADCs). These devices incorporate an "integrator output
zero" phase which guarantees overrange recovery. The
performance of existing TC7126, TC7126A and ICL7126based systems may be upgraded with minor changes to
external, passive components.
The TC7136A has an improved internal zener reference voltage circuit which maintains the analog common
temperature drift to 35 ppm/°C (typical) and 75 ppm/°C
(maximum). This represents an improvement of two to four
times over similar 3-1/2 digit converters. The costly, spaceconsuming external reference source may be removed.
The TC7136 limits linearity error to less than 1 count
on 200 mV or 2V full-scale ranges. Roll-over error - the
difference in readings for equal magnitude but opposite
polarity input signals - is below ±1 count. High-impedance
differential inputs offer 1 pA leakage currents and a 10120
input impedance. The differential reference input allows
ratiometric measurements for ohms or bridge transducer
measurements. The 15 ~Vp_p noise performance guarantees a "rock solid" reading. The auto-zero cycle guarantees
a zero display readout for a OV input.
The single-chip CMOS TC7136 incorporates all the
active devices for a 3-1/2 digit ADC to directly drive an
LCD. The internal oscillator, precision voltage reference,
and display segmentlbackplane drivers simplify system
integration, reduce board space requirements and lower
total cost. A low-cost, high-resolution (0.05%) indicating
meter requires only a display, four resistors, four capacitors and a 9V battery. The flat package option eases the
mechanical design of low-cost, hand-held multimeters.
The TC7136A dual-slope conversion technique rejects
interference signals if the converter's integration time is set
to a multiple of the interference signal period. This is especially useful in industrial measurement environments where
50 Hz, 60 Hz, and 400 Hz line frequency signals are
present.
ORDERING INFORMATION
Part No.
TC7136ACPL
TC7136CPL
TC7136ARCPL
TC7136RCPL
TC7136AIJL
TC71361JL
TC7136ACKW
TC7136CKW
TC7136ACLW
TC7136CLW
Pin
Layout
Temperature
Range
40-Pin Plastic DIP
Normal
O°Cto +70°C
40-Pin Plastic DIP
Reversed
O°C to +70°C
40-Pin CerDIP
Normal
-25°C to +85°C
44-Pin Plastic Flat
Formed Leads
O°C to +70°C
Package
44-Pin PLCC
O°C to +70°C
1-192
Reference
Temperature
Coefficient (Max)
75 ppm/°C
150 ppm/°C
75 ppm/°C
150 ppm/°C
100 ppm/°C
150 ppm/°C
75 ppm/°C
150 ppm/°C
75 ppm/°C
150 ppm/°C
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
PIN CONFIGURATIONS
9 ...w
+a:
o
.,,,
.,,,
TC7136CLW
TC7136ACLW
(PLCC)
... ......
Ie
I
...
....
w
~
01
2
..J
~
Q.
Ie
TC7136CKW
TC7136ACKW
(FLAT PACKAGE)
... CC... 0...
CI
• NORMAL PIN
CONFIGURATION
N
~.:,;
CI
OSC1
OSC 1
OSC2
OSC2
10's
~L
100's
B2
A2
1
TC7136
TC7136A
5
A1
VREF
6
F1
CREF
7
G1
CREF
ANALOG
COMMON
yiN
8
E1
VIN
VIN
1
CAZ
CAZ
CREF
ANALOG
COMMON
yiN
VBUFF
E3
1000's~AB4
POL
(MINUS SIGN)
G2
C3
A3
G3
l
...
Q
C1
VREF
V,NT
V-
F3
N
w
VREF
F2
B3
N
CC
V REF
E2
03
.. .....
Ie
B1
CREF
.,,,
N
0
D'l
OSC3
C2
N
Q
V+
TEST
1's
..r
VBUFF
V,NT
V-
I
L
J
100's
100's
C3
A3
G3
BP
(BACKPLANE)
BP
(BACKPLANE)
NC
G2
=NO INTERNAL CONNECTION
1-193
1's
02
C2
B2
F2
"
E2
03
B3
F
10's
~
100's
E:J
AB4"-1OOO's
POL
(MINUS SIGN)
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to V-) ......................................... +15V
Analog Input Voltage (Either Input) (Note 1) ........ V+ to VReference Input Voltage (Either Input) ................. V+ to VClock Input ...................................................... TEST to V+
Power Dissipation (Note 2)
CerDIP (J) .................................................... 1000 mW
Plastic DIP (P) ............................................... 800 mW
Flat Package (K, L) ........................................ 500 mW
Operating Temperature Range
C Devices .............................................. O°C to +70°C
I Devices ............................................ -25°C to +85°C
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 60 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: VS = 9V, fClK = 16 kHz, and TA = +25°C, unless otherwise noted.
Symbol
Min
Typ
Max
-000.0
±OOO.O
+000.0
I Unit
Parameter
Test Conditions
Zero Input Reading
VIN= OV
Full Scale = 200 mV
Zero Reading Drift
VIN = OV, O°C .;;; TA .;;; +70°C
-
0.2
1
Ratiometric Reading
VIN = VREF, VREF = 100 mV
999
999/1000
1000
Nonlinearity Error
Full Scale = 200 mV or 2V
Max Deviation From Best
Straight Line
-1
±0.2
1
Roll-Over Error
-VIN = +VIN = 200 mV
-1
±0.2
Noise
VIN = OV, Full Scale = 200 mV
-
15
IL
Input Leakage CUrrent
VIN= OV
-
1
10
pA
CMRR
Common-Mode Rejection
Ratio
VCM = ±1V, VIN = OV,
Full Scale = 200 mV
-
50
-
IlVN
Scale Factor Temperature
Coefficient
VIN = 199 mV, O°C.;;; TA';;; +70°C
Ext Ref Temp Coeff = 0 ppm/DC
-
1
5
ppm/DC
-
35
70
75
150
ppm/DC
ppm/DC
-
35
70
100
150
ppm/DC
ppm/DC
2.7
3.05
3.35
V
Input
NL
eN
1
-
Digital
Reading
IlV/oC
Digital
Reading
Count
Count
IlVp.p
Analog Common
Analog Common
Temperature Coefficient
VCTC
250 ill Between Common and V+
O°C.;;; TA';;; +70°C
TC7136A
"C" Commercial Temp TC7136
Ranoe Devices
-25°C.;;; T A .;;; +S5°C TC7136A
"I" Industrial Temp
TC7136
Range Devices
Analog Common Voltage
250 kW Between Common and V+
VSD
LCD Segment Drive Voltage
V+ to V = 9V
VBD
LCD Backplane Drive Voltage
V+ to V- = 9V
Vc
-
LCD Drive
Power Supply
Is
70
Power Supply Current
VIN = OV, V+ to V- = 9V (Note 6)
100
lilA
Input volteges may exceed supply voltages when input current is limited to 100 IIA.
Dissipation rating assumes device is mounted with all leads soldered to PC board.
Refer to 'Differential Input' discussion.
Sackplane drive is in-phase with segment drive for 'off' segment and 180° out-of-phase for 'on' segment. Frequency is 20 times
conversion rate. Average DC component is less than 50 mY.
5. See 'Typical Operating Circuit'.
6. A 48 kHz oscillator increases current by 20 IIA (typical). Common current not included.
NOTES: 1.
2.
3.
4.
1-194
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DiGITAL CONVERTERS
TC7136
TC7136A
PIN DESCRIPTION
40-Pin DIP
Pin Number
Normal
(Reverse)
Name
Description
Positive supply voltage.
(40)
V+
2
(39)
D1
Activates the D section of the untts display.
3
(38)
C1
Activates the C section of the units display.
4
5
(37)
(36)
81
A1
Activates the 8 section of the untts display.
Activates the A section of the units display.
6
(35)
Fl
Activates the F section of the untts display.
7
(34)
Gl
Activates the G section of the units display.
8
(33)
E1
Activates the E section of the units display.
9
10
(32)
(31)
D2
C2
Activates the C section of the tens display.
Activates the D section of the tens display.
11
(30)
82
Activates the 8 section of the tens display.
12
(29)
A2
Activates the A section of the tens display.
13
(28)
F2
Activates the F section of the tens display.
14
(27)
E2
Activates the E section of the tens display.
15
(26)
Activates the D section of the hundreds display.
16
(25)
D3
83
17
(24)
Fa
Activates the F section of the hundreds display.
18
(23)
Ea
Activates the E section of the hundreds display.
19
(22)
A84
Activates both halves of the 1 in the thousands display.
20
(21)
21
(20)
POL
8P
Activates the negative polarity display.
Backplane drive output.
22
(19)
Ga
Activates the G section of the hundreds display.
23
(18)
Activates the A section of the hundreds display.
24
(17)
Aa
Ca
25
(16)
Activates the G section of the tens display.
26
(15)
G2
V
27
(14)
VINT
28
(13)
VSUFF
29
(12)
CAZ
The size of the auto-zero capacitor influences the system noise. Use a 0.471J.F
capacitor for a 200 mV full scale, and a 0.1 IJ.F capacitor for a 2V full scale. See
paragraph on Auto-Zero Capacttor for more details.
30
(11)
(10)
VIN
VIN+
The low input signal is connected to this pin.
31
32
(9)
33
(8)
ANALOG
COMMON
Activates the 8 section of the hundreds display.
Activates the C section of the hundreds display.
Negative power supply voltage.
The integrating capacitor should be selected to give the maximum vottage swing that
ensures component tolerance build-up will not allow the integrator output to saturate.
When analog common is used as a reference and the conversion rate is 3 readings
per second, a 0.0471J.F capacitor may be used. The capacitor must have a low
dielectric constant to prevent roll-over errors. See Integrating Capacitor section for
additional details.
Integration resistor connection. Use a 180 kQ for a 200 mV full-scale range and a
1.8 MQ for 2V full-scale range.
The high input signal is connected to this pin.
This pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. See
paragraph on Analog Common for more details. It also acts as a reference voltage
source.
See pin 34.
1-195
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
PIN DESCRIPTION (Cont.)
40-Pin DIP
Pin Number
Normal
(Reverse)
Name
Description
(7)
CREF+
A 0.1 J.lF capacitor is used in most applications. If a large common-mode voHage
exists (for example, the VIN- pin is not at analog common), and a 200 mV scale is
used, a 1 J.lF capacitor is recommended and will hold the roll-over error to 0.5 count.
34
See pin 36.
35
(6)
36
(5)
VREF
V REF+
37
(4)
TEST
Lamp test. When pulled high (to V+) all segments will be turned on and the display
should read -1888. It may also be used as a negative supply for externally-generated
decimal points. See paragraph under Test for additional information.
The analog input required to generate a full-scale output (1999 counts). Place 100 mV
between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35 and 36 for
2V full scale. See paragraph on Reference Voltage.
38
(3)
asc3
See pin 40.
39
40
(2)
(1 )
aSC2
asc1
See pin 40.
Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per
second) connect pin 40 to the junction of a 180 kn resistor and a 50 pF capacitor. The
180 kn resistor is tied to pin 39 and the 50 pF capacttor is tied to pin 38.
GENERAL THEORY OF OPERATION
Dual.Slope Conversion Principles
The TC7136A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7136A
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
REF
VOLTAGE
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period (tSI) , measured by counting clock pulses. An
opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal (tAl).
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
J.-
RC
where:
VA
tSI
tRI
f
tsl
0
V
V (t)dt= ~
IN
Figure 1
RC'
For a constant VIN:
= Reference voltage
= Signal integration time (fixed)
= Reference voltage integration time (variable).
1-196
Basic Dual-Slope Converter
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
30
iii'
:2-
z
\
o
t;
w
..,
20
V'
w
a:
l!Io
\
y'
I~
after an overrange conversion. The count forthis phase is a
function of the number of counts required by the deintegrate
phase.
Thecount lasts from 11 to 140 counts for non-overrange
conversions and from 31 to 640 counts for overrange
conversions.
V~
,
Auto-Zero Phase
,,
:;; 10
~
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on
CAZ compensates for device offset Voltages. The auto-zero
phase residual is typically 10 IiV to 15 IiV.
The auto-zero duration is from 910 to 2900 counts for
non-overrange conversions and from 300 to 910 counts for
overrange conversions.
:;;
a:
~
o
-
l -V
0.111
Figure 2
V
t
I
i
ITEASUjEMiNTrrm
111
1011
INPUT FREQUENCY
Normal-Mode Rejection of Dual-Slope Converter
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
Signal Integration Phase
The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN-. The differential input
signal is integrated for a fixed time period. The TC7136A
signal integration period is 1000 clock periods or counts. The
externally-set clock frequency is divided by four before
clocking the internal counters. The integration time period is:
tSI =
ANALOG SECTION
where fose
In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC7136 and TC7136A
designs incorporate an "integrator output-zero cycle" and an
"auto-zero cycle." These additional cycles ensure the integrator starts at OV (even after a severe overrange conversion) and that all offset voltage errors (buffer amplifier,
integrator and comparator) are removed from the conversion. A true digital zero reading is assured without any
external adjustments.
A complete conversion consists of four distinct phases:
(1)
(2)
(3)
(4)
Integrator output-zero phase
Auto-zero phase
Signal integrate phase
Reference deintegrate phase
Integrator Output-Zero Phase
This phase guarantees the integrator output is at OV
before the system-zero phase is entered. This ensures that
true system offset voltages will be compensated for even
4
-f-
ose
x 1000,
= external clock frequency.
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, VIN- should be tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that signals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
Reference Integrate Phase
The third phase is reference integrate or deintegrate.
is internally connected to analog common and VIN+ is
connected across the previously-charged reference capacitor. Circuitry within the chip ensures the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
VIN-
1-197
-t-4
00
............
..........
ww
0)0)
»
TYPICAL SEGMENT OUTPUT
,
V'
LCD
~"
TC7136A
C REF
!I
~
V~EF
CR~
....
VREF
~ CREF
VBUFF
34 ""T36-----"?;;~-------'
;
'"
§
~
~
co
~
OJ
»
z
g
...
..
!2
»
oC)
r-
1
26
T
,,
,..
V~--------------I
I
L.....J
1
37'
~TEST
~
Or-
,
... -_".!'
OSC1
ROSC
C OSC
'0
S!:e
e-o
i!o
r:e
om
0]'
Zw
<.!..
mi\5
:lI
-to
m-
:lie
(/)-4
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-OIGITAL CONVERTERS
TC7136
TC7136A
INT
DENT
Y
1000
than several minutes. LCDs may be destroyed if operated
with DC levels for extended periods.
The display font and segment drive assignment are
shown in Rgure 6.
----.r
"+tL..______
II
I
I
.j;=1-2000+J.
:*:11-140
ZI -+1-------.....
AZl
DISPLAY FONT
DI23456789
I
..Ij.- 910-2900 .~
!-._ _ _ _ _ _ _
IfoI~I-------4000 --------l~~1
Figure 4
y
INT
I
ZI
I
,1OOO'ST100'sT10'BT1'Sl
1--1 8 8 81
Conversion Timing During Normal Operation
1000
---!r
+fL..______
Figure 6
I
_~_ _...I!+==2001-2090==4L_ __:_
DEINT·
-
AZ
System Timing
31-640~
-i,!--________________
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The four-phase measurement
cycle takes a total of 4000 counts, or 16,000 clock pulses. The
4000-count cycle is independent of input signal magnitude.
Each phase of the measurement cycle has the following
length:
1
3_0_0-_9__
10~
f~
Figure 5
4000
Display FONT and Segment Assignment
----=-.r--i~
(1) Auto-zero phase: 3000 to 2900 counts
(1200 to 11,600 clock pulses)
(2) Signal integrate: 1000 counts
(4000 clock pulses)
Conversion Timing During Overrange Operation
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is
This time period is fixed. The integration period is:
1000~
tSI = 4000
VREF
tf~cJ,
where fose is the externally-set clock frequency.
DIGITAL SECTION
The TC7136A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency divided by 800. For three conversions per
second the backplane frequency is 60 Hz with a 5V nominal
amplitude. When a segment driver is in-phase with the
backplane signal, the segment is "OFF." An out-of-phase
segment drive signal causes the segment to be "ON," or
visible. This AC drive configuration results in negligible DC
voltage across each LCD segment, ensuring long LCD life.
The polarity segment driver is "ON" for negative analog
inputs. If VIN+ and VIN- are reversed, this indicator would
reverse.
On the TC7136A, when the test pin is pulled to V+, all
segments are turned "ON." The display reads -1888. During
this mode the LCD segments have a constant DC voltage
impressed. Do not leave the display in this mode for more
(3) Reference integrate: 0 to 2000 counts
(4) Zero integrator: 11 to 640 counts
The TC7136 is a drop-in replacement for the TC7126
and ICL7126. The TC7136A offers a greatly-improved internal reference temperature coefficient. Minor component
value changes are required to upgrade existing designs and
improve the noise performance.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor (CAZ)
The CAl capacitor size has some influence on system
noise. A 0.47 ~F capacitor is recommended for 200 mV fullscale applications where 1 LSB is 100 IN. A 0.1 ~F capacitor
is adequate for 2V full-scale applications. A Mylar-type
dielectric capacitor is adequate.
1·199
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
Oscillator Components
Reference Voltage Capacitor (CREF)
The reference voltage used to ramp the integrator
output voltage back to zero during the reference integrate
phase is stored on CREF. A 0.1 I1F capacitor is acceptable
when VREF- is tied to analog common. If a large commonmode voltage exists (VREF- analog common) and the
application requires a 200 mV full scale, increase CREF to
1 I1F. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
*
Integrating Capacitor (C'NT)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage reference this case, a ±2V full-scale integrator output swing is
satisfactory. For 3 readings per second (fose = 48 kHz) a
0.047I1F value is suggested. For one reading per second,
0.15 IlF is recommended. If a different oscillator frequency
is used, CINT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
An exact expression for CINT is:
. (4000) (
CINT=
where: fose
VFS
RINT
VINT
=
=
=
=
1
VFs l
1 (tliNT]
Note that fose is + 4 to generate the TC7136A's intemal
clock. The backplane drive signal is derived by dividing fose
by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz,
40 kHz, 33-1/3 kHz, etc. should be selected. For 50 Hz
rejection, oscillator frequencies of 200 kHz, 100kHz, 66-213
kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that
40 kHz (2.5 readings per second) will reject both 50 Hz and
60 Hz (also 400 Hz and 440 Hz).
Required Full-Scale Voltage·
,
VINT
Clock frequency at pin 38
Full-scale input voltage
Integrating resistor .
Desired full-scale integrator output swing.
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling current
is 6 1lA. The integrator and buffer can supply 1 IlA drive
currents with negligible linearity errors. RINT is chosen to
remain in the output stage linear drive region, but not so
large that PC board leakage currents induce errors. For a
200 mV full scale, RINT is 180 kn. A2V full scale requires
1.8Mn.
RINT
CINT
NOTE:
0.45
ose= AG'
200mV
2V
Integrating Resistor (R'NT)
Value
f
A full-scale reading (2000 counts) requires the input
signal be twice the reference Voltage.
ToSc)
Nominal
should be 50 pF. Rose is selected from the
Reference Voltage Selection
CINT must have low dielectric absorption to minimize
roll-over error. An inexpensive polypropylene capacitor is
recommended.
Component
case
equation:
Full-Sc~'e Voltage
200mV
2V
0.471!F
180 kn
0.0471!F
1.8 Mn
0.0471!F
lose =48 kHz (3 readings per sec). Rose =k.Q, Case =50 pF.
100mV
lV
In some applications, a scale factor otherthan unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, a pressure transducer
output for 2000 Ib/in. 2 is 400 mY. Rather than dividing the
input voltage by two, the reference voltage should be set to
200 mY. This permits the transducer input to be used
directly.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analog common and VIN-. The transducer output is connected between VIN+ and analog common.
DEVICE PIN FUNCTIONAL DESCRIPTION
Differential Signal Inputs
VIN+ (Pin 31), VIN- (Pin 30)
The TC7136A is designed with true differential inputs
and accepts input signals within the input stage commonmode voltage range (VeM). The typical range is V+ -1 V to V+1V. Common-mode voltages are removed from the system
when the TC7136A operates from a battery or floating power
source (isolated from measured system), and VIN- is connected to analog common (VeoM). (See Figure 7.)
1-200
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
l'C7136
TC7136A
MEASURED
SYSTEM
I+---Iv+
9V
Figure 7
Common-Mode Voltage Removed in Battery Operation With V,N
In systems where common-mode voltages exist, the
86 dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large positive
VCM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output
positive along with VCM {see Figure 8.} For such applications, the integrator output swing can be reduced below the
recommended 2V full-scale swing. The integrator output
will swing within 0.3V of V+ or V- without increased
linearity error.
Differential Reference
(Pin 36), VREF- (Pin 35)
The reference voltage can be generated anywhere
within the V+ to V- power supply range.
To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
VREF+
+
r
Figure 8
v, =~ [VCM =V'N]
Whera:
I
t,
.•
4000
=Integration
time ='osc
=Integration capacitor
C,
R, = Integration resistor
Common-Mode Voltage Reduces Available Integrator
Swing (VCOM V,N)
*
=Analog Common
The TC7136A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable Voltage, suitable for use as a voltage reference.
The temperature coefficient of analog common is typically
35 ppm/°C.
ANALOG COMMON (Pin 32)
The analog common pin is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.35V below V+. Analog common is
tied internally to an N-channel FET capable of sinking
1001JA. This FET will hold the common line at 3V below V+
if an external load attempts to pull the common line toward
V+. Analog common source current is limited to 1 IJA. Analog
common is therefore easily pulled to a more negative
voltage {i.e., below V+ -3V}.
The TC7136A connects the internal V'N+ and V'N- inputs to analog common during the auto-zero phase. During
the reference-integrate phase, V'N- is connected to analog
common. If VIN- is not externally connected to analog
common, a common-mode voltage exists, but is rejected by
the converter's 86 dB common-mode rejection ratio. In
battery operation, analog common and V'N- are usually
connected, removing common-mode voltage concerns. In
systems where V'N- is connected to the power supply
ground or to a given voltage, analog common should be
connected to V'N-.
The analog common pin serves to set the analog section reference, or common point. The TC7136A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float)
with respect to the TC7136A power source. The analog
common potential of V+ -3V gives a 7V end of battery life
voltage. The common potential has a 0.001%/% voltage
coefficient.
1-201
lOW POWER, 3-1/2 DIGIT
ANAlOG-TO-DIGITAl CONVERTERS
TC7136
TC7136A
With sufficiently high total supply voltage (V+-V- >7V),
analog common is a very stable potential with excellent
temperature stability (typically 35 ppm/°c). This potential
can be used to generate the TC7136A's reference voltage.
An external voltage reference will be unnecessary in most
cases because of the 35 ppm/°C temperature coefficient.
See TC7136A Internal Voltage Reference discussion.
TC7136
TC7136A
TEST (Pin 37)
The test pin potential is 5V less than V+. Test may be
used as the negative power supply connection for external
CMOS logic. The test pin is tied to the internally-generated
negative logic supply through a 500n resistor. The test pin
load should not be more than 1 rnA. See the Applications
Section for additional information on using test as a negative
digital logic supply.
If test is pulled high (to V+), all segments plus the minus
sign will be activated. Do not operate in this mode for more
than several minutes. With Test = V+, the LCD segments are
impressed with a DC voltage which will destroy the LCD.
VREF
VREF
SET VREF
Figure 10
9'
180
E
160
ott
:i~
w
c..
::;;
l!:!
40 l20
r-
I TYPICAL:
~r-I
TC7136A
~rTC7136
ICL7136
0
Figure 9
Analog Common Temperature Coefficient
TC7136A Internal Voltage Reference Connection
Manufacturer
Address/Phone
Crystaloid
Electronics
5282 Hudson Dr.,
Hudson, OH 44236
216-655-2429
770 Airport Blvd.,
Burlingame, CA 94010
415-347-9916
1800 Vernon St., Ste. 2
Roseville, CA 95678
916-783-7878
612 E. Lake St.,
Lake Mills, WI 53551
414-648-2361
VGI, Inc.
r-
=112 VFULL SCALE
Several manufacturers supply standard LCDs to interface with the TC7136A 3-1/2 digit analog-to-digital converter.
r-
GUARANTEED
MAXIMUM NO MAXIMUM
.-----1 SPECIFIED
Z~
I
I
TYPICAL
OZ 140 lI
I
::;;!!!
::;;!:! 120 lI
I
ou..
I
I
I
I
ClO 100 r0 0
GUARANTEED I
I
~w
..
A/v--'--~A ~---+------~.---~--¥--~--1-......
16
,...
•
.,~
~~~gg-UTPUT
(1 =+,0=-)
'Optional visual indication of negative input.
NOTE: Values for R should be between 10 kn and 100 kn.
1-211
:
.. >--e---
------... +.-'
'---+-0
I
I
I
I
TC8750
3-1/2 DIGIT ADC WITH
PARALLEL BDC OUTPUT
TC8750
APPLICATION/DESIGN CIRCUITS (Cont.)
Microprocessor-Based ADC System
17
16
15
19
+5V
CH8
ANALOG
SENSOR
INPUTS
24 MSB
1
2
3
4
5
6
7
8
9
10
11
12
I'
-=
"50S"
ANALOG
MULTIPLEXER
15
..,'"
TC8750
CH1
14
13
12
11
10
9
8
7
6
5
4
3
LSB 2
PERIPHERAL
INTERFACE
ADAPTER
(PIA)
DATA VAUDt;:;-~--I---::-1CB1
18
START
19 CB2
51 kn
·OFFSET CORRECTION
IN SOFTWARE
"'1~9-~~'"
20kO
100kO
-5V
1-212
VO.
1 I'F
6821
OR
6521
~"'TELEDYNE
COMPONENTS
TC14433
TC14433A
TC14433B
3-1/2 DIGIT ADC
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The TC1433 is a low power, high-performance, monolithic CMOS 3-1/2 digit AID converter. The TC14433 combines both analog and digital circuits on a single IC, thus
minimizing the number of external components. This dualslope AID converter provides automatic polarity and zero
correction with the addition of two extemal resistors and two
capacitors. The full-scale voHage range ofthis ratiometric IC
extends from 199.9 millivoHs to 1.999 voHs. The TC14433B
can operate over a wide range of power supply voltages,
including batteries and standard 5-volt supplies.
The TC14433 will interface with the TC7211A (LCD)and
TC7212A (LED) display drivers.
The TC14433A1B feature improved performance over
the industry standard TC14433. Rollover, which is the
measurement of identical positive and negative signals, is
guaranteed to have the same reading within one count for
the TC14433A, and within four counts for the TC14433B.
Power consumption of the TC14433A1B is typically 4 mW,
approximately one-half that ofthe industry standard TC14433.
Accuracy: ±O.05% of Reading ±1 Count
Two Voltage Ranges: 1.999Vand 199.9 mV
Up to 25 Conversions Per Second
ZIN > 1000M Ohms
Single Positive Voltage Reference
Auto-Polarity and Auto-Zero
Overrange and Underrange Signals Available
Operates in Auto-Ranging Circuits
Uses On-Chip System Clock or External Clock
Wide Supply Range: e.g., ±4.5V to ±8V
Available in Surface-Mount Packages
APPLICATIONS
•
•
•
•
•
•
•
•
Portable Instruments
Digital Voltmeters
Digital Panel Meters
Digital Scales
Digital Thermometers
Remote AID Sensing Systems
MPU Systems
See Application Notes 19 and 21
BLOCK DIAGRAM
~------------------------------------------'2~3
QO-Q3
BCD DATA
OR
VREF REFERENCE VOLTAGE
VAG ANALOG GROUND
Vx
ANALOG INPUT
CONmOL
LOGIC
DISPLAY 9
UPDATE
DU
,....,
OVERRANGE
Voo= PIN 24
Vss = PIN 13
VEE. PIN 12
INTEGRATOR
1·213
OFFSET
3-1/2 DIGIT ADC
TC14433
TC14433A·
TC144338
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
DC Supply Voltage
Voo to VEE
V
-0.5 to +18
Vdc
Voltage, Any Pin,
Referenced to VEE
DC Current Drain
Per Pin
Operating
Temperature Range
Storage Temperature
Range
-0.5 to
Voo +0.5
Vdc
I
10
mAdc
TA
-40 to +85
°C
TSTG
-65 to +150
°C
(Vss
=0 or VEE)
Symbol
Value
Unit
DC Supply Voltage:
VDO to Analog Ground
VEE to Analog Ground
Parameter
Voo
VEE
+5 to +8
-2.8to-8
Vdc
Vdc
Clock Frequency
fClK
32 to 400
kHz
Zero Offset
Correction Capacitor
Co
0.1 to±20%
I1F
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under 'Absolute Maximum Ratings' may cause perma·
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS
(C, =O.lI1F mylar, R, =470 knat VAEF =2V, R, =27 kn at V REF =200 mY, Co =O.lI1F, Rc =300 kn; all voltages referenced
to Analog Ground, pin 1.)
Characteristic
Analog Input
Rollover Error (Difference
in reading for equal pos~ive and
negative reading near
full-scale)
-V'N +V'N: 200 mV Full-Scale
=
Symbol
Unit
14433A
-1
-
+1
14433B
-
-
-4
-
+4
14433
-
-
-
-
-
Linearity Output Reading (Note 1)
(VREF = 2V)
(V REF = 200 mY)
-
Stability Output Reading (Note 2)
(Vx= 1.99V, VREF =2V)
(Vx = 199 mY, VREF = 200 mY)
-
Zero Output Reading
(Vx = OV, V REF = 2V)
Bias Current:
Analog Input
Reference Input
Analog Ground
-
-
-
Counts
-
5
5
-5
-5
-
-
-0.05
-1 count
+0.05
+0.05
+1 count
-
-
%rdg
-
5
5
-5
-5
-
2
-
-
LSD
LSD
-5
-
0
0
-
-
3
5
-
-
-
-
-
LSD
-
5
5
5
-5
-5
-5
--
-
-
±100
±100
±500
-
-
-
±20
±20
±20
-
-
-
pA
pA
pA
5
-5
-
-
-
65
-
-
-
dB
5
5
5
5
-5
-5
-5
-5
-
0
5
-5
5
Common-Mode Rejection
(Vx = l.4V, VREF = 2V,
foe = 32 kHz)
-
-
Digital
Output Voltage (V•• = OV)
(V•• = -5V)
Pins 14 to 23
"0" Level
"1" Level
"0" Level
"1" Level
VOL
VOH
VOL
VOH
-
0.05
4.95
-4.95
4.95
4.95
-
4.95
1-214
-
0.05
-4.95
-
4.95
4.95
0.05
-4.95
-
V
V
V
V
3-1/2 DIGIT ADC
TC144333
TC14433A
TC144338
VDD
Characteristic
Symbol Vdc Vdc
Output Current - Pins 14 to 23
(Vss = OV)
(VOH = 4.6V) Source
(VOL = O.4V) Sink
(Vss = OV)
(VOH = 5V) Source
(VOL = -4.5V) Sink
IOH
IOl
5
5
-5
= 300 k.Q)
fClK
5
-5
lou
5
-5
5
8
5
8
-5
10
10
5
Clock Frequency (Rc
Input Current -
-40°C
VEE
DU
Power
Quiescent Current
(Vooto VEE' Iss = 0) 14433A1B
14433
Supply Rejection
(Voo to VEE' Iss = 0, V REF
= 2V)
IOH
IOl
-
5
5
Min
-5 -0.25
0.64
-5
-0.62
1.6
-5
Max
-
-
-
25°C
85°C
Min
Typ
Max
-0.2
0.51
-0.36
0.88
-
-0.5
1.3
Min
Max
-
-0.14
0.36
-0.9
2.25
-
-0.35
0.9
66
-
-
Unit
-
kHz
-
±1
~
mA
mA
rnA
rnA
-
±0.3
-
3.7
7.4
3.7
7.4
-
0.4
1.4
0.9
1.8
2
4
2
4
-
-8
-
-
1.6
3.2
1.6
3.2
mA
mA
mA
mA
-5
-
-
-
0.5
-
-
-
mVN
-B
-5
±0.00001 ±0.3
NOTES: 1. Accuracy - The accuracy of the meter at full-scale is the accuracy of the setting of the reference voltage. Zero is recalculated during
each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other
than positive full-scale and zero is defined as the linearity specification.
2. Three LSD stability for 200 mV scale is defined as the range that the LSD will occupy 95% of the time.
3. Pin numbers refer to 24-pin DIP.
ORDERING INFORMATION
Part No.
Package
Temperature
Range
TC14433AEPG
TC 14433BEPG
TC14433EPG
24-Pin Plastic DIP
-40°C to +85°C
TC14433EJG
TC14433EJG
TC14433EJG
24-Pin CerDIP
-40°C to +85°C
TC14433ELI
TC14433AELI
2B-Pin PLCC
28-Pin PLCC
-40°C to +B5°C
-40°C to +85°C
1-215
Part No.
TC14433EBQ
TC14433EBQ
Package
60-Pin Plastic
Flat Package:
Formed Leads
Temperature
Range
3-1/2 DIGIT ADC
TC14433
TC14433A
TC144338
TYPICAL CHARACTERISTICS
-
r--.......
1"""',
f-
VEE=-8V
VDO=+8V
-...... --...
NOTE: ROLLOVER ERROR IS THE DIFFERENCE
IN OUTPUT READING FOR THE SAME
ANALOG INPUT SWITCHED FROM
POSITIVE TO NEGATIVE.
r--
r--
- -
VEE=-5V
Voo=+5V
-3
-2
-1
0
1
2
3
(IV 00 !-IV EE I) - SUPPLY VOLTAGE SKEW (V)
4
-40
Figure 1. Typical Rollover Error VB Power Supply Skew
-20
0
2D
40
60
T A - TEMPERATURE (·C)
ao
100
Figure 2. Typical Quiescent Power Supply Current
VB Temperature
S
;;(
;;( -3
.§. 4
~
III
.§.
II:
II:
3
:::>
()
;
Ie: 2
i:
f/)
r/'
1
~
!z
III
a: -2
a:
I·C
--
:::>
o
"
o
~
~
V
-1
234
----
-4O"C
I
":,2~·C
-8S·C
...-
/. ~
o "".
o
5
,/1"'""
/' ~~
1
_0
1
./"
V
()
t 2S• C
+8S·C
./" roo-
~
_0
1
V OS - DRAIN TO SOURCE VOLTAGE (Vdc)
-1
-2
-3
-4
Vos -DRAIN TO SOURCE VOLTAGE (Vdc)
Figure 4. Typical P-Channel Source Current at
Voo-V.s = 5 Volts
Figure 3. Typical N-Channel Sink Current at
VDD-V" = 5 Volts
iii"
~ 4
-<
is
NOTE: ",S% TYPICAL VARIATION OVER
SUPPLY VOLTAGES RANGE OF
",4.SV TO ",8V.
3
~ 2
'-",SVSUPPLY
~
ti
ffi
~
0
IE
-1
w
~
~
U -2
90-3
..........
--
..aVSUPPLV-
NORMALIZED AT 2S·C
1-4
J~
10kn
100kn
lMn
RC - CLOCK FREQUENCY RESISTOR
-40
-20
0
20
40
60
T A - TEMPERATURE (OC)
Figure 6. Typical % Change of Clock Frequency
vs Temperature
Figure 5. Typical Clock Frequency VB Resistor (Re)
CONVERSION RATE = CLOCK FREQUENCY 1 5%
16,400
'" •
MULTIPLEX RATE
-5
=CLOCK ':EQUENCY
1-216
80
3-1/2 DIGIT ADC
TC14433
TC14433A
TC14433B
PIN CONFIGURATIONS
R,
R,/C,
C,
Zl (.) a:
!il
>
R,
=
Vx (max)
C,
WHERE:
R,ISINkQ
Voo IS THE VOLTAGE AT PIN 24 REFERENCED TO VAG
Vx IS THE VOLTAGE AT PIN 3 REFERENCED TO VAG
ICLK IS THE CLOCK FREQUENCY AT PIN '0 IN kHz
3..2....
l>.V
l>.V = Voo - Vx (max) -0.5
T= 40003 -I-'ClK
(.)
z
0
Ia:owO(.)
In
III
'ft::;)
:>'
til
~
w
w
:>
(.)
(.)
Z
(.)
z
NC
NC
NC
NC
NC
NC
DU
CO 2
CO,
C,
SUB
R,/C,
NC
NC
R,
NC
NC
~~~~~~~~~~~~~~~~~~~~~NC
(.)
z
...
~
>
(.)
>< (.) (.) (.)
z > z z z
NOTES:
,. NC = NO INTERNAL CONNECTION
2. PINS 8, 23, 38 AND 53 ARE CONNECTED TO THE DIE SUBSTRATE.
THE POTENTIAL AT THESE PINS IS APPROXIMATELY V+. NO EXTERNAL CONNECTIONS SHOULD BE MADE.
'-2'7
3-1/2 DIGIT ADC
TC14433
TC14433A
TC14433B
PIN DESCRIPTIONS
Pin No.
60-Pin
FP
Pin No.
24-Pin Symbol
DIP
7
VAG
Description
This is the analog ground; it has a high input impedance - This pin determines the reference level
for the unknown input voltage (Vx) and the reference voltage (VREF).
10
Reference vokage - Full-scale output is equal to the voltage applied to VREF. Therefore, full-scale
voltage of 1.999V requires 2V reference and 199.9 mV full-scale requires a 200 mV reference.
VREF functions as system reset also. When switched to VEE' the system is reset to the beginning
of the conversion cycle.
12
The unknown input vokage (Vx) is measured as a ratio of the reference voltage (VREF ) in a
ratiometric AID conversion.
19
22
24
These pins are for external components used for the integration function in the dual slope
conversion. Typical values are 0.1 !iF (mylar) capacitor for C,.
R, 470 kn (resistor) for 2V full-scale.
R, = 27 kn (resistor) for 200 mV full-scale.
Clock frequency of 66 kHz gives 250 ms conversion time. See equation below for calculation
of integrator component values.
25
26
These pins are used for connecting the offset correction capacitor. The recommended value
is 0.1 !iF.
27
Display update input pin - When DU is connected to the EOC output every conversion is
displayed.
New data will be strobed into the output latches during the conversion cycle if a positive edge is
received on DU prior to the ramp-down cycle. When this pin is driven from an external source, the
vokage should be referenced to V ••.
=
Clock input pins - The TC14433 has its own oscillator system clock. Connecting a single
resistor between ClK, and ClK. sets the clock frequency.
A crystal or OC circuit may be inserted in lieu of a resistor for improved stability. ClK" the clock
input, can be driven from an external clock source, which need only have standard CMOS output
drive. This pin is referenced to VEE for external clock inputs. A 300 kn resistor yields a clock
frequency of about 66 kHz. (See typical characteristic curves; see Figure 9 for alternate circuits.)
34
10
ClK,
36
11
ClK.
37
12
VEE
Negative power current - Connection pin for the most negative supply. Please note the current
for the output drive circuit is returned through V••. Typical supply current is 0.8 mAo
39
13
V ••
Negative power supply for output circuitry - This pin sets the low vokage level for the output pins
(BCD, Digit Selects, EOC, OR). When connected to analog ground, the output voltage is from
analog ground to V00. If connected to VEE' the output swing is from VEE to V 00. The recommended
operating range for V •• is between the V OD -3 voks and VEE.
40
14
EOC
End of conversion output generates a pulse at the end of each conversion cycle. This generated
pulse width is equal to one-half the period of the system clock.
41
15
OR
Overrange pin -
49
16
OS.
51
52
17
18
OS,
OS,
54
19
OS,
Digit select pins - The dig~ select output goes high when the respective digit is selected. The
MSD (1/2 dig~) turns on immediately after an EOC pulse.
The remaining digits turn on in sequence from MSD to LSD.
To ensure that the BCD data has settled, an inter-digit blanking time of two clock periods is
included.
Clock frequency divided by 80 equals multiplex rate. For example, a system clock of 60 kHz gives
a multiplex rate of 0.8 kHz.
5
4
20
21
O.
0,
57
55
22
23
a.0,
See Figure 12 for dig~ select timing diagram.
BCD data output pins - Mukiplexed BCD outputs contain three full digits of information during
digit select OS" DS3 , OS•.
During OS" the 1/2 dig~, overrange, underrange and polarity information is available.
Refer to truth table.
6
24
Veo
Posnive power supply -
Normally this pin is set high. When Vx exceeds V REF the OR pin is low.
This is the most positive power supply pin.
1-218
3-1/2 DIGIT ADC
TC14433
TC14433A
TC144338
CIRCUIT DESCRIPTION
The TC14433 CMOS IC becomes a modified dualslope AID with a minimum of external components. This IC
has the customary CMOS digital logic circuitry, as well as
CMOS analog circuitry. It provides the user with digital
functions (such as counters, latches, multiplexers) and
analog functions (such as operational amplifiers and comparators) on a single chip.
Features of this system include auto-zero, high input
impedances and auto-polarity. Low power consumption
and a wide range of power supply voltages are also advantages of this CMOS device. The system's auto-zero
function compensates for the offset voltage of the intemal
amplifiers and comparators. In this "ratiometric system," the
output reading is the ratio of the unknown voltage to the
reference voltage, where a ratio of 1 is equal to the maximum
count of 1999. It takes approximately 16,000 clock periods
to complete one conversion cycle. Each conversion cycle
may be divided into 6 segments. Figure 7 shows the
conversion cycle in 6 segments for both positive and negative inputs.
Segment 1 - The offset capacitor (CO>' which compensates for the input offset voltages of the buffer and
integrator amplifiers, is charged during this period. However, the integrator capacitor is shorted. This segment
requires 4000 clock periods.
Segment 2 - During this segment, the integrator output decreases to the comparator threshold voltage. At this
time, a number of counts equivalent to the input offset
voltage of the comparator is stored in the offset latches for
later use in the auto-zero process. The time forthis segment
is variable and less than 800 clock periods.
.
START
TIME
SEGMENT
NUMBER
3
4
Figure 7. Integrator Waveforms at Pin 6
Figure 8. Equivalent Circuit Diagrams of the Analog
Section During Segment 4 of the Timing Cycle
(8) LC Oscillator Circuit
r -_ _~-,-,10'i CLK1
r-_---1~--~.!:10~ CLK1
11'"
11'"
L
TC14433
TC14433
+-____1'-'1'-1 CLKo
~W\r-.........!.1.!f1 CLKO
47K
C
10 pF < Cj AND C2 < 200 pF
l'
f= 21'TiViiLC L.._ _ _ _--I
FOR L
Figure 9. Alternate Oscillator Circuits
1-219
.
END
1
(A) Crystal Oscillator Circuit
IBM
.
= 5 mH AND C = 0.01
JlF, f ;,32 kHz
3-1./2 DIGIT ADC
TC14433
TC14433A
TC14433B
Segment 3 - This segment of the conversion cycle is
the same as Segment 1.
Segment 4- Segment 4 is an up-going ramp cycle with
the unknown input voltage (Vx) as the input to the integrator.
Figure 8 shows the equivalent configuration of the analog
section of the TC14433. The actual configuration of the
analog section is dependent upon the polarity of the input
voltage during the previous conversion cycle.
Segment 5 - This segment is a down-going ramp
11'"
TC04
period with the reference voltage as the input to the integrator. Segment 5 of the conversion cycle has a time equal to
the number of counts stored in the offset storage latches
during Segment 2. As a result, the system zeros automatically.
Segment 6 - This is an extension of Segment 5. The
time period forthis portion is 4000 clock periods. The results
of the AJD conversion cycle are determined in this portion of
the conversion cycle.
20K
+5V
r------..--<>-5V ':'
+5V
Vx
':'
+5V
SEGMENT
RESISTORS
1500 (7)
':'
Rt
4
5
6
11'"
TC14433
20
13
-5V
0.11'P'
7
8
0.11'F
9
14
15 19 18 17 16
7
6
5
4
10~--~~------,
3
2
14~--~~---~
11~--~~------,
12~--~~-----,
13~--~~-----,
15~--~~---.
1 141316
-5V
MINUS SIGN
~----+-. -5Vo----~~r--,
-5V
2000
MPS-A12 PLUS SIGN
DS 1
'R 1 = 470 kO FOR 2V RANGE
R1 = 27 kO FOR 200 mV RANGE
"MYLAR CAPACITOR
Figure 10. 3-1/2 Digit Voltmeter Common-Anode Displays, Flashing Overrange
1-220
3-1/2 DIGIT ADC
TC14433
TC14433A
TC144338
~~
COl
+V
810 C 8 APhLD
g fed c b a
I
I
II
.."" .."
0
1
"
2CLOCK
0
1
~+V
~-V
II
.."
-
"
z~~~E'i~O~~CC~~C:~s
_ _ _ _ _ _---I~ ~
"'..11-----I~~118 CLOCK CYCLES
J
145438
g fed c b a
-J 1-112 CLOCK CYCLE
nL....-~
~+V
II
BlOC 8 APhLD
f-o-V
Rgure 11. 3-1/2 Digit Voltmeter with LCD Display
DS1
112 DIGIT
(MSD)
6+V
145438
-<)-V
g fed c b a
MINUS
EOC
140248
~'"
+vLvr
o
~~
I
Rl
~I____________~
~I
CYCLES
----J .....1'-_
__
D~
DS 4
(LSD)
Figure 12. Digit Select Timing Diagram
1-221
I
3-1/2 DIGIT ADC
TC14433
TC14433A
TC14433B
APPLICATIONS INFORMATION
Figure 14 is an example of a 3-1/2 digit LED voltmeter
with a minimum of external components (only 11 additional
components). In this circuit, the 14511 B provides the
segment drive and the 75492 or 1413 provides sink for digit
current. Display is blanked during the overrange condition.
Figure 10 is an example of a 3-1/2 digit voltmeter using
the TC14433 with common-anode displays. This system
requires a 2.5V reference. Full-scale may be adjusted to
1.999Vor 199.9 mV.lnputoverrange is indicated by flashing
a display. This display uses LEOs with common anode digit
lines. Power supply for this system is shown as a dual ±5V
supply; however, the TC14433 will operate over a wide
voltage range (see recommended operating conditions,
page 2).
The circuit in Figure 11 shows a 3-1/2 digit LCD
voltmeter. The 14024B provides the low frequency square
wave signal drive to the LCD backplane. Dual power
supplies are shown here; however, one supply may be
used when Vss is connected to VEE. In this case, VAG must
be at least 2.8V above VEE.
When only segments band c of the decoder are
connected to the 1/2 digit ofthe display, 4, 0, 7 and 3 appear
as 1.
The overrange indication (03 = 0 and 0 0 = 1) occurs
when the count is greater than 1999; e.g., 1.999V for a
reference of 2V. The underrange indication, useful for autoranging circuits, occurs when the count is less than 180;
e.g., 0.180V for a reference of 2V.
TRUTH TABLE
Coded Condition
ofMSD
Q3 Q. Q, Qo
1
1
1
1
0
0
0
0
+0
-0
.+0 UR
-OUR
+1
-1
+1 OR
-OaR
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
BCD to 7-Segment
Decoding
0
0
1
1
0
0
1
1
Blank
Blank
Blank
Blank
4-}
0-1
7-1
3-1
Hook..,
only
segments
band c
toMSD
NOTES:
0, - 1/2 digit, low for '1", high for "0'
Q~ Polarity: "1 = positive, ·0· = negative
0, - Out of range condition exists if 0, = 1. When used in conjunction
with 0" the type of out of range condition is indicated; i.e., 0, = 0
->ORorQ,=1->UR.
R
CAUTION
If the most significant digit is connected to a
display other than a "1" only, such as a full
digit display, segments other than band c must
be disconnected. The BCD to 7-segment
decoder must blank on BCD inputs 1010 to 1111.
MULTIPLEXED
BCD
OS10S2
ii
1
I
I I
I
Do 01 O2 0 3
Voo -
voo -
L-C
14042B POL
0001 02 03
0001 02 03
I I I
I I I
DO 0 1 02 03
DO 01 O2 0 3
14175B
C - Voo
POL 14175B
I
I I
Voo
Do 0 1 02 03
Cl--
POL 14042B
R
I
I I 1
I I
Do 01 02 03
I
POL 14042B
DO 01 02 03
c-
0001 02 03
I
Voo- POL 14175B
14042B POL f- Voo
00 01 02 03
I I
I I I
DO 01 02 0 3
Cr-
'--c
DO 01 02 03
Cr- Voo- POL 14175B
0001 02 03
0001 02 03
0001 02 03
0001 02 03
11 i i
l L! l
!! !!
l l !!
Cr-
EOC
Figure 13. Demultiplexing for TC14433 BCD Data
1-222
3-1/2 Digit ADC
TC14433
TC14433A
TC14433B
470K O.1~F O.1~F
I
RESISTOR
NETWORK
OR
INDIVIDUAL
RESISTOR'
..,,,
A
81
R
a
~.~DI4511BdR
~~~~
1==
TC04
~~JV~-t--,
LT
For VREF =2000V
COMMON
CATHODE
LEDOISPLAY
V : 1.999V lull scale
For VREF = 200 mV
V: 199.9 mV full scale
(change 470K to R 27K
=
and decimal point position)
Peak digit current for an eight
displayed is 7 times the segment
current.
*To increase segment current
75492
OR
L~=============~ DIGIT1413·
DRIVERS
capability add two 75491 les
between 14511 B and Resistor
Network. The use of the 1413
ALTERNATE OVERRANGE CIRCUrr
WrrH SEPARATED LED
as digit driver increases digit
current capability over the 75492.
~
**V can range between -2.8 and
-11V.
Figure 14. 3-1/2 Digit Voltmeter with Low Component Count Using Common Cathode Displays
"r--
+5V
+5V
,.
TC04
LEO DISPLY
+Vcc
4
1Y 7
2Y 12
•
1m
LED
~
05 3 17
DS4 16
TC14433
3-112 DIGIT
AID CONVERTER
,
14
15
,.
17
,.
18
BRT
35
GNO
3.
GNO
A(l.)
B(15)
C(3)
0(2)
E(l)
F(18)
G(17)
A4 2. A(")
B4 21 B(10)
~2 C(I)
C4
D4
OU
EOC
DISPLAY
FLASHES ON
OVERRANGE
=
~I:l
E4 24
F4 2. F(12)
G4 25 G(7)'
+/
r
TO
LED
01
02
03
04
OS,
DS2 18
"r--
27 BO
21 B1
2•
30
MONSANTO
MAN 6630
0"
+5V~:
)"
LED
0
'-'
MONSANTO
MAN 6610
0
)" '-'
LED
'NUMBERS IN PARENTHESES DENOTE PIN
CONNECTIONS FOR MONSANTO DISPLAYS.
Figure 15. TC7212A Interface to TC14433 3-1/2 Digit ADC
1-223
NOTES
1-224
Section 2
Binary AID Converters
Display AID Converters
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
~f'"TELEDYNE
COMPONENTS
TC500
TC500A
INTEGRATING CONVERTER ANALOG PROCESSORS
FEATURES
IMPROVED PERFORMANCE
Resolution ••.••.••.••..•• Up to 16 Bits + Sign (TC500A)
Differential Analog Input
Differential Reference
Low Linearity Error ....................................... 0.003%
Fast Zero-Crossing Comparator .......•.......•....... 41JS
Low Power Dissipation ................................. 10 mW
Auto-Zero Cycle Eliminates Zero-Scale Error
and Drift
Zero Integrator Phase Speeds Recovery From
Overrange Input Signals
Automatic Internal Polarity Detection
Low Input Current ................................... 15 pA Max
Wide Analog Input Voltage .........•................... ±4.2V
Microprocessor Control of Dual-Slope ADC
Conversion
•
•
•
•
•
•
•
•
•
•
•
•
The TC500A is an improved version of the popular
TC500. The improvements allow up to 16 bits of resolution
(plus sign) or faster conversion times for lower resolution
applications.
GENERAL DESCRIPTION
The CMOS TC500fTC500A contain all the analog circuits needed to construct an integrating analog-to-digital
converter. The analog input buffer, integrator, analog
switches, comparator and phase control logic are all on chip.
The dual-slope converter uses time to quantize the
analog input signal. A microprocessor and software routine
perform the digital function of "counting clocks" for the dualslope integrating converter process. The user can control
resolution and conversion speed through software. The
TC500fTC500A analog building block can be used to construct a fast or high-resolution converter by modifying software routines.
FUNCTIONAL DIAGRAM
CONTROL LOGIC
A B CONVERTER STATE
o 0 ZERO INTEGRATOR OUTPUT
o 1 AUTO-ZERO
1 0 SIGNAL INTEGRATE
1 1 DEINTEGRATE
~'"
TC500ITC500A
COMP
OUTPUT
ANALOG~5+-
+-____________
__~____~____________________
~
COMMON
10 SWI
Vm~~DO------~------------------~
V-S
V+
S
15-0 GND
.....>--11-
~
CONTROL LOGIC
1074·1
2-1
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
A microprocessor controls the TC500fTC500A through
the A and B logic input signals. Four phases are possible:
auto-zero, signal integrate, reference integrate (deintegrate),
and integrator zero output.
The TC500fTC500A comparator's output provides polarity and integrator zero-crossing information. The comparator output is always low when the integrator crosses
zero during the deintegrate phase. This signals the end of a
conversion to the processor.
A precision, dual-slope integrating converter with automatic zero-scale offset voltage and drift correction requires
only a reference, three capacitors, a resistor and a controller. The TC500fTC500A contain the analog circuits needed
to construct a dual-slope integrating converter with an autozero phase. A zero-integrator output phase can be selected
to eliminate errors caused by out-of-range input signals. The
zero-integrator phase greatly improves recovery after an
overrange conversion.
The CMOS TC500fTC500A operate from ±5V supplies.
Power dissipation is only 10 mW. Leakage currents at the
differential inputs are a low 10 pA. The TC500fTC500A
differential reference inputs allow easy ratiometric measurements.
Although the TC500A is pin-for-pin compatible with the
TC500, some programming constraints are imposed. (See
"Integrator Output Zero.'1
ORDERING INFORMATION
Part No_
Package
Temperature Range
System Resolution
O·Cto +70·C
16-8it (30 ppm)
-2S·C to +8S·C
16-8it (30 ppm)
TCSOOACPE
16-Pin Plastic DIP
TCSOOAIJE
16-Pin CerDIP
TCSOOACOE
16-Pin SO
O·Cto +70·C
16-8it (30 ppm)
TCSOOCPE
16-Pin Plastic DIP
O·Cto +70·C
4-1/2 Digits (50 ppm)
TCSOOIJE
16-Pin CerDIP
-2S·C to +85·C
4-1/2 Dig~s (SO ppm)
TCSOOCOE
16-Pin SO
O·Cto +70·C
4-1/2 Dig~s (SO ppm)
PIN CONFIGURATIONS
CPEIIJE
COE
BUF 4
ANALOG
COMMON
CREF
CREF
VREF 8
2-2
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
ABSOLUTE MAXIMUM RATINGS
Supply (Vs+ to Vs-) ................................................... +18V
Positive Supply Voltage (Vs+ to GND) ...................... + 12V
Negative Supply Voltage (Vs- to GND) ..................... -12V
Analog Input Voltage (VIN+ or VIN-) ................... Vs+ to VsLogic Input Voltage .................... Vs+ +0.3V to GND --O.3V
Package Power Dissipation ...................................... 0.5W
Ambient Operating Temperature Range
Plastic Package (C) ............................... O°C to +70°C
CerDIP Package (I) ............................ -25°C to +85°C
Storage Temperature Range .................. --65°C to +150°C
Lead Temperature (Soldering, 60 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause pennanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
effect device reliabilily.
ELECTRICAL CHARACTERISTICS: TA = +25°C, Vs =±5V, unless otherwise specified. CAZ = CREF = 0.1 ~F.
Symbol
Parameter
Test Conditions
Min
TC500
Typ
TCSOOA
Typ
Max
Max
Min
50
-
-
30
0.005
-
-
0.003
Unit
Analog
Resolution
Note 1
ZSE
Zero-Scale Error
Note 1
ENL
End Point Linear~y
Note 1
NL
Best Case Straight
Line Linear~
Notes 1 and 2
DNL
Differential Nonlinearity
TCzs
Zero-Scale
Temperature
Coefficient
Full-Scale Symmetry
Error (Roll-Over Error)
Ratiometric Reading
SYE
FSTC
liN
CMRR
VCMR
Full-Scale Temperature
Coefficient
Input Current
Common-Mode
Rejection Ratio
-
Over Operating
Temperature Range
VIN = VREF = 1V
Over Operating
Temperature Range
External Reference
TC=o ppm/DC
VIN=OV
-lV,;;VCM';;1V
Common-Mode
Voltage Range
Vs=±5V
Integrator Output Swing
Vs =±5V
eN
Noise
%
%
%
0.005
-
0.005
-
-
0.0025
-
2
-
-
-
0.Q1
-
-
0.006
%
-
-
0.035
-
10
-
-
0.035
-
10
%
ppm/DC
-
6
15
pA
so
-
dB
1
0.Q1
-
6
15
-
SO
-
-
Vs+-1.5
-
Vs +o.s
-
VIN= OV
ppm
-
Vs +1.5
Analog Input Signal Range
-
30
0.005
0.Q1
-
0.003
-
0.0025
1
2
%
jJ.V/oC
Vs +1.5
-
Vs+-1.5 V
±4.1
-
Vs+-O.S
Vs +O.S
-
Vs+-O.S V
±4.1
-
-
30
-
V
jJ.Vp.p
Digital
Reference Input Signal
Range
Vs +1
-
Vs+-1
Vs +1
-
Vs+-1
V
4
-
-
4
-
-
V
-
-
0.4
-
-
0.4
V
-
3.5
-
-
V
-
-
1
V
-
0.05
VOH
Comparator Logic 1,
Output High
ISOURCE = SOO jJ.A
VOL
Comparator Logic 0,
Output Low
ISINK= 4mA
VIH
Logic 1, Input High Voltage
3.5
-
VIL
Logic 0, Input Low Voltage
-
0.05
-
-
4
-
IL
Logic Input Current
tD
Comparator Delay
Logic lor 0
2-3
1
-
4
-
jJ.A
iJ.S
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Test Conditions
Min
TC500
Typ
TC500A
Typ
Max
Max
Min
-
1.5
15
10
-
-
-8
-3
-
-
15
7
-
Unit
Power
-
Supply Current
Vs = ±5V, A = 1, 8 = 1
Power Dissipation
Vs=±5V
Positive Supply
4
Operating Voltage Range
Negative Supply
-3
Vs
Operating Voltage Range
Vs+-Vs
Supply Operating
7
Voltage Range
NOTES: 1. Integrate time ;;>200 ms, auto-zero time ;;>100 ms, VINT (peak) = 4V.
2. End point linearity at ±1/4, ±112, ±3/4 FS after full-scale adjustment.
Is
PD
Vs+
1
-
4
1
1.5
15
10
mA
mW
V
-8
V
15
V
OPERATIONAL THEORY
Auto-Zero Phase
The TC500 and TC500A are dual-slope, integrating
analog processors which are used with a microprocessor to
generate analog-to-digital conversions of up to 16 bits of
resolution. Although the TC500 and TC500A are virtually the
same, the TC500A is recommended for applications requiring more than 14 bits of resolution.
The TC500 and TC500A incorporate a system zero
phase and integrator output voltage zero phase, in addition
to the normal two-phase, dual-slope measurement cycle.
Reduced system errors, fewer calibration steps, and shorter
overrange recovery time result.
The TC500 and TC500A measurement cycle can use all
four phases, if desired.
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error
voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SW, switches. The
internal input points connect to analog common. The reference capacitor charges to the reference voltage potential
through SWR. A feedback loop, closed around the integrator
and comparator, charges the CAZ capacitor with a voltage to
compensate for buffer amplifier, integrator and comparator
offset Voltages.
Analog Input Signal Integration Phase
(1) Auto zero
(2) Analog input signal integration
(3) Reference voltage integration (deintegrate)
(4) Integrator output zero
Internal analog gate status is shown in Table I for each
phase (see the functional diagram).
The TC500rrC500A integrate the differential voltage
between the (+) and (-) inputs. The differential voltage must
be within the device's common-mode range.
The input signal polarity is normally checked via software at the end of this phase.
Table I. Internal Analog Gate Status
Internal Analog Gate Status
Conversion Phase
SW,
SWR'+
SWRr
SWz
Closed
Auto-Zero (A=O, 8=1)
Input Signal Integration
Closed
(A=1,8=0)
Closed'
Reference Voltage
Deintegration (A=1, 8=1)
Integrator Output Zero
(A=O, 8=0)
'Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
2-4
SWR
SWI
Closed
Closed
SW'Z
Closed
Closed
Closed
Closed
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
Reference Voltage Deintegration Phase
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output
back to zero.
Integrator Output Zero Phase
This phase guarantees the integrator output is at OV
when the system zero phase is entered and that the true
system offset voltages are compensated. This phase is
used at the end of the reference voltage deintegration
(DEINT) phase and SHOULD be used for all TC500ITC500A
applications. This phase MUST be used for resolutions of
more than 14 bits. If this phase is not used, the value of the
auto-zero capacitor (CAZ) must be about 23 the value of the
integration capacitor (C'NT) to reduce the effects of chargesharing. The integrator output zero phase should be programmed to operate until the output of the comparator
returns "high" (1) or for fixed time of about 2 ms.
ANALOG SECTION
Differential Inputs (VIN+ [Pin 11], VIN- [Pin 1OJ)
The TC500ITC500A operate with differential voltages
within the input amplifier common-mode range. The input
amplifier common-mode range extends from O.BV below
positive supply to O.BV above negative supply. Within this
common-mode voltage range, a common-mode rejection is
typically BO dB. Full accuracy is maintained, however, when
the inputs are no less than 1.5V from either supply.
The integrator output also follows the common-mode
Voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a
large, positive common-mode voltage with a near full-scale
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common-mode
voltage. For these critical applications, the integrator swing
can be reduced. The integrator output can swing within 0.9V
of either supply without loss of linearity.
Differential Reference
(VREF+ [Pin 9], VREF- [Pin 8])
The reference voltage can be generated anywhere
within 1V of the power supply voltage of the converter. Rollover error is caused by the reference capacitor losing or
gaining charge due to stray capacitance on its nodes. The
difference in reference for (+) or H input voltages will cause
a roll-over error. This error can be minimized by using a large
reference capacitor in comparison to the stray capacitance.
Phase Control Inputs (A [Pin 12], B [Pin 13])
The A, B unlatched logic inputs select the TC500/
TC500A operating phase. The A, B inputs are normally
driven by a microprocessor 1/0 port or peripheral 1/0 chip.
Comparator Output
By monitoring the comparator output during the fixedsignal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion.
The comparator output is high for positive signals and low
for negative signals during the signal-integrate phase.
During the reference deintegrate phase, the comparator
output will make a high-to-Iow transition as the integrator
output ramp crosses zero. The transition is used to signal the
processor that the conversion is complete.
The internal comparator delay is 4 jJ.s, typically.
Figure 1 shows the comparator output for large positive
and negative signal inputs. For signal inputs at or near zero
volts, however, the integrator swing is nonexistent. If common-mode noise is present, the comparator can switch
several times during the signal-integrate period. To ensure
that the polarity reading is correct, the comparator output
should be read and stored at the end of signal integrate.
A "low" (0) on the TC500ITC500A comparator, during
the deintegrate phase, signals the processor that the conversion is complete.
The comparator output is undefined during the autozero and the integrator output zero phases.
GENERAL THEORY OF OPERATION
Analog Common (Pin 5)
Analog common is used as V'N return during systemzero and reference deintegrate. If V'N- is different from
analog common, a common-mode voltage exists in the
system. This signal is rejected by the excellent CMRR of the
converter. In most applications, V'N- will be set at a fixed
known voltage (i.e., power supply common). A commonmode voltage will exist when V'N- is not connected to analog
common.
Dual-Slope Conversion Principles
The TC500 is an integrating analog-to-digital converter
building block. An understanding of the dual-slope conversion technique will aid in following the detailed TC500A
operation theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
2-5
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
I
SIGNAL
INTEGRATE - - ...
I
REFERENCE
.. DEINTEGRATE
SIGNAL
~"GAA"
i
vl~ REFERENCE
DB.....RA"
NT<_'~~
INTE~~~~~~ _ _ _......
~V\ZERO
'\,
CROSSING
OUTPUT
COMP~~~~~~ _ _ _--'
I
I
\
ZERO
CROSSING
COMP~~~~~~ _ _ _--'
A. Positive Input Signal
B. Negative Input Signal
Rgure 1. Comparator Output
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo·
site polarity constant reference voltage is then integrated
until the integrator output voltage retums to zero. The
TC500ITC500A automatically switch in the proper polarity
reference signal. The reference integration time is directly
proportional to the input signal (Figure 2).
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "rampdown." The TC500ITC500A comparator zero-crossing signals the processor to indicate the deintegrate cycle is
complete.
A simple mathematical equation relates the input signal,
reference voltage and integration time:
stiNT
VREF tOEINT
1
VIN (t) dt = -;,;=---;::=::..:..
RINT CINT 0
RINT CINT
where:
VREF = Reference voltage
tiNT
= Signal integration time (fixed)
tOEINT = reference voltage integration time (variable)
~'"
TC500lTC500A
ANALOG
INPUT
0-4----------0
REF
VOLTAGE
SWITCH DRIVER
PHASE
CONTROL
POLARITY
CONTROL
Rgure 2. Basic Dual-Slope Converter
2-6
CONTROL
LOGIC
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
__________________________________________________T_C_5_0_0A_
For a constant VIN:
V
IN =
V
tDEINT
REF tiNT
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large
conversion errors that plague succesive approximation converters in high-noise environments.
Integrating converters provide noise rejection automatically with at least a 20-dB/decade attenuation rate.
Interference signals with frequencies at integral multiples of
the integration period are, theoretically, completely removed.
This intuitively makes sense, since the average value of a
sine wave of frequency (1ft) averaged over a period (t) is
zero.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference signals.
The ability to reject such signals is shown by a normal mode
rejection plot (Figure 3). Normal mode rejection is practically
set to 50 to 65 dB, since the line frequency can deviate by a
few tenths of a percent (Figure 4).
Criteria for CAZ and CREF
C
AZ ~
C
This equation is for reference only. Use 0.11-LF capacitor
for all applications that have 8 or more conversions per
second. Use a 0.221-LF capacitor for 3 to 7 conversions per
second, and a 0.471-LF capacitor for 2 or less conversions
per second.
COMPONENT VALUE SELECTION
Integrating Resistor (RINT)
The desired full-scale input voltage and output current
capability of the input buffer and integrator amplifier set the
integration resistor value. The internal class A output stage
amplifiers will supply a 20-!-LA drive current with minimal
linearity error. RINT is easily calculated for a 20-!-LA full-scale
current:
Full-Scale Input Voltage (V)
R M (M)
Q=
20
~~
For loop stability, RINT should be ;;;,50 kn.
Reference Capacitor (CREF)
A 0.1-I-LF capacitor is suggested. Larger values may be
used to limit roll-over errors. Low leakage capacitors (such
as polypropylene) are required.
Auto-Zero Capacitor (CAl)
2N tiNT (VINT + VREF) ILEAKAGE
REF ~
VINT VREF
A 0.1-I1F polypropylene capacitor is suggested.
where:
N = resolution (bits)
ILEAKAGE = 15 pA
VINT (see Figure 2)
80
i70
z
o
"1'-
i3 60
...,w
W
II:
w
o
oJ
c(
~
~
t;
...,w
.......
20
V,
W
II:
0.1
~
~
,,
~
~ 10
NORMAL
MODE=20LOG ISIN60"I(h~~)1
60,,1(1 ±~~)
DEV = DEVIATION FROM 60 Hz
I =INTEGRATION PERIOD
oJ
~
II:
o
Z
1.0
0
0.11T
~
1""''''
lIT
101T
INPUT FREQUENCY
LINE FREQUENCY DEVIATION FROM 60 Hz (%)
Figure 3. Normal Mode Rejection
Input Frequency
T = MEASUREMENT
PERIOD
z
Q
30 REJECTION
20
0.01
30
:!!.
t=O.l sec
"
50
o
::::; 40
~
III
I
I I I
1"-
Figure 4. Intregrating Converter Normal Mode Rejection vs
60 Hz Line Frequency Variations
VB
2·7
IEJII
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
Signal-to-Noise Ratio
Integrating Capacitor (CINT)
The integrating capacitor should be selected to maximize integrator output swing. The integrator output will
swing to within 0.8V of Vs+ or Vs- without saturating.
Using the suggested 20-~ full-scale buffer output current, the integrating capacitor is easily calculated:
CINT =
SIN (dB) = 20 Log ( VINV
30 fL
The maximum performance of the TC500/TC500A require that overshoot at the end of the deintegration phase be
minimized. Also, the integrator zero phase may be terminated as soon asthe comparator output returns to "high" (1).
(tiNT) (VFS) ~ 5 tiNT (fLF)
(VINT) (RINT)
where:
tiNT = Integration period
VFS = Full-scale input voltage
VINT = Integrator output voltage swing
OVERSHOOT
INTEGRATOR
OUTPUT
(PIN 1)
A very important integrating capacitor characteristic is
dielectric absorption. Polypropylene capacitors give
undetectable errors at reasonable cost. Polyester and polycarbonate capacitors may also be used in less critical
applications.
The threshold noise (NTH) is the algebraic sum of the
integrator noise and the comparator noise. This value is
typically about 30 fL V. The graph shows how the value of the
reference voltage can influence the results of the final count.
Errors caused by the low-frequency buffer noise may be
reduced by increased integration times.
ZERO
CROSSING
COMPARATOR
OUTPUT (PIN 14)
I"
.1- DEINTEGRATE PHASE
INTEGRATE
PHASE
INTEGRATOR
ZERO PHASE
NOISE
s
Normal REF
Low REF
V REF
SLOPE (S) = RINT
e lNT
NTH = Noise Threshold
2-8
High REF
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
TC500A DESIGN EXAMPLE (See "Component Selection Example")
TIMING CONDITIONS: A) AZ PLUS ZI. ••••••••••••••• 10,000 CLOCK PERIODS (40 m.)
B) INT••••••••••.••••••••••••••••••• 10,000 CLOCK PERIODS (40 m.)
C) DEINT.. ••••••••••••••••••••••• VIN (V) 10,000 CLOCK PERIODS (14 bib)
D) CLOCK PERIOD .•.•••.. 411.
E) VFS............................. :t2.5V
CINT 1
V+
S
CINT
2
~V
CAZ
3
4
RINT
16
TYPICAL WAVEFORMS
GND
Vi
I
COMP
CAZ
~t- OU~
BUF
TC500A
5 ANALOG
COM
CREF
A
SEQUENCER
AND
CONTROL
LOGIC
13
12
I
I
+VIN
I
I
PIN 1
VREF
B
VREF
I
I
PIN 1 4 - - f T J - -
yiN
YiN
CREF
I
PIN
I 1-Y
I ;
-VIN
VREF
CINT
O.lI1 F
RINT
250kQ
CAZ
O.lI1 F
I
I
.J/i'\L
I
r-1
I
I
I
PIN14~
I
TC500A TO IBM PCIXT PRINTER PORT
+5Vo-.-------------------__- - - - - - - - ,
10kO
16
Vs
CREF
VREF
IBM
PCIXT
PORT
0378
HEX
I:
~t-
12
A
VREF
TCSOOA BUF
13
6
~"
9
TC04
8
4 100 kO
CAZ
F-----+I 8
10
1+____..;.14"'"1 COMP
CINT f-!-----..J 0.22 IIF
VtN
VIN
GND
1.!.!._~-..J\101/l0Ilk,..°O +
O.OlI1F
INPUT
t~,:~g~ f!5:.....-......____________~._,
15~__________~------------~
2-9
fI
CREF O.lI1 F
Vs
I
I
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
Interrupt Operation
One solution to overcome this condition is to have the
microprocessor monitor the comparator output. It can then
end the deintegration phase as soon as it sees a zero.
Another solution is to have the microprocessor enable
the interrupt and look althe comparator output. If the output
is high, the interrupt will be properly triggered. If the output
is low, end the deintegration phase and disable the interrupt.
Either solution will produce, reliable low voltage conversions.
The comparator output stays low during the Integration
phase (A=1 , 9=0) whenever the input polarity is negative. In
those cases where the input polarity is negative AND very
near zero, the zero-crossing occurs before the comparator
has had a chance to go positive. Thus, no negative-edge will
be generated and the microprocessor will not be interrupted.
With a negative input voltage very near zero, the output
of the comparator does not have enough time to get full
positive. This anomaly is caused by the comparator delay
and rise time limitations.
,
I
I..
ZERO
CROSSING
INTEGRATION WAVEFORM
"""- ~
INTEGRATION TIME
-.
DEINTEGRATION TIME
. . . . - COMPARATOR DELAY
j-
I
COMPARATOR OUTPUT~l
I
I
l-+-IDEAL
I
~ACTUAL
Rate of Conversion
Component Selection Example
The conversion times for the TC500fTC500A are a
function of many variables and constants. The dominate
component is CINT:
Known:
Conversion Time (sec) =
1)
2)
3)
4)
5)
Supply voltage for TC500A
Maximum input voltage
Integration time
Output resolution (bits)
Clock period
0.4 x CINT (IlF) x (2 + (V INN REF))
The assumptionsforthis equation are suggested but not
strictly required. They are:
Assume:
Auto-zero time (TAll = Integration time (TNT)
Peak integration voltage (VI NT) = 4V
Maximum buffer current (VIN(MA)()/RINT) = 20 J1A
2·10
Vsup = ±5V
VIN(MAX) = ±2.5V
TINT=40ms
N=14bits
tCLOCK =4 Ils
(Vsup)
(VIN(MAX)
(TINT)
(N)
(tCLOCK)
Vsup = IVsupl
VIN(MAX) = IVIN(MAx)1
INTEGRATING CONVERTER
ANALOG PROCESSORS
TC500
TC500A
VIN(MAX)
RINT=--ISUF(MAX)
Step 1 : Calculate RINT
Normalization
The reference voltage can be adjusted to scale the
deintegrate count to be directly equivalent to the input
voltage.
Where ISUF(MAX) ~ 20 IlA
RINT = 2.5V = 125K
201lA
Since:
KINT = CountsNolt
VREF
If:
VREF is adjusted such that
Use 130K
:. IsuF =
;3~~
= 19.2 IlA
10000 Counts
VREF = 10000 CountsNolt
C INT= TINT ISUF(MAX)
VINT
Step 2: Calculate CINT
Where VINT= Vsup -1V = 4V
~
KINT
= 1V
10000 CountsNolt
and N ~ 14.61 Bits
Then:
KOEINT =
e.g.,
If KDEINT = 18357 Counts,
then VIN = 1.8357V
100~V
CINT = 40 ms 19.2 IlA = 0.192 ~F
4V
Use 0.2
~F
BONDING DIAGRAM
V 1NT C1NT
Step 3: Calculate VREF
RINT
TDE'NT
Where T OEINT = 2N tCLOCK
V
REF
= 4V'0.2~F'130K=1587 V
2N !cLOCK
. ...
Step 4: Calculate integrate count
Where RINT
.J
TINT
KINT=-tCLOCK
40ms
-4-- = 10,000 Counts
~s
~
~~~~~~~~~-J
J
KINT = VIN 10,000
Results: KOEINT = VIN V
REF
1.587...V
Where KOEINT = Number of clock periods
during T OEINT
2-11
NOTES
2·12
~~TELEDYNE
COMPONENTS
TC800
1S-BIT PLUS SIGN, INTEGRATING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
15-Bit Resolution Plus Sign Bit
Dynamic Range ............................................... 96 dB
Integrating Dual-Slope Converter
-Monotonic
- Eliminates 50/60 Hz 'Line' Interference
- High-Noise Immunity
- Auto-Zero Cycle Eliminates Trimming
-Incorporates Integrator Zero Cycle for Fast
Overload Recovery
Three-State Data Bit/Sign Outputs
- 8-Bit or 16-Bit Parallel Data Transfer
to f..lProcessor Bus
UART Control Signals
- Serial Data Transmission
- 'Handshake' Data Transfer
- Distributed Control Systems
- Fiber-Optic Transmission Systems
•
•
•
•
•
•
•
•
•
Easy Conversion Cycle Monitoring and Control
- Data Valid Output Signal
- Continuous or Convert-on-Command Operation
High-Impedance Differential Input
- Maximum Input Current .............................. 15 pA
Low Input Noise .......................................... 15 f..lVp.p
On-Chip Crystal Oscillator for 2.5 ConversionslSec
-fXTAL = 2.4576 MHz
-Integration Period (Rejects 50, 50, 400 Hz
Interference Signals) ................................ 100 ms
Supply Operation ................................................ ±5V
- Low Power Dissipation ••••••...•••••••..••••••••••• 20 mW
Static-Discharge Protected Inputs
Available in 60-Pin Flat Package
FUNCTIONAL DIAGRAM
YBUF Csz
35
2.
34
33
32
r- - ------ ------- ---I
I
I
I
I
I
I
I
I
+ 37: $1
YIN D-t--OO......-I----+iXh
VINi-oJ."r-_-+
ANALOG COMMON """'~---if-
VIN+ o-e.l--_-+~
CH4+
CH",
CH2+
40
LBEN
41
iiBEN
'.,',.
CHI.
'".
,
MODE
DROST
u. OE
"
EN
AST
v+
NOTE: Pin numbers are
for 68-pin PLCC package.
2-31
12-BIT ~P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V+) ................................... +6.2V
Negative Supply Voltage (V-) .................................. -9.0V
Analog Input Voltage Range (Note 1) .................. V+ to VReference Input Voltage Range .......................... V+ to VDigital Input or Output
(Note 2) .......................................... V+ to DGND - 0.3
Power Dissipation (Note 3) ........................... 1W @ +85°C
Operating Temperature
Commercial .............................................. ooC to 70°C
Industrial ............................................ -25°C to +85°C
Storage Temperature ............................. -65°C to +150°C
Lead Temperature (60 sec.) .................................. +300°C
NOTE: All devices contain diodes to protect inputs against damage due to
high-static voltages orelectric fields. However; it is advised precautions be
taken not to exceed maximum recommended input voltages. All unused
inputs must be connected to an appropriate logic level (VDD or GND).
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
pennanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
NOTES: 1. Input voltages may exceed supply voltages if input current is
limited to ±1 00 I'A.
2. Connecting any digital inputs or outputs to voltages greater
or less than GND may cause destructive device latchthan
up. Therefore, it is recommended that inputs from sources
other than the same power supply should not be applied to
the TC804 before its power supply is eslsblished. In multiple
supply systems, the supply to the device should be activated
first.
3. This limitreferstothatofthe package and will notoccurduring
nonnaloperation.
v,
ORDERING INFORMATION
Part No.
TC804CLS
tC804CBQ
TC8041LS
Package
Temperature
Range
68-pin PLCC
.60-pin Plastic
Surface Mount
68-pin PLCC
2-32
12-BIT /-tP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
ELECTRICAL CHARACTERISTICS:
V+ = 5V, V- = -5V, 15 Conversions/Sec,
(unless otherwise noted)
Symbol
Test Conditions
Parameter
Min
1MHz Crystal, TA = 25°C
Typ
Max
-
5.0
7.0
7.5
10
Unit
Analog Multiplexer Section
rDsON
On Resistance
-25°C S TA S 85°C
KO
tBM
Break-belore-Make
250
450
-
nSec
tAD
Address Delay, Transparent
-
150
180
nSec
-
70
650
750
nSec
nSec
-------
tww
Address Set-up, Write
50
tWR
Write Delay
-
CORR
Channel Ofl Rejection Ratio
-25°C S TA S 85°C
liN = 10Hz
-
600
650
100
-
dB
Converter Section
Zero Input Reading
Ratiometric Reading
VIN = 0, VFS = 409.6mV
VIN = VREF = 204.8mV
00016
00016
00016
NLE
Non-linearity Error
VFS = 204.8 or 409.6mV
-1
7FF16
±0.2
1
ROE
RolI·over Error
VFS = 204.8 or 409.6mV
-1
±0.2
1
CMRR
Common-mode
Rejection Ratio
VCM = ±1V, VIN = OV
-
50
100
V-+l.5
-
--------
Common-mode Voltage Range
VCMR
Vn
Noise (aver. pk-pk)
III
Input Leakage Current
TCo
Zero Reading Drilt
TCFS
Full-scale Gain Tempeo
TA=25°C
DoC S TA S 70°C
-25°Cs T A S 85°C
DOC S TA S 70°C
-25°C S TA S 85°C
Over Range Recovery
(Next Conversion)
Count
Count
Count
('
Count
IlVN
V+-l.5
V
-
15
50
-
20
100
150
45
200
300
IlV
pA
0.2
0.8
1.0
2.0
IlV/oC
-
DoC S TA S 70°C
-25°C S TA S 85°C
-
1
7
5
15
ppm/°C
-
VFS = 204.8mV
-
±1
±2
Count
V
SupplylReference Section
V+
V-
Positive Supply Voltage
4.5
5.0
5.5
Negative Supply Voltage
-4.5
-5.0
-5.5
V
1+
Supply Current V+ to GND
1.5
2.0
2.0
2.5
mA
-1.5
-2.0
-3.0
-2.0
-2.5
-3.2
mA
-
25
30
50
75
ppm/°C
._._--
-25°C S TA S 85°C
--_ ..
1-
Supply Current V- to GND
-25°C S TA S 85°C
(wI respect to V+)
VREF
Reference Voltage
TCREF
Relerence Voltage Tempco
oosTAs70°C
-25°C S TA S 85°C
-2.8
V
Digital Section
VOH
Output High (SYSCLK, SIP)
IOl = -1001lA
-
4.5
-
V
VOH
Output High (B 1-B 12, OR,
POL, STATUS)
IOl=-lOOIlA
3.5
4.7
-
V
VOL
Output Low (SYSCLK, SIP)
IOl= 0.5mA
-
0.2
-
V
VOL
Output Low (B 1-B12, OR,
POL STATUS)
IOl= 1.6mA
-
0.2
0.4
V
B1-B12, OR, STATUS
-
.01
1.0
IlA
-----
IOl
Output Leakage
(High Impedance)
---
2-33
-
12-BIT J,lP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Test CondHlons
Parameter
Min
Typ
Max
-
-
50
30
100
30
50
-
UnH
Digital Section (Cont.)
Control 110 Loading
Input High Voltage
Input Low Voltage
Input Pull-up Current
TEST
Input Pull-down Current Mode
Mode Input Pulse Width
WR,WE
VIH
VIL
Ipu
Ipo
tw
LBEN, HBEN, OE
2.5
-
(All except TEST)
-
1
-
pF
V
V
JJ.A
JJ.A
-
J.lA
nSec
5.0
2.0
3.0
MHz
rnA
rnA
Oscillator Section
lose
OSCOH
OSCOL
Frequency of Oscillation
Output Current High
Output Current Low
0.8
- --
1.0
1
1.5
ANALOG MULTIPLEXER TIMING DIAGRAM
A(0-2) OLD ADDRESS (X)
NEW ADDRESS (V)
A(0-1) OLD ADDRESS (X)
X NEW ADDRESS (V) XXX
'ww
CHX
CHX
CHV _ _ _ _ _ _
I. __
.'_._'B_M_I-....I
CHV
------------------~
Write Mode
Transparent Mode
2-34
12-BIT IlP-COMPATIBLE
MULTIPLEXED AID CONVERTER
_________________________________________________T_C_8_0_4
PIN DESCRIPTION
6O-Pln
Flat
Pack
6S-Pln
PLCC
Symbol
Description
62
DGND
Digital Ground, OV, Ground return for all input and output logic.
2
63
TEST
Input HIGH-Normal operation, Input LOW-Force all bits high. (For test
purposes only.)
3
64
INT/EXT
Oscillator Select:
Input HIGH-8elect Crystal Oscillator
Input LOW-8elect External Oscillator Input
4
65
OSC1
Crystal or Clock input
5
66
Crystal
6
67
OSCo
SYSCLK
7
68
FSo
Conversion Rate (Bit 0)
System Clock-buffered system clock output
Conversion Rate (Bit 1)
8
1
9
2
FS1
SIP
Signal Integrate Phase
10
3
RUN/HOLD
Run or Hold:
11
4
SGUDIF
12
5
WE
Write Enable: Input HIGH-Multiplexer Address Write Disabled,
Input LOW-Multiplexer Address Write Enabled
13
6
WR
Write:
Input HIGH-Multiplexer Address Latched,
Input LOW-Multiplexer Address Enabled
14
7
RST
Reset Latch:
Input HIGH-Muttiplexer Enabled,
Input LOW-Muttiplexer Disabled
15
8
A2
Analog Multiplexer Address (Bit 2, Latchable)
16
11
A1
Analog Multiplexer Address (Bit 1, Latchable)
17
12
Ao
Analog Multiplexer Address (Bit 0, Latchable)
18
13
EN
Analog Multiplexer Enable (Address QualWier, Latchable)
19
20
21
14
15
16
VCH8+/CH4-
22
17
CH7+/CH3CH6+/CH2-
Negative Supply Voltage
Analog High (Chan. 8)1Analog Low (Chan. 4)
Analog High (Chan. 7)/Analog Low (Chan. 3)
23
18
CH5+/CH1-
Analog High (Chan. 5)/Analog Low (Chan. 1)
VINANALOG
COMMON
Mux OUVAnalog in (Low)
24
19
25
20
26
21
27
22
28
29
30
Input HIGH-Performs continuous conversions,
Input LOW-Converter will stop in Auto-Zero.
Analog Mux Mode: Input HIGH-8elect 8 Channel, Single-ended,
Input LOW-Select 4 Channel, Differential.
---------.-----
Analog High (Chan. 6)/Analog Low (Chan. 2)
Internal ground reference for analog circuits
Mux Out/Analog In (High)
VIN+
CH4+
Analog High (Chan. 4)
23
CH3+
Analog High (Chan. 3)
24
CH2+
Analog High (Chan. 2)
CH1+
31
25
28
VREF+
Analog High (Chan. 1)
Reference Voltage High
32
29
CREF+
Reference Capacitor High
Reference Capacitor Low
33
30
CREF-
34
31
VREP-
Reference Voltage Low
35
32
BUFIN
Buffer Input
36
33
BUFOUT
Buffer Output
37
34
CAZ
Auto Zero Capacitor
2-35
_._---------------_ ..
IEJII
12-BIT /lP-COMPATIBLE
MULTIPLEXED AID CONVERTER
Description
Integrator Output
Pos~ive Supply Voltage
Reference Output
Data Request, Input (2)
Output Enable, Input(1)/Output(2)
Low Byte Enable, Input(1)/Output(2)
High Byte Enable, Input(1)/Output(2)
Mode Select, Input:
LOW-Direct Output Mode(1)
HIGH-Hand Shake Mode(2)
Status Bn, Output: HIGH during Integrate and Deintegrate until data is latched,
LOW during Auto-Zero and Integrate-Zero
Polar~
Bit, Output: HIGH-Posnive,
LOW-Negative
Over Range Bit, Output: HIGH-0verrange,
LOW-Non-Overrange
Data B~ 12 (Most Signfficant Data Bit)
Data Bit 11
--------,::-'-'----------=---=--,----------------------------Data Bit 10
Data Bit 9
--------="---------=---=----c=-=-cc=-cc-.,.,.,---=,---:--,--,--c-=c-=..,...,--,-----,,---=,--,-------------------Data Bit 8 (STATUS in High Byte of 8-bit BUS Mode. See Text)
Data Bit 7
=:-----::-:-----:::-'---------=-Da--:t-a-=B::-n-=6-------------------------------Data Bit 5
Data Bit4
Data Bit 3
Data Bit 2
Data Bit 1, (Least Significant Bit)
~---~----,~---------=---=--:--------------------------
2-36
12-BIT ~P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
MODE SELECTION AND DATA TRANSFER
INTERFACING (All pin references are to PLCC
Status can also be read on the B8 output when HBEN is low
and LBEN is high.
package)
INTERFACING
The direct output mode is a fully complemented microprocessor interface which can support either an 8 or 16 bit
data bus. The microprocessor programming has direct
control over the data transfer technique. The status bit
(STATUS) from the TC804 supplies the information to. the
microprocessor to insure proper timing and data handling.
The TC804 will be in the direct output mode as long as
the MODE input is LOW. An internal pull-down resistor
insures that this is the default mode if it is left unconnected.
When the TC804 is in the indirect mode, OUTPUT
ENABLE (OE), LOW BYTE ENABLE (LBEN) and HIGH
BYTE ENABLE (HBEN) become inputs. These inputs are
then used to control the data transfer. The DATA REQUEST
(DRQST) input is not used and should be tied HIGH. (see
"DIRECT Interfacing")
Direct Mode
Combinations of chip enable and byte enable control
signals which may be used when interfacing the TC804 to
parallel data lines are shown in Figure 2. The OE input may
be tied low, allowing either byte to be controlled by its own
enable (Figure 2A). Figure 2B shows the HBEN and LBEN
as flag inputs, and OE as a master enable, which could be
the READ strobe available from most microprocessors.
Figure 2C shows a configuration where the two byte enables
are connected together. The OE is a chip select, and the
HBEN and LBEN may be used as a second chip select or
connected to ground.
Direct Output Mode Data Transfer
OE
AS INPUT
The low order byte (bits 1 through 8) and the high order
byte (bits 9 through 12 plus the polarity and overrang~ bits)
are accessible under control of OE (pin 38), LBEN (Pin 40)
and HBEN (pin 41). These three inputs are all active LOW.
Internal pullup resistors are provided for an inactive HIGH
when left open. A LOW on OE will permit a LOW on input
HBEN and/or LBEN to output data to the bus. A LOW on
HBEN selects the 6-bit high data byte, a LOW on LBEN
selects the 8-bit low data byte and a LOW on both HBEN and
LBEN selects the whole 14-bit data word.
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output (pin 45).
This will prevent accessing the data while it is being updated.
HBEN
AS INPUT
LBEN
AS INPUT
HIGH-BYTE
DATA
LOW-BYTE
DATA
----- =HIGH IMPEDANCE
Figure 1
A.
B.
GND
MODE
MODE
~'"
B9-812
POL,OR
C.
~'"
B1-B12
POL,OR
MODE
14
~'"
ANALOG
IN
RUN/HOLD
LBEN
CONTROL
LBEN
GNDOR
CHIP SELECT 2 -
Figure 2
ANALOG
IN
RUN/HOLD
CONVERT
6
B1-B8
RUNtHOLo
CONVERT
......- - - - - '
Direct Mode Chip and Byte Enable Combinations
2-37
OE
B9-B12
POL,OR
TC804
TC804
B1-B8
CHIP SELECT
GND
OE
6
TC804
ANALOG
IN
CHIP SELECT 1
GND
TC804 Direct Mode Output Timing
CONVERT
BVTEFLAGS
12-BIT JlP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
DIRECT MODE TRUTH TABLE
Inputs
MODE
0
0
0
0
0
DRQST*
1
1
1
1
1
Outputs
LBEN
X
0
1
0
1
OE
1
0
0
0
X
HBEN
X
0
0
1
1
STATUS
1
0
0
0
0
B1-B8
high Z
Bg-B12, OR, POL
high Z
low byte
high byte
highZ"
high byte
low byte
highZ
highZ
high Z
------
DROST should be tied high.
··Output 88 is active, and reflects the converter status. This permits the status to be monitored without requiring a separate JLP input pin for the STATUS output (pin 45).
Table 1. TC804 Direct Mode Timing Requirements
Symbol
Description
Min
Typ
Max
t8EA
Byte Enable Width
200
tDAB
Data Access Time
From Byte Enable
500
150
300
ns
tDHB
Data Hold Time
From Byte Enable
150
300
ns
tCEA
Chip Enable Width
tDAC
Data Access Time
From Chip Enable
Data Hold Time
From Chip Enable
500
200
400
ns
200
400
ns
tDHC
300
Units
ns
ns
2-38
12-BIT ~P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
GNO
ANALOG
SELECT
MODE
~'"
OE
89-812
POL,OR
81-88
STATUS
8255
(MODE 0)
8
-----(FLAG)
AO-A1
CS
PAS-PAO
..sv
RUN/HOLD
TC804
ANALOG
IN
07-00
6
87C48
8008,8080,
8085, 8048, ETC.
PCS
GNO------~--~
Figure 3
Handshake Mode (MODE
Full-Time Parallel Interface to MCS-48, -80, -85 Microcomputer
=1 orJl)
Handshake Mode Data Transfer
The TC804 actively controls the data transferto peripherals through the handshake data transfer mode. In this
mode, OE (pin 38), LBEN (pin 40) and HBEN (pin 41) are
each TTL compatible outputs. A LOW on OE Signals that
valid data is available forthe peripheral. A LOW on HBEN or
LBEN indicates which data byte is being transferred. A HIGH
input to the TC804 on DROST (pin 38) initializes the data
transfer. The high byte is transferred first followed by the low
byte. Data DROST may be taken LOW to delay the transfer
between data bytes.
Handshake output sequences may be performed on
demand by triggering the converter into handshake mode
with a low to high edge on the MODE input. A handshake
output sequence triggered is shown in Figure 5. The DROST
input is low when the converter enters handshake mode.
The whole output sequence is controlled by the DROST
input, and the sequence for the first (high order) byte is
similar to the sequence for the second byte.
These diagrams also show that the output sequence
can take longer than a conversion cycle. New data will not
be latched when the handshake mode is still in progress and
is therefore lost.
The handshake mode is an alternative means of interfacing the TC804 to digital systems. It provides a means for
having the TC804 become active in controlling the flow of
data. This mode allows a direct interface between the TC804
and standard UART's with no external logic required. The
TC804 provides all the control and flag signals necessary to
sequence the data into the UART and initiate the serial
transmission.
The handshake mode is activated when the MODE
input pin is held high. The data transfer sequence is started
at the end of the conversion cycle and after new data has
been stored in the output latches.
The data transfer sequence may also be initiated at any
time during the conversion cycle by a positive going pulse
applied to the MODE pin. If the low to high transition occurs
while new data is being stored, the entry into the handshake
mode is delayed until the data is stable.
Whenever the handshake mode has been activated,
OUTPUT ENABLE (OE), LOW BYTE ENABLE (LBEN) and
HIGH BYTE ENABLE (HBEN) become outputs. These
outputs are then used to "talk to" the UART. The DATA
REOUEST (DROST) input is used by the UART to transfer
data. (see "UART Interfacing")
2-39
12-BIT /lP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
HANDSHAKE MODE TRUTH TABLE
Inputs
MODE1
1
X
X
X
X
Outputs
DRQST
QE2
0
1
JI..
1
0
1
1
LBEN
1
HBEN
1
STATUS
1
1
0
0
0
High Z
0
high Z
1
1
JI..
0
0
0
1
1
1
1
Bg-B12, OR, POL
B1-Bs
highZ
high Z
high byte
- . - -----------_._--high by1e
highZ
low by1e
high Z
------ - - - - - - - - - - - _. ._------
high Z
NOTES: 1_MOOE pulsed high or held high
2. Dat> strobe
ANALOG
SELECT
RD WR
11"
TC804
ANALOG
IN
B9--B12
POL,OR
6
Bl-B8
8
07-00
AO-Al
CS
PAiPAo
OE
87C48
8008,8080,
8085, 8048, ETC.
8255
(MODE 1)
PC4
SEND
RUN/HOi])
PC6
MODE
PC7
Figure 4
INTR
Handshake Interface-TC804 to MCS-48, -80, -85
2-40
12-BIT f.!P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
INTEGRATOR
OUTPUT
ZERO CROSSING OCCURS
I¥ ZERO CROSSING DETECTED
'J/-
~
INTERNAL CLOCK
---I"T"'L-I--- r--~ ~~ ~rL..
INTERNAL LATCH
STATUS OUTPUT
------Ir-I--+-----f--I-----+---1f----------1
1_-1-------/--+------+-.., TERMINATES
UART
INTERNAL MODE _.NO_R;,;,;M
_ _ _ _ _ _-I¥ DRQST SENSED"
OE
DRQST SENSED,,*, /
UART MODE
MODE LOW,
NOT IN
HANDSHAKE
MODE
DISABLES
I'- - - - OUTPUTS
....
'CEILOAD,
I__ J;_J; __
HBEN,
tt
---~~---+-~
HBEN
~
_______________________/
HIGH-BYTE DATA , - - - - - - \ , -----
~
LBEN
lOW-BYTE DATA
LBEN, OE
DATA VALID
'---------------t---t----------%~~rnWtil~ =DON'T CARE
-----
Figure 5
iI-_LL_
I\..
MODE HIGH ACTIVATES
CElLO AD, HBEN, LBEN
=W~W~M~l1,~"t.cE
~~D~A~TA~V~A=U=D~
-----------
_LL -_THREE-STATE
WITH PULL-UP
TC804 Handshake with DRQST Input Held Positive
ZERO CROSSING OCCURS
INTEGRATOR OUTPUT _ _-"Ir-t¥=-_ZE_RO CROSSING DETECTED
INTERNAL CLOCK
INTERNAL LATCH - - - - - - '
STATUS OUTPUT
-------i
INTERNAL MODE
;.;,~~_~;,;,;~_ _ _ _ _-!I-D~R~Q~S~T:----S \--+-1-----'1 r--f--Ilr;.~~I~IieS
~SENSED
SEND INPUT (UART TBRE) .;;",,''-A_~'';%'I''M'''''-"%'%y
OE OUTPUT (UART TBRl)
-------1--;..
HBEN
------+-l
----'~
HIGH-BYTE DATA ------------- -LBEN
----------s, \--- -DATA VALID
------+-+----J, r---+-ol..
LOW-BYTE DATA .------------ -~I,Mlt.tlM!
=DON'T CARE
Figure 6
__ u _
---------\~---
DATA VALID
=THREE-STATE HIGH IMPEDANCE
TC804 Handshake-Typical UART Interface Timing
2-41
--
-------
12-BIT IlP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
TC804 ANALOG MULTIPLEXER
The on-board analog multiplexer can be configured for
eight channel, single-ended input or for four channel, differential input. The signal/differential input (SIG/DIF) selects
the configuration. The eight channel mode is selected when
SIG/DIF (pin 4) is tied HIGH and the four channel mode is
selected when SIGIDIF is tied LOW. Either mode of operation permits both latched and transparent addressing.
A LOW on the reset input (RST) or writing a low into the
enable input (EN) opens all (4 or 8) channels which permits
direct input through the dedicated analog inputs (VIN+ and
VIN-). An external analog multiplexer may be used instead
of the internal multiplexer or in conjunction with it. (See
"Analog Multiplexer Expansion").
ANALOG MULTIPLEXER TRUTH TABLE
SGL/DIF
WE
WR
RST
EN
A2
A,
Ao
X
X
X
X
X
X
0
X
0
X
0
X
0
1
1
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Converter Input
Note
I
I
(1)
VIN+
VIN+
VINVIN-
(1)
no change
(2)
no change
(2)
x =don't care
NOTES:
1. Analog multiplexer disables. V,N+ and V,,,.. are inputs to 1he AID converter.
2. Analog channel address is latched. VIN+ and VIM- are the outputs of the multiplexer as wen as the inputs to the AID converter. The multiplexer channel selection
cannol be changed if either WE or WR is HIGH.
EIGHT CHANNEL OPERATION (SGUDIF
=1)
Each of the single-ended inputs is referenced to VIN- and must comply with the same common-mode input.
A,
A2
SGL/DIF
WE
WR
RST
EN
1
1
1
0
0
0
1
1
1
1
1
3-bit address
1
3-bit address
.s-
.s-
O
Ao
Converter Input
CHN+
CHN+
CHN+
3-bit add ress
VINVINVIN-
N =1 thru8 (Ao. A,. A2)
FOUR CHANNEL OPERATION (SGUDIF = 0)
Bit 3 of the multiplexer address (A2) has no function when the four channel mode is selected. Each input is independently
differential and may have different common-mode offsets.
A,
SGL/DIF
WE
WR
RST
EN
A2
0
0
0
0
0
0
1
1
1
1
1
1
X
2-bit address
X
X
2-bit address
.s-
.s.0
Ao
2-bit address
x = don·t care. N = 1 thru 4 (Ao. A,)
2-42
Converter Input
CHN+
CHN+
CHN+
CHNCHNCHN-
12-BIT /lP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
ANALOG MULTIPLEXER ADDRESSING (all pin
ANALOG SECTION (all pin references are to PLCC
references are to PLCC package)
package)
Single-Ended/Differential (SIG/DIF, pin 4)
The analog section of the TC804 will perform conversions at a rate determined by the clock frequency and the
inputs to the Conversion Rate Selection (bit 0, pin 7 and bil
1, pin 8). (See Conversion Rate table page 20).
Each measurement cycle is divided into four phases.
They are: 1) Auto-Zero (AZ), 2) Signal Integrate (INT), 3)
Reference Deinlegrate (DE) and 4) Zero Integrate (ZI).
If SIG/DIF is HIGH then the 8-channel, single-ended
mode is selected. If SIGIDIF is LOW then the 4-channel,
differential mode is selected.
The analog multiplexer has an internal address
demultiplexer which is configured as either a "2 of 8" f~r 4channel operation or as a "1 of 8" for 8-channel operation.
1) Auto-Zero
Write (WR, pin 6)
The WR input may be held LOW in order to employ
transparent address operation. In transparent operation, the
multiplexer switches respond directly to the inputs on the
address lines (Ao, A" A2) and Enable input (EN, pin 13).
The "latched" mode is entered whenever WR goes
HIGH. The inputs on the address lines have no effect on the
multiplexer switches until WR is pulsed LOW. These address lines may now be used for another purpose.
Write Enable (WE, pin 5)
The Auto-Zero phase has a duration of from 2048 10
6144 counts. During this phase, the analog input Signal and
reference voltage are disconnected from the analog section.
The Auto-Zero capacitor (CAZ) is charged to a value which
represents the total system offsets. The charge on CAZ will
then be used to compensate the input during the signal
integrate (INT) and the reference deintegrate (DE) phase~.
This phase is also used to charge the reference capacItor (CREF) to the value of the reference voltage.
2) Signal Integrate
The WE input must be LOW in order for the WR input to
be enabled. The WE and WR inputs are AND'ed internally.
The Signal Integrate phase is selected for 2048 counts
(Integrate Count). During this phase, the analog input Signal
is connected to the input of the buffer amplifier. The integrating amplifier will charge the integrate capacitor (CINT) at a
rate determined by the value of the input signal.
At the end of the signal integrate phase, the voltage on
CINT will be equal to:
Enable (EN, pin 13)
The EN input is like an address input in that it may also
be latched in by a LOW to HIGH transition on the WR input.
Reset (RST, pin 7)
VINT = VIN x Integrate Count x fcLOCK
RINT • CINT
The RST input overrides all other inputs to the analog
multiplexer. All of the multiplexer switches are open whenever RST is LOW.
(equ 1)
3) Reference Deintegrate
ANALOG MULTIPLEXER EXPANSION
The length of the Reference Deintegrate phase is determined by the absolute value of the voltage on CINT at the end
of the Signal Integrate phase, (Le. VINT). The reference
capacitor (CREF) is connected to the input of .the buffer
amplifier in the opposite phase of the Input signal. The
integrating amplifier will then cause the integrate ~apacit~r
(CINT) to start discharging at a constant rate. ThiS rate IS
determined by the value of the reference voltage. The 12-bit
counter counts clock pulses during this phase and stops
when CINT is fully discharged (Le. zero-crossing).
The final count of the 12-bit counter is the binary value
of the input signal and is equal to:
The analog multiplexer section of the TC804 may be
expanded by using an external multiplexer either in conjunc.
tion with, or instead of, the internal multiplexer.
The extemal multiplexer may be selected at any time
when the internal multiplexer is disconnected:
A LOW on the RST input or writing a logic LOW into the
enable bit (EN, WR, and WE are LOW) will disconnect the
internal multiplexer output from the analog input to the
TC804 converter.
If an external analog multiplexer is to be used alone then
RST should be tied LOW. If an external analog multiplexer
is to be used in conjunction with the on-board multiplexer,
EN should be used to switch between multiplexers.
Deintegrate Count =
2-43
RINT. CINT
fCLO~ (equ 2)
12-81T JlP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
4) Zero Integrate
De-Integrate Phase (DI)
The Zero-Integrate phase is invoked only when an
overrange has occurred. It has a duration of up to 1024
counts. This phase is used to completely discharge CAZ and
CINT prior to the Auto-Zero phase. This insures that there is
no residual charge on either capacitor which may cause a
false auto-zero.
Input high is connected across the previously charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (established by AUTO-ZERO) with a fixed slope. The time, represented by the numberof clock periods counted fortheoutput
to return to zero, is proportional to the input signal.
Dual Slope Conversion Equation
(combine equ 1 and equ 2)
Deintegrate Count =
VIN
VREF
Zero-Integrator Phase (ZI)
x Integrate Count
The ZI phase only occurs when an input overrange
condition exists. The function of the ZI phase is to eliminate
residual charge on the integrator capacitor after an overrange
measurement. Unless removed, the residual charge will be
transferred to the auto-zero capacitor and cause an error in
the succeeding conversion.
The ZI phase virtually eliminates hysteresis or "cross
talk" in multiplexed systems. An overrange input on one
channel will not cause an error on the next channel measured. This feature is especially useful in thermocouple
measurements, where unused (or broken thermocouple)
inputs are pulled to the positive supply rail.
During ZI, the reference capacitor is charged to the
reference voltage. The Signal inputs are disconnected from
the buffer and integrator. The comparator output is connected to the buffer input, causing the integrator output to be
driven rapidly to OV (Figure 8). The ZI phase only occurs
following an overrange and lasts for a maximum of 1024
clock periods.
DETAILED DESCRIPTION
Analog Section
The Functional Diagram shows a block diagram of the
Analog Section of the TC804. The circuit will perform conversions at a rate determined by the clock frequency (8192
clock periods per cycle), when the RUN/HOLD input is left
open or connected to V+. Each measurement cycle is
divided into four phases as shown in Figure 8. They are: (1)
Auto-Zero (Al), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase (AZ)
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, CAZ, to compensate for
offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the Al
accuracy is limited only by the noise ofthe system. The offset
referred to the input is less than 101lV.
Differential Input
The TC804 has been optimized for operation with analog-common near digital ground. With +5V and -5V power
supplies, a full ±4V full-scale integrator swing maximizes the
analog section's performance.
A typical CMRR of 86dB is achieved for input differential
voltages anywhere within the typical common-mode range
of 1.0 Volts below the positive supply to 1.5 Volts above the
negative supply. However, for optimum performance the
VIN+ and VIN- inputs should not come within 2V of either
supply rail. Since the integrator also swings with the common-mode voltage, care must be exercised to assure the
integrator does not saturate. A worst case condition is near
a full-scale negative differential input voltage with a large
positive common-mode voltage. The negative input signal
drives the integrator positive when most of its swing has
been used up by the positive common-mode Voltage. In
such cases, the integrator swing can be reduced to less than
Signal Integrate Phase (51)
The buffer and integrator inputs are removed from
COMMON and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter power supply, input low can be tied
to analog common to establish the correct common-mode
voltage.
2-44
12·BIT IlP·COMPATIBLE
MULTIPLEXED AID CONVERTER
________________________________________________T_C_8__
04
the recommended ±4V full-scale value, with some loss of
accuracy. The integrator output can swing to within 0.3 Volts
of either supply without loss of linearity.
Differential Reference
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Rollover
voltage is the main source of common-mode error. It is
caused by the reference capacitor losing or gaining charge
due to stray capacity on its nodes. With a large commonmode voltage, the reference capacitor can gain charge
(increase voltage) when called upon to deintegrate a
positive signal and lose charge (decrease voltage) when
called upon to deintegrate a negative input signal. This
difference in reference for (+) or H input voltage will cause
a roll-over error. This error can be held to less than 0.5 count
worst case by using a large reference capacitor in comparison to the stray capacitance. To minimize roll-over error
from these above sources keep the reference commonmode voltage near or at analog common.
Digital Section
The digital section is shown in the block diagram,
(Figure 9), and includes the clock oscillator and scaling
circuit, a 12-bit binary counter with output latches and TTLcompatible three-state output drivers, UART handshake
logic, polarity, overrange and control logic.
Inputs driven from TTL gates should have 3-5KQ pullup resistors added for maximum noise immunity. For minimum power consu mption , all inputs should swingfromGND
(low) to V+ (high).
STATUS Output
During a conversion cycle, the STATUS output goes
high at the beginning of Signal Integrate and goes low onehalf clock period after new data from the conversion has
been stored in the output latches. See Figure B. The signal
may be used as a "data valid" flag to drive interrupts, or for
monitoring the status of the converter. (Data will not change
while STATUS is low). Status is also output on Data BitB,
when the TCB04 is in direct mode (Mode = 0, LBEN = 1,
HBEN = 0).
MODE input is pulsed high, the converter enters the UART
handshake mode and outputs the data in two bytes, then
retums to "direct" mode. When the MODE input is kept high,
the converter will output data in the handshake mode at the
end of every conversion cycle. With MODE = 0 (Direct BUS
Transfer) the DRQST input should be tied to V+. (See
Handshake Mode Section).
RUN/HOLD Input
With RUN/HOLD high or open, the circuit operates
normally as a dual slope AID as shown in Figure B. Conversion cycles operate continuously with the output latches
updated after zero crossing in the deintegrate mode. An
intemal pull-up resistor is provided to insure a high level with
an open input.
The RUN/HOLD may be used to shorten conversion
time. If the RUN/HOLD goes low at anytime after zero
crossing in the de-integrate mode, the circuit will jump to
auto-zero and eliminate that portion of time normally spent
in de-integrate.
If RUN/HOLD stays or goes low the conversion will
complete with minimum time in de-integrate. It will stay in
auto-zero for the minimum time and wait in auto-zero for a
high in the RUN/HOLD input. As shown in Figure 10, the
STATUS output will go high seven clock periods after RUN/
HOLD is changed to high, and the converter will begin the
integrate phase of the next conversion.
The RUN/HOLD input allows controlled conversion interface. The converter may be held at idle in auto-zero with
RUN/HOLD low. The conversion is started when RUN/
HOLD goes high and the new data is valid when the
STATUS output goes low (or is transferred to the UARTsee Handshake Mode). Run/HOLD may now go low, terminating de integrate and ensuring a minimum auto-zero time
before stopping to wait for the next conversion. Conversion
time can be minimized by ensuring RUN/HOLD goes low
during deintegrate, after zero crossing, and goes high after
the hold point is reached. The required activity on the RUN/
HOLD input can be provided by connecting itto the Buffered
Oscillator output. In this mode, the input value measured
determines the conversion time.
Signal Integrate Phase (SIP) Output
The SIP output is high when the TCB04 is in the Signal
integrate phase of a conversion. SIP should be used to
control multiplexer address changes. The fall;ng edge of SIP
indicates that the TCB04 has completed signal integration
for the current conversion cycle, and that the analog input
can be changed. Changing the multiplexer address on the
falling edge of SIP will guarantee maximum analog input
signal settling time before the next conversion.
MODE Input
The output mode of the converter is controlled by the
MODE Input. The converter is in its "Direct" output mode,
when the MODE pin is low or left open. The output data is
directly accessible under the control of the chip and byte
enable inputs (this input is provided with a pull-down resistor
to ensure a low level when the pin is left open). When the
2-45
IEIII
12-BIT J.1P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
Oscillator
are added to the OSCillator, as shown in Figure 11. A crystal
is then connected to the OSCl and OSCO inputs. In this
configuration, the oscillator will operate with most crystals in
the 1 to 5 MHz range.
The conversion rate is pin programmable, using the FSO
and FSl inputs. The frequency select divider will divide the
oscillator frequency by 2, 4, 8 or 16. The buff~red ADC
system clock is available at the SYSCLK output. Divider
values can be hard-wired or jurnper selected, or can be
controlled by software via two bits of a f.lP output port. The
divider truth table is shown in Figure 12.
The TC804 is designed to operate with an internal
crystal oscillator or with an external clock. The oscillator
mode is selected with the INT/EXT input. A programmable
divider permits control of the conversion rate, using hardware or software, over a range of 8 to 1.
For external oscillator operation, the INT/EXT input is
connected to DGND. The external oscillator is connected to
the OSCl input, as shown in Figure 10. The oscillator signal
should swing from DGND to V+. The ADC system clock
frequency will be the oscillator frequency divided by the
value selected by the frequency select divider.
Connecting INT/EXT to V+ enables the internal crystal
oscillator. Two on-chip capacitors and a feedback device
DE TERMINATED
STATIC IN
AT ZERO CROSSING ~ AUTD-ZERO
LHOLDSTATE
DETECTIOaNPHASEI
INT
_ _ _ _ _~~
PHASE II
INTEGRATOR OUTPUT
INTERNAL CLOCK
"'11"~~
7COUN
.
INTERNAL LATCH
•
STATUS OUTPUT
RUN/HOLD INPUT
!---------------~-::~
"NOTE: RUN/HOLD input is ignored until end of auto-zero phase.
~--------------------------------------------------------------------------.-------
Figure 7
TC804 RUN/HOLD Operation
v+
1
1
"f-
TC804
SYSCLOCK
INTI
SYSCLOCK
EXT
EXTERNAL
OSCILLATOR
INPUT
Figure 10
v+
NC
External Oscillator Connection
Figure 11
2-46
TC804 Crystal Oscillator
12-BIT ~P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
ZI~
~
INTEGRATOR OUTPUT
FOR OVERRANGE INPUT
~
, ___ ZERO INTEGRATOR
PHASE FORCES
INTEGRATOR
OUTPUTTOOV
~
_ _ _ _,.
INTEGRATOR OUTPUT '---_~--+_
FOR NORMAL INPUT rINTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
t::::l=====t==t~::::::t:
FIXED
2048 -~--+--
MIN
COUNTS
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO VIN
Figure 8
TEST
t
B
11
AFTER ZERO CROSSING, ANALOG SECTION
WILL BE IN AUTO-ZERO CONFIGURATION
Conversion Timing (RUN/HOLD Pin High)
HIGH ORDER
BYTE OUTPUTS
B
POL OR 12
~_....~_
t
B
10
B
9
LOWORDER
BYTE OUTPUTS
B
8
B
7
BB
6 5
B
4
B
3
--;1
B
2
B
1
-I
i
-----------1
i
I
I
I
I
~--L-~-L~--L-~-L~--L-~-L~--~.---------~---.~LBEN
..,,,
~----_4~--~HBEN
~--.__~_r~--.__~_r~--.__~_r~--~.-------~ti---.~OE
TC804
I
i
COMPOUT
TO
A2
ANALOG {
INT
SECTION
DEINT(.!
DEINT(-
ZI
STATUS RUNt
HOLD
OSC2
OSC1
INT/
FSO
FS1
SYSCLK
MODE DRQST
En
~-------------------------------------------------
Figure 9
Digital Section
2-47
J
·1
12-BIT IlP-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
Test Input
Integrating Capacitor
The counter and its outputs may be tested easily. When
the TEST input is connected to DGND, the intemal clock is
disabled, and the counter outputs are all forced into the high
state. When the input returns tothe 1/2 (V+- DGND) voltage
or to V+ and one clock is input, the counter outputs will all be
clocked to the low state.
The counter output latches are enabled when the TEST
input is taken to a level halfway between V+ and DGND
allowing the counter contents to be examined anytime.
The integrating capacitor CINT should be selected to
give the maximum integrator output voltage swing that will
not saturate the integrator to within 0.3V from either supply.
A ±3.5V to ±4V integrator output swing is nominal for the
TC804 with ±5V supplies and ANALOG COMMON connectedto DGND. For7-1/2 conversions persecond (61. 72Hz
internal clock frequency) nominal values CINT and Cp;z are
0.15J.lF and 0.33J.lF, respectively. These values should be
changed if different clock frequencies are used to maintain
the integrator output voltage swing. The value of CINT is
given by:
Component Value Selection
(2048 x Clock Period) (20j.lA)
The integrator output swing for full-scale should be as
large as possible. For example, with ±5V supplies and
ANALOG COMMON connected to DGND, the nominal
integrator output swing at full-scale is ±4V. Since the integrator output can go to 0.3V from either supply without
significantly effecting linearity, a 4V integrator output swing
allows 0.7V for variations in output swing due to component
value and oscillator tolerances. With ±5V supplies and a
common-mode voltage range of ±1 V required, the component values should be selected to provide ±3V integrator
output swing. Noise and rollover errors will be slightly worse
than in the ±4V case. For large common-mode voltage
ranges, the integrator output swing must be reduced further.
This will increase both noise and rollover errors. To improve
the performance, ±6V supplies may be used.
CINT=
Integrator Output Voltage Swing (VINT)
Integrating Converter Features
The output of integrating AID converters represents the
integral or average of an input voltage over a fixed period of
time. Compared with techniques in which the input is
sampled and held, the integrating converter will average the
effects of noise. A second important characteristic is that
time is used to quantise the ariswer, resulting in extremely
small non-linearity errors and no missing output codes. The
integrating converter also has very good rejection of frequencies whose periods are an integral multiple of the
measurement period. This feature can be used to advantage in reducing line frequency noise. (Figure 13.)
~
30
~
t = MEASUREMENT
PERIOD
Z
S
O
,y,
.,w20
Il!
DIGITAL
V
~
INPUT
,,
~ 10
..J
<
~
o
Z
·i
-
,
.,,"
0
0.1/t
11t
101t
INPUT FREQUENCY
Figure 12
Recommended Component Values for VFS = 409.6mV.
(See Table Following Page.)
Figure 13
2-48
Normal Mode Rejection of Dual-Slope Convertar
as a Function of Frequency.
12-BIT ~P-COMPATIBLE
MULTIPLEXED AID CONVERTER
TC804
... _--
._-----
Conversion Rate
FS1
FSo
RINT
CAZ
CINT
Rx
60 Conv/Sec
0
0
1
1
0
1
0
1
24K
24K
24K
20K
.033~
.01S~
son
son
son
on
30 Conv/Sec
15 Conv/Sec
---_.. _-
7.5 Conv/Sec
Multiply AINT by
~50
f-.
for VFS = 2.048V.
2-49
.068~
.033~
O.lS~
.068~
0.33~
O.lS~
NOTES
2-50
~~TELEDYNE
COMPONENTS
TC8S0
1S-BIT, FAST-INTEGRATING CMOS ANALOG-TO-OIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
15-bit Resolution Plus Sign Bit
Up to 40 Conversions per Second
12 Conversions per Second Guaranteed
Integrating ADC Technique
-Monotonic
- High Noise Immunity
- Auto-Zeroed Amplifiers Eliminate Offset
Trimming
Wide Dynamic Range ...................................... 96 dB
Low Input Bias Current.. ................................. 30 pA
Low Input Noise .......................................... 30 /lVp.p
•
•
•
Sensitivity ....................................................... 100 /lV
Flexible Operational Control
- Continuous or On-Demand Conversions
- Data Valid Output
Bus Compatible, 3-State Data Outputs
- 8-Bit Data Bus
- Simple /lP Interface
- Two Chip Enables
- Read ADC Result Like Memory
±5V Power Supply Operation .....••..•...•...•..... 20 mW
40-Pin Dual-in-Line or 44-Pin PLCC Packages
FUNCTIONAL DIAGRAM
BUFF
39 34 36
INTIN
24
2S
-5V
+SV
DBO
DB7
INTOUT
23
IN+ o-I~3~2--J~~~
IN- <>-ir-=37
1 --t
COMMON ~r3""0--t_ _.....J
~~
TCBSO
AID
CONTROL
SEQUENCER
BUS INTERFACE
DECODE LOGIC
17
6
3
4
CONTI UH OVRl WR RD CS CE
POL
DEMAND
1096·'
2·51
1S-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-OIGITAL CONVERTER
TC8S0
GENERAL DESCRIPTION
The TC850 is a monolithic CMOS analog-to-digital
converter (ADC) with resolution of 15 bits plus sign. It
combines a chopper-stabilized buffer and integrator with a
unique multiple-slope integration technique that increases
conversion speed. The result is 16 times improvement in
speed over previous 15-bit, monolithic integrating ADCs
(from 2.5 conversions per sec up to 40 per sec). Faster
conversion speed is especially welcome in systems with
human interface, such as digital scales.
The TCS50 incorporates an ADC and a ~P-compatible
digital interface. Only a voltage reference and a few noncritical passive components are required to form a complete 15bit plus sign ADC.
CMOS processing provides the TC850 with highimpedance differential inputs. Input bias current is typically
only 30 pA, permitting direct interface to sensors. Input
sensitivity of 100 ~V per least significant bit (LSB) eliminates
the need for precision external amplifiers. The internal
amplifiers are auto-zeroed , guaranteeing a zero digital output
with OV analog input. Zero adjustment potentiometers or
calibrations are not required.
The TCS50 outputs data on an 8-bit, 3-state bus. Digital
inputs are CMOS compatible; outputs are TTUCMOS compatible. Chip-enable and byte-select inputs combined with
an end-of-conversion output ensures easy interfacing to a
wide variety of microprocessors. Conversions can be performed continuously or on command. In continuous mode,
data is read as three consecutive bytes and manipulation of
address lines is not required.
Operating from ±5V supplies, the TC850 dissipates only
20 mW. It is packaged in 40-pin plastic or ceramic dual-inline packages (DIPs) and in a 44-pin plastic leaded chip
carrier (PLCC), surface-mount package.
ORDERING INFORMATION
Part No.
Package
44-Pin PLCC
O·Cto +70·C
TC850CPL
40-Pin Plastic DIP
O·Cto +70·C
TC850lLW
44-Pin PLCC
40-Pin CerDIP
TC850lJL
PIN CONFIGURATIONS
v+
S
REF~
R
I~ I~ I~
c EF1
CREF1
CONT/DEMAND
5
REF-
OVR/POL
6
CREF2
OVR/POL 7
cREF2
REF;
IN+
"'''
TC850
"'''
IN-
TC850CLW
TC850lLW
COMMON
C1NTB
C1NTA
CBUFA
CBUFB
BUFFER
INTIN
1NTOUT
TEST
vii
COMP
NC = NO INTERNAL CONNEcnoN
2·52
Temperature Range
TC850CLW
-25·C to +85·C
-25·C to +85·C
15-8IT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
Te850
ABSOLUTE MAXIMUM RATINGS
Lead Temperature (Soldering, 10 sec) .................. +300°C
Package Power Dissipation
CerDIP ................................................... 1W@ +85°C
Plastic DIP .......................................... 0.5W@ +lO°C
Plastic PLCC Package ........................ 0.5W@ +lO°C
Positive Supply Voltage (Vs+ to GND) ........................ +6V
Negative Supply Voltage (Vs- to GND) ....................... -9V
Analog Input voltage (IN+ or IW) ...................... Vs+ to VsVoltage Reference Input
(REFt+, REFt-, REF2+) .............................. Vs+ to VsLogic Input Voltage .................... Vs+ +0.3V to GND -0.3V
Current Into Any Pin ................................................ 10 mA
While Operating ............................................... 100 IlA
Ambient Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
Vs = ±5V, fCLK = 61.44 kHz, VFS = 3.2768V, T A = 25°C, Fig. 1 Test Circuit
Symbol
Parameter
Test Conditions
Zero-Scale Error
End Point Linearity Error
VIN = OV
-VFS::; VIN::; +VFS
-
VIN = OV, T A = 25°C
O°C::; TA::; +lO°C
-25° ::; T A::; +85°C
-
ItN
VCMR
CMRR
Differential Nonlinearity
Input Leakage Current
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Full-Scale Gain Temperature
Coefficient
eN
Is+
Input Noise
Not Exceeded 95% of Time
VOH
Output High Voltage
VOL
lop
Output Low Voltage
VIH
Input High Voltage
Input Low Voltage
Input Pull-Up Current
Output Leakage Current
Ipo
Input Pull-Down Current
losc
CIN
Oscillator Output Current
Input Capacitance
COUT
tCE
Output Capacitance
Chip-Enable Access Time
tRE
Read-Enable Access Time
tOHc
Data Hold From CS or CE
tOHR
Data Hold From RD
lop
OVR/POL Data Access Time
..
Unit
±0.5
±2
±0.5
LSB
LSB
75
-
...
_-
3
Vs+ -1.5
80
2
_ _-
... .. ...
-
..
...
.-
0.3
_
_--
3.5
10 = 500 IlA
10 = 1.6 mA
Pins 8-15, High-Impedance State
Note 3
3.5
Note 3
Pins 2, 3, 4, 6, 7; VIN = OV
Pins 1, 5; VIN = 5V
. -_._- ...._.
Pin 18, VOUT = 2.5V
-"--------_.----"Pins 1-1, 17
Pins 8-15, High-Impedance State
------- -----------CS or CE, RD = Low (Note 1)
-.--CS = High, CE = Low (Note 1)
RD = Low (Note 1)
CS = High, CE = Low (Note 1)
-
-
CS = High, CE = Low, RD = Low
(Note 1)
-
2
nA
V
dB
5
ppm/oC
-'2--
-----
IlV/oC
.
0.5
2
-------- -------- ----30
-2-- 3.5
-
r----
3.5
LSB
--
IlVp.p
mA
mA
4.9
-
V
0.15
0.4
V
IlA
V
0.1
1
2.3
-
2.1
4
-
14
140
1 ..
-_
15
230
1
-
r----'--
-
-
V
Il A
Il A
~-
Il A
pF
450
pF
ns
190
450
ns
250
ns
210
450
450
140
300
ns
--
..
-
[--
-----
LSB
pA
-
Vs +f.s
._-- [--
2-53
Max
1.1
--_.
-
-----------_.. _------------ -_..
VIN = OV
Typ
±0.25
±1
±0.1
30
-
VIN = OV, VCM = ±1V
External Ref Temperature
Coefficient = 0 ppmrC
O°C::; TA ::; +70°C
O°C::; TA ::; +lO°C
VIN = ±3.275V
Positive Supply Current
Negative Supply Current
IL
Ipu
Over Operating Temperature Range
Zero-Scale Error
Temperature Coefficient
FUll-Scale Magnitude
Symmetry Error
Is
Min
ns
...
-
15·BIT, FAST·INTEGRATING CMOS
ANALOG· TO·DIGITAL CONVERTER
TC850
ELECTRICAL CHARACTERISTICS (Cant.)
Symbol
Parameter
Test Conditions
Typ
Max
Unit
tLH
LowlHigh Byte Access Time
CS = High, CE = Low, RD = Low (Not~ 1)
Min
-
140
300
ns
Clock Setup Time
Positive or Negative Pulse Width
100
-
tWRE
RD Minimum Pulse Width
CS = High, CE = Low (Note 2)
tWRD
RD Minimum Delay Time
CS = High, CE = Low (Note 2)
twwR
WR Minimum Pulse Width
CS = High, CE = Low, Demand Mode
Clock Setup Time
Positive or Negative Pulse Width
----_._-----
---.. --
-.-_.450
150
75
------ -:-----100
--~
f------.--
ns
1---ns
- - - - - _._----
50
-
---- ..--
--_._._-- ---_.25
ns
-~--.
ns
ns
---
NOTES: 1. Demand mode, CONT/DEMAND = low. Figure 10 timing diagram. CL = 100 pF.
2. Continuous mode, CONT/DEMAND = high. Figure 12 timing diagram.
3. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TIL compatibility, external pull-up resistors to Vcc are
recommended.
PIN DESCRIPTIONS
4G-Pin DIP
Pin No.
Symbol
Description
Chip select, active high. Logically ANDed with CE to enable read and write inputs. (See
note 4.)
Chip enable, active low. (See note 5.)
2
CE
CE--;;'Jow) and in-demand mode
Write input, active low. When chip is selected(CS;';high
3
WR
(CONTIDEMAND = low), a logic Iowan WR starts a conversion. (See note 4.)
~---------=~----;R~e-a-'dC-:i-np-u-:-t,-a-c"ti'-ve-;-lo-w-.
7:
W'"h-e-n-=:C=S- ';'l1ighand CE=iow;a:-iDgiclow on RD enables the 3-state
4
RD
data outputs. (See note 5.)
Conversion control input. WhenCONTlDEMANO--;;-low, coriversioris are initiated by the WR
5
CONTIDEMAND
input. When CONTIDEMAND = high, conversions are pertormed continuously. (See note 4.)
---------6
OVR/POL
Overrange/polarity data-select input. When making conversions in the demand mode (CONTI
DEMAND = low), OVRIPOL controls the data output on DB7 when the high-order byte is
active. (See note 5.)
Low/high byte-select input. When CONT/DEMAND = low, this input controls whether low-byte
7
UR
or high-byte data is enabled on DBO through DB7. (See note 5.)
8
DB?
Most significant data bit output. When reading the A/D conversion result, the polarity,
overrange, and DB? data are output on this pin. (See text.)
Data outputs DB6-DBO. 3-state, bus compatibi9~-·---------·---------- - - - - - - . - - 9-15
DB6-DBO
CS
and
-----.------~----~---
=-------=::-::O=-----,AlDc=:-c-o-nv-'-e-r-,si,-o-n-st:-aC-tu-s-o-u.,.tp-u-,-t.
BUSY--goeStoaTogic highalthebeginning a/iii!! deintegrate16
BUSY
phase and goes low when conversion is complete. The falling edge of BUSY can be used to
generate a IJ.P interrupt.
17
Crystal oscillator connection or external oscillator input.
OSCI
18
Crystal oscillator connection.
OSC2
19
For factory testing purposes only. Do not make external connection to this pin.
TEST
20
Digital ground connection.
DGND
21
COMP
Connection for comparator auto-zero capaCitor. Bypass to Vs with 0.1 IJ.F.
22
Negative power supply connection, typically -5V.
Vs
23
Output of the integrator amplifier. Connect to CINT.
INToUT
Input to the integrator amplifier. Connec(to-summirig node-olRiNT and CINT. -----------24
INTIN
=------=;-=~=-----;O"'u-:-tP-u-:t-o"7f-,;th-e-;i-np=-u-:t"7b-u-;;ffe-r-'-.""C'-o-nn-e-c-'-tteo RINT ......- .... ----.-----.-----..-.---.---.-------.-------25
BUFFER
Connection for buffer auto-zero capacitor.S-ypasi;iQ Vs- withO.1-;tF~- -------------26
CBUFB
=-------==:::..::..----;CO=--n-n-ec-t-:-io-n-t-07b-uffcc-e-r-a-u-to---ze-r-o-capacitor.
Bypass/a Vs- withO.1-;tF:-- ----------27
CBUFA
--------"--- ----_._---------_. _._-------_..
28
Connection for integrator auto-zero capacitor. Bypass to Vs- with 0.1 IJ.F.
CINTA
29
Connection for integratorauto-zero capacitor. BYPllss to Vs- ~~ 0.1 IJ.F. __________ _
CINTB
~-----~~~~--~A-na~l-og-co-m-m-on-.~-~-
30
COMMON
31
IN-
Negative differential analog input.
15-8IT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
__________________________________________________
TC_8_5_0
PIN DESCRIPTIONS
40-Pin DIP
Pin No.
Symbol
Description
30
COMMON
c-::-_ _ _ _ _ _
-===-___--::A_na-:I:-;-og=--;co_m_m.,.o-;-n_.--;__
._____ .__.__ .____.
REF2+
33
Positive input for reference voltage VREF2. (VREF2 =_~E!'1/64L _ ___ _
34
CREF2+
Positive connection for VREF2 reference capacitor.
... _.........__..
35
CREF2Negative connection for VREF2 reference capacit~~_ ... ____.__
36
REF
Negative input for reference voltages.
37
CREF1Negative connection for VREF1 reference capacitor._____ _
--_.
38
Positive connection for VREF1 reference capacitor.
CREF1+
REF1+
39
Positive input for VREF1.
40
Vs+
Positive power supply connection, typically +5V.
NOTES: 4. This pin incorporates a pull-down resistor to DGND.
5. This pin incorporates a pull-up resistor to Vs·.
are immune to the large conversion errors that plague
successive approximation converters in high-noise environments.
A simple mathematical equation relates the input Signal,
reference voltage, and integration time:
THEORY OF OPERATION
The TC850 is a multiple-slope, integrating analog-todigital converter (ADC). The multiple-slope conversion process, combined with chopper-stabilized amplifiers, results
in a significant increase in ADC speed, while maintaining
very high resolution and accuracy.
_l__ft sl V
RC
Dual-Slope Conversion Principles
0
IN
(t) dt = _VR tF!!_
RC '
where: VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
The conventional dual-slope converter measurement
cycle (shown in Figure 2A) has two distinct phases:
(1) Input signal integration
Multiple-Slope Conversion Principles
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, complete conversion
requires the integrator output to "ramp-up" and "rampdown." Most dual-slope converters add a third phase, autozero. During auto-zero, offset voltages of the input buffer,
integrator, and comparator are nulled, thereby eliminating
the need for zero-offset adjustments.
Dual-slope converter accuracy is unrelated to the integrating resistor and capaCitor values, as long as they are
stable during a measurement cycle. By converting the
unknown analog input voltage into an easily-measured
function of time, the dual-slope converter reduces the need
for expensive, precision passive components.
Noise immunity is an inherent benefit of the integrating
conversion method. Noise spikes are integrated, or averaged, to zero during the integration period. Integrating ADCs
One limitation of the dual-slope measurement technique is conversion speed. In a typical dual-slope method,
the auto-zero and integrate times are each one-half of the
deintegrate time. For a 15-biI conversion, 214 + 214 + 2 15
(65,536) clock pulses are required for auto-zero, integrate,
and deintegrate phases, respectively. The large number of
clock cycles effectively limits the conversion rate to a.bout
2.5 conversions per second, when a typical analog CMOS
fabrication process is used.
The TC850 uses a multiple-slope conversion technique
to increase conversion speed (Figure 28). This technique
makes use of a two-slope deintegration phase and permits
15-bit resolution up to 40 conversions per second.
During the TC850's deintegration phase, the integration
capaCitor is rapidly discharged to yield a resolution of 9 bits.
At this point, some charge will remain on the capacitor. This
remaining charge is then slowly deintegrated, producing an
additional 6 bits of resolution. The result is 15 bits of
resolution achieved with only 29 + 26 (512 + 64, or 576) clock
pulses fordeintegration. A complete conversion cycle occupies only 1280 clock pulses.
2-55
IEIII
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-OIGITAL CONVERTER
TC850
+5V
-sv
IN+
··9
DB7
DB6
DB5
DB4
DB3
DB2
",r""
DBl
DBa
TC850
1 CS
2ce
3 WR
4 RD
5 CONT/DEMAND
6 OVA/POL
7 uti
17
osc1
0 61 .44
kHZ 18
OSC2
21
COMP
INCOMMON
REFf
REF2
REF-
32
~
100 ItO
SIGNAL
INTEGRATE
REFERENCE
DEINTEGRATE
/
31
30
39
33
38
CAEFl
CREFl 37
34
cAEF2
CREF2 35
BUFFER 25
24
INTIN
INToUT 23
ENDOF
CONVERSION
/
AUTO
INTEGRATOR =ZE:::R.:.:O=-jt!=--+-~"I-_ _ _ _ _ _ ov
OUTPUT
TIME_
+1.6384V
+0.0265V
1~F"
Figure 2A
Dual-Slope ADC Cycle
1~F"
120 ItO
"FAST" REFERENCE
DEINTEGRATE
(9oBIT RESOLUTION)
SIGNAL
INTEGRATE \
CINT
TEST 19
~
\
"SLOW" REFERENCE
DEINTEGRATE
(6-BIT RESOLUTION)
NC
~
AUTO
INTEGRATOR ZERO
OUTPUT
k$L1/ ~~~~lRSION
OV
TlME_
NOTES: Unless otherwise specified, all 0.1 ~F capac~ors are film dielectric.
Ceramic capacitors are not recommended.
NC = No internal connection.
• Polypropylene capac~ors .
Figure 2B
Zero-Integrator Phase
•• 100 pF Mica capacitors.
Figure 1
During the zero-integrator phase, the differential input
signal is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero-input condition. At the
same time, a feedback loop is closed around the input buffer,
integrator, and comparator. The feedback loop ensures the
integrator output is near OV before the signal-integrate
phase begins.
During this phase, a chopper-stabilization technique is
used to cancel offset errors in the input buffer, integrator,
and comparator. Error voltages are stored on the CSUFF,
CINT, and COMP capacitors. The zero-integrate phase
requires 246 clock cycles.
Standard Circuit Configuration
In order to generate "fast-slow" integration phases, two
voltage references are required. The primary reference
(VREF1) is set to one-half of the full-scale voltage (typically
VREFl
1.6384V, and VFS
3.2768V). The secondary
voltage reference (VREF2) is set to VREF1/64 (typically 25.6
mV). To maintain 15-bit linearity, a tolerance of 0.5% for
VREF2 is recommended.
=
"Fast-Slow" Reference Deintegrate Cycle
=
ANALOG SECTION DESCRIPTION
The TC850 analog section consists of an input buffer
amplifier, integrator. amplifier, comparator, and analog
switches. A simplified block diagram is shown in Figure 3.
Signal-Integrate Phase
The zero-integrator loop is opened and the internal
differential inputs are connected to IN+ and IN-. The differential input signal is integrated for a fixed time period. The
TC850 signal-integrate period is 256 clock periods, or counts.
The crystal oscillator frequency is +4 before clocking the
internal counters.
Conversion Timing
Each conversion consists of three phases: (1) Zero
Integrator, (2) Signal Integrate, and (3) Reference Integrate
(or Deintegrate). Each conversion cycle requires 1280 internal clock cycles (Figure 4).
2-56
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
CREF2
RINT
REF2+
CREF2
BUFF
CINT
INTIN
INTOUT
TO
DIGITAL
SECTION
INTEGRATOR'
COMPARATOR'
• AUTO-ZEROED
AMPLIFIERS
COMMONo-----~~--.-----------------~
IN-o-~r-~--------------------------------------~
Figure 3
INTERNAL
CLOCK
I"
JlIlJLo
1280 CLOCK CYCLES
0
oJUUL JUULo
0
oJlIlJL
0
,~----------n8----------~~~1
REFERENCE INTEGRATE
Rgure 4
Conversion Timing
The integration time period is:
tSI
TCSSO
Analog Section Simplified Schematic
I"
CONVE~Jl~~
~'"
Duringthe slowdeintegrate phase, the internal VIN+ node
is now connected to the CREF2 capacitor, and the residual
charge on the integrator capacitor is further discharged a
maximum of 64 clock pulses. At this point, the analog input
voltage has been converted with 15 bits of resolution.
If the analog input is greater than full scale, the TC850
performs up to three overrange deintegrate subphases.
Each subphase occupies a maximum of 64 clock pulses.
The overrange feature permits analog inputs up to 192 LSBs
greater than full scale to be correctly converted. This feature
permits the user to digitally null up to 192 counts of input
offset, while retaining full 15-bit resolution.
In addition to 512 counts of fast, 64 counts of slow, and
192 counts of overrange deintegrate, the reference-integrate phase uses 10 clock pulses to permit internal nodes to
settle. Therefore, the reference integrate cycle occupies 778
clock pulses.
= ..i.. x 256
fasc
Reference-Integrate Phase
During reference-integrate phase, the charge stored on
the integrator capacitor is discharged. The time required to
discharge the capacitor is proportional to the analog input
voltage.
The reference integrate phase is divided into three
subphases: (1) fast, (2) slow, and (3) overrange deintegrate.
During fast deintegrate, VIN- is intemally connected to
analog common and VIN+ is connected across the previously-charged reference capacitor (CREF1). The integrator
capacitor is rapidly discharged for a maximum of 512 internal clock pulses, yielding 9 bits of resolution.
2-57
1S-BIT, FAST-INTEGRATING CMOS
ANALOG-TO;'OIGITAL CONVERTER
TC8S0
Pin Description (Analog)
Differential Inputs (IN+ and IN-)
The analog signal to be measured is applied at the IN+
and IN- inputs. The differential input voltage must be within
the common-mode range of the converter. The input common-mode range extends from Vs+ -1.5V to Vs- +1.5V.
Within this common-mode voltage range, an 86 dB CMRR
is typical.
The integrator output also follows the common-mode
voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a
large, positive common-mode voltage with a near full-sc~le
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
available swing has been used up by the positive commonmode voltage. For applications where maximum commonmode range is critical, integrator swing can be reduced. The
integrator output can swing within O.4V of either supply
without loss of linearity.
The reference voltage inputs are fully differential, and
the reference voltage can be generated anywhere within the
power supply voltage ofthe converter. However, to minimize
roll-over error, especially at high conversion rates, keep the
reference common-mode voltage (Le., REF-) near or at the
analog common potential. All voltage reference inputs are
high impedance. Average reference input current is typically
only 30 pA.
Analog Common (COMMON)
Analog common is used as the IN- return during the
zero-integrator and deintegrate phases of each conversion.
If IN- is at a different potential than analog common, a
common-mode voltage exists in the system. This signal is
rejected by the 86 dB CMRR of the converter. However, in
most applications, IN- will be set at a fixed, known voltage
(power supply common, for instance). In this case, analog
common should be tied to the same point so that the
common-mode voltage is eliminated.
DIGITAL SECTION DESCRIPTION
Differential Reference (VREF)
The TC850 requires two reference voltage sources in
order to generate the "fast-slow" deintegrate phases. The
main voltage reference (VREF1) is applied between th.e
REF1+ and REF- pins. The secondary reference (VREF2) IS
applied between the REF2+ and REF- pins.
The TC850 digital section consists oftwo sets of conversion counters, control and sequencing logic, clock oscillator
and divider, data latches, and an 8-bit, 3-state interface bus.
A simplified schematic of the bus interface logic is shown in
Figure 5.
3-STATE
OCTAL
BUFFER
2-~~~T 1-__~.!.7____-,
8
DBO-DB7 <4---------.,,<-"---j
8
UH>---------------+---------~
RD>-----------------~~-~
CE >---------"""CIIi"l
~"
TC850
CS
POUOVR>----------------+------------------~j_--_,
WR
>-----~::§:>e>_::~~
CONTI >-______________- ;
START
CONVERSION
DEMAND
END OF
1..-_______________ CONVERSION
Figure 5
Bus Interface Simplified Schematic
2-58
TO AID
CONTROL
LOGIC
15-8IT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TCS50
Clock Oscillator
Demand Mode Operation
When CONT/DEMAND is low, the TC850 performs one
conversion each time the chip is selected and the WR input
is pulsed low. Data is valid on the falling edge of the BUSY
output and can be accessed using the interface truth table
(Table I).
The TC850 includes a crystal oscillator on-chip. All that
is required is to connect a crystal across OSCl and OSC2
pins, and to add two inexpensive capacitors (Figure 1). The
oscillator output is +4 prior to clocking the AID internal
counters. For example, a 100 kHz crystal produces a system
clock frequency of 25 kHz. Since each conversion requires
1280 clock periods, in this case the conversion rate will be
25,000/1280, or 19.5 conversions per second.
In most applications, however, an external clock is
divided down from the microprocessor clock. In this case,
the OSCl pin is used as the external oscillator input and
OSC2 is left unconnected. The external clock driver should
swing from digital ground to Vs+. The +4 function is active for
both external clock and crystal oscillator operations.
Continuous Mode Operation
When CONT/DEMAND is high, the TC850 continuously
performs conversions. Data will be valid on the falling edge
of the BUSY output, and remains valid for 443-1/2 clock
cycles.
The low/high (LiR) byte-select and overrange/polarity
(OVR/POL) inputs are disabled during continuous mode
operation. Data must be read in three consecutive bytes, as
shown in Table I.
Digital Operating Modes
NOTE: In continuous mode, the conversion result must be read within 443·
1/2 clock cycles of the BUSY output falling edge. After this time (I.e., 1/2
clock cycle before BUSY goes high) the internal counters are reset and the
data is lost.
Two modes of operation are available with the TC850,
continuous conversions and on-demand. The operating
mode is controlled by the CONT/DEMAND input. The bus
interface method is different for continuous and demand
modes of operation.
Table I. Bus Interface Truth Table
CE·CS
RD
CONT/DEMAND
UH
OVR/POL
DB7
DB6-DBO
Pins 1 and 2
Pin 4
0
0
PinS
0
0
Pin 7
0
0
PinG
0
1
Pin 9-Pin 15 (Note 1)
Data Bits 14-8
Data Bits 14 8
0
0
1
X
0
1
X
X
1
X
X
X
X
X
X
X
PinS
"1" = Input Positive
"1" = Input OVerrange
(Note 2)
Data Bit 7
Note 3
High-Impedance State
High-Impedance State
o
o
o
o
o
Data Bits 6 0
NOTES: 1. Pin numbers refer to 40-pin DIP.
2. Extended overrange operation: Although rated at 15 bits (±32,767 counts) of resolution. the TC850 provides an additional 191 counts
above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage which will be properly converted is
3. 2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190.
For example, with a full-scale voltage of 3.2768V:
VIN
3.2767V
3.2768V
3.2769V
3.2867V
Overrange Bil
Low
High
High
High
Low Byle
255,0
00010
001,0
099,0
Dala Bils 14-8
127,0
0'0
010
010
3. Continuous mode data transfer:
a. In continuous mode. data MUST be read in three sequenlial bytes after the BUSY oulput goes low:
(1) The first byte read will be the high-order byte, with DB7 = polarity.
(2) The second byte read will contain the low-order byte.
(3) The third byte read will again be the high-order byte, but with DB7 = overrange.
b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY.
_
c. The RD input must go high after each byte is read, so that the internal byte counter will be incremented. However. the CS and CE
inputs can remain enabled through the entire data transfer sequence.
2-59
1S-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TCSSO
Pin Description (Digital)
pulsed low. The conversion is complete and data can be
read after the falling edge of the BUSY output. In demand
mode, data can be read in any sequence, and remains valid
until WR is again pulsed low.
Chip Select and Chip Enable (CS and CE)
The CS and CE inputs permit easy interfacing to a
variety of digital bus systems. CE is active low while CS is
active high. These inputs are logically ANDed internally and
are used to enable the RD and WR inputs.
Busy Output (BUSY)
The BUSY output is used to convey an end-of-conversion to external logic. BUSY goes high at the beginning of
the deintegrate phase and goes low at the end of the
conversion cycle. Data is valid on the falling edge of BUSY.
The output-high period is fixed at 836 clock periods, regardless of the analog input value. BUSY is active during
continuous and demand mode operation.
This output can also be used to generate an end-o/conversion interrupt in ~P-based systems. Noninterruptdriven systems can poll BUSY to determine when data is
valid.
Write Enable Input (WR)
The write input is used to initiate a conversion when the
TC850 is in demand mode. CS and CE must be active forthe
WR input to be recognized. The status of the data bus is
meaningless during the WR pulse, because no data is
actually written into the TC850.
Read Enable Input (RD)
_
The read input, combined with CS and CE, enables the
3-state data bus outputs. Also, in continuous mode, the
rising edge of the RD input activates an internal byte counter
to sequentially read the three data bytes.
ANALOG SECTION APPLICATIONS
Component Selection
Low/High Byte Select (L/H)
The uH input determines whether the low (least significant) byte or high (most Significant) byte of data is placed on
the 3-state data bus. This input is meaningful only when the
TC850 is in the demand mode. In the continuous mode, data
must be read in three predetermined bytes, so the uH input
is ignored.
Reference Voltage
The typical value for reference voltage VREF1 is 1.6384V.
This value yields a full-scale voltage of 3.2768V and resolution of 100 ~V per step. The VREF2 value is derived by
dividing VREF1 by 64. Thus, typical VREF2 value is 1.6384VI
64, or 25.6 mY. The VREF2 value should be adjusted within
±1 % to maintain 15-bit accuracy for the total conversion
process; i.e.,
Overrange/Polarity Bit Select (OVR/POL)
The TC850 provides 15 bits of resolution, plus polarity
and overrange bits. Thus, 17 bits of information must be
transferred on an 8-bit data bus. To accomplish this, the
overrange and polarity bits are multiplexed onto data bit DB7
of the most significant byte. When OVR/POL is high, DB7 of
the high byte contains the overrange status (high = analog
input overrange, low = input within full scale). When OVRI
POL is low, DB7 is high for positive analog input polarity and
low for negative polarity. The OVR/POL input ~ meaningful
only when CS, CE, and RD are active, and UH is low (I.e.,
the most significant byte is selected). OVR/POL is ignored
when the TC850 is in continuous mode.
VREF1
VREF2 = - ± 101
10.
64
The reference voltage is not limited to exactly 1.6384V,
however, because the TC850 performs a ratiometric conversion. Therefore, the conversion result will be:
Digital counts =
--y~-. 16384.
VREF1
The full-scale voltage can range from 3.2V to 3.5V. Fullscale voltages of less than 3.2V will result in increased noise
in the least significant bits, while a full-scale above 3.5V will
exceed the input common-mode range.
Continuous/Demand Mode Input (CONT/DEMAND)
This input controls the TC850 operating mode. When
CONT/DEMAND is high, the TC8S0 performs conversions
continuously. In continuous mode, data must be read in the
prescribed sequence shown in Table I. Also, all three data
bytes must be read within 443-1/2 internal clock cycles after
the BUSY output goes low. After 443-1/2 clock cycles data
will be lost.
When CONT/DEMAND is low, the TC850 begins a
conversion each time CS and CE are active and WR is
Integration Resistor
The TC850 buffer supplies 25 ~ of integrator charging
current with minimal linearity error. RINT is easily calculated:
R
_ YFULL SCALE
INT2S~
For a full-scale voltage of 3.2768V, values of RINT
between 120 kn and 150 kn are acceptable.
2-60
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
Integration Capacitor
The integration capacitor should be selected to produce
an integrator swing of =4V at full scale. The capacitor value
is easily calculated:
C
=
VFS. 4 • 256
RINT
4V • fCLOCK
where fCLOCK is the crystal or external oscillator frequency
and VFS is the maximum input voltage.
The integration capacitor should be selected for low
dielectric absorption to prevent roll-over errors. A polypropylene, polyester or polycarbonate dielectric capacitor is
recommended.
Reference Capacitors
The reference capacitors require a low leakage dielectric, such as polypropylene, polyester or polycarbonate. A
value of 1 I1F is recommended for operation over the temperature range. If high-temperature operation is not required, the CREF values can be reduced.
equal to one or more line frequency cycles. The desired
clock frequency is selected as follows:
fCLOCK = fNOISE
X
4 x 256,
where fNOISE is the noise frequency to be rejected, 4 represents the clock divider, and 256 is the number of integrate
cycles.
For example, 60 Hz nOise will be rejected with a clock
frequency of 61.44 kHz, giving a conversion rate of 12
conversions/sec. Integer submultiples of 61.44 kHz (such
as 30.72 kHz, etc.) will also reject 60 Hz noise. For 50 Hz
noise rejection, a 51.2 kHz frequency is recommended.
If noise rejection is not important, other clock frequencies can be used. The TC850 will typically operate at
conversion rates ranging from 3 to 40 conversions/sec,
corresponding to OSCillator frequencies from 15.36 kHz to
204.8 kHz.
SYSTEM
CLOCK
Auto-Zero Capacitors
Five capacitors are required to auto-zero the input
buffer, integrator amplifier, and comparator. Recommended
capacitors are 0.1 I1F film dielectric (such as polyester or
polypropylene). Ceramic capacitors are not recommended.
~ 100pF
~ 100pF
DIGITAL SECTION APPLICATION
Oscillator
Figure 6
The TC850 may operate with a crystal oscillator. The
crystal selected should be designed for a Pierce oscillator,
such as an AT-cut quartz crystal. The crystal oscillator
schematic is shown in Figure 6.
Since low frequency crystals are very large and ceramic
resonators are too lossy, the TC850 clock should be derived
from an external source, such as a microprocessor clock.
The clock should be input on the OSCI pin and no connection should be made to the OSC2 pin. The external clock
should swing between DGND and Vs+.
Since oscillator frequency is +4 internally and each
conversion requires 1280 internal clock cycles, the conversion time will be:
Crystal Oscillator Schematic
Data Bus Interfacing
The TC850 provides an easy and flexible digital interface. A 3-state data bus and six control inputs permit the
TC850 to be treated as a memory device, in most applications. The conversion result can be accessed over an 8-bit
bus or via a I1P 110 port.
A typical I1P bus interface for the TC850 is shown in
Figure 7. In this example, the TC850 operates in the demand
mode, and conversion begins when a write operation is
performed to any decoded address space. The BUSY
output interrupts the I1P at the end-of-conversion.
The ND conversion result is read as three memory
bytes. The two LSBs of the address bus select high/low byte
and overrange/polarity bit data, while high-order address
lines enable the CE input.
Figure 8 shows a typical interface to a I1P I/O port or
single-chip I1C. The TC850 operates in the continuous
mode, and can either interrupt the I1C/I1P or be polled with
an input pin.
Conversion time = fCLOCK x 4 x 1280.
An important advantage of the integrating ADC is the
ability to reject periodic noise. This feature is most often
used to reject line frequency (50 Hz or 60 Hz) noise. Noise
rejection is accomplished by selecting the integration period
2-61
15-8IT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TCS50
Since the PAD-PA7 inputs are dedicated to reading
ND data, the ND CS/CE inputs can be enabled continuDBO
OBI
DB2
DB3
DB4
DBS
DB6
DB7
CS
~"
TCS50
'ADDRES~[
DECODE
lIR
OVR/POL
iii'i
WR
BUSY
CS t-+SV
CONTI
DEMAND
DBO
OBI
DB2
DB3
DB4
DBS
DB6
DB7
A2
ously. In continuous mode, data must be read in3 bytes, as
shown in Table I. The required RD pulses are provided by a
I!C/I!P output pin.
The circuit of Figure 8 can also operate in the demand
mode, with the start-up conversion strobe generated by a
I!C/I!P output pin. In this case, the UH and CaNT/DEMAND
inputs can be controlled by I/O pins and the RD input
connected to digital ground.
liP
A1S
AD
AI
RD
WR
INTERRUPT
Demand Mode Interface Timing
When CaNT/DEMAND input is low, the TC850 performs a conversion each time CE and CS are active and WR
is strobed low.
The demand mode conversion timing is shown in Figure
9. BUSY goes low and data is valid 1155 clock pulses after
WR goes low. After BUSY goes low, 125 additional clock
cycles are required before the next conversion cycle will
begin.
Once conversion is started, WR is ignored for 1100
internal clock cycles. After 1100 clock cycles, another WR
pulse is recognized and initiates a new conversion when the
present conversion is complete. A negative edge on WR is
required to begin conversion. If WR is held low, conversions
will not occur continuously.
The ND conversion data is valid on the falling edge of
BUSY, and remains valid until one-half internal clock cycle
before BUSY goes high on the succeeding conversion.
BUSY can be monitored with an I/O pin to determine end of
conversion, or to generate a I!P interrupt.
In demand mode, the three data bytes can be read in
any desired order. The TC850 is simply regarded as three
bytes of memory and accessed accordingly. The bus output
timing is shown in Figure 10.
.-&
ADDRESS
xOO
xOI
x 10
Figure 7
~"
TCSSO
DATA BUS
HIGH BYTE AND POLARITY
LOW BYTE
HIGH BYTE AND OVERRANGE
Interface to Typlcall1P Data Bus
DBO
OBI
DB2
DB3
DB4
DBS
DB6
DB7
BUSY
RD
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
.!!
COR P
II110
PO T
INTERRUPT
PBO
Continuous Mode Interface Timing
CONT/DEMAND t:r-+5V
CS
CE WR
When the CaNT/DEMAND input is high, the TC850
performs conversions continuously. Data will be valid on the
falling edge of BUSY, and all three bytes must be read within
443-1/2 intemal clock cycles of BUSY going low. The timing
diagram is shown in Figure 11.
In continuous mode, OVR/POL and UH byte-select
inputs are ignored. The TC850 automatically cycles through
three data bytes, as shown in Table I. Bus output timing in
the continuous mode is shown in Figure 12.
~ N~
Figure S Interface to Typicall1P 110 Port or Single-Chip I1C
2-62
1S-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-OIGITAL CONVERTER
TC8S0
INTERNAL
CLOCK
CS·CE
-11flfL... :.JU1IL........ -11flfL
~, I_
-I
'''90COOK C'CLE'
~\
,
\
I
~NEXTCONVERT
: WRPULSES
ARE IGNORED
,\...I
'\
COMMAND WILL
BE RECOGNIZED
:
319 CLOCK
, - CYCLES
-------------------------------t, ,'
,
PREVIOUS CONVERSION
DATA VALID
DATA MEANINGLESS
Figure 9
CS·CE
r
- toHC
tCE
--J
iI
- -
-
.-
'RE
tDHR
I
I
DB7
HI-Z
..
"..,
I
HI-Z
NEW CONVERSION DATA VALID
Conversion Timing, Demand Mode
I'
DBG-DB6
CONVERSION
CAN BEGIN
----'J
BUSY
DBG-DB7
~NEXT
:
,
, _ 836 CLOCK CYCLES_'
,
:--125 CLOCK_ _ '
.'
\
CYCLES:
I
'\...I
\
\
\
DATA BITS
OT06
DATA BITS 8 TO 14
J
"1" = INPUT
OVERRANGE
OVRlPOL
"1" = POSITIVE
POLARITY
HIGH IMPEDANCE
HIGH IMPEDANCE
I
1
DON'T CARE
tLH
---------------~\~------------D-O-N-'-T-C-A-R-E------------
UH
~----------------------NOTE: CONT/DEMAND = LOW
• AD (as well as CS and GE) can go HIGH after each byte is read (i.e., in a ~p bus interface)
or remain LOW during the entire DATA-READ sequence (Le"
~p
I/O port interface),
Figure lOBus Output Timing, Demand Mode
2-63
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
INTERNAL
CLOCK
BUSY
JlJUL .
. . . ..JlflJl: . . . .:J1J1JL. .
..J. .
_1_
t-----
I
II
,..------"""\
DATA MEANINGLESS
DBO-DB7
Figure 11
CONTI
DATAVAUD
112 CLOCK
CYCLE
DATA
MEANINGLESS
Conversion Timing, Continuous Mode
-----r--f(l
DEMAND - - - '
\~________________________________________________________
BUSY
-----'n~/
RD
DBO-DB7
DATA BITS 0-7
HI-Z
NOTES: CS = HIGH;
DATA BITS 8-14
OVERRANGE
CE = LOW
Figure 12
Bus Output Timing, Continuous Mode
2-64
HIGH-IMPEDANCE
STATE
"~TELEDYNE
COMPONENTS
TC71 09
TC7109A.
12-BIT /lP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
FEATURES
GENERAL DESCRIPTION
•
The TC7l09A is a l2-bit plus sign, CMOS low-power
analog-to-digital converter (ADC). Only eight passive components and a crystal are required to form a complete dualslope integrating ADC.
The improved VOH source current TC7l09A has features that make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applications.
These features include typical input bias current of 1 pA, drift
of less than 1 IlV/oC, input noise typically 15 IlVp-p, and
auto-zero. True dffferential input and reference allow measurement of bridge-type transducers such as load cells,
strain gauges, and temperature transducers.
The TC7109A provides a versatile digital interface. In
the direct mode, chip select and high/low byte enables
control parallel bus interface. In the handshake mode, the
TC71 09A will operate with industry-standard UARTs in controlling serial data transmission - ideal for remote data
logging. Control and monitoring of conversion timing is provided by the RUN/HOLD input and STATUS output.
For applications requiring more resolution, see the
TC500, l5-bit plus sign ADC data sheet.
The TC71 09A has improved overrange recovery performance and higher output drive capability than the original
TC7109. All new (or existing) designs should specify the
TC7109A wherever possible.
Zero-Integrator Cycle for Fast Recovery From
Input Overloads
Eliminates Cross Talk in Multiplexed Systems
12-Bit Plus Sign Integrating AID Converter With
Overrange Indication
Sign Magnitude Coding Format
True Differential Signal Input and Differential
Reference Input
Low NOise ............................................. 15IlVp_p Typ
High Normal Mode Noise and Line Frequency
Rejection
Input Current .............................................. 1 pA Typ
No Zero Adjustment
TTL-Compatible, Byte-Organized Tri-State
Outputs
UART Handshake Mode for Simple Serial Data
Transmission
Power DISSipation ••••••••••••••• Less Than 20 mW Typ
Internal Voltage Reference
•
•
•
•
•
•
•
•
•
•
•
•
FUNCTIONAL DIAGRAM
REF
CAP+
37
··i---- ••
·•••
··•
·•
INPUT 35: INT
HI
•
•
COIIMON
INPUT
LO
AZ
0'33~1_-+_...:.;,-+
•
341 INT
1
I
-
ANALJg
SECTION
{COMPOUT
I~~
DE (~
1
--------L..r----r-'
Uv
l--------i9 - is--------------- 40-------------------'2 -----'26 --:12 -;. --;. -;; --21 ----27' ----, -~~~
v-
y+
STATUS
~ ~C~ ~r.: ~~ MODE
OUT
1076-1
2-65
SEND
GND
12-BIT IlP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
ORDERING INFORMATION
Part No.
Package
TC7109ACPL
TC7109ACKW
40-Pin Plastic DIP
44-Pin Flat
TC7109ACLW
TC7109AIJL
TC7109AMJL
Temperature
Range
Package
Part No.
O·Cto +70·C
O·C to +70·C
TC7109CPL
TC7109CKW
40-Pin Plastic DIP
44-Pin Flat
44-Pin PLCC
40-Pin CerDIP
O·C to +70·C
-25·C to +85·C
TC7109CLW
TC71091JL
44-Pin PLCC
40-Pin CerDIP
O·Cto +70·C
-25·C to +85·C
40-Pin CerDIP
-55·C to +125·C
TC7109MJL
40-Pin CerDIP
-55·C to + 125°C
PIN CONFIGURATIONS
~
...
TC7109ACKW
TC7109CKW
(FLAT PACKAGE)
;;; Iii
w
B7
I-
B6
I~
Ii I~I~
u
Z
w
0
0
i!!O
I-
..J ""1-
:s
u
u
u
::e
B5
I
B4
i!!O
0
z
rr
B3
·0
"
B2
Bl
TEST
LBEN
HBEN
CEILOAD
- ._ _ _- - r -
~
...
TC7109ACLW
TC7109CLW
(PLCC)
NO
Temperature
Range
=NO INTERNAL CONNECTION
21
;;; § I~ I~ I~
lu
2-66
::>
0
VI
0
w .... ::>
VI ::>0
IOU
VI
0
oVI
+
i!!O
O·Cto +70·C
O·C to +70·C
12-BIT /lP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
------------------------------------------------------------------------------------Static-sensitive device. Unused devices must be stored in conductive
material. Protect dsvices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (GND to v+) ........................ +S.2V
Negative Supply voltage (GND to V-) .......................... -9V
Analog Input Voltage (Low to High) (Note 1) ......... V+ to VReference Input Voltage (Low to High (Note 1) ..... V+ to VDigital Input Voltage (Pins 2-27) (Note 2) ........ GND -o.3V
Power Dissipation (Note 3)
Ceramic Package .................................... 1W at +85°C
Plastic Package ............................... 500 mWat +70°C
Operating Temperature Range
Plastic Package (C) ................................ 0°Cto +70°C
Ceramic Package (I) .......................... -25°C to +85°C
(M) ...................... -55°C to +125°C
Storage Temperature Range ................... -65°C to +150°C
Lead Temperature (Soldering. SO sec) .................. +300°C
NOTES: 1. Input voltages may exceed supply voltages if input current is
limited to :t100 !IA.
2. Connecting any digital inputs or outputs to voltages greater
than V' or less than GND may cause destructive device latchup. Therefore. it is recommended that inputs from sources
other than the same power supply should not be applied to
the TC7109A before its power supply is established. In
multiple supply systems. the supply to the device should be
ELECTRICAL CHARACTERISTICS: All parameters with V+ = +5V. V- = -5V. GND = OV. TA = +25°C.
unless otherwise indicated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Analog
Overload Recovery Time
(TC7109A)
Zero Input Reading
Ratiometric Reading
NL
CMRR
VCMA
eN
liN
TCzs
TCFS
I'
Is
Nonlinearity (Max Deviation
From Best Straight Line Fit)
Roll-Over Error (Dffference in
Reading for Equal Positive and
Negative Inputs Near (Full Scale)
Input Common-Mode
Rejection Ratio
Common-Mode Voltage
Range
Noise (P-P Value Nat
Exceeded 95% at Time)
Leakage Current at Input
Zero Reading Drfft
Scale-Factor
Temperature Coefficient
Supply Current
(V+taGND)
Supply Current (V+ to V-)
0
VIN =OV
Full Scale =409.6 mV
VIN= VREF
VREF m 204.8 mV
Full Scale = 409.6 mV to
2.048V Over Full Operating
Temperature Range
Full Scale = 409.6 mV to
2.048V Over Full Operating
Temperature Range
VCM :tW. VIN =OV
Full Scale = 409.6 mV
Input High. Input Low.
and Common Pins
VIN K OV
Full Scale = 409.6 mV
VIN. All Packages: +25°C
C Device: O°C 'II TA 'II +70·C
I Device: -25°C'll TA 'II +85°C
M Device: -55°C 'II TA 'II + 125°C
VIN= OV
VIN = 408.9 mV =>7770a
Reading. Ext Ref =0 ppmJOC
VIN = OV. Crystal Oscillator
3.58 MHz Test Circuit
Pins 2-21. 25. 26. 27. 29 Open
2-67
Measurement
Cycle
f-:::'-:--_
.......
=-=- Octal Reading
+OOOOa
1
-oOooa
±OOOOa
37778
40008
-1
37778
4000a
±0.2
+1
Count
-1
:to.02
+1
Count
50
V-+l.5
Octal Reading
J!.VN
V'-1
15
V
J!.V
1
20
100
2
0.2
1
10
100
250
5
1
5
pA
pA
pA
nA
J!.VJOC
J!.VJOC
700
1500
J!.A
700
1500
J!.A
_._-_.
2
12-81T JiP-COMPATI8LE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09'
TC7109A
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VREF
Ref Out Voltage
Referenced to V+, 25 kQ
Between V+ and Ref Out
-2.4
-2.8
-3.2
V
TCREF
Ref Out Temperature
Coefficient
25 kG Between V+ and Ref Out
O·C'lI TA'lI +70·C
Output High Voltage
TC7109: loup 100 jU\
TC7109A: lOUT = 700 jU\
Pins2-16,18,19,20
Output low Voltage
lOUT = 1.6 mA
Pins 3-16 High Impedance
80
ppml"C,
4.3
V
Digital
VOH
--
VOL
Output leakage Current
Control 110
Pull-Up Current
---
Control 110 loading
Pins 18, 19, 20 VOUT = V+-3V
Mode Input at GND
HBEN, Pin 19; lBEN, Pin 18
VIH
Input High Voltage
Pins 18-21, 26, 27
Referenced to GND
V1L
Input low Voltage
Pins 18-21, 26, 27
Referenced to GND
Input Pull-Up Current
Pins 26, 27; VOUT = V+-3V
Pins 17, 24; VOUT = V+-3V
--
3.5
0.2
0.4
±0.01
5
±1
50
Input Pull-Down Current
Pin 21; VOUT - GND = +3V
VOUT= 2.5V
5
25
1
------
1
.. -...•- ... -.
_._---- f---- 1------1.5
- - I - - - 1---"-.~
Oscillator Output Current, Low
--_.-----
tw
Buffered Oscillator Output
Current, High
Buffered Oscillator Output
Current, low
VOUT= 2.5V
2
VOUT= 2.5V
5
VOUT= 2.5V
Mode Input Pulse Width
60
pF
V
1
Oscillator Output Current, High
jU\
/LA
2.5
--_.
--
V
V
/LA
/LA
/LA
mA
- .. ------..
~---
mA
r--:------mA
ns
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, anti-static tubes, or other conducting material. Use proper anti-static handling
procedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent
damage.
2-68
.. -
mA
.---~--
12-BIT f.1P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
PIN DESCRIPTION
40·Pin DIP
Pin Number
Name
1
GND
2
STATUS
Description
Digital ground, OV, ground return for all digital logic.
Output high during integrate and deintegrate until data is latched. Output low when analog
section is in auto-zero or zero-integrator configuration.
3
POL
Polarity -
4
OR
Overrange -
5
B'2
Bit 12 (Most Significant Bit)
6
B"
B,o
Bit 11
7
B
B9
Bit 9
9
B8
BitB
10
B7
Bit 7
11
B6
Bit 6
B5
Bit 5
13
B4
Bit 4
14
B3
Bit 3
15
Bit2
16
B2
B,
17
TEST
18
LBEN
19
HBEN
20
CE/LOAD
21
MODE
22
OSCIN
23
OSCOUT
OSCSEL
25
BUFOSCOUT
26
RUN/HOLD
27
SEND
High if overranged.
Bit 10
12
24
High for positive input.
All Three-State Data Bits
Bit 1 (Least Significant Bit)
Input High - Normal operation. Input Low - Forces all bit outputs high.
Note: This input is used for test purposes only.
Low-Byte Enable - With MODE (Pin 21) low":',a::-:n::-::d;;C"'E""I;;=LO~Ai
LBEN
~~
B1-88
TC7109A
BOOS, 8080, 8OS5
8
CEILOAD
* MEMR or lOR for 8OS0/8228 system.
GND
+5V
Figure 17
TC7109A Direct Interface to 808OI8OS5
2-82
12-BIT JlP-COMPATIBLE
ANALOG-TO-OIGITAL CONVERTERS
TC71 09
TC7109A
GND
+5V
MODE RUNIHOLD
B9-812
POL,OR
"'"
MC6800
OR
MCS650X
TC7109A
HBEN
LBEN 140---1
ADDRESS DATA CONTROL
BUS
BUS
BUS
Figure 18
TC7109A Direct Interface to MC6800 Bus
D7-DO
B9-812
POL,OR
ANALOG
c=> "'"
TC7109A
PA7-PAO
CEILOAD
PC4
SEND
PC5
AO-A1
CS
87C48
8008,8080,
8085, 8048, ETC.
8255
(MODE 1)
RUNIHOLD
MODE
Figure 19
PC7
PC3
INTR
TC7109A Handshake Interface to MCS-48, -80, -85 Microcomputers
2·83
12-BIT f..lP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
Handshake Mode
The handshake mode provides an interface to a wide
variety of external devices. The byte enables may be used
as byte identification flags or as load enables and external
latches may be clocked by the rising edge of CEILOAD. A
handshake interface to Intel microprocessors using an 8255
PPI is shown in Figure 19. The handshake operation with
the 8255 is controlled by inverting its Input Buffer Full (IBF)
flag to drive the SEND input to the TC71 09A, and using the
CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port
used. If the 8255 IBF flag is low and the TC7109A is in
handshake mode, the next word will be strobed into the
port. The strobe will cause IBF to go high (SEND goes low),
which will keep the enabled byte outputs active. The PPI
will generate an interrupt which, when executed, will result
in the data being read. The IBF will be reset low when the
byte is read, causing the TC7109A to sequence into the
next byte. The MODE input to the TC71 09A is connected to
the control line on the PPI.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left high, or tied high
separately. (The data access must take less time than a
conversion.) The output sequence can be obtained on
demand if this output is made to go from low to high. and
the interrupt may be used to reset the MODE bit.
Conversions may be obtained on command under software control by driving the RUN/HOLD inputlo the TC71 09A
by a bit of the 8255. Another peripheral device may be
serviced by the unused port of the 8255. The 8155 may be
used in a similar manner. The MCS650X microprocessors
are shown in Figure 20 with MODE and RUN/HOLD tied
high to save port outputs.
The handshake mode is particularly useful for directly
interfacing to industry-standard UARTs (such as Western
Digital TR1602), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure 1. In this
Circuit, any word received by the UART causes the UART
DR (Data Ready) output to go high. The MODE input to the
TC7109A goes high, triggering the TC7109A into handshake mode. The high-order byte is output to the UART
and when the UART has transferred the data to the Transmitter register, TBRE (SEND) goes high again, LBEN will
go high, driving the UART DRR (Data Ready Reset) which
will signal the end of the transfer of data from the TC71 09A
to the UART.
An extension of the typical connection to several
TC7109A's with one UART is shown in Figure 21. In this
circuit, the word received by the UART (available at the
RBR outputs when DR is high) is used to select which
converter will handshake with the UART. Up to eight
TC7109A's may interface with one UART, with no external
components. Up to 256 converters may be accessed on
one serial line with additional components.
+5V - - - 4 - - - - ,
MODE
CRA 1--100-01 1
~f'
MC6820
TC7l09A
MC6800
OR
MCS650X
PAO-PA7
CEiLOAD I----::-I~
SEND
ADDRESS
BUS
Figure 20
DATA CONTROL
BUS
BUS
TC7109A Handshake Interface to MCS-6800, MCS650X Microprocessors
2-84
12-BIT IlP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
B
TBRL ORR
TBRE
W
\
ANALOG
C)
RBRI-RBR8
r------
SERIAL INPUT
I--
SFD
If G~D
~I
T
I
SERIAL OUTPUT
6402 CMOS UART
~
TBR1-TBR8
/').
T
I
1
8-BIT DATA BUS
I I
MODE CEI SEND
LOAD
B9-BI2
POL,OR
~~
I I
0
Bl-B8
TC7109A
-
=J
-
8
ANALOG
c=>
I I I
0
MODE CEI SEND
LOAD
B9-BI2 fPOL,OR
~~
Bl-B8
TC7109A
RUNIHOLD r-+5V
\
MODE CEI SEND
LOAD
B9-BI2 fPOL,OR
P c=>
ANALOG
~~
8
r--
BI-88
TC7109A
RUNIHOLD -+5V
tJ
-
8
RUNIHOLD -+5V
HBEN
LBEN
HBEN
LBEN
HBEN
LBEN
I
I
I
I
I
I
Figure 21
0
Handshake Interface for Multiplexed Converters
Integrating Converter Features
The output of integrating ADCs represents the integral,
or average, of an input voltage over a fixed period of time.
Compared with techniques in which the input is sampled and
held, the integrating converter averages the effects of noise.
A second important characteristic is that time is used to
quantize the answer, resulting in extremely small, nonlinearity
errors and no missing output codes. The integrating converter also has very good rejection of frequencies whose
periods are an integral multiple of the measurement period.
This feature can be used to advantage in reducing line
frequency noise (Figure 22).
~
30
IA~
t =MEASUREMENT
PERIOD
0..
IY
Z
o
ti
..,
w
w
20
V
,,'f
a:
w
c
o
::;;
/
/
~
a:
!i
/
10
0
0.11t
i,....-
...... 1-'
lit
INPUT FREQUENCY
10ft
Figure 22 Normal Mode Rejection of Dual-Slope Converter as a
Function of Frequency
2-85
12-BIT IlP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC71 09
TC7109A
BONDING DIAGRAM
LO
.l~--(:OMIMON
-INT
.J---AZ
B.
83
. , , __-REF OUT
82
B1
JJ11J:lJ 41,1),
CE/LOAD
j 4 - -_ _ _ _...c:.= 0.132"
2-86
OSC OUT
OUT HOLD
~
C')
c::i
~"'TELEDYNE
COMPONENTS
TC8702
TC8704
TC8705
BINARY OUTPUT ANALOG-TO-DIGITAL CONVERTERS
FEATURES
•
•
•
•
•
High Accuracy - Up to 12-Bit Resolution With
<±112 LSB Error
Monotonic Performance - No Missing Codes
Monolithic CMOS Construction Gives Low Power
Dissipation .............................................. 20 mW Typ
Contains All Required Active Elements - Needs
Only Passive Support Components, Reference
Voltage, and Dual-Power Supply
High Stability Over Full Temperature Range
- Gain Temperature Coefficient ... <25 ppml°C Typ
- Zero Drift ..........•............................• <30 ,.NloC Typ
- Differential Nonlinearity Drift ..... <25 ppmfOC Typ
•
•
•
•
•
Latched Parallel Binary Outputs
Three-State, Bus Compatible Outputs
(TC8704 and TC8705)
LPTTL, 74LS, CMOS Compatible Outputs and
Control Inputs
Strobed or Free-Running Conversion
Infinite Input Range - Any Positive Voltage Can
Be Applied Via a Scaling Resistor
TEST CIRCUIT
~'"
O.lIlF
.r1
TC8702fTC8704ITC8705
+5V
:;
INITIATE
CONVERSION
19
BINARY
OUTPUTS
22
L-+~_~~~=-~~...:=========:f2==3'--ODATA
VALID
13
SOkQ
-5V
V REF
NOTES: "Any VREF greaterihan -tV can be used:
VREF
RREF= - 20 I1A
For example, with VREF = -5V, RREF = 250 k.Q
--No connection for TC8702.
1097·1 (4344)
4344 ILL F01
2-87
BINARY OUTPUT
ANALOG-TO-OIGITAL CONVERTERS
TC8702
TC8704
TC8705
GENERAL DESCRIPTION
PIN CONFIGURATION
The TC8702fTC8704ITC8705 are 10- and 12-bit monolithic CMOS analog-to-digital converters (ADCs). Fully selfcontained in a single 24-pin dual-in-line package, each
converter requires only passive support components, reference and power supplies.
Conversion is performed by an incremental charge
balancing technique which has inherently high accuracy,
linearity and noise immunity. An amplifier integrates the sum
of the unknown analog current and pulses of a reference
current, and the number of pulses (charge increments)
needed to maintain the amplifier summing junction near·
zero are counted. At the end of conversion, the total count
is latched into the digital outputs as a 10- or 12-bit binary
word.
The TC8704/8705 features a three-state output bus
controlled by an output enable input. The output enable
control switches to a high impedance or off-state when held
high. The off-state allows bus-organized output connections. On the TC8702, outputs are always active.
BIT 11
(MSB)
BIT 10
BIT9
(TCS704 MSB)
1
2
BITS
BIT7 5
BITS
DIGITS
OUT
BIT3
NOTE: Do not make oonnections to pins 1 or 2 on TC8704.
These pins are internally connected .
• No oonnection for TC8702
4344 Ill.. F02
ORDERING INFORMATION
Part No.
Previous
Part No.
TC8702EHG
TC8702MJG
TSC8702CN
TSC8702CN
Resolution
Conversion
Time (ms)
Package
20
24-Pin CerDIP
20
5
24-Pin CerDIP
24-Pin Plastic DIP
TC8704CPG
TSC8704CJ
l2-Bit
l2-Bit
10-Bit
TC8704EJG
TC8704MJG
TSC8704CL
10-Bit
5
10-Bit
TC8705CPG
TSC8704BL
TSC8705CJ
5
20
24-Pin CerDIP
24-Pin Plastic DIP
TC8705EHG
TC8705MHG
TSC8705CL
TSC8705BL
20
20
24-Pin CerDIP
24-Pin CerDIP
l2-Bit
l2-Bit
l2-Bit
2-88
24-Pin CarDIP
Temperature
Range
-40°C to +85°C
-55°C to + 125°C
O°Cto +70°C
-40·C to +85°C
-55°C to + 125°C
O°C to +70°C
-40°C to +85°C
-55°C to + 125°C
BINARY OUTPUT
ANALOG-TO-OIGITAL CONVERTERS
TC8702
TC8704
TC8705
ABSOLUTE MAXIMUM RATINGS
VDD-VSS ................................................................. +18V
liN ..........................................................................±10 mA
IREF .......................................................................±10 mA
Digital Input Voltage ........................... -0.3V to VDD +0.3V
Operating VDD and Vss Range ..................... +3.SV to +7V
Storage Temperature Range .................. -65°G to +1S0oG
Operating Temperature Range
GPG ....................................................... ooG to +70oG
EJG .................................................... -40oG to +85°C
MJG, MHG ....................................... -5SoG to +125°G
Package Dissipation ............................................. SOO mW
Lead Temperature (Soldering, 10 sec) .................. +300oG
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS: VDD = +SV, Vss =-SV, VGND = 0, VREF = -6.4V, RBIAS = 100 kn, test
circuit shown, unless otherwise specified. T A = +2soG unless full temperature range is specified (-5soG to + 12SOG for
MJG and MHG packages, -40 oG to +8S0G for EJG package, OOG to +70 oG for GPG package).
Parameter
Test Conditions
Definition
Unit
Accuracy
Resolution Accuracy
TC8704
TC8702lTC8705
-
-
-
Bits
Bits
±1/4
±1/2
±1/2
LSB
-
1
±1.5
-
±1/4
11/2
±1/2
Variation in Differential Nonlinearity
Due to Temperature Change
-
12.5
±5
±5
pprnt'"C
Variation From Exact A (Compensate
by Trimming RIN or RREF)
-
±2
±5
±5
%of
Nominal
Variation in A Due to Temperature
Change
-
±25
±75
±80
pprnt'"C
-
±10
±50
±50
mV
Variation in Zero Offset Due to
Temperature Change
-
13
±5
±8
pprnt'"C
liN Full Scale
Full-Scale Analog Input Current
to Achieve Specified Accuracy
-
10
-
IREF
Reference Current Input to
Achieve Specified Accuracy
-
-20
-
-
Binary Word Length of
Digital Output
10
12
Relative Accuracy
Output Deviation From Straight Line
Between Normalized Zero and
Full-Scale Input
(TC8705CPG Only)
-
Differential
Nonlinearity
Deviation From 1 LSB Between
Transition Points
Differential Nonlinearity
Temperature Drift
Full Temperature
Range
Gain Variance
Gain Temperature
Drift
Zero Offset
Zero Temperature
Drift
Full Temperature
Range
liN = 0, CINT = 68 pF, Correction at Zero Adjust to Give
Zero Output When Input is Zero
RADJ= 1 kn
(See Test Circuit)
Full Temperature
Range
Analog Input (See Note)
.-
Digital Input
-
-
LSB
LSB
~A
~A
VIN(I)
Full Temperature
Range
Logic "I" Input Threshold for
Initiate Conversion Input
3.5
-
-
-
V
VIN(O)
Full Temperature
Range
Logic "0' Input Threshold for
Initiate Conversion Input
-
-
1.5
1.5
V
2-89
BINARY OUTPUT
ANALOG-TO-DiGITAL CONVERTERS
TC8702
TC8704
TC8705
ELECTRICAL CHARACTERISTICS (Cant.)
Parameter
Test Conditions
Definition
Propagation Delay
Output Enable
(TC8704, TC8705)
CL= 100 pF,
RL= 1 kn
Digital Output
IO(OFF)
(TC8704, TC8705)
VOUT(1)
VOUT(O)
OE = 3.5V
O.4V < Vc < 2.4V
Off-State Output Current
-
0.1
±10
Full Temperature
Range,
IOUT= -10 itA
lOUT = -500 itA
Logic "1" Output Voltage
for Digits Out, Busy, and
Data Valid Outputs
4.5
2.4
-
-
-
-
-
V
V
-
-
0.4
0.4
V
-
-
5
20
6
24
6
24
ms
ms
167
42
200
50
-
-
-
sec
-
-
-
ns
mA
mA
Logic "0" Output Voltage
Full Temperature
Range, Voo= 4.75V for Digits Out, Busy, and
Data Valid Outputs
lOUT = 500 I1A
±10
I1A
Dynamic
Conversion Time
TC8704
TC8702, TC8705
Full Temperature
Range
Conversion Rate in
Free-Run Mode
TC8704
TC8702, TC8705
V1NT CONV = +5V
Minimum Pulse Width
for Initiate Conversion
Full Temperature
Range
Time Required to Perform One
Complete AID Conversion
500
Supply Current
100 Quiescent
J/H Packages
P Package
Iss Quiescent
J/H Packages
P Package
Supply Sensitivity
Full Temperature
Range,
VINT CONY = OV
Current Required From Positive
Supply During Operation
-
1.4
1.4
2.5
5
3.5
-
Full Temperature
Range,
VINT CONV = OV
Voo ±1V, Vss ±1V
Current Required From Negative
Supply During Operation
-
-1.6
-1.6
-2.5
-5
-3.5
Change in Full-Scale Gain vs
Supply Voltage Change
-
±0.5
±1
±1
%N
IVool = IVssl =
5V±1V
Change in full-Scale Gain vs
Supply Voltage Change for
Tracking Supplies
-
±0.05
±0.1
±0.1
'Yo/V
-
-
rnA
mA
NOTE: lIN and IREF pIns connect to the summIng Junction of an operational amplifier. Voltage sources cannot be attached dIrectly but must be
buffered by extemal resistors. See 'Test Circuit.'
2-90
BINARY OUTPUT
ANALOG-TO-DIGITAL CONVERTERS
TC8702
TC8704
TC8705
TIMING DIAGRAMS
Clocked Mode
INITIATE
CONVERSION
Free-Run Mode
VIH - - -_--...,,-mm=~~
o
VOL - - - - ' - - I I
DATA VOH - - - i - - - - - - f
VALID VOL-DIGITS VOH ---i~-----fl---,==,""~~
OUT
VOL---i~----~~-~~~~--f
_~~~ns
CONVERSION _ _ ~
TIME
RECYCLE
TIME
~2.5I1s
4344110L F03
CIRCUIT DESCRIPTION
During conversion, the sum of a continuous current (liN)
and pulses of a reference current (IREF) is integrated for a
fixed number of clock periods. liN is proportional to the
analog voltage; IREF is switched in for exactly one clock
period just frequently enough to maintain the output of the
integrator near zero. Thus, the charge from the continuous
hN is balanced against the pulses of IREF. The total number
of IREF pulses needed during the conversion period to maintain the charge balance is counted, and the result (in binary)
is latched into the outputs at the end of the conversion.
The converter contains two counters and a clock, in
addition to an operational amplifier, comparator, latching
output buffers, and housekeeping logic. One counter is a
clock counter which starts counting clock pulses after a
reset pulse; when the required count is reached, the clock
counter generates a pulse to start the end-of-conversion
routine. The other counter is a data counter, which is reset
synchronously with the clock counter and counts the number of times IREF is switched into the summing input of the
amplifier during the period defined by the clock counter.
When the initiate conversion input is strobed with a
positive signal, the busy line latches high and a 10 Ils
(times given are approximate) start-up cycle begins. The
integrating capacitor is discharged and both counters are
reset during this start-up period. Conversion begins at the
end of the reset pulse and ends with a pulse generated
either by the clock counter or by an overflow condition in
the data counter. This pulse disables further inputs into
both counters and triggers a 10 Ils shutdown cycle. During
the shutdown cycle, data valid goes low for 5 1lS. This
binary sequence is shown in the timing diagrams. Busy is
true high and, when the circuit is busy, initiate conversion
has no effect and may be high or low. Data valid is also true
high. The data from a conversion remains valid for as long
as power is applied to the circuit or until data valid falls at
the end of a subsequent conversion, at which time the
output data is updated to reflect the latest conversion.
PIN FUNCTIONS
Initiate Conversion Input
Accepts CMOS and most +5V logic inputs. Applying a
logic "1" to the initiate conversion pin initiates the AID
conversion cycle. Once conversion has been initiated, the
cycle cannot be interrupted, and the initiate conversion pin
is disabled until conversion is complete. Two modes of
operation are permitted: clocked orfree-running. For clocked
operation, the initiate conversion input is held at logic "0" for
standby and taken to logic" 1" when a conversion is desired.
For free-running operation, the initiate conversion pin is
connected to VDD or similar permanent logic "1" Voltage.
Busy Output
A digital status output which is compatible with CMOS
logic and low-power TTL (can sink and source 500 ilA). A
logic "1" output on the busy pin indicates a conversion
cycle is in process. A logic "1" to logic "0" transition indicates conversion is complete and the result has been
latched at the digit out pins. A logic "0" to logic "1" transition
indicates a new conversion cycle has been initiated. If the
2-91
BINARY OUTPUT
ANALOG-TO-DIGITAL CONVERTERS
TC8702
TC8704
TC8705
device is operating in the free-running mode, the busy
output will remain low for approximately 2.5 J.lS, marking
the completion and initiation of consecutive conversion
cycles.
RIN. RREF
Values of these components are chosen to give a fullscale input current of approximately 10 IlA and a reference
current of approximately -20 1lA:
Data Valid Output
A digital status which is compatible with CMOS logic and
low-power TTL (can sink and source 50 1lA). A logic "1"
output at the data valid pin indicates the digits out pins are
latched with the result of the last conversion cycle. The data
valid output goes to logic "0" approximately 5 /!s before the
completion of a conversion cycle. During this 5 J.lS interval
new data is being transferred to the digits out pins, and the
digits out are not valid.
Digits Out
The binary digit outputs (Bit 0 ... Bit 11) which are the
result of the AID conversion. These outputs are CMOS logic
and low-power TTL compatible.
APPLICATIONS INFORMATION
Input/Output Relationships
Digital counts = VIN' A • RREF
RIN ,VREF
A = 2064 for TC8704; 8208 for TC8702fTC8705
where digital counts is the value of the binary output word
presented at digits out pins in response to VIN.
The digital output code format is as follows:
Digital Outputs
MSB
VIN ,,; Full Scale
=Full Scale -1 LSB
=1 LSB
VREF .
-20 IlA
Examples:
10V
RIN= ~~ =1 Mn
10 IlA
RREF = --6.4V = 320 kn
-201lA
Note that these values are approximations, and the
exact relationships are defined by the transfer equation. In
practice, the value of RIN typically would be trimmed using
the optional gain adjust circuit to obtain full-scale output at
VIN full scale (see adjustment procedure). Metal film resistors with 1% tolerance or better are recommended for highaccuracy applications because of their thermal stability and
low-noise generation.
Specifications for the TC87XX are based on RBIAS =
100 kn ±1 0%, unless otherwise noted. However, there are
instances when the designer may want to change this
resistor in order to affect the conversion time and the supply
current. By decreasing RBIAS, the AID will convert much
faster and the supply current will be higher. For example,
when RBIAS is 20kn, the conversion time is reduced by 1/3,
and the supply current will increase from 2 rnA to 7 mAo
Likewise, if RBIAS is increased, the conversion time will be
longer and the supply current will be much lower. For
example, when RBIAS = 1 Mn, the conversion time will be six
times longer, and supply current is now reduced to 0.5 mAo
For details of this relationship, refer to AN-9 typicalperformance curves.
LSB
111
111
000
000
ROAMP
... 1
... 1
... 1
... 0
The exact value is not critical, but should have a nominal
value of 100n ±10%. Locate close to pin 14.
Two's complement coding can be generated by inverting the Most
Significant Bit (MSB) signal.
The exact value is not critical, but should have a nominal
value of 270 pF ±20%. Locate close to pin 14.
,,;0
1 ...
1 ...
0 ...
0 ...
RREF =
RBIAS
The analog input voltage (VIN) is related to the output by
the transfer equation:
Analog Input
R - VIN Full Scale
IN =
10 IlA
COAMP
External Component Selection
CINT
The exact value is not critical, but should have a nominal value of 68 pF ±10%. Low leakage types are recommended, although mica or ceramic devices can be used in
applications where their temperature limits are not exceeded. Locate as close as possible to pins 14 and 15.
Obtaining a high-accuracy conversion system depends
on the voltage regulation of VREF and thermal stability of RIN
and RREF. The exact dependence is given by the transfer
function. System accuracy also depends, to a lesser degree,
on the voltage regulation of Voo and Vss. Supply connections Voo andVss should have bypass capacitors of 0.1/!F
value, or larger, at the device pins.
2-92
BINARY OUTPUT
ANALOG-TO-DIGITAL CONVERTERS
TC8702
TC8704
TC8705
recommended transition points be used in setting the zero
and full-scale values. The recommended procedure is:
VREF
A negative reference voltage must be supplied. This
may be obtained from a constant current source circuit or
from the negative supply.
(1) Set initiate conversion control high to provide freerun operation and verify converter is operating.
Voo, Vss
Power supplies of ±5V are recommended, with 0.05%
line and load regulation, and 0.1 ~F decoupling capacitors.
(2) Set VIN to +1/2 LSB and trim the zero-adjust circuit
to obtain a 000 ... 000 ... to 000 ... 001 transition.
This will correctly locate the zero end.
Adjustment Procedure
(3) For full-scale adjustment, set VIN to the full-scale
value less 1-1/2 LSB and trim the gain-adjust circuit
for a 111 ... 11 0 to 111 ... 111 transition.
The test circuit diagram shows optional circuits for
trimming the zero location and full-scale gain. Because the
digital outputs remain constant outside of the normal
operating range (i.e., below zero and above full scale), it is
If adjustments are performed in this order, there should
be no interaction and they should not have to be repeated.
TYPICAL APPLICATIONIDESIGN CIRCUITS
TC8705 Interface to MC6821 PIA
V+=+5V
TO
MC6809
j.!P
IA~: ----,--==-,
..r-t-_ _..:2=-j3 DATA VALID
CAl ...
CA2
A4
AO ----'_ _
:.=.,
Al---:='-j
TO 6809 j.!P
INTERRUPT
IRQA
..J'"'1..
21 START
CONY
BITS 1-8
Bl-88
15
~
__J""'.~
ANALOG
INPUT
""r--
MC6821
TC870S
BITS 9-12
B9-812
4344 ILL Fa.!
2-93
BINARY OUTPUT
ANALOG-TO-DIGITAL CONVERTERS
TC8702
TC8704
TC8705
TYPICAL APPLICATIONIDESIGN CIRCUITS (Cont.)
Bipolar Operation (+ and -Inputs)
ABSOLUTE VALUE CIRCUIT WITH SIGN
+5V
RREF
-VREF
O---------JV~r_------------~------------~1~-----1----------
r--..I
I
'- _________ _
15
I
---1-----------1
I
I
I
I
I.....
I
I
I
I
I
I
112 RIN
R
14
r-~vv~~~IVv-~-------.--~--¥--~--1-......
16
I
.. >--~--------1+"
,..
ROAMP
+
*
MV5054' ..,.... COAMP
~
'----t-o()
~~:'J'gUTPUT
(1 =+.0=-)
2N2222
.,~
TC8702
TC8704
TC870S
OR EQUIVALENT
'Optional visual indication of negative input.
NOTE: Values for R should be between 10 kn and 100 kn.
Reference Voltage Supply
+5V:t5%
+12V
3.3 kCl
>-.-..~~ TO RREF (100 kCl)
FOR 8700 SERIES
NOTE: VREF = 2V using voltages derived from 8080A ILP.
04344 ILL FOS
2-94
BINARY OUTPUT
ANALOG-TO-DIGITAL CONVERTERS
TC8702
TC8704
TC8705
TYPICAL PERFORMANCE CURVES
Conversion Time vs R B1AS
Supply Current vs
RBIAS
10.0
10.0
r-T = +25°C
f=~D=+5V
r-VsS=-5V
_.-
./
,
7" ~-
C(
J
~=+25°C
DO=+5V
VSS=-5V
I
0.1
100k
RBIAS(Q)
1.7
w
z
~
i1.2
~....-~
I'.....
~ 0.9
~
::::; 0.7
:&
"
c(
~ 0.5
---+--
z
0.3
0.7 L......---L_-'------'_....J..._'------L---l
-65 -25
0
25
50 75 100 125
TEMPERATURE ("C)
23456789
Voo=VSs(V)
Supply Current vs Temperature
Supply Current vs Supply Voltage
7r---r--r---r-,--,--,--.
.-
2.2
- -- 1--------
6 ----
I I
-----2.0
i"...
C(
!.
1l
~
1.8
C
.9
1.6
1~5
3
,
_\..
o
~ 0.9 /-V_+-_--+_+-_+ --+---+----1
- T A = +25°C --
\.
~ 1.1
:&
z
\
1.3
w
> 1.1 r - i - - - - --+----+--=-""",,-'=---1
--
T~=+2~OC-
\
~ 1.5
z
~ 0.8-~-
4
5
6
7
Voo=VSs(V)
8
1M
Conversion Time vs Supply Voltage
Conversion Time vs Temperature
~-
100k
RBIAS(Q)
10k
1M
1.4 r----r--r---r--,.--,---,---,
w
VOO=+5V
~ 1.31--- VSS =-5V- - -- ----- ---
fil1.O
1.0
~
--
0.1
10k
8
...... r--..,
!.
9
-25
Voo= +5V
VSS=-5V
"'-
........
........ r--..
i--
o
25
50 75 100
TEMPERATURE ("C)
125
4344 ILL. Foe
2·95
BINARY OUTPUT
ANALOG-TO-OIGITAL CONVERTERS
TC8702
TC8704
TC8705
TYPICAL PERFORMANCE CURVES (Cant.)
Output Source Current
vs Temperature
Output Source Current
vs Supply Voltage
5.5
8
5.0
7
V~~I~WV
VSS=-7V
ffttHt-.
~5'C
4.5
€
~
4.0
-
~ 3.5
.. _..
I'
I- voo= +5V
1----
VSS=-5V
I
1.5
0.1
~
"
--
VOO=+5V
Vs =-5V
5
-
J:4
\1\
2.5 /--2.0
€
r\f\
+125'C
3.0 ------ -_.-
~
6
j;+25'C
3
r-
2
I I
1.0
IOH(mA)
-[ I I II
II
0.1
~
--- ----"
~
1.0
1---+-+-il-tl~-+~l-Hl.ctII"-...tr
71-1l-s'+--+5'-+C+++tH
I -I 1111
>-
V
0.50
0.25
1----+-+:;;!4K,j,oI'f---l--++-t-t++tH
0.25
0~E:~~
--
0.1
Linearity vs Reference
Current Input
CD
2.0
~
1.0
0.5
~
a:
ffi
33pF
68pF
150pF
r- 33 pF
1.0
IOl(mA)
~ -0.5
II
~ -1.0
z
:::; -2.0
-3.0
III
III
2
VOO=+5V
~
1.2
CI
~
1.1
~~
1.0
fil~
0.9
---
:::;
~
0.8
_-
~
~
If-II 111
rr
::
'I
/
~
:/
0 I-
iX
II
I
CINT
30?pF
V"
CINT
...... 68pF
lS0pF
n
N
--
._.. -
...
Z
:-3io
5 10 20 50100
IREF(IlA)
I
,/
c- VSS=-5V
V
V
V
/
-- ---
0.7
-25
0255075
TEMPERATURE ('C)
2-96
/'
L'"
0.6
-55
200 500
10.0
Three-State Propagation Delay
(TC8704, TC8705)
1.3
I_I II
J
V
VOO=+7V
VSS=-7V
t:::1::
IOl(mA)
II III1
I
VL.
o
10.0
~,
/
~
1----+-+-H--HI1f-Hf-l--I+-++-I*1+H
3.0
10.0
II
VOO=+3.5V
VSS=-3·5V
:; 0.75
0.50
1~
r--- VSS = - 5V
1.0
I)
~1
1\
Jo~=IJJI
1.25
I
... 0.75 1--+-++-+-+-t'HI--I-4I--Ft-=t-++++11
~
f\
1.0
IOH(mA)
1.5
IT'.J-HU-t+t-I/-I---tl/t-l--H-+t-t+
+25-c
'1\
Output Sink Current
vs Supply Voltage
I III'
~~~:~~~11
~
voo= +3.5V
vss = -3.5V
Output Sink Current
vs Temperature
1.5
1.25
I'
j--..
o
10.0
1'1'.
100
125
4344 ILL F07
Section 3
VOltage-to-Frequencyl
Frequency-to-Voltage
Converters
Display AID Converters
Binary AID Converters
Yoltage.to-Freq_ncy/Frequency-lo-Yoltage Converter.
2
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
~"'TELEDYNE
COMPONENTS
4731
4733
HIGH-RELIABILITY HYBRID
VOLTAGE-TO-FREQUENCY CONVERTERS
GENERAL DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
The 4731 and 4733 low-drift voltage-to-frequency (V-to-
Power Supply Range ...•............•............ ±9V to ±18V
Ultra-Linear
Overrange .......................................................... 100%
Dynamic Range .............................................. 126 dB
Common-Mode Rejection Ratio ..........•.......•... 60 dB
Low Full-Scale Drift
Low Zero-Offset Voltage Drift
TTL, CMOS, HNIL Compatible Output
F) converters produce output pulse trains whose repetition
rate is a precision linear function of the input voltage. These
low-drift, ultra-linear devices can handle pos~ive, negative
and differential input signals, and can operate with a wide
range of power supply voltages.
W~h 126 dB of dynamic range, 70 dB CMRR, and 100%
overrange, these devices provide linear operation with input
voltagesfrom±1 0JlVto+20V. Theircurrent input pin (actually
the summing point of an op amp) can resolve currents as low
as 1000 pA, making it possible to operate with full-scale input
voltages from less than 250 mV to greater than 100V.
Their 0.002% nonlinearity is the equivalent of 16-bit endpoint linearity. Differential nonlinear~y and dynamic range
approach 20 bits.
The 4731 and 4733 are packaged in 24-pin hermetic
metal packages. Standard devices are specified for O°C to
+70°C operation. The High Reliabil~y (HR) versions are
specified for -55°C to + 125°C operation.
APPLICATIONS
•
•
•
•
•
No Drift Integrate/Hold
High Common-Mode Voltage Isolation
2-Wire Digital Transmission
20-Bit Analog-to-Digital Converters
Optical Data Link
SIMPLIFIED BLOCK DIAGRAM
1----------------------------------------------.
EOS
,:8
~'"
R3
,
473114733
5:
•
20
:12
R2
+VIN n-..o...;.;;-",I\J'\~"
,,
,,
.-.=.24'-'-0 TTL
I
'10
O-~,~---'
,,
,
:11
,,
,,
,,
+Vee
R5
,'9
,,
liN
O-Vee
rlf--'2::3:;-0 OUTPUT
R4
e
R&
:L _____________________________________________
~~--~======~------4_22~2+_OCOMMON
J
3-1
HIGH-RELIABILITY HYBRID
VOLTAGE-TO-FREQUENCY CONVERTERS
4731
4733
PIN CONFIGURATION
Pin
No.
Designation
Pin
No.
1
2
NC
NC
24
23
3
NC
22
4
5
6
7
8
9
10
11
NC
21
20
12
-Vee
NC
19
NC
Eos
+VINTRIM
liN
-VIN
+VIN
18
17
16
lS
14
13
Designation
TTL
fOUT
COMMON
.00000000000
1
NC
12
~'"
+Vcc
NC
4731/4733
NC
NC
24
13
000000000000
NC
NC
NC
NC
NC = No internal connection
ABSOLUTE MAXIMUM RATINGS
Vee
+VIN
-VIN
VID
liN
Te
TSTG
Power Supplies ............................................ ±18V
Positive Input Voltage (Note 1) .................... ±21V
Negative Input Voltage ................................. ±Vce
Differential Input Voltage (Note 1) .................. Vee
Current Input ............................................. 210 ~
Specified Temperature Range (Case)
4731/4733 ................................... O°C to +70°C
4731-HR/4733-HR ................ -55°C to +125°C
Storage Temperature Range ..... -{)5°C to +150°C
ELECTRICAL CHARACTERISTICS:
Symbol
Parameter
Input
+VIN
-VIN
Typ
Positive Input Voltage
-
Negative Input Voltage
-8
10
-10
Common-Mode Input Voltage
-7
Common-Mode Rejection Ratio
VIO
liN
Differential Input Voltage
Current Input Range
R+IN
FLIN
RIIN
=+25°C, ±Vee =±15V, unless otherwise indicated.
Min
VCM
CMRR
Vos
Vos/TC
Te
Test Conditions
=
=
VCM ±6V, VOIFF O.SV
Referenced to -VIN (Note 1)
60
.001
100
10
-
Max
Unit
20
V
-
V
+7
V
-
dB
V
120
ItA
-
±s
dB
mV
--
±1
±6
±20
±20
±20
J.LVrC
+VIN Input Impedance
7S
100
12S
kn
-VIN Input Impedance
Current Input Impedance
10
100
<0.1
-
Mn
n
Input Dynamic Range
Input Offset Voltage
Input Offset Voltage vs
Temperature
Adjustable to Zero
-2SoC to +8SoC
+2S"C to + 12SoC } Typical for standard
+2S"C to -SsoC } tested for H R
Virtual Ground
3-2
-
-
-
±100
J.LVrC
±SO
J.LV/oC
-
HIGH-RELIABILITY HYBRID
VOLTAGE-TO-FREQUENCY CONVERTERS
4731
4733
ELECTRICAL CHARACTERISTICS
(Cont.)
Symbol
Parameter
Test Conditions
Min
Output
VOH
Output High Voltage
IOH=4mA
2.4
VOL
Output Low Voltage
IOL=-16 mA
-
-
2.8
3.5
Ro
Transfer
fOUT
Output Impedance
~ VIN Equals VIN - (-VIN)
Output Frequency
fA
Scaling Frequency
4731
4733
Adjustable to Typical
Adjustable to Typical
fAfTC
fA vs Temperature
4731
-55°C to + 125°C
-25°C to +85°C
-55°C 10 + 125°C
-25°C to +85°C
4733
fAvsTime
IFS
Full-Scale Current
IFSfTC
IFS vs Temperature
Per Day
Per Month
4731
4733
IFS vs Time
+25°C to +85°C
+25°C to -25°C
+25°C to +85°C
+25°C to -25°C
Per Day
Per Month
kHz
kHz
9.95
99.5
10
100
10.05
100.5
-
-
±8
±7
±12
±10
±50
±25
±50
±30
ppmi°C
ppmi°C
ppmi°C
ppmi°C
-
±10
±30
-
ppmiD
ppmiM
75
100
125
-
±4
±7
±6
±10
~A
ppmi°C
ppmi°C
ppmi°C
ppmi°C
-
±10
±30
-
-
-
-
kHz
kHz
ppmiD
ppmiM
O/OFS
O/OFS
0.01% Accuracy
0.002% Accuracy
10
1
-
30
3
~
-
1
100
-
s
s
-
-
~s
1 to 2 Pulses@New Freq+(5 ~s)
~VIN
= 1OOV to 10V or
~IIN = 1 mA to 0.1 mA
IVeel -I-Veel
fA vs Power Supplies
IFS vs Power Supplies
x fA] + 10V
[liN x fA] + IFS
±0.02
Quiescent Current
VOS vs Power Supplies
[~VIN
±O.Ol
Settling Time
PSRR3
kQ
±0.002 ±0.005
4731
4733
PSRR2
4.2
-
liN Linearity Error (Note 2)
Icc
PSRR1
V
V
liN = 1 nA to 120 ~A
-VIN Linearity Error (Note 2)
liNLE
tpw
Power Supplies
Voltage Range
Vee
Voltage Asymmetry
0.4
VIN = -100 ~V to (-Vee +7V)
-VINLE
Overload Recovery
5.0
%FS
%FS
%FS
VIN = 100 ~Vto 12V
-55°C to + 125°C } Tested for
-25°C to + 125°C } HR only
Dynamic
ts
-
Unit
±0.OO2 ±D.005
±O.OOS ±0.03
±D.OOS ±0.01
+VIN Linearity Error (Note 2)
Warm-Up Time
Max
-
+VINLE
Output Pulse Width
Typ
Constant Voltage at Pin 8
-
0.14
1
±9
±15
±18
V
-
-
±2
V
-
±17
±2S
mA
±10
±20
ppmi%
-
±10
±20
ppmi%
-
±3
±20
IlV/%
NOTES: 1. +VIN has a 100 Idl internal resistor and a 210 ~ maximum input current limit. The voltage input,
if current-limited by a series input resistor, is virtually unlimited.
2. Linearity specifications apply only after offset and gain have been trimmed to nominal.
3. Limits printed in boldface type are guaranteed and 100% production lested. Limils in nonnal fonl are guaranteed but not 100%
production tested.
3-3
ms
HIGH-RELIABILITY HYBRID
VOLTAGE-TO-FREQUENCY CONVERTERS
4731
4733
THEORY OF OPERATION
Basic Connections
To take maximum advantage of the 4731/4733's versatility, a functional block diagram and theory of operation are
provided herein. With this information, input and output
circuitry is easily modified to handle virtually any input signal
or output load.
The 4731 and 4733 are free-running (astable), voltagecontrolled multivibrators (see Block Diagram). The effective
currents from the four inputs (+VIN, +VIN TRIM, +IINand Eos)
are summed at the inverting input of op-amp A 1. A 1 and
transistor 01 form a precision current pump, producing
current (I). Current charges capacitor C at a rate which is a
precise linear function of the device's input signal.
When the voltage impressed on C (due to I) reaches a
fixed precision threshold, the Schmitt trigger output changes
state and triggers the one-shot (monostable) multivibrator,
which in turn produces a single constant-width output pulse.
This pulse performs two functions. Amplified by 02, it is the
output of the V-to-F converter and also activates the precision charge dispenser (PCD). The PCD discharges C to the
same "zero" level every time an output pulse is produced.
Thus, capacitor C is repeatedly charged and discharged
between two precise voltages at a rate which is a linear
function of the device's voltage and/or current input signal.
This action produces the waveforms shown in the timing
diagram of Figure 11.
The 4731 and 4733 are factory trimmed and operate as
specified without additional components. Figures 1 and 2
illustrate the basic connections for positive or negative input
signals and also show the optional offset adjustment connection. Pin 9 (+VIN TRIM) and pin 12 (+VIN) are inputs for
positive voltage signals. +VIN is used when accuracy to
±0.1 % full scale is acceptable or when external components
cannot be accommodated. +VIN TRIM is used when greater
full-scale accuracy is required because it allows the use of
an external trim adjustment potentiometer. Pin 10 (lIN) is a
direct input to the input amplifier summing junction, and is
used to input positive-current signals. Its full-scale accuracy
is limited to ±2S% of the inherent input current full-scale
factor mentioned earlier. Pin 11 (-VIN) can be used to input
negative voltage signals, as shown in Figure 2.
Zero and Full-Scale Trim
When greater accuracy is required, input offset voltage
(Eos) is trimmed to zero. For positive inputs only, full-scale
output frequency (fOUT) is trimmed to 10 kHz or 100 kHz,
depending on the device being used, with external potentiometers (illustrated in Figures 1 and 2). Note that full-scale
trim components should have temperature coefficients similar to the full-scale TC of the device being used.
TRIM THEORY
The V-to-F input circuit zero and full-scale trim are
performed at the input circuit amp A 1 (see block diagram).
The user may treat the V-to-F input as an operational
amplifier, within certain limits.
No signal combination should be applied to the V-to-F
inputs which will drive the A 1 output positive. A frequency
output will not result if total current into the V-to-F positive
inputs (A 1 , summing point) becomes negative with respect
to the V-to-F negative input. If this occurs, D1 becomes
forward-biased, 01 will cut off, and current (I) and fOUT will
be zero.
The inherent input current full-scale factor is 100 ~
±2S% for a full-scale output. All current adjustment trimming
must take this ±2S% tolerance into account. Resistor R1
(see block diagram) is factory laser trimmed so that a fullscale input to +VIN TRIM (pin 9) produces an output 101 %
±O.S%of nominal full scale; i.e., a +10V input to +VIN TRIM
of the 4731 produces a 10.1 kHz ±o.OS kHz output. Resistor
R2 is factory trimmed so that +V IN is within ±O.S% of nominal
full scale; i.e., a +10V input to +VIN of the 4731 produces a
10kHz ±o.OS kHz output. Both +VIN and +VIN TRIM inputs
are trimmed with and specified for Vee = ±1SV at 2SoC.
.rf-o TTL
'OUT
o-.-IH:> COMMON
50kQ~. .
o
,-++-o +VCC -vcc o-+--..:1c:.5V.:......J
o
o
o
o
o
+VIN TRIM
.N
o
liN
OTO+100"A
o
-VIN 0--
15:..:V
L....:::+..::
EOSg.. J n,2kQ
013
Figure 1.
3-4
+VIN o-+-H:> 010 +10V
Positive Voltage/Current Inputa
j
HIGH-RELIABILITY HYBRID
VOLTAGE-TO-FREQUENCY CONVERTERS
4731
4733
TTL
TTL
1.
Q-4~--o fOUT
0
0
~~~JCOMMON
o
+15V
0
L-.:.+..:.;15:,,;V'-++-G +Vcc
o
o
o
o
o
o
fOUT
COMMON
50kn
-Vcc
cr-+--....:1.=..5V,--,
0
0
0
013
EOS~+----'
+VINTRIMO
liN 0
-VIN o--f--OOV TO-aV
50kQ
+Vcc
0
0
0
o
o
013
0
1.
0
0
0
EOS
+VIN TRIM 0
liN
-VIN
+VINO
+VIN
IA x RA = IB x RB
EC = liN max [(RAxRB) + (RA+RB)1
EC must be '" signal source compliance voltage
Figure 2.
Negative Voltage Input
Figure 3.
Zero and Full-Scale Trim for Positive Input Currents
TRIM PROCEDURES
1. Apply 10 mV between +VINand ground. Adjustthe50 kn
potentiometer to setfoUT equal to 10Hz (4731) or 100 Hz
(4733).
-8V> VIN > +10V
This series of V-to-F converters can be operated with
input voltages greater than +10V by connecting a fixed
resistor and trim potentiometer in series with the +VIN or
+VIN TRIM inputs (see Figure 4). The same effect can be
realized by using a properly selected series resistor and
inputting the signal to the current input (+IIN). For inputs more
negative than -aV, the attenuator network of Figure 5
performs well. For either positive or negative inputs the
zero trim and other adjustments remain the same as in
Figures 1 and 2.
2. Apply +10V between +VIN and ground. Adjust R1 to set
fOUT equal to 10 kHz (4731) or 100 kHz (4733).
3. Repeat (1) and (2) until zero and full scale are set
precisely. Note: Zero is set at 10Hz to 100 Hz out for
10 mV in, because it is impractical to measure 0 Hz out
for OV in.
Full-scale accuracy for +hN is ±25%. Greater accuracy
is obtained by using the full-scale and zero trim circuit shown
in Figure 3. Resistor dividers RA and RB are only used when
the actual input current is greater than that necessary to
produce a nominal full-scale output frequency.
-10V < Full-Scale VIN < +10V
If full-scale input voltage is between +10 !lV and +1 V,
the full-scale output is set to nominal full scale by using the
current-input terminal with a series resistor, as shown in
Figure 6.
If full-scale input signal is between-10Vand -10 !lV, a
low-drift amplifier (such as the 1435) should be used to
amplify the Signal full scale to-10V, or even + 1OV, and then
apply the signal as usual (Le., Figures 1 and 2). This
preamplification technique can also be used with positive
input signals.
FULL-SCALE FACTOR CHANGE
The specified input voltage full-scale factor for the 4731
and 4733 is 9.9V ±0.5% with respect to -VIN (or +100 J.IA
±25% liN) to produce a full-scale output frequency. Many
applications require a full-scale output for other (larger or
smaller) full-scale input signals or input polarities. Figures 4,
5 and 6 illustrate how to operate with such input signals.
3-5
..
HIGH·RELIABILITY HYBRID
VOLTAGE·TO·FREQUENCY CONVERTERS
4731
4733
TTL
CH~-ofOUT
D---O -15V
o
o
SUM POINT 0
OUTPUT 0-+-41>-0 VOUT
FSINPUT
013
FSADJO
*R1 + R2 = (5 x 1010) + Desired Full-Scale in Hz
Figure 5. Input Conditioned for Small Ae Signal with DC Offset
Figure 4_ Custom Full-Scale Factor
Operation With HNIL or CMOS Logic
Operation With DC Common Mode
To obtain maximum noise immunity with a particular
logic type, the threshold should be set approximately halfway between the upper and lower logic levels. For example,
a 2 kn, 5% resistor connected between REF IN and + 15V
provides a threshold of +6V (a typical CMOS or HNIL
threshold level). Adjusting the threshold voltage in this
manner has no impact on the zero and full-scale trim
techniques discussed earlier.
When the input signal is small and impressed on a DC
voltage (i.e .• +9V DC ±500 mV AC). it should be capacitively
coupled to the 4736. as shown in Figure 5. If the DC voltage
is large. greater than ±Vee. the input should be protected
against transients with diodes. as shown in Figure 6.
Signals greater than ±Vcc peak-to-peak may also be
attenuated with a simple resistive divider and the appropriate threshold level. as discussed earlier.
Operation With Signals Less Than +2V Peak
Scale Expansion and Bipolar Output
Connecting an 11 kn, 5% resistor between REF IN and
-15V will set the threshold at OV with hysteresis of approximately 340 mV. Nowthe input signal only needs to be larger
than 340 mV. However, input signals less than 500 mV
should be used with care. They may produce erroneous
output voltage due to the uncertainty of the hysteresis level.
For input signals less than 500 mV, hysteresis should be
reduced by connecting a 2000 resistor between REF IN and
COMMON. This will lower the hysteresis and noise immunityto approximately 60 mV (see Figure 5). A 1000 resistor
provides 30 mV'Of hysteresis, which is the minimum recommended value. When operating in this mode the 4736 is
virtually a zero-crossing detector.
If an output voltage of -5V to +5V is required for 500 kHz
to 1 MHz input, the same technique described in "Scale
Expansion and Output Offset" is used. The scale is dOUbled
and the output is offset a total of -15V (from + 1OV to -5V) by
additional current into the SUMMING POINT (pin 9);
Output Ripple Filtering and Response Time
By definition. frequency-to-voltage conversion is
converting an AC signal to a DC level. Therefore. there must
be ripple on the output. This ripple is filtered by a frequency
variable filter and by an internal RC network consisting of RF
and a capacitor (C2) (see block diagram). Additionalfiltering
3-16
HIGH-RELIABILITY HYBRID
FREQUENCY-TO-VOLTAGE CONVERTER
4736
is obtained by adding an external capacitance between the
summing point and output.
The response time of the F-to-V converter (how fast the
output voltage changes for a step change in the input
frequency) is the RC time constant of the ripple filter. If
external capacitance is added, response time is increased.
If faster response with reduced ripple voltage is required, a
higher frequency-to-voltage should be used or a multipole
(i.e., sharp cutoff) low-passfiltershouldfollowthefrequencyto-voltage.
11 lin
0.1
t
~ +l00VDC
fiN
REF IN
1.
0
0
0
-Vee
+VCC
0
0
0
0
ZERO ADJ 0
0
SUM POINT 0
0
OUTPUT
0
FSINPUT
0
FSADJO
013
+15V
-15V
Your
Figure 6. Input Conditioned for Small AC Signallmprassecl on Large DC Voltage
3-17
NOTES
3-18
~"'TELEDYNE
COMPONENTS
4743
HIGH FREQUENCY, HYBRID
VOLTAGE TO FREQUENCY CONVERTER
GENERAL DESCRIPTION
The 4743 hybrid voltage to frequency converter offers a
full scale output of 1 OMHz, and can be externally trimmed to
any value from its rated full scale output down to 2.5 MHz.
The 4743 has full differential input and can be driven with
positive voltage, negative voltage, or positive current. Common mode rejection ratio, with VCM 10 volts, is 80 dB. With
external resistors, the input is easily adapted to accept
almost any input signal range. The output stage of the unit
is a single uncommitted transistor that operates as a saturated switch. A pull-up resistor for TTL compatibility is
internal to the 4743. An external resistor can be added to
make the output CMOS compatible, and the output can drive
10 TTL loads.
The 4743 has quick response time, and settles to within
±0.01 %FSofa newfrequency in 15 JlSec. Overload recovery
time is approximately 10 output signal periods. Dynamic
range is greater than 100 dB, and input/output linearity over
a ±1 0 mV to ±1 0.5V input range is ±0.05%FS plus ±0.05%
of signal. Initial zero offset erroris±8mV (8kHz). ZeroOftset
error is externally adjustable to zero. Initial full scale accuracy is ±50 kHz, and full scale error is also externally
adjustable to zero. If full scale adjust is not employed, Pins
7 and 9 must be tied together.
The standard 4743 is specified for O°C to +70°C operation. The -HR version is specified for -55°C to +125°C
operation.
FEATURES
•
•
•
•
•
•
Full Scale Output ............................................ 10MHz
Fully Differential Input
Dynamic Range ............................................... 10OdB
Linearity ............................................................ 11-Bit
Supplies ••.••••..••••.•••••••••••••••.•..•.•..••..••.•.• ±14V to ±18V
Easily Modified for Different 110 Signals
=
APPLICATIONS
•
•
•
•
•
Two-Wire Digital Data Transmission
Ratiometric Data Conversion
Long Term Integrators
Fiber Optic Data Links
FM Modulation
BLOCK DIAGRAM
15V
f-
25kn
-15V
Offset
Adjust
8
10MO
C
10kn
+Vin 12
..
20 +Vce
5 -Vee
1 +Vee
..
2kn
lin 10
24 TTL
23 Output
-Yin 11
Full
7
lkn*E Scale
Adjust 9
I"
1kn
R
Ground 2~
221GroUnd
OJ" System Analog Ground
·If Full Scale Aqustmentisnotused,
Pin 7 and Pin 9 must be tied together.
1057-1
3-19
l
..
HIGH FREQUENCY, HYBRID
VOLTAGE-TO-FREQUENCY
CONVERTER
4743
PIN CONFIGURATION
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
Designation
+VCC
GROUND
NC
NC
-Vcc
NC
FULL SCALE ADJUST
OFFSET ADJUST
FULL SCALE ADJUST
+IIN
-VIN
+VIN
Pin
No.
24
23
22
21
20
19
18
17
16
15
14
13
Designation
TIL
fOUT
GROUND
NC
.00000000000
1
+Vcc
NC
NC
NC
NC
NC
NC
NC
.,,,
12
4743
24
13
000000000000
Ne = No internal connection
ABSOLUTE MAXIMUM RATINGS
Vee
±VIN
VID
liN
Te
TSTG
Power Supplies _...... _...... _............................. ±22V
Input Voltage (Note 1) .................................. ±15V
Differential Input Voltage ................................ Vee
Current Input ............................................. 2.1 mA
Specified Temperature Range, Case
4743 ............................................ O°C to +70°C
4743-HR ................................ -55°Cto+125°C
Storage Temperature Range ..... -65°C to +150°C
ELECTRICAL CHARACTERISTICS:
Symbol
Input
+VIN
-VIN
VCM
CMRR
VIO
liN
Vas
VosTC
PSRR1
Te = +25°C, ±Vee = ±15V, unless otherwise indicated.
Parameter
Test Conditions
Positive Input Range (Note 1)
Negative Input Range
Common Mode Input Range
Common Mode Rejection Ratio
DHferentiallnput Voltage
Current Input Range
Input Dynamic Range
Input Offset Voltage
Input Offset DrHt
Vas vs. Power Supplies
For specified linearity
For specHied linearity
Referenced to -VIN
Adjustable to zero
Constant voHage at Pin 8
3-20
Min
0.0001
-0.0001
-
60
10.5
0.0001
100
-
Typ
Max
Unit
-
10.5
-10.5
±10
V
V
V
dB
V
80
12
-
±8
-
1.2
-
±20
±100
±20
rnA
dB
mV
IlVI"C
IlVl%
HIGH FREQUENCY, HYBRID
VOLTAGE-TO-FREQUENCY
CONVERTER
4743
ELECTRICAL CHARACTERISTICS: (continued)
Symbol
Parameter
Input (cont.)
+VIN Input Impedance
R+IN
-VIN Input Impedance
R.IN
liN Input Impedance
RIIN
Output
VOH
VOL
Ro
Dynamic
ts
Transfer
fo
Output High Voltage
Output Low Vo~age
Output Impedance
NOTES:
Min
Typ
-
10
20
<0.1
Virtual Ground
-
10H= 400llA
IOL= -16 rnA
2.4
tNIN = +20V to + 1OV
Output Frequency
AVIN equals VIN - (-VIN)
@ VIN = 1O.OOOOV pins 7 & 9 shorted @ 25°C.
Te
=TMIN to TMAX
@10MHz,±14to±18V
=
=
=
VOM ±1 OV, Vdil .5V
VIN 10 mV to 10V
-
Max Unit
-
kn
-
kn
-
-
632
666
5
0.4
700
15
-
-
Settling Time to ±0.01 % 10V step
Overload Recovery
Full Scale Frequency
Full Scale Current
fA vs Temperature
IFs vs Temperature
fA vs Power Supplies
Common-Mode Rejection Ratio
+VIN Linearity Error (Note 2)
+VINLE
-VIN Linearity Error (Note 2)
-VINLE
liN Linearity Error (Note 2)
IINLE
tpw
Output Pulse Width
Power Supplies
Vo~age Range
Vee
Vo~age Asymmetry
Positive Supply Quiescent Current
+Iee
Negative Supply Quiescent Current
-Icc
Power Dissipation
Po
fA
IFS
fA Te
IFS Te
±PSRR
CMRR
Test Conditions
-
-
10
[AVIN x fAI + 10V
[liN x fA] + IFs
10
10.1
10.2
.75
1
1.25
±100
±40
30
-125
125
60
120
-.100 <.05
.100
-.100
.100
<.05
-.100
<.05
.100
20
65
-
-
-
@ 10 MHz
IVeel - I-Veel
±14
±15
-
-
-
75
-25
1500
±18
±4
90
-35
1875
n
V
V
Q
IlS
Cycles
MHz
MHz
MHz
mA
ppm/DC
ppm/DC
ppm/%AV
dB
%FS
%FS
%FS
ns
V
V
rnA
rnA
rnW
I. +VIN has a lOi10 MQ
Accepts Any Voltage Waveshape
Frequency MeterslTachometer
Speedometers
Analog Data Transmission and Recording
Medicallsolation
Motor Control
RPM Indicator
FM Demodulation
Frequency MultiplierlDivider
Flow Measurement and Control
PIN CONFIGURATIONS
so
DIP
ISlAS
ZEROADJ
VDD
NC
2
ISlAS
1
voo
ZEROADJ
2
NC
AMPUFIER OUT
AMPUREROUT
COMPARATOR IN
COMPARATOR IN
FREQf20UT
FREQf20UT
9
OUTPUT COMMON
9
8
PULSE FREQ OUT
8
OUTPUT COMMON
PULSE FREQ OUT
NC = NO INTERNAL CONNECTION
11Q6.1
3-23
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The TC9400fTC9401fTC9402 are low-cost voltage-tofrequency (V/F) converters combining bipolar and CMOS
technology on the same substrate. The converters accept a
variable analog input signal and generate an output pulse
train whose frequency is linearly proportional to the input
voltage.
The devices can also be used as highly-accuratefrequency-to-voltage (FN) converters, accepting virtually any
input frequency waveform and providing a linearly-proportional voltage output.
A complete v/F or FN system requires the addition of
two capacitors, three resistors, and reference voltage.
Voo-VSS ................................................................. +18V
ORDERING INFORMATION
Part No.
Linearity
(VIF)
TC9400CPD
0.05%
TC9400EJD
0.05%
TC9400COD
TC9401CPD
0.05%
0.01%
TC9401EJD
0.01%
TC9402CJD
0.25%
TC9402EJD
0.25%
Package
14-Pin
Plastic DIP
14-Pin
CerDIP
14-Pin SO
14-Pin
Plastic DIP
14-Pin
CerDIP
14-Pin
Plastic DIP
14-Pin
CerDIP
Temperature
Range
hN ............................................................................ 10mA
VOUT Max -VOUT Common ....................................... +25V
VREF - Vss ...............................................................-1.5V
Storage Temperature Range .................. -65°C to +150°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
E Device ............................................. -40°C to +85°C
Package Dissipation ............................................. 500 mW
Lead Temperature (Soldering, 10 sec) ..................+300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
O°Cto +70°C
-40°C to +85°C
O°C to +70°C
O°C to +70°C
-40°C to +85°C
O°C to +70°C
-40°C to +85 °C
3-24
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
ELECTRICAL CHARACTERISTICS:
VDD = +5V, Vss =-5V, VGND = 0, VREF =-5V, RBIAS = 100 kil,
Full Scale =10 kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified -40°C to +85°C for
E device, O°C to +70°C for C device.
VOL TAGE-TO-FREQUENCY
Parameter
Definition
TC9401
TC9400
TC9402
Min Typ Max Min Typ Max Min Typ Max Unit
Accuracy
Output Deviation From Straight
Line Between Normalized Zero
and Full-Scale Input
-
0.004 0.01
-
0.01
0.05
-
0.05 0.25
% Full
Scale
Linearity 100 kHz
Output Deviation From Straight
Line Between Normalized Zero
and Full-Scale Input
-
0.04 0.08
-
0.1
0.25
-
0.25
% Full
Scale
Gain Temperature
Drift (Note 1)
Variation in Gain A Due to
Temperature Change
-
±25
-
±25
±40
-
±50 ±100 ppml°C
Full Scale
Gain Variance
Variation From Exact A Compensate
by Trimming RIN, VREF, or CREF
-
±10
-
±10
-
-
±10
Zero Offset (Note 2)
Correction at Zero Adjust for Zero
Output When Input is Zero
-
±10
±50
-
±10
±50
-
±20 ±100
Zero Temperature
Drift (Note 1)
Variation in Zero Offset Due to
Temperature Change
-
±25
±50
-
±25
±50
-
±50 ±100 IlV'oC
liN Full Scale
Full-Scale Analog Input Current to
Achieve Specified Accuracy
-
10
-
-
10
liN Overrange
Overrange Current
50
Settling Time to 0.1 % Full Scale
-
-
Response Time
-
-
VSAT @ 10L = 10 jlA
(Note 3)
Logic "0" Output Voltage
-
-
0.4
-
VOUT Max - VOUT
Common (Note 4)
Voltage Range Between Output
and Common
-
-
18
-
3
-
-
2
2
6
-
-1.5
-1.5
-4
-
-6
Linear~y
10kHz
±40
-
0.5
-
%of
Nominal
mV
Analog Input
2
-
-
-
10
-
50
50
jlA
-
-
-
2
2
-
Cycle
-
0.4
-
-
0.4
V
-
-
18
-
-
18
V
-
3
-
-
3
-
IlS
-
2
2
-
-
-
6
3
10
mA
mA
-1.5
-1.5
-6
jlA
Digital Output
Pulse Frequency
Output Width
Supply Current
100 Quiescent
E Device (Note 9)
C Device
Current Required From Positive
Supply During Operation
-
Iss Quiescent
E Device (Note 10)
C Device
Current Required From Negative
Supply During Operation
Voo Supply
Operating Range of Positive Supply
Vss Supply
Operating Range of Negative Supply
-
-
4
-
4
-4
-
-
-
-3
-10
mA
mA
4
-
7.5
4
-
7.5
4
-
7.5
V
-4
-
-7.5
-4
-
-7.5
-4
-
-7.5
V
Reference Voltage
VREF-VSS
NOTES:
Range of Voltage Reference Input
I
-1
-1
1. Full temperature range.
2.IIN=0.
3. Full temperature range, lOUT = 10 mA.
4. lOUT = 10 flA.
5. 10 Hz to 100 kHz.
6. 5 fls minimum positive pulse width and 0.5 fls minimum
negative pulse width.
7.
8.
9.
10.
11.
3-25
-1
IV
'" = IF =20 ns.
RL ;'2 kn.
Full temperature range, VIN -O.IV.
VIN=-O.IV.
liN connects the summing junction of an operational
amplifier. Voltage sources cannot be attached directly,
but must be buffered byextemal resistors.
=
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
_____________________ ________________ _
+5V
t~
I
6 1 GND
11
VDD
+5V
I
I
fOUTla
I
I
I
+5V
I
I
I
I
I
foui2110
COMP
IN
19
OUTPUT I
-2.5V
COMMON
~'"
TC9400
TC9401
TC9402
Vss
-------------------4
RBIAS
100 k!l
Figure 1
10 Hz to 10 kHz VIF Converter
VOLTAGE·TO·FREQUENCY (v/F)
CIRCUIT DESCRIPTION
At the end of the charging period, CREF is shorted out,
dissipating the stored reference charge, so when the output again crosses zero, the system is ready to recycle. In
this manner, the continued discharging of the integrating
capacitor by the input is balanced out by fixed charges from
the reference voltage. As the input voltage is increased,
the number of reference pulses required to maintain balance increases, causing the output frequency to also
increase. Since each charge increment is fixed, the increase
in frequency with voltage is near. In addition, the accuracy
of the output pulses does not directly affect the linearity of
the V/F. It must simply be long enough for full charge
transfer to take place.
The TC9400 VlF converter operates on the principal of
charge balancing. The input voltage (VIN) is converted to a
current (liN) by the input resistor. This current is then converted to a charge by the integrating capacitor and shows
up as lineariy decreasing voltage at the output of the op
amp. The zero crossing of the output is sensed by the
comparator causing the reference voltage to be applied to
the reference capacitor for a time period long enough to
virtually charge the capacitor to the reference voltage. This
action reduces the charge on the integrating capacitor by a
fixed amount (q = CREF x VREF), causing the op-amp output
to step up a finite amount.
3·26
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
u
~
TYP
"--__. . . i.
AMP
OUT
NOTES: 1. To adjust fMIN , set V IN = 10 mV and adjust the 50 k.Q offsetfor 10Hz output.
2. To adjustfMAX, set VIN = 10V and adjust RIN orVREF for 10 kHz output.
3. To increase fOUT MAX to 100 kHz, change CREF to 27 pF and CINT to 75 pF.
4. For high-performance applications, use high-stability components for RIN , C REF , VREF (metal film
resistors and glass capacitors). Also, separate output ground (pin 9) from input ground (pin 6).
Figure 2
Output Waveforms
Freq/2 Out
The TC9400 contains a "self-start" circuit to ensure the
V/F converter always operates properly when power is first
applied. In the event during "power-on" the op-amp output is
below comparator threshold, and CREF is already charged,
a positive voltage step will not occur. The op-amp output will
continue to decrease until it crosses the -2.SV threshold of
the "self-start" comparator. When this happens, a resistor is
connected to the op-amp input, causing the outputto quickly
go positive until the TC9400 is once again in its normal
operating mode.
The TC9400 utilizes both bipolar and MaS transistors
on the same substrate, taking advantage ofthe bestfeatures
of each. MaS transistors are used at the inputs to reduce
offset and bias currents. Bipolar transistors are used in the
op amp for high gain, and on all outputs for excellent current
driving capabilities, CMOS logic is used throughout to minimize power consumption.
This output is an open-collector bipolar transistor providing a square wave one-half the frequency of the pulse
frequency output. This output requires a pull-up resistor and
interfaces directly with MaS, CMOS, and TIL logic.
Output Common
The emitters of both the freq/2 out and the pulse freq out
are connected to this pin. An output level swing from the
collector voltage to ground or to the Vss supply may be
obtained by connecting to the appropriate point.
RBIAS
Specifications for the TC9400 are based on RSIAS =
100 kn ±1 0%, unless otherwise noted. RSIAS may be varied
between the range of 82 kn :,; RSIAS :,; 120 kn.
PIN FUNCTIONS
Amplifier Out
Comparator Input
The output stage of the operational amplifier. A negative-going ramp signal is available atthis pin in the VIF mode.
In the FN mode, a voltage proportional to the frequency
input is generated.
In the V/F mode, this input is connected to the amplifier
output (pin 12) and triggers the 3 Jls pulse delay when the
input voltage passes its threshold. In the FN mode, the input
frequency is applied to the comparator input.
Zero Adjust
Pulse Freq Out
The non inverting input of the operational amplifier. The
low-frequency set point is determined by adjusting the
voltage at this pin.
This output is an open-collector bipolar transistor providing a pulse waveform whose frequency is proportional to
the input voltage. This output requires a pull-up resistor and
interfaces directly with MaS, CMOS and TTL logic.
3-27
VOLTAGE-TO-FREQUENCYI
FREQUENCY..TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
Improved stability and linearity are obtained when
CINT :,; 4CREF. Low-leakage types are recommended,
although mica and ceramic devices can be used in applications where their temperature limits are not exceeded.
Locate as close as possible to pins 12 and 13.
The inverting input of the operational amplifier and the
summing junction when connected in the V/F mode. An
input current of 10 ~ is specified for nominal full scale, but
an overrange current up to 50 ~ can be used without
detrimental effect to the circuit operation.
CREF
The exact value is not critical and may be used to trim the
full-scale frequency (see "Input/Output Relationships"). Glass
film or air trimmer capacitors are recommended because of
their stability and low leakage. Locate as close as possible
to pins 5 and 3.
VREF
A reference voltage from either a precision source orthe
Vss supply may be applied to this pin. Accuracy will be
dependent on the voltage regulation and temperature characteristics of the circuitry.
The charging current for CREF is derived from the
internal circuitry and switched by the break-before-make
switch to this pin.
Voo. Vss
Power supplies of ±5V are recommended. For highaccuracy requirements, 0.05% line and load regulation and
0.1 ~F disc decoupling capacitors located near the pins are
recommended.
VlF CONVERTER DESIGN INFORMATION
Adjustment Procedure
Input/Output Relationships
Figure 1 shows a circuit for trimming the zero location.
Full scale may be trimmed by adjusting RIN, VREF, or CREF.
Recommended procedure for a 10kHz full-scale frequency
is as follows:
VREF
Out
The output frequency (fOUT) is related to the analog input
voltage (VIN) by the transfer equation:
Frequency out ;
~x
RIN
(1) Set VIN to 10 mV and trim the zero adjust circuit to
obtain a 10Hz output frequency.
1
fOUT.
(VREF) (CREF)
(2) Set VIN to 10V and trim either RIN, VREF, or CREF to
obtain a 10kHz output frequency.
External Component Selection
RIN
If adjustments ar performed in this order, there should be no
interaction and they should not have to be repeated.
The value of this component is chosen to give a fullscale input current of approximately 10 ~:
R
'" VIN Full Scale
IN 10~
.
SOO
10V
Example: RIN == - - ; 1 MQ.
\
10~
400
Note that the value is an approximation and the exact
relationship is defined by the transfer equation. In practice,
the value of RIN typically would be trimmed to obtain fullscale frequency at VIN full scale (see "Adjustment Procedure"). Metal film resistors with 1% tolerance or belter are
recommended for high-accuracy applications because of
their thermal stability and low-noise generation.
...
u.
~ 300
+
vss=~v
\
RIN=IMQ
VIN=+10V
TA= +2S"C
l\.
10kHz \
u:-
.s:
",
ll:i 200
.....
II:
(.)
100
CINT
The exact value is not critical but is related to CREF by
the relationship:
Voo= +SV
" _ 100kHz
o
-1
Figure 3
3-28
-2
-3
-4
VREF(V)
Recommended
~
-6
CREF va VREF
-7
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
V+
=BV TO 15V (AXED)
10kQ
> .......--':-IVREF
~'"
TC9400
VIN o-..JVV\.......----<~......~...., liN
OV-l0V
liN _
!.-r~"""4~--r:9:-1
100 kQ
V+
Rl
R2
10V 1 MQ 10kQ
l2V 14MQ 14 kQ
15V 2MQ 20kQ
Figure 4
Fixed Voltage - Single Supply Operation
V+= 10VTO 15V
10 kQ
~'"
t-=_-o
TC9400
VIN o - - ' V V ' v _ - - - _ - _ - , 3
OV-l0V
~;""TO:-""'T':4:"""'1~9
100
kQ
Figure 5
Variable Voltage - Single Supply Operation
3-29
fOU
r'2
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
y+ = 10Y TO 15Y
10 k,Q
14
B.2Y
2
F-+-.....O'OUT
R1
620k,Q
~'"
TC9400
100
k,Q
IGAIN ADJUSTI
0.01 11 F
Figure 6
I
Single Yariable Supply Yoltage With Offset and Gain Adjust
ELECTRICAL CHARACTERISTICS: VDD =+5V, Vss =-5V, VGND =0, VREF =-5V, RalAS =100 kn,
Full Scale = 10kHz, unless otherwise specified. TA =+25°0, unless temperature range is specified -40°C to +85°C for E
device, O°C to +70°C for C device.
FREQUENCY-TO-VOLTAGE
Parameter
Definition
Accuracy
Nonlinearity (Note 5)
Input Frequency
Range (Note 6)
Frequency Input
Positive Excursion
(Note 7)
Negative Excursion
(Note 7)
Minimum Positive
Pulse Width (Note 7)
Minimum Negative
Pulse Width (Note 7)
Input Impedance
Deviation From Ideal Transfer
Function as a Percentage
Full-Scale Voltage
Frequency Range for Specified
Nonlinearity
Voltage Required to Turn
Comparator On
Voltage Required to Turn
Comparator Off
Time Between Threshold
Crossings
Time Between Threshold
Crossings
Unit
0.Q1 0.02
0.02 0.05
0.05 0.25
% Full
Scale
10
100k
10
100k
10
100k
Hz
0.4
Voo
0.4
Voo
0.4
Voo
V
-0.4
-2
-0.4
-2
-0.4
-2
V
10
3-30
5
5
5
lIS
0.5
0.5
0.5
).Is
10
10
MW
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
ELECTRICAL CHARACTERISTICS (Cont.)
FREQUENCY-TO-VOLTAGE
Parameter
Definition
Analog Outputs
Output Voltage
(Note 8)
Output Loading
Voltage Range 01 Op Amp Output
for Specified Nonlinearity
Resistive Loading at Output 01
OpAmp
Voo-1
Voo-1
2
V
Voo-1
2
kW
2
Supply Current
100 Quiescent
E Device (Note 9)
C Device
Iss Quiescent
E Device (Note 10)
CDevice
Current Required From Positive
Supply During Operation
2
2
Current Required From Negative
Supply During Operation
Voo Supply
Operating Range of Positive Supply
Vss Supply
Operating Range of Negative Supply
-1.5
-1.5
4
-4
4
6
2
2
4
6
-4
-6
7.5
-7.5
-1.5
-1.5
-4
mA
-6
4
7.5
-4
-7.5
4
-4
3
10
mA
-3
-10
mA
mA
7.5
-7.5
V
V
Reference Voltage
Range of Voltage Reference Input
VREF-VSS
NOTES: 1. Full temperatura range.
2. IIN=O.
V
-1
7.
8.
9.
10.
11.
3. Full temperature range, lOUT = 10 mA.
4. lOUT = 10 ItA.
5. 10 Hz to 100 kHz.
6. 5 ~ minimum positive pulse width and 0.5 ~ minimum
negative pulse width.
FREQUENCY-TO-VOLTAGE (FN)
CIRCUIT DESCRIPTION
tR = tF = 20 ns.
RL 2:2 k!l.
Full temperature range, VIN = -{l.1 V.
VIN = -{l.IV.
l,N connects the summing junction of an operational
amplifier. Voltage sources cannot be attached directly,
but must be buffered byextemal resistors.
CINT can be increased to lowerlhe ripple. Values of 1 J!F
to 100 J!F are perfectly acceptable for low frequencies.
When the TC9400 is used in the single-supply mode,
VREF is defined as the voltage difference between pin 7 and
pin 2.
When used as an FIV converter, the TC9400 generates
an output voltage linearly proportional to the input frequency
waveform.
Each zero crossing at the comparator's input causes a
precise amount of charge (q = CREF x VREF) to be dispensed
into the op amp's summing junction. This charge in turn flows
through the feedback resistor, generating voltage pulses at
the output of the op amp. A capacitor (CINT) across RINT
averages these pulses into a DC voltage which is linearly
proportional to the input frequency.
Input Voltage Levels
The input signal must cross through zero in order to trip
the comparator. To overcome the hysteresis, the amplitude
must be greater than ±200 mY.
If only a unipolar input signal (fiN) is available, it is
recommended an offset circuit utilizing a resistor be used or
the signal be coupled in via a capacitor.
For 1 00 kHz maximum input, RINT should be decreased
to 100 kn.
FN CONVERTER DESIGN INFORMATION
Input/Output Relationships
The output voltage is related to the input frequency (fiN)
by the transfer equation:
VOUT = [VREF CREF RINT) fiN.
The response time to a change in fiN is equal to (RINT
CINT). The amount of ripple on VOUT is inversely proportional
to CINT and the input frequency.
NOTE: CREF should be increased for low fiN max. Adjust CREF so VouTis
approximately 2.SV to 3V for maximum input frequency. When fiN max is
less than 1 kHz, the duty cycle should be greater than 20% to ensure CREF
is fully charged and discharged.
3-31
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
v+
~'"
TC9400
TC9401
TC9402
COMP
fiN
o-..tt.,I..::.IN:.--I
.
- - --,
I
I
~VO~~~~------------------------------Ol~--~~F-~
CINT
tOOOpF
~--~~----~~~~---4--0VO
2 ZERO ADJUST
tOO k!l
~vo-~~------------------~------~
Figure 7 DC - to kHz FN Converter
Input Buffer
0·U;~1
fOUT and fOUT/2 are not used in the FN mode. However,
these outputs may be useful for some applications, such as
a buffer to feed additional circuitry. Then, fOUT will follow the
inputfrequency waveform, except that fOUT will go high 31ls
after fiN goes high; fOUT/2 will be squarewave with a frequency of one-half fOUT.
Ifthese outputs are not used, pins 8,9 and 10 may be
left floating or connected to ground.
INPUT
fOUT
~DELAY=3I1S
fouyl2!
Figure 8
r
r'"1. . . ; . . . . - - - : . . ._ _. . . .
FN Digital Outputs
3-32
VOLTAGE-TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
y+ = 10Y TO 15Y
14
.....--<_-_--=6'-1 GND
1i'"
10
kn
liN
t-=-~~---,
0.001
TC9400
pF
'~ >-_-'VV'v_ _.....-=2'-! ~~O
AMPOUT~~.....-~~O
11 COMP
IN
GND . - 6 " - - - - - - - 0
YO
')(\C
\..TV
100ka
6.2Y
NOTES: 1. The input is now referenced to 6.2V (pin 6). The input signal must therefore be restricted to be greater than 4V (pin 6, 2V)
and less than 10V to 15V (Voo).
If the signal is AC coupled, a l00kn to 10 Mn resistor must be placed between the inpul(pin 11) and ground (pin 6).
2. The output will now be referenced to pin 6 which is at 6.2V (Vi). For frequency meter applications, a 1 rnA meter with a
series-scaling resistor can be placed across pins 6 and 12.
Figure 9
FN Single Supply
The sawtooth ripple on the output of an FN can be
eliminated without affecting the F/v's response time by
using the circuit in Figure 10. The circuit has a DC gain of +1.
Any AC components (such as a ripple) are amplified positively via the lower path and negatively via the upper path.
When both paths have the same gain, AC ripple is cancelled.
The amount of cancellation is directly proportional to gain
matching. Ifthe two paths are matched within 10%, the ripple
will be lowered by 1/10. For 1% matching, the ripple is
lowered by 1/100. The 10 k.n potentiometer is used to make
the gain equal in both paths. This circuit is insensitive to
frequency changes and signal waveshape.
10ka
FN POWER-ON RESET
In FIV mode, the TC9400 output voltage will occasionally be at its maximum value when power is first applied. This
condition remains until the first pulse is applied to fiN. In most
frequency-measurement applications this is not a problem,
because proper operation begins as soon as the frequency
input is applied.
Figure 10 FN Ripple Eliminator
3-33
VOLTAGE,.TO-FREQUENCYI
FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400
TC9401
TC9402
In some cases, however, the TC9400 output must be
zero at power-on without a frequency input. In such cases,
a capacitor connected from pin 11 to VDD will usually be
sufficient to pulse the TC9400 and provide a power-on reset
(see Figure 11A). Where predictable power-on operation is
critical, a more complicated circuit, such as Figure 11 B, may
be required.
r---------~---oVDD
14
1000 pF
v
fIN 0---/'111 lill
'\r-.......__...._.-....:1,1 COMPARATOR
(AI
VDD
(B)
3
VCC
CLRA
100kn
~~
CD4538
vss
111FT
8
-=
-=
Figure 11
Power..()n OperationiResel
3-34
TC9400
Section 4
Sensor Products
Display AID Converters
Binary AJD Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
..
.,"'TELEDYNE
COMPONENTS
TC620
TC621
SOLID STATE TEMPERATURE SENSOR
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
The TC620 and TC621 are solid-state temperature
switches designed to replace mechanical switches in temperature sensing and control applications. Ambient temperature is sensed and compared to programmable temperature minimums and maximums.
Both devices provide a LOW LIMIT and HIGH LIMIT
logical output as well as a CONTROL output. On the TC620,
the LOW LIMIT is low when the measured temperature is
below the low temperature set-point and the HIGH LIMIT is
low when the measured temperature is below the high
temperature set-point. The TC621 provides the same output
functions except that the logical states are inverted. These
outputs allow for easy 'over' and 'under' temperature detection.
The CONTROL output provides a programmable hysteresis in that it goes high when the measured temperature
goes above the HIGH LIMIT set-point and returns to low
when the measured temperature goes below the LOW
LIMIT set-point. The CONTROL output of either device is
easily applied to a temperature control system.
±3°C Absolute Temperature Accuracy
2 kV ESD Protection on All Pins
Replaces Mechanical Thermostats and Switches
On-Chip Temperature Sense (TC620)
External Temperature Sense (TC621)
8-Pin DIP or SOIC for Direct PCB Mounting
2 User-Programmable Temperature Set Points
2 Independent Temperature Limit Outputs
Heat/Cool Regulate Output
APPLICATIONS
•
•
•
•
•
System Over-Temperature Shutdown
Advanced Thermal Warning
Fan Speed Control Circuits
Vibration-Immune Temperature Sensing
Accurate Appliance Temperature Sensing
FUNCTIONAL DIAGRAM
8
r1~----------+I"VCC
r--------------1~VCC
1.2V
REF
.,~
NC
.,~
TC621
TC620
1
THERMI~Ji'c~ -,-11--+-~
,>_......_1-'7 LOW LIMIT
LOW SET
_21--+-..-I
HIGH SET
_31-_..-1
HIGH SET
2
-+--H>-I
LOW SET
-+--_>-1
,>....+_1-'6 -LO-W-L-IM-IT
>-......+----11-6 HIGH UMIT
3
5
GND
4
CONTROL
GND
4
5
RLOWRHIGH
NOTE: LATCH Q is "C" (STANDARD)
LATCHQi. "H" (OPTION)
NOTE: LATCHQis "C" (STANDARD)
LATCH Q I. "H" (OPTION)
CONTROL
43691U F01
1111·1 (4369)
4·1
II
SOLID STATE
TEMPERATURE SENSOR
TC620
TC621
If power is applied to the device while the sensed
temperature is between the LOW SET temperature and the
HIGH SETtemperature, the LOW LIMIT output will go 'high'
('low' forthe TC621) and the CONTROL output will go 'high'.
The resistance value forthe TC620 can be determined
by inserting the desired trip temperature (T) into the following formulas:
Our proprietary technology provides excellent absolute
temperature accuracy (±3°C). The low current requirement
of these devices make them especially appealing in battery
powered applications. The TC620 and TC621 have no
moving parts so they are rugged and work well in equipment
that needs to take a lot of abuse. Automotive, marine and
industrial users will benefit from the ruggedness of these
devices.
The LOW LIMIT and HIGH LIMIT temperatures are set
by connecting the appropriate resistors to the LOW SET and
HIGH SET inputs. The value of these SET resistors are a
function of the temperature sensing element.
For Temperatures
below 70°C
Rtrip = 0.783 x T + 91
above 70°C
Rtrip = T + 77
Where Rtrip = Programming resistor value in k ohms
T = Desired trip temperature in degrees C
For example, to program the device to trip at 50°C,
the programming resistor would be:
Rtrip = 0.783 x 50 + 91 = 130.2 kil.
The TC621 can source or sink 10 mA per output. The
outputs of the TC620 can source or sink 1mA. If higher
currents are utilized in the TC620, the device will generate
internal heat, possibly causing erroneous temperature sensing.
Internal Temperature Sensor (TC620)
The TC620 incorporates an on-board positive-temperature-coefficient (PTC) thermal sensor which reacts to the
internal temperature of the die. The LOW SET resistor
(pin 2) should always be lower than the HIGH SET resistor
(pin 3) to insure proper operation.
External Temperature Sensor (TC621)
The TC621 performs the same function as the TC620
but employs a user supplied temperature sensing device.
The most common type of temperature sensor is a negativetemperature-coefficient (NTC) thermistor. An NTC sensor
requires that the input and output functions be reversed from
that of the TC620. This means that the HIGH SET resistor
(pin 2) should always be lower than the LOW SET resistor
(pin 3) to insure proper operation. See the applications
section of this data sheet for recommendations on selecting
the thermistor.
REGULATE ON ,
"H" OPTION: •
,
REGULATE ON
"C" OPTION
. ' REGULATE ON
: "H" OPTION
,
HIGH LIMIT ' - - - ' :
:
ON: ~I
HIGH'
I
V"
iZWUMITO~
,
SETPOINT
,
.!
:
DESIGN PARAMETERS
4369 ILL F02
The designer must be sure that the LOW SET programming resistor is smaller than the HIGH SET programming
resistor for the TC620 or that the LOW SET resistor is larger
than the HIGH SET resistor when using the TC621 with an
NTC external thermistor. No damage will be done tothe part
if this is not correct but the CONTROL output logic will be
effected.
The LOW LIMIT and HIGH LIMIT outputs will go to a
'high' state ('low' state for TC621) whenever the temperature of the device (or external thermistor) exceeds the
temperature programmed for the respective inputs.
The CONTROL output latch will go to a 'high' whenever
the sensed temperature exceeds the HIGH SET temperature and will go to a 'low' if the sensed temperature drops
below the LOW SET temperature. A bonding option may be
used to invert the CONTROL output logic for heating applications. The part number for this option has an 'H' instead of
a 'C' placed after the '620' or '621' digits.
TC6201621 Input VB. Output Logic
SOO
700
g 600
~ 500
~
400
~ 300
w
a: 200
~
'-i'
......
r"'--"""
r- I--
100
0345678910111213141516171819
SUPPLY VOLTAGE (VI
4369 III Faa
Output Resistance VB. Supply Voltage
4-2
SOLID STATE
TEMPERATURE SENSOR
TC620
TC621
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Power Dissipation
Plastic .................................................................... 1W
CerDIP ........................................................... 800 mW
Derating Factors
Plastic ........................................................... 8 mW/oC
CerDIP ....................................................... 6.4 mW/oC
Supply Voltage ............................................................ 20V
Input Voltage Any Input .............. (Gnd -0.3) to (VDD +0.3)
Operating Temperature
M Version .............................................. -55 to +125°C
E Version ................................................ -40 to +85°C
C Version ................................................... 0 to +70°C
Maximum Chip Temperature ................................. + 150°C
Storage Temperature .................................. -65 to +150°C
Lead Temperature (10 sec) ................................... +300°C
Part No.
Static-sensitive device. Unused devices must be stored in ccnductive
material. Protect devices from static discharge and static fields. Stresses
abcve those listed under 'Absclute Maximum Ratings' may cause pennanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absclute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Supply Vo~age
Supply Current
Output Resistance
Output Current 620
621
620
621
Output Current
Absolute Accuracy
[fi
a:
110
90
70
...... \.-'
I..---- I---"'"'
~
l"..-- ~
o
10
20
O°C to +70°C
-40°C to +85°C
O°Cto +70°C
-40°C to +85°C
-55°C to + 125°C
TC621CCOA
TC621CEOA
TC621CCPA
TC621CEPA
TC621CMJA
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
SOIC
SOIC
Plastic DIP
Plastic DIP
Ceramic DIP
O°Cto+ 70°C
-40°C to +85°C
O°Cto +70°C
-40°C to +85°C
-55°C to +125°C
TC620HCOA
TC620HEOA
TC620HCPA
TC620HEPA
TC620HMJA
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
SOIC
SOIC
Plastic DIP
Plastic DIP
Ceramic DIP
O°C to +70°C
-40°C to +85°C
O°C to +70°C
-4Q°C to +B5°C
-55°C to + 125°C
TC621 HCOA
TC621HEOA
TC621 HCPA
TC621HEPA
TC621HMJA
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
SOIC
SOIC
Plastic DIP
Plastic DIP
Ceramic DIP
O·Cto +70°C
-40°C to +85°C
O°Cto +70°C
-40°C to +85°C
-55°C to + 125°C
T-3
~
;!:130
SOIC
SOIC
Plastic DIP
Plastic DIP
Ceramic DIP
Typ
140
400
...... 1--"
190
~ 170
!!l
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
4.5
210
~ 150
TC620CCOA
TC620CEOA
TC620CCPA
TC620CEPA
TC620CMJA
Min
Output High or Low
Temp Sensed Source/Sink
Temp Sensed Source/Sink
CooVHeat
Source/Sink
CooVHeat
Source/Sink
T =Programmed Temperature
30 40 50 60 70 80 90 100 110 120 130
TEMPERATURE ("C)
0436SILL F04
TC620 Sense Resistors VB. Trip Temperature
4-3
Ambient
Temperature
Package
T
Max
Unit
18
200
1000
1
10
1
10
V
I1A
T+3
n
mA
mA
mA
mA
·C
SOLID STATE
TEMPERATURE SENSOR
TC620
TC621
TYPICAL APPLICATIONS
Dual Speed Temperature Control
speed cannot keep the temperature below the HIGH TEMP
set point. then the driver turns on continuously which increases the fan speed to high. The TC620 will monitor the
temperature and only allow the fan to operate when needed.
and at the required speed to maintain the desired temperature. A higher power option can be designed by adding a
resistor and a power MOSFET.
The Dual Speed Temperature Control adds features to
the basic controller by using the TC4469 quad driver. Two of
the drivers are configured in a simple oscillator. When the
temperature is below the LOW TEMP set point. the output of
the driver is off. When the temperature exceeds the LOW
TEMP set point. the TC4469 gates the oscillator signal to the
outputs ofthe driver. This square wave signal modulates the
remaining outputs and drives the motor at a low speed. Ifthis
+12V
8 0 •1 IIF ~
~ 10 II,...F_ _ _+
___---J\J1'\)M
VMOTOR
I
FAN MOTOR
I
I
1N4148
.--...1.;;..... 6
_-·"'.H,-........
r--------------,
I
I
I
I
l!~
______________
~
HIGHER POWER OPTION
TEMPERATURE SCALE
O"C - 30"C (FAN OFF)
7
3O"C - 5O"C (FAN I,.OW)
50"C - UP (FAN HIGH)
FAN MOTOR
4369 ILL F05
Temperature Controlled Fan
In the Temperature Controlled Fan schematic. a high
and a low temperature is selected by two 'set' resistors. The
TC620 then monitors the ambient temperature and will turn
on the FET switch when the temperature exceeds the HIGH
TEMP set point. The fan remains on until the temperature
decreases to the LOW TEMP set point. This provides the
hysteresis. In this application. the fan will not turn on unless
needed. This makes for a high-power fan control with only
four parts.
The TC621 uses an external themistor to monitor the
ambient temperature.
+12V
+12V
THERMISTOR
(NTC)
FAN MOTOR
..,'"
TC621
4369 III Foe
4-4
SOLID STATE
TEMPERATURE SENSOR
TC620
TC621
TYPICAL NTC THERMISTOR
USING THE TC621
The TC621 uses an external thermistor to monitor the
controlling temperature. A thermistor with a resistance value
of approximately 1OOkU at 25°C is recommended.
Typical thermistors exhibit a negative temperature coefficient (NTC) which must be considered when selecting the
set-point resistors. A temperature set-point is selected by
picking a resistor whose value is equal to the resistance of
the thermistor at the desired temperature.
A 30kU resistor between HIGH TEMP (pin 2)and VDD
(pin 8) will set the high temperature trip point at +50°C and
a 49kU resistor on LOW TEMP (pin 3) will set the low
temperature trip point to +40°C.
350
I
\
300
0
i
!
250
200
1
150
>-
100
J!
-""- 1"-..
"'
50
10
TYPICAL APPLICATIONS
20
-t---
30
...
r- r70
60
Temperature (OC)
4369 III F07
Solid State Thermostat
Typical Thermistor Resistance vs Temperature
The Solid State Thermostat diagram shows how the
TC620 can be used to control home, industrial and commercial heating and cooling applications in a low cost, simple
approach. The TC620 monitors the temperature and when
heating is required, turns on the FET swich. This applies
power to the gas valve and turns off the "standby" indicator.
The Nicad battery provides power to the circuit when the
FET is energized. 05 and R2 provide current limited power
to the circuit when the FET is off. This also keeps the Nicad
battery recharged. R3 and R4 set the desired hysteresis to
prevent rapid cycling of the heating or cooling equipment.
1N4002
1N4002
L
50
8K
1N4002
STANDBY
,- ,-
IV
22 }IF
-=- ~YCAD
2.2k
4369 III Faa
·-~SolidStateThermos~tat.
_ -
4.5VTO 18V
HIGH
TEMP
\\ ~~:p
WARNING
4369 III F09
TC620 Heating/Cooling Application
4-5
NOTES
4-6
"~TELEDYNE
COMPONENTS
TC626
SOLID-STATE TEMPERATURE SENSOR
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
The TC626 is a solid-state temperature sensor designed to replace mechanical switches in temperaturesensing applications. The ambient temperature is sensed
and compared to an internal programmed temperature. The
preset internal temperatures can be ordered in 5°C increments, from O°C to +125°C.
Our proprietary technology provides high, absolutetemperature accuracy (±3°C). Since there are no moving parts,
the TC626 is rugged and works well in harsh environments
that could damage and reduce the life of mechanical temperature sensors. Automotive and industrial users will benefit
from its immunity to vibration.
2 kV ESD Protection on All Pins
On-Chip Temperature Sensing
Replaces Mechanical Thermostats and Switches
TO-220 package for "Hot Spot" Mounting
TO-92 Package for Direct Circuit Board Mounting
±3°C Absolute Temperature Accuracy
10 mA Output Signal TO-92 Package
50 mA Output Signal TO-220 Package
APPLICATIONS
•
•
•
•
•
System Overtemperature Shutdown
Advanced Thermal Warning
Fan Speed Control Circuits
Vibration-Immune Temperature Sensing
Accurate Appliance Temperature Sensing
DESIGN PARAMETERS
The output will remain low until the internally programmedtemperature is reached. Thedevicethen switches
its output high. This output signal can source and sink up to
10 rnA (TO-92 package) and 50 rnA (TO-220 package).
The heat-sinking ability of the surface to which the
device is attached can permit higher power applications
since the internal heating of the device will be negligible
compared to the ambient temperature.
The hysteresis of the TC626 is 5 degrees at 20°C. At
higher temperatures, it increases.
SYSTEM OVERTEMPERATURE
PROTECTION
PIN CONFIGURATIONS
5VTO lav
TO-220
o
TO-92
SYSTEM POWER
123
1 = OUTPUT
=
1 2 3
2 VCC (CASE)
3= GROUND
NC = NORMALLY CLOSED
4368 ILL F01
1112-1 (4368)
4366 ILL F02
4-7
flRIEUM~NARV ~NfORMAT~ON
SOLID-STATE
TEMPERATURE SENSOR
TC626
ORDERING INFORMATION
Part Number"
TC626XXXCAB
TC626XXXEAB
TC626XXXVAB
TC626XXXCZB
TC626XXXEZB
TC626XXXVZB
Temperature
Range
Package
3-Pin TO-220
3-Pin TO-220
3-Pin TO-220
3-Pin TO-92
3-Pin TO-92
3-Pin TO-92
• xxx is temperature in 5°C increments, from 0 to +125°C (a 50°C part
would be TC626050CAB).
ELECTRICAL CHARACTERISTICS: VDD =+5V unless otherwise specified.
Parameter
Supply
Test Conditions
Vo~age
Min
Typ
Max
4.5
-
18
V
300
600
I1A
75
W
rnA
rnA
-
Supply Current
Output Resistance
Output High or Low
Output Current
Source/Sink, Vee
-
-
=18V
Source/Sink, Vee =4.5V
-
25
10
Units
Absolute Accuracy
T-3
T
T+3
·C
Differential
3.5
5
6.5
·C
Teledyne Components reserves the right to make changes in the circuitry or specifications detailed in this manual at any time without notice. Minimums
and maximums are guaranteed. All other specifications are intended as guidelines only. Teledyne Components assumes no responsibility for the use of
any circuits described herein and makes no representetions that they are free from patent infringement
SWITCHING LOGIC
/
Switching HystarealB
VB. Temperature
PROGRAMMED
TRIP~OINT
140
I
I
I
I
I
120 r--TURNON
••••• TURNOFF
:.....I------~
I
50r---~~---\~r----L--
!i:'00
40~-~~----~~---.--
II!
80
~
60
~
~ 40
..
~
~.,
.
~
:/-.'(..
'
lL.~ •
~
~~
20
SWITCHING HYSTERESIS
4388 ILL F03
4-8
4368 ILL F04
~"'TELEDYNE
COMPONENTS
TC675
TC676
FAST NiCAD/Ni-HYDRIDE BATTERY CHARGER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast Charge Cycle
Automatic Overcharge Protection
Fail Safe Fast Charge Shut-Off
Programmable MiniMax Ambient Limits
Selectable Charge Rate
Automatic Trickle Charge
Forced Trickle Charge (TC675)
Timer Reset Pin (TC676)
Safety Features
Temperature Controlled Shut-Off
Time Controlled Shut-Off
Dual Mode Automatic Shut-Off
Automatic Battery Insertion Detector
GENERAL DESCRIPTION
The TC675 and TC676 are designed for use with both
NiCad and NiHydride batteries. These two devices meet the
needs of the system designer whose battery charge applications require fast, reliable, and safe design.
The many automatic, programmable and selectable
features of these devices provide capabilities found only in
more expensive implementations. This, combined with inherent device capability of use in both AC or DC power
sources, provide a flexible cost-effective solution to battery
recharge maintenance.
FUNCTIONAL BLOCK DIAGRAM
V'N
Battery Powered Applications
-Power Tools
-Laptop/Notebook Computers
-Medical
-Emergency Lighting Systems
-Communications
-Cellular Phones/Mobile Radio
-Portable Instruments
-'-'-If-1......,....-t--+--t-+-- TO INTERNAL CIRCUITRY (Von>
BAT'"i~~?;TECT
>---¥- SCR DR'VE
....----'''--------If''.c.... ~:~~~y
.----~~ LED OUT
I+'H""AL""F...!TlI:.::'C::::K"'LE'--_ _ _-.
lOGIC
CONTROL I+F:..:U::::LL::..:Tc:.:R':::;CKo::L:::.E_ _- - ,
~
6
CLOCk IN
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _-+'1.::...2 lRICKLEIRESET*
-================::j-"13. . CHARGERATE
L ___________
• Tel75 'TRICKLE', "1' - TRICKLE-CHARGE
Te876 'RESET', 'o'-FAST..cHARGE
NOTE: PIN NUMBERS REFER TO 14-PIN DIP
4367 ILL F01
1113-1 (4367)
4-9
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
ORDERING INFORMATION
Part No.
TC675CPD
TC675EPD
TC675MJD
TC675COE
TC676CPD
TC676EPD
TC676MJD
TC676COE
Package
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin Ceramic DIP
16-Pin Plastic SOIC
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin Ceramic DIP
16-Pin Plastic SOIC
ABSOLUTE MAXIMUM RATINGS
Power Dissipation
Plastic .......................................................... 1000 mW
Ceramic ......................................................... 800 mW
Derating Factors
Plastic ........................................................... 8 mW/oC
Ceramic ..................................................... 6.4 mW/oC
Operating Temperature
M Version ......................................... -55°C to +125°C
E Version ........................................... -40°C to +85°C
C Version ............................................... O°C to +70°C
Storage Temperature ............................. -65°C to +150°C
Lead Temperature (10 sec) ................................... +300°C
Max Zener Current (liN) ........................................... 50 rnA
Operating
Temp Range
O°C to+70°C
-40°C to +85°C
-55°C to + 125°C
O°Cto +70°C
O°Cto +70°C
-40·C to +85°C
-55°C to +125°C
O°C to +70°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the Operational Specifications is not implied. Any
exposure to Absolute Maximum Rating Conditions may affect device
reliability.
OPERATIONAL SPECIFICATIONS: unless otherwise specified TA =+25°C; Is =6 triA.
Symbol
Supply
Is
Vz
Rz
Voo
100
Parameter
Condition
Supply Current
Zener Clamp Voltage
Zener Output Resistance
DC Input on VREG
Internal Circuit Current
(thru current limit resistor)
Iz=6mA
Iz= 10 rnA to 30 mA
VINOpen
Voo (VREG) = 5V
Regulated Output
VREG Output Resistance
IREG= 5 mA
IREG = 0 mA to 5 rnA
Min
Typ
Max
Unit
1
6
6
6.3
10
5
0.3
30
7
20
6
1
mA
V
4
-
Q
V
mA
Regulator
RREG
Switch Resistance (ros ON)
MAX Switch
RSWMAX
HIGH Switch
RSWHIGH
LOW Switch
RSWLOW
DELTA Switch
RSWOELTA
LED Drive
RSWLEO
Threshold Voltage Tolerance
MAX
OVMAX
213 VREG
HIGH
112 VREG
OVHIGH
LOW
1/3 VREG
OVLOW
DELTA
1/6 VREG
OVOELTA
TCliV
Threshold Voltage Temp Coefficient
V
Q
-
-
-
4-10
-
200
450
350
300
80
Q
-
±4
±4
±4
±4
±0.01
±10
±10
±10
±10
±0.1
%
%
%
Q
Q
Q
Q
%
%/oC
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
OPERATIONAL SPECIFICATIONS (Cant): unless otherwise specified TA = +25°C; Is = 6 rnA.
Symbol
Parameter
Condition
Min
Output
IOHG
IOLG
VOLL
SCR Gate Drive Source
SCR Gate Drive Sink
LED Low Output Vo~age
Digital Input
IILCR
IIHTR
IILBD
CHARGE RATE Pull-up Current
TRICKLE/RESET Pull-down Current
BATTERY DETECT Pull-up Current
lOLL = 10 rnA
Typ
-
-
-
-
-
5
3
-
Max
-
Unit
-
rnA
rnA
0.8
V
10
25
20
J.lA
J.lA
J.LA
ELECTRICAL CHARACTERISTICS: unless otherwise specified TA =Operating Temperature Range; Is =6 rnA.
Symbol
Supply
Is
Vz
Rz
Voo
100
Parameter
Condition
Min
Typ
Max
Unit
Supply Current
Zener Clamp Vokage
Zener Output Resistance
DC Input on VREG
Internal Circuit Current
(thru current limit resistor)
Iz= 6 rnA
Iz = 10 mA to 30 mA
VINOpen
Voo (VREG) = 5V
1.2
5.5
6
-
30
7.5
25
6
1.2
mA
V
Regulated Output
VREG Output Resistance
IREG = 0 rnA to 5 mA
IREG= 5 rnA
4
-
-
5
0.5
Q
V
mA
Regulator
RREG
Switch Resistance (ros ON)
MAXSw~ch
RSWMAX
HIGH Switch
RSWHIGH
LOW Switch
RSWLOW
DELTA Switch
RSWOELTA
LED Drive
RSWLEO
-
Threshold Voltage Tolerance
MAX
2/3 VREG
fNMAX
HIGH
1/2 VREG
IiVHIGH
LOW
IiVLOW
1/3 VREG
DELTA
1/6 VREG
IiVOELTA
Threshold Vokage Temp Coefficient
TCIiV
Output
IOHG
IOLG
VOLL
Digital Input
IILCR
hHTR
hLBD
SCR Gate Drive Source
SCR Gate Drive Sink
LED Low Output Voltage
V
-
lOLL = 10 mA
CHARGE RATE Pull-up Current
TRICKLE/RESET Pull-down Current
BATTERY DETECT Pull-up Current
4-11
-
260
510
410
360
100
Q
-
±10
±10
±10
±10
0.1
%
%
%
%
%/OC
-
-
-
-
-
5
3
-
Q
Q
Q
Q
rnA
rnA
1
V
15
35
25
J.lA
J.lA
J.LA
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
TIMER-COUNTER
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Charge Time Counter
(1.517 Hr @ 120 Hz)
-
655360
-
Counts
Delay Time Counter
(1.07 Min @ 120 Hz)
-
7680
DEVICE OPERATION
-
Counts
Time Control
(All pin numbers refer to the 14-pin dip package)
The TC675 and TC676 both use an on-board timercounter which limits the maximum duration of the fastcharge cycle to 1.5 hours (1.8 hrs @ 50 HzAC power). There
is also a time delay of 60 seconds (77 sec @ 50 Hz AC
power) before starting a fast-charge cycle. This delay gives
the battery temperature sensor time to stabilize.
The counters are clocked by the full-wave rectified AC
input. This clock rate is divided by 655,360 to time out the
1.517 hour (1.82 hrs @ 50 Hz AC power) maximum for the
fast-charge cycle. A faster or slower clock may be used to
modify the timing.
Temperature Control
Safety is critical in charging NiCadlNi-Hydride batteries
because a fast-charge applied under the wrong conditions
may cause severe damage to the battery and it's surroundings. The battery temperature is monitored by an
external thermistor and the controller will not allow the
battery to start a fast-charge cycle while the battery temperature is too hot or too cold. A NiCad/Ni-Hydride battery
tends to warm up during a fast-charge cycle so a temperature
that was too highto allow the charging to start may not be too
high to allow the charging to continue. Another temperature
threshold causes the charger to stop the fast-charge cycle
as soon as the battery temperature gets too high.
A charger may also be required to work in cold ambient
temperatures. The preprogrammed absolute maximum
charging temperature may be too high for these conditions
so a separate 'delta' temperature may be used. This will stop
the fast-charge cycle ifthe battery temperature exceeds the
ambient temperature by a predetermined amount. This
option requires a second thermistor to monitor the ambient
temperature.
Full-Charge or Half-Charge Option
Both the TC675 and TC676 have a half-charge selection option. The CHARGE RATE input has an internal pullup to select the full-charge mode (7/8 duty cycle). A low on
this pin will select the half-charge mode (7116 duty cycle).
This input may be selected or toggled anytime during a fastcharge cycle without effecting the time-out sequence.
Trickle-Charge
The trickle-charge mode of the TC675 and the TC676
runs at =7% ofthe fast-charge mode (1/16 duty cycle for fullcharge and 1/32 duty cycle for half-charge) and is the default
mode whenever the fast-charge cycle is not running.
PIN CONFIGURATIONS
14-Pin DIP
SCRDRIVE
3
BAT DETECT
4
.,~
CPD
EPD
EJD
MJD
16-Pin SOIC
VIN
VIN
CHARGE RATE
CHARGE RATE
TRICKLEIRESET
RDELTA
TRICKLEIRESET
SCR DRIVE
3
BAT DETECT
4
CLOCKIN
6
RDELTA
RHIGH
7
RLOW
RLOW
.,~
COE
EOE
NlC
NlC
RBAT
4367 ILL F02
4-12
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
TRICKLE/RESET (PIN 12)
normal-charge mode as default. A low on this pin will select
1/2 the current charge rate, i. e. if the charger is in full-charge
then a low on pin 13 will select 1/2 full-charge, if the charger
is in trickle-charge then 1/2 trickle-charge is selected .
The only difference between the TC675 and the TC676
is the operation of the input on pin 12.
On the TC675 (pin 12 = 'TRICKLE'), a high (Voo) on this
pin will hold the charger in the trickle-charge mode. The
internal timer will continue to count down. If the timer hasn't
timed out, the charger will go back to the full-charge mode
if this pin is returned to low (OV).
On the TC676 (pin 12 = 'RESET), low transition (Voo to
OV) on this pin will reset the timer and initialize a fast-charge
cycle.
LED OUTPUT (PIN 2)
This pin has a pull-down resistor to ground. With power
applied and no battery installed, and during the 1 minute
start delay, the transistor is on steady. The output will toggle
at a 3 Hz rate during a fast-charge cycle. The output will stay
on steady during the trickle-charge mode.
BATTERY SENSE (PIN 4)
CONTROL TEMPERATURE
This input is internally pulled up to about 1 volt. It is
designed to be capacitively coupled to the cathode of the
SCR (the positive terminal of the battery). Without a battery
present, the pulses from the full-wave rectified AC signal are
coupled by a bypass resistor around the SCR into the battery
input through the capacitor. This produces a zero-crossing
waveform at the battery pin which is interpreted as a 'no
battery' condition. The presence of a battery will prevent
these zero-crossings and the TC675rrC676 can begin a
charge sequence.
Some battery packs contain a diode in series with the
cells for safety purposes. This diode may prevent the battery
from clamping the waveform to prevent zero-crossings. The
auxiliary detect circuitry should be added to cause the diode,
if present, to forward bias, which will then clamp the waveform to prevent zero-crossings and will indicate the presence of the battery.
Each control temperature has a unique voltage threshold which is derived as a ratio of an internal, zener generated
reference voltage (VREG).
TMAX (fNMAX =2/3 VREG)
the charger will stop the fast-charge mode if the
battery temperature reaches this value.
THIGH (IIVHIGH = 1/2 VREG)
the charger will not start the fast-charge mode if the
battery temperature is above this value.
TLOW (fNLOW = 1/3 VREG)
the charger will not start the fast-charge mode if the
battery temperature is below this value.
TOELTA (OVOELTA = 1/6 VREG)
the charger will stop the fast-charge mode if the
battery temperature exceeds the ambient temperature by this value.
CLOCK IN (PIN 6)
THERMISTOR TEMPERATURE SENSOR
This input accepts the rectified AC signal and uses the
pulses to establish timing. The waveform must reach zero
volts during the pulse off time for accurate timing. Noise on
this line could cause false clock triggering which can be
prevented by placing a 0.01 IlF capacitor from pin 6 to
ground. This input is internally clamped to the Voo (Voo)
potential (z6V). A current limiting resistor must be used to
connect the rectified AC signal.
A common type of thermistor for this application is a
negative-temperature-coefficient (NTC) with a relatively high
resistance ratio. Some examplesofthis type are KC009-NO,
KC020-NO or RL1006-53 from Keystone.
Thermistor Characteristics
Thetransferfunction (Resistance vs. Temperature) of a
normal NTC thermistor takes the form:
In RT =Ao + A1rr + A2//2 = ... + AwrN (T in °Kelvin)
The first three terms ofthis equation are sufficientlo give
a fit of better than ±0.01 °C. The coefficients may be determined by setting up 3 simultaneous equations based on 3
known points.
The following calculations are based on a typical NTC
thermistor (Keystone RL1006-53.4K-140-01) with resistance values of 48.15 kOat40°C (313.15°K), 100 kOat25°C
(298.15 K) and 221.8 kO at 10°C (282.15°K).
SCR DRIVE (PIN 3)
A 1.5 kHz pulse is the output on this pin which turns on
the SCR during each cycle of the rectified AC waveform.
This signal should be capacitively coupled to the gate of the
SCR. A 0.01 IlF capacitor will effectively turn on the SCR
and block any DC component.
CHARGE RATE (PIN 13)
This input has an intemal pull-up which selects the
4-13
..
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
1st point:
In (48150)
=
2nd point:
In (100000)
= Ao + A1/298.15 + A:f298.152
3rd point:
In (221800)
=
RHIGH (pin 7):
THIGH = 30°C, 3VHIGH = 1/2, RBAT30 = 77.8k,
Ao + A1/313.15 + A:f313.152
RHIGH= RBAf.30 - RBAf.30 = 77.8k -77.8k = 77.8k
'iNHIGH
1/2
RLOW (pin 10):
TLOW = 20°C, 3VLOW = 1/3, RBAT20 = 129.4k,
Ao + A1/283.15 + A:f283.152
Solving these three equations for
Ao, A1 and A2 yields:
RT = In-1 {-5.825 + 5821/T - 194235fT2}
RLOW= RBAr20 - RBAr20 = 129.4k -129.4k = 268.8k
'iNLOW
1/3
ROELTA (PIN 11)
350
\
i300
~
\
250
I-
!I.! 200
III
1\
~150
o
Iii
100
ct
W
50
:i!
i!:
o
\
"'
o
10
20
"
30
r""40
roo
50
60
70
TEMPERATURE ("C)
SETTING UP THE
CONTROL TEMPERATURES
Assume an application which requires that the battery
charger not start while the battery temperature is below
20°C (TLOW) or above 30°C (THIGH). Also assume that the
battery should stop charging if it's temperature gets up to
either 40°C (TMAX) or 20°C {TDELTN above an ambient
temperature of 15°C (TAMB).
The control temperatures are programmed as a function
of the resistance value of the battery temperature thermistor
(RBATT) when it is at the temperature to be programmed (T)
and the threshold voltage ratio (3Vx).
The form of the equation to determine the values of
RLOW, RHIGH and RMAX is as follows:
A second thermistor can be used to modify the battery
temperature shutdown point as a function of the ambient
temperature. A 'delta' temperature may be set up to limit the
battery temperature to some value above ambient. This
value is called T DELTA and the ambient temperature that it
works against is called T AMB.
This control is very important for applications which are
required to work over a wide range of ambient temperatures.
Once a T DELTA value has been set up to work at some TAMB
then the T DELTA will change inversely proportional to TAMB.
This means that as the ambient temperature goes up, the
trip point goes upat an ever decreasing rate because T DELTA
goes down.
The form of the equation to determine the values of
RDELTA is different than the ones for the other temperature
control resistors because two thermistors are used. If the
same thermistor type is used for monitoring the ambient
temperature as is used to monitor the battery temperature
then the value of RDELTA, based on the above example, is
calculated thus:
T DELTA = 20°C, TAMB = 15°C,
TBAT = TAMB + TDELTA = 35°C, 3VDELTA = 1/6,
RDELTA = RBAT35 - RBAT35 - RAMB15 =
dJDELTA
61 k _ 61k -168.7k = 197.3k
1/6
50
~45
Rx=RBATT -RBATT
22
i'
ffi
~
I-
~
RMAX (pin 8):
T MAX = 40°C, 3VMAX = 2/3, RBAT40 = 48.1 k,
TSHUTDOWN
35
g
.!
RMAX= RBAT40 - RBAT40 =48.1k -48.1k = 24k
dJMAX
213
30
::l
iJi
'"
40
~
25
'"
19
~
18
17
'"
16
~
ct
~
ill
I-
T
"f'oii
I ~E~T~
IIII
15 ~
14 iil
13 c
12
10 12 14 16 18 20 22 24 26 28 30
AMBIENT TEMPERATURE ("C)
4-14
~
20~
r-.
~
'iNx
where RBATT is the resistance of the
battery thermistor at temperature T
connected to pin 9.
21
FAST NiCAD/Ni-HYDRIDE
BATTERY CHARGER
TC675
TC676
TYPICAL APPLICATION
..
fYY\
10k
2.2k
2.2k
14
LED
\\
VIN
2
271<
1~11'---+--i
AUXILIARY
BATIERY
DETECT
CIRCUITRY
1-
LED OUT
VREG
CLOCK IN
S
B
24.3k
RMAX
_~I~~~~T
~"
RESISTOR
(SEE NOTE)
r- --I
I
I
I
I
I
I
I
I
I
I
6
I
I
I
I
I
I
I
TC67S
TC676
SCR DRIVE
~47~F
RLOW
10
7
7B.7k
RHIGH
BATIERY DETECT
TAMB
100k
@2S"C
I
___
10~F JI
RDELTA
·r--'
CHARGE RATE
9
I
I
NICADor
I
I
:
Ni-HYDRIDE I _
BATTERY I - I
PACK
L_
RBAT
TBAT
+
274k
TRICKLEIRESET
11
137k
13
12
GND
100K@2S"C
• IF INTERNAL DIODE IS NOT PRESENT,
AUXILIARY BATIERY DETECT NOT NEEDED.
IMPORTANT NOTE: THE TC67S AND TC676 WILL MONITOR THE CHARGE nME AND THE BATIERY TEMPERATURE
BUT DOES NOT CONTROL THE CHARGING CURRENT. THE DESIGNER MUST LIMIT THE CHARGE CURRENT TO THE
BATTERY BASED ON THE APPROPRIATE RATE FOR THE TYPE AND NUMBER OF CELLS IN THE NICADINI-HYDRIDE
BATTERY TO BE CHARGED. EXCEEDING THE BATIERY MANUFACTURER'S MAXIMUM CHARGE CURRENT CAN
RESULT IN DEGRADED PERFORMANCE OR EVEN CATASTROPHIC FAILURE.
CHARGING CURRENT CAN BE LIMITED WITH A RESISTOR, AS SHOWN, OR BY MATCHING THE MAXIMUM TRANSFORMER OUTPUT CURRENT TO THE BATIERY CHARGING RATE.
43671u' F03
CHARGING NiCAD BATTERIES
FROM A DC SOURCE
by the presence of a battery such that it does not provide
zero-crossings on pin 6.
A SET/RESET latch may be controlled by the SCR
DRIVE output (pin 3) and the timing clock (pin 6) which can
then mediate the charge current to the battery.
DC voltage may be supplied directly to the internal
circuitry through pinS. Undertheseconditions, VREGbecomes
V DO and must be at least 4 volts and no greater than 6 volts.
The internal circuitry will take about 300 ~ (1 mA max) and
the VIN input (pin 14) should be left open.
The TC67S and TC676 are designed to control the
charging of NiCadlNi-Hydride batteries from a self-clocking,
self-commutating power source (full-wave rectified, unfiltered
50/60 Hz AC power). Some applications may require that
the NiCad be charged from a DC power source, i. e. batteryto-battery .
When a DC power source is used, the application must
provide clock pulse to CLOCK IN (pin 6) to control the timing
and a pulse train to BATTERY DETECT (pin 4) whenever a
battery is NOT present. This pulse train should be modified
4-15
NOTES
4-16
Section 5
Power Supply ControllCs
Display ND Converters
Binary ND Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control IC.
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
..
~"'TELEDYNE
COMPONENTS
TC170
CMOS CURRENT-MODE PWM CONTROLLER
FEATURES
•
Low Supply Current With
CMOS Technology ..•...............•............. 3.8 mA Max
Current-Mode Control
Internal Reference ....................................•........ 5.1V
Fast Rise/Fall Times (Cl = 1000 pF) ............... 50 ns
Dual Push-Pull Outputs
Direct-Power MOSFET Drive
High Totem-Pole Output Drive .................... 300 mA
Differential Current-Sense Amplifier
Programmable Current Limit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Soft-Start Operation
Double-Pulse Suppression
Undervoltage Lockout
..
Wide Supply Voltage Operation .............. 8V to 16V _
High Frequency Operation .......................... 200 kHz
Plastic and CerDIP Packages
Available with Low OFF State Outputs
Low Power, Pin-Compatible Replacement for
UC3846
BLOCK DIAGRAM
2
.-------------------------------------- ---------------------------1
VIN
1
15 1
1
1
TC170
Ro
.--..;.11:.::30 VDD
o-!!..l--r-----,
COU--:~
OUTPUT
A(IL)
______~
SYNCH~~------__~~~----------r_~--~~
(-)CURRENT
SENSE INPUT
(+)CURRENT
SENSE INPUT
OUTPUT
B(IL)
.......-+.:..::0 GROUND
COMP~~----~--~
_I
•
1
- - - - - ______ 1
(+)ERROR
AMP INPUT
(-)ERROR
AMP INPUT
t -....."-"---if-------+-----f------------....I -'-'0
1
1
1
1
CURRENT LlMITI
SOFT-START ADJUST
1
SHUTDOWN
COMPARATOR
1
1
1
116
!----4p-+-OSHUTDOWN
3S0mV
lOCK·UP
AMPLIFIER
_
350
mV
6kU
NOTE: Oulpuls low in
OFF slate.
1014--1
5·1
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
PIN CONFIGURATION
GENERAL DESCRIPTION
The TC170 brings low-power CMOS technology to the
current-mode-switching power supply controller market.
Maximum supply current is 3.B mAo Bipolar current-mode
control integrated circuits require five times more operating
current. Low power supply current eliminates auxiliary power
transformers. In off-line powering schemes, where a simple
zener diode circuit provides device supply voltage, power
dissipation is greatly reduced. CMOS technology decreases
system cost, increases power efficiency, reduces heat generation, and increases total system reliability.
The dual totem-pole CMOS outputs drive power
MOSFETs or bipolar transistors. The 50-ns typical output
rise and fall times, a 1000-pF capacitive loads, minimize
MOSFET power dissipation. Output peak current is 300 mAo
The TC170 contains a full array of system-protection
circuits. The undervoltage lockout circuit forces outputs
OFF if the supply voltage drops below 7V. A soft-start
feature is also available. The soft-start option forces the
PWM outputs to initially operate at a minimum duty cycle
and low peak output current. The TC170 can be directly
turned off through a remote-shutdown control pin. The
shutdown mode can be latched (power must be turned off
to restart system) or nonlatched. The soft-start feature can
also be used in system-shutdown applications. Doubleoutput pulse suppression guarantees output drive pulses
always alternate from one output driver to the other. Peak
current is user-adjustable.
Current-mode control lets users parallel power supply
modules. Two or more TC170 controllers can be slaved
together for parallel operation. Circuits can operate from a
master TC170 internal oscillator or an external system
oscillator.
The TC170 operates from an BV to 16V power supply.
An internal 2%, 5.1 V reference minimizes external component count. The TC170 is pin compatible with the Unit rode
UC18461284613846 bipolar controller.
Other advantages inherent in current-mode control include superior line and load regulation and automatic symmetry correction in push-pull converters.
CURRENT LlMITI
SOFT START
VREP>UT
(-) CURRENT-~~~~~
Part No.
Package
16-Pin Plastic DIP
16-Pin CerDIP
16-Pin CerDIP
16-Pin SO
16-Pin SO
16-Pin Plastic DIP
SHUTDOWN
3
(+) CURRENT-~~~~~
(+) ERROR AMP INPUT 5
(-) ERROR AMP INPUT 6
COMPENSATION
11 OUTPUT A
1
SYNCHRONIZATION
NOTE: Outputs low in 'OFF' state.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................................................ 18V
Output Voltage ................................................. V DD or 18V
Analog Inputs ....................................... -0.3V to Vs + 0.3V
Storage Temperature Range .................. ~5°C to + 150°C
Lead Temperature (Soldering, ·10 sec) .................. +300°C
Maximum Chip Temperature ................................... 150°C
CerDIP Package Thermal Resistance:
9JA (Junction to Ambient) .............................. 10SoC/W
9JC (Junction to Case) .................................... 60°C/W
Plastic Package Thermal Resistance:
9JA (Junction to Ambient) .............................. 140°C/W
9JC (Junction to Case) .................................... 70°C/W
Operating Temperature Range
Commercial ............................................ O°C to +70°C
Industrial ............................................ -2SoC to +85°C
Military .............................................. -55°C to + 125°C
Static-sensitive device. Unused devices must be stonld in conductive
material. Protect devices from static discharge and static fields. Stnlsses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These ani stnlSS ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections 01 the specifications is not
implied. Exposunl to Absolute Maximum Rating Conditions for
extended periods may affect device nlliability.
ORDERING INFORMATION
TC170CPE
TC170lJE
TC170MJE
TC170COE
TC170EOE
TC170EPE
1
Operating
Temperature
Range
O°C to +70°C
-25°C to +85°C
-5SoC to +12SoC
O°Cto +70°C
--40°C to +85°C
O°Cto +70°C
5-2
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
ELECTRICAL CHARACTERISTICS: VIN =16V. Ro =24 kn. Co =1 nF. TA =25°C. unless otherwise indicated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
5
5.1
5.3
V
5
15
mV
13
20
0.4
0.5
mV
mV/oC
Unit
Reference Voltage
VREF
Output Voltage
Line Regulation
Load Regulation
VRTC
Temperature Coefficient
=
=
lOUT 1 mA
VIN BVto 16V
lOUT = 1 mA to 10 mA
Over Operating Temperature Range
Oscillator
Oscillator Frequency
Voltage Stability
Temperature Stability
..
35
VIN = BVto 16V
Over Operating Temperature Range
42
46
kHz
1.1
1.5
"IoN
5
10
%
30
mV
Error Amplifier
Vos
Input Offset Voltage
IB
Input Bias Current
VCMRR
Common-Mode Input Voltage
VIN = BVto 16V
0
AVOL
BW
Open-Loop Vo~age Gain
VOUT=1Vt06V
70
1
Voo-2V
nA
V
dB
CMRR
Unity Gain Bandwidth
Common-Mode Rejection Ratio
VCMV OVto 14V
60
dB
PSRR
Power Supply Rejection Ratio
VIN= BVto 16V
60
dB
Amplifier Gain
Pin 3 = OVto 1.W
3
Maximum Differential Input Signal
VPIN4 - VPIN3
..
1.2
MHz
Current Sense Amplifier
Common-Mode Input Voltage
3.15
0
3.3
VN
S1.1
V
Vo0-3V
V
Current limit AdJust
IB
Current Limit Offset Voltage
V
Input Bias Current
nA
Shutdown Terminal
VTB
Threshold Vo~age
VIN
Input Vo~age Range
0.3
0.35
0
Minimum Latching Current at Pin 1
0.4
V
Voo
V
~A
125
Maximum Nonlatching Current at Pin 1
50
~A
Output Stage
Voo
Output Voltage
Pin 13
Output Low Level
ISINK= 20 mA
Voo
0.4
V
VOL
VOL
Output Low Level
ISINK = 100 mA
2
VOH
Output High Level
ISOURCE = 20 mA
Voo-1V
V
V
VOL
Output High Level
ISOURCE = 100 mA
Voo-4V
tR
Output Rise Time
CL=1000pF
50
150
ns
tF
Output Fall Time
CL= 1000 pF
50
150
ns
V
V
Undervoltage Lockout
Start-Up
Threshold
V
V
Threshold Hysteresis
Supply
2.7
Is Standby Supply Current
5-3
3.B
mA
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
Peak Current Limit Setup
The input pulse to pin 16 should be at least SOO ns wide
and have an amplitude of at least 1V in order to get the
minimum propagation delay from input to output. If these
parameters are met, the delay should be less than 600 ns at
2SoC; however, the delay time will increase as the device
temperature rises.
Resistors R1 and R2atthecurrent limit input (pin 1) set
the TC170 peak current limit (Figure 1). The potential at pin
1 is easily calculated:
V1=VREF
~
R1 + R2
Soft Restart From Shutdown
R1 should be selected first. The shutdown circuit feature is not latched for (VREF - 0.35)/R1 <50 I!A and is
latched for currents greater than 1251!A.
The error amplifier output voltage is clamped from
going above V1 through the limit buffer amplifier. Peak
current is sensed by RS and amplified by the current
amplifier which has a fixed gain of 3.15.
Ipcl, the peak current limit, is the current that causes
the PWM comparator noninverting input to exceed V1; the
potential at the inverting input. Once the comparator trip
point is exceeded, both outputs are disabled.
Ipcl is easily calculated:
Ipcl =
A soft restart can be programmed if nonlatched shutdown operation is used.
A capacitor at pin 1 will cause a gradual increase in
potential toward V1. When the voltage at pin 1 reaches
0.7SV, the PWM latch set input is removed and the circuit
establishes a regulated output voltage. The soft-start operation forces the PWM output drivers to initially operate with
minimum duty cycle and low peak currents.
Even if a soft start is not required, it is necessary to
insert a capacitor between pin 1 and ground if the current Il
is greater than 12SI!A. This capacitor will prevent "noise
triggering" of the latch, yet minimize the soft-start effect.
V1 -0.75V
3.15 (RS)
Soft-Start Power-Up
During power-up, a capacitor at R1, R2 initiates a softstart cycle. As the input voltage (pin 1S) exceeds the
undervoltage lockout potential (7.7V), 04 is turned off,
ending undervoltage lockout. Whenever the PWM comparator inverting input is below O.SV, both outputs are
disabled.
When the undervoltage lockout level is passed, the
capacitor begins to charge. The PWM duty cycle increases
until the operating output voltage is reached. Soft-start
operation forces the PWM output drivers to initially operate
with minimum duty cycle and low peak current.
where:
R2
V1 =VREF - - R1 + R2
VREF = Internal voltage reference = 5.1V
3.1S = Gain of current-sense amplifier
0.7SV = Current limit offset
Both driver outputs (pins 11 and 14) are OFF (low) when
the peak current limit is exceeded. When the sensed current
goes below Ipel, the circuit operates normally.
Current-Sense Amplifier
Output Shutdown
The current-sense amplifier operates at a fixed gain of
3.1S. Maximum differential input voltage (VPIN4-VPIN3) is
1.1 V. Common-mode input voltage range is OV to VIN - 3V.
Resistive-sensing methods are shown in Figure 2. In
Figure 2(A), a simple RC filter limits transient voltage spikes
at pin 4, caused by external output transistor-collector
capacitance. Transformer coupling (Figure 3) offers isol.ation and better power efficiency, but cost and compleXity
increase.
In orderto minimize the propagation delay from the input
to the current amplifier to the output terminals, the current
ramp should be in the order of 1 ~ in width (min). Typical
time delay values are in the 300 to 400 ns region at 2SoC.
The delay time increases with device temperature so that at
SO°C, the delay times may be increased by as much as
100 ns.
The TC170 outputs can be turned off quickly through
the shutdown input (pin 16). A signal greater than 350 mV
at pin 16 forces the shutdown comparator output high. The
PWM latch is held set, disabling the outputs.
02 is also turned on. If VREF/R1 is greater than 12SI!A,
positive feedback through the lock-up amplifier and 01
keeps the inverting PWM comparator inverting input below
0.7SV. 03 remains on even after the shutdown input signal
is removed, because of the positive feedback. The stat.e
can be cleared only through a power-up cycle. Outputs Will
be disabled whenever the potential at pin 1 is below O. 7SV.
The shutdown terminal gives a fast, direct way to disable the TC170 output transistors. System protection and
remote shutdown applications are possible.
5-4
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
SWITCH
CURRENT~
t
________________________________________________
~~I~O
______________
~
x 3.15 CURRENT-5ENSE
AMPLIFIER
11""---........-
---L-
S
~~RVOLTAGE
•
PWMLATCH
5.1V
LOCKOUT
2
R1
V1
R2
..,.
":"
16
350mV
6ke
~f"
TC170
Figure 1
R1 and R2 Set Maximum Peak Output Current
-4=
...---'V\~II
+
R'
4
RS
C
~f"TC170
'OPTIONAL RC ALTER ":"
(A) Ground Reference
(8) Above-Ground R_istive Sensing
Figure 2
R_I.tive Sensing
5-5
I
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
....-_ _ _....:9=-1 RO
..,~
TC170
8 Co
1i~TC170
MASTER
SYNC
10
COMP
7
..,~
1/2TC4427
Figure 3
Transformer Isolated Current Sense
V+
S
Undervoltage Lockout
The undervoltage lockout circuit forces the TC170 outputs OFF (low) if the supply voltage is below 7. 7V. Threshold
hysteresis is 0.75V and guarantees clean, jitter-free turn-on
and turn-off points. The hysteresis also reduces capacitive
filtering requirements at the PWM controller supply input
(pin 15).
2
vREF
9
RO
7
10
SYNC
COMP
..,~
TC170
8
Co
SLAVE
Circuit Synchronization
Current-mode-controlled power supplies can be operated in parallel with a common load. Paralleled converters
will equally share the load current. Voltage-mode controllers unequally share the load current, decreasing system
reliability.
Two or more TC170 controllers can be slaved together
for parallel operation. Circuits can operate from a master
TC170 internal oscillator with an external driver (Figure 4).
Devices can also be slaved to an external oscillator (Figure 5). Disable internal slave device oscillators by grounding
pin 8. Slave controllers derive an oscillator from the bidirectional synchronization output signal at pin 10.
Pin 10 is bidirectional in that it is intended to be both a
sync output and input. This is accomplished by making the
output driver "weak." This is advantageous in that it eliminates an additional pin from the package but does not
enable the device to directly drive another device. In order
to make it an effective driver, a buffer is required (Figure 4).
In order to use pin 10 as a sync input, it is necessary to
overcome the internal driver. This requires a pulse with an
amplitude equal to Vcc. Since Vcc must be above 8.25V
for the undervoltage lockout to be disabled, a CMOS or
open-collector TTL driver should be used.
Figure 4
Master/Slave Parallel Operation
Vs
15
..,~
TC170
9
15
'PULSE WIDTH OF
OSCILLATOR IS = TD
Figure 5
5-6
..,~
10 SYNC TC170
External Clock Synchronization
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
..
Figure 6
Oscillator Circuit
Oscillator Frequency and Output Dead Time
The oscillator frequency for Ro = 24 kO and
Co = 1000 pF is:
Fo=
[
1.27
RoCo -
50
_45
~40
2800 ]
Co
Ro2Co Co+150x1o-12
w
~35
C
Iii
where: Ro = Oscillator Resistor (0)
Co = Oscillator Capacitor (F)
Fo = Oscillator Frequency (Hz)
a:
~
20
:s 15
oJ
The oscillator resistor can range from 5 kn to 50 kn.
Oscillator capacitor can range from 250 pF to 1000 pF.
Figure 7 shows typical operation for various resistance and
capacitance values.
During transitions between the two outputs, simultaneous conduction is prevented. Oscillator fall time controls
the output off, or dead time (Figure 6).
Dead time is approximately:
iji
o
10
5
o
Figure 7
2000 [CoJ
TD = ---;:-::-;-
1-
30
iii
~25
,
l\\ 1.
l\1
\\ ~ ~
\ \
\ 1\ I\.
~
TA=+25'C_
, , '\
~~
I" ",
...... ~50PIF
~ ~ ...... ["00.", ......
f' t"--.
~
I
~ooojF ~50 PF
20 40 60 80 100 120 140 160 180 200
OSCILLATOR FREQUENCY (kHz)
Oscillator Frequency VB Oscillator Resistance
where: Ro = Oscillator Resistor (kn)
Co = Oscillator Capacitor (pF)
T D = Output Dead Time (sec)
(~~)
Maximum possible duty cycle is set by the dead time.
5-7
CMOS CURRENT-MODE
PWM CONTROLLER
TC170
TYPICAL CHARACTERISTIC CURVES
Output Rise and Fall Times
Output Rise and Fall Times
cl I
TA=+2S0
CLOAD = 500 pF
Vs= 16V
I
IJ
TA =+2SoC
C LOAD = 1800 pF
VS= 16V
I
.)
t
,
V
SV
DIV
~
BONDING DIAGRAM
NOTES: 1. Backside of die is common to Voo
2. Backside of die is not metallized
'r
/
t
r\
!\
SOns
~ DIV - r--
I'..
cl I
,
SV
DIV
\
Output Rise and Fall Times
I
t
"
\
./
V
,
SOns
DIV -
\
TA=+2S0
C LOAD = 1000 pF
Vs = 16V
V
~
SV
DIV
l-
"
SOns- r-Dly
I
5-8
~,,"TELEDYNE
COMPONENTS
TC172
TC173
BiCMOS CURRENT-MODE PWM CONTROLLER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TC1721173 are current-mode BiCMOS PWM controllCs. With a low 1.5 mA supply current along with the high
drive currents (1.2A typical), they provide a low-cost solution
for many PWM needs, since they can be driven without a 5060 Hz transformer and can directly drive MOSFETs up to
Hex 3 size.
The TC1721173 are based on the popular UC3842-type
architecture, but are improved to bring out more control
features to operate at higher frequency (1 MHz) and provide
more output drive power.
The TC1721173 add additional features. They come in
a 16-pin package. The additional pins allow more functions:
a linear timing ramp for the clock (instead of exponential),
user-adjustable undervoltage start and hysteresis level, as
well as separate output drive and control grounds. In addition, the TC1721173 provides a separate shutdown pin for
fast output shutdown, and an open-collector output pin that
pulls low when the user-adjusted undervoHage lockout
drops out.
•
•
Low Power BiCMOS Construction
Low Supply Current ............................... 1.S mA Typ
Wide Supply Voltage Operation •••••••.••.••. 8V to 18V
Latch-Up Immunity •••...••..•••.•.••• SOO mA on Outputs
Inputs Will Withstand Neg Inputs to -SV
High Output Drive •...••..•••.••.•..••..••...•••.•••.• 1.2A Peak
Current Mode Control
Fast Rise/Fall Times •••.•••.••••..••..••• 60 ns @ 1000 pF
High Frequency Operation ••.•••..•..•.•....•••.••••.•• 1 MHz
Clock Ramp Reset Current •••••••...•.•.•.• 2.S mA ±10%
Adjustable UV Lockout
Adjustable UV Hysteresis
Shutdown Pin Available
UV Lockout Pin Available .•...•.. 30V Open Collector
Duty Cycle Limited to •..•••••••.••.•.••.•.••.•..•..•....•••.. 99%
Soft-Start Duty Cycle Limit .......•........••...•......... 49%
Low Propagation Delay Current Amp
to Output ................................................. 140 ns Typ
Low Propagation Delay Shutdown
to Output •••.••••..•••.•.•..•••••••••.•••.••••..•.•...•....• 90 ns Typ
2kV ESD Protection
BLOCK DIAGRAM
VIN o-.:'~4_ _ _ _ _-.
GNO 0 .....' _ _ _,
'
28V
~
ClK
r~OUTPUT
VDD
UVHI~1~5_-----r::~:::1
UVlO~------t:~;:~
UV
~PWRGNO
:
:-- ---~-=:-O::-O::-=-:=-:.:;--,
I
_
I
ISENSE 0-:06_-C""'--I
I
0 Q
~..........----_fC
.....,r--"'lL~
_
TOGGLE USED ON
TSC173 ONLY
1.4V
3_ _ _-1
VFB 0-:0
COMPO-':------------~
SHUT ON 0,.;::5'--______________-1
4342 ILL F01
1015-1 (4342)
5
BiCMOS CURRENT-MODE
PWM CONTROLLER
TC172
TC173
PIN CONFIGURATION
ORDERING INFORMATION
Part No.
Package
TCl7*MJE
TC17"EOE
TC17"EPE
TC17"EJE
TC17"COE
TC17"CPA
16·Pin CerDIP
16-Pin SOIC Wide
16-Pin Plastic DIP
-55·C to + 125·C
-40·C to +85·C
-40·C to +85·C
Temperature
16-Pin CerDIP
16-Pin SOIC Wide
l6-Pin Plastic DIP
-40·C to +85·C
O~Cto +70·C
O·Cto +70·C
COMP
1
VDD
SHUTDN 5
OUT
GND
" The last digit defines the specific device:
172 - 99% duty cycle limit
173 - 49% duty cycle limit
9 OUTPUTGND
4342 ILL F02
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for:
-55°C :> T A :> 125°C for TC1721173MXX
-40°C ::; T A :> 85°C for TC1721173EXX
O°C :> TA :> 70°C for TC1721173CXX
Vee = 15V (Note 4); RT = 10 k.O; CT = 330 pF
TC1721173MXX
TC1721173EXX
Parameter
TC1721173CXX
Test Conditions
Min
Typ
Max
Min
Typ
Max
Units
4.95
5
±3
±5
5.05
±10
±15
4.9
5
±3
5.10
±10
Temperature Coefficient
TJ=25·C, 10=1 rnA
12 :> VIN :> 18V, 10 = 5 ~A
1 mA:>lo:>ll rnA
(Note 1)
±0.25
±0.5
±5
±0.25
±0.5
V
mV
mV
mV/·C
Total Output Variation
Line, Load, Temperature (Note 1)
4.9
Output Noise Voltage
10 Hz::;f:> 10 kHz, TA= 25·C
(Note 1)
TA = 125·C, 1000 Hrs. (Note 1)
Reference Section
Output Voltage
Line Regulation
Load Regulation
Long-Term Stability
5.1
4.82
100
5.18
V
~V
100
±0.5
Output Short Circuit
±15
±0.5
%
rnA
-20
-50
-100
-30
-50
-100
490
520
560
490
520
560
kHz
0.2
2
2.26
0.3
3
2.85
0.2
2
%N
2.65
0.3
3
2.85
±15
0.3
±50
2
mV
N/A
Oscillator Section
=25·C (Note 5)
Initial Accuracy
TJ
Voltage Coefficient
Temperature Coefficient
12::;Vcc::;18V
Amplitude
Maximum Frequency
T MIN:> TA::; T MAX (Note 1)
VPIN4 Peak-to-Peak
2.45
1
2.45
1
%I·C
V
MHz
Error Amp Section
Input Offset Voltage
Input Bias Current
VPINI = 2.5V
±15
0.3
±50
2
AVOL
2::;Vo::;4V
70
90
(Note 1)
650
90
750
70
Unity Gain Bandwidth
650
750
MHz
PSRR
12::;Vcc:>18V
80
100
80
100
dB
5-10
dB
BiCMOS CURRENT-MODE
PWM CONTROLLER
TC172
TC173
ELECTRICAL CHARACTERISTICS (Cant.)
TC1721173MXX
TC1721173EXX
Parameter
Test Conditions
Min
Output Sink Current
VPIN2= 2.7V, VPINI = 1.1V
1.2
Output Source Current
VouTHigh
VPIN2 = 2.3V, VPINI = 5V
VPIN2 = 2.3V, RL = 10K to Ground
3
5.8
VouTLow
Rise/Fall Response Time
VPIN2 = 2.7V, RL = 10K to Pin 8
(Note 1)
0.1
Typ
TC1721173CXX
Max
Min
Typ
Max
1.5
1.5
1.7
3.4
6
6.5
3.4
5.8
4.2
6.0
6.5
0.7
1.1
0.1
0.7
1.1
V
5
7
5
7
jJ.s
2.8
0.85
2.9
0.95
3.1
2.8
2.9
3.1
VN
1.05
0.85
0.95
1.05
70
80
70
80
Units
Error Amp Section (Cont.)
mA
mA
V
Current Sense Section
Gain Ratio
(Notes 2 and 3)
Maximum Input Signal
VPINI = 5V (Note 2)
PSRR
12 ~ Vcc ~ 18V (Note 2)
V
dB
Input Bias Current
±0.3
±2
±O.3
±2
N/A
Delay to Output
140
100
140
100
ns
n
n
Output Section
RDSON
ISINK=20 mA
7
15
7
15
RDSON
11
20
11
15
Rise Time
ISOURCE = 20 mA
CL = 1 nF (Note 1)
40
60
CL= 1 nF (Note 1)
30
60
40
35
Fall Time
30
40
ns
ns
Cross Conduction
CL= 0 nF
6.5
VooMaximum
Peak Output Current
Pin 12 (Note 1)
18
V
1.5
A
6.5
18
10,000 pF Load
1.1
1.2
1.5
1.1
1.2
nc
Undervoltage Lockout Section
Start Threshold
User Defined
8
18
8
18
V
Undervoltage Threshold
User Defined
8
18
8
18
V
100
100
mV
Minimum Shutdown Pulse Width
100
100
ns
Shutdown Delay
100
100
Undervoltage Indicator
Pulldown Voltage
Shutdown Section
Shutdown Threshold
1.5
1.5
ns
V
PWM Section
Maximum Duty Cycle
95
46
172
173
97
48
100
50
a
Minimum Duty Cycle
95
47
97
48
100
50
0
%
%
%
Total Standby Current
50
50
170
300
1.5
mA
2
4. Adjust Vee above the start threshold before setting at 15V.
5. Output frequency equals oscillator frequency for the TC172. Output
frequency is one-half oscillator frequency for the TC173.
Start-Up Current
Operating Supply Current
VPIN2 = VPIN3 = OV
NOTES: 1. These parameters, although guaranteed, are not 100%
tested in production.
2. Parameter measured at trip point of latch with VPIN2 = 0
3. Gain defined as:
aVPINl
A
= aVPIN3; 0 ~ VPIN3 ~ 0.8V
5-11
170
300
NOTES
5-12
~"'TELEDYNE
COMPONENTS
TC15C25
TC25C25
TC35C25
TC15C27
TC25C27
TC35C27
BiCMOS PWM CONTROLLERS
FEATURES
•
•
•
•
•
•
•
Low Power BiCMOS Construction
Low Supply Current .•............................. 1.0 mA Typ
Latch Up Immunity ...........•.... > SOO mA on Outputs
Below Rail Input Protection .•............................. -5V
High Output Drive .....•................•........ 500 mA Peak
Fast RiselFall Time ..........•............ so ns @ 1000 pF
High Frequency Operation .........•....... Up To 1 MHz
•
•
•
•
•
•
Tri-state Sync Pin For Easy Parallel Operation
Undervoltage Hysterisis Guaranteed
Shutdown Pin Available
Double Ended
Soft Start, With Small Cap
Low Prop Delay Shutdown
to Output ................................................. 140 ns Typ
FUNCTIONAL DIAGRAM
VREF
+VIN
12
SYNC
3
~
r~;;;;N~l-rlt::::::::!:r35_C"I25
15
GNO
RT
~-----------
16
6
5
~~
COMP
9
PWM
LATCH
IN-
RL.-_-'
+6V
IN+
50l'A
SO~ ~-----------1~~
START
10'--_ _...,
SHUTDOWN 0..:..:
1013-1
5·13
13
II 11 VOO
....-i-TOA
. .
BiCMOS PWM CONTROLLERS
TC15C25
TC25C25
TC35C25
TC15C27
TC25C27
TC35C27
GENERAL DESCRIPTION
REPLACING BIPOLAR VERSIONS WITH CMOS
The TC35C25 and TC35C27 family of PWM controllers
are CMOS implementations of the industry standard 3525
and 3527 voltage mode SMPS ICs.
. These second generation CMOS devices employ
Teledyne Components' Tough BiCMOSTM process for latchup proof operation. They offer much lower power consumption
than any of their previous CMOS or bipolar counterparts.
These controllers have separate supply pins for the
control and output sections of the circuit. This allows
'bootstrap' operation. The CMOS output stage allows the
output voltage to swing to within 25 mV of either rail.
Other improved features include tighter hysteresis and
undervoltage start-up specifications over temperature, and
very low input bias current on all inputs.
Although the pin-out and functions are the same for both
the Bipolarand CMOS versions, there are several differences
that need to be taken into account. The reference voltage on
the TC35C25/27 is 4V instead of 5V and the oscillator ramp
is 3V, not 4V. The RT and CT values are different for any
particular frequency and dead-time requirement.
The most important difference is that the absolute
maximum rating of the VDD and VIN voltages for the
TC35C25/27 is 18V, whereas the UC3525/27 is 40V.
OUTPUT SECTION
The output stage ofthe TC35C25/27 is comprised oftwo
pairs of complimentary CMOS drivers operating in a pushpull mode. Each output is capable of sinking or sourcing
nearly 500 rnA of peak current. They are also capable of
absorbing just as much 'kick-back' current without latching.
ORDERING INFORMATION
Part No.
Configuration
Pkg.JTemperature
TC15C25MJE
Non-Inverting
TC15C27MJE
Inverting
TC25C25EOE
Non-Inverting
TC25C25EPE
Non-Inverting
TC25C27EOE
Non-Inverting
TC25C27EPE
Inverting
TC35C25COE
Non-Inverting
TC35C25CPE
Non-Inverting
TC35C27COE
Inverting
TC35C27CPE
Inverting
16-Pin CerDIP
-55 to + 125°C
16-Pin CerDlP
-55 to + 125°C
16-Pin SOIC (wide)
-40 to +85°C
16-Pin Plastic DIP
-40 to +85°C
16-Pin SOIC (wide)
-40 to +85°C
16-Pin Plastic DIP
-40 to +85°C
16-Pin SOIC (wide)
Oto +70°C
16-Pin Plastic DIP
o to +70°C
16-Pin SOIC (wide)
o to +70°C
16-Pin Plastic DIP
Oto +70°C
SOFT START
A soft restart recovery rate may be selected by placing
a capacitor from SOFT START (pin 8) to ground. The
calculation for the recovery timing is approximately
60 mslJ.1F.
.
SOFT START will mediate the start-up from undervoltage
recovery, power-on or SHUTDOWN.
SHUTDOWN
There is a minimum delay, non-latching shutdown feature
on the TC35C25/27 PWM controller. Both outputs may be
turned off by applying a positive voltage to SHUTDOWN (pin
10). Returning the pin back to ground will reinitialize the soft
start cycle.
OSCILLATOR SECTION
A tri-state feature has been added to accommodate
systems which require multiple controllers to be run in a
'master/slave' configuration. The timing resistor pin (RT, pin 6)
may be tied to VREF to place the sync pin (SYNC, pin 3) in a
high impedance state. This will allow the chip to be clocked
from an external source.
The sync output (OSC OUT, pin 4) of the TC35C25 can
drive several sync inputs configured in this manner.
5·14
BiCMOS PWM CONTROLLERS
TC15C25
TC25C25
TC35C25
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
15C2X ....................................... -55CO::; TA::; +125°C
25C2X ......................................... -40CO::; TA::; +85°C
35C2X ............................................. 0Co::; TA::; +70°C
Supply Voltage ............................................................ 18V
Maximum Chip Temperature ................................... 150°C
Storage Temperature ............................. --ti5°C to +150°C
Lead Temperature (10 sec) ..................................... 300°C
Package Thermal Resistance
CerDip ReJ-A ................................................. 150°CIW
CerDip ReJ-c ................................................... 55° CIW
PDIP ReJ-A .................................................... 125°CIW
PDIP ReJ-c ...................................................... 45°CIW
SOIC ReJ-A .................................................... 25O°CIW
SOIC ReJ-c ...................................................... 75°CIW
ELECTRICAL CHARACTERISTICS:
TC15C27
TC25C27
TC35C27
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from stetic discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
unless otherwise specified VIN = Voo = 16V, TA = 25°C, RT = 3.7 kf.!,
Ro = 760n, CT = 1000 pF; (See test circuit).
Parameter
Conditions
Min
Typ
Max
Units
10=1 mA
VIN = 8 to 18V, (note 2)
Ii = 1 to 12 mA, (note 2)
(notes 1, 2)
Worst Case, (note 2)
(note 1)
3.95
4
±4
±4
±0.01
4
±50
40
21
4.05
±10
±15
±0.4
4.15
V
mV
mV
mV/·C
V
mV/l000 Hrs
rnA
±2
±0.01
±3
±0.1
%
±0.025
3.2
50
5.5
170
2.2
±0.06
3.4
60
6.7
200
2.8
%rc
-
Reference Section
Output Vottage
Line Regulation
Load Regulation
Temperature Coefficient
VREF
Long Term Drift
Short Circuit Current
Output Noise
-
3.85
-
VREF to GND (note 2)
10Hz ~ f ~ 10kHz, (note 1)
20
-
70
Il VRMS
Oscillator
Initial Accuracy
Vottage Coefficient
Temperature Coefficient
@
Osc Ramp Amplitude
Reset Switch RDS (ON)
Clock Amplitude
Clock Min Width
Sync Threshold
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Gain Bandwidth Product
Output Low Level
Output High Level
CMRR
-
(note 2)
2.9
35
4.9
fDSC = 100 kHz, RL = 1Mn, (notes 1, 2)
Ro = on, (note 1) Cr= 100 pF, Rr= ln
Rr pin tied to VREF, Cr pin at GND,
(note 2)
Sync Vottage = 4V, V(Rr) = 4V (note 2
Sync Amplitude = 5V, (note 1)
Sync Input Current
Min Sync Pulse Width
MaxOsc Freq
Error Amplifier (VCM
-
97 kHz
VIN = 8 to 18V, (note 2)
(notes 1, 2)
1.8
-
130
±1
175
Rr= 1 kn, Cr= 100 pF, Ro= on,
(note 1)
1.0
-
-
(note 2)
-
±15
±200
±100
RL = 100 kn, (note 2)
(note 1, 2)
RL = 100 kn (N Channel), (note 2)
RL = 100 kn (NPN), (note 2)
VCM = 0.5 to 4.7V, (note 2)
70
0.7
±5
±50
±25
85
0.9
10
5.4
75
%N
V
n
V
ns
V
Il A
ns
MHz
= 2.5V)
5-15
4.9
60
1.2
20
5.9
mV
pA
pA
dB
MHz
mV
V
-
dB
-
-
BiCMOS PWM CONTROLLERS
TC15C25
TC25C25
TC35C25
TC15C27
TC25C27
TC35C27
ELECTRICAL CHARACTERISTICS (Cont): unless otherwise specified VIN = Voo = 16V, TA = 25°C,
RT = 3.7 kn, Ro = 7600, CT = 1000 pF; (See test circuit).
Parameter
Conditions
Min
Typ
90
120
Max
Units
Error Amplifier (VCM = 2.5V) (Cont )
=8 to 18V, (note 2)
=
=
=
-
Supply Vo~age Rejection
VIN
Slew Rate
CLOAO 50 pF, ACL 1
V(EA+) 1V to 3V Pulse, (notes 1,2)
-
1
Min Duty Cycle
(note 1)
-
-
0
%
Max Duty Cycle
losc = 100 kHz, (note 1)
45
49
-
%
Input Threshold
V(CT) = 0.6V, (note 2)
0.5
0.6
0.7
V
Input Threshold
V(CT) = 3.6V, (note 2)
3.4
3.6
3.7
V
Input Bias Current
(note 1)
-
-
±1
JJ.A
Soft Start Current
VSHUTDOWN = OV, (note 2)
30
46
75
VSHUTDOWN = 3V, (note 2)
-
JJ.A
Soft Start Vo~age
30
100
mV
Shutdown Input Current
VSHUTDOWN = 3V, (note 2)
±1
±100
nA
Min Shutdown Pulse Width
VSHUTOOWN = 5V Pulse, (notes 1, 2)
-
20
40
ns
Shutdown Delay
VSHUTOOWN = 5V Pulse, (notes 1, 2)
130
140
220
ns
1.5
2.4
3
V
dB
V/Jl.S
PWM Comparator
Soft Start Section
Shutdown Threshold
Output Drivers (each output) (note 2)
ISINK = 20 mA (note 2)
Output High Level Ros (ON)
ISOURCE = 20 mA (note 2)
Rise Time
CL = 1 nF, (notes 1,2)
Fall Time
CL = 1 nF, (notes 1, 2)
Power Supply
-
Output Low Level Ros (ON)
-
13
25
Q
20
35
Q
55
80
ns
40
65
ns
Supply Current
losc = 100 kHz (See Test Circuit)
-
1
1.6
mA
UV Lockout Threshold
(note 2)
6.6
7
7.3
V
UV Lockout Hysteresis
(note 2)
1.7
2.2
2.5
V
Start-Up Current
(note 2)
-
75
200
JJ.A
NOTES: 1. Nottested.
2. Guaranteed over operating temperature range.
Teledyne Components reserves the right to make changes in the circuitry or speCifications detailed in this manual at any time without notice. Minimums
and maximums are guaranteed. All other specifications are intended as guidelines only. Teledyne Components assumes no responsibility for the use of
any circuits described herein and makes no representations that they are free lrom patent infringement.
5-16
BiCMOS PWM CONTROLLERS
TC15C25
TC25C25
TC35C25
TC15C27
TC25C27
TC35C27
PIN CONFIGURATIONS
16-Pin DIP
OSCOUT
4
16-Pin SOIC
VREF
VREF
Vi;'
vi;'
OUTPUTB
"'' '
TC15C2S127
TC25C2S127
TC35C25127
OSCOUT
VOO
"'' '
TC15C25127
TC25C25127
TC35C25127
4
GND
DISCHARGE
7
a
VOO
GNO
OUTPUT A
OUTPUT A
SOFT START
OUTPUTB
SHUTDOWN
DISCHARGE
7
SOFT START
a
SHUTDOWN
TYPICAL CHARACTERISTIC CURVES
Oscillator Frequency
vs. Ctand Rt
Dead Time
vs. Ct and Discharge Resistor
3000
Supply Current
vs. Frequency
r-.-r-,-,-.-,--.--.-.,
~or----.----.----'----,
BOO
VOO = VIN • 16V, TA +25"C
35
700 I--"r--t-----+---y
_ 600
~
30
"---"\d--------,Y"-.-r
~25
~500~~-r~~~~
~4001----~~~~~~
o
... 300
F""';;;;::;;;;f7""'~;;;:::t-::=-,
.§. 20
0
£1 15
VOo= 16V, TA +25"C
CL
2500
=2200 pF,-t--t--t+if---1f--l
CL=1~pF~~~~~-1
~,--t-~,--t--t--:l
VOO = 16V, TA +25"C, Rl = 10k
Ct = 1000 pF
!2000
w
1500
Ct =500 pF
!
r-~~~~~F-~ ~~ 1000 I--+-+---:'~+-+':~"+"~""F-l
200b-~~~~+-----t--~~
100~:a~.
?zoo 400
BOO
600
Cl (pF)
1000
°0L.::...'-0L...2....L..-0.L..4....L......J0.L...6....JL.......J0.L...a....JL.....J
FREQUENCY (MHz)
5-17
1000
NOTES
5-18
~"'TELEDYNE
COMPONENTS
TC18C4213/4/5
TC28C4213/4/5
TC38C4213/4/5
BiCMOS CURRENT MODE PWM CONTROLLER
FEATURES
•
•
•
•
•
•
•
Low Power BiCMOS Design
Tough CMOSTM Construction
Low Supply Current ••••..•••••• 1.0 mA Typ @ 100 kHz
Wide Supply Voltage Operation •...•••.•.•••• 8V to 18V
Latch-Up Immunity ••.••..•...••..••.. 500 mA on Outputs
Input Will Withstand Negative Inputs to -5 Volts
High Output Drive .•.•...••..•........•...•...•...•... 0.7A Peak
(1.2A on 14 and 16-Pin Versions)
•
•
•
•
•
•
•
2 kV ESD Protection
Current Mode Control
Fast RiselFall Time (Max) ••.••••.•••..• 60 ns @ 1000 pf
High Frequency Operation ............••...••..•.•.• 300 kHz
Clock Ramp Reset Current ................ 2.5 mA ±10%
Low Propagation Delay Current Amp
to Output ................................................. 140 ns Typ
Pin Compatible with UC3842f38431384413845
BLOCK DIAGRAM
ClK
~VDD
UNDER VOLTAGE
SECTION
ANALOG
GND
~OUTPUT
UVGOOD
0--------.
9
1--41-----.....,
}o
POWER
GROUND
PWM COMPARATOR
_
ERROR AMP
50"10 DUTY CYCLE
TOGGLE
(TC38C44 AND
TC38C45 ONLY)
LIMIT BUFFER
1.4V
2.5V
VFB03- - - - I
COMPo------~
PIN NUMBERS FOR
14-PIN DIP
1016-1
5-19
5
BiCMOS CURRENT MODE
PWM CONTROLLER
TC18C42131415
TC28C4213/4/5
TC38C4213/4/5
GENERAL DESCRIPTION
The TC3SC42131415 are current mode BiCMOS PWM
controllCs. With a low 1.0 rnA supply current along with the
high drive currents (0.7A peak) they provide a low cost
solution for a PWM that operates to 300 kHz and directly
drives MOSFETs up to HEX 3 size.
Performance of the oscillator and current sense amplifier have been greatly improved over previous bipolar versions. Voltage and temperature stability have been improved by a factor of 3. Noise immunity (PSRR) has also
been improved. These improvements make for a more
reliable power system.
Tough CMOSTM design and construction provide input
and output latch protection, outstanding ESD tolerance, and
high reliability manufacturing techniques and materials.
Tough CMOSTM means high reliability.
The TC3SC421314/5 are pin compatible with earlier
bipolar versions so that designers can easily update older
designs. Improvements have been added though. For example, clock ramp reset current is specified at 2.5 rnA
(±10%) for accurate deadtime control. A few component
values must be changed (RT & CT) to use TC3SC42 family
in existing bipolar designs:
The 14-pin DIP and 16-pin SO versions have separate
and internally isolated grounds, and are rated for higher
output current (1.2A). These separate grounds allow for
'bootstrap' operation of the PWM to further improve efficiency.
ramp amplitude to increase with frequency due to comparator delay. Minimum values for CT and RT are 33 pF and 1 kn
respectively. Maximum values are dependent on leakage
currents in the capacitor, not on the input currents to the
RT/CTpin.
Frequency of Operation
The frequency of oscillation for the TC3SC4X family is
controlled by a resistor to VREF (RT) and a capacitor to ground
(CT). VREF supplies current through the resistor and charges
the capacitor until its voltage reaches the threshold of the
upper comparator (",2.5V). A 2.5 rnA current is then applied
to the capacitor to discharge it to near ground (=O.15V). The
discharge current is then shut off and the cycle repeats. An
approximate equation for the frequency of operation is:
to '" _1_
(RT in Ohms and CT in Farads)
RTCT
The value of RT affects the discharge current and the
upper and lower comparators each have delay. As RT gets
smaller and as the frequency of operation gets higher, the
above equation falls apart. Figure 5 illustrates this effect.
Dead Time
The value of RT has a effect on the discharge rate but the
primary consideration is the value of CT. The time required
to discharge the capacitor is approximately 1000 CT.
ORDERING INFORMATION
REFERENCE SECTION
The reference is a zener based design with a buffer
amplifier to drive the output. It is unstable with capacitances
between O.OlIlF and 3.3IlF. In a normal application a 4. 71lF
is used. In some lower noise layouts the capacitor can be
eliminated entirely.
The reference is active as soon as the 3SC4X has
power supplied. This is different than its bipolar counterparts, in that the bipolar reference comes on only after the IC
has come out of its under voltage mode. Thus, on the
3SC4X, the reference pin can not be used as a reset function
such as on a soft start circuit.
Part No.
TC1SC··MJA
TC1SC**MJD
TC2SC·*EJA
TC2SC·*EJD
TC2SC**EOE
TC2SC·*EPA
TC2SC·*EPD
TC3SC**COE
TC3SC·*CPA
TC3SC**CPD
OSCILLATOR SECTION
Package
S-pin CerDlP
14-pin CerDIP
a-pin CerDlP
14-pin CerDIP
16-pin SOIC Wide
S-pin Plastic DIP
14-pin Plastic
16-pin SOIC Wide
a-pin Plastic DIP
14-pinPlastic
T"mperature
-55°C to +125°C
-55°C to + 125°C
-40°C to +S5°C
-40°C to +S5°C
-40°C to +S5°C
-40°C to +S5°C
-40°C to +S5°C
O°Cto +70°C
O°Cto +70°C
O°Cto +70°C
Duty Cycle Limitation
The osc;illator frequency is set by the combination of a
resistor from the reference to the RT/CT pin and by a capacitor from this pin to ground. The oscillator is designed to
have ramp amplitude from 0.15 to 2.5 volts. This is approximate, as over shoot on the oscillator comparator causes the
Start-up Voltage
14.5 V
S.4 V
5-20
99%
49%
XSC42
XSC43
XaC44
XSC45
BiCMOS CURRENT MODE
PWM CONTROLLER
TC18C4213/4/5
TC28C4213/4/5
TC38C4213/4/5
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATIONS
Supply Voltage ............................................................ 18V
Maximum Chip Temperature ................................... 150°C
Storage Temperature ............................. -{)5°C to +150°C
Lead Temperature (10 sec) ................................... +300°C
Package Thermal Resistance
CerDip ReJ-A ................................................. 150°C/W
CerDip ReJ-c ................................................... 55°CIW
PDIP ReJ-A .................................................... 125°C/W
PDIP ReJ-c ...................................................... 45°C/W
SOIC ReJ-A .................................................... 250°CIW
SOIC ReJ-c ...................................................... 75°C/W
Operating Temperature
18C4X .......................................-55C°!> TA!> +125°C
28C4X ......................................... -40C°!> TA!> +85°C
38C4X ............................................. OC°!> TA!> +70°C
S·Pin DIP
"'"
CPA
EJA
EPA
MJA
14-Pin DIP
VREF
NC
"'"
VIN
CPO
EPO
EJO
MJO
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
pennanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
VOO
OUTPUT
8
POWERGNO
Package Power Dissipation
16·Pin SO
NC
VREF
VIN
"'"
COE
EOE
VOO
OUTPUT
GNO
POWERGNO
50
75
100
125
AMBIENT TEMPERATURE (OC)
5-21
150
BiCMOS CURRENT MODE
PWM CONTROLLER
TC18C4213/4/5
TC28C4213/4/5
TC38C4213/4/5
ELECTRICAL CHARACTERISTICS: unless otherwise stated, these specifications apply over specified
temperature range. VIN = Voo = 15V; RT = 71 kQ; CT = 150 pF
TC18C4X
TC28C4X
Parameter
I Typ I
TC38C4X
Test Conditions
Min
Output Voltage
TA= 25°C,lo= 1 mA
4.95
Line Regulation
9.5V S VINS 15V, 10 = 1 rnA
Load Regulation
lmAslosl1 rnA
-
±5
±15
Temp Stability
(note 1)
-
±0.25
±0.5
Output Noise Voltage
10 Hz sf S 10 kHz,TA= 25°C (note 1)
Long Term Stability
TA= 125°C, 1000 Hrs. (note 1)
-
±0.5
I Typ I
Max
Units
4.90
5
5.10
V
-
±3
±10
mV
±3
±10
±0.25
±0.5
mV
mV/oC
-30
-50
Max
Min
5
5.05
±3
±10
Reference Section
-20
Output Short Circuit
100
-50
-100
100
±0.5
-100
I1V(rms)
%
mA
Oscillator Section
Initial Accuracy
TA= 25°C (note 4)
95
100
105
95
100
105
kHz
Voltage Stability
-
±0.2
±0.3
±0.3
%
±0.01
±0.05
-
±0.2
Temp Stability
9.5V" VIN" 15V
TMIN" TA S TMAX (note 1); Figure 2
±0.01
±0.03
%/OC
Clock Ramp Reset
RT/CT pin at 4V
2.25
2.5
2.75
2.25
2.5
2.75
mA
Amplitude
RT/CT pin peak to peak
2.45
2.65
2.B5
2.45
2.65
2.B5
V
Maximum Freq
(note 1)
300
-
-
300
-
-
kHz
Error Amp Section
V(COMP) = 2.5V
(note 1)
-
±15
±50
-
±0.3
±2
AVOL
Gain Bandwidth Product
2VSVoS4V
70
90
-
(note 1)
650
750
Input Offset Voltage
Input Bias Current
-
±15
±50
mV
±0.3
±2
nA
70
90
-
dB
-
650
750
-
kHz
BO
100
1.5
1.7
3.9
4.2
-
rnA
rnA
V
PSRR
9.5V S VIN S 15V
BO
100
Output Sink Current
VFB = 2.7V, V(COMP) = 1.lV (note 1)
1.2
1.5
Output Source Current
VFB = 2.3V, V(COMP) = 5V (note 1)
VFB = 2.3V, RL = 10k to ground
3
3.4
-
5.B
6
6.5
5.8
6
6.5
VouTLow
Rise Response
VFB = 2.7V, RL = 10k to VREF
0.1
0.7
1.1
0.1
0.7
1.1
V
(note 1)
-
5
7
-
5
7
Fall Response
(note 1)
-
3
5
-
3
5
I1S
I1S
VOUT High
dB
Current Sense Section
Gain Ratio
(notes 2 &3)
Maximum Input Signal
V(COMP)
PSRR
Input Bias Current
9.5V " VIN S 15V (notes 1, 2 & 5)
(note 1)
Delay to Output
V(ISENSE) = 1V (note 1); Figure 3
=5V (note 2)
2.B
2.9
3.1
2.8
2.9
3.1
VN
0.85
0.95
1.05
0.B5
0.95
1.05
V
70
BO
70
BO
-
-
±0.3
±2
-
140
160
-
-
dB
±0.3
±2
nA
140
150
ns
Output Section
rDS(ON)
ISINK= 20 rnA
rDS(ON)
Rise Time
ISOURCE = 20 mA
CL= 1 nF(note 1)
Fall Time
CL = 1 nF (note 1)
Cross Conduction
VDD Max
-
7
15
-
7
15
11
20
-
11
15
n
n
35
60
ns
30
40
ns
6.5
-
nC
18
V
40
60
30
40
In coulombs (note 1)
-
6.5
(note 1)
-
-
-
lB
5-22
-
-
BiCMOS CURRENT MODE
PWM CONTROLLER
TC18C4213/4/5
TC28C4213/4/5
TC38C4213/4/5
ELECTRICAL CHARACTERISTICS (Cont):
temperature range. VIN = Voo= 15V; RT = 71
kn;
unless otherwise stated, these specifications apply over specified
CT = 150 pF.
TC18C4X
TC28C4X
Parameter
Test Conditions
ITyp l Max
Min
TC38C4X
Min
I Typ I Max
Units
Under Voltage Lockout Section
Start Threshold
Under Voltage Threshold
X8C4214
X8C43/5
X8C4214
X8C43I5
14.1
14.5
14.9
14.1
14.5
14.9
V
8
8.4
8.8
8
8.4
8.8
V
8.6
9
9.4
8.6
9
9.4
V
7.3
7.6
7.9
7.3
7.6
7.9
V
95
97
100
95
97
100
46
48
50
47
48
50
%
%
%
PWM Section
Maximum Duty Cycle
X8C4213 (note 1)
X8C4415 (note 1)
a
0
Minimum Duty Cycle
Supply Current
StartUp
TA
Operating
=25°C, VIN < Vuv; Figure 1
=V(ISENSE) =OV; Figure 4
j!A
mA
VFB
NOTES: 1. These parameters, although guaranteed, are not 100%
tested in production.
2. Parameter measured at trip point of latch.
3. Gain ratio is defined as:
4. Output frequency equals oscillator frequency for the
XBC42 and XBC43. Output frequency is one half oscillator
frequency for the XBC44 and XBC45.
5. PSRR of VREF, Error Amp and PWM Comparator
combination.
A\bOMP
AV(lsENSE)
where 0 ,,; V(lsENsE) ,,; O.BV
Teledyne Components reserves the right to make changes in the circuitl}' or specifications detailed in this manual at any time without notice. Minimums
and maximums are guaranteed. All other specifications are intended as guidelines only. Teledyne Components assumes no responsibility for the use of
any circuits described herein and makes no representations that they are free from patent infringement.
BENCH TEST OPERATIONAL SIMULATION
The timing ramp (RT/CT) is buffered by the emitter follower and fed back to the ISENSE input. This ramp simulates the
dVdT current ramp which would flow through the primary of the transformer. The output voltage of the power supply is
simulated by feeding some'ofthe reference voltage into VFB. The combination of the two input levels determines the operating
characteristics of the current mode controller.
10k
RT
1
COMP
VREF
8
lOOk
2
5k
IRAMP
VFB
VIN
3
ISENSE
10k
4
GND
RT"CT
5·23
VOO (16V)
OUTPUT
GND
BiCMOS CURRENT MODE
PWM CONTROLLER
TC18C421314/5
TC28C4213/4/5
TC38C4213/4/5
TYPICAL CHARACTERISTICS
Oscillator Frequency Changes
vs. Temperature
Start Current vs. Temperature
150
145
-'
1- 1 1
T -,
135
130
1-125
~12O
MAXTYP
,
,-
"",
1/
100
"
..... r-...
'N'
:lii
-99
~
ifi
~
"",
i--'" ~
r1
-~INI.1~V
!
; 120
1\
,./'
./
w
Q
110
100
0 20 40 60 80100120140
TEMPERATURE (OC)
V
90
-S5
/.
V
/
o
Rgure2
25
50
70
TEMPERATURE (OC)
125
Rgure3
Frequency of Operation
Dead Time vs. CT
10nF
10nF
1
f= 100kHz
.1
:c 1_6
SQ
I
91.4
1.2
/
_130
~-40-20
100 vs. Temperature
1_8
140
\
Rgure 1
2_0
"' " '\
97
MINTYP
1~0-40_20 0 20 40 60 80 100120140
TEMPERATURE (OC)
ISENSE to Out Delay
150
vl~J5vl-
~ 98
110
,
......
",
~
- 115
105
...
VIN= vSTART
140
i
101
.,
J
"
"
X
V
'"
,
"
100 kHz
FREQUENCY
Rgure5
5-24
/
/
,
-,~
-'-
'"
1.0
100pF
-10-40-20 0 20 40 60 80 100120140
10 kHz
TEMPERATURE (OC)
Figure 4
1/
RT= 10 kHz
RT= 22 kHz
RT=47 kHz
RT= 100 kHz
~
1 MHz
100pF
1oo.n8
I
111_
DISCHARGE TIME
Figure 6
10 118
~"'TELEDYNE
COMPONENTS
TC18C46
TC28C46
TC38C46
TC18C47
TC28C47
TC38C47
CMOS CURRENT MODE PWM CONTROLLER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Isolated Output Drive
Low Power CMOS Construction
Low Supply Current .................................. 2 mA Typ
Wide Supply Voltage Operation .............. 8V to 18V
Latch-Up Immunity ................... 500 mA on Outputs
Above and Below Rail Input Protection ............. 6V
High Output Drive ............................... 500 mA Peak
Current Mode Control
Fast Rise/Fall Time ....................... 50 ns @ 1000 pF
High Frequency Operation .......................... 500 kHz
UV Hysteresis Guaranteed
•
•
•
•
•
•
•
Shutdown Pin Available
Double Ended
Soft Start
Low Prop Delay Current Amp
to Output .............................................. < 350 ns Typ
Low Prop Delay Shutdown
to Output .............................................. < 400 ns Typ
TC38C46I47 Pin Compatible with
Unitrode UC3846/3847
ESD Protected .................................................. ±2 kV
BLOCK DIAGRAM
VREF
r-------------------------- ---------------------------,
I
,+-_--I-'1=..30 Veo
+--1-1-17:"1-0 OUTPUT A .n.
smc~~-------------1--------r_--~~--~~
-CURRENT
SENSE INPUT
3
+-__-;-'1..:..40
+ CURRENT
COMPENSATION
-ERROR
AMP INPUT
OUTPUT B
....._~--OGROUND
SENSE INPUT
O-=--+-----------i
5
t-....-~+-------------_..----t_------------_r_"'"O
CURRENT LIMIT
SOFT START ADJUST
+ ERROR
AMP INPUT
t_----_-rl:.;;6-o SHUTDOWN
350mV
3.5kO
L
1017·1
TCI6C46
3.5kO
TCI6C47
TC26C46
TC26C47
TC36C46
TC36C47
_________________________________________________
5-25
TC36C46 OUTPUTS
LOW IN OFF STATE
~
TC36C46 OUTPUTS
HIGH IN OFF STATE
.n.
CMOS CURRENT MODE
PWM CONTROLLER
TC18C46
TC28C46
TC38C46
TC18C47
TC28C47
TC38C47
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The TC38C46I47 are current mode CMOS PWM controllCs. These only draw 2 rnA supply current, so they can
be driven without a costly 50-60 Hz transformer. The output
drive stage is capable of high drive currents, 300 rnA typical.
The TC38C46147 are pin compatible with earlier bipolar
products so that designers can easily update older designs.
A number of improvements have been added.
This second generation part has been designed with an
isolated drive stage. Unlike its cousin, the TC170, the output
stage of the TC38C46/47 can be run from a separate power
supply such asa secondary winding on an output transformer.
This allows for bootstrap start-up of the power supply.
Output Current, Source or Sink (Pins 1, 14) ......... 500 rnA
Analog Inputs (Pins 3,4,5,6, 16) ................ -O.3V to +VIN
Reference Output Current (Pin 2) ......................... -30 rnA
Sync Output Current (Pin 10) .................................. -5 rnA
Error Amplifier Output Current (Pin 7) ..................... -5 rnA
Soft Start Sink Current (Pin 1) ................................. 50 rnA
Oscillator Charging Current (Pin 9) ........................... 5 mA
Supply Voltage ............................................................ 18V
Maximum Chip Temperature .................................. 150 °c
Storage Temperature ............................. -65°C to +150°C
Lead Temperature (10 sec) .................................... 300 °c
Package Thermal Resistance
CerDIP RaJ.A ................................................................. 150°CIW
CerDIP RaJ-c .................................................................... 55°CIW
PDIP RaJ-A ...................................................................... 125°CIW
PDIP RaJ-c ........................................................................ 45°CIW
SOIC RaJ-A ..................................................................... 250°CIW
SOIC RaJ-A ........................................................................ 75°CIW
ORDERING INFORMATION
Part No.
Configuration
Pkg.lTemperature
TC18C46MJE
Non-Inverting
TC18C47MJE
Inverting
TC28C46EOE
Non-Inverting
TC28C46EPE
Non-Inverting
TC28C47EOE
Non-Inverting
TC28C47EPE
Non-Inverting
TC38C46COE
Non-Inverting
TC38C46CPE
Non-Inverting
TC38C47COE
Inverting
TC38C47CPE
Inverting
16-Pin CerDIP
-55 to +125°C
16-Pin CerDIP
-55 to + 125°C
16-Pin SOIC (wide)
-40 to +85°C
16-Pin Plastic DIP
-40 to +85°C
16-Pin SOIC (wide)
-40to+85°C
16-Pin Plastic DIP
-40 to +85°C
16-Pin SOIC (wide)
Oto +70°C
16-Pin Plastic DIP
Oto +70°C
16-Pin SOIC (wide)
Oto +70°C
16-Pin Plastic DIP
Oto +70°C
NOTES: 1. AU voltages are wilh respect to Ground, Pin 13. Currents
are positive into, negative out of the specified tenninal.
2. Static-sensitive device. Unused devices must be stored in
conductive material. Protect devices from static discharge
and static fields. Stresses above those listed under
Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only and
functional operation of the device at these or any other
conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to
Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
5-26
CMOS CURRENT MODE
PWM CONTROLLER
TC18C46
TC28C46
TC38C46
TC18C47
TC28C47
TC38C47
PIN CONFIGURATION
16-Pin SO
16-Pin DIP
CURRENT UMITI
SOFT START
CURRENT UMITI
SOFT START
SHUTDOWN
VREF
2
- CURRENT SENSE
3
+ CURRENT SENSE
4
+ ERROR AMP
5
-ERROR AMP
6
COMPENSATION
7
SHUTDOWN
VIN
~'"
TC18C46
TC18C47
TC28C46
TC28C47
TC38C46
TC38C47
VIN
~'"
OUTPUTB
- CURRENT SENSE
3
VDD
+ CURRENT SENSE
4
GROUND
+ ERROR AMP
5
OUTPUT A
-ERROR AMP
6
OUTPUT A
COMPENSATION
7
SYNC
SYNC
OUTPUTB
TC28C46
TC28C47
TC38C46
TC38C47
VDD
GROUND
ELECTRICAL CHARACTERISTICS: unless otherwise stated, these specifications apply for
T A = -55°C to + 125°C for TC18C461TC18C47; -40°C to +85°C for the TC28C461TC28C47; and O°C to +70°C for the
TC38C461TC38C47; VIN = Voo = 16V; RT = 30.1 k; CT = 270 pF.
TC18C46/47
TC28C46/47
Parameter
TC38C46147
Test Conditions
Min
Typ
Max
Tf = 25°C, 10 = 1 mA
VIN= 8Vto 16V
10= lmAto 10 mA
Over Operating Range, (note 1)
Line, Load, and Temperature (note 1)
Tf = 125°C, 1000 Hrs (note 1)
5.05
5.1
:t4
5.15
:t20
:t4
:to.2
:t20
:to.5
5.24
Min
Typ
Max
Units
5
5.1
:t4
:t4
:to.2
5.20
:t20
:t20
:to.5
5.26
V
mV
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temp Coefficient
Total Output Range
Long Term Drift
Short Circu~
Output Current
Output Noise Voltage
4.97
-
4.94
-
mV
mV/oC
VREF= OV
20
-
70
20
-
70
V
mV
mA
10 Hz:!>f:!> 10 kHz,Tf= 25°C (note 1)
-
22
-
-
22
-
J.lV(rms)
96.5
102
:t.l
106.5
:tl.5
96.5
101
:t.l
106.5
:tl.5
%N
:t.04
:to.06
3
:t.04
2
:to.06
%/oC
1.2
-
:t50
-
-
:t50
-
Oscillator Section
Initial Accuracy
Voltage Coefficient
Temp Coefficient
Tf=25°C
VIN = 8Vto 16V
Over Operating Range (note 1)
-
Clock Ramp
Reset Current
Osc Ramp Amplitude
Sync Output High Level
(note 1)
Sync Output Low Level
Sync Input High Level
Sync Input Low Level
(note 1)
Pin 8 = OV, (note 1)
Pin 8 = OV, (note 1)
Sync Voltage = 5.25V, Pin 8 = OV
Sync Input Current
1.2
2
3.6
3.8
4
3.6
VOD
-0.5
-
-
VOD
-0.5
-
-
0.5
12
8.5
8.5
±5
-
5·27
-
5
:t50
kHz
3
mA
3.8
4
-
-
V
V
-
-
0.5
12
8.5
8.5
±5
-
-
5
:t50
V
V
V
nA
CMOS CURRENT MODE
PWM CONTROLLER
TC18C46
TC28C46
TC38C46
TC18C47
TC28C47
TC38C47
ELECTRICAL CHARACTERISTICS (Cont): unless otherwise stated, these specifications apply for
TA = -55°C to + 125°C for TC18C461TC18C47; -40°C to +85°C for the TC28C461TC28C47; and O°C to +70°C for the
TC38C461TC38C47; VJN =Voo = 16V; RT =30.1k; CT =270 pF.
TC18C46147
TC28C46147
Parameter
Test Conditions
Min
I Typ I
TC38C46147
Max
Min
-
I Typ I
Max
Units
±5
±O.l
±25
±0.5
mV
±0.1
±0.5
nA
-
Error Amp Section
-
Input Offset Voltage
±5
Input Bias Current
-
±10
±25
±100
Input Offset Current
-
±10
±100
-
Open Loop Voltage Gain
AVO = lVto 6V, RL= lOOk
TJ = 25°C (note 1)
70
90
Gain Bandwidth Product
0.7
1
CMRR
VCM = OVto l1V
70
90
PSRR
Output Sink Current
VIN = SVto 16V
V(EA-) = 5V, V(EA+) = 4.9V,
V(COMP) = 1.2V
70
2
90
Output Source Current
V(EA -) = 5V, V(EA+) = 5.1V,
V(COMP) = 2.5V
5
High Level Output Volt
RL = (COMP) 5 k.Q to GND, ACL = 300
4.9
Low Level Output Volt
Slew Rate
RL = (COMP) 5 k.Q to GND. ACL = 300
1.3
70
90
0.7
1
nA
dB
MHz
70
90
70
90
4
-
2
4
-
mA
10
-
5
10
-
mA
5
5.1
4.9
0.4
0.9
-
2
-
1.3
-
dB
dB
5
5.1
V
0.4
0.9
V
2
-
VllJ.s
Current Sense Section
Amplifier Gain
(notes 2, 3)
2.7
3
3.4
2.7
3
3.4
V
Max Differential
Input Signal (VPin 4-VPin 3)
Input Offset Voltage
(note 2)
1.1
1.5
1.S
1.1
1.5
1.S
V
(note 2)
0.4
0.65
0.S5
0.4
0.65
0.S5
V
CMRR
VCM= lVto 12V. (note 2)
40
60
40
60
-
dB
PSRR
VIN = SV to 16V, (note 2)
40
60
-
Input Bias Current
(note 1)
-
±1
±100
Input Offset Current
(note 1)
-
±0.1
-
Input Common Mode Range (note 1)
Delay to Outputs
0
Tf = 25°C. (note 1)
40
60
-
dB
±1
±100
nA
±2
-
±0.1
±2
nA
11
0
-
V
mV
150
225
400
150
225
11
400
320
360
400
320
360
400
VIN
0
-
140
-
65
-
-
ns
Current Limit Adjust Section
Current Limit Voltage Offset
Input Impedance
(Shutdown Unlatched)
Shutdown TerminaJ Section
Threshold Voltage
Input Vottage Range
(note 1)
0
Min Latching
Current (lPin 1)
(note 4)
140
-
Max Non-Latching
Current (IPin1)
(note 5)
-
-
VIN
V
-
IJ.A
65
v..A
Min Pulse Width
(note 1)
100
50
-
100
50
-
ns
Delay to Outputs
(note 1)
125
250
400
125
250
400
ns
5-28
CMOS CURRENT MODE
PWM CONTROLLER
TC18C47
TC28C47
TC38C47
TC18C46
TC28C46
TC38C46
ELECTRICAL CHARACTERISTICS (Cont): unless otherwise stated, these specifications apply for
TA = -55°C to + 125°C for TC18C46ITC18C47; -40°C to +85°C for the TC28C46fTC28C47; and O°C to +70°C for the
TC38C46fTC38C47; VIN = VDD = 16V; RT = 30.1 k; CT = 270 pF.
TC18C46I47
TC28C46I47
Parameter
Test Conditions
Min
I Typ I
TC38C46I47
Max
Min
I Typ
I
Max
Units
Output Section
Output Low Level ros (ON)
ISINK=20
-
rnA
-
Output High Level rOS (ON) ISOURCE = 20 mA
Output Rise Time
CL= 1 mF
Output Fall Time
-
CL= 1 mF
10
20
20
35
55
90
55
90
-
-
10
20
20
35
n
n
55
90
ns
55
90
ns
Under Voltage Lockout Section
Under Voltage Threshold
6.6
7
7.3
6.6
7
7.3
V
Start Threshold
7.5
7.8
8
7.5
7.8
8
V
Threshold Hysteresis
0.6
0.8
1
0.6
0.8
1
V
Total Standby Current
Supply Current
Start-Up Current
4. Current into Pin 1 guaranteed to latch circuit in shutdown
NOTES: 1. These parameters, although guaranteed over the
reoommended operating oonditions, are not 100% tested
in production.
2. Parameter measured at trip point of latch with VPin 6 =
VREF, VPln 16 = OV.
state.
5. Current into Pin 1 guaranteed not to latch circuit in
shutdown state.
3. Amplifiergain is defined as:G = ~in 7 ; ~in 4 = OV to 1V
l:M>in 4
5-29
NOTES
5-30
~"'TELEDYNE
COMPONENTS
TC7660
DC-TO-DC VOLTAGE CONVERTER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC7660 DC-to-DC voltage converter will generate
a negative voltage from a positive source. With two external
capacitors, the TC7660 will convert a 1.5V to 10V input
signal to a -1.5V to -10V level. The TC7660 easily generates -5V in +5V digital systems.
Many analog-to-digital converters, digital-to-analog
converters, operational amplifiers, and multiplexers require
negative supply Voltages. The TC7660 allows +5V digital
logic systems to incorporate these analog components
without adding an additional main power source. The TC7660
can lower total system cost, ease engineering development,
and save space, power and weight.
The TC7660 charges a capacitor to the applied supply
voltage. Internal analog gates connect the capacitor across
the output. Charge is transferred to an output storage
capacitor, completing the voltage conversion. Operation
requires only two external capacitors for supply voltage
<6.5V.
•
•
Converts +5V Logic Supply to ±5V System
Wide Input Voltage Range .•.....••..•......... 1.5V to 10V
Efficient Voltage Conversion ......................... 99.9%
Excellent Power Efficiency ............................... 98%
Low Power Supply .•....•....•...•.....•...•...•.. 5oo!lA Max
Low Cost and Easy to Use
- Only Two External Capacitors Required
RS232 Negative Power Supply
Available in Small Outline (SO) Package
BLOCK DIAGRAM
OSC
LV
7
0--'-+-1
....-_ _ _ _ _ _+4'---0 CAP-
6
0--+---.....- - _ - - '
....._-+"-5-0 VOUT
3
GND
5-31
DC-TO-DC VOLTAGE CONVERTER
TC7660
Contained on-chip are a series DC power supply regulator, RC oscillator, voltage-level translator, four output
power MOS switches, and a unique logic element which
ensures latch-Up free operation.
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5V. This
frequency can be lowered by the addition of an external
capacitor to the OSC terminal (pin 7), or the oscillator may
be overdriven by an external clock.
The low voltage (LV) terminal (pin 6) may be tied to GND
(pin 3) to bypass the internal series regulator and improve
LV operation. At medium-to-high voltages (+3.5V to +1 OV),
the LV pin is left floating to prevent device latch-up.
The TC7660 open-circuit output voltage is equal to the
input voltage to within 0.1 %. The TC7660 has a 98% power
conversion efficiency for 2 mA to 5 mA load currents.
ORDERING INFORMATION
Part No.
Package
Temperature
Range
TC7660CPA
8·Pin Plastic DIP
TC7660lJA
8·Pin CerDIP
-40°C to +85°C
O°Cto +70°C
TC7660EOA
8·Pin Plastic DIP
-40°C to +85°C
TC7660EPA
8·Pin Plastic DIP
-40°C to +85°C
TC7660MJA
8-Pin CerDIP
-55°Cto+125°C
TC7660COA
8·Pin SO
O°Cto +70°C
PIN CONFIGURATION (DIP and SO)
LOW
VOLTAGE (LV)
NC = NO INTERNAL CONNECTION
5-32
DC-TO-DC VOLTAGE CONVERTER
TC7660
ABSOLUTE MAXIMUM RATINGS
Supply VoHage ....................................................... + 10.5V
LV and OSC Inputs
VoHage (Note 1) ............................ -O.3Vto (V++0.3V)
forV+ <5.5V
(V+-5.5V) to (V+ +0.3V)
forV+ <5.5V
Current Into LV (Note 1) ...................... 20 J.lA for V+ >3.5V
Output Short Duration (VSUPPLY .;; 5.5V) ......... Continuous
Power Dissipation (Note 2)
CerDIP ........................................................... 500 mW
Plastic DIP ..................................................... 375 mW
Operating Temperature Range
C Suffix .................................................. O°C to +70°C
I Suffix ................................................ -25°C to +85°C
E Suffix .............................................. -40°C to +85°C
M Suffix ............................................ -55°C to +125°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Slatic-sensitive device. Unused devices must be stored in conductive
material. Protect devices from slatic discharge and slatic fields. Stresses
above those listed under'Absolute Maximum Ratings' may cause pennanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: V+ = 5V, TA = +25°C, Casc = 0, Test Circuit (Figure 1), unless otherwise
indicated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
1+
Supply Current
RL=oo
-
170
500
V+H1
Supply Voltage Range, High
O°C .. TA" +70°C,
RL = 10 ka, LV Open
-55°C .. TA" +125°C,
10ka,LVOpen
3
-
6.5
IlA
V
3
-
5
V
1.5
-
3.5
V
3
-
10
V
(Dx Out of Circu~) (Note 3)
Unit
V+L1
Supply Vo~age Range, Low
(Dx Out of Circuit)
Min .. TA" Max,
RL= 10ka, LVtoGND
V+H2
Supply Voltage Range, High
(Dx In Circu~)
Min .. TA" Max,
RL = 10 ka, LV Open
V+L2
Supply Voltage Range, Low
(Dx In Circuit)
Min .. TA" Max,
RL= 10 ka, LV to GND
1.5
-
3.5
V
ROUT
Output Source Resistance
lOUT = 20 mA, TA= 25°C
-
55
100
n
-
120
n
lOUT = 20 mA, -25°C .. TA.. +85°C
(I Device)
-
-
130
n
lOUT = 20 mA, -55°C .. TA.. + 125°C
(M Device)
-
-
150
n
V+ = 2V, lOUT = 3 mA, LV to GND
DOC .. TA" +70°C
-
-
300
n
V+ = 2V, lOUT = 3 mA, LV to GND
-55°C .. TA.. 125°C (Note 3)
-
-
600
n
10
-
kHz
-
ka
lOUT = 20 mA, O°C .. TA" +70°C
(C Device)
+
fose
PEF
Oscillator Frequency
Power Efficiency
RL= 5 ka
95
98
VOUTEF
Voltage Conversion Efficiency
97
99.9
Zose
Oscillator Impedance
RL=oo
V+=2V
-
V+= 5V
1
100
-
%
%
Mn
NOTES: 1. Connecting any input tenninal to vollages greater than c+ or less than GND may ceuse destructive latch-Up. It is recommended that no
inputs from sources operating from extemal supplies be applied prior to 'power up' of the TC7660.
2. Derate linearly above 50°C by 5.5 mW/"C.
3. TC7660M only.
5-33
DC-TO-DC VOLTAGE CONVERTER
TC7660
TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 1)
Operating Voltage vs Temperature
Power Conversion Eft vs Osc Freq
12
10
~ 98
~ l"'\1'\.
SUPPLY VOLTAGE RANGE
~
~
8
..J
6
g
~
"WITH Dx
~
~
'-"'\
0.-'\
~'"
~
Z
w
0-"
SUPPLY VOLTAGE RANGE
WITHOUTDx
~
2
-25
88
Z
86
o +25 +50 +75 +100 +125
TEMPERATURE (DC)
Output Source Resistance vs Supply Voltage
10k
III
r---...
lOUT = 1 rnA
III
lU
IOUT=15rnA
B4
TA = +25 DC
82
v+ =+5Y
80
100
1k
OSCILLATOR FREQUENCY (Hz)
10k
Output Source Resistance vs Temperature
5oor-~---r--.---r--.---r--'
TA = +25 DC
9:
c~ 450 I---+--+-+--I---+--!---I
~
~
Z
~4oo
1M
iii
W
a:
~
200
1---+---t--+---"1r--+---::;;;;..-!""'--l
W
\.
a:
~ 150 I---+-+--=-+""'>
~
5l
~
ill~
90
....
-55
~
o
~
o
v.
94
92
8a:
UI
96
...~
W
Z
~ 0-.'\ l"-.'\:
..... ~
>
....~ 4
iii
w
a:
100
~
o
UI
!;
~
o
1OOk
!;
o
10k
o
2
3
4
5
6
7
8
100
50
F--t--!---t--II---t---t--::1
bd.--4-"""",~~m;1I
O'--.....I-__-'-__-'-__'----l..__...l--..J
-55
-25
0
+25 +50 +75 +100 +125
TEMPERATURE (DC)
SUPPLY VOLTAGE (Y)
Unloaded Osc Freq vs Temperature
Freq of Osc vs Ext Osc Capacitance
10k
20
=
TA +25DC
V+_ +5V
'N
::t:
~
>
(.)
Z
Y+= +5V
18
16
\
W
~
0
W
14
If
a: 12
0
I\..
5
..J
10
U
UI
0
6
-55
10
1
10
100
1000
OSCILLATOR CAPACITANCE (pF)
8
10k
5-34
\
""-25
.....
......
,
--
0
+25 +50 +75 +100 +125
TEMPERATURE (DC)
DC·TO·DC VOLTAGE CONVERTER
TC7660
TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)
o
Output Voltage vs Output Current
VS=3V/
-1
>
-2
;;~
(!I
~-4
V
V
V
4V
o
1/ / III
V
/
-1
'I
;;~
V "6vV V
(!I
I--'
V
-9
Output Voltage vs Load Current
2
~2
~
I
w
::l
i
Output Voltage vs Output Current
\
TA =.2SO C
v+= +2V
\
\
\
,
1
0
-1
~-2
/
::l
O~
,...,..,.
-4
-5
TA=+2S0C
LV OPEN
Ox IN CIRCUIT
10 20 30 40 SO 60 70 SO 90 100
OUTPUT CURRENT (mA)
:
!
10
"
o
I
3
I-
-10
10 20 30 40 SO 60 70 SO 90 100
OUTPUT CURRENT (mA)
T A = +2SoC
V+=+SV
4
g
-8 ,r
-9
TA = +2SoC
LVOPEN -
S
,r
Ii
VI. '1/ I
V/, '/
......
-/-V ~
Lr /. Iff.
" V1/
-8
o
/ J 'JJ
g...o ,r V X /i rl
V Y: /
!5-6
A~V ~ /
!5 -7
9V/
o
o
-10
'/
/~v ./
~-4 ,r
...I
g...o i.,..o-' . / ~
6.SV
k-' ~ V
!5-6
A!5 -7 V
...I
VS~V
>-2 /
V SV V V,~
~
Output Voltage vs Output Current
o
10
.."
\
\
)
"
./
~OPEssn
I I
SO
-
.-- ~LOPE150n
-2
20 30 40 SO 60 70
LOAD CURRENT (rnA)
,......- ,......-V
0
7
2
3
4
5
6
LOAD CURRENT (mA)
8
Supply Current and Power Conversion Efficiency vs Load Current
~100
~ 90
r-~
so
zt>
w
...........
U 70
ii:
LIw
z
30
II:
20
8
~
f
0
(j
itw
~
40
10
...-....... '-./ ~
/
SO
,
./
1.S
3.0
4.5
6.0
7.5
LOAD CURRENT (mA)
~
40
""\
SO
70
60
\
/
/
20
20
30
40
SO
LOAD CURRENT (mA)
<"
!.
lZ
W
II:
II:
U
30
TA= +2SoC
V+ ...2V
10
i~
40 ::l
I
NOTE: The curves on the right include in the supply current that current fed directly into the load (Rd from V+ (see Figure 1).
Thus, approximately half the supply current goes directiy to the positive side of the load, ancfthe other half through
the TC7660, to the negative side of the load. Ideally, VOUT=2 V'N'IS",2IL' so V,N olS ",VOUToIL'
S-35
SO
1/
20
o
9.0
/
/
90
/--
")
/
30
10
/
/
60
SO
~
o
70
~
Z
8II:
'/
V
100
100
ego r - ...........
~
~ SO
./ t'\
60
~
II:
!l!
z
~
20
TA = +25°C
10
60
o
~
A-
A-
::l
UI
DC-TO-DC VOLTAGE CONVERTER
TC7660
:r
NOTES:
~
10 IIF
• For large values of COSC (>1000 pFl, the values
of C l and C2 should be increased to 100 IIF.
Figure 3. Idealized Switched Capacitor
•• Ox is required for supply voltages greater than
6.SVat-SS°'; TA ,; +70°C. Refer to performance
curves for additional information.
The four switches in Figure 3 are M08 power switches;
81 is a P-channel device, and 82, 83 and 84 are N-channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of 83 and 84 must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (VOUT = V+), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latCh-Up.
This problem is eliminated in the TC7660 by a logic
network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 83 and
84 to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the TC7660 is an
integral part ofthe anti-latch-up circuitry. Its inherent voltage
drop can, however, degrade operation at low voltages. To
improve low-voltage operation, the LV pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left
open to ensure latch-up-proof operation and prevent device
damage.
Figure 1. TC7660 Test Circuit
I
r,n;,
vOUT
GNO
Vl
Cl\P·
OSC
v'
Figure 2. Chip Topography
Circuit Description
The TC7660 contains all the necessary circuitry to
complete a voltage doubler, with the exception of two
external capacitors, which may be inexpensive 10 J.lF polarized electrolytic capacitors. Operation is best understood by
considering Figure 3, which shows an idealized voltage
doubler. Capacitor Cl is charged to a voltage, V+, forthe half
cycle when switches Sl and S3 are closed. (Note: Switches
82 and 84 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
81 and 83 open, thereby shifting capacitor Cl negatively by
V+ volts. Charge is then transferred from Cl to C2, such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2.
Theoretical Power Efficiency
Considerations
In theory, a voltage multiplier can approach 100%
efficiency if certain conditions are met:
.
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
S-36
OC-TO-OC VOLTAGE CONVERTER
TC7660
The TC7660 approaches these conditions for negative
voltage multiplication if large values of C 1 and C2 are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs. The energy lost
is defined by:
VI and V2 are the voltages on Cl during the pump and
transfer cycles. If the impedances of Cl and C2 are relatively
high at the pump frequency (refer to Figure 3), compared to
the value of RL, there will be a substantial difference in
voltages VI and V2. Therefore, it is not only desirable to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
Cl in order to achieve maximum efficiency of operation.
Dos and Don'ts
• 00 not exceed maximum supply Voltages.
• 00 not connect LV terminal to GNO for supply voltages
TYPICAL APPLICATIONS
Simple Negative Voltage Converter
Figure 4 shows typical connections to provide a negative supply where a positive supply is available. A similar
scheme may be employed for supply voltages anywhere in
the operating range of +1.SV to +10V, keeping in mind that
pin 6 (LV) is tied to the supply negative (GND) only for supply
voltages below 3.5V, and that diode Ox must be included for
proper operation at higher voltage and/or elevated temperatures.
The output characteristics of the circuit in Figure 4 are
those of a nearly ideal voltage source in series with 700.
Thus, for a load current of -lOrnA and a supply voltage of
+SV, the output voltage would be -4.3V.
The dynamic output impedance of the TC7660 is due,
primarily, to capacitive reactance of the charge transfer
capacitor (Cl). Since this capacitor is connected to the
output for only 1/2 of the cycle, the equation is:
2
X c = - - =3.180,
2m Cl
where f = 10 kHz and Cl = 10 IlF.
greater than 3.5V.
• 00 not short circuit the output to V+ supply for voltages
above 5.5V for extended periods; however, transient
conditions including start-up are okay.
v+
• When using polarized capacitors, the + terminal of Cl
must be connected to pin 2 of the TC7660 and the +
terminal of C2 must be connected to GNO.
Ox
~,...- ~
,
v.OUT"
,
~
C2
L ___ ..J
• Add diode Ox (as shown in Figure 1) for high-voltage,
elevated-temperature applications. A 1N914 diode is
suitable.
~10"F
Considerations for High Voltage
and Elevated Temperature
"NOTES: 1. VOUT = -n V+ for 1.SV '" V+ '" 6.SV.
2. VOUT = -n (V+-VFDX) for 6.5V '" V+ '" 10V.
The TC7660 will operate efficiently over its specified
temperature range with only two external passive components (storage and pump capacitors), provided the operating supply voltage does not exceed 6.SVat +70°C and SVat
+ 125°C. Exceeding these maximums at the temperatures
indicated may result in destructive latch-up of the TC7660.
Operation at supply voltages up to 10V over the full
temperature range, without danger of latch-up, can be
achieved by adding a general-purpose diode in series with
the TC7660 output, as shown by Ox in the circuit diagrams.
The effect of this diode on overall circuit performance is the
reduction of output voltage by one diode drop (approximately O.6V).
5·37
Figure 4. Simple Negative Converter
Paralleling Devices
Any number of TC7660 voltage converters may be
paralleled to reduce output resistance (Figure S). The reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, Cl. The resultant output
resistance would be approximately:
R QUT=
ROUT (of TC7660)
n (number of devices)
DC-TO-DC VOLTAGE CONVERTER
TC7660
I
I
L ___ ....I
Figure 5. Paralleling Devices Lowers Output Impedance
Cascading Devices
The TC7660 may be cascaded as shown (Figure 6) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual TC7660
ROUT values.
Changing the TC7660 Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 7. In order to prevent possible
device latch-up, a 1 k.Q resistor must be used in series with
the clock output. In a situation where the designer has
generated the external clock frequency using TTL logic, the
addition of a 10 k.Q pull-up resistor to V+ supply is required.
Note that the pump frequency with external clocking, as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.
Ii is alsu pussibie to increase the conversion efficiency
of the TC7660 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, Case, as shown in
Figure 8. Lowering the oscillator frequency will cause an
undesirable increase inthe impedance ofthe pump (Cl) and
the reservoir (C2) capacitors. To overcome this, increase the
values of Cl and C2 by the same factor that the frequency
has been reduced. For example, the addition of a 100 pF
capacitor between pin 7 (OSC) and pin 8 (V+) will lower the
oscillator frequency to 1 kHz from its nominal frequency of
10kHz (a multiple of 10), and necessitate a corresponding
increase in the values of Cl and C2 (from 10 ~F to 100 ~F).
V+
10llF
*NOTES:
1. vOUT =-n V+ for 1.5V..;V+";S.5V.
I
?1.----
l ___ -I
2. VOUT =-n (V+-VFDX) forS.5V..; V+..; 10V.
I
Figure 6. Increased Output Voltage by Cascading Devices
5-38
DC-TO-DC VOLTAGE CONVERTER
TC7660
Combined Negative Voltage Conversion
and Positive Supply Multiplication
Figure 10 combines the functions shown in Figures 4
and 9 to provide negative voltage conversion and positive
voltage multiplication simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from
an existing +5V supply. In this instance, capacitors C1 and
Ca perform the pump and reservoir functions, respectively,
for the generation of the negative voltage, while capacitors
C2 and C4 are pump and reservoir, respectively, for the
multiplied positive Voltage. There is a penalty in this con·
figuration which combines both functions, however, in that
the source impedances of the generated supplies will be
somewhat higher due to the finite impedance ofthe common
charge pump driver at pin 2 of the device.
Figure 7. External Clocking
V+
Figure 8. Lowering Oscillator Frequency
Positive Voltage Multiplication
The TC7660 may be employed to achieve positive
voltage multiplication using the circuit shown in Figure 9. In
this application, the pump inverter switches of the TC7660
are used to charge Cl to a voltage level of V+-VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode 01). On the transfer cycle, the voltage on C1 plus the
supply voltage (V+) is applied through diode 02 to capacitor
C2. The voltage thus created on C2 becomes (2 V+) - (2 VF),
or twice the supply voltage minus the combined forward
voltage drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend
on the output current, but for V+ = 5V and an output current
of 10 rnA, it will be approximately 600.
Figure 10. Combined Negative Converter and Positive Multiplier
Efficient Positive Voltage
Multiplication/Conversion
Since the switches that allow the charge pumping op·
eration are bidirectional, the charge transfer can be per·
formed backwards as easily as forwards. Figure 11 shows
a TC7660 transforming -5V to +5V (or +5V to +1 OV, etc.).
The only problem here is that the internal clock and switch·
drive section will not operate until some positive voltage has
been generated. An initial inefficient pump, as shown in
Figure 10, could be used to start this circuit up, after which
it will bypass the other (0 1 and 02 in Figure 10 would never
turn on), or else the diode and resistor shown dotted in
Figure 11 can be used to "force" the internal regulator on.
v+
VOUT=
(2 V+)-(2 VF)
Figure 9. Positive Voltage Multiplier
5·39
DC-TO-DC VOLTAGE CONVERTER
TC7660
Negative Voltage Generation for
Display ADCs
VOUT=-V-
The TC71 06 is designed to work from a 9V battery. With
a fixed power supply system, the TC7106 will perform
conversions with input signal referenced to power supply
ground.
Negative Supply Generation for
4-1/2 Digit Data Acquisition System
The TC7135 is a 4-1/2 digit ADC operating from ±5V
supplies. The TC7660 provides an inexpensive -5V source.
(See AN16 and AN17 for TC7135 interface details and
software routines.)
Figure 11. Positive Voltage Conversion
Voltage Splitting
The same bidirectional characteristics used in Figure 11
can also be used to split a higher supply in half, as shown in
Figure 12. The combined load will be evenly shared between
the two sides. Once again, a high value resistor to the LV pin
ensures start-up. Because the switches share the load in
parallel, the output impedance is much lower than in the
standard circuits, and higher currents can be drawn from the
device. By using this ciiCUit, and then the (;in;uii oj Figure 6,
+ 15V can be converted (via +7.5V and -7.5V) to a nominal
-15V, though with rather high series resistance (-2500).
l
I
+
I
'3
'3
~
-'
v+
LCD
DRIVE
..,'"
TC7106
COM 32
31
-o}
(3-1:O~~GIT IN Hlt=+_ _
2r--I.:8:....,
..,'"
5
4 TC7660 t -.......-'--"-'
Figure 12. Splitting a Supply in Half
Figure 13a. Fixed Power Supply Operation of TC7106 ADC
5-40
VIN
DC-TO-DC VOLTAGE CONVERTER
TC7660
+5V
~f'
8
TC7660
5
3
+
26 V-
~f'
TC7107A
+1993
/,-,;';';;;";..;;;....0
IN LOF....---o
}V
IN
COMMON ANODE
LED DISPLAY
Figure 13b. Negative Power Supply Generation for TC71 CTIA ADC
+5V
8
:'
20kn
~f'
TC9491
l00kn
2
3
+
11
V+
REF IN
13
14
B2
15
ANALOG
B4
16
COMMON
B8
27
INPUT
OR
UR 28
INPUT
23
POL
REF CAP05 12
26
REF CAP +
STROBE
25
INTOUT RUNIHOLD
AZIN
BUFF OUT
100kn
~f'
TC7135
DIGITAL
GND
24
6502 liP BUS
DATA BUS
2
3
4
5
6
7
8
9
40
39
V- Bl
01
02
03
04
BUSY
CLOCK IN
20
19
18
17
21
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
CA1
CA2
DO
ADDRESS
BUS
07
R~O
CONTROL
BUS
RS3
CS1
CS2
NC
NC
NC
NC
NC
PBO-PB7
22 CLOCK
INPUT
f= 120
kHz
RESET
RIW
SY6522
02
IRQ
VSS
:'
:'
Figure 14. TC7660 Supplies -5V for Converters in Microprocessor-Controlled Data Acquisition Systems
5-41
NOTES
5-42
~,,"TELEDYNE
COMPONENTS
TC7662A
OC-TO-OC CONVERTER
FEATURES
•
•
•
•
•
•
•
Equivalent to ICL76621SI7661ITC76601lTC1044
Increased Output Current •••..••..•.•...•...••..••..••. 40 rnA
No External Diodes Required
Wide Operating Range •..••.•••...••..•.•.••...•... 3V to 18V
Low Output Impedance @ IL = 20 rnA •.•.••. 40n Typ
No Low-Voltage Terminal Required
CMOS Construction
GENERAL DESCRIPTION
The TC7662A is an improved version of the industrystandard TC7660fTC7662 switched capacitor DC-to-DC
converters. CMOS construction and advanced design result in a device with twice the output power of the TC7662
and requires fewer parts in many applications.
The TC7662A can source 40 rnA versus the TC7662's
20 rnA capability. As an inverter, the TC7662A can output
voltages as high as 18V and as low as 3V, without the need
for external diodes. The output impedance of the device is
a low 40n (typical), voltage conversion efficiency is 99.9%,
and power conversion efficiency is 97%.
See TC962 if higher output current is required.
The low-voltage terminal (pin 6) required in some TC7662
applications has been eliminated. Only two external capacitors are required for inverter applications. If an external clock
is needed to drive the TC7662A (such as when paralleling),
driving pin 7 directly will cause the internal oscillator to sync
to the external clock.
The TC7662A can be used in applications such as
VOUT =-VIN, VOUT = 2 VIN, VOUT = VIt./2, and VOUT = ±nVIN.
It may also be used as a DC-to-DC inverter, a doubler,
a plus and minus supply splitter, and (when combined with
other TC7662A's), as a voltage multiplier greater than two.
The TC7662A is compatible with the LTC1 044,
ICL7660, ICL7662, S17661, and TC7660. It is recommended
for designs requiring greater power and/or less input-tooutput voltage drop.
FUNCTIONAL DIAGRAM
8
Vs
GND
3
OUT
t-___40
+
CAP-
5
1033-1
5·43
DC-TO-DC CONVERTER
TC7662A
ORDERING INFORMATION
Part No.
Package
TC7662ACPA
TC7662AIJA
TC7662AEPA
TC7662AMJA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vs to GND ........................................ +18V
Input Voltage (Any Pin) ................. (VS + 0.3) to (Vs - 0.3)
Current Into Any Pin ................................................ 10 rnA
Operating Temperature Range
CPA .......................................................... 0° to +70°C
IJA ..................................................... -25°C to +85°C
EPA ................................................... -40°C to +85°C
MJA ................................................. -55°C to +125°C
Max Dissipation
CPA, EPA ...................................................... 375 mW
IJA, MJA ........................................................ 500 mW
Package Thermal Resistance
CPA, EPA 9JA ............................................... 140°CIW
IJA, MJA 9JA ................................................... 90°CIW
Storage Temperature Range .................. ~5°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
ESD 'Protection ...................................................... ±2000V
Output Short Circuit ................. Continuous (at 5.5V Input)
Temperature
Range
8-Pin Plastic DIP
8-Pin CerDIP
8-Pin Plastic DIP
8-Pin CerDIP
PIN CONFIGURATION
NC = NO INTERNAL CONNECTION
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from stetic discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS:
Symbol
Parameter
Vs
Is
Supply Voltage
Supply Current
Vs=+15V
VS = 15V, TA =+25°C (See Test Circuit)
Test Conditions
RL=TA=+25°C
0~TA~+70°C
-55 ~TA ~ +125°C
Vs=+5V
TA=+25°C
0~TA~+70°C
Ro
Output Source
Resistance
Cosc
PEFF
Oscillator Frequency
Power Efficiency
VEFF
Voltage Efficiency
-55 ~TA ~+125°C
IL= 20 rnA, Vs = +15V
IL = 40 rnA, Vs = +15V
IL = 3 rnA, Vs = +5V
Min
Typ
Max
3
-
18
V
700
I1A
I1A
I1A
I!A
I1A
I1A
93
510
560
650
190
210
210
40
50
100
12
97
-
%
99
99.9
%
96
-
-
-
Vs=+15V
RL=2 kQ
V+s=+15V
RL=Over Temperature Range
5-44
-
50
60
125
-
Unit
Q
Q
Q
kHz
%
DC-TO-DC CONVERTER
TC7662A
TEST CIRCUIT
8
J..!
J.!!-----+.=
NC ....--!..i
2
3
7
----,
TC7662A
6 NC :~: COSC
,L,
y+
~IL (+5V)
RL
L.....-~L__J~5--"---t--
YOUT
Rgure 1
(~V)
Capacitor Equivalent Circuit
Note one of its characteristics is ESR (equivalent series
resistance). This parasitic resistance winds up in series with
the load. Thus, both voltage and power conversion efficiency are compromised if a low ESR capacitor is not used.
For example, in the "Test Circuit", changing Cp and CR
capacitors with typical ESR to low ESR types, the effective
converter output impedance changed from 4S0 to 400, an
improvement of 12%.
This applies to all types of capacitors, including film
types (polyester, polycarbonate etc.).
Some applications information suggest the capacitor is
not critical and attribute the limiting factor of the capacitor to
its reactive value. Let's examine this:
APPLICATIONS INFORMATION
Theory of Operation
The TC7662A is a capacitive pump (sometimes called
a switched capacitor circuit), where four MOSFET switches
control the charge and discharge of a capacitor.
The functional diagram (page 1) shows how the switching action works. SW1 and SW2 are tumed on simultaneously, charging C1 to the supply voltage, V§. This assumes that the on resistance of the MOSFETs in series
with the capacitor results in a charging time (3 time constants) less than the on time provided by the oscillator
frequency, as shown:
Xc = _1_ and
21tf C
Zc
Xc
= OS
'
where OS (duty cycle) = SO%.
Thus, Zc = 1.330 at f = 12 kHz, where C = 10 ~F.
For the TC7662A, f = 12,000 Hz, and a typical value of
C would be 10 ~F. This a reactive impedance of =1.33W. If
the ESR is as great as SW, the reactive value is not as critical
as it would first appear, as the ESR would predominate. The
SW value is typical of a general-purpose electrolytic capacitor.
3 (RDS(ON) C1) ----,
~~
TC1426
TC1427
TC1428
NONINVERTING
OUTP~~___
(TC1427)
GND
NOTE: TC1428 has one inverting and one noninverting driver.
Ground any unused driver input.
1012-1
6-3
INVERTING
[>o>--__O_U_T~UT
(TC1426)
1.2A DUAL HIGH-SPEED MOSF.ET DRIVERS
TC1426
TC1427
TC1428
PIN CONFIGURATIONS
ORDERING INFORMATION
Part No.
Package
Configuration
TC1426COA
8·Pin SO
Inverting
O°Cto +70°C
Range
TC1426CPA
8·Pin
Plastic DIP
Inverting
ODCto +70°C
TC1426EPA
8·Pin
Plastic DIP
Inverting
·40°C to +85 DC
TC1426EOA
8·Pin
SO
Inverting
·40°C to +85°C
TC1427COA
8·Pin SO
Non·lnverting
NC
NC
~
INVERTING
IN B
OUTB
NC
NC
TC1427CPA
8·Pin
Plastic DIP
Non·lnverting
O°Cto +70°C
ODCto +70 DC
TC1427EPA
8·Pin
Plastic DIP
Non·lnverting
·40DC to +85°C
TC1427EOA
8·Pin
SO
Non·lnverting
·40DC to +85 DC
TC1428COA
8·Pin SO
Inverting and
Non·lnverting
O°Cto +70°C
TC1428CPA
8·Pin
Plastic DIP
Inverting and
Non·lnverting
ODCto +70°C
TC1428EPA
8·Pin
Plastic DIP
Inverting lind
Non·lnverting
~40QC
TC1428.EOA
8·Pin
SO
Inverting and
Non·lnverting
·40°C to +85 DC
~
NON·INVERTING
INB
~
~
NC
INB
Test Circuit
NC = NO CONNECTION
to +8q OC
Test Circuit
VOO=16V
VOO=16V
INPUTo-f--1I>-+-?--o
TC1426
(1/2 TC1428)
TC1427
(112 TC1428)
+5V
INPUT
INPUT
-O.4V
Voo ----::::i=!L
OUTPUT
OUTPUT
--"'I
OV _ _ _
Figure 2. Non·lnverting Driver Switching Time
Figure 1. Inverting Driver Switching Time
6-4
1.2A DUAL HIGH-SPEED MOSFET DRIVERS
TC1426
TC1427
TC1428
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2 and 3)
Stresses above those listed under' Absolute Maximum Ratings' may
cause permanent damage to the device. These are stress mtings only, and
functional opemtion of the device at these or any other conditions above
those indicated inthe opemtional sections of the specifications is not
implied. Exposure to absolute maximum mting conditions for extended
periods may affect device reliability.
Power Dissipation
Plastic DIP ............................................................... 1W
SOIC ................................................................ 500mW
Derating Factor
Plastic DIP ...................................................... 8 mW/oC
SOIC ............................................................... 4 mW/oC
Supply Voltage ............................................................ 18V
Input Voltage, Any Terminal. ....... Vs + 0.3V to GND -0.3V
Operating Temperature: C Version .............. O°C to +70°C
: EVersion ........... -40°C to +85°C
Maximum Chip Temperature ................................. + 150°C
Storage Temperature ............................. +65°C to +160°C
Lead Temperature (10 sec) ................................... +300°C
ELECTRICAL CHARACTERISTICS (TA = 25°C with 4.5V.;;; Voo' '" 16V unless otherwise specified.)
Symbol
I
Parameter
I
Test Conditions
I
Min
I
Typ
I
Max
Unit
Input
V'H
Logic 1, Input Voltage
3
V'L
Logic 0, Input Voltage
-
I'N
Output
Input Current
OV.;;; V'N';;; Voo
-1
VOH
High Output Voltage
Test Figures 1 and 2
V oo-O·025
VOL
Low Output Voltage
Test Figures 1 and 2
Ro
Output Resistance
V'N =0.8V
lOUT = 10 rnA, Voo = 16V
-
V'N =3V
lOUT = 10 mA, Voo = 16V
IpK
Peak Output Current
I
Latch-Up Current
-
-
V
0.8
V
1
I1A
-
V
0.025
V
12
18
n
-
8
12
n
-
1.2
-
Withstand Reverse Current
>500
-
-
-
A
-
rnA
35
ns
25
ns
75
ns
75
ns
Switching Time (Note 1)
tR
Rise Time
Test Figures 1 and 2
tF
Fall Time
Test Figures 1 and 2
tOl
Delay Time
Test Figures 1 and 2
t02
Delay Time
Test Figures 1 and 2
Power Supply Current
V'N = 3V (Both Inputs)
mA
V'N = OV (Both Inputs)
mA
Power Supply
Note: 1. Switching times guaranteed by design.
6-5
1.2A DUAL HIGH-SPEED MOSFET DRIVERS
TC1426
TC1427
TC1428
ELECTRICAL CHARACTERISTICS
(Over operating temperature range with 4.5V ~ VDO+ ~ 16V unless otherwise specified.)
Symbol I
Input
I
Test Conditions
I
Min
Typ
Max
Unit
Logic 1, Input Voltage
3
-
-
V
V'L
Logic 0, Input Voltage
-
0.8
V
I'N
Input Current
10
JlA
V'H
Parameter
OV ~ V'N ~ Voo
-10
-
Output
VOH
High Output Voltage
Test Figures 1 and 2
V oo-0.025
-
-
VOL
Low Output Voltage
Test Figures 1 and 2
-
-
0.025
V
Ro
Output Resistance
V'N =0.8V
lOUT = 10 mA, Voo = 16V
-
15
23
Q
-
10
18
Q
Withstand Reverse Current
>500
-
-
mA
--
60
ns
40
ns
125
ns
125
ns
V'N = 3V
lOUT = 10 mA, Voo = 16V
I
Latch-Up Current
V
Switching Time
tR
Rise Time
Test Figures 1 and 2
tF
Fall Time
Test Figures 1 and 2
-
t01
Delay Time
Test Figures 1 and 2
-
t02
LJelayTime
Test Figures 1 and 2
-
Power Supply Current
V'N = 3V (Both Inputs)
rnA
V'N = OV (Both Inputs)
mA
Power Supply
SUPPLY BYPASSING
INPUT STAGE
Large currents are required to charge and discharge
large capacitive loads quickly. For example, charging a
1OOO-pF load 16V in 25 ns requires an O.8A current from the
device power supply.
To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low-inductance ceramic
MLC capacitors with short lead lengths «0.5-in.) should be
used. A 1.0-/-lF film capacitor in parallel with one or two
O.1-/-lF ceramic MLC capacitors normally provides adequate
bypassing.
The input voltage level changes the no-load or quiescent supply current. The N-channel MOSFET input stage
transistor drives a 2.5 mA current source load. With a logic
"1" input, the maximum quiescent supply current is 9 mAo
Logic "0" input level signals reduce quiescent current to 500
JlA maximum. Unused driver inputs must be connected
to VDO or GND. Minimum power dissipation occurs for logic
"0" inputs for the TC1426/27/28.
The drivers are designed with 100 mV of hysteresis.
This provides clean transitions and minimizes output stage
current spiking when changing states. Input voltage
thresholds are approximately 1.5V, making logic "1" input
any voltage greater than 1.5V upto Voo.lnputcurrent is less
than 1 JlA over this range.
The TC1426/27/28 may be directly driven by the TL494,
SG1526/27, TC38C42, TC170 and similar switch-mode
power supply integrated circuits.
GROUNDING
The TC1426 and TC1428 contain inverting drivers.
Ground potential drops developed in common ground impedances from input to output will appear as negative
feedback and degrade switching speed characteristics.
Individual ground returns forthe input and output circuits
or a ground plane should be used.
6-6
1.2A DUAL HIGH-SPEED MOSFET DRIVERS
TC1426
TC1427
TC1428
TYPICAL CHARACTERISTIC CURVES
Rise Time vs Supply Voltage
550
......
~
r-....
r-- I-'iii" 330
.:.
w
~
I I
I I
r-....
440
r-...
......
.......
264
~
r-....
......
..... ~oolF
1
i'" r--..
110
70
'iii"
10,000 pF
r-... """;"1
r
.......
66
2200 pF
.:. 60
w
::Ii
;:::50
r-.... .....
4ioo~F
r- to- 1-0
2200pF
4700pF
I
Cl = 1000 pF
TA = +2SoC
,
i""'- .......
1
Delay Time vs Supply Voltage
80
TA = +25°C
. ~ _I
i""'- ......
220
Fall Time vs Supply Voltage
330
TA = +25°C
~
1\ ~
r' ~ :::-1"- totOl
40
t02
I I
o
5
7
9
11
Voo(V)
13
15
Rise and Fall Times vs Temperature
40
Cl = lOOOpF
voo= +15V
....
..... I--""
~
~
j..-f"'1
,....
I
I
tOl
L
~
V
~d
25
45
1,...0
65
8S
105
TEMPERATURE (OC)
125
o
100
V
::Ii
;:::
~
V ~~
IY'"........
100
10 .........::
100
!Ii! 100
1000
10,000
CAPACITIVE LOAD (pF)
2200
±± Vo~'~15V
SVoo .... ~
~~
15Voo
~~
j",.-I-'''''''
Cl = l000pF=
TA = +2SOC
!
......
L
"
~
~15VoO
LVoo=SV
~ t:::~
10
100
_I-
i
10Voo
V
~
.....
V20kHz
voo= 10V
;:::
10VOD
~
.1
Supply Current vs Frequency
Fall Time vs Capacitive Load
r=TA = +25°C
5Voo
V
~
iOy
V
520
940 1360 1780
CAPACITIVE LOAD (pF)
~
!w 100
15
500 kHz
V
1000
~TAI=+k5!d
13
!-eCl= 1000 pF
Voo=1SV
24 TA= +25°C
J",...o ......
-
o
125
11
Voo (V)
Supply Current vs Capacitive Load
j...o- ~
~
Rise Time vs Capacitive Load
1000
~ i--'"
t02
.1
65
85
105
TEMPERATURE ("C)
9
7
30
..,....
8
45
15
Cl= 1000pF
Voo= +15V
tFAll
25
J
13
Delay Time vs Temperature
I-L- ~ l-
o
11
Voo(V)
~
~
..... I--""
9
7
o
1000
10,000
CAPACITIVE LOAD (pF)
6-7
10
~
100
1000
FREQUENCY (kHz)
10,000
1.2A DUAL HIGH-SPEED MOSFET DRIVERS
TC1426
TC1427
TC1428
TYPICAL CHARACTERISTIC CURVES (Cont.)
Low-State Output Resistance
15
~lodm~
13
1,\
'\.
TA =+25'C
42
,
~50mA
I' ~
, --r-
7
5
26
" ~ '\ ........ r-...
5
7
9
r.:::: ~
11
Voo(V)
13
-
15
~
5
7
9
g
/
~
D..
5
13
15
o
25
I
~
sOle
-4 'l'w/'e
=
~
I'\..
~
"
~
50
75
100
125
150
AMBIENT TEMPERATURE ('e)
Crossover Energy Loss
!
10-8
1
V
~
-' 10
SLOPf
11
Voo(V)
BOTH INPUTS LOGIC
I'\..
~
200
....\
/
w
I'\..
rE400 ~
r\
10mA ...... r::::::
20
BOTH INPUTS LOGIC "0"
o
-S
I\,
-
I'\..
~ 600
\
~omA
PDIJ
'\. I'\..SLOPE
= -8 mwrc
800
Quiescent Power Supply
Current vs Supply Voltage
20
~15
I'\..
I
\
Quiescent Power Supply
Current vs Supply Voltage
g;VI
I
l00mA
18 ~"h..
10
Package Power Dissipation
1000
TA = +25'C
34
"- ~ '\
I--l0mA
High-State Output Resistance
50
/
/
["rr rIb!
/'
V'
Iv
o
o
50
100 150 200 300
SUPPLY CURRENT (JlA)
400
1
234
5
SUPPLY CURRENT (mA)
6-8
6
6
8
10 12
Voo (V)
14
16
18
~,,"TELEDYNE
COMPONENTS
TC426
TC427
TC428
DUAL HIGH-SPEED POWER MOSFET DRIVERS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
High-Speed Switching (CL = 1000 pF) ............. 30 ns
High Peak Output Current ................................. 1.SA
High Output Voltage Swing .................... VDo-2S mV
GNO+2SmV
Low Input Current (Logic "0" or "1 ") ................ 1 IlA
TTUCMOS Input Compatible
Available in Inverting and Noninverting
Configurations
Wide Operating Supply Voltage ............ 4.SV to 18V
Current Consumption
-Inputs Low .................................................. 0.4 mA
- Inputs High ....................................................8 mA
Single Supply Operation
Low Output Impedance ...........•..•.......................... 6n
Pinout Equivalent of 050026 and MMH0026
Latch-Up Resistant: Withstands >500 mA
Reverse Current
ESO Protected ...........•........•................................ 2 kV
The TC426rrC427rrC428 are dual CMOS high-speed
drivers. A TTUCMOS input voltage level is translated into
an output voltage level swing equaling the supply. The
CMOS output will be within 25 mV of ground or positive
supply. Bipolar designs are capable of swinging only within
1V of the supply.
The low impedance, high-current driver outputs will
swing a 1000 pF load 18V in 30 ns. The unique current and
voltage drive qualities make the TC4261TC427rrC428 ideal
power MOSFET drivers, line drivers, and DC-to-DC converter building blocks.
Input logic signals may equal the power supply voltage.
Input current is a low 1 ~, making direct interface to
CMOS/bipolar switch-mode power supply control ICs possible, as well as open-collector analog comparators.
Quiescent power supply current is 8 mA maximum.
The TC426 requires 1/5 the current of the pin-compatible
bipolar DS0026 device. This is important in DC-to-DC
converter applications with power efficiency constraints
and high-frequency switch-mode power supply applications.
Quiescent current is typically 6 mA when driving a 1000 pF
load 18V at 100 kHz.
The inverting TC426 driver is pin-compatible with the
bipolar DS0026 and MMH0026 devices. The TC427 is
noninverting; the TC428 contains an inverting and noninverting driver.
FUNCTIONAL DIAGRAM
V+O--'--~--..,
~"
TC426
TC427
TC428
NONINVERTING
OUTPUT
INVERTING
OUTPUT
(TC42~;---~26)
GND
NOTE: TC428 has one inverting and one noninverting driver.
Ground any unused driver input.
1018-1
6-9
DUAL HIGH·SPEED
POWER MOSFET DRIVERS
TC426
TC427
TC428
ORDERING INFORMATION
PIN CONFIGURATIONS (DIP and SO)
Part No.
Package
Configuration
Temperature
Range
TC426CPA
TC427CPA
TC428CPA
TC426COA
TC427COA
TC428COA
Inverting
Noninverting
Complementary
Inverting
Noninverting
Complementary
o·C to +70·C
o·C to +70·C
O·Cto +70·C
O·C to +70·C
ODC to +70 DC
O·C to +70·C
TC426IJA
TC4271JA
TC4281JA
8-Pin PDIP
8-Pin PDIP
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
8-PinSOIC
8-Pin CerOlP
8-Pin CerOlP
8-Pin CerOlP
TC426EOA
TC427EOA
TC428EOA
TC426MJA
TC427MJA
TC428MJA
8-PinSOIC
8-Pin SOIC
8-PinSOIC
8-Pin CerOlP
8-Pin CerOlP
8-Pin CerOlP
NC
~
INA
INVERTING
INB
-2S·C to +8S·C
Inverting
_2SDC to +85DC
Noninverting
Complementary -2S·C to +8S·C
Inverting
-40·C to +85DC
Noninverting
-40·C to +8SDC
Complementary -40·C to +8S"C
Inverting
-5S·C to + 12S·C
-SSDC to + 12SDC
Noninverting
Complementary -5S DC to + 12S·C
~
INA
NONINVERTING
INB
5 OUTB
COMPLEMENTARY
NC = NO INTERNAL CONNECTION
VDD= f8V
VDD=f8V
INPUT 0--1---1
INPUTo--I--~
>--+-.-0 OUTPUT
~ CL = fOOOpF
~~
~~
TC426
TC427
(112 TC428)
(112 TC428)
..sV
+5V - -
INPUT
~O.4V
-
-
-_----"'\1
INPUT
fO%
f8V - - -
f8V---~~_
OUTPUT
OUTPUT
OV
OV
Figure 2. Noninverling Driver Switching Time Test Circuit
Figure f. Inverting Driver Switching TIme Test Circuit
6-10
DUAL HIGH-SPEED
POWER MOSFET DRIVERS
TC426
TC427
TC428
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................................................... +20V
Input Voltage, Any Terminal ....... Voo+0.3V to GND -0.3V
Power Dissipation
Plastic ............................................................ 1000 mW
CerDIP ............................................................. 800 mW
SOIC ................................................................ 500 mW
Derating Factor
Plastic ............................................................. 8 mW/oC
CerDIP ......................................................... 6.4 mW/oC
SOIC ............................................................... 4mWrC
Operating Temperature Range
C Version ................................................. O°C to +70°C
I Version ............................................... -25°C to +85°C
E Version .............................................. -4O°C to +85°C
M Version ........................................... -55°C to + 125°C
ELECTRICAL CHARACTERISTICS: TA
Symbol
Parameter
Maximum Chip Temperature ................................. + 150°C
Storage Temperature Range .................. ~5°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure toaboolute maximum rating conditions for extended periods may
effect device reliability.
=+25°C with 4.5V .;;; Voo';;; 18V, unless otherwise specified.
Test Conditions
Min
Typ
Max
Unit
Input
VIH
Logic 1, High Input VoHage
2.4
VIL
Logic 0, Low Input Voltage
-
liN
Input Current
OV,;; V IN ,;;VDD
-1
-
-
V
0.8
V
1
~
Output
VOH
High Output Voltage
VOL
Low Output Voltage
ROH
High Output Resistance
ROL
IpK
Low Output Resistance
VDD-O.025
=10 mA, VDD =18V
lOUT =10 mA, VDD =18V
lOUT
Peak Output Current
-
-
1.5
10
6
-
V
0.025
V
15
10
n
n
-
A
Switching Time (Note 1)
tR
Rise Time
Test Figure 1
-
-
30
ns
tF
Fall Time
Test Figure 1
-
20
ns
t01
Delay Time
Test Figure 1
-
-
50
ns
t02
Delay Time
Test Figure 1
-
-
75
ns
Power Supply Current
VIN = 3V (Both Inputs)
VIN = OV (Both Inputs)
Power Supply
Is
6-11
mA
mA
DUAL HIGH-SPEED
POWER MOSFET DRIVERS
TC426
TC427
TC428
ELECTRICAL CHARACTERISTICS:
Over operating temperature range with 4.5V '" VDD '" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
-
0.8
V
10
IlA
-
V
Unit
Input
VIH
Logic 1, High Input Voltage
2.4
VIL
Logic 0, Low Input Voltage
-
hN
Input Current
-10
OV,,; VIN"; Voo
-
V
Output
-
VOH
High Output Voltage
Voo-O.025
VOL
Low Output Voltage
-
-
0.025
V
ROH
High Output Resistance
-
13
20
n
ROL
Low Output Resistance
-
8
15
W
-
60
ns
40
ns
=10 mA, Voo =18V
lOUT =10 mA, Voo =18V
lOUT
Switching Time (Note 1)
tR
Rise Time
Test Figure 1
-
tF
Fall Time
Test Figure 1
-
to!
Delay Time
Test Figure 1
t02
Delay Time
Test Figure 1
-
Power Supply Current
VIN 3V (Both Inputs)
VIN = OV (Both Inputs)
75
ns
120
ns
Power Supply
Is
=
mA
rnA
NOTE: 1. Switching times guaranteed by design.
SUPPLY BYPASSING
INPUT STAGE
Charging and discharging large capacitive loads quickly
requires large currents. For example, charging a 1000-pF
load 18V in 25 ns requires an 0.8A current from the device
power supply.
To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low-inductance ceramic
disk capacitors with short lead lengths «0.5 in.) should be
used. A 1 IlF film capacitor in parallel with one or two
0.1 IlF ceramic disk capacitors normally provides adequate
bypassing.
The input voltage level changes the no-load or quiescent supply current. The N-channel MOSFET input stage
transistor drives a 2.5 mA current source load. With a logic
"1" input, the maximum quiescent supply current is 8 mAo
Logic "0" input level signals reduce quiescent current to
0.4 rnA maximum. Minimum power dissipation occurs for
logic "0" inputs for the TC426/427/428. Unused driver
inputs must be connected to Voo or GND.
The drivers are designed with 100 mV of hysteresis.
This provides clean transitions and minimizes output stage
current spiking when changing states. Input voltage thresholds are approximately 1.5V, making the device TTL compatible over the 4.5V to 18V supply operating range. Input
current is less than 1 J.LA over this range.
The TC426/427/428 may be directly driven by the
TL494, SG 1526/1527, SG 1524, SE5560, and similar switchmode power supply integrated circuits.
GROUNDING
The TC426 and TC428 contain inverting drivers. Ground
potential drops developed in common ground impedances
from input to output will appear as negative feedback and
degrade switching speed characteristics.
Individual ground returns for the input and output circuits
or a ground plane should be used.
6-12
DUAL HIGH-SPEED
POWER MOSFET DRIVERS
TC426
TC427
TC428
POWER DISSIPATION
The supply current vs frequency and supply current vs
capacitive load characteristic curves will aid in determining
power dissipation calculations.
The TC426/427/428 CMOS drivers have greatly reduced quiescent DC power consumption. Maximum quiescent current is 8 mA compared to the DS0026 40 mA
specification. For a 15V supply, power dissipation is typically 40 mW.
In power MOSFET drive applications the Poc term is
negligible. MOSFET power transistors are high impedance, capacitive input devices. In applications where resistive loads or relays are driven, the Poc component will
normally dominate.
The magnitude of PAC is readily estimated for several
cases:
B.
A.
Two other power dissipation components are:
• Output stage AC and DC load power.
• Transition state power.
1. f
2. CL
3. Vs
4. PAC
Output stage power is:
Po = Poc + PAC
= Vo (Ioc) + f CL Vs
= 20kHZ
=1000 pf
= 18V
=65mW
1. f
2. CL
3. VS
4. PAC
= 200 kHz
=1000 pf
=15V
=45mW
During output level state changes, a current surge will
flow through the series connected Nand P channel output
MOSFETS as one device is turning "ON" while the other is
turning "OFF". The current spike flows only during output
transitions. The input levels should not be maintained between the logic "0" and logic "1" levels. Unused driver inputs must be tied to ground and not be allowed to float.
Average power dissipation will be reduced by minimizing
input rise times. As shown in the characteristic curves,
average supply current is frequency dependent.
Where:
Vo = DC output voltage
loc = DC output load current
f
= Switching frequency
Vs = Supply voltage
TYPICAL CHARACTERISTICS CURVES
Rise and Fall Times vs
Supply Voltage
70
60
50
90
c L = 1000 pF
TA=+2s'e _
1\,
80
'\ ........
"-
20
10
o
5
!"....
~
"iii" 70
.s.
I\.
1'....
10
15
SUPPLY VOLTAGE (V)
Rise and Fall Times vs
Temperature
Delay Times vs Supply Voltage
~ 60
r!a
IF-
20
=
35
e L = 1000 pF
voo = 18V
I
100
30
V
\
50
'\
UJ
C 40
30
o
40
~
j.:
S
e L = 1000 pF
TA +25'e
5
10
15
SUPPLY VOLTAGE (V)
6-13
-
/
~
IF
V V
01-
20
. . .V
IR
V
10
o
-25
o
25
50 75 100 125 150
TEMPERATURE ee)
DUAL HIGH·SPEED
POWER MOSFET DRIVERS
TC426
TC427
TC428
TYPICAL CHARACTERISTICS CURVES (Cont.)
Supply Current vs
Capacitive Load
Delay Times vs Temperature
100
V
C L = 1000 pF
90 VDD =lSV
.
so
.:.
:;;
so
tD2
/
1:
V
ffi
50
!!i
40
200!k~IJ
~ 30
""-
j"l4
U
..J
50
C
40
30
-25
0
-
iil
tDl
20
-
10
o
25
50
75 100 125 150
TEMPERATURE ("C)
10
!z
I!ia:
.:.
V1O'-t
100
1000
CAPACITIVE LOAD (pF)
10K
VI
I
_ro
1
1/
~
VDD1=S?
1.32
V
/1~
v >
/'
0.44
A
~
1000
o
20
1
/
,I
o
1
-::: g
~ Ksv
~ 0.4S
~
o
....
0.24
V
/
V
~ P""
/
/
/
./~
~~
/
.,.,
10/
. /~
~y- -
~~
o
10 20 30 40 50 60 70 80 90100
CURRENT SUNK (mA)
Package Power Dissipation
1000 ~-"'-"'--'---r---'
. i l .!.
II
800 ~---'~-+--t--t---l
/
~
600 k---j----''''t-.......- t - - i - - I
~ ~Of-~~--+-~~---+---i
/
200
I'
o
- f-VDD=5~ L
~ 0.72
~
V
6
1
CI
NO LOAD
BOTH INPUTS LOGIC "0"
TA = +25°C
1/
2
3
4
5
SUPPLY CURRENT (mA)
:::.
UJ
Supply Voltage vs
Quiescent Supply Current
20
~
.1
0.96
10 20 30 40 50 60 70 SO 90100
CURRENT SOURCED (mA)
Supply Voltage vs
Quiescent Supply Current
NO LOAD
BOTH INPUTS LOGIC" 1"
TA = +25°C
~
~ ~ F-'"
10K
Low Output vs Voltage
~
~II
10
100
FREQUENCY (kHz)
100
1000
CAPACITIVE LOAD (pF)
~T/If'+25'C-
2 o.ss
V
10
1.20
I
II
"":::l
.eo
.I~
I- A=
20
u
~ 10
V
10
1.76
:::l
tF
UJ
:;;
-i ~25,i:
VDD =1SV
<"
E
-
rl
100
High Output vs Voltage
2.20
TA =+25'C
c L = 1000 pF
tR
j:
Supply Current vs Frequency
30
.
60
a:
60
UJ
T =
V,D
I-
j:
>
~
'in = 10kHz
........ 6
112 ">-"0---1+ 1710 pI
~=2:
"l
lN4001
VOUT
1------4(1----1<1<11------....
lN4001
1
~I
47 pI
6-15
0
-11.0 I--I--I-+~-+--+-+--+--+--+---l
-12.0
-13.0
-14.0
/
V
~'----J----'--'---'--'--'----'----'----'----'
o
5 10 20 30 40 50 60 70 80 90 100
'OUT (mA)
NOTES
6-16
~"'TELEDYNE
COMPONENTS
TC429
SINGLE HIGH-SPEED, CMOS POWER MOSFET DRIVER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The TC429 is a high-speed, single CMOS-level translator and driver. Designed specifically to drive highly capacitive power MOSFET gates, the TC429 features 2.50 output
impedance and 6A peak output current drive.
A 2500 pF capacitive load will be driven 18V in 25 ns.
Delay time through the device is 60 ns. The rapid switching
times with large capacitive loads minimize MOSFET transition power loss.
A TTUCMOS input logic level is translated into an
output voltage swing that equals the supply and will swing
to within 25 mV of ground or VDD. Input voltage swing may
equal the supply. Logic input current is under 10 !lA, making
direct interface to CMOSlbipolar switch-mode power supply
controllers easy. Input "speed-up" capacitors are not
required.
The CMOS design minimizes quiescent power supply
current. With a logic 1 input, power supply current is 5 rnA
maximum and decreases to 0.5 mA for logic 0 inputs.
For dual devices, see the TC426ITC427ITC428 data
sheet.
For noninverting applications, or applications requiring
latch-up protection, see the TC4420ITC4429 data sheet.
•
•
•
•
High Peak Output Current ................................... 6A
Wide Operating Range ............................. 7V to 18V
High-Impedance CMOS Logic Input
Logic Input Threshold Independent of
Supply Voltage
Low Supply Current
- With Logic 1Input ..•..•....••.................... 5 mA Max
- With Logic 0 Input ............................. 0.5 mA Max
Output Voltage Swing Within 25 mV of Ground
orVoo
Low Delay Time ........................................ 75 ns Max
High Capacitive Load Drive Capability
- tRISE, tFALL 35 ns Max With CLOAO 2500 pF
=
=
APPLICATIONS
•
•
•
•
Switch-Mode Power Supplies
CCD Drivers
Pulse Transformer Drive
Class 0 Switching Amplifiers
TYPICAL APPLICATION
r---------------------------------------~--_1~,8-oVDD
.,'"
TC429
'1
6,7
~
~OUTPUT
INPUT O>-'2'--__-
e
TO. 1I1F
=-
..
e>
=-
0
INPUT
...~
2
~
OUTPUT
T
CL=2500pF
=INPUT
O.4V
18V
OUTPUT
Figure 1
TIMEI1OOft01DIVI
Inverting Driver Switching Time Test Circuit
6-19
SINGLE HIGH-SPEED, CMOS
POWER MOSFET DRIVER
TC429
TYPICAL CHARACTERISTICS CURVES
Rise/Fall Times vs. Supply Voltage
Rise/Fall Times vs. Temperature
60
100
TA = +2S OC
c L = 2500 pF
CL = 2500pF
VOO=+15V
50
00 =+15V
..,40
.5.
~
r--... ...........
~
tF
tR
r-- r--
10
15
SUPPLY VOLTAGE (V)
20
20
~
.:::;;-
10
~~
,. -;:::."
1=1 ~~~~C
25 50 75 100 125 150
TEMPERATURE (OC)
Delay Times vs. Temperature
~
C =2500 pF
&:
::::l
t02
~
I-M""
20
200 kHz
10
~
50
20 kHzl
10K
100
1K
CAPACITIVE LOAO (pF)
Supply Current vs. Frequency
50
«40
V
II:
::::l
(J
~
c..
c..
Vo
20
o
5
V-
4
c
t01
./
_ 10
100
FREQUENCY (kHz)
TA=+25°
~T LOGICI"1..1
V
1K
0
~\
'\\.
~
60
I
~
..... .......
t02-
r-t01
"....
if
80
w
-
10
15
SUPPLY VOLTAGE (V)
20
Supply Current vs. Temperature
VOO=+18O.~~
R -~
4
.....".
ItJr.UT LOGIC" 1"
.........
.......
=18VI
'/'~
.....
1
1=
~
25 50 75 100 125 150
TEMPERATURE (OC)
~~
i)l10
;;;-100
:;;
-SO -25 0
5V
15II: 30
L
V
1
/'
V
.§.
I-
V
/'
V
/
Supply Current vs. Supply Voltage
11l~
TA = +25°C
CL = 2500 pF
40
120
/
i/
Ul
10K
r- TA = +25°C
80
400 kHz
1K
CAPACITIVE LOAO (pF)
Delay Times vs. Supply Voltage
CL = 2500 pF
VOO=+15V
~ 40
30
~
140
.§. 50
(J
1
100
-SO -25 0
IZ
II:
::::l
~
V
~
90
r--~0=+15
tF
....-!: ~ -
30
Supply Current vs. Capacitive Load
70
I.
tF
w
20
«
~=+25°C
50
'"
60
Rise/Fall Times vs. Capacitive Load
60
r--...
...... .....
II
4
8
12
16
SUPPLY VOLTAGE (V)
6-20
20
2
-75-50 -25 0 25 50 75 100 125150
TEMPERATURE (OC)
SINGLE HIGH-SPEED, CMOS
POWER MOSFET DRIVER
TC429
TYPICAL CHARACTERISTICS CURVES (Cont.)
Voltage Transfer Characteristics
20
High Output Voltage vs. Current
400r=--c=~'----r---r--~
TA = +25'C
TA = +25'C
Low Output Voltage vs. Current
400r=--c=~-r---r--~---'
TA=+25'C
HYSTERISIS
~~v
Jmv
-
200mV
o
tf
0.250.500.75 1 1.251.50 1.75 2
INPUT VOLTAGE (V)
o
20
40
60
80
CURRENT SOURCED (rnA)
o
100
SUPPLY BYPASSING
20
40
60
80
CURRENT SUNK (rnA)
100
+lav
Charging and discharging large capacitive loads quickly
requires large currents. For example, charging a 2500 pF
load 18V in 25 ns requires a 1.8A current from the device's
power supply.
To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low-inductance ceramic
disk capacitors with short lead lengths «0.5 in.) should be
used. A 1 IJF film capacitor in parallel with one or two 0.1 IJF
ceramic disk capacitors normally provides adequate bypassing.
lav
O.lI1F
LOGIC
GROUND
)C~~-J ~.---o~
0--.-"
I
+
6A
PC. TRACE RESISTANCE = o.osn
GROUNDING
The high-current capability of the TC429 demands
careful PC board layout for best performance. Since the
TC429 is an inverting driver, any ground lead impedance will
appear as negative feedback which can degrade switching
speed. The feedback is especially noticeable with slow risetime inputs, such as those produced by an open-collector
output with resistor pull-up. The TC429 input structure
includes about 300 mVof hysteresis to ensure clean transitions and freedom from oscillation, but attention to layout is
still recommended.
Figure 2 shows the feedback effect in detail. As the
TC429 input begins to go positive, the output goes negative
and several amperes of current flow in the ground lead. As
little as 0.050 of PC trace resistance can produce hundreds
of millivolts at the TC429 ground pins. If the driving logic is
referenced to power ground, the effective logic input level is
reduced and oscillations may result.
6-21
POWER
GROUND O--L-"
Rgure 2
Switching lime Degradation Due to Negative Faedback
To ensure optimum device performance, separate ground
traces should be provided for the logic and power connections. Connecting logic ground directly to the TC429 GND
pins ensures full logic drive to the input and fast output
switching. Both GND pins should be connected to power
ground.
INPUT STAGE
The input voltage level changes the no-load or quiescent
supply current. The N-channel MOSFET input stage transistor drives a 3 rnA current source load. With a logic "1" input,
the maximum quiescent supply current is 5 rnA. Logic "0"
input level signals reduce quiescent current to 500 JJA maximum.
•
SINGLE HIGH-SPEED, CMOS
POWER MOSFET DRIVER
TC429
The TC429 input is designed to provide 300 mV of
hysteresis, providing clean transitions and minimizing output stage current spiking when changing states. Input voltage levels are approximately 1.5V, making the device TTL
compatible over the 7V to 1SV operating supply range. Input
current is less than 10 ~ over this range.
The TC429 can be directly driven by TL494, SG15261
1527, SG 1524, SE5560 or similar switch-mode power supply integrated circuits. By off-loading the power-driving
duties to the TC429, the power supply controller can operate
at lower dissipation, improving performance and reliability.
POWER DISSIPATION
Quiescent power dissipation depends on input signal
duty cycle. A logic low input results in a low-power dissipation mode with only 0.5 rnA total current drain. Logic high
signals raise the current to 5 mA maximum. The queiscent
power dissipation is:
Pa = Vs (0 (IH) + (1-0) Ill,
where: IH = Quiescent current with input high (5 mA max)
IL = Quiescent current with input low (0.5 rnA max)
o = Duty cycle.
Transition power dissipation arises because the output
stage N- and P-channel MOS transistors are "on" simultaneously for a very short period when the output changes.
The transition package power dissipation is approximately:
CMOS circuits usually permit the user to ignore power
dissipation. Logic families such as the 4000 and 74C have
outputs that can only supply a few milliamperes of current,
and even shorting outputs to ground will not force enough
current to destroy the device. The TC429, however, can
source or sink several amperes and drive large capacitive
loads at high frequency. The packgae power dissipation limit
can easily be exceeded. Therefore, some attention should
be given to power dissipation when driving low impedance
loads and/or operating at high frequency.
The supply current versus frequency and supply current
versus capacitive load characteristic curves will aid in determining power dissipation calculations. Table I lists the maximum operating frequency for several power supply voltages
when driving a 2500 pF load. More accurate power dissipation figures can be obtained by summing the three power
sources.
Input signal duty cycle, power supply voltage, and
capacitive load influence package power dissipation. Given
power dissipation and package thermal resistance, the
maximum ambient operation temperature is easily calculated. The S-pin cerOIP junction-to-ambient thermal resistance is 150°CIW. At +25°C, the package is rated at SOO mW
maximum dissipation. Maximum allowable chip temperature is + 150°C.
Three components make up total package power dissipation:
PT = f Vs (3310-11).
An example shows the relative magnitude for each item.
Example 1:
C =2500pF
Vs = 15V
o =50%
f = 200 kHz
PD = Package power dissipation = Pc + PT + Pa
= 113 mW + 90 mW + 26 mW
=229mW.
Maximum operating temperature = TJ - 6JA (Po)
= 115°C,
where: TJ = Maximum allowable junction temperature
(+150°C)
6JA = Junction-to-ambient thermal resistance
(50°CIW, CerOIP).
NOTE:
(1) Capacitive load dissipation (Pc)
(2) Quiescent power (Pa)
(3) Transition power (PT)
The capacitive load-caused dissipation is a direct function of frequency, capacitive load, and supply Voltage. The
package power dissipation is:
Pc =f C VS2,
where: f = Switching frequency
C = Capacitive load
Vs = Supply Voltage.
6-22
Ambient operating temperature should not exceed +B5°C for
IJA devices or +125°C for MJA devices.
SINGLE HIGH-SPEED, CMOS
POWER MOSFET DRIVER
TC429
Table I. Maximum Operating Frequencies
Vs
fMax
lav
500 kHz
700 kHz
1.3 MHz
>2 MHz
15V
10V
5V
+18V
18V
J;;
1. CerDIP Package (9JA = 150°C/W)
2. TA= +25°C
3. CL = 2500 pF
CONDITIONS:
~. . .~ol
2.4V
O.lIlF
Package Power Dissipation
900
3:
800
~
600
.sz 700
KOVAR LEAD FRAME
CERDIP PACKAGE
8JA 150°C/W
"'-
,,~
"
!!: 500
l$l
is 400
a:
~ 300
~
i
Figure 3
"-
"
200
100
o
25
50
75
100
Peak Output Current Test Circuit
Chip Pad Layout
INPUT (21
""
125
63
150
AMBIENT TEMPERATURE eC)
(8)
Peak Output Current Capability
1~---1Cl4mll
TIME
(sp./Divi
POWER-ON OSCILLATION
It is extremely important that all MOSFET DRIVER
applications be evaluated for the possibility of having
HIGH-POWER OSCILLATIONS occurring during the
POWER-ON cycle.
POWER-ON OSCILLATIONS are due to trace size and
layout as well as component placement. A 'quick fix' for most
applications which exhibit POWER-ON OSCILLATION
problems is to place approximately 10 kQ in series with the
input of the MOSFET driver.
6-23
---.-I
NOTES
6-24
~"'TELEDYNE
COMPONENTS
TC430
FAST CMOS CCD DRIVER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Range ............. 4.5V.;;;: (Voo - Vss)';;;: 12V
nUCMOS-Compatible Inputs
Low Delay Time ...........•....•.•..................... 15 ns Typ
Rise and Fall Times ......... 2200 pF Load, 25 ns Typ
Peak Output Current ............................................ 3A
Output Can Be Floated Below Digital Return
Level Shifting for Split-Supply Operation
Guaranteed Skew
Complementary Outputs
10 MHz Operation With Adequate Heat Sink
Drives 1000 pF at 4 MHz, in CerDIP With No
External Heat Sink (10V Voo- Vss)
Low Output Impedance ................................ 5Q Max
Low Quiescent Current ............................ 5 mA Max
CCD Driver
MOSFET Driver
Laser Diode Driver
Differential Line Driver
PIN Diode Driver
Level Shifting Driver
FUNCTIONAL DIAGRAM
VDD
6
VDD
5
HYSTERESIS
OUTPUT
Vo 2 (Q)
TO DIGITAL
RETURN
~'"
TC430
VDD
7. OUTPUT
V01
DIGITAL
RETURN
3
TO DIGITAL
RETURN
vss
OUTPUT
RETURN
1020·1
6-25
(0)
FAST CMOS CCD DRIVER
TC430
GENERAL DESCRIPTION
The TC430 is a super-fast CMOS power driver for
driving CCDs and other loads. The TC430 operates at
frequencies to 10 MHz and drives loads greater than 2200 pF.
Peak current output is 3A.
The input is TTUCMOS compatible. Digital return and
output return can be at different Voltages, allowing operation
with output swings between positive and negative supplies
without sacrificing AC performance when driven from TTL.
The ability to swing negative is important when driving CCD
devices.
The output stages have been designed so the rising
edge of one output crosses the 50% point of the transition
within 5 ns of the other. This makes the TC430 ideal for
driving CCDs and achieving high contrast images.
CMOS construction achieves low quiescent power (less
than 5 rnA at 15V and 25°C) and low input current requirements. This device requires fewer external components
than bipolar devices like the DS0026 which need external
speed-up capacitors.
ORDERING INFORMATION
Part No.
Package
TC430CPA
TC430lJA
TC430MJA
8-Pin Plastic
8-Pin CerDIP
8-Pin CerDIP
Temperature
Range
O°Cto +70°C
-25°C to +85°C
-55°C to + 125°C
PIN CONFIGURATION
DIGITAL
GROUND
NC
7 V0 1 (Q)
VDD
5 V02 (Q)
BONDING DIAGRAM
NOTES:
1. Back of die is common to Voo.
2. Bak if die is not metalized
6-26
FAST CMOS CCD DRIVER
TC430
ABSOLUTE MAXIMUM RATINGS
Power Dissipation at +25°C
Plastic .......................................................... 1000 mW
CerDIP ........................................................... 800 mW
Derating Factors
Plastic ........................................................... 8 mW/oC
CerDIP ....................................................... 6.4 mW/oC
Supply Voltage ....................................... Voo - Vss .;; 15V
Voo - VOR';; 15V
Input Voltage, Any Terminal ............................. Voo +O.3V
Operating Temperature Range
M Version ......................................... -55°C to + 125°C
I Version ............................................. -25°C to +85°C
C Version ............................................... O°C to +70°C
Maximum Chip Temperature ................................... 150°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................... 300°C
CerDIP Re-JA ....................................................... 150°CIW
Plastic RS-JA ....................................................... 125°CIW
ESD Protection ........................................................ 2000V
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: TA =+25°C with 4.5V .;; (Voo - VOR) .;; 12V, 4.5V .;; (Voo - VSS) .;; 12V
Symbol
Parameter
VIH
Logic 1, High Input Voltage
VIL
Logic 0, Low Input Voltage
liN
Input Current
VOH
High Output Voltage
VOL
Low Output Voltage
Ro
Output Resistance
Test Conditions
Min
Typ
2.4
1.6
1.3
OV.;; VIN';; Voo
-10
Max
Unit
V
0.8
V
10
itA
V
Voo-O.025
Vss+0.025
V
VIN = OV, lOUT = lOrnA, Vss = OV,
Voo= 12V
3
5
n
=lOrnA, Vss = OV,
3
5
n
VIN = 3V, lOUT
Voo= 12V
IpK
Peak Output Current
Voo= 12V
3
tSKEW1
Output Pulse Skew
Figure 2
3
5
IsKEW2
tR
Output Pulse Skew
Figure 2
3
5
ns
Rise Time
22
30
ns
tF
Fall Time
Figure 1
CL = 2200 pF, Voo = 12V
Figure 1
CL = 2200 pF, Voo = 12V
22
30
ns
ns
A
ns
t01
Delay Time
Figure 1
18
25
t02
Delay Time
Figure 1
18
25
ns
Is
Quiescent Power Supply
Current
VIN = 3V, Voo = 12V, Vss = OV
VIN = OV, Voo = 12V, Vss = OV
2.9
5
0.3
mA
mA
NOTE: Switching times are guaranteed by design.
6-27
FAST CMOS CCDDRIVER
TC430
ELECTRICAL CHARACTERISTICS: 4.5V.;; (Voo - VORl .;; 12V; 4.5V .;; (VOO - Vss) .;; 12V, TA =-55OC to +125°C
Symbol
Parameter
VIH
Logic 1, High Input Vonage
VIL
Logic 0, Low Input Vonage
liN
Input Current
VOH
High Output Voltage
VOL
Low Output Vonage
Ro
Output Resistance
Test Conditions
Min
Typ
Max
2.4
V
-10
OV';; VIN';; Voo
Unit
0.8
V
10
j.lA
V
Voo-O·025
Vss+0.025
V
VIN = OV, lOUT = 10 mA, Vss = OV,
Voo= 12V
4.5
7
n
VIN = 3V, lOUT = 10 mA, Vss = OV,
Voo= 12V
4.5
7
n
IpK
Peak Output Current
Voo = 12V
3
tSKEW1
Output Pulse Skew
Figure 2
5
10
ns
tSKEW2
Output Pulse Skew
Figure 2
5
10
ns
tR
Rise Time
Figure 1
CL = 2200 pF, Voo = 12V
40
ns
tF
Fall Time
Figure 1
CL = 2200 pF, Voo = 12V
40
ns
ns
A
t01
Delay Time
Figure 1
35
too
Delay Time
Figure 1
35
ns
Is
Quiescent Power Supply
Current
VIN = 3V, Voo = 12V, Vss = OV
VIN = OV, Voo = 12V, Vss = OV
8
0.5
rnA
rnA
5
NOTE: Switching times are guaranteed by design.
VDD
VSS
Vss
Figure 1
Driver Switching TIme
Figure 2
6-28
Output Drive Skew
FAST CMOS CCD DRIVER
TC430
TEST CIRCUIT
o.k't
O.1IJF
CERAMIC
F
CERA IC
INPUT
BNC
•
21
51Q
DIGITAL
RETURN
•
•
1,•
I
---- 3
V01
•
•
•15
•
TC430
____ J •
V02
CLOAD
CLOAD
(2) A minimum 4.SV must be rnaintained between
digital retum and Voo.
(3) Decoupling between Voo and Vss is critical.
(4) Single-point (star) ground systems should be used.
APPLICATIONS INFORMATION
Functional Description
The TC430 is fabricated with a super-fast silicon gate
process. The input stage consists of a Schmitt trigger
which drives a level shift circuit. The level shift circuit allows
the input signal to be referenced to some point other than
the output retum, pin 3 (Vss). This allows the output to swing
positive and negative relative to the digital return (pin 1).
The output stage is a low-impedance MOSFET totem
pole that can source or sink currents up to 3A peak. This type
of output can swing to within millivolts of either rail when
driving capacitive loads. Output rise times are on the order
of 3 ns, while propagation delays are in the 1S ns region.
For decoupling between digital return and Voo [item (1)
above] a 1 iJ.F SOV polyester film cap (such as a Wima
MKS-2) in parallel with a multilayer ceramic 0.1 iJ.F SO X7R
(such as an AVX dip guard) will work well. These capacitors have to be mounted as close as possible to the respective pins on the TC430 to minimize circuit inductance.
Circuits that are improperly decoupled will exhibit oscillations on the output.
A minimum 4.SV between digital return and Voo [item
(2) above] is necessary to ensure that the level shifting and
hysteresis circuits have enough voltage to function properly. Put another way, the input circuit is referenced to the
positive supply, not the negative supply.
Decoupling of the Vss to Voo [item (3) above] is important because of the high peak current catlability of the
output of the TC430. The suggested decoupling is a low
ESR polyester film capacitor (such as the 1 iJ.F 50V MKS2) and a ceramic capacitor (such as the AVX 0.1 iJ.F 50V
dip guard).
Application Tips
Due to its high speed and short transition times, proper
layout of the PC board is critical. See Application Note 28
for further information on the effects of layout.
Additional precautions that must be made in addition to
those in Application Note 28 are:
(1) Decoupling between the digital return and Voo is
critical.
6-29
FAST CMOS CCD DRIVER
TC430
Delay Time vs Voo
Delay Time vs Temperature
25.0
55
\
50
45
\
~ 35
VOO=12V
22.5
\
~.7VIN
~ 30
.,
\
w
c 25
- --
"- ~VIN
......... r-..
20
c
r--
4.5VIN f - -
--
6
VOO
8
10
.... ~ - ' ......
12.5
10.0
7.5
~o
12
NOTE: Digital return tied to Vss.
-40 -20
0 20 40 60 80 100 120 140
TEMPERATURE ('C)
NOTE: Digital return tied to Vss.
Supply Current vs Frequency
Rise/Fall Times vs Temperature
50
87.5
CLOAO = 200 pF
VOo= 12V
45
/
w
::;;
>=
tF /
-
25
20
15
67.1
V
35
30
~
:::. ;...-
/
"/
~
V
1
'/
TC430 (CerOIPjI
~ 46.7
D.
D.
tR
V
~
26.3
10
~
5
~o
-40 -20
V
VOO - V DO = 10V (NO OUTPUT LOAD)
40
.,.:-
t01
I-
2.5
6VIN
4
.-- ~~
5.0
~ t----
15
2
,.
::;;
>=
>
~
l,...--' ...-
17.5
;; 15.0
\
>=
t01
20.0
5.9
0.5
0 20 4060 80 100 120 140
TEMPERATURE eC)
NOTE: Digital return tied to Vss.
6-30
/
/
1.9
3.2
4.6
5.9
7.3
FREQUENCY (MHz)
8.6
10
FAST CMOS CCD DRIVER
TC430
Input Signal Considerations
The parallel combination of the two capacitors forms a
low-impedance source of power across a broad frequency
range for the output stage. This will ensure that for any load
and frequency of operation the output will be as "clean" as
is practical.
The use of single-point grounds [item (4) above] is very
critical. Due to the high peak currents that the TC430 is
capable of generating, any additional trace or wire length
can cause L di/dt drops that can effect the output and in the
extreme cause the device to fail due to voltage breakdown.
Application Note 28 explains parasitic inductance problems further.
The amplitude of the input signal has a significant
effect on the propagation delay through the IC.
While the device can be driven with a signal as small
as 2V, propagation delays will be in the 40 ns region. If the
input is increased to 5V, delays will be in the 15 ns region.
The input stage of the TC430 is a MOSFET gate. Thus,
it is of high impedance and requires little drive current. This
eliminates the need for speed-up capacitors as with older
bipolar parts. The use of speed-up capacitors is not recommended, as they can cause voltage-doubling effects that
can be detrimental to the life of the device.
Operation From a Single Supply
Table I Maximum Operating Frequency
Max Frequency
Vs
If the TC430 is operated from a single supply voltage,
the digital return pin must be tied to the Vss pin. This eliminates the need for the decoupling capacitors from VDD to
digital return.
12V
10V
5V
4MHz
9.1 MHz
20 MHz
Conditions: 1. CerDIP Package (8JA = 150'CIW)
2. TA =25'C
3. No load
Load Return Path
It is very important to return the load currents directly to,
and in the shortest possible distance to V ss, pin 3. Again, this
is due to the parasitic inductance of the PC board trace or
wire. The test circuit shows how the load capacitors, CLOAD,
are returned to the same point as the decoupling capacitors
which is directly on pin 3.
Crossover Energy Loss
10-41
1000
NOIP
SLOPE = -41 mWI'C
.."..,..
800
./
V
/
L
~
['... I'\.
p~ "ag~ ~werD ssipat on
~ 600
~~
!.
V
rP 400
200
10-9
~" L'\.
CerOIP
,;::-...
SLOPE = -6.4 mWI'C
I"''
..... ~
o
4
6
8
10
12
14
25
16
VSUPPLY (Voo-ISS>
6-31
50
75
100
125
AMBIENT TEMPERATURE ('C)
"
150
FAST CMOS CCD DRIVER
TC430
APPLICATIONS
TIL
CLOCK IN
5
01
7
02
TIL
START IN
2kn
112 7474
7
~--->---t-o
soon
VIDEO CLOCK DRIVER FOR CCD CAMERA
-8V
6-32
TIMING SIGNAL OUT
"''''TELEDYNE
COMPONENTS
TC4401
6A OPEN-DRAIN MOSFET DRIVER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC4401 is a CMOS buffer-driver constructed with
complementary MOS outputs, where the drains of the final
output totem pole have been left disconnected so individual connections can be made to the pull-up and pulldown sections of the output. This allows the insertion of
individual drain current-limiting resistors in the pull-up and
pull-down sections of the output, thus allowing the user to
define the rates of rise and fall times desired for a capaci·
tive load, or a reduced output swing if driving a resistive
load, orto limit base current when driving a bipolar transistor.
Minimum rise and fall times, with no resistors, will be less
than 30 ns for a 2S00-pF load. There is no upper limit.
For driving MOSFETs in motor·control applications,
where slow-onlfast-off operation is desired, the TC4401 is
superior to the previously-used technique of adding a dioderesistor combination between the driver output and the
MOSFET, because it allows accurate control of turn-on,
while maintaining fast turn-off and maximum noise immunity
for the device being driven.
When used to drive bipolar transistors, this driver
maintains the high speeds common to other Teledyne
drivers and allows insertion of a base current-limiting
resistor, while providing a separate half-output for fast turnoff. By proper positioning of the resistor, either npn or pnp
transistors can be driven.
Independently-Programmable Rise and Fall Times
High Peak Output Current ••......•..•••.......•.... 6A Peak
Low Output Impedance ..•...•...•....•..•......... 2.S0 Typ
High Speed tR, tF ••...•...•.. <30 ns with 1800 pF Load
Short Delay Times .................................•..• SSns Typ
Wide Operating Range .......................... 4.SV to 18V
APPLICATIONS
•
•
•
•
•
Motor Controls
Self-Commutating MOSFET Bridge Driver
Driving Bipolar Transistors
Driver for Nonoverlapping Totem Poles
Reach-Up/Reach-Down Driver
RUGGED
•
•
•
•
Tough CMOS Construction
Latch-Up Protected: Will Withstand >1.S rnA
Reverse Current (Either Polarity)
Input Withstands Negative Swings Up to -SV
ESD Protected .....•..........•.......•.......•.......•..••......•• 4kV
FUNCTIONAL DIAGRAM
1,8
r------.-----------------------------------------.---QVDD
2mA
7
1----0 PULL UP
6
1----0 PULL DOWN
I
2
INPUTo--..................~
4.7V
,,
,
4,5
"'' '
TC4401
:
GND~~~--~~--~----------------------------------------~
EFFECTIVE
INPUT
C=38pF
6-33
6A OPEN-DRAIN MOSFET DRIVER
TC4401
For driving many loads in low-power regimes, this
driver, because it has very low quiescent current «150 iJA)
and eliminates shoot-through currents in the output stage,
requires significantly less power than similar drivers, and
can be helpful in meeting low-power budgets.
Because neither drain in an output is dependent on the
other (though they do switch simultaneously), this device
can also be used as an open-drain buffer/driver where both
drains are available in one device, thus minimizing chip
count. An unused open drain should be returned to the
supply rail its device source are connected to (pull-down to
ground, pull-up to VDD) , to prevent static damage. Alternatively, in situations where timing resistors, or other means of
limiting crossover currents are used, multiple TC4401 's may
be paralleled for greater current-carrying capacity.
The TC4401 is built using Teledyne Components' new
Tough CMOS process and is capable of giving reliable
service in the most demanding electrical environments: it
will not latch under any conditions within its power and
voltage ratings; it is not subject to damage when up to 5V of
noise spiking of either polarity occurs on the ground pin; and
it can accept, without damage or logic upset, up to 1.5 amp
of reverse current (of either polarity) being forced back into
the outputs. All terminals are fully protected against up to
2 kV of electrostatic discharge.
ORDERING INFORMATION
Part No.
Logic
Package
TC4401CPA
TC4401EPA
TC4401COA
TC4401EOA
TC44011JA
TC4401MJA
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
8-Pin
Temperature Range
PDIP
PDIP
SOIC
SOIC
CerDIP
CerDIP
O°Cto +70°C
-40°C to +85°C
O°C to +70°C
-40°C to +85°C
-25°C to +85°C
-55°C to +125°C
PIN CONFIGURATIONS
sOle
DIP
VDD
VDD
INPUT
PULL UP
NC
PULL DOWN
NC
GND
GND
NC = NO CONNECTION
NOTE:
1. Duplicate pins must both be connected for proper operation.
6-34
VDD
PULL UP
PULL DOWN
GND
6A OPEN-DRAIN MOSFET DRIVER
TC4401
ABSOLUTE MAXIMUM RATINGS
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
Supply Voltage .......................................................... +22V
Input Voltage ............................ Voo + O.3V to GND - 5.0V
Input Current (VIN > Voo) ......................................... 50mA
Power Dissipation, T A ,,;25°C
PDIP ...................................................................... 1W
SOIC ............................................................... 500mW
CerDIP ............................................................ 800mW
Derating Factors (To Ambient)
PDIP ............................................................. 8 mW/oC
SOIC ............................................................. 4 mW/oC
CerDIP ....................................................... 6.4 mW/oC
Storage Temperature Range .................. -65°C to + 150°C
Maximum Chip Temperature ................................. + 150°C
Operating Temperature Range
C Version ............................................... O°C to +70°C
I Version ............................................. -25°C to +85°C
E Version ........................................... -40°C to +85°C
M Version ......................................... -55°C to +125°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
ELECTRICAL CHARACTERISTICS: TA = +25°C with 4.5V '" Voo'" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
1.8
-
V
VIL
Logic 0 Low Input Voltage
-
1.3
0.8
V
VIN (Max)
Input Voltage Range
-5
-
Voo+0.3
V
liN
Input Current
OV", VIN '" Voo
-10
-
10
~A
VOH
High Output Voltage
See Figure 1
Voo-0.025
V
Low Output VOltage
See Figure 1
-
-
-
VOL
0.025
V
Ro
Output Resistance, High
lav
IOUT= 10 rnA, Voo = lav
-
2.1
2.8
-
1.5
2.5
n
n
Output
Ro
Output Resistance, Low
IpK
Peak Output Current
IREV
Latch-Up Protection
Withstand Reverse Current
lOUT = 10 rnA, Voo =
Voo= 18V
Duty Cycle", 2%
t '" 300 ~s
>1.5
6
-
-
-
A
A
25
35
ns
25
35
ns
55
75
ns
55
75
ns
I
1.5
150
rnA
I ~A
-I
18
IV
SWltchmg Time (Note 1)
tR
Rise Time
Figure 1, CL = 2500 pF
tF
Fall Time
Figure 1, CL = 2500 pF
t01
Delay Time
Figure 1
-
t02
Delay Time
Figure 1
-
Power Supply
Is
Power Supply Current
Voo
Operating Input Voltage
0.45
55
4.5
NOTE: 1. Switching times guaranteed by design.
6-35
6A OPEN-DRAIN MOSFET DRIVER
TC4401
ELECTRICAL CHARACTERISTICS:
Measured over operating temperature range with 4.SV "" Voo "" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
-
-
V
-
0.8
V
Max
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
VIL
Logic 0 Low Input Voltage
-
VIN (Max)
Input Voltage Range
-5
liN
Input Current
OV .. VIN" Vs
VOH
High Output Voltage
See Figure 1
VOL
Low Output Voltage
See Figure 1
Ro
Output Resistance, High
IOUT= 10
Voo = 18V
-
Ro
Output Resistance, Low
IOUT=
Voo = 18V
-10
Voo+O.3
V
10
ILA
-
V
Output
rnA,
10 rnA.
Voo-0.025
-
-
0.025
V
3
5
Q
-
2.3
5
Q
-
32
60
ns
34
60
ns
-
50
100
ns
65
100
ns
-
SWitching Time (Note 1)
tR
Rise Time
Figure 1, CL = 2500 pF
tF
Fall Time
Figure 1, CL = 2500 pF
t01
DelilyTime
Figure 1
too
Delay Time
Figure 1
Power Supply
Is
rnA
Power Supply Current
ILA
Voo
Operating Input Voltage
V
NOTE: 1. Switching times guaranteed by design.
Voo= 1av
~ 11'F
a
+5V
INPUT
OUTPUT
1ev
OUTPUT
OV
5
100 kHz SQUARE WAVE
TRISE = TFALL" 10ns
Figure 1. Switching Time Test Circuit
6-36
6A OPEN-DRAIN MOSFET DRIVER
TC4401
TYPICAL CHARACTERISTICS CURVES
Rise Time vs Supply Voltage
120
100
.,..:.
w
::;:
"
"
i"-....
60
-
;::
40
0 5
,..,dl
9
c l l=
2~00 ~F
13
11
Voo(V)
o
15
5
.,.
.:.
100
100
BO
80
~
./
,
40
/ ~
w
::;:
;::
VOO=l~
,
20
r-.. .....
7
Cl l= 4~00
--
......;
tFAll
w
~F
~
~
~'"
20
13
9
11
Voo(V)
~40 - V o o i r
o
-20
~o
15
V
L
Cl= 2200 pF
voo= 18V
..
40
.1
f- 102
.:.
r- 7
;::
i--'
w 30
::;:
>-
.:3
w
""'"
-
l,...--' ..".
....}-'"
_r'"
101
""'"
..... I-L
~
r\.
iil45
10
1000
1000
f--
«
V
zw
::::l
10
til
20
60
TA("C)
100
6
140
8
10
12
14
16
SUPPLY VOLTAGE (V)
18V
,/
I-
z 100
56
w
>..J
ill
28
~
14
Il.
Il.
-t1r
~~kHJ.
100
1000
CAPACITIVE LOAD (pF)
6-37
/
/
10
::::l
til
~~HZ
o
10V
5V
II:
II:
::::l
0
500kHz"
o
18
=
<-
Il.
-20
4
.§.
o
i
102
..............
Cl= 2200 pF
II:
II: 42
::::l
c
~O
Voo=15V
70
.§.
I-
140
Supply Current vs Frequency
84
20
o
35
10,000
Supply Current vs Capacitive Load
~
100
"' ~
c
CAPACITIVE LOAD (pF)
,/
20
60
TA ("C)
!55 \
w
~ 50 \ I'"
..-:: ....
~~
Voo=~ ~o=18V
CAPACITIVE LOAD (pF)
50
IRISE
60
V
40
Propagation Delay Time
vs Temperature
-
Propagation Delay Time
vs Supply Voltage
20
10,000
~
10
~
w
10
1000
~
65
::;:
;::
VVoo= 18V
...-
I-- ~ :;:::..
Cl= 2200 pF
60
./
Voo=5Y
.,. 30
.:.
Fall Time vs Capacitive Load
Rise Time vs Capacitive Load
60
= 10,000 pF
.........
r-- I -
20
I I I
I I I
~C l
.....
w
::;:
;:: 40
I
40
r-...
-
.,. 60
.1.
Cl = 2200 pF
VOO= 18V
i""-.."
.:.
..... ~=4700pF
-
~
BO
I I I
r7
=ll0,~0 ~F
1
Rise and Fall Times vs Temperature
........
.........
....... r-...
r-
20
I I I
I I I
........
BO
Fall Time vs Supply Voltage
100
10,000
/
o
o
100
1000
FREQUENCY (kHz)
10,000
6A OPEN-DRAIN MOSFET DRIVER
TC4401
TYPICAL CHARACTERISTICS CURVES (Cont.)
Quiescent Power Supply
Current vs Supply Voltage
Quiescent Power Supply
Current vs Temperature
20
5
LOGIC "1" INPUT
LOGIC "0" INPUT
VtJo= 18V
I-
ffi
a:
a:
4
700
I
~
Q.
Q.
::;)
til
100
200
300
400
SUPPLY CURRENT (IIA)
~
,
-20
200
~
f" ~
2
!
iIII..
~N:Ar
o
a:
1.5
1°iA
1
5
7
9
11
Voo(V)
13
~
15
3
!lij120
i=
140
LOAD = 2200 pF
5
w
80
i::!NPur~
r-...
INPUT3V
.......
c
40
o
i,...--
5
...... ..... '"
/
-
...... ,-INPUT5V
I~P~T 8y A~DJOV
6
7
8
9 10 11 12 13 14 15
Voo (V)
6-38
,
SOmA
~
"
~
20
60
100
TEMPERATURE ('C)
160
'100mA
9....
::J
~~
"Ilj
V
Effect of Input Amplitude
on Propagation Delay
Low-State Output Resistance
2.5
-
I
1/'"
500
400
-60
500
I
~omA
V
600
....I
/
~
10m~
/
::;)
I{
--
~
.:!:
I
o
~
--~I----""'-o OUTPUT
10 kO
+5V
+5V
INPUT
INPUT
= 0.4V·
= 0.4V
16V
16V---~~
OUTPUT
OUTPUT
ov-----'i
OV
Figure 1 Switching lime Test Circuits
6-44
90%
1.SA HIGH-SPEED,
FLOATING LOAD DRIVER
TC4403
TYPICAL CHARACTERISTICS CURVES
Rise Time vs Supply Voltage
100
47~0;PF
80
ffi
T =+25°C-
...... r.......
.... ..........
20
4
6
.......
8
......
2200 pf""'oo.,
;;!
.,!l- 40
1500 pF
1000 pF
10
12
14
16
,
..... ........
----
..J
470 ~F
o
I\..
3300 F.........
'iii 60
oS
-- --
22,2.0 pF'-
40
T
-1
TA=+25°C-
~I,P
80
)..
33~lpF'
'iii 60
oS
w
U>
Fall Time vs Supply Voltage
100
....
20
r-.
o
18
4
6
10
8
VOO
IT
80
ffi
40
100
1/.11
II 11h~
IJ' ",
1/ jrj 15V
./ / /
.,!l- 40
A
~
20
o
100
1000
100
10,000
1000
Propagation Delay vs
Input Amplitude
Rise and Fall Times vs
Temperature
I
100
'iii
oS 80
>
~
60
c 40
~I::::::,
-1--+--+-+--+-+-1
18L-~-L~~~-L~--~~~
45
= 10V
f-J-.
\\
w
22~4=~~~+-~-+--~~~
25
VOO
j::
~ 24
5
+-
1
:;
w
-55 -35 -15
~OAO = 2200 pF _
I
t01 J-.
f- f-
w
!26~4-~-+--~+-~~
tFALL
10,000
CLOAO (pF)
C LOAO (pF)
20
,tir
..J
..J
0(
/ I)rt 15V
./ /v
o
18
II
'iii 60
oS
1/,10V
I II
I,
16
I
80
II
20
I
TA=+25°C
5V
U>
14
Fall Time vs Capacitive Load
Rise Time vs Capacitive Load
60
12
VOO
100
'iii
oS
w
1500 pF
1000 pF
470
20
65 85 105 125
o
1
2
3
4
t02
5
6
7
INPUT (V)
TEMPERATURE (OC)
6-45
8
9 10 11 12
1.SA HIGH-SPEED,
FLOATING LOAD DRIVER
TC4403
TYPICAL CHARACTERISTICS CURVES (Cont.)
Delay Time vs Temperature
Delay Time vs Supply Voltage
50
50
....:.
w
:::i
i=
>
35
c
30
:3w
"
45
!w
~
40
~~
.........
:::i
i=
to2
~
w
~
t02
c
40
35
V
30
25
25
20
"/
.....
-
.,., V
V
20
4
6
8
10
12
14
16
...-
CLOAO = 2200 pF
C LOAO= 2200 pF
TA =+25'C
~
45
~5~5~5
18
5
V
i-"'""
~
~
:.;r
~
~
V
/"
$1~1~
TEMPERATURE (OC)
VOO
Quiescent Current vs Temperature
1.4
Quiescent Current vs Voltage
TA = +25°C -
1.2
~OTHIINPU~S = 11 -
;;C
.§.
1
z
w 0.8 r-- en 0.6
w
5
INPUTS = 1
0.2 I-- -
INPUTS = 0
~
en
0.0
-55
0.01
4
6
8
10
12
14
16
18
VOO
Z
Q.
en
0
rr
......
4
2
4
I"-,...
6
WbRS)CAS~: -
--
TYP
=-t:
8
(GNO)
"- ~TJ=+150'C
8
6
;"+-+-IN
(V DO)
"\ .....
10
-15 5 25 45 65 85 105 125
TEMPERATURE (OC)
IN
14
12
~5
BONDING DIAGRAM
Output Resistance vs
Supply Voltage
i\.
V
.E 0.4
BOTH INPUTS = 0
0.1
.E
§:
-...- I--"'"
()
IZ
~
/'
1.0
I-
10
12
14
r-
16
18
(V OO)
VOO
NOTES: 1. Back of die is not metallized.
2. Back of die is common to V DD•
3. Dual bond pads must BOTH be connected.
6·46
~"'TELEDYNE
COMPONENTS
TC4404
TC440S
1.SA DUAL OPEN-DRAIN MOSFET DRIVERS
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The TC4404 and TC4405 are CMOS buffer-drivers
constructed with complementary MOS outputs, where the
drains of the final output totem pole have been left
disconnected so individual connections can be made to the
pull-up and pull-down sections of the output. This allows
the insertion of individual drain-current-limiting resistors in
the pull-up and pull-down sections of the output, thus allowing the user to define the rates of rise and fall desired
for a capacitive load, or a reduced output swing if driving a
resistive load, or to limit base current when driving a bipolar
transistor. Minimum rise and fall times, with no resistors,
will be less than 30 ns for a 1000-pF load. There is no
upper limit.
For driving MOSFETs in motor-control applications,
where slow-onlfast-off operation is desired, these devices
are superior to the previously-used technique of adding a
diode-resistor combination between the driver output and
the MOSFET, because they allow accurate control of turnon, while maintaining fast turn-off and maximum noise
immunity for an OFF device.
When used to drive bipolar transistors, these drivers
maintain the high speeds common to other Teledyne drivers and allow insertion of a base current-limiting resistor,
while providing a separate half-output for fast turn-off. By
proper positioning of the resistor, either npn or pnp transistors can be driven.
Independently-Programmable Rise and Fall Times
Low Output Impedance ................................ 70. Typ
High Speed tR. tF ••.•.•.••..• <30 ns with 1000 pF Load
Short Delay Times
Wide Operating Range ..•.•...•..•..•••..••..•.. 4.5Vto 18V
APPLICATIONS
•
•
•
•
•
Motor Controls
Self-Commutating MOSFET Bridge Driver
Driving Bipolar Transistors
Driver for Nonoverlapping Totem Poles
Reach-Up/Reach-Down Driver
RUGGED
•
•
•
Tough CMOS™ Construction
Latch-Up Protected: Will Withstand >500 mA
Reverse Current (Either Polarity)
Input Withstands Negative Swings Up to -5V
FUNCTIONAL DIAGRAM
~--~---------------------------------------4~~1GVDD
"""
.rt>l.~~
TC4404
r
i
INPUT 0-:2:...>(",,3)'---41---*---'
V-
~~PULLDOWN
"""
TC4405
,,
,
:
GND~4~~~-*----~--------------------------------------~
EFFECTIVE
INPUT
C 12pF
1023-1
A (B)
6-47
eo,,",
-=_
1.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
For driving many loads in low-power regimes, these
drivers, because they eliminate shoot-through currents in the
output stage, require significantly less power at higher frequencies, and can be helpful in meeting low-power budgets.
Because neither drain in an output is dependent on the
other, these devices can also be used as open-drain buffer1
drivers where both drains are available in one device, thus
minimizing chip count. Unused open drains should be
returned to the supply rail their device sources are connected
to (pull-downs to ground, pull-ups to VDD), to prevent static
damage. In addition, in situations where timing resistors, or
other means of limiting crossover currents are used, like
drains may be paralleled for greater current carrying capacity.
These devices are built using Teledyne Components'
new Tough CMOS process and are capable of giving reliable service in the most demanding electrical environments:
they will not latch under any conditions within their power
and voltage ratings; they are not subject to damage when up
to 5V of noise spiking of either polarity occurs on their
ground pin; and they can accept, without damage or logic
upset, up to 1/2 amp of reverse current (of either polarity)
being forced back into their outputs. All terminals are fully
protected against up to 2 kV of electrostatic discharge.
ORDERING INFORMATION
Part No.
Logic
Package
TC4404CPA
TC4404COA
TC4405CPA
TC4405COA
TC4404EPA
TC4404EOA
TC4405EPA
TC4405EOA
TC4404MJA
TC4405MJA
Inverting
Inverting
Noninverting
Noninverting
Inverting
Inverting
Noninverting
Noninverting
Inverting
Noninverting
8-Pin PDIP
8-PinSOIC
8-Pin PDIP
8-Pin SOIC
8-Pin PDIP
8-Pin SOIC
8-Pin PDIP
8-Pin SOIC
8-Pin CerDIP
8-Pin CerDIP
ABSOLUTE MAXIMUM RATINGS
Temperature Range
O°Cto +70°C
O°Cto +70°C
O°Cto +70°C
O°Cto +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
Supply Voltage .......................................................... +22V
Maximum Chip Temperature ................................. + 150°C
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Package Thermal Resistance
CerDIP RaJ·A ................................................ 150°CIW
CerDIP RaJ.c .................................................. 55°CIW
PDIP RaJ.A ................................................... 1250CIW
PDIP RaJ.c ..................................................... 45°CIW
SOIC RaJ-A ................................................... 250°C/W
SOIC RaJ-C ..................................................... 75°C/W
Operating Temperature Range
C Version ............................................... O°C to +70°C
E Version ........................................... -40°C to +85°C
M Version ......................................... -55°C to +125°C
Package Power Dissipation
1000~---r----r----.----r---.
BOOk---~----+-----~--~---1
~ 600 k----+---~l---'~-+----+---_I
,p 400 1------""'!oo.:---+-~...3ooC----t---l
200
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
50
75
100
125
AMBIENT TEMPERATURE (OC)
6·48
150
1.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
POWER-ON OSCILLATION
It is extremely important that all MOSFET DRIVER applications be evaluated for the possibility of having HIGHPOWER OSCILLATIONS occurring during the POWER-ON cycle.
POWER-ON OSCILLATIONS are due to trace size and layout as well as component placement. A 'quick fix' for most
applications which exhibit POWER-ON OSCILLATION problems is to place approximately 10 kn in series with the input of
the MOSFET driver.
ELECTRICAL CHARACTERISTICS:
Specifications measured at TA = +25°C with 4.5V ~ Voo ~ 1BV, unless otherwise specified.
Symbol
Test Conditions
Parameter
Min
Typ
-
I Max
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
VIL
Logic 0 Low Input Voltage
-
liN
Input Current
-5V ~ VIN ~ Voo
-1
0.8
1
V
V
!LA
Output
VOH
High Output Voltage
Voo-0.025
-
VOL
Ro
Low Output Voltage
-
IpK
Peak Output Current
Any Drain
-
loc
IR
Continuous Output Current
Any Drain
-
Latch-Up Protection
Any Drain
Withstand Reverse Current
V
V
10
n
1.5
-
A
-
100
mA
>500
-
-
mA
Figure I, CL
-
25
30
ns
Figure 1, CL
-
25
30
ns
-
-
30
ns
-
-
50
ns
lOUT = 10 mA, Voo = 18V; Any Drain
Output Resistance
0.025
7
SWitching Time (Note 1)
tR
Rise Time
tF
Fall Time
t01
Delay Time
t02
Delay Time
=1000 pF
=1000 pF
Figure I, CL =1000 pF
Figure 1, CL =1000 pF
Power Supply
Is
Power Supply Current
VIN
VIN
NOTE:
=3V (80th Inputs)
=OV (80th Inputs)
mA
mA
1. Switching times guaranteed by design.
PIN CONFIGURATIONS
Voo
DIP
SOIC
.,'"
TC4404
1 •
.,'"
TC4404
BBOTTOM
.,'"
.,'"
TC4405
TC4405
6-49
1.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
ELECTRICAL CHARACTERISTICS: Specifications measured over operating temperature range
with 4.5V :s; VDD :s; 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input
VIH
VIL
Logic 1 High Input Voltage
Logic 0 Low Input Voltage
liN
Input Current
2.4
-10
-5V $ VIN:S; Voo
-
-
0.8
V
V
10
IlA
-
V
V
Output
IDe
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Continuous Output Current
IR
Latch-Up Protection
VOH
VOL
Ro
IpK
Voo-0.025
-
=
lOUT 10 mA, Voo
Any Drain
Any Drain
=18V; Any Drain
-
>500
Any Drain
Withstand Reverse Current
9
0.025
12
1.5
-
n
100
A
mA
-
-
mA
-
40
40
40
ns
ns
ns
60
ns
-
Switching Time (Note 1)
tR
tF
t01
t02
Rise Time
Fall Time
Delay Time
Figure
Figure
Figure
Figure
Delay Time
1,
1,
1,
1,
CL = 1000
CL = 1000
CL = 1000
CL = 1000
-
pF
pF
pF
pF
-
-
-
-
Power Supply
Is
NOTE
=
Power Supply Current
VIN 3V (Both Inputs)
VIN = OV (Both Inputs)
mA
mA
1. Switching times guaranteed by design.
+SV
INPUT
=0.4
VDD=18V
:r: 0.1
':'
10%
18V
jlF
OUTPUT
':"
OV
2,3
INPUT o--t--I
INVERTING DRIVER
+sv - - - - -r-----'\I
INPUT
=0.4V'_...l.10~%::...J!
4
18V - - OUTPUT
OV
-----'I
NONINVERTING DRIVER
Figure 1
Switching Time Test Circuit
6-50
1.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
TYPICAL CHARACTERISTICS CURVES
Rise Time vs. Supply Voltage
Fall Time vs. Supply Voltage
100
100
- - \ 2200 pF
."
80
."
., 60
l¥ ""-
--
.......... r-.
..........
~
r470 pF ....... .......
w
U)
40
100pF
o
4
6
8
10 12
Voo
14
"- ~
20
l00pF
16
o
18
4
I
80
/
20
o
--
,
J
l~V
.,40
15V
w
~
20
10,000
,
" ~ ...........
I
,I,
\
20
10
- r----
o
2
tOl
r---- -
VOo= 10V
TA= +25'C
.
c:
;;30
:5
i= 20
>-
:sc
......
~~
-~
.1
50
'"
~~
i.--'"
r--- t 02
r--...:
-....
"-
-:::;:.. i""
101-
r-....
-
tRISE
10
4
6
8
10
12
Voo
14
16
18
Quiescent Supply Current
vs. Voltage
10
,~
TA = +25"C
- -- -<-
.- .- f-'
~
BOTH INPUTS = 1
.§.
...... ~
I-
ffiu
1
U)
w
10
:5
.9
I-
10
10,000
CLOAO = 1000 pF
.TA = +25"C
VOO= 17.5V
I I
V LOAO = 1000 pF ;---r---- 102-
l..- I8
1000
CLOAO(PF)
Propagation Delay
vs. Supply Voltage
60
50
w
4
6
VORIVE(V)
100
voo= 17.5V
~40
r- -
t02
.........
r-
o
18
i-"
~~
V
Propagation Delay Time
vs. Temperature
I
I
I
I
I
CLOAO = 1000 pF-
'\.
50
16
I I
10
-55 -35 -15 5 25 45 65 85 105125
TEMPERATURE ("e)
Effect of Input Amplitude
on Delay Time
60
_
tFALl
/
1000
CLOAO(pF)
14
20
60
30
~
100
10 12
voo
l~V
,15V
V/
r--
.s
I
//
i-"~
.",
I
8
T
I
/.
-I"-
-C LOAO = 1000 pI'
50
I
/
I
If
~
60
v~~~~~
I
TA = +25"v
6
I/voo= 5V
80
)500 pF
-
1 1 1
TA =+25"C
Rise and Fall Times
vs. Temperature
Fall Time vs. Capacitive Load
100
TA = +25"~
"""'10'L~ ...........
I--.
~7~" .....
II-
--
..,......,.
20
~~200IF
80
)500pF
lOQOp~
.s
,j
TA = +25"C
Rise Time vs. Capacitive Load
100
BOTH INPUTS
tOl
-55 -35 -15 5 25 45 65 85 105125
TEMPERATURE ("C)
6-51
0.1
4
6
8
=0
10 12
VOO
~
14
16
18
i.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
TYPICAL CHARACTERISTICS CURVES (Cont.)
Quiescent Supply Current
vs. Temperature
4.0
Pull-Up Output Resistance
25
V~O~18~ I
\
\
BOTH INPUTS = 1
20
C( 3.5
.§.
§:
~
~ 3.0
w
:;
.9 2.5
.....
Z
015
r..... j'-....
'\
!g'
j'-.... .......
rr.~
...... .......
10
....... ~
~
-65 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (·C)
\
"
".......
4
6
\
8
I
I
-
TYP@+25·C- -
'-1-1
10 12
Voo
6-52
14
-
16
18
"- .......
"
"I\..
"- i'..
10
"
8
5
4
6
I
I
-
WORST CASE @TJ =+150·C
\
WORST CASE
@ TJ = +150·C-
"'}.....L
I
1\
20
8
5
Pull-Down Output Resistance
25
8
-
r---....
~+rc- -
10
r12
Voo
14
-
16
18
1.SA DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4404
TC440S
TYPICAL APPLICATIONS
Zero Crossover Current Totem-Pole Switch
Driving Bipolar Transistors
d
VDD ----..-----------------,
VDD ------.--------------.
(4.5V-18V)
--'-'1
FROM TIL
(4.5V-18V)
mo"={
J-oVOUT
19
GND----~----------~
GND------~--------------~
Servo Motor Control
+24V - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ - - -.....------SOO mA
Reverse Current (Either Polarity)
Input Withstands Negative Swings Up to -SV
FUNCTIONAL DIAGRAM
r -____~--------------------------------------~~~1
~'"
2mA
TC4406
30omllv......__
INPUT o-2..:..(3..:..)___............~
4.7V
,,
,,
-<~~~
i
r V' ~~
~'"
TC4407
GND~4--~'--~~--4---------------------------------------~
EFFECTIVE
A (B)
INPUT
C
1024-1
VDD
20pF
6-55
PUllUP
PUllDOWN
1P!RIEUIMHNA!RY
~NfFO!RMAT~ON
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
For driving many loads in low-power regimes, these
drivers, because they have very low quiescent current
«250~) and eliminate shoot-through currents in the output stage, require significantly less power than similar drivers, and can be helpful in meeting low-power budgets.
Because neither drain in an output is dependent on the
other (though they do switch simultaneously), these devices
can also be used as open-drain buffer/drivers where both
drains are available in one device, thus minimizing chip
count. Unused open drains should be returned to the supply
rail their device sources are connected to (pull-downs to
ground, pull-ups to V DO), to prevent static damage. Alternatively, in situations where timing resistors, or other means of
limiting crossover currents are used, like drains may be
paralleled for greater current-carrying capacity.
The TC4406 and TC4407 are built using Teledyne
Components' newTough CMOS process and are capable of
giving reliable service in the most demanding electrical
environments: they will not latch under any conditions within
their power and voltage ratings; they are not subject to
damage when up to 5V of noise spiking of either polarity
occurs on their ground pin; and they can accept, without
damage or logic upset, up to 1/2 amp of reverse current (of
either polarity) being forced back into their outputs. All
terminals are fully protected against up to 2 kV of electrostatic discharge.
ORDERING INFORMATION
Part No.
Logic
Package
TC4406CPA
TC4406EPA
TC4406EOE
TC4406MJA
TC4406COE
TC4407CPA
TC4407EPA
TC4407EOE
TC4407MJA
TC4407COE
Inverting
Inverting
Inverting
Inverting
Inverting
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
8-Pin PDIP
8-Pin PDIP
16-Pin SO Wide
8-Pin CerDIP
16-Pin SO Wide
8-Pin PDIP
8-Pin PDIP
16-Pin SO Wide
8-Pin CerDIP
16-Pin SO Wide
Temperature Range
O°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
O°C to +70°C
O°Cto +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
O°C to +70°C
PIN CONFIGURATIONS
8-Pin DIP
8-Pin DIP
~'"
~"
TC4406
TC4407
16-Pin Wide SOIC
16-Pln Wide SOIC
VDD
AUP
VDD
A UP
VDD
AUP
VDD
AUP
NC
INA
INB
~'"
TC4406
NC
sup
INA
suP
INB
sup
NC
GND
SOOWN
GND
GND
SDOWN
GND
NOTE 1
NOTE:
NC
AOOWN
NC = NO CONNECTION
1. Duplicate pins must both be connected for proper operation.
6-56
A DOWN
~'"
TC4407
BUP
BUP
B UP
BDOWN
BDOWN
NOTE 1
[P>IRlIEUM~NAIRlV ~NfOIRlMAT~ON
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
ABSOLUTE MAXIMUM RATINGS
Package Power Dissipation
1000 r - - - - , - - - - , - - - - , - - - . , - - - ,
Supply Voltage .......................................................... +22V
Maximum Chip Temperature ................................. + 150°C
Storage Temperature Range .................. --65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Package Thermal Resistance
CerDIP RSJ-A ................................................ 150°CIW
CerDIP RSJ-C .................................................. 550C/W
PDIP R9J-A ................................................... 125°C/W
PDIP R9J-c ..................................................... 45°C/W
SOIC R9J-A ................................................... 250°CIW
SOIC RSJ-c ..................................................... 75°CIW
Operating Temperature Range
C Version ............................................... O°C to +70°C
E Version ........................................... -40°C to +85°C
M Version ......................................... -55°C to +125°C
BOO~-~~-+---~--+-~
~ 600
S
C
0..
~--~--~~~+----+--~
400
......--+----l
I--"""'..---+""O"~
III
200
50
75
100
125
AMBIENT TEMPERATURE COC)
150
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS:
unless otherwise specified, specifications measured at T A = +25°C with 4.5V :::; Voo :::; 18V.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input
VIH
Logic 1 High Input Vo~age
2.4
-
-
VIL
Logic 0 Low Input Voltage
-
-
0.8
V
liN
Input Current
-1
-
1
IlA
-
V
-5V:::; VIN:::; Voo
V
Output
VOH
High Output Voltage
VOL
Low Output Voltage
Ro
Output Resistance, Pull Up
Voo-D.025
-
-
-
0.025
V
2.8
5
3.5
5
n
n
-
A
Ro
Output Resistance, Pull Down
lOUT: 10 mA, Voo = 18V
IpK
Peak Output Current
Any Drain
-
loc
IR
Continuous Output Current
Any Drain
-
-
150
mA
Latch-Up Protection
Withstand Reverse Current
Any Drain
> 500
-
-
mA
lOUT: 10 mA, Voo= 18V
3
Switching Time (Note 1)
tR
Rise Time
Figure 1, CL = 1800 pF
-
23
35
ns
IF
Fall Time
Figure 1, CL = 1800 pF
-
25
35
ns
tOl
Delay Time
Figure 1, CL = 1800 pF
-
33
75
ns
t02
Delay Time
Figure 1, CL = 1800 pF
-
38
75
ns
Power Supply Current
VIN = 3V (Both Inputs)
mA
VIN: OV (Both Inputs)
mA
Power Supply
Is
6-57
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
ELECTRICAL CHARACTERISTICS:
Specifications measured over operating temperature range with 4.5V 5 VDD S 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
-
-
V
-
O.B
V
10
jJA
-
V
Max
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
VIL
Logic 0 Low Input Voltage
-
liN
Input Current
-10
-5V S VIN S Voo
Output
VOH
High Output Voltage
Voo-0.025
VOL
Ro
Low Output Voltage
Output Resistance, Pull Up
-
IOUT= 10 mA, Voo= lBV
Ro
Output Resistance, Pull Down
lOUT = 10 mA, Voo = 18V
IpK
Peak Output Current
loc
Continuous Output Current
Any Drain
Any Drain
IR
Latch-Up Protection
Any Drain
Withstand Reverse Current
-
-
0.025
V
3.7
B
n
n
-
4.3
-
3
-
A
-
-
150
mA
-
-
mA
>500
B
Switching Time (Note 1)
tR
Rise Time
Figure 1, CL = 1800 pF
-
-
60
ns
tF
Fall Time
Figure 1, CL = 1800 pF
ns
Delay Time
Figure 1, CL = 1BOO pF
100
ns
t02
Delay Time
Figure 1, CL = 1800 pF
-
-
60
tOl
-
100
ns
Power Supply Current
VIN = 3V (Both Inputs)
mA
VIN = OV (Both Inputs)
mA
Power Supply
Is
NOTE:
1. Switching times guaranteed by design.
Teledyne Components reserves the right to make changes in the circuitry or specifications detailed in this manual at any time without notice. Minimums
and maximums are guaranteed. All other specifications are intended as guidelines only. Teledyne Components assumes no responsibility for the use of
any circuits described herein and makes no representations that they are free from patent infringement.
+5V
INPUT
VDD =18V
l8V----:::~L
OUTPUT
INPUTo--:2,3+-lI:X)--+~~
INVERTING DRIVER
+5V
INPUT
O.4V
l8V
OUTPUT
ov---....Ji
NONINVERTING DRIVER
Figure 1
Switching Time Test Circuit
6-58
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
TYPICAL CHARACTERISTICS CURVES
Rise Time vs. Supply Voltage
100
Fall Time vs. Supply Voltage
I
I
TA=+25'C-
47~:PF
80
100
\..
Ui' 60
.s
III
iF 40
33~"
222,0 pF"-
.... f"...
.... i!.::'
20
470 ~F
........
--
20
10 12
VOO
14
18
6
Fall Time
vs. Capacitive Load
w
12
VOO
14
16
1/
100
A
o
100
10V
.s
!26r-+-~-r-+~~~
11 15V
~
"
C 40
""~ ~
20
10,000
20
1!!s'-5--3.!..5-_..J.
1-5 -5'-2.l..5--'45-6'-5-8..L.5- 1..J.0-5 -'125
TEMPERATURE ('C)
o
C LOA., 2200 pF
to
"
25
25
6
8
10 12
VOO
V CJ::
./
V"
./ ..". ./
14
16
18
,/
/
t02
V"
20
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('C)
6-59
4 5 6 7 8 9 10 11 12
INPUT (V)
I
I
T ~+25'C
".
~
~
1 2 3
t02
Quiescent Supply Current
vs. Voltage
Delay Time
Temperature
VS.
t02
4
r-
l
w
45
r--
~
i= 60
I-
50
.........
VOO = 18V
I-TA = +25'C
I
~
w
;;§ 24
C LOAD' 2200 pF
~~
-
tOl
Ui' 80
50
~
CLOAO = 2200 pF
I
r- -
Propagation Delay Time
vs. Supply Voltage
45
10,000
Propagation Delay
vs. Input Amplitude
100
1000
CLOAO(PF)
~
1000
CLOAO(PF)
Rise and Fall Times
vs. Temperature
/ IIV
/ /fl
20
i"""
o
18
OV
III
:.&V
20
10
i
IL /1.15V
/ /X
iF 40
VOO=5V~
J
J
III
I
I I I
TA = +25'C
80
20
-
1500 pF \1000 pF
8
i/
.s
... ..;::I--..
470r
16
I.!.
VOO=5V
Ui' 60
..........
.... ........... r-.....
1500 pF \1000 pF
100
X0
....
22~p~ r-...
r--....
II
80 r- TA = +25'C
~
33
.......
8
6
_I
47~IPF
80
Rise Time vs. Capacitive Load
100
I
I
TA=+25'C-
1
~OTHIINPUts = ~
;(
S
I-
Z
~
BOTH INPUTS = 0
!!! 0.1
;:)
.9
0.01
4
6
8
10 12
VOO
14
16
18
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
TYPICAL CHARACTERISTICS CURVES (Cont.)
Quiescent Current
vs. Temperature
Output Resistance (Pull Up)
vs. Supply Voltage
1.4
14
/
1.0
!Zw 0.8 u
14
\ WORST CASE @ TJ
1.2
1
INPU!!::..!-.......
12
\~
,V
....
.9 0.4
M
- r-
4
INPUTS=O
-65 -35 -15 5 25 45 65 85 105 125
TEMPERATURE
2
4
"6
......
.........
It-
10 12
Voo
6-60
WORST CASE @ T J = +150·C
~
i'..
I'-... ..........
r- r-
TYP
8
\
=+ISO·C
12
ffiO.6
:5
0.2
Output Resistance (Pull Down)
vs. Supply Voltage
..... r-...
6
14
16
18
2
4
6
-
~
8
10 12
Voo
14
16
18
3A DUAL OPEN-DRAIN
MOSFET DRIVERS
TC4406
TC4407
TYPICAL APPLICATIONS
Zero Crossover-Current Totem-Pole Switch
Reach-Up and Reach-Down Driving
d
VDD----~------,
+ 1 2 V - - - - - _ - - . . - - +12V
(4.5V-18V)
~f+
FROM TTL
J-oVOUT
'9
+ 5 V - - - _ - - t - - . . . . - - +5V
GND--~~--------~
FROM TTL {
Driving Bipolar Transistors
GND---*---r----
VDD - - - _ - - - - - - - - ,
(4.5V-1BV)
- 1 2 V - - - - - - -......--12V
GND---------~
High-Side Switch
VDD
(4.5V-18V)
-----,
~'"
BONDING DIAGRAM
ON\2£!:
(TTL)
NOTE: Unused drains should be connected to
their respective supplies.
POWER-ON OSCILLATION
It is extremely important that all MOSFET
DRIVER applications be evaluated for the possibility of having HIGH-POWER OSCILLATIONS occurring during the POWER-ON cycle.
POWER-ON OSCILLATIONS are due to trace
size and layout as well as component placement. A
'quick fix' for most applications which exhibit POWERON OSCILLATION problems is to place approximately 10 kn in series with the input of the MOSFET
driver.
OUTPUTB
OUTPUT A
NOTES: 1. Back of die is common to Voo.
2. Back of die is not metallized.
3. Dual bond pads must BOTH be connected (Voo and GND).
6-61
NOTES
6-62
..,"'TELEDYNE
COMPONENTS
TC4420
TC4429
6A HIGH-SPEED MOSFET DRIVERS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Tough CMOSTM Construction
Latch-Up Protected: Will Withstand >1.5A
Reverse Output Current
Logic Input Will Withstand Negative Swing Up
to 5V
ESD Protected .......•....•.........•............................. 4 kV
Matched Rise and Fall Times .....•......•............. 25 ns
High Peak Output Current ..•.....•........•........ 6A Peak
Wide Operating Range .......................... 4.5V to 18V
High Capacitive Load Drive ..................... 10,000 pF
Low Delay Time .....•.................................. 55 ns Typ
Logic High Input, Any Voltage .............. 2.4V to Voo
Low Supply Current With Logic "1" Input ... 450 I1A
Low Output Impedance .........••.............•.......•.... 2.5Q
Output Voltage Swing to Within 25 mV of Ground
orVoo
Switch-Mode Power Supplies
Motor Controls
Pulse Transformer Driver
Class D Switching Amplifiers
FUNCTIONAL DIAGRAM
r---~------------------------------------~~OVDD
~'"
TC4429
INPUT
.ri>4
~
rrO"mfl
I
r~
0-_-.-.....
--'
,,
~'"
,
,
I
_1_
TC4420
4.7V
T
GNDo-~--~----~------------------------------------~
EFFECTIVE
INPUT
C=38pF
1025·1
6-63
III
6A HIGH-SPEED MOSFET DRIVERS
TC4420
TC4429
GENERAL DESCRIPTION
The TC4420/4429 Tough CMOSTM drivers are efficient
and easy to use. These devices are 6A (peak) single output
MOSFET drivers.
The TC4420/4429 will drive even the largest MOSFETs.
These devices are tough due to extra steps taken to
protect them from failures. An epitaxial layer is used to
prevent CMOS latch-Up. Proprietary circuits allow the input
to swing negative as much as 5V without damaging the
part. Special circuits have been added to protect against
damage from electrostatic discharge. A special molding
compound is used for increased moisture resistance and
ability to withstand high Voltages. They are also tough
because of Teledyne Components' world-class process
controls and device quality.
Because these devices are fabricated in CMOS, they
run cool, use less power and are easier to drive. The rail-torail swing capability of CMOS better insures adequate gate
voltage to the MOSFET during power up/down sequencing.
The Tough CMOSTM drivers are easy to use. Three or
more discrete components can be replaced with a single
device to save PCB area. Any logic input from 2.4V to VDD
can be used without external speed-up capacitors or resistor
networks.
This family is available in inverting (TC4429) and
non inverting (TC4420) configurations. The TC4429 is pin
compatible with the popular TC429.
ORDERING INFORMATION
Part No.
Logic
Package
Temperature Range
TC4420CPA
Noninverting
B-Pin PDIP
O°Cto +70°C
TC4420EPA
Noninverting
B-Pin PDIP
TC4420COA
Noninverting
B-Pin SOIC
40°C to +B5°C
DOC to +70°C
TC4420EOA
Noninverting
B-Pin SOIC
40°C to +B5°C
TC4420lJA
Noninverting
B-Pin CerDIP
25°C to +B5°C
TC4420MJA
Noninverting
B-Pin CerDIP
55°C to + 125°C
TC4420CAT
Noninverting
5-Pin TO-220
O°Cto +70°C
TC4429CPA
Inverting
O°Cto+70°C
TC4429EPA
Inverting
B-Pin PDIP
B-Pin PDIP
TC4429COA
Inverting
B-Pin SOIC
O°Cto +70°C
TC4429EOA
Inverting
B-Pin SOIC
40°C to +B5°C
TC44291JA
Inverting
B-Pin CerDIP
25°C to +B5°C
TC4429MJA
Inverting
B-Pin CerDIP
55°C to + 125°C
TC4429CAT
Inverting
5-Pin TO-220
O°Cto +70°C
40°C to +B5°C
PIN CONFIGURATIONS
CAT
DIP
Voo
o
INPUT
SOIC
8 VOO
OUTPUT
2
V0008 Voo
INPUT
2
NC
3
GND 4
Tab Is
Common
toVOO
I-CCC!:::;
~Z
cz IS:
zCl> Cll-
NOTE: Duplicate pins must both be connected
for proper operation.
::J
o
6-64
7 OUTPUT
6 OUTPUT
5 GNO
6A HIGH-SPEED MOSFET DRIVERS
TC4420
TC4429
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................................................... +20V
Input Voltage .................................................. -5V to >Voo
Input Current (VIN > Voo) ........................................ 50 mA
Power Dissipation, TA "" 25°C
PDIP ...................................................................... 1W
SOIC .............................................................. 500 mW
CerDIP ........................................................... 800 mW
5-Pin TO-220 ...................................................... 1.5W
Power Dissipation, Tc ::; 25°C
5-Pin TO-220 .................................................... 12.5W
Derating Factors (To Ambient)
PDIP ............................................................. 8 mW/oC
SOIC ............................................................ .4 mW/OC
CerDIP ....................................................... 6.4 mW/oC
5-Pin TO-220 .............................................. 12 mW/oC
Thermal Impedances (To Case)
5-Pin TO-220 R8J-A ...................................................... 10°CIW
Storage Temperature Range .................. -55°C to +150°C
Operating Temperature (Chip) .............................. +150°C
Operating Temperature Range (Ambient)
C Version ............................................... O°C to +70°C
I Version ............................................. -25°C to +85°C
E Version ........................................... -40°C to +85°C
M Version ......................................... -55°C to +125°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS: TA = +25°C with 4.5V "" Voo"" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
I
Typ
I
Max
Unit
Input
VIH
Logic 1 High Input Vo~age
2.4
1.8
-
V
VIL
Logic 0 Low Input Voltage
-
1.3
0.8
V
VIN (Max)
Input Vo~age Range
liN
Input Current
OV ~ VIN ~ Voo
VOH
High Output Voltage
See Figure 1
VOL
Low Output Voltage
See Figure 1
Ro
Output Resistance, High
lOUT = 10 rnA, Voo
Ro
Output Resistance, Low
10UT= 10 mA, Voo
IpK
Peak Output Current
Voo = 18V (See Figure 5)
IREV
Latch-Up Protection
Withstand Reverse Current
Duty Cycle ~ 2%
t ~ 300!!s
-5
-
Voo+0.3
-10
-
10
Voo-O.025
-
-
0.025
V
-
2.1
2.8
-
1.5
2.5
0
0
6
-
A
25
35
ns
25
35
ns
55
75
ns
55
75
ns
0.45
55
1.5
150
I!A
18
V
V
!!A
Output
=18V
=18V
>1.5
-
V
A
SWitching Time (Note 1)
=2500 pF
=2500 pF
tR
Rise Time
Figure 1, CL
tF
Fall Time
Figure 1, CL
t01
Delay Time
Figure 1
t02
Delay Time
Figure 1
-
Power Supply Current
VIN= 3V
VIN= OV
-
Power Supply
Is
Voo
4.5
Operating Input Voltage
6-65
-
rnA
•
SA HIGH-SPEED MOSFET DRIVERS
TC4420
TC4429
ELECTRICAL CHARACTERISTICS:
Measured over operating temperature range with 4.5V "" Voo "" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
-
-
V
VIL
VIN (Max)
Logic 0 Low Input Voltage
-
-
0.8
V
Input Voltage Range
-5
-
V
-10
-
Voo+0.3
10
Voo-D·025
-
-
V
Input Current
OV"" VIN "" Vs
VOH
High Output Voltage
See Figure 1
VOL
Low Output Voltage
See Figure 1
Ro
Output Resistance, High
Ro
Output Resistance, Low
liN
Output
~A
-
0.025
V
lOUT = 10 mA, Voo= 18V
-
3
5
IOUT= 10 mA, Voo = 18V
-
2.3
5
n
n
-
32
60
ns
34
60
ns
50
65
100
100
ns
ns
~A
Switching Time (Note 1)
tR
Rise Time
Figure 1, CL = 2500 pF
tF
Fall Time
Figure 1, CL = 2500 pF
Delay Time
Delay Time
Figure 1
Figure 1
-
Power Supply Current
VIN= 3V
VIN= OV
-
0.45
60
3
400
4.5
-
18
t01
t02
Power Supply
Is
-
Operating Input Voltage
Voo
NOTE: 1. Switching times guaranteed by design.
Voo = 18V
71~F
INPUT
0.1
~F
=0.4V
INPUT 0-11-=-21--1
+18V--~~
.;.c)--r-+-.....~ OUTPUT
OUTPUT
~ CL = 2500 pF
OV
INPUT: 100 kHz, square wave,
'..'SE = tFALL ,;; 10 nS
Figure 1. Switching Time Test Circuit
6-66
mA
V
6A HIGH-SPEED MOSFET DRIVERS
TC4420
TC4429
TYPICAL CHARACTERISTICS CURVES
Rise Time vs Supply Voltage
120
........
~
100
.,
S
w
:::;;
i=
Fall Time vs Supply Voltage
........
50
.......
A=ll0,~~F
Cl= 2200 pF
VOo= 18V
i"'-
80
'I. 1 J
........
60
40
r-
20
........ r-.....
- 7
I I I
1=4.}00~F
c l l=
~
2~00 ~F
r--....c l = 10,000 pF
........ ~
40
I I I
o
15
13
5
-i'- ......
~
.,
S
100
80
80
V'
,
Voo=5'!/
40
VOO=10
,
20
.- rt
20
Cl=2200pF
13
o
-60
15
-20
V
k=:: i:'
,
~
iil45
.......
C
.,
Cl=2200pF
Voo=18V
40
-
......r--_7
S
.... -,....
w 30
:;
i=
>
:::520
w
,I
-t02
-
c
'" i--""
1/
1000
f- VOo= 15\1
~70
«
to1
z
w
a:
a:
o
~
500 kHz
28
-
::J
en
-20
20
60
TA("C)
100
140
14
o
11~YI
/
I- 100
::J
o
a..
a..
~OOkHZ
/
/
10
::J
en
~~z
100
1000
CAPACITIVE LOAD (pF)
6-67
>
--'
10V
5V
::J
0
It
18
1= Cl= 2200 pF
V DD ) ..................... 50 mA
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS (TA = 25°C with 4.5V .;; VDD';; 18V unless otherwise specified.)
Symbol
Parameter
Test Conditions
I
Min
I Typ I
Max
Unit
Input
V,H
Logic 1 Input Voltage
2.4
1.8
-
V
V'L
Logic 0 Input Voltage
-
1.3
0.8
V
liN
Input Current
10
JlA
OV,;; V ,N .;; VDD
-10
-
V DD-0.025
-
Output
-
VOH
High Output Voltage
See Figure 1
VOL
Low Output Voltage
See Figure 1
-
-
Ro
Output Resistance, High
V DD = 18V, 10 = 10 mA
-
1.4
-
n
Ro
Output Resistance, Low
VDD =18V,1 0 =10mA
-
0.9
1.7
n
V DD = 18V
-
9
-
A
-
-
mA
IpK
Peak Output Current
IDC
Continuous Output Current
IREV
Latch-Up Protection
Withstand Reverse
Current
0.025
2
Duty Cycle.;; 2%
t.;; 300 Jls
>1500
V
V
A
Switching Time (Note 1)
tR
Rise Time
Figure 1, CL = 10,000 pF
-
60
75
ns
tF
Fall Time
Figure 1, CL = 10,000 pF
-
60
75
ns
tD1
Delay Time
Figure 1
-
30
60
ns
tD2
Delay Time
Figure 1
-
33
60
ns
Power Supply Current
V ,N = 3V
-
0.2
1.5
mA
V ,N = OV
-
55
150
JlA
4.5
-
18
V
Power Supply
Is
VDD
Operating Input Voltage
6-71
-=_
9A HIGH-SPEED FET DRIVER
TC4421
TC4422
ELECTRICAL CHARACTERISTICS
(Measured over operating temperature range with 4.5V .;; Vs';; 18V unless otherwise specified.)
Symbol
Parameter
I
Test Conditions
Min
I
Typ
Max
Unit
Input
V'H
Logic 1 Input Voltage
2.4
-
-
V'L
Logic 0 Input Voltage
-
-
0.8
V
OV,;; V'N';; Voo
-10
-
10
IJA
V oo-O·025
-
I'N
Output
Input Current
VOH
High Output Voltage
See Figure 1
VOL
Low Output Voltage
See Figure 1
-
-
Ro
Output Resistance, High
Voo = 18V, 10 = 10 mA
-
Ro
Output Resistance, Low
V 00 = 18V, 10 = 10 mA
Figure 1, CL = 10,000 pF
Figure 1, CL = 10,000 pF
Switching Time (Note 1)
Rise Time
tR
-
V
V
0.025
V
2.4
3.6
-
1.8
2.7
n
n
-
60
120
ns
tF
Fall Time
-
60
120
ns
t01
Delay Time
Figure 1
-
50
80
ns
Delay Time
t02
Power Supply
Figure 1
-
65
80
ns
V'N =3V
-
0.45
3
mA
V'N = OV
-
0.06
0.2
mA
18
V
Power Supply Current
Is
Operating Input Voltage
Voo
4.5
-
NOTE: 1. Switching times guaranteed by design.
Voo= 18V
~ O.lI1F
+5V
INPUT
O.lI1F
=0.4V
INPUT
2
+18V
OUTPUT
OUTPUT
TC4421
~ CL= 10,000 pF
OV
INPUT: 100 kHz, square wave,
tRISE = ~ALl ,; IOnS
Figure 1. Switching Time Test Circuit
6-72
9A HIGH-SPEED FET DRIVER
TC4421
TC4422
TYPICAL CHARACTERISTIC CURVES
Fall Time vs Supply Voltage
Rise Time vs Supply Voltage
220
180
\
200
.........
!f.
~
80
4700 pF.........
-r--
60
40
1000 pF
20
o
4
1---..
S
...J
-~
t- ""-
--
8
6
' " 22,000 pF
., 120
............
10,000 pF
\
140
~22,OOOpF
160
., 140
c:
~ 120
!!:! 100
,
160
\
180
100
80
........ 1'0... 10,000 pF
60
--- -
r-
~OpF
40
20
10
12
14
16
o
18
1000 pF
4
8
6
10
Voo
II
200
~
~ 150
I /
10V
!
300
II ~VI
250
/
!f.
100
/1/
S
::l
;.
V 15V
150
I l15V
100
t:)~
50
o
100
1000
100
100000
10000
CLOAO(pF)
Rise and Fall Times vs Temperature
I
I
I
I
UJ
::;;
i=
50
40
30
I
-
/'"
~
-40
V
.......
o
.."..""
V
100000
/'
'~
S
UJ
::;;
i= 35
V
'\
/
t01
tF~LL I
30
4
6-73
...........
~
t02
......;;,:,.. io-
'-
25
120
I
\\\
.,40
./
I
CLOAO= 1000 pF
\
45
/
I-- I-- tR1SE/,
10000
CLOAO(pF)
Propagation Delay vs Supply Voltage
~
70
60
1000
50
t-- cLOAO = 10,000 pF
80 I--VOO= 15V
.,S
18
I
10V-fA
., 200
o F"""
90
16
I
5~1
250
~V
50
14
Fall Time vs Capacitive Load
Rise Time vs Capacitive Load
300
12
VOO
6
8
10
12
VOO
14
16
18
9A HIGH-SPEED FET DRIVER
TC4421
TC4422
TYPICAL CHARACTERISTIC CURVES (Cont.)
Supply Current vs Capacitive Load
(Voo = 18V)
220
Supply Current vs Frequency
(Voo = 18V)
180
II
200
160
~
140
120
iII. 100
jl
40
I I
C
63.2 kHz
J
I
/
./
632 kHz
o
100
1000
:l:~
10,000
f- 0.1
80
80
~F
1/
10
100
FREQUENCY (kHz)
I
r--
J
.....
/
~
1----+--++++++++--j-+1f--t+t-t-tl't-tU'-l
100
80~-+-+~1+H+IF-+J'--It~~~~
jl
60 -
~F..I
100
FREQUENCY (kHz)
10
I
/
120
200kHz
100
80
70
I
if
I
C
-
10
0
100
2MHz
V-
80
.§.
~ 60
,/
II.
II.
IJ
63.2 kHz
1000
4700pF
.
:>
JII 40
632 kHz
0.1
V-
1..-+'11
......
10,000
1000
Supply Current vs Frequency
(Voo=6V)
100
C
.§. 60
~ 50
1mb!
VI I-' " ....... ~~ .JJ1111
__
J~"ii~~~~==t~:r~4~ro~P~F~
L
o
100,000
90
~
/
20
Supply Current vs Capacitive Load
(Voo=6V)
20
0.1
40~-+~~~+H~-+~~H+~~
V
o
J
:l:
20kHz
200 kHz
1/
47,000 pF
63.2 kHz
~
1.125 MHz
I J..J.l.l.
~632kHZ
'I
C_
E 120r--r-rrr~+-~/~~~~I/~
100
:> 40
JII
30
--+-
140~-4-1~rH~--~-L~~~~
I
80 r--T"
20
.I
22,000 pF
10,000 pF
II
./
.§. 100 r-- 2MHz
40
III
160~-4-4~~~--~~~~~~
I
120
60
1000
180.--,-,....,..rn~--------~nT"
140
:>
V,~
Supply Current vs Frequency
(Voo = 12)
160
JII
/
__U
100,000
180
~
.L
....~
~ I-' 114r~~ pF
20~-¥~~~~~~'
o L-1~~~ffit:-~47~0~PFJ]II~II!I
Supply Current vs Capacitive Load,
(Voo= 12)
II.
II.
11
:H-t+lH--lt-,-+F-M-1Ht.l'l---H
j
IJ
ct.OAO (pF)
C
I
120 1--+-I-++-I#I-H+C/~Nc-I+-l.o.++I-1I++-I-/H
40~-¥~~~~~~~~
20kHz
"
200kHz
1/
tttI--J,H
.§. 100~-+~+1~HL-1II4'~~~~~+4
jl
r-- Till
II
I 111111,
10,000P~'i..
II
r-- l'm~HZ/ V
20
I 22,000 pF
47,000 pF
II
80
60
I
: : e-r-
180 f--2MHz
C
.-....,......,..,....,..,..,.,.....---n~....,.....,.......,Tmr-"T""1
20
20kHz
o
10
100,000
CLOAO(pF)
6·74
~F
~
47rO PF;
I ill
I
/
J""lV
V
/.
II
22, OOOpF
11/
~ ~i-"
100
FREQUENCY (kHz)
ilill
10,O~0 pF
/
V
./
470pF
1000
9A HIGH-SPEED FET DRIVER
TC4421
TC4422
TYPICAL CHARACTERISTIC CURVES (Cont.)
Propagation Delay vs Input Amplitude
120
110
VOO = 10V
80
70
60
.s
UJ
::;;
VV
0
\\
,\
02
102/
0
....... r--
r-- - 101
2
1
o
V
/
, ,t
\\.
50
40
30
20
10
>=
L'
5
CLOAO = 10000V
100
90
..,
Propagation Delay vs Temperature
0
1
5;.-
~~
[/
,/
-<01
V
20
1234567
INPUT (V)
-60 -40 -20
10
Crossover Energy vs Supply Voltage
0
20 40
TA('C)
60
80 100 120
Quiescent Supply Current
vs Temperature
10-6
;:::VOo=18V
~
/'
/
10-8
4
i--
INPUT
;:=
INPUT = 0
i--
8
6
10
12
14
16
1
18
VOO
-60 -40 -20
0
20
40
60
80 100 120
TJ ("C)
NOTE: The values on this graph represent the loss seen
by the driver during a complete cycle. For the loss
in a single transition, divide the stated value by 2.
High-State Output Resistance
vs Supply Voltage
Low-State Output Resistance
vs Supply Voltage
6
5.5
5.5
\
4.5
~~
~
II:
5
I
4.5
t\. TJ = 150' C
9:
Z
I
""-
3.5
"I" ,i"""
3
2.5
- TJ=25'C
1.5
...........
r--
1
0.5
4
1
6
8
10
--
12
14
9:
4
Z
3.5
;p
2.5
e.
I-
16
3
~ ~J=150'C
" t"--... T"-
2
1.5
1
-
0.5
4
18
~
TJ =25'C
8
--
r--
10
12
VOO(V)
VOO(V)
6-75
.....
14
16
18
NOTES
6-76
~"'TELEDYNE
TC4423
TC4424
TC4425
COMPONENTS
3A DUAL HIGH-SPEED MOSFET DRIVERS
FEATURES
•
•
•
•
•
•
•
•
•
Tough CMOS™ Construction
Latch-Up Protected: Will Withstand 1.5A Reverse
Current
Logic Input Will Withstand Negative Swing Up
to 5V
ESD Protected ...•..•.......•...•..•......•...................... .4 kV
High Peak Output Current .................................... 3A
Wide Operating Range ........................•.. 4.5V to 18V
High Capacitive Load
Drive Capability .............................. 1800 pF in 25 ns
Short Delay Times .......•........................... <40 ns Typ
Consistent Delay Times With Changes in Supply
Voltage
•
•
•
•
•
•
•
•
Matched RiselFall Times
Logic High Input, Any Voltage ..••...••.•.... 2.4V to Voo
Logic Input Threshold Independent of Supply
Voltage
Low Supply Current
- With Logic "1" Input .................................. 3.5 rnA
- With Logic "0" Input ...............................••. 350 IlA
Low Input Impedance ................................ 3.5WTyp
Output Voltage Swing to Within 25 mV of Ground
orVoo
Pinouts Same as TC1426127128; TC4426127128
Available in Inverting, Noninverting, and
Differential Configurations
FUNCTIONAL DIAGRAM
r---~------------------------------------~~~VDD
INVERTING
r1
r~~
~~
i
INPUT
O--l--0.5A
Reverse Current
Input Will Withstand Negative Inputs Up to 5V
ESD Protected ....•...............................................4 kV
High Peak Output Current ................................ 1.5A
Wide Operating Range .......................... 4.5V to 18V
High Capacitive Load
Drive Capability ............................. 1000 pF in 25 ns
Short Delay Time ......•............................. <40 ns Typ
Consistent Delay Times With Changes in
Supply Voltage
Matched Rise and Fall Times
•
•
•
•
•
•
•
Logic High Input for Any Voltage From 2.4V to Voo
Logic Input Threshold Independent of Supply
Voltage
Low Supply Current
- With Logic "1" Input ......•.....•.......••....•.........4 rnA
- With Logic "0" Input ................................. 400 !lA
Low Output Impedance ........................................ 70.
Output Voltage Swing to Within 25 mV of Ground
orVOD
Pinout Same as TC426fTC427fTC428
Available in Inverting, Noninverting, and
Differential Configurations
FUNCTIONAL DIAGRAM
r-----~~--------------------------------------~-oVDD
INVERTING
OUTPUTS
~
:~' ~~
D---------'-NONINVERTING
OUTPUTS
INPUT a--4>--......
-4,.......J
,
,,
,
.L
T
~
~'"
TC4426fTC4427fTC4428
GNDo-~----~--~~------------------------------------~
EFFECTIVE
INPUT
C = 12 pF
NOTES: 1. TC4428 has one inverting and one noninverting driver.
2. Ground any unused driver input.
1028-1
6·85
OUTPUT
III
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
GENERAL DESCRIPTION
The TC442614427/4428 are CMOS buffer/drivers built
using Teledyne Components' new Tough CMOS process.
They are improved versions of the earlier TC4261427/428
family of buffer/drivers (with which they are pin compatible)
and are capable of giving reliable service in far more
demanding electrical environments. They will not latch up
under any conditions within their power and voltage ratings.
They are not subject to damage when up to 5V of noise
spiking (of either polarity) occurs on the ground pin. They
can accept, without damage or logic upset, up to 500 rnA of
reverse current (of either polarity) being forced back into
their outputs. All terminals are fully protected against up to
4 kV of electrostatic discharge.
In addition, Teledyne now uses a custom-developed
molding epoxy for plastic packages which, in tests, produced zero device failures after 10,000 hours in an 85°C85% R.H. environment, and contains 50% less sodium and
chlorine contamination than standard commercial molding
compounds, increasing device lifetimes.
As a result, the TC4426/4427/4428 drivers are much
easier to use, more flexible in operation, and much more
forgiving than any other drivers (CMOS or bipolar) currently
available. Because they are fabricated in CMOS, they
dissipate a minimum of power and provide rail-to-rail voltage
swings to ensure the logic state of any load they are driving.
Although primarily intendedfordriving power MOSFETs,
the TC442614427/4428 drivers are equally well-suited to
driving any other load (capacitive, resistive, or inductive)
which requires a low-impedance driver capable of high peak
currents and fast switching times. For example, heavily
loaded clock lines, coaxial cables, or piezoelectrictransducers all can be driven from the TC4426/4427/4428. The only
known limitation on loading is that total power dissipated in
the driver must be kept within the maximum power dissipation limits of the package.
As MOSFET drivers, the TC442614427/4428 can easily
switch 1000 pF gate capacitances in under 30 ns, and
provide low enough impedances in both the ON and OFF
states to ensure the MOSFET's intended state will not be
affected, even by large transients.
Generally, the design of the TC4426/4427/4428 has
taken into account 5 years of field use (and abuse) of
Teledyne's earlier parts, with the goal of making these parts
immune to all forms of improper operation known from that
period, except exceeding the breakdown voltage and power
dissipation ratings.
ORDERING INFORMATION
Part No.
Package
Temperature
Range
TC4426COA
8-Pin SOIC
TC4426EOA
-40°C to +85°C
TC4426CPA
8-Pin SOIC
8-Pin Plastic DIP
TC4426EPA
TC4426EJA
TC4426MJA
8-Pin Plastic DIP
8-Pin CerDIP
8-Pin CerDIP
-40°C to +85°C
TC4427COA
TC4427EOA
8-Pin SOIC
TC4427CPA
8-Pin SOIC
8-Pin Plastic DIP
TC4427EPA
TC4427EJA
8-Pin Plastic DIP
8-Pin CerDIP
TC4427MJA
8-Pin CerDIP
8-Pin SOIC
TC4428COA
TC4428EOA
8-PinSOIC
O°Cto +70°C
O°Cto +70°C
-40°C to +85°C
-55°C to + 125°C
O°Cto +70°C
-40°C to +85°C
O°Cto +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to + 125°C
O°Cto +70°C
-40°C to +85°C
TC4428EPA
TC4428EJA
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin CerDIP
O°Cto +70°C
-40°C to +85°C
TC4428MJA
8-Pin CerDIP
-55°C to + 125°C
TC4428CPA
6-86
-40°C to +85°C
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
Package Power Dissipation
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................................................... +22V
Input Voltage, IN A or IN B .......... Voo+0.3V to GND-5.0V
Maximum Chip Temperature ................................. + 150°C
Storage Temperature Range .................. --65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Package Thermal Resistance
CerDIP R8J-A ................................................. 150°C/W
CerDIP R8J.e ................................................... 50°CIW
PDIP R8J.A .................................................... 125°C/W
PDIP R8J.e ...................................................... 42°C/W
SOIC R8J-A .................................................... 250°CIW
SOIC ReJ-e ...................................................... 75°C/W
Operating Temperature Range
C Version ............................................... O°C to +70°C
E Version ........................................... -40°C to +85°C
M Version ......................................... -55°C to +125°C
Power Dissipation
Plastic .......................................................... 1000 mW
CerDIP ........................................................... 800 mW
SOIC .............................................................. 500 mW
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under "Absolute Maximum Ratings' may cause perma·
nent damage to the device. These are stress ratings only and functional
800~----~-----+------r-----~----~
~
.§.
OOOr-----~~~~----t-----t---~
III
200
50
75
100
125
150
AMBIENT TEMPERATURE ("e)
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS: TA =+25°C with 4.5V '" Voo'" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
I
Typ
I
Max
I
Unit
Input
VIH
Logic 1 High Input Voltage
2.4
VIL
Logic 0 Low Input Voltage
-
liN
Output
Input Current
OV",VIN"'VOO
VOH
High Output Voltage
VOL
Low Output Vottage
Ro
IpK
Output Resistance
Voo= 18V, 10= 10mA
Peak Output Current
Latch-Up Protection
Withstand Reverse Current
Duty Cycle'" 2%
t '" 3OO!Ls
IREV
-1
Voo-0.025
-
-
-
-
-
7
>0.5
-
V
0.8
V
1
!LA
-
V
0.025
V
10
n
-
-
-
A
A
ns
1.5
Switching Time (Note 1)
tR
Rise Time
Figure 1
-
25
30
tF
Fall Time
Figure 1
25
30
ns
t01
Delay Time
Figure 1
ns
Figure 1
-
30
Delay Time
-
50
ns
Power Supply Current
VIN = 3V (Both Inputs)
VIN = OV (Both Inputs)
t02
Power Supply
Is
NOTE: 1. Switching times are guaranteed by design.
6-87
mA
mA
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
PIN CONFIGURATIONS
~
~
INVERTING
NONINVERTING
~
Ne = NO INTERNAL CONNECTION
DIFFERENTIAL
NOTE: sOle pinout is identical to DIP.
ELECTRICAL CHARACTERISTICS
Specifications measured over operating temperature range with 4.5V ,,;; VDD";; 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
. Min
Typ
Max
-
0.8
I
Unit
Input
VIH
Logic 1 High Input Vo~age
2.4
VIL
Logic 0 Low Input Voltage
-
liN
Input Current
OV,;;VIN';;VOO
-1
-
1
V
V
IlA
Output
VOH
High Output Voltage
Voo-O.025
-
VOL
Low Output Vottage
-
Ro
IpK
Output Resistance
Peak Output Current
VOD= 18V.lo= 10mA
-
IREV
LatCh-Up Protection
Withstand Reverse Current
Duty Cycle.;; 2%
t.;; 300 Ils
>0.5
-
V
0.025
V
12
Q
-
-
A
A
-
9
1.5
Switching Time (Note 1)
-
tF
Rise Time
Fall Time
Figure 1
Figure 1
tOI
Delay Time
Figure 1
t02
Delay Time
Figure 1
Power Supply Current
VIN = 3V (Both Inputs)
VIN = OV (Both Inputs)
tR
-
40
ns
-
40
ns
40
ns
-
60
ns
Power Supply
Is
NOTE: 1. Switching times ara guaranteed by design.
6-88
mA
mA
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
+5V
INPUT
~0.4V
Voo= 18V
r
VOO
0.1 I'F
OUTPUT
-=
OV
INPUT o=2:z....4'+-_~
'.t
OUTPUT
Inverting Driver
CL = 1000 pF
+5V
INPUT
3
10%
~0.4V
Voo
OUTPUT
OV
Noninverting Driver
Figure 1. Switching Time Test Circuit
BONDING DIAGRAM
Crossover Energy Loss
10-8
9
8
7
6
INA
~
./
V
5
.:l"
«
GND
4
/
3
2
I
INB
/
6
./
V
/
8
10
12
Voo
14
16
18
NOTE: The values on this graph represent the loss seen by both
drivers in a package during one complete cycle. For a single
driver. divide the stated values by 2. For a single transition of a
single driver, divide the slated value by 4.
NOTES:
1. Back of die is common to VDO'
2. Back of die is not metallized.
6-89
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
TYPICAL CHARACTERISTICS CURVES
Rise Time vs Supply Voltage
100
~200~F
80
.,.:.
r---....
~
1000pF"
w
40
470pF ........
I'--
20
---
........... r--
'f....
UI
r--
6
'.]"-
-
.:.
1~~ ............. r-.
"'""
...........
:l
c:(
I--
-
j:r 40
4~",""
20
I
4
1500p~
., 60
r-.
-
100pF
o
~2200~F
80
15~ pF"'"
60
ffi
Fall Time vs Supply Voltage
100
I
o
10
8
12
VOO
14
16
4
18
-
100pF
6
8
r---
r---
10
12
14
100
1/5V
80
I
60
I
.,
.:.
10V
15V
40
1-
1'/
~
~
60
II
/
V/
40
20
............: ..,;:. F::: ~~
-
I
/
....I
....I
Iv
UI
o
5V
II
80
/
w
20
o
1000
eLOAO(pF)
100
Rise and Fall Times vs Temperature
50 _
15V
_-": 1-"1-"
1000
eLOAD(pF)
10,000
Propagation Delay vs Supply Voltage
60
eLOAO = 1000 pF
VOO=17.5V
-
eLOAO = 1000 pF-
.,
50
iU'
~
40
:5
30
.......
t02
c
., 40
.:.
w
30
tFALL
20
OV
I
V
..... ""
V
,........
100
10,000
60
~
18
Fall TIme vs Capacitive Load
Rise TIme vs Capacitive Load
ffi
16
VOO
100
.,.:.
r--
-:I'" ~
10
-55 -35 -15
~~
>
."
w
C
::::::::V
20
~ISE
5
25 45 65 85
TEMPERATURE ee)
-
101
10
105 125
4
6·90
6
8
10
12
VOO
14
16
1.8
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
TYPICAL CHARACTERISTICS CURVES (Cont.)
Effect of Input Amplitude on Delay Time
60
I
I
I
ClOAO= 1000 pF
VOO= 10V
50
'Vi'
.:.
Propagation Delay Time vs Temperature
60
50
w 40
"I'-...
\
j:::
\
>
:sw 30
C
I\,
20
w
::;;
, t02
o
o
-
-
4
6
VORIVE(V)
2
1/
o
10
8
-55 -35 -15
ct
..- ~
IN~UTS = 1
I
.s
........
8
5
.9
--
0.1
.1_
10
12
14
16
r-- r-.
2.5
2.0
-55 -35 -15
18
High-State Output Resistance
"\
20
"'-. TYP
8
.........
@
.....
10
\
5
r---
"-
r--
"
" .........
-
TA = +25·C
25 45
TA(·C)
"-
I--.
........
~
8
10
12
......
8
14
16
105 125
18
4
VOO
6
r--
8
10
--
12
VOO
6-91
~
-
r-.... TYP @ T A = +25·C
5
6
85
WORST CASE @ TJ = +150·C
10
5
4
65
r--
1,\
WORST CASE @ TJ = +150·C
"-
-
............ r---.
Low-State Output Resistance
25
'\
"-
BOTH INPUTS = 1
~-
VOO
20
105 125
3.5
~ 3.0
\
85
65
~
r-- BOTH INPUTS = 0
25
25 45
TA("C)
VOo= 16V
ffl
6
5
Quiescent Supply Current vs Temperature
1= TA= +25·C
4
--
20
4.0
-
..-
~
l..-- --tOl
. / I--'""
c
Quiescent Supply Current vs Voltage
r-- B6TH
...... ~
/V
:sw 30
r-
k---:"
,- VLOAO= 1000 pF
>
tOl
i'...l
40
j:::
. . .r- I--..
I
.1.
'Vi'
.:.
r-...
::;;
I
r-- voo= 16V
rr-
14
16
18
1.SA DUAL HIGH-SPEED FET DRIVERS
TC4426
TC4427
TC4428
SUPPLY CURRENT CHARACTERISTICS CURVES (Load on Single Output Only)
Supply Current vs Capacitive Load
Supply Current vs Frequency
60
60
2 MHz
voo= 18V
:i'
.s
40
~ 30
V
~)""
V
-
~
~ f...-
l- I--i--
10
I
:i'
.s
100
1000
~~
o
10,000
10
100
1000
FREQUENCY (kHz)
CLOAO(pF)
Supply Current vs Capacitive Load
60
50
:i'
.s
40
V
~
30
Q.
Q.
[.....-- j..-'
::J
J!l 20
10
V
100
:i'
.s
I
2200 pF
/
I.
40
II l~OOr
Q.
Q.
900 kHz
/
I I I
V
--
::J
J!l 20
600 kHz
~II
I II
10
k::::: ~
200 kHz
20 kHz
1000
CLOAO(pF)
I
I I I
50
o
10,000
10
-LtJ
L
100
1000
FREQUENCY (kHz)
Supply Current vs Frequency
Supply Current vs Capacitive Load
60
I
~ 30
-
o
I
VOO = 12V
/
I'V
l-
fo--
Supply Current vs Frequency
60
~2 ~H~
voo= 12V
V
/ it'"
10
I I I
L
V
::J
J!l 20
20 kHz
o
100pF
Q.
Q.
200 kHz
t-
V
40
~ 30
iiiII
.....-
11111
2200 pF
50
I II
/
::J
J!l 20
~ 9~JH~
/
Q.
Q.
'00")
VOO= 18V
1111
50
60
I
I
VOO=6V
I I I I
voo =6V
50
50
2200 pF
10
o
--
100
V
i--
/
-'
~---1000
2ri
90~
k~Z
600 kHz
200 kHz
20 kHz
1000pF
10
~!""
I
o
10,000
10
CLOAO(pF)
6-92
~
~rl
100
1000
FREQUENCY (kHz)
~~TELEDYNE
COMPONENTS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
POWER LOGIC CMOS QUAD DRIVERS
APPLICATIONS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Tough CMOS Construction
Latchproof! Withstands 500 mA Inductive Kickback
3 Input Logic Choices
- AND/NAND/AND+lnv
4 Output Structures
- Pull-UpJPull-Down/Totem PoleJ
Pull-Down with Clamp Diode
Inverting or Non-Inverting Outputs
Symmetrical Rise and Fall Times ................... 25 ns
Short, Equal Delay Times ................................ 75 ns
High Peak Output Current ................................ 1.2A
Wide Operating Range •••....•..•......•....•••.... 4.5 to 18V
Inputs = Logic 1 for Any Input From 2.4V to Voo
2 kV ESD Protection on All Pins
lM
General-Purpose CMOS Logic Buffer
Driving All Four MOSFETs in an H-Bridge
Direct Small Motor Driver
Relay or Peripheral Drivers
Dual Differential Output Power Drivers
CCD Driver
Pin-Switching Network Driver
LED Driver
High Side Switch
LOGIC DIAGRAMS
TC44X8
TC44X7
1A
1B
2A
2B
3A
3B
4A
4B
1Y
1A
1B
3
4
2Y
2A
2B
2Y
5
6
3Y
3A
3B
3Y
8
9
4Y
4A
4B
4Y
2
- -
VDD
Jlom,",
1
TC446X
VDD
Jj
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
4A
4B
4Y
rOUTPUT
J~
TC448X
VDD
j
JI-OOUTPUT
6-93
-
TC445X
VDD
GND
1029-1
OUTPUT
1
1Y
GND
TC44X9
- -
JI-O
TC443X
VDD
•
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
GENERAL DESCRIPTION
The TC44XX family of four-output CMOS buffer/drivers
are an expansion from our earlier single- and dual-output
drivers. Each driver has been equipped with a two-input
logic gate for added flexibility. Four output configurations
have also been provided, so high-efficiency CMOS drivers
can be used whether the application requires a totem-pole
output or pull-up/pull-down output, or pull-down with a clamp
diode. These different input and output combinations make
these Power Logic'" drivers well suited for a wide range of
applications.
Although commonly used for driving power MOSFETs
and similar highly capacitive loads, these drivers are equally
well suited to driving any other load (capacitive, resistive, or
inductive) which requires a high efficiency, low-impedance
driver capable of high peak currents, rail-to-rail voltage
swings, and fast switching times. For example, relays and
solenoids can be driven with the 445X driver which contains
an internal clamp diode which will shunt inductive flybacks
back to the supply. The 443X driver provides a fast, low
impedance path to ground for devices referenced to the
upper supply rail like indicators, sounders or pin drivers. The
448X driver can source up to 250 mA into loads referenced
to ground. Heavily loaded clock lines, coaxial cables, and
piezoelectric transducers can all be driven easily with the
44XX series drivers. The only limitation on loading is that
total power dissipation in the IC must be kept within the
power dissipation limits of the package.
The TC44XX series drivers are built using Teledyne
Component's new Tough CMOS process, which makes
them easy and forgiving parts to use; capable of giving
reliable service in very demanding operating environments.
They will not latch under any conditions within their power
and voltage ratings. They are not subject to damage when
up to 5V of noise spiking (either polarity) occurs on the
ground line. They can accept up to half an amp of inductive
kickback current (either polarity) into their outputs without
damage or logic upset. In addition, all terminals are protected against ESD to at least 2000V. Even the molding
epoxy used on our plastic packages has been custom
developed to contain less sodium and chlorine contamination than standard commercial molding compounds. In
tests, it demonstrated zero device failures after 10,000
hours in an 85°C, 85% relative humidity environment.
ORDERING INFORMATION
Part No.
Package
TC44**CPD
TC44**COE
14-Pin Plastic DIP
16-Pin Wide SOIC
TC44'*EPD
14-Pin Plastic DIP
16-Pin Wide SOIC
TC44'*EOE
TC44**EJD
TC44**MJD
Temp. Range
0° to +70°C
0° to +70°C
_40° to +S5°C
_40° to +S5°C
14-Pin CerDIP
-40° to +S5°C
14-Pin CerDIP
-55° to + 125°C
"Two digits must be added in this position to define the device input
and output configuration:
TC44XX
.----=L
3
5
6
8
Pull-Down
Pull-Down with Clamp Diode
Pull-Up and Down
Pull-Up
7 NAND
8 AND
9 AND with INV
The first digit represents output structure. The second digit represents
input logic. Example: TC4487 has a pull-up output and a NAND input.
TRUTH TABLE
Outputs
Inputs
Part No.
A
B
443X
445X
446X
448X
TC44'7
NAND
H
H
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
F
F
F
F
L
L
L
L
F
L
L
L
F
F
F
F
L
L
L
L
F
L
L
L
H
H
H
H
L
L
L
L
H
L
L
F
H
H
H
H
F
F
F
F
H
F
F
TC44*S
AND
TC44'9
AND!
INV
H = High
6-94
L = Low
F = Floating
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................................................... +20V
Input Voltage ......................... (GND - 5V) to (Voo + 0.3V)
Maximum Chip Temperature
Operating ........................................................ +150°C
Storage ............................................... -65° to +150°C
Maximum Lead Temperature
(Soldering, 10 sec) .......................................... +300°C
Operating Ambient Temperature Range
C Device ................................................... 0° to +70°C
E Device ............................................... -40° to +85°C
M Device ............................................. -55° to +125°C
Power Dissipation
JD Package (14-Pin CerDIP) ............................ 1.25W
PO Package (14-Pin Plastic DIP) ....................... 1.5W
OE Package (16-Pin Wide SOIC) .......................... 1W
Package Thermal Resistance
JD Package (14-Pin CerDIP)
RSJ.A ............. 10 mW/oC
RSJ.c ............ .45 mW/oC
PO Package (14-Pin Plastic DIP) RSJ-A ............. 12 mWrC
RSJ-c ............. 20 mW/oC
OE Package (16-Pin Wide SOl C) ReJ-A ................ 8 mWrC
RqJ-c ............. 31 mW/oC
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devic~s from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: Measured at TA= +25°C with 4.5V '" Voo '" 18V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Input
VIH
Logic 1, High Input Voltage
Note 3
2.4
VIL
Logic 0, Low Input Vo~age
Note 3
0
VDD
0.8
liN
Input Current
OV",VIN",VDD
-1
1
VOH
High Output Voltage
ILOAO = 10 rnA (Note 1)
VOL
Low Output Voltage
ILOAD = 10 mA (Note 1)
Ro
IpK
Output Resistance
lOUT = 10 mA, VDD = 18V
loe
Continuous Output Current
Single Output
Total Package
I
Latch-Up Protection
Withstand Reverse Current
4.5V'" VDD "" 16V
V
~A
Output
V
Voo-O.15
10
Peak Output Current
0.15
V
15
n
1.2
A
300
500
500
mA
mA
mA
SWitching Time
tR
Rise Time
Figure 1
15
25
ns
tF
Fall Time
Figure 1
15
25
ns
tD1
Delay Time
Figure 1
40
75
ns
tD2
Delay Time
Figure 1
40
75
ns
Power Supply
Is
Power Supply Current
VDD
Power Supply Vo~age
mA
V
Note 2
6-95
III
POWER LOGIC CMOS
QUAD DRIVERS
TC4467/8/9
TC4487/8/9
TC4437/8/9
TC4457/8/9
ELECTRICAL CHARACTERISTICS: Measured throughout operating temperature range with 4.5V ..;;; VDD";;; 18V,
unless otherwise specified.
Parameter
Symbol
Test Conditions
Min
2.4
Typ
Max
Unit
Input
VIH
Logic 1, High Input VoHage
(Note 3)
VIL
Logic 0, Low Input VoHage
(Note 3)
liN
Input Current
OV";;;VIN,,,VDD
VOH
High Output Voltage
ILOAD
VOL
Low Output VoHage
ILOAD
Ro
Output Resistance
lOUT = 10 mA, VDD
IpK
Peak Output Current
I
Latch-Up Protection
Withstand Reverse Current
V
0.8
-1
1
V
!!A
Output
=10 mA (Note 1)
=10 mA (Note 1)
V
VDD-D·30
= 18V
20
0.30
V
30
n
1.2
A
500
4.5V'" VDD";;; 16V
mA
SWltchmg Time
tR
Rise Time
Figure 1
50
ns
tF
Fall Time
Figure 1
50
ns
tD1
Delay Time
Figure 1
100
ns
tD2
Delay Time
Figure 1
100
ns
Power Supply
Is
Power Supply Current
Is
Power Supply VoHage
mA
V
Note 2
NOTES: 1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.
2. When driving all four outputs simultaneously in the same direction, Voo shall be limited to 16V. This reduces the chance that internal
dv/dt will cause high-power dissipation in the device.
3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to
dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5 Ils to avoid high internal
peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input
levels specified in the 'Electrical Characteristics' to avoid increased power dissipation in the device.
PIN CONFIGURATIONS
PACKAGE POWER DISSIPATION
1500
~---"T---r--""'---"----'
1250
1A
18
~
S
14-Pin
Dual-In-Une
Package
16-Pin Wide SO
750r----+~~~~~_r----+---_;
,F
500r----+----+-~~~~-+----1
250r----+-----+----_r~~~--_;
OL-__
25
~
50
__
~
____
75
~
100
__
~
__
125
~
150
AMBIENT TEMPERATURE COC)
6-96
voo
Voo
2A
1Y
28
2Y
3A
3Y
38
4Y
GND
48
GND
4A
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
Supply Bypassing
Large currents are required to charge and discharge
large capacitive loads quickly. For example, charging a
1000 pF load 18V in 25 ns requires a 0.8A current from the
device's power supply.
To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low inductance ceramic disk
capacitors with short lead lengths «0.5 in.) should be used.
A 1 ~F film capacitor in parallel with one or two 0.1 ~F
ceramic disk capacitors normally provides adequate bypassing.
Grounding
The TC44X7 and TC44X9 contain inverting drivers.
Ground potential drops developed in common ground impedances from input to output will appear as negative
feedback and degrade switching speed characteristics.
Individual ground returns for input and output circuits or
a ground plane should be used.
TC4467/8/9
TC4487/8/9
Three components make up total package power
dissipation:
(1) Load caused dissipation (PLl
(2) Quiescent power (Pa)
(3) Transition power (Pr).
A capacitive-load-caused dissipation (driving MOSFET
gates), is a direct function of frequency, capacitive load, and
supply voltage. The power dissipation is:
where: f = Switching frequency
C = Capacitive load
Vs = Supply voltage.
A resistive-load-caused dissipation for ground-referenced loads is a function of duty cycle, load current, and
load voltage. The power dissipation is:
Input Stage
The input voltage level changes the no load or quiescent
supply current. The N-channel MOSFET inputstagetransistor drives a 2.5 mA current source load. With logic "0"
outputs, maximum quiescent supply current is 4 rnA. Logic
"1" output level signals reduce quiescent current to 1.4 rnA
maximum. Unused driver inputs must be connected to VDD
or Vss. Minimum power dissipation occurs for logic "1"
outputs.
The drivers are designed with 50 mV of hysteresis. This
provides clean transitions and minimizes output stage current spiking when changing states. Input voltage thresholds
are approximately 1.5V, making Logic 1 input any voltage
greater than 1.5V up to VDD. Input current is less than 1 ~
over this range.
Power Dissipation
The supply current versus frequency and supply current
versus capacitive load characteristic curves will aid in determining power dissipation calculations.
Teledyne Components' CMOS drivers have greatly
reduced quiescent DC power consumption. Maximum quiescent current is 4 mA, compared to the D469's 20 rnA
specification.
Input signal duty cycle, power supply voltage, and load
type influence package power dissipation. Given power
dissipation and package thermal resistance, the maximum
ambient operation temperature is easily calculated. The 14pin plastic package junction-to-ambient thermal resistance
is 83.3°C/W. At +25°C, the package is rated at 1500 mW
maximum dissipation. Maximum allowable chip temperature is +150°C.
6-97
where: D = Duty cycle
Vs =Supply voltage
VL = Load voltage
IL = Load current.
A resistive-Ioad-caused dissipation for supply-referenced loads is a function of duty cycle, load current, and
output Voltage. The power dissipation is:
where: f = Switching frequency
Va =Device output voltage
IL = Load current.
Quiescent power dissipation depends on input signal
duty cycle. Logic high outputs result in a lower power
dissipation mode with only 0.6 rnA total current drain (all
devices driven). Logic low outputs raise the currentto 4 rnA
maximum. The quiescent power dissipation is:
Po = Vs (D(lH) + (1-D)ILJ,
where: IH = Quiescent current with all outputs low
(4 rnA max)
IL = Quiescent current with all outputs high
(0.6mAmax)
D = Duty cycle
Vs =Supply Voltage.
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
Transition power dissipation arises in the totem-pole
configuration (TC446X) because the output stage
N-channel and P-channel MOS transistors are ON
simultaneously for a very short period when the output
changes. The transition power dissipation is approximately:
Maximum operating temperature:
where: TJ
(+150°C)
9JA = Junction-to-ambient thermal resistance
(83.3°CIW) 14-pin plastic package.
PT =f Vs (10 X 10-9).
Package power dissipation is the sum of load, quiescent and transition power dissipations. An example shows
the relative magnitude for each term:
C = 1000 pF capacitive load
Vs = 15V
D =50%
f =200 kHz
PD = Package Power Dissipation
= Maximum allowable junction temperature
NOTE:
Ambient operating temperature should not exceed +85°C for
'EJO' device or +125°C for "MJD' device.
=PL + Po + PT
= 45 mW + 35 mW + 30 mW = 110 mW.
Voo
+5V
1A
18
2A
28
3A
38
4A
48
VOUT
470pF
INPUT
(A,B)
-O.4V
10%
VOO - - OUTPUT
OV
Figure 1 Switching Time Test Circuit
6-98
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
CHARACTERISTICS CURVES
Rise Time vs Supply Voltage
(TC446X, TC448X)
Fall Time vs Supply Voltage
(TC443X, TC445X, TC446X)
140
140
2200lpF
120
100
0
.:.
80
w 1- 1000
!!l 60
~
40
120
f-16001~
I--
i'-...
re.::, ..........
r--..... .............
J . . . . . r-.... r--
47~~
--
1'\
100 1-150!
20 r-loopF
9
7
11
13
VSUPPLY(V)
15
17
~
19
5
Rise Time vs Capacitive Load
(TC446X, TC448X)
/
V
80
!!l 60
S
20 ioo"'"
.-V
J
~
II
40
o
.s
:::J
j,lOY
15V
w
5
o
VSUPPLY= 17.SV
cLOAO = 470 pF
---
-50
J
19
1
.1
::::::-
0 60
.s
w
:;
J
t(RISE)
(TC446X, TC448X)
25
50
75
TEMPERATURE (DC)
V
10,000
1000
CLOAO(PF)
Propagation Delay Time vs Supply Voltage
i= 40
100
\
...........
r::::: r-............
S
w
Q
o
i-'10V
15V
80
t(FALL)
(TC443X, Ti445X, ~
.,::::::::::::. ~
-25
J.....- 1--"'1-'"
~oo
10,000
Rise/Fall Times vs Temperature
~ 10
17
/
~
40
20
25
.s
V
.::-
V
I--'"
80
-'
~ 60
1000
CLOAO(pF)
015
15
11 5V
100
r-
20
11
13
VSUPPLY(V)
120
5V
100
-
9
140
120
w
7
Fall Time vs Capacitive Load
(TC443X, TC445X, TC446X)
140
o
•
~
r-r--
1--4701~
I
.s
~
l000'pF........... r--..
20 I- 100 eF
5
2200P~
125
6-99
-
CL01AO=
47~ pF
1
1
l.
.L
t Ol
(TC446X, TC448X)
1
t02
,~(TC443X, TC445X, TC446X)
20
6
8
10
12
VSUPPLY (V)
1
14
1
16
18
POWER LOGIC CMOS
QUAD DRIVERS
TC4467/8/9
TC4487/8/9
TC4437/8/9
TC4457/8/9
CHARACTERISTICS CURVES (Cont.)
Input Amplitude vs Delay Times
Propagation Delay Times vs Temperature
140
120
70
Voo= 12V
r\.
I\.
w
:;; 80
-'
w
c
40
!w 50
to~
"
i=
>
60
c(
60 r--
"INPUT RISING
I 100
I~FALUNG .......... """'-
w
4
3
5
6
VORIVE (V)
7
9
8
~
t02
- ---~
~
C
r---
20
2
-~ t::- ~
40
tOl
r-- toll
l,....-
-
~
S
1
I
I
I
Voo= 17.5V
CLOAO = 470 pF VIN= 0, 5V
30
2~
10
-40
o
-20
~
~
60
TEMPERATURE eC)
80
1~
100
Quiescent Supply Current vs Temperature
Quiescent Supply Current vs Supply Voltage
2.5
3.5
,I
2.0
/
ct
E
-;'1.5
Z
~
w 1•O
5
--:::::
,iJ
0.5
6
-"
~ r--
ct
.§. 2.5
--
OUTPUTV'
10
12
VSUPPLY(V)
14
16
-
-
I-
iij2.0
o
131.5
5
25
~20
o
jg 15
a:
-
0.5
o
18
-60
-40
-20
0
20
40
60
TJUNCTION (OC)
80
100
120
Low-State Output Resistance
(TC443X, TC445X, TC446X)
35
35
a
"""
OUTPUTS LOW
High-State Output Resistance
(TC446X, TC448X)
30
l,....- V
~
OUTPUTS HIGH
_01.0
OUTPUTS = 1
8
VOO =17.5V
3.0
.........
"
..................
30
I.
TJ= +150°C
I
"""
25
I"...l
~20
Z
r--
-
TJ = +25°C
..........
g15
--..;".,--
10
a: 10
5
5
...............
-........-. r--
---
TJ = +150°C
TJ = +25°C
6
8
10
12
14
16
o
4
18
VSUPPLY(V)
6-100
6
8
10
12
VSUPPLY(V)
14
16
18
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
SUPPLY CURRENT CHARACTERISTICS (Load on Single Output Only)
Supply Current vs Frequency
(TC446X)
Supply Current vs Capacitive Load
(TC446X)
60
50
60
.l.
fiMH~
Voo= 18V
I
l000pF
< 40
/
.,..,...
10
o
-- ---'"
100
~ 30
--
./
0.
0.
500kHz
~ 20
20~kH~
./
.... 10-'
I
~
20 kHz
~o
10,000
1000
CLOAO(pF)
~ 30
o
100
10,000
Voo= 12V
/
--- --
l'P~
/
100
1000
FREQUENCY (kHz)
~
~
I--
/2200 pF
50
V
S
10
,;
..
Supply Current vs Frequency
(TC446X)
j2MH.
< 40
.¥ 20
I
/
60
Voo= 12V
50
0.
0.
---../~
10
I
Supply Current vs Capacitive Load
(TC446X)
60
/
S
/
V
IJ 220J PFi
Voo= 18V
50
MH,
/
If
1 MHz
/
-............
1000 pF
v~
10- 500kHz
r-
I I
10
20? k~Z
20kHz
-:::::: ~J.-o'
10,000
100
FREQUENCY (kHz)
Supply Current vs Capacitive Load
(TC446X)
/
1l
i--"""
1000
liP!
10,000
Supply Current vs Frequency
(TC446X)
60
60
VOp=6V
VOO=6V
50
50
<40
S
2200pF
>-
10
~oo
/
--
",
.........
1000
CLOAO(pF)
2i
~ 30
HZ
A
0.
:::I
.!!' 20
~1
MHz
I-- 500kHz
200 kHz
20kHz
";°iPr
10
10,000
6-101
_J.-o'
100
1000
FREQUENCY (kHz)
...J.l~~F
10,000
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
TYPICAL APPLICATIONS
Quad Relay Driver Interface
Stepper Motor Drive
+5VTO+15V
+5VTO+15V
14
DIGITAL
CONTRO
LOGIC
1
2
3
4
5
6
TC4469
"'"
TC
4459
8
12
RELAY
4
11
A0-44-+::.t-a
10
9
BD-1~-+-+--I
7
Quad Driver for H-Bridge Motor Control
+5VTO +15V
6-102
POWER LOGIC CMOS
QUAD DRIVERS
TC4437/8/9
TC4457/8/9
TC4467/8/9
TC4487/8/9
TYPICAL APPLICATIONS (Cont.)
48-Volt, 3-Phase Brushless Output Stage
48V
R3
3.3
kQ
+---r---r-------11 1A
01
1N4744
2 18
......--r-----t-""-I3 2A
R1
3.3
4 28
5
kQ
5W
......----~13A
U1
11
6 38
3Yi-'-'----t--------'-'-'F:::..-----t
8
02
03
04
4A 4~
10
9 48 ""II 4Y
TC4469
GND
7
15V
1 1A
r--____::i
2 18
.----+--:3;-l2A
4 28
5 3A
U2
6 38
3Y\-1:..:.1----t---------f---------l
8
4A 4~
10
9 48 ""II 4Y
C-
LED Driver Interface
+5V TO +15V
14
VDD
DIGITAL
CONTROL
LOGIC
1
~~
2 1A TC4439
13
18
1Y
3
2A
12
4
28
2Y
5
3A
11
6
38
3Y
8
4A
9
10
48
4Y
6·103
\\ \\ \\
\\ \\ \\
\\ \\ \\
\\ \\ \\
NOTES
6··104
~~TELEDYNE
COMPONENTS
TC4460
TC4461
TC4462
TC4463
CURRENT-SENSING, 6 AMP POWER MOSFET DRIVER
FEATURES
•
•
•
•
•
•
•
Complete Fault-Sensing Power Driver
- High Peak Output Current Driver
- Comparator
-Latch
High Peak Output Current ..•....................•...........• 6A
Matched Rise and Fall Times
High Capacitive Load Drive
Capability .....•.....•.....•....•.....•....•.....• 2500 pF in 25 ns
Output Swing to within 25 mV of DGND or Voo
Low Output Impedance •...•.•...••....••....•.....•...•.•... 2.5Q
Fast Comparator ....................................... 170 ns typ
•
•
•
•
Precision Comparator Threshold ... 100 mV ±10 mV
Latch Status Output
Tough CMOSTM Construction
Logic Input Will Withstand Negative Swing
Upto-5V
Latch-up Protected: Will Withstand> 1.5A
Reverse Output Current
Logic High Input, Any Supply Voltage 2.4V to Voo
Low Supply Current
-With Logic '1·lnput.. .........•......•.....•....•.....•... 6 mA
- With Logic '0' Input ....................................... 3 mA
•
•
•
FUNCTIONAL DIAGRAM
VDD
VDD
12
13
r .. -.. -.. --------------------------------- --------- -.. ------.. -------------.. ---.. --.. -------------.. ~
.!!
.i!
NON·INVERTING
OUTPUT
INPUTO--i-_~
:10
t-_-+."-0 vOUT
:11
'--+-:....oVOUT
DGNDO-,8'-!-.....---...--'
DGND'o-=9'-t-----'
>---t..:.:14'-OLOCK
RESETO""2'+----..!.
VS+
3
IN+
56
IN-
-4~!
''I11III
TC4460-TC4463
100mV
I:.'.
--"-t--II-....- - - i
too _________ .... __ .. ______ ____ .. ______________________ .. ___ .. ______ .. ___ .. _.. _.. _______ .... __ .......... ______ .. j
7
CBYPASS
4
AGND
NOTE: PIN NUMBERS SHOWN FOR 14·PIN DIP.
4351 ILL FOl
1030-1 (4351)
6·105
-=~
CURRENT-SENSING, 6 AMP
POWER MOSFET DRIVER
TC4460
TC4461
TC4462
TC4463
GENERAL DESCRIPTION
ORDERING INFORMATION
The TC4460/4461/446214463 are high speed CMOS
drivers which incorporate a comparator input to terminate
the output pulse. These devices are ideal for driving power
MOSFETS, such as SENSEFETS®, which include a separate output which mirrors drain current.
The TC4460 devices consist of a power driver, comparator, and latch. In normal operation the device operates
as a power driver with a 6 A peak current totem-pole
output. When the comparator threshold is exceeded, the
latch is set and the output turns off. The output will not turn
on again until the latch is reset. A 'LOCK' output is provided to signal that the output is disabled.
The TC4460 is ideal for applications which require fast
response to an overload condition, such as PWM motor
drive circuits. The response time is enhanced because the
overload indication does not have to propagate through the
control loop circuitry. Instead, the comparator directly
monitors the SENSEFET current and turns off the driver
output. The comparator delay is typically only 170 ns.
The comparator threshold is set internally at 100 mV
±10 mV. In most applications the comparator threshold will
be referenced to analog ground, but the comparator common mode range extends from 0 V to 3 V.
With a comparator threshold of only 100 mV, low value
resistors can be used to monitor the SENSEFET's current.
Low impedances maximize the SENSEFET linearity, as
well as improving response time and reducing noise.
The totem-pole output will sink or source 6 A peak
current, with an output impedance of 2.5Q. Output swing is
to within 25mV of either supply rail, which ensures that a
power MOSFET will be turned fully ON or fully OFF. Rise
and fall times are only 25 ns with a 2500 pF load. Maximum load capacitance is essentially limited by package
power dissipation.
The TC4460/4461/446214463 are built with Teledyne
Component's Tough CMOSTM process. Digital inputs are
protected from noise spikes up to 5V below ground, while
the output will accept up to 1.5A of reverse current (of
either polarity) without damage.
Part No.
TC4460CPD
TC4460COE
TC4460EPD
TC4460EOE
TC4460MJD
TC4461CPD
TC4461COE
TC4461EPD
TC4461EOE
TC4461MJD
TC4462CPD
TC4462COE
TC4462EPD
TC4462EOE
TC4462MJD
TC4463CPD
TC4463COE
TC4463EPD
TC4463EOE
TC4463MJD
6-106
Output
Reset
Polarity Polarity Package
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
Inverting
Inverting
Inverting
Inverting
Inverting
Noninverting
Noninverting
Noninverting
Noninveiting
Noninverting
Inverting
Inverting
Inverting
Inverting
Inverting
Temp
Range
Low 8-Pin PDIP
O°Cto+70°C
Low 8-PinSOIC
O°Cto+70°C
Low 8-Pin PDIP -40°C to +85°C
Low 8-PinSOIC -40°C to +85°C
Low 8-Pin CerDI P -55°C to + 125°C
Low 8-Pin PDIP -55°Cto+125°C
Low 8-Pin PDIP -55°Cto+125°C
Low 8-Pin PDIP -55°Cto+125°C
Low 8-Pin PDIP -55°Cto+125°C
Low 8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°Cto+125°C
Hi
8-Pin PDIP -55°C to + 125°C
Hi
8-Pin PDIP -55°Cto+125°C
CURRENT-SENSING, 6 AMP
POWER MOSFET DRIVER
TC4460
TC4461
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Digital and Analog ........................... +22V
Input Voltage, Pins 1 and 2 ......... VDD+0.3V to GND-5.0V
Input Voltage,
Pins5 and 6 ................. Vs++0.3V to Analog GND-0.3V
Maximum Chip Temperature ................................. + 150°C
Storage Temperature Range .................. --65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Package Thermal Resistance
CerDIP RBJ-A ................................................ 150°CIW
CerDIP RBJ-C ................................................... 55° C/E
PDIP RBJ-A .................................................... 125°CIW
PDIP RBJ-C ..................................................... 45°CIW
SOIC RBJ-A ................................................... 250°C/W
SOIC RBJ-C ..................................................... 75°C/W
Operating Temperature Range
C Device ................................................ O°C to + 70°C
E Device ............................................. --40°C to +85°C
M Device .......................................... -55°C to +125°C
Power Disipation
Plastic DIP ................................................... 1000 mW
CerDIP ........................................................... 800 mW
SOIC .............................................................. 500mW
DIP
LOCK
VDD
~'"
TC4460TC4463
V DD
V OUT
VOUT
CBVPASS
SOIC
INPUT
LOCK
1
VDD
~'"
TC4460TC4463
CBVPASS
VDD
VOUT
VOUT
Static-sensitive device. Unused devices must be stored in ccnductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
DGND
IN+
7
TC4462
TC4463
DGND
NC
NOTE: DUPLICATE PINS MUST BOTH BE
CONNECTED FOR PROPER OPERATION.
NC = NO INTERNAL CONNECTION
4351 ILL 02
6-107
_
. .
CURRENT-SENSING, 6 AMP
POWER MOSFET DRIVER
TC4460
TC4461
TC4462
TC4463
ELECTRICAL CHARACTERISTICS: TA = +25°C with 4.5V::;; Voo::;; l8V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
I
Units
Input
VIH
Logic 1 High Input Voltage
2.4
Vil
IN
Logic 1 Low Input Voltage
-
Input Current
OV" VIN "Voo
-
-
-
V
0.8
V
-10
-
10
J.LA
Voo-O.025
-
Output
VOH
High Output Voltage
VOL
Low Output Vottage
_.
-
0.025
V
V
Ro
Output Resistance, High
IOUT= 10mA, Voo = 18V
-
2.2
2.8
.Q
Ro
IpK
Output Resistance, Low
IOUT= 10mA, Voo = 18V
-
1.9
2.5
.Q
-
6
-
A
IREV
Latch-Up Protection
Withstand Reverse Current
Duty Cycle" 2%
t" 300 J.Ls
1.5
-
-
A
-
21
25
ns
21
25
ns
-
65
75
ns
65
75
ns
Peak Output Current
SWltchmg Time (Note 1)
tR
Rise Time
Figure 1, Cl = 2500 pF
tF
FaliTime
Figure 1, Cl = 2500 pF
t01
Delay Time
Figure 1, CL = 2500 pF
t02
Delay Time
Figure 1, CL = 2500 pF
Comparator (Note 1)
IIN+
Comparator Input Bias
Current (Plus)
-
-
1
J.LA
liN-
Comparator Input Bias
Current (Minus)
-
-
150
J.LA
Vos
Comparator Offset
90
Comparator Common Mode
Range
-
110
VeMR
3
V
170
200
ns
170
200
ns
70
100
ns
90
120
0
-
Teoo
Comparator Delay to VOUT
25 mV Overdrive
Teol
Comparator Delay to LOCK
25 mV Overdrive
TROL
Reset Delay to LOCK
TRDO
Reset Delay to Output
Latch Input High
Pin 2, RESET
2.4
-
Latch Input Low
Pin 2, RESET
-
-
Power Supply Current
VIN = 3V (Both Inputs)
VIN = OV (Both Inputs)
VIHl
VILL
------ ----------- -
-------
mV
ns
V
0.8
V
Power Supply
Is
NOTES: 1. Switching times guaranteed by design.
6-108
mA
mA
CURREN~SEN~NG,6AMP
POWER MOSFET DRIVER
TC4462
TC4463
TC4460
TC4461
ELECTRICAL CHARACTERISTICS: Over operating temperature range with 4.5V$ VDD = 18V, unless
otherwise specified.
Symbol
Parameter
Test Conditions
Min
I Max I Units
Typ
Input
VIH
Logic 1 High Input Voltage
VIL
Logic 1 Low Input Voltage
IN
Input Current
2.4
-
-
f - - - - . - - f---------.
OV ~ VIN ~ VDD
-10
-
VDD-0.025
-
0.8
V
V
10
J.tA
-
V
Output
VOH
VOL
High Output Voltage
Ro
Output Resistance, High
IOUT= 10mA, VDD = 18V
Ro
IpK
Output Resistance, Low
IOUT= 10mA, VDD = 18V
IREV
Latch-Up Protection
Withstand Reverse Current
._._-
Low Output Voltage
-- ------ c--------
Peak Output Current
Duty Cycle
t ~ 300 J.ts
~
2%
2.8
-
3.5
1.5
-
6
5
-
.-
0.025
V
- - - c------5
Q
-
Q
A
A
SWltchmg Time (Note 1)
tR
Rise Time
Figure 1, CL = 2500 pF
-
30
35
ns
tF
FaliTime
Figure 1, CL
35
ns
Delay Time
-
30
tD1
80
90
ns
tD2
Delay Time
= 2500 pF
Figure 1, CL = 2500 pF
Figure 1, CL = 2500 pF
-
80
90
ns
-
Comparator (Note 1)
IIN+
Comparator Input Bias
Current (Plus)
-
-
1
J.tA
IIN-
Comparator Input Bias
Current (Minus)
-
150
J.tA
Vos
Comparator Offset
85
-
115
VeMR
Comparator Common Mode
Range
0
-
3
mV
V
-_.. ---- ------- ------------ -- 280
-150
ns -._----- -----------150
280
Comparator Delay to LOCK
ns
. _ - - - - - - - - - - - - ....... __._-_.- .. _.---- - - - - - - - - - ,---------Reset Delay to LOCK
70
140
ns
. ---_.- - - 90
160
ns
Reset Delay to Output
--_.
-------- - - - - - - ---------Latch Input High
Pin 2, RESET
V
2.4
-V
Latch Input Low
Pin 2, RESET
0.8
.. _----_.
.~-.--
TeDo
TeDL
Comparator Delay to VOUT
25 mV Overdrive
25 mV Overdrive
~----------
TRDL
TRDO
VIHL
VILL
Power Supply
Is
Power Supply Current
VIN = 3V (Both Inputs)
VIN = OV (Both Inputs)
NOTES: t. Switching times guaranteed by design.
6-109
mA
mA
•
CURRENT-SENSING, 6 AMP
POWER MOSFET DRIVER
TC4460
TC4461
TC4462
TC4463
SWITCHING TIME TEST CIRCUIT
..()OUTPUT
INpuTo-----'-+---i ~)-------=JJ+-=.:..:...:.-
I
I
I
I
3
VS+ = 16Vo--.:.....,...------,
6
~'" ::
TC4460TC4463
5
:
I
I
I
1____ -
_______ _
7
_____________ JII
4
INPUT: 100 kHz, SQUARE WAVE,
tRISE = tFALL ~ 10ns
4351 ILL F03
NONINVERTING DRIVER
INVERTING DRIVER
INPUT
INPUT
t02
16V --~'!!IL
OUTPUT
OUTPUT
OV _ _ _.r
4351 ILL F04
4351 ILL FOS
6-110
.,"TELEDYNE
COMPONENTS
TC4626
TC4627
POWER CMOS DRIVERS WITH
VDD
TRIPLER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC4626/4627 are single CMOS high speed drivers
with an on board voltage tripler. Three external capacitors
are required for the voltage tripler function. The part works
with input supply voltages from 2.6 volts to 6 volts depending
on the exact load requirements. An internal undervoltage
lockout circuit keeps the driver section disenabled while the
voltage at VORIVE remains below 9 volts.
Power driver with on Board Voltage Tripier
Low IDD < 2.0 mA
Small Package - 8 Pin PDIP
Under voltage Circuitry
Fast Rise-Fall Time < 50 ns @ 1000pF
Below Rail Input Protection
FUNCTIONAL DIAGRAM
..r. --
EXT
-C1+
®
T ___ C1- -=-----1
EXT
G) 10V
..r.--- C2 ®
7
15V
VORIVE
EXT
7
VOLTAGE
TRIPLER
Voo -+----1
IN
GNO ___- - ' - - - - - - - - -...
NOTE: Pin numbers correspond to 8-pin package
1031·1
®
~--~~----~r-------------'-----l
6-111
-=_.
POWER CMOS DRIVERS WITH VDD TRIPLER
TC4626
TC4627
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Part No.
Package
TC4626MJA
a·Pin CerDIP
TC4627MJA
a·Pin CerDIP
TC4626EPA
a·Pin PDIP
TC4627EPA
a·Pin PDIP
TC4626EOE
16·Pin SOIC
TC4627EOE
16·Pin SOIC
TC4626CPA
a·Pin PDIP
TC4627CPA
a·Pin PDIP
TC4626COE
16·Pin SOIC
TC4627COE
16-Pin SOIC
Power Dissipation
PDIP ................................................................ 500mW
CerDIP .............................................................. 800mW
Derating Factor
PDIP ........................................ 5.6 mW/oC Above 36°C
CerDIP ......................................................... 6.0 mW/oC
Supply Voltage ............................................................ 18V
Input Voltage, Any Terminal ....... V s + 0.3V to GND -Q.3V
Operating Temperature: M Version ........ -55°C to +125°C
EVersion ........... -40°C to +85°C
C Version .............. O°C to +70°C
Maximum Chip Temperature ................................. + 150°C
Storage Temperature .............................. -60 D C to + 150°C
Lead Temperature (10 sec) ................................... +300°C
PIN CONFIGURATIONS
SOIC
DIP
6-112
POWER CMOS DRIVERS WITH VDD TRIPLER
TC4626
TC4627
ELECTRICAL CHARACTERISTICS
Symbol
Driver Input
(TA = 25°C Voo= 5V C, = C 2 = C 3 1OIJ.F unless otherwise specified.)
Parameter
Test Conditions
I
Min
I
Typ
I
Max
I
Unit
V IH
Logic 1, Input Voltage
2.4
-
-
V
VIL
Logic 0, Input Voltage
-
0.8
V
liN
Input Current
-1
-
1
IlA
VOAIVE-0.025
-
OV ,,;; V IN ,,;; VOAIVE
Driver Output
V OH
High Output Voltage
VOL
Low Output Voltage
Ro
Output Resistance
VIN = 0.8V
-
-
-
-
V
0.025
V
10
15
n
-
6
10
n
-
1.5
-
A
-
40
ns
40
ns
-
-
40
ns
1.0
-
-
IOlIT = 10 rnA, Voo = 5V
VIN = 3V
IOlIT = 10 rnA, Voo = 5V
Peak Output Current
IpK
SWltchmg Time
tA
Rise Time
Test Figure 1,2
tF
Fall Time
Test Figure 1,2
to,
"Delay Time
Test Figure 1,2
t02
FMAX
Delay Time
Test Figure 1,2
R3
Voltage Tripier Output
Source Resistance
R2
Voltage Doubler Output
Source Resistance
Maximum Switching Frequency
Test Figure 1
40
ns
MHz
Voo = 5V, VOAIVE> 10V
IL = 10 rnA, Voo =5V
-
220
400
n
-
120
200
n
12
-
28
KHz
4.5
-
-
V
Fosc
Oscillator Frequency
Vose
Oscillator Amplitude
Measured at C1-
UV
UndelVoltage Threshold
@ VOAIVE
8.5
9
9.5
V
V STAFrr
Start Up Voltage
@ VOAIVE
10.5
11
11.5
V
VOAIVE
@V oo =5V
No Load
14.7
-
R LOAo = 10Kn
-
V
Power Supply
Power Supply Current
VIN = LOW or HIGH
rnA
V
Supply Voltage
6-113
POWER CMOS DRIVERS WITH Voo TRIPLER
TC4626
TC4627
SWITCHING TIME TEST CIRCUITS
VDRIVE
VDRIVE
':"
o
0
INPUT
®
INPUTo--I---I I~)--IH~
® Cl+
lOIlF
OUTPUT
Cl+
Cl
CD
Cl-
® C2
~~
TC4627
®
-=-
101lF~C2
':"
+5V
+5V - -
INPUT*
-
-
-,._-----..J
INPUT*
-O.4V
~0.4V
10%
VDRIVE - - -
VDRIVE --~=L
OUTPUT
OUTPUT
OV _ _ _ _-'I
OV
"100kHz SQUARE WAVE
"100kHz SQUARE WAVE
t,=lt
TA =1+25'C
<"
e
;;8
CJ
.5.100
zW
i3
w
Ul
II:
/
W
>
W
V
4
!:iD..
2
I-
o
0.25 0.5 0.75 1.0 1.25
OUTPUT VOLTAGE (VI
1.5
II:
o
LL
~
0
0.01
1
10
0.1
REVERSE CURRENT (mAl
I
I
:>
TA=+25'C
<"
.5. 8
w
.5. 100
INPUT
zW
§
o
I}l
J:
~
0.1
o
200
400
TIME (msl
o
600
0.5
5
J
CJ
~ 4
g
I:l
D..
0
TC05
Response Time
T A =+25'C
w
c
II:
~ 0.4
~
./
0.6
~
3
§! 2
OUTPUT
II:
o
LL
0.2
o
0.01
0.1
1
10
FORWARD CURRENT (mAl
100
o
o
2
/
I:l
~ 0
~
200
400
TIME (msl
7-4
II
6
....I
INPUT
w
~ 0.8
I
w
1.0
1.5 2.0 2.5
OUTPUT VOLTAGE (VI
10
-t~~~I~~,t
~1.0
...-
~
,
II:
TC05: Forward Voltage vs
Forward Current
1.2
!f
II:
0.5
o
10
u
100
I
c(
u
OUTPUT
111111111 I
TA = +25'C
Z
II:
CJ
~ 1.5
0.1
1
10
,FORWARD CURRENT (mAl
CJ
I-
0
I---'
TC05: Output Voltage Change
vs Reverse Current
10
TA = +25'C
/
0
0.01
100
TC05: Output Voltage vs
Reverse Current
5.0
> 1.0
-
,/
0.2
1000
10.0
§!
g 0.6
c
~
:;:: 0.4
:l
TC04
Response Time
~
w
~
I
§!
V
II:
~
V
w
~ 0.8
CJ
~
i~I~I~~5'~
~1.0
w
10
0.1 0
1.2
~~ ~ ~~15'~
z
~
() 6
I-
II:
II:
f-
TC04: Forward Voltage vs
Forward Current
600
3.0
o
0.01
0.1
1
10
REVERSE CURRENT (mAl
100
Section 8
Chopper-Stabi Iized
Operational Amplifiers
Display AID Converters
1
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifier.
8
High Performance Amplifiers!Buffers
9
Video Display Drivers
10
Display Drivers
11
Anaiog Switches and Multiplexers
12
Data Communications
13
Discrete OM OS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
"'~TELEDYNE
COMPONENTS
TC900
LOW POWER, CHOPPER-STABILIZED OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The TegOO is a low power, precision operational amplifier. Its 200 f.lA maximum supply current reduces device
power requirements over 15 times, compared to 7650
devices.
Offset voltage isa low 5 JlV with drift at 0.05 JlV/oC.lnput
offset voltage (Vos) errors are removed and adjustment
potentiometers are not necessary. The chopper-stabilized
error-correction technique keeps offset voltage errors near
zero throughout the device's operating temperature range.
The TegOO performance advantages are achieved
without additional manufacturing complexity and costs incurred with laser or "zener zap" Vos trim techniques. The
TC900 is one of the lowest cost, low power, precision operational amplifiers available.
The TegOO nulling scheme corrects both DC Vos errors
and Vos drift errors with temperature. A nulling amplifier
alternately corrects its own Vos errors and the main amplifier
Vas errors. Offset-nulling voltages are stored on two usersupplied external capacitors. The capacitors connect to the
internal amplifier Vos null points. The main amplifier input
signal is never switched. The nulling scheme keeps Vos
Low Power Dissipation ................................... 2 mW
Low Power Supply Current ......................•... 140 JlA
Low-Input Offset Voltage .................•........ 5 JlV Max
Low-Input Offset Voltage Drift ....... 0.05 JlVloC Max
High-Impedance Differential CMOS Inputs ..• 10120
High Open-Loop Voltage Gain .............. 120 dB Min
Low Input Noise Voltage ..•..•......•.............• 0.3 JlVp.p
High Slew Rate ............................................. O.2 VlJls
Unity-Gain Stable
Available in 8-Pin DIP and SO
FUNCTIONAL DIAGRAM
-- ~;IE-:r -- -:
OUTPUT
CLAMP
OSCILLATOR
EXTCLKIN '
INTCLKOUT:
14-PINDIP
,
ONLY
,
B' - - - - - - - - -'
+
~--~~----------------OOUTPUT
B'
CAANDCB
EXTERNAL
CAPACITORS
~f'"
TC900
NULL
AMPLIFIER
1(199.1
8-1
8
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
errors low throughout the operating temperature range. Laser
and "zener zap" trimming can correct for Vos at only one
temperature.
The nulling-circuit oscillator and control circuits are
integrated on-chip. Only two external Vos error storage
capacitors are required. The TC900 operates as a
conventional operational amplifier with vastly improved input
specifications. The low Vos and Vos drift errors make the
TC900 ideal for thermocouple, thermistor, and strain gauge
applications. Low DC errors and high open-loop gain make
the TC900 an excellent preamplifier for precision analog-todigital converters, such as the TC7135, TC850 and TC71 09A.
The 14-pin package has an external oscillator input to
drive the nulling circuitry. Both the 8-pin and 14-pin packages
have an output voltage clamp circuit to minimize overload
recovery time.
PIN CONFIGURATIONS
14-Pin DIP
INT/EXT
8-Pin SO
8-Pin DIP
"r--
"r--
TC900
13 ~XlU~LOCK
NC
(GUARD)
"r--
TC900
TC900
NC
(GUARD)
12
~JT~~~CK
v~
OUTPUT
CLAMP
NC =NO INTERNAL CONNECTION
ORDERING INFORMATION
Part No.
Package
Temperature
Range
Maximum
Vos
Maximum
Supply Current
TC900ACPA
TC900ACOA
TC900AIJA
TC900ACPD
8-Pin Plastic DIP
8-Pin SO
8-Pin CerDIP
14-Pin Plastic DIP
14-Pin CerDIP
8-Pin Plastic DIP
8-Pin SO
8-Pin CerDIP
14-Pin Plastic DIP
14-Pin CerDIP
O·Cto+70·C
O·Cto +70·C
-25·C to +85·C
O·Cto +70·C
-25·C to +85·C
O·C to +70·C
O·Cto +70·C
-25·C to +85·C
O·Cto+70·C
-25·C to +85·C
51!V
51!V
51!V
51!V
51!V
151!V
151!V
151!V
151!V
151!V
2OOl!A
2OOl!A
2OOl!A
200l!A
2OOl!A
4OOl!A
4OOl!A
400 l!A
400l!A
400l!A
TC900AIJD
TC900BCPA
TC900BCOA
TC900BIJA
TC900BCPD
TC900BIJD
8-2
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
Package Power Dissipation (TA = 25°C) .............. 500 mW
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs+to VS-) ............................. +18V
Input Voltage ........................... (Vs+ +0.3V) to (Vs- -O.3V)
Voltage on Oscillator Control Pins .................... Vs+ to VsOutput Short-Circuit Duration .............................. Indefinite
Current Into Any Pin ................................................ 10 rnA
While Operating (Note 4) ................................. 100 IlA
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Static-sensitive device. Unused devices must be stored in conductive
material to protect them from possible static damage. Stresses above those
listed under' Absolute Maximum Ratings' may cause permanent damage
to the device. These are stress ratings only and functional operation of the
device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL CHARACTERISTICS: Vs+ = +5V, Vs- = -5V, CA = CB = 0.1 I!F, TA = +25°C
Symbol
Parameter
Test Conditions
Unit
Input
-
Vos
Input Offset Voltage
TCVos
Input Offset Voltage vs
Temperature Coefficient
Operating Temperature
Range (Note 1)
IBIAS
Average Input Bias
Current (Note 5)
TA = +25°C
DoC';; T A ,;; + 70°C
-25°C,;; T A ,;; +85°C
los
Input Offset Current
TA = +25°C
eN
Input Noise Voltage
Rs = 100.0, 0.1 Hz to 10Hz
Rs = 100.0, 0.1 to 1 Hz
RIN
CMVR
CMRR
Common-Mode Rejection Ratio
CMVR = -5V to +2V
Av
Large-Signal Voltage Gain
VOUT
Output Vo~age Swing
(Note 3)
-
0.02
5
-
-
15
0.05
-
0.1
0.3
I!V
l!V/oC
-
-
-
-
80
100
140
pA
pA
pA
0.5
-
pA
-
I!Vp.p
I!Vp.p
-
-
-
50
70
100
0.5
-
-
-
4
0.3
-
-
Input Resistance
-
1012
Common-Mode Voltage Range
Vs
110
130
RL= 10 k.Q
120
130
RL= 10 k.Q
RL = 100 k.Q
-4.7
-4.9
-
-
+3.5
+3.9
Clamp ON Current (Note 2)
RL= 100 k.Q
20
90
200
20
Clamp OFF Current (Note 2)
-4V < VOUT < 4V
-
1
-
-
1
0.7
-
-
0.7
-
MHz
0.2
-
V/j.lS
0.5
-
I!S
%
-
-
-
-
-
4
0.3
-
1012
Vs+-2
Vs
-
100
-
-
.0
Vs+-2
V
-
dB
Output
-
100
-4.7
-4.9
-
+3.5
+3.9
-
V
V
90
200
I!A
-
pA
dB
Dynamic
BW
Unity-Gain Bandwidth
Unity Gain (+1)
SR
Slew Rate
C = 50 pF, RL = 100
k.o
Rise Time
Overshoot
fCH
Internal Chopping Frequency
Pins 12-14 Open (14-Pin DIP)
-
0.2
0.5
18
150
-
-
18
-
150
Hz
Supply
Vs+to Vs-
Operating Supply Range
4.5
-
16
4.5
Is
PSRR
Supply Current
No Load
-
140
200
Power Supply Rejection Ratio
Vs = ±3V to ±8V
120
-
-
-
NOTES: 1.
2.
3.
4.
5.
Operating temperature range is -25°C to +85°C for 'I' grade and O°C to +70'C for 'C' grade.
See 'Output Clamp' discussion.
Output clamp not connected.
Limiting input current to 100 j.lA is recommended to avoid latch-up problems.
Average current caused by switch charge transfer at input.
B-3
100
-
16
-
400
-
-
V
I!A
dB
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
Chopper-Stabilized Operational Amplifiers
Clock Operation
The TC900 is the first commercially-available, lowpower, chopper-stabilized amplifer. Its maximum supply
current is 15 times lower than the pin-compatible TC7650.
Figure 1 shows how low supply current is achieved without
sacrificing offset voltage or offset voltage drift performance.
The internal oscillator is set for a 150 Hz nominal
chopping frequency. With the 14-pin device, the 150 Hz
internal chopping frequency is available at the INTERNAL
CLOCK OUTPUT (pin 12). A 300 Hz nominal signal will be
present at the EXTERNAL CLOCK INPUT pin (pin 13) with
INT/EXT high or open. This is the internal clock signal
before a divide-by-two operation.
The 14-pin device can be driven by an external clock.
The INTfEXT input (pin 14) has an internal pull-up and may
be left open for internal clock operation. If an external clock
is used, INT/EXT must be tied to Vs- (pin 7) to disable the
internal clock. The external clock signal is applied to the
external clock input.
Nulling-Capacitor Connection
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is made to
Vs- (pin 4) on the 8-pin device and to capacitor return- (CRET,
pin 8) on the 14-pin device. The common connection should
be made through a separate PC trace or wire to avoid
voltage drops. Internally, Vs- is connected to CRET. (See
Figure 2.)
10mA
IZ
W
r-'-
a:
a:
I-
>
....
IL
IL
:::l
1/1
-
"''" 1= "''" =
:::l
0
1 mA
I-
~
=
=
-
II-
-
t=
::;;
:::l
::;;
~
::;;
"''"
l00IlA
"''"
ll-
TC900A TC900B TC7650A TC7650
Supply Current vs Offset Voltage
Supply Current vs Vos Drift
10mA
!Zw
10mA
"'m~650i
a:
a:
a:
a:
almA
>
....
IL
:::l
1/1
~
::;;
almA
~
"'~TC900B-
IL
f---
!Zw
t9f':TC7650
IL
IL
~
::;;
l00IlA
~
1~TC~'01~
",,"TC9OOB
:::l
1/1
i'1I,"TC900A
;1," TC7650
i'1I,"TC900A
l00IlA
~
::;;
::;;
10 llA
0.01
0.1
1
MAXIMUM OFFSET VOLTAGE
DRIFT /llVrc)
lOIlA
ll1V
10
Figure 1
8-4
lOIlV
l00IlV
MAXIMUM OFFSET VOLTAGE
1 mV
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
l
NTERNAL POSITIVE
CLAMP BIAS
P-CHANNEL
ri~t~----o
__
-r;
H---oVS
~
OUTPUT
CLAMP PIN
N-CHANNEL
INTERNAL NEGATIVE
CLAMP BIAS
L - - - - - - - - o 6t~~8T PIN
14-PIN PACKAGE
8-PIN PACKAGE
Figure 3. Internal Clamp Circuit
(PIN a IS INTERNALLY CONNECTED
to PIN 7 ON 14-PIN PACKAGE)
O.lI1F
O.lI1F
Figure 2. Nulling Capacitor Connection
The external clock amplitude should swing between Vs+
and ground for power supplies up to ±6V, and between Vs+
and Vs+ -f3V for higher supply voltages.
At low frequencies, the external-clock duty cycle is not
critical, since an internal divide-by-two gives the desired
50% switching duty cycle. The offset storage correction
capacitors are charged only when the external clock input is
high. A 50% to 80% external-clock positive duty cycle is
desired for frequencies above 500 Hz to guarantee transients settle before the internal switches open.
The external clock input can also be used as a strobe
input. If a strobe signal is connected at the external clock
input, so that it is low during the time an overload signal is
applied, neither capacitor will be charged. Leakage currents
INPUT--t_----1
>-......--1. OUTPUT
R3 + (R11R2) ;;. 100 k.Q
FOR FULL CLAMP EFFECT
CONNECT CAPACITORS TO
Vs WITH a-PIN PACKAGE
Figure 4. Noninverting Amplifier With Optional Clamp
Output Clamp
Chopper-stabilized systems can show long overload
recovery times. If the output is driven to either supply rail,
output saturation occurs; the inputs are no longer held at a
"virtual ground." The Vas null circuit treats the differential
signal as an offset and tries to correct it by charging the
external capacitors. The nulling circuit also saturates. Once
the input signal returns to normal, the response time is
lengthened by the long recovery time of the nulling amplifier
and external capacitors.
Through an external clamp connection, the TC900
eliminates the overload recovery problem by reducing the
feedback network gain before the output voltage reaches
either supply rail.
The output clamp circuit is shown in Figure 3, with typical
inverting and noninverting circuit connections shown in
Figures 4 and 5. Output voltage versus clamp circuit current
INPUT
'>-.....--1.
OUTPUT
(Rlll R2 ) ;;.100kQ
FOR FULL CLAMP
EFFECT
O.lI1F O.lI1F
CONNECT CAPACITORS TO
Vs WITH 8-PIN PACKAGE
Figure 5. Inverting Amplifier With Optional Clamp
characteristics are shown in the typical operating curves.
Forthe clamp to be fully effective, the impedance across the
clamp output should be >100 kil.
8-5
•
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
Static Protection
junctions are at the same temperature, thermoelectric voltages, typically around 0.1IlV/oC, but up to tens of 1l~/oCfor
some materials, will be generated. In order to realize the
benefits extremely low offset voltages provide, it is essential
to take special precautions to avoid temperature gradients.
All components should be enclosed to eliminate air movements, especially those caused by power-dissipating elements in the system. Low thermoelectric-coefficient connections should be used where possible, and power supply
voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and separation
from surrounding heat-dissipating elements is advised .
All device pins are static-protected. However, strong
static fields and discharges should be avoided, as they can
degrade diode junction characteristics and increase inputleakage currents.
Many companies are actively involved in providing
services, educational materials, and supplies to aid electronic manufacturers in establishing "static safe" work areas
where CMOS components are handled. Two such companiesare:
• 3M
Static Control Systems Division
223-25W EM Center
St. Paul, MN 55101
(800) 792-1072
Pin Compatibility
On the 8-pin TC900, the external null storage capacitors
are connected to pins 1 and 8. On most other operational
amplifiers these are lett open, or are used for offset potentiometer or compensation capacitor connections .
For OP05 and OP07 operational amplifiers, the replacement of the offset null potentiometer between pins 1 and 8
by two capacitors from the pins to Vs- will convert the OP051
07 pin configuration forTC900 operation. For LM1 08 devices,
the compensation capacitor is replaced by the extemal
nulling capacitors. The LM1 01/7481709 pinouts are modified
similarly by removing any circuit connections to pin 5. On the
TC900, pin 5 is the output clamp connection. Other operational amplifiers may use this pin as an offset orcompensation
point.
The minor modifications needed to retrofit a TC900 to
existing sockets operating at reduced power supply voltages make prototyping and circuit verification straightforward.
• Semtronics
P.O. Box 592
Martinsville, NJ 08836
(210) 561-9520
Input Bias Current
The TC900 inputs are never disconnected from the
main internal amplifier. The null amplifier samples the input
offset voltage and corrects DC errors and drift by storing
compensating voltages on external capacitor~. However,
the sampling causes charge transfer at the Inputs. The
charge transfer represents a peak impulse current of
200 nA to 290 nA at the inputs when the internal clock
makes a transition.
Latch-Up Avoidance
Component Selection
Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteri~
tics similar to an SCA. Under certain circumstances, thiS
junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition,
voltages greater than 0.3V beyond the supply rails should
not be applied to any pin. In general, the amplifier supplies
must be established at the same time (or before) any input
signals are applied. If this is not possible, the drive. circuits
must limit input current flow to under 0.1 rnA to avoid latchup.
The two required capacitors, CA and Cs, have optimum
values, depending on the clock or chopping frequency. For
the present internal clock, the correct value is 0.1 .IlF. To
maintain the same relationship between the chopping frequency and the nulling time constant, the capacitor values
should be scaled in proportion to the external clock, if used.
High~quality, film-type capacitors (such as Mylar) are preferred. Ceramic or other lower-grade capacitors may be
suitable in some applications. Forfast settling on initial turnon, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several
seconds may be required to settle to microvolt levels.
Thermoelectric Potentials
Precision DC measurements are ultimately limited by
thermoelectric potentials developed in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all
8-6
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
TYPICAL CHARACTERISTICS CURVES
Input Voltage Noise vs
External Clock Frequency
30
Ii.
d.
>
\
\\
a.
~ 20
o
Z
w 15
~
g
10
Rs
i
~
'" 100Q
CI
VSI~ ~~~V
P~~I~W~I s~IIJ~1
Z
~
4
~ 3
'f'
oJ
g
~
I-
~
:::l
r-..I"-
5
o
i"""
I
CI
o
2
1
o
100
FREQUENCY (Hz)
10
1k
100
1k
10k
100k
LOAD RESISTANCE (Q)
Positive Clamp Current
r-
I
VS =:t5V
I
/'
/
(.)
100pA
10pA
1 pA
3.0
I
/
I
100J.lA -VS=:t5V
J
./
10l1A
ffi 111A
1/
a:
/
§
100nA
(.)
IL
10 nA
::;;
:5
J
1nA
I
(.)
100pA
10pA
/
3.2
3.4
3.6
3.8
4.0
POSITIVE OUTPUT VOLTAGE (V)
1 pA
-3.8
4.2
~
6
Z
r-T1 =+~5.C
""",
~ 4
""", ......
w
~ 2
:;
g 0
l!l-2
~
z-4
""",
..........
r---....
~-6
::;;
8-8
,;'
.......
r---....
..........
"
02345678
SUPPLY VOLTAGE (V)
8-7
/
I
-4.0 -4.2 -4.4 -4.6 -4.8
NEGATIVE OUTPUT VOLTAGE (V)
Input Common-Mode Voltage Range
vs Supply Voltage
~ 8
i"""
/
I-
if
1 nA
1M
Negative Clamp Current
1 mA
!Z 1 J.lA
Il!a: 100 nA
G 10nA
IL
~
NE~I~~~~ SWI~~
5
w
l-
1!:
6
~W= 0.1 Lz~~ 110lJJ
\
25
Output Voltage Swing
vs Load Resistance
-s.o
LOW POWER, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC900
TYPICAL CHARACTERISTICS CURVES (Cont.)
Offset Voltage vs
Common-Mode Voltage
Slew Rate
~
RL=100kn
I- GAIN = +1
II
INTPUT
~
~
1\
g
;."J
1\ ZERO
'if~UTPUT- VOLTS
HORIZONTAL SCALE = 5 ~IV
300
r- T~ = ~25'cl
~240
ffi
~
~ 180
~
U
>
/
150
~ 120
/
~ 90
III
_10- r--
...-V
20
10
V
- TC900B
210
V
o
'\
TA= +25'C
VS=:t5V
1\
-6 -0 -4 -3 -2 -1 0 1 2 3
COMMON-MODE VOLTAGE (V)
o
r--r...........
......... 1'
iii'
~-10
z
./
<-20
TC900A
" -30
60
30
\
4
Gain and Phase vs Frequency
30
/
-_4>-----------+6-0 OUTPUT
NOTES: 1. 'Internal capacitors; external capacitors not required.
2. Pin numbers are for S·pin 01 P.
1100·1
S-9
8
MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC901
PIN CONFIGURATION (DIP and SO)
Notable electrical characteristics are low supply current
(450 IJA, typical), single-supply operation (5V to 32V), low
input offset voltage (7 I1V, typical), low noise «5 I1Vp-p,
typical, for a 10Hz bandwidth), and fast recovery from
saturation without the use of external clamp circuitry.
~""
TC901
Pin Compatibility
The CMOS TC901 is pin compatible with other chopperstabilized amplifiers, such as the 7650, 7652 and 1052.
Amplifiers such as the 7650 require 0.1 I1F external capacitors connected to pins 1 and 8. The TC901 includes the
chopper capacitors on-chip, so external capacitors are not
required. Since pins 1, 5 and 8 of the TC901 are not
connected, the TC901 can directly replace other chopperstabilized amplifiers in existing circuits.
The TC901 pinout also matches many popular bipolar
and JFET op-amps, such as the OP-07, OP20, LM1 01,
LM1 08, 356 and 741. In many applications that operate from
±15V power supplies, the TC901 offers superior electrical
performance and is a functional pin-compatible replacement. Offset voltage correction potentiometers, compensation capacitors, and chopper-stabilization capacitors can be
removed when retrofitting existing equipment designs.
System parts count, assembly time, and system cost are
reduced, while reliability and performance are improved.
ORDERING INFORMATION
Part No.
Package
TC901COA
TC901CPA
TC9011JA
TC901MJA
8-Pin
8-Pin
8-Pin
8-Pin
SO
Plastic DIP
CerDIP
CerDIP
Temperature
Range
NC
=NO INTERNAL CONNECTION
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs+ to Vs-) ............................. +36V
Input Voltage ............................. (Vs++0.3V) to (Vs--O.3V)
Current Into Any Pin ................................................ 10 rnA
While Operating ............................................... 100 IJA
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering,·10 sec) .................. +300°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
M Device .......................................... -55°C to +125°C
Package Power Dissipation (TA = +25°C)
CerDIP ........................................................... 500 mW
Plastic DIP ..................................................... 375 mW
O°C to +70°C
O°C to +70°C
-25°C to +85°C
-55°C to + 125°C
Static-sensitive device. Appropriate precautions should be taken when
handling, shipping, or storing these devices. Stresses above those
listed under 'Absolute Maximum Ratings' may cause permanent
damage to the devices. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
8-10
MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC901
ELECTRICAL CHARACTERISTICS: Vs ±15V, TA =+25°C, unless otherwise indicated (each amplifier).
Symbol
Parameter
Test Conditions
Min
Typ
Max
Vos
Input Offset Voltage
(Figure 2)
TA = +25°C
-
7
15
VosffC
Average Temperature
Coefficient of Input
Offset Voltage
O°C.;;TA .;;+70°C
-
0.05
0.15
ISlAS
Average Input Bias
Current
TA = +25°C
0°C.;;TA.;;+70°C
-25°C.;; TA';; +85°C
-
50
10
10
los
Average Input Offset Current
eN
Input Voltage Noise
(Figure lB)
TA=+25°C
0.1 to 1 Hz, Rs';; loon
-
30
0.2
0.2
eN
Input Voltage Noise
(Figure lAl
0.1 to 10 Hz, Rs .;;100n
-
CMRR
Common-Mode Rejection
Ratio
Vs ,;;VCM.;;Vs+-2V
CMVR
Common-Mode Voltage
Range
Vs = ±5V to ±15V
AOL
Open-Loop Voltage Gain
Output Voltage Swing
RL= 10 kQ, Vs= ±15V
Closed-Loop Bandwidth
(Figure 7)
Closed-Loop Gain = +1
VOUT
BW
RL= 10 kQ
50
100
1.2
-
!lVp-p
5
-
!lVp-p
120
140
-
dB
Vs
-
120
140
-
V
dB
-
Vs+-l.2
-
0.8
-
MHz
2
-
V/!lS
Slew Rate
RL = 10 kQ, CL = 50 pF
-
Power Supply Rejection Ratio
Vs = ±5Vto±15V
120
140
Vs
Operating Supply Voltage
Range
Note 1
±3
-
Quiescent Supply (Figure 2)
Vs = ±15V
-
B-l1
Vs+-2
Vs +1
PSRR
1. Single supply operation: Vs· = +5V to +32V.
!lV/DC
pA
nA
nA
pA
-
sr
Is
NOTE:
Units
!lV
0.45
V
dB
±16
V
0.6
rnA
MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC901
2V
INPUT
2VIDIV OV
N
J:
5!2:
l
~~
_::L
o-
s:
,,-
OV
N
J:
0
.>
OUTPUT
5VIDIV
~~
_::L
0-
~
-15V
2
0
3
4
5
1 seclDlV
Figure 1
./
"",V
9
I
(
10
12
.....
18
J".. 1-'
!I
lij
20
11
14
16
~
o
7
8
9
10
5 msIDlV
Figure 3
Input Voltage Noise
VOS -......- 0 OUTPUT
GAIN =40
Rl = 1 kn
R2 = 40 k!l
Figure 5
8-12
Saturation Test Circuit
MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC901
Thermocouple Errors
Avoiding Latch-Up
Heating one joint of a loop made from two different
metallic wires causes current flow. This is known as the
Seebeck effect. By breaking the loop, an open-circuit voltage (Seebeck voltage) can be measured. Junction temperature and metal type determine the magnitude. Typical values are 0.1 ~V/oC to 10 ~V/oC. Thermal-induced voltages
can be many times larger than the TC901 's offset voltage
drift. Unless unwanted thermocouple potentials can be
controlled, system performance will be less than optimum.
Unwanted thermocouple junctions are created when
leads are soldered or sockets/connectors are used. Low
thermoelectric coefficient solder can reduce errors. A 60%
Cd/40% Sn Pb solder has one-tenth the thermal voltage of
common 64% Snl36% Pb solder at a copper junction.
The number and type of dissimilar metallic junctions in
the input circuit loop should be balanced. If the junctions are
kept at the same temperature, their summation will add to
zero-canceling errors (Figure 6).
Shielding precision analog circuits from air currents especially those caused by power dissipating components
and fans - will minimize temperature gradients and minimize thermocouple-induced errors.
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding the
supplies by 0.3V should not be applied to the device pins.
Larger voltages can turn the p-n-p-n device on, causing
excessive device power supply current and excessive power
dissipation. TC901 's power supply should be established at
the same time (or before) input signals are applied. If this is
not possible, input current should be limited to 100 ~ to
avoid triggering the p-n-p-n structure.
Static Protection
Input pins are protected against electrostatic fields.
Static handling procedures should be used with all CMOS
devices. Many companies provide services, educational
material, and supplies to aid electronic equipment manufacturers establish "static safe" CMOS component handling
areas. Two such companies are:
• 3M
Static Control Systems Division
223-23W EM Center
St. Paul, MN 55101
(800) 792-1072
• Semtronics
P.O. Box 592
Martinsville, NJ 08836
(201) 561-9520
J3
J -- J4}
J
NO TEMPERATURE DIFFERENTIAL
J~: J~ AND SAME METALLIC CONNECTION.
J2
>
Figure 6
Unwanted Thermocouple Errors Eliminated by Reducing
Thermal Gradients and Balancing Junctions
8-13
8
MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC901
+50
+40
........
-
+30
+20
iii'
+10
~
0
~
+240
~
- -.......-
"
+180
-'..... ~
~~
CI
-10
PHASE MARGIN
I-- 10 k.Q with 50 pF LOAD
36' at 700 kHz at 70'C
-30
I-- 40' it 800 kHi at 25'C
-20
-120
-180
-40
1
10
100
lk
10k
FREQUENCY (Hz)
Rgure 7
lOOk
1M
Phase-Gain
BONDING DIAGRAM
8-14
~"'TELEDYNE
COMPONENTS
TC911
AUTO-ZEROED MONOLITHIC OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
Wide Bandwidth ........................................... 1.5 MHz
High Open-Loop Voltage Gain
(RL = 10 kn) .................................................... 120 dB
Low Input Voltage Noise
(0.1 Hz to 1 Hz) ..................•...•••...........••.•.. 0.65 11Vp_p
Pin Compatible With ICL7650
Lower System Parts Count
•
•
First Monolithic Chopper-Stabilized Amplifier
With On-Chip Nulling Capacitors
Offset Voltage .................................................... 5IlV
Offset Voltage Drift •.•..•••............•.....•..•.... 0.05IlV/OC
Low Supply Current ..•••.••••.•.••.••...••.•.••••.•••...• 350 IlA
High Common-Mode Rejection .................... 116 dB
Single Supply Operation ....................... 4.5V to 16V
High Slew Rate .•.•.••••.•.•••.••••.••....••.•..••.••..••••. 2.5 V/lls
•
•
•
II
FUNCTIONAL DIAGRAM
Vs
~'"
Vii
TC911
4
-INPUT
2
7
Vos CORRECTION AMPLIFIER
+
A
B
B
INTERNAL
OSCILLATOR
(fOSC ~200 Hz)
~
+INPUT
LOW IMPEDANCE
OUTPUT BUFFER
3
*NOTE: Internal capacitors. No external capacitors required.
1101·1
8·15
6
OUTPUT
AUTO-ZEROED MONOLITHIC
OPERATIONAL AMPLIFIER
TC911
GENERAL DESCRIPTION
The TC911 CMOS auto-zeroed operational amplifier is
the first complete monolithic chopper-stabilized amplifier.
Chopper operational amplifiers like the ICL7650n652 and
LTC1052 require user-supplied, extemal offset compensation storage capacitors. External capacitors are not required with the TC911. Just as easy to use as the conventional 741 type amplifier, the TC911 significantly reduces offset voltage errors. Pinout matches the OP07/741/
7650 a-pin mini-DIP configuration.
Several system benefits arise by eliminating the external chopper capacitors: lower system parts count; reduced
assembly time and cost; greater system reliability; reduced
PC board layout effort and greater board area utilization.
Also, space savings can be significant in multiple-amplifier
designs.
Electrical specifications include 151lV maximum offset
voltage, 0.15 /lV/DC maximum offset voltage temperature
coefficient. Offset voltage error is five times lower than the
premium OP07E bipolar device. The TC911 improves offset drift performance by eight times.
Low offset voltage errors eliminate trim procedures
during manufacturing, periodic recalibrations, and reliability problems caused by damaged or misadjusted trim potentiometers.
The TC911 automatically corrects offset voltage drift
with time. Operational amplifier long-term drift is less easily
controlled and more expensive to maintain when low offset
errors are obtained by trimming thin-film resistors. The
TC911 internal circuits correct errors repetitively at a 200 Hz
rate. Long-term drift is effectively eliminated.
The TC911 operates from dual or single power supplies. Supply current is typically 350 IJ.A. Single 4.5V to 16V
supply operation is possible, making single 9V battery
operation possible. The TC7660 DC-to-DC converter can
easily supply a negative potential in dual-supply applications where only a +5V system supply is available.
Open-loop voltage gain is 115 dB minimum with a 10 kQ
load. Unity gain bandwidth is 1.5 MHz. Slew rate is 2.5 Vllls.
Common-mode rejection ratio is 116 dB. Input commonmode range extends from 2V below the positive supply to
the negative supply.
The TC911 is available in three package types: a-pin
plastic DIP, ceramic DIP and SO-package. Die are available
for hybrid applications.
For precision dual- and quad-monolithic chopperstabilized amplifiers, see the TC913 (dual) and TC914 (quad)
data sheets.
ORDERING INFORMATION
Part No.
Package
TC911ACPA
B·Pin
Plastic DIP
B-Pin SO
B-Pin
Plastic DIP
B-Pin SO
B-Pin
CerDIP
8-Pin
CerDIP
TC911ACOA
TC911BCPA
TC911 BCOA
TC911AIJA
TC911BIJA
Temperature
Range
Maximum
Offset
Voltage
O·Cto +70·C
15J.1V
O·Cto+70·C
O·Cto+70·C
15J.1V
30J.1V
O·Cto +70·C
-25·C to +B5·C
30J.1V
15J.1V
-25·C to +B5·C
30J.1V
PIN CONFIGURATION (SO and DIP)
NC
=NO INTERNAL CONNECTION
BONDING DIAGRAM
·f·)OU~p:-
Vi 141
(7)
.·+--.+INF'UT (31
]
ill
.·i!o--INPUT (2)
NOTES: 1. Back of die is common to Vee.
2. Back of die is not metalized.
8·16
AUTO-ZEROED MONOLITHIC
OPERATIONAL AMPLIFIER
TC911
ABSOLUTE MAXIMUM RATINGS
=
Total Supply Voltage (Vs to Wi) ............................... +18V
Input Voltage ............................... (VS+0.3V) to (Vs -0.3V)
Current into Any Pin ................................................ 10 rnA
While Operating .................................... '" ........ 100
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
Package Power Dissipation (TA +25°C)
CerDIP ........................................................... 500 mW
Plastic DIP and SO ........................................ 375 mW
I!A
ELECTRICAL CHARACTERISTICS:
Symbol
Static-sensitive device. Unused devices should be stored in conductive
material. Stresses above those listed under "Absolute Maximum Ratinlls"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sectionsof the specifications is not
implied.
Vs =±5V, TA = +25°C, unless otherwise indicated.
Parameter
Test Conditions
Vos
Input Offset Voltage
TA= +25°C
TCVos
Average Temperature
Coefficient of Input
Offset Voltage
O°C ~ TA ~ +70°C
-25°C ~ TA ~ +85°C
16
Average Input Bias
Current
TA= +25°C
O°C ~ TA ~ +70°C
-25°C ~ TA ~ +85°C
Min
TC911A
Typ
Max
TC911B
Typ
Max
Unit
-
5
15
-
15
30
-
0.05
0.05
0.15
0.15
-
-
0.1
0.1
0.25
0.25
J.LV
J.LV/oC
J.LV/oC
-
-
70
3
4
-
-
-
-
-
120
4
6
pA
nA
nA
-
5
20
10
40
pA
-
0.65
11
J.LVp.p
J.LVp_p
105
110
-
Vs
-
110
120
-
los
Average Input
Offset Current
eN
Input Voltage Noise
0.1 to 1 Hz, Rs ~ 1000
0.1 to 10 Hz, Rs ~ 1000
-
0.65
11
CMRR
Common-Mode
Rejection Ratio
Vs~VcM~VS-2.2
110
116
-
CMVR
Common-Mode
Voltage Range
Vs
-
Vs-2
AOL
Open-Loop Voltage
Gain
RL= 10 kO, Vo= ±4V
115
120
VOUT
BW
Output Voltage Swing
RL=10kO
Closed Loop Gain = +1
Vs+0.3
SR
Slew Rate
PSRR
Power Supply
Rejection Ratio
Vs
Is
Closed Loop
Bandwidth
Min
-
-
1.5
-
-
-
Vs-O.9
Vs+0.3
-
-
1.5
dB
Vs-2
V
-
dB
VIi-0.9
-
V
MHz
RL 10 kO, CL 50 pF
±3.3V to ±5.5V
-
2.5
-
-
2.5
-
112
-
-
105
-
-
V/J.LS
dB
Operating Supply
Voltage Range
Split Supply
Single Supply
±3
4.5
-
-
±B
16
±3
4.5
-
±B
16
V
V
Quiescent Supply
Current
Vs=±5V
-
350
600
-
BOO
J.LA
=
=
8-17
-
..
AUTO-ZEROED MONOLITHIC
OPERATIONAL AMPLIFIER
TC911
TYPICAL CHARACTERISTICS CURVES
700
450
TA= +25·C
\
~400
ffi
./
a: 400
a:
/'
::>
°300
~
Do
!!i
30
-
TA = +25·C
-==
w
rg
r-
5
I
~ 15
IL
IL
Do
:!!:
o
~
~
-
......
y-
INPUT
~
INPUT
50
Output Voltage Swing vs
Load Resistance
j
30
:!!: 20
~
Do
10
g
0
o
5.8
225
11111
~
~
-IGAIN
'PHASE
.
Vs= o,5V
TA= +25·C
RL =10kO
TA = +25·C
180
5.0
VS=~5V
......
135
~
90
....
~.
45
0
6
~
:::-10
~-20
'I
m
•
:!!.
w
l~kwllNW
11111
III
+SWING
INPUT
."
20
....
RL = 10 kO
TA=+ 5·
OUTPUT =
2 VlDIV
h.L
-180
10M
1.0
100
8-18
lk
10k
lOOk
LOAD RESISTANCE (0)
1M
AUTO-ZEROED MONOLITHIC
OPERATIONAL AMPLIFIER
TC911
Pin Compatibility
(Seebeck Voltage) can be measured. Junction temperature
and metal type determine the magnitude. Typical values are
0.1 IlV/oC to 10 IlVfOC. Thermal-induced voltages can be
many times largerthanthe TC911 offset voltage drift. Unless
unwanted thermocouple potentials can be controlled, system performance will be less than optimum.
Unwanted thermocouple junctions are created when
leads are soldered or sockets/connectors are used. Low
thermo-electric coefficient solder can reduce errors. A 60%
Snl36% Pb solder has 1/10 the thermal voltage of common
64% Snl36% Pb solder at a copper junction.
The number and type of dissimilar metallic junctions in
the input circuit loop should be balanced. 1ft he junctions are
kept at the same temperature, their summation will add to
zero-canceling errors (Figure 1).
Shielding precision analog circuits from air currents especially those caused by power dissipating components
and fans - will minimize temperature gradients and thermocouple-induced errors.
The CMOS TC911 is pin compatible with the GEllntersil
ICL7650 chopper-stabilized amplifier. The ICL7650 must
use extemal 0.1 IlF capacitors connected at pins 1 and 8.
With the TC911 , external offset voltage error canceling
capacitors are not required. On the TCS911 pins 1, 8 and
5 are not connected internally. The ICL7650 uses pin 5 as an
optional output clamp connection. Extemal chopper capacitors and clamp connections are not necessary with
the TC911. External circuits connected to pins 1 ,8 and 5 will
have no effect. The TC911 can be quickly evaluated in
existing ICL7650 designs. Since external capacitors are not
required, system part count, assembly time, and total system cost are reduced. Reliability is increased and PC board
layout eased by having the error storage capacitors integrated on the TC911 chip.
The TC911 pinout matches many existing op-amps:
741, LM101, LM108, OPOS-OP08, OP20, OP21, ICL7650
and ICL7652. In many applications operating from +5V
supplies the TC911 offers superior electrical performance
and can be a functional pin-compatible replacement. Offset
voltage correction potentiometers, compensation capacitors, and chopper-stabilization capacitors can be removed
when retrofitting existing equipment designs.
Avoiding Latch-Up
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding the
supplies by 0.3V should not be applied to the device pins.
Larger voltages can turn the p-n-p-n device on, causing
excessive device power supply current and excessive power
dissipation. TC911 power supplies should be established at
the same time or before input signals are applied. If this is not
possible input current should be limited to 0.1 rnA to avoid
triggering the p-n-p-n structure.
Thermocouple Errors
Heating one joint of a loop made from two different
metallic wires causes current flow. This is known as the
Seebeck effect. By breaking the loop, an open circuit voltage
=
=
JJ 3 - JJ 4} NO TEMPERATURE DIFFERENTIAL
J2 J5 AND SAME METALLIC CONNECTION
1- 6
J
2
J1
Static Protection
Input pins are protected against electrostatic fields.
Static handling procedures should be used with all CMOS
devices. Many companies provide services, educational
material, and supplies to aid electronic equipment manufacturers to establish "static safe" CMOS component handling
areas. A partial company list is:
....-------"1
• 3M
• Semtronics
P.O. Box 592
Static Control Systems Div
223-23W EM Center
Martinsville, NJ 08836
St Paul, MN 55101
(201) 561-9520
(800) 792-1072
Overload Recovery
The TC911 recovers quickly from the output saturation.
Typical recovery time from positive output saturation is
20 ms. Negative output saturation recovery time is typically
5ms.
Figure 1. Unwanted Thermocouple Errors Eliminated by
Reducing Thermal Gradients and Balancing Junctions
8·19
AUTO-ZEROED MONOLITHIC
OPERATIONAL AMPLIFIER
TC911
TYPICAL APPLICATIONS
Thermometer Circuit
10-Volt Precision Reference
+9V
"'"
TC911
>""---'-0 VOUT
=10V
"'"
TC911
VOUT = VTEMP [1 +
d VOUT
dT
= [1
R2(~ ~:~
Ra
RJ
+ R1
+'"2\R3 I1R1
)] - [VREF
~J
)~ d (VTEMP ) ~ K (2.1 mVI"C)
J
dT
K=1+~
R3 11R1
Programmable Gain Amplifier With Input Multiplexer
+5V
IN 1 oIN2 OIN3oIN4 o-
INPUT
CHANNEL
SELECT
GND
-5V
9 9
"'"
+5V -5V
~
-
~
TC445
INPUT
SWITCH
A1 ~A3A4WR
r---<
r---<
I--
"'"
+5V
-JiN
?
?
TC445
X1
X10
X100
~ 18k!:! <:> 99k!:!
~,
X1000
S
999kQ
-".
r--
~
WR
68HC11
" ' " TC911
~--~--,--~--,--oVOUT
GAIN
SELECT
A1
~
LATCH
A2 A3 A4
I
I
Ii r~i
1kQ
1 kQ
8·20
-
- -
-
-
~~TELEDYNE
COMPONENTS
TC913
DUAL AUTO-ZEROED OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
First Monolithic Dual Auto-Zeroed Operational
Amplifier
Chopper Amplifier Performance Without External
Capacitors
-Vos ........................................................ 15IJ.VMax
- Vos Drift ....•....•............................. 0.15IJ.VPC Max
- Saves Cost/Assembly of Four "Chopper"
Capacitors
SO Packages Available
High DC Gain ................................................. 120 dB
Low Supply Current ..••.•...••..••....•...••.•..•••.••••. 650 IJ.A
•
•
•
•
•
•
Low Input Voltage Noise
(0.1 Hz to 10 Hz) ••..••....•.....•.....•................ 0.65IJ.Vp_p
Wide Common-Mode
Voltage Range ................................... Vs- to Vs+ -2V
High Common-Mode Rejection .•••.•••••.••.•...•• 116 dB
Dual or Single Supply Operation .......••.. ±3V to ±8V
+4.5V to +16V
Excellent AC Operating Characteristics
- Slew Rate .....•..........•.....•.......................... 2.5 V/lJ.s
- Unity-Gain Bandwidth •..•.•...•••......•.••...•••• 1.5 MHz
Pin Compatible With LM358, OP14, MC1458,
ICL7621, TL082, TLC322
FUNCTIONAL DIAGRAM
vii
4
..,~
TC913
8
r------------------------VOS CORRECTION AMPUFIER
A
A
B
B
INTERNAL
OSCILLATOR
('OSC ~ 200 Hz)
~-------LOW IMPEDANCE
OUTPUT BUFFER
~NPUTO_-+~~----~--~
+INPUT
o_-+-i-------......---I
>-----<~--i----_+-o OUTPUT
1 OF 2 AMPUFIERS SHOWN
"NOTE: Internal capacitors. No external capacitors required.
1102-1
8-21
8
DUAL AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC913
GENERAL DESCRIPTION
The TC913 is the world's first complete monolithic,
dual auto-zeroed operational amplifier. The TC913 sets a
new standard for low-power, precision dual-operational
amplifiers. Chopper-stabilized or auto-zeroed amplifiers offer
low offset voltage errors by periodically sampling offset
error, and storing correction voltages on capacitors. Previous single amplifier designs required two user-supplied,
external 0.1 ItF error storage correction capacitors - much
too large for on-chip integration. The unique TC913 architecture requires smaller capacitors, making on-chip integration possible. Microvolt offset levels are achieved and
external capacitors are not required.
The TC913 system benefits are apparent when contrasted with a TC7650 chopper amplifier circuit implementation. A single TC913 replaces two TC7650's and four
capacitors. Five components and assembly steps are
eliminated.
The TC913 pinout matches many popular dualoperational amplifiers: OP04, TLC322, LM358, and ICL7621
are typical examples. In many applications, operating from
dual 5V power supplies or single supplies, the TC913
offers superior electrical performance, and can be a
functional drop-in replacement; printed circuit board rework
is not necessary. The TC913's low offset voltage error
eliminates offset voltage trim potentiometers often needed
with bipolar and low-accuracy CMOS operational amplifiers.
The TC913 takes full advantage of Teledyne's proprietary CMOS technology. The TC913's 650 IJ.A supply current (250 IJ.A per amplifier) makes the TC913 the lowest
power, precision dual-operational amplifier available. The
250 IJ.A amplifier supply current does not compromise AC
performance. Unity gain bandwidth is 1.5 MHz and slew
rate is 2.5 V/lts.
For single- and quad-operational amplifiers, see the
TC911 and TC914 data sheets.
ORDERING INFORMATION
Temperature
Range
Part No.
Package
TC9l3ACPA
O·Cto +70·C
8-Pin
Plastic DIP
O·Cto +70·C
8-Pin SO
O·Cto +70·C
8-Pin
Plastic DIP
O·Cto +70·C
8-Pin SO
8-Pin
-25·C to +85·C
CerDIP
-25·C to +85·C
8-Pin
CerDIP
TC913ACOA
TC9l3BCPA
TC9l3BCOA
TC913AIJA
TC9l3BIJA
PIN CONFIGURATION (SO and DIP)
"''''
Te913
8-22
Maximum
Offset
Voltage
l 5 1·tV
l5~V
30~V
30~V
15~V
30~V
DUAL AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC913
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs to Vi) ............................... +18V
Input Voltage ............................... (Vs+0.3V) to (Vi -0.3V)
Current into Any Pin ................................................ 1 0 mA
While Operating ............................................... 100 IJ.A
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
ELECTRICAL CHARACTERISTICS:
Package Power Dissipation (TA = +25°C)
CerDIP ........................................................... 500 mW
Plastic DIP and SO ........................................ 375 mW
Static-sensitive device. Unused devices should be stored in conductive
material. Stresses above those listed under "Absolute Maximum Ratings"
may cause pennanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied.
VS = ±5V, TA = +25°C, unless otherwise indicated.
Symbol
Parameter
Test Conditions
Vos
TCVos
Input Offset Voltage
Average Temperature
Coefficient of Input
Offset Voltage
TA= +25°C
O°C ~ TA ~ +70°C
-25°C ~ TA ~ +85°C
-
18
Average Input Bias
Current
TA = +25°C
O°C 5 TA 5 +70°C
-25°C 5 TA 5 +85°C
-
Vs
Is
-
Max
Unit
-
15
0.1
0.1
30
0.25
0.25
~V
90
3
4
20
-
-
120
6
40
pA
nA
nA
pA
-
0.6
11
-
~Vp_p
-
-
~Vp_p
100
110
-
dB
Vs-2
V
-
-
0.6
11
Common-Mode
Rejection Ratio
Common-Mode
Voltage Range
Vs5VCM~VS-2.2V
110
116
-
Vs
-
Vs-2
Vs
-
Open-Loop Vottage
Gain
Output Voltage Swing
Closed-Loop
Bandwidth
Slew Rate
RL=10kO,Vo=±4V
115
120
-
110
120
RL= 10 kO
Closed Loop Gain = +1
Vs+0.3
Wi-0.9
Vs +0.3
CMRR
PSRR
15
0.15
0.15
-
Input Voltage Noise
SR
5
0.05
0.05
-
TC913B
Typ
Min
0.1 to 1 Hz, Rs 51000
0.1 to 10 Hz, Rs ~ 1000
eN
Your
BW
Max
5
Average Input
Offset Current
AOL
-
TC913A
Typ
-
los
CMVR
Min
Power Supply
Rejection Ratio
Operating Supply
Voltage Range
Quiescent Supply
Current
-
-
ViI-0.9
dB
-
1.5
-
V
MHz
-
-
2.5
-
100
-
-
dB
-
±8
16
±3
4.5
-
-
-
±8
16
V
V
0.65
0.85
-
-
1.1
mA
1.5
-
RL= 10 kO, CL= 50 pF
±3.3V ~ Vs ~ ±5.5V
-
2.5
110
-
Split Supply
Single Supply
±3
4.5
Vs=±5V
-
8-23
10
4
~V1°C
~V1°C
V/~s
DUAL AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC913
TYPICAL CHARACTERISTICS CURVES
Supply Current vs
:I:
Supply Voltage
Input Offset Voltage vs Common-Mode Voltage
35
1200
TA = +25°C
.:!:
.::
ffi
w
800
600
V
~
IL
IL
:::J
~
./
a:
a:
i3
400
--
f..-~~
200
I-
~
o
I-
:::J
~
40
I
30
~ 20
Cl
96
. ..
~
8
PHASE
Vs= :t5V
TA=+25°C
RL = 10 k.Q
5.0
I"-
10
135
~
90
~ 4.2
45
~,
0
0
~
~ -10
,./
~ -4 -3 ~ ~
0 1 234
INPUT COMMON-MODE VOLTAGE (V)
TA=~25°C
180
.... I',
GAIN
"-
Output Voltage Swing vs Load Resistance
225
IIII
r-r-
"- .....
5
o
Gain and Phase vs Frequency
50
10
IL
34567
:I: SUPPLY VOLTAGE (V)
2
15
I>-
V
o
25
g 20
/
III
IL
VS=:l:SV
TA = +25°C
>" 30
<"1000
-45
9
() -20
gu
w
~
!:iIL
!:i
::r::
IL
o
,....
~
~
i:2-
-SO
-30
Vs=:l:SV
11111 IIII
-SWING
I I I II
""
+SWING
2.6
" 1.8
-135
-40
10k
-180
10M
lOOk
1M
FREQUENCY (Hz)
1.0
100
Negative Overload Recovery Time
lk
10k
lOOk
LOAD RESISTANCE (0)
1M
Positive Overload Recovery Time
RL = 10k.Q
-TA =+2So C
L
OJJT=
2VIDIV
L
INPUT
J
OV-
1'1,
J
ov _
OUTPUT
INPUT
=2VIDV
GAIN =-20
INPUT
GAIN =-20
HORIZONTAL SCALE = 20 msIDlV
HORIZONTAL SCALE = 20 mslDlV
8-24
DUAL AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC913
Theory of Operation
Avoiding Latch-Up
Each of the TC913's two op-amps actually consists of
two amplifiers. A main amplifier is always connected from
the input to the output. A separate nulling amplifier alternately nulls its own offset and then the offset of the amplifier.
Since each amplifier is continuously being nUlled, offset
voltage drift with time, temperature, and power supply
variations is greatly reduced.
All nulling circuitry is intemal and the nulling operation is
transparent to the user. Offset nulling voltages are stored on
two internal capacitors. An internal oscillator and control
logic, shared by the TC913's two amplifiers, control the
nulling process.
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding the
supplies by 0.3V shOUld not be applied to the device pins.
Larger voltages can turn the p-n-p-n device on, causing
excessive device power supply current and power dissipation. The TC913's power supplies should be established at
the same time or before input signals are applied. If this is not
possible, input current should be limited to 0.1 mA to avoid
triggering the p-n-p-n structure.
Static Protection
Input pins are protected against electrostatic fields.
Static handling procedures should be used with all CMOS
devices. Many companies provide services, educational
material, and supplies to aid electronic equipment manufac- . .
turers to establish "static safe" CMOS component handling
:
areas. A partial company list is:
Pin Compatibility
The TC913 pinout is compatible with OP14, LM358,
MC1458, LT1013, TLC322, and similar dual op-amps. In
many circuits operating from single or ±5V supplies, the
TC913 is a drop-in replacement offering DC performance
rivaling that of the best single op-amps.
The TC913's amplifiers include a low-impedance class
AS output buffer. Some previous CMOS chopper amplifiers
used a high-impedance output stage which made open-loop
gain dependent on load resistance. The TC913's open-loop
gain is not dependent on load resistance.
• 3M
Static Control Systems Div
223-23W EM Center
St. Paul, MN 55101
(800) 792-1072
• Semtronics
P.O. Sox 592
Martinsville, NJ 08836
(201) 561-9520
Overload Recovery
The TC913 recovers quickly from output saturation.
Typical recovery time from positive output saturation is
20 ms. Negative output saturation recovery time is typically
5ms.
8-25
NOTES
8-26
~~TELEDYNE
COMPONENTS
TC914
QUAD AUTO-ZEROED OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
First Monolithic Quad Auto-Zeroed Operational
Amplifier
Chopper Amplifier Performance Without External
Capacitors
- vos ........................................................ 15 ~V Max
- Vas Drift .•.............•.....•...........•....• 0.15 ~V/oC Max
- Saves Cost/Assembly of Eight "Chopper"
Capacitors
High DC Gain ................................................. 110 dB
Low Supply Current ...................................... 1.5 mA
•
•
•
•
•
Wide Common-Mode
Voltage Range ................................... Vs- to Vs+ -2V
High Common-Mode Rejection .••.....••....••••.• 110 dB
Dual or Single Supply Operation ••.••.•••.• ±3V to ±8V
+4.5V to +16V
Excellent AC Operating Characteristics
- Slew Rate ••.....•..•.••..•••.•..•••..•.•••••••.••••.•••••• 2.5 V/~
- Unity-Gain Bandwidth ............................. 1.5 MHz
Pin Compatible With LM358. TLC274. LM324.
OP11. ICL7641/42
FUNCTIONAL DIAGRAM
11
4
~'"
~-------------------------,
Vas CORRECTION AMPURER
A
A
B
B
INTERNAL
OSCILLATOR
(fOSC =200 Hz)
LOW IMPEDANCE
OUTPUT BUFFER
-INPUT o--t--!--....- - - t - -....
+INPUT
TC914
>----._--;.------+--o OUTPUT
0-+--1----....--1
1 OF 4 AMPLIFIERS SHOWN
~----------------------------------~
'NOTE: Internal capacitors. No external capacitors required.
1103-1
8-27
QUAD AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC914
GENERAL DESCRIPTION
The TC914 is the world's first complete monolithic
quad auto-zeroed operational amplifier. The TC914 sets a
new standard for low-power, precision quad operational
amplifiers. Chopper-stabilized (or auto-zeroed) amplifiers
offer low offset voltage errors by periodically sampling
offset error, and storing correction voltages on capacitors.
Previous single amplifier designs required two user-supplied, external 0.1 ~F error storage correction capacitorsmuch too large for on-chip integration. The unique TC914
architecture requires smaller capacitors, making on-chip
integration possible. Microvolt offset levels are achieved
and external capacitors are not required.
The TC914 system benefits are apparent when contrasted with a TC7650 chopper amplifier circuit implementation. A single TC914 replaces four 7650's and eight
capacitors. Eleven components and assembly steps are
eliminated.
The TC914 pinout matches many popular quad operational amplifiers: OP11, TLC274, LTC1014, LM348, and
ICL7642/41 are typical examples. In many applications,
operating from dual5V or single power supplies, the TC914
offers superior electrical performance, and can be a functional drop-in replacement; printed circuit board rework is
not necessary. The TC914's low offset voltage error eliminates offset voltage trim potentiometers often needed with
bipolar and low-accuracy CMOS operational amplifiers.
The TC914 takes full advantage of Teledyne's proprietary CMOS technology. Its 1.5 mA supply current (250 ~
per amplifier) makes the TC914 the lowest power, precision quad operational amplifier available. The 250 ~ amplifier supply current does not compromise AC performance.
Unity-gain bandwidth is 1.5 MHz and slew rate is 2.5 V/~s.
For single- and dual-operational amplifiers, see the
TC911 and TC913 data sheets.
ORDERING INFORMATION
Part No.
TC914ACPD
TC914BCPD
TC914AIJD
TC914BIJD
TC914ACOE
Package
Temperature
Range
14-Pin
Plastic DIP
14-Pin
Plastic DIP
14-Pin
CerDIP
14-Pin
CerDIP
16-Pin SO
O°C to +70°C
15~V
O°Clo +70°C
30~V
-25°C to +85°C
15~V
-25°C to +85°C
30~V
O°C to +70°C
15~V
PIN CONFIGURATIONS
14-Pin DIP
16-Pin SO
NC
8-28
Maximum
Offset
Voltage
=NO INTERNAL CONNECTION
QUAD AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC914
ABSOLUTE MAXIMUM RATINGS
Package Power Dissipation (TA = +25°C)
CerDIP ........................................................... 500 mW
Plastic DIP and SO ........................................ 375 mW
Total Supply Voltage (V+s to V-s) ............................ +18V
Input Voltage ............................ (V+s+0.3V) to (V-s -0.3V)
Current into Any Pin ................................................ lOrnA
While Operating ............................................... 100 jJ.A
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device ............................................... -25°C to +85°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those lislad under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: Vs = ±5V, T A = +25°C, unless otherwise indicated.
Symbol Parameter
Test Conditions
Min
TC913A
Typ
Max
TC9138
Typ
-
5
15
Max
Unit
-
15
30
-
0.05
0.05
0.15
0.15
-
-
0.25
0.25
I1V
I1V/o C
I1V/o C
-
-
90
3
4
-
-
-
120
4
6
pA
nA
nA
5
20
-
10
40
pA
-
-
0.6
11
-
-
100
110
-
I1V p.p
I1V p.p
dB
Min
Vos
Input Offset Voltage
TA=+25°C
TCVos
Average Temperature
Coefficient of Input
Offset Voltage
0°C:s;TA:S;+70°C
-25°C:s; TA:S; +85°C
18
Average Input Bias
Current
TA = +25°C
O°C:s; TA:S; +70°C
-25°C:s; TA:S; +85°C
los
Average Input
Offset Current
TA= +25°C
-
eN
Input Voltage Noise
0.1 to 1 Hz, Rs:S; loon
0.1 to 10 Hz, Rs :s; loon
-
-
0.6
11
Vs:S;VcM:S;Vs-2.2V
110
116
Vs
-
Vs-2
Vs
-
115
120
-
110
120
-
Vs-O.9
Vs+0.3
-
-
1.5
-
2.5
CMRR
Common-Mode
Rejection Ratio
CMVR
Common-Mode
Voltage Range
AOL
Open-Loop Voltage
Gain
VOUT
BW
RL= 10 kn, Vo= ±4V
Output Voltage Swing
RL= 10 kn
Closed-Loop
Bandwidth
Closed Loop Gain = +1
Vs+0.3
-
1.5
2.5
-
SR
Slew Rate
RL= 10 kn,CL=50pF
-
PSRR
Power Supply
Rejection Ratio
±3.3V :s; Vs :s; ±5.5V
110
-
-
100
Vs
Operating Supply
Voltage Range
Split Supply
Single Supply
±3
4.5
-
-
±8
16
±3
4.5
Quiescent Supply
Current
Vs=±5V
-
-
1.6
-
Is
8-29
-
-
VS-2
Vs-0.9
V
dB
V
-
MHz
-
-
V/I1 S
dB
±8
16
V
V
2.2
rnA
QUAD AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC914
TYPICAL CHARACTERISTICS CURVES
Supply Current vs :t Supply Voltage
Input Offset Voltage vs Common-Mode Voltage
35
1800
TA=+25'C
1600
~ 1400
iii 1200
I-
a
a:
1000
I
>
800
...J
Il.
Il.
~
600
/
400
/
----
....... v
.a:
w
~
o
I-
~
I
o
I-
~
10
\. .....
i!: 5
34567
:t SUPPLY VOLTAGE (V)
2
o
~
8
Gain and Phase vs Frequency
. ..
~
30
~
20 c- GAIN
"-
10
9
0
o
15
II.
J
50
40
25
g 20
V
200
TA=+25'C
VS =:t5V
>30
·1111
PHASE
....
:---
TA=+25:
VS=:t5V
RL = 10kQ
I
....
filrn -11)
TA=~25"C
180
5.0
135
€
90
~ 4.2
0
r....
i:!!.
~
g 3.4
~
::c
I-
w
!WiN1J
VS=:t5V
.......
~
I I II
~SWING
:J
!5"- 2.6
-45 "-
90-20
~ -4 -3 ~ ~
0 1 234
INPUT COMMON·MODE VOLTAGE (V)
Output Voltage Swing vs Load Resistance
225
45
~,
~
o
-90
+I
1.8
-135
-30
-40
10k
-180
10M
lOOk
1M
FREQUENCY (Hz)
1.0
100
1k
10k
100k
LOAD RESISTANCE (Q)
1M
Positive Overload Recovery Time
Negative Overload Recovery Time
TA=+25'C
10 kQ
C- RL =
L
OUTPUT =
2 VIDIV
L~
INPUT
J
OV-
1'1,
J
OUTPUT
=2VtrAV
INPUT
GAIN =-20
OV _
INPUT
GAIN =-20
HORIZONTAL SCALE = 20 mslDlV
HORIZONTAL SCALE = 20 ms/DIV
8-30
QUAD AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC914
Theory of Operation
Static Protection
Each of the TC914's four op-amps actually consists of
two amplifiers. A main amplifier is always connected from
the input to the output. A separate nulling amplifier alternately nulls its own offset and then the offset of the main
amplifier. Since each amplifier is continuously being nulled,
offset voltage drift with time, temperature and power supply
variations is greatly reduced.
All nulling circuitry is internal and the nulling operation is
transparent to the user. Offset nulling voltages are stored on
two internal capacitors. An internal oscillator and control
logic, shared by the TC914's two amplifiers, control the
nulling process.
Input pins are protected against electrostatic fields.
Static handling procedures should be used with all CMOS
devices. Many companies provide services, educational
material, and supplies to aid electronic equipment manufacturers to establish "static safe" CMOS component handling
areas. A partial company list is:
• 3M
Static Control Systems Div
223-23W EM Center
st. Paul, MN 55101
(800) 792-1072
• Semtronics
P.O. Box 592
Martinsville, NJ 08836
(201) 561-9520
Pin Compatibility
The TC914 pinout is compatible with OP11, LM324,
LM348, LT1014, TLC274, and similar quad op-amps. In
many circuits operating from single or ±5V supplies, the
TC914 is a drop-in replacement, offering DC performance
rivaling that of the best single op-amps.
The TC914's amplifiers include a low-impedance, class
AB output buffer. Some previous CMOS chopper amplifiers
used a high-impedance output stage which made open-loop
gain dependent on load resistance. The TC914's open-loop
gain is not dependent on load resistance.
Overload Recovery
The TC914 recovers quickly from output saturation.
Typical recovery time from positive output saturation is
20 ms. Negative output saturation recovery time is typically
5ms.
Avoiding Latch-Up
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding the
supplies by 0.3V should not be applied to the device pins.
Larger voltages can turn the p-n-p-n device on, causing
excessive device power supply current and power dissipation. The TC914's power supplies should be established at
the same time or before input signals are applied. Ifthis is not
possible, input current should be limited to 0.1 mA to avoid
triggering the p-n-p-n structure.
8·31
NOTES
8-32
..,"TELEDYNE
COMPONENTS
TC915
HIGH-VOLTAGE, AUTO-ZEROED OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC915 is a high-voltage, high-performance CMOS,
chopper-stabilized operational amplifier. It can operate from
the same ±15V power supplies commonly used to power
bipolar op amps, such as the OP07 and 741. Previous
CMOS chopper-stabilized amplifiers, such as the TC7650,
were limited to operating from ±7.5V power supplies.
The TC915's maximum Vos specification is only 10 I!V,
almost a factor of 7 improvement over the industry-standard
OP07E. The maximum Vosdriftof 0.1I!V/oC is 12 times less
than the OP07E. Input bias and offset currents (both only
100 pA maximum) are factors of 20 improvements.
In addition to low initial offset errors, the nulling circuitry
ensures excellent performance over time and temperature.
Long-term drift, which results in periodic recalibration, is
effectively eliminated. The nulling circuitry continues to operate over the full temperature range, whereas laser and
"zener zap" trimming are only done at a single temperature.
The result is a significant decrease in temperature-induced
errors.
•
•
•
•
•
High-Voltage Operation ••..•...••.......••..•..•.•••...•... ±15V
Low Offset Voltage .................................. 10 I!V Max
Low Offset Voltage Drift •..•.•..••••••.•..••...•••.• 0.2I!V/"C
Low Input Bias Current .•....................... 200 pA Max
High Open-Loop Voltage Gain .•....•.....•........ 140 dB
Wide Common-Mode
Voltage Range .....................................-15V to +13V
Low Input Voltage Noise
(0.1 Hz to 1 Hz) .....................•...................... 0.2I!Vp.p
Low Supply Current ......................................... 1 rnA
Single Supply Operation .......................... 7V to 32V
Pin Compatible With ICL7650
Output Clamp Speeds Overload Recovery Time
FUNCTIONAL DIAGRAM
"'"
OUTPUT
CLAMP
CIRCUIT
TC915
+
>-_...........- - - 0 OUTPUT
INPUT
Ce
Ce
A
FTOVSORCR
e'
e
CA
OSC
e
CA
A
A'
e'
------------,
A'
I
INT/EXT
:
EXTClKIN :
' - - -..... INT ClK OUT:
CA AND Ce EXTERNAL CAPACITORS
,
14-PIN DIP ONLY
:
~-----------------~
CA= Ce=O.1I1 F
8-33
-=~
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
The TC915 operates from dual- or single-power supplies. Supply current is typically 1 rnA with ±15V supplies.
Single supply operation extends from +7V to +32V, and the
input common-mode range extends to Vs-. For battery operation, see the low-power TC900 data sheet.
The TC915's open-loop gain is 120 dB minimum. Unlike
the TC7650, the TC915's gain is independent of load resistance. The low-impedance output will drive a 10 kn load to
±14V. An output clamp circuit is provided to minimize overload recovery time.
The TC915 uses two amplifiers to correct offset voHage
errors. A main amplifier is always in the signal path, which
prevents switching spikes at the output. A separate nulling
amplifier aHernately corrects its own Vas error and then the
main amplifier's Vas error. Only two external capacitors are
required to store the nulling error voHages. All active nulling
circuitry, including switches and oscillators, are included onchip.
TC915 does not require complicated processing and
testing procedures associated with laser or "zener zap" Vas
trimming schemes. Simplified fabrication and high yields
combine to make the TC915 one of the lowest-priced
precision op amps available. It is available in a-pin and 14pin plastic or ceramic dual-in-line packages. Dice are available for hybrid applications.
ORDERING INFORMATION
Part No.
Package
TC91SCPA
8-Pin
Plastic DIP
8-Pin CerDIP
8-Pin CerDIP
14-Pin
Plastic DIP
14-Pin CerDIP
14-Pin CerDIP
TC91SIJA
TC91SMJA
TC91SCPD
TC91SIJD
TC91SMJD
Temperature
Range
Max
Vos
O·Cto +70·C
10ILV
-2S·C to +8S·C
-SS·C to + 12S·C
O·Cto +70·C
10ILV
10ILV
10ILV
-2S·C to +8S·C
-5S·C to + 12S·C
10ILV
10ILV
PIN CONFIGURATION
13 EXT CLOCK
INPUT
NC
(GUARD)
12
~JT~t~CK
NC
(GUARD)
9
OUTPUT CLAMP
Vs 7
NC
=NO INTERNAL CONNECTION
8-34
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs+ to Vs-) ............................. +36V
Input Voltage ........................... (Vs+ +0.3V) to (Vs- -0.3V)
Storage Temperature Range .................. ~5°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Current Into Any Pin ................................................ 10 mA
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
M Device .......................................... -55°C to +125°C
ELECTRICAL CHARACTERISTICS:
Symbol
Package Power Dissipation (TA = +25°C)
CerDIP ........................................................... 500 mW
Plastic DIP ..................................................... 375 mW
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devicas from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect devica reliability.
Vs = ±15V, TA = +25°C, unless otherwise indicated.
Parameter
Test Conditions
Vas
TCVos
Input Offset Voltage
Input Offset Voltage vs
Temperature Coefficient
O°C.,; TA"; +70°C
-25°C.,; T A .,; +85'C
Ie
Input Bias Current
Min
I
Typ
Max
Unit
30
10
0.1
0.3
100
-
-
ltV
llV/oC
ItV/'C
pA
pA
pA
pA
Input
los
eN
Input Offset Current
Input Voltage Noise
CMRR
CMVR
Common-Mode Rejection Ratio
Common-Mode Vo~age Range
Open-Loop voltage Gain
Output Voltage Swing
Closed-Loop Bandwidth
Slew Rate
Power Supply Rejection Ratio
Supply Voltage Operating Range
Quiescent Supply
AOL
Your
BW
PSRR
Vs
Is
TA = +25'C
O°C.,; TA"; +70'C
-25'C .,; TA .,; +85'C
0.1 to 1 Hz, Rs"; loon
0.1 to 10 Hz, Rs"; lOon
Vs .,; VCM .,; Vs+ 2
0.01
-
-
-
120
50
0.2
0.8
140
Vs
120
140
-
RL-l0 kn, Va - ±10V
RL= 10 kn
Closed-Loop Gain = + 1
Vs +1
RL - 10 kn, CL - 50 pF
Vs - ±5Vto±15V
(Note 1)
Vs-+15V
120
±3.5
10
100
Vs+ 2
Vs+ 1.2
0.5
0.5
140
1
±16
1.5
ItVp-p
ItVp-p
dB
V
dB
V
MHz
V/lts
dB
V
rnA
NOTE: 1. Single supply operation: Vs + = +7V to +32V.
Theory of Operation
Figure 1 shows the major elements of the TC915. There
are two amplifiers: a main (signal) amplifier and a nulling
amplifier. Both have offset-nulling capability. The main amplifier is always connected to the output. The nulling amplifier alternately samples and adjusts its own offset, then the
offset of the main amplifier.
A two-phase operation nulls the main amplifier. During
the first phase, the A pair of switches close, while the B
switches open. The nulling amp's inputs are shorted and its
output is fed back to the nulling input. Capacitor CA charges
to a voltage which will maintain the nulling amp in its nulled
state.
8-35
During the second phase, the B switches close and the
A switches open. The nulling amplifier's inputs now sample
the offset voltage of the main amplifier. The nulling amplifier
drives the main amplifier's nulling input to cancel the main
amplifier's offset Voltage. Capacitor CB stores the nulling
voltage of the main amplifier while the nulling amplifier is
being nulled on the next cycle.
The TC915 design also incorporates an additional output buffer stage. The buffer provides a low-impedance
output traditionally associated with bipolar op amps. Some
CMOS chopper-stabilized amplifiers, such as the TC7650,
have a high-output impedance which makes open-loop gain
proportional to load resistance. The TC915's open-loop gain
is not dependent on load resistance.
III
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
MAIN
AMPLIFIER
~--~--o OUTPUT
ANALOG INPUT
LOW IMPEDANCE
BUFFER
B
~""
CB
TC915
V
V
A
'--{)._--_---{)-----,
Figure 1
EXTERNAL
CAPACITORS
CA
The TC915 Contains Nulling and Main Amplifiesr (Offset Correction Voltages Are Stored on Two External Capacitors)
Pin Compatibility
Since the TC915 operates from the same ±15V power
supplies as bipolar op amps, upgrading existing circuits is
simple. The bipolar op amp's nulling and compensation
components are removed and the TC915's nulling capacitors are added.
On the 8-pin mini-DIP, the extemal null storage capacitors are connected to pins 1 and 8. On most other operational amplifiers these are left open or used for offset
potentiometer or compensation capacitor connections.
For OP05 and OP07 operational amplifiers, replacing
the offset null potentiometer between pins 1 and 8 with two
capacitors from the pins to Vs- converts the OP05/07 pin
configuration for TC915 operation. The 741 is easily upgraded by removing the nulling potentiometer between pin
4 and pins 1 and 5, then connecting capacitors from pin 4 to
pins 1 and 8. For LM1 08 devices, the compensation capacitoris replaced by the extemal nulling capacitors. The LM1 01/
748/709 pinouts are similarly modified by removing any
circuit connections to pin 5. Pin 5 on the TC915 is the output
clamp connection. Other operational amplifiers may use this
pin as an offset or compensation point.
The minor modifications needed to retrofit a TC915 to
existing sockets make prototyping and circuit verification
straightforward.
CA and CB should be 0.1 IlF film capacitors. Mylar
capacitors are suitable.
Component Selection
The two required capacitors, CA and Cs, have optimum
values, depending on the clock or chopping frequency. For
the preset internal clock, the correct value is 0.1 1lF. To
maintain the same relationship between the chopping frequency and the nulling time constant, the capacitor values
should be scaled in proportion to the external clock, if used.
High-quality, film-type capacitors (such as Mylar) are preferred. Ceramic or other lower-grade capacitors may be
suitable in some applications. For fast settling at initial
turn-on, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several
seconds may be required to settle to 1 IlV.
1--*-----0 vi;
Nulling Capacitors
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is made to
Vs- (pin 4) on the 8-pin packages and to capacitor retum
(CRET, pin 8) on the 14-pin packages. The common connection should be made through a separate PC trace or wire, to
avoid voltage drops. Internally, Vs- is connected to CRET.
14-PIN PACKAGE
8-PIN PACKAGE
(PIN 8 IS INTERNALLY CONNECTED TO PIN 7
ON THE 14-PIN PACKAGE)
Figure 2
8-36
Nulling Capacitor Connection
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
Clock Operation
Figures 4 and 5. For the clamp to be fully effective, the
impedance across the clamp output should be > 100 kn.
When the clamp is used, the clamp OFF leakage will add
to input bias current. However, clamp leakage in the OFF
state is typically only 1 pA.
The internal oscillator is set for a 1000 Hz norninal
frequency on both the 8-pin and 14-pin DI Ps. With the 14-pin
device, the 250 Hz internal frequency is available at the
INTERNAL CLOCK OUTPUT (pin 12). A 1000 Hz norninal
signal will be present at the EXTERNAL CLOCK INPUT (pin
13) with INT/EXT high or open. This is the internal clock
signal before a divide-by-four operation.
The 14-pin device can be driven by an external clock.
The INT/EXJ: input (pin 14) has an internal pull-up and may
be left open for internal clock operation. If an external clock
is used, INT/EXT must be tied to Vs- (pin 7) to disable the
internal clock. The external clock signal is applied to the
external clock input.
The external clock amplitude should swing between
Vs+ and ground for power supplies up to ±6V, and between
Vs+ and Vs+ -6V for higher supply voltages. When the
external clock is generated by +5V logic, capacitive coupling to pin 13 (through a 0.1 ~F capacitor) will provide
adequate drive.
At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-four gives the desired
50% switching duty cycle. The offset storage correction
capacitors are charged only when the external clock input is
high. A 50% to 80% external clock positive duty cycle is
desired for frequencies above 500 Hz to guarantee transients settle before the internal switches open.
The external clock input can also be used as a strobe
input. If a stobe signal is connected at the external clock
input, so that it is low during the time an overload signal is
applied, neither capacitor will be charged. This function can
be used to prevent input transients from overloading the
nulling circuitry. Leakage currents at the capacitor pins are
very low, minimizing offset voltage drift during strobe operation.
Input Bias Current
The TC915 inputs are never disconnected from the
main internal amplifier. The null amplifier samples the input
offset voltage and corrects DC errors and drift by storing
compensating voltages on external capacitors. However,
the sampling causes charge transfer at the inputs.
The impulse current is not usually a problem, because
the amount of charge transferred is very small. Care should
be exercised, however, when replacing high-input bias
current bipolar op amps. Conventional design practice is to
cancel bias current by matching the input impedances
(Figure 6a). The TC915 has an input bias current of only
i
NTERNAL POSITIVE
CLAMP BIAS
~
VT =
-O.7V
viS-
viS
11'- - - -'}","- - -{)
P-CHANNEl
..--
OUTPUT
~ CLAMP PIN
~INTERNAL NEGATIVE
N-CHANNEl
CLAMP BIAS
= VS + VT= VS + O.7V
' - - - - - - - - - 0 6tWUT PIN
Figure 3
Internal Clamp Circuit
Output Clamp
0.1!1F O.1IJF
Chopper-stabilized systems can show long overload
recovery times. If the output is driven to either supply rail,
output saturation occurs; the inputs are no longer held at a
"virtual ground." The Vas null circuit treats the differential
signal as an offset and tries to correct it by charging the
external capacitors. The nulling circuit also saturates. Once
the input signal returns to normal, the response time is
lengthened by the long recovery time of the nulling amplifier
and external capacitors.
Through the external-clamp connection, the TC915
eliminates the overload recovery problem by reducing the
feedback network gain before the output voltage reaches
either supply rail.
The output clamp circuit is shown in Figure 3, with typical
inverting and non inverting circuit connections shown in
INPUT--i_----I
>-.......--I~ OUTPUT
CONNECT CAPACITORS TO
Vs WITH 8-PIN PACKAGE
Figure 4
8-37
Noninverting Amplifier With Optional Clamp
..
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition,
voltages greater than 0.3V beyond the supply rails should
not be applied to any pin. In general, the amplifier supplies
must be established at the same time, or before, any input
signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 0.1 rnA to avoid latchup.
>--+--. OUTPUT
Static Protection
All device pins are static-protected. However, strong
static fields and discharges should be avoided as they can
degrade diode junction characteristics and increase inputleakage currents.
Many companies are actively involved in providing
services, educational materials, and supplies to aid electronic manufacturers in establishing "static safe" work areas
where CMOS components are handled. Two such companies are:
O.1I1F O.1I1F
CONNECT CAPACITORS TO
vi WITH a-PIN PACKAGE
Figure 5
Inverting Amplifier With Optional Clamp
100 pA maximum, so the additional resistor is not necessary. In fact, including the resistor will make the charge
injection current, passing through the impedance balancing
resistor, appear as a noise source. When replacing an
existing op amp with the TC915, either omit the resistor or
bypass it to ground with a ·capacitor (Figure 6b).
.3M
Static Control Systems Division
223-25W EM Center
St. Paul, MN 55101
(800) 792-1072
Latch-Up Avoidance
• Semtronics
P.O. Box 592
Martinsville, NJ 08836
(210) 561-9520
Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCR. Under certain circumstances, this
+15V
INPUT (}..--'\JV\,.......-=-4
6
RS·RF~
Rs+RF
~v",v-----o
BIAS CURRENT
CANCELLATION
RESISTOR
!
-15V
!
O.1I1F
FREQUENCY
COMPENSATION
-15V
(a) High Input Bias Current Op Amp
Figure 6
OFFSET
NULUNG
(b) Low Input Bias Current TC915
Input Bias Current Cancellation
8-38
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
TYPICAL CHARACTERISTICS CURVES
Supply Current
vs :I: Supply Voltage
Input Offset Voltage
vs Common-Mode Voltage
1400
35
TA =+25'C
TA= +25'C
I- Vs = :l:15V
a>30
w
1200
C(
~
1000
~
800
()
600
1- ~
II:
::l
~
-
r--
/
V
~
25
g20
I-
~
15
II.
0..
0..
o 10
400
i}l
50..
200
3!;
o
5
o
2
4
6 8 10 12 14 16 18 20
:I: SUPPLY VOLTAGE (V)
f0~~
225
18
180
~15
CLOSE[)'LOOP GAIN = 100
C(
"
"~
12
90
PHASE
w
"~
10
45
9
'"
g
0
0
i~
"
Ul
..J
::t
~
I::l
o
-45
lk
TA = +25'C
~ 12
8
w
1M
Input Offset Voltage
vs Clock Frequency
,.
4
V
,.
. /I--""
./
>
a
~ 15
~
g
I-
0
~ -4
"- r-.......
~ -8
1-12
o
8 -16
lk
10k
lOOk
LOAD RESISTANCE (n)
20
~ 16
~
g
POSITIVE SWING
3
100
1M
10k
lOOk
FREQUENCY (Hz)
~
NE~~~W~ sWI~I~1
6
Input Common-Mode Voltage
Range vs :I: Supply Voltage
:iII:
""-
o
-90
-20
100
-
w
0..
-10
V~I~ ~I~I~V
z
135
\
in 20
~
z
Gll~1
r-..
r-
Output Voltage Swing
vs Load Resistance
50
30
-
-15 -12 -9 -6 -3 0 +3 +6 +9 +12 +15
INPUT COMMON-MODE VOLTAGE (V)
Gain and Phase
vs Frequency
40
r-
o
2
~
II.
o
~
VCM=VS
.........
~
5
3!;
"""'" .........
4
6
8
10 12 14
:I: SUPPLY VOLTAGE (V)
v
10
V
/'
o
100
lk
10k
EXT CLOCK INPUT FREQUENCY (Hz)
16
6-39
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIER
TC915
TYPICAL CHARACTERISTICS CURVES (Cont.)
Input Offset Voltage
vs ::t Supply Voltage
Input Voltage Noise
7
TA= +2S"C
VS= :l:1SV
TA= +2S"C
I
BAN.fA~~~~tAoill T.~I~?I~~1
.lIIAA. At.
J
,v'Tvr l'
J
B~D\~'IIDiH =1 0.1 ~O ~ Hz
-I r T
-
-
RS = loon
VERTICAL = 1 IIVIDIV
HORIZONTAL = 1 .aclDIV
1
o
2
4
:I:
Negative Overload
Recovery Time
IN~TI
1 1
i
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
I I
I II
INPUT
VERTICAL
SC~LE 2 VIDIV
I I
Ir
OUTPUT
VERTICAL
SCALE .. S VIDI~I
-
,I
RL=10kn
TA= +2S"C r--rOV
IL
VERTICAL
SCALE = 2 VIDIV
OV
V
V
Positive Overload
Recovery Time
RL = 10kn
'- TA=+2S"C
I'
,,/
V
I I
"ov
OUTPUT
VERTICAL
SCfLE 1= S ~IDIV
I I
\
ov
GA:N=~l~
GAiN=~l00
HORIZONTAL SCALE = SO msIDlV
HORIZONTAL SCALE = 50 msIDlV
8-40
",,"TELEDYNE
COMPONENTS
TC918
LOW-COST CMOS OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Low Power Supply Current ..•••.••••••....•. 800 IJA Max
Low Input Offset Voltage .•..•.••.•.......••••••. 50 ~V Max
Low Input Offset Voltage Drift •........• 0.8IlV/"C Max
High-Impedance Differential
CMOS Inputs ••...........•••••••••..........••.••...........••. 1012g
High Open-Loop Voltage Gain ••••..••.....• 100 dB Min
Low Input Noise Voltage .••.•.......•...•.••.....•. 0.3IlVp.p
Compensated Internally for Stable Unity-Gain
Operation
High Common-Mode Rejection ......•.••.•••• 98 dB Min
Small Outline (SO) Packages Available
The TC918 is a general-purpose, low-cost CMOS
operational amplifier. By periodically sampling input offset
voltage and storing compensating voltages in external
capacitors, low offset voltage errors are possible. The
correction circuits compensate offset voltage drift with
temperature and time. Offset voltage temperature coefficient
is 0.8IlV/oC maximum; Vos is 50 IlV maximum.
The TC918 performance advantages are achieved
without the manufacturing complexity and costs incurred
with laser or "zener zap" Vos trim techniques. The TC918
offers a 0.2 Vllls slew rate and a 700 kHz unity-gain
bandwidth. Open-loop voltage gain is 100 dB.
Operating from ±5V supplies, the TC918' s power dissipation is under 10 mW. In +5V-only systems, the TC7660
DC-to-DC converter can supply the TC918's negative supply potential. The TC918 will also operate from a single
+5V supply.
For lower power dissipation and offset voltage errors,
see the TC900 and TC7650ITC7650A specifications.
FUNCTIONAL DIAGRAM
Vs Vs
.,'"
CLAMP
TC918
OUTPUT
CLAMP
CIRCUIT
+0--_-1
~------~~--------------~OUTPUT
INPUT
CA
CONNECT TO
VSORCRON
14·PIN PACKAGE
{0------1
0------11----------'
'--IN-TE-R-N-A-l-' ... -INUEXT - - - - :
OSCilLATOR
AND CONTROL
..._ _C_IR_C_U_IT_......
CB
EXT ClK IN
INT ClK OUT
1
1
:
1
1
14-PIN DIP ONLY 11
11__________
1105-1
8-41
LOW-COST CMOS
OPERATIONAL AMPLIFIER
TC918
ORDERING INFORMATION
Part No.
Package
TC918CPA
TC918COA
TC9181JA
8-Pin Plastic DIP
8-Pin SO
8-Pin CerDIP
TC918CPD
14-Pin Plastic DIP
TC9181JD
14-Pin CerDIP
PIN CONFIGURATIONS
Temperature
Range
Max
O°Cto +70°C
SOILV
SO ILV
0"Cto+70°C
-2SoC to +8SoC
O°Cto +70°C
-2SoC to +8SoC
14-Pin DIP
Vos
8-Pin DIP
SOILV
SOILV
SOILV
OUTPUT
CLAMP
NC
=NO INTERNAL CONNECTION
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs+ to Vs-) ............................. +lBV
Input Voltage .......................... (Vs+ +0.3V) to (Vs- -0.3V)
Voltage on Oscillator Control Pins ................... Vs+ to VsOutput Short Circuit Duration .............................. Indefinite
Current Into Any Pin ................................................ lOrnA
While Operating (Note 4) ................................. 100 J.IA
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
Package Power Dissipation (TA = +25°C)
Plastic and CerDlP ........................................ 500 mW
Static-sensitive device. Unused devices must be stored in conductive
material to protect them from possible static damage. Stresses above
those listed under' Absolute Maximum Ratings' may cause permanent
damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: Vs+ = +5V, Vs- =-5V, CA = Cs = 0.1IlF, TA = +25°C.
Symbol
Parameter
Test Conditions
Input Offset Voltage
TA= +2SOC
Input Offset Voltage vs
Average Temperature
Coefficient
Operating Temperature
Range (Note 1)
IBIAS
Average Input Bias Current
(Note S)
Min
I
Typ
Max
Unit
Input
Vos
TCVos
-
-
SO
0.4
0.8
ILV
lLV/oC
TA=+2SoC
-
-
100
pA
-
O.S
-
ILV p.p
ILV p.p
Q
los
Input Offset Current
TA = +2SOC
eN
Input Noise Voltage
Rs = 100Q, 0 to 10Hz
Rs = 100Q, 0 to 1 Hz
RIN
CMVR
Input Resistance
Common-Mode Voltage Range
CMRR
Common-Mode Rejection Ratio
CMVR = -SV to +2V
8-42
4
0.3
-
1012
Vs
98
11S
s
V -2
-
pA
V
dB
LOW-COST CMOS
OPERATIONAL AMPLIFIER
TC918
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Test Conditions
Min
Typ
Large-Signal Vo~age Gain
Output Vo~age Swing (Note 3)
100
-4.7
-4.9
20
130
Clamp ON Current (Note 2)
Clamp OFF Current (Note 2)
RL= 10 k.Q
RL = 25 k.Q
RL = 100 k.Q
RL= 100 k.Q
-4V < Your < +4V
Unity-Gain Bandwidth
Slew Rate
Unity Gain (+1)
CL = 50 pF, RL = 10
Max
Units
Output
Av
Your
Dynamic
BW
SR
Supply
Vs+to Vs-
-
-
+3.5
+3.9
200
90
1
-
-
dB
V
V
I1A
pA
MHz
V/I1S
k.Q
-
Operating Supply Range
4.5
No Load
Supply Current
Is
105
PSRR
Power Supply Rejection Ratio
Vs = ±3V to ±8V
NOTES: 1. Operating temperature range is -25°C to +85°C for 'I' devices and O°C to +70°C for 'C' devices.
2. See "Output Clamp" discussion.
3. Output clamp not connected.
4. Limiting input current to 100 ItA is recommended to avoid latch-up problems.
5. Average current caused by switch charge transfer at input.
-
16
800
300
-
-
V
I1A
dB
Op-Amp Performance Comparison
The TC918 is a low-cost, low-power, precision amplifier. A comparison between the TC918 and other amplifiers
is shown in Figure 1.
Supply Current YS Offset Voltage
Maximum Vos
YS
Vos Drift
10
!1 1 0 m v _.
~
OP02D
OP07C
CA3493 B
~~
crA3~~r
<
t;.
~+-H+tttl+-H-H+++.OP02
lUff
C
I II
~
w
g
OPOS G!lU30S
OP12 GI-ttftOP12 F
!;IIII!III~O~P~12~G/~11
OPOSG
1 mV
-r-
~~
.o~rA
!IOO"VI===;IFIT~C9~1~81~~IC;A311493iiBI!IIIIIII
i
TlC271 B
'ICl76; 1 'Be'
IQ = 100 "A)
0.1
10"y
O~D
II
OP02C
f-- r- Te918
._
+
I IIII 10mV
10llV~~~~~_~~~a-~~~uu
0.1
100 "V
1 mV
MAXIMUM OFFSET VOLTAGE
1
10
MAXIMUM OFFSET VOLTAGE (IIVrC)
Figure 1. TC91S Comparison to Other Amplifiers
8-43
100
LOW-COST CMOS
OPERATIONAL AMPLIFIER
TC918
Nulling Capacitors
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is made
to Vs- (pin 4 on 8-pin devices) and to capacitor return CRET
(pin 8 on 14-pin devices). The common connection should
be made through a separate PC trace or wire to avoid
voltage drops.
Internally, Vs- is connected to CRET.
CA and CB should be 0.1 IlF film capacitors. Mylar
capacitors are suitable.
V+
S
The external clock amplitude should swing between
Vs+ and ground for power supplies up to ±6V and between
Vs+ and Vs+ -6V for higher supply voltages.
At low frequencies, the external clock duty cycle is not
critical, since an internal divide-by-two gives the desired
50% switching duty cycle. The offset storage correction
capacitors are charged only when the external clock input
is high. A 50% to 80% external clock-positive duty cycle is
desired for frequencies above 500 Hz to guarantee transients settle before the internal switches open.
The external clock input can also be used as a strobe
input. If a strobe signal is connected at the external clock
input, so that it is low during the time an overload signal is
applied, neither capacitor will be charged. The leakage
currents at the capacitor pins are very low.
Output Clamp
HI~--CVS
14-PIN PACKAGE
8-PIN PACKAGE
(PIN B IS INTERNAllY
CONNECTED TO PIN 7
ON 14-PIN PACKAGE)
Figure 2. Nulling Capacitor Connection
If the output is driven to either supply rail, output saturation occurs. The inputs are no longer held at a "virtual
ground." The Vos null circuit treats the differential signal as
an offset and tries to correct it by charging the external
capacitors. The nulling circuit also saturates. Once the input
signal returns to normal, the response time is lengthened by
the long recovery time of the internal correction circuit and
external capacitors.
Through an external clamp connection, the TC918 eliminates the overload recovery problem by reducing the feedback network gain before the output voltage reaches either
supply rail.
Normally, the clamp pin is not connected.
i
Clock Operation
The internal oscillator is set for a 150 Hz nominal
frequency. With the 14-pin device, the 150 Hz intemal
frequency is available at the internal clock output (pin 12).
A 300 Hz nominal signal will be present at the external
clock input (pin 13), with INT/EXT high or open. This is the
internal clock signal before a divide-by-two operation.
The :!±:pin device can be driven by an external clock.
The INT/EXT input (pin 14) has an internal pull-up and may
be left open for internal clock operation. If an external clock
is used, INT/EXT must be tied to Vs- (pin 7) to disable the
internal clock. The external clock signal is applied to the
external clock input (pin 13).
NTERNAL POSITIVE
CLAMP BIAS
'--0
..-----, P-CHANNEl
rl
~
,--_~J
~
OUTPUT
CLAMP PIN
N-CHANNEl
INTERNAL NEGATIVE
CLAMP BIAS
'---------o~
TC918
OUTPUT PIN
Figure 3. Internal Clamp Circuit
8-44
LOW-COST CMOS
OPERATIONAL AMPLIFIER
TC918
Latch-Up Avoidance
O.lIlF
Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCR. Under certain circumstances, this
junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition,
voltages greater than 0.3V beyond the supply rails should
not be applied to any pin. In general, the amplifier supplies
must be established either at the same time or before any
input signals are applied. If this is not possible, the drive
circuits must limit input current flow to under 0.1 mA to
avoid latch-up.
O.lIlF
~""
TC918
INPUT-t-----!
>---"-I~
Ra +(Rl 'R2 )
;. 100 k!:!
FOR FULL CLAMP EFFECT
OUTPUT
Rl
-=
CONNECT CAPACITORS TO
Vs WITH 8-PIN DEVICE
TYPICAL CHARACTERISTIC CURVES
Gain and Phase vs Frequency
Figure 4. Noninverting Amplifier With Optional Clamp
30
20
R2
270
..........
10
~""
0
TC918
INPUT
,.........
"
225
I
180
GAIN
:'\
.......
iii"
:!!. -10
z
Ci: -20
OUTPUT
vs= ",5V
TA= +25'C
'\
PHASE
(!j
-30
1"\
o
\
-40
-45
-So
O.lIlF O.lIlF
-90
-00
10k
CONNECT CAPACITORS TO
Vs WITH 8-PIN DEVICE
-135
10M
lOOk
1M
UNITY-GAIN BANDWIDTH (Hz)
Figure 5. Inverting Amplifier With Optional Clamp
Input CMVR vs Supply Voltage
>"
12
;;;- 10
Input Bias Current
TAI=
+2~'C
(!j
~
The TC918's inputs are never disconnected from the
main internal amplifier. The null amplifier samples the input
offset voltage and corrects DC errors and drift by storing
compensating voltages on external capacitors. The sampling, however, causes charge transfer at the inputs. The
charge transfer represents a peak impulse current of 200 nA
to 290 nA at the inputs when the intemal clock makes a
transition.
8
w 6
(!j
:;'"
g
4
~
0
o
2
:::0 -2
Z
o -4
:::0
:::0 -0
8
8-45
-8
...-........
.......... ........
-
V
........
.......... .........
.........
r---...
02345678
SUPPLY VOLTAGE (V)
III
NOTES
8-46
~,,"TELEDYNE
COMPONENTS
TC7650
CHOPPER-STABILIZED OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Low Input Offset Voltage ................................ 0.7IlV
Low Input Offset Voltage Drift ......... 0.05IlVI"C Max
Low Input Bias Current ............................ 10 pA Max
High Impedance Differential CMOS Inputs .... 10120
High Open-Loop Voltage Gain ............... 120 dB Min
Low Input Noise Voltage .......................... 2.0 11 Vp-p
High Slew Rate .............................................. 2.5 V/lls
Low-Power Operation .................................... 20 mW
Output Clamp Speeds Recovery Time
Compensated Internally for Stable Unity Gain
Operation
Direct Replacement for ICL7650
Available in 8-Pin Dip
GENERAL DESCRIPTION
The TC7650 CMOS chopper-stabilized operational
amplifier practically removes offset voltage error terms
from system error calculations. The 51lV maximum Vos
specification. for example, represents a 15 times improvement over the industry-standard OP07E. The 50 nV/oC
offset drift specification is over 25 times lower than the
OP07E. The increased performance eliminates Vas trim
procedures, periodic potentiometer adjustment and the reliability problems caused by damaged trimmers.
The TC7650 performance advantages are achieved
without the additional manufacturing complexity and cost
incurred with laser or "zener zap" Vas trim techniques. The
TC7650 is one of the lowest cost precision-operational
amplifiers available.
The TC7650 nulling scheme corrects both DC Vas
errors and Vas drift errors with temperature. A nulling
amplifieraltemately corrects its own Vas errors and the main . .
amplifier Vos error. Offset nulling voltages are stored on two
:
user-supplied external capacitors. The capacitors connect
to the intemal amplifier Vas null points. The main amplifier
input signal is never switched. Switching spikes are not
present at the TC7650 output. The null scheme keeps Vas
errors low throughout the operating temperature range.
Laser and "zener zap" trimming can correct for Vas at only
one temperature.
FUNCTIONAL DIAGRAM
-14::PIN rnpONlY"
OUTPUT 0------1
CLAMP
OSCillATOR
I
INTIEXT
EXT ClK IN
ClKOUT
I
1____ ---_1
>-----+----'~--"------o OUTPUT
INPUTS
"'"
TC7650
-FOR B-PIN DIP, CONNECT TO
B
A
vs4349 ILL F01
1083-1(434.)
8-47
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
ABSOLUTE MAXIMUM RATINGS
The nulling circuit oscillator and control circuits are
integrated on-chip. Only two external Vas error storage
capacitors are required. The TC7650 operates as a conventional operational amplifier with improved input specifications. The low Vas and Vas drift errors make the TC7650
ideal for thermocouple, thermistor, and strain-gauge applications. Low DC errors and high open-loop gain make the
TC7650 an excellent preamplifier for precision analog-todigital converters, such as the TC7135 and TC800.
The 14-pin dual-in-line package (DIP) has an external
oscillator input to drive the nulling circuitry for optimum noise
performance. Both the 8- and 14-pin DIPs have an output
voltage clamp circuit to minimize overload recovery time.
Total Supply Voltage (Vs+ to Vs-) ............................... 18V
Input Voltage ............................. (Vs++0.3V) to (Vs--0.3V)
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................... 300°C
Voltage on Oscillator Control Pins .................... Vs+ to VsOutput Short Circuit Duration .............................. Indefinite
Current Into Any Pin ................................................ 10 mA
While Operating (Note 4) ................................. 100 !!A
Operating Temperature Range
I Device .............................................. -25°C to +85°C
C Device ................................................ O°C to +70°C
Package Power Dissipation (TA = 25°C)
CerDIP ........................................................... 500 mW
Plastic DIP ..................................................... 375 mW
ORDERING INFORMATION
Part No.
Package
TC7650CPA
TC7650lJA
TC7650CPD
TC7650lJD
8-Pin Plastic DIP
8-Pin CerDIP
14-Pin Plastic DIP
14-Pin CerDIP
Temperature
Range
Max
Vos
O°C to +70°C
25°C to +85°C
O°Cto +70°C
25°C to +85°C
5~V
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
5~V
5~V
5~V
PIN CONFIGURATIONS
8-Pin DIP
(+) INPUT
Viii
CLAMP
14-Pin DIP
INT/EXT
CA
NC
(GUARD)
EXTCLK
INPUT
INTCLK
OUTPUT
(-) INPUT
Vs
(+) INPUT
OUTPUT
NC
(GUARD)
OUTPUT
CLAMP
Viii
NC
=NO INTERNAL CONNECTION
4349 ILL F02
8-48
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
ELECTRICAL CHARACTERISTICS: vs+ = +5V, vs- = -5V, CA = CB = 0.1 I1F, TA = 25°C
Symbol
Parameter
Test Conditions
Input Offset Voltage
TA= +25°C
Over Operating Temp Range
(Note 1)
Min
Typ
Max
-
±0.7
± 1.0
±5
-
0.Q1
0.05
-
100
-
Units
Input
Vos
AVos/AT
Input Offset Voltage
Average Temperature
Coefficient
Operating Temperature Range
(Note 1)
Offset Voltage vs. Time
IBIAS
Input Bias Current
TA=+25°C
O°C ~ TA ~ +70°C
-25°C ~ TA ~ +85°C
los
Input Offset Current
TA = +25°C
eNP-p
Input Noise Vo~age
Rs = 1000, 0 to 10Hz
IN
Input Noise Current
f= 10Hz
RIN
CMVR
Input Resistance
Common-Mode
Vo~age Range
-
-
-
--
1.5
35
100
10
150
400
-
0.5
-
-
2
0.01
-
-
10'2
IlV
llV/oC
nVI
month
pA
pA
pA
pA
IlVp-p
pAl-.JHz
0
-5
-5.2
to +2
+1.6
V
Common-Mode
Rejection Ratio
CMVR = -5Vto +1.5V
120
130
-
dB
A
Large Signal Vonage
Gain
RL= 10 k.Q
120
130
-
dB
VOUT
Output Voltage Swing
(Note 3)
RL= 10 k.Q
RL = 100 k.Q
±4.7
-
±4.85
±4.95
-
V
V
Clamp ON Current
(Note 2)
RL= 100 k.Q
25
70
200
IlA
Clamp OFF Current
(Note 2)
-4V < VOUT < +4V
-
1
-
pA
-
2.0
-
V/1lS
CMRR
Output
Dynamic
Bw
Unity-Gain Bandwidth
Unity Gain (+1)
SR
Slew Rate
CL= 50 pF, RL= 10 k.Q
tR
fCH
-
2.5
MHz
Rise Time
-
0.2
Overshoot
-
20
-
%
120
200
375
Hz
4.5
-
Internal Chopping
Frequency
Pins 12-14 Open (DIP)
-
IlS
Supply
Vs+, Vs-
Operating Supply Range
Is
Supply Current
No Load
-
PSRR
Power Supply
Rejection Ratio
Vs = ±3V to ±8V
120
NOTES: 1.
2.
3.
4.
2
130
Operating temperature range IS -25°C to +85°C for 'I' grade and O°C to +70°C for 'C' grade.
See 'Output Clamp' discussion.
Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics.
Limiting input current to 100 I-IA is recommended to avoid latch-up problems.
8-49
16
3.5
V
mA
dB
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
Theory of Operation
Figure 1 shows the major elements of the TC7650.
There are two amplifiers (the main amplifier and the nulling
amplifier), and both .have offset-null capability. The main
amplifier is connected full-time from the input to the output.
The nulling amplifier, under the control of the chopping
frequency oscillator and clock circuit, alternately nulls itself
and the main amplifier. Two external capacitors provide the
required storage of the nulling potentials and the necessary
nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges,
and is also independent of the output level, thus giving
exceptionally high CMRR, PSRR, and AVOL.
Careful balancing ofthe input switches minimizes chopper frequency charge injection atthe input terminals, and the
feed-forward-type injection into the compensation capacitor
that can cause output spikes in this type circuit.
Thecircuit's offset voltage compensation is easily shown.
With the nulling inputs shorted, a voltage almost identical to
the nulling amplifier offset voltage is stored on CA. The
effective offset voltage at the null amplifier input is:
1
VOSE = AN + 1
(1 )
VOSN
Afterthe nulling amplifier is zeroed, the main amplifier is
zeroed; the A switches open and B switches close.
The output voltage equation is:
Substituting (1)
--7
(2) and assuming AN» 1:
Vo = AM AN [ (V+-V-) + VOSM: VOSN ]
N
(3)
As desired, the device offset voltages are reduced by
the high open-loop gain of the nulling amplifier.
Output Stage/Load Driving
The output circuit is a high-impedance stage (approximately 18 kn). With loads less than this, the chopper
amplifier behaves in some ways like a transconductance
amplifier whose open-loop gain is proportional to load resistance. For example, the open-loop gain will be 17 dB lower
with a 1 knloadthanwitha 10 knload.lftheamplifierisused
strictly for DC, the lower gain is of little consequence, since
the DC gain is typically greater than 120 dB, even with a 1 kn
load. In wideband applications, the best frequency response
will be achieved with a load resistor of 10 kn or higher. This
results in a smooth 6 dB/octave response from 0.1 Hz to 2
MHz, with phase shifts of less than 10° in the transition
region, where the main amplifier takes over from the null
amplifier. The clock frequency sets the transition region.
Intermodulatiori
Previous chopper-stabilized amplifiers have suffered
from intermodulation effects between the chopperfrequency
and input signals. These arise because the finite AC gain of
the amplifier results in a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies, and causing disturbances to the gain and
phase versus frequency characteristics near the chopping
frequency. These effects are substantially reduced in the
TC7650 by feeding the nulling circuit with a dynamic current
corresponding to the compensation capacitor current in
such a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.
v+
0------+-------------1+
ANALOG INPUT
MAIN
AMPLIFIER
L>---oVOUT
B
~'"
TC7650
A
GAIN = AN, OFFSET = VOSN
4349 ILL Faa
Figure 1
TC76S0 Contains a Nulling and Main Amplifier. Offset Correction Voltages Are Stored on Two External Capacitors.
8-50
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
The external clock input can also be used as a strobe
input. If a strobe signal is connected at the external clock
input so that it is low during the time an overload signal is
applied, neither capacitor will be charged. The leakage
currents at the capacitors pins are very low. At 25°C a typical
TC7650 will drift less than 10 J.l.V/sec.
Vs Vs
Output Clamp
r.--OVs
14-PIN PACKAGE
a-PIN PACKAGE
4349 ILL F04
Figure 2
Nulling Capacitor Connection
Nulling Capacitor Connection
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is made to
Vs- (pin 4) on the 8-pin packages and to capacitor retum
(CR, pin 8) on the 14-pin packages. The common connection
should be made through either a separate PC trace or wire,
to avoid voltage drops. The capacitors outside fOil, if possible, should be connected to CR or Vs-.
Clock Operation
Chopper-stabilized systems can show long recovery
times from overloads. If the output is driven to either supply
rail, output saturation occurs. The inputs are no longer held
at a "virtual ground." The Vos null circuit treats the differential signal as an offset and tries to correct it by charging the
external capacitors. The nulling circuit also saturates. Once
the input signal retums to normal, the response time is
lengthened by the long recovery time of the nulling amplifier
and external capacitors.
Through an extemal clamp connection, the TC7650
eliminates the overload recovery problem by reducing the
feedback network gain before the output voltage reaches
either supply rail.
ir--..,
NTERNAL
POSITIVE CLAMP BIAS ~ v+ -VT~ V+ -0.7V
rl
P-CHANNEl
1_-0
tOUTPUT
~_~I
The intemal oscillator is set for a 200 Hz nominal
chopping frequency on both the 8-and 14-pin DIPs. With the
14-pin DIP TC7650, the 200 Hz intemal chopping frequency
is available at the intemal clock output (pin 12). A 400 Hz
nominal signal will be present at the external clock input pin
(pin 13) with INT/EXT high or open. This is the internal clock
signal before a divide-by-two operation.
The 14-pin DIP device can be driven by an extemal
clock. The INT/EXT input (pin 14) has an internal pull-up and
may be left open for internal clock operation. If an extemal
clock is used, INT/EXT must be tied to Vs- (pin 7) to disable
the intemal clock. The external clock signal is applied to the
external clock input (pin 13).
The external clock amplitude should swing between Vs+
and ground for power supplies up to ±6V and between V+
and V+ --6V for higher supply voltages.
At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the desired
50% switching duty cycle. The offset storage correction
capacitors are charged only when the extemal clock input is
high. A 50% to 80% external clock positive duty cycle is
desired for frequencies above 500 Hz to guarantee transients settle before the intemal switches open.
--r;
INTERNAL
NEGATIVEClAMPBIAS~ V=+VT
~ V +0.7V
1-.-------0 OUTPUT
TC7650
PIN
4349 ILL FOS
Figure 3
'CONNECT TO Vs
ON 8-PIN DIP.
Internal Clamp Circuit
0.11'F
""'"
TC7650
INPUT-----I
> ......--I~
OUTPUT
R3 +( R1'R 2 );;, 100kn
FOR FUll CLAMP EFFECT.
4349 III F06
Figure 4
8-51
CLAMP PIN
N-CHANNEl
Noninvertlng Amplifier With Optional Clamp
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
LatCh-Up Avoidance
~'"
TC7650
INPUT
>-......---I~ OUTPUT
(R 1 11 R2h 100kn
FOR FULL CLAMP
EFFECT.
• CONNECT TO
ON S-PIN DIP.
Figure 5
VA
0.1 JlF 0.1 JlF
434Q ILL F07
Inverting Amplifier With Optional Clamp
The output clamp circuit is shown in Figure 3, with typical
inverting and noninverting circuit connections shown in
Figures 4 and 5. Output voltage versus clamp circuit current
characteristics are shown in the typical operating curves.
For the clamp to be fully effective, the impedance across the
clamp output should be greater than 100 kilo
Static Protection
All device pins are static-protected. Strong static fields
and discharges should be avoided, however, as they can
degrade diode junction characteristics and increase inputleakage currents.
Many companies are actively involved in providing
services, educational material, and supplies to aid electronic manufacturers in establishing "static safe" work areas where CMOS components are handled. A partial company listing is:
• 3M
Static Control Systems Division
223-25W EM Center
St. Paul, MN 55101
(800) 792-1072
• Semtronics
P.O. Box 592
Martinsville, NJ 08836
(210) 561-9520
• American Converters
1919 South Butlerfield Road
Mundelein, IL 60060
(312) 362-9000
• ACL
1960 East Devon Avenue
Elk Grove Village, IL 60007
(312) 981-9212
Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCA. Under certain circumstances this
junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition, no
voltage greater than 0.3V beyond the supply rails should be
applied to any pin. In general, the amplifier supplies must be
established either at the same time or before any input
signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 0.1 rnA to avoid latchup.
Thermoelectric Potentials
Precision DC measurements are ultimately limited by
thermoelectric potentials developed in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all
junctions are at the same temperature, thermoelectric voltages, typically around 0.1I1V/oC, but uptotens of I1VfOC for
some materials, will be generated. In order to realize the
benefits extremely-low offset voltages provide, it is essential
to take special precautions to avoid temperature gradients.
All components should be enclosed to eliminate air movement, especially those caused by power-dissipating elements in the system. Low thermoelectric-coefficient connections should be used where possible and power supply
voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and separation
from surrounding heat-dissipating elements is advised.
Pin Compatibility
On the 8-pin mini-DI P TC7650, the external null storage
capacitors are connected to pins 1 and 8. On most other
operational amplifiers these are left open or are used for
offset potentiometer or compensation capacitor connections.
For OP05 and OP07 operational amplifiers, the replacement of the offset null potentiometer between pins 1 and 8
by two capacitors from the pins to V s- will convert the OP05/
07 pin configurations for TC7650 operation. For LM108
devices, the compensation capacitor is replaced by the
external nulling capacitors. The LM1 01/7481709 pinouts are
modified similarly by removing any circuit connections to pin
5. On the TC7650, pin 5 is the output clamp connection.
Other operational amplifiers may use this pin as an offst or
compensation point.
The minor modifications needed to retrofit a TC7650
into existing sockets operating at reduced power supply
voltages make prototyping and circuit verification straightforward.
8·52
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
Input Guarding
High impedance, low leakage CMOS inputs allow the
TC7650to make measurements of high-impedance sources.
Stray leakage paths can increase input currents and decrease input resistance unless inputs are guarded. A guard
is a conductive PC trace surrounding the input terminals.
The ring connects to a low-impedance point at the same
potential as the inputs. Stray leakages are absorbed by the
low-impedance ring. The equal potential between ring and
inputs prevents input leakage currents. Typical guard connections are shown in Figure 6.
The 14-pin DIP configuration has been specifically
designed to ease input guarding. The pins adjacent to the
inputs are unused.
In applications requiring low leakage currents, boards
should be cleaned thoroughly and blown dry after soldering.
Protective coatings will prevent future board contamination.
Inverting Amplifier
INPUT
OUTPUT
Noninverting Amplifier
Component Selection
R2
The two required capacitors, CA and CB, have optimum
values, depending on the clock or chopping frequency. For
the preset internal clock, the correct value is 0.1 j.lF. To
maintain the same relationship between the chopping frequency and the nulling time constant, the capacitor values
should be scaled in proportion to the external clock, if used.
High-quality film-type capacitors (such as Mylar) are preferred; ceramic or other lower-grade capacitors may be
suitable in some applications. For fast settling on initial turnon, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several
seconds may be required to settle to 1 j.lV.
OUTPUT
-=
INPUT
=
NOTE: R
3
R1 R2
R1 +R2
SHOULD BE LOW
IMPEDANCE FOR
OPTIMUM GUARDING.
Follower
OUTPUT
INPUT
O--f-+--1.J...
·USE RaTO COMPENSATE FOR
LARGE SOURCE RESISTANCES,
OR FOR CLAMP OPERATION.
4349 ILL F08
Figure 6
Input Guard Connection
8-53
CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7650
TYPICAL CHARACTERISTIC CURVES
Positive Clamp Current
vs Output Voltage
1 mA
I
I
0.1 mA TA = +2SoC
Vs=:tSV
".~
0.01 mA
!Z
1"A
g::
0.1"A
w
~ 0.01"A
U
/
1nA
0.1 nA
0.01 nA
1 mA
I _I_
= +25°C
0.1 mA TA
Vs =:t5V
~
!Z
V"
w
g::
J
0.1"A
~
u
II
V
/
1 nA
I
0.1 nA
V
0.01 nA
4.0 4.1 4.2 4.3 4.4 4.S 4.6 4.7 4.8 4.9
1 pA
-4.0-4.1 -4.2 -4.3 -4.4 -4.5 -4.6 -4.7 -4.8-4.9 -5.0
OUTPUT VOLTAGE (V)
s.o
OUTPUT VOLTAGE (V)
Supply Current vs
Supply Voltage
.5.
ffi
2.2
./
::I
~
....a.
1.8
a.
::I
In
1.4
1.0
"-
".
I
II
/
V
30
225
20
180
10
~
"'
o
~
I-
a:
a:
GainJPhase vs Frequency
_TAI= +4soc l
",2.6
iii
:!!. -10
Z
"' -20
Cl
135
GAIN
\
"PHASE
6
7
8
9
10 11 12 13 14 15
~~IN lill~O
10k
, I II
100k
FREQUENCY (Hz)
8-54
..
'6i
:!!.
w
0
~
::I:
a.
-135
-CLOSED-LOOP
1k
SUPPLY VOLTAGE (V)
45
-90
-40
-SO
90
-45
-30
-60
5
"-
/;'
~ 0.01"A
J
~
1"A
::I
1 pA
3.0
~
0.01 mA
/';'
::I
~
Negative Clamp Current
vs Output Voltage
1M
-180
10M
4349 ILL F10
.,"'TELEDYNE
COMPONENTS
TC7652*
LOW NOISE, CHOPPER-STABILIZED OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Low Offset Over Temperature Range ............ 10 ~V
Ultra-Low Long-Term Drift ..•............. 150 nVlMonth
Low Temperature Drift ............................. 100 nVioC
Low DC Input Bias Current ............................. 15 pA
High Gain, CMRR and PSRR •................ 110 dB Min
Low Input Noise VoHage ....... 0.2 ~Vp_Pj DC to 1 Hz
Internally-Compensated for Utility-Gain Operation
Clamp Circuit for Fast Overload Recovery
The TC7652 low noise, chopper-stabilized operational
amplifier improves noise performance and provides a wider
common-mode input voltage range. It offers low-input offset voltage and timeltemperature stability, with reduced
bandwidth and slew rate. CMOS circuitry eliminates most
chopping spikes intermodulation effects and overrange
lockup problems.
The TC7652 compares inverting and noninverting input
voltages in an amplifier nulled by alternate clock phases.
Two external capacitors store the correcting potentials on
two amplifier-nulling inputs. All control circuitry, including the
clock oscillator, is self-contained. The TC7652 is intemallycompensated for unity-gain operation. If required. the 14-pin
version can use an external clock.
The functional diagram shows the main components of
the TC7652. The main and nulling amplifiers have offsetnull capability. The main amp is continuously connected
FUNCTIONAL DIAGRAM
"'"
TC7652
---------.
14-PIN DIP ONLY 1
OUTPUT CLAMP 0>------1
(NOT ON "Z" PINOUn
INPUTS
OSCILLATOR
INTIEXT
1
EXT CLK IN
:
1
CLKOUT
1
1________ 1
~-----._-~~~~----_oOUTPUT
A
NOTE: 1. For a·pin DIP connect to \'$. or to eRET on
1085-1
a·55
'z' pinout.
·Patented
LOW NOISE, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7652
from input to output. Controlled by the chopping-frequency
oscillator and clock circuit, the nulling amp alternately nulls
itself and the main amp. The nulling connections (MOSFET
gates) are high impedance. Two external capacitors provide nulling potential storage and nulling loop-time constraints. Nulling operates over the full common-mode and
power supply ranges. lildependent of the output level, this
arrangement gives exceptionally high CMRR, PSRR, and
PIN CONFIGURATIONS
AVOL.
The input switches are closely matched to reduce
chopper frequency charge injection at the input terminals.
The main cause of output spikes in this type circuit (feedforward-type injection into the compensation capacitor) is
minimized.
Other chopper-stabilized amplifiers experience intermodulation effects between chopper frequency and input
signals. The finite AC gain of the amplifier requires a small
AC signal at the input. The zeroing circuit sees this as an
error signal, which it chops and feeds back. The circuit also
injects sum-and-difference frequencies and causes gain
and phaselfrequency characteristics disturbances near the
chopping frequency.
The TC7652 reduces these intermodulation effects by
feeding the nulling circuit a dynamic current that corresponds to the compensation capacitor current and cancels
the portion of the input signal from finite AC gain. In this way,
the major cause of TC7652 error is minimized. The gain and
phase disturbances are held to such low values thatthey can
usually be ignored.
+INPUT
OUTPUT
CLAMP
Vs
NC
CRET
=NO INTERNAL CONNECTION
(MAY BE USED AS INPUT GUARD)
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (Vs+ to Vs-) ............................. +18V
Input Voltage ............................. (Vs++0.3V) to (Vs--0.3V)
Voltage on Oscillator Control Pins .................... Vs+ to VsDuration of Output Short Circuit .......................... Indefinite
Current Into Any Pin ................................................ lOrnA
While Operating (Note 4) ................................. 100).IA
Continuous Total Power Dissipation (TA = 25°C)
CerDIP ........................................................... 500 mW
Plastic DIP ..................................................... 375 mW
Storage Temperature Range .................. -65°C to + 150°C
Operating Temperature Range
C Device ................................................ O°C to +70°C
I Device .............................................. -25°C to +85°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
ORDERING INFORMATION
Part No.
TC7652CPA
TC7652ZCPA
TC76521JA
TC7652CPD
TC7652IJD
TC7652MJA
TC7652MJD
TC7652ZMJA
TC7652ZIJA
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from stetic discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
8-56
Package
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin CerDIP
14-Pin Plastic DIP
14-Pin CerDIP
8-Pin CerDIP
14-Pin CerDIP
8-Pin CerDIP
8-Pin CerDIP
Temperature
Range
O°C to +70°C
O°Cto +70°C
-25°C to +85°C
O°C to +70°C
-25°C to +85°C
-55°C to +125°C
-55°C to + 125°C
-55°C to +125°C
-25°C to +85°C
LOW NOISE, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7652
ELECTRICAL CHARACTERISTICS: vs+ =+5V, vs- =-5V, TA =+25°C, unless otherwise indicated.
Symbol
Parameter
Test Conditions
Typ
Max
Vos
Input Offset Voltage
TA= +25°C
Over Operating Temperature Range
(Note 1)
±2
±10
±5
TCVos
Average Temperature
Coefficient of Input
Offset Voltage
Operating Temperature Range
(Note 1)
0.01
0.05
JiV/oC
Vos/AT
Offset Voltage vs Time
IBIAS
Input Bias Current
(CLKOn)
TA=+25°C
DoC < TA < +70°C
-25°C < TA < +85°C
30
100
250
100
pA
pA
pA
IBIAS
Input Bias Current
(CLKOff)
TA= +25°C
DoC < TA < +70°C
-25°C < TA < +85°C
15
35
100
30
los
Input Offset Current
TA= +25°C
25
150
RIN
Input Resistance
Large Signal Voltage
Gain
OL
Min
150
RL=10kn
VOUT=±4V
RL=10kn
RL= 100 kn
Unit
JiV
nV/mo
1000
pA
pA
pA
pA
10 '2
n
120
150
dB
±4.7
±4.85
±4.95
V
V
VOUT
Output Voltage Swing
(Note 3)
CMVR
Common-Mode
Voltage Range
MRR
Common-Mode
Rejection Ratio
CMVR = -4.3V to +3.5V
120
140
dB
PSRR
Power Supply
Rejection Ratio
±3Vto±8V
120
140
dB
eN
Input Noise Voltage
Rs = 100n, DC to 1 Hz
OCto 10 Hz
0.2
0.7
IN
GBW
Input Noise Current
f= 10 Hz
0.01
pM/Hz
0.4
SR
Slew Rate
Vs+, Vs
Operating Supply Range
Is
Supply Current
No Load
fCH
Internal Chopping
Frequency
Pins 12-14 Open (DIP)
100
275
MHz
V/Jis
%
V
mA
Hz
Clamp ON Current
(Note 2)
RL= 100 kn
25
100
JiA
Clamp OFF Current
(Note 2)
-4V .. VOUT < +10V
1
pA
-4.3
Unity-Gain Bandwidth
1.5
5
1
CL = 50 pF, RL = 10 kn
Overshoot
NOTES: 1.
2.
3.
4.
+3.5
15
5
16
1
3
V
JiVp.p
JiVp.p
-25°C to +85°C, or O°C to +70°C.
See "Output Clamp' under detailed description.
Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics.
Limiting input current to 100 J.LA is recommended to avoid latch-up problems. Typically, 1 rnA is safe; however, this is not guaranteed.
8-57
LOW NOISE, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7652
If the TC7652's output saturates, error voltages on the
external capacitors will slow overload recovery. This condition can be avoided if a strobe signal is available. The strobe
signal is applied to EXT ClK IN and the overload signal is
applied to the amplifier while the strobe is low. In this case,
neither capacitor will be charged. The low leakage of the
capacitor pins allow long measurements to be made with
negligible errors (typical capaCitor drift is 10 ~V/sec).
Capacitor Connection
Connect the null-storage capacitors to the CA and CB
pins with a common connection to the CRET pin (14-pin
TC7652 or 8-pin TC7652Z) or to Vs- (8-pin TC7652). When
connecting to Vs-, avoid injecting load current IR drops into
the capacitive circuitry by making this connection directly via
a separate wire or PC trace.
Output Clamp
APPLICATION NOTES
Component Selection
In chopper-stabilized amplifiers, the output clamp pin
reduces overload recovery time. When a connection is
madetothe inverting input pin (summing junction), a current
path is created between that point and the output pin, just
before the device output saturates. This prevents uncontroiled differential input voltages and charge buildup on
correction-storage capacitors. Output swing is reduced.
CA and CB (external capacitors) should be in the 0.1 ~F
to 1 ~F range. For minimum clock ripple nOise, use a 1 ~F
capacitor in broad bandwidth circuits. For limited bandwidth
applications where clock ripple is filtered out, use a 0.1 ~F
capacitor for slightly lower offset voltage. High-quality filmtype capacitors (polyester or polypropylene) are recommended, although a lower grade (ceramic) may work in some
applications. For quickest settling after initialturn-<>n, use low
dielectric absorption capacitors (e.g., polypropylene). With
ceramic capacitors, settling to 1 ~V takes several seconds.
Clock
The TC7652 has a 550 kHz internal oscillator, which is
divided by two before clocking the input chopper switches.
The 275 Hz chopping frequency is available at INT ClK OUT
(pin 12) on 14-pin devices. In normal operation, INT/EXT
(pin 14), which has an internal pull-up, can be left open.
An external clock can also be used. To disable the
internal clock and use an external one, the INT/EXT pin rnust
be tied to Vs-. The external clock signal is then applied to
the EXT ClK IN input (pin 13). An internal divide-by-two
provides a 50% switching duty cycle. The capacitors are
only charged when EXT ClK IN is high, so a 50% to 80%
positive duty cycle is recommended for higher clock frequencies. The external clock can swing between Vs+ and
Vs-, with the logic threshold about 2.5V below Vs+.
The output of the internal oscillator, before the divide-bytwo circuit, is available at EXT ClK IN when INT/EXT is high
or unconnected. This output can serve as the clock input for
a second TC7652 (operating in a master/slave mode), so that
both op amps will clock at the same frequency. This prevents
clock intermodulation effects when two TC7652's are used in
a differential amplifier configuration.
Static Protection Although input diodes static protect all
device pins, avoid strong static fields and discharges that
can cause degraded diode junction characteristics and
produce increased input-leakage currents.
LatCh-Up
Junction-isolated CMOS circuits have a 4-layer (p-np-n) structure similar to an SCA. Sometimes this junction
can be triggered into a low-impedance state and produce
excessive supply current. Therefore, avoid applying voltage
greater than 0.3V beyond the supply rails to any pin. Establish the amplifier supplies at the same time or before any
input signals are applied. If this is not possible, drive circuits
must limit input current flow to under 1 rnA to avoid latch-up,
even under fault conditions.
Output Stage/Load Driving
The output circuit is high impedance (about 18 kW).
With lesser loads, the chopper amplifier behaves somewhat
like a transconductance amplifier with an open-loop gain
proportional to load resistance. (For example, the open-loop
gain is 17 dB lower with a 1 kW load than with a 10 kW load.)
lithe amp is used only for DC, the DC gain is typically greater
than 120 dB (even with a 1 kW load), and this lower gain is
inconsequential. Forwideband, the bestfrequency response
occurs with a load resistor of at least 10 kW. This produces
a 6 dB/octave response from 0.1 Hz to 2 MHz, with phase
shifts of less than 2 degrees in the transition region, where
the main amplifier takes over from the null amplifier.
TEST CIRCUIT
~f'
TC7652
~-----~VOUT
V\.,..-----( VTH
200k!lt02Mn
Figure 4
-=
Figure 1
Low Offset Comparator
Noninverting Amplifier With Optional Clamp
~'"
TC7652
~'"
TC7652
INPUT
>-~--I'" OUTPUT
IN {
Figure 2
Inverting Amplifier With Optional Clamp
r-_----I
Figure 5
OUT
1437 Offset-Nulled by TC7652
-7.5V
i J - - - - < +15V
>-_....
1-+---+ +7.5V
OUT
~'"
TC7652
lM!l
Figure 3
Using 741 to Boost Output Drive Capability
Figure 6
8-60
Splitting +15V With the 7660 at >95% Efficiency
LOW NOISE, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7652
TYPICAL CHARACTERISTICS CURVES
Output Resistance
vs Output Vohage
Supply Current va :t Supply Voltage
1400
-5.0
1200
~
1000
_
000
~
~
>-
..~
Positive Clamp Current
1 mA
-'
600
V
/
V
...~
~
I
5
a:
ffi
1 lolA
~
0.11'A
~
D.01IJA
.
I
/
5o
L
200
0.1 rnA
'"
0,01 rnA
I
SINK/
g ....o
I
400
..... ......
/
1/ I
I
/
1 nA
/SOURCE
0.1 nA
iL
0.01 nA
./
I
-3.0
o
:t
4
5
•
SUPPLY VOLT AGE (V)
',./'
1 pA
1k
10k
look
OUTPUT RESISTANCE (0)
100
2
4.0 4.1
1M
V
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.'
OUTPUT VOLT AGE (V)
Noise at 0.1 Hz to 10 Hz
Negative Clamp Current
1 mA
!z
0.01 mA
~
1IJA
~
0.11JA
~
0.011JA
u
I
.........
0.1 rnA
1/
I
II"
-'-
A
Ald. A.. .M lal III
~n. .AI" .It
.,.,
w
I
rrl
/
1 nA
1:1
Ir
L
rfT 1
I
I
I
I
1 pA
4.0 4.1
11
:I
/
0.1 nA
0.01 nA
5.0
4.2 4.3 4.4 4.5 4.8 4.7 4.8 4.9 5.0
OUTPUT VOLT AGE (V)
~
Noise at 0 1 Hz to 1 Hz
51ewRate
I
I
I
1/1
I
I
[\;. -r. ~
:
r
,... 6 ~
-
:
:
:
-
Phase-Gain (Bode Plot)*
••
••
I
-1I
:!!.
-. ... "-..
"
10
10
Input Offset Voltage vs Common-Mode Voltage
>4.0
/
;; 3.5
S
3.0
./
1.5
~ 1.0
z
-
,.,-
0,5
-6
-4
---
..........-
/
-2
COMMON·MODE VOLTAGE (V)
8-61
100
1k
10k
:!!.
",
100k
FREQUENCY (Hz)
*NOTE:
~
~
-20
:
1
, --. ...... ...
...120
~
-10
1\1
g 2.5
.100
~
3'
SlJslDIV
$ 2.0
.240
~
'
~ 2.
-1-- -
I
1 _aoIOIV
PHASE
40
iii"
:I
V
GAIN
V
~V.
::t2.5V supplies; no load to 10k load.
:II
if
-120
-180
1M
LOW NOISE, CHOPPER-STABILIZED
OPERATIONAL AMPLIFIER
TC7652
BONDING DIAGRAM
8-62
~~TELEDYNE
COMPONENTS
TC9420
TC9421
HIGH-VOLTAGE, AUTO-ZEROED OPERATIONAL AMPLIFIERS
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC9420 and TC9421 are high-voltage, high·
performance, CMOS chopper-stabilized operational amplifiers. They can operate from the same ±15V power sup·
plies as commonly used to power bipolar op-amps, such as
the OP07 and OP741. Previous CMOS chopper amplifiers,
such as the 7650, were limited to operating from ±7.5V
supplies.
Maximum Vos for the TC94201TC9421 is only 51lV,
almost a factor of 14 improvement over the industry-stan·
dard OP07E. The maximum Vos drift of O.lIlVrC is 12
times less than the OP07E. Input bias and offset currents,
both only 30 pA maximum, are factors of 60 improvements.
•
•
•
•
High-Voltage Operation ...................................±15V
Low Offset Voltage .................................... 5 11V Max
Low Offset Voltage Drift ••....•.....••....••...•... 0.1IlVrC
Low Input Bias Current ........•.................. 30 pA Max
High Open-Loop Voltage Gain ..................... 140 dB
Wide Common-Mode Voltage
Range ................................................... -15Vto +13V
Low Input Voltage Noise
(0.1 Hz to 1 Hz) ...••....••.•.•••........•......•.......... 0.2IlVp.p
Low Supply Current ......................................... 1 rnA
Single Supply Operation .......................... 7V to 32V
Output Clamp Speeds Overload Recovery Time
FUNCTIONAL DIAGRAM
~""
OUTPUT
CLAMP
CIRCUIT
TC9420
TC9421
+
>-~-----o OUTPUT
INPUT
Ce
B
F'"",OAC,
CA
B'
A'
OSC
B
CA
A
A
B'
A'
------------1
I
CA AND CB EXTERNAL CAPACITORS
INT/EXT
:
EXTClKIN
:
:
L..-_-+- ClK OUT
I _________________
14-PIN DIP ONLY
:
L
~
CA =C B =O.lI1F
1107·1
8·63
8
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
In addition to low initial offset errors, the nulling circuitry
ensures excellent performance over time and temperature.
Long-term drift, which results in periodic recalibration, is
effectively eliminated. The nulling circuitry continues to operate overthe full temperature range, whereas laser and "zener
zap" trimming are only done at a single temperature. The
result is a significant decrease in temperature-induced errors.
The TC9420rrC9421 operate from dual or single power
supplies. Supply current is typically 1 mA with ±15V supplies.
Single supply operation extends from +7V to +32V, and the
input common-mode range extends to Vs-. For battery operation, see the low-power TC900 data sheet.
The TC9420rrC9421 open-loop gain is 120 dB minimum. Unlike the 7650, the TC9420rrC9421 gain is independent of load resistance. The low impedance output will
drive a 10 kn load to ±14V. An output clamp circuit is
provided to minimize overload recovery time.
The TC9420rrC9421 use two amplifiers to correct offset voltage errors. A main amplifier is always in the signal
path, which prevents switching spikes at the output. A
separate nulling amplifier alternately corrects its own Vas
error. Only two external capacitors are required to store the
nulling error voltages. All active nulling circuitry, including
switches and oscillator, are included on the chip.
The TC9420rrC9421 are pin compatible with Maxim's
MAX 420/421.
PIN CONFIGURATIONS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Part No.
Package
TC9420CPA
8-Pin
Plastic DIP
TC9420EJA
8-Pin
Temperature
Range
(+)INPUT
Vs
13 ~X:~fNAL CLOCK
NC(GUARD)
(-) INPUT
(+)INPUT
NC(GUARD) 6
8-Pin
Total Supply Voltage (Vs+ to Vs-) ............................. +36V
Input Voltage ......................... (Vs+ + 0.3V) to (Vs- - 0.3V)
Storage Temperature Range .................. -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Current Into Any Pin ................................................ 10 mA
Operating Temperature Range
C Device ................................................ O°C to + 70°C
E Device ............................................. -40°C to +85°C
Package Power Dissipation (TA =+25°C)
CerDIP Package ............................................ 500 mW
Plastic Package ............................................. 375 mW
Max
Vos
O°Cto +70°C
-40°C to +85°C
-40°C to +85°C
Plastic DIP
TC9421CPD
TC9421EJD
14-Pin
Plastic DIP
14-Pin
O°Cto +70°C
-40°C to +85°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause perma·
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
CerDIP
TC9421EPD
14-Pin
9 OUTPUT CLAMP
NC = NO INTERNAL CONNECTION
CerDIP
TC9420EPA
12 ~J¥~NfL CLOCK
-40°C to +85°C
Plastic DIP
8·64
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
ELECTRICAL CHARACTERISTICS: vs+ = 15V, vs- = 15V, TA = +25°C. Test circuit unless noted.
Symbol
Vas
Parameter
Test Conditions
Input Offset Voltage
TA= +25°C
OVer Temperature Range
tNos
AT
16
Typ
Max
Unit
C
E
C
E
±1
±1
±2
±2
±10
±5
±20
±10
,N
ILV
ILV
ILV
Average Temperature
Coefficient of Input
Offset Voltage
OVer Temperature Range
E
0.02
0.1
ILV/oC
Input Bias Current
TA= +25°C
C
E
C
E
10
10
30
35
100
30
pA
pA
pA
pA
C
E
C
E
15
1S
30
SO
200
60
pA
pA
pA
pA
Over Temperature Range
los
Min
Input Offset Current
TA = +2SoC
Over Temperature Range
RIN
Input Resistance
1012
£1
AVOL
Large Signal Voltage
Gain
RL = 10 k£1, VOUT= ±10V, TA = +25°C
Over Temperature Range
120
120
150
150
dB
dB
VOUT
Output Voltage Swing
CLAMP Not Connected
±12
±14.5
±14.95
V
V
CMVR
Common-Mode
Vonage Range
+12,-1S
+13,-15.1
V
CMRR
Common-Mode
Rejection Ratio
CMVR = +12Vto -1SV
OVer Temperature Range
120
140
dB
PSRR
Power Supply
Rejection Ratio
±3V to ±16.5V OVer
Temperature Range
120
140
dB
eN
Input Noise Vonage
(Peak-to-Peak Value Not
Exceeded 95% of Time)
Rs= 100£1
0.3
1.1
ILVp.p
ILVp_p
f= 10Hz
0.01
pANRZ
IN
Input Noise Current
UGBW
Unity-Gain Bandwidth
sr
Slew Rate
tR
RL=10kn
RL= 100 kn
OCto 1 Hz
OCto 10 Hz
SOO
kHz
0.5
V/IJ.S
Rise Time
0.7
Overshoot
20
J.1s
%
CL= SO pF, RL= 10 kn
Vs+' Vs
Operating Supply Range
(Note 1)
±2.5
Is
Supply Current
No Load, TA = +25°C
Over Temperature Range
1.3
fCH
Internal Chopping
Frequency
Pins 12-14 Open (TC9421)
2S0
Hz
100
I!A
Clamp ON Current
RL= 100 kn
Clamp OFF Current
-10V .. VOUT" +10V
25
Offset Voltage vs Time
±16.S
1
100
NOTES: 1. Single supply operation: Vs+ = +7V to +32V.
8-65
2
3.5
V
mA
mA
pA
nVNfJO
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
Theory of Operation
Figure 1 shows the major elements of the TC9420/
TC9421. There are two amplifiers: the main (signal) amplifier and the nulling amplifier. Both have offset nulling capability. The main amplifier is always connected to the output.
The nulling amplifier alternately samples and adjusts its own
offset and then the offset of the main amplifier.
A two-phase operation nulls the main amplifier. During
the first phase, the A pair of switches close, while the B
switches open. Then nulling amp's inputs are shorted and its
output is fed back to the nulling input. Capacitor CA charges
to a voltage which will maintain the nulling amp in ITS nulled
state.
During the second phase, the B SWITches close and the
A switches open. The nulling amp's inputs now sample the
offset voltage of the main amp. The nulling amp drives the
main amp's nulling input to cancel the main amplifier's offset
voltage. CapacITor CB stores the nulling voltage of the main
amplifier while the nulling amp is being nulled on the next
cycle.
The TC9420/TC9421 design also incorporates an additional output buffer stage. The buffer provides a low impedance output traditionally associated with bipolar op amps.
Some CMOS chopper-stabilized amplifiers, such as the
7650, have a high output impedance which makes open-loop
gain proportional to load resistance. The TC94201TC9421
open-loop gain is not dependent on load resistance.
Pin Compatibility
Since the TC9420/9421 operate from the same ±15V
power supplies as bipolar op amps, upgrading existing
circuits is simple. The bipolar op amp's nulling and compensation components are removed, and the TC9420/TC9421
nulling capacITors are added.
On the 8-pin mini-DIP (TC9420), the external null storage capacitors are connected to pins 1 and 8. On most other
op amps they are left open or used for offset potentiometer
or compensation capacITor connections.
For OP05 and OP07 operational amplifiers, replacing
the offset null pot between pins 1 and 8 with two capacitors
from the pins to CRET will convert the OP05/07 pin configuration for TC9420 operation. The 741 is easily upgraded by removing the nulling pot between pin 4 and pins
1 and 5, then connecting capacitors from pin 4 to pins 1
and 8. For LM108 devices, the compensation capacitor is
replaced by the external nulling capacitors. The LM101/
7481709 pinouts are modified similarly by also removing
any cirCUIT connections to pin 5.
The minor modifications needed to retrofit a TC9420
into existing sockets make prototyping and cirCUIT verification straightforward.
Nulling Capacitors
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is made to
CRET (pin 5) on the 8-pin packages and to capacitor return
(CRET, pin 8) on the 14-pin packages. The common connection should be made through either a separate pc trace
or wire to avoid voltage drops.
Internally, Vs- is connected to CRET.
CA and CB should be 0.1 I1F film capacitors. Mylar
capacitors are suitable.
>--+--0 OUTPUT
V-o-~------~----~
v+
ANALOG
INPUT
LOW IMPEDANCE
BUFFER
B
~'"
TC9420
TC9421
CB
V
__--<>----,
V
A
EXTERNAL
CAPACITORS
CA
Figure 1. TC94201TC9421 Contain a Nulling and Main Amplifier. Offset Correction Voltages Are Stored on Two EX1ernal Capacitors.
8-66
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
Vs Vs
14-PIN PACKAGE
clock is generated by +5V logic, capacitive coupling to pin 13
(through a 0.1 j.lF capacitor) will provide adequate drive.
At low frequencies, the external clock duty cycle is not
critical, since an internal + 4 gives the desired 50% switching
duty cycle. The offset storage correction capacitors are
charged only when the external clock input is high. A 50% to
80% external clock positive duty cycle is desired forfrequencies above 500 Hz to guarantee transients settle before the
internal switches open.
The external clock input can also be used as a strobe
input. If a strobe signal is connected at the external clock
input so that it is low during the time an overload signal is
applied, neither capacitor will be charged. This function can
be used to prevent input transients from overloading the
nulling circuitry. Leakage currents at the capacitor pins are
very low, so offset voltage drift during strobe operation is
minimized.
V+
S
S-PIN PACKAGE
(PIN 8 IS INTERNALLY
CONNECTED TO PIN 7)
Output Clamp
Figure 2. Nulling Capacitor Connection
Chopper-stabilized systems can show long recovery
times from overloads. If the output is driven to either supply
rail, output saturation occurs. The inputs are no longer held
at a "virtual ground." The Vas null circuit treats the differential signal as an offset and tries to correct it by charging the
external capacitors. The nulling circuit also saturates. Once
the input signal returns to normal, response time is lengthened by the long recovery time of the nulling amplifier and
external capacitors.
Through an external clamp connection, the TC9421
eliminates the overload recovery problem by reducing the
feedback network gain before the output voltage reaches
either supply rail.
The output clamp circuit is shown in Figure 3, with
typical inverting and noninverting circuit connections shown
in Figures 4 and 5. For the clamp to be fully effective, the
impedance across the clamp output should be >100 kil.
When the clamp is used, the clamp "OFF" leakage will
add to input bias current. However, clamp leakage in the
"OFF" state is typically only 1 pA.
Component Selection
The two required capacitors, CA and CB, have optimum
values, depending on the clock or chopping frequency. For
the preset internal clock, the correct value is 0.1 j.lF. To
maintain the same relationship between the chopping
frequency and nulling time constant, the capacitor values
should be scaled in proportion to the external clock, if used.
High-quality film-type capacitors (such as Mylar) are preferred. Ceramic or other lower-grade capacitors may be
suitable in some applications. Forfast settling on initial turnon, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several
seconds may be required to settle to 1 j.lV.
Clock Operation
The internal oscillator is set for a 1000 Hz nominal
frequency on both the 8-pin and 14-pin 01 Ps. With the 14-pin
01 P (TC9421), the 250-Hz internal frequency is available at
the internal clock output (pin 12). A 1000 Hz nominal signal
will be present at the external clock input (pin 13) with INT/
EXT high or open. This is the internal clock signal before a
+4 operation.
The 14-pin device can be driven by an external clock.
The INT/EXT input (pin 14) has an internal pull-up and may
be left open for internal clock operation. If an external clock
is used, INT/EXT must be tied to Vs- (pin 7) to disable the
internal clock. The external clock signal is applied to the
external clock input (pin 13).
The external clock amplitude should swing between Vs+
and ground for power supplies up to ±6V, and between Vs+
and Vs+ -f3V for higher supply voltages. When the external
Input Bias Current
The TC9420ITC9421 are never disconnected from the
main internal amplifier. The null amplifier samples the input
offset voltage and corrects DC errors and drift by storing
compensating voltages on external capacitors. The sampling, however, causes charge transfer at the inputs.
The impulse current is not usually a problem because
the amount of charge transferred is very small. Care should
be exercised, however, when replacing high-input bias
current bipolar op amps. Conventional design practice is to
cancel bias current by matching the input impedances
(Figure 6a). The TC9420ITC9421 have input bias current of
8-67
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
i
NTERNAL
POSITIVE CLAMP BIAS
r----,
~
only 100 pA maximum, so the additional resistor is not
necessary. In fact, including the resistor makes the charge
injection current, passing through the impedance-balancing
resistor, appear as a noise source. When replacing an
existing op amp with the TC94201TC9421, omit the resistor
or bypass it to ground with a capacitor (Figure 6b).
+
+
Vs -VT ~ Vs - O.7V
P-CHANNEl
~.-1_-0 OUTPUT
t'--_----'l
Latch-Up Avoidance
CLAMP PIN
T=
Junction-isolated' CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCA. Under certain circumstances, this
junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition,
voltages greater than 0.3V beyond the supply rails should
not be applied to any pin. In general, the amplifier supplies
must be established at the same time or before any input
signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 0.1 rnA to avoid latchup.
N-CHANNEl
INTERNAL
NEGATIVE CLAMP BIAS - Vs + VT
~ VS+O.7V
L---------o
TC942arTC9421
OUTPUT PIN
Figure 3. Internal Clamp Circuit
O.1I1F
Static Protection
O.1I1F
~'"
All device pins are static-protected. Strong static fields
and discharges should be avoided, however, as they can
degrade diode junction characteristics and increase inputleakage currents.
Many companies are actively involved in providing
services, eductional materials. and supplies to aid electronic
manufacturers in establishing "static safe" work areas where
CMOS components are handled. A partial company listing
is:
TC9420
TC9421
INPUT_------!
>-'-I~ OUTPUT
R3 + ( R 1/R2 ) ;, 100 k.Q
FOR FUll CLAMP EFFECT
-3M
Static Control Systems Division
223-25W EM Center
St. Paul, MN 55101
(800) 792-1072
Figure 4. Noninverting Amplifier With Optional Clamp
- Semtronics
P.O. Box 592
Martinsville, NJ 08836
(210) 561-9520
~'"
TC9420
TC9421
INPUT
>-.......~~
OUTPUT
(R 1 II R2 ) .. 100 k.Q
FOR FUll CLAMP
EFFECT
O.1I1F O.1I1F
Figure 5. Inverting Amplifier With Optional Clamp
8-68
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
...,'"
+1SV
TC9420
INPUT <>---\1'\1
I
.¢.
-1SV
/
FREQUENCY
COMPENSATION
OMIT OR BYPASS
RESISTOR WITH
TC91S
(a) High-Input Bias Current Op Amp
-1SV
(b) Low-Input Bias Current (TC9420)
Figure 6. Input Bias Current Cancellation
TYPICAL CHARACTERISTICS CURVES
Input Offset Voltage vs
Common-Mode Voltage
Supply Current
vs Supply Voltage
35
1400
TA= +2S D C
~
1200
<"
.:: 1000
~
~
a:
800
()
600
/'.-- f-
:::I
~
/
ro-
f-"
V
w
~
25
g
20
I-
~
15
u..
Q.
~
TA = +2S D C
D
30 c- Vs= +1S C
o
400
5
III
10
Q.
iE
200
o
5
o
o
2
4
:I:
~ I-
-
f-""
L.-
-
I--
""
-15 -12 -9 -6 -3 0 +3 +6 +9 +12 +15
INPUT COMMON·MODE VOLTAGE (V)
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
8·69
•
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
TYPICAL CHARACTERISTICS CURVES (Cont.)
Gain and Phase
vs Frequency
Output Voltage Swing
vs Load Resistance
50
CLOSEO:LOOP GAIN = 100
.
III
40
GAIN
30
"
~20
225
18
180
>,,15
90
~ 10
45
,
o
lk
~ 9
!fa!
a..
..J
~
:r:
I-
6
::J
a..
I-
::J
0
3
o
-90
1 MHz
10k
lOOk
FREQUENCY (Hz)
loon
TA = +25"C
~ 12
.,/
~
,./ V
z
~
8
~
4
~
0
I-
~ -4
~
k
w
I-"'"
~ 15
V-
~
~
w
.......
-8
~ -12
8 -16
lMn
20
~ 16
~
Z
o
1 kn
10 kn
100 kn
LOAD RESISTANCE
Input Offset Voltage
vs Clock Frequency
Input Common-Mode Voltage
Range vs Supply Voltage
!:i
POSITIVE SWING
w
-45
-20
100 Hz
111111
IlrEIGI~~II~~ S~I~I~II
Cl
0
-10
I'U
1
~ 12
i:!!.
w
PHASE
z
z
135
1\
V~I~ ~I~~V
o
2
r--.....
10
V
LL.
o
VCM =Vs
........ ..........
!:i
a..
.........
5
./'
l5
r-....
4
6
8 10 12 14
:t SUPPLY VOLTAGE (V)
o
100
lk
10k
EXTERNAL CLOCK INPUT FREQUENCY (Hz)
16
Input Offset Voltage
vs Supply Voltage
Input Voltage Noise
7
VCC =:t15V
TA = +25"C
TA = +25"C
>':'6
j
w
I
Cl
~ 5
If..BANDWIDTH = 0.1 TO 10 Hz
,lI A A
v
AA, fhA ••I.AII
-r"(
.Il
..J
.1.111
~
T
tii
/
4
~
B~ND~dH =1 0.1 ~O ~ Hz
-I
r T
~ 3
!:i
Rs = loon
VERTICAL = 1 IIVIDIV
HORIZONTAL = 1 SECIDIV
-r-
~ 2
V
/'
V
1
o
8-70
2
4 6 8 10 12 14 16 18 20
:t SUPPLY VOLTAGE (V)
HIGH-VOLTAGE, AUTO-ZEROED
OPERATIONAL AMPLIFIERS
TC9420
TC9421
TYPICAL CHARACTERISTICS CURVES (Cont.)
Positive Overload
Recovery Time
Negative Overload
Recovery Time
I I
RL=10kQ
-TA=+2S o C
I
I
r
IN~UTI
I II
INPUT
VERTICAL
SCfLE 2VIDIV
t
I I
ouhut
VERTICAL
SCALE = 2V1DIV
OV
Ir
rl
L
I I
-
V ..... OV
VERTICAL
SCALE = SVIDIV
,I
RL = 10kQ
TA= +2So C r-- OV
OUTPUT
VERTICAL
SC~LEI= Sy'DIV
I I
\
ob
GAlN=I_1
GAIN =-100
OV
HORIZONTAL SCALE = 50 mS/DIV
HORIZONTAL SCALE = 50 mS/DIV
8-71
..
NOTES
8-72
Section 9
High Performance
Ampl ifiers/B uffers
Display AID Converters
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Ampliflers/Buffer.
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
..
~"'TELEDYNE
COMPONENTS
1321
WIDE BAND, HIGH SLEW RATE
OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The 1321 is a bipolar input operational amplifier that
combines high speed AC performance (35V/J.lS slew rate,
100 MHz GBWP) with superior DC characteristics (300 Mn
input impedance, ±5 nA input bias current, 100 dB gain).
This combination of features makes it ideal for video and
pulse amplifiers, fast integrators, high-Q active filters, and
high-speed current-to-voltage converters.
This device is internally compensated for stable operation in circuits operating at closed loop gains of 5 or above_
For operation at lower closed loop gains, an external compensation capacitor is required from Pin 8 to ground (or the
alternate stabilizing scheme shown in Figure 1 may be
LowCost
Fast Settling ....................................... 0.1% in 1 J.lsec
Slew Rate ••••.•..•.•...•.•••....••..•.•.•...•..•....•.•..••••. 35V/J.lsec
Full Power Bandwidth ....•......•.....•••.•..•••......• 600 kHz
Open Loop Gain ............................................. 100 dB
Gain Bandwidth Product •.....•.....••.•.........•••. 100 MHz
APPLICATIONS
•
•
•
•
•
•
High-Frequency Amplifiers
Current-to-Voltage Converters
Video Amplifiers
Differential Amplifiers
Line Drivers
Wide band Precision
used).
. .
The standard 1321 is housed in a small outline, metal
•
TO-99 case and IS specified for O°C to +75°C operation.
PIN CONFIGURATION
Pin
No.
Designation
OFFSET ADJUST
-IN
+IN
-Vee
OFFSET ADJUST
OUTPUT
2
3
4
5
6
7
8
+Vee
BANDWIDTH CONTROL
BOTTOM VIEW
9-1
1037 1
v
-
- ...-
--
WIDEBAND, HIGH .SLEW RATE
OPERATIONAL AMPLIFIER
1321
ABSOLUTE MAXIMUM RATINGS
vee
VI OF
Te
TSTG
Supply VoHage ........................................... ±22.5V
Differential Input Voltage ............................... ±12V
Operating Temperature Range (Case)
1321 .............................................. O°Cto+75°C
Storage Temperature Range ...... --65°C to +150°C
ELECTRICAL CHARACTERISTICS: Te = +25°C, ±Vee = ±15V, Rl = 2 kn unless otherwise indicated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input
Ib
-
Input Bias Current
TMINto TMAX
lOS
Input Offset Current
vas
Input Offset Voltage
VOSTC
vas vs Temperature
TMIN to TMAX
Without external trim
PSRR
Input Offset vs Power Supply
VICM
CMRR
Common Mode
Common Mode Rejection Ratio
For DC linear operation
@ DC
liD
Differential Input Impedance
@DC
±5
-
±25
±40
nA
nA
±5
±25
±40
nA
nA
-
±3
±5
±5
mV
llV/oc
-
-
90
±11
±12
-
100
-
300
Output
-
dB
V
dB
Mn
va
Voltage
±10
±12
Current
±10
±18
-
V
10
@DC
98
104
dB
14
-
-
Stable operation w/o compensation
Voltage Gain
AOL
Open Loop Vottage Gain
ACL
Closed Loop Gain
Frequency Response
GBWP
Gain Bandwidth Product
FPBW
Full Power Bandwidth
=10, Cc =0 pF, 11 =10 kHz
=0 pF
Slew Rate
dB
-
MHz
70
100
320
600
-
1
ACL ~ 5, Cc = 0 pF
±20
±35
-
Ils
V/IlS
-
45
25
15
-
nVNHz
nVNHz
nVNHz
-
±15
±22.5
±3
±4
Noise (Referenced to Input)
en
Midband (10 10Hz)
Highband (10 100 Hz)
Wideband (10 1 kHz to 100 kHz)
=
=
=
Power Supplies
Po·wer Supply Vottage
Vcc
Quiescent Supply Current
Icc
-
ACL ~ 5, Cc
ACL
Time Response
ts
Settling Time
1OV step to 0.1%
sr
mA
Vce
=±15V
9-2
-
kHz
V
mA
WIDEBAND, HIGH SLEW RATE
OPERATIONAL AMPLIFIER
1321
I lao
10k
I
e
VIN
VOUT
Figure 1.
~
~
40
2D
0
Figure 2.
Optional Stabilizing Scheme
(for uni1y gain stabili1y at high speed)
9-3
Bode Plot
NOTES
9-4
~,"TELEDYNE
COMPONENTS
1322
WIDEBAND, HIGH SLEW RATE
OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The 1322 is a high-speed, fast-settling operational
amplifier designed for a wide variety of high-speed signal
processing tasks. Its fast, accurate settling performance
(200 ns to 0.1% accuracy for a 10V step) and good DC
specifications (84 dB open loop gain, 10 mV offset voltage)
make the 1322 eminently suitable for high speed 8- and 10bit data conversion applications. In addition, its high slew
rate (120V/~) serves it well in high-speed pulse circuits,
signal generators, or other circuits where full output swings
at signal frequencies as high as 1.6 MHz are required.
This device is internally compensated for stable operation in circuits operating at closed loop gains of 3 or above.
For operation at lower closed loop gains, an external compensation capacitor is required from Pin 8 to ground (or the
alternate stabilizing scheme shown in Figure 1 may be
used).
The standard 1322 is housed in a small outline, metal
TO-99 case and is specified for ooe to +75°C operation.
Low Cost
Fast Settling ..........•..................... 0.1% in 200 ns typo
Slew Rate ..•...•.........••...........•..................... 120V/~sec
Full Power Bandwidth .•....•........................... 1.6 MHz
Open Loop Gain ............................................... 84 dB
Gain Bandwidth Product •.............................. 20 MHz
APPLICATIONS
•
•
•
•
•
•
High-Frequency Amplifiers
Current-to-Voltage Converters
Video Amplifiers
Differential Amplifiers
Line Drivers
Wideband Precision
PIN CONFIGURATION
Pin
No.
2
3
4
5
6
7
B
1038-1
Designation
OFFSET ADJUST
-IN
+IN
-Vcc
OFFSET ADJUST
OUTPUT
+Vcc
BANDWIDTH CONTROL
BOTTOM VIEW
9·5
...
.:.
WIDEBAND, HIGH SLEW RATE
OPERATIONAL AMPLIFIER
1322
ABSOLUTE MAXIMUM RATINGS
vee
VIDF
Te
TSTG
Supply Voltage .............................................. ±20V
Differential Input Voltage ............................... ±15V
Operating Temperature Range (Case)
1322 .............................................. O°C to +75°C
Storage Temperature Range ...... -65°C to +150°C
ELECTRICAL CHARACTERISTICS: Te =+25°C, ±Vee =±15V, RL =2 kn unless otherwise indicated.
Symbol
Parameter
Input
Ib
Input Bias Current
Test Conditions
TMINto TMAX
lOS
VOS
VOSTC
PSRR
VICM
CMRR
llo
Input Offset Current
Input Offset Voltage
VOS vs Temperature
Input Offset vs Power Supply
Common Mode
Common Mode Rejection Ratio
Differential Input Impedance
Output
VO
Voltage
10
Current
VoJtageGain
AOL
Open Loop Voltage Gain
ACL
Closed Loop Gain
Frequency Response
GBWP
Gain Bandwidth Product
FPBW
Full Power Bandwidth
Time Response
Is
Settling Time
sr
Slew Rate
Noise (Referenced to Input)
en
Wideband (10Hz to 1 kHz)
Power Supplies
Power Supply Voltage
Vcc
Quiescent Supply Current
Icc
TMIN to TMAX
Without external trim
Min
Typ
Max
Unit
--
±125
±250
±500
±50
±100
±10
nA
nA
nA
nA
mV
-
-
±20
-
-
±5
±30
90
±10
-
-
-
IlV/oC
90
100
-
40
-
dB
V
dB
Mn
±10
±10
±12
±20
-
V
rnA
@DC
Stable operation wlo compensation
77
10
84
-
-
-
dB
dB
ACL~3,
ACL = 10, f = 10 kHz
Cc= 0
10
1.2
20
1.6
-
MHz
MHz
10V step to 0.1%
ACL=3,Cc=0
200
±120
-
±80
-
ns
V/IlS
-
1
-
IlVRMS
-
±15
±4
±20
±6
V
For DC linear operation
@DC
@ DC
Vcc=±15V
9-6
-
-
rnA
WIDEBAND, HIGH SLEW RATE
OPERATIONAL AMPLIFIER
1322
10k
III
OPTIONAL
COMPENSATION
II
OpFII
10k
'"
VOUT
F::
"
3CpF
~.
t'
II
lliIIp&
~
3IIDpF
I IIIiDCIIIf
~
'bot
lOG
Figure 1.
Optional Stabilizing Scheme
(for unity gain stability at high speed)
I ""
Figure 2.
9·7
Bode Plot
lau
,_
NOTES
9-8
~"'TELEDYNE
COMPONENTS
1332
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The 1332 bipolar amplifier provides solutions to problems not solved with the typical 741. Specifications are
optimized to provide such capabilities as low drift, high
output voltage swing and high speed.
This true differential operational amplifier is matched
pin-for-pin with the standard 741 (including 10 Kn optional
trim-pot connection).
The 1332's smooth 6 dB/octave roll off provides stable
operation at all values of gain, even when connected as a
unity gain follower.
The 1332 has a low initial offset voltage of 6 mV and is
specified for O°C to +75°C operation.
Full Power Frequency .................................... 25 kHz
±Vcc Range ........................................................ ±40V
Common Mode Range ....................................... ±35V
Slew Rate ......................................................... ±5V/l1s
APPLICATIONS
•
•
•
Precision High Voltage Source
Avionics, 48V Operation
Process Control
PIN CONFIGURATION
Pin
No.
G
4
-IN
+IN
-Vee
5
OFFSET ADJUST
2
3
Optional
10 k.Q
Eos Trim
Designation
OFFSET ADJUST
6
OUTPUT
7
+Vcc
NC (Bandwidth Control)
B
BOTTOM VIEW
1039-1
9-9
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
1332
ABSOLUTE MAXIMUM RATINGS
vee
VIDF
V,eM
Te
TSTG
Supply Voltage .............................................. ±40V
Differential Input Voltage ............................... ±Vee
Common Mode Input Voltage ........................ ±Vee
Operating Temperature Range (Case)
1332 .............................................. O°C to +75°C
Storage Temperature Range ...... --65°C to +150°C
ELECTRICAL CHARACTERISTICS:
Symbol
InpUt
IB
IslTC
los
Vos
Vos/TC
PSRR
V'CM
CMRR
Parameter
Te = +25°C, Vee = ±40V, unless otherwise noted.
Test Conditions
Initial Input Bias Current
Without External Trim
IB vs Temperature
Input Offset Current
Input Offset VoltageWithout External Trim
Vos vs Temperature
@DC
Input Offset vs Power Supply
Common-Mode Input Voltage
DC Linear Operation
@ DC
Common-Mode Rejection Ratio
Differential-Mode Input Impedance
Common-Mode Input Impedance
Z'DF
Z'CM
Output
Output Voltage
Vo
Output Current
10
Voltage Gain
Open-Loop Voltage Gain
AOL
Frequency Response
UGBW
Unity Gain Bandwidth
FPBW
Full Power Bandwidth
Time Response
Slew Rate
sr
RL
=Rated Load
Open Loop
Sine Wave, 3 to 5% distortion
Power Supplies
Power Supply Voltage
Vcc
Icc
Quiescent Supply Current
Min
-
-
74
74
-
9-10
±2
±15
90
100
200
1000
30
0.4
30
±6
±20
nA
nAloC
nA
mV
IlV/oC
-
dB
±35
V
dB
MQ
MQ
-
±35
±10
±12
100
106
-
dB
-
4
25
-
MHz
kHz
-
±5
-
V/JlS
-
±40
V
±3.2
±4.5
mA
-
NOTE: The inputs are protected to ±Vcc. The output is protected against short circuit to ground.
-
Max Unit
-
-
±10
Quiescent
Typ
-
V
mA
HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
1332
Single Supply Operation
The 1332, operating with a ±40V power supply, can
drive ±35V into 2.7 kn at 25 kHz (Figures 1 & 2). Under
maximum load conditions, the output can be short circuited
to common without danger, as the outpu1 is limited by a chip
temperature sensing circuit.
To decrease bandwidth, capacitance may be added
between Pin 8 and common. The effect of this capacitance
is shown in Figure 3.
Figure 4 shows a 1332 operating as an inverter from a
single supply. This will allow a 1332 to operate from a 48V
aircraft or vessel power.
..
'110
f---
"
VSU"LY" tiDY
>
~
i
"0
>
......
'"
So
o'"
~
~
..
~
I
.!iSDe: \"Z5DC,
·lD
15
10
fll 11/
' ,/"1+1Sle
..!
II
+t'JIC
..
'IIOK
Frequency, Hz
AV" I, VSU"l Y " tlDV
".~"
AY-',VSUPPly-:t4DV
..,
VIN .-35\/
Figure 2.
g.
o
,"
',. ,* *
Output Current
VCC
'L • ,....
10
>--""'--0 eo
tll
...
I"
VIN··1511
·20
·30
I
~-+-~
~ 1,.,
120,---------.-
"r---t--+--"'~~~~'::
~ .r---t--+--t---4~~~~~~
o
.•
_ssGc
Output load Current, rnA
Output Voltage Swing vs Frequency at 25'C
CD
IS
10
Ll ~\..
l
I
I
/I 1/ /1 !"
.,
• 1ft
·. ·1
I
I
11 I
VIN =·15V
r--+15DC
I
_5s Oe I tlSDC /+llSIIC
'OK
.\".>
1-
0
0
>
:>
I!:
:>
I!:
:>
/
..
400
800
"
100
1K
LOAD RESISTANCE (0)
Figure 5.
/'
10mV
·10
200
10mV
Output Voltage Swing vs Load Resistance
Figure 6.
9·15
V
~
200
300
400
500
SETILING TIME (n8)
Settling Time for Various Output Step Voltages
B..
MONOLITHIC
WIDEBAND, JFET INPUT
OPERATIONAL AMPLIFIER
1344
~
I
ill
~
.. r\. ""~ k. T
1""-.....)"
~
2D
~
~
~
~:: ~
a.
r
'DO
"
Figure 8.
-
Input Noise Cunent
-
1
,.
~
~.
SOLM'C8 Realst8ncfl,. 100 kn
..........
¥
~7
Source Reefsbnc:e=OO
0
>
l
1"-"-
12.
w
U
1
1
~
I!
~
a4
~
~3
~
a,
~
100K
'OK
FREQUENCY (Hz)
Input Noise Voltage and
Noise Current vs Frequency
VI
TEMPEFlATUflE(OC}
Figure 7.
100
............... .....
Input Offset Voltage and
Bias Current vs Temperature
35
:J:.VCC=~OV
1
30
lil
25
~
........
10
\
20
""!:i
15
:t:Vcc=:s:.7V
>
....
10
:tVcc=:t10V
~
."
Figure 9.
~
-........ \
0
"0
>-i
......
~Q
~~
Ul Z
100K
10K
lOOK
1M
ffiQ
;:>i~
il!
10M
FREQUENCY (Hz)
Common Mode Rejection Ratio vs Frequency
·Vee
~
..
8D
.Vee
••
20
10
100
10K
lK
100K
FREQUENCY (Hz)
Figure 10. Output Voltage Swing vs Frequency
Figure 11. Power Supply Rejection Ratio vs Frequency
10
00
8D
70
'"
.
50
~ i"'..
r----...~
.pF
......... I "pF
'>1 . . . . . . . . "'-I
........
................
"
~
" "'''
.:-.....'"
"'pF
.........
/".,
..............."')(
"
"
.
........ ""pF
/"-
"~r-..
10
10
1k
..
,
,,..
1M
lDO
~
....
1K
10K
lK
FREQUENCY (Hz)
:s:.Vcc=:t:15V
~
w
lDD
"'
~I\
........
1'\\
,OM
''M
FREQUENCY (Hz)
-80
·40
40
TEMPERATURE
Figure 12. Open Loop Frequency Response For Various
Bandwidth Control Capacitances
80
120
~c
Figure 13. Power Supply Current vs Temperature
9·16
1M
~,"TELEDYNE
COMPONENTS
1346
MONOLITHIC
LOW BIAS CURRENT
OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The 1346 High Performance, Monolithic Operational
Amplifier combines JFET/Bipolar technology and dielectric
isolation to provide the best AC and DC characteristics
available in any monolithic device of its type. Specifications
of 250 fA input bias current and 3 mV maximum offset
voltage combined with 2 MHz unity gain bandwidth and 7VI
Jls slew rate make the 1346 ideal for such applications as
high impedance, high performance buffers, precision track!
hold amplifiers and long-term precision integrators. The
1346 is housed in an S-pin TO-99 package.
Unity Gain Bandwidth Product ....................... 2 MHz
Bias Current ................................................... ±2S0 fA
Offset Voltage .••......•.......•....•.•.....••.....••...±3 mV Max
Settling to ±D.1% •••.....•.....•.•...•.•....•.......•••...•••.•..• 2 JlS
Power Consumption •••••.•••••.•••..•.•.•..••..•.. 30 mW Max
APPLICATIONS
•
•
•
Track/Hold Amplifiers
Electrometer Amplifiers
Precision Amplifiers
PIN CONFIGURATION
Pin
No.
Designation
2
3
4
5
6
7
8
TRIM
INVERTING INPUT
NON-INVERTING INPUT
-Vee
TRIM
OUTPUT
+Vcc
CASE
1041·1
BOTTOM VIEW
9-17
..
MONOLITHIC
LOW BIAS CURRENT
OPERATIONAL AMPLIFIER
1346
ABSOLUTE MAXIMUM RATINGS
Vee
VIDF
Te
TSTG
PD
Supply Voltage .............................................. ±20V
Differential Input Voltage ............................... ±Vee
Operating Temperature Range (Case)
1346 .............................................. O°C to +75°C
Storage Temperature Range ...... --65°C to +150°C
Power Dissipation ...................................... 300mW
ELECTRICAL CHARACTERISTICS:
Symbol
Parameter
Te = +25°C, Vee = ±15V, unless otherwise noted.
Test Conditions
Min
Typ
Max Unit
Input
Is
-
Input Bias Current
TMINto TMAX
los
Input Offset Current
PSRR
Input Offset vs Power Supply
TMINto TMAX
Without External Trim
TMINtoTMAX
@ DC, Vee ±1 OV to ±20V
VI eM
CMRR
Common-Mode Input Voltage
Common-Mode Rejection Ratio
DC Linear Operation
@DC
liD
Differential Input Impedance
@ DC
Va
Output Voltage
RL= 2 kQ
10
Output Current
lose
Output Short Circuit Current
lo
Output Impedance
Vos
Input Offset Voltage
=
-
-
±0.25
±6
±0.03
±1
±1
-
±1
±30
pA
pA
±0.2
±5
pA
pA
±3
±4
mV
mV
85
105
-
dB
±10
±12
110
-
V
dB
1
-
GQ
±10
±12
±10
±15
-
mA
-
(Note 1)
-
Q
90
-
-
Output
-
25
RL=2kQ
TMINto TMAX
106
103
120
RL= 2kQ
-
V
-
Voltage Gain
AOL
Open-Loop Voltage Gain
-
-
dB
dB
110
-
kHz
±4
2
±7
-
-
75
-
-
±15
±20
±0.8
±1
-
Frequency Response
UGBW
Unity-Gain Bandwidth
FPBW
Full-Power Bandwidth
Time Response
ts
sr
SetllingTime
Slew Rate
tR
Small Signal Rise Time
10V Step to 0.1%
Power Supplies
Vee
Power Supply Voltage
lee
Quiescent Supply Current
Vee
=±15V
-
2
Note 1: Output can withstand a short to ground for an indefinite length of time. Shorts to either supply will result in destruction.
9-18
MHz
llS
V/llS
ns
V
mA
MONOLITHIC
lOW BIAS CURRENT
OPERATIONAL AMPLIFIER
1346
Applications Information
The 1346 is one of the lowest input bias current monolithic operational amplifiers available. When used in applications requiring maximum performance, precautions must
be taken against unwanted noise and leakage current. To
minimize leakage currents a teflon socket is recommended.
IN 0 - - - - - - - 1
~----_.~~.-_o
Bypass capacitors should be as near as possible to the unit
and the unit should be as near as possible to the signal
source. The dielectric isolation process and JFET input
design protect the 1346 against input signal transients
beyond the level of the supplies as well as large differential
signals equal to the differential supply voltage without
degradation of performance.
OUT
.,,,
-,;,----0 OUT
IN
SOpF
1346
Figure 1.
Slew Rate and Transient Response
Figure 2.
Suggested Offset Adjustment Circuit
RI
~S-"'--OOUT
">.;S,.....4----00UT
Figure 3.
Current to Voltage Converter
Figure 4.
9-19
Very High Impedance Noninverting Amplifier
..
NOTES
9-20
~"'TELEDYNE
COMPONENTS
1430
FAST SETTLING, FET INPUT
OPERATIONAL AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The 1430 is a high speed, precision, FET input hybrid op
amp that features fast settling time, low bias current, high
slew rate, wide bandwidth, and good phase margin. Guaranteed settling time of 200nsec (10V step to 0.01%) and a
design that is tailored for inverting applications make the
1430 an ideal output amplifier for fast 12 bit 01A converters
and other applications such as sample-hold amplifiers and
radar pulse amplifiers.
The 1430 was carefully designed so that output settling
time would not vary appreciably with closed loop gain
(Figure 1). This is particularly important for currentto voltage
converter applications as with high speed current-output
OACs (see Figure 2). The 1430 requires only a feedback
capacitor for stability at closed-loop gains of unity and
above.
The 1430 is packaged in a 14-pin metal platform package. Both the standard 1430 and the High Reliability (HR)
1430 are specified to operate over the -55°C to +125°C
temperature range.
Settling Time to ±O.01% (10V step) •••••..• 200 ns Max
Operating Temperature •••••••••••.••••••• -55°C to +125°C
Gain Bandwidth Product ............................. 100 MHz
Slew Rate •••••••••••••••••••••.••••••••••••••.••••••••.••••..... 750V/Jls
Output ..................................................±11 V, ±55 mA
APPLICATIONS
•
•
•
•
Digltal-to-Analog Converters
SampleIHold Circuits
Pulse Amplifiers
Wideband Amplifiers
PIN CONFIGURATION
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1042-1
Designation
NC
TRIM
TRIM
-IN
+IN
-Vee
NC
COM
NC
OUTPUT
1430
~'"
@
1
@@@ @@ @
2
3
4
5
6
7
BOTTOM VIEW
+Vcc
TRIM
NC
NC
9-21
14
13
@
@@@@
12
11
10
9
8
@
@
•
FAST SETTLING, FET INPUT
OPERATIONAL· AMPLIFIER
1430
300 ns ,..---T"'""--..,-----,
~
1=
"::Jz 200 n8 1---+---:::.....
~
'+----:::;00/
11
~ 100 ns ~""""-+---+-----1
Ons~
1
__
~
__
~
__
5
10
CLOSED LOOP GAIN
~'"
r - - - -....
21
.;z
o
ii:
~
r---H---.,
DIGITAL
INPUT
1430
10
DIA
CONVERTER ....,,'+---1
~
15
Rf= lK
Cf = 10pF
Figure 1.
SeWing Time VB Closed Loop Gain
Figure 2.
Output Amplifier for DIA Converter
ABSOLUTE MAXIMUM RATINGS
T STG Storage Temperature Range ...... -65°C to + 150°C
(1) Operation above 85°C requires a 20°C/W heat sink.
Supply Voltage .............................................. ±18V
Differential Input Voltage ............................... ±Vee
Common Mode Input Voltage ........................ ±Vcc
Operating Temperature Range (Case)
1430 ......................................... -55°C to + 125°C
1430-HR ............................. -55°C to +125°C (1)
DC CHARACTERISTICS: (Note 1) Vee = ±15V, RL = 1 kil, inverting circuits only, Te = 25°C,
unless otherwise noted.
1430
Symbol
Parameter
Vos
Input Offset Voltage
VosTC
Input Offset Voltage Drift vs Temperature
Test Conditions
Average, T MIN to T MAX
1430-HR
Min Typ Max Min Typ Max Unit
-
-
±0.5
±2
±40
-
±10
±100
Is
Input Bias Current
IsTC
Input Bias Current Drift vs Temperature
los
Input Offset Current
10sTC
Input Offset Current Drift vs Temperature
Average, T MIN to T MAX Doubles every 11°C
AVOL
PSRR
Open-Loop Voltage Gain
RL=200Q
CMRR
Common-Mode Rejection Ratio
CMR
Common-Mode Range (DC Linear Operation)
liD
Differential Input Impedance
llCM
Common-Mode Input Impedance
Vo
Output Vottage Swing
10
Output Current
Isc
Output Short-Circuit Current
-
±110
Ro
Output Resistance (DC Open-Loop)
-
-
1000
-
Vcc
Supply Voltage Range (Operating)
±10
±15
±IB
Icc
Quiescent Supply Current
-
±20
±25
Average, T MIN to T MAX Doubles every 11°C
-
Power Supply Rejection Ratio
VCM = ±2V
±2
106
120
-
80
-
65
-
+3/-10
-
10"113
-
-
-
-
10"113
-
RL=200Q
±10
±11
-
RL= 200Q
±50
±55
-
-
±0.5
±40
±10
±2
Doubles every 11°C
-
±2
-
pA
Doubles every 11 °C
-
106
dB
-
-
120
BO
65
+31-10
10"113
10"113
±10 ±11
±50 ±55
-
-
dB
dB
V
QllpF
QllpF
-
V
mA
-
±110
-
mA
-
1000
-
Q
±10
±15
±IB
V
-
±20
±25
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100"10 production tested. Limits in nonnal font are guaranteed but not 100"10
production tested.
9-22
mV
±100 "V/"C
±100 pA
FAST SETTLING, FET INPUT
OPERATIONAL AMPLIFIER
1430
AC CHARACTERISTICS: (Note 1) Vee =±15V, Rl = 1 kil, inverting circuits only, Te = 25°C,
unless otherwise noted.
Symbol
Parameter
Test Conditions
SR
GBWP
UGBW
Slew Rate
Gain-Bandwidth Product
Unity-Gain Bandwidth
f= 1 MHz
ts
Settling Time (ACL = -1 )
en
Input Voltage Noise Density
in
CL
Input Current Noise Dens~y
Capacitive Load (maximum w/o oscillation)
1430
1430-HR
Min Typ Max Min Typ Max Unit
750
100
60
-
70
85
175
70
100
180
80
100
240
16
200
--
-
10V step/l%
10Vstep/0.l%
10V step/O.Ol%
5Vstep/l%
5V step/O.l %
5V step/O.Ol%
2Vstepl1%
2V step/O.l %
2V step/O.Ol%
f= 1 kHz
f= 1 kHz
-
80
-
100
0.2
-
-
-
-
80
-
-
100
750
100
60
70
85
175
70
100
180
80
100
240
16
0.2
-
-
--
MHz
MHz
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
pAr/Hz
200
-
--
-
NOTES: 1. limits printed in boldface type are guaranteed and 100% production tested. limits in nonna! font are guaranteed but not 100%
production tested.
9-23
VlIlS
nVNHz
pF
III
FAST SETTLING, FET INPUT
OPERATIONAL AMPLIFIER
1430
1+---
ACTUAL SETTLING TIME
RINGING
FINAL VALUE
TAil
j::i;f=~=====::===~::.:..:.::
Figure 3. The Composition of Settling Time
Defining Settling Time
and "ring" as it settles toward the final value. Settling time
includes not only the slew rate but also that portion of the
ringing time in which the peaks exceed the settling time error
band.
The error band is generally expressed as a percentage of the op-amps full scale output (i.e. 0.01 % or 1 mV for
a 10V amplifier). When observing settling time on an oscilloscope the amplifier may appear to have settled because
the ringing has ceased but the observed value is outside the
error band for a few seconds until it drifts within the error
band. This "long tail" phenomenon is often a source of error.
The long tail makes it virtually impossible to calculate settling
time by using slew rate, and ringing characteristics as the
sole factors. Also, knowing the settling time to a given
accuracy (i.e. 0.1 %) is not helpful in extrapolating the settling
time to a higher accuracy, such as 0.01 % and vice versa.
If settling time cannot be extrapolated, calculated,
guessed or ignored, it must be measured. This can be
difficult and misleading if the proper procedures are not
followed precisely. (Figure 4 illustrates the 1430's settling
characteristics using the test circuit shown in Figure 5A).
Settling time is the important specification when handling fast (sub-microsecond rise time), precision (0.1% or
better amplitude accuracy) pulses. Settling time is the total
time required, after the application of an input step (voltage
or current), for a circuit's output to reach and stay within an
error band specified in relation to the output's final value (see
Figure 3).
Settling time cannot be predicted from bandwidth or
slew rate. A step input to the amplifier will cause the output
to slew at its maximum rate toward the final value. When this
value is reached the output will usually overshoot slightly
Measuring Settling Time
It is not possible to obtain 0.1 % or 0.01 % accurate
measurements directly from an oscilloscope looking at the
output waveform. Measuring a 1OV signal, at high sensitivity
for proper resolution, will overdrive the scope's input amplifier such that it's own recovery time will be much longer than
the settling time being measured. Measuring settling time to
0.01 % requires a clipping amplifier to prevent overloading
the oscilloscope's input (Figure 58).
+SV~
INPUT VOLTAGE - 10V STEP
- 30 nsec FALL TIME
,
,
-5V
,
+0.5 MV' ----'---------cO=U-=M-=M::c
y, - - - ---......;.,----,-,,,_- SUMMING POINT -0.5 MV'
r-:_ _-'E='-R"'R""OR"--_ _
---~:\-\
:
:,
\
_____ I
I
-'-./':,
,,
,,
200 ns '-4--
I
MAX
I
'0.01 % Referred to Output
Figure 4.
Figure 5.
143011430-HR Settling TIme
9-24
Test Circuit and Clipping Amplifier
FAST SETTLING, FET INPUT
OPERATIONAL AMPLIFIER
1430
15 pF
TEST SIGNAL
10VSTEP
@ 10KHz
A.U.T.
Rt'
TO CLIPPER AMPLIFIER
OR EMITTER FOLLOWER
SCHOTTKY DIODES
HP 5082-Z835 OR EQUIVALENT
Figure 5A. Test Circuit
The test circuit (Figure 5A) is an excellent method for
fast-settling time measurements. In this circuit Rin and Rfare
matched to Rin' and Rt'. When the Amplifier Under Test
(AUT) settles to ±O.01 % of a 20V step (±2 mV) the settling
point settles to ±1 mV. A FET follower with less than 1 pF
input capacitance (3N128) is used in the clipper amp to
buffer the settling point. The two schottky diodes acting as
limiters on the settling point do not store a charge nor present
much capacitive loading. Therefore, the lag due to capacitance, ~3 pF, in combination with Rf' = Ri' = 1 kn can be as
low as 1 .5 ns. Be sure to use an ideal square wave source
for testing, since a square wave with significant ripple can
unfairly cause an amplifier to look bad.
This method allows you to look directly at the true AUT
output, yet avoids most drawbacks due to the output signal
subtraction from the input signal.
Why not connect the 3N 128 buffer directly to the summing point? Because of feedback capacitance, Ct, and the
(A.U.T.) input capacitance, Cin. Many fast-settling amplifiers give best results when some finite amount of feedback
capacitance is used. The effect of changing Cf can be seen
at the settling point but not at the summing point. In addition,
some good amplifiers have significant input capacitance
dueto "Miilercapacitance" orfeedforward capacitors. In this
case, it is possible to see the true settling only at the settling
point. You can test at the summing point if the result is the
same as at the settling point; but if there is a difference
measure at the settling point.
+15V
O.05~F
-3600 TRIM
FORGAINOF5
9
5.1k
39k
lk
Figure 5B. Clipping Amplifier
9-25
eo
FAST SETTLING, FET INPUT
OPERATIONAL AMPLIFIER
1430
120
""
100
iii'
z
:!!.
80
<
CI
60
0
40
:Z:
20
co.
9
w
co.
0
0
-20
1
10
100
Figure 6_
" "\ '\
An amplifier is of little use in precision work if it's output
for a 400ns pulse rises in 10ns, overshoots 20%, rings for
1OOns, and, due to a tail does not arrive at and remain within
0.01% of the final value for another 600ns. A 1430 will be
within 0.01 % of final value within 200ns.
To operate the 14300r1430-'HR from +85°Cto+125°C,
a 20°C per watt heat sink must be attached. A suggested
device is the Thermalloy Model 6007A· modified by removing the two fins at each end and adding an aluminum 'hold
down bar" (Figure 7). Heat sink compound must be used
between the 1430 and the heat sink.
"
*Thennalloy
2021 West Valley View Lane
Dallas, TX 75234
lk 10k lOOk 1M 10M 100M
FREQUENCY (Hz)
Open-Loop Gain vs Frequency
n-
QQ
~~~
0.093
.
//
~
~
1_09
- /'
~ (2_80) -..,... /
1.25 _ _.,.,
(3.20)
-/
MODIFIED
THERMALLOY MODEL 6oo7A
HEAT SINK
NOTE: Dimensions: in. (em)
Figure 7.
9-26
Heat Sink Assembly
0.37
(0.94)
0.75
(1.90)
"~TELEDYNE
COMPONENTS
1435
OPERATIONAL AMPLIFIER -
HIGH-FREQUENCY, FAST-SETTLING
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The 1435 is an ultra-fast, differential-input operational
amplifier designed for precision amplification of wideband,
complex waveforms with frequency components from DC
to 100 MHz. Such performance is made possible by a
unique design featuring high open-loop gain, flat frequency
response beyond 10kHz, and smooth 6 dB/octave rolloff to
greater than 100 MHz.
Applications of the 1435 are based on using the precision capabilities of a differential-input op amp at higher
frequencies than previously possible. These applications
include video mixers with 20 dB to 40 dB gain, fully-differential-input, and 0.1 % gain stability; peak detectors (and
sample/holds) that can capture 10V, 50 ns pulses to 1%
accuracy and 70 ns pulses to 0.01% accuracy; video AID
and D/A converters; submicrosecond, precision analog
comparators.
The standard 1435 is specified for QOC to +70°C operation. For high-reliability military/aerospace applications, the
1435 High Reliability (HR) version is specified for-55°C to
+125°C operation.
Settling Time to 0.01 % ..................................... 70 ns
Gain Bandwidth Product ................................ 1 GHz
Common-Mode Rejection Ratio ...•..........••... 100 dB
Open-Loop Gain .............................................. 95 dB
Operating Temperature (-HR) •...... -55°C to +125°C
APPLICATIONS
•
•
•
•
•
Radar and Sonar Signal Processing
Microwave Transmitter Modulators
Graphic CRT Displays
Linear Video Mixers
Video ADCs, DACs, S/Hs
PIN CONFIGURATION
PIN
NO.
1
2
3
4
5
6
7
DESIGNATION
PIN
NO.
..,'"
1435
DESIGNATION
OPTIONAL BYPASS CAPACITOR
8
+INPUT
OUTPUT SOURCE
9
COMPENSATION CAPACITOR
10
NC
NC
+VCC
EOSTRIM
EOSTRIM
-INPUT
11
NC
12
13
14
-VCC
OUTPUT SINK
CASE COMMON
@) @) @)@) @) @) @)
1
NC = NO INTERNAL CONNECTION
1043-1
9·27
2
3
4
5
6
7
9
8
BonOMVIEW
14
13
12
11
10
@ @ @@ @ @ @
•
HIGH-FREQUENCY, FAST-SETTLING
OPERATIONAL AMPLIFIER
1435
ABSOLUTE MAXIMUM RATINGS
Vcc
VID
VICM
Supply Voltage ............................................. ±18V
Differential Input Voltage ................................ ±4V
Common-Mode Input Voltage ...................... ±1 OV
Tc
TSTG
DC CHARACTERISTICS:
Operating Temperature Range (Case)
1435 ............................................ O°C to +70°C
1435-HR ................................ -55°C to +125°C
Storage Temperature Range ..... ~5°C to +150°C
(Note 1) Vcc = ±15V, RL = 500n, Tc = 25°C, unless otherwise noted.
1435
Symbol
Parameter
Vos
VosTC
la
la TC
Isc
Ro
Input Offset Voltage
Input Offset Voltage Drift vs Temperature
Input Bias Current
Input Bias Current Drift vs Temperature
Input Offset Current
lnputOffset Current Drift vs Temperature
Open-Loop Vottage Gain
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
Common-Mode Range (DC Linear Operation)
Differential Input Impedance
Common-Mode Input Impedance
Output Vottage Swing
Output Current
Output Short-Circuit Current
Output Resistance (DC Open-Loop)
Vcc
Icc
Supply Vottage Range (Operating)
Quiescent Supply Current
los
10sTC
AVOL
PSRR
CMRR
CMR
liD
llCM
Vo
10
Test Conditions
Average, TMIN to TMAX
Min
-
Average, TMIN to TMAX
-
Average, TMIN to TMAX
80
VCM = ±5V
CMRR~74dB
80
±7
-
-
1435-HR
Typ Max Min Typ Max
±2
±5
±10
±50
±0.3
±2
95
86
100
±8.5
2.5kll2
lMII2
±5
±30
-
±2
±5
±10
±50
±0.3
-
-
-
-
-
80
-
-
-
80
±7
-
-
-
±5
±7
±10
±14
-
-16/+35
-
-
100
-
±12
±15
±25
-
-
±16
±30
-
-
-
±2
95
86
100
±8.5
-
-
-
2.5kll2
1MII2
±5 ±7
±10 ±14
-
-161+3E
-
100
±12 ±15
- ±25
Unit
±5 mV
±25 JlVrC
±30 I1A
±150 nArC
-
±16
±30
IlA
nArC
dB
dB
dB
V
QllpF
QllpF
V
mA
mA
Q
V
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS:
(Note 1) Vce = ±15V, RL = 1 kn, Ce = 2 pF, Te = 25°C, unless otherwise noted.
1435
1435-HR
Symbol
Parameter
Test Conditions
Min
Typ Max Min Typ Max
SA
GBWP
UGBW
Slew Rate
Gain-Bandwidth Product
Unity-Gain Bandwidth
Settling Time (ACL = -1 )
Cc=O
f = 10 MHz, Cc = a
250
700
Cc= a
1OV step/0.025%
10V step/0.01%
5V step/t%
5V step/a. 1%
1V step/1%
1V step/a. 1%
f= 1 kHz
f= 1 kHz
NG > 2, Cc = 3 pF
-
300
1000
150
60
70
25
40
10
20
16
25
ts
en
in
CL
Input Vottage Noise Density
Input Current Noise Density
Capacitive Load (Maximum w/o oscillation)
-
1000
-
-
85
-
60
-
-
250 300
700 1000
- 150
60
- 70
- 25
40
10
20
16
25
1000
-
-
-
75
-
60
-
-
-
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tE!sted. Limits in normal font are guaranteed but not 100%
production tested.
9-28
Unit
V/JlS
MHz
MHz
ns
ns
ns
ns
ns
ns
nVNHz
pANHz
pF
HIGH-FREQUENCY, FAST-SETTLING
OPERATIONAL AMPLIFIER
1435
APPLICATION INFORMATION
Basic Connections and Wiring Techniques
verter, integrator, etc. However, it must be used at a noise
gain of at least 2 (noise gain = 1 + RF/RIN). For example, it
can operate as a gain-of -one inverter (Figure 1), or differential amplifier, but as a non-inverting amplifier, it must have a
gain of at least 2.
Capacitor C1 (shown in Figure 1), is a 2 pF compensation capacitor which must be used to maintain stable operation when noise gain is less than 10.
Resistor R3 connected to the (+) input compensates for
the (-) input bias current. It should be equal to RIN and RF in
parallel. The 1 kil, Eos adjust potentiometer is optional. The
1 IiF bypass capacitor (C2) on pin 1 may be necessary to
prevent oscillation of the output stage when driving capacitive loads.
When operating at the low impedances required by the
1435, care should be taken to include the load provided.by
the feedback resistor when calculating the total load on
amplifier output.
A schematic and suggested physical layout of basic
connections for the 1435 are shown in Figure 1. Illustrated
are wiring techniques recommended to obtain specified high
frequencyltime response from the 1435. The circuit should
be built on a ground plane with minimum length, point-topoint connections, wired directly to the pins of the 1435. If a
socket is necessary, it should be made of Teflon (such as the
Augat model 114-AG-2A). Remember, 1000n and 10 pF
provide a time constant of 10 ns.
The 1435 has a Class A output stage. Pin 2 isa follower
output, while pin 13 is a current sink used to provide
quiescent bias for the follower, as well as sinking load
current for negative output swings. For most applications,
pins 2 and 13 (the output circuit) are connected together.
Stability and Compensation
The 1435 operates in any conventional op-amp circuits,
including the non inverting amplifier, current-to-voltage con-
NOTE:
V
Represents connection to ground plane.
NOTES:
(RF)(R IN ) .
.
1. R3 = - - - bias current compensation.
RF + RIN
2. 1 I'F bypass capacitors should be solid tantalum.
3. Pins 9, 10, 11 = no connection
Figure 1. Suggested Layout and Schematic
9-29
HIGH-FREQUENCY, FAST-SETTLING
OPERATIONAL AMPLIFIER
1435
Operation as a Current-to-Voltage Converter
100
iii' 80
:!!.
z
C
60
D.
40
"
0
9
Z
20
0
0
270
i
o
::t:
;;
1=1~~;':r~~1'80
90 ~
W
D.
D.
~O
100
1G
1k
The 1435 is an optimum choice for a current-to-voltage
converter because of its excellent Eos and los temperature
coefficients (TC). When used with a current output DAC the
required noise gain of ~ is provided by using the output
impedance of the DAC (see Figure 4). The initial input bias
current of the 1435 is compensated by the addition of Rc,
which is equal to the parallel combination of the feedback
resistor and the input (DAC output) impedance. The typical
los TC of 2 nA/oC times the feedback resistor (2.5 kn)
produces 5 J!V1°C of output drift over temperature, and the
typical Eos TC of 5 J!V/oC times a noise gain of 3.1 contributes only 15.5 J!V/oC to the output drift.
Figure 2. Open-Loop Gain and Phase vs Frequency
Operation 'as a Fo"ower
When operated as a follower, the 1435 requires a noise
gain of at least 2 for stability. Figure 3 shows one method of
obtaining a noise gain of 2.
-Vcc +vcc
RC=RFIIRs
NG= 1 +RpRS
3pF
NOTE: ZI = 2.3 pF
II < 30 MHz
1.5 pF, 30 MHz < II < 100 MHz
2300
II < 150 MHz
IFP (10 Vp•p ) = 9 MHz (full·power bandwidth)
NOTES:
I~IIII£I
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1. TC = contributions: EOS TC X NG = 15.5 IJ.Vf'C
lOS TC X RF = 5IJ.Vf'C
2. Average overall output drift- 20.51J.V/oC
Figure 4. The 1435 as a Fast Current-to·Voltage Converter
lG
Figure 3. The 1435 as High Impedance Input Follower
9-30
HIGH-FREQUENCY, FAST-SETILING
OPERATIONAL AMPLIFIER
1435
Settling-Time Measurement
The measurement of amplifier settling time to 0.01%
under 100 ns accuracy requires great care. The 1435's
settling time may be measured using the circuit shown in
Figure 5. The settling-time test point is connected to an
emitter-follower bufferforO.1 % measurement and to a gainof-5 amplifier for 0.01 %. (For a detailed discussion of these
measurementtechniques, see Teledyne Components' Model
1430 data sheet.)
iii 120
!!.
~
100
........
Z
§w
80
II:
60
........
~~
"'- "-
~
I!lo
:::;
Z
i8
40
20
lk
10k
"
~
lOOk
1M
10M
FREQUENCY (Hz)
100M
Figure 6. CMRR VB Frequency
:N~
+VCC
::--...
"''"'\
figureS. Settling-Time Test Circuit
100
lk
10k
lOOk
FREQUENCY (Hz)
Figure 7. PSRR va Frequency
9-31
1M
III
HIGH-FREQUENCY, FAST-SETTLING
OPERATIONAL AMPLIFIER
1435
r
250~--~--+---+---+---+-~~
Ui'
.s
200 ~--~--+w
+
r-+
::;:
i=
CI 150
T
z
:::i
I:w
0.125
(0.318)
100 1-----1-~'-.;£.f------.,.A
I/)
ALUMINUM
HOLD-DOWN BAR
0.40
(1.02)
~ 125
/~
(3:20)
I
,...---~
~0.093
4
6
NOISE GAIN(1 +
8
10
IA
(g::~)
0.093
2
W.230)
II~nn'~
(0.2:1 ~~
o
~
9?'
/0
0.75
12
;4- (~::) _./
~
~~)
(1.90)
:.r-----L-'---'-
1.25 ___--.,,/
(3.20)
-/
Figure 8. Typical Settling Time vs Noise Gain
MODIFIED
THERMALLOY MODEL 6007A
HEAT SINK
CMRRlPSRR vs Frequency
Figure 6 plots CMRR versus frequency, illustrating that
the 1435 is fully differential at video frequencies and is an
excellent choice for differential and non-inverting applications.
Figure 7 plots PSRR versus frequency, and illustrates
the need to bypass the power supplies at video frequencies
(to prevent oscillation).
NOTE: Dimensions: in. (cm)
Figure 9. 143S-HR Heat Sink Assembly
Settling Time vs Noise Gain
The dependency of the 1435's dynamic performance on
circuit gain is shown in Figure 8. Because of the enormous
gain bandwidth ofthe 1435, settling time remains good even
with significant gain.
~~
1435
Operation Above +85°C
In order to operate the 1435-HR from +85°C to +125°C,
it must be used with a 18°CIW heat sink. A suggested heat
sink is the Thermalloy Model 6007A· (modified by removing
thetwofinsat each end and adding the aluminum hold-down
bar, as shown in Figure 10.) Heat-sink compound must be
used between the 1435-H R and the heat sink.
NOTE: Series diodes reduce the effect of
diode capacitance on response.
Figure 10. Input Protection
• To obtain the heat sinks mentioned here, please contact:
Thermalloy
2021 West Valley View Lane
Dallas, TX 75234
9-32
HIGH-FREQUENCY, FAST-SETTLING
OPERATIONAL AMPLIFIER
1435
WARNING
10 k.Q
If -Vee is open, the output will follow +Vee. Depending on
the feedback network, this may cause an input differential
vo~age greater than ±4V, which will degrade the input
transistors. To maximize frequency response, the 1435
DOES NOT have input protection. Therefore, the following
precautions MUST be taken:
Cc
2pF
1000
1. Do not apply +Vee before -Vee.
2. Do not apply voltage to either input (pins 7 and
8) prior to application of ±Vee.
3. Provide input protection per Figure 10.
-15V
+15V
Figure 11. Burn-in Circuit
9-33
..
NOTES
9-34
~"'TELEDYNE
COMPONENTS
1437
OPERATIONAL AMPLIFIER -
WIDE BAND, FAST-SETTLING
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The 1437 hybrid op amp offers versatility in wideband
steady-state and fast-transient applications. It stands out
for speed and predictability, as exemplified by its fast,
smooth settling. The absence of large transients and oscillations in the settling waveform make the 1437 a dependable system element that can resolve settling problems
associated with ADCs, DACs, and sampling circuits.
The 1437 has excellent DC characteristics: ±200 pA
input bias current, 95 dB open-loop gain, and ±0.5 mV input
offset Voltage. The choice of a single external compensation
capacitor ensures a 40 MHz bandwidth at a variety of gains.
True differential inputs ensure superior performance in all
circuit configurations: inverting, non inverting, or differential.
With an attractive price/performance ratio, the 1437 is an
industry-standard for high-speed, high-accuracy signal processing and data acquisition.
The 1437 is packaged in an a-pin TO-99 can and is
specified for O°C to +70°C operation. The 1437 High Reliability (HR) version is specified for -55°C to + 125°C operation.
Gain Bandwidth Product ............................ 350 MHz
Unity Gain Bandwidth •....•....•...•..•....•........... 40 MHz
Settling Time to 0.1% (10V step) .•.......•..••....•.. 85 ns
Output ...............•................................. ±12V, ±24 mA
Small, TO-99 Package
Single External Compensation Capacitor
FET Input
APPLICATIONS
•
•
•
•
•
Current-to-Voltage DACs
Pulse Amplifiers
Radar and Sonar Signal Processing
Graphics CRT Displays
Video ADCs, DACs, and SlHs
PIN CONFIGURATION
PIN
NO.
2
3
4
5
6
7
8
DESIGNATION
OFFSET TRIM
INVERTING INPUT
NONINVERTING INPUT
-Vcc
OFFSET TRIM
OUTPUT
+Vcc
COMPENSATION
BOTTOM VIEW
1044-1
9-35
9
WIDEBAND,FAST-SETTLING
OPERATIONAL AMPLIFIER
1437
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .............................................. ±20V
TSTG Storage Temperature Range ...... -65°C to +150°C
Overall Junction-to-Case Thermal
Differential Input Voltage ............................... ±25V
Resistance (Note 1) .................................. 32°C/W
Common-Mode Input Voltage ....................... ±Vcc
Output Transistor Junction-to-Case Thermal
Operating Temperature Range (Case)
Resistance (Note 2) ................................... 65°C/W
1437 .............................................. O°C to +70°C
1437-HR .................................. -55°C to +125°C
NOTES: 1. Overall thermal resistance during normal operating conditions. Multiply this value by the power dissipation of the entire 1437 to
determine maximum temperature rise case to junction in the hybrid.
2. Individual thermal resistence of the output stage. The 1437 is a Class AS amplifier. To calculate the output transistor temperature rise
case to junction, multiply this figure by the power dissipation of the output transistor. At AC frequencies above 100 Hz, the effective
thermal resistance of the output stage will drop 32.S'CNJ forthe 1437.
eJC
DC CHARACTERISTICS:
(Note 1) Vcc =±15V, RL = 500n, Tc = 25°C, unless otherwise noted.
Test Conditions
1437-HR
Min Typ Max Unit
Parameter
Vas
VosTC
Input Offset Voltage
16
16 TC
Input Bias Current
los
los TC
AvoL
PSRR
Open-Loop Vokage Gain
88
95
-
88
95
-
dB
Power Supply Rejection Ratio
-
76
-
76
-
dB
CMRR
Common-Mode Rejection Ratio
60
78
-
60
78
-
dB
CMR
Common-Mode Range (DC Linear Operation) CMRR~54dB
±10
±12
liD
Differential Input Impedance
llCM
Va
Output Voltage Swing
±10
10
Output Current
±20
±24
Isc
Output Short-Circuit Current
-
±50
Ro
Output Resistance (DC Open-Loop)
-
Input Offset Vo~age Drift vs Temperature
Input Bias Current Drift vs Temperature
Average, T MIN to T MAX
Min
1437
Typ Max
Symbol
-
±0.5
±2
-
±15
-
±200
-
-
±0.5
±2
mV
±15
±50
IJ-V/"C
±200
-
Doubles every 11 'c
Input Offset Current
Average, T MIN to T MAX Doubles every 11 'c
±20
-
Input Offset Current Drift vs Temperature
Average, T MIN to T MAX Doubles every 11 '9
Doubles every 11 'c
VCM = ±8V
-
Common-Mode Input Impedance
Vee
Supply Vokage Range (Operating)
Icc
Quiescent Supply Current
±12
-
1011 113
-
1011 113
-
±12
90
-
±15
±20
±12
±15
-
±20
±10 ±12
-
-
pA
pA
-
V
-
0"113
-
OllpF
-
011 113
-
OllpF
±10 ±12
V
±20
±24
-
±50
-
mA
-
90
-
0
±15
±20
V
±12
±15
mA
±12
-
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100'% production tested. Limits in normal font are guaranteed but not 100'%
production tested.
AC CHARACTERISTICS:
Symbol
Parameter
SA
Slew Rate
(Note 1) Vcc = ±15V, RL = 500n, Cc = 0 pF, Tc = 25°C, unless otherwise noted.
Test Conditions
Min
-
GBWP
Gain-Bandwidth Product
f= 10 MHz
-
UGBW
Unity-Gain Bandwidth
Cc = 27 pF
-
t.
Settling Time (AcL = -1, Cc = 15 pF)
10V step/1%
10Vstep/0.1%
10V step/0.025%
1OV step/O.O";.
Cc=15pF
en
Input VoHage Noise Density
f= 1 kHz
-
1437
1437-HR
Typ Max Min Typ Max Unit
400
225
350
40
-
65
85
150
180
-
10
-
-
-
-
-
400
225
-
350
-
MHz
-
-
40
-
MHz
-
-
65
85
150
180
-
ns
ns
ns
ns
1.20
-
-
-
10
120
-
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100'% production tested. Limits in normal font are guaranteed but not 100'%
production tested.
9-36
V/)lS
V/IJ-s
nV-,'Hz
WIDE BAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1437
APPLICATIONS
3-9pF
The basic connections for the 1437 in the inverting
mode are shown in Figure 1.
2.5 k.Q
""
1437
D/A
""
1437
>''---_-0 VOUT
Figure 3. Current-to-Voltage Converter
Stability and Compensation
NOTES: An
For wide bandwidth applications, the 1437 can achieve
30 MHz bandwidth at 20 dB gain with a 2 pF compensation
capacitor, as shown in Figure 4. The 1437 can operate as a
unity-gain buffer out to 40 MHz bandwidth with 27 pF
compensation (Figure 5). The 1437 is stable without a
compensation capacitor in applications with gains greater
than 30 dB, such as a video amplifier (Figure 6), where the
gain is 70 dB and a compensation capacitor is not needed.
Referto Figure 8 to determine the required compensation for
other gain selections.
Eos trim potentiometer is optional.
Power supplies should be bypassed with
1 J.lF tantalum and 0.01 J.lF ceramic capacitors.
Use of a finned heat sink is recommended.
Figure 1. Normal Inverting Operation
Data Conversion
Fast settling time, low bias and offset currents, and
modest power consumption make the 1437 an excellent
choice for use in data conversion applications. Figure 2
illustrates the 1437 as a fast-settling input buffer to a 12-bit
AID converter.
10k!!
""
1 k.Q
1437
IN
12-BIT
Figure 4. Inverting Gain of 10
AID
""
1437
""
Figure 2. Fast-Settling Buffer
1437
Figure 3 demonstrates the 1437 used as a current-tovoltage converter for a 12-bit DAC.
20pF
2000
Figure 5. 40 MHz Unity-Gain Buffer
9-37
WIDEBAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1437
'.I~~~!~~~GV
.,~
.... "-~"'i"" .... 1........
1437
INPUT
.."
3.45kQ
OUTPUT ==~
2OmV/em
FV
2OmV/D1V
.... ···!-··l-.. _.•..
50n
5V/D1V
-cv
•
SETTLING
1OOllS/Cm
Figure 6. Video Amplifier
.. eo ...
Figure 7b. Settling-Time Graph
Settling-Time Measurements
100
A typical settling-time measurement circuit for the 1437
is shown in Figure 7a; a photograph of a typical measurement is shown in Figure 7b. Figure 11 presents a graph of
settling time to either 100 mV or 10 mV versus the output
step size.
80
60
m
CF (1-5 pF)
~
z
40
:0(
Cl
20
0
1k
10k
0.1M
1M
10M
100M
FREQUENCY (Hz)
Figure 8. Open-Loop Gain and Phase vs Frequency
2kQ
470n
-15V hN'V"'"-"-'M"-""'
2kQ
VERROR
TO SCOPE
...---=.:..::.='"'-47-0-n.... CL.. 10 pF
L-~-4.-AJ'IfIv--l+ 15V
6.5
N' 6.0
a:~ 5.5
w_ 5.0
~F 4.5
~o 4.0
..:.i 3.5
SO 3.0
2.5
ID 2.0
1.5
u.::i:
NOTES: All resistors 1%, all capacitors 10%. Refer to 1430
data sheet for discussion on settling-time measu remen!.
All capacitors in !1F unless otherwise indicated.
~
.......
1
.......
2
......
~
4
8
16
32
INVERTING GAIN (dB)
64
Figure 7a. Typical Settling-Time Test Circuit
Figure 9. Full-Power Bandwidth vs Inverting Gain
9-38
WIDE BAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1437
~
~
~
~
c(
a:
;:
~
VI
420
400
380
360
340
320
300
280
260
240
220
200
/
./
./
'"
/
'"
/
"
---
Z
o
90
tiw
"
~~70
a:!5
w~
co
0-
~~ 50
4
8
16
INVERTING GAIN (dB)
32
::;;
64
""
"
§l
2
8
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 10. Slew Rate vs Inverting Gai n
Figure 13. CMRR vs Frequency
+10
~
w
+5
Cl
r----
V
_ ...r:.r:.
c(
!:i
,
0
~
I:;)
Il.
-0
I-
Z
N
ti
~
w
...,
I
w~
a:!5
0
-10
80
>~
~
-'0
'00
Il.j::
Il.c(
~"'o
ijla:
a:
w
;:
~~
:;)
100
0
60
0
Il.
100
40
60
80
100 120
SETTLING TIME (ns)
140
1k
'"
10k
100k
FREQUENCY (Hz)
Figure 14. PSRR vs Frequency
Figure 11. Settling Time vs Output Voltage Change
---;;:--1a: a:
+
--..:;;- 4 I--I---+-;:-''d--
z
~
~
z
2 i---t----1---+---+--t-----"""t---''''1
o
2
4
6
8
10
12
14
CAPACITANCE COMPENSATION (pF)
Figure 12. Noise Gain vs Cc for 16% Overshoot
9-39
1M
NOTES
9-40
~"'TELEDYNE
COMPONENTS
1438
OPERATIONAL AMPLIFIER -
WIDEBAND, FAST-SETTLING
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The 1438 hybrid operational amplifier offers versatility
in wideband steady-state and fast-transient applications.
The 1438 stands out for speed and predictability, as
exemplified by its fast, smooth settling. The absence of
large transients and oscillations in the settling waveform
make it a dependable system element that can resolve
settling problems associated with ADCs, DACs, and
sampling circuits.
The 1438 has excellent DC characteristics: t200 pA
input bias current, 93 dB open-loop gain, and to.5 mV
input offset voltage. The choice of a single external compensation capacitor is all that is needed to ensure a 40
MHz bandwidth at a variety of gains. True differential inputs ensure superior performance in all circuit configurations, whether inverting, noninverting, or differential. With
an attractive price/performance ratio, the 1438 is an industry standard for high-speed, high-accuracy signal processing and data acquisition.
The 1438 is packaged in a 12-pin TO-8 can and is
specified for O°C to +70°C operation. The High Reliability
(-HRl version is specified for -55°C to +125°C operation.
Gain-Bandwidth Product ........................... 350 MHz
Unity Gain Bandwidth ....•...................•......... 40 MHz
Settling Time to 0.1% (10V step) •.••.•....•..•.•..•.. S5 ns
Output ................................................. t12V, t60 mA
Small, TO-S Package
Single External Compensation Capacitor
FET Input
APPLICATIONS
•
•
•
•
•
Current-to-Voltage DACs
Pulse Amplifiers
Radar and Sonar Signal Processing
Graphics CRT Displays
Video ADCs, DACs, and SlHs
PIN CONFIGURATION
PIN
NO.
1
2
3
4
5
6
NC
1045-1
DESIGNATION
PIN
NO.
NC
OFFSET TRIM
INVERTING INPUT
NONINVERTING INPUT
12
11
10
9
-VCC
NC
7
B
DESIGNATION
NC
COMPENSATION
+VCC
OUTPUT
OFFSET TRIM
NC
=NO INTERNAL CONNECTION
BOTTOM VIEW
9-41
9
WIDEBAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1438
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range ...... --65°C to + 150°C
Supply Voltage .............................................. ±20V
Overall Junction-to-Case Thermal
Differential Input Voltage ............................... ±25V
Resistance (Note 1) ................................... 19°C/W
Common-Mode Input Voltage ....................... ±Vee
Output Transistor Junction-to-Case Thermal
Operating Temperature Range (Case)
Resistance (Note 2) ................................... 35°CIW
1438 .............................................. O°C to +70°C
1438-HR .................................. -55°C to +125°C
NOTES: 1. Overall thermal resistance during normal operating conditions. Multiply this value by the power dissipation of the entire 1438 to
determine maximum temperature rise case to junction in the hybrid.
2. Individual thermal resistance of the output stage. The 1438 is a Class AB amplifier. To calculate the output transistor temperature rise
case to junction, multiply this figure by the power dissipation of the output transistor. At AC frequencies above 100 Hz, the effective
thermal resistance of the output stage will drop 32.soCIW for the 1438.
DC CHARACTERISTICS:
-
(Note 1) Vee = ±15V, RL = 200>2, T e = 25°C, unless otherwise noted.
Symbol
Parameter
Vas
Input Offset Voltage
Vas TC
Input Offset Voltage Drift vs Temperature
18
Input Bias Current
18 TC
Input Bias Current Drift vs Temperature
los
Input Offset Current
los TC
Input Offset Current Drift vs Temperature
AvoL
PSRR
Open-Loop Voltage Gain
CMRR
Common-Mode Rejection Ratio
CMR
Test Conditions
Average, T MIN to T MAX
Average, T MIN to T MAX
Average, T MIN to T MAX
Power Supply Rejection Ratio
VCM = ±8V
Common-Mode Range (DC Linear Operation) CMRR;:> 54 dB
Min
-
1438
Typ Max
±0.5
±2
±15
-
±200
60
78
±10
±12
Differential Input Impedance
-
10"113
Common-Mode Input Impedance
-
10"113
Vo
Output Voltage Swing
±10
±12
10
Output Current
±50
±60
Isc
Output Short-Circuit Current
Ro
Output Resistance (DC Open-Loop)
Supply Voltage Range (Operating)
Quiescent Supply Current
±0.5
±2
mV
±15
±50
J.l.Vre
-
±200
-
pA
±20
- ±20 pA
Doubles every 11°e Doubles every 11°e 86
93
86
93
dB
dB
76
76
-
ZIO
Icc
Unit
-
Doubles every 11°C Doubles every 11°C -
ZICM
Vee
1438-HR
Min Typ Max
±12
-
±125
90
-
-
±15
±20
±12
±15
60
78
±10
±12
-
0"113
0"113
±10
±12
±50
±60
±12
-
±125
90
-
dB
V
OllpF
OllpF
V
mA
mA
0
±15
±20
V
±12
±15
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS:
Symbol
Parameter
SR
Slew Rate
(Note 1) Vee = ±15V, RL = 2000, Ce = 0 pF, Te = 25°C, unless otherwise noted.
Test Conditions
Cc =15 pF
Min
1438-HR
1438
Typ Max Min Typ Max
-
400
225
GBWP
Gain-Bandwidth Product
f= 10 MHz
-
350
UGBW
Unity-Gain Bandwidth
Cc= 27 pF
40
ts
Settling Time (ACL = -1, Cc = 15 pF)
10V step/l %
10V step/O.l%
1OV step/0.025%
10V step/O.Ol%
-
en
Input Voltage Noise Density
f= 1 kHz
65
85
150
180
10
-
-
120
-
-
-
-
400
225
350
40
65
85
150
180
10
-
120
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-42
Unit
V/Il S
V/IlS
MHz
MHz
ns
ns
ns
ns
nV/"Hz
WIDEBAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1438
APPLICATIONS
3-9pF
Basic connections for the 1438 in the normal inverting
mode are shown in Figure 1.
2.5 kn
1438
~'"
D/A
lOUT
>=:...--....--0 VOUT
Figure 3. Current-to-Voltage Converter
1438
Stability and Compensation
For wide bandwidth applications, the 1438 can achieve
30 MHz bandwidth at 20 dB gain with a 2 pF compensation
capacitor, as shown in Figure 4. The 1438 can operate as a
unity-gain buffer out to 40 MHz bandwidth with 27 pF
compensation (Figure 5). The 1438 is stable without a
compensation capacitor in applications with gains greater
than 30 dB, such as a video amplifier (Figure 6), where the
gain is 70 dB and a compensation capacitor is not needed.
Referto Figure 8 to determine the required compensation for
other gain selections.
NOTES: An E05 trim potentiometer is optional.
Power supplies should be bypassed with
1 I1F tantalum and 0.01 I1F ceramic capacitors.
Use of a finned heat sink is recommended.
Figure 1. Normal Inverting Operation
Data Conversion
10kn
Fast settling time, low bias and offset currents, and
modest power consumption make the 1438 an excellent
choice for use in data conversion applications. Figure 2
illustrates the 1438 as a fast-settling input buffer to a 12-bit
AID converter.
1 kn
~'"
1438
1 k.Q
I!!:J
Figure 4. Inverting Gain of 10
...
I-
IN
12-BIT
AID
1438
~'"
:J
o
~'"
1438
..J
~
CJ
is
27pF
VOUT
Figure 2. Fast-SeWing Buffer
Figure 3 demonstrates the 1438 used as a current-tovoltage converter for a 12-bit DAC.
20pF
200n
Figure 5. 40 MHz Unity-Gain Buffer
9-43
9
WIDEBAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1438
J··......
........ ~f .. ·i ............... .. wINlOW
..,~
1438
3.45 k.Q
-4N
FV
2OmVIOW
50n
SETTUNG
.. 80 ...
100na{cm
TIME ZERO
Figure 6. Video Amplifier
Figure 7b. Settling-Time Graph
Settling-Time Measurements
A typical settling-time measurement circuit for the 1438
is shown in Figure 7a; a photograph of a typical measurement is shown in Figure 7b. Figure 11 presents a graph of
settling time to either 100 mV or 10 mV versus the output
step size.
100
i:!!.
80
90
60
180 ~
w
UJ
A-
iD
z
:!!.
40
:a:CJ
20
..,~
0
1438
lk
10k
O.lM
1M
10M
FREQUENCY (Hz)
100M
Figure 8. Open-loop Gain and Phase va Frequency
2k.Q
4700
-15V hMI'--......-'I!If--'
2k.Q
VERROR
TO SCOPE
..--..::..::="-47-0-n..... Cl.;10 pF
6.5
... 6.0
a:~ 5.5
w_ 5.0
~j!: 4.5
tl.0 4.0
...:.§ 3.5
03.0
u..~ 2.5
Ie 2.0
1.5
..15V
HP5082-2811
(OREQUIV)
5
NOTES: All resistors 1%, all capacitors 10%. Refer to 1430
data sheet for discussion on settling-time measurement.
All capacitors in I1F unless otherwise indicated.
-........
1
2
4
8
16
32
INVERTING GAIN (dB)
64
Figure 9. Full-Power Bandwidth va Inverting Gain
Figure 7a. Typical Settling-Time Test Circuit
9·44
WIDEBAND, FAST-SETTLING
OPERATIONAL AMPLIFIER
1438
~
420
400
I--
~
~ 340
I!:! 320
«
, ./
300
260
~ 240
90
Q
/
13w
V
w~
CO
OJ:
I'
./
~~
III 220
4
8
16
INVERTING GAIN (dB)
32
SO
64
'"
'\
!i:;;
200
2
"
~~70
a:'lj
./
a: 280
==
Z
.."
380
360
8
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 10. Slew Rate vs Inverting Gain
Figure 13. CMRR vs Frequency
+10
€
w
+5
CJ
«
~
g
Z
0
V ;1
r--- 'r-....<§>
~
I
~~ 80
~!
0
I:::l
...
-'0
~~
ijla:
a:
w
'\ "'q, -~,{o
-6
I:::l
100
1=
0
w
~~
0
-10
60
==
~
100
40
60
80
100 120
SETTLING TIME (ns)
140
'" "
1k
10k
100k
FREQUENCY (Hz)
Figure 14. PSRR vs Frequency
Figure 11. Settling Time vs Output Voltage Change
........... 6
...1-
a::j:'
"-'"
z"
4
'i:
CJ
W
III
6z
2
o
2
4
6
8
10
12
14
CAPACITANCE COMPENSATION (pF)
Figure 12. Noise Gain vs Cc for 16% Overshoot
9-45
1M
NOTES
9-46
~"'TELEDYNE
COMPONENTS
1443
OPERATIONAL AMPLIFIER - FAST-SETTLING,
FULLY-DIFFERENTIAL, FET-INPUT
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The 1443's combination of high speed, wide bandwidth, excellent DC characteristics, and low-gain stability
places it at the forefront of high-performance operational
amplifiers. Its 2 GHz gain-bandwidth product, 1200 V/IlS
slew rate (when compensated for unity gain), and 130 ns
settling time clearly make it an outstanding high-speed
device. It has been carefully engineered to eliminate the
low-gain stability problems that have historically plagued
high-speed op amps such as the 883554. For example, as
a unity-gain follower with a 54 pF capacitive load, the 1443
has a small signal (3 dB) bandwidth of 120 MHz, yet still
has 35° of phase margin, without using exotic circuit techniques.
The 1443 has a fully-differential FET input followed by
a bipolar gain stage that, together, produce excellent DC
characteristics. Common-mode rejection ratio (CMRR) is
80 dB (minimum). Offset voltage and bias current are
guaranteed less than ±3 mV and -50 pA, respectively.
Open-loop gain is 100 dB (minimum). External compensation with a single capacitor allows users to tailor 1443
performance for different applications.
The 1443 is packaged in an a-pin TO-3 can and is
specified for O°C to +70°C operation. The 1443 High Reliability (HR) version is specified for -55°C to +125°C operation.
Gain-Bandwidth Product .......................... 2000 MHz
Unity-Gain Bandwidth .................................. 80 MHz
Slew Rate @ ACL =-1 ............................... 1200 VlIlS
Settling Time to 0.01% (10V step) •.••.••.••••••••. 130 ns
Open Loop Gain ............................................ 110 dB
Output.. .....•.•...••....•.•..••.•..•..•..•••...•••. ±13V, ±130 mA
Excellent Low Gain Stability
APPLICATIONS
•
•
•
•
•
•
Video Instrumentation
High-Speed Follower
Low Error Current Integrator
Radar
Video Frequency Filters
Video Line Driver
PIN CONFIGURATION
PIN
NO.
DESIGNATION
OUTPUT
2
3
4
5
6
7
8
+Vcc
COMPENSATION
EOSTRIM
-INPUT
+INPUT
-Vcc
EOSTRIM
BOTTOM VIEW
1046-1
9·47
9
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
ABSOLUTE MAXIMUM RATINGS
Vee
VID
VleM
Te
T STG
Supply Voltage .............................................. ±18V
Differential Input Voltage ............................... ±25V
Common-Mode Input Voltage ....................... ±Vee
Operating Temperature Range (Case)
1443 .............................................. O°C to +70°C
1443-HR .................................. -55°C to +125°C
Storage Temperature Range ...... -65°C to + 150°C
DC CHARACTERISTICS:
(Note 1) Vee
=±15V, RL = 1 kn, Te =25°C, unless otherwise noted.
1443
Symbol
Parameter
Test Conditions
Vos
Input Offset Voltage
VosTC
Input Offset Voltage Drift vs Temperature
18
Input Bias Current
18 TC
Input Bias Current Drift vs Temperature
Average, TMIN to TMAX
1443-HR
Min
Typ
Max Min Typ
-
±1
±3
±25
-
±10
±50
-
-
los
Input Offset Current
Input Offset Current Drift vs Temperature
AvoL
PSRR
Open-Loop Voltage Gain
Power Supply Rejection Ratio
70
90
CMRR
Common-Mode Rejection Ratio
80
100
±7
±9
-
1011 11
-
1011 11
-
±10.5 ±13
-
liD
Differential Input Impedance
Common-Mode Input Impedance
Va
Output Voltage Swing
10
Output Current
Isc
Output Short-Circuit Current
Ro
±3
mV
±25
±75
,,"v/"e
±10
±50
±5
-
-
±5
Average, T MIN to TMAX Doubles every 11 °e Doubles every 11 °e
100 110
100 110
RL = 1000
-
-
VCM = ±5V
Common-Mode Range (DC Linear Operation) CMRR ~ 74 dB
llCM
Max Unit
±1
Average, TMIN to TMAX Doubles every 11 °e Doubles every 11°C
10sTC
CMR
-
RL= 1000
±100 ±130
-
±160
-
Output Resistance (DC Open·Loop)
-
200
-
Vcc
Supply Voltage Range (Operating)
±12
±15
±18
Icc
Quiescent Supply Current
±45
±55
(Note 2)
-
-
pA
pA
dB
dB
70
90
80
100
±7
±9
V
-
-
1011 113
-
OllpF
±10.5 ±13
-
V
±100 ±130
rnA
±160
-
200
-
0
1011 113
-
±12 ±15
-
±45
dB
OllpF
mA
±18
V
±55
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
2. The 1443 cannot withstand a continuous short·circuit to ground.
AC CHARACTERISTICS:
(Note 1) Vee
=±15V, RL = 1 kn, Ce =short, Te =25°C, unless otherwise noted.
1443
Symbol
Parameter
Test Conditions
Min
Typ
SR
GBWP
Slew Rate
RL = 1000, ACL=-l
f = 100 kHz, RL = 2000,
Cc = 0 pF, f = 1 MHz,
RL = 2000, Cc = 10 pF
900
1200
90
2000
130
-
80
-
50
80
130
Gain-Bandwidth Product
UGBW
Unity-Gain Bandwidth
ts
Settling Time (ACL = -1 )
10Vstep/l%
10Vstep/0.l%
10V step/O.Ol%
en
Input Voltage Noise Density
f = 1 kHz
CL
Capacitive Load (maximum w/o oscillation) RL = 1000, ACL=-1
-
-
15
>300
1443-HR
Max
-
Min Typ
900 1200
90
2000
130
-
-
80
-
-
50
80
130
-
-
165
-
-
-
15
>300
Max Unit
-
V/flS
MHz
MHz
-
MHz
165
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-48
ns
ns
ns
nVNHz
pF
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
40
100
RL=200n
90
80 ~O,_r- ~r=OPEN
I
70
I'-..
A'"""!\
I
iii' 60 ~
/ Cc=
!I
~ 50
10pF ~
z 40
c =
~
~
\
Cl 30
OR
........:: ~ I'....: 'r'I
20
V
~
10
~
~
o ./
Cc= SHORT
-10
lOOk 500k 2M 5M 20M 50M 200M
FREQUENCY (Hz)
/
L
r-d
«
Is'
r-....
35
0
109>
20 ~
30 i!:
40 ~
50 ~
60 W
70 ~
80
90
30
o
-10
lOOk
Figure 2.
~
i3
~
500k
lka00_
,
--
--.. 'I"
Ii
/Iii
'1fl
~
~
«
Cl
10
5
0
,,-/'i.
Figure 4.
o
!
a
CC=SHORT
RL=oo
r-
2050200
Figure 5.
18
16
N
J: 14
~
20M
\
>-
60
CO 50
OJ:: 40
=i!~ 30
~
20
::i
10
~ 10
~ 8
o
2k 20k 200k 2M 20M 200M
FREQUENCY (Hz)
Figure 6.
CMRR vs Frequency
9-49
\
'""-
~ 6
4
2
IE
0
PSRR VB Frequency
\
~12
Figure 3.
2k 20k 200k 2M
FREQUENCY (Hz)
NOTE: Good PSRR vs frequency means smaller
supply bypasses can be used 10 suppress
supply nOise feedthrough.
80
a
!
~
iE
\'"
o
CC=SHORT
RL =00
1
30Z
40
-10
90eL
110
50 200
/I
l
10
20
Gain and Phase vs Frequency lor Variable Cl
120
110
100
90
80
70
60
50
40
30
20
10
Gain and Phase VB Frequency for Variable Rl
-10
" "-VI
/,
[)(
o
lOOpF- ~
50
54pF
~ I- 54pF 60
20pF
~
20pF
-5 -iOpF
70
~10pF
./~
-10
80
J--- ~ lOOpF
-15
90
1
2
5 10 20
so 100 200 500
FREQUENCY (MHz)
~
2M 5M 20M 50M 200M
FREQUENCY (Hz)
1:
h
11 III
L I rJ
.\
\
~~
o
15
z
wiii' 70
15
~
10 'iii
20
30 z
40
icon
50 ~
lloon 60 ~
70 ~
80 J:
~-
"'- ~
20
iii'
iE
"
~
25
Figure 1. Gain and Phase VB Frequency for Variable Compensation
100
90 Cc = SHORT
80
70
iii' 60
~ 50 b.......
z 40
i"~ 30
20 I-- ~ loon ........
10 I-- r-- 200nk
RL=2oon
~C=SHORT
o
I'-....
10
20
30
INVERTING GAIN (dB)
40
Utilizable Full·Power Bandwidth
•
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
APPLICATIONS INFORMATION
Compensation
The 1443's design allows users to tailor its compensation, and thereby its performance, to suit different applications. The total effective compensation is an internal 5
pF capacitor in series with whatever capacitor is placed
between the compensation input (pin 3) and the. output
(pin 1).
To minimize low frequency «1 MHz) slewing error and
maximize bandwidth for higher gains (>30 dB), the external
compensation capacitance should range from 0 pF (open)
to 5 pF. For best transient response at lower gains, values
greater than 5 pF are recommended. Above approxima~ely
15 pF, a short is recommended in lieu of a larger capacitor.
The exact value of compensation depends on how much
ringing and overshoot an application allows. Most low-gain
applications will achieve best overall results by shorting pin
1 to pin 3.
Following selection of a compensation capacitor (Ce), a
feedback capacitor (CFB) must be selected to properly
compensate for input capacitance:
that noise gain is the multiple of amplifier input noise which
appears at the amplifier output. In case of low CC, CFB may
be increased to provide extra phase lead. The choice of CFB
is best made on the basis of permissible overshoot after Cc
has been chosen on the basis of gain.
Bypassing
The traditional practice of decoupling power supply
lines with bypass capacitors is necessary to prevent highfrequency oscillations resulting from power supply lead
inductance and parasitic capacitance. Unfortunately, the
bypass capacitor and lead inductance form a tank circuit
that can ring when a step change in the op-amp output forces
a current pulse from the supply. In many cases, adding a
dissipative element (a resistor) will damp the ringing; its
exact value is not critical, but its presence is.
CFB = 2 pF/(NG-1),
where NG = noise gain.
Noise gain is defined as 1/~, where ~ is equal to the
fraction of the output signal that is fed back to the input. Note
Figure 8.
Follower Configuration
+Vcc
3
2
1
111FT
-=
in
:!!.
z
:cc
~
-2
I
-3
L
-4
J
Cl
-6
-6
49.9kn
140
\
-1
>--+-eo
160
1\
0
2
~V"
-7
V
120
"tI
80
20
o
-9
-10 00•1 0.2 0.5 1 2
NOTE: ll1F or larger tantalum supply bypass capacitors
are recommended for fast-settling applications.
Figure 7.
5 1020 50100
9)()
FREQUENCY (MHz)
Typical Connection
Figure 9.
9-50
:c1/1
:~
-3
-VCC
i
100 ~
Frequency Response (As a Follower)
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
Follower
Differential Amplifier
When used as a unity-gain follower (Figure 8), the 1443
has a 3 dB bandwidth of 120 MHz with only 1 dB of peaking,
as shown in Figure 9. Pulse response in this configuration is
shown in Figure 10.
With fully-differential capabilities, the 1443 lends itselfto
many system configurations. Figure 12 shows a Iypical
configuration for the 1443 as a wideband (approximately
15 MHz) differential amplifier with 20 dB gain.
Unity-Gain Inverter
As a unity-gain inverter (Figure 11), the 1443 has a
typical 3 dB bandwidth of 60 MHz. It will settle quickly even
with loads of CL = 100 pF and RL = 1oon, yet will not oscillate
if RIN is open.
~'"
1443
Figure 12.
Wideband Differential Amplifier
High-Speed Coaxial Driver
Figure 10.
Figure 13 shows the 1443 being used as a high-speed
coaxial line driver. The 1443 can drive a 50n cable to ±5V
with 50Q terminating resistors at both ends to minimize
reflections. Using 1% termination resistors and 50Q line,
ghosts are attenuated at least 77 dB. Without the series 50n
resistor at the amplifier output, ghosts may only be attenuated by 38 dB.
Follower Pulse Response
CFB
1 pF
C FB
2pF
ei
1 k!l
499!l
ei
eo
CL
~'"
49.9!l
1443
:-
Figure 11.
:-
Figure 13.
Unity-Gain Inverter
9-51
High-Speed Coaxial Driver
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
HIGH-FREQUENCY
TROUBLESHOOTING TECHNIQUES
Check for op-amp oscillations at zero volt output and at
several additional output points in each polarity. You will
often find that oscillations exist at one or two points in the
circuits' output range. These might be observed only as
unexplained perturbations on the output (they may not
appear as bursts) due to envelope detection, as previously
discussed.
Parasitic Oscillations
With VH F operational amplifiers like the 1443, it is not
enough to only be concerned with stability problems due to
loop closure. Of equal concern (and often times more
annoying) are oscillations due to parasitics. Parasitic oscillations are apt to arise in VHF op-amp circuits in which lead
lengths are long (>1/2 inch), or loop areas are large (>1
cm 2) at the summing junction, feedback capacitor, power
supply pins, or ground-return paths (from bypass capacitors
or the amplifier case).
For the 1443, these oscillations may contain frequencies up to 0.5 GHz. Therefore, you cannot always count on
seeing them with an oscilloscope. When parasitic oscillation
occurs, it often appears as a DC offset because circuit
conductance nonlinearities detect its RF envelope. If what
appears to be a DC offset is noisy and erratic, or responsive
to the placement of your finger or a test probe, parasitic
oscillations may be the problem.
Parasitic oscillations are also likely if there is any significant lead length separating the amplifier output from its
load capacitance. The lead inductance and load capacitance form a series LC circuit that looks like a larger and
larger capacitor as it approaches resonant frequency from
below.
Even lead lengths associated with attaching an oscilloscope probe can cause problems. For a typical scope
probe, with the ground attached 10 cm from the measurement point, the ground lead and probe form a series LC
circuit of approximately 100 nH and 12 pF. At 100 MHz
band-edge for the 1443, the apparent probe capacitance
will dOUble. In parallel with already-existing circuit capacitances, this 24 pF may be enough to cause oscillation. A
good practice is to wrap the ground lead around the probe
tip. An even better practice is to use a probe socket
(Tektronix 131-0258-00) installed in the circuit, with careful
choice of the ground return route.
Semiconductor capacitances and bandwidths are
nonlinearly-dependent on voltage and current. Devices that
oscillate at one voltage level may not oscillate at another.
The Finger as an Analog Development Tool
In 15V systems, the finger can be a useful investigative
tool, if thoughtfully applied. It can couple signals in and out
and can also be used as a load. A well-Iaid-out RF op-amp
circuit will be only slightly affected by a light touch. Dramatic
changes reveal a sensitive point! Check a circuit by touching
the amplifier case, the supply rails (carefully), ground, control knobs, chassis parts, etc. If things change markedly
when you touch these a~eas, parasitics may be the problem.
Other Considerations
Problems commonly associated with video amplifiers
are naturally present in VHF circuits. Therefore, proper
compensation of input capacitance by CFB cannot be ignored. Nor can the impedance (inductance) of the ground
return paths (though use of a ground-plane is helpful, it is
no panacea).
Thermal Considerations
The 1443 has internal current limiting but can only
withstand an output short to ground if, during the short, the
output current is negative as often as positive during each
100 ms period. It is not short-circuit-proof under all conditions. Maximum continuous junction temperature should
be kept below +150°C.
The case-to-ambient thermal resistance of the TO-3
package is eCA = 35°CIW. For the two output transistors,
eJC is 95°CIW.With a 20 Vp_p output sinusoid, the effective
eJC of these two transistors is 65°C/W. A heat sink is
required above +75°C ambient (+85°C for sinusoidal output)
if a 200n load is used. With a 100n load, a heat sink is
required above +4QOC ambient (+50°C for sinusoidal output).
9-52
FAST-SETTLING, FULLY-DIFFERENTIAL
FET-INPUT OPERATIONAL AMPLIFIER
1443
130
_120
()
~110
w
§
100
!;(
90
rr
w 80
Q.
:;; 70
I!! 60
50
~2.5
ACSINE
,
W~
/
10<100 mA
Z
Q
./'
/"
/
~
!;( 2.01--"0,;0--=1-----+----1
DC
Q.
iii
III
/'
c
~
'0 <1oomA
100
150
LOAD RESISTANCE (ill
~
200
15
.
1.0'------'-----'-------'
50
100
150
LOAD RESISTANCE (ill
200
Figure 15. Worst-Case Power Dissipation vs Load Resistance
Figure 14. Maximum Allowable Case Temperature va Load
Resistance With Worst-Case Power Dissipation
9·53
NOTES
9-54
~"'TELEDYNE
COMPONENTS
1460
OPERATIONAL AMPLIFIER -
HIGH SPEED, VMOS OUTPUT
FEATURES
•
•
•
•
•
•
GENERAL DESCRIPTION
Output .•..•....•...••...•....•........................ ±31V, ±2oo rnA
Gain-Bandwidth Product ................................. 1 GHz
Slew Rate ................................................... 300V/J..LSec
VMOS Output Stage
No SOA Restrictions
Fully Differential Input
The 1460 heralds a new era in high power, wideband
operational amplifiers. Designed for ATE signal amplification and pin driving, the 1460 surpasses the competition in
speed (1 GHz gain bandwidth product, 300V/Ilsec slew
rate) and in output capability (full ±31V, ±200 mA output).
The 1460 is a fully differential input, single-ended output
device with internal current limiting and external compensation. A single capacitor allows users to tailor 1460 performance to different applications.
The 1460 is ideal for high speed, high gain applications that require a ±30V, high current output. It is optimized for gains greater than five, making it a superb choice
for either analog or digital signal amplification at video
frequencies. Secondary breakdown problems associated
with most power op amps are virtually eliminated in the
1460 through the use of a unique VMOS output stage. The
output voltage and current are limited only by power dissipation and not by safe operating area curves. For any
application in which the amplifier will ,be dissipating more
than one watt of power, an external heat sink must be
used. The thermal resistance of the 1460 is 20°C/watt
(9Jc) and 50°C/watt (9JA)' Junction temperatures should
not exceed 150°C for normal operation or 200°C for a
short-circuit condition.
The 1460 is packaged in an 8-pin TO-3 can. The
standard unit is specified for O°C to +70°C operation. The
1460 High Reliability (HR) version is specified for -55°C to
+125°C operation.
APPLICATIONS
•
•
•
•
Video Amplifiers
Video Yoke Drivers
ATE Pin Drivers
Driving Inductive and Capacitive Loads
PIN CONFIGURATION
PIN
NO.
DESIGNATION
OUTPUT
2
OFFSET ADJUST
3
4
5
6
7
8
+VCC
+IN
-IN
-Vec
COMPENSATION
COMPENSATION/OFFSET ADJUST
BOTTOM VIEW
1047·1
9-55
9
HIGH SPEED, VMOS OUTPUT
OPERATIONAL AMPLIFIER
1460
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .............................................. ±40V
Differential Input Voltage ................................. ±6V
Common-Mode Input Voltage ............................... .
............................................. +Vee to (+Vee - 60V)
DC CHARACTERISTICS:
TSTG
Operating Temperature Range (Case)
1460 .............................................. O°C to +70°C
1460-HR .................................. -55°C to +125°C
Storage Temperature Range ...... -65°C to +150°C
(Note 1) Vee = ±36V, RL = 10 k!l, Te = 25°C, unless otherwise noted.
1460
Parameter
Test Conditions
Vos
VosTC
16
16 TC
llCM
Vo
10
Isc
Ro
Input Offset Voltage
Input Offset Voltage Drift vs Temperature
Input Bias Current
Input Bias Current Drift vs Temperature
Input Offset Current
Input Offset Current Drift vs Temperature
Open-Loop Voltage Gain
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
Common-Mode Range (DC Linear Operation)
DHferentiallnput Impedance
Common-Mode Input Impedance
Output Voltage Swing
Output Current
Output Short-Circuit Current
Output Resistance (DC Open-Loop)
Vcc
Icc
Supply Voltage Range (Operating)
Quiescent Supply Current
±1
±5 mV
±10 ±50 llV/oC
±5
±15 IlA
Average, TMIN to T MAX - ±50 ±150 nAloC
- ±0.3 ±1.5 IJ.A
nAloC
±3
Average, T MIN to T MAX 80
80
92
dB
RL = 2000
75
75 100
- dB
70
70
dB
VCM = -18V1+30V
85
CMRR ~64 dB
-201+32 -221+34
-201+3 221+34
V
OllpF
7.Sk113
- 7.Sk113C - lMII6 OllpF
- lMII6 ±30 ±31
RL= 2000
- ±30 ±31 - V
±150 ±200
±150 ±200 mA
- ±250 ±300 - ±250 ±300 mA
20
0
- 20
±15 ±36 ±40 ±15 ±36 ±40 V
±20 ±25
- ±20 ±25 mA
los
losTC
AvoL
PSRR
CMRR
CMR
liD
Average, T MIN to T MAX
Min
1460-HR
Symbol
-
-
Typ Max Min Typ Max Unit
±1
±5
±10
±5
±15
±50
±0.3 ±1.5
±3
92
100
85
-
-
-
-
-
-
-
-
-
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS:
(Note 1) Vee = ±36V, RL = 10 k!l, Ce = 0 pF, Te = 25°C, unless otherwise noted.
1460-H~
1460
Symbol
Parameter
SR
Slew Rate
GBWP
UGBW
ts
Gain-Bandwidth Product
Unity-Gain Bandwidth
Settling Time (AcL = -6, Cc = 40 pF)
Test Conditions
Min
Cc= 40pF
f=10MHz
30V step/O.l%
10Vstep/0.l%
50
-
-
Typ Max Min Typ
300
65
1000
74
1
0.8
-
-
50
-
-
-
-
-
-
-
-
Max Unit
300
65
-
1000
74
1
0.8
-
-
-
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-56
V/1lS
V/IlS
MHz
MHz
Ils
IlS
HIGH SPEED, VMOS OUTPUT
OPERATIONAL AMPLIFIER
1460
STANDARD CONFIGURATION
Optional
Input
Protection
Cc
100pFforCc =180pF
200 pF tor Cc = 330 pF
o pF otherwise
APPLICATIONS INFORMATION
Figures 1 and 2 illustrate low gain noninverting and
inverting applications. The 1460's compensation capacitor
for each of these applications was chosen for 10 MHz
bandwidth operation.
The application in Figure 3 has a 10 MHz bandwidth and
an inverting gain of 100 yielding 1 GHz gain bandwidth
product. Notice that there is no compensation capacitor on
the 1460. No compensation capacitor is needed for gains
over 100. However, a feedback capacitor between 1 pF and
10 pF is recommended to compensate for the 1460's input
capacitance.
In the absence of a positive supply voltage, the output
will follow the negative supply. Should such a condition
occur, it is possible, depending on the feedback network
used, that the maximum allowable differential input voltage
may be exceeded. If there is a possibility that the differe~tial
input voltage may exceed ±6V, input overvoltage protection,
shown in the Standard Configuration diagram, should be
used.
Compensation
For optimum performance and noise rejection, power
supplies should be bypassed with 11lF tantalum ?apacitors.
When driving heavy loads, more bypass capacitance may
be needed.
160pF
VOUT
200n
Figure 1.
10 MHz Noninverting Gain of Two Amplifier
Figure 2.
9-57
10 MHz Inverting Gain of Six Amplifier
9
HIGH SPEED, VMOS OUTPUT
OPERATIONAL AMPLIFIER
1460
~60
z
o
~
40r-__~__-+~~~~~__~
1M
10M
FREQUENCY (Hz)
1k
Rgure 3.
Cc
o pF
10 pF
20 pF
40 pF
80 pF
180 pF
330 pF
10 MHz Inverting Gain of 100
Rgure 4.
100M
Bode Plot
Frequency
at Unity Gain
Phase
at Unity Gain
Frequency
at 180·
74 MHz
74 MHz
55 MHz
50 MHz
32 MHz
17MHz
10MHz
275 0
267 0
277"
216 0
1650
1320
118 0
5MHz
25 MHz
32 MHz
36 MHz
37 MHz
250V/~s
45 MHz
50 MHz
13V/~s
FigureS.
A.C. Characteristics vs Cc
9·58
Slew Rate
125V/~s
84V/~
50V/~
28V/~s
7V/I!S
HIGH SPEED, VMOS OUTPUT
OPERATIONAL AMPLIFIER
1460
i=
5.12MHz
2.56 MHz
1.28MHz
"'0 640 kHz
~:i! 320 kHz
:::;CD 160 kHz
80 kHz
40 kHz
:J!2
::l;;:
;;cffi
:f;;:
oQ.
--
10volta n
2
4
Cc =40pF
......
30volt. nal
Iii" 80
~
16
32
64
128
10 Hz
Full Power Bandwidth vs Inverting Gain
"[ 640
:> 320
- 160
~ 80
a: 40
;;: ~g ,... .....-
Cc-160pF
~
III
60
2
Figure 7.
--- -
100 Hz 1 kHz 10 kHz
FREQUENCY
Figure 8.
-
"
100 kHz
CMRR VB Frequency
Cc=lSpF
~100
!
........Cc=40pF
64
16
32
4
8
INVERTING GAIN at RL = 200Q
~
256
INVERTING GAIN at RL = 200(1
Figure 6.
.........
:!!.
a:
a:
a:
a:
If
"~
80
f"
128
10 Hz
100 Hz 1 kHz 10 kHz
FREQUENCY
Figure 9.
Slew Rate VB Inverting Gain
9-59
100 kHz
PSRR vs Frequency
NOTES
9-60
~"'TELEDYNE
COMPONENTS
1461
OPERATIONAL AMPLIFIER - HIGH-SPEED,
HIGH-POWER, VMOS-OUTPUT
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The 1461 is an extremely fast, FET-input, VMOS-output, power operational amplifier. It operates from ±15V to
±40V supplies, has output voltages up to ±34V, and output
currents up to ±750 rnA. Its unique VMOS-output stage
eliminates the safe operating area (SOA) restrictions and
secondary breakdown problems that plague virtually all
other presently-available power op amps. The 1461 's ability to handle high output currents at any voltage eliminates
the intricate problems normally caused by driving capacitive or inductive loads.
The 1461's combination of speed and power characteristics is unmatched. Its 115 dB open-loop gain, 1 GHz
gain-bandwidth product, and 1000 V/JlS slew rate make it
an outstanding high-speed op amp.
The 1461 is housed in a 14-pin dual-in-line package
with "ears" for easy mounting to heat sinks. Compensation
is accomplished with a single external capacitor. Two external current-limiting resistors are optional.
The standard 1461 is specified for O°C to +70°C operation. For high-reliability military/aerospace applications,
the High Reliability (HR)1461 version is specified for-55°C
to + 125°C operation.
Output ....•....•.....•...............•............... ±34V, ±750 rnA
Gain-Bandwidth Product ................................ 1 GHz
Slew Rate ................................................... 1000 V/IlS
FET Input
VMOS-Output Stage
No SOA Restrictions
Operation (-HR) .............................. -55°C to +125°C
APPLICATIONS
•
•
•
•
•
Video Yoke Drivers
Video Distribution Amplifiers
High-Speed ATE Pin Drivers
High-Accuracy Audio Amplification
Driving Inductive and Capacitive Loads
PIN CONFIGURATION
PIN
NO.
2
3
4
5
6
7
NC
1048·1
DESIGNATION
-IN
+IN
NC
NC
-VCC
-ILiMIT
NC
PIN
NO.
.,'"
DESIGNATION
8
OUTPUT
9
10
11
12
13
14
+ILlMIT
+VCC
COMPENSATION
COMPENSATION
OFFSET ADJUST
OFFSET ADJUST
1461
0000000
14 13 12 11 10 9
8
TOP VIEW
1
2
3
4
5
6
7
.000000
=NO INTERNAL CONNECTION
9-61
...
.:.
HIGH-SPEED, HIGH-POWER, VMOSOUTPUT OPERATIONAL AMPLIFIER
1461
ABSOLUTE MAXIMUM RATINGS
Vee
VIO
VleM
Te
T sm
8Je
Supply Voltage ............................................... ±45V
Differential Input Voltage ................................ ±25V
Common-Mode Input Voltage ........................ ±Vee
Operating Temperature Range (Case)
1461 .............................................. 0°Cto+70°C
1461-HR .................................. -55°C to +125°C
DC CHARACTERISTICS:
(Note 1) Vee
Storage Temperature Range ....... -65°C to + 150°C
Output Transistor Junction-to-Case
Thermal Resistance ................................... 11 °CIW
=±36V. RL =10 kn. T e =25°C. unless otherwise noted.
1461
Symbol
Parameter
Test Conditions
Vos
VosTC
Input Offset Voltage
Input Offset Voltage Drift vs Temperature
16
16 TC
Input Bias Current Drift vs Temperature
los
Input Offset Current
10sTC
Input Offset Current Drift vs Temperature
AVOL
PSRR
Open-Loop Voltage Gain
CMRR
CMR
Common-Mode Rejection Ratio
VCM = ±22V'
Common-Modlll Range (DC Linear Operation) CMRR -10
....
!50
I--+---+---+----+----':oa-l-l
D.E
~ ....
(J
....
::J
D.
....
::J
V
±140 ...---..,...---.,......-..,...---,----,
II
-----~-----------oVO
5
RCL = O.65V
-ILiMIT
'Optional foldover current limiting.
0.65 + 0.33 x Va
20.33+ RFO
O.471'F
CERAMIC~
1060-1
RCL
I Fa = Current limit at output voltage Va
RFo = Current foldover resistor in kQ
RCL = Current-limit resistor in 0
Va = Instantaneous output voltage
9-69
HIGH-VOLTAGE, VERY-HIGH-POWER
OPERATIONAL AMPLIFIER
1468 (TePA12)
PIN CONFIGURATION
PIN
NO.
DESIGNATION
OUTPUT
2
3
4
5
+IUMIT
+Vee
+INPUT
-INPUT
6
7
-Vee
FOLDOVER
8
-Ill MIT
BOTTOM VIEW
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range ....... -65°C to +150°C
Supply Voltage ............................................... ±50V
Junction Temperature
Differential Input Voltage ..................... ±(IVccl-3V)
(Output Transistor) (Note l) .. :..................... +200°C
VICM Common-Mode Input Voltage ........................ ±Vcc
Junction-to-Case Thermal Resistance
Output Current ................................................ ±15A
10
(Output Transistor) (Note 2) ............ O.9°C/W @ AC
Internal Power Dissipation ............................. 125W
Po
1.4°CIW @ DC
Operating Temperature Range (Case)
Te
1468 .......................................... -25°C to +85°C
1468-HR .................................. -55°C to +125°C
NOTES: 1. Prolonged operation at maximum junction temperature will result in reduced product life. Derate intemal power
dissipation to achieve high MTBF.
2. AC rating applies if the output current altemates between both output transistors at a rate greater than 60 Hz.
Vcc
VIO
DC CHARACTERISTICS:
(Note 1) VCC = ±40V, RL = 1
1<.0,
T C = 25°C, unless otherwise noted.
1468
Symbol
Parameter
Vos
Input Offset Voltage
Vos TC
Input Offset Voltage Drift vs Temperature
IB
IBTC
Input Bias Current Drift vs Temperature
Test Conditions
Typ
Max
±2
±6
Average, TMIN to TMAX
-
±10
-
-
±12
±30
Average, TMIN to TMAX
±50
-
-
±12
±30
Average, T MIN to T MAX
±50
96
110
108
74
74
90
100
-
Input Bias Current
los
Input Offset Current
10sTC
Input Offset Current Drift vs Temperature
AvoL
Open-Loop Vottage Gain
RL= 8£1
PSRR
Power Supply Rejection Ratio
CMRR
Common-Mode Rejection Ratio
1468-HR
Min
CMR
VCM = ±33V
Common-Mode Range (DC Linear Operation) CMRR~68 dB
liD
Differential Input Impedance
Vo
Output Voltage Swing
10
Isc
Output Current
Output Short-Circuit Current
Ro
Output Resistance (DC Open-Loop)
Vee
Supply Voltage Range (Operating)
lee
Quiescent Supply Current
-
Min Typ
-
±10
-
±12
-
±12
±50
±50
±6 mV
±65 llVloC
±30 nA
±400 pAloC
±30 nA
±400 pAloC
-
110
108
-
dB
dB
74
74
90
100
-
dB
-
£1llpF
-
-
V
V
-
A
±37
-
200M1I3
-
-
10UT= 5A
10UT= 10A
±35
±34
-
±35
±34
Peak
Note 2
±10
-
±35 ±37
200MII3
-
-
-
-
-
-
2
-
-
±10
±40
±45
-
±25
±50
-
Max Unit
96
±35
-
±2
±10
-
V
2
-
£1
±10
±40
±45
V
-
±25
±50
rnA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
2. Current limiting is set by user via extemal resistors.
9-70
dB
A
HIGH-VOLTAGE, VERY-HIGH-POWER
OPERATIONAL AMPLIFIER
1468 (TCPA12)
AC CHARACTERISTICS: (Note 1) Vcc = ±40V, RL = 1 kn, Tc = 25°C, unless otherwise noted.
1468
Symbol
Parameter
Test Conditions
SR
GBWP
UGBW
ts
en
in
CL
Slew Rate
Gain-Bandwidth Product
Unity-Gain Bandwidth
Settling Time (AcL = -1)
Input Voltage Noise Density
Input Current Noise Density
Capacitive Load (Maximum w/o oscillation)
Typ Max Min Typ Max Unit
2.5
5
4
4
2
16
0.18
-
f = 1 MHz, RL = 80
-
2V step/0.1 %
f= 1 kHz
f= 1 kHz
AcL= +1
1468-HR
Min
1500
-
-
2.5
-
SOA 1500
5
4
4
2
16
0.18
-
-
-
V/JlS
MHz
MHz
JlS
nVNHz
pANHz
SOA pF
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
Output Current Limiting
The 1468 output can be current limited using the ±luMIT
formulas shown in the standard configuration diagram. In
some applications, foldover current limiting can be used to
allow increased output current as the 1468 output approaches the power supply rail voltage. To calculate the
foldover current limit, use the formula for IFO shown in the
diagram. The following procedures should be followed:
1. Calculate a value for RCL that provides a safe current
limit at Vo = OV.
2. Calculate the maximum value of IFO * by using a value
of on for RFO. This is the maximum current limit
possible using the foldover current-limit option.
3. Calculate a value for RFO using the value for RCL
calculated in step 1 , and a desired IFO limit which is
lower than the maximum limit calculated in step 2.
"This calculation assumes the output voltage (Vo) is the same polarity
as the current carrying supply voltage. If not, invert the polarity of Vo
before making this calculation.
120
BOND WIRE LIMITED
100
\
80
iii"
If ~ 5 "=-""""''''=-*,-,N-=C.
!Zg31-----'l"'o..~.....,,;
I\..
z
(!J
o
"" '"
~ 60
«
:::;;
40
20
~=r 2 1---+--1:..~d~.--P~
II: II:
\.
0
-20
o
G0 1.5 1--+---1'''''
~ g 11---+--+~~-+~~~~'
1=:::: 0.71--+--+~~-++-+-f""";!!'
5 0.5 I---+--+~~-+~-+-+-+B'"
\
O~~--~~~~~~~~~~
\
10
100
1k
10
15
20 25 303540 50 6070BO 100
SUPPLY TO OUTPUT DIFFERENTIAL
VOLTAGE (V)
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 1.
Bode Plot
Figure 2.
9-71
Safe Operating Area (SOA)
NOTES
9-72
~~TELEDYNE
COMPONENTS
1480
OPERATIONAL AMPLIFIER -
FAST-SETTLING, HIGH-VOLTAGE
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The 1480 is a fully-differential FET-input operational
amplifier capable of operating over a voltage supply range
of ±15V to ±150V with common-mode and output voltages
ranging to within 10V of the supply voltages, and output
currents of up to ±1 00 rnA. The 1480 is pin compatible with
the 8B3583, but has superior time and frequency performance. Gain-bandwidth product is 18 MHz, slew rate is
1OOV/flS, and unity-gain bandwidth is 5 MHz.
The input of the 1480 is fully protected. It can withstand common-mode voltages to ±( IVee I+5)V, differential
voltages to 450V, and input voltage slew rates to 150 kVI
fls. Output current is short-circuit limited at ±125 rnA. The
true differential FET-input (typical CMRR is 125 dB) limits
input bias current to ±200 pA (maximum). The bias and
offset current drifts are small enough to greatly reduce the
large offset drifts normally associated with high-voltage
circuits.
The 1480 is packaged in a TO-3 metal can and is
specified for O°C to +70°C operation. The 1480 High Reliability (HR) version is specified for -55°C to + 125°C operation.
•
•
•
Output .•....••..•.....••...............•........... ±143V, ±100 mA
Settling Time (100V Step to ±0.01%) ...... 2.5 fls Max
Common-Mode Voltage ............•........••.....•.•.. ±140V
Input Overvoltage and Output Short-Circuit
Protected
Standard TO-3 Can
883583 Compatible with Improved
AC Performance
Operating Temperature (-HR) ....... -55°C to +125°C
APPLICATIONS
•
•
•
ATE Pin Drivers
Electrostatic Deflection
High-Voltage DACs
NORMAL INVERTING OPERATION
·OPTIONAL
OFFSET
ADJUST
NOTE: The metal case is electrically isolated. It is
recommended that it be grounded during use.
1049·1
9·73
9
FAST-SETTLING, HIGH-VOLTAGE
OPERATIONAL AMPLIFIER
1480
PIN CONFIGURATION
PIN
NO.
DESIGNATION
OUTPUT
2
6
+VCC
OFFSET TRIM
OFFSET TRIM
-IN
+IN
7
8
-VCC
NC
3
4
5
BOTTOM VIEW
NC =NO INTERNAL CONNECTION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................................ ±160V
Differential Input Voltage (Note 1) ............... ±450V
Common-Mode Input Voltage ............. ±(Vce +5)V
Input Slew Rate (Notes 1, 2) ............... ±150 kV/Jls
Te
TSTG
Operating Temperature Range (Case)
1480 .............................................. O°C to +70°C
1480-HR .................................. -55°C to + 125°C
Storage Temperature Range ...... -65°C to +150°C
NOTES: 1. Includes power-off conditions.
2. The high differential voltage and dv/dt ratings of the input prevent input stage blowout even if the input is direcUy shorted to either rail.
Such shorts do stress the input, however, and we cannot guarantee protection for durations exceeding a few seconds.
DC CHARACTERISTICS:
(Note 1) Vee =±150V, RL = 10
kn, Te = 25°C, unless otherwise noted.
1480
Symbol
Parameter
Vas
Input Offset Voltage
Vas TC
Input Offset Voltage Drift vs Temperature
18
18 TC
Input Bias Current
los
Input Offset Current
los TC
Input Offset Current Drift vs Temperature
AVOL
Open-Loop Voltage Gain
Input Bias Current Drift vs Temperature
Test Conditions
-
-
±15
±100 !lV/DC
±50
±200
-
±50
±200 pA
±3
-
95
120
115
-
RL= 1.8 kn
100
120
-
110
125
-
-
DHferential Input Impedance
Output Short-Circuit Current
±15
Max Unit
Average, T MIN to T MAX
liD
Isc
±1
±40
- ±40
Doubles every 11 DC Doubles every 11 DC
Common-Mode Range (DC Linear Operation) CMRR~ 104dB
Output Current
-
-
CMR
10
±3
Doubles every 11 DC Doubles every 11 DC
Power Supply Rejection Ratio
Common-Mode Input Impedance
±1
Min Typ
Average, T MIN to T MAX
Common-Mode Rejection Ratio
Output Voltage Swing
Max
Average, T MIN to T MAX
PSRR
Va
1480-HR
Typ
-
CMRR
llCM
Min
VCM = ±130
RL= 1.8 kn
±135 ±140
-
-
95
120
115
100
120
110
125
-
OllpF
-
V
-
-
±140 ±143
±75 ±100
-
-
±125
-
200
Ro
Output Resistance (DC Open-Loop)
Vce
Supply Voltage Range (Operating)
±15
-
±150
±15
Icc
Quiescent Supply Current
-
±10
±12
-
200
-
dB
1011 113
1011 113
±125
dB
-
-
-
RL = 5000 (Note 2)
dB
dB
1011 115
±140 ±143
-
pA
-
-
10"115
±100
-
-
±135 ±140
±75
-
mV
±10
-
V
OllpF
mA
mA
0
±150 V
±12
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
2. The 1480 is short-circuit protected to ground or either supply for supply voltages totaling <100V. It is short-circuit protected to ground only
for supplies totalling up to 160V.
9-74
FAST-SETTLING, HIGH-VOLTAGE
OPERATIONAL AMPLIFIER
1480
AC CHARACTERISTICS:
(Note 1) Vee = ±150V, RL = 10 kil, T e = 25°C, unless otherwise noted.
Symbol
Parameter
Test Conditions
SR
GBWP
UGBW
Slew Rate
Gain-Bandwidth Product
f=100kHz
Unity-Gain Bandwidth
ts
Settling Time (ACL
en
Input Voltage Noise Density
CL
Capacitive Load (Maximum w/o oscillation)
=-10)
1OOV step/O.l %
1OOV step/O.Ol %
f= 1 kHz
Min
1480
1480-HR
Typ Max Min Typ Max Unit
-
100
-
18
-
5
-
1
1.5
20
100
250
-
-
-
-
100
18
-
-
5
1.5
2.5
-
-
1
- 1.5
- 20
100 250
-
1.5
2.5
Ils
-
nWIHz
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-75
V/IlS
MHz
MHz
Il s
pF
NOTES
9-76
"'~TELEDYNE
COMPONENTS
1481
OPERATIONAL AMPLIFIER -
HIGH-VOLTAGE
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The 1481 is a high-voltage operational amplifier capable
of operating with supply voltages as high as ± 75V or as low
as ±15V. It can provide output voltage swings as high as
±70V with output currents to ±1 00 rnA (short circuit limited
to ±125 mAl. The cascoded FET input stage is fully overvoltage protected.
This operational amplifier features a 25V/ps slew rate
and a 4.5 MHz unity-gain bandwidth. Maximum input offset
voltage is ±3 mV, and minimum open-loop gain is 94 dB
(full load). The Class AB output stage can drive up to
10,000 pF capacitive loads at closed-loop gains of 10 or
more. Pin compatible with the B83581, the 1481 features
more than double the output current capability of its
competitor's and faster settling time.
The 1481 is packaged in an 8-pin TO-3 can. The
standard unit is specified for O°C to +70°C operation. The
1481 High Reliability (HR) version is specified for -55°C to
+125°C operation.
Output ...............................................±70V, ±100 mA
Fully Differential FET Input
Wide Supply Range ..•..••........•....•....... ±15V to ±75V
Input Overvoltage Protected
Output Current Limited at ±125 mA
APPLICATIONS
•
•
ATE Pin Drivers
Electrostatic Deflection
PIN CONFIGURATION
NORMAL INVERTING OPERATION
>-----'--+--0 VOUT
BOTTOM VIEW
PIN
NO.
NOTE: The metal case is electrically isolated.
It is recommended the case be grounded
during use.
2
3
4
±Vcc
OFFSET TRIM
OFFSET TRIM
5
-INPUT
+INPUT
6
7
8
1050-1
DESIGNATION
OUTPUT
-vcc
9-77
-Vcc
NC
NC
=NO INTERNAL
CONNECTION
9
HIGH-VOLTAGE
OPERATIONAL AMPLIFIER
1481
ABSOLUTE MAXIMUM RATINGS
Vee
VID
VleM
Te
Supply Voltage .............................................. ±80V
Differential Input Voltage ............................... ±Vee
Common-Mode Input Voltage ....................... ±Vee
Operating Temperature Range (Case)
1481 .............................................. O°C to +70°C
1481-HR .................................. -55°C to +125°C
TSTG
9Je
Storage Temperature Range ...... -65°C to + 150°C
Output Transistor Junction-to-Case Thermal ....... .
Resistance .................................................. 6°CIW
DC CHARACTERISTICS: (Note 1) Vee = ±75V, RL = 10 kil, Te = 25°C, unless otherwise noted.
1481
Parameter
Vos
Input Offset Voltage
VosTC
Input Offset Voltage Drift vs Temperature
Average, T MIN to T MAX
Is
Is TC
Input Bias Current
±10 ±100
±10 ±100 pA
Average, T MIN to T MAX Doubles every 11 DC Doubles every 11 DC
los
Input Offset Current
10sTC
Input Offset Current Drift vs Temperature
AVOL
Open-Loop Vokage Gain
Input Bias Current Drift vs Temperature
Test Conditions
1481-HR
Symbol
Min
Typ
Max Min Typ
-
±1
±3
-
±15
-
-
±10
-
±1
±3
mV
-
±15
±50
iJ.v/"e
-
Average, T MIN to T MAX Doubles every 11 DC Doubles every 11 DC
108
108
94 106 94 106
RL= 8500
-
PSRR
Power Supply Rejection Ratio
70
94
-
70
94
Common-Mode Rejection Ratio
70
94
70
94
±65
±70
-
1011 11
1011 11
-
±68
±73
±70
±80
±100
CMR
VCM = ±60
Common-Mode Range (DC Linear Operation) CMRR ~ 64 dB
ZID
Dffferentialinput Impedance
ZICM
Common-Mode Input Impedance
Vo
Output Voltage Swing
RL = 8500
Output Current
Isc
Output Short-Circuit Current
-
±10
CMRR
10
Max Unit
-
RL=3300
-
Ro
Output Resistance (DC Open-Loop)
-
Vcc
Supply Voltage Range (Operating)
±15
Icc
Quiescent Supply Current
-
-
±125 ±150
±65 ±70
-
-
-
V
-
-
±80 ±100
-
dB
dB
dB
-
±73
±68 ±70
pA
-
-
1011 11e
1011 11
-
dB
OllpF
OllpF
V
V
rnA
±125 ±150 rnA
-
-
-
0
-
±75
±15
-
±75
V
±11
±15
-
±11
±15
rnA
100
100
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS: (Note 1) Vee =±75V, RL = 10 kil, Te = 25°C, unless otherwise noted.
1481
Symbol
Parameter
Test Conditions
SR
GBWP
Slew Rate
Gain-Bandwidth Product
f = 100 kHz
UGBW
Unity-Gain Bandwidth
t.
Settling Time (AcL = -1)
100V step/O.l %
en
Input Voltage Noise Density
f= 1 kHz
CL
Capacitive Load (Maximum w/o oscillation) ACL~ 10
1481-HR
Min
Typ
Max
-
25
7.5
-
3
4.5
-
7.5
10,000
20
-
Min Typ
-
-
25
7.5
Max Unit
-
-
3
4.5
-
-
-
7.5
-
-
-
10,000
MHz
20
-
iJ.s
nVNHz
-
-
pF
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-78
V/Jls
MHz
~"'TELEDYNE
COMPONENTS
1482
OPERATIONAL AMPLIFIER -
HIGH-VOLTAGE
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The 1482 is a high voltage operational amplifier capable
of operating with supply voltages as high as ±75V, or as low
as ±15V. It can provide output swings as high as ± 70V with
output currents to ±40 mA (short circuit limited to ±65 mAl.
The cascoded FET input stage is fully overvoltage protected.
This op amp features a 25V1IlS slew rate and a 7.5 MHz
unity gain-bandwidth. Maximum input offset voltage is
±3 mV, and minimum open loop gain is 94 d8 (full load). The
class A8 output stage can drive up to 10,000 pF capacitive
loads at closed loop gains of ten or more. The 1482 is pin
and performance compatible with the 883581, but with
faster settling time.
The 1482 is packaged in an 8 pin, TO-3 package. The
standard unit is specified for O°C to +70°C operation. The
1482 High Reliability (HR) version is specified for -55°C to
+125°C operation.
Output ••••.•.•••••.••••••••.•••.••••..••••.•.•..••.••••• ±70V, ±40 mA
Fully Differential FET Input
Wide Supply Range .......•.•.....•.•........•.. ±15V to ±75V
Input Overvoltage Protected
Output Current Limited at ±65 mA
Low Supply Current •••••...•.•..•....•..••••.••.•.••.•.• ±6.5 mA
APPLICATIONS
•
•
ATE Pin Drivers
Electrostatic Deflection
PIN CONFIGURATION
NORMAL INVERTING OPERATION
BOTTOM VIEW
7
PIN
NO.
DESIGNATION
-vee
OUTPUT
NOTE: The metal case is electrically isolated.
It is recommended the case be grounded
during use.
2
3
4
5
9-79
+Vee
OFFSET TRIM
OFFSET TRIM
-INPUT
6
+INPUT
7
8
-vec
NC
NC
=NO INTERNAL
CONNECTION
_
•_
_
HIGH-VOLTAGE
OPERATIONAL AMPLIFIER
1482
ABSOLUTE MAXIMUM RATINGS
Vcc
VID
VICM
Tc
Supply Voltage .............................................. ±80V
Differential Input Voltage ............................... ±Vcc
Common-Mode Input Voltage ....................... ±Vcc
Operating Temperature Range (Case)
1482 .............................................. O°C to +70°C
1482-HR .................................. -55°C to +125°C
DC CHARACTERISTICS:
T STG
9JC
Storage Temperature Range ...... ~oC to + 150°C
Output Transistor Junction-to-Case Thermal
Resistance ................................................ 12°C/W
(Note 1) Vcc = ±75V, Rl = 10 kn, Tc = 25°C, unless otherwise noted.
1482
Symbol
Parameter
Vas
Vos TC
Input Offset Voltage
Input Offset Voltage Drift vs Temperature
Input Bias Current
Input Bias Current Drift vs Temperature
Input Offset Current
Input Offset Current Drift vs Temperature
Open-Loop Voltage Gain
Is
IsTC
los
los TC
AVOL
PSRR
CMRR
CMR
liD
llCM
Va
10
Isc
Ro
Vcc
Icc
Test Conditions
Min
1482-HR
Typ Max Min Typ Max Unit
-
-
±1
±3
±1
±3
±15
- ±15 ±50
±10 ±100
- ±10 ±100
Average, T MIN to TMAX Doubles every II·C Doubles every II·C
±10
- ±10 Average, T MIN to T MAX Doubles every II·C Doubles every II·C
108
108
94
106
RL=2 k.O
94 106
Power Supply Rejection Ratio
70
94
70
94
Common-Mode Rejection Ratio
94
70
94
70
VCM = ±60
Common-Mode Range (DC Linear Operation) CMRR~64 dB
±65 ±70
±65 ±70
101111E
Differential Input Impedance
- 1011 11e Common-Mode Input Impedance
1011 113
- 1011 11
Output Voltage Swing
±73
- ±73
±68 ±70
RL= 2 k.O
- ±68 ±70 ±35 ±40
Output Current
±35 ±40
Output Short-Circuit Current
±65 ±80
RL=680n
±65 ±80
Output Resistance (DC Open-Loop)
100
100
Supply Voltage Range (Operating)
±15
±75 ±15
±75
Quiescent Supply Current
±6.5 ±8
±6.5 ±8
Average, T MIN to T MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV
/1V/"C
pA
pA
dB
dB
dB
dB
V
nllpF
nllpF
V
V
rnA
rnA
n
V
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS:
(Note 1) Vcc = ±75V, Rl = 10 kn, Tc = 25°C, unless otherwise noted.
1482
Symbol
Parameter
Test Conditions
SR
GBWP
UGBW
Slew Rate
Gain-Bandwidth Product
Un~y-Gain Bandwidth
f=100kHz
t.
en
in
CL
Settling Time (ACL = -1)
Input Voltage Noise Density
Input Current Noise Density
Capacitive Load (Maximum wlo oscillation)
100V step/O.l%
f = 1 kHz
f= 1 kHz
AcL~
10
Min
-
25
9
5
7.5
7.5
20
10,000
1482-HR
Typ Max Min Typ Max Unit
-
-
-
-
5
-
-
-
-
10,000
-
25
9
7.5
7.5
20
-
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-80
V/Jls
MHz
MHz
/1S
nVNHz
pM/Hz
pF
.,"'TELEDYNE
COMPONENTS
4856
LOW COST MICROCIRCUIT
SAMPLE/HOLD AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The 4856 is a high performance sample/hold amplifier
for applications requiring high speed and small size. This
unit has been designed for maximum versatility in circuit
design and "tailoring" of specifications. With a minimum of
external components, the 4856 can be used inverting or
non-inverting, with or without gain. In the sample mode, the
4856 acts as an op amp and any of the standard op amp
feedback circuits may be externally connected to control
such parameters as gain and frequency response.
In addition, the externally connected hold capacitor
enables the user to achieve the best compromise between
acquisition time and droop rate forthe particular application.
A standard device is specified for GOC to +75°C. The High
Reliability (HR) version is specified for -55°C to + 125°C
temperature range.
•
Gain-Bandwidth Product .............................. 2.5 MHz
Acquisition Time to 0.1% ............................ 2.3Ilsec
Slew Rate ....................................................... 5V/llsec
Ultra-Versatile: Inverting, Non-inverting,
With or Without Gain
Wide Temperature Range Version Available
APPLICATIONS
•
•
•
•
Data Acquisition Systems
Analog Memories
Data Distribution Systems
Deglitch Circuits
BLOCK DIAGRAM
SAMPLE!
IN-
HOLD CONTROL
IN+
GND
----'1
NC
HOLD CAP.
o----.~+_~~~-
v-
NC
NC
v+
OUT
NC
NOTES: 1. Use Cermet Potentiometer
2. CH shOUld be a polystyrene, mica, or
teflon capacitor. The value of CH to
be determined from Figure 1.
1OS&-1
9-81
CH
--t--...J
II
LOW COST MICROCIRCUIT
SAMPLE/HOLD AMPLIFIER
4856
PIN CONFIGURATION
Pin
No.
DeSignation
Pin
No.
Designation
1
-IN
8
NC
2
+IN
9
3
OFFSET ADJUST
10
+V
NC
4
OFFSET ADJUST
11
HOLD CAP.
""
4856
5
-V
6
NC
12
13
NC
GND
7
OUT
14
SAMPLE/HOLD CONTROL
DC CHARACTERISTICS: (Note 1) Vee =±15V, Unity Gain Configuration, CH = 1000 pF, Te =25°C unless
otherwise noted.
4856
Symbol
Parameter
VIN
Input VoHage Range
RIN
Input Resistance
Input Bias Current
18
Test Conditions
±10
5
TMIN to TMAX
Input Offset Current
los
TMIN to TMAX
Input Offset Voltage
VOs
TMINto TMAX
-
PSRR
Power Supply Rejection Ratio
Vo
Output Voltage Swing
10
Output Current
Ro
Output Resistance (DC)
AVOL
Vp
Large Signal VoHage Gain
Pedestal Voltage
CMR
Common-Mode Range
VIH
Logic "1" Input VoHage
2
VIL
Logic "0" Input Vottage
-
Icc
Quiescent Supply Current
RL= 2 kn
4856·HR
Min Typ Max Min Typ Max Unit
10
±40
-
-
±200
-
10
50
±2
±3
±4
-
80
90
±10
-
±15
-
±15
88
94
-
10
20
-
-
-
0.8
3.5
2.5
5.5
3.5
±2
±3
±4
±6
mV
mV
-
dB
90
-
0.15
88
94
±10
2
-
MQ
-
-
-
V
nA
nA
10
80
±200
±400
50
100
-
-
RL= 2 kn
-
±40
±10
VIN=OV
-
-
-
-
Supply
Negative Supply
10
-
0.15
Pos~ive
-
5
-
±10
±10
-
-
10
20
-
-
nA
nA
V
rnA
n
dB
mV
V
-
V
-
0.8
V
3.5
2.5
5.5
3.5
rnA
rnA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS: (Note 1) Vee =±15V, Unity Gain Configuration, CH
=1000 pF, Te =25°C unless
otherwise noted.
4856
Symbol
Parameter
Test Conditions
tacq
Acquisition Time
to 0.01% of 10V step
to 0.1% of 10V step
tad
tai
sr
~
Aperture Delay Time
Aperture Jitter
Slew Rate
Vo=10Vpp
t,
Rise Time
RL= 2k
GBW
Gain-Bandwidth Product
9-82
4856·HR
Min Typ Max Min Typ Max Unit
--
3.2
2.3
6
-
30
3.5
5
-
-
75
100
2.5
-
5
4
-
3.2
2.3
6
liS
4
IlS
30
-
ns
3.5
5
-
VlIlS
75
100
-
2.5
-
-
-
5
-
ns
ns
MHz
LOW COST MICROCIRCUIT
SAMPLE/HOLD AMPLIFIER
4856
IN
OUT
GAIN-·~
Rl
INVERTING CONFIGURATION
MAKE R3 = n,R2
(R1 +R2)
Figure 1.
Typical Performance Curve
Offset Voltage Trim
OUT
The offset voltage, in either the "Sample" or "Hold"
mode, may be trimmed to OV while cycling between sample
and hold with OV input and adjusting the 100 kQ potentiometer (Block Diagram) for OV output. This does not, however,
reduce the difference between the Sample and Hold offset
voltages to zero.
GAIN
=(R1R~ R2). FOR GAIN =1.00
R1
Rl =oo,R2=O
NON-INVERTING CONFIGURATION
Droop Rate Adjust
Figure 2.
The Droop Rate forthis unit is determined from the value
of the external capacitance, (CH), shown in the Block
Diagram. Figure 1 shows the curves that give the value of
CH for the desired Droop Rate, as well as the effect on
Acquisition Time.
To minimize errors caused by dielectric absorption, it is
important to choose a polystyrene, mica, or teflon capacitor
forthe external hold capacitor. The external capacitor should
be located close to the unit to reduce the effects of stray
inductance.
Pin Programming
Guard Ring
Leakage paths on the P.C. board and on the package
surface must be minimized to reduce Droop Rate during
hold. The output line forms a guard ring around the Hold
Capacitance pin, which, because of the very nearly equal
potentials between the output and the Hold Capacitance pin,
will result in a very low leakage current. In addition, Pins 10
and 12, which are not internally connected, may be connected to the guard ring to reduce package surface leakage.
Figure 3.
9-83
Guard Ring Layout (Bottom View)
•
NOTES
9-84
~"'TELEDYNE
COMPONENTS
4860
FAST, 12-BIT
SAMPLE/HOLD AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
The 4860 is a very fast, high-resolution sample/hold
(track/hold) amplifier. Its acquisition time and sample-tohold settling time (a StH's two throughput limiting specifications) are guaranteed to ±0.01 'Yo, unlike other S/H amplifiers that only achieve ±0.1 % or ±1 %. The 4860 acquires a
10V signal step to ±0.01 % in 200 nsec maximum and then
tracks signal components up to 16 MHz. In the track mode,
offset error is typically ±0.5 mV, and gain error is typically
±0.05%. When commanded to Hold the 4860's output
settles within ±0.01 %FS of its final value in 100 nsec
maximum. The aperture delay time is 6 nsec, aperture jitter
is ±50 psec, and pedestal is a minimal ±2.5 mV. In the hold
mode the output droop rate is a low 5 ~V/lJ.Sec maximum and
feedthroughattenuation, at 2.5 MHz, is an impressive 74 dB.
Its 24-pin, dual-in-line package, gain of -1, ±10V input!
output range, and TTL compatible logic make the 4860's
performance compatible with many industry standard devices. Being a second-generation design, however, the
4860 is superior to these units in almost every performance
specification. Faster switching and better feedthrough attenuation are the results of our unique MOSFET switching
scheme. Shorter acquisition and settling times and considerably lower droop are the result of our proprietary high
speed, FET input op amp designs.
A standard device is specified for O°C to +70°C. The
High Reliability (HR) version is specified for-55°C to + 125°C
temperature range.
•
•
•
•
Acquisition Time for a 10V Step to ±0.01%FS
..................................................................200 ns Max
Sample-to-Hold Settling Time ................ 100 ns Max
Aperture Jitter .............................................±50 psec
Feedthrough Attenuation ................................ 74 dB
TTL Compatible
APPLICATIONS
•
•
•
•
•
Transient Recorders
Fast Fourier Analysis
High Speed DASs
High Speed DDSs
Analog Delay and Storage
BLOCK DIAGRAM
.,r-
1 k!l
4860
GROUND
15 0---.
~~~AND
11
ANALOG
OUTPUT
O--.r-...
~g~~AND
12
GROUND
10 0 - .
-"!
=
PS BYPASS
CAPACITORS
..
:!:
T
- - 0 21
11
-.-
-.-
SYSTEM ANALOG GROUND
1059·1
9-85
~9
~:
023
GROUND
+5V
:1::
GROUND
9
FAST, 12-BIT
TRACKlHOLD AMPLIFIER
4860
PIN CONFIGURATION
Pin
No.
Designation
Pin
No.
Designation
1
ANALOG OUTPUT
13
ANALOG INPUT
2
NC
14
NC
3
NC
15
GROUND
4
16
NC
5
NC
NC
17
6
NC
18
7
NC
8
NC
9
BOTTOM VIEW
@
24
1
@
@
23
2
@
@
22
3
@
NC
@
21
4
@
NC
@
20
5
@
19
NC
@
19
6
@
20
NC
@
18
7
@
@
17
8
@
@
16
9
@
@
15
10
@
@
14
11
@
@
13
12
@
+5VSUPPLY
21
10
GROUND
22
GROUND
-15V SUPPLY
11
HOLD
23
GROUND
12
HOLD
24
+15VSUPPLY
NC = No internal connection
ABSOLUTE MAXIMUM RATINGS
Vee
Voo
VIN
VIO
±15V Supplies .............................................. ±18V
+5V Supply ....................................... -0.5V to +7V
Analog Input .................................................±Vee
Digitallnput .................................... -0.5V to +5.5V
Te
TSTG
Operating Temperature Range (Case)
4860 ............................................ O°C to +70°C
4860-HR ................................ -55°C to +125°C
Storage Temperature Range ..... --65°C to +150°C
DC CHARACTERISTICS: (Note 1) Vee = ±15V. Unity Gain Configuration, CH = 1000 pF. Te = 25°C unless
otherwise noted.
4860
Symbol
Parameter
Test Conditions
VIN
Input Vo~age Range
liN
Input Impedance
VOs
VosTC
Input Offset Voltage
Track Mode
Input Offset Voltage vs Temperature
TMINto TMAX
PSRR
Power Supply Rejection Ratio
Vo
Output Voltage Swing
10
Output Current
lo
Output Impedance
Av
Voltage Gain
AA
Gain Accuracy
Gain Nonlinearity
Av TC
Vp
Gain Drift
VpTC
Pedestal Drift
Pedestal Voltage
Typ
-
±0.5
±5
-
±60
±300
-
66
-
-
±10.25 ±11.S0
RL=2k.Q
±40
-
-
0.1
-
VIN= OV
9-86
4860-HR
Max
1
±10.25 ±11.50
TMINto TMAX
AL
Min
-
-1
-
±0.05
±0.05
±O.1
±O.15
±0.003 ±O.OI
±0.5
±5
±2.5
±20
±80
-
Min
Typ
±10.25 ±11.S0
-
-
-
1
±0.5
±5
±60
±300
66
-
±10.25 ±11.S0
±40
Max
0.1
-1
-
±0.05 ±O.1
±0.05 ±0.15
0.003 ±O.OI
±0.5
±5
±2.5
±20
±80
-
Unit
V
k.Q
mV
JlVloC
dB
V
mA
n
VN
%
%
%FS
pprni"C
mV
INi"C
FAST, 12-BIT
TRACK/HOLD AMPLIFIER
4860
DC CHARACTERISTICS: (Continued)
Symbol
Parameter
Test Conditions
V,H
Logic "1" Input Voltage
Min
4860
Typ
2
-
-
2
-
0.8
-
-
V,L
Logic "0" Input Voltage
±Vcc
Voltage Range
±15V Supply
±5V Supply
±Icc
Quiescent Current
±15V Supply
±5V Supply
Po
Power Dissipation
-
-
Max
±3
±5
-
±21
17
730
±25
25
875
Min
-
4860-HR
Typ Max
-
-
-
-
-
Unit
V
-
0.8
V
±3
±5
-
%
%
±21
17
730
±25
25
875
mA
mA
mW
NOTES: 1. Limits pnnted In boldface type are guaranteed and 100% production tested. Limits In normal font are guaranteed but not 100%
production tested.
AC CHARACTERISTICS: (Note 1) Vee =±15V, Unity Gain Configuration, CH = 1000 pF, Te= 25°C unless
otherwise noted.
4860
4860-HR
Min Typ Max Min Typ Max Unit
Symbol
Parameter
Test Conditions
taeq
Acquisition Time
1OV step to 0.01 %FS (±1 mY)
1OV step to 0.1 %FS (±10 mY)
1OV step to 1%FS (±100 mY)
1V step to 1%FS (±100 mY)
-
to 0.01%FS (±1 mY)
to 0.1%FS (±10 mY)
ts
Settling Time, Sample to Hold
VTSH
Sample tol Hold Transient
tad
Aperture Delay Time
toi
sr
Aperture Jitter
Slew Rate
BW
Small Signal Bandwidth (-3 dB)
VHO
Droop Rate
FRR
Feedthrough Rejection Ratio
-
160
100
90
75
200
170
-
-
60
40
100
-
-
I = 2.5 MHz, Y'N = 20 Vp-p
9-87
-
-
-
160
100
90
75
200
170
60
40
100
-
ns
ns
ns
ns
180
-
-
180
-
30
-
-
30
-
ns
±50
-
±50
-
ps
±300
-
-
±300
-
16
-
-
16
-
MHz
±0.5
±5
-
±0.5
±5
f!V/f!s
-
-
74
-
dB
74
ns
ns
mVp-p
V/JlS
FAST, 12-BIT
TRACK/HOLD AMPLIFIER
4860
APPLICATIONS INFORMATION
Capacitive and Resistive Loading
The 4860 is ideally suited for 12 to 14-bit high speed data
acquisition/distribution systems. In a ±10V system, its
±0.01%FS (±0.005%FSR) linearity is equivalent to better
than ±1/2LSB in 13 bits. Its low ±5Ops aperture uncertainty
enables it to accurately (±1/2LSB in 12 bits) sample signals
with slew rates up to 24.4V/~isec. Its low, 511V1~ec, output
droop rate enables it to hold signals to ±1/2L8B in 14 bits for
up to 12511sec. The 4860 is functionally laser trimmed at the
factory to correct offset, pedestal and gain errors, and is
designed to be used without external adjustments. If system
requirements call for tighter accuracies, units can be selected at the factory or adjustments can be made to the AID
or D/A used with the 4860.
In order to avoid oscillations, current limiting or performance variations over temperature, the 4860's output loading has certain restrictions. To avoid oscillation the largest
capacitive load is typically 250 pF. The largest recommended resistive load is 500n, although values as low as
250n may be used. Acquisition and sample-to-hold settling
times are relatively unaffected by resistive loads down to
250n and capacitive loads up to 50 pF. However, higher
capacitive loads will affect both acquisition and settling time.
1.0
0.9
- 0.8
~ 0.7
- 0.6
.~ 0.5
<-,0.4
Grounding and Bypassing
With proper grounding and bypassing, the 4860 meets
all its published performance specifications without any
additional external components. The device has four ground
pins (Pins 10, 15, 21 and 23), and all must be tied together
and connected to system analog ground as close to the
package as possible. It is preferable to have a large analog
ground plane beneath the 4860 and have all four ground
pins soldered directly to it. Pin 10 is particularly sensitive to
ground noise because most of the digital elements that
constitute the switch drive circuit are grounded to Pin 10.
Noise in the switch drive circuit couples directly to the main
op amp summing junction-the most noise-sensitive point in
any 8/H circuit. Most digital ground currents enter or leave
the 4860 through Pin 10, therefore, in order to keep the
output clean, care must be taken to ensure that no ground
potentials exist between Pin 10 and the other ground pins.
This is why Pin 10 must be tied to the analog and not the
digital ground system. For the same reason, the +5V digital
logic supply (Pin 9) should be kept as clean as possible. This
supply (as well as the ±15V supplies, Pins 24 and 22) is
bypassed to ground with a 0.0111F ceramic capacitor inside
the 4860. In critical applications, additional external 0.111Fto
111F tantalum bypass capacitors may be required.
......
go.
..........
"-
l\
/
45"
/
0.3
0.2
0.1
."
0.01 0.03 0.1
0.3
1.0
'"
o·
3.0 10.0
Frequencv (MHz)
Figure 1.
Track Mode Gain Amplitude and Phase Response
Aperature Jitter
The most common use of sample (track)/hold amplifiers
is as an input for AID converters to permit the accurate
digitizing of signals with slew rates (frequencies) much
higher than the AID alone could handle. A rule of thumb for
obtaining desired accuracy in successive approximation
type AID conversion is to ensure that the analog input signal
being converted does not change by more than ±1/2L8B
during the conversion. Applying this rule to any given AID
converter, one can calculate an input slew rate limit beyond
which accurate digitizing is impossible. The slew rate can
then be converted to a frequency limit if you choose to speak
in those terms.
Example: For a 12-bit 500ns AID converter with a
±2.5V input range, 1/2LSB is equivalent to .61 mV. If the
input is not allowed to change more than .61 mV in 500 ns,
theADC's input slew rate limit is±1.22 mV/l1sec. If one were
trying to accurately digitize a ±2.5V sine wave its frequency
would have to be less than 77.7 Hz.
Sample/Hold Command
A TTL logic "0" applied to Pin 11, or a logic "1" applied
to Pin 12 puts the 4860 into the sample (track) mode. In this
mode, the device acts as an inverting unity gain amplifier,
and its output follows (tracks) its input. A logic "1" applied to
Pin 11 and a logic "0" applied to Pin 12 puts the 4860 into the
hold mode, and the output is held constant at the level
present when the hold command was given. If Pin 11 is used
to control the 4860, Pin 12 must be connected to digital
ground. If Pin 12 is used to controlthe 4860, Pin 11 must be
tied to +5V. Pins 11 and 12 each represent 1 TTL load to the
digital drive circuit.
9-88
FAST, 12-BIT
TRACK/HOLD AMPLIFIER
4860
For example:
dvtdt (max)
1.22mVtl1s
=2.5rocosrot (Max)
=2.5ro
The 4860 has a ±50 psec aperture jitter. This means
there is a 100 psec period during which the input signal
should not change more than ±1t2LSB. If, for example, you
are using the 4860 StH infrontofa 12-bitAlDconverter, then
1t2LSB = 0.61 mY. The input signal slew rate limitation for
accurate digitizing is then 0.61 mVt100 psec or 6.1 Vtl1sec.
This is equivalenttothe highest slew rate one would encounter
in a ±2.5V sine wave with a frequency of 388 kHz. This is a
considerable improvement over the 78 Hz sine wave that a
12-bit, 500 ns ADC could accurately digitize without a StH.
Notice that 388 kHz to 78 Hz is the same ratio as 500 nsec,
the ADC's conversion time, to 100 psec, the 4860's aperture
jitter.
1.22mVtl15 = 57tf
77.7 (Hz)
= f (Max)
A sample/hold in front of an AID converter can "freeze"
the converter's input signal whenever a conversion is made.
Even though the StH reduces system throughput, because
the StH acquisition time has to be added to the AID conversion time, it makes it possible for the AID to accurately
digitize input signals with much higher slew rates (frequencies). How is this accomplished? Let's look at the timing for
a conversion that uses a sample/hold input buffer.
Once a StH (TtH) has acquired an input signal and is
tracking it, the s/H can be commanded to hold at any instant.
There is normally a small delay between the time the unit is
commanded to hold and the time it actually holds. This delay
is called aperture delay time or aperture time delay. It
normally does not present a problem because the hold
command signal can be advanced in time to make the
amplifier hold at the correct time. Aperture delay time can
vary as a given device takes sample after sample. The
sample-to-sample variation in aperture delay time is called
aperture jitter. Although aperture delay time is not normally
a problem, aperture jitter is a problem. This is because it is
impossible to control or compensate for aperture jitter. Since
we have no control during the period of aperture jitter, would
like our input signal to change as little as possible during this
period. To return to our rule ofthumb, we don't wantthe input
to change by more than ±1t2LSB. Therefore, if we're using
a StH in front of an AID converter, the slew rate limitation is
no longer ±1t2LSB during the conversion time but ±1t2LSB
during the aperture jitter time.
IrU~itl~: :~ dl: : ~:~t~ j~:\; ;~Jt s:~:~ ~I:;:~ dl~ : :~t~1: ~jl III
50
Figure 3.
150 200 250
Time (nsec)
300
Acquisition Accuracy vs Acquisition Time for 10V Step
This procedure, which determines how fast a signal a
given s/H permits one to digitize, assumes that the output
droop rate of the chosen sample/hold is low enough to keep
the AID's input constant to within ±1t2LSB during a conversion time. It also assumes that at the input slew rate
(frequency) of interest, the StH's output is not slew rate
(bandwidth) limited. Lastly, the fact that a given StH and
AID combination can accurately digitize the fastest portions
of a 388 kHz sine wave does not mean that the same
combination can be used to digitize that signal forreproduction
purposes. Nyquist criteria state that you have to sample a
388 kHz sine wave at twice its frequency, i.e. you have to
take a sample every 1.25IJ.Sec. The 48601ADC combination
must sample at least this fast to reproduce the input.
f~I~t:::=:=t==:j~1£~~JI
1
10
100
Input Signal Slew Rate (V IJI#C)
Aperture Jitter Window - l00psec
For v(t) - 10sinwt, dv/dt (max) - 20ri
Figure 2.
100
Accuracy Error Due to Aperture Uncertainty
9-89
FAST,12-BIT
TRACKlHOLD AMPLIFIER
4860
Using the 4860 with AID Converters
There. are two important considerations when using
S/Hs to drive successive approximation AIDs. The first is a
dual requirement-the S/H's output stage should exhibit a
very low impedance compared to the AID's input impedance, usually 1 to 10 kn, at frequencies up to five times the
AID's clock period; and the SIH should be able to recover
from current transients in a time interval smaller than the
AID's clock period. These requirements are based on the
fact that successive approximation AID's internal D/A converter changes its output current just priortothe determination
of each output bit, therefore, the StH will be required to sink
or source large, high frequency current transients and
recoverwithinoneclockperiod.lnthe hold mode the4860's
output impedance is typically 0.1Q. Its outP~ typically
recovers (to ±0.01 'Yo) from a 2mA step in less than 100 nsec.
The s~cond c~nsi~eration involves the S/H's sample-tohold tra~slent setthng time. If the same timing pulse that puts
the StH Into the hold mode initiates the AID conversion the
transient settling time has to be short enough to ensure'that
the AID has a stable, accurate input when it makes the final
decision on whether its MSB output should be a "1" or "0".
This decision normally takes place one clock period after a
conversion has begun.
In most applications by using the 4860 in front of a
successive approximation AID converter, the 4860's HOLD
or HOLD can be driven directly from the converter's status
output. The status output changes state when the converter
receives a convert command, and this change can be used
to drive the StH from the track to the hold mode. The reverse
change in state of the status output at the end of the
conversion can also be used to set the StH back into the
track mode.
9-90
.,"'TELEDYNE
COMPONENTS
TP0032
OPERATIONAL AMPLIFIER -
HIGH-SPEED, FET-INPUT
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The TP0032 is a high slew rate, FET-input, fully-differential operational amplifier. It features 85 dB open-loop gain,
a wide bandwidth (25 MHz @ AcL = +1), high-input impedance (1011 0), and high-output drive capabilities.
The TP0032 can be used as a direct replacement for
LH0032-type op amps and is far more capable. It features
the following performance improvements:
The Choice Device for All 0032 Applications
Open-Loop Gain ...•....................................•..... 85 dB
Settling Time to ±1% ..••.•...•.••..•..•..•..•..•..•......• 100 ns
Slew Rate ................•......•.....•.......•...............• 650V/lls
APPLICATIONS
•
•
•
•
High-Speed ADC Comparators
ADC and SHA Integrators
High-Speed Integrators
Video Amplifiers
1. Increased open-loop gain; improves linearity and
eliminates output voltage droop.
2. Superior second-stage biasing and decreased gain
sensitivity to the transconductance of the JFET input
yields faster, more consistent settling times.
3. The addition of supply current compensation over
temperature improves dynamic response versus
temperature.
4. Improved phase margin allows smaller compensation capacitance values to be used in low-gain
applications, which means higher slew rates and
faster settling times, and useful features for new
designs.
The standard TP0032 is specified for -55°C to +125°C
operation. The TP0032 High Reliability (HR) version is
specified for -55°C to + 125°C operation.
PIN CONFIGURATION
PIN
NO.
1
2
3
DESIGNATION
4
NC
OUTPUTCOMP
BALANCE/COMP
BALANCE/COMP
5
INVERTING INPUT
6
NONINVERTING INPUT
PIN
NO.
7
8
9
10
11
12
DESIGNATION
NC
NC
NC
-VCC
OUTPUT
+VCC
NC = NO INTERNAL CONNECTION
1108-1
BOTTOM VIEW
9·91
HIGH-SPEED, FET-INPUT
OPERATIONAL AMPLIFIER
TP0032
ABSOLUTE MAXIMUM RATINGS
Te
Supply Voltage ............................................. ±18V
Differential Input Voltage .............................. ±30V
Common-Mode Input Voltage ...................... ±Vee
Operating Temperature Range (Case)
.............................................. -55°C to +125°C
Storage Temperature Range ..... -65°C to +150°C
TSTG
DC CHARACTERISTICS: (Note 1) Vee =±15V, RL = 1 kn, Te = 25°C, unless otherwise noted.
Symbol
Parameter
Vos
Input Offset Voltage
Test Conditions
VosTC
Input Offset Vottage Drift vs Temperature
18
Input Bias Current
IsTC
Input Bias Current Drift vs Temperature
los
Input Offset Current
Min
TPOO32
Typ Max
-
TMINto TMAX
-
±2
±4
Average, T MIN to T MAX
-
±25
-
±10
±5
±100
TMIN to TMAX
-
TMINto TMAX
10sTC
Input Offset Current Drift vs Temperature
Open-Loop Voltage Gain
-
-
-
-
±2
±4
±25
±10
±5
±5
±10
-
±5
±12
±25
-
-
±5
±12
±25
±25
Average, T MIN to T MAX Doubles every II·C Doubles every II·C
pA
nA
-
-
-
70
70
85
83
-
50
70
-
50
70
-
50
70
50
70
-
dB
±10
-
±10
±12
1011 112
-
V
nllpF
1011 113
-
nllpF
±10 fi:13.5
-
V
±10 ft13.5
mA
n
PSRR
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
CMR
Common-Mode Range (DC Linear Operation) CMRR ~ 44 dB
ZID
Differential Input Impedance
-
±12
1011 112
ZICM
Common-Mode Input Impedance
-
10 11 113
-
Vo
Output Voltage Swing
±10 ±13.5
-
10
Output Current
±10 ±13.5
Isc
Output Short-Circuit Current
Ro
-
-
-
-
dB
dB
dB
N/A
-
-
-
90
-
±15
±18
±10
±15
±18
V
±17
±20
-
±17
±20
mA
N/A
Output Resistance (DC Open-Loop)
-
90
Vcc
Supply Voltage Range (Operating)
±10
Icc
Quiescent Supply Current
-
(Note 2)
-
-
CMRR
VCM = ±8V
JlV/·C
85
83
70
TMINto TMAX
mV
mV
±100 pA
±50 nA
Average, T MIN to T MAX Doubles every II·C Doubles every II·C
-
AvoL
±5
TPOO32-HR
Min Typ Max Unit
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
2. The TP0032 is not output short-circuit protected and neither are other vendors' 0032's.
AC CHARACTERISTICS: (Note 1) Vee = ±15V, RL = 1 kn, Cel = 4 pF, Ce2 = 100 pF, Te = 25°C,
unless otherwise noted.
Symbol
Parameter
TPOO32
Typ Max
Test Conditions
Min
350
650
-
-
600
-
SA
Slew Rate
Av=+l
GBWP
Gain-Bandwidth Product
f = 100 kHz, CC1
CC2= OpF
UGBW
Unity-Gain Bandwidth
Av=+l
-
25
-
t.
Settling Time (ACL = -1)
20V step/l%
20V step/O.l%
-
100
300
-
=0 pF,
TPOO32-HR
Min Typ Max Unit
350
650
-
-
MHz
-
25
-
MHz
-
100
300
-
ns
ns
-
NOTES: 1. Limits printed in boldf!lce type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
9-92
VlJls
600
-
HIGH-SPEED, FET-INPUT
OPERATIONAL AMPLIFIER
TP0032
APPLICATIONS INFORMATION
exact value will vary with the effects of layout and closedloop gain, and is therefore determined case by case.
When using the TP0032 in a noninverting configuration,
it may be advantageous to bootstrap the case and/or a guard
conductor to the inverting input. This practice will divert
leakage currents away from the non inverting input and
reduce effective input capacitance.
Wiring Recommendations
As with most high-speed op amps, the TP0032 is
sensitive to circuit board layout; Le., stray reactances. The
power supplies should be bypassed as close to pins 10 and
12 as possible. Use low-inductance capacitors, such as
0.01 JlF disc ceramics. Any other compensation capacitors,
if used, should be located as close as possible to the
appropriate pins to minimize stray capacitance. Good
grounding techniques, as always, should be used.
Heat Sinking
When operating the TP0032 at TA = +25°C, the case
temperature will be approximately +65°C. Although the
TP0032 is specified for operation without a heat sink, bias
current performance may be improved with the use of a
small heat sink, such as the Thermalloy 2240 or equivalent.
The case is electrically isolated, so it may be connected to
the heat sink. However, this will add capacitance to all pins
and will probably necessitate compensation readjustment.
Input Capacitance
The TP0032's input capacitance is typically 2-3 pF. To
compensate for this, it is recommended that a small capacitor be placed across the feedback resistor. The value of this
capacitor should be on the order of several picofarads. The
INPUT
_.--<> OUTPUT
;3>-,-1.!.-1
>-1!..!1,--_0 OUTPUT
INPUTS {
-Vee
10
9k.Q
1 k.Q
-Vee
=
Figure 2. lOX Buffer Amplifier
Figure 1. Offset Null
9-93
..
HIGH-SPEED, FET-INPUT
OPERATIONAL AMPLIFIER
TP0032
LMl13
iii"
12
:!!.
INPUT
Z
C
NIr-+-D OUTPUT
Cl
w
Cl
~
10
g
100
90
80 "70
i'.. G~IN
60
.......
50
'40 I----PHASE
30
20
10
0
" '"
=4&r
Cl
C2 = 1 pF
RL=l kQ
45
-
90
lk
10k
.......
i'.
"
135
180
.......
lOOk
1M
10M
FREQUENCY (Hz)
100M
Figure 6. Bode Plot (Unity Gain Compensation)
Figure 3. Output Short-Circuit Protection
2.5 ,---,.--.,---.--..,--,..--...,
z~ 2.0 1----t-.3oo,~
12
INPUT
o
!i 1 5 I--i-o.=--+----""~--+--+---l
iisZ 1.0
n...-',,,,,
Do.
>''-'--.....0
OUTPUT
•
ffi
~ 0.5 I---I---If---I--I--""f---J
Do.
o
Figure 4. Unity-Gain Amplifier
iii"
:!!.
Z
C
Cl
w
Cl
~
g
100
90
80
........
70
60
50 _PHASE'
40
30
20
10
0
"-
lk
10k
"-
I
GAI~
.......
25
50
75
100
125
TEMPERATURE (OC)
Figure 7. Maximum Power Dissipation
80
Cl =OpF
~=OpF
RL=l kQ
-"'"
.........~
0
45
90
135
.'\.
\.'\..
\'\..
lOOk
1M
10M
FREQUENCY (Hz)
iii" 70
w:2. 60
f---
"- "\..
"-'\
co
i:!!.
§l!i
W
OZ
Do.
81rl...
20
II:
10
~
Zll:
50
40
~g
30
w
180
\
o
10k
100M
lOOk
1M
10M 100M
FREQUENCY (Hz)
Figure 8. CMRR VB Frequency
Figure 5. Bode Plot (Uncompensated)
9-94
1
w
!{l
"- ......... r---...
-VCC
o
150
if
HIGH-SPEED, FET-INPUT
OPERATIONAL AMPLIFIER
TP0032
+20
~
w +10
I
I
I
CJ
~
g
...
24
J.VCC=±1SV
1 ,I.
0
::l
:( 22
E
;:- 20
AV=+1
RL = 1 len
~
-10
-20
i3
~
a..
iil
V
o
100
200
-"
9ofJ'/
fJ'jofJ/
~ 18
a:
a..
!;
o
~/
Z
\
\
300
400
16
14
,\fJ~/
12
10
500
5
TIME (ns)
Figure 9. Large Signal Pulse Response
r
10
15
SUPPLY VOLTAGE (V)
20
Figure 10. Supply Current vs Supply Voltage
•
9-95
NOTES
9-96
~,,"TELEDYNE
COMPONENTS
TP0033
HIGH-SPEED, UNITY-GAIN BUFFERIDRIVER AMPLIFIER
FEATURES
GENERAL DESCRIPTION
•
•
The TP0033 is a high-speed, high-input impedance,
unity-gain buffer amplifier that is pin, package and performance equivalent to the ubiquitous LH0033. This device
matches or exceeds the performance of its counterpart in all
applications, yet typically draws just ±14 rnA quiescent
current, versus ±20 rnA typical for the LH0033.
The TP0033 has a FET input stage which provides
high-input impedance (10 11 0), low-input bias current
(0.5 nA), and low initial input offset voltage (±10 mY). The
device operates with supply voltages from ±5V to ±20V
(single supply operation is permissible). With nominal ±15V
supplies, the TP0033 delivers a guaranteed output of ±12V
into 1 kn. Other key large-signal specifications are 1500 VI
JlS slew rate and 25 ns settling time for the unit to settle a
2V step (typical "flash" ADC full-scale input) to within ±1 %
(±20 mY) of final value.
A 100 MHz bandwidth, 2.9 ns rise time and 1.2 ns
propagation delay are key small-signal specifications that
further demonstrate the TP0033's suitability for highfrequency, signal-buffering applications.
The TP0033 is housed in a 12-pin TO-8 can. The
standard device is specified for -25°C to +85°C operation.
The High Reliability (HR) version is specified for -55°C to
+125°C operation.
Replaces All 0033's
High Speed
- Bandwidth ..................................... DC to 100 MHz
- Slew Rate ............................................... 1500 V/lls
Settling Time to ±1% (2V step) ......................... 25 ns
Low Quiescent Current ..•...•••........................±14 mA
•
•
APPLICATIONS
•
•
•
•
Input-Buffering Flash ADCs
CRT Deflection Yoke Drive
Coaxial Line Driver
Critical Military, Biomedical and Process Control
Environments
PIN CONFIGURATION
Pin
No.
Designation
Pin
No.
1
+Vcc
7
OFFSET TRIM
2
3
4
NC
8
NC
NC
NC
5
6
INPUT
9
10
11
12
OFFSET PRESET
0
Designation
03
0
0
5
6
I 02
-Vce
V'
0 1
OUTPUT
12 11 10
0
-
0
BOTTOM
VIEW
9·97
70
80
0
V+
NC = No internal connection
1109-1
4
90
III
HIGH-SPEED, UNITY-GAIN
BUFFER/DRIVER AMPLIFIER
TP0033
ABSOLUTE MAXIMUM RATINGS
Tc
+VCC- Supply Voltage ......... : ..................................... 40V
(-Vcc)
Input Voltage ................................................ ±Vcc
VI
Power Dissipation (See Figure 9) ................ 1.SW
Po
DC CHARACTERISTICS:
Symbol
Parameter
AVN
VoHage Gain
Vos
Input Offset Voltage
TSTG
(Note 1) Vcc = ±1SV, RL = 1
kO,
Operating Temperature Range (Case)
TP0033 .................................... -2SoC to +85°C
TP0033-HR ........................... -SSoC to +12SoC
Storage Temperature Range ..... -65°C to +1S0°C
Rs = 100n, Tc = 2SoC, unless otherwise noted.
Test Conditions
TMINtoTMAX
TPOO33
TPOO33-HR
Typ Max Min Typ Max
Min
0.96
0.98
1.00
-
±5
±10
-
±50
±0.5
-
-
±2.5
-
60
-
-
-
-
-
Vos TC
Input Offset Voltage Drift vs Temperature
18
Input Bias Current
PSRR
Power Supply Rejection Ratio
ZI
Input Impedance
1010
1011
Vo
Output Voltage Swing
±12
±9
±13
Average, TMIN to TMAX
TMINtoTMAX
RL= 100
Vee=±5V
(Note 2)
-
-
-
6
-
N!A
Output Resistance (DC Open-Loop)
-
6
Vee
Supply VoHage Range (Operating)
±5
±15
lee
Quiescent Supply Current
-
±14
±12
Ise
Output Short-Circuit Current
Ro
Vee =±5V
PD
Quiescent Power Dissipation
Vee =±5V
-
-
0.96 0.98
420
120
-
-
-
±5
±50
±0.5
-
Unit
1.00
VN
±10
±15
mV
mV
±250 !lVrC
±2.5 nA
±50 nA
60
1010 1011
-
dB
±12 ±13
±9
-
-
V
V
VP-P
-
Q
-
6
-
N!A
-
mA
6
10
Q
±20
±5
±15
±20
V
±22
-
±14
±12
±22
mA
mA
420
120
660
10
660
-
-
mW
mW
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
2. The TP0033 is not output short-circuit protected and neither are other vendors' 0033's.
Peak instantaneous output current must not exceed ±250 rnA.
Continuous output current must not exceed ±1 00 rnA.
AC CHARACTERISTICS:
(Note 1) Vcc = ±1SV, RL = 1
kO,
Rs = son, Tc = 2SoC, unless otherwise noted.
Test Conditions
Min
TPOO33-HR
TPOO33
Typ Max Min Typ Max Unit
Symbol
Parameter
SR
BW
Slew Rate
Bandwidth (-3 dB)
VIN = 1.0 VRMS
-
100
c1>NL
Phase Non-Linearity
BW = 1 Hz to 20 MHz
-
2
1000 1500
1.2
-
<0.1
-
ts
Settling Time
2V step!l0/0
-
25
tr
Rise Time
.1.VIN= 0.5V
-
2.9
tpd
THD
Propagation Delay
.1.VIN= 0.5V
f> 1 kHz
Total Harmonic Distortion
-
-
1000 1500
-
100
2
-
-
MHz
0
25
-
ns
2.9
-
ns
1.2
<0.1
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100%
production tested.
.
9·98
V/IJ.S
ns
0/0
HIGH-SPEED, UNITY-GAIN
BUFFER/DRIVER AMPLIFIER
TP0033
APPLICATIONS INFORMATION
Offset Adjustment
closely as possible to the case. If pins 1 and 12 or pins 9 and
10 are not tied together, each pin should be decoupled by a
low-inductance (0.1 I!F) ceramic disc capacitor, grounded
as close as possible to the case.
The TP0033 is factory-trimmed for low initial offset
voltage. This is achieved by laser trimming and is implemented by tying pin 6 (offset preset) to pin 7 (offset adjust
input). If the offset needs adjusting for any reason (see
"Single or Unbalanced Power Supplies"), it can be done by
using the offset null scheme shown in Figure 1. If an
adjustable offset is not needed, pin 7 must be tied to pin 6.
(Pin 7 cannot be left open.)
Reactive Loading
The TP0033 output can drive large (several thousand
pF) capacitive loads and long, properly terminated coaxial
lines without tendency to oscillate. Peak capacitive output
current levels should not exceed 250 mA.
Current Limiting
Single or Unbalanced Power Supplies
The output of the TP0033 is not short-circuit protected
and should not exceed ±1 00 mA steady-state or ±250 mA
peak instantaneous current. For overcurrent protection, the
maximum output current of the TP0033 can be limited by the
use of current-limiting resistors as shown in Figure 2, or by
an active current-source circuit as shown in Figure 3. Whether
or not the current is limited, pins 1 and 9 must be connected
to +Vee and -Vee, respectively.
The TP0033 can operate from unbalanced power supplies, such as the +5V/-12V rails prevalent in MaS-based
logic systems. An output offset voltage will result, but is
correctable by the nulling method shown in Figure 1. It is
predictable (with sufficient accuracy) as follows:
Offset (V) = (1-Gain) (I+Veel- I-Veel)/2
gain is typically 0.985; therefore:
Wiring Recommendations
Offset (V) = 0.0075 (I+Veel- I-Veel)
The TP0033, like any high-speed device, is sensitive to
layout inductances; therefore, ground planes are recommended. For best performance, each power supply should
be individually decoupled; i.e., bypassed to ground. If pin 1
is tied directly to pin 12 and pin 9 is tied directly to pin 10
(Figure 1), connect low-inductance (0.1 I!F) ceramic disc
capacitors directly to pins 10 and 12 and ground them as
Heat Sinking
Idling in a +25°C ambient environment, the TP0033 has
an approximate case temperature of +65°C. For best
performance, a heat sink (Thermalloy 2240 or equivalent) is
recommended, particularly for extended temperature
operation .
....--_--0 +Vee
OFFSET
PRESET
(OPEN)
INPUT
INPUT
OUTPUT
OFFSET
ADJUST
loon
RANGE =±15mV
'--+--Cl - vee
+Vee
-Vee
RUM ~ +Ise = -Ise
Ise"l00mA
Figure 2.
Figure 1. Basic Offset Null
9-99
Resistive Output Current Limiting
III
HIGH-SPEED, UNITY-GAIN
BUFFER/DRIVER AMPLIFIER
TP0033
INPUT
>---=--:.-1-.... OUTPUT
INPUT
'SELECT R ~ SOQ FOR BEST PULSE
RESPONSE: 1% < OVERSHOOT < 2%.
FOR ALL CASES, ENSURE THAT:
AVIN x CL SIO S±250mA
At
Figure 5.
Capacitive Drive
~~--~-O-VCC
Q 1 = Q3 = 2N2905
Q 2 Q 4 = 2N2219
=
R
Figure 3.
A
+3
~
«
C!I
Active Current-Source Output Current Limiting
Z
CL=33t~
0
I
RL=50Q--
~
~
>
AVIN x CL S 10 S ±250 mA
At
Coaxial Cable Driver
9-100
'/
-10
Figure 6.
FOR ALL CASES, ENSURE THAT:
~~
RL= 1 kQ
o
IN
q \
\
~
o
Figure 4.
l
J
CL=l20pF
0.6V
LIM ~ ILiM
3
10
30
FREQUENCY (MHz)
100
Frequency Response for Various Loads
HIGH-SPEED, UNITY-GAIN
BUFFERIDRIVER AMPLIFIER
TP0033
60
2.5
~ 50
~2.0
m
:!!.
o
+VCC
II:
..,w
40
>
30
..J
II.
II.
iiiII:
20
~
10
w
Q
!< 1.5
-VC~'"
W
II:
II.
0.01
jg
i5 1.0
g
....
II.
....
::l
::l
0
o
3
Power Supply Rejection Ratio
f
-OUTPUT
I
I
I
I
-0
-10
-12
-14
\
\
\
t+-- {INPUT
IJ
o
10
Figure 8.
1\
\
\
\
,
VCC=±15V
RL=1k.Q
RS = 500
20 30 40
TIME (ns)
50
60
~
Figure 9.
"\
I
+2
0
-2
-4
~
~
~ 0.5
+12
CI
I"-~/~
,~
II:
0.03
0.1
0.3
FREQUENCY (MHz)
+10
....'..J"
"~"of.
II.
Figure 7.
+8
+6
~ +4
w
r--..
z
'"'"
~
t3
-
70
Large Signal Response
9-101
~
50
~
roo
TEMPERATURE (OC)
1~
Maximum Power Dissipation
150
NOTES
9-102
~~TELEDYNE
COMPONENTS
TP3554
OPERATIONAL AMPLIFIER -
HIGH-SPEED, WIDE BAND
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TP3554 is a fully differential, wideband operational amplifier with 2 GHz gain bandwidth product, 1200 VI
Jls slew rate, and ±12V, ±125mA output. Settling time for a
10V step to 0.01 % is guaranteed less than 250 ns, and
external cornpensation allows users to optimize bandwidth,
slew rate, or settling time in different applications.
The TP3554 is an improved second source to the BurrBrown BB3554. In most applications, the TP3554 is a dropin replacement for the BB3554, having similar bandwidth
and slew rate characteristics with similar compensation. In
other applications, the TP3554's superior design approach
will solve many of the problems encountered with the
BB3554. The TP3554's improved interior loop stability
overcomes the BB3554's pronounced tendency to ring or
oscillate at 120 MHz, especially at lower gains (higher
compensations). The improved loop stability also results in
an improved capacitive load capability. The TP3554 does
not have input overload problems. Input slew rate does not
affect settling time, and there are no input rise time restrictions. This eliminates many of the problems encountered in
pulse-amplifier applications. The TP3554 has a much lower
quiescent current drain, ±14 mA typical, (±20 mA maximum) and a lower short-circuit output current.
The standard TP3554 is housed in a TO-3 metal can
and is specified for -25°C to +85°C operation. The TP3554
High Reliability (HR) version is specified for -55°C to +125°C
operation.
Stable at Low Gain
Gain Bandwidth Product ............•................... 2 GHz
Slew Rate ....•.............................................. 1200 V/Jls
Output ....•.•.....•••...•...•.........•............•. ±12V, ±125 mA
Low Quiescent Current ....•.....••.••..•....•....•.... ±14 mA
Operating Temperature (-HR) •...... -55°C to +125°C
APPLICATIONS
•
•
•
•
•
Pulse Amplifiers
Fast BufferlFollowers
Fast D/A Converters
Video Instrumentation
Video Frequency Filters
ABSOLUTE MAXIMUM RATINGS
Vcc
VID
VICM
Tc
TSTG
Supply Voltage ............................................. ±18V
Differential Input Voltage .............................. ±25V
Common-Mode Input Voltage ...................... ±Vcc
Operating Temperature Range (Case)
TP3554 .................................... -25°C to +85°C
TP3554-HR ........................... -55°C to +125°C
Storage Temperature Range ..... -65°C to + 150°C
PIN CONFIGURATION
PIN
NO.
DESIGNATION
1
OUTPUT
2
+Vcc
COMPENSATION (PIN 3 TO 1)
3
4
5
6
7
8
OFFSET ADJUST
INVERTING INPUT
NONINVERTING INPUT
-Vcc
OFFSET ADJUST
BonOMVIEW
111Q.1
9·103
HIGH-SPEED, WIDEBAND
OPERATIONAL AMPLIFIER
TP3554
DC CHARACTERISTICS:
(Note 1) Vee
=±15V, RL = 1 kn, Te =25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Vos
Input Offset Voltage
VosTC
Input Offset Voltage Drift vs Temperature
18
Input Bias Current
18 TC
Input Bias Current Drift vs Temperature
los
losTe
Input Offset Current
Input Offset Current Drift vs Temperature
AVOL
Open-Loop Voltage Gain
Average, T MIN to TMAX
Common-Mode Range (DC Linear Operation) CMRR~64 dB
10
Output Current
Isc
Output Short-Circuit Current
Ro
Output Resistance (DC Open-Loop)
VCC
Icc
±10
±50
-
±0.5
±2
±20
±50 IN/"C
±50 pA
±10
mV
-
CMR
Output Voltage Swing
-
Average, TMIN to TMAX Doubles evelY 11 °e Doubles evelY 11°C
100 106
100 106
RL =1000
90
96
90
96
-
Power Supply Rejection Ratio
Differential Input Impedance
±2
±20
-
Common-Mode Rejection Ratio
Common-Mode Input Impedance
±0.5
-
PSRR
ZICM
Vo
-
TP3554
TP3554-HR
Typ Max Min Typ Max Unit
Average, T MIN to TMAX Doubles evelY 11°C Doubles evelY 11°C
±2
±2
-
CMRR
ZID
Min
VCM = +5V/-10V
80
110
-
80
110
70
86
-
70
86
-
+B/-13
-
+8/-13
-
10"112
-
RL= 1000
1011 112
±10.5 ±12
-
±100 ±125
-
-
±150
±100
Supply Voltage Range (Operating)
±8
±15
Quiescent Supply Current
-
±14
(Note 2)
-
-
1011 112
1011 112
±10.5 ±12
±100 ±125
-
-
pA
dB
dB
dB
dB
V
OllpF
OllpF
V
mA
-
±150
-
±100
-
0
±18
±8
±15
±18
V
±20
-
±14
±20
mA
mA
NOTES: 1. Limits printed in boldface type are guaranteed and 100"10 production tested. Limits in normal font are guaranteed but not 100"10
production tested.
2. Typical output resistence is 200 at f = 10 MHz.
AC CHARACTERISTICS:
(Note 1) Vee = ±15V, RL = 1
kn, Ce = 0 pF, Te = 25°C, unless otherwise noted.
P3554
Typ Max
Symbol
Parameter
Test Conditions
Min
SA
GBWP
Slew Rate
RL = 100n
1000 1200
Gain-Bandwidth Product
@AOL= 10
@AOL=100
@ AOL= 1000
150 225
425 725
1000 2000
-
UGBW
Unity-Gain Bandwidth
t.
Settling Time (ACL = -1, Cc = 12 pF)
10V step/1%
1OV step/O. 1%
10V step/0.01"lo
en
Input Voltage Noise Density
f = 1 kHz
CL
Capacitive Load (maximum w/o oscillation)
-
-
-
TP3554-HR
Min Typ Max Unit
1000 1200
-
150 225
425 725
1000 2000
-
90
-
-
90
40
100
150
-
-
-
40
100
150
250
10
-
-
10
75
-
-
75
-
-
9-104
MHz
250
ns
ns
ns
-
pF
-
NOTES: 1. Limits printed in boldface type are guaranteed and 100"10 production tested. Limits in normal font are guaranteed but not 100"10
production tested.
V/l1s
MHz
MHz
MHz
nVNHz
HIGH-SPEED, WIDE BAND
OPERATIONAL AMPLIFIER
TP3554
110
100
I'.
iii'
:!:!.
Z
<
60~
III
lila:
z
a: O
w
:=i=
0.
o.W
W
40 ~
RL =
200n
1 -I 1
100k
0 0
80 ~
..,
a:
70
60
50
40
30
20
10
I
40
",CL=50P~~
30
~
iii' 20
:!:!.
Z
10
Cl
0
- ' - - - 0 VOUT
Optional Offset Adjustment
If the TP3554's guaranteed offset error is too large for a
particular application, the initial offset may be adjusted to
zero by connecting a 20 kn. linear potentiometer between
pins 4 and 8, with the wiper connected to the positive supply,
as shown in Figure 7. A small, non inductive potentiometer is
9·106
OFFSET
ADJUST
Figure 7. Unity Gain Inverter
HIGH-SPEED, WIDE BAND
OPERATIONAL AMPLIFIER
TP3554
Slew Rate
10k(}
Slew rate is dependent upon compensation. Decreasing the compensation capacitor value will increase the
available slew rate. Stray capacitances may have the same
effect as the compensation capacitor. To avoid limiting the
slew rate performance, stray capacitances should be minimized.
>-----OVOUT
-=
TP3554
Rgure 10. Inverting Gain of 100 Amplifier
>-'--......- 0
VOUT
DUMMY
SUMMING
JUNCTION
TP3554
ERROR
SIGNAL
.---------<1>--<1>-0
Rgure 8. Follower
Heat Sinking
The TP3554 does not require a heat sink for operation
in most environments. However, the use of a heat sink
reduces the case temperature rise and results in lower
junction operating temperatures. At extreme temperatures
and under full load conditions, a heat sink will be necessary
(as indicated in Figure 6). When heat sinking the TP3554, it
is recommended the heat sink be connected directly to the
amplifier case and the combination not be connected to the
ground plane. The addition of a heat sink to an alreadyfunctional circuit will probably require slight compensation
adjustment for optimum performance, due to the change in
stray capacitances. The added stray capacitance to each
pin from the heat sink will depend on the thickness and type
of heat sink used.
1 kQ
~'"
TP3554
HP5082-2835
330Q
5.6kQ
Figure 11. Typical SeHlingTime Test Circuit
1.2pF
>'-......-OVOUT
Figure 9. Inverting Gain of 10 Amplifier
9·107
NOTES
9-108
Section 10
Video Display Drivers
Display NO Converters
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
•
~"'TELEDYNE
COMPONENTS
1900
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The 1900 isa high performance monolithic variable gain
transconductance amplifier with a high voHage open collector output capable of driving a video display (CRT cathode)
directly. Typical rise times of 2.4ns are achieved using a
peaking inductor with a 2000 load resistor and a 6pF total
load (CRT and parasitic capacitance).
Differential inputs and a linear adjustable gain stage
with an output offset adjustment make the 1900 versatile
and well suited for many applications. The TIL BLANK input
will set the output to a pre-determined black level independent of signal input.
The 1900 is available in a 24-pin DIP power-tab package. A suitable heat sink must be attached to maintain the
junction temperature with the recommended operating range.
Rise Time into a 6pF load •••....••..........••....•.•..••• 2.4ns
Output Signal ................................................. SOV p-p
Linear Variable Gain •••.••.•••.••.••.••••..••.•..•..•..•• 0 to 100
24-Pin Power-Tab Package
APPLICATIONS
•
•
High Resolution Monochrome Displays
High Resolution RGB Displays (Three Packages)
FUNCTIONAL DIAGRAM
lIeB
BLANK
110
IIOF"
VIN+
VINIIIQ
..,r-
QNDD
1900
QNDA
IIREF"
1053·1
+4------a::;:m
10-1
I
~
IICC
VEE
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
1900
PIN CONFIGURATION
Pin
No.
Pin
No.
Designation
GND
2
3
4
5
6
VREF
VOF
VIG
GNDA
VIN+
VINVEE
VEE
Vee
7
8
9
10
11
12
Designation
GNO
24
23
22
21
20
19
18
GND
GND
GND
SUB
SUB
GNO
17
GND
GND
GND
GNO
16
15
14
13
BLANK
GND
GND
SUB
SUB
VOUT
VOUT
NC
NC
Ves
Ves
Vee
Vee
GNO
GNO
NC = NO INlERNAL CONNECTION
ABSOLUTE MAXIMUM RATINGS* TA = 2S0C unless otherwise noted.
TSTG
VVAA
VVCB
Vvcc
VVEE
VDIFF
VCM
Operating Temperature Range (Junction)
................................................................ +lS0°C
Storage Temperature ................ -SSoC to +lS0°C
Output Signal Supply, wrt VVCB ............................ 6SV
Common Base Supply .................................. 20V
Positive IC Supply ......................................... 12V
Negative IC Supply ...................................... -12V
Differential Input Voltage, Signal ..................... 2V
Common Mode Input Voltage, Signal ........ ±2.0V
VVIG
VVOF
VBIANK
IVREF
Ts
Gain Input Voltage .......................................... 6V
Offset Input Voltage ........................................ 6V
Blank Input Voltage ......................................... 6V
Reference Output Current.. ......................... -SmA
Lead Temperature (solder <10 sec) ........ +260°C
Thermal Characteristics
R9JC
Thermal Resistance (Junction to Case)
................................................................. +6CIW
"An absolute maximum rating defines a bias, mechanical stress, or environmental condition beyond which the device may become unserviceable.
The 1900 is static sensitive. Proper handling techniques for static·sensitive parts should be employed.
TYPICAL POWER CONSUMPTION TA= 2S0C Power Dissipation at VVAA = 70V, RL = 2000
Vo - VBLACK
Duty Cycle %
o
o
35
35
50
100
80
80
IC Po (Watts)
1.6
7.8
6.5
5.6
Load Po (Watts)
Total Po (Watts)
o
1.6
13.9
11.4
15.6
6.1
4.9
10
10·2
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
1900
AC ELECTRICAL CHARACTERISTICS: VEE = -10.5V, Vee = +10V, VAA = +70V, Rl = 2000, VBLANK = O.4V,
VIN"::; 725mV, TA = 25°C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
BW3dS
t,
Bandwidth, 3dB
Rise Time, Output
VYOF = OV, RL = 50.0
200
-
t.
Settling Time
MHz
ns
ns
ns
gm
Transconductance
RL = 0, tr(YIN) = 400ps
RL = 200.0. t,(YIN) = 1ns. CL = 6pF (Note 1)
90% point to 100% ±2%. no peaking
network. CL = 3.5pF
VYIG= 5.0V
VYIG= 1.0V
VYIG= O.OV
VYIG = 4.0V. VYOF = 1.0V
VYIN = 0.20V. VYOF = 1.0V
-
-
LEA
LEGA
TD
RYIN
CYIN
NOTES:
Amplifier Linearity Error
Gain Adjust Linearity Error
Thermal Distortion
Signal Input Impedance
Signal Input Capacitance
-
-
400
70
-25
-
-
10k
VYIN= O.OV
VYIN= O.OV
1.75
2.04
-
2.8
6
600
mS (Note 2)
110
mS
25
mS
±2 %GS (Note 3)
±2
%
±2
%
-
20k
2
-
n
pF
1. Total load capacitance on Ihe output node of the Ie including approximately 3pF load capacitor. 2pF parasitic board capacitance. and
1pF parasitic probe capacitance. with a peaking inductor as shown in the typical connection diagram.
2. "5' • Siemens (IN).
3. '%GS' means percent of grey scale, referring to RS·343 standard video levels.
DC ELECTRICAL CHARACTERISTICS: VEE = -10.5V, Vee = +10V, VAA = +70V, Rl = 2000, VBLANK = O.4V,
TA = 25°C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VREF
Iycc
Reference Output Voltage
10=2mA
5.25
40
-65
21
-600
-400
0.5
0.5
-50
-1
-1
-
5.75
70
-100
40
-400
-200
10
10
V
mA
mA
mA
50
1
1
25
120
2
10
1
IlA
mA
mA
mA
mA
mA
mA
mA
dB
IYEE
Iycs
ISLANK
IYOF
IYIG
IYIN
10
LllcfLlT
LllolLlVIG
LllolLlVIN
CMRR
PSRR
Positive Supply Current
Negatiye Supply Current
Common Base Supply Current
Blank Input Current
Offset Adjust Input Current
Gain Adjust Input Current
Signal Input Current
Output Current
Output Current YS Temperature
Output Current YS Gain Adjust
Output Current YS Signal Adjust
Common Mode Rejection Ratio
Power Supply Rejection Ratio
VSLANK = O.4V
VSLANK = 2.4V
VYOF= 1V
VYIG= 5V
VYIN= OV
VSLANK = 2.4V. VYOF = 1.0V
VSLANK = 2.4V, VYOF = 3.0V
VYIN = O.OV. VYOF = O.OV. VYIG = 4.0V
VYIN = O.OV. VYOF = 5.0V. VYIG = O.OV
TA = +25·C to +70·C
VYIN = OV. LlVYIG = 5.0V
VSLANK = 2.4V. LlVYIN = 0.3V
VCM =±0.5V
VYEE. VYCC = ±5%
10-3
80
-2
-10
-1
25
-
-
-
-
-
40
30
-
IlA
IlA
IlA
IlA
dB
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
1900
YEEo---~~--~----~----~~--------~~--------~
C-10.'SY)
::H1-
Y A C+70Y)
2_U _F'___- t
100V
R~
200
1011
.,r
1900
"
YO~----------------~
'So
~~[:>-------~~B~ANK
note:
~U"'PS CRT CATHODE.
PROTECTION CIRCUITRY.
AND PARASITIC C•
'C~OAD
• 1.12.13 • .1.4.15
22.23.24
High current ground
Typical Connection Diagram
714
~'..'r···+J·3~··············4'..'.......'...'.'~
lSYNC Period
2 BLANK only period
3BLACK period
4Video Signal
Typical Video Signal
10·4
",y
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
1900
APPLICATIONS INFORMATION
VIN+, VINVIN+ and VIW are the analog input pins. It is recommended that signals applied to these inputs be kept within
±1.3V with respect to ground. The input pins accept RS-343
signals of VVIN = ±0.714mV pop, and will operate properly
with common mode range of ±0.5V with respect to ground
(excluding signal). Although large offsets can be handled
safely without damage to the device, output linearity suffers
and therefore is not recommended.
VIG is the overall DC gain control that will vary the device
gain from 0 to 80. An internal reference supply, V REF (Pin 2),
provides the 5V nominally needed to drive the gain and
offset inputs (see typical connection diagram). Normally a
5kf.l potentiometer between VREF and ground varies the
gain, but an external source can be used, instead of VREF,
with sorne additional degradation of gain stability with temperature.
Gain control through VIG is a linear relationship. Zero to
100% of the gain range of 0 to 100 is achieved by varying this
input from 0 to 5 volts. This yields the following relationship
for overall voltage gain of this device (for 10 ~250mA):
VAA - Vo = VIN· gm· RL
VAA - Vo
= VIN(V) (VIG(V)· 0.1
• RL)
The overall gain of this device can vary by ±20% due to
normal process variations of internal components «150ppm/
°C). ·If multiple devices are used in a system provisions
should be made so that they all track thermally (i.e., a
common heat sink), to offset any changes with varying
ambient conditions.
VOF
VOF is an input control which sets the output quiescent
current and therefore the output offset voltage (see Black
level). Output quiescent current can be adjusted from 5mA
to 55mA when VOF is adjusted from 0 to 5.5V. Normally
adjustment is done by using a 5kf.l potentiometer between
VREF and ground (see typical application diagram).
TYPICAL RGB CONFIGURATION
r----,--------------__________________
741
~REF
.--_ _ _ _jV oc:
'1r1900
vo 1-+----+
RED
'r-_ _ _jVOF
r-----~v
::~r1900
VO
r
--_OJ
r-~--~
~~~n Hw., Sink
.1,.nCh Sell.
,. .....
".vLc:._)
GREEN
r-_ _ _lvOF
REF
~____~vOC:
:
. . . . . . . . . .i
• • VO~________~
1900
BLUE
For color tracking the output reference voltage of one device should be buffered and used to drive all three devices. The monolithic construction of this
device will allow tracking from chip to chip. To ensure uniform temperature in multi-Chip circuits, a single heat sink should be used.
10-5
MONOLITHIC, HIGH VOLTAGE
VIDEO DRIVER FOR CRT MONITORS
1900
BLANK
Vo
When asserted (Blank =TIL High), this input disables
the video signal and allows the output to rise to the predetermined blank level independent of the VOF control when
VOF is between 0 to 3V. Above 3V there is some interaction
between VOF and the Blank level. Blank is independent of
the input signal.
The output of the 1900 is an open collector of a cascode
circuit. This output works with nominal output supplies of VAA
=+70V. The high voltage supply must be greater than any
applied VCB voltage for proper operation. The 1900 drives
loads up to 250mA. Optimum performance can be achieved
when a peaking network is used (see typical connection
diagram).
BLACK
Black level is the output voltage developed across the
external resistor load that is achieved with OV video input.
This level can be modified by the quiescent operating point
setup at the VOF input (Pin 3). Adjustmentsfor output current
from 5mA to 55mA are easily made by varying the bias as
VOF from OV to 5.5V.
VREF
VREF is a bias reference made available for ease in
adjusting the offset, and gain inputs. This is a zener reference with a nominal output voltage of 5.5V ±5% which can
source up to 4mA.
VeB
The output stage consists of a common-base highvoltage stage and a high-speed low voltage current amplifier in a cascode arrangement. The VCB input is the base
connection to the common base device of this stage. Care
should be taken to provide a stable DC voltage at this point
of nominally +10V. High frequency compensation at this
input is required to avoid output oscillations. A series 150
resistor with a 15pF capacitor to ground is recommended
(see typical connection diagram). Smaller values of this RC
combination will improve output rise/fall times, but can
cause output oscillations near 330M Hz.
SUB
SUB is the internal connectiontothe substrate and must
be connected to VEE, the most negative voltage applied to
the device. Proper bypassing of the substrate supply, SUB
(Pins 20,21) and the VEE supply (Pins 8,9) is required to
prevent output oscillations.
Power Supply
A +10V and -10.5V supply are required for proper
operation. These supplies can be set at ±12V for convenience but this will add additional heat through power dissipation internal to the package. The high voltage supply can
be any voltage above the VCB supply, but not greater than
VCB plus 65V. To achieve good performance from the 1900,
close attention to high frequency grounding practices and
printed circuit board layout is mandatory.
Supply Sequencing
Power supply sequencing is important to avoid internal
device latch-up. To avoid sequencing problems external
diodes should be placed from VEE to ground, from ground to
Vcc and from Vcc to the output supply VAA (see typical
connection diagram). With the external diodes in the circuit
the most negative supply, VEE, should be turned on first.
Power Dissipation
The 1900 dissipates a large amount of power due to
different speed and load driving requirements. The PowerTab package provides a low thermal resistance path from
the chip to an external heat sink. Care should be taken in the
board design to provide sufficient heat sinking capacity to
allow operation over the intended operating range. When
mounting to a chassis the device tab (heat sink) is attached
to VEE (-10.5V). II is recommended that a low thermal resistance insulator be used when attaching to a grounded
chassis.
Initial Step
Initial setup of the device requires proper setup of the
VOF and VIG inputs for balanced riselfall times. If too little
quiescent current is allowed it will slow the output rise time
and limit eventual bandwidth.
10-6
~~TELEDYNE
COMPONENTS
1902
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
FEATURES
APPLICATIONS
•
•
•
•
•
Output Signals Into 10 pF ............................. 90 Vp.p
Rise and Fall Times @ 50 Vp_p ............................... 2.5 ns
Linear Gain Adjustment for Matching
Versions Available to Match Specific CRT
Requirements
CRT Monitors
- Projection
- High-Resolution Monochrome
- High-Resolution RGB
STANDARD CONFIGURATION DIAGRAM
+HV
~
+15V ! - - - - - - - - - - - < l I - - - -......-,
lliF +
-10.5V f-----.---..-~.
T
1 F
0.1
0.1
~'"
1902
~.~
\7
+
II+R
IIFF
2211F
VEEr4V~E~E+_5V=EE~-~~-----;-H-V-R-ES-;-HV-BU-F-F~ER
16,17
0.01
IIF~
Lp
20,21
0.01
IIF~
TO BIAS
CIRCUITRY
23
VOUT (TO CRT)
~ BLANK
25 CATHODE CURRENT
-VIN o-t.:...7-i""""'""----....~l..
+VIN o-t-"s--a..""'--------'(y
5 kil
22
NC
24
NC
<....I---+--+-......---'''+'-~
1,2,14,15, lS, 19,28,29,30
1054-1
10-7
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1902
GENERAL DESCRIPTION
The 1902 is a high-performance, high-voltage amplifier
designed to drive the cathode in high-resolution, highbrightness CRT monitors and projection displays.
The 1902 is replete with differential inputs, blanking
control, linearly-adjustable gain stage, adjustable offset,
and a differential emitter-follower output stage. The 1902 is
capable of driving 10 pFto 20 pF loads, can be driven directly
from a standard video DAC, and is RS170 and RS343
compatible.
The 1902 has three variants for different applications.
The internal high-voltage resistor and output transistors are
varied to strike the optimum balance between output voltage
from 40V to 90V, and rise/fall times from 2.2 ns to 4.5 ns. The
1902-0 has no internal high-voltage resistor, thereby allowing the designer to select a high-voltage resistor to suit the
specific application.
The 1902 is housed in a hermetically-sealed, 30-pin
flat pack with SO-mil center pins on two sides. It has mounting
flanges suitable for 4-40 screws. The 1902-X is specified
for -2SoC to +8SoC operation. The 1902-X-HR is specified
for-S5°C to +12SOC operation.
PIN CONFIGURATION
PIN
NO.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DESIGNATION
GND
GND
BLANK
VEE
VEE
VEE
-VIN
+VIN
GND
GND
VGAIN
VOFF
VREF
GND
GND
PIN
NO.
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DESIGNATION
3O-Pin Flat Package
GND
GND
GND
o o o
VCC
VCC
GND
NC
~~
VOUT
NC
HVBUFFER
HVBUFFER
GND
GND
HVRESISTOR
HVRESISTOR
1902
15
o o o
HV = HIGH VOLTAGE
NC = NO INTERNAL CONNECTION
ABSOLUTE MAXIMUM RATINGS
VHV
Vcc
VEE
VIDF
VICM
VIG
VIOS
VBLANK
IRP
IREF
TC
Pull-Up Resistor Supply ................ (VHV Max +5V)
Positive IC Supply ........................................ +17V
Negative IC Supply ...................................... -12V
Differential Input Voltage ................................ +2V
Common-Mode Input Voltage ........................ ±2V
Gain Adjustment Input Voltage ...................... +6V
Offset Adjust Input Voltage ............................ +6V
Blank Input Voltage ........................................ +6V
Total Current Through Rp (Note 1) .......... 290 mA
Reference Output Current .......................... -S mA
Operating Case Temperature Range
1902-X ..................................... -2SoC to +8SoC
1902-X-HR ............................ -55°C to +125°C
TSTG
Ts
10-8
Operating Junction
Temperature Range .................. -SSoC to +150°C
Junction-to-Case Thermal Resistance ..... 10°C/W
(for QCAS and Control IC)
1.2soC/W
(for Rp internal)
Storage Temperature Range ..... -55°C to +1S0°C
Lead Temperature (Soldering, <10 sec) ... +260°C
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1902
ELECTRICAL CHARACTERISTICS: Te =+25°C, VEE =-10.5V, Vee = +15V, VHV = Max, that is: 120Vfor
1902-0,2 and 70V for 1902-4, VBLANK = TTL Lo, VIG = VOF = ±VIN = OV, Cl = 10 pF<2), unless otherwise noted.
Symbol
Parameter
Test Conditions
Input
VIN
Input Vottage Range
Referenced to Ground,
Excluding VCM
Min
Typ
Max
-
-
iO.714
Is
Input Bias Current
-50
VCM
CMRR
Input Common-Mode Range
-o.S
Common-Mode Rejection Ratio
-
VCM =±O.SV
40
RIN
Signal Input Impedance
10
20
CIN
Signal Input Capacitance
-
2
VOF
Offset Adjust Input Voltage
IOF
Offset Adjust Input Current
VIG
Gain Adjust Input Voltage
Gain Adjust Input Current
IIG
Digital Inputs
Input Logic "0" Current
ill
IIH
Output
Vo
Rp
VIJ.S
0
VOF= IV
O.S
VIG= SV
O.S
0
VBLANK = OAV
-600
Input Logic "1" Current
VBLANK = 2.4V
-400
1902-0, :2
Output Voltage
Range, Peak-to-Peak 1902-4
VHV = Max (Note 3)
VHV= Max
Rp is External, User-Selected
Internal Pull-Up
Resistor
1902-0
1902-2
1902-4
VI!. in BLANK Mode
(VI!.=VHV-VO)
(Note 4)
1902-0, -2
1902-4
VSLANK =
VSLANK =
VSLANK =
VSLANK =
VSLANK
2AV,
2.4V,
2.4V,
2AV,
2AV,
=
VOF =
VOF =
VOF =
VOF =
VOF =
1V,
1V,
1V,
1 V,
1V,
VIG =
VIG =
VIG =
VIG =
VIG =
0
3S0
190
SV
SV
SV
SV
SV
-Rp
-0.4
-0.4
-0.2
-0.4
VIJ.SIR
VI!. BLANK Mode
Input Rejection
(VI!. = VHV - Vol
(Note 4)
1902-0, -2
1902-4
VSLANK = 2.4V, I!.VIN = 0.3V, VIG = SV
VBLANK = 2AV, I!.VIN = 0.3V, VIG = SV
VBLANK = 2.4V, I!.VIN = 0.3V, VIG = SV
--
Vl!JVos
VI!. vs Offset Adjust
Min
Max
1902-0, -2
1902-4
1902-0, -2
1902-4
VOF =
VOF =
VOF=
VOF=
0.2
0.1
32
16
VI!JVIG
VI!. vs Gain Adjust
(Gain Adjust
Rejection)
(Note 4)
1902-0, -2
1902-4
VI!. Tc
VI!. Over
Temperature
(Note 4)
1902-0, -2
1902-4
I!.VIG = SV
I!.VIG= SV
I!.VIG= SV
T C = +2SoC to + 7SoC
T c = +25°C to + 75°C
T C = +25°C to + 7SoC
VREF
Reference Voltage
IREF
Reference Current
OV, VIG = 3V
OV, VIG = 3.SV
SV
SV
Vcc and VEE = Nominal ±1 0%
-
S.25
-
10·9
Note 3
SO
Unit
V
~
O.S
V
-
dB
-
pF
-
kn
S.S
V
10
S
IlA
V
10
IlA
-400
IlA
-200
~
90
so
Vp.p
Vp.p
n
n
n
-
0
420
210
-
2xRp
0.8
1
0.4
1
mV
V
V
V
V
±2xRp
±O.S
±0.4
mV
V
V
-
-
-
10
6
S2
26
V
V
V
V
±10xRp mV
±4
V
±2
V
±2xRp
±O.S
±OA
5.75
4
mV
V
V
V
mA
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1902
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Transfer
A
Parameter
Voltage Gain
(Note 3)
1902-0,2
1902-4
Test Conditions
Min
VIG = 3V, aVIN = 0.6V
VIG = 3.0V, aVIN = 0.6V
71.5
36
=lV, VCM ~ ±0.5V
LEA
Linearity Error Amplifier
VIG = 4V, VOF
LEGA
Linearity Error Gain Adjust
VIN = 0.2V, VOF = 1V, VCM ~ ±0.5V
Dynamic
tRftF
tBPW
THD
Output Rise and Fall 1902-0 (25°C)
(-55,125°C)
(10% to 90%)
1902-2 (25°C)
(-55,125°C)
CL = 15 pF (Note 2) 1902-4 (25°C)
(-55,125·C)
Blanking Input Pulse Width
aVIN = 0.6V,
aVIN = 0.6V,
aVIN = 0.6V,
aVIN = 0.6V,
aVIN = 0.6V,
tNIN = 0.6V,
VouTfrom 20V to 110V
VouTfrom 20Vto 110V
VouTfrom 20V to 110V
VouTfrom 20Vto 110V
VouTfrom 15V to 65V
VouTfrom 15Vto 65V
Max
Unit
-
133.8
67
VN
VN
-
±2
%GS
(Note 5)
-
-
±2
%
-
---
5.0
7.0
4.0
5.0
2.5
3.0
ns
ns
ns
ns
ns
ns
-
30
ns
-
±2
%GS
(Note 5)
-
-
-
Thermal Distortion
Power Supplies
Positive IC Voltage
Vcc
Negative IC Voltage
VEE
Typ
-
-
Acceptable Range
14.5
15
15.5
V
Acceptable Range
-10
-10.5
-11
V
-
120
70
V
V
100
mA
-100
mA
VHVMAX
High-Voltage Supply 1902-0, -2
1902-4
Icc
Positive Supply Current
80
lEE
PSRR
Negative Supply Current
-70
-
25
30
PD
Power Dissipation
-
-
(Note 8)
-
Power Supply Rejection Ratio
VEE and Vcc = Nominal ±5%
dB
W
Limits printed in boldface type are guaranteed and are 100% production tested. Limits in normal font are guaranteed but not 100% tested.
Standard product tested at room temperature only. HR product tested at +125·C, 25·C, & -55·C.
NOTES: t. This limit only applies when VI-N is greater than 9OV.
2. Total load capacitance on the output mode of the IC includes load capacitance and paraSitic.
3. All characterization measurements are made using a 4000 resistor: internal (-2) or external (-0).
4. This speCification applies to the 1902-0 when a custom pull-up resistor is selected by the user.
5. '%GS' means percent of 9rey scale, referring to RS343 standard video levels.
6. Rise and fall times depend on the value of Rp and Lp, peaking inductor (user-selected) and output load.
7. To meet the maximum speed, input rise times of less than 1 ns are needed. These limits are tested to guarantee device functionality.
8. See Table I, page 6, for power dissipation specifications.
10-10
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1902
ORDERING INFORMATION
Rp
(0)
Part
Number
High Voltage
(V)
tRAt Vpp Max
Case Operating
Temperature
120
120
120
120
70
70
(Note 2)
(Note 2)
90V/4.0 ns
90V/4.0 ns
50V/2.5 ns
50V/2.5 ns
-25°C to +85°C
-55°C to + 125°C
-25°C to +85°C
-55°C to + 125°C
-25°C to +85°C
-55°C to + 125°C
1902-0
(Note 1)
1902-0-HR
(Note 1)
1902-2
400
1902-2-HR
400
1902-4
200
1902-4-HR
200
NOTES: I.Rp is user-defined and supplied. The internal Rp = OQ.
2.1R is dependent upon user·defined Rp and VHV .
EVALUATION BOARDS
Board
Number
Driver
Number
6149-0
1902-0
6149-2
1902-2
6149-4
1902-4
6149-98
6149-99
Description
These are demonstration boards which allow a user to quickly and easily evaluate the
operating characteristics of the video display drivers in conjunction with the user's
display. These cards cO!1tain the chosen driver, all necessary connectors (power supply,
input/output, control signal) as well as gain and offset adjustment circuits. These boards
are compact (4.5" x 4.5" max) and are supplied with an attached heat sink for thermal
management. An application note is included with evaluation board to simplify the
evaluation of driver performance.
Heat sink kit used with the evaluation board.
Fully assembled evaluation board with no hybrid inserted.
APPLICATIONS INFORMATION
Initial Setup
The initial setup of the 1902 requires proper setting of
the VOF and VIG inputs to obtain balanced rise/fall times. If
the quiescent current level (VOF) is set too low, it slows the
output rise time and limits the bandwidth of the 1902. If it is
set too high, it will limit the fall time. Similar effects result if
the gain control (VIG) is set too high.
Signal Inputs
The analog inputs are +VIN and-VIN. They are designed
to accept RS343 signals, ±0.714 Vp_p. It is recommended
that the input signal be limited to ±1.3V referenced to ground
(0.714V signal +0.5V common mode). Offsets of ±2V (referenced to ground, signal included) can be tolerated without
damage to the device, but are not recommended.
Output Voltage
The output voltage is controlled by the breakdown
voltages of transistors OCAS, ON and Op (see standard
configuration diagram), and the value of Rp. The maximum
output voltage swing is determined by Vp_p 250 mA x Rp.
The dash-numbered versions of the 1902 differ in the values
=
of Rp, Lp, and the breakdown voltages of the output transistors.
Rise and fall time specifications are based on very
conservatively-peaked devices «5% overshoot); i.e., Lp is
low. The pull-up resistor (Rp) is connected directly to pins
16 and 17. Extemal peaking can be added, use inductors
with a high self-resonant frequency, and try to minimize
capacitive coupling to ground. If no extemal resistors or
inductors are added, use good, high-frequency bypassing
on pins 16 and 17.
Care should be taken to limit the amount of the gain
and offset adjustment so the total current through Rp does
not cause excessive power dissipation. The gain adjust can
set the AC current swing to greater than 250 mA (250 mAp.
p = 100 Vp_p on 4000). Higher currents and lower Rp values
result in faster rise and fall times. For VHV > 90V, do not
exceed a total of 290 mA through Rp.
Accesstothe intemal Rp also means the 1902 can bevery
easily configured for low power (but slower speed) applications
by adding external resistance. Note that the device is characterized with a 4000 resistor. Higher Rp values will degrade
other specifications in addition to riselfall times.
If large arc protection resistors are used (>500), series
inductance may improve the rise time of the output signal.
10-11
1[1
HIGH-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1902
DC Gain (Contrast) Control
Reference Voltage
VIG is the DC gain (contrast) control input. It can vary the
device gain linearly from 0 to 80 by inputting a voltage from
OV to 5V. The internal reference (VREF, pin 13) is designed
to drive this input as well as the offset control input. Normally,
a 5 kn potentiometer between VREF and GND (see standard
configuration diagram) is used to vary the gain; however,
any external OV to 5V DC source can be used, but some
temperature performance degradation will result.
The gain equation for the 1902 is:
Vo= VHV-VO
= VIN X VIG x 0.1 (±20%) x Rp* (±5%) x 0.9
V REF is a zener reference with a nominal output voltage
of 5.5V ±5%, and can source up to 4 mAo It is used to adjust
offset and gain.
Power Supplies
Power supplies of 15V (±5%) and -10.5V (±5%) are
required for proper operation. The negative supply can be
set to -12V, but will increase the internal power dissipation
and case temperature. VHV is a function of the 1902 version
selected. The maximum value is 120V, allowing up to 90
Vp_p output signals. Assume that the absolute maximum
value is VHV (listed in the specification table) plus 5V; Le., the
1902-2 absolute maximum equals 125V. It is recommended
the 1902 not be operated above VHV. Because the output
from this type of circuit is referenced to the VHV rail, it is
important that VHV is very stable. In other words, there is no
PSRR for VHV. Your system supply will determine your DC
stability.
To achieve maximum high-frequency performance, good
high-frequency grounding practices and PC board layout
are mandatory.
• Rp is inside the hybrid. Standard values are 200n ±5% and 400n ±5%.
Other values can be added externally.
The overall gain of the 1902 may vary by ±20% due
to process variations of internal components. Temperature
variations also effect gain by as much as 150 ppml"C. If
more than one 1902 is used in a system, steps should be
taken to make them track thermally (Le., a common heat
sink). This will reduce any mismatches due to varying
ambient conditions.
Offset (Brightness) Control
Supply Sequencing
VOF is the output offset (brightness) control input. It sets
the quiescent output current in Rp, thereby setting the output
quiescent voltage level. Output quiescent voltage can be
adjusted from (severalllA x Rp) to (100 rnA x Rp), nominal.
From VHV this is accomplished by inputting a DC voltage in
the OV t05.5V range atVOF. Normally, this input is from a5
kn potentiometer between VREF and GND (see standard
configuration diagram).
It is essential that the VHV supply be brought up before
VEE and Vce when using the higher voltage versions of the
1902. Supply sequencing is of less importance when VHV is
less than 90V. The recommended sequence is VHV, Vee, then
VEE. If sequencing cannot be done, the supplies should be
brought up within a few milliseconds of each other.
Blank
Power Dissipation
The blank input, when asserted (Le., TIL HIGH), disables the video input of the 1902 and sets the output to
approximately VHV. This input is independent of the input
signal and operates with TIL levels.
The 1902 power dissipation will vary in accordance to
load requirements and pixel size. The 1902 flat pack is
designed to provide a low thermal resistance path from the
hybrid circuit to an external heat sink. Mounting flanges
provide solid mechanical and thermal attachment of the
package to the heat sink. In addition, the package is electrically isolated so no mounting inSUlators are needed and
the heat sink can be at any convenient potential.
Table I. Typical Power Dissipations
% ofTime Signal Is at
Average Power
Average Power
Black
White
Max Signal
Blank
Black
White
Output Stage
Total
Level
level
Level
Level
(Noles 1, 2)
(Nole.I,2)
(V)
(V)
(Vo-Ve",cK)
(V)
Level
Device
VHV
(V)
(%)
(%)
(%)
(W)
(W)
1902-2
120
110
20
0
100
0
0
0
2.5
1902-2
120
110
20
90
20
40
40
13.2
15.7
1902-4
70
65
15
0
100
0
0
2.5
1902-4
70
65
15
50
20
40
40
8.4
10.59
NOTES:
1.
Input stage quiescent power is approximately 2.5W.
2.
Power dissipations listed do not include power dissipation due to switching.
10-12
~,"TELEDYNE
COMPONENTS
1903
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
FEATURES
APPLICATIONS
•
•
•
•
•
•
Output Signals Into 10 pF Loads .................. 80 Vp.p
Rise and Fall Times @ 80 Vp.p ................................. <4 ns
User-Defined Pull-Down Resistor
Linear Gain Adjustment for Matching
Versions Available to Match Specific CRT
Requirements
CRT Monitors
- Projection
- High-Resolution
-Beam Index
STANDARD CONFIGURATION
+20V
/----------+---.-.
~f'
1903
-10.SV ; . - _ - . . - - ' - - _ - - - . . ,
lliF
F "~ 'rE=E---f--:-'=-f-::-=-'=t:_=r-+::~:::~:::::::::~....L.:2:.:6___. . ,
0.1
NC
0.1
0.01
~IIF
NC
TOBIAS
CIRCUITRY
NC
NC
JIb BLANK
23
-VIN o-I-'-.,.....~----,
+VIN 0-1-"-........"'------1('.::1
1,2,9,10
14,15,29,30
GND
.....- - - + - - H V
~2211F
1055-1
10-13
VOUT
(TO CRT)
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1903
GENERAL DESCRIPTION
The 1903 is a high-performance, high-voltage amplifier
designed to drive the grid in high-resolution, high-brightness
CRT monitors and projection displays.
The 1903 is replete with differential inputs, blanking
control, linearly-adjustable gain stage, adjustable offset and
a differential emitter-follower output stage. It is capable of
driving 10 pF to 20 pF loads, can be driven directly from a
standard video DAC, and is RS170 and RS343 compatible.
The 1903 has four variants to suit different applications.
There are basically two types: Those with internal pull-down
resistors and those that allow the user to choose and apply
their own pull-down resistor. The parts within these two
types differ in peak-to-peak output signal swing. The 1903o and 1903-2 are 90 V pop versions specified at less than 4
ns rise and fall times. The 1903-0 and 1903-2 operate from
a-95V rail.
The 1903's are housed in hermetically-sealed, 30-pin
flat packs with mounting flanges suitable for 4-40 screws.
The standard 1903-X is specified for-25°C to +85°C operation. The 1903-X-HR is specified for -55°C to + 125°C
operation.
PIN CONFIGURATION
PIN
NO.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PIN
DESIGNATION
NO.
DESIGNATION
GND
GND
BLANK
VEE
VEE
VEE
-VIN
30
29
28
27
26
25
24
23
22
21
20
19
18
GND
GND
+VIN
GND
GND
VGAIN
VOFF
VREF
GND
GND
17
16
3O-Pin Flat Package
Vcc
Vce
NC
NC
NC
PIN 1
CONTRASTING
coLORED
GLASS
VOUT
NC
HVBUFFER
HVBUFFER
GND
GND
HVRESISTOR
HVRESISTOR
0
0
0
"''''
1903
15
0
HV = HIGH VOLTAGE
NC. NO INTERNAL CONNECTION
10-14
0
0
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1903
ORDERING INFORMATION
Part Number
Rp
VHV
Output Range
1903-0
OQ'
-95V
-5Vto -85V
-25°C to +85°C
1903-0-HR
OQ'
-95V
-5Vto-85V
-55°C to + 125°C
1903-2
400Q
-95V
-5Vto -85V
3 ns
4.5 ns
-25°C to +85°C
1903-2-HR
400Q
-95V
-5Vto-85V
3 ns
4.5 ns
-55°C to + 125°C
Rise Time
Fall Time
Case Operating Temperature
'User must provide an external Rp.
"Rise and fall times for devices with external Rp will approach the times specified here for corresponding values of external Rp versus internal Rp and
output voltage swing.
EVALUATION BOARDS
Board
Number
Driver
Number
6150-0
1903
6150-2
1903-2
6150-98
6150-99
Description
These are demonstration boards which allow a user to quickly and easily evaluate
the operating characteristics of the video display drivers in conjunction with the user's
display. These cards contain the chosen driver, all necessary connectors (power supply,
inpuVoutput, control signal) as well as gain and offset adjustment circuits. These boards are
compact (4.5" x 4.5" max) and are supplied with an attached heat sink for thermal
management. An application note is included with evaluation board to simplify the
evaluation of driver performance.
Heat sink used with the evaluation board.
Fully assembled evaluation board w~h no hybrid inserted.
ABSOLUTE MAXIMUM RATINGS
VHV
Vcc
VEE
VIDF
V,CM
V,G
VOF
VSLANK
IRP
IREF
Load Resistor Supply .................... (VHV Max +5V)
Positive IC Supply ........................................ +22V
Negative IC Supply ...................................... -12V
Differential Input Voltage ................................ +2V
Common-Mode Input Voltage ........................ ±2V
Gain Adjustment Input Voltage ...................... +6V
Offset Adjustment Input Voltage .................... +6V
Blank Input Voltage ........................................ +6V
Total Current Through Rp (Note 1) .......... 290 mA
Reference Output Current .......................... -5 rnA
Tc
TSTG
Ts
Operating Case Temperature Range
1903 ........................................ -25°C to +85°C
1903-X-HR ............................ -55°C to +125°C
Operating Junction Temperature Range
.............................................. -55°C to +150°C
Junction-to-Case Thermal Resistance
.................... 10°CIW (For QCAS and control IC)
............................... 1.25°C/W (For Rp internal)
Storage Temperature Range ..... -55°C to +150°C
Lead Temperature (Soldering, <10 sec) ... +260°C
ELECTRICAL CHARACTERISTICS: Tc = +25°C, VEE =-10.5V, Vce =20V, VHV = Max, that is, -95V, VSLANK =
TIL Low, V,G = VOF = ±V'N = OV, CL = 10 pF(2), and external Rp = 4000 (1903-0), unless otherwise noted.
Parameter
Test Conditions
Y,N
Input Vo~age Range
Referenced to Ground,
Excluding VCM
18
Input Bias Current
Input Common-Mode Range
Symbol
Input
VCM
10-15
Sbgrp*
Min
Typ
Max
Unit
-
-
-
±0.714
V
-
-50
-
50
-
-
IIA
-0.5
0.5
V
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1903
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Test Conditions
Input (cont.)
Common-Mode Rejection Ratio
CMRR
Signal Input Impedance
RIN
Signal Input Capacitance
CIN
Offset Adjust Input Vottage
VOF
Offset Adjust Input Current
IOF
Gain Adjust Input Vottage
VIG
Gain Adjust Input Current
IIG
Digital Inputs
Input Logic "0" Current
IlL
Input Logic ",. Current
IIH
Output
Output Voltage Range 1903-0,-2
Vo
Rp
Internal Pull-Down
1903-0
Resistor
1903-2
1903-0
VA in BLANK Mode
VAS
(Note 4)
1903-2
(VA=VHV-VO)
VASIR
VtfJos
VoNlG
VA Tc
VREF
IREF
Transfer
A
Min
-
VCM =±0.5V
10
0
0.5
0
0.5
VOF= IV
VIG=5V
VBLANK = O.4V
VB LANK = 2.4V
VHV= Max
Rp is External and is User-Supplied
Linearity Error Gain Adjust
VIN = 0.2V, VOF = 1V, VCM:!> ±O.5V
1903-0, -2
Output Rise Time
2SoC, -55°C
From ±VIN (Note 5)
Output Fall Time
1903-0, -2
From ±VIN (Note S)
25°C, -55°C
Output Rise and Fall 1903-0, -2
Time From±VIN (Note S)
Blanking Input Pulse Width
Thermal Distortion
t.VIN= 0.6V, tR (VIN) = 1 ns, Q= IS pF
Vo = -5V to -8SV (Note 2)
t.VIN = 0.6V, tR (VIN) = 1 ns, CL = 15 pF
Vo = -SV to -85V (Note 2)
HR only, 125°C
tR, tF
tBPW
THO
-
-
0
-
5.5
10
5
10
-400
-200
I1A
I1A
I1A
V
V
mV
V
mV
V
V
-
-10
-32
±10xR
±4
±2xRp
±0.84
5.75
4
-
-
133.8
±2
-
-
±2
-
3
4
ns
-
4
6
ns
-
6
9
ns
30
-
~.8
~.2
-52
-
-5.25
71.5
--
-
80
dB
kn
pF
V
I1A
V
V
V
mV
V
-
10-16
-
0.4
0.4
2xRp
0.8
-2.5xRp
-1
-2xRp
LEGA
40
20
2
Unit
420
Rp
VBLANK = 2.4V, VOF = IV, VIG = SV
BLANK Mode Input (Note 4)
VBLANK = 2.4V, t.VIN = 0.3V, VIG = SV
1903-0, -3
Rejection
VBLANK = 2.4V, t.VIN = 0.3V, VIG = SV
VAOffset Voltage (Note that 1903-0 uses 4000 load resistor)
Min
1903-2
VIG=4V
1903-2
Max
VOF= SV
VA vs Gain Adjust
1903-0
t.VIG=SV
t.VIG=5V
'903-2
VA Over Temperature 1903-0
Tc = +25°C to +7SoC
1903-2
Tc = +2SoC to +7SoC
Reference Vottage
Vcc and VEE = Nominal ±1 0%
Reference Current
Max
Vp.p
0
0
mV
-2xRp
Voltage Gain (Note 4) 1903-0, -2
VIG = 3V, t.VIN = 0.6V
Linearity Error AmplHier VIG = 4V, VOF = 1V, VCM :!>±O.5V
tF
-
380
VBLANK= 2.4V, VOF= IV, VIG= 5V
LEA
Dynamic
tR
-600
-400
Typ
-
±2
rnA
VN
%GS
(Note 3)
%GS
(Note 3)
ns
%GS
(Note 3)
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1903
ELECTRICAL CHARACTERISTICS (Cont.)
Parameter
Symbol
Test Conditions
Min
Power Supplies
Positive IC Voltage
Vcc
Negative IC Vo~age
VEE
High Vo~age Supply
VHV
1903-0, -2
1903-1, -3
Icc
Positive Supply Current
lEE
PSRR
Negative Supply Current
PD
Power Dissipation
Power Supply Rejection Ratio
VEE and Vcc
=Nominal ±5%
Typ
Max
19.5
20
20.5
V
-10
-10.5
-11
V
0
0
-105
-85
V
V
100
-90
rnA
rnA
25
-
-
(Note 6)
-
W
-
Unit
dB
Limits printed in boldface type are guaranteed and 100% production tested. Limits in normal font are guaranteed but not 100% production tested.
Standard part tested at room temperature. HR parts tested at +12SoC, -55°C & +2SoC.
NOTES: 1.
2.
3.
4.
5.
This limit only applies when VHV is greater than --60V.
Totelload capacitance on the output mode of the IC includes load capacitance and parasitic.
'%GS' means percent of grey scale, referring to RS343 standard video levels.
All characterization measurements are made using a 4000 resistor.
Rise and fall times for devices with external Rp will approach the times specified here for corresponding values of external Rp versus
intemal Rp and output voltage swing, depending on PC board layout parasitics.
6. Refer to Table I, page 6, for power. dissipation specifications.
APPLICATIONS INFORMATION
Initial Setup
If large arc-protection resistors are used; i.e., >SOO, use
of a series inductor may improve the rise time of the output
signal.
The initial setup of the 1903 requires proper setting of
the VOF and VIG inputs to obtain balanced rise and fall
times. If the black level (VOF) is set too low, it will slow the
output fall time and limit the bandwidth of the 1903. If it is
set too high, it will limit the rise time. Similar effects will
result if the gain control (VIG) is set too high.
Signal Inputs
The analog inputs are +VINand-VIN. They are designed
to accept RS343 signals, ±0.714 Vp_p. It is recommended
that the input signal be limited to ±1.3V, referenced to
ground (0.714V signal + O.SV common mode). Offsets of
±2V (referenced to ground, signal included) can be tolerated
without damage to the device, but are not recommended.
DC Gain (Contrast) Control
VIG is the DC gain (contrast) control input. It can vary the
device gain linearly from 0 to 100 by inputting a voltage from
OV to SV. The internal reference (VREF, pin 13) is designed
to drive this input as well as the offset control input. Normally,
as kn potentiometer between VREF and GND (see standard
configuration diagram) is used to vary the gain. However,
any external OV to SV DC source can be used, but some
temperature performance degradation will result.
The gain equation for the 1903 is:
[VHV - Vol
Output Voltage
The output voltage is controlled by the breakdown
voltages of transistors QCAS, QN, and Qp (see standard
configuration diagram), and the value of Rp. The maximum
output voltage swing is determined by Vpp =2S0 rnA x Rp.
The rise and fall time specifications are based on
conservatively-peaked devices «S% at the max Vp_p). The
internal pull-down resistor (Rp) is connected directly to pins
16 and 17. External peaking can be added; use inductors
with a high self-resonant frequency and try to minimize
capacitive coupling to ground. If no external resistors or
inductors are added, use good, high-frequency bypassing
on pins 16 and 17.
=(VIN x VIG x 0.1
(±20%)
x Rp (±S%) x 0.9
>Rp can be the intemal 4000 resistor or an external user-definedl
supplied resistor.
The overall gain of the 1903 may vary by ±20% due to
process variations of the internal components. Temperature
variations also affect gain by as much as lS0 ppm/°C. If
more than one 1903 is used in a system, steps should be
taken to have thern track thermally; i.e., a common heat sink.
This will reduce any mismatches due to varying ambient
conditions.
10-17
III
I
HIGH NEGATIVE-VOLTAGE VIDEO DRIVER
FOR CRT MONITORS
1903
Offset (Brightness) Control
VOF is the output offset (brightness) control input. It sets
the quiescent output current, in Rp, thereby setting the output quiescent voltage level. Output quiescent voltage can be
adjusted from several !-lAx Rp to 100 rnA x Rp, nominal, from
the VHV rail. This is accomplished by inputting a DC voltage
in the OV to 5.5V range at VOF. Normally, this input is from
a 5 kW potentiometer bertween VREF and GND (see standard configuration diagram).
Blank
Due to the fact the output from this type of circuit is
referenced to the VHV rail, there is no PSRR for VHV.
Therefore, it is important that the VHV rail is very stable. Your
system power supply will determine your DC stability.
To achieve maximum high-frequency performance, good
high-frequency grounding practices and PC board layout
are mandatory. For best performance, the case must be
held at AC ground. That is, if the case cannot be grounded
directly (such as through a grounded heat sink), it should be
capacitively grounded.
Supply Sequencing
The blank input, when asserted (Le., TTL HIGH), disables the video input of the 1903 and sets the output to
approximately VHV. This input is independent of the input
signal and operates with TTL levels.
It is essential that the VHV supply be brought up before
VEE and Vee when using the higher voltage version of the
1903. Supply sequencing is less important when VHV is less
than -70V. The recommended sequence is VHV, Vee then
VEE. If sequencing is not possible, the supplies should be
brought up within a few milliseconds of each other.
Reference Voltage
VREF is a zener reference with a nominal output voltage
of 5.5V ±5%, and can source up to 4 rnA. It is used in
adjusting offset and gain.
Power Dissipation
Power Supply
Power supplies of 20V (±5%) and -10.5V (±5%) are
required for proper operation. The negative supply can be
set to -12V, but will increase the intemal power dissipation
and case temperature. VHV is a function of the 1903 version
selected. The maximum voltage is -95V, allowing up to 80
Vp_p output signals. The absolute maxi{l1um voltage, to
preclude damage, is equal to the VHV listed'in the specification table, plus 5V. For example, the 1903-0 absolute maximum is -100V. It is recommended that the high voltage
supply not exceed the listed VHV.
The 1903 power dissipation will vary in accordance to
load requirements and pixel size. The 1903 flat pack is
designed to provide a low thermal resistance path from the
hybrid circuit to an external heat sink. Mounting flanges
provide solid mechanical and thermal attachment of the
package to the heat sink. In addition, the package is electrically isolated 50 no mounting insulators are needed and the
heat sink can be at any convenient voltage potential. (See
Table I.)
Table I. Typical Power Dissipations
Device
VHV
(V)
Black
Level
(V)
1903-2
1903-2
-95
-95
-85
-85
White
Level
(V)
Max. Signal
(VO-VBLAcl()
(V)
-5
0
80
-5
% of Time Signal is at
Blank
Black
White
Level
Level
Level
(%)
(%)
(%)
100
20
0
40
NOTES: 1. Input stage quiescent power is approximataly 2.5W.
2. Power dissipations listed do not include power dissipation due to switching.
10-18
0
40
Average Power
Output Stage
(Notes 1, 2)
(W)
Average Power
Total
(Notes 1, 2)
(W)
0
13.5
2.5
16
Section 11
Display Drivers
Display AID Converters
Binary AID Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
III
~"'TELEDYNE
COMPONENTS
TC7211A
TC7212A
4-DIGIT CMOS DISPLAY DECODER/DRIVER
FEATURES
GENERAL DESCRIPTION
TC7211 A (LCD DRIVER)
The TC7211A (LCD DecoderlDriver) and TC7212A
(LED Decoder/Driver) is a direct drive, 4-digit, 7-segment
display decoder and driver.
The TC7211 A drives conventional LCDs. An RC oscillator, divider chain, backplane driver, and 28-segment outputs are provided on a single CMOS chip. The segment
drivers supply square waves of the same frequency as the
backplane, but in-phase for an OFF segment and out-ofphase for an ON segment. The net DC voltage applied
between driver segment and backplane is zero.
The TC7212A Drives common -anode LED displays
with 28 current controlled, low leakage, open, N-Channel
output transistors. The brightness control input can be
used as a digital display enable. A varying voltage at the
control input will allow continuous display brightness control.
The TC7211A (LCD) and TC7212A (LED) requires
only 4 data bit inputs and 4 digit select signals to interface
with multiplexed BCD or binary output devices (such as the
ICM7217, ICM7226, ICL71 03 and TC7135). The4-bitbinary
input code is decoded into the 7-segment alphanumeric
code known as "Code B."
The "Code B" output format results in a 0 to 9, -, E, H, •
L, P or blank display. True BCD or binary inputs will be
correctly decoded to the 7-segment display format.
The CMOS TC7211A and TC7212A are available in a
40-pin epoxy dual-in-line package and a compact 60-pin
flat package. All inputs are protected against static discharge.
•
•
•
•
•
•
•
•
4-Digit Nonmultiplexed, 7-Segment LCD Outputs
With Backplane Driver
RC Oscillator On Chip Generates Backplane Drive
Signal
Eliminates DC Bias Which Degrades LCD Life
Backplane Input/Output Pin Permits Synchronization of Cascaded Slave Device to a Master
Backplane Signal
Separate Digit Select Inputs to Accept Multiplexed
BCDlBinary Inputs
Binary and BCD Inputs Decoded to Code B
(0 to 9, -, E, H, L, P, Blank)
Pin Compatible and Functionally Equivalent to
ICM7211A and DF411
Connect to TC7135 in Flat Package for Compact
4-1/2 Digit Meter Systems
TC7212A (LED DRIVER)
•
•
•
•
1082-1
28 Current Limited Outputs Drive Common-Anode
LEOs at Greater than 5 mA Per Segment
Brightness Input Allows Potentiometer Control of
LED Segment Current Pin Also Serves as Digital
Display Enable
Same Input Configuration and Output Decoding
as the TC7211 A
Pin compatible and Functionally Equivalent to
iCM7212A
11-1
4-DIGIT CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
.,,,
FUNCTIONAL BLOCK DIAGRAM
04
TC7211A
GND - - .
SELECT
DIGIT
INPUTS
02
03
SEGMENT
OUTPUTS
SEGMENT
OUTPUTS
SEGMENT
OUTPUTS
01
SEGMENT
OUTPUTS
~D:D:::t:I:::
{~~~~~~~~~~~~======b======:L~_____J
~t;~E
OSCILLATOR
(~~~~
+128
DRIVER
OSCIL~~~~~ O--I~-.-D-~~-:e-C-~-R-I.t-'" =R=U=N=N=IN=G~)_ _ _ _ _E_N....1LE
_11
BACKPLANE
INPUT/OUTPUT
FUNCTIONAL BLOCK DIAGRAM
.,,,
TC7212A
04
SEGMENT
OUTPUTS
02
03
SEGMENT
OUTPUTS
SEGMENT
OUTPUTS
01
SEGMENT
OUTPUTS
BRIGHT·
NESS
SELECT
mGIT
INPUTS
{~~~~~~~~~~~~======b======:L______~
11·2
4-DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
PIN CONFIGURATIONS
01
C1
81
A1
OSCILLATOR
GND
~I
D3
D2
E2
DIGIT
SELECT
INPUTS
01
G2
A3
: IDA,.
83
eo
C3
F4
F2
81
03
G4
E3
E4
G3
D4
F3
C4
A4
B4
INPUTS
- -u Q- m
+ - ~
oo zu -C zu m
~ > w a
o
Ul
-
~
~
m
zu zu
•
11-3
4·DIGIT CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
PIN CONFIGURATIONS
0 0 ...
z z "
D1
E1
C1
G1
B1
F1
A1
BRT
GND
GND
C2
D3
D2
:
~I
DIGIT
SELECT
INPUTS
~I
B2
DATA
:
INPUTS
B2
E2
G2
F2
A3
B3
C3
F4
D3
G4
E3
E4
G3
D4
F3
C4
A4
B4
NOTES: 1. NC "" No internal connection.
2. Pins 8, 23, 38 and 53 are connected to the die substrate.
The potential at these pins is approximately 0'.
No extemal connections should be made.
11-4
4-DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
ORDERING INFORMATION
Part No.
Driver
Type
TC7211AIPL
LCD
TIMING DIAGRAMS
Output
Code
Input
Config.
40-Pin
Plastic DIP
Code B
MuHiplexed
4-bit Binary
or BCD
Package
TC7212AIPL
LED
40-Pin
Plastic DIP
Code B
Multiplexed
4-bit Binary
or BCD
TC7211AIJL
LCD
40-Pin
CerDIP
Code B
Multiplexed
4-bit Binary
or BCD
CodeB
MUltiplexed
4-bit Binary
or BCD
TC7212AIJL
TC7211AIBO
40-Pin
CerDIP
LED
LCD
60-Pin
Flat Package
Form Leads
Code B
TC7212AIBO
LED
Flat Package
Form Leads
Dn-l
DIGIT
SELECT
On
OSCILLATOR
FREQUENCY
BACKPLANE
INPUT/OUTPUT
OFF SEGMENTS
Multiplexed
4-bit Binary
or BCD
60-Pin
Code B
tSA
DIGIT
SELECT
ON SEGMENTS
N1nnnF~~
14
~I
128 CYCLES
I
L
1~~tes+I--cY~Es+l
I
I
L
I
Multiplexed
4-bit Binary
or BCD
III
TEST CIRCUIT
LOAD EACH
SEGMENT TO
BACKPLANE
wrrH200pF
CAPACITOR
J
I- _:-1_-_-_-_-_-_-_'__ 1
20
11-5
4~DIGIT
CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................... +6.5V
Input Voltage, Any Terminal
(Note 2) .................................... V+ +O.3V, GND -0.3V
Power Dissipation (Note 1) ....................... 0.8 Wat +70°C
Operating Tempen~ture Range ................ -20°C to +85°C
Storage Temperature Range .................. ~5°C to +150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
thOse indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
NOTES: 1. This lim~ refers to that olthe package and will not be realized
during normal operation.
2. Due to the SCR structure inherent in the CMOS process,
connecting any terminal to volteges greater than V' or less
that GND may caUse destructive latch-up. For this reason it
is recommended that inputs from external sources not operating on the same power supply not be applied to the device
before its supply is established, and, in multiple supply
systems, the supply to the TC7211 AlTC7212A be tu med on
Stresses above those listed under' Absolute Maximum Ratings' may
cause permanent damage to the device. These are stress ratings only. and
functional operation of the device et these or any other conditions above
first.
TABLE I: OPERATING CHARACTERISTICS
Test Conditions: All parameters measured with V+ = 5V
TC7211 A Characteristics (LCD Decoder/Driver)
Symbol
Parameter
Test Conditions
Operating Voltage Range
Vsup
lop
losci
tRFS
tRFB
fosc
fBP
Operating Current
Oscillator Input Current
Segment Rise/Fall Time
Backplane Rise/Fall Time
Oscillator Frequency
Backplane Frequency
Display Blank
Pin 36
CL=200pF
CL =5000pF
Pin 36 Floating
Pin 36 Floating
TC7212A Characteristics (Common-Anode LED DecoderlDriver)
Operating Voltage Range
Vsup
lop
Operating Current
Pin 5 (Brightness),
Min
3
-
-
4
-
lop
Display Off
Operating Current
Pins 27-34 = GROUND
Pin 5 at V+, Display all 8's
ISLK
ISEG
VIH
VIL
Segment Leakage Current
Segment On Current
Logic "1» High Input Voltage
Logic "fj' Low Input Voltage
Segment Off
-
Segment On, Va = +3V
5
3
hLK
CIN
Input Leakage Current
Input Capacitance
Pins 27-34
Pins 27-34
IBPLK
BPlBrightness Input Current
Leakage
Measured atPin 5 With
Pin 36atGND
CBPI
BPlBrightness Input Capacitance All Devices
-
AC Characteristics (LCD and LED DecoderlDriver)
Chip Select Active Pulse Width Refer to Timing Diagrams
tSA
tos
Data Valid Time
tOH
tlDS
Data Hold Time
Inter-Digit Select Time
-
Refer to Timing Diagrams
Refer to Timing Diagrams
Refer to Timing Diagrams
11-6
-
Typ
5
10
Max
6
50
±2
0.5
±10
1.5
16
125
-
Ils
kHz
Hz
5
10
6
50
j.iA
200
±0.01
-
mA
±1
8
-
j.iA
mA
V
V
-
-
-
±0.01
5
±0.01
1
-
200
2
-
1
±1
Unit
V
j.iA
j.iA
j.iA
V
-
j.iA
pF
±1
j.iA
200
-
pF
-
-
~
-
-
Ils
ns
ns
IJ.S
4-DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
INPUT DEFINITIONS
In this table, V+ and GND are considered to be normal operating input logic levels. For lowest power consumption, input
signals should swing over the full supply.
Input
Pin No.
Condition
BO
27 (49)
Bl
28 (50)
V· = Logic "1"
GND = Logic "0"
V· = Logic "1"
GND = Logic "0"
B2
29 (51)
B3
30 (52)
OSC
36 (1)
Dl
D2
D3
D4
31 (54)
32 (55)
33(56)
34(57)
Function
Ones (Least Significant)
Twos
V· = Logic "1"
GND = Logic "0"
V· = Logic "1"
GND = Logic "0"
Floating or with
external capacitor GND
V· = Active
GND = Inactive
Data Input Bits
Fours
Eights (Most Significant)
Oscillator input. Disables BP output devices, allowing segments to be
synchronized to an external signal input at the BP terminal (pin 5)
Dl Digit Select (Least Signfficant)
D2 Digit Select
D3 Digit Select
D4 Digit Select (Most Signfficant)
OUTPUT DEFINITIONS
Output pins are defined by the alphabetical segment assignment and numerical digital assignment.
Output
Pin No.
Function
Al
37 (3)
A
Segment Drive Digit 1
Bl
38 (5)
B
Cl
39 (6) C
Dl
40 (7) D
El
2(10)
E
Fl
4 (12)
F
Gl
3 (11) G
A2
Segment Drive Digit 2
6 (18)
A
B2
7(19)
B
C2
8 (20) C
D2
9 (21) D
E2
10 (22)
E
F2
12 (25)
F
G2
11 (24) G
'Pin number in parentheses ( ) are for SO-pin flat pack.
(LSD)
1 11
Output
Pin No.
A3
B3
C3
D3
E3
F3
G3
13 (26)
14 (27)
15 (28)
16 (33)
17 (34)
19 (36)
18 (35)
20 (37)
21 (39)
22 (40)
23 (41)
24 (42)
26 (48)
25 (43)
A4
B4
C4
D4
E4
F4
G4
1 1
Function
Segment Drive
A
B
C
D
E
F
G
A
B
C
D
E
F
G
1 1
Segment Drive
FeB
03
02
01
A
..
E'JC
0
°898
..
LJ ...J
11-7
~
Digit 4
III
(MSD)
1 11
DIGIT ASSIGNMENT
04
Digit 3
4·DIGIT CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
TYPICAL OPERATING CHARACTERISTICS CURVES
Operating Supply Current
vs Supply Voltage
180
30
LCD DEVICES
DISPLAY BLANK
PIN 36 OPEN
25
,,
II',
,
"j
/ l/;
TA=+25°C
'iO'
ii5.
Il.
~~
5
TA= +70°C
1
e'
60
.'
i"'"
1
o
7
~
10 ~I\= +25°"
I}
8
1/
3
j
~
ffi
900
~
~
2
,#'
300
l/
!.I
./
o
234
VPIN5VOLTS
5
6
;
j
V
/
i..,..-
e5
4
V + VOLTS
11·8
-
I- --I
V+=5V
f-
V+=4V
II
pF7
6
~
o
'fJ
I......
Vj=6V _ f--
A
4
5
V+VOLTS
LED DEVICES
DISPLAY ALL EIGHTS
LED FORWARD
VOLTAGE DROP
VFLED=1.7V
1200 PIN5ATV+
TA=+25°C
tI. 600
III /
5
1500
~
4
j
1/ C~sb=~~F
1800
II
/
1
.J.-+-"i
~
"
'/
~ 10
Operating Power (LED Display)
vs Supply Voltage
LED Segment Current vs
Brightness Control Voltage
15
2
~F
A
I-~
1
PI~~A~V~
TA=+25°C
(~IN ~6 r!:~N)
V
OSC= 220
23456
V+VOLTS
SEGMENT OUTPUT AT +3V -
V
30
~~~
1
90
III
1.1 A
1/J;&
10
1/ 4o~cJo
120
1/
o
150
,
15
I IJ'
IAI
TA = +25°C
~~=~acloc :- I--
20
LED Segment Current
vs Output Voltage
Backplane Frequency
vs Supply Voltage
6
o
234
VoVOLTS
5
6
4-DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
BASIC OPERATION
The TC7211A drives 4-digit by 7-segment LCOs. The
device contains 28 individual segment drivers, a backplane
driver, an on-chip oscillator, and a divider chain to generate
the backplane signal.
The 28 CMOS segment drivers and backplane driver
contain ratioed N- and P-channel transistors for identical
"ON" resistance. The equal resistances eliminate the DC
output driver component resulting from unequal rise and fall
times. This ensures maximum LCD life.
The backplane output driver can be disabled by grounding the OSCILLATOR input (pin 36). The 28 output segment
drivers can therefore be synchronized directly to an input
signal at the backplane (BP) terminal (pin 5). Several slave
devices may be cascaded to the backplane output of a
master device. The backplane signal may also be derived
from an external source. These features permit interfacing
to single backplane LCOs with characters in multiples of
four. (See Figure 1.)
Each slave's backplane input represents only a 200 pF
capacitive load to the master backplane driver (comparable
to one additional segment). The number of slave devices
drivable by a master device is therefore set by the larger
display backplane capacitive load. The master backplane
output will drive the display backplane of 16 one-half-inch
characters with rise and fall times under 5 ~. This represents
a system with three slave devices and a fourth master device
driving the backplane.
If more than four devices are slaved together, the
backplane signal should be derived externally and all
TC7211 A devices slaved to it. The external drive signal
must drive a high capacitive load with 1J.1S to 2 ~ rise and
fall times. The backplane frequency is normally 125 Hz. At
lower display ambient temperatures, the frequency may be
reduced to compensate for display response time.
The on-chip RC oscillator free-runs at approximately
16 kHz. A +128 circuit provides the 125 Hz backplane
frequency. The oscillator frequency may be reduced by
connecting an external capacitor between the oscillator
terminal and V+. (See typical operating characteristics
curves.)
The free-running oscillator may be overridden (if desired) by an external clock. The backplane driver, however,
must not be disabled during the external clock's negative or
low portion, as this will result in a DC drive component
being applied to the LCD, limiting the LC~'s life. To prevent backplane driver disabling, the oscillator input should
be driven from the positive supply to no less than one-fifth
the supply voltage above ground. A backplane disable
signal will not be sensed if the driving signal remains above
ground by one-fifth the supply voltage. An alternate method
for externally driving the oscillator permits the oscillator input
to swing the full supply voltage range. The oscillator input
signal duty cycle is skewed so the low portion duration is less
than 1 Ils. The backplane disable sensing circuit will not
respond to such a short signal.
08 07 D6 OSl04 03 02 01
S-°L~J 1888 8i8 888
+5Y- Y+
GNO
-n
1
DB
07
D6
05
04
03
02
01
4{4
I
BACKPLAN~t
MASTER 2B
+5Y- V+ SEGMENTS
GNOHIGH ORDER
OSC B3-8004 03 02 01 BP
BCDIBINARY
DATA
01 GIT
SELE CT
INPUTS
BACKPLANE
SLAVE 28
SEGMENTS
HIGH ORDER
BACKPLANE
~ OSC B3-BO 04 D3 02 D1 BP
I
_-1'4
I
1
Aji~
Te72 11A
Figure ,. TC7211AM Driving an S-Digit LCD Display in Master/Slave Configuration
11-9
III
4·DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
TC7212A LED Decoder
The brightness input may also be operated digitally as
a display enable. At a logic 1 the display is fully "ON" and at
a logic signal of varying duty cycle also. When operating with
LEOs at a higher temperatures andlor higher supply voltages, the device power dissipation may need to be reduced
to prevent excessive chip temperature rise. The maximum
TC7212AM LED Decoder/Driver
The TC7212AM directly drives four digit, seven segment, common-anode LED displays. The 28 segment drivers are low leakage, current controlled, open drain Nchannel MOS transistors.
A brightness input (pin 5) can be used in two ways to
control output transistor drain current. The voltage at the
brightness control input is transferred to the output transistor
gate for "ON" segments. The brightness voltage directly
modulates the segment drivers "ON" resistance. A variable
brightness control may be implemented with a single potentiometer (Figure 4). A high value potentiomenter (100 kO to
1MO ) will minimize power consumption. The maximum
power dissipation is 1 watt at 25° C. Derate linearly above 35°
C to 500 mW at 70°C (-15 mWfO C above 35°C). Power
dissipation for the device is given by:
The TC7211A accepts multiplexed binary or BCD input
data at pin 27 (LSB) through pin 30 (MSB). Pins 31 (LSD)
through 34 (MSD) are the digit select lines. When the digit
select line is taken to logic "1", input data is decoded and
stored in the enabled output latch of the selected digit. More
than one digit select line may be activated simultaneously.
The same character will be written into all selected digits.
(See Figure 5 for decoder segment assignments.)
Table I. Output Code
B3
0
0
0
0
0
0
0
0
1
1
P = (V+ -VFLEO) (lsEG) (nSEG)
where VFLEO is the LED forward voltage drop, ISEG is segment current, and nseg is the number of "ON" segments. Ifthe
device is operated at elevated temperatures, the segment
current can be limited through the brightness input to keep
power dissipation within the limits described above.
The display may be blanked (all segments OFF) by
applying the input code 1111 or by driving the brightness pin
witha logic). If brightness control is not needed, pin 5 should
be tied to 5.0 V.
100 kO -1MO
F
_
Binary Input
B2
B1
BO
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CodeB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 3. Segment Assignment
V+ (LED ANODES)
TO BRIGHTNESS CONTROL
(PINS)
Figure 2. Brightness Control
Input Configuration and Output Codes
The TC7211AM accepts a 4-bit. true binary (positive
level =logic "1") input at pin 27 (LSB) through pin 30 (MSB).
The binary input is decoded to the 7-segment output known
as Code B. The output display format is 0 to 9, -, E. H. L,
P and blank display (see Table I). Segment assignments are
shown in Figure 3. The TC7211AM will correctly decode
binary and BCD true codes to a 7-segment output.
11-10
0
1
2
3
4
5
6
7
8
9
E
H
L
P
(Blank)
4-DIGIT CMOS DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
Special Order Decoder Option
Applications Information
The TC7211 A is mask programmed to give the 16
combinations of 7 -segment output codes. For large volume
orders (50K pieces minimum), custom decoder options are
available. Contact Teledyne Components for details.
The TC7212 A has two ground pins. Theses should be
connected together.
TYPICAL APPLICATIONS
v+=5vo-r-----------;:=========+~
35
LCD
37-40
188881
2-26
28 SEGMENTS
AND BACKPLANE
Jf
04 34
03 33
..,~ 021-"3:=.2_ _ _ _ _++-,
TC7211A 01 t=3:..::1_ _ _ _ _ _-t-jh
OB3
OB2
OBl
OBO
30
29
28
27
r:8:-:"'s--~V~+'24
4'8
2'8
l's
COUNT 8
STORE 9
DC
23
20
ICM
7217 01 28
02 27
UP/ON 10
03 26
RESET14L-___-10~4~2~5~-~
III
Figure 4. LCD Display Interface to 4-0igit Counter
t=+--t----iK ~OCK
r-~rr4081--~
I
5 OP
31 01
SEG
04
11"
2,3,4
6-26
1-=+--+-+----+-------""-103 TC7211A
29
B2
28 B1
37-40
osc 3~r-+5V
OPTIONAL
CAP.
27
1/4 CD 4030
+Syo-----IL...J
Figure 5: 4-112 Digit AOC Interfaced to LCD
11-11
y+ 1
4-DIGITCMOS ,DISPLAY
DECODER/DRIVER
TC7211A
TC7212A
TYPICAL APPLICATIONS (Cent.)
4·112 DIGIT LCD
+5V
1/2 CD4030
23
POL
D1t2~0----~ir-1---~-~-_--~C~D=40a=-~;~________~~~~~~ D1
mt1~9-t---1r-----~~~________________+-~3~2~D2
D3 18
33 D3
~n
~~
-'f"
I
-'f"
TC7135
88 16
'------------CD4071
I
30
84 15
29 82
82 14
81 13
28
~-----r----------------+-~~81
"-------'--1L-"
27 80
I
D5 12
!.------------
D
1/4 CD4081
112
Q
26
CD4013
S~08E~~~---+-5V--~T~~~------~CLK
OR
27
TC7211A
83
1/4 CD4030
Figure 6. 4·1/2 Digit ADC Interfaced to LCD Display with Digit 81anking on Overrange
11-12
GND 35
4-DIGIT CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
TYPICAL APPLICATIONS (Cont.)
28 SEGMENTS
01-04
+5Vo--H...,.......,
-BACKPLANE
OV
+5V
5 8P
31 01
32
D2
33
SEG
2,3,4
6-26
37--40
OS
34
30
29
ICL71C03(A)
28
27
100kn
INPUT
D4
83
..,r-
TC7211A
OPTIONAL
CAP.
82
OSC 3!!::"_ +5V
Bl
22-100pF
II
BO
O.II1F
35
GNO
v+ 1
+5V
CLOCK IN
120 kHz = 3 REAOINGSISEC
ll1F
36
kn
ICL8052(A)
8068(A)
300
kQ
-15V
-=
ANALOG GNO
Figure 7. 4-1/2 Digit ADC Interfaced to LCD Display with Digit Blanking on Overrange
11-13
III
4-DIGIT CMOS DISPLAY
DECODERIDRIVER
TC7211A
TC7212A
TYPICAL APPLICATIONS (Cont.)
PERIPHERAL
INTERFACE
I
J-...._--.;<..c:..4~
DIGIT 4
~~cr:CT
PORT
6522
VIA
AL. J-.....---,~'-I
4
~:~1
DIGIT 3 DIGIT 2 DIGIT 1
BACKPLANE
~~
TC7211A
GND
V+
+5V
ADDITIONAL
VO
Figure 8: LCD Interface to SY6522 VIA
2.SkD
SooD
1 kD
1 kD
1.2kD
4.5
kD
TOVR
::-
LVR
80
81
..,'"
82
VR
83
D4
RC
T1
T2
RCT
20
kn
8P
TC7211A
100
kn
54036
ADC
TENS
ONES
LSD
Figure 9: Digital Scale With LCD Readout
11-14
D3
02
01
GNO
~~TELEDYNE
COMPONENTS
TC7211AM
TC7212AM
BUS COMPATIBLE 4-DIGIT CMOS DECODER/DRIVER
FEATURES
GENERAL DESCRIPTION
TC7211AM (LCD DRIVER)
The TC7211 AM (LCD Decoder/driver) and TC7211 AM
are CMOS direct drive, 4-digit, 7-segment display decoder
and driver. The devices are bus compatible making microprocessor controlled displays possible. Two chip select
signals control data and digit select code latching prior to
decoding and display. External data latches are unnecessary.
The TC7211AM drives conventional LCDs. An RC oscillator, divider chain, backplane driver, and 28-segment
outputs are provided on a single CMOS chip. The segment
drivers supply square waves of the same frequency as the
backplane, but in-phase for an OFF segment and out:>fphase for an ON segment. The net DC voltage apphed
between driver segment and backplane is near zero maximizing display lifetime.
The TC7212AM drives common-anode LED displays
with 28 current controlled, low leakage, open drain, NChannel output transistors. The brightness control input
can be used as a digital display enable. A varying voltage
at the control input will allow continous display brightness
control.
The four bit binary input code is decoded into the
seven segment alphanumeric code known as "Code B".
The "Code B" output format results in a 0 to 9,-, E, H, L, P
or blank display. True BCD or binary inputs will be correctly
decoded to the seven segment display format.
•
•
•
•
•
•
•
4-Digit Non-Multiplexed 7-Segment LCD Outputs
With Backplane Driver
Input and Digit Select Data Latches
RC Oscillator On-Chip Generates Backplane
Drive Signal
Eliminates DC Bias Which Degrades LCD Life
Backplane Input/Output Pin Permits
Synchronization of Cascaded Slave Device to
a Master Backplane Signal
Binary and BCD Inputs Decoded to Code B
(0 to 9, -, E, H, L, P, Blank)
Pin Compatible and Functionally Equivalent to
ICM7211AM
TC7212AM (LED DRIVER)
•
•
•
•
•
1083-1
28 Current Limited Outputs Drive Common-Anode
LEOs at 8 mA Per Segment
Input and Digit Select Data Latches
Brightness Input Allows Potentiometer Control of
LED Segment current. Pin Also Serves as Digital
Display Enable
Same Input Configuration and Output Decoding
as the TCM7211AM
Pin Compatible and Functionally Equivalent to
ICM7212AM
11-15
•
BUS COMPATIBLE, 4-DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
FUNCTIONAL BLOCK DIAGRAM
..,,,
D4
SEGMENT
OUTPUTS
TC7211AM
GND
DATA {
INPUTS
27
28
29
30
D3
SEGMENT
OUTPUTS
D2
SEGMENT
OUTPUTS
D1
SEGMENT
OUTPUTS
~ :=t:c::cc::::t:::
eo
B1
B2
B3
4-BIT
LATCH
ENABLE
DIGIT {
SELECT
INPUTS
31 DS1
32 DS2
2-BIT
LATCH
2-TO-4
DECODER
ENABLE
CS1
CS2
BACKPLANE
DRIVER
OSCILLATOR 0 36
INPUT
BACKPLANE
(INPUT/OUTPUT)
YD~~~t6R~1
ORDERING INFORMATION
Part No_
Driver
Type
Package
Input
Code
TC7211AMIPL LCD
40-Pin
Plastic
Code B
TC7212AMIPL LED
40-Pin
CodeB
Plastic
Output
Config.
Data and
Digit Select
Latches
Data and
Digit Select
Latches
11-16
BUS COMPATIBLE, 4·DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
FUNCTIONAL BLOCK DIAGRAM
04
SEGMENT
OUTPUTS
~'"
TC7212AM
D2
03
SEGMENT
OUTPUTS
SEGMENT
OUTPUTS
01
SEGMENT
OUTPUTS
BRIGHTNESS
DATA {
INPUTS
27
28
29
30
80
81
82
B3
4-81T
LATCH
ENABLE
DIGIT {
SELECT
INPUTS
31
32
DSI
DS2
2-BIT
LATCH
2-TC>-4
DECODER
ENABLE
CSI
CS2
•
PIN CONFIGURATIONS
01
D1
Cl
Cl
Bl
Bl
Al
Al
OSCILLATOR
E2
G2
F2
B
GND
GND
GND
CHIP SELECT 2 (CS2)
CHIP SELECT 2 (CS2)
CHIP SELECT 1 (CS1)
CHIP SELECT 1 (CS1)
DIGIT SELECT 2 (DS2)
DIGIT SI'LECT 2 (052)
:I
DIGIT SELECT 1 (DS1)
~I
DIGIT SELECT 1 (OSI)
A3
B2
Bl
DATA
INPUTS
B3
BO
C3
F4
F4
D3
G4
G4
E3
E4
E4
G3
D4
D4
F3
C4
C4
A4
B4
B4
Bl
BO
11-17
DATA
INPUTS
BUS COMPATIBLE, 4-DlGIT
CMOS DECODERIDRIVER
TC7211AM
TC7212AM
ABSOLUTE MAXIMUM RATINGS
those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Supply Voltage ......................................................... +6.5V
Input Voltage, Any Terminal
(Note 2) .................................... V+ +0.3V, GND -0.3V
Power Dissipation (Note 1) ........................... 1W at +70°C
Operating Temperature Range ................ -20°C to +85°C
Storage Temperature Range .................. -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) .................. +300°C
Stresses above those listed under •Absolute Maximum Ratings' may
cause pennanentdamage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above
NOTES: 1. This limit refers to that of the package and will not be realized
during nonnal operation.
2. Due to the SCR structure inherent in the CMOS process,
connecting any tenninal to voltages greater than V' or less
than GND may cause destructive latch-Up. For this reason, it
is recommended that inputs from ex1emal sources not oparating on the same power supply not be applied to the device
before its supply is established, and, in multiple supply
systems, the supply to the TC7211 AM be tumed on first.
TABLE I: OPERATING CHARACTERISTICS
Test Conditions:
All parameters measured with V+ = 5V
TC7211 AM Characteristics (LCD DecoderlDriver)
Symbol
Parameter
Test Conditions
Min
Typ
Max
3
5
6
Unit
Vsup
Operating Voltage Range
lop
Operating Current
Display Blank
-
10
50
(.IA
losci
Oscillator Input Current
Pin 36
-
±2
±10
(.IA
tRFS
Segment Rise/Fall Time
CL =200pF
-
0.5
(.IA
Backplane Rise/Fall Time
CL =5000 pF
-
-
tRFB
1.5
fosc
Oscillator Frequency
Pin 36 Floating
-
16
fBP
Backplane Frequency
Pin 36 Floating
-
125
-
V
J.1S
kHz
Hz
TC7212AM Characteristics (Common-Anode LED Decoder/Driver)
Vsup
Operating Voltage Range
lop
Operating Current
Pin 5 (Brightness),
4
5
6
V
-
10
50
(.IA
Display Off
Pins 27-34 = GROUND
lop
Operating Current
Pin 5 at V+, Display all 8's
-
rnA
ISLK
Segment Off
-
200
Segment Leakage Current
±0.01
±1
(.IA
ISEG
Segment On Current
Segment On, Vso = +3V
5
8
-
mA
-
V
Input Characteristics (LCD and LED DecoderlDriver)
VIH
Logic "1" High Input Voltage
3
-
VIL
Logic "Ci' Low Input Voltage
-
-
1
IILK
Input Leakage Current
Pins 27-34
-
±0.01
±1
(.IA
CIN
Input Capacitance
Pins 27-34
5
-
pF
IBPLK
BP/Brightness Input Current
Leakage
Measured at Pin 5 With
Pin 36 at GND
-
±0.01
±1
(.IA
eBPI
BP/Brightness Input Capacitance All Devices
-
200
-
pF
11-18
V
BUS COMPATIBLE, 4~DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
TABLE I: OPERATING CHARACTERISTICS
Test Conditions:
All parameters measured with V+ = 5V
AC Characteristics (LCD and LED DecoderlDriver)
Symbol
tCSA
tDS
Parameter
Chip Select Active Pulse Width
Test Conditions
(Note 3)
Min
200
Data Setup Time
tDH
Data Hold Time
tiCS
Inter-Chip Select Time
100
10
2
Typ
0
-
Max
-
Unit
ns
ns
ns
~s
NOTE: 3. Other chip select (CS) is etther held at logic zero or both CS 1 and CS2 driven together.
TIMING DIAGRAMS
(cf:'1~~
r
tcsA
tICS
CS2
(CSt)
tos
DATA AND
DIGIT
I
SELECT
I
CODE
tOH
~DON"CARE
Figure 1: BUS Interface TIming Diagram (LED or LCD)
OSCtLLATOR ... rl ).., ......... ,; }, ...... rl)'" ......... rl
FREQUENCyJU" UUUU"UUU •• UUUU·
1_'28CYCLES~
IN:~i~~~~i ---"
,
L
1~~E?f+cY~~E~
OFF SEGMENTS
---'I
,
L
L--_---II
ON SEGMENTS _ _ _---I
Figure 2: LCD Display Waveforms
11-19
II
BUS COMPATIBLE, 4-DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
INPUT DEFINITIONS
In this table, V+ and GND are considered to be normal operating input logic levels. For lowest power consumption, input
signals should swing over the full supply.
Input
Pin No.
BO
27
V+ Logic "1"
GND Logic "0·
Condition
B1
28
V' Logic "1·
GND = Logic "0·
Twos
B2
29
V+ = Logic "1"
GND = Logic "0·
Fours
=
Function
=
Ones (Least Significant)
=
=
Data Input Bits
B3
30
V+ Logic "1"
GND Logic "0"
Eights (Most Significant)
OSC
36
Floating or w~h
external capacitor GND
Oscillator input. Disables BP output devices, allowing segments to be
synchronized to an external signal input at the BP terminal (pin 5)
=
=
DS1
31
V+ Logical One
DS2, DS1 = 00 Selects D4 }
- - - - - - - - - - - - - - - - - - - DS2. DS1 01 Selects D3
DS2
32
GND Logical Zero
DS2, DS1 10 Selects D2
DS2, DS1 = 11 Selects D1
=
=
=
Digit Select Inputs
=
CS1
33
When both CS1 and CS2 are low, the data and digit select input
V' Inactive
- - - - - - - - - - - - - - - - - - - latches are open or enabled.
On the rising of CS1 or CS2, data is latched, decoded and stored in
34
GND Active
CS2
the output drive latches.
=
OUTPUT DEFINITIONS
Output pins are defined by the alphabetical segment assignment and numerical digital assignment.
Output
Pin No.
Output
Function
A1
B1
C1
D1
E1
F1
G1
37
38
39
40
2
4
3
A Segment Drive
B
C
D
E
F
G
Digit 1
A2
6
7
8
9
10
12
11
A Segment Drive
8
C
0
E
F
G
Digit 2
82
C2
02
E2
F2
G2
(LSD)
1 11
Function
13
14
15
16
17
19
18
A Segment Drive
B
C
D
E
F
G
Digit 3
A4
20
21
22
23
24
26
25
A Segment Drive
8
C
0
E
F
G
Digit 4
B4
C4
04
E4
F4
G4
1 1
Pin No.
A3
B3
C3
D3
E3
F3
G3
1 1
1 11
DIGIT ASSIGNMENT
04
A
FQB
EClc
..
D
03
D2
01
ge08
CJ ~'L' ..
11-20
(MSD)
BUS COMPATIBLE, 4-DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
TYPICAL OPERATING CHARACTERISTICS CURVES
Operating Supply Current
vs Supply Voltage
Backplane Frequency
vs Supply Voltage
30
180
LCD DEVICES
DISPLAY BLANK
PIN 36 OPEN
25
120
:
TA=+25'C
III
60
I/. ~
TA=+70'C
2
1
3
4
5
V+VOLTS
6
o
7
LED Segment Current vs
Brightness Control Voltage
15
I- SEGMENT OUTPUT AT +3V - t -
10 I--' p..= +25'"
/
"w
1500
:;::
1200
E
:;;
}fJ
6
1
LED DEVICES
DISPLAY ALL EIGHTS
LED FORWARD
VOLTAGE DROP
VFLED=1,7V
PIN 5 ATV+
TA=+2S'C
Q.
V
600
300
I""""
5
6
!J
II
7
o
JV
IIIi/
r.I
-
- f-I
V+=5V
I-
V+=4V
234
VoVOLTS
5
6
LI
6
•
_L
If
IL
III
tL
V
0
2
3
4
VPIN5 VOLTS
5
234
5
V+VOLTS
:;::
2
o
i..-' ~6S~=\z:z~F
..... I-!-~
Cosc = 220 pF--
a: 900
w
4
1/ 1/
I.......r
,......
V+=6V
I
?;'~N)
1800
~
V
c(
r
~
~
~
Operating Power (LED Display)
vs Supply VoHage
1/
8
.'
30
,.:;~
(~IN
,/
.'
Q.
1/ b
5
o
N
;S 90
V II,
1/ V;
/ ~
10
V
f-:rA= +25'~
4o~10 ~F
lL
~
PIN5ATV+
A
150
II'
15
~1
TA = +25'C
T~=~26'C ?- -
LED Segment Current
vs Output VoHage
.
l.-'
0
4
5
V + VOLTS
11-21
6
BUS COMPATIBLE, 4-DIGIT
CMOS DECODERIDRIVER
TC7211AM
TC7212AM
BASIC OPERATION
The TC7211AM drives 4-digit, 7-segment LCOs. This
device contains 28 individual segment drivers, a backplane
driver, a self-contained oscillator, and a divider chain to
generate the backplane signal.
The 28 CMOS segment drivers and backplane driver
contain ratioed N- and P-channel transistors for identical
"ON" resistance. The equal resistances eliminate the DC
output driver component resulting from unequal rise and fall
times. This ensures maximum LCD life.
The backplane output driver can be disabled by grounding the OSCILLATOR input (pin 36). The 28 output segment
drivers can therefore be synchronized directly to an input
signal at the backplane (BP) terminal (pin 5). Several slave
devices may be cascaded to the backplane output of a
master device. The backplane signal may also be derived
from an external source. These features permit interfacing
to single backplane LCOs with characters in mUltiples of
four.
Each slave's backplane input represents only a 200 pF
capacitive load to the master backplane driver (comparable
to one additional segment). The number of slave devices
drivable by a master device is therefore set by the larger
display backplane capacitive load. The master backplane
output will drive the display backplane of 16 one-half-inch
characters with rise and fall times under 51J.S. This represents
a system with three slave devices and a fourth master device
driving the backplane. (See Figure 1.)
If more than four devices are slaved together, the
backplane signal should be derived externally and all
TC7211AM devices slaved to it. The external drive signal
must drive a high capacitive load with 1~s to 2 ~s rise and
fall times. The backplane frequency is normally 125 Hz. At
lower display ambient temperatures, the frequency may be
reduced to compensate for display response time.
The on-chip RC oscillator free-runs at approximately
16 kHz. A +128 circuit provides the 125 Hz backplane
frequency. The oscillator frequency may be reduced by
connecting an external capacitor between the oscillator
terminal and V+. (See typical operating characteristics
curves.)
The free-running oscillator may be overridden (if desired) by an external clock. The backplane driver, however,
must not be disabled during the external clock's negative or
low portion, as this will result in a DC drive component
being applied to the LCD, limiting the LCD's life. To prevent backplane driver disabling, the oscillator input should
be driven from the positive supply to no less than one-fifth
the supply voltage above ground. A backplane disable
signal will not be sensed if the driving signal remains above
ground by one-fifth the supply voltage. An altemate method
for externally driving the oscillator permits the oscillator input
to swing the full supply voltage range.
The oscillator input signal duty cycle is skewed so the low
portion duration is less than 1 ~s. The backplane disable
sensing circuit will not respond to such a short signal.
D8 D7 06 05104 D3 02 01
..,,,
TC7211AM
SELECT
DIGIT
1:::===~t:=======~
Figure 3. TC7211AM Driving an 8-Digit LCD Display
in Master/Slave Configuration
TC7212AM LED Decoder/Driver
The TC7212AM directly drives 4-digit, 7-segment, common-anode LED displays. The 28 segment drivers are low
leakage, current controlled, open drain N·channel MOS
transistors.
A brightness input (pin 5) can be used in two ways to
control output transistor drain current. The voltage at the
brightness control input is transferred to the output transistor
gate for "ON" segments. The brightness voltage directly
modulates the segment drivers "ON" resistance. A variable
brightness control may be implemented with a single potentiometer (Figure 4). A high value potentiomenter (1 00 kil
to 1 Mil ) will minimize power consumption.
The brightness input may also be operated digitally as
a display enable. At a logic 1 the display is fully "ON" and at
a logic signal of varying duty cycle also. When operating with
LEOs at a higher temperatures and/or higher supply voltages, the device power dissipation may need to be reduced
to prevent excessive chip temperature rise. The maximum
power dissipation is 1 watt at 25° C. Derate linearly above
35°C to 500 mW at 70°C (-15 mW/oC above 35°C). Power
dissipation for the device is given by:
P = (V+ -VFLED) (ISEG) (nsEG)
where VFLED is the LED forward voltage drop, ISEG is segment current, and nseg is the number of "ON" segments. If
11-22
BUS COMPATIBLE, 4·DIGIT
CMOS DECODER/DRIVER
TC7211AM
TC7212AM
the device is operated at elevated temperatures, the segment current can be limited through the brightness input to
keep power dissipation within the limits described above.
The display may be blanked (all segments OFF) by
applying the input code 1111 or by driving the brightness pin
witha logic ). If brightness control is not needed, pin 5 should
be tied to 5.0 V.
100 kfi - lMO
F
_
Table 1: Output Code
B3
0
0
0
0
0
0
0
0
1
1
V+(LED ANODES)
TO BRIGHTNESS CONTROL
(PINS)
Figure 4. Brightness Control
Input Configuration and Output Codes
The TC7211AM accepts a 4-bit, true binary (positive
level =logic "1") input at pin 27 (LSB) through pin 30 (MSB).
The binary input is decoded to the 7 -segment output known
as Code B. The output display format is 0 to 9, - , E, H, L,
P and blank display (see Table I). Segment assignments are
shown in Figure 2. The TC7211AM will correctly decode
binary and BCD true codes to a 7-segment output.
The TC7211 AM is designed to interface with a data bus
and display data under microprocessor control. Four data
inputs (pins 27-30) and two digit select input bits (pins 31
and 32) are written into input buffer latches. The rising edge
of either chip select causes data to be latched, decoded and
stored in the selected digit ouptut data latch. The 2-bit digit
code selects the appropriate output digit latch. The 4-bit
display data word is decoded to the "Code B" 7-segment
output format.
For applications where bus compatibility is not required,
refertothe TC7211A (LCD) 4-digitdecoderdriverdatasheet.
This device is designed to accept multiplexed BCD/binary
input data for display under the control of four separate digit
select control signals.
Binary Input
B2
B1
BO
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
CodeB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
E
H
L
P
Blank
Figure 2. Segment Assignment
Special Order Decoder Option
The TC7211A is mask programmed to give the 16
combinations of 7-segment output codes. For large volume
orders (50K pieces minimum), custom decoder options are
available. Contact Teledyne Components for details.
Applications Information
The TC7212AM has two ground pins. These pins should
be connected together.
11-23
III
NOTES
11·24
"'~TELEDYNE
COMPONENTS
TC9404
SERIAL INPUT/16-BIT PARALLEL OUTPUT PERIPHERAL DRIVER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The TC9404 is a serial inputl16-bit parallel output shift
register. High output power MOS switching transistors make
the TC9404 an ideal interface circuit between microprocessor I/O ports and high current/voltage peripherals.
The CMOS construction limits quiescent power dissipation
t020mW.
The TC9404 common-source, open-drain MOS outputs
sustain 15V in the OFF state and maintain leakage currents
under 1 00 ~A. The 16 parallel outputs continuously sink 60
High Voltage Outputs ......................................... 1SV
High Output Current Sink Capability ..•..••...•• 60 mA
Low Standby Power •••••••••.••.••.••••..•.....•...•..•.. 20 mW
High-Speed Operation .................................... 3 MHz
16 Parallel Outputs
Cascading Possible for Longer Data Words
APPLICATIONS
•
•
•
•
Incandescent Lamp Driver
Thermal Printhead Driver
LED Bar-Graph Driver
High Current, Microprocessor Serial Port
Extender
\
Relay/Solenoid Driver
Tungsten Lamp Driver
SCR Gate Driver
•
•
•
rnA (VSAT!!, 0.5V).
Successive connection of serial data outputs to serial
data inputs makes longer length seriaJ-to-parallel
conversions possible. Device cascading makes the TC9404
an ideal thermal print head or high-resolution LED bar-graph
driver.
II
SIMPLIFIED SCHEMATIC
V+
LOGICGND
CLOCK~~-----.--.--.--+--.--+--.--1--1~~~~~~~-.--.-~
SERIAL
DATA
INPUT
OUTPUT
Ji
SERIAL
DATA
OUTPUT
7
17
GND1~12~~__~~~. .~~. .~~~~~~~~~~~~~. .~~~~__~~
~--~~+-~~~~~~~~~~~~~~~~~~
9 10 11
13
8
OUTPUT
GND
"v"v"v - - -0 VB
.,'"
TC9404
RLOAD
Ql
Q2
Q3
Q4
Q5
~
Q7
Q8
Q9
Ql0 Q11 Q12 Q13 Q14 Q15 Q16
NOTE: Logic "1' serial data input bit turns output NMOS on.
1034·1
11·25
SERIAL INPUT/16-BIT PARALLEL
OUTPUT PERIPHERAL DRIVER
TC9404
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to Logic Ground) ............................ 7V
Digital Logic Input Voltage ......................................... 5.5V
Parallel Output Drain Voltage ...................................... 22V
Parallel Output Drain Current .................................. SO rnA
Logic Ground to Output Ground
Potential Difference ........................................ 100 mV
Package Power DiSSipation
CerDIP ................................................... 1W @ +S5°C
CerDIP .............................................. 0.4W @ +125°C
Plastic Package ..................................... 1W @ +70°C
Operating Temperature
CerDIP (IJ) .................................. -25°C!> TA!> +S5°C
CerDIP (MJ) .............................. -55°C!> TA!> +125°C
Plastic Package(CP) ....................... O°C!> TA!> +70°C
Storage Temperature ...................... --65°C!> TA!> +150°C
Lead Temperature (Soldering, 60 sec) .................. +300°C
SERIAL DATA
INPUT
LOGICGND 2
Ql
ORDERING INFORMATION
Part No.
Package
TC9404CPG
24-Pin
Plastic DIP
24-Pin
CerDIP
24-Pin
CerDIP
TC94041JG
TC9404MJG
Temperature
Range
Output
Voltage
O°Cto +70°C
15V
-25°C to +85°C
15V
-55°C to + 125°C
15V
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above Ihose listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
Ihose indicated in the operational sections of Ihe specifications is not
implied. I;:xposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
11-26
SERIAL INPUTI16-BIT PARALLEL
OUTPUT PERIPHERAL DRIVER
TC9404
ELECTRICAL CHARACTERISTICS: VS = 5V. O°C ~ TA ~ +70°C for TC9404CPG and -25°C ~ TA ~ +85°C
for TC94041JG. and -55°C to +125°C for TC9404MJG. unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
0.35
0.5
V
V
Unit
Output
-
VSAT
Output ON Voltage
VB
I/O
Output OFF Voltage
-
-
15
Output Sink Current
VSAT sO.5V (Note 1)
60
-
mA
lox
Output Leakage Current
Vs = 4.75V. VB = 15V
-
-
100
~A
VOH
Serial Output
Logic "1" Voltage
IOH = 400 ~A
10H = 10 ~A
2.4
4.5
VOL
Serial Output
Logic "0" Voltage
IOL=5mA
-
VrNH
Logic '1" Input Voltage
Vs= 5.25V
3.3
VINL
Logic "0" Input Voltage
Vs= 5.25V
IrNH
Logic "1" Input Current
Vs= 5.25V
-
IINL
Logic "0" Input Current
VINL= 0.4V
Vs= 5.25V
CIN
Input Capacitance
VINL= OV
10= 60 mA
Vs= 4.75V
-
-
--
V
V
0.4
V
-
V
0.8
V
Input
-
-
-
400
-
15
-
~A
20
V
~A
Timing
tDH
Serial Input
Data Hold Time
20
0
-
ns
tDS
Serial Input
Data Set-Up Time
100
70
-
ns
-
MHz
tcp
Clock Frequency
tpw
Clock Pulse Width
tpLH
Parallel Output
Low-to-High
Transition Time
tPHL
tSLH
IsHL
"
3
5
150
100
VB = 15V
RL = 3300
CL = 25 pF
-
-
150
ns
Parallel Output
High-to-Low
Transition Time
VB = 15V
RL= 3300
CL = 25 pF
-
-
150
ns
Serial Output
Low-to-High
Trans~ion Time
-
-
150
ns
CL = 25 pF
-
-
75
ns
V
Serial Output
High-to-Low
Transition Time
IOH=400~A
IOL=5mA
CL = 25 pF
-
ns
Power
Vs
Operating Supply Vo~age
Is
Quiescent Power Supply
Vs= 5.25V
Ic= 0 Hz
VIHL= OV
lo=OmA
Pin 22 Open
NOTE 1. Maintain chip temperature :5:150°C.
11-27
4.75
5
5.25
-
1
4
mA
III
SERIAL INPUT/16-BIT PARALLEL
OUTPUT PERIPHERAL DRIVER
TC9404
FUNCTION TABLE
TIMING DIAGRAMS
a) Serial Input Data Hold and Set-Up Times
O%
~
Data Input
ON
.
Q1
Q2
Q3
L
01
02
03
... 016
L*
01
02
... 015
H*
01
02
015
X
. CLOCK=t;O%
50%
Parallel Outputs
Clock Input
H
SERIAL
DATA
INPUT
50%
tDS
L
f
f
tDH
I'7J77l DATA TRANSITIONS
rttad
ALLOWED
L= Logic 0
H = Logic 1
L* = Output NMOSON
b) Serial Output Transition Times
H* = Output NMOS OFF
X = Don't Care
CLOCK
SERIAL
f
I'-_ _ _ OUTPUT
%
t;
c) Parallel Output Transition Times
50%
CLOCK
ff%
P~~biL
= Transition from Low-to-High
01, 02, ... 016 = Data inputs at clock time T-N.
Data is inverted at the parallel outputs.
50%
tpLH
tpHL
11-28
••• Q16
SERIAL INPUT/16-BIT PARALLEL
OUTPUT PERIPHERAL DRIVER
TC9404
APPLICATIONS
Microprocessor-Controlled LED
Bar-Graph Display
Thermal Printhead Driver
PRINT VOLTAGE
SINGLE BOARD MICROCOMPUTER
(SYM-Ol)
SERIAL
DATA
INPUT
+5V
CLOCK
~'"
TC9404
GND
DATA
INPUT
t------oVB
~'"
TC9404
LED BAR-GRAPH DISPLAY
V+
+5V
11-29
GND
•
NOTES
11-30
..,"'TELEDYNE
COMPONENTS
TC9405
16-BIT PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
FEATURES
Saturation Voltage vs Sink Current
90
I-
80
TA = 25°C
VB = 15V
./
70
,/'
60
1
50
ffi
30
./
~ 40
./
/"
•
,/
20
10
o
•
•
•
•
•
•
•
o
/
V
0.05
0.1
0.15
0.2
0.25
High Voltage Outputs ..................... 15V
High Output Current Sink Capability ...... 60 rnA
Low Standby Power .................... 1 rnW
High-Speed Operation .................. 3 MHz
16 Latched Parallel Outputs
Cascading Possible for Longer Data Words
Dual-Rank Latches and STROBE Input for
Ripple-Free Data Update
OUTPUt ENABLE Input Disables Outputs
Without Corrupting Data
0.3
VOUT(V)
FUNCTIONAL DIAGRAM
III
..,~
TC940S
cLocKO=4r----~~r_~~~~~--.__.--.__.--~~--~~--~,
SERIAL
DATA
OUTPUT
SERIAL
DATA
INPUT
STROBE~4r----~~~~~~~~~~~~~~~~.,~~.,~~
0Ii'i'PITi'
ENABLE
RLOAD
3
4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Qs
Ql0 Q11 Q12 Q13 Q 14 Q15 Q16
--------~RLOAD
~- - - - - ---
VB
VB
1035-1
Q9
11-31
16.. 81T PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
TC9405
GENERAL DESCRIPTION
APPLICATIONS
The TC9405 is a serial input, 16-bit parallel-latched
output shift register. Master/slave data latches and high
output power MOS switching transistors combine to make
the TC9405 an ideal interface circuit between microprocessor 1/0 ports and high currentlvoltage peripherals. The
CMOS construction limits quiescent power dissipation to
1 mW.
The TC9405 common-source, open-drain MOS outputs sustain 15V in the OFF state and maintain leakage
currents under 100 1lA. The low output ON resistance
allows all 16 channels to simultaneously sink 60 rnA with a
saturation voltage of 0.5V maximum and power dissipation
of 480 mW. Typical power dissipation of 16 channels sinking
60 rnA is only 325 mW.
Dual rank latches and a STROBE input permit glitchfree data updating. With the STROBE input high, data is
entered into master latches on each rising edge of the
CLOCK input. When STROBE is brought low, data is
transferred to the slave latches simultaneously. An OUTPUT
ENABLE (OE) input is also included, so that all outputs can
be turned off. Both STROBE and OUTPUT ENABLE are
asynchronous, level-sensitive inputs.
Successive connection of serial data outputs to serial
data inputs make longer length serial-to-parallel conversions possible. Device cascading makes the TC9405 an
ideal thermal printhead, high-resolution LED bar-graph, or
incandescent lamp driver.
•
•
•
•
•
•
•
Incandescent Lamp Driver
Thermal Printhead Driver
LED Bar-Graph Driver
High Current, Microprocessor Serial Port Expander
RelaylSolenoid Driver
Tungsten Lamp Driver
SCR Gate Driver
PIN CONFIGURATIONS
SERIAL DATA 1
INPUT
S'i'ROBE 2
ORDERING INFORMATION
Part
Package
Temperature Range
Output Voltage
24-Pin Plastic DIP
O°Cto +70°C
15V
TC94051JG
24-Pin CerDIP
-25°C to +85°C
15V
TC9405MJG
24-Pin CerDIP
-55°C to +125°C
15V
TC9405CPG
11-32
16-BIT PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
TC9405
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Voo to Ground) .................. 7V
Digital Logic Input voltage ..................... 5.5V
Parallel Output Drain Voltage ................... 18V
Parallel Output Drain Current ................. 80 mA
Package Power Dissipation
CerDIPPackage .................... 1VV@85°C
CerDIP Package .................. 0.4VV @ 125°C
Epoxy Package ..................... 1VV@ 70°C
ELECTRICAL CHARACTERISTICS
Symbol
Operating Temperature
CerDIP Package (IJG) ........ -25°C"" TA "" +85°C
CerDIP Package (MJG) ...... -55°C "" TA "" +125°C
Epoxy Package (CPG) ......... O°C "" TA "" +70°C
Storage Temperature .......... --65°C "" TA "" +150°C
Lead Temperature (Soldering, 60 sec) ........ +300°C
Voo = 5V
TA
TC9405C ............. O°C to +70°C
TC94051 ............ -25°C to +85°C
TC9405M .......... -55°C to +125°C
Parameter
Test Conditions
Unit
V ,NH
Logic 1 Input Voltage
Voo =5.25V
2.4
V,NL
Logic 0 Input Voltage
V oo =5.25V
I'NH
Logic 1 Input Current
V ,NH = 2.4V
Voo = 5.25V
I'NL
Logic 0 Input Current
V ,NL = 0.8V
Voo =5.25V
Input
-
V
-
-
0.8
V
-
-
40
~
-
-
40
~
15
-
pF
0.4
V
-
C'N
Input Capacitance
VOH
Serial Output
Logic 1 Voltage
10H = 400 J.IA
10H = 10 J.IA
2.4
4.5
VOL
Serial Output
Logic 0 Voltage
10L =3.6 mA
-
0.25
0.4
V
-
-
0.6
V
15
V
Y'N =OV
4.7
4.98
-
V
V
Output
V SAT
Output ON Voltage
10 = 60 mA
Voo = 4.75V, TA = 24°C
(Note 2)
VSAT
Output ON Voltage
10=60 mA
Voo = 4.75V, TA = FULL
(Note 2)
VB
Output OFF Voltage
10
Output Sink Current
V SAT ",,0.6V
(Note 1)
60
-
-
rnA
lox
Output Leakage Current
Voo =4.75V
VB = 15V
-
-
100
~
11-33
III
16-BIT PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
TC9405
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Timing
tDH
Serial Input
Data Hold Time
TA :: 25°C
40
20
-
ns
tDS
Serial Input
Data Set-Up Time
TA .. 25°C
50
0
-
ns
fc
Maximum Clock Frequency
TA = 25°C
3
5
MHz
tpw
Clock Pulse Width
TA = 25°C
150
100
-
tpLHl
Parallel Output
Low-to-High
Transition Time
STROBE = LOW
OE = LOW
(Note 3 and Figure 1)
-
-
300
ns
tpHLl
Parallel Output
High-to-Low
Transition Time
STROBE = LOW
OE = LOW
(Note 3 and Figure 1)
-
-
300
ns
tpLH2
Parallel Output
Low-to-High
Transition Time
STROBE = ' - OE:: LOW
(Note 3 and Figure 1)
-
-
300
ns
tpLHL2
Parallel Output
High-to-Low
Transition Time
STROBE='-OE = LOW
(Note 3 and Figure 1)
-
-
300
ns
tpLHE
Parallel Output
Low-to-High
Transition Time
STROBE = Don't Care
OE .. f
(Note 3 and Figure 1)
-
-
250
ns
tpHLE
Parallel Output
High-to-Low
Transition Time
STROBE - Don't Care
OE=,-(Note 3 and Figure 1)
-
-
250
ns
tSHL
Serial Output
High-to-Low
Transition Time
IOL =3.6 rnA
CL = 25 pF, TA '" 25°C
-
-
150
ns
tSLH
Serial Output
Low-to-High
Transition Time
IOH'" 400 IJA
CL '" 25 pF, TA = 25°C
-
-
150
ns
tspw
Strobe Pulse Width
TA '" 25°C
80
-
-
ns
+4.75
+5
+5.25
V
-
50
200
IJA
ns
Supply
VDD
Operating Supply Voltage
Is
Quiescent Power Supply
VDD '" 5.25V, fc '" 0 Hz
V1NL =OV, lo=OmA
Pin 22 Open
NOTES:
1. Maintain die temperature '" 150°C.
2. VSAT increases by 0.1 V when all outputs are sinking 60 rnA due to internal ground drop and self-heating.
3. VB = 15V, Rl = 330Q, Cl = 25 pF, TA = 25°C.
11-34
16-BIT PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
TC9405
FUNCTION TABLE
Figure 1. Timing Diagrams
Data
Input
a) Serial Input Data Hold and Set-Up Times
O%
~
50%
~S
OE
CLOCK=t;0%
SERIAL
DATA
INPUT
50%
~H
F'77'J7,1 DATA TRANSITIONS
~ ALLOWED
STROBE
Parallel Outputs
(ON)
Clock
Input
a,
L
L
L
X
L
L
H
L
L
L
L
H
X
X
H
X
X
X
f
f
O2
a. ... 0,.
D,
D2
D3 ... D,.
L*
D,
D2 ... D'5
H*
D,
D2 ... D'5
Maintains Last
Valid State
H*
H*
H*
H*
b) Serial Output Transition Times
L =Logic 0
H = Logic 1
L* = Output NMOS ON
H* = Output NMOS OFF
X =Don't Care
f = Transition from low-to-high
D" D2, .. .D'6 = Data outputs before the low-to-high
transition of the clock
c) Parallel Output T~sition Times
(STROBE = Low, OE = Low)
NOTE: OE and STROBE inputs are level-sensitive, nol edge-triggered.
: ,::,
~
50%
OUTPUT _
.....-'1
tpHL1
d) STROBE Input Transition Times
(OE= Low)
O"I.
~
50%
e)
S'i'Ro'BE
=tf0%
PARALLEL
OUTPUT
tpHL2
50%
tpLH2
0lifP0T ENABLE Transition Times
(STROBE = Don't Care)
~
O%
50%
ENABLE
0iJi'iiliT
PARALLEL
OUTPUT
tpHLE
~O%
50%
tpLHE
11-35
16-BIT PARALLEL-LATCHED OUTPUT
PERIPHERAL DRIVER
TC9405
APPLICATIONS
MICROPROCESSOR CONTROLLED LED
BAR-GRAPH DISPLAY
SINGLE BOARD MICROCOMPUTER
(SYM-01)
BONDING DIAGRAM
+5V
~"l
au",,,
...-.-0.•
"--Q.~
OE
SERIAL
DATA
INPUT
J!]
CLOCK
".~
..,~
TC9405
1------oVB
LED BAR·GRAPH DISPLAY
THERMAL PRINTHEAD DRIVER
PRINTo-_....._
VOLTAGE VB
......-
......- , - - , - - r - - - - , - - - - , - - + -......---,
THERMAL PRINTHEAD
Q1
SERIAL
DATA
INPUT
DATA
INPUT
GND
Q2 -
-
-
Q1
Q16
..,~
TC9405
SERIAL
OUTPUT
STROBE
OE V+
------
DATA
INPUT
V+
+5V
STROBE
UNES
11-36
Q2 - - -
Q16
..,~
TC9405
bE
-=
Section 12
Analog Switches and
Multiplexers
Display AID Converters
Binary AID Converters
2
Voltage-to-FrequencY/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog SwHches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
"~TELEDYNE
COMPONENTS
CDG201
MONOLITHIC CMOS/DMOS, QUAD SPST ANALOG SWITCH
FEATURES
GENERAL DESCRIPTION
•
•
•
The CDG201 features TTL-compatible input logic and
wideband lateral DMOS switches on a single chip. The onchip reference used for TTL compatibility gives an added
advantage of constant logic switching over a wide range of
supply voltages and temperature without a separate power
supply. Industry-standard pinout makes the CDG201 particularly suitable for replacing existing analog switches,
while upgrading high-frequency performance.
•
•
High OFF Isolation •••...•••.••..••••.•.••• 66 dB @ 10 MHz
Wide Bandwidth Switches ••..•.••.. -1 dB @ 100 MHz
Low Channel-to-Channel
Cross Talk ••••.••••.•.••....••.•••••..•.••..•. -80 dB @ 10 MHz
TTL Compatible
Industry-Standard Pinout
APPLICATIONS
•
•
•
•
Glitch-Free Analog Switching
RF and Video
Track-and-Hold
Sample-and-Hold
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
y+
lEI
NC
NOTES:
1. Four SPST switches per package.
2. Switches shown in logic "1" (OFF) position.
3. ON = Logic '0' ,.;; O.BY.
OFF = Logic '1' ,.;; 2.4V.
12-1
= NO INTERNAL CONNECTION
MONOLitHIC CMOS/DMOS,
QUAD SPST ANALOG SWITCH
CDG201
ORDERING INFORMATION
Part No.
Package
ABSOLUTE MAXIMUM RATINGS
operating
Temperature Range
CDG201COE
16-Pin Plastic SO
O·C to +70°C
CDG201CPE
CDG201EOE
CDG201EPE
16-Pin Plastic DIP
16-Pin Plastic SO
16-Pin Plastic DIP
-40°C to +S5°C
-40°C to +S5°C
CDG201EJE
CDG201MJE
16-Pin CerDIP
16-Pin CerDI P
-40°C to +S5°C
-55°C to + 125°C
O°Cto +70°C
RECOMMENDED OPERATING CONDITIONS
Negative Supply Voltage ............................... -8V to -15V
Positive Supply Voltage ................................. +SV to + 15V
Control Input Voltage Range ............................. OV to +5V
Operating Temperature Range
C Suffix ................................................ O°C to +70°C
E Suffix ............................................ -40°C to +S5°C
M Suffix .......................................... -55°C to +125°C
ELECTRICAL CHARACTERISTICS:
Symbol
Supply Voltage .......................................................... ±20V
Control Input Voltage Range .............. V+ +O.3V, V- -o.3V
Continuous Current, Any Pin Except S'or D ........... 20 rnA
Continuous Current, S or D ..................................... 30 rnA
Peak Pulsed Current, S or D,
SO ~s, 1"10, Duty Cycle ...................................... gO rnA
Maximum Junction Temperature ........................... + 150°C
Storage Temperature Range .................. -65°C to +150°C
Power Dissipation
(Derate at 5.5 mW/oC, Above +S5°C) ............ 500 mW
NOrE:: All devices contain diodes to protect inputs against damage due to
high-static voltages or electric fields. However, it is advised precautions be
taken not to exceed maximum recommended input voltages. All unused
inputs must be connected to an appropriate logic level (Voo or GND).
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
TA=+25°C, V-=-15V, V+=+15V
Parameter
Test Conditions
I Min I Typ I Max I Unit
Static
VANALOG
Analog Signal Range
rDS(ON)
Switch ON Resistance
Vs = +2V, VIN = OV
Vs = +10V, VIN = OV
High Level Input Voltage,
Logic "1" (OFF)
VIH
-10
+10
V
0
45
100
SO
0
0
2.4
-
-
V
-
-
O.S
V
-
0.Q1
0.1
0.1
~A
0.02
-
0.2
-
-
-
VIL
Low Level Input Voltage,
Logic "0" (ON)
liN
Logic Input Leakage Current
VIN= +15V
-
ID(OFF)
Switch OFF Leakage Current
VD = +10V, Vs = -10V, VIN = +2.4V
IS(OFF)
Sw~ch OFF Leakage Current
Vs = +10V, VD = -10V, VIN = +2.4V
11+
Negative Supply Quiescent Current
VIN = OV to +2.4V
Pos~ive Supply Quiescent Current
tON
tOFF
OIAR
CCRR
Cross-Coupling Rejection Ratio
CD
Drain-Node Capacitance
Cs
Source-Node Capac~ance
VIN= +2.4V
40
SO
160
Vs=-10V, VIN=OV
~A
5
nA
0.4
5
nA
-0.3
-1
mA
VIN = OV to +2.4V
-
0.6
2
mA
Switch· Turn-On Time
See Switching Times Test Circuit
-
400
600
ns
Switch Turn-Off Time
See Switching Times Test Circuit
-
70
300
Off Isolation Rejection Ratio
f = 10 MHz, RL= 500
f = 10 MHz, RL= 500
VD = Vs = OV, f = 1 MHz, VIN = +2.4V
VD = Vs = OV, f = 1 MHz, VIN = +2.4V
60
66
DynamiC
12-2
-
SO
-
0.3
-
3
-
ns
dB
dB
pF
pF
MONOLITHIC CMOSIDMOS,
QUAD SPST ANALOG SWITCH
CDG201
ELECTRICAL CHARACTERISTICS:
V- =-15V, V+ = +15V
Limits at Temperature Extremes
Symbol
Unit
Test Conditions
Parameter
Static
VANALOG
rDS(ON)
Analog Signal Range
Switch ON Resistance
±10
80
80
160
±10
80
80
160
±10
±10
±10
V
Vs = -10V, VIN = OV
Vs = +2V, VIN = OV
Vs=+10V, VIN=OV
120
120
240
120
120
240
150
150
300
n
n
n
liN
Logic Input Leakage Current
VIN = +2.4V
VIN = +15V
0.1
0.1
0.1
0.1
1
2
1
2
10
20
ID(OFF)
Switch OFF Leakage Current
VD = +10V, Vs = -10V,
VIN= +2.4V
5
5
100
100
1000
itA
itA
nA
IS(OFF)
Switch OFF Leakage Current
Vs = +10V, VD = -10V,
VIN= +2.4V
5
5
100
100
1000
nA
I
Negative Supply Quiescent Current
VIN = OV to +2.4
-1
-1
-1
-1
-1
mA
1+
Positive Supply Quiescent Current
VIN = OV to +2.4
2
2
2
2
2
mA
SWITCHING TIMES TEST CIRCUIT
TEST WAVEFORMS
3V
+15V
SWITCH
INPUT 0-+----0,...+3V
LOGIC INPUT:
tR<6ns
tF< 4 ns
SWITCH
OUTPUT
50"10
A--+-o~~---,--OVO
SWITCH INPUT
-+---------+--
LOGIC
INPUT
90%
SWITCH OUtPUT
OV
-15V
NOTE: Switch shown in logic "1" (OFF) position.
12-3
90%
MONOLITHIC CMOS/DMOS,
QUAD SPST ANALOG SWITCH
CDG201
. TYPICAL CHARACTERISTICS CURVES
Switching Times vs
Ambient Temperature
Switching TImes vs
Supply Voltage
800
800
V-, V+=:t15V
700 -R L =50!l
cL = 12 pF
.. 600 -VS=3V
VS=3V
700 I-RL = son
CL 12pF
r-- TA " +25°C
=
:[600
.s
~ 500
1=
(!I
z
J:
~ 500
,
400
1=
toN
(!I
z
400
J:
~ 300
g 300
~
~
200
-toFF
100
o
7.5
10
12.5
:t SUPPLY VOLTAGE (V)
5
o
15
9">" 2.0
!:!
(!I
9
~
'oFF
I
0 25 50 75 100 125 150
AMBIENT TEMPERATURE (OC)
Supply Currents vs
Ambient Temperature
0.7
2.1
II:
---
-
-SO -25
TA= +25°C
i!:
~
100
2.2
~ 1.9
-
r-
200
Logic Threshold vs
Supply Voltage
o
,.-
~
./
,./
V
0.6
/
I'----~
I'----
C("
.s 0.5
!z
~ 0.4
II:
::J
o 0.3
1.8
8:
r-..... r-..
0.2
::J
(J)
1.6
0.1
" "
......
~
1.7
1+
v-, V+=:t15V
1-
----r-
I"-..
-
VIN =+2.4V
o
1.5
8
9
10
11
12
13
14
:t SUPPLY VOLTAGE (V)
15
-50 -25
0
25 50
75 100 125
AMBIENT TEMPERATURE (OC)
12-4
MONOLITHIC CMOS/DMOS,
QUAD SPST ANALOG SWITCH
CDG201
TYPICAL CHARACTERISTICS CURVES (Cont.)
Insertion Loss vs Frequency
Switch-Off Isolation Rejection Ratio vs Frequency
o
100
z
~
90
w
80
.,0w
. ....
RL=l kQ_
..
a:
z~
OlD
g~
70
~
60
!lla: 50
LL
2
III
III
3
....t
Z
4
0
r"-r-.,
O!;(
iii
:!!.
0
~
LL
RL=50Q
a:
w
5
3:
6
VI
9
40
::t:
T A =+25"C
30 f- Y-, y+= :t15Y
RL=50!1
20
1
2
5
10 20
FREQUENCY (MHz)
0
I-
§:
III
S
50
100
1
Switch-On Resistance vs Analog Voltage
z
;!
TA = +125"C
125
!ll
III
w 100
a:
TA=+85"\
75
!ll
50
9
I-
50
z
~
~
TA= +25"C
25
-10
-5
0
5
SOURCE VOLTAGE (V)
80
I
70
Y-, Y+=:tSY
w 60
0
I
50
Y-, Y+=:t15Y
!ll
VI
-
I
I-~
o
~
0.6
~
0.5
a:
i--"
15
!:! 0.4
1
J I
YS = 0.3 YRMS
....t
I .11.1 III.
0 0 .1
I-
RL = 1 kQ, Ys = 1 YRMS
12-5
'\
f\
o
1
100
rtf4.J.
-RIL=~U,ll ~
;!
ITil
5
10 20
50
FREQUENCY (MHz)
0.3
I I II
I J I[
RL = 50 kQ, Ys = 1 YRMS
!li::t: 0.2
~
2
Y-, y+= :t15Y
TA = +25"C
z
20 f-TA = +25"C
RL=50Q
VI 10 f-Y =O.l Y
s
RMS
-I
7.5
10
12.5
:t SUPPLY YOLTAGE (V)
O.S
~
30
1
I
I I
e...O.7
z
~
o
~
15
Total Harmonic Distortion YS Frequency
a:
~
I
5
w 40
z
TA= ;S5"C
r-:::: ~
:::-~
TA= +25"C
25
10
Switch-On Resistance YS Frequency
z
;!
100
o
o
§:
100
II II
125
~t:fZC
I"75
!fi
a:
/
...:::;: ~ V
::t:
0
50
RL=50Q
175 YS=O.l YRMS
f= 1 KHz
~ 150
./~ ~
z
3:III
§:
/
w 150
0
I-
5
10 20
FREQUENCY (MHz)
200
Y-, Y+=:t15Y
RL=50Q
§:175
z
9
2
Switch-On Resistance YS Supply Voltage
200
;!
TA = +25"C
Y-, y+= .,15Y
YS =O.l YRMS
7
4
10
40
FREQUENCY (MHz)
NOTES
12-6
~~TELEDYNE
COMPONENTS
CDG211
QUAD MONOLITHIC, SPST CMOS/DMOS ANALOG SWITCH
FEATURES
GENERAL DESCRIPTION
•
•
•
Teledyne Components' CDG211 low-cost analog switch
features TTL-compatible input logic and wideband lateral
DMOS switches on a single chip. The on-chip reference
used for TTL compatibility gives the added advantage of
constant logic switching over a wide range of supply voltages and temperature without a separate power supply.
Industry-standard pinout makes the CDG211 particularly
suitable for replacement of existing analog switches and
upgrading high frequency performance at the same time.
High OFF Isolation ••...•.••..•••.•..••••.• 66 dB @ 10 MHz
Wide Bandwidth Switches .••. 0.9 x DC @ 100 MHz
Low Channel-to-Channel
Cross Talk .................................... -80 dB @ 10 MHz
TTL Compatible
Low OFF Leakage
Industry-Standard Pinouts
•
•
•
APPLICATIONS
•
Switches
- Glitch-Free Analog
- RF and Video
- Track-and-Hold
- Sample-and-Hold
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
(TOP VIEW)
NC = NO INTERNAL CONNECTION
NOTES: 1. Four SPST switches per package.
2. Switches shown in logic "1" (OFF) position.
3. ON = Logic '0' .. C.BV
OFF = Logic '1' .. 2.4V
1063·1
(TOP VIEW)
12-7
QUAD MONOLITHIC, SPST
CMOSIDMOS ANALOG SWITCH
CDG211
ORDERING INFORMATION
Part No.
Package
CDG211CJ
CDG201DY
16-Pin Plastic DIP
16-Pin SO
RECOMMENDED OPERATING CONDITIONS
Operating
Temperature Range
O·Cto +70·C
-40°C to +85°C
YY+
YIN
Ys
Top
Negative Supply Yoltage ....................... -8Y to -15Y
Positive Supply Yoltage ........................ +8Y to +15Y
Control Input Yoltage Range ..................... OY to +5Y
Analog Switch Yoltage Range .......................... ±10Y
Operating Temperature Range
C Suffix ............................................ O°C to +70°C
D Suffix ........................................ -40°C to +85°C
NOTE: All devices contain diodes 10 protect inputs against damage due to
high static voltages or electric fields; however, it is advised that precautions
be taken not 10 exceed the maximum recommended input voltages. All
unused inputs must be connected 10 an appropriate logic voltage level (Voo
orGND).
ABSOLUTE MAXIMUM RATINGS
YY+
YIN
IL
Negative Supply Yoltage .................................. -20Y
Positive Supply Yoltage .................................... +20Y
Control Input Yoltage
Range ......................................... Y+ +0.3Y, Y- -O.3Y
Continuous Current, Any Pin Except S or D ... 30 mA
Is
Is
Continuous Current, S or D ............................ 30 mA
Peak Pulsed Current, S or D,
80 IJ.S, 1%, Duty Cycle .................................... 90 rnA
Tsm Storage Temperature Range ......... -55°C to +125°C
PD Power Dissipation ........................................ 500 mW
ELECTRICAL CHARACTERISTICS: TA = +25°C, Y- = -15Y, Y+ = + 15Y per channel, unless otherwise noted.
Symbol
Parameter
Static
VANALOG
rOS(ON)
Analog Signal Range
Switch ON Resistance
Test Conditions
Vs = -10V, VIN = 0
Vs= +2V, VIN = 0
Vs = +10V, VIN = 0
VIH
VIL
liN
High Level Input Voltage
Low Level Input Vo~age
Logic Input Leakage Current
IO(OFF)
IS(OFF)
I
1+
Switch OFF Leakage Current
Switch OFF Leakage Current
Negative Supply Quiescent Current
Positive Supply Quiescent Current
VIN= +2.4V
VIN = +15V
Vo=+10V, Vs=-10V, VIN= +2.4V
Vs +10V, Vo = -10V, VIN = +2.4V
VIN = 0 or +2.4V
VIN = 0 or +2.4V
Switch Turn-On Time
Switch Turn-Off Time
OFF Isolation Rejection Ratio
Cross-Coupling Rejection Ratio
Drain-Node Capacitance
Source-Node Capacitance
See Switching Times Test Circuit
See Switching Times Test Circuit
f = 10 MHz, RL = 50n
f=10MHz, RL=50n
Vo= Vs= 0, f= 1 MHz, VIN= +2.4V
Vo= Vs= 0, f = 1 MHz, VIN= +2.4V
Dynamic
tON
tOFF
OIRR
CCRR
Co
Cs
Min
Typ
Max
Unit
-10
-
+10
80
80
160
V
n
n
n
V
V
---
2.4
-
=
12-8
--
60
-
40
45
100
-
0.01
0.02
0.2
0.4
-{l.3
0.6
400
70
66
80
0.3
3
0.8
0.1
0.1
5
5
-1
2
600
300
-
-
f.IA
j.LA
nA
nA
rnA
mA
ns
ns
dB
dB
pF
pF
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCH
CDG211
v- =-15V, V+ =+15V per channel, unless otherwise noted.
ELECTRICAL CHARACTERISTICS:
Limits at Temperature Extremes
Symbol
Parameter
Maximum
-40°C O°C
Test Conditions
TA =
+70°C
@
+85°C Unit
Static
VANALOG
Analog Signal Range
rOS(ON)
Switch ON Resistance
±10
±10
±10
±10
V
80
80
120
120
n
liN
Logic Input Leakage Current
160
160
0.1
240
1
240
1
n
0.1
IO(OFF)
Switch OFF Leakage Current
Vo= +10V, Vs = -10V,
VIN= +2.4V
5
5
100
100
nA
IS/OFF)
Switch OFF Leakage Current
Vs = +10V, Vo = -10V,
VIN=+2.4V
5
5
100
100
nA
1-
Negative Supply Quiescent Current
VIN = 0 or +2.4V
-1
-1
-1
-1
rnA
1+
Positive Supply Quiescent Current
VIN = 0 or +2.4V
2
2
2
2
rnA
Vs = -10V, VIN = 0,
Vs= +2V
Vs = +10V, VIN = 0
VIN=+2.4V,
VIN= +15V
SWITCHING TIMES TEST CIRCUIT
!LA
TEST WAVEFORMS
3V
+15V
(VS)
SWITCH o--t---{T
INPUT
+3V
LOGIC INPUT:
!R<6ns
IF< 4 ns
SWITCH
OUTPUT
r
~+-o-~--,--oVO
SWITCH INPUT
(VS)
CL =12 PF
LOGIC
INPUT
--t---------t--
Vo -SWITCH OUTPUT
OV
-15V
NOTE: Switch shown in logic "1" (OFF) position.
12-9
0.9%
0.9%
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCH
CDG211
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Time vs
Supply Voltage
Switching Time vs
Ambient Temperature
800
800
VS=3VI
700 I-RL = 50n
CL = 12 pF
., GOO t- TA = +25°C
.,600
.5-
.5~ 500
i=
CI 400
,
Z
:i:
1=
300
~
200
~ 500
i=
CI 400
'oN
Z
:i:
--
100
1=
300
~
200
7.5
10.0
12.5
SUPPLY VOLTAGE (V)
5.0
:I:
15.0
o
ili
w
II:
iE
1.8
o
~
1.7
1.9
0.7
./
/'
'oFF
Supply Current vs
Ambient Temperature
TA= +25°C
V
r-
-50 -25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (DC)
2.2
>9" 2.0
--
-- ---
o
Logic Threshold vs
Supply Voltage
2.1
I-
~I -
100
'oFF
o
V-, v+=:l:15V
700 I-RL = 50n
CL = 12pF
t- Vs = 3V
0.6
/"
r---.. ....
<-.§. 0.5
~ r-.......
!i:
~ 0.4
II:
:::l
00.3
r--.... ............
~
~ 0.2
1+
.... ~
............
r--... :--I--..
1-
:::l
I/)
0.1 I-V-, V += :1:15.
VIN=+2.4V
1.6
o
1.5
8
9
:I:
10
11
12
13
14
SUPPLY VOLTAGE (V)
15
-50 -25 0
25 50
75 +100 125
AMBIENT TEMPERATURE (OC)
12·10
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCH
CDG211
TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)
Off Isolation vs Frequency
. ....
90
Z
2
so
tiw
RL=1 kO
.
U3iil 70
a:"
z-
r"....
02 60
j:;!ci
::la: 50
0
ra
Insertion Loss vs Frequency
o
100
'r--
RL=500
40
u.
u.
TA =+25'C
30 -V-,V+=:t15V
RL=500
20
1
2
5
10 20
FREQUENCY (MHz)
0
S
100
50
1
Switch ON Resistance vs Analog Voltage
§:
w
~ 120
Z
0
ra
50
!Il
40
Ul
80
o
60
~
40
g
20
~
a:
/
30
::t
RL=500
20 -VS=0.1 VRMS
f=1kHz
10
0
r-
100
IfI
80
V-, V+=:tSV
w 60
0
i--
V-, v+= :t15V
iii 40
w
...... ~
~
i-"'
0.4
§l
0.3
5
10 20
FREQUENCY (MHz)
I
VS=0.3VRMS
1.ll.jlll.
...J
0 0.1
~
50
RL = 1 kO, Vs = 1 VRMS
12·11
~
i\
o
1
100
*
_RIL=~oU,11 ~
;!
·1 1 ITil
2
~
1
!i::t 0.2
RL=500
10 -V S =0.1 VRMS
1
0.5
z
~ 20 -TA =+25'C
o
~
is
I
::t
I Lli
J II
RL = 50 k!l, Vs= 1 VRM
ii! 0.6
I
a:
z 30
0
V-, v+= :t15V
TA = +25'C
lO.7
I I
50
Ul
15
Total Harmonic Distortion vs Frequency
o.s
I I
70
7.5
10
12.5
:t SUPPLY VOLTAGE (V)
5
Switch ON Resistance vs Frequency
~
50
o
10
-5
0
5
SOURCE VOLTAGE (V)
-10
;!
:---
z
o
z
r--....
w
./
g
60
z
f3a:
~
5
10 20
FREQUENCY (MHz)
;!
;!100
~
,
70
V-, v+= :t15V
140 RL=500
z
2
Switch ON Resistance vs Supply Voltage
160
§:
TA=+25'C
v-, v+= :t15V
VS =0.1 VRMS
7
4
10
40
FREQUENCY (MHz)
100
NOTES
12-12
..,"'TELEDYNE
COMPONENTS
CDG2214,
HIGH-SPEED ANALOG SWITCH
FEATURES
GENERAL DESCRIPTION
•
Teledyne Components' CMOSIDMOS analog switches
feature high-speed, low-power CMOS input logic and level
translation circuitry, and high-speed, low-capacitance, lateral DMOS switches. CMOS and lateral DMOS circuitry are
fabricated together on a single silicon chip.
•
•
•
•
Ultra-High OFF Isolation ........... >40 dB @ 100 MHz
>25 dB @ 200 MHz
High-Speed Switching
-tON ................................................................. 40ns
-tOFF ............................................................. 20 ns
CMOS-Compatible Inputs
Low ON Resistance .......................................... <500
Wide Bandwidth .......................... -3 dB @ 250 MHz
APPLICATIONS
•
•
•
RF and Video Switches
High-Frequency Data Acquisition
High-Frequency Multiplexers
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP
.,~
LOGIC IN
GND
CDG2214
IN-S
GND
LOGIC IN
(TOPYIEW)
NC
IN-S
3
o--t---'"
=NO INTERNAL CONNECTION
D-OUT
SO
NOTES:
1. One SPST swilch per package.
2. Switch shown in logic 'I' position.
3. Logic '0' ..;1V; Logic 'I' "'4.SV
4. Logic '0' =ON; Logic 'I' =OFF
LOGIC IN
y+
GND
Y-
IN-S
D-OUT
GND
Y(TOPYIEW)
,004-'
12·13
HIGH-SPEED ANALOG SWITCH
CDG2214
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Negative Supply VoHage ........................................... -20V
Positive Supply Voltage ............................................ +20V
Control Input VoHage Range .............. V+ +0.3V, V- -{).3V
Continuous Current, Any Pin
Except S or 0 .......................................................... 20 rnA
Continuous Current, S or 0 .................................... .40 rnA
Peak Pulsed Current, S or 0,
80 ~s, 1%, Duty Cycle ........................................... 100 rnA
Junction Temperature Range ................. -55°C to +125°C
Storage Temperature Range .................. -65°C to + 125°C
Power Dissipation ................................................ 500 mW
(Derate at 12 mW/oC, Above +85°C)
.
Negative Supply VoHage ............................... -5V to -15V
Positive Supply Voltage ................................. +5V to + 15V
Control Input Voltage Range ............................. 0V to +5V
Operating Temperature Range
C Suffix ................................................... O°c to +70°C
E Suffix ............................................... -40°C to +85°C
M Suffix ............................................ -55°C to +125°C
ORDERING INFORMATION
Part No.
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
Symbol
CDG2214CPA
CDG2214EPA
CDG2214MJA
CDG2214COA
CDG2214EOA
Operating
Temperature Range
Package
O°C to +70°C
-40°C to +85°C
-55°C to +125°C
O°cto +70°C
-40°C to +85°C
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin CerDIP
8-Pin Plastic SO
8-Pin Plastic SO
T A = +25°C, V- = -15V, V+ = + 15V per channel, unless otherwise noted.
Parameter
Test Conditions
I Min I Typ I Max I Unit
Static
VANALOG
rDS(ON)
Analog Signal Range
Switch ON Resistance
VIH
VIL
liN
High Level Input Voltage
Low Level Input Vo~age
Logic Input Leakage Current
ID(OFF)
IS(OFF)
I
1+
Sw~ch OFF Leakage Currant
Switch OFF Leakage Current
Negative Supply Quiescent Current
Positive Supply Quiescent Current
Vs=-10V
Vs= +2V
Vs=+10V
-10
-
-
45
50
130
3.4
--
4.5
VIN=+5V
VIN = +15V
VD=+10V, Vs=-10V, VIN=+5V
Vs = +10V, VD = -10V, VIN = +5V
VIN= OorV+
VIN= OorV+
-
-
-
-
+10
80
80
160
-
V
n
n
n
V
V
1
0.1
0.1
5
5
!LA
!LA
nA
nA
-
-8
rnA
8
mA
40
20
40
25
7.8
0.3
3
60
40
ns
ns
dB
dB
dB
pF
pF
0.01
0.02
0.2
0.2
Dynamic
tON
tOFF
OIRR
Switch Turn-On Time
Switch Turn-Off Time
Off Isolation Rejection Ratio
IL
CD
Insertion Loss
Drain-Node Capacitance
Source-Node Capacitance
Cs
VIN = 5V, RL = 50n, CL = 12 pF
VIN = 5V, RL = 50n, CL = 12 pF
f = 100 MHz, RL = 50n
f = 200 MHz, RL = 50n
f = 200 MHz, RL = 50n
VD = 0, f = 1 MHz, VIN = OV
Vs = 0, f = 1 MHz, VIN = OV
12-14
37
22
-
-
-
13
-
HIGH-SPEED ANALOG SWITCH
CDG2214
ELECTRICAL CHARACTERISTICS:
V-
=-15V, V+ =+15V per channel, unless otherwise noted.
Limits at Temperature Extremes
Symbol
Parameter
Test Conditions
Unit
Static
VANALOG
Analog Signal Range
±10
±10
±10
±10
V
rDS(ON)
Switch ON Resistance
Vs= +2V
Vs -10V
Vs = +10V
80
80
160
80
80
160
120
120
240
150
150
300
Q
Q
Q
liN
Logic Input Leakage Current
VIN= +5V
VIN = +15V
0.1
0.1
0.1
0.1
1
2
10
20
j.lA
j.lA
ID(OFF)
Switch OFF Leakage Current
5
5
200
1000
nA
IS(OFF)
Switch OFF Leakage Current
5
5
200
1000
nA
I
1+
Negative Supply Quiescent Current
VD=+10V, Vs=-10V,
VIN= +5V
Vs = +10V, VD = -10V,
VIN=+5V
VIN= 0 orV+
-8
-8
-10
-10
mA
Positive Supply Quiescent Current
VIN= 0 orV+
8
8
10
10
mA
=
SWITCHING TIMES TEST CIRCUIT
TEST WAVEFORMS
5V
+15V
SWITCH
INPUT
+3V
LOGIC INPUT:
tR <6 ns
tF<4 ns
SWITCH
OUTPUT
o--t---cr
A-~~~~---,--OVo
SWITCH INPUT
LOGIC
INPUT
50"/0
--+---------+-0.90/0
0.9%
SWITCH OUTPUT
-15V
o
NOTE: Switch shown in logic "I" (OFF) position.
TEST RESULTS
5V
LOGIC
INPUT
o
,
~1
II
\
--
1\
-
1\
r- t= 50 nslDlV- I--
1.-.-
SWITCH Vo
OUTPUT
0
12-15
1
I
~
,......
IfI
HIGH-SPEED ANALOG SWITCH
CDG2214
TYPICAL PERFORMANCE CHARACTERISTICS
Switch ON Resistance
vs Supply Voltage
Switch ON Resistance
vs Source Voltage
140
140
g
w
!i
YANALOG = +0.3Y
RL=5OQ
120
100
-
j!
re
!l3
a:
z
60
g
40
~
20
o
":--.... ......... r-....
80
~100
. r-f--.
m 80
--
o
7.5
10.0
12.5
SUPPLY VOLTAGE (V)
a:
~ 60 f-TA = +85·C
~
~
40
'/
Tt=+i5•C
o
15.0
-10
-5
0
+5
SOURCE YOLTAGE (V)
+10
Off Isolation vs Frequency
Insertion Loss vs Frequency
,,
80
y+, V""=:t15V
RL=5OO
""
/'
:::::::V
20
:I:
o
~
711
~
~A=+85·C
TA=+2S:C
5.0
V+,1.- =115Y
RL=5OQ
g 120
70
y+, V""=:t15Y
RL =500
,
~
1,\
\
\
\
\
10
o
10
20
o
10
50 100 200
500 1000
FREQUENCY (MHz)
12·16
20
50 100 200
500 1000
FREQUENCY (MHz)
~~TELEDYNE
COMPONENTS
CDG2269
DUAL SPOT CMOS/DMOS ANALOG SWITCH WITH DATA LATCH
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
Teledyne Components' CMOSIDMOS analog switches
feature high,speed, low-power CMOS input logic and level
translation circuitry, and high-speed, low-capacitance, lateral DMOS switches. CMOS and lateral DMOS circuitry are
fabricated together on a single silicon chip. This device is
designed for applications where high OFF isolation at high
frequencies is needed.
High OFF Isolation
Low Channel-to-Channel Cross Talk
Wide Bandwidth
Analog Signal Range .......................... +1 OV to -10V
Low ON Resistance .................................... 20W Typ
APPLICATIONS
•
•
•
RF and Video Switches
High-Speed Precision Data Acquisition
L-PAD Digital-Controlled Attenuators
LOGIC DIAGRAM
2
SW 110 IN
SW2IOIN
6
5
OUTSW1/0
OUT SW 210
SW2I1
Q
Ao
C
3
~'"
CDG2269
11
SW2I1 IN
SW 1/1 IN
Q
15
Q
A1
LE
7
LT
0
Q
13
14
9
10
NOTE: Switches shown in logic '0' position.
1065·1
IfI
LT
0
12·17
OUTSW2IO
SW2I1
OUTSW 1/1
DUAL SPDT CMOSIDMOS ANALOG
SWITCH WITH DATA LATCH
CDG2269
PIN CONFIGURATIONS
v+
SW1/0lN
SW1/00UT
CLEARIRESET
SW1/00UT
Ao
ANALOGGND
Ao
SW2Il
GND
SW 2f{)
v+
SW 1/0 IN 1
CLEAR/RESET
ANALOGGND
SW2Il
GND
GND
ANALOGGND 6
GND
ANALOGGND 6
Al
A,
OUTSW 1/1
LATCH ENABLE 7
LATCH ENABLE
V(TOP VIEW)
(TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
FUNCTION TABLE
Input
Switch
A
LE
C
SW,
SW2
L
OFF
OFF
ON
X
X
L
L
L
L
H
L
ON
H
H
H
NOTES:
OFF
ON
Note 1
Nola 2
1. Hold input state one setup before LE high-to-Iow
transition. If input state is low, then switch ON. If input
state is high, then switch OFF.
2. SWl SW2'
=
ORDERING INFORMATION
Part No.
Package
CDG2269CPE
CDG2269COE
16-Pin Plastic DIP
16-Pin SO
IN SW 1/1
Operating
Temperature Range
O°C to + 70°C
O°C to + 70·C
Negative Supply Voltage ........................................... -20V
Positive Supply Voltage ............................................ +20V
Control Input Voltage
Range ................................................. V+ +O.3V, V- -O.3V
Continuous Current, Any Pin Except S or D ........... 20 mA
Continuous Current, S or D ..................................... 30 mA
Peak Pulsed Current, S or D,
80l1s, 1%, Duty Cycle ........................................... 100 rnA
Junction Temperature Range ................. -55°C to +125°C
Storage Temperature Range .................. -65°C to +150°C
Power Dissipation ................................................ 500 mW
NOTE: All devices conlain diodes to protect inputs against damage due to
high-static voltages or electric fields. However, it is advised precautions be
taken not to exceed the maximum recommended input voltages. All unused
inputsmuslbeconnectedto an appropriate logic voltage level (Voo orGND).
Stresses above those listed under Absolute Maximum Ratings may cause
pennanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not
implied. Exposure to Absolute Maximum Rating Conditions for extended
periods may affect device reliability.
12-18
DUAL SPOT CMOSIDMOS ANALOG
SWITCH WITH DATA LATCH
CDG2269
RECOMMENDED OPERATING CONDITIONS
Negative Supply Voltage ............................... -BV to -15V
Positive Supply Voltage ................................. +BV to +15V
Control Input Voltage Range ............................. OV to +5V
Operating Temperature Range .................... O°C to +70°C
ELECTRICAL CHARACTERISTICS: TA = +25°C. V- = -15V. V+ = + 15V per channel. unless otherwise noted.
Symbol
Parameter
Test Conditions
I Min I Typ I Max I Unit
Static
VANALOG
Analog Signal Range
rOS(ON)
Sw~ch
rDS(ON)
Switch ON Resistance
(Switches 1/0 and 1/1)
V,H
-10
-
V
-
29
40
100
13
20
50
+10
80
80
160
40
40
80
Logic "1" High Input Voltage
4.5
3.4
-
V,L
Logic '0" Low Input Voltage
-
liN
Logic Input Leakage Current
Sw~ch OFF Leakage Current
(Switches 210 and 211)
0.01
0.02
0.4
0.1
0.1
IO(OFF)
V'N=+5V
V'N=+15V
Vo=+10V. Vs=-10V
-
5
l1 A
l1 A
nA
IS(OFF)
Switch OFF Leakage Current
(Switches 210 and 211)
Switch OFF Leakage Current
(Switches 1/0 and 1/1)
Sw~ch OFF Leakage Current
(Sw~ches 1/0 and 1/1)
Vs=+10V. Vo=-10V
-
4
20
nA
Vo=+10V. Vs=-10V
-
0.4
5
nA
Vs = +10V. Vo = -10V
-
4
20
nA
Negative Supply Quiescent Current
V,N = OVorV+
V'N= OVorV+
-
-0.05
Pos~ive
-D.5
0.5
l1A
l1 A
-
250
200
250
200
250
150
150
180
100
180
140
180
90
120
ns
ns
ns
ns
ns
ns
ns
150
50
90
40
IO(OFF)
IS(OFF)
I
1+
ON Resistance
(Sw~ches 210 and 211 )
Supply Quiescent Current
Vs=-10V.ls=-1 rnA
Vs=+2V,ls= 1 rnA
Vs = +10V,ls = -1 rnA
Vs = -10V. Is = -1 rnA
Vs = +2V, Is = 1 rnA
Vs = +10V. Is = -1 rnA
-
0.03
1
n
n
n
n
n
n
V
V
Dynamic
to
Is
tH
tw
OIRR
Propagation Delay
Data to Switch ON
Data to Switch OFF
Latch Enable to Sw~ch ON
Latch Enable to Switch OFF
Clear to Sw~ch ON
Clear to Sw~ch OFF
Setup Tirne
Hold Tirne
Pulse Width
-
ns
ns
Off Isolation Rejection Ratio
(Switches 1/0 and 1/1)
Frequency Roll-Off (Bandwidth)
f= 10 MHz. RL= 50n
f = 200 MHz. RL = 50n
42
12
45
15
Vo
0.6
-
pF
Cs
Source-Node Capac~ance
-
dB
Drain-Node Capacitance
=200 MHz, RL = 50n
=OV. f = 1 MHz, V,N = OV
Vs =OV, f =1 MHz. V,N =OV
3
Co
6
-
pF
f
12-19
1
-
dB
dB
lEI
DUAL SPOT CMOSIDMOS ANALOG
SWITCH WITH DATA LATCH
CDG2269
TYPICAL PERFORMANCE CHARACTERISTICS CURVES
Switch ON Resistance vs
Analog Input Voltage
70
v~
w
~
!!l
f3a:
z
o
70
= ~10V
I
so
20
III
10
~~
o
-10 -8
-
f3
~
o
~~~
==
-2
0
+2
+4
so
~
40
TA=+SS;s... ~
r--
o
-4
-3
-2
-1
ANALOG INPUT VOLTAGE (V)
-5
+6
Switch ON Resistance vs
Analog Input Voltage
aw
U
~
!!l
f3
70
SW 110 AND SW 1/1
40
~
o
30
~
20
III
10
TA= +8SoC
o
-lS
~
~
~
i
IJ
Z
o
......
~
~ 30
It
o
~
o
+10
12·20
IN~JR~I~~I
LOSS
....
\
20
10
I
-10
-5
0
+S
ANALOG INPUT VOLTAGE (V)
50
40
= :t15V
jrl7fn
"i"
S
TA = +2SoC
'j
V~
"
60
I
so
0
Off Isolation and Insertion Loss
vs Frequency
V~= ~15V
60
~
A = +2SoC
10
ANALOGINPUTVOLTAGE(~
70
C:: ::::.- "'T'
30
~
t::
III
-4
SW 110 AND SW 1/1
U 20
TA=+2SoC- r---
,.... -
-8
~
!!l
l/~
TA=+IISoC
30
~
w
U
)'1
40
v~=~sv
a6(l
SW 110 AND SW 1/1
aGO
U
Switch ON Resistance vs
Analog Input Voltage
1
2
mllnrrliil
10 20
100 200
FREQUENCY (MHz)
o
DUAL SPOT CMOSIDMOS ANALOG
SWITCH WITH DATA LATCH
CDG2269
TYPICAL PERFORMANCE CHARACTERISTICS CURVES (Cont.)
Supply Current vs
Ambient Temperature
Logic Threshold vs
Ambient Temperature
3.5
350
3.0
300
:;-
C
C(
2.5
v~
....J
o
ili
w
a:
= ~15V
Z
a:
(.) 150
~
~ 100
/
Ul
0.5
50
o
o
-55 -35 -15
+5
+25
+45 +65 +85
I'
V
/" ./'
Q.
v~= ~5V '------
....J
V
15
25
./
35
./
1'1+
V"
45
55
65
75
AMBIENT TEMPERATURE (OC)
AMBIENT TEMPERATURE (OC)
Logic Input Leakage Current
vs Ambient Temperature
Switch OFF Leakage vs
Ambient Temperature
85
100~~~
35
C( 30
1
VIN=+15y
I
oS
w 25
20
~ 15
Q.
i!l:
,/'
l/
(.) 10
c;
o
...J
/
:::l
V
/
/
~ 200
(.)
~
I-
I-
2.0
g 1.0
~
I
oS 250
~ 1.5
c(
v~ l ~15J
v IN = OV OR 15V
5
o
15
"
25
V
35
",
. . .V
45
'"
oS 20
gllJ ~~~~ ~
-c;,~~~
10
. . . V~
'
...... . /
~
tt
o
J:
I
65
2.0
g 1.0~~~a§~~
==
V~ = ~15V
VN=+5V
55
~
C(
Ul
75
0.2
IS(OFF) @ Vs = 10V, 'Vo = :"10V
ID(OFF) @ Vo = 10V, Vs = -10V
0.1 '----'-_...l...----"_--'-_"'---'--.-I
15 25 35 45 55
65 75 85
85
AMBIENT TEMPERATURE (OC)
AMBIENT TEMPERATURE (OC)
12-21
IfI
NOTES
12-22
""'TELEDYNE
COMPONENTS
CDG308
CDG309
CDG4308
CDG4309
QUAD MONOLITHIC, SPST CMOS/DMOS ANALOG SWITCHES
FEATURES
•
•
•
•
•
•
GENERAL DESCRIPTION
High OFF Isolation ........................ 68 dB @ 10 MHz
Low Insertion Loss ••••••.••••••••••••••• -1 dB @ 100 MHz
Low Channel-to-Channel
Cross Talk •.••••••.••.••••••..••.••••••.•••.•• -80 dB @ 10 MHz
CMOS-Compatible Inputs
Low OFF Leakage
Industry Standard Pinout (CDG3081CDG309)
Teledyne Components' CMOS/DMOS analog switches
feature high-speed, low-power CMOS input logic and level
translation circuitry, and high-speed, low-capacitance, lateral DMOS switches. CMOS and lateral DMOS circuitry are
fabricated together on a single silicon chip. The CDG4308
and CDG4309 use the same die as CDG308 and CDG309;
the extra isolating pin between switch input and output
increases isolation by 6 dB.
APPLICATIONS
•
•
•
•
Glitch-Free Analog Switching
RF and Video
Track-and-Hold
Sample-and-Hold
FUNCTIONAL BLOCK DIAGRAMS
~'"
~'"
CDG309
CDG4309
COG308
COG4308
SI
SI
INI
INI
°1
°1
~
S2
IN2
IN2
°2
°2
S3
S3
IN3
IN3
°3
°3
S4
S4
IN4
IN4
°4
°4
NOTES: 1. Four SPST switches per package.
2. Switches shown in logic "I" position.
3. COG308/CDG4308: Logic "0" = OFF; Logic "I" = ON
CDG309/CDG4309: LoQic ''0" = ON; LOQic "I" = OFF
1066-1
12-23
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCHES
CDG308
CDG309
CDG4308
CDG4309
PIN CONFIGURATIONS
°2
NC
IN1
IN2
IN2
°1
°2
82
°2
82
82
Y+
y+
NC
NC
NC
83
83
83
NC
81
Y+
03
°3
IN4
IN3
(TOP VIEW)
(TOPYIEW)
(TOPYIEW)
NC = NO INTERNAL CONNECTION
ORDERING INFORMATION
Part No.
CDG30SCOE
CDG30SCPE
CDG30SEJE
CDG308EOE
CDG308EPE
CDG30SMJE
CDG309COE
CDG309CPE
CDG309EJE
CDG309EOE
CDG309EPE
CDG309MJe
CDG430SCPP
CDG430SEPP
CDG4309CPP
CDG4309EPP
Package
16-Pin SO
16-Pin Plastic DIP
16-Pin CerDIP
16-Pin 50
16-Pin Plastic DIP
16-Pin CerDIP
16-Pin 50
16-Pin Plastic DIP
16-Pin CerDIP
16-Pin SO
16-Pin Plastic DIP
16-Pin CerDIP
20-Pin Plastic DIP
20-Pin Plastic DIP
20-Pin Plastic DIP
20-Pin Plastic DIP
ABSOLUTE MAXIMUM RATINGS
Operating
Temperature Range
O°Cto +70°C
O°Cto +70°C
-40°C to +S5°C
-40°C to +S5°C
-40°C to +85°C
-55°C to +125°C
O°C to +70°C
O°C to +70°C
-40°C to +S5°C
-40°C to +S5°C
-40°C to +S5°C
-55°C to +125°C
O°C to +70°C
-40oGto +S5°C
O°C to +70°C
-40°C to +S5°C
Negative Supply Voltage ........................................... -20V
Positive Supply Voltage ............................................ +20V
Control Input Voltage Range .............. V+ +0.3V, V- -o.3V
Continuous Current, Any Pin Except 5 or D ........... 20 rnA
Continuous Current, S or D ..................................... 30 rnA
Peak Pulsed Current, S or D,
SO j.ls, 1%, Duty Cycle .................................... 1S0 rnA
Junction Temperature Range ................. -55°C to +125°C
Storage Temperature Range .................. -65°C to +150°C
Power Dissipation ................................................ 500 mW
NOTE: All devices contain diodes to protect inputs against damage due to
high·static voltages orelectric fields. However, it is advised precautions be
taken notto exceed the maximum recommended input voltages. All unused
inputs must be connected to an appropriate Jogicvoltagelevel (YooorGND).
Statio-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
12-24
QUAD MONOLITHIC, SPST
CMOSIDMOS ANALOG SWITCHES
CDG308
CDG309
CDG4308
CDG4309
RECOMMENDED OPERATING CONDITIONS
Negative Supply Voltage ............................... -8V to -15V
Positive Supply Voltage ................................. +8V to + 15V
Control Input Voltage Range ............................. OV to +5V
Analog Switch Voltage Range ................................... ±10V
Operating Temperature Range
C Suffix .................................................. O°C to +70°C
E Suffix ............................................... -40°C to +85°C
M Suffix ............................................ -55°C to +125°C
ELECTRICAL CHARACTERISTICS:
TA = +25°C, V- = -15V, V+ = + 15V per channel, unless otherwise noted.
Symbol
Test Conditions
Parameter
I Min I Typ I Max I
Static
VANALOG
rOS(ON)
Analog Signal Range
Switch ON Resistance
VIH
VIL
liN
IO(OFF)
Switch OFF Leakage Current
IS(OFF)
Switch OFF Leakage Current
I
1+
-10
-
+10
80
80
160
Unit
V
n
n
n
V
--
40
45
100
High Level Input Voltage
4.5
3.4
--
-
Low Level Input Voltage
0.01
0.02
1
0.1
0.1
0.2
5
I1A
I1A
nA
Vs=+10V, Vo=-10V
VIN = +5V (CDG309/CDG4309)
VIN = +1 V (CDG308/CDG4308)
-
0.4
5
nA
Negative Supply Quiescent
Current
VIN = +5V (CDG309/CDG4309)
VIN = +lV (CDG308/CDG4308)
-
-0.1
-0.5
I1A
Positive Supply Quiescent
Current
VIN = +5V (CDG309/CDG4309)
VIN = + 1V (CDG308/CDG4308)
-
0.1
0.5
I1A
tON
Switch Turn-On Time
-
140
250
ns
tOFF
Switch Turn-Dff Time
VIN = + 1V (CDG308lCDG4308)
VIN = +5V (CDG309/CDG4309)
VIN = +lV (CDG308/CDG4308)
VIN = +5V (CDG309/CDG4309)
-
80
220
ns
OIRR
Ofl Isolation Rejection Ratio
60
66
CCRR
Cross-Coupling Rejection Ratio
62
68
80
dB
dB
dB
Co
Drain-Node Capacitance
pF
pF
Logic Input Leakage Current
Vs=-10V
Vs= +2V
Vs = +10V
VIN= +5V
VIN=+15V
Vo=+10V, Vs=-10V
VIN = +5V (CDG309/CDG4309)
VIN = + 1V (CDG308/CDG4308)
Dynamic
I = 10 MHz, RL = 50n (CDG308lCDG309)
I = 10 MHz, RL = 50n (CDG4308lCDG4309)
I = 10 MHz, RL = 50n
Vo = Vs = 0, I = 1 MHz
-
-
0.3
-
-
3
-
V
VIN = +1V (CDG308lCDG4308)
VIN = +5V (CDG309/CDG4309)
Cs
Source-Node Capacitance
Vo = Vs = 0, I = 1 MHz
Vs = 0, I = 1 MHz, VIN = OV
VIN = +5V (CDG309/CDG4309)
12-25
IfI
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCHES
CDG308
CDG309
CDG4308
CDG4309
ELECTRICAL CHARACTERISTICS:
v- = -15V, V+ = +15V per channel, unless otherwise noted.
Limits at Temperature Extremes
Symbol
Test Conditions
Parameter
Static
VANALOG
Analog Signal Range
±10
±10
±10
±10
±10
V
rOS(ON)
Switch ON Resistance
Vs = +2V, Vs = -10V
Vs = +10V
80
160
80
160
120
240
120
240
150
300
Q
Q
liN
Logic Input Leakage Current
0.1
0.1
0.1
0.1
1
2
1
2
10
20
5
5
100
100
1000
5
5
100
100
1000
nA
IO(OFF)
Switch OFF Leakage Current
VIN= +5V
VIN = +15V
Vo=+10V, Vs=-10V
I(OFF)
I
Switch OFF Leakage Current
Vs=+10V, Vo=-10V
Negative Supply Quiescent Current
-0.5
-0.5
-20
-20
-100
J.1A
1+
Positive Supply Quiescent Current
0.5
0.5
20
20
100
J.1A
SWITCH CONTACTS
APPLICATIONS
Switches are bidirectional (analog input can be to source
or drain). However, for optimum performance in video applications, connect input to source and output to drain. (See
Figure 1.)
Very Low Distortion Circuit for Low
Frequency/Large Signal Applications
POWER SUPPLY DECOUPLING CIRCUIT
By inserting 1 kf.l resistors in series with V+ and Vpower supply lines, and decoupling both pins at the device
socket, it is possible to improve video switch power supply
rejection ratios by 50 dB at frequencies of 20 MHz and
higher. (See Figure 2.)
y+
The circuit shown in Figure 3 provides very low distortion «O.l%) and high off isolation (>90 dB) at signal levels
equal to the supply voltage. The signal passes through a "T"
switch configuration and at the same time modulates the
power supply. This modulation maintains a constant ON
resistance, rOS(ON), which in turn reduces distortion. R5 is for
bypassing the power supply and has a typical yalue of 1 kQ;
R4 should be a value that can be accommodated by the
signal source as load; R3 is only necessary at loads lower
..,'"
CDG3081CDG309
CDG43081CDG4309
CDG3081CDG309
CDG43081CDG4309
ri
0.22 \IF
1 kQ
t - - - . - - - - ' \ I V \ r - - - o y+
IN
IN
y-
GND
'--_ _ _ _ _ _ _ _ _-'1 LI_ _--'
CMOS
CIRCUITRY
Figure 1
J.1A
J.1A
nA
DMOS
SWITCH
1 kQ
Figure 2
Functional Diagram (1 of 4 Channels)
12·26
Power Supply Decoupling Circuit
QUAD MONOLITHIC, SPST
CMOSIDMOS ANALOG SWITCHES
CDG308
CDG309
than 100n and should be selected during initial circuit
design; C1 has to be large enough for the lowest signal to
pass and C2 will have to bypass all signals. R1 and R2 set
up the logic "1" level for the control input and should be set
t05V.
CDG4308
CDG4309
Logic Inverter
The circuit shown in Figure 4 provides logic inversion
with two resistors and one switch. It does not require additionallogic parts. The resistors divide the supply voltage to a
5V level when high, and are switched to a low level via the
switch. This configuration allows a single-pole, single-throw
switch to be changed into a single-pole, double-throw switch.
ANAL~~ o-HHI-O..--O'I
V+
"""
CDG308lCDG309
CDG4308lCDG4309
R1
ANALOG IN
ANALOG OUT
,,~
5V
CDG308
CDG309
CDG4308
CDG4309
.n..
rL
R2
L..---+------oV-
-=
Figure 3
Figure 4
Low Distortion, Rail-to-Rail Analog Swiblh
TEST CIRCUITS
Switching Times
+15V
"""
CDG3081CDG309
CDG43081CDG4309
SWITCH
INPUTo-+-----'
""---0 V-
=0.22 jJF 1110 jJF
ON RESISTANCE
20 MHz TO 100 MHz
'NOTE: C
=0.22 jJF 1110 jJF
Distortion vs Frequency
~'""
r--......--oV+
CDG308lCDG309
CDG4308lCDG4309
HP
GENERATOR
(OREQUIV)
I
C'
H:r-...........;D::o-.,
son
HP
SPECTRUM
ANALYZER
(OR EQUIV)
S
I-f-+-_--"<>--'
&.-_-<>-_.....1
500
'NOTE: C
=0.22 jJF 1110 IIF
t----ovHARMONIC OISTORTION
10 MHz TO 40 MHz
12·28
QUAD MONOLITHIC, SPST
CMOSIDMOS ANALOG SWITCHES
CDG308
CDG309
CDG4308
CDG4309
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Time
vs Supply Voltage
Off Isolation Rejection Ratio
vs Frequency
300 . - - - - - - . - - - . . . . , . . . . . . - - - - ,
I
~
!Ii!
95
I
90 f-- TA = +25"C
85 I-RL =500
80 f-- V-, v+ = ",15V
200
iii'
:E.. 75
I---~.._-----'..__-I------l
oZ
i=
70
CI
i= 65
~
u::
~60 r-.
z
!:: 100
o
I----+---+----=.....;::t
...
55
~ 50
fE
45
40
35
o
15
5
10
'" SUPPLY VOLTAGE (V)
.
20
85
~
60
II:
Z
o
~
~
40
/
/
I-!A = +25"C
I
a RL =500 I
;;;80 I- VANALOG = 100 mVRMS
J
~
75
!:!l 70
ffl
11:65
Z
~60
...........
............. .........
(J
0
50
45
-5
0
+5
ANALOG VOLTAGE (V)
IfI
f= 1 kHz
(J
20
-10
--
30
40 50 60 708090100
FREQUENCY (MHz)
~55
o
r--
90
TA =+25"C
_RL =50!l
glOO V-, V+=",15V
iii
r-- .....
Switch ON Resistance
vs Supply Voltage
120
80
~
~rG308r~
Switch ON Resistance
vs Analog Voltage
~
-----
CDG430814309
+10
12-29
5
6
-.........
8
10
12
'" SUPPLY VOLTAGE (V)
.........;::,.
15
QUAD MONOLITHIC, SPST
CMOS/DMOS ANALOG SWITCHES
CDG4308
CDG4309
CDG308
CDG309
TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)
Switch ON Resistance
vs Frequency
0.85
S5
=
TA +25°C
RL = 500.
YANALOG = 100 mYRMS
gBO
w
(J 75
~!Il
1ft
Switch ON Resistance vs
Supply Voltage and Frequency
TA = +25°C
RL =500.
VANALOG = 100 mVRMS
0.80
~ 0.75
;;; 0.70
~ 0.65
<
70
Ii; 0.60
a:
z 65
o
V-, Y+=:tSY
~
ilia:
-----
~
z
o
0.50
:z: 0.45
~V
60 V-, Y+=:t10Y
III 55 V-, Y+=:t1 nv
V-, y+= :t15Y
50
40
60
20
FREQUENCY (MHz)
0.55 -V-, y+ = :t10Y
(.)
~ 0.40 -V-, y+ = :t12Y
III 0.35
BO
0.30
100
20
40
60
FREQUENCY (MHz)
Total Harmonic Distortion
vs Frequency
TA=+25YOC
1000
500
200
100
300
z 100
50
~ 20
a: 105
2
1
2i
0.3
0.1
0.05
0.02
1.05
0
1=
a: 0.95
e
0.S5
Z
0.80
(J
!i
0.50
...J
0.20
!i:z:
<
I-
e
/
V-, y+ = :t15Y,
YANALOG = 1 YRMS
.;::.;z...
~
~
.......
T
10
~
"""
V-, y+ = :t15Y,
0.10 YANALOG = 0.3 YRMS
0.05
l
V-, y+ = :t10Y, YANALOG = 1 YRMS
~
=!A=+25°C
rRL = 500.
rf= 10 kHz
r V-,Y+ = :t15Y
r-r-~
Power Supply Rejection Ratio
vs Frequency
iii 150
"0
0'140
~130
~12O
TA = +2SoC
YMOD = 4Y -f-p
Y-, y+ =:t15Y
~ 110
(J 100
~
90
~
so ~S!}~' .~?!}1 ~I!H ~E~1U!~r~..
It
70
~
60
50
a:
a:
~
~
40
30
0.1
~P~RR
+fSR~
0.2
=
TOTAL HARMONIC
----r-
-
COMPENSATED
.........
./
.3
1.0
3.0
5.0
ANALOG INPUT VOLTAGE (VAMS)
40
20
FREQUENCY (MHz)
100
Distortion vs
Analog Input Voltage
1.35
~
z
SO
WITHOUT
~EC?UP~NG
~
~
0.5 1.0 2
5 10.0
FREQUENCY (MHz)
12-30
20
"'~TELEDYNE
COMPONENTS
CDG4500
4-CHANNEL CMOSIDMOS HIGH-FREQUENCY MULTIPLEXER
FEATURES
GENERAL DESCRIPTION
•
•
Teledyne CMOS/DMOS Analog Multiplexers feature
high-speed, low-power 5 volt CMOS input logic and level
translation circuitry and high speed, low capacitance Lateral
DMOS switches. CMOS and Lateral DMOS circuitry are
fabricated together on a single silicon chip. This part is
designed for applications where high "off" isolation at high
frequencies is needed. The 14 pin configuration gives a
compact board layout without impacting 'off" isolation and by
use of the enable allows higher levels of multiplexing.
All devices contain diodes to protect inputs against
damage due to high static voltages or electric fields; however, it is advised that precautions betaken notto exceed the
maximum recommended input voltages. All unused inputs
must be connected to an appropriate logic level (either Vee
or GND).
•
•
•
•
•
High OFF Isolation, >62dB @ 10 MHz
Low Channel-to-Channel Crosstalk,
>8OdB @ 10 MHz
5 Volt CMOS Compatible Inputs
Low ON Resistance, 40 n typo
Wide Bandwidth, -3.OdB @ 100 MHz
Wide Analog Signal Range +10V to -10V
High Speed Logic Control
APPLICATIONS
•
•
RF & Video Switches
High Speed Precision Data Acquisition
FUNCTION DIAGRAM
PIN CONFIGURATION
•
OUT
vNlC
IN 1
IN4
IN2G----'
NlC
IN 3 0--------'
IN4G-------~
434BILl F01
FUNCTION TABLE
TOP VIEW
ENABLE
A.J
AI
CHANNEL
H
X
X
OFF
L
L
L
81
L
H
L
82
L
L
H
83
L
H
H
S4
CDG4500AK
CDG4500BK
(See Package 14)
4346 ILL F02
X= Undefined
1061-1 (4346)
CDG4500BJ
CDG4500cJ
(See Package 9)
12·31
4-CHANNEL CMOS/DMOS
HIGH-FREQUENCY MULTIPLEXER
CDG4500
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
VV+
VIN
4-Channel Multiplexer
with Enable
Commercial Temp.
Range
Industrial Temp.
Range
Military Temp.
Range
IL
Is
Is
TJ
Ts
Po
Negative Supply Voltage ................................. -20V
Positive Supply Voltage ................................... +20V
Control Input Voltage
Range ...................................... V+ +0.3V, V---O.3V
Continuous Current, any Pin except S or D ... 20mA
Continuous Current, S or D ............................ 30mA
Peak Pulsed Current, S or D, 80~sec, 1%
Duty Cycle .................................................... 1OOmA
Junction Temperature Range ....... -55°C to +125°C
Storage Temperature Range ........ -55°C to +125°C
Power Dissipation (derate at 12mW/oC,
above +85°C) .............................................. 500mW
RECOMMENDED OPERATING CONDITIONS
VV+
VIN
Top
Negative Supply Voltage ..................... -8.0 to -15V
Positive Supply Voltage ....................... +8.0 to +15V
Control Input Voltage Range ...................... 0 to +5V
Operating Temperature
(A Suffix) ........................................... -55 to + 125°C
(8 Suffix) ............................................. -40 to +85°C
(C Suffix) ................................................. 0 to +70°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause pennanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions foreXlended periods may
affect device reliability.
12-32
14-Pin
Plastic DIP
CDG4500 CPD
14-Pin
Ceramic DIP
CDG4500 EPD CDG4500 EJD
CDG4500 MJD
4-CHANNEL CMOS/DMOS
HIGH-FREQUENCY MULTIPLEXER
CDG4500
ELECTRICAL CHARACTERISTICS: 01- =-15V, v+;: +15V, per channel,
Symbol
Parameter
Test Conditions
unless otherwise noted, TA
Min
Typ
Max
-
40
45
100
+10
80
80
160
=+25°C)
Units
Static
VANALOG
Analog Signal Range
rOS(on)
Channel On Resistance
-10
VIH
Logic High Level Input Voltage
4.5
3.4
VIL
Logic Low Level Input Vonage
-
-
1.0
V
liN
Logic Input Leakage Current
VIN= +5.0V
VIN = +15V
-
0.01
0.02
0.1
0.1
J.LA.
IO(OFF)
IS(OFF)
1-
Switch OFF Leakage Current
Vo = +10V, Vs -10V
Vs = +10V, VD = -10V
5.0
5.0
nA
Negative Supply Queiescent Current
VIN = 0 or V+
-
0.2
0.4
-1.4
-4.0
mA
1+
Positive Supply Quiescent Current
VIN= 0 orV+
-
1.6
4.0
mA
-
150
250
nsec
120
220
nsec
-'
-
-
dB
Vs = -10V
Vs=+2.0V
Vs=+10V
-
--
=
-
V
0
V
Dynamic
tON
Switch Turn-On Time (All inputs)
VIN= 5.0V
tOFF
Switch Turn-OFF Time (All inputs)
CeRR
All Crosstalk
Single Channel Crosstalk
Frequency Roll-Off (BandWidth)
VIN= 5.0V
f = 10 MHz, RL = 500
f = 10 MHz, RL; 500
f = 100 MHz, RL = 500
Cd
Cs
Output Node Capacitance
Vo = 0, f = 1 MHz, VIN = 0
Input Node Capacitance
Vs
-
62
80
-
=0, f = 1 MHz, VIN = 0
ELECTRICAL CHARACTERISTICS: (V-;: -15V, V+ =+15V,
-
1.0
3.0
8.0
12.0
pF
2.5
4.0
pF
per channel, unless otherwise noted)
LIMITS AT TEMPERATURE EXTREMES
Symbol
Parameter
Test Conditions
Units
Static
±10
±10
±10
±10
±10
V
Vs = -10V,ls = -1.0 mA
Vs = +2.0V,ls; +1.0 mA
Vs; +10V,ls '" -1.0 mA
80
80
160
80
80
160
120
120
240
120
120
240
150
150
300
0
0
0
Logic Input
Leakage Currents
VIN= +5.0V
VIN; +15V
0.1
0.1
0.1
0.1
1.0
2.0
1.0
2.0
10
20
J.lA
Switch OFF
Leakage Currents
Vo +10V, Vs -10V
Vs = +10V, Vo; -10V
5.0
5.0
5.0
5.0
100
100
100
100
1000
1000
nA
VIN= OorV+
-4.0
-4.0
-4.0
-4.0
-4.0
mA
VIN= 0 orV+
4.0
4.0
4.0
4.0
4.0
mA
VANALOG
rOS(on)
Analog Signal Range
Channel On Resistance
liN
IO(OFF)
IS(OFF)
1-
Supply
1+
Quiescent Currents
=
=
12-33
IfI
NOTES
12-34
"'~TELEDYNE
COMPONENTS
CDG5341
DUAL MONOLITHIC, SPST CMOS/DMOS
"T" CONFIGURATION ANALOG SWITCH
FEATURES
GENERAL DESCRIPTION
•
•
Teledyne Components' CMOS/DMOS analog switches
feature high-speed, low-power 5V CMOS input logic and
level translation circuitry, and high-speed, low-capacitance,
lateral DMOS switches. CMOS and lateral DMOS circuitry
are fabricated together on a single silicon chip.
Ultra-High OFF Isolation •..••.•..•... >80 dB @ 10 MHz
Low Channel-to-Channel
Cross Talk .................................... -80 dB @ 10 MHz
CMOS-Compatible Inputs
Low ON Resistance ........................................ <110Q
Wide Bandwidth •.••••••••..•.•••..••.•••.•• -1 dB @ SO MHz
•
•
•
APPLICATIONS
•
•
RF and Video Switches
Data Acquisition
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
~~
COG5341
3
I
iI1>---~Q
I
I
I
I
lEI
01
r----------.---------~Q
____ J
2
COMMON 1
v+
I
I
4
GNO
5
9
S2~+_----~~:~----~~~:~~r-~Q 02
I
:
7
r----------.-------i--f!--o
---,
COMMON 2
I
I
(TOPV'I:W)
NC
NOTI:S: 1. Two SPST 'T' switches per package.
2. Switchs shown in logic '0' position.
3. Compensation networks can be connected
to COMMON 1 and COMMON 2.
4. Switches are 'BRI:AK-before-MAKE'
5. Logic '0' = OFF; Logic '1' = ON
106&-1
12-35
=NO INTERNAL CONNECTION
DUAL MONOLITHIC, SPST CMOSIDMOS
"T" CONFIGURATION ANALOG SWITCH
CDG5341
ORDERING INFORMATION
Part No.
CDG5341EPE
CDG5341CPE
CDG5341EJE
CDG5341MJE
Operating
Package
ABSOLUTE MAXIMUM RATINGS
Temperature Range
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin CerDIP
14-Pin CerDIP
-40°C to +S5°C
0°CtO+70°C
-40°C to +S5°C
-55°C to + 125°C
RECOMMENDED OPERATING CONDITIONS
Negative Supply Voltage ............................... -8V to -15V
Positive Supply Voltage ................................. +8V to + 15V
Control Input VoHage Range ............................. OV to +5V
Analog Switch Voltage Range ................................... ±10V
Operating Temperature Range
M Suffix ...................................... -55°C to +125°C
E Suffix ........................................ -40°C to +85°C
C Suffix ............................................ O°C to +70°C
ELECTRICAL CHARACTERISTICS:
Symbol
TA
Parameter
Negative Supply Voltage ........................................... -20V
Positive Supply Voltage ............................................ +20V
Control Input VoHage
Range ................................................. V+ +0.3V, V- -0.3V
Continuous Current, Any Pin Except S or D ........... 20 mA
Continuous Current, S or D ..................................... 30 mA
Peak Pulsed Current, S or D,
80 I1s, 1%, Duty Cycle ........................................... 100 mA
Junction Temperature Range ................. -55°C to +125°C
Storage Temperature Range .................. -65°C to + 150°C
Power Dissipation ................................................ 500 mW
(Derate at 12 mW/oC Above +85°C)
NOTE: All devices contain diodes to protect inputs against damage due to
high-stetic voltages or electric fields. However, it is advised precautions be
taken not to exceed the maximum recommended inputvoltagas. All unused
inputsmustbeconnectedtoan appropriate logic voltage level (VooorGND).
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is
not implied. Exposure to Absolute Maximum Rating Conditions for
extended periods may affect device reliability.
=+25°C, V- =-15V, V+ =+ 15V per channel, unless otherwise noted.
Test Conditions
I Min I Typ I Max I Unit
Static
-10
VANALOG
rOS(ON)
Analog Signal Range
Switch ON Resistance
VIH
VIL
liN
High Level Input Voltage
Low Level Input Voltage
Logic Input Leakage Current
IO(OFF)
IS(OFF)
11+
Switch OFF Leakage Current
Switch OFF Leakage Current
Negative Supply Quiescent Current
Positive Supply Quiescent Current
VIN= +5V
VIN=+15V
Vo=+10V, Vs=-10V
Vs = +10V, Vo = -10V
VIN= 0 orV+
VIN= 0 orV+
Switch Turn-On Time
Switch Turn-Off Time
Off Isolation Rejection Ratio
Cross-Coupling Rejection Ratio
Frequency Roll-Off (Bandwidth)
Drain-Node Capacitance
Source-Node Capacitance
VIN=+5V
VIN=+5V
f= 10 MHz, RL= 500
f = 10 MHz, RL = 500
f= 10 MHz, RL= 500
Vo = 0, f = 1 MHz, VIN = OV
Vs = 0, f = 1 MHz, VIN = OV
Vs=-10V, Is=-1 mA
Vs = +2V, Is = 1 rnA
Vs=+10V, Is=-1 mA
-
-
4.5
-
100
110
200
3.4
-
+10
160
160
320
-
-
0.01
0.02
0.2
0.2
-0.1
0.1
1
0.1
0.1
5
5
-0.5
0.5
-
150
SO
250
220
80
SO
-
-
-
-
1
0.3
3
-
-
V
0
0
0
V
V
IIA
IIA
nA
nA
IIA
IIA
Dynamic
tON
tOFF
OIRR
CCRR
Co
Cs
12-36
-
3
ns
ns
dB
dB
dB
pF
pF
DUAL MONOLITHIC, SPST CMOSIDMOS
"T" CONFIGURATION ANALOG SWITCH
CDG5341
ELECTRICAL CHARACTERISTICS:
v- = -15V. V+ = +15V per channel. unless otherwise noted.
Limits at Temperature Extremes
Symbol
Test Conditions
Parameter
Unit
Static
VANALOG
Analog Signal Range
±10
±10
±10
V
Switch ON Resistance
Vs=-10V.ls=-1 mA
Vs = +2V.ls = +1 mA
Vs = +10V. Is = -1 mA
±10
160
160
320
±10
rOS(ON)
160
160
320
240
240
480
240
240
480
300
300
600
Q
Q
Q
liN
Logic Input Leakage Current
VIN= +5V
VIN= +15V
0.1
0.1
0.1
0.1
1
2
1
2
10
20
~A
~A
IO(OFF)
Switch OFF Leakage Current
Vo=+10V. Vs=-10V
5
5
100
100
1000
nA
IS(OFF)
I
Switch OFF Leakage Current
5
-0.5
5
100
100
1000
nA
Negative Supply Quiescent Current
Vs=+10V.Vo=-10V
VIN= 0 orV+
-0.5
-20
-20
-100
~A
1+
Positive Supply Quiescent Current
VIN = 0 orV+
0.5
0.5
20
20
100
~A
TYPICAL PERFORMANCE CHARACTERISTICS CURVES
Switch ON Resistance vs Frequency
Off Isolation Rejection Ratio vs Frequency
95
90
iii"
~
Z
Q
~
"
135
,
~ 75
+i50b I I IIII
~ 125
85
80
TA ~
V- = :t15V
§: 130 I- V+,
VANLOG = 100 mVRMS
~
I\.
Iii
'\
120
iii
V
w
~ 115
"\
LI.
~ 70
TA= +25°C
65 -v+, v-= :t15.
RL =500
i I I II
60
1
2
5
10
20
FREQUENCY (MHz)
o
'"
50
~
110
III
105
100
100
V
1
2
Switching Time vs Supply Voltage
350
300
'iii
.s.
~
...
"
250
200
!',.''''-toN
to~ ~
CI
z
~ 150
3E
III
~
100
50 I-TA= +25°C
o
I
5
10
:t SUPPLY VOLTAGE (V)
12-37
15
5
10
20
FREQUENCY (MHz)
50
100
NOTES
12-38
.,"'TELEDYNE
COMPONENTS
TC4201
TC4202
TC4203
QUAD SINGLE-POLE CMOS ANALOG SWITCHES
FEATURES
•
•
•
•
•
•
GENERAL DESCRIPTION
Low rDS(ON) (+2S C) ................................. <17SQ Max
Analog Input Leakage Current .•..•••..•.••..•..••.••.. 1 nA
Analog Input Equal to Supply
Supply Current .............................................. 300 ~
Low-Current Logic Input
Pin Compatible With DG201 (TC4201)
0
The TC4201, TC4202 and TC4203 are quad CMOS
analog switches, specifically designed for low supply voltage applications. Special care was taken to reduce crosstalk and feedthrough, while maintaining uniform "on" resistance at supply voltages as low as ±1.5V. This also results
in extremely low charge transfer during switching, typically
5 pC, compared to 30 pC with similar devices.
Charge transfer is an extremely important consideration
in the design of sample-and-hold circuits, lOW-level analog
signal switching, and interfacing to high-input impedances,
such as those presented by analog-to-digital converters.
This switch family offers four independent single-pole,
single-throw (SPST) circuits and features single- or dualsupply operation, with analog input voltage range equal to
the supply Voltage. The CMOS design requires very low
supply current.
The TC4201 consists of four nonnally-open (Form A)
contacts.
The TC4202 consists of four·nonnally-open (Form 8)
contacts.
The TC4203 combines two Form A contacts with two
Form 8 contacts, and may be configured as two Form C
(SPDT) circuits.
PIN CONFIGURATIONS
A4
A4
A4
D4
04
04
S4
54
S4
NC
NC
NC
S3
S3
S3
03
03
03
v;
NC = NO INTERNAL CONNECTION
12-39
QUAD SINGLE-POLE
CMOS ANALOG SWITCHES
TC4201
TC4202
TC4203
TRUTH TABLE
TC4203
Logic
TC4201
SW1-4
TC4202
SW1-4
SW1
SW2
SW3
SW4
0
Closed
Open
Open
Open
Closed
Closed
1
Open
Closed
Closed
Closed
Open
Open
ORDERING INFORMATION
Part No.
Package
TC420XCPE
16·Pin Plastic DIP
16-Pin SO Wide
TC420XCOE
TC420XIJE
16-Pin CerDIP
TC420XMJE
16-Pin CerDIP
NOTE: X= 1,2 or3.
Temperature Range
O·Cto +70·C
O·C to + 70·C
-2S·C to +8S·C
-SS·C to + 12S·C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Vs+toVs- .......................................................... +lBV
VS+to GND ......................................................... +lBV
Vs-to GND .........................................................-lBV
VsorVotoVs- ......................................... OVto+1BV
VSorVotoVS+ ......................................... OVto-1BV
VOIGITAL to GND ............................................. VS-, Vs+
Current'
Any Pin ............................................................. 20 mA
S or D. Peak (1 ms, 10% Duty Cycle) ............... 70 mA
Storage Temperature Range .................. +6SoC to +lS0°C
Operating Temperature Range
Plastic DIP (C) ....................................... O°C to +70°C
CerDIP (I) ........................................... -2SoC to +BSoC
CerDIP (M) ....................................... -5SoC to +12SoC
Package Power Dissipation (TA = +2S°C)
Plastic DIP (C) ........................... 37S mW (Notes 1. 2)
CerDIP (I and M) ........................ SOO mW (Notes 1. 3)
* Input voltages that exceed Vs' or Vs- will be clamped by intemal
diodes. Umit current to maximum current ratings.
NOTES: 1. All pins soldered or welded to PC board.
2. Derate at 6.5 mW/"C above +75°C.
3. Derate at 13 mW/"C above +75·C.
Static-sensitive devices. Unused devices should be stored in conductive
material. Stresses above those listed under' Absolute Maximum Ratings'
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied.
ELECTRICAL CHARACTERISTICS: Vs+ =+SV. Vs- =OV. GND =OV. unless otherwise indicated.
Symbol
Parameter
O°Cto -25°C to -55°C to
+25°C
+70°C
+B5°C
+125°C
Min Typ Max Min Max Min Max Min Max Unit
Test Conditions
Switches
Vs, Vo
Analog Input Signal
Range
rOS(ON)
Drain Source
On Resistance
Source Off Leakage
Current
IS(OFF)
IO(OFF)
IO(ON)
Drain Off Leakage
Current
Drain On Leakage
Current
0
-
S
0
S
Is = 1 mA, Switch On
-
lOS
19S
-
240
-
240
Vs = O.SV to 4.SV,
Vo = 4.5 to O.SV, Switch Off
-
0.01
1
-
100
-
100
Vs = O.SV to 4.SV.
Vo = 4.5 to O.SV. Switch Off
-
0.01
1
-
100
-
100
0.02
1
-
200
-
200
Vo = Vs = O.SV to 4.5V,
Switch Off
12-40
0
S
0
S
V
260
n
120
nA
-
120
nA
-
230
nA
-
QUAD SINGLE-POLE
CMOS ANALOG SWITCHES
TC4201
TC4202
TC4203
ELECTRICAL CHARACTERISTICS:
Symbol
Parameter
vs+ = +5V, vs- = -5V, GND = av, unless otherwise indicated.
O°Cto -25°C to -55°C to
+25°C
+70°C
+85°C
+125°C
Min Typ Max Min Max Min Max Min Max Unit
Test Conditions
Switches
-5
-
+5
-5
+5
-5
+5
-5
+5
V
VD ±3.5V, Switch On,
Is= 1 mA
-
95
175
-
230
-
230
-
250
n
Source Off Leakage
Current
Vs = ±4.5V, VD = +4.5V,
Swttch Off
-
0.01
1
-
100
-
100
-
120
nA
ID(oFF)
Drain Off Leakage
Current
Vs = ±4.5V, VD = +4.5V,
Switch Off
-
0.Q1
1
-
100
-
100
-
120
nA
ID(oN)
Drain On Leakage
Current
VD = Vs = ±4.5V,
Swttch On
-
0.02
1
-
200
-
200
-
230
nA
Vs, VD
Analog Input Signal
Range
rDS(ON)
Drain Source
On Resistance
Is(oFF)
..
Digital
=
VINH
Input High Voltage
(Logic "1")
-
1.5
2.4
-
2.4
-
2.4
-
2.4
V
VINL
Input Low Voltage
(Logic "0")
0.8
1.5
-
0.8
-
0.8
-
0.8
-
V
IINH
Input Current Wtth
Input High Voltage
VIN= 5V
-
0.001
1
-
10
-
10
-
12
IlA
IINL
Input Current Wtth
Input Low Vottage
VIN= OV
-
0.001
1
-
10
-
10
-
12
J.LA
tON
Turn-On Time
See Switch Time
Test Circuit
-
250
500
-
650
-
650
-
750
ns
tOFF
Turn-Off Time
See Switch Time
Test Circuit
-
185
350
-
450
-
450
-
550
ns
QINJ
Charge Injection
CL = 1 nF, VGEN = OV,
RGEN= on
-
5
-
-
-
-
-
-
-
pC
CS(OFF)
Source Off
Capacitance
Drain Off Capacitance
VD = Vs = OV, f = 100 kHz
8
-
-
-
8
-
-
-
-
-
pF
Vo = Vs = OV, f = 100 kHz
-
pF
Channel-On
Capacitance
-
-
CC(ON)
-
OIRR
Off Isolation
-
-
-
-
-
-
-
dB
85
-
-
Cross-Talk Rejection
f = 100 kHz, RL = 1000n
f = 100 kHz, RL = 1000n
-
CCRR
Dynamic
CD(OFF)
VD = Vs = OV, f = 100 kHz
-
23
65
-
pF
dB
Power Supply
Is+
Positive Supply
Current
VIN= 5V
-
275
500
-
700
-
700
-
750
IlA
Is
Negative Supply
Current
VIN= 5V
-
0.Q1
10
-
10
-
10
-
12
IlA
16
3
16
3
16
3
Supply Operating Range
3
Vs+ to Vs and Vs+ to GND
12-41
QUAD SINGLE-POLE
CMOS ANALOG SWITCHES
TC4201
TC4202
TC4203
TYPICAL CHARACTERISTIC CURVES
Turn-On/Off Time vs Temperature
700
Cross TalklFeedthrough vs Frequency
-160
T~ ~ :2~!6
-150
iii'
550
.s... 450
..... 500
g -110
~~ -100
~i= -90
olil
~
~ 400
i=
-80 ~
I'
-70
~
-60
CROSSTALK
-40
10k
350
300
250
~·~.L.l111
-50 FEEOTHROUGH
I I~
lOOk
1M
FREQUENCY (Hz)
200
150
10M
...
-
...
~~
...
_...
1--
toFF
On Resistance vs Temperature
500
Cf450
iU'400
VS=:t5V
Vo,s=ov
240
§: 220
~200
~35O
! 180
!ii300
ffl250
~200
V
0150
100
50
7.5
- --
"... i'"
280
260
ITA = ~25DC
550
-f(~
,...
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE CDC)
On Resistance vs Input Voltage
600
o
vO,s=ov
600
3i' -120
~
VSI=:t5~
650
-140
-130
vs= :t2.5V
/'" --.1
l'
vs=~
VS=:t7.5V
5.0
!!l 160
UI
~
II!
r
2.5
0
-2.5 -5.0
INPUT VOLTAGE (V)
140
~ 120
100
f-----
80
60
-7.5
-
~
,.,.. ,.,..
--
-
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE CDC)
12·42
QUAD SINGLE-POLE
CMOS ANALOG SWITCHES
TC4201
TC4202
TC4203
TEST CIRCUITS
Switching Time
LOGIC INPUT: ~. If <20 ns
+SV
LOGIC "0"
SWITCH
OUTPUT
SWITCH S1
INPUT 0 - , - - - - - ( : 1 '
Vs =+2V
= SWITCH ON
50%
o
50%
S~~~ VS--t-------+--9O%.r-------+~
LOGIC
INPUT
SWITCH
OUTPUT
Vo - - I - - J
-
JL
toN
NOTE: Repeat test for A2. A3 and A4.
Charge Injection
AV
L
---I--.......--oVO
l.J"
I
CL = 1000 pF
VO~
-..
INxO'N\
ION
..
~-
Q=CAV
Off Isolation
Channel-to-Channel Cross-Talk
-SV
CCRR
12-43
=20 Log ~~
-SV
NOTES
12-44
~~TELEDYNE
COMPONENTS
TC441
TC442
TC443
MICROPROCESSOR COMPATIBLE CMOS ANALOG SWITCHES
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The TC441 , TC442 and TC443 are CMOS quad, SPST
analog switches with data address latches. Their pinouts
match the "201/221" analog switch configuration. The write
input (WR, pin 12) is not used on the 2011221. The address
latch is transparent when WR is tied low.
This switch family features single- or dual-supply operation, with analog input voltage range equal to the supply
voltage. The CMOS design requires very low supply current.
The TC441 has four normally-closed (Form 8) contacts,
the TC442 has four normally-open contacts (Form A), and
the TC443 has two normally-open and two normally-closed
contacts.
The TC443 can be configured as two DPST (Form C)
switches.
Data Address Latch On-Chip
Transparent Latch With WR =0
Write Pulse Operation ................................ < 250 ns
Dual- or Single-Supply Operation
Low rOS(ON) (+25°C) ..........••...•...•••.........• < 1750 Max
Supply Current •....••...•••...•••..•.....•....•.....••...•.. 300 ~A
Analog Input Equal to Supply
Analog Input Leakage Current ......................... 1 nA
TTUCMOS Compatible
Low-Current Logic Input
Pin Compatible With DG201 and DG221 (TC441)
PIN CONFIGURATIONS
A4
A4
A4
04
04
D4
S4
54
54
vs
vs
vs
WR
WR
WR
03
03
D3
swrrcHES SHOWN WITH An = 0
12-45
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC441
TC442
TC443
ORDERING INFORMATION
Part No.
TC44XCPE
TC44XCOE
TC44XIJE
TC44XMJE
ABSOLUTE MAXIMUM RATINGS
Package
Temperature Range
16-Pin Plastic DIP
16-Pin Plastic SO
16-Pin CerDIP
16-Pin CerDIP
O·Cto +70·C
O·Cto +70·C
-2S·C to +8S·C
-SS·C to + 12S·C
Supply Voltages
Vs+toVs- .......................................................... +18V
Vs+to GND ......................................................... +18V
Vs-to GND ......................................................... -18V
Vs or Vo to Vs+ ............................................ OV.-18V
VsorVoto Vs- ............................................ OV. +18V
VOIGITAL to GND ............................................. Vs-. Vs+
Current"
Any Pin ............................................................. 20 mA
S or D. Peak (1 ns. 10% Duty Cycle) ................ 70 mA
Storage Temperature Range .................. -65°C to +150°C
Operating Temperature Range
Plastic DIP (C) ....................................... O°C to +70°C
CerDIP (I) ........................................... -25°C to +85°C
CerDIP (M) ........................................ -55°Cto + 125°C
Package Power Dissipation (TA +25°C)
Plastic DIP (C) ..................... 375 mW (Notes 1 and 2)
CerDIP (I and M) .................. 500 mW (Notes 1 and 3)
X.1,20r3.
TRUTH TABLE (Switch State)
WR
TC441
TC442
0
Closed
Open
o
0
x
TC443
SW1,
SW3,
SW1,
Open
Closed
SW3,
Maintain Previous State
SW2 Open
SW4 Closed
SW2 Closed
SW4 Open
=
TIMING DIAGRAM
* Input voltages that exceed Vs· orVs-wili be clamped by internal
diodes. Limit current to maximum current ratings.
NOTES: 1. All pins soldered or welded to PC board.
2. Derate at 6.5 mWI"C.
3. Derate at 13 mWI"C above +75°C .
4. Static-sensitive device. Unused devices must be stored in
conductive material. Protect devices from static discharge
and static fields. Stresses above those listed under
Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only and
functional operation of the device at these or any other
conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to
Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ADDRESS VAUD
ADDRESS
.1
tww
. - - tosw _
tDHW
WR~' - -_ _ _ _ _ _ _...J/toHW:
"-<50-ns
tosW: <250 ns
tww: <250ns
ELECTRICAL CHARACTERISTICS:
Symbol
Parameter
Vs+
= +5V. Vs- = OV. GND = OV. unless otherwise indicated.
-25°C -55°C to
O°Cto
+05°C
+25°C
+70°C
+125°C
Min Typ Max MiniMax MiniMax MiniMax Unit
I
Test Conditions
I
Switches
Vs. Vo
rOS(ON)
IS(OFF)
ID(OFF)
IO(ON)
Analog Input Signal
Range
Drain Source
On Resistance
Source Off Leakage
Current
Drain Off Leakage
Current
Drain On Leakage
Current
Is
=1 mA, Switch On
Vs = O.SV-4.SV.
Vo = 4.SV-o.SV. Switch Off
Vs = 0.SV-4.SV,
Vo = 4.SV-o.SV. Switch Off
Vo = Vs = 0.SV-4.5V.
Switch Off
12-46
0
-
S
-
lOS
19S
-
0.01
-
0
5
0
S
-
240
240
1
-
100
-
0.01
1
-
100
0.02
1
-
200
0
S
V
260
n
100
-
120
nA
-
100
-
120
nA
-
200
-
230
nA
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC441
TC442
TC443
ELECTRICAL CHARACTERISTICS:
Vs+ = +5V, Vs- = -5V, GND =
+25°C
Symbol
Parameter
Test Conditions
Min
I Typ I
av, unless otherwise indicated.
O°Cto
-25°C
-55°C to
+85°C
+70°C
+125°C
Max MiniMax MiniMax Min ~ax
Unit
Switches
-5
-
+5
-5
+5
-5
+5
-5
+5
V
Vo = ±3.5V, Switch On,
Is = 1 mA
-
95
175
-
230
-
230
-
250
a
Source Ofl Leakage
Current
Vs = ±4.5V, Vo = +4.5V,
Switch Off
-
0.01
1
-
100
-
100
-
120
nA
IO(OFF)
Drain Ofl Leakage
Current
Vs = ±4.5V, Vo = +4.5V,
Switch Off
0.01
1
-
100
-
100
-
120
nA
IO(ON)
Drain On Leakage
Current
Vo = Vs = ±4.5V,
Switch On
0.02
1
-
200
-
200
-
230
nA
Vs, Vo
Analog Input Signal
Range
rOS(ON)
Drain Source
On Resistance
IS(OFF)
-
Digital
VINH
Input High Voltage
(Logic "1")
-
1.5
2.4
-
2.4
-
2.4
-
2.4
V
VINL
Input Low VoHage
(Logic "0")
0.8
1.5
-
0.8
-
0.8
-
0.8
-
V
IINH
Input Current With
Input High Voltage
VOIGITAL = 5V
-
0.001
1
-
10
-
10
-
12
IlA
IINL
Input Current With
Input Low VoHage
VOIGITAL = OV
-
0.001
1
-
10
-
10
-
12
IlA
tww
Write Pulse Width
See Timing Diagram
-
-
250
500
650
-
325
See Timing Diagram
-
325
Data Setup Time
-
250
tosw
Dynamic
250
50
325
50
-
tOHW
Data Hold Time
See Timing Diagram
tON
Turn-On Time
See Switch Time
Test Circuit
tOFF
Turn-Off Time
See Switch Time
Test Circuit
-
185
350
-
450
-
450
qNJ
Charge Injection
CL = 1 nF, VGEN = OV,
RGEN= 00
-
5
-
-
-
-
-
-
CS(OFF)
Source-Ofl
Capacitance
Vo = Vs = OV, I = 100 kHz
-
8
-
-
-
-
-
-
CO(OFF)
Drain-Off Capacitance
Vo = Vs = OV, I = 100 kHz
-
Vo = Vs = OV, I = 100 kHz
23
-
-
Channel-On
Capacitance
(Except TC444
-
-
CC(ON)
-
-
-
OIRR
Off Isolation
1= 100 kHz, RL = 10000
-
65
-
-
-
CCRR
Cross-Talk Rejection
1= 100 kHz, RL= 1000W
-
-
8
50
325
375
ns
375
ns
50
ns
750
ns
550
ns
-
pC
-
pF
- - -
pF
650
-
-
-
-
pF
-
-
-
-
dB
-
70
-
-
275
500
10
-
700
10
-
700
0.01
16
3
16
3
16
-
-
dB
Power Supply
Is+
Positive Supply Current
VOIGITAL = 5V
Is
Negative Supply
Current
VOIGITAL = 5V
10
- 1750 lIlA
112 lIlA
-
Supply Operating Range
3
12-47
3
116
IV
If!
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC441
TC442
TC443
TYPICAL CHARACTERISTIC CURVES
Crosstalk & Feedthrough
vs. Frequency
Turn-OnlTurn-Off Time
vs. Temperature
400
-90
i ,
a-80
o
350
r\
~-70
..
..J
~
~
1\
~-50
~
w
CROSSTALK
,"
~r,
~-60
200
t.
FEEOTHROUGH
111111111
-40
10k
I I
10M
On Resistance
vs. Temperature
TA=25°C
200
... ~
,,~
-
7.5
5.0
z
..... ~
I
~
Vs
~
til
0100
w
a:
°eo
02
...;-...
r--
,~
z~120
",.
i-"
,/
"
V
V
i"""
60
-65 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (OC)
BONDING DIAGRAM
VS=:t5.0V
~ 100
140
150
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE eC)
r h"
w
.. .....
"TOFF
V
.,150
o
V ...... .....
g
KON
/
.1
~
Vs = :t2.5V
.:.
50
/
I-""
1''''
100k
1M
FREQUENCY (Hz)
250
/
250
VS=:t5V
Vo,s=OV
.".
L
/
I 300
b
III
o
160
VS =:t5V
vO,s=OV
TA=25°C
\~,
:l
On Resistance
vs. Temperature
=r
A2.-
S2
GND
I I
I
-At
66 mil
A3-
5V
2.5
0
-2.5 -5.0 -7.5
INPUT VOLTAGE (V)
12-48
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC441
TC442
TC443
TEST CIRCUITS
WR Switching Time
=
LOGIC INPUT tR' tF < 20 ns
LOGIC "0" = SWITCH ON
_
3V
WR
A1
SWITCH
OUTPUT
01
3V-----,
o ------'-r----'
VS---------t~====~~Vo
0 _ _ _ _ _ _+_'
-= GND
NOTE: REPEAT TEST FOR A2 • A3 AND A 4 .
Charge Injection
I
CL
=1000pF
Q=Ct>V
Off Isolation
+5V
IfI
Channel-to-Channel Cross Talk
C=0.1
+5V
~F
C=O.1~F
CCRR = 20 Log VS1
VD2
SIGNAL
GENERATOR
OV
NC
-5V
12-49
NOTES
12-50
.,"'TELEDYNE
COMPONENTS
TC444
TC445
TC446
TC447
MICROPROCESSOR COMPATIBLE CMOS ANALOG SWITCHES
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TC444, TC445 , TC446 and TC447 are CMOS
analog switches offering low on-resistance at low supply
voltages. Each provides for transparent (nonlatched) or
latched addresses, making them ideal for microprocessor
interface applications.
This switch family features single- or dual-supply operation, with analog input range equal to supply voltages.
The CMOS design requires very low supply current.
The TC444 is configured as two single-pole, threeposition switches. Either switch can be independently selected (transparent or latched) for its own A or B position.
(See TC444 Switch Circuit.)
Also, both switches are put in the C position (both open)
by pulling the DISABLE input low. These various switch
positions can be latched using the WRITE (WR) input. This
switch is especially useful in muHi-path operations requiring
complete isolation.
The TC445 is configured as four independent, normallyopen switches. The WR input is used to latch the switches
in any selected mode, or may be held low for transparent
operation.
The TC446 has the same features as the TC445 , except
the switches are normally closed.
The TC447 provides two normally-open and two normally-closed switches. Its operation is the same as the
TC445 and TC446.
The TC444 is pin compatible with the AD7592. The
TC445ITC446 is pin compatible with the AD7590/AD7591.
Data Address Latch On-Chip
Low-Power CMOS
Write ................................................................ 250 ns
Transparent Latch With WR = 0
Write Pulse Operation ................................. <250 ns
Address Hold Time ........................................ <50 ns
Dual- or Single-Supply Operation
rDS(ON) (+25°C) ......................................... <175(1 Max
Supply Current .............................................. 300 IlA
Analog Input Equal to Supply
Analog Input Leakage Current ......................... 1 nA
nUCMOS Compatible
Low-Current Logic Input
Pin Compatible With AD7590 Series
PIN CONFIGURATION
~"
..,,,
~"
TC444
TC445
TC446
51
OUT 1
52
OUT2
'INTERNALLY PULLED HIGH.
NOTE:
1073-1
All swttches shown with An = O.
12-51
~"
TC447
1m
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC444
TC445
TC446
TC447
ORDERING INFORMATION
TC444 SWITCH CIRCUIT
Part No.
"A"---O
l
Package
Temperature Range
TC444
"c"~
"S" - - - 0 '",
NOTE; Both switches may be latched in the off state
by pulling WR high when DISABLE is low.
TIMING DIAGRAM
TC444CPD
14·Pin Plastic DIP
TC444COD
14·Pin Plastic SO
TC444IJD
14-Pin CerDIP
-25°C to +85°C
TC444MJD
14-Pin CerDIP
-55°C to + 125°C
O°Cto+70°C
O°Cto +70°C
TC445J446I447
TC44XCPE
16·Pin Plastic DIP
TC44XCOE
16·Pin Plastic SO
TC44XIJE
16·Pin CerDIP
-25°C to +85°C
TC44XMJE
16·Pin CerDlP
-55°C to + 125°C
O°Cto+70°C
O°Cto +70°C
X=5,6or7
ADDRESS
""","""",:.v-I
ADDRESS VAUD
TC444 TRUTH TABLE (Switch State)
DIsABLE
AN
WR
0
X
X
All switches open
0
0
S2 to OUT 1 closed
S4 to OUT 2 closed
0
51 to OUT 1 closed
53 to OUT 2 closed
X
TC44514461447 TRUTH TABLE (Switch State)
TC444
Maintain previous state
AN
WR
TC445
TC446
TC447
0
0
Open
Closed
SW1, SW4 open
SW2, SW3 closed
0
Closed
Open
SW1, SW4 closed
5W2, SW3 open
X
X = Don't Care
12·52
Maintain previous state
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC444
TC445
TC446
TC447
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Vs+toVs- .......................................................... +18V
Vs+to GND ......................................................... +18V
Vs-to GND ......................................................... -18V
VsorVotoVs+ ............................................ OV.-18V
VsorVotoVs- ............................................ OV.+18V
VOIGITAL to GND ............................................. Vs-. Vs+
Current"
Any Pin ............................................................. 20 rnA
S or D. Peak (1 ns. 10% Duty Cycle) ................ 70 rnA
Storage Temperature ............................. -65°C to +150°C
ELECTRICAL CHARACTERISTICS:
Symbol
Switches
Vs. Vo
rOS(ON)
IS(OFF)
IO(OFF)
IO(ON)
Parameter
Analog Input Signal
Range
Drain Source
On Resistance
Source Off Leakage
Current
Drain Off Leakage
Current
Drain On Leakage
Current
Switches
Vs. Vo
rOS(ON)
IS(OFF)
IO(OFF)
lo(oN)
Digital
VINH
VINL
Parameter
Analog Input Signal
Range
Drain Source
On Resistance
Source Off Leakage
Current
Drain Off Leakage
Current
Drain On Leakage
Current
'Input voltages that exceed Vs· or Vs- will be clamped by intemal
diodes. Umit current to maximum current ratin9s.
NOTES: 1. All pins soldered or welded to PC board.
2. Derate at 6.5 mWrC.
3. Derate at 13 mWrC above +75"C.
Vs+ = +5V. Vs- = OV. GND = OV. unless otherwise indicated.
O°Cto -25°C to -55°C to
+25°C
+70°C
+85°C
+125°C
Min Typ Max Min Max Min Max Min Max Unit
Test Conditions
0
-
Is = 1 rnA. Switch On
-
Vs = O.SV to 4.SV.
Vo = 4.S to O.SV. Switch Off
Vs = O.SV to 4.SV.
Vo = 4.S to O.SV. Switch Off
=
Vo = Vs O.SV to 4.SV.
Swttch Off
ELECTRICAL CHARACTERISTICS:
Symbol
Operating Temperature Range
Plastic DIP (C) ....................................... O°C to +70°C
CerDIP (I) ........................................... -25°C to +85°C
CerDIP (M) ........................................ -55°Cto +125°C
Package Power Dissipation (TA = +25°C)
Plastic DIP (C) ........................... 375 mW (Notes 1. 2)
CerDIP (I and M) ........................ 500 mW (Notes 1. 3)
S
0
S
0
S
0
S
V
lOS
19S
-
240
-
240
-
260
n
-
0.01
1
-
100
-
100
-
120
nA
-
0.01
1
-
100
-
100
-
120
nA
-
0.02
1
-
200
-
200
-
230
nA
Vs+ = +5V. Vs- =-5V. GND = OV. unless otherwise indicated.
O°Cto -25°C to -55°C to
+85°C
+25°C
+70°C
+125°C
Min Typ Max Min Max Min Max Min Max Unit
Test Conditions
-S
-
S
-S
S
-S
S
-S
S
V
Vo = ±3.SV. Switch On.
Is= 1 rnA
-
9S
17S
-
230
-
230
-
2S0
n
Vs = ±4.SV. Vo = +4.SV.
Switch Off
-
0.01
1
-
100
-
100
-
120
nA
Vs = ±4.SV. Vo = +4.SV.
Switch Off
-
0.01
1
-
100
-
100
-
120
nA
Vo = Vs = ±4.SV.
Switch On
-
0.02
1
-
200
-
200
-
230
nA
-
1.S
2.4
-
2.4
-
2.4
-
2.4
V
0.8
1.S
-
0.8
-
0.8
-
0.8
-
V
Input High Voltage
(Logic "1")
Input Low Vottage
(Logic "a")
12·53
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC444
TC445
TC446
TC447
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
Parameter
Digital (Cont.)
Input Current With
IINH
Input High Voltage
Input Current With
hNL
Input Low Voltage
DISABLE Input
VINH
(TC444)
DISABLE Input
VINL
(TC444)
Dynamic
Write Pulse Width
tww
Data Setup Time
tosw
Data Hold Time
tOHW
Turn-On Time
tON
tOFF
Turn-Off Time
QINJ
Charge Injection
CS(OFF)
Source-Ofl
Capacitance
Drain-Oll
Capacitance
Channel-On
Capacitance
(Except TC444)
Channel-On
Capacitance
(TC444 Only)
Ofl Isolation
Cross-Talk Rejection
CO(OFF)
CC(ON)
CC(ON)
O°Cto -25°C to -55°Cto
+700C
+25°C
+85°C
+125°C
Min Typ Max Min Max Min Max Min Max Unit
Test Conditions
VOIGITAL = 5V
-
0.001
1
-
10
-
10
-
12
j.LA
VOIGITAL = OV
-
0.001
1
-
10
-
10
-
12
J.lA
VDIGITAL = 5V
-
0.1
10
15
-
15
-
17
j.LA
5
10
-
15
-
15
-
15
J.lA
See Timing Diagram
See Timing Diagram
See Timing Diagram
See Switch Time
Test Circuit
See Switch Time
Test Circuit
CL = 1 nF, VGEN = OV,
RGEN= on
Vo = Vs = OV, I = 100 kHz
-
-
-
325
325
50
650
-
325
325
50
650
-
250
250
250
50
500
-
375
375
50
750
ns
ns
ns
ns
-
185
350
-
450
-
450
-
550
ns
-
5
-
-
-
-
-
8
-
-
-
-
- - - - -
Vo = Vs = OV, I = 100 kHz
-
8
-
-
-
-
-
-
Vo = Vs = OV, I = 100 kHz
-
23
-
-
-
-
-
-
Vo = Vs = OV, I = 100 kHz
-
30
-
-
-
-
- - -
-
65
70
-
- - -
-
-
-
-
dB
dB
-
275
500
700
-
700
-
750
J.lA
-
0.01
10
-
10
-
10
-
12
J.lA
3
-
16
3
16
3
16
3
16
V
VOIGITAL = OV
DIRR
1= 100 kHz, RL= 1000n
CCRR
1= 100 kHz, RL = 1000n
Power Supply
Is+
Positive Supply
VOIGITAL = 5V
Current
Negative Supply
Is
VOIGITAL = 5V
Current
Supply Operating Range
Vs+ to Vs- and Vs+ to GND
12-54
-
-
-
-
pC
pF
pF
pF
pF
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC444
TC445
TC446
TC447
TYPICAL CHARACTERISTIC CURVES
Turn-OnlTurn-Off Time vs Temperature
Cross TalklFeedthrough vs Frequency
-160
700
T~I=!i5Iog
-150
-140
600
iii -130
i'
ufil
~
'iii'
500
.,5.450
w
:; 400
-90
-80 ::-...
.......
-70
i=
250
N:.L~IIII
-so FEEOTHROUGH
-40
10k
350
300
CROSSTALK
-60
I~
200
100k
1M
FREQUENCY (Hz)
10M
I TA
-- --
~
~-
toFF
On Resistance vs Temperature
=125°C
VS =:t5V
VO,s=OV
260
240
8'450
;;:;400
§: 220
~ 200
350
~180
I-
!D 3OO
,...
[3250
~200
V
0150
50
l'
Vs = :t5'!,:
VS=:t7.5V
5.0
~ 160
~ 140
VS=:t2.5V I-----"i....-".I
100
7.5
.... ....
280
500
o
--
...........
to~
~J
.......
150
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (OC)
On Resistance vs Input Voltage
600
550
~
.l
550
~ -120
;:!: g -110
f1! ~ -100
~j!:
I
VS =:t5V _
VO,S=OV _
650
~ 120
~
-
100
r----
2.5
0
-2.5 -5.0
INPUT VOLTAGE (V)
80
-- - -f-""'"
I-'
60
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (OC)
-7.5
12·55
MICROPROCESSOR COMPATIBLE
CMOS ANALOG SWITCHES
TC444
TC445
TC446
TC447
TEST CIRCUITS
Switching Time
+5V
LOGIC
INPUT
SWITCH
INPUT
VS--~------------~--LOGIC
INPUT
'oFF
n
Charge Injection
o--t--.--o Vo
~
OFF
Q=cAv
OIRR Off Isolation
OIRR
CCRR Channel-to-Channel Cross-Talk
Vs
=20 Log Vi)
CCRR = 20 Log -
VS1
V02
0.111F
+5V
.0-~::-------,
v+
ANALVZER
~V
~V
12·56
Section 13
Data Communications
Display NO Converters
Binary NO Converters
2
Voltage-to-Frequency/Frequency-to-Voltage Converters
3
Sensor Products
4
Power Supply Control ICs
5
Power MOSFET, Motor and PIN Drivers
6
References
7
Chopper-Stabilized Operational Amplifiers
8
High Performance Amplifiers/Buffers
9
Video Display Drivers
10
Display Drivers
11
Analog Switches and Multiplexers
12
Data Communications
13
Discrete DMOS Products
14
Reliability and Quality Assurance
15
Ordering Information
16
Package Information
17
Sales Offices
18
.,"'TELEDYNE
COMPONENTS
TC232*
DUAL RS-232 TRANSMITTER/RECEIVER AND POWER SUPPLY
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
The TC232 is a dual RS-232 transmitter/receiver that
complies with EIA RS-232C guidelines and is ideal for all
RS-232C communication links. This device has a SV power
supply and two charge pump voltage converters that produce
±10V power supplies.
The TC232 has four level translators. Two are RS·232
transmitters that convert TTUCMOS input levels to 9V RS·
232 outputs. The other two translators are RS-232 receivers
that convert RS-232 inputs to SV TTUCMOS output levels.
The receivers have a nominal threshold of 1.3V, a typical
hysteresis of O.SV, and can operate with up to ±30V inputs.
Meets All RS-232C Specifications
Operates From Single 5V Power Supply
2 Drivers and 2 Receivers
On-Board Voltage Quadrupler
Input Levels ..•••••.......••......•••....•.••.....•............•... ±30V
Output Swing With +5V Supply •...•..•.••........•..... ±9V
Low Power CMOS ....••........••....•........••......•.•..... 5 mA
TYPICAL APPLICATION
+5VINPUT
C3'
10 pF
+
----:l\-z,---,
10 PF:c
16
Vcc
+5V TO +10V
VOLTAGE DOUBLER
,
2
,
v+ I--~"""----,
+10V
+
+10VTO-l0V
v- -10V
~_ _~~~~V:0~LT~A:G:E~IN:V~E~R~T~ER~_ _~6
TT~~~~~ 1
10 T2IN
>-----If---.....
----I
'NOTE: C3 can be connected between
V+ and VCC for convenience.
1070-1
.x>------+--... }
T
C3'
10 pF
~~"
15
13·'
'Patented
DUAL RS-232 TRANSMITTER!
RECEIVER AND POWER SUPPLY
TC232
ORDERING INFORMATION
APPUCATIONS
The TC232 is ideal for all RS-232C communication links:
Battery-powered systems, computers, instruments, moderns,
and peripherals. It can run without the 12V power supplies
other RS-232 devices require.
Part No.
Package
Temperature
Range
TC232CPE
TC232CJE
16-Pin Plastic
16-Pin CerDIP
O°C to +70°C
O°C to +70°C
TC2321JE
16-Pin CerDIP
-25°C to +85°C
TC232EPE
16-Pin Plastic
-40°C to +85°C
TC2321PE
TC232EJE
16-Pin Plastic
-25°C to +85°C
-40°C to +85°C
TC232COE
16-Pin SO
O°C to +70°C
TC232EOE
16-Pin SO
-40°C to +85°C
TC232MJE
16-Pin CerDIP
-55°C to + 125°C
16-Pin CerDIP
PIN CONFIGURATIONS
COE
EOE
CPE
CJE
IJE
EPE
IPE
EJE
MJE
.,'"
TC232
ABSOLUTE MAXIMUM RATINGS
Power Dissipation
CerDIP ........................................................... 675 mW
Derate 9.5 mW/oC Above +70°C
Plastic DIP ..................................................... 375 mW
Derate 7 mW/oC Above +70°C
Small Outline (SO) ......................................... 375 mW
Derate 7 mW/oC Above +70°C
vee .............................................................................. +6V
V+ ............................................................................ +12V
V- ............................................................................ +12V
Input Voltages
T11N, T21N ..................................... -0.3 to (Vee +0.3V)
R11N, R21N .......................................................... ±30V
Output Voltages
T1oUT, T20UT ....................... (V+ +0.3V) to (V- -O.3V)
R1oUT, R20UT .............................. -0.3 to (Vee +0.3V)
Short Circuit Duration
V+ .................................................................... 30 sec
V- .................................................................... 30 sec
T1oUT, T20uT .......................................... Continuous
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under' Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
13-2
DUAL RS-232 TRANSMITTER!
RECEIVER AND POWER SUPPLY
TC232
ELECTRICAL CHARACTERISTICS: Vee = SV ±1 0%, TA = operating temperature range, test circuit unless
otherwise noted.
Parameter
Output Voltage Swing
Test Conditions
Min
Typ
Max
Unit
±5
±9
±10
V
T10UT, T20UT Loaded With
3 kO to Ground
Power Supply Current
5
Input Logic Threshold Low
T1IN, T21N
Input Logic Threshold High
T1IN, T21N
T1IN, T21N = OV
Logic Pull-Up Current
RS-232 Input Threshold High
Vee = 5V
J.lA
V
+30
1.2
0.8
RS-232 Input Hysteresis
RS-232 Input Resistance
T A = +25°C, Vee = 5V
TTUCMOS Output Voltage Low
lOUT = 3.2 mA
TTUCMOS Output Voltage High
IOUT=-l mA
RS-232 to TTL or TTL to RS-232
Propagation Delay
200
V
15
-30
Vee = 5V
mA
V
2
RS-232 Input Voltage Operating Range
RS-232 Input Threshold Low
10
0.8
Instantaneous Slew Rate
CL = 10 pF, RL = 3 kO to 7 kO,
T A = +25°C (Note 1)
Transition Region Slew Rate
RL = 3 kO, CL = 2500 pF
Measured From +3V to -3V
or-3Vto+3V
Output Resistance
Vee = V+ = V- = OV, VOUT
V
1.7
2.4
V
0.2
0.5
1
V
3
5
7
0.4
kO
V
V
3.5
0.5
J.ls
30
VlJ.ls
3
=±2V
VlJ.lS
0
300
RS-232 Output
Short-Circuit Current
mA
±10
NOTE 1. Sample tested.
DETAILED DESCRIPTION
V+, V- Output Voltages vs Load Current
The TC232 contains a +SV to ±10V dual charge pump
voltage converter, a dual transmitter and a dual receiver.
+5V to ±10V Dual Charge Pump
Voltage Converter
~ 8"""':+=""I-~:-t-1.t-t=""";;:F-r-l
~
i!.... 7 1--!-+....r-t--30r-t--''''''''..!:--t--l
The TC232 power supply consists of two charge pumps.
One uses external capacitor Cl to double the +SV input to
+10V, with output impedance of about 2000. The other
uses C2 to invert +10V to -10V, with overall output
impedance of 4S00 (including effects of +SV to + 1OV
doubler impedance).
The clock in the doubler circuit will start at >=4.2V in the
typical part, but external loads may make this point rise to as
high as 4.SV with a load of 2 k.Q on each of the two output
Voltages.
Because of this, use of the doubler and inverter to run
external circuits should be limited. The maximum current
should be no more than 2.S rnA from the +1 OV and -1 OV in
order to guarantee start-up of the doubler clock.
~
!:iDo.
!:i s I--t--t--+-t-f--.,...-t-"*-t--l
o
CONDITIONS:
4 A) TA =+2S C
D
B) TRANSMITTER OUTPUTS
3
OPEN CIRCUIT
o
13-3
1
2
3 4 S 6 7
"LOAD' (mA)
8
9
10
DUAL RS-232 TRANSMITTER!
RECEIVER AND POWER SUPPLY
TC232
The test circuit employs 221lF capacitors for C1 to C4,
butthe value is not critical. These capacitors usually are lowcost aluminum electrolytic capacitors, or polyester if size is
critical.
.
Increasing C1 and C2 to 47 IlF lowers the output
impedance of the +1 OV doubler and the -10V inverter by
the change in the ESR of the capacitors.
Increasing C3 and C4lowers ripple on the ±1 OV voltage
outputs and 16 kHz ripple on the RS-232 outputs. Where
size is critical, the value of C1 to C4 can be lowered to
1 IlF. The use of a low ESR-value capacitor will help lower
the output ripple and keep the output impedance of the
±10V as low as possible.
With Vee at 5V, the outputs will go from (V+-0.6V) to Vwith no load and will swing ±9V when loaded with 3 kil. The
minimum output voltage swing, with Vee at 4.5V and at
maximum ambient temperature, is ±5V. This conforms to
RS-232 specifications for "worst-case" conditions.
EIA RS-232C specs limit the slew rate at output to
less than 30V/lJ.S.
The powered-down output impedance (Vee =OV) is a
minimum of 300n with ±2V applied to outputs.
The outputs are short-circuit-protected and can be shortcircuited to ground indefinitely.
Dual Transmitter
TC232 receivers meet RS-232C input specifications.
Input impedance is between 3 kil and 7 kil. Switching
thresholds are within the ±3V limits, and the receivers
withstand up to ±30V inputs. RS-232 and TTUCMOS input
compatible, the receivers have 0.8V VIL and 2.4V VIH with
0.5V hysteresis to reject noise.
The TTUCMOS compatible receiver output is low when
RS-232 input is greater than 2.4V. It is high when input is
floating or between +0.8Vand -30V.
TC232 transmitters are CMOS inverters driven by ±1 OV
internally-generated voltages. The input is TTUCMOS
compatible, with a logic threshold of about 26% of Vee
(1.3V for 5V Vee). The input of an unused transmitter can
be left unconnected. An internal 400 kil pull-up resistor
connected between the transmitter input and Vee pulls the
input high and forces the unused transmitter output to the
low state.
Dual Receiver
TEST CIRCUIT
'1f"
TC232
.---11
C1 +
22J1F
22 JlF
+ 2
..c?
-=
C3
'----13
+4.SV TO +5.SV
INPUT
ct
V+
c1'
~ + . - - - 1 4 C;
22J1F
'----15
Ci
TTUCMOS OUTPUT
C4
RS-232
OUTPUT
..c-1
-= 22J1F
........ ,,,,,,,... 7
TTUCMOS INPUT
I-_-.
,oJ
D
60-----:
'~--Is
·oil
110-----:
.~O--<>'2
III
G
i,
L.:,.
•
G
~.
G
11
<>-::::J--J-<)4
1
• 0-----,,
6
,~C>-<)S
a o-1fLo
o
s
,
'~O--O12
110-----,
,,
140-----,
16~c>-<)13
Note:
Q
30-----,
,
Pin numbers correspond to
Package Pinout
•
PIN CONFIGURATION
0-11Lo
4 !
os'
o-:=r--Kt-Q
5
<>-:=r--KtQ
11
'o?f~12
14
o---:=:J---t2
SUBSTRATE
4361 FHD F01
1123-1 (4361)
.4381 FHDFD2
14-23
QUAD OMOS FET ANALOG
SWITCH ARRAYS
S05400
S05401
S05402
ABSOLUTE MAXIMUM RATINGS:
Tc =+25°C. unless otherwise noted.
VOB Drain-Body Voltage
8D5400 ........................................................... +25V
8D5401 ........................................................... + 15V
8D5402 ........................................................ +22.5V
Vos Drain-80urce Voltage
8D5400 ........................................................... +20V
8D5401 ........................................................... +10V
8D5402 ........................................................... +15V
VSB 80urce-Body Voltage
8D5400 ................ ~ .......................................... +25V
8D5401 ........................................................... +15V
8D5402 ........................................................ +22.5V
Vso 80urce-Drain Voltage
8D5400 ........................................................... +20V
8D5401 ........................................................... +10V
8D5402 ........................................................... +15V
VGB Gate-Body Voltage
8D5400 ................................................ -O.3V. +30V
8D5401 ................................................ -O.3V. +25V
8D5402 ................................................ -O.3V. +30V
VGO Gate-Drain Voltage
8D5400 ................................................. -25V. +30V
8D5401 ................................................. -15V. +25V
8D5402 .............................................. -22.5V. +30V
VGS
Gate-80urce Voltage
8D5400 ................................................. -25V. +30V
8D5401 ................................................. -15V. +25V
8D5402 .............................................. -22.5V. +SOV
10
Continuous Drain Current .............................. 50 rnA
Po Total Package Power Dissipation
@ or Below T A = +25°C .............................. 640 mW
Linear Derating Factor .......................... 5.33 mW/oC
Po
8ingle Device Power Dissipation
@ or Below TA = +25°C .............................. 300 mW
TJ
Operating Junction
Temperature Range ........................... O°C to +70°C
TSTG 8torage Temperature Range ........ -55°C to +125°C
Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
14-24
QUAD DMOS FET ANALOG
SWITCH ARRAYS
S05400
S05401
S05402
ELECTRICAL CHARACTERISTICS (TA = +25°C per channel, unless otherwise noted.)
Parameter
Test Conditions
BVos
Drain-Source
Breakdown Voltage
10 = 10 nA, VGS = VBS = -5V
20
25
-
10
25
-
15
25
-
V
BVso
Source-Drain
Breakdown Voltage
Is = 10 nA, VGO = VBO =-5V
20
-
-
10
-
-
15
-
-
V
BVoa
Drain-Substrate
Breakdown Voltage
ID = 10 nA, VGB = OV,
Source OPEN
25
-
22.5
-
-
V
Source-Substrate
Breakdown Voltage
Is = 10 IIA, VGB
Drain OPEN
=OV,
25
-
-
-
BVSB
-
-
22.5
-
-
V
10(OFF)
Drain-Source
OFF Current
VGS = VBS = -5V, Vos = 10V
VGs=VBs=-5V, Vos= 15V
VGS = VBS = -5V, Vos = 20V
-
-
-
-
-
-
nA
Source-Drain
OFF Current
VGO = VBO = -5V, Vso = 10V
VGO = VBO = -5V, Vso = 15V
VGO = VBO = -5V, Vso = 20V
Gate-Body Source
Leakage Current
VOB = VSB = OV, VGB = 25V
VOB = VSB = OV, VGB = 30V
VGS(TH)
Gate Source
Threshold Voltage
VDS = VGS, 10 = 1 IIA,
VSB=OV
0.1
rOS(ON)
Drain-Source
ON Resistance
VGs= 5V, 10= 1 mA,
VSB=OV
VGs= 10V, 10= 1 mA,
VSB=OV
VGS= 15V, 10= 1 mA,
VSB=OV
VGS = 20V, 10 = 1 mA,
VSB=OV
Symbol
Static
IS(OFF)
IGBS
-
-
15
15
-
1
-
1
2
-
50
-
-
-
-
-
10
10
-
10
10
-
-
-
-
10
-
-
-
10
-
-
-
nA
-
-
-
0.1
1
2
0.1
1
2
V
70
-
50
70
50
70
0
30
-
-
30
-
30
-
-
23
-
23
-
0
23
19
-
-
19
-
-
19
-
0
5
-
1
5
-
1
5
0
-
-
1
~A
1
0
Drain-Source Match
ON Resistance
VGs= 5V, 10= 1 mA,
VSB= OV
-
1
gm(FS)
Common-Source
Forward
Transconductance
Vos = 10V, 10 = 20 mA,
VSB = 01= 1 kHz
10
12
-
10
12
-
10
12
-
mmhos
C(GS+GO+GB)
Gate Node
Capacitance
Vos = 10V, VGS= VBS =-15V,
1=1 MHz
-
2.4
3.5
-
2.4
3.5
-
2.4
3.5
pF
C(GS+OB)
Drain Node
Capacitance
Vos = 10V, VGS= VBS=-15V,
1=1 MHz
-
1.3
1.5
-
1.3
1.5
-
1.3
1.5
pF
C(GS+SB)
Source Node
Capacitance
Vos = 10V, VGS= VBS=-15V,
1= 1 MHz
-
3.5
4
-
3.5
4
-
3.5
4
pF
ClOG)
Reverse Transfer
Capacitance
Vos= 10V, VGS= VBS=-15V,
1= 1 MHz
-
0.3
0.5
-
0.3
0.5
-
0.3
0.5
pF
-
-
dB
rOSM(ON)
Dynamic
CT
Cross-Talk
1=3 kHz, ~=6000
-
-107
-
-107
Turn ON Delay
Time
Voo = 5V, VG(ON) = 10V,
RL= 6800, RG = 510
-
0.7
1
-
0.7
1
-
-107
to(ON)
0.7
1
ns
tR
Rise Time
Voo = 5V, VG(ON) = 10V,
RL= 6800, RG = 510
-
0.8
1
-
0.8
1
-
0.8
1
ns
tOFF
Turn OFF Time
Voo = 5V, VG(ON) = 10V,
RL= 6800, RG = 510
-
10
-
10
-
10
14-25
-
-
-
-
ns
III
QUAO OMOS FET ANALOG
SWITCH ARRAYS
S05400
S05401
S05402
TEST WAVEFORMS
SWITCHING TIMES TEST CIRCUIT
o
INPUT PULSE
trs 0.5 nSEC
PULSE WIDTH-l00 "SEC
5100
SAMPUNG OSCILLOSCOPE
tr < 0.36 nSEC
Ain > 1Mn
Gin < 2.0 pF
510
..(IV _ _
-!.::.=~
_ _ _ _ _ _.z-
OSCILLOSCOPE
4361 FHD F03
4361 FHO F04
TYPICAL PERFORMANCE CHARACTERISTICS: TA =+25°C per channel, unless otherwise noted.
Drain-Source On Resistance
vs Gate-Source Voltage
g
w
0
Z
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