1992_Xilinx_Programmable_Gate_Array_Data_Book 1992 Xilinx Programmable Gate Array Data Book

User Manual: 1992_Xilinx_Programmable_Gate_Array_Data_Book

Open the PDF directly: View PDF .
Page Count: 418

Download
Open PDF In Browser	View PDF

~ XILINX

The Programmable Gate Array
,

·DataBook

1992

~ LINX

The Programmable Gate Array
Data Book

2100 Logic Drive
San. Jose, California 95124
Telephone: (408) 559-7778

e>Copyright 1992 by Xilinx, Inc. All Rights Reserved

Patents Pending

Contributors
Peter AHke
Nick Camilleri
Jim Chumbley
Atsuko D'Amour
Rick Dudley
Abu Eghan
Chuck Erickson
Lee Farrell
Brad Fawcett
Chuck Fox
Dave Galli

Jim Hsieh
Clay Johnson
Steve Knapp
Dave Lautzenheiser
Mark Markham
Farid Mazouni
Bob McGrath
Bill O'Neill
George Nelson
Bernard New
Julie Ng

Wes Patterson
Richard Ravel
Ed Resler
Mitch Richman
Randy Saldinger
Steve Schreifels
Robert Stransky
Mustafa Vezioroglu
Thomas Waugh
PerryWu
Bob Zielke

Xilinx, Logic Cell, LCA, XACT, and XACTOR, are trademarks of Xilinx,
Inc. The Programmable Gate Array Company is a Service Mark of
Xilinx, Inc.
IBM is a registered trademark and PCIAT, PC/XT, PS/2, and Micro
Channel are trademarks of International Business Machines
Corporation. ABEL and ABEL FPGA are trademarks and Data 1/0 is a
registered trademark of Data 1/0 Corporation. FutureNet is a registered
trademark and DASH is a trademark of FutureNet Corporation, a Data
1/0 Company. SimuCad and Silos are registered trademarks and P-Silos
and PIC-Silos are trademarks of SimuCad Corporation. Microsoft is a
registered trademark and MS-DOS is a trademark of Microsoft
Corporation. Logitech is a registered trademark of LOGITECH Inc. Lotus
is a registered trademark of Lotus Development Corporation.
AboveBoard and AboveBoardiPS are trademarks of Intel Corporation.
RAMpage!, SixPakPlus and SixPakPremium are registered trademarKs
of ASTResearch, Inc. Mouse Systems is a trademark of MouseSystems
Corporation. Centronics is a registered trademark of Centronics Data
Computer Corporation. PAL and PALASM are registered trademarks of
Advanced Micro Devices, Inc. UNIX is a trademark of AT&T
Technologies, Inc. CUPL is a trademark of Logical Devices, Inc.. Apollo
and AEGIS are registered trademarks of Hewlett-Packard Corporation.
Mentor and IDEA are registered trademarks and OuickSim, NETED,
EXPAND are trademarks of Mentor Graphics, Inc. ValidGED and

ValidSim are trademarks of Valid Logic Systems, Inc. Sun is a registered
trademark of Sun Microsystems, Inc. SCHEMA 11+ and SCHEMA III are
trademarks of Omation Corporation. OrCAD is a registered trademark of
OrCAD Systems Corporation. VI EWlogic, VIEWsim, and VI EWdraw are
registered trademarks of VIEWlogic Systems, Inc. CASE Technology is
a trademark of CASE Technology, a division of Teradyne's Electronic
Design Automation Group. DECstation is a trademark of Digital
Equipment Corporation. Design Framework, Amadeus and Veritime are
trademarks, and Verilog-XL is a registered trademark of Cadence
Design Systems, Inc.

Xilinx, Inc. does not assume any liability arising out of the application or
use of any product described herein; nor does it convey any license under
its patent, copyright or maskwork rights or any rights of others. Xilinx,lnc.
reserves the right to make changes, at any time, in order to improve
reliability, function or design and to supply the best product possible.
Xilinx, Inc. cannot assume responsibility for the use of any circuitry
described other than circuitry entirely embodied in their product. No other
circuit patent licenses are implied. Xilinx, Inc. cannot assume
responsibility for any circuits shown or repreSent thaI they are free from
patent infringement or of any other third party right. Xilinx, Inc. assumes
no obligation to correct any errors contained herein or to advise any user
of this text of any correction if such be made.

SECTION TITLES

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7 Article Reprints

B Index

TABLE OF CONTENTS

1 Programmable Gate Arrays
. About the Company
Introduction to Programmable Gate Arrays
A Cost of Ownership Comparison

1-1
1-3
1-11

2 Product Specifications
XC3000 Logic Cell Array Family
XC2064, XC2018 Logic Cell Arrays
Military Logic Cell Arrays
XC2018B Military Logic Cell Array
XC3020B Military Logic Cell Array
XC3042B Military Logic Cell Array
XC3090B Military Logic Cell Array
XC1736N1765 Serial Configuration PROM
Sockets

2-1
2-61
2-103
2-107
2-119
2-137
2-157
2-175
2-187

3 Quality, Testing, and Packaging
Quality Assurance and Reliability
Test Methodology
Packaging

3-1
3-12
3-18

4 Technical Support
Technical Seminars and Users' Group Meetings
Video Tapes
Newsletter
Technical Bulletin Board
Field Applications Engineers
Training Course
Technical Literature

4-1
4-2
4-3
4-4
4-6
4-7
4-8

5 Development Systems
OVerview
AutomatiC CAE Tools Product Overview
Product Briefs
Xilinx Development System Support Agreements
LCA Macro Library Listings
Development System Hardware Requirements

5-3
5-4
5-19
5-33
5-34
5-40

6 Applications
Introduction
Estimating Size and Performance
Designing with the XC3000 Family
Designing with the XC2000 Family
Additional Electrical Pararneters
LCA Performance
Delay Tracking
Start-up and Reset

6·1
6~3

6-7
6-8
6-9
6-11
6-14
6-15

TABLE OF CONTENTS

6 Applications

(Conf'dJ

Metastable Recovery
Battery Backup for Logic Cell Arrays
Compact Multiplexer and Barrel Shifter
Majority Logic, Parity
Multiple Address Decoding
Binary Adders, Subtractors, and Accumulators
Adders and Comparators
Conditional Sum Adder
Building Latches Out of Logic
Synchronous Counters, Fast and Compact
30 MHz Binary Counter Uses Less than One CLB per Bit
Up/Down Counter Uses One CLB per Bit
Loadable Up/Down Counter Uses One CLB per Bit
30 MHz Counter with Synchronous Reset/Preset
Fast Bidirectional Counters for Robotics
40 MHz Presettable Counter
Asynchronous Preset in XC3000 CLBs
Frequency/Phase Comparator for Phase-Locked-Loops
Gigahertz Presettable Counter
75 MHz Frequency Counter or Programmable Delay
Serial Pattern Detectors
Serial Code Conversion Binary to BCD
Serial Code Conversion BCD to Binary
Corner Bender or 8-Bit Format Converter
100 MHz Frequency Counter
Megabit FIFO in Two Chips
State Machines
Complex State Machine in One LCA
PS/2 Micro Channel Interface
DRAM Controller with Error Correction

6-16
6-18
6-19
6-20
6-21
6-22
6-23
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-36
6-37
6-38
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-48
6-49
6-50
6-52

7 Article Reprints
Building Reconfigurable Peripheral Controllers
Accelerate FPGA Macros with One Hot Approach
Reprogrammable Missile: How an FPGA Adds Flexibility to
Navy's Tomahawk
Pivoting Monitor Increases Versatility of Workstations
Two, Two, Two Chips in One
LCA Stars in Video
Taking Advantage of Reconfigurable Logic
Faster Turnaround for a T1 Interface
Using Programmable Logic Cell Arrays In a Satellite Earthstation
Programmable Logic Betters the Odds for Bet-Slip readers
Building Tomorrow's Disk Controller Today

8

7-1
7-8
7-13
7-15
7-19
7-22
7-24
7-33
7-35
7-40
7-44

Index
Index
Sales Office Listing

8-1
8-5

The Programmable Gate Array Company

PROGRAMMABLE LOGIC
DEVICES

GATE ARRAYS

EXTENSIVE
SIMULATION

PRIMITIVE

DEVELOPMENT
TOOLS

1162 01

THE PROGRAMMABLE GATE ARRAY
(LOGIC CELLTM ARRAY)

SECTION 1
Programmable Gate Arrays

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Programmable Gate Arrays

About the Company ............................................................................ 1-1
Introduction to Programmable Gate Arrays ......................................... 1-3
Programmable Gate Array Architecture .............................................. 1-4
Development Systems ........................................................................ 1-9
Technical Support ............................................................................... 1-10
A Cost of Ownership Comparison ....................................................... 1-11
Executive Summary ............................................................................ 1-11
ROM vs EPROM Analogy ................................................................... 1-12
Who Recognizes the Costs? ............................................................... 1-13
Fixed Development Costs ................................................................... 1-13
Variable Costs ..................................................................................... 1-15
Yield to Production .............................................................................. 1-17
Cost of Ownership Analysis ................................................................ 1-18
Break-even Analysis ........................................................................... 1-19
Time to Market .................................................................................... 1-19
Product Life Cycles ............................................................................. 1-19

About the Company ...

Xilinx was founded in 1984 based on the revolutionary
idea, to combine the high logic density and versatility of
gate arrays with the time-to-market advantages and offthe-shelf availability of user programmable standard parts.
In 1985, Xilinx produced the world's first fieldprogrammable gate array (FPGA). The company holds
patents on FPGA architecture and technology, and today
is the largest supplier of devices in this IC category,
predicted to be the fastest growing segment of the
semiconductor industry in the nineties. To date, the
company has sold over 8500 development systems and
five million FPGAs to more than 3500 system
manufacturers worldwide.

patible with the stringent time-to-market requirements.
With Xilinx FPGAs, design engineers can bring new products to market quickly without sacrificing the benefits of
integration. Many systems can be manufactured with only
three types of standard high-volume components-microprocessors, memories and FPGAs.
Xilinx strategy is to focus its resources on creating new ICs
and development system software, on market development and creation of a diverse customer base across a
broad range of geographic and market-application segments. The company avoids the large capital commitment
and overhead burden associated with owning a waferfabrication facility by establishing a manufacturing alliance
with Seiko Epson who has manufactured all of the company's FPGA production wafers to date. In 1989, Xilinx
entered into an agreement with AT&T to provide additional
production capacity. Each of these manufacturers uses
the same proven CMOS processing used to manufacture
high-speed static RAMs (SRAMs). Using a standard
process is cost-effective and produces FPGAs with established reliability, and provides forearly access to advances
in CMOS technology.

Xilinx has maintained market leadership with a succession
of new products that have increased FPGA density
sevenfold, improved FPGA speed fivefold, and reduced
FPGA cost by a factor of fou r-all in less than three years.
Competitive pressures have forced manufacturers of electronic systems to bring increasingly complex products to
market rapidly. Requirements for improved functionality,
performance, reliability and lower cost are often
addressed through the integration of ever larger numbers
of transistors onto a single IC. In systems such.as
computers, telecommunications systems, medical diagnostic equipment and control systems, integration results
in faster speed, smaller size, lower power consumption
and lower costs. However, the length of time required to
develop these more sophisticated systems is often incom-

The company markets its products in North America
through a network of five .direct-sales offices, 65
manufacturers' rep locations and six distributors. Outside
North America, the company sells its products through
direct-sales offices in England, Germany and Japan and
through manufacturers' reps and distributors in 45 offices
in 20 countries.

1-1

II

1-2

Introduction to
Programmable Gate Arrays
Steady advances in the level of intergration in electronic
circuits have improved many equipment features, reducing
costs, power consumption, and system size, while
increasing performance and reliability. Increasing levels of
integration are most evident in microprocessor and
memory ICs. With each process generation, the
technology gap between these VLSI circuits and other
standard logic ICs has widened. To achieve comparable
densities for their proprietary logic functions, designers of
digital equipment have been forced to consider factoryprogrammed custom and semicustom Application Specific
Integrated Circuits (ASICs).

Field Programmable Gate Arrays (FPGAs), are highdensity ASICs that can be configured by the user. They
combine the logic integration benefits of custom VLSI with
the design, production, and time-to-market advantages of
standard products. Designers define the logic functions of
the circuit and revise these functions as necessary. Thus
FPGAs can be designed and verified in a few days, as
opposed to several weeks for custom gate arrays; FPGA
design changes can require as little as a few hours,
compared to several weeks for a custom array. This
results in significant cost savings by reducing the risks of
design changes, rescheduling, and eliminating nonrecurring engineering costs.

ASIC ALTERNATIVES
Application Specific ICs are the best solution for most logic functions.
The best ASIC solution depends on density requirements and production volumes.
20,000

STANDARD
CELL AND
CUSTOM

10,000

z

0

;::
()

z

5,000
FIELD PROGRAMMABLE
GATE ARRAYS

~

ill

1,000

I-

<
Cl

100
0
100

1,000

10,000

100,000

VOLUME/DESIGN

o

o

Field Programmable Gate Arrays

Unlike conventional gate arrays, FPGAs require no fixed
costs, and no custom factory fabrication. Since each device
is identical, manufacturing costs follow the same learning
curve as other high-volume standard product ICs.

•

1101 01

Standard Cell and Custom ICs

Standard cell and custom ICs require unique masks for all
layers used in manufacturing. This imposes extra costs
and delays for development, but results in the lowest
production costs for high volume applications. Standard
cell ICs offer the advantages of high level building blocks
and analog functions .

Programmable Logic Devices (PLDs)
"

PLDs are often used in place of five to ten SSI/MSI
devices, and are the most efficient ASIC solution for
densities upto a few hundred gates. Programmable Logic
Devices (PLDs) include a number of competing alternatives, all based on variations of AND-OR plane architectures. The primary limitations of the PLD architecture are
the number of flip-flops, the number of input/output signals, and the rigidity of the AND-OR plane logic and its
interconnections. The use of one fu nction often precludes
the use of many other similar functions.

Gate Arrays

Gate arrays implement user logic by interconnecting transistors or simple gates into more complex functions during
the last stages of the manufacturing process. Gate arrays
offer densities up to 100,000 gates or more, with utilization
of 80-90% for smaller devices, and 40-60% for the largest.
Unlike standard IC products, gate-array costs include fixed
costs as well as production cost per unit. Gate arrays
become cost effective when production volumes are high
enough to provide a broad base to amortize fixed costs:

1-3

II

Introduction to Programmable Gate Arrays

Programmable Gate Array Architecture

l::

Xilinx's proprietary Logic Cell™ Array (LCATM)
architecture is similar to that of other gate arrays,
with an interior matrix of logic blocks and a surrounding
ring of 1/0 interface blocks. Interconnect resources occupy
the channels between the rows and columns of logic
blocks, and between the logic blocks and the I/O blocks.

0

00

0
a

00
a

Like a microprocessor, the LCAdevice is a program-driven
logic device. The functions of the LCA configurable logic
blocks and I/O blocks, and their interconnection, are
controlled by a configuration program stored in an on-chip
memory. The configuration program is loaded automatically from an external memory on power-up or on command, or is programmed by a microprocessor as a part of
system initialization.

00
a

00
0

00

LCA performance is determined by the logic speed, storage elements, and programmable interconnect. It is
specified by the maximum toggle rate for a logic-block
storage element configured as a toggle flip-flop. For
typical applications, system clock rates are one-third to
one-half the maximum flip-flop toggle rate .

0

D
0
0

D
0

D
0

D

DOD

DO

a

0

D

a
Do

0

D

D
0

0

0

°

0

°a
°

Do

0

D
0

0

D

D

D

D
0

a

0

0

0

0

D

0

D
0

0

0
0

0

D

D

DO

0

0
0

0

0
0

0

0

D

D
0

0

D

D
0

0

0

0

0

D

D

0

D

D

0
0

0

0

DO

D

0

D

DOD

0

0

0

0

0

0

0

D

0

DO

0

0

0

D
0

0

D

0

0

00

0

0
0

0

o

0
0

0

0

a

0

0

0

a

00

0

D
0

DO

0

DOD

DO

0

DO

0

1101 02

.di

.8
.0

.d

.x

ax
COMBINATORIAL
FUNCTION

ClB OUTPUTS

.9

av

.y

.9C

.,. (ENABLE)----"1

.k

.rd
·0· (INHIBIT)----"1
(GLOBALRESET)-------'

1101 03

Configurable Logic Block
The core of the LCA device is a matrix of identical Configurable Logic Blocks (CLBs). Each CLB contains programmable combinatorial logic and storage registers. The
combinatorial logic section of the block is capable
of implementing any Boolean function of its input variables. The registers can be loaded from the combinatorial
logic or directly from a CLB input. The register outputs can
drive the combinatorial logic directly via an internal
feedback path.

1-4

Input/Output Block
The periphery of the LCA device is made up of user
programmable Input/Output Blocks (lOBs). Each block
can be programmed independently to be an input, an
output with 3-state control ora bidirectional pin. Inputs can
be programmed to recognize either TIL or CMOS thresholds. Each lOB also includes flip-flops that can be used to
buffer inputs and outputs.

3-sTATE_l-"--+----=:)IL.:>--i-,

(OUTPUT ENABLE)
OUT

-!-'---IL/

II
DIRECT IN . . . . . . , ; - - - - j - - - - - - ,
REGISTERED IN 4--';"':""---j---j

j}

PROGRAM
CONTROllED

o '"

MULTIPLEXER

PROGRAMMABLE INTERCONNECTION POINT or PIP

110501A

D
00
0

000 00 00
0
0

0

0

0
0

0
0
0

D

0
0

0

0

0

0

0

0

0

0

0
0

0

0

0

0

0
0

0

0
0

0

0

'"

0
0

0

0

0

0

0

0

0
0

0
0
0

0

0

0

0

0

0
0

0

0

0

0

0

0

0
1101 05

0
0

0

0

0

0
0

0

0

00

0

0
0

DO
0

Do
0

Do

Interconnect
The flexibility of the LCA device is due to the programmabie resources that control the interconnection of any
two points on the chip. Like other gate arrays, the LCA
interconnection resources include a two-layer metal network of lines that run horizontally and vertically in the rows
and columns between the CLBs. Programmable switches
connect the inputs and outputs of lOBs and CLBs to
nearby metal lines. Crosspoint switches and interchanges
at the intersections of rows and columns can switch
signals from one path to another. Long lines run the entire
length or breadth of the chip, bypassing interchanges to
provide distribution of critical signals with minimum delay
or skew.

0
0

0
0

0

0

0

0

0

0

0

0

000

000 000 00 0 000 00 0 00 0

1101 02

1-5

Introduction to Programmable Gate Arrays

XC2000
Programmable Logic Cell Array Family

The XC2000 series of LCA devices was introduced in 1985.
Price reductions since that time have reflected steadily
increasing production volumes. The family includes two
compatible arrays: the XC2064 with 1200 gates, and the
XC2018 with 1800 gates.

Features

o

Fully user-programmable:

• 1/0 Functions
• Logic and storage functions
• Interconnections

o

Three performance options: 50-,70- and 100-MHz
toggle rates

o

Three package types: Dual in-line package
Plastic leaded chip carrier
Pin grid array
TTL or CMOS input thresholds

o
THE XC2000 Family Members

XC2064
Equivalent Gates

XC2018

1200

Configurable Logic Blocks

100

Combinatorial Logic Functions

128

200

Latches and Flip-Flops

122

174

58

74

InputlOutputs

XC1736A and XC1765
CMOS Serial Configuration PROM
The Serial Configuration PROMs are companion devices that provide
permanent storage of LCA configuration programs. They can be used
whenever a dedicated device is preferable to sharing of a larger
EPROM, or to loading from a microprocessor.

Features

1800

64

o

One-Time Programmable (OTP) 36,288- or 65,536-bit serial
memory designed to store configuration programs for FPGAs

o
o

Simple interface to a Logic Cell Array requires only two 1/0 pins

o
o

Cascadable for large arrays or many LCA devices

o
o

Daisy-chain support for multiple devices
Storage of multiple configurations for a single LCA device
Low-power CMOS EPROM process
Space-efficient, low-cost 8-pin DIPs

1-6

XC3000
Logic Cell Array Family
The XC3000 series is a second generation family of
CMOS Logic Cell Arrays that includes five compatible
members with logic densities from 2000 to 9000 gates.

II

Features

0

Fully user-programmable:
• I/O Functions
• Logic and storage functions
• Interconnections

0

Five member product family
• 2000-9000 gates
• Compatibility for ease of design
migration

0 Programmable voltage slew rates on
outputs

Four performance options:
·50-,70-,100- and 125-MHz
toggle rates

0 Three package types:
• Plastic leaded chip carrier
• Pin grid array
• Quad flat package

0

0 Second generation architecture
• 5-input logic functions
• 2 flip-flops per CLB/IOB
• Enhanced routing resources
• 3-state drivers for wide ANDs

The XC3000 Family Members
XC3020

XC3030

XC3042

XC3064

XC3090

2000

3000

4200

6400

9000

Configurable Logic Blocks

64

100

144

224

320

Combinatorial Logic Functions

128

200

288

448

640

Latches and Flip-Flops

256

360

480

688

928

Input/Outputs

64

80

96

120

144

Equivalent Gates

1-7

Introduction to Programmable Gate Arrays

XC4000
Lagle Cell Array Family

achieve fully automated implementation of complex, highperformance designs. It is the first FPGA family to break
the 20,000-gate barrier; the first member of the XC4000
family will be sampled in late 1990.

The XC4000 series, the third-generation family of CMOS
LCA devices, combines architectural versatility, on-chip
RAM, increased speed and gate complexity with abundant
routing resources and new, sophisticated software, to

Features

0

Third generation user-programmable
gate array
Abundant Flip-Flops
Flexible function generators
On-chip fast RAM
Dedicated high-speed Carry
Propagation circuit
Fast, wide decoders
Unlimited number of logic levels
Hierarchy of interconnect lines
Intemal3-state bus capability

0

0

0

0
0

Flexible array architecture
Programmable I/O blocks
Programmable logic blocks
Programmable interconnects
Programmable wide decoders

··
··

Sub-micron CMOS process
High speed (toggle/shift rate
>100 MHz, counters >50 MHz)
• Low power consumption
Systems-oriented features
Slew-rate limited outputs
Programmable input pull-up or pulldown resistors
Configured by loading binary file
Unlimited reprogrammability
Six programming modes
Development system runs on '386based PC and on many popular
workstations
Fully automatic placement and
routing plus optional interactive
enhancements

·

··
··
·

XC4000 Family Members

XC4002

4003

4004

4005

4006

4008

4010

4013

4016

4020

Appr. Gate Count

2,000

3,000

4,000

5,000

6,000

8,000

10,000

13,000

16,000

20,000

CLB Matrix

8x8

10 x 10

12 x 12

14 x 14

16 x 16

24 x 24 26 x 26

30 x 30

64

100

144

196

256

Configurable Logic Blocks
Max RAM Bits
InpuVOutpts

18 x 18 20 x 20
324

400

576

676

900

18,432

21,632

28,800

192

208

240

2,048

3,200

4,608

6,272

8,192

10,368

12,800

64

80

96

112

128

144

160

The XC4000 family of Logic Cell Arrays is not covered in this Data Book.

Ask for the separate XC4000 Product Description.

1-8

Development Systems
Designing with Xilinx FPGAs is similar to designing with other gate arrays.
Designers can use familiar CAE tools for design entry and simulation. The
open Xilinx development system includes a standard netlist format, the Xilinx
Netlist File (XNF), that provides a bridge between schematic editors or
simulators, and the XACT software for design implementation and real time
design verification. The Xilinx software is supported on the PC/AT and
compatibles as well as on popular engineering workstations.

III

Step 1
DS371
DESIGN
ENTRY

Design Entry Software
consists of libraries and netlist interfaces
for standard CAE software such as
FutureNet, Schema, OrCAD, VIEWlogic,
Mentor, Valid, CASE, and PALASM. Programmable gate array libraries permit
design entry with standard TTL functions,
with Boolean equations, and with userdefined macros.

LOGIC REDUCTION
PARTITIONING AND
OPTIMIZATION
PLACE AND ROUTE

Simulation Software

Step 2
DESIGN
IMPLEMENTATION

includes models and netlist interfaces to
standard simulator software, such as
SILOS and CADAT, that is used for logic
and timing simulations.

Design Implementation Software

DESIGN EDITOR
TIMING CALCULATOR
DOWNLOAD CABLE
BrrSTREAM GENERATOR

is used to convert schematic netlists and
Boolean equations into efficient designs
for programmable gate arrays. The software includes programs that perform partitioning, optimization, placement and
routing, and interactive design editing.

Step 3
DESIGN
VERIFICATION

E:X1llNX
XC3020·70
PC68C
X9201MB730

In-circuit Design Verification Tools

X1765

1-9

permit real-time verification and
debugging of a programmable gate array
design as soon as it is placed and routed.
Designers benefit from faster and more
comprehensive design verification, and
from reduced requirements to generate
simulation vectors to exercise a design.

Introduction to Programmable Gate Arrays

o
o
o
o
o

Technical Support
SOFTWARE UPDATES

Xilinx is continuing to improve the XACT development
system software, and new versions are released two or
three times per year. Updates are provided free of charge
during the first year after purchase, provided the user
returns the registration card. After the first year, users are
encouraged to purchase a Software Maintenance Agreement to continue to receive software updates.

Read files from the bulletin board
Check current software version numbers
Download files
Upload files
Leave messages for other bulletin-board users.

TECHNICAL LITERATURE

In addition to this databook, technical literature for the
Xilinx programmable gate array includes four volumes that
are delivered with every XACT development system.

TRAINING COURSES

To get up-to-speed quickly, new Xilinx users are invited to
attend comprehensive training classes. These classes
are taught by factory experts and include the latest software and hardware advances.

o

User's Guide
The User's Guide is a collection of "how to" applications
notes on such subjects as getting started with an LCA
design, Boolean equation design entry, use of the
simulator, placement and routing optimization, and
LCA configuration.

o

Reference Manuals (2 vols)
The XACT Reference Manuals include a detailed description of each Xilinx software program.

o

Macro library
The Xilinx development system includes over 100
macros, including counters, registers, and multiplexers. The macro library manual includes schematics
and documentation for each macro.

XILINX USER GROUPS

Xilinx users are invited to attend training and information
exchange sessions that are held two-to-three times per
year in various locations worldwide. These User Group
meetings are intended for experienced users of Xilinx
Programmable Gate Arrays, and they emphasize the
efficient use of the XACT development system.
FIELD APPLICATIONS
ENGINEERS

Xilinx provides local technical support to customers
through a network of Field Applications Engineers (FAEs).
For the name and phone number of the nearest FAE,
customers may call one of the Xilinx sales offices listed in
the back of this book.
APPLICATIONS HOT LINE

Xilinx maintains an applications hot line to provide technical support to LCA users. This service is available from
7:30 amto 6:00 pm Pacific Time. Call (408) 879-5199 or
(800) 255-7778 and ask for Applications Engineering.
BULLETIN BOARD

To provide customers with up-to-date information and an
immediate response to questions, Xilinx provides 24-hour
access to an electronic bulletin board. The Xilinx Technical bulletin board provides the following services to all
registered XACT development-system customers.

HO

A Cost of Ownership
Comparison

CONTENTS
Executive Summary
ROM vs EPROM Analogy
Who Recognizes the Costs?
Total Cost = Fixed Cost + (Variable Cost) (Units)
Fixed Development Costs for Gate Arrays
Simulation
Time to Design For Testability
NRECharges
Design Iterations
Test Program Development
Second Source
Summary of Fixed Development Costs

Field Programmable
Gate Arrays (FPGAs)

Gate Arrays

Standard product
Off-the-Shelf delivery
Fast time to market
Programmed by the user
NoNRE
No inventory risk
Fully factory tested
Simulation useful
In-circuit design verification
Design changes anytime
Second source exists

Custom product
Months to manufacture
Manufacturing delays
Programmed in the factory
NRECosts
Design specific
User develops test
Simulation critical
Not possible
NRE charge repeated
Additional cost and time

Variable Costs
Unit Cost (Cents/Gate)
Inventory

looks at the various categories of costs, both fixed and
variable, for devices from 2000 to 9000 gates, 80% of the
gate-array market according to most studies.

Yield to Production
Cost Of Ownership Analysis
Break-even Analysis
Time to Market
Product Life Cycles
References

Because the gate array has fixed or up-front development
costs (NRE, extra simulation time, generating test vectors,
etc.) that the FPGA does not, its total cost of ownership is
higher until a sufficient quantity is purchased. This analysis allows the user to calculate total cost of ownership at
different quantities and derive break-even quantities the volume below which it is more cost effective to use the
FPGA (Break-even Analysis section). The overall objective is to determine the production volumes at which each
product is most cost effective.

EXECUTIVE SUMMARY
Introduction
Custom or mask-programmed gate arrays have many
hidden costs beyond the obvious unit cost and NRE (nonrecurring engineering) charges. Most of these additional
costs are due to the fact that a gate array is a custom
integrated circuit, one manufactured exclusively for a
particular customer. Compared to a standard product,
there are many hidden expenses, both during the design
phase and after purchase, beyond the direct device cost.

Conclusion
The choice between FPGA- and mask-programmed gate
arrays must take into account more than the NRE and
cents/gate unit cost. The use of a custom product entails
many other costs and risks. Because of these fixed costs,
it is less expensive at lower volumes to use a standard
product: an FPGA. Since many of the hidden costs of
using a custom gate array do not accrue to anyone
department, only the project manager can recognize the
total cost.

Field-programmable gate arrays (FPGAs), on the other
hand, are high-volume standard products-manufactured
and fully tested devices that are used by all customers.
There is no customizalion of the silicon.

Similar considerations have led to the widespread acceptance of EPROM memories as compared to ROMs, despite a higher EPROM cost per unit. The same factors can
be applied in the choice of a gate array.

Methodology
This analysis compares the total costs of custom gate
arrays with those of field-programmable gate arrays. It

1-11

II

A Cost of Ownership Comparison

Figure 1 shows a representative break-even graph for a
2000-gate device using 1990 data. The vertical axis
shows the total project cost-fixed costs plus unit costs
multiplied by the number of units. At lower volumes, the
custom gate array is more expensive because of fixed
costs that are incurred even if no units are purchased. The
FPGA project cost starts at zero, but rises faster because
of a higher cost per-unit. In this case the break-even
volume is between 10k and 20k units. The various
components of this analysis are discussed in the following
sections. Also, guidelines are given to help the user make
a simple calculation for a specific solution.

Several significant factors are omitted from Figure 1. First,
the additional fixed costs (NRE, simulation) of bringing on
a custom-gate-array second source are not included.
Second, and much more important, the cost of the longer
time to market when designing with the mask gate array is
not included. This factor is reviewed in the Time to Market
section. Both of these factors would raise the custom gate
array curve and increase the break-even quantity. In other
words, the FPGA would be more cost effective at an even
higher production volume.
ROM VS EPROM ANALOGY
There is a relevant historical precedent for the use of a
flexible standard product instead of a custom product with
a lower direct cost per unit. While EPROMs have a cost per
bit that is two to three times that of ROMs, they have
consistently captured almost half the programmable
memory market, measured in bits shipped. See Figure 2.
Many of the reasons for the use of EPROMs are the same
as those for the use of programmable gate arrays: faster
time to market, lower inventory risks, easy design
changes, faster delivery, and second sources. The higher
price per bit is offset by the elimination of inventory and
production risks.

TOTAL
PROJECT
COST ($)

~~J5~~~~

NRE
SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERATIONS

I

Gate arrays have even more disadvantages versus programmable gate arrays than do ROMs versus EPROMs.
The upfront design time, risk, and expense of ROMs is
minimal, while that of gate arrays is substantial. ROM test
tape generation is automatic, while that for gate arrays
requires extensive engineering effort. Therefore, FPGAs
may be even more widely used versus gate arrays than are
EPROMs versus ROMs.

~--------~----------~
10k

20k

PRQJECT UNITS

-

CUSTOM GATE ARRAY

1102 01A

-FPGA

Figure 1. Typical Break-even Analysis 2000 Gates-1990

140
120
100

TERABITS
SHIPPED

80

•

ROM

[l) EPROM

60
40
20
0
1983

1984

1985

1986

1987

1988

1989

EPROM MIL¢/BIT 10.9
ROM MIL¢iBIT 4.5

9.2
3.2

4.0
1.7

2.5
1.0

1.8
0.7

1.3
0.5

0.9
0.4

2.9

2.4

2.5

2.6

2.6

RATIO

2.4

2.3
SOURCE: DATAQUEST

Figure 2. ROM/EPROM Analogy

1-12

110205

WHO RECOGNIZES THE COSTS?

explicitly for computer time, an estimate would be $2,500
and 2.5 man weeks of simulation effort for a 2000-gate
array, and $5,000 and seven man weeks for a 9000-gate
array. This compares to 0.5 and 1 week forthe FPGA, with
no Simulation charge.

Many of the elements of the total cost of ownership for a
gate array do not accrue to a single department, and often
are not fully recognized. For example, the additional
engineering time needed to design for testability may not
be seen by purchasing. The inventory costs of a custom
product may not be recognized by the design department.
However, these are real costs, and they influence the
profitability of the product and company. The. person
making the choice between custom gate arrays and
FPGAs should consider the total costs of ownership for
each alternative.

Typically one fully burdened man week, including
computer support, costs about $2000.
2000 Gates

9000 Gates

$2.Sk
2.SMW

$Sk
7MW

None
O.SMW

lMW

Gate Array
Simulation Charge
Man Weeks

TOTAL COST = FIXED COST +
(VARIABLE COST)(UNITS)

FPGA

The total costs of using a product can be separated into
two components. The first is the fixed costs: up-front development costs that are independent of volume. Some
examples of these for gate arrays are the masking charge,
simulation charge, and test program development. Due to
amortization of these costs, the user's cost per unit can be
very high until a sufficient volume of units is purchased.
The second component of total cost is the variable cost,
the incremental cost per unit. Besides the obvious unit
cost, another element of variable cost is inventory cost.

Simulation Charge
Man Weeks

None

Time to Design for Testability
One key to getting a successful gate array the firsttime is to
focus on testing issues. The user must guarantee that the
device can be fully tested in a reasonable amount of time.
Since the gate array vendor's only guarantee is that the
device will pass the test program, the user must be certain
that if the Ie meets the user-generated test specifications,
it will work in the Circuit.

This analysis will examine costs by these two categories.
Fixed costs are summarized first, then variable costs.
They are added to produce total cost.

Spending extra time in the design phase provides insurance that the device can be tested. A Dataquest ASIC
Market Report observes that "an engineer can sit down at a
$20,000 CAE/CAD station and design a $1,000,000 test
problem." Designing in testability may also be the only way
to provide for testing of complex sequential circuitry, or
elements like long counters. Therefore the gate array designer must spend additional time in the design phase. An
estimate is one additional week for a 2000-gate array, and
two additional weeks for a 9000-gate array.

FIXED DEVELOPMENT COSTS
Simulation
With a custom product, it is critical that the device work the
first time. Otherwise, the user must pay to have the device
prototyped a second time and will incur the manufacturing
delay a second time. Custom gate arrays do not support a
conventional, iterative, modular design process-the
design is all-or-nothing. Simulation is a useful tool with
FPGAs, but it is a critical one with gate arrays, and the
designer can expect to spend more time simulating a
custom gate array design. The programmable gate array
designer can count on in-circuit verification and on-line
changes if necessary.

The FPGA is a standard product with no incremental test
costs. It is fully tested by Xilinx before Shipment. No application-specific testing is needed.
Gate Array Incremental Cost

Gate array simulation cost includes both computer time
charges and the time of the engineer doing the simulation.
While the gate-array vendor mayor may not charge

1-13

2000 Gates

9000 Gates

1 Man Week

2 Man Weeks

II

A Cost of Ownership Comparison
NRECharges

Test Program Development

NRE (Non-Recurring Engineering) charges cover the online vendor interface, design verification, mask charges,
prototype samples and a nominal simulation (pre- and
post-layout) time. The charges may vary with estimated
production volumes. At volumes below 50,000 units,
$10,000 to $20,000 is a competitive quote for lower density
gate arrays. Atthe 9000-gate level, NRE charges may be
in excess of $30,000.

As noted in the Time to Design for Testability section, testability is critical to production success for gate arrays.
Gate-array vendors rarely make production errors, but
faulty devices may not be detected because the test vectors are not comprehensive.
The estimate for test -vector deve lopment is two weeks for
a 2000-gate array, and four weeks for a 9000-gate array.
Since the FPGA is a standard product, it is fully tested at
the factory. No application-specific testing is needed.

There are no NRE charges for programmable gate arrays.
The entire design process is done by the customer. FPGA
software tools run on common workstations and personal
computers, and are much less expensive than comparable tools for custom gate arrays.

A risk that the program manager should consider involves
the level of experience or knowledge that the design team
has with test development. If the first-pass design is unsuccessful, how much time and effort will be required to
debug the problem? Both additional cost and time to market are at risk.

Typical Gate Array NRE for 10,000 to 50,000 units
2000 Gates

9000 Gates

$10k-$20k

$20 k-$40k

Gate Array Incremental Cost
2000 Gates
2 Man Weeks

Design Iterations
The phrase "We need to add this feature" is all too common to the designer of electronic equipment. Designers
often find themselves faced with the need to modify a
design during prototyping or initial customer evaluation. Changes may be required to add features or reduce
costs. As systems become more complex, "bugs" can be
more prevalent.

4 Man Weeks

Second Source
If a second source is required, the gate-array designer
must identify a compatible vendor and resubmit the design. This involves another NRE charge and time for
translating logic and resimulation. The model used here is
the NRE charge plus one half the simulation cost.

Design iterations are almost never due to the failure of
the gate-array vendor. Rather, there are risks associated
with the choice of an inflexible technology in a very
dynamic industry.

Field-programmable gate arrays are standard products
that already have a second source.
Gate Array Incremental Cost'"

Industry data suggest that about half of all gate-array designs are modified before they are released to production.
When a modification is required, NRE costs are incurred
forthe second pass. Since resimulation is likely to involve
less effort than the initial simulation, 25% (50% probability
times one half the effort) of the simulation cost is added.

NRE
Simulation
Charge
Man Weeks

Gate Array Incremental Cost
50%
Probability

9000 Gates

2000 Gates

9000 Gates

$10k-$20k

$20 k-$40 k

$1.25k
1MW

$2.5k
3MW

Summary of Gate Array Fixed DevelopmentCosts

(original NRE time and cost + one half of
original simulation time and cost)

The summary in Table 1 shows typical fixed costs for both
a 2000-gate and a 9000-gate array. Since assumptions
may vary, a blank column is provided as a worksheet.

1-14

1. Simulation
NRE
Man Weeks
2. Design for Testability
3. NRE Charges
4. Design Iterations @ 50% probability
NRE
Man Weeks
5. Test Program Development
6. Second Source (NRE + 50% SIM)
NRE
Man Weeks

Total Without Second Source
NRE
Man Weeks
Total With Second Source
NRE
Man Weeks
Total Fixed Costs@ $2 klMW
Without Second Source
With Second Source

Typical
2000 Gates

Typical
9000 Gates

$2,500
2MW
1MW
$10 k-$20 k

$5,000
7MW
2MW
$20 k-$40 k

$8,125
0.5MW
2MW

$16,250
1.5MW
4MW

$16,250
lMW

$32,500
3MW

$25,625
5.5MW

$51,250
14.5MW

$41,875
6.5MW

$83,750
17.5MW

$36,265
$54,875

$80,250
$118,750

Customer
Application

II

@$

IMW

Table 1. Typical Fixed Costs

while gate arrays are in a more mature phase of the cycle.
Price comparisions should be based on projections over
the production life of the product.

V ARIABLE COSTS

Production Unit Cost (Cents/Gate)
Gate-array prices are often quoted in terms of cents per
gate. For 1.2 micron, 2000-gate arrays, at the volumes
considered in this analysis (10,000 to 30,000 units), a
figure of 0.15 . - 0.20 centslgate (without package) is
typical. At similar volumes, the cost per gate (without
package) for an FPGA is two to three times the cost of a
custom gate array. For reasons explained below, this gap
is expected to narrow over the next few years. All of the
centslgate numbers are for die only. Since CMOS gate
arrays and FPGAs use the same packages, the package
adders are equivalent.

A standard product has more silicon content and less factory overhead than a custom product. Since all customers
buy the same product, there is more of the semiconductor
learning curve with cumulative volume. Given the profitability levels of array manufacturers, gate array prices may
decline only slightly over time and could even rise.
1991 FPGA Unit CostsWithout Package

An important consideration in calculating the total cost of
ownership is the year during which most of the production
volume will be purchased. Since FPGAs are newer
products, their cost is declining at a steeper rate than gate
arrays. They are in the introduction phase of the life cycle,

Programmable
(Cents/Gate)

1-15

2000
Gates

4000
Gates

9000
Gates

20kQty
0.30-0.40

10kQty
0.40-0.50

10kQty
0.50-0.60

A Cost of Ownership Comparison

volume applications, few gate arrays are retooled to take
advantage of process advances. The time from design
start to end of production lifetime is usually several years.
Overthis period, the FPGAwill move to successively more
advanced processes, resulting in steadily decreasing
costs. By the end of the production lifetime, the FPGA will
be several processes ahead and the cost difference will be
reduced significantly.

Process Technology

There are also technology reasons for the steeper decline
in FPGA cost. Figure 3 shows that the processes used for
logic ICs, including gate arrays, typically lag behind those
used for memory ICs. Since the FPGA is a standard IC
built on a memory process, it can take advantage of each
new process to shrink the die and reduce costs.
With a conventional gate array, the process that is available at the time of design is usually used throughout the
production lifetime of the product. Except for very high-

YEAR

Pad-Limited Ole Sizes

As gate arrays and FPGAs grow in liD pin count, a phenomenon known as "pad-limiting" is more likely to occur.
The spacing between I/O pads is determined by mechanical limitations of the equipment used for lead bonding. In
I/O-intensive applications the number of pads around the
outer edge ofthe die determines the die size, instead of the
number of gates. See Figure 4. In I/O-intensive applications, a "cost per I/O" may be a more useful measure than
"cost per gate."
For a given I/O count, in the pad-limited case the FPGA
and the gate array would be the same die size. As a result,
the higher volume, standard product, FPGAcouid actually
be less expensive on a per-unit basis than the customproduct gate array. There would be no break-even quantity - the FPGA would have a lower cost of ownership at
all volumes.

1102 02

Figure 3. Process Evolution

PAD-LIMITED DIE

350

000000000000000

300

o
o
o
o
o
o
o
o
o
o
o
o
o

250
DIE 200
WIDTH
MILS 150

100
50
0
40

0
0
0
0
0
0
0
0
0
0
0
0
0

000000000000000
60

80

100

120

140

160

180

NUMBER OF PADS

Figure 4. Minimum Ole Size vs 1/0

1-16

1102 03A

Effect of Die Cost on Total Cost

mum economical wafer-lot quantity. Inventory is created
and costs are incurred. Moreover, there is the problem of
inventory ownership if the parts are never ordered by the
customer.

Figure 5 illustrates a third point about the capability of FPGAs to narrow the cost difference with custom gate arrays.
The chart shows the contribution to total device cost of
wafer, die, assembly and test. Wafer cost represents
about 20% to 40% of the total device cost, and die cost
about 30% to 50%. A 50% difference in die cost - between
a gate array and a FPGA - shown in the chart translates to
only a 20% difference (80 vs 100) in total cost by the time
the device has been tested. This comparison is based on
production of the FPGA in a more advanced process than
the custom gate array, as discussed in the Unit Cost
(Cents/Gate) section.

Althoughthe safety stock reserve is a function olthe cost of
the product itself, a figure of 10% is reasonable for gate
arrays that have unit costs under $25.00. In comparison,
since changes to FPGAs can be. made in software in minutes, and since only one part type is widely stocked, the
comparative safety stock reserve is 0%.
Gate Array Incremental Inventory Cost
10% Additional Unit Cost

Inventory Reserves
Inventories include extra devices ordered and stocked to
cover contingencies. For acustom product, this is the only
way parts can be delivered in less than the normal production time (2-4 months). Contingencies are often thought of
in terms of negative events like a defective lot or manufacturing shortfalls.

YIELD TO PRODUCTION
Due to rapidly changing markets, many designs never go
into production. Sometimes a company will develop competing projects, with only one moving to production. Many
times the market will change, or competition will emerge,
and projects will be cancelled or redirected. Of course
each design team expects that its project will succeed, but
in the aggregate this is not true. If a company chooses gate
arrays as the primary logic technology, and starts many
designs, this factor will occur.

However, contingencies also include positive events like
stocking for large, upside orders orwhere demand is difficult to estimate. This can be especially true during a
product's introduction, when design changes and demand
spikes occur simultaneously.

According to Dataquest ASIC and Standard Logic Semiconductor Volume 1,only 50% of gate-array designs go
into production. Therefore, the true cost of the gate array
should recognize additional costs for simulation, designing for testability, and NRE. For 2000 gates, using the
numbers in the Summary of Fixed Development Costs
section, this would mean an additional ($2,500 + 3 MW +
$15,000). For 9000 gates the number is ($5,000 + 8 MW +
$30,000).

With a custom product it is also necessary to build inventory as the product nears the end of its life cycle. Demand
is low and difficult to forecast, and it may not be possible
to reorder a small quantity. Spares and replacements
must be stocked. A JIT(just in time) inventory system is
less practical.
Since minimum manufacturing quantities for semiconductors are determined by wafer lots, a custom product will
have excess WIP (work in process) or finished goods inventory if the desired order quantity is less than the mini-

100



~

...J

40

W

c:
20
0
WAFER

DIE

ASSEMBLY

TEST

Figure 5. Relative Manufacturing Cost by Stage of Completion

1-17

1102 04A

II

A Cost of Ownership Comparison

Table 2 is a form that can be used for calculating the total
cost of ownership at various volumes. Table 2 pOints to the
"break-even quantity"-the quantity where the unit cost of
the two devices is the same--of the next section.

COST OF OWNERSHIP ANALYSIS

While gate arrays have a lower unit cost, they have incremental fixed costs that must be incurred before the first unit
is received. Example costs are shown in Table 1 (Summary of Fixed Development Costs). Therefore, at lower
unit volumes the FPGA is less expensive, until the gate
array can amortize the up-front fixed costs.

Project Quantity

1,000

5,000

Gate Array-No second source
1. Fixed costs from Table 1
2. Unn cost
3. Inventory reserves: (Line 2)(1.1)
4. Total variable cost

~

(Line 3)(Oty)

5. Total cost = Line 1 + Line 4
6. Unit cost = Line Slaty

Gate Array-second source
7. Fixed costs from Table 1
8. Second source costs
9. Total fixed costs
10. Total variable cost-Line 4 above
11. Total cost = Line 9 + Line 10
12. Unit cost = Line 11/0ty

Field Programmable Gate Array
13. Unit cost

Table 2. Total Cost vs Volume Purchased

1-18

10,000

20,000

BREAK EVEN ANALYSIS

At the 2,000 gate level, assume the gate array is used in a
$2,000 product that has 15% profit margins. For 10,000
units sold:

Figure 6 is a graphic representation of the break-even
calculation for the case of 2000 gates, 1990 pricing, and
no second source. Up to the break-even unit volume,
the programmable gate array solution has a lower total
project cost.

Lost Profit = $2,000 x 10,OOOx 15%x 113= $1.0 million or
$100 per device
At the 9000 gate level, assume the gate array is used in a
$10,000 product that has 20% profit margins. For 2000
units sold:

Similar graphs can be built for different assumptions
by filling in Table 1. For the gate array, the break-even
graph is merely line 5 or line 11 plotted versus quantity.
For the FPGA it is line 13 times the quantity plotted
versus the quantity.

Lost Profit =$10,000 x 2,000 x 20% x 113 = $1.33 million or
$667 per device
Note that these catastrophic costs are not included in any
of the previous sections. They are a quantitative estimate
of the risk of using a custom product.

TOTAL
PROJECT
COST ($)

PRODUCT LIFE CYCLES
Throughout the electronics industry, the product lifetimes
are shrinking. In the personal computer industry, it is not
uncommon to find product upgrades within 6 t012 months.
This means that the volumes associated with anyone
gate- array design can be much smaller than anticipated,
even if the end product still exists. It also means that it is
critical to achieve a rapid design time.

~:~6~~~~~ }

NRE
SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERAT10NS

~----------~----------~
10k

20 k

PROJECT UN 1TS

Figure 6 shows that 2000-gate FPGAs are more economical at volumes up to 10,000 to 20,000 units. These volumes will represent an increasing number of products.

- - - CUSTOM GATE ARRAY
- - FPGA
110205

REFERENCES
Figure 6. Typical Break-even Analysis 2000 Gates-1990

1. Technology Research Group Letter, March 1986,
page 7.
2. Dataquest Inc., Gate Arrays-Product AnalYSiS,
page 3, ASIC and Standard Logic Semiconductors,
1987.

TIME TO MARKET
There are numerous examples of products that failed due
to late market entry. A study by McKinsey &Co. stated that
a product that is six months late to market will miss out on
1/3 of the potential profit over the product lifetime. If there
is any problem in simulation, or any iteration of the gate
array design, a gate array would easily add six months to a
product schedule.

3. Reinertsen, Donald G.,"Whodunit? The Search forthe
New-Product Killers," Electronic Business, July 1983,
pages 62-66.
4. Integrated Circuit Engineering Corp., ASIC Outlook,
1987.

1-19

II

The Programmable Gate Array Company

1-20

SECTION 2
Product Specifications

1

2

Programmable Gate Arrays

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Product Specifications

XC3000 Logic Cell Array Family
Features, Description, Architecture ............................................... 2-1
Programmable Interconnect .......................................................... 2-7
Crystal Oscillator ............................................................................ 2-13
Programming ................................................................................. 2-14
Special Configuration Functions .................................................... 2-21
Performance .................................................................................. 2-24
Power ............................................................................................. 2-27

Pin Descriptions ............................................................................. 2-29
Pin Assignments ............................................................................ 2-32
Electrical Parameters ..................................................................... 2-40
PGA Pinouts and Physical Dimensions ......................................... 2-51
Component Selection and Ordering Information ........................... 2-60
XC2064, XC2018 Logic Cell Arrays
Features, Description, Architecture ............................................... 2-61
Programmable Interconnect .......................................................... 2-66
Crystal Oscillator ............................................................................ 2-68
Power ............................................................................................. 2-70
Programming ................................................................................. 2-72
Special Configuration Functions .................................................... 2-78
Performance .................................................................................. 2-78

Development Systems ................................................................... 2-84
Pin Descriptions ............................................................................. 2-84
Pin Assignments ............................................................................ 2-86
Electrical Parameters ..................................................................... 2-88
Component Selection, Ordering Information,
Physical Dimensions ................................................................ 2-98
Military Logic Cell Arrays
Introduction ... ................................................................................. 2-103
XC2018B ....................................................................................... 2-107
XC3020B ....................................................................................... 2-119
XC3042B ....................................................................................... 2-137
XC3090B ....................................................................................... 2-157
Serial Configuration PROM
XC1736NXC1765 Features, Descriptions .................................... 2-175
Electrical Parameters ... .................................................................. 2-179
Serial-PROM-Programming Support ............................................. 2-184
Physical Dimensions, Ordering Information ................................... 2-185
Sockets ............................................................................................... 2-187

XC3000
Logic Cell™ Array Family
Product Specification
FEATURES

The LCA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded
in any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk.
On-chip
initialization logic provides for optional automatic loading
of program data at power-up. Xilinx's companion XC1736
Serial Configuration PROM provides a very simple serial
configuration program storage in a one-time
programmable 8-pin DIP.

• High Performance-70-, 100- and 125-MHz Toggle
Rates
• Second Generation Field-Programmable Gate Array
• 110 functions
• Digital logic functions
• Interconnections
• Flexible array architecture
• Compatible arrays, 2000 to 9000 gate
logic complexity
• Extensive register and I/O capabilities
• High fan-out signal distribution
• Internal 3-state bus capabilities
• TIL or CMOS input thresholds
• On-chip oscillator amplifier
• Standard product availability
• Low-power, CMOS, static-memory technology
• Performance equivalent to TIL SSI/MSI
• 100% factory pre-tested
• Selectable configuration modes
• Complete XACT'"M development system
• Schematic Capture
• Automatic Place/Route
• Logic and Timing Simulation
• Design Editor
• Library and User Macros
• Timing Calculator
• XACTOR In-Circuit Verifier
• Standard PROM File Interface

Basic
Array

Logic
Capacity
( gates)

XC3020
XC3030
XC3042
XC3064
XC3090

2000
3000
4200
6400
9000

Conflgurable
Logic
Blocks

64
100
144
224
320

Max
User
1I0s

No. Program
of
Data
Pads (bits)

64
80
96
120
144

74
98
118
140
166

14,779
22,176
30,784
46,064
64,160

The XC3000 Logic Cell Arrays are an enhanced family of
Field Programmable Gate Arrays that provide a variety of
logic capacities, package styles, temperature ranges and
speed grades.

DESCRIPTION
ARCHITECTURE

The CMOS XC3000 Logic CeWM Array (LCNM) family
provides a group of high-performance, high-density,
digital integrated circuits. Their regular, extendable,
flexible, user-programmable array architecture is
composed ·of a configuration program store plus three
types of configurable elements: a perimeter Of lOBs, a core
array of CLBs and resources for interconnection. The
general structure of an LCA device is shown in Figure 1 on
the next page. The XACT development system provides
schematic capture and auto place-and-route for design
entry. Logic and timing Simulation, and in-circuit emulation
are available as deSign verification alternatives. The
design editor is used for interactive design optimization,
and to compile the data pattem that represents the
configuration program.

The perimeter of configurable I/O Blocks (lOBs) provides
a programmable interface between the internal logic array
and the device package pins. The array of Configurable
Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks,
analogous to printed circuit board traces connecting
MSI/SSI packages.
The blocks' logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with
metal segments joined by program-controlled pass tran-

2-1

•

XC3000 Logic Cell Array Family

sistors. These LCA functions are established by a configuration program which is loaded into an internal, distributed
array of configuration memory cells. The configuration
program is loaded into the LCA device at power-up and
may be reloaded on command. The Logic Cell Array
includes logic and control signals to implement automatic
or passive configuration. Program data may be either bit
serial or byte parallel. The XACT development system
generates the configuration program bitstream used to
configure the Logic Cell Array. The memory loading
process is independent of the user logic functions.

and only read during readback. During normal operation,
the cell provides continuous control and the pass transistor
is "off" and does not affect cell stability. This is quite
different from the operation of conventional memory devices, in which the cells are frequently read and re-written.
The memory cell outputs Q and Q use ground and Vcc
levels and provide continuous, direct control. The additional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory

Configuration Memory

";':';':':':':':':':':':':':':':':':':':':'::':':';::

....-----;::.- Q

The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
configuration memory based on this design is assured
even under adverse conditions. Compared with other
programming alternatives, static memory provides the
best combination of high density, high performance, high
reliability and comprehensive testability. As shown in
Figure 2, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration

JJ

Y-

CONFIGURATION
L"OCONTROL
:::

1105 12

Figure 2. Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.

3·STATE BUFFERS WITH ACCESS
TO HORIZONTAL LONG LINES

CONFIGURABLE LOGIC
BLOCKS

y-~y-

~

o
Y-

0

y-

.}.-

U

U
JJ

Y-

O

0

Y-

II:
W

IZ

Y-

Y-

a
0w

::2:

RD

G

.a

-iaXL

F......--+...-t-------l-+--r-t----rl:jr .X

ax

L

--+--"':~'-----lCOMBINATORIAL
FUNCTION

LOGIC
VARIABLES.d

.e

II

,--

r--------r----~~O

CLB OUTPUTS

GH-+-_+....-Bt-~I-N---,__----1-+-_---J-H~-y

ay

L-----1G

~

0

MUX-

T

r--1

'-----r___,
I

ENABLECLOCK-+~·e~c-------------~I

"1" (ENABLE)

----~LJ

D

a

>RD

--

CLOCK-+~·k----------~l ~r------~
L~

RESET_+-~.m~_ _ _ _ _ _ _ _ _ _ _ _ _

DIRECT

_1r---,
I

"0"

(INHIBIT)

I

------tUr--r=v---'J)--J-----J

(GLOBAL RESET)
110502A

Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section,
two flip-flops and a program memory controlled multiplexer selection of function.
It has: five logic variable inputs .a, .b, .c, .d and .e.
a direct data in .di
an enable clock .ec
a clock (invertible) .k
an asynchronous reset .rd
two outputs .X and .y

2-5

XC3000 Logic Cell Array Family

:._"""---.'-----"""'.""-'-"--".-------"j

r'''·''''''''''''''''·''''''-''~''''·-······W.'.'.W.'.~W-''W.W'''.-''---1

:1

0'

:~
:i~
;

c _!

'*,~I"

I '.I&"II!~:M-==llr=rr~I~~~~~t}-----tj-rb~~~AL
I
oo,,'~ ~"AA_' I
I
H--H";---~-IL/
~ c;-J
OWOK -

-~~o,

r-OO

G

OFUPT04
VARIABLES

D~

'DO

J

~

~

~

E-i

l.w"'.~"."'w,,,,.''''.''''''__'''''''''''w.'.w'''''w.'.w.''''.''''.''w.""w.w..",,,~~.J

FG

FG

MODE

MODE

F
ANY FUNCTION
OF 5 VARIABLES

Dl

~~'ll-OI
,
r,
!

G

~

!

l"y,,~~~,,~~~~.~_~~.:~~~I~.~~'~~m.m)

5b

F
MODE

-02
D2

-

FUNCTION OF 6 VARIABLES

FGM
MODE
1105 03A

Figure 6. C8BCP Macro. TheC8BCP macro (moduI0-8
binary counter with parallel enable and clock enable) uses
one combinatorial logic block of each option.

Figure 5
Sa. Combinatorial Logic Option FG generates two functions of
four variables each. One variable, A, must be common to
both functions. The second and third variable can be any
choice of of B, C, ax and Oy. The fourth variable can be
any choice of 0 or E.
5b. Combinatorial Logic Option F generates any function of five
variables: A, 0, E and and two choices out of B, C, ax, Qy.
5c. Combinatorial Logic Option FGM allows variable E to select
between two functions of four variables: Both have common
inputs Aand Dand any choice out of B, C, ax and Oyforthe
remaining two variables. Option 3 can then implement some
functions of six or seven variables.

2-6

(as are block outputs) they are usable only for block
input connection and not routing. Figure 8 illustrates

reset by the active Low chip input, RESET, or during the
configuration process. The flip-flops share the enable
clock [.ee] which, when Low, recirculates the flip-flops'
present states and inhibits response to the data-in or
combinatorial function inputs on a CLB. The user may
enable these control inputs and select their sources. The
user may also select the clock net input [.k], as well as its
active sense within each logic block. This programmable
inversion eliminates the need to route both phases of a
clock signal throughout the device. Flexible routing allows
use of common or individual CLB clocking.

routing access to logic block input variables, control inputs
and block outputs. Three types of metal resources are
provided to accommodate various network interconnect
requirements:
• General Purpose Interconnect
• Direct Connection
• Long Lines (multiplexed busses and wide AND gates)

General Purpose Interconnect
The combinatorial-logic portion of the logic block uses a 32
by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal
block flip-flops are used as table address inputs. The
combinatorial propagation delay through the network is
independent of the logic function generated and is spike
free for single input variable changes. This technique can
generate two independent logic functions of up to four
variables each as shown in Figure Sa, or a single function
of five variables as shown in Figure Sb, or some functions
of seven variables as shown in Figure Sc. Figure 6 shows
a modulo 8 binary counter with parallel enable. It uses one
CLB of each type. The partial functions of six or seven
variables are implemented using the input variable [.e] to
dynamically select between two functions of four different
variables. Forthe two functions of four variables each, the
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. Forthe single
function of five variables and merged functions of six or
seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the logic blocks and lOBs.

General purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical metal
segments located between the rows and columns of logic
and lOBs. Each segment is the "height" or ''width'' of a logic
block. Switching matrices join the ends of these segments
and allow programmed interconnections between the
metal grid segments of adjoining rows and columns. The
switches of an unprogrammed device are all nonconducting. The connections through the switch matrix
may be established by the automatic routing or by using
Editnet to select the desired pairs of matrix pins to be
connected or disconnected. The legitimate switching
matrix combinations for each pin are indicated in Figure 10
and may be highlighted by the use of the Show-Matrix
command in XACT.
INTERCONNECT
"PIPs"

SWITCHING
MATRIX

. 1-'.:

/= .

t-·.:

0,::,',:,::0
.. . :

~-

...

PROGRAMMABLE INTERCONNECT
Programmable-interconnection resources in the Logic
Cell Array provide routing paths to connect inputs and
outputs of the I/O and logic blocks into logic networks.
Interconnections between blocks are composed from a
two-layer grid of metal segments. Specially designed pass
transistors, each controlled by a configuration bit, form
programmable interconnect points (PIPs) and switching
matrices used to implement the necessary connections
between selected metal segments and block pins. Figure
7 is an example of a routed net. The XACT development
system provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for
design optimization. The inputs of the logic or lOBs are
multiplexers which can be programmed to select an input
network from the adjacent interconnect segments. As the

t-· :

"::0
.
..

....
:

t ,.;':
CONFIGURABLE
LOGIC BLOCK

~-

'

4.: .:
INTERCONNECT
BUFFER

X119i'

Figure j'. An XACT view of routing resources used to form a
typical interconnection network from CLB GA.

switch connections to block inputs are unidirectional

2-7

XC3000 Logic Cell Array Family

····15
'::eJ t-·.:.: .
.' r· ..
0'·:' "0·:·· :0:"

t·.; .:
~ .. '

~.~.-+~~

~-

..

...

~'

.::.fj

. r

t·.;.

t- . .;.

'0
"'0"
!- ""," " \" 1--"", ""
.
.

.

""

CLB CONTROL INPUTS

..

.

.

CLB YOUTPUT

0. ·· .'.... 0". \'" 0" '\' O'
....

......
......

.....
..0.
. .....
.......
. ..

""

~- .':

~ .':

: :

0:,
..
:

:

'~ ::

..

.0. ......
.... ........ "

'

:

'~- ,':
:

t,

:0'

.. ,
..

'

:

.

:

t- , ..
~-

:

'::5

,

~

:

:

.. +"

CLB LOGIC INPUTS

CLBXOUTPUT

.. ..

.. . ..

r'
.... :
.. ~

0':,

':.',13

: :

:

.

. .

'

..

:

t- , ..

:0'
..
,

,

~-

'::G

'

:

..

~.

:

:

Figure 8. XACT Development System Locations of interconnect
access, CLB control inputs, logic inputs and outputs. The dot pattern
represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP which drives from a horizontal to a vertical line.
D:V->H is a PIP which drives from a vertical to a horizontal line.
D:C->T is a "T" PIP which drives from a cross of a T to the tail.
D:CW is a corner PIP which drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is "on."

2-8

~'

X1198

~!'T'I\'X
}'\)lii,.".%l t -_~
Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
of the "Show BIOI" command in XACT. The other PIPs
adjacent to the matrices are access to or from long lines.
The development system automatically defines the buffer
direction based on the location of the interconnection
network source. The delay calculator of the XACT development system automatically calculates and displays the
block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worstcase delay model is provided by an XACT option.

interconnect to drive the .d input of the block immediately
above and the .a input of the block below. Direct intercon-

V ~ 10 ~ ~
1

2

5

4

3

7~ ~~ ~~ ~= ~~
6

7

8

10

9

~ ~ ~ ~ (J
II
~~ =~ ~~

Direct Interconnect
Direct interconnect, shown in Figure 11, provides the most
efficient implementation of networks between adjacent
logic or 1/0 Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the .x output may be connected directly to
the .b input of the CLB immediately to its right and to the .c
input of the CLB to its left. The. y output can use direct

11

12

13

16

17

18

ee
14

15

19

20

1105 13

Figure 10. Switch Matrix Interconnection Options
for Each Pin. Switch matrices on the edges are different.
Use Show Matrix menu option in XACT

'::{9 :..
:

.' t· ..

..

0'·:'
..

~-

··a
"

~

·::a

t·

.

,

t·.; .

. ~q . .

-

SWITCHING
MATRIX

GRID OF GENERAL INTERCONNECT
METAL SEGMENTS

·::a eJ

..

'

:

..

. .

'0"
+-

:

:
:

i.:

r·.;
.
..

..

..

:
:

:

;"

t

..

2-9

~

El

Figure 11. CLB.X and.Y Outputs. The.x and.y
outputs of each CLB have single contact, direct
access to inputs of adjacent CLBs.

Figure 9. LCA General-Purpose Interconnect.
Composed of a grid of metal segments which may be
interconnected through switch matrices to form networks
for CLB and lOB inputs and outputs.

~

X1198

XC3000 Logic Cell Array Family
GLOBAL BUFFER DiRECT INPUT

GLOBAL BUFFER iNTERCONNECT

o

o

0
ALTERNATE BUFFER DIRECT iNPUT

*UNBONDED lOBs (6 PLACES)

Figure 12. X3020 Die-Edge lOBs. The X3020 die-edge lOBs are provided with direct access to adjacent CLBs.

2-10

X1200

nect should be used to maximize the speed of highperformance portions of logic. Where logic blocks are
adjacent to lOBs, direct connect is provided alternately to
the 108 inputs [.1] and outputs [.0] on all four edges of the
die. The right edge provides additional direct connects
from CLB outputs to adjacent lOBs. Direct interconnections of lOBs with CLBs are shown in Figure 12.

A buffer in the upper left corner of the LCA chip drives a
global net which is available to all .k inputs of logic blocks.
Using the global buffer for a clock Signal provides a skewfree, high fan-out, synchronized clock for use at any or all
of the I/O and logic blocks. Configuration bits for the .k
input to each logic block can select this global line or
another routing resource as the clock source for its flipflops. This net may also be programmed to drive the die
edge clock lines for lOB use. An enhanced speed, CMOS
threshold, direct access to this buffer is available at the
second pad from the top of the left die edge.

Long Lines
The long lines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Long lines, shown in Figure 13, run vertically and
horizontally the height or width of the interconnect area.
Each interconnection column has three vertical long lines,
and each interconnection row has two horizontal long
lines. Two additional long lines are located adjacent to the
outer sets of switching matrices. In devices larger than the
XC3020, two vertical long lines in each column are connectable half-length lines. On the XC3020, only the outer
long lines are connectable half-length lines.

A buffer in the lower right corner of the array drives a
horizontal long line that can drive programmed connections to a vertical long line in each interconnection column.
This alternate buffer also has low skew and high fan-out.
The network formed by this alternate buffer's long lines
can be selected to drive the .k inputs of the logic blocks.
CMOS threshold, high speed access to this buffer is
available from the third pad from the bottom of the right die
edge.

Long lines can be driven by a logic block or lOB output on
a cOlumn-by-column basis. This capability provides a
common low skew control or clock line within each column
of logic blocks. Interconnections of these long lines are
shown in Figure 14. Isolation buffers are provided at each
input to a long line and are enabled automatically by the
development system when a connection is made.

A pair of 3-state buffers, located adjacent to each CLB,
permits logic to drive the horizontal long lines. Logic
operation of the 3-state buffer controls allows them to
implement wide multiplexing functions. Any 3-state buffer
input can be selected as drive for the horizontal long-line
bus by applying a Low logic level on its 3-state control line.
See Figure 15a. The user is required to avoid contention

Internal Busses

ON-CHIP
3-STATE
BUFFERS
PULL-UP
RESISTORS<
FOR ON-CHIP
OPEN DRAIN
SIGNALS
~ru~--------~--~gu~------~~~---------r~u---H+----~~~

..
"0

2 HORIZONTAL LONG LINES

Ei .':'

. fsA} :-:';

r·.;

, t-.;

::@ .'. ;
p

'fl'"
" t· ..

·U·-;-

.- :.
....
X1243

Figure 13. Horizontal and Vertical long lines. These long lines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the LeA.

2-11

II

XC3000 Logic Cell Array Family

15b. Pull-up resistors are available at each end of the long
line to provide a High output when all connected buffers
are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals
drive the 3-state control lines, these buffers form mUltiplexers (3-state busses). In this case, care must be used

which can result from muHiple drivers with opposing logic
levels. Control of the 3-state input by the same signal that
drives the buffer input, creates an open-drain wired-AND
function. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the long line Low. See Figure

_J:;::::;====;::;:;:::;;:;=====;::;:;::::;==9~;=;:::;:::~;=;:~==:;;:::;;=;;::_1I0 BLOCK CLOCK NETS

o

C

(2 PER DIE EDGE)

3-STATE
BUFFERS

X1244

Figure 14. Programmable Interconnection of Long Lines. This is provided at the edges of the routing area. Three-state
buffers allow the use of horizontal long lines to form on-chip wired-AND and multiplexed buses. The left two non-clock vertical long
lines per column (except XC3020) and the outer perimeter long lines may be programmed as connectible half-length lines.

1105

Figure 15a.

3-State Buffers Implement a Wired-.AND Function. When all the buffer
3-state lines are High, (high impedance), the pull-up resistor(s) provide the
High output. The buffer inputs are driven by the control signals or a Low.

04

I if" if" I
==

T

6E

X1741

Figure 15b. 3-State Buffers Implement a MUltiplexer.
The selection is accomplished by the buffer 3-state signal.

2-12

lator components as shown in Figure 17. A divide by two
option is available to assure symmetry. The oscillator
circuit becomes active before configuration is complete in
order to allow the oscillator to stabilize. Actual internal
connection is delayed until completion of configuration. In
Figure 17 the feedback resistor R1, between the output
and input, biases the amplifier at threshold. The value
should be as large as practical to minimize loading of the
crystal. The inversion of the amplifier, together with the
R-C networks and an AT-cut series resonant crystal,
produce the 360-degree phase shift of the Pierce oscillator. A series resistor R2 may be included to add to the
amplifier output impedance when needed for phase-shift
control, crystal resistance matching, orto limitthe amplifier
input swing to control clipping at large amplitudes. Excess
feedback voltage may be corrected by the ratio of C2/C1.
The amplifier is designed to be used from 1 MHz to one-

to prevent contention through multiple active buffers of
conflicting levels on a common line. Each horizontal long
line is also driven by a weak keeper circuit that prevents
undefined floating levels by maintaining the previous logic
level when the line is not driven by an active buffer or a pullup resistor. Figure 16 shows 3-state buffers, long lines and
pull-up resistors.
CRYSTAL OSCILLATOR

Figure 16 also shows the location of an internal high speed
inverting amplifier which may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the
oscillator is configured by MAKEBITS and connected as a
signal source, two special user lOBs are also configured to
connect the oscillator amplifier with external crystal oscil-

III

BIOI RECTIONAL
INTERCONNECT
BUFFERS

II I

II;G

1

-

-

N

+

/

3 VERTICAL LONG
LINES PE.R COLUMN

II;H
.1

~
y\.\.

I iii-I
I

~
..,....-

'-n--

~

Del

L

tI:

~f.~
~j
AJ

I II

e:JCO

--

~

;.......=.e

~

[]

D

D

D

OSCILLATOR
AMPLIFIE:R OUTPUT
OIRECTINPUT OF P47
TO AUXILIARY BUFFER

CRYSTAL OSCILLATOR
BUFFER

'--

P

;;;..

HORIZONTAL LONG LINE

V
~ ·--1

ffl
0-

_e:J e:J

HORIZONTAL LONG LINE

: / PULL-UP RESISTOR

p

I

I
Iw'I

1/0 CLOCKS

I ilJ V

A

I...-..::-

1111

o < DATA FRAME #001 >
o < DATA FRAME #002 >
o < DATA FRAME #003 >

o < DATA FRAME # 196>
o < DATA FRAME#197 >

DUMMY BITS'
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)

111
111
111

]

HEADER

FOR XC3020

J

111
111

1111

197 CONFIGURATION DATA FRAMES

PROGRAM DATA

(EACH FRAME CONSISTS OF:
A START BIT (0)
A 71-BIT DATA FIELD
THREE STOP BITS

REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN

POSTAMBLE CODE (4 BITS MINIMUM)

'THE LCA DEVICES REOUIRE FOUR DUMMY BITS MIN; XACT 2.10 GENERATES EIGHT DUMMY BITS

Device

XC3020

Gates

2000

1105 OSA

XC3030

XC3042

3000

4200

100
(10 x 10)

144
(12x12)

224
(16x14)

320
(20 x 16)

64

80

96

120

144

256

360

480

688

928

Horizontal Long Lines

16

20

24

32

40

TBUFs/Horizontal LL

9

11

13

15

17

92

108

140

172

197

241

285

329

373

Program Data =
14779
Bits x Frames + 4 bits
(excludes header)

22176

30784

46064

64160

22216

30824

46104

64200

CLBs
Row x Col

64
(8 x 8)

lOBs
Flip-flops

Bits per Frame
75
(includingl start and 3 stop bits)
Frames

PROM size (bits)
Program Data
+ 40-bit Header

=

14819

XC3064
6400

XC3090
9000

Figure 19. Internal Configuration Data Structure for an LCA. This shows the preamble, length count
and data frames which are generated by the XACT Development System.
The Length Count produced by the MAKEBIT program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8]- (2 :> K :> 4) where K is a function of DONE and RESET timing selected. An additional 8 is added
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.

2-16

supply currents. If unused blocks are not sufficient to
complete the 'tie,' the FLAGNET command of EDITLCA
can be used to indicate nets which must not be used to
drive the remaining unused routing, as that might affect
timing of user nets. NORESTORE will retain the results of
TIE for timing analysis with QUERYNET before RESTORE returns the design to the untied condition. TIE can
be omitted for quick breadboard iterations where a few
additional milliamps of Icc are acceptable.

selection pins at the start of configuration time determine
the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configuration mode. Various Xilinx Field Programmable Gate
Arrays have different sizes and numbers of data frames.
To maintain compatibility between various device types,
the Xilinx 2000 and 3000 product families use compatible
configuration formats. For the XC3020, configuration
requires 14779 bits for each device, arranged in 197 data
frames. An additional 40 bits are used in the header. See
Figure 20. The specific data format for each device is
produced by the MAKEBITS command of the development system and one or more of these files can then be
combined and appended to a length count preamble and
be transformed into a PROM format file by the 'MAKE
PROM' command of the XACT development system. A
compatibility exception precludes the use of a 2000-series
device as the master for 3000-series devices if their DONE
or RESET are programmed to occur after their outputs
become active. The '1ie" option ofthe MAKEBITS program
defines output levels of unused blocks of a design and
connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic

The configuration bitstream begins with High preamble
bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the LCA is set
to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the LCA, it is internally
assembled into a data word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The configuration loading process is complete when the current length
count equals the loaded length count and the required
configuration program data frames have been written.
Internal user flip-flops are held reset during configuration.

POSTAMBLE

r"J J' bYGI--:~'- T-f!. .-.j3i-r1 ,-,- 41

-

IPREAMBLE I LENGTH COUNT I

If

DATA

I Irl

START

I I

LENG TH COUNT'
START
WEAK PULL-UP

IrOACTIVE

HIGH
DOUT LEAD DEVICE

112 CLOCK CYCLE
DELAY FROM DATA INPUT

PROGRAM

/

INTERNAL RESET ' \

* The configuration data consists of a composite
40-bit preamble/length count, followed by one or
more concatenated LeA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.

V
\

Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.

Figure 20_ Configuration and Start-up of One or More LCAs.

2-17

DONE

1105068

II

XC3000 Logic Cell Array Family

portions of the system. The state diagram of Figure 18
illustrates the configuration process.

Two user-programmable pins are defined in the unconfigured Logic Cell array. High During Configuration (HDC)
and Low During Configuration (LDC) as well as
DONEIPROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length count compares, the user I/O pins become
active. Options in the MAKEBITS program allow timing
choices of one clock earlier or laterforthe timing ofthe end
of the internal logic reset and the assertion of the DONE
signal. The open-drain DONEIPROG output can be ANDtied with multiple LCAs and used as an active-High
READY, an active-Low PROM enable or a RESETto other

.

• IF READBACK IS
ACTIVATED, A
5-1<0 RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 1<0 M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USERVO.

I I

-=!:=-

MO
'--

'---

-

GENERALPURPOSE
USERVO
PINS

Master Mode
In Master mode, the LCA device automatically loads
configuration data from an external memory device. There
are three Master modes that use the internal timing source
to supply the configuration clock (CCLK) to time the
incoming data. Serial Master mode uses serial configuration data supplied to Data-in (DIN) from a synchronous
serial source such as the Xilinx Serial Configuration
PROM shown in Figure 21. Parallel Master Low and
Master High modes automatically use parallel data sup-

+r

M1 PWRDWN

DOUT

OPTIONAL
l...+ DAISY-CHAINED
LCAsWITH

M2

,..

g~~~~'D~ATIONS

HOC

--c LOC
--c INIT

-

}0_'
1/0

PINS

-

XC3000
LCA
DEVICE

OPTIONAL

f---- SLAVE LCAs

WITH IDENTICAL
CONFIGURATIONS

_

+5V

II

RESET--< RESET
DIN
CCLK
DIP

r

CLK

CE

~w.

Vpp

Vee
DATA

_____ •_________ ,

.

:

DATA

L-....l CLK

SCP
CEO

~C1736A1XC1765

"v

r

:

CE

CASCADED
SERIAL
MEMORY

.

OE
_. _____________ ._ • ..1

(HIGH RESETS THE XC1736A1XC1765 ADDR ESS POINTER)

=~

(~~
(OUTPUT)

X1548A

Figure 21. Master Serial Mode. The one-time-programmable XC1736A1XC1765 Serial Configuration PROM supports
automatic loading of configuration programs up to 36K!64K bits. Mu~iple devices can be cascaded to support additional
LCAs. An early D/f' inhibits the PROM data output a CCLK cycle before the LCA 1I0s become active.

2-18

plied to the DO-D7 pins in response to the 16-bit address
generated by the LCA. Figure 22 shows an example of the
parallel Master mode connections required. The LCA HEX
starting address is 0000 and increments for Master Low
mode and it is FFFF and decrements for Master High
mode. These two modes provide address compatibility
with microprocessors which begin execution from opposite ends of memory. For Master High or Low, data bytes
are read in parallel by each Read Clock (RCLK) and

internally serialized by the Configuration Clock. As each
data byte is read, the least significant bit of the next byte,
DO, becomes the next bit in the internal serial configuration
word. One Master-mode LCA can be used to interface the
configuration program-store and pass additional concatenated configuration data to additional LCAs in a serial
daisy-chain fashion. CCLK is provided for the slaved
devices and their serialized data is supplied from DOUTto
DIN - DOUT to DIN etc.

USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS

+5V

• IF READBACK IS
ACTIVATED, A
5-kn RESISTOR IS
REQUIRED IN
SERIES WITH M1

opnONAL

5kn

DOUT
M2

CCLK

DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

II

HOC
GENERALPURPOSE
USER 110
PINS

A15
RCLK

A14

INIT

A13

EPROM

A12

OR~~~C:ER)

} OTHER
110 PINS

A11
A10

RESET

A10

RESET

A9

A9

D7

/lJ3.

/lJ3

LCA

A7

A7

07

AS

AS

os

A5

AS

D5

A4

A4

D4

A3

A3

D3

A2

A2

02

A1

A1

01

AO

AO

DO

DIP

OE
CE

DATA BUS

cd'--_______

(od~t\1 ___---J~\.._A_DD_RE_SS_....: _ _ _ _ _
00-'-D7
N-1 BYTE
RCLK - {

118CCLK
(OUTPUT)

XXXXX

PROM:

BYTE N

1C XXXXX

BYTE N+1

"'-"'''-lU..._ _ _ _ __

~-----~:acru~=====~
.

.

BCCLKs

\

'-------

CCLK~

(OUTPUT)

(ouWtY~

ysotBYTEtF D7OfBYTEt0 ?OOfBYTEN
X1549

Figure 22. Master Parallel Mode. Configuration data are loaded automatically from an external byte wide PROM.
An early DIP inhibits the PROM outputs a CCLK cycle before the LCA lIas become active.

2-19

XC3000 Logic Cell Array Family

Peripheral Mode

modes, Peripheral mode may also be used as a lead
device for a daisy-chain of slave devices.

Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion ofthe active low Write Strobe (WS), and two
active low and one active high Chip Selects (CSO, CS1,
CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Logic Cell Array will accept one byte of configuration
data on the 00-07 inputs for each selected processor
Write cycle. Each byte of data is loaded into a buffer
register. The LCA generates a configuration clock from
the internal timing generator and serializes the parallel
input data for internal framing or for succeeding slaves on
Data Out (DOUT). A output High on READY/BUSY pin
indicates the completion of loading for each byte when the
input register is ready for a new byte. As with Master

CON TROL
SIG NALS

ADDRESS
BUS

Slave mode provides a simple interface for loading the
Logic Cell Array configuration as shown in Figure 24.
Serial data are supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisychain configurations in which the data input are supplied
by the previous Logic Cell Array's data out, while the clock
is supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
Daisy-Chain
The XACT development system is used to create a composite configuration for selected LCAs including: a pre-

8
DO-7

MO

M1PWR
DWN

DO-7

CCLK

~

f'.+5V

f'L-

ADDRESS
DECODE
LOGIC

+5V

I*ll

DATA
BUS

'I

Slave Mode

P----<

OPTIONAL

DOUT I - -

-

I--

-

M2

CSO

f--

DAISY -CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

HDC I - -

LCA

LDC

p--

CS1
CS2

OTHER
WS ----,!?PINS

RDY/BUSY

{

GENERA LPURPOS E
USER 1/0
PINS

-

INIT

~

REPROGRAM

• IF READBACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN SERIES
WITHM1

5

DIP

V

RESET

WS
CSO
CSI
CS2

\\\\\\\\
W/Illl

DO-D7

X

CCLK

(INTERNAL) \ .

DOUT

j

00

\\\\

\ill
X

lll7

\oJ

-----------------------~

~

RDY/BUSY

Figure 23. Peripheral Mode. Configuration data are loaded using a byte-wide data bus from a microprocessor.

2-20

1105 18C

amble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 25. Loading
continues while the lead device has received its configuration program and the current length count has not reached
the full value. The additional data are passed through the
lead device and appear on the Data Out (DOUT) pin in
serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output
data and data in of down-stream LCAs. Data are read in
on DIN of slave devices by the positive edge of CCLK and
shifted out the DOUT on the negative edge of CCLK. A
parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM
address rate, while a Peripheral mode device produces a
burst of 8 CCLKs for each chip select and write-strobe

cycle. The internal timing generator continues to operate
for general timing and synchronization of inputs in all
modes.
SPECIAL CONFIGURATION FUNCTIONS
The configuration data include control over several special
functions in addition to the normal user logic functions and
interconnect:
•
•
•
•
•
•

Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two

Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
development system bitstream generation process.

+5V

MO

• IF READBACK IS
ACTIVATED, A
5-kO RESISTOR IS
REQUIRED IN
SERIES WITH M1

M1 PWRDWN

MICRO
COMPUTER
CCLK

STAB

M2

DIN

DO

DOUT
HOC

D1
110
PORT

LDC

D2
D3

+5V
LCA

D4

GENERALPURPOSE
USER 110
PINS

OTHER {
110 PINS

D5
D6

-

OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

DIP

D7
RESET

DIN

-1X.
1
I: __t
-."---"-------~f------~-------.~~~~~--------J~

==X~

BI,-TN
__

BITN+1

CCLK ________

DOUT---------------------------~r-----------

(OUT Pun ________________--.,._B_IT_N_-_1______..Ltyy\.JL:Ji......___
B_IT_N__"--__-,1105198

Figure 24. Slave Mode. Bit-seria.l configuration data are read at rising edge of the CClK.
Data on DOUT are provided on the falling edge of CClK.

2-21

II

XC3000 Logic Cell Array Family

Input Thresholds

Readback

Prior to the completion of configuration all LCA input
thresholds are TIL compatible. Upon completion of configuration the input thresholds become either TIL or
CMOS compatible as programmed. The use of the TIL
threshold option requires some additional supply current
forthreshold shifting. The exception is the threshold ofthe
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user 1/0 pins each have a high impedance pull-up. The
configuration program can be used to enable the lOB pullup resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.

The contents of a Logic Cell Array may be read back if it
has been programmed with a bitstream in which the
Readback option has been enabled. Readback may be
used for verification of configuration and as a method of
determining the state of internal logic nodes during debugging with the XACTOR In-Circuit debugger. There are
three options in generating the configuration bitstream:

• IF :tfte2~~~.lf
5-kO RESISTOR IS

REOUIRED1N
SERIES WITH M1

l

• "Never" will inhibit the Readback capability.
• "One-time," will inhibit Readback after one Readback
has been executed to verify the configuration.
• "On-command" will allow unrestricted use of Readback .

.5 V

5kO

CCLK

5kO

CCLK

OOUTr---------------------~ DIN

DIN

lCA
SLAVE 11

M2

5kO

eelK

DOUT

HDC

GENERAL·
PURPOSE

MO M1 PWRDWN

MO M1 PWRDWN

DOUT
lCA
SLAVE#n

M2

M2

A15

HDC

HDC

A1'

A1'

lDC

A13

A13

A12

A12

All

All

LeA

Al0

Al0

MASTER

A9

A9

DIP

DIP

07

A8

A8

RESET

RESET

06

A7

A7

AS

ACLK

A15

USERI/Q
PINS

EPROM

f7J~T~s

05

A6

D4

A5

A5

03

A.

A4

02

A3

A3

01

A2

A2

DO

A1

A1

AO

AO

DIP
RESET

INIT

GENERAL·
PURPOSE
USERJ/O
PINS

lDC

OTHER {
IJOPINS

OTHER {
I/O PINS

INIT

GENERAL·

PURPOSE
USER lIC
PINS

INIT

NOTE: XC2000 DEVICES DO NOT
HAVE INIT TO HOLD OFF A MASTER
DEVICE. Rrnl OF A MASTER DEVICE
SHOULD BE ASSERTED BY AN EXTERNAL
TIMING CIRCUIT TO ALLOW FOR LeA CCLK
VARIATIONS IN CLEAR STATE TIME.

DE
N.G.

.5 V

CE

5 knEACH
OPEN

COLLECT~

X1550

SYSTEM RESET

Figure 25. Master Mode Configuration with Daisy Chained Slave Mode Devices.
All are configured from the common EPROM source. The Slave mode device lNlT signals
delay the Master device configuration until they are initialized. A well defined termination
of SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DIP and early internal RESET".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)

2-22

Readback is accomplished without the use of any of the
user 110 pins; only MO, M1 and CCLK are used. The
initiation of Readback is produced by a Low to High
transition of the MO/RTRIG (Read Trigger) pin. The CCLK
input must then be driven by external logic to read back the
configuration data. The first three Low-to-High CCLK
transitions clock out dummy data. The subsequent Lowto-High CCLK transitions shift the data frame information
out on the M1 IRDATA (Read Data) pin. Note thatthe logic
polarity is always inverted, a zero in configuration becomes a one in Readback, and vice versa. Note also that
each Readback frame has one Start bit (read back as a
one) but, unlike in configuration, each Readback frame
has only one Stop bit (read back as a zero). The third
leading dummy bit mentioned above can be considered
the Start bit of the first frame. All data frames must be read
back to complete the process and return the Mode Select
and CCLK pins to their normal functions.
Readback data includes the current state of each internal
logic block storage element, and the state of the .i and .q
pins on each lOB. These data are imbedded into unused
configuration bit positions during Readback. This state
information is used by the XACT development system InCircuit Verifier to provide visibility into the internal operation olthe logic while the system is operating. To readback
a uniform time-sample of all storage elements, it may be
necessary to inhibit the system clock.

are AND-wired and used to force a RESET on the master
(see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls
DONE!PROG Low. Once it recognizes a stable request,
the Logic Cell Array will hold a Low until the new configuration has been completed. Even if the re-program request is externally held Low beyond the configuration
period, the Logic Cell Array will begin operation upon
completion of configuration.
DONE Pull-up
DONE!PROG is an open-drain 1/0 pin that indicates the
LCA is in the operational state. An optional internal pull-up
resistor can be enabled by the user of the XACT development system when MAKE BITS is executed. The DONE!
PROG pins of multiple LCAs in a daisy-chain may be
connected together to indicate all are DONE or to direct
them all to re-program.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MAKEBITS pro.gram to occur a CCLK
cycle before, or after, the timing of outputs being activated.
See Figure 20. This facilitates control of external functions
such as a PROM enable or holding a system in a wait state.
RESET Timing

Reprogram
The LCA configuration memory can be re-written while the
device is operating in the user's system. To initiate a reprogramming cycle, the dual-function pin DONE/PROG
must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles olthe
LCA internal timing generator. When re-program begins,
the user-programmable 1/0 output buffers are disabled
and high-impedance pull-ups are providedforthe package
pins. The device returns to the Clear state and clears the
configuration memory before it indicates 'initialized'.
Since this Clear operation uses chip-individual internal
timing, the master might complete the clear operation and
then start configuration before the slave has completed the
Clearoperation. To avoid this problem, the slave INIT pins

As with DONE timing, the timing of the release of the
internal RESET can be controlled by a selection in the
MAKEBITS program to occur a CCLK cycle before, or
after, the timing of outputs being enabled. See Figure 20.
This reset maintains all user programmable flip-flops and
latches in a zero state during configuration.
Crystal Oscillator Division
A selection in the MAKEBITS program allows the user to
incorporate a dedicated divide-by-two flip-flop in the crystal oscillator function. This provides higher assurance of a
symmetrical timing signal. Although the frequency stability of crystal oscillators is high, the symmetry of the
waveform can be affected by bias or feedback drive.

II

XC3000 Logic Cell Array Family
the flip-flop element. The delay from the clock source to
the output of the logic block is critical in the timing of signals
produced by storage elements. Loading of a logic-block
output is limited only by the resulting propagation delay of
the larger interconnect network. Speed performance of
the logic block is a function of supply voltage and
temperature. See Figure 29.

PERFORMANCE
Device Performance
The LCA high performance is due in part to the manufacturing process, which is similarto that used for high-speed
CMOS static memories. Performance can be measured in
terms of minimum propagation times for logic elements.
Traditionally, the toggle frequency of a flip-flop has been
used to describe the overall performance of a gate array.
The configuration for determining the toggle performance
of the Logic Cell Array is shown in Figure 26. The flip-flop
output Q is fed back through the combinatorial logic as Q
to form the toggle flip-flop.

Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
fast path for a signal. The single metal segment used for
long lines exhibits low resistance from end to end, but
relatively high capacitance. Signals driven through a
programmable switch will have the additional impedance
of the switch added to their normal drive impedance.

Actual LCA performance is determined by the timing of
critical paths, including both the fixed timing for the logic
and storage elements in that path, and the timing associated with the routing of the network. Internal worst-case
timing values are included in the performance data to allow
the user to make the best use of the capabilities of the
device. The XACT development system timing calculator
or XACT generated simulation models should be used to
calculate worst case paths by using actual impedance and
loading information. Figure 27 shows a variety of elements
which are involved in determining system performance.
Actual measurement of internal timing is not practical and
often only the sum of component timing is relevant as inthe
case of input to output. The relationship between input and
output timing is arbitrary and only the total determines
performance. Timing components of internal functions
may be determined by measurement of differences at the
pins of the package. A synchronous logic function which
involves a clock to block-output, and a block-input to clock
set-up is capable of higher speed operation than a logic
configuration of two synchronous blocks with an extra
combinatorial block level between them. System clock
rates to 60% of the toggle frequency are practical for logic
in which an extra combinatorial level is located between
synchronized blocks. This allows implementation of
functions of up to 25 variables. The use of the wired-AN D
is also available for wide, high-speed functions.

General-purpose interconnect performance depends on
the number of switches and segments used, the presence
of the bidirectional repowering buffers and the overall
loading on the signal path at all points along the path. In
calculating the worst-case timing for a general interconnect path the timing-calculator portion of the XACT development system accounts for all of these elements. As an
approximation, interconnect timing is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the time is a sum of R-C
time each approximated by an R times the total C it drives.
The R of the switch and the C of the interconnect is a
function of the particular device performance grade. For a
string of three local interconnects, the approximate time at
the first segment, afterthe first switch resistance would be
three units; an additional two units after the next switch
plus an additional unit after the last switch in the chain. The
interconnect R-C chain terminates at each re-powering
buffer. The capacitance of the actual block inputs is not
significant; the capacitance is in the interconnect metal
and switches. See Figure 28.

Logic Block Performance
Logic block performance is expressed as the propagation
time from the interconnect point at the input of the
combinatorial logic to the output of the block in the
interconnect area. Combinatorial performance is
independent of the specific logic function because of the
table look-up based implementation. Timing is different
when the combinatorial logic is used in conjunction with
the storage element. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to

owJ'-·····_···- - - - 0
I...............H. . . . . ~
Figure 26. Toggle Flip-Flop. This is used
to characterize device periormance.

2-24

110507

E:X1l1NX

CLB
LOGIC

1-+-+---1

t. . ~. ~. . . ~..
(K)

••....N.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.::·

:::,', ..•..,...................................... .

CLOCK--~----------+---------------------~~

PAD------1

I~.-----------TO~----------~·I
-70

Speed Grade
Symbol

Description

Min

-100

Max

Units

-125

Min Max

Min Max
5.5

ns

6

ns
ns
ns

4

3

ns

9

6

5

ns

13

10

9

ns

7

9

Logic input to Output

Combinatorial

Tn:o

K Clock

To output
Logic-input setup
Logic-input hold

TCKO
TICK
TCKI

Pad to input (direct)

TplD

6

Output to pad (fast)

TOPF

110 clock to pad (fast)

TOKPO

InpuUOutput

110521A

7

8
8

6

7
0

0

0

Figure 27. Examples of Primary Block Speed Factors.
Actual timing is a function of various block factors oombined with routing factors.
Overall performance can be evaluated with the XACT timing·calculator or by an optional simUlation.
SWITCH

; ___ . _--;It" MATRIX -.......:...; ___ . ___ ;
CLB

:

R2

:

:

R3

:

TIMING: INCREMENTAL
IF Rl ~ R2 = R3 • RAND C1= C2 • C3 • C
THEN CUMULATIVE TIMING
T1 .3AC
=3AC

T2 =3AC+2RC

T3=3AC+2RC+1RC

=SAC

= SAC

6AC+BUFFER

110523B

Figure 28. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.

2-25

III

XC3000

Lo~lc

Cell Array Family
SPECIFIED WORST-CASE VALUES

~~

1.00

." ~\I.-\1!"~ ~

~",..~~~

~.,.,
~~

0.80

TYPICAL COMMERCIAL
(+ 5.0 V, 25'C)

•
•

TYPICAL MILITARY
0.40

MIN}AJI,l",.A~:! i4~5~Vl- ~ ~ -:

MIN COMMERCIAL 4.75 V
CA 5. _~_~~

MIN MILITARy .15~5~Vl ~ ~ - -'
.. -.. ------ ... --_............
----------------------- - ... - -

.. - ..

0.20

I

----

... ----- ----

r:::::---------------55

-40

o

-20

40

25

70

80

I

100

125

TEMPERATURE ('C)

X1045

Figure 29_ Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations.

GND

Vee

+ --+--+--+--+--+--+ --+,
,
+, --+ -- +--+
--+ --+-,, + --+
,
,,
+ --+ --+ --+ --+ --+ --+ --+
+, --+, -- +-+- -+ -- + --+ -- +
,
,
,,
+--+--+ --+--+--+--+--+
_-r--H-t"-....
+--+--+--+--+-+ --+ -- + --+ --+ --+ --+ -- +,
,
+ --+ --+ --+ -- + --+ --+ -- +
I

I

I

,

I

I

I

I

I

I

I
I

I
I

I
I

I

I

I

I

I

I

I

I

I
I

I

GROUND AND
Vee RING FOR
1/0 DRIVERS

I

LOGIC POWER GRID

GND
1105~

Figure 30. LCA Power Distribution.

2-26

E:XllINX
POWER

In an LCA, the fraction of nodes changing on a given clock
is typically low (10-20%). For example, in a large binary
counter, the average clock cycle produces changes equal
to one CLB output at the clock frequency. Typical global
clock-buffer power is between 1.7 mW/MHz for the
XC3020 and 3.6 mWIMHz for the XC3090. The internal
capacitive load is more a function of interconnect than fanout. With a typical load of three general interconnect
segments, each CLB output requires about 0.4 mW per
MHz of its output frequency.

Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and 1/0.
Inside the LCA, a dedicated Vcc and ground ring surrounding the logic array provides power to the 1/0 drivers.
See Figure 30. An independent matrix of Vcc and ground
lines supplies the interior logic of the device. This power
distribution grid provides a stable supply and ground for all
internal logic, providing the external package power pins
are all connected and appropriately decoupled. Typically
a 0.1-J.1F capacitor connected near the VCC and ground
pins will provide adequate decoupling.

Total Power = Vee· lceo + external (dc + capacitive)
+ internal (CLB + lOB + long line + pull-up)

Output buffers capable of driving the specified 4-mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers nearthe ground pads. The 1/0 Block output
buffers have a slew-limited mode which should be used
where output rise and fall times are not speed critical.
Slew-limited outputs mai.ntain their dc drive capability,
but generate less external reflections and internal noise. A
maximum total external capacitive load for simultaneous
fast mode switching in the same direction is 500 pF per
powerlground pin pair. For slew-rate limited outputs, this.
total is four times larger.
Power Consumption
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any deSign, Figure 31
can b~ used to calculate the total power requirement
based on the sum of the capacitive and dc loads both
external and internal. The COnfiguration option of TTL chip
input threshold requires power for the threshold reference.
The power required by the static memory cells that hold the
configuration data is very low and may be maintained in a
power-down mode.

Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
power loss. The Logic Cell Array has built in power-down
logic which, when activated;. will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their· high-impedance state with no pull-ups.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.4V, the required current
can be as low as 10 J.1A at room temperature.
To force the Logic Cell Array into the Power-Down state,
the user must pull the PWRDWN pin Low and continue
to supply a retention voltage to the. VCC pins. When
normal power is restored, VCC is elevated to its normal
operating voltage and PWRDWN is returned to a High.
The Logic Cell Array resumes operation with the same
internal sequence that occurs at the conclusion of
configuration. Internal-I/O and logic-block storage
elements will be reset, the outputs will become enabled
and the DONEIPROG pin will be released. No configuration programming is involved.
When the power supply is removed from a CMOS device,
it is possible to supply some power from an input signal.
The conventional electro-static input protection is implemented with diodes to the supply and ground. A positive
voltage applied to an input (or output) will cause the
positive protection diode to conduct and drive the Vcc
connection. This condition can produce invalid power
conditions and should be avoided. A large series resistor
might be used to limitthe current or a bipolar buffer may be
used to isolate the input signal.

Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and
frequency dependent power is 25 J.1W/pF/MHz per output.
Another component of I/O power is the de loading on each
output pin by devices driven by the Logic Cell Array.
Internal power dissipation is a function of the number and
size ofthe nodes, and the frequency at which they change.

2-27

II

XC3000 Logic Cell Array Family

500

100
90

, "

SO

70

/

60

./

./

50
40

/
150

/

,

100

,

"

/

,

40

,

/

/

"

/

"
,1'

"

/

/
/

/

/

6

5

/

/

20 CLB OUTPUTS 4
(7.2 mW/MHz)

/

V

/

3

/
2

.9
.S

/

/

3

/

/

V

/

/

.7

/

.6

.5

.4

/

/

/

0.5
1/

/

V

/

(rnA)

4

/

[,

0.5

/

/

V

10

S

/V

/

50 CLB OUTPUTS 10
(1SmW/MHz)

5

/

"

,

/

/

/

20

V

/
[,

./

/

,11'

/

30

(mW)

3020 GLOBAL CLOCK BUFFER 1
OR
ONE OUTPUT WITH 50 pF LOAD
(1.S mW/MHz)

20

/

II'
50

30

.3

/

.2

.1
2

3

4

5

10

20

30

40

50

FREQUENCY MHz
ONE CLB OR lOB OUTPUT /
DRIVING THREE LOCAL
INTERCONNECTS
(0.36 mW/MHz)
1105 09

Figure 31. LCA Power Consumption by Element. Total chip power is the sum of Vcc·leeo plus effective internal and external
values of frequency dependent capacitive charging currents and duty factor dependent resistive loads.

2-28

E:XJUNX
PIN DESCRIPTIONS

DONEIPROG (DIP)
DONE is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of
configuration, the LCA circuitry becomes active in a synchronous order;· DONE is programmed to go active High
one cycle either before or after the outputs go active.

Permanently Dedicated Pins.
Vcc
Two to eight (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.

Once configuration is done, a High-to-Low transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.

GND
Two to eight (depending on package type) connections to
ground. All must be connected.

MOIRTRIG
As Mode 0, this input and M1, M2 are sampled before the
start of configu ration to establish the configuration mode to
be used.

PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
1-MHz· ClOck. During configuration,PWRDWN must be
High. If not used, PWRDWN must be tied toVcc '

A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.

RESET
This is an active Low input which has three functions.

M1/RDATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be uSed. If Readback is never used; M1 canbetieddirectly
to ground or Vcc' If Readback is ever used, M1 must use
a 5-kn resistor to ground or Vcc ' to accommodate the
RDATA output.

Prior to the start of configuration, a Low input will delay the
start of the configuration process; An internal circuit
senses the application of. power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins.

As an active Low Read· Data, after configuration is
complete, this pin is the output of tM Readback data.

If RESET is asserted during a configuration, the LCA
device is re-initialIzed and restarts the configuration at the
termination of RESET.
If RESET is· asserted after configura:tion .is complete, it
provides a global asynchronous reset.ot all lOB and CLB
storage elements of the LCA device..
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During Readback, CCLK is a clock input
for shifting configuration data out of the LCA
CCLK drives dynamic circl,Jitryinsidethe LCA. The Low
time may, therefore, not exceed a few microseconds.
When used as an irlput, CCLK must be "parked High An
internal pull-up reSistor maintains High when the pin is not
being. driven. .
D

•

2-29

III

XC3000 Logic Cell Array Family

User 110 Pins that can have special functions.

RClK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used). After configuration is complete, this
pin becomes a user-programmed 110 pin.

M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.

ROY/BUSY
During Peripheral parallel mode configuration this pin
indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.

HOC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.

00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed
I/O pins.

lOC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.

Ao-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable I/O pins.

INIT
OIN

This is an active Low open-drain output which is held Low
during the power stabilization and internal clearing of the
configuration memory. It can be used to indicate status to
a configuring microprocessor or, as a wired AND of several
slave mode devices, a hold-off signal for a master mode
device. After configuration this pin becomes a userprogrammable I/O pin.

During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input. After configuration
is complete, this pin becomes a user-programmed I/O pin.

OOUT

This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.

During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.
After configuration is complete, this pin becomes a userprogrammed I/O pin.

XTl1

TClKIN

This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.

This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to
the global clock net, and the global clock net should be
used as the primary clock source, this pin is usually the
clock input to the Chip.

BClKIN

XTl2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
I/O Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MakeBits program.

Unrestricted User I/O Pins.

CSO, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control
configuration-data entry in the Peripheral mode.
Simultaneous assertion of all four inputs generates a Write
to the internal data buffer. The removal of any assertion
clocks in the DO-D7 data. In Master-Parallel mode, WS
and CS2 are the AO and A 1 outputs. After configuration,
these pins are user-programmable I/O pins.

I/O
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted
I/O pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 50 kn to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.

2-30

XC3000 Family Configuration Pin Assignments

USER
OPERATION

175
PGA

PWR DWN (II

PWR DWN m

PWR DWN (II

PWR DW 1m

vce

vce

vcc

vce
1I<;t:t

tiicM11fui
(HIG,,*,H;K--+-'iMT~'
MO (HIG"
MO

uw:
OW

I
I

M1 .uW
MO (HIGH

Ml
Me

PWRDWNm

vce
I

0""

Ml
MO

UW

lU

18

ow (I)

HG ; (H
; (l

He

(HI<

HG ; (HII

HI

2'!.. E

~ ~

'4

'"

'0"

26

C8

20

lJ

4U

,62

~14

114

4<

--""_

1-"'-"-

44

••

J,

,,4""
41

,,0

~ ~ ~ ~
""
44
..R~~~~~

'lhQI'£

,INn

tr-I[

0<

~

~

RlJA'1A,
HIHlu(l)

;(HI~

j)QJl

I'NT

,,<""
.. ,
41
J"

20""

E
HOC (HI

22

"" "

JIL

lNll

14

4"

110
110

lb

~~~~

3NI

RESE"

i'fESE'f (I)

(I)

DONE
: DATA
I

DONI
UAIA

DATA 6
: DATA 5

DONI
DAIA

DATA 6
DATA 5

DAIA6
DATA 5

~~

~,~

vce

vce

28

45

55

I J10

40

Ob

30

41

01

40

00

IK
I Jl
I H1U

'",

80
-"

82
,O,J.

65

N13

80

,bb.Ml::::
RDY/BC
IRCLR"
RC[
,:::::Ii:>: DATA 0 I ':';;:":» DAIAO(I) :{;'i>iDAIA (1)((
DUL
DUL
DUL
CClK
LK
(;l LK

,»»'{

'»{:>,

DOl
CClK

I
DC

ce

:'

I

II

A(

A(

-"

~

.E.

~2

A3
A3
A15
A15
A4
A4
,A14A14
A5
A5
GND
GN
~13
_,,13

.A1.£

.M.

.M.
.Al2,

A7

A'

Al
A8
AlO
A9

All
A8
Al
A9

56

70

38
39
4C

00
O.

IJ

OU

t4

~

I D10,98
Iv
I '"

01

99
1C

,83
84
85

M5
N4
N<

00

°

MJ

"

ilU

IA

..!.'!.. lE.'.".

'

"0

14 ~ ~
15 ~ ~
,. 143 .H3

K
-J------------

CLB OUTPUT (X,V)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

------;=:
't=® TICK-~'"
'w

Ir::.::.-----~I

CLBCLOCK
@TCL

CLBINPUT
(DIRECT IN)

®

TECCK

CLBINPUT
(ENABLE CLOCK) _ _ _ _ _-'1"-_ _ _ _ _ _

-+__=-_,,'-______

CLBOUTPUT
(FLIP-FLOP)

CLBINPUT
(RESET DIRECT)

CLBOUTPUT
(FLIP-FLOP)
1105 26

BUFFER (Internal) SWITCHING CHARACTERISTIC GUIDELINES
Speed Grade

-70

-100

-125

Symbol

Max

Max

Max

TplD

8

7.5

7

ns

TplDC

6.5

6

5.7

ns

TBUF driving a Horizontal Long line (L.L.).
I to L.L. while T is Low (buffer active)
TJ, to L.L. active and valid with single pull-up resistor
TJ, to L.L. active and valid with pair of pull-up resistors
Ti to L.L. High with single pull-up resistor
Ti to L.L. High with pair of pull-up resistors

TIO
TON
TON
Tpus
TpUF

5
11
12
24
17

4.7
10
11
22
15

4.5
9
10
17
12

ns
ns
ns
ns
ns

BIOI
Bidirectional buffer delay

TBIDI

2

1.8

1.7

ns

Description
Global and Alternate Clock Dlstrlbutlon*
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Fast (CMOS only) input pad through clock
Or:
buffer to any CLB or lOB clock input

• Timing is based on the XC3042, for other devices see XACT timing calculator.

2-42

Units

CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

Speed Grade
Description

Symbol

-70

Min

Max

Units

-125

-100

Min Max

Min Max

Combinatorial Delay

Logic Variables a, b, c, d, e, to outputs x or y

1

TllO

9

7

5.5

ns

8

TCKO

6

5

4.5

ns

TOLO

13

10

8

ns

Sequential delay

Clock k to outputs x or y
Clock k to outputs x or y when Q is returned
through function generators For G to drive x or y
Set-up time before clock K

Logic Variables
Data In
Enable Clock
Reset Direct inactive

a,b,c,d,e
di
ec
rd

8

6

TICK
TOICK
TECCK

5
7
1

7
4
5
1

3
4.5
1

ns
ns
ns
ns

3
5
7

TCKI
TCKOI
TCKEC

0
4
0

0
2
0

0
1.5
0

ns
ns
ns

11
12

TCH
TCl
FClK

5
5
70

4
4
100

3
3
125

ns
ns
MHz

13
9

TRPW
TRIO

8

TMRW
TMRO

25

2
4

6

Hold Time after clock k

Logic Variables
Data In
Enable Clock

a, b,c,d, e
di
ec

Clock

Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (rd)

rd width
delay from rd to outputs x or y

6

ns
ns

17

ns
ns

6

7

8

7

Global Reset (RESET Pad)'

RESET width (Low)
delay from RESET pad to outputs x or y

21
23

20
19

'Timing is based on the XC3042, for other devices seeXACT timing calculator.
Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

2-43

II

XC3000 Logic Cell Array Family
lOB SWITCHING CHARACTERISTIC GUIDELINES
1/0 BLOCK (I)

1/0 PAD INPUT

-----®-TPIDT--=_f===~-teD

TplCK

110 CLOCK

(lK/OK)

14---- @

TIOL -----<~----

VO BLOCK (RI)

1/0 BLOCK (0)

1/0 PAD OUTPUT

(DIRECT)

1/0 PAD OUTPUT

--------------------,r0) TOKPO

(REGISTERED)

J--1r-0-TT-SON--@-TT-~j I

1/0 PADTS

1/0 PAD OUTPUT

--------~(~

____________~r__
110527C

PROGRAM-CONTROLLED MEMORY CELLS

Vee

.,
3· STATE

--to-.:.:~~~--+--------=:::.J;L>---t-,

(OUTPUT ENABLE)

OUT

~,!---,,'--"
.,
:;

----+-------,
"----+---1

DIRECT IN

~,',-:

REGISTERED IN

~,,,~

.,

or
LATCH

.ok

j}

jk

L-._ _.l-_ _ _ _ _ _ _ (GLOBAL RESET)

~M U~LT '~P LE~LXE DR jjf-.. -. ----------i~:
o.

PROGRAMMABLE INTERCONNECTION POINT or PIP

2-44

110S01A

lOB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

-100

-70
Description
Propagation Delays (Input)
Pad to Direct In (i)
Pad to Registered In (q) with latch transparent
Clock (ik) to Registered In (q)

Symbol

Max

Min

Max

Min

4
17
4

Max

Set-up Time (Input)
Pad to Clock (ik) set-up time

1

T plCK

Propagation Delays (Output)
Clock (ok) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(Slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)

7
7
10
10
9
9
8
8

TOKPO
T OKPO
TOPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON

Set-up and Hold Times (Output)
Output (0) to clock (ok) set-up time
Output (0) to clock (ok) hold time

5
6

TOOK
TOKO

10
0

9
0

8
0

ns
ns

11
12

T IOH
TIOl
FClK

5
5
70

4
4
100

3
3
125

ns
ns
MHz

13
15
15

TRRI
T RPO
TRPO

17

20

16

10
27
6
23
8
25
12
29

13
33
9
29
8
28
14
34

25
35
53

3
16
3

ns
ns
ns

4

Global Reset Delays (based on XC3042)
RESET Pad to Registered In (q)
RESET Pad to output pad (fast)
(slew-rate limited)

6
21
5.5

Units

TplO
TpTG
TIKRI

Clock
Clock High time
Clock Low lime
Max. flip-flop toggle rate

3

Min

-125

24
33
45

ns

9
24
5
20
7
24
11
27

23
29
42

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
For larger capacitive loads, see page 6-9.
Typical slew rate limited output rise/fall limes are approximately four times longer.
A maximum total external capacitive load for simUltaneous fast mode switching in the same direction
is 200 pF per power/ground pin pair. For slew-rate limited outputs this total is four times larger. Exceeding this
maximum capacitive load can result in ground bounce of >1.5 V amplitude, <5 ns duration, which might cause
problems when the LCA drives clocks and other asynchronous signals.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured
with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (.ik)
In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value.
Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately
before the internal clock edge (ik)will not be recognized.
For a more detailed description see the discussion on "LCA Performance" in the Applications Section.

2-45

III

XC3000 Logic Cell Array Family

GENERAL LCA SWITCHING CHARACTERISTICS

~"-------IIII"_---.(0TRW)_ _ _ _ _ _ __

RESET

MO/M1/M2

DONE/PROG

------~~'~~.~-------------------------------------------­
~®TPGW~

____--1___[0

INIT
(OUTPUT)

USER STATE

-

TpGI

______C_LE_A..R~,..S-TA-T-E-----........../
n

CONFIGURATION STATE

\~-.............../

Vee (VALID)

r-NOTE 3-+j
-----------------------------------------------~\
Ir~t-----•\.. ____ iP
VCCPD
/~

110528

-70
Description
RESET (2)

DONEIPROG

Symbol

MO, M1, M2 setup lime required
MO, M1, M2 hold time required
RESET Width (Low) req. for Abort

2
3

Width (Low) required for Re-config.
INIT response after Dip is pulled Low

Min

4

TMR
TRM
TMRW

1
1
6

5
6

TpGW
TpGI

6

PWRDWN (3) Power Down Vcc

VCCPD

-100

Max

Min Max
1
1
6

Min Max
Ils
IlS
IlS

1
6

6
7

2.3

Units

°

6
7

2.3

-125

7
2.3

IlS
IlS
V

Notes: 1. At power-up, Vee must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a > 1-~s High level on RESET, followed by a >6-~s Low level on RESET and DIP after Vee has
reached 4.0 V.
2.

RESET timing relative to valid mode lines (MO,

M1, M2) is relevant when RESET is used to delay configuration.

3. PWRDWN transitions must occur while Vcc >4.0 V.

2-46

MASTER SERIAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CClK

(OUTPUT)

SERIAL DATA IN

SERIAlDOUT

(OUTPUT) _ _ _ _ _J

'-_ _ _ _ _-..1 ' - -_ _ _ _ _-1

' -_ _ _ _ _ _ __

1105 29

Speed Grade

-70

Description
CCLK3

Data In setup
Data In hold

Symbol
1
2

TDSCK
TCKDS

Min
60
0

Max

-100

-125

Min Max

Min Max

60
0

60
0

Units

II
ns
ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vee rise time of> 100 ms, or a non-monotonically
rising Vcc may require> 1-IlS High level on RESET, followed by a >6-J.lS Low level on liESET and oil' after Vcc has
reached 4.0 V.
2. Configuration can be controled by holding RESET Low with or until after the
is High.
3. Master-serial-mode timing is based on slave-mode testing.

2-47

mrr of all daisy-chain slave-mode devices

XC3000 Logic Cell Array Family

MASTER PARALLEL MODE PROGRAMMING SWITCHING CHARACTERISTICS

AO-A15

ADDRESS for BYTE n

(OUTPUl)

ADDRESS for BYTE n + 1

DO--D7

RClK
(OUTPUl)

~~:======~=-7-C-C-lK-S---------------~'~~---

/

CClK
(OUTPUl)
DOUT
(OUTPUl)

D7
BYTE n-1
110530

-70
Description
RCLK

To address valid
To data setup
To data hold
RCLK high
RCLK low

Symbol

1
2
3

T RAC
T DRC
T RCD
T RCH
TRCl

-100

-125

Min

Max

Min

Max

Min

Max

0
60
0
600
4.0

200

0 200
60
0
600
4.0

0
60
0
600
4.0

200

Units

ns
ns
ns
ns
Ils

Notes: 1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a > 1-~ High level on RESET, followed by a >6-~ Low level on RESET and Dff> after Vee has
reached 4.0 V.
2. Configuration can be controlled by holding RESET Low with or until after the lNIT of all daisy-chain slave-mode devices
is High.

This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.

2-48

PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

..

\

/

(

CS1ICSO

CS2

I

\

,,

,»

WS

00-07

CCLK

'...

'..

.'

ROYIBUSY

OOUT

,.

II

'" ---,

'"---,

_______________________ 1,,

_-IX'--~x'"__ _____~

I..----'X'---_L
1105 lOA

-70
Description
Write

ROY

Notes:

Symbol

Min

Max

-100

-125

Units

Min Max

Min Max

Effective Write time required
(CSO • CS1 • CS2 • WS)

1

TCA

100

100

100

ns

DIN Setup time required
DIN Hold time required

2
3

Toe
Tco

60
0

60
0

60
0

ns
ns

ROY/BUSY delay after end of WS

4

TWTRB

Earliest next WS after end of BUSY

5

TRBWT

0

BUSY Low time generated

6

TBUSY

2

60

60

2

9

2

ns
ns

0

0

9

60

9

CCLK
Periods

1. At power-up, Vee must rise from 2.0 V to Voc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of >100 ms, or a non-monotonicall)
rising Vee may require a> 1-1lS High level on 11ES"ET, followed by a >6-1lS Low level on RESET and DIP after Vee has
reached 4.0 V.
2. Configuration must be delayed until the

lN1T of alilCAs is

High.

m

to CCLK cycle for the new byte of data depends on completion of previous byte processing and
3. Time from end of
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.

This timing diagram shows very relaxed requirements:
Data need not be held beyond the rising edge ofWS. BUSY will go active within 60 ns after the end ofWS. BUSY will stay
active for several microseconds. WS may be asserted immediately after the end of1JUSY.

2-49

XC3000 Logic Cell Array Family

SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS

::

~0 '=t:I4_@_2_"[_re~ re" ___.'.f*,:", '~ '=j~_"[_C _L r___
___

(OUTPUT)

l

BIT N -1

BIT N

-70
Description
CCLK

To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency

Symbol

3
1
2
4

5

Tcco
Tocc
TCCD
TCCH
TCCL
Fcc

Min

-100

Max

5.0
10

-125
Min Max Units

Min Max

100

100
60
0
0.05
0.05

110531

60
0
0.05
0.05

5.0
10

100
60
0
0.05
0.05 5.0
10

ns
ns
ns
J.l.S
J.l.S
MHz

Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the

fiiIlT of all LCAs is High.

3. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vcc rise time of > 100 ms, or a non-monotonically
rising Vcc may require a> 1-lls High level on RESET, followed by a >6-lls Low level on RESET and DIP" after Vcc has
reached 4.0 V.

PROGRAM READBACK SWITCHING CHARACTERISTICS
DONEIPROG
(OUTPUT)

____-LI___________________________________ _

RTRIG(Mo)

CCLK(1)
RDATA
(OUTPUT)

X1753

-70
RTRIG
CCLK

Notes:

Description
RTRIG High

1

TRTH

250

RTRIG setup
RDATA delay
High time
Low time

2
3
5
4

TRTCC

200

Symbol

TCCRD
TCCH
TCCL

Min

Min Max

250

5

100
0.5
0.5

1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (MO positive transition) shall not be done until after one clock following active 1/0 pins.
3. Readback should not be initiated until configuration is complete.

2-50

Min Max Units
250
ns

200

200
100

0.5
0.5

-125

-100

Max

5

0.5
0.5

100

ns
ns

5

J.l.S
J.l.S

E:XIUNX
PGA PIN-OUTS

2

3

4

5

6

7

8

9 10 11

@@@)1@@@)@l@)@@@
1@@@)Q@;)(@C@@@@@@

A
B

O@ffi
D 00
E 000
F 008
GOOO
H 00
J OCID

@8@

c

8

7

6

5

4

3

2

1

A
B

@® c
@@)

TOP

11 10 9

O@@
8®@

V~EW

D

E
F

Component

O~@ G

Side

@O

H

080

~@ J
O®@OO@OOO~@ K

K

II

L
2

3

4

5

6

7

8

9 10 11

ED

= Index pin which mayor may not be electrically connected to pin C2

(NC)

= Pin Not Connected for XC3020, unlabeled pin = unrestricted I/O pin

11 10 9

8

7

6

5

4

6

5

3

2

1

PG84 Pin-outs-XC3042, XC3030, XC3020

I

2

3

4

5

6

7

8

14 13 12 II 10 9

9 10 II 12 13 14

@@)@)OOOOOOO@)@)@)@ A
B @OOOOOOOOOOO®® B
c 0@Oe008800eO®0 c
D <@@8
80~ D
A

~ ~i8 TO~ VH~W 8~8 ~
G

H

J
K

L

Component

@)(@8

@l@e
@)@O
@l00
@@e

Side

80(l@

eoo
000
000
eO@)

M 0@~8@®e8®08®~0
N @@O@O@®@~O®O~O
p @OOO@)~O@@O@O@@Y
I

2

3

4

5

6

7

8

G

H

J
K

L
M
N
p

8

7

4

3

2

I

@)@)@)@)OOOOOOO@)@)@ A
B ®®OOOOOOOOOOO@ B
C 0®Oe008800eO@0 c
D ~08
8@<@ D
E O@O
OO@'E
F 000
OW@ F
A

G

~
K
L

@08~OTTOM V~[EW 8(@@
8@i@
Solder Side O@@)

886
000

00@l
e@@

@oe

G
H

J

K

L

0@®80®8e®@8~@0 M
N O~O®O~@®@O@O®@ N

M

p

9 10 II 12 13 14

@Y@0@)0@l@l0@@)000@
14 13 12 II 10 9

(NC) = Pin Not Connected for XC3042, unlabeled pin = unrestricted I/O pin

PG132 Pin-outs-XC3064, XC3042-PG, -PP

2-51

8

7

6

5

4

3

2

I

p

XC3000 Logic Cell Array Family

PGA PIN-OUTS (cont'd)
1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

16 15 14 13 12 II 10 9

A

@@OOOOOOOOOOO@@ A
B O@OOOOOOOOOOO®@)O B
c @@800000000008®0 c
D @)08@00088000080~

D

8

7

6

5

4

3

2

I

A@@OOOOOOOOOOO@@
A
B O&)®OOOOOOOOOOO@O B
C 0®800000000008@)@ c
D ~08000088000@80@)

D

@)O@ E
@OO E E OO@
F O(@O
000 F F 000
O(@O F
G 000
lrOlPl V~IEW
000 G
H @@)8
Component
8@0 H ~ 8i~ [8l0lrlrOM V~IEW ~~~ ~
J 008
800 J
Solder Side
6~~ ~
K @@JO
Side
000 K ~
L O@O
000 L L 000
O@O L
M @)O@
000 M M 000
@O@) M
N @08®00088000®800 N N008®00088000@80@N
p @@)801®00®000®08@0 p
p 0@80®000®001®08@)@ p
R 08®0®0@~@~000~®0 R RO®~000~@~@0®0®80R
T @@@OO@OOOOOOO@@@ T
T @@@OOOOOOO@OO@@@ T
E

@O~

886

I

2

3

4

5

6

7

8

9 10 II 12 13 14 15 16

16 15 14 13 12 II 10 9

(NC) ~ Pin Not Connected, unlabeled pin ~ unrestricted 1/0 pin

PG175 Pln-outs-XC3090-PG, -PP

2-52

8

7

6

5

4

3

2

I

PHYSICAL DIMENSIONS

PIN

#1IDLOCATION
(EITHER POS.)

7

~m
0.050TVP
NON-CUM

----j

~---s-;~-~ ~J®"~
29
28

III

e JA -- 40-451 "CfW
°CfW
a
""JC
--10-1

LEAD CO-PLANARITY
±0.002
DIMENSIONS .
IN INCHES
1105 42B

44- PI"n PLCCPaCkage=-_ _ _ _ _ _ __

PIN NO. 1NO 1 IDENTIFIER
PIN
.

0.045

X~4~5-0~~V:::::::~::::::::::~~:::::::=:~~U
61

CCLK
DOUTIIO

0.990
± 0.005
0.954
±0.004

Vee

Vee

LEAD PITCH
0.050 TYPICAL

RESET
DONE

jt~rcr~~TOO.9~54T±~no.~oo~,~

0.028

==Ftr-1: __~_

LEAD CO-PLANARITY
± 0.002
DIMENSIONS
IN INCHES

0.990 ± 0.005
TOP VIEW

110534C

68- P"
In PLCC Package

2-53

XC3000 Logic Cell Array Family

PHYSICAL DIMENSIONS (Continued)

L
IL.

PINNO.1

0.045

x

450",

0.045

PIN NO.1 IDENTIFIER

11

75

PWRDWN

CCLK
DOUT/IO

1 .190

±o.005

1.000

1.154
±0.004

Vee

TYP

Vee

1.120
±0.010
0.D18

.-L

T

M1
MO

-= "-

DONE
RESET

il

0.028 ~=+=~~,

~t--'-'--33_1.154±0.004_~53
u

,UUUQue

__

-1-

joI ~l- - - - - - - - 1 . 1 9 0 ± O.005--------1~.

LEAD PITCH
0.050 TYPICAL

TOP VIEW
DIMENSIONS IN INCHES

E>JA= 30-35 °CIW
E>Jc= 3-7 °CIW

1105 36C

84-Pin PLCC Package

0.130
±0.010
1 1 + . - - - - - - , . , 0 0 ± 0.012 sar-------->l·1

~

1.000 ± 0.010

I+--

0.100TYP

ffi ffi

.~

:t:t
'-V 'V

0.100
TYP

ffiffi

:t:t

~

I

'V 'V

*H ~

~H
G

II r

r

1.00a
±0.01 o

-E:rE

~

INDEX PIN

r
r
/'L>.

{J

I

.L
TA

±006~8DIA

r
r

r

II

r

r.

lIr.

1"':\
'-../

f::\
~

'-J
10

1

J.-o.oso

E>JA = 30-35 °CIW

TYP.0.070
DlA~.08 MAX

/

±O.010

11

BOTTOM VIEW

NOTE: INDEX PIN MAY OR MAY NOTSE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES

E>JC= 4-7 'CIW

84-Pin PGA Package

2-54

110535C

PHYSICAL DIMENSIONS (Continued)

0.009 ± 0.005
81

0.705 ± 0.010

10------ 0.742 R E F - - - - - . j

LEAD PITCH
0.0256TYP

TOP VIEW
"'5-7"

~ ~ru ~IDnnonnonnonnnnouu
0.5H 0.006

L

.

II

////

~~<'//~

0_1181

°S:TING PLANE

0.031 ± 0.006

4
DIMENSIONS IN INCHES

9 JA = 55-70° CIW

9 Jc =5-WCIW

X1747

100-Pln PQFP Package

1----------1.275> 0.020SQ.----------I

0.0650 ± O.OOSO
LEADFRAME
0.0045 MIN
0.0080 MAX

0.008 MIN
0.013 MAX

DEVITREOUS
SOLDER GLASS

r

MARKING

0.580 TO 0.650
CAVr!Y SIZE

DEPC

4X 0.020R

LEAD PITCH 0.025 TYPICAL

BOTTOM VIEW

9JC

=5-8° C/W

0.0300 ±O.OOSO

0.0500 .0.0050
0.120 MAX

DIMENSIONS IN INCHES

(LID SIDE UP)
(DIE FACING UP)

e JA = 40-50° C/W

0.145 MAXJ

SIDE VIEW
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS,
TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES (619) 425-3970 CHULA VISTA, CA.
X1750

100-Pln CQFP Package

2-55

XC3000 Logic Cell Array Family
PHYSICAL DIMENSIONS (Continued)
0.040 X 45"

1

4PLCS

2

3

..

5

6

7

8

9

10

11

12

13

PIN
KOVAR

14

1

0000000,000000
00000000000000
M00000000000000
000
000
000
000
000
000
000
+
000
000
000
000
000
000
0000
c 008
000000
000 000000
000000
p

0.Q18 ± 0.002 DIA~
132 PLCS

0

TVP 0.070 DIA

± 0.005

N

L

K

J

H

0.645

± 0.006

1.460

± 0.015

G
F

E

B

0.070

± 0.01 SO

l
_

U~~BO

~

~W-±OOO9
I.m

---±°J.ci87·----->!

10-'.

1.300TYP------->!

!---------±\,~~5-------1
BOTTOM VIEW

110538B

132-Pin PGA Package

1

2

3

"

5

6

7

6

9

10

11

12

13

14

1.460
±O.Ol

CHAMFER
0.039 X4S'"

REF

I.

r-

0.050

± 0.004
0.100 ±0.002

.1

1.300±0.012------oI.I
1.460 ± 0.015--'-~------i-.

BOTTOM VIEW

06C
±

DIMENSIONS IN INCHES

0.197

tl

0.070
1105 438

132-Pin PPGA Package

2-56

PHYSICAL DIMENSIONS (Continued)
, - - - - - - SEAnNG PLANE
0.031

~ g:gg:

0.063 REF

•

PIN#1ID.

40

9JA = 30-35" erN
9JC = 3-5" erN

X1159A

DIMENSIONS IN INCHES

160-Pin PQFP Package

LEADFRAME
00045 MIN
0.0080 MAX

J1J-

0.0650 ± 0.0050

DEVITREOUS
SOLDER GlASS

.~[

L

0145

BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

0.0500

± 0.0050

0.120 MAX

LEAD PITCH 0.025 TYPICAL

9JA = 35-45" CrN
9JC = 3-5" erN

MAXJ~! ~

0.0300 ± 0.0050

SIDE VIEW

DIMENSIONS IN INCHES
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS, TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES INC. (619) 425-3970 CHULA VISTA, CA.
X1556

164-Pin CQFP Package

2-57

XC3000 Logic Cell Array Family

PHYSICAL DIMENSIONS (Continued)
TOPYIEW

o

+----

INDEX (A,)

e JA =16.4 °CIW

--tt---t- eJC =O.5-1.0°CIW

0.025 REF

WE,O METALIC HEATSINK
ELECTRICALLY CONNECTED TO VC

PIN KOVAR
0.005 R. TYP.

0.0,6 REF

,. GGGGGGGGGGGGGGG o - t t - - - - - r
15 G0GGGGGG,GGGGGG0
TYP DIA
MG0GG0GGGGGGG0000
13 GGGG
12 GGGG
GGGG
11GGGG
GGGG
lOGGGG
GGGG
,.660
GGGG ±
rt' G ~-=G---::G~_ _ +
±
sa
,.
GGGG
'GGGG
7GGGG
GGGG
GGGG
·GGGG
GGGG
·GGGG
4GGGG
DIELECTRIC
3G0GG
COAT
2G0GG
STAND-OFF PIN
4 PLACES
'GGGG
0

0.070
± 0.005

0.845

0.009

0.Q16

±0.Q15

T

R

P

N

BOTTOM VIEW
110537C

175·Pln PGA Package (Ceramic)
2-58

E:XlUNX
PHYSICAL DIMENSIONS (Continued)
TOP VIEW

0

0

0

0

0

0

0

0

0

000

0

0

0

0

0

0

0

0

0

o

0

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

o

0

o

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

I

-tI

0

o

0

0

o

0

0

0

0

o

0

0

0

0

0

0

0

o

0

0

0

0

0

0

o

0

0

0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

o
o

0

0

0

0

0

0

0

0

0

0

0

0

6 JA =22'C/W
6Jc= 1.6 'CIW

r-

•

0.071 ± 0.006

,0.070 to.008

0.046

REFl

"~ !.~1o~ ,-"

PIN
KOVAR

0.005

1YP

r.

"

0.100 TIP

16
15
14
13
12
11
10

r
rrmTTffilT
UlhO'O~OIA
T

OJ97

l

@ @ @ @ @ @ @ @ @@@@@@@e
@ @@ @ @ @ @ @ @)@@@@@@@
@ @ @ @ @ @ @ @ @@@@@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
I
@@@@
@@@@
1.660sa
±0.o16
9
@@@@
@@@@
±liJ.~2
8
@@@@
@@@@
7 @@@@
@@@@
~ COAT
DIELECTRIC
I
6 @@@@
@~@)@
5-@@@@
@@@@
4-@@@@
@@@@
3
@@@@@@@@ @@@@@@@@
2@@@@@@@@ @@@@@@~@
tft@@@@@@@ @@@@@@~ )0

-+-

T

R

0.070
± 0.005
DIATYP

P

N

M

L

K

J

H

G

F

1

E

0

C

B

A
BOTTOM VIEW

~ 4STAND.OFF
PIN
PLACES
1991018

175-Pin PPGA Package (Plastic)

2-59

Component Selection and
Ordering Information
COMPONENT AVAILABILITY (9/91)

XC2064

XC2018

XC3020

XC3030

f-:-::':+---::--

XC3042

XC3084

XC3090

X1104A

COMPATIBLE PACKAGE OPTIONS

XC1736A/XC1765-PDBC Plastic B-Pin Mini-DIP
-40°C to B5°C
XC1736A/XC1765-CDBM Ceramic B-Pln Mini-DIP
-55°C to 125°C

A range of LCA devices is available in identical packages
with identical pin-outs. A design can thus be started with
one device, then migrated to a larger or smaller chip while
retaining the original footprint and PC-board layout.

LCA Temperature Options
Symbol

Description

C
I

Commercial
Industrial
Mil Temp
Military

M
B

ORDERING INFORMATION
Example:

~~~~
Toggle
Ra1e

=:l]

Temperature

Examples:

O°Cto 70°C
-40°C to 85°C
-55°C to 125°C
MIL-STD-883, Class B

r

PC 68:
PC 84:
PG84:
PO 100:
PG 132:
PO 160:

2064-2018-3020-3030
2018-3020-3030-30423064-3090
2018-3020-3030-3042
3020-3030-3042
3042-3064
3064-3090

Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.

XC3020-70PC68C

Temperature
Range

XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more 1/0.

Number of Pins

Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out different from a PGA device.

Package Type

2-60

XC2064/XC2018
Logic CeW Array
M

Product Specification
FEATURES

Part
Number

Logic
Capacity
(gates)

• Fully Field-Programmable:
• 1/0 functions
• Digital logic functions
• Interconnections
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent
to 1200 and 1800 gates
• Standard product availability
• 100% factory-tested
• Selectable configuration modes
• Low-power, CMOS, static-memory technology
• Performance equivalent to TTL SSI/MSI
• TTL or CMOS input thresholds
• Complete development system support
• XACT Design Editor
• Schematic Entry
• XACTOR In-Circuit Emulator
• Macro Library
• Timing Calculator
• Logic and Timing Simulator
• Auto Place I Route

XC2064
XC2018

1200
1800

Configurable
Logic
Blocks

User
II0s

64
100

58
74

Configuration
Program
(bits)

12038
17878

The LCA logic functions and interconnections are
determined by data stored in internal static-memory cells.
On-chip logic provides for automatic loading of
configuration data at power-up. The program data can
reside in an EEPROM, EPROM or ROM on the circuit
board or on a floppy disk or hard disk. The program can be
loaded in a number of modes to accommodate various
system requirements.

ARCHITECTURE
The general structure of a Logic Cell Array is shown in
Figure 1. The elements of the array include three categories of user programmable elements: 1/0 Blocks (lOBs),
Configurable Logic Blocks (CLBs) and Programmable
Interconnections. The II0Bs provide an interface between
the logic array and the device package pins. The CLBs
perform user-specified logiC functions, and the interconnect resources are programmed to form networks that
carry logic signals among the blocks.

DESCRIPTION
The Logic CelJTM Array (LCATM) is a high density CMOS
integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:
InpuUOutput Blocks, logic blocks and Interconnect. The
designer can define individual 1/0 blocks for interface to
external circuitry, define logic blocks to implement logic
~ functions and define interconnection networks to compose
larger scale logic functions. The XACTTM Development
System provides interactive graphic design capture and
automatic routing. Both logic simulation and in-circuit
emulation are available for design verification.

LCA configuration is established through a distributed
array of memory cells.The XACT development system
generates the program used to configure the Logic Celi
Array which includes logic to implement automatic
configuration.
Configuration Memory
The configuration of the Logic Celi Array is established by
programming memory cells which determine the logic
functions and interconnections. The memory loading
process is independent of the user logic functions.

The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and
speed grades.

2-61

II

XC2064/2018 Logic Cell Array

affected by extreme power supply excursions or very high
levels of alpha particle radiation. In reliability testing no
soft errors have been observed, even in the presence of
very high doses of alpha radiation.

The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Based on this design,
which has been patented, integrity of the LCA configuration memory is assured even under adverse conditions.
Compared with other programming alternatives, static
memory provides the best combination of high density,
high performance, high reliability and comprehensive
testability. As shown in Figure 2, the basic memory cell
consists oftwo CMOS inverters plus a pass transistor used
for writing data to the cell. The cell is only written during
configuration and only read during readback. During
normal operation the pass transistor is "off" and does not
affect the stability of the cell. This is quite different from the
normal operation of conventional memory devices, in
which the cells are continuously read and rewritten.

Input/Output Block
Each user-configurable I/O block (lOB) provides an interface between the external package pin of the device and
the internal logic. Each I/O block includes a programmable
input path and a programmable output buffer. It also
provides input clamping diodes to provide protection from
electro-static damage, and circuits to protect the LCA from
latch-up due to input currents. Figure 3 shows the general
structure of the I/O block.
The input buffer portion of each I/O block provides threshold detection to translate external signals applied to the
package pin to internal logic levels. The input buffer
threshold of the I/O blocks can be programmed to be
compatible with either TTL (1.4 V) oreMOS (2.2 V) levels.

The outputs Q and Q control pass-transistor gates directly.
The absence of sense amplifiers and the output capacitive
load provide additional stability to the cell. Due to the
structure of the configuration memory cells, they are not

1/0 BLOCK

g Og

D
CONFIGURABLE
LOGIC BLOCK~

-[}
-[}
-[}
-[}
-[}
-[}
-[}

o

0 0 0

0 01 0 0
0 OJ 0 0
0 0 0 0
..

INTERCONNECT AREA

Figure 1. Logic Cell Array Structure

2-62

•

110401

l:XlllNX
The buffered input signal drives both the data input of an
edge-triggered D flip-flop and one input of a two-input
multiplexer. The output of the flip-flop provides the other
input to the multiplexer. The user can select either the
direct input path or the registered input, based on the
content of the memory cell controlling the multiplexer. The
110 Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input.

the 110 block output buffer. Each 110 block output buffer is
controlled by the contents of two configuration memory
cells which turn the buffer ON or OFF or select 3-state
buffer control. The user may also select the output buffer
3-state control (I/O block pin TS). When this I/O block
output control signal is High (a logic "1"), the buffer is
disabled and the package pin is high-impedance.

Output buffers in the I/O blocks provide 4-mA drive for high
fan-out CMOS or TIL-compatible signal levels. The
output data (driving I/O block pin 0) is the data source for

An array of Configurable Logic Blocks (CLBs) provides the
functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix in the

Configurable Logic Block

III
READ or
WRITE

DATA

110512

Figure 2. Configuration Memory Cell

TS (OUTPUT ENABLE)

OUT

IN

D

QI----'

VOCLOCK

~

_ PROGRAM·CONTROLLED
~ - MULTIPLEXER
110403

Figure 3. 110 Block

2-63

XC2064/2018 Logic Cell Array

X

OUTPUTS

INPUTS

A
B
C

0

G

Y

COMB.
LOGIC

F

CLOCK
1104 04

Figure 4. Configurable Logic Block

logic block inputs and the storage element output "0". A
third form of the combinatorial logic (Option 3) is a special
case ofthe 2-function form in which the B input dynamically
selects between the two function tables providing a single

center of the device. The XC2064 has 64 such blocks
arranged in an 8-rowby 8-column matrix. The XC2018 has
100 logic blocks arranged in a 10 by 10 matrix.
Each logic block has a combinatorial logic section, a
storage element, and an internal routing and control section. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
from the interconnect adjacentto the block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
The logic block combinatorial logic uses a table look-up
memory to implement Boolean functions. This tech-nique
can generate any logic function of up to four variables with
a high speed sixteen-bit memory. The propagation delay
through the combinatorial network is independent of the
function generated. Each block can perform any function
of four variables or any two functions of three variables
each. The variables may be selected from among the four
inputs and the block's storage element output "0"'.
Figure 5 shows various options which may be specified for
the combinatorial logic.

A

B

C
D

lithe single 4-variable configuration is selected (Option 1),
the F and G outputs are identical. If the 2-function
alternative is selected (Option 2), logic functions F and G
may be independent functions of three variables each.
The three variables can be selected from among the four

-

rc:-

ANY
FUNCTION
OF 4
VARIABLES

G

OPTION 1
1 FUNCTION OF 4
VARIABLES

2-64

-

EXIUNX
merged logic function output. This dynamic selection
allows some 5-variable functions to be generated from the
four block inputs and storage element Q. Combinatorial
functions are restricted in that one may not use both its
storage element output Q and the input variable ofthe logic
block pin "0" in the same function.

A -~i-"'---l

SET

F---------Io

If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edgesensitive "0" type flip-flop or a level-sensitive "0" latch.
The clock or enable for each storage element can be
selected from:

a

K-~;;--__I

C-~':--__I

• The special-purpose clock input K
• The general-purpose input C
• The combinatorial function G
The user may also select the clock active sense within
each logic block. This programmable inversion eliminates the need to route both phases of a clock signal
throughout the device.

Figure 6. CLB Storage Elememt

The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchronous SET and RESET controls are provided for each
storage element. The user may enable these controls
independently and select their source. They are active

High inputs and the asynchronous reset is dominant. The
storage elements are reset by the active-Low chip RESET
pin as well as by the initialization phase preceding configuration. If the storage element is not used, it is disabled.

1104 06

B

A
B
C

A
ANY
FUNCTION
OF3
VARIABLES

F
C

0

ANY
FUNCTION
OF3
VARIABLES

F

ANY'
FUNCTION
OF3 '
VARIABLES

G

0

A
ANY
FUNCTION
OF3
VARIABLES

0

G
C

0

OPTION 2

OPTION 3

2 FUNCTiONS OF 3
VARIABLES

OYNAM IC SELECTION OF
2 FUNCTIONS OF 3
VARIABLES

Figure 5. CLB Combinatorial Logic Options
Note: Variables 0 and Q can not be used in the same function.

2-65

110405

•

XC2064/2018 Logic Cell Array
The two block outputs, X and Y, can be driven by either the
combinatorial functions, F or G, or the storage element
output Q (Figure 4). Selection ofthe outputs is completely
interchangeable and may be made to optimize routing
efficiencies of the networks interconnecting the logic
blocks and I/O blocks.

and then toggling the states of the interconnect points by
selecting them with the "mouse". In this mode, the connections through the switch matrix may be established by
selecting pairs of matrix pins. The switching matrix combinations are indicated in Figure 7b.
Special buffers within the interconnect area provide periodic signal isolation and restoration for higher general
interconnect fan-out and beUer performance. The repowering buffers are bidirectional, since signals must be
able to propagate in either direction on a general interconnect segment. Direction controls are automatically established by the Logic Cell Array development system software. Repowering buffers are provided only for the
general-purpose interconnect since the direct and long
line resources do not exhibit the same R-C delay accumulation. The Logic Cell Array is divided into nine sections
with buffers automatically provided for general interconnect at the boundaries of these sections. These boundaries can be viewed with the development system. For
routing within a section, no buffers are used. The delay
calculator of the XACT development system automatically
calculates and displays the block, interconnect and buffer
delays for any selected paths.

PROGRAMMABLE INTERCONNECT
Programmable interconnection resources inthe Logic Cell
Array provide routing paths to connect inputs and outputs
of the I/O and logic blocks into desired networks. All
interconnections are composed of metal segments, with
programmable switching points provided to implement the
necessary routing. Three types of resources accommodate different types of networks:
• General purpose interconnect
• Long lines
• Direct connection
General·Purpose Interconnect
General-purpose interconnect, as shown in Figure 7a, is
composed of four horizontal metal segments between the
rows and five vertical metal segments between the columns of logic and I/O blocks. Each segment is only the
"height" or ''width'' of a logic block. Where these segments
would cross at the intersections of rows and columns,
switching matrices are provided to allow interconnections
of metal segments from the adjoining rows and columns.
Switches in the switch matrices and on block outputs are
specially designed transistors, each controlled by a configuration bit.

B

CLB

,,-

,,
• .J

A

Logic-block output switches provide contacts to adjacent
general interconnect segments and therefore to the
switching matrix at each end of those segments. A switch
matrix can connect an interconnect segment to other
segments to form a network. Figure 7a shows the general
interconnect used to route a signal from one logic block to
three other logic blocks. As shown, combinations of
closed switches in a switch matrix allow multiple branches
for each network. The inputs of the logic or I/O blocks are
multiplexers that can be program-med with configuration
bits to select an input network from the adjacent interconnect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable on/yfor input connection. The development system software provides automatic routing of these interconnections. Interactive routing is also available for design
optimization. This is accomplished by selecting a network

B

C

CLB

K

X

Y

CLB

SEE FIG. 7b

0
6+1+1----+1

CLB

110407

Figure 7a. General·Purpose Interconnect

2-66

l':XllINX
2 VERTICAL
LONG LINES
,.----J---., ,-A-,

I I I I

I

AVAILABLE PROGRAMMABLE
SWITCH MATRIX INTERCONNECTIONS
OF GENERAL INTERCONNECT
SEGMENTS BY PIN

I I

I

I
I
I
I

Q-i

O

"0

SWITCH
MATRICES

QQO

O·--lJ.__, ":

-O--t:rT

o

0

~2
3

a

3

..

7

..

6

5

6

~
2

I
I

:

•

3

7

·.

I

a

•

2

I

•

3

7

•

Q-i

-}

0

_
_

QQO
OQ 0

,._,:0

0

2

7

3

•

• •

a

3

•

•

• •
2

~ ~
2

4 HORIZONTAL
GENERAL PURPOSE
INTERCONNECT

2

7

• •

I
I
I

o

S

a

5

0. 0.

x

::

~2

•

7

•

3

7

•

• •

•

3

7

•

• •

I
I

I

I
I
I

I

I I I I

,

5 VERTICAL
GENERAL PURPOSE
INTERCONNECT
BETWEEN SWITCH
MATRICES

' \ PROGRAMMABLE
INTERCONNECT POINTS
(CO NOT USE MORE THAN
ONE PER INPUT PIN)
1104 08

Figure 7b. Routing and Switch Matrix Connections

Long Lines

the global bufferfor a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
blocks. At each block, a configuration bit for the K input to
the block can select this global line as the storage element
clock signal. AHernatively, other clock sources can be
used.

Long-lines, shown in Figure Sa, run both vertically and
horizontally the height or width of the interconnect area.
Each vertical interconnection column has two long lines;
each horizontal row has one, with an additional long line
adjacent to each set of I/O blocks. The long lines bypass
the switch matrices and are intended primarily for signals
that must travel a long distance or must have minimum
skew among multiple destinations.

A second buffer below the bottom row of the array drives
a horizontal long line which, inturn, can drive a vertical long
line in each interconnection column. This alternate buffer
also has low skew and high fan-out capability. The
network formed by this alternate buffer's long lines can be
selected to drive the S, C or K inputs of the logic blocks.

.'
A global buffer in the Logic Cell Array is available to drive
a single signal to all 8 and K inputs of logic blocks. Using

2-67

XC2064/2018 Logic Cell Array

a a
a a
a a
SWITCH
MATRIX

----.J

B

~

L-

X

D CLB

Y

SWITCH
MATRIX

----.J

TW~o~~R~II~~~-

L-

HORIZONTAL
LONG LINE

r-- ~~~~AL~NE
1104 09

Figure 8a. Long Line Interconnect

bottom of the die. Direct interconnections of 1/0 blocks
with CLBs are shown in Figure 8b.

Alternatively, these long lines can be driven by a logic or
I/O block on a column by column basis. This capability
provides a common, low-skew clock or control line within
each column of logic blocks. Interconnections of these
long lines are shown in Figure 8b.

CRYSTAL OSCILLATOR
An internal high speed inverting amplifier is available to
implement an on-chip crystal oscillator. It is associated
with the auxiliary clock buffer in the lower right corner of the
die. When configured to drive the auxiliary clock buffer,
two special adjacent user 1/0 blocks are also configured to
connect the oscillator amplifier with external crystal oscillator components, as shown in Figure 10. This circuit
becomes active before configuration is complete in order
to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. The
feedback resistor Rl between output and input, biases the
amplifier at threshold. It should be as large a value as
practical to minimize loading of the crystal. The inversion
of the amplifier, together with the R-C networks and
crystal, produce the 360-degree phase shift of the Pierce
oscillator. A series resistor R2 may be included to add to

Direct Interconnect
Direct interconnect, shown in Figure 9, provides the most
efficient implementation of networks between adjacent
logic or 1/0 blocks. Signals routed from block to block by
means of direct interconnect exhibit minimum interconnect propagation and use minimum interconnect resources. For each Configurable Logic Block, the X output
may be connected directly to the C or D inputs of the CLB
above and to the A or B inputs of the CLB below it. The Y
output can use direct interconnect to drive the B input of the
block immediately to its right. Where logic blocks are
adjacent to 1/0 blocks, direct connect is provided to the
1/0 block input (I) on the left edge of the die, the output (0)
on the right edge, or both on 1/0 blocks at the top and

2-68

GLOBAL
BUFFER

VERTICAL LONG LINES
(2 PER COLUMN)

HORIZONTAL LONG LINES
(1 PERROW)

II
t;
LU

Z

z

8a:

~

~

/

/

1/0 CLOCKS
(1PER EDGE)

ALTERNATE
BUFFER

OSCILLATOR
AMPLIFIER
Xl205

Figure ab. XC2064 Long Lines, 1/0 Clocks, I/O Direct Interconnect

2-69

XC206412018 Logic Cell Array

the amplifier output impedance when needed for phaseshift control or crystal resistance matching or to limit the
amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be adjusted by the
ratio of C2/C1. The amplifier is designed to be used over
the range from 1 MHz up to one-half the specified CLB
toggle frequency. Use at frequencies below 1 MHz may
require individual characterization with respect to a series
resistance. Operation at frequencies above 20 MHz
generally requires a crystal to operate in a third overtone
mode, in which the fundamental frequency must be suppressed by the R-C networks. When the amplifier does not
drive the auxiliary buffer, these I/O blocks and their package pins are available for general user I/O.
POWER
Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
For packages having more than 48 pins, two Vcc pins and
two ground pins are provided (see Figure 11). Inside the
LCA, a dedicated Vee and ground ring surrounding the
logic array provides power to the I/O drivers. An independent matrix of Vcc and ground lines supplies the interior
logic of the device. This power distribution grid provides a
stable supply and ground for all internal logic, providingthe
external package power pins are appropriately decoupled.
Typically a 0.1 JlF capacitor connected between the Vee
and ground pins near the package will provide adequate
decoupling.

110410

Figure 9. Direct Interconnect

~ EXTERNAL

ON-CHIP

:::

i

ALTERNATE
CLOCK BUFFER

~

o
o

Output buffers capable of driving the specified 4 rnA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads. Multiple Vee and
ground pin connections are required for package types
which provide them.

I*
~"!

R2

..I

lC2

C1

SUGGESTED COMPONENT VALUES
R1 0.5-1 MQ
R2 0-1 Kn

(may be required for low
frequency, phase
shih and/or compensation
level for crystal Q)
C1,C210-40pF
Y1 1 - 20 MHz AT cut series

XTAL1

XTAL2

48 DIP

33

30

68 PLCC

46

43

68PGA

J10

L10

84 PLCC

56

53

84PGA

K11

L11

resonant
1104 11

Figure 10. Crystal Oscillator

2-70

Power Consumption

the sum of capacitive and resistive loading of the devices
driven by the Logic Cell Array.
Internal power supply dissipation is a function of clock
frequency and the number of nodes changing on each
clock. In an LCA the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a 16-bit
binary counter, the average clock produces a change in
slightly less than 2 of the 16 bits. In a 4-input AND gate
there will be 2 transitions in 16 states. Typical global clock
buffer power is about 3 mW I MHz for the XC2064 and 4
mW I MHz for the XC2018. With a ''typical'' load of three
general interconnect segments, each Configurable LogiC
Block output requires about 0.4 mW I MHz of its output
frequency. Graphs of power versus operating frequency
are shown in Table 1 on page 2-83.

The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. Only quiescent power is
required for the LCA configured for CMOS input levels.
The TTL input level configuration option requires additional
power for level shifting. The power required by the static
memory cells which hold the configuration data is very low
and may be maintained in a power-down mode.
Typically most of power dissipation is produced by capacitive loads on the output buffers, since the power per output
is 25 ',lW I pF I MHz. Another component of 1/0 power is
the DC loading on each output pin. For any given system,
the user can calculate the 1/0 power requirement based on

•

GND

+ --+ -- + _. + _. +- -+ -- + --+

GROUND AND
VeeRING FOR
110 DRIVERS

+ -- + --+-- +- -+- -+ --+--+
1
I

I
I

I
I

I
I

1
I

I
I

I

+- -+ -- + -- + --+ -- + --+ --+
I

I

I

I

I

,

I

1

I

I

I

I

I

I

+ -- +--+-- + --+- -+--+ --+
Vee

I
I

I
I

I
I

I
I

I
I

I
I

+ --+ --+-- + --+ -- + --+ --+
:

:

:

:

:

:

:_.;..'++1_____

+--+--+--+--+-- --+--+
I

I
I

t

I
I

I
I

1
I

LOGIC POWER GRID

+ -- +, --+-- + --+-+ --+ --+
"
,

"

+ -- +- -+ --+ --+- -+ --+- -+

GND
1104 12

Figure 11. LeA Power Distribution

2-71

XC2064/2018 Logic Cell Array

PROGRAMMING

Input thresholds for user I/O pins can be selected to be
either TTL-compatible or CMOS-compatible. At powerup, all inputs are TTL-compatible and remain in that state
until the LeA begins operation. If the user has selected
CMOS compatibility, the input thresholds are changed to
CMOS levels during configuration.

Configuration data to define the function and interconnection within a Logic Cell Array are loaded automatically
at power-up or upon command. Several methods of
automatically loading the required data are designed into
the Logic Cell Array and are determined by logic levels
applied to mode selection pins at configuration time. The
form of the data may be either serial or parallel, depending
on the configuration mode. The programming data are
independent of the configuration mode selected. The
state diagram of Figure 12 illustrates the configuration
process.

Figure 13 shows the specific data arrangement for the
XC2064 device. Future products will use the same data
format to maintain compatibility between different devices
of the Xilinx product line, but they will have different sizes
and numbers of data frames. For the XC2064,

POWER-ON DELAY IS
214 CYCLES FOR NON-MASTER MODE-11 TO 33 mS
216 CYCLES FOR MASTER MODE-43TO 130 mS
USER 110 PINS WITH HIC}H IMPEDANCE PULL-UP
HDC = HIGH
LDC= LOW

LOW ON DONE/PROGRAM AND RESET
CLEAR IS
-160 CYCLES FOR THE XC2064-100 TO 320 liS
-200 CYCLES FOR THE XC2018-125 TO 390 liS

1'0414

Figure 12. A State Diagram of the Configuration Process for Power-up and Re-program

11111111
0010
< 24-BIT LENGTH COUNT>
1111

o < DATA FRAME # 001 >
o < DATA FRAME # 002 >

o < DATA FRAME # 003 >

o < DATA FRAME # 159>
o 
1111

DUMMY BITS (4 BITS MINIMUM). XACT 2.10 GENERATES 8
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)

111
111
111
CONFIGURATION
FRAMES
DATA BITS
PER FRAME

B~TS

XC2018

XC2064

196

160

87

71

111
111

HEADER

PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN

POSTAMBLE CODE (4 BITS MINIMUM)

START·UP REQUIRES THREE CONFIGURATION CLOCKS BEYOND LENGTH COUNT
110415

Figure 13. XC2064 Internal Configuration Data Arrangement

2-72

configuration requires 12,038 bits for each device. Forthe
XC2018, the configuration of each device requires 17,878
bits. The XC2064 uses 160 configuration data frames and
the XC2018 uses 197.

MODE PIN
MODE SELECTED

The configuration bit stream begins with preamble bits, a
preamble code and a length count. The length count is
loaded into the control logic of the Logic Cell Array and is
used to determine the completion of the configuration
process. When configuration is initiated, a 24-bit length
counter is set to 0 and begins to count the total number of
configuration clock cycles applied to the device. When the
current length count equals the loaded length count, the
configuration process is complete. Two clocks before
completion, the internal logic becomes active and is reset.
On the next clock, the inputs and outputs become active as
configured and consideration should be given to avoid
configuration signal contention. (A ttention must be paid to
avoid contention on pins which are used as inputs during
configuration and become outputs in operation.) On the
last configuration clock, the completion of configuration is
signalled by the release of the DONE I PROG pin of the
device as the device begins operation. This open-drain
output can be AN D-tied with multiple Logic Cell Arrays and
used as an active-High READY or active-Low, RESET, to
other portions of the system. High during configuration
(HDC) and low during configuration (LDC), are released
one CCLK cycle before DONE is asserted. In master
mode configurations, it is convenient to use LDC as an
active-Low EPROM chip enable.

MO

M1

M2

0

0

0

MASTER SERIAL

0

0

1

MASTER LOW MODE

0

1

1

MASTER HIGH MODE

1

0

1

PERIPHERAL MODE

1

SLAVE MODE

1

1

MASTER LOW ADDRESSES BEGIN AT 0000 AND INCREMENT
MASTER HIGH ADDRESSES BEGIN AT FFFF AND DECREMENT
1104 13

Figure 14. Configuration Mode Selection

Initialization Phase
When power is applied, an internal power-on-reset circuit
is triggered. When Vcc reaches the voltage at which the
LCA begins to operate (nominally 2.5 to 3 V), the chip is
initialized, outputs are made high-impedance and a timeout is initiated to allow time for power to stabilize. This
time-out (11 to 33 ms) is determined by a counter driven
by a self-generated, internal sampling clock that drives the
configuration clock (CCLK) in master configuration mode.
This internal sampling clock will vary with process,
temperature and power supply over the range of 0.5 to
1.5 MHz. LCAs with mode lines set for master mode will
time-out of their initialization using a longer counter (43 to
130 ms) to assure that all devices, which it may be driving
in a daisy chain, will be ready. Configuration using
peripheral or slave modes must be delayed long enough
for this initialization to be completed.

As each data bit is supplied to the LCA, it is internally
assembled into a data word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The last word
must be loaded before the current length count compare
is true. If the configuration data are in error, e.g., PROM
address lines swapped, the LCA will not be ready at the
length count and the counter will cycle through an additional complete count prior to configuration being "done".

The initialization phase may be extended by asserting the
active-Low external RESET. If a configuration has begun,
an assertion of RESET will initiate an abort, including an
orderly clearing of partially loaded configuration memory
bitS. After about three clock cycles for synchronization,
initialization will require about 160 additional cycles of the
internal sampling clock (197 for the XC2018) to clear the
internal memory before another configuration may begin.
Reprogramming is initialized bya High-to-Low transition
on RESET (after RESET has been High for at least 6 J.1.S)
followed by a Low level (for at least 6 Ils) on both the
RESET and the open-drain DONE/PROG pins. This returns the LCA to the CLEAR state, as shown in Fig. 12.

Figure 14 shows the selection of the configuration mode
based on the state of the mode pins MO and M1. These
package pins are sampled prior to the start of the
configuration process to determine the mode to be used.
Once configuration is DONE and subsequent operation
has begun, the mode pins may be used to perform data
readback, as discussed later. An additional mode pin,
M2, must be defined at the start ·of configuration. This
package pin is a user-configurable 110 after configuration
is complete.

2-73

II

XC2064/2018 Logic Cell Array

Master Mode

significant bit of each byte, normally DO, is the next bit in the
serial stream.

In Master mode, the Logic Cell Array automatically loads
the configuration program from an external memory device. Figure 15a shows an example of the Master mode
connections required. The Logic Cell Array provides 16
address outputs and the control signals RCLK (Read
Clock), HOC (High during configuration) and LDC (Low
during configuration) to execute Read cycles from the
external memory. Parallel S-bit data words are read and
internally serialized. As each data word is read, the least

Addresses supplied by the Logic Cell Array can be selected by the mode lines to begin at address
and
incremented to reach the memory (master Low mode), or
they can begin at address FFFF Hex and be decremented
(master High mode). This capability is provided to allow
the Logic Cell Array to share external memory with another
device, such as a microprocessor. For example, if the
processor begins its execution from Low memory, the

°

r-+-------~~~~-+5V

* IF READBACK IS
ACTIVATED. A
5·kQ RESISTOR IS
REQUIRED IN
SERIES WITH Ml

5kQ

USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS

OPTIONAL

DOUT
M2

CCLK

DAISY·CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

HDC
A15

GENERAL·
PURPOSE
USER I/O
PINS

RCLK

A14
A13
A12

} OTHER
I/O PINS

EPROM

OR~~C:ER)

All
AID

AID

RESET

A9

A9

D7

A8

A8

A7

A7

LeA

A6

A6

A5

A5

A4

A4

A3

A3

A2

A2

Al

Al

AD

AD

01

OE
DONE

CE

D/P

DATA BUS

cd

(OO~~
X"'"'' :
D~D7---N-'1-B-YT-E-J~~-----P-R-0-M~:~-----B-YT-E-N--C====XXXXXK~XT--B-YT-E-N-+1-----

(OUT~(iJ-r~

1/8 CCLK

--{

1

\

I14----------...:.~;c;:K:=====j.
8 CCLKs

\'------

(OUTPUT)
C C L K =

(OUf~UUTj

jJ60fBYTENi p70iBYTENj jOOfBYTEN
X1011

Figure 15a. Master Parallel Mode. Configuration data are loaded automaticaly from an external byte wide PROM.
An XC2000 LDC signal can provide a PROM inhibit as the user IIOs become active.

2-74

Logic Cell Array can load itself from High memory and
enable the processor to begin execution once configuration is completed. The Done/PROG output pin can be
used to hold the processor in a Reset state until the Logic
Cell Array has completed the configuration process

Figure 16 shows the peripheral mode connections.
Processor Write cycles are decoded from the common
assertion of the active-Low write strobe (I OWRT), and two
active-Low and of the active-High chip selects (CSa CS1
CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Logic Cell Array will accept one bit of the configuration
program on the data input (DIN) pin for each processor
Write cycle. Data is supplied in the serial sequence
described earlier.

The Master Serial mode uses serial configuration data,
synchronized by the rising edge of CCLK, as shown in
Figure 15b.

Since only a single bit from the processor data bus is
loaded per cycle, the loading process involves the processor reading a byte or word of data, writing a bit of the
data to the Logic cell Array, shifting the word and writing a

Peripheral Mode (Bit Serial)
Peripheral mode provides a simplified interface through
which the device may be loaded as a processor peripheral.

* IF READBACK IS
ACTIVATED. A
5·kn RESISTOR IS
REQUIRED IN
SERIES WITH M1

DURING CONFIGURATION
THE 5 kn M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL·UP.
BUT IT ALLOWS M2 TO
BE USER 1/0.

II

*

+r
I M1I PWRDWN

-b

MO

'---

-

GENERAL·
P URPOSE
USER VO
PINS

DOUT

OPTIONAL
~ DAISY·CHAINED
LCAsWITH

M2

,..

g~~~[i,~Nd"ATIONS

HOC

--< LDC

-

}m","

110 PINS

-

LCA

OPTIONAL

~SLAVELCAs
_

WITH IDENTICAL
CONFIGURATIONS

+5V

II

RESET-r RESET
DIN
CCLK
LOC
DONE- ! - DIP

vpp
Vee
DATA
SERIAL
MEMORY
CLK

r

CE

CEO

o;C1736A1XC1765

"
V

r------------------

---i

P---~

CASCADED
SERIAL
MEMORY

L

(HIGH RESETS THE XC1736A1XC1765 ADDRESS POINTER)

=~

{~~

(OUTPUT)
X1013

Figure 15b. Master Serial Mode. The one time programmable XC1.736A Serial Configuration PROM
supports automatic loading of configuration programs up to 36 Kbits. Multiple XC1736As can be cascaded to
support additional LCAs. An XC2000 LDC signal can provide an XC1736A inhibit as the user II0s become active.

2-75

XC2064/2018 Logic Cell Array

bit until all bits of the word are written, then continuing in
the same fashion with the next word, etc. After the
configuration program has been loaded, an additional
three clocks (a total of three more than the length count)
must be supplied in order to complete the configuration
process. When more than one device is being used in the
system, each device can be assigned a different bit in the
processor data bus, and multiple devices can be loaded on
each processor write cycle. This "broadside" loading
method provides a very easy and time-efficient method of
loading several devices.

LCA in the chain, and the clock is supplied by the lead
device, which is configured in master or peripheral mode.
After the configuration program has been loaded, an
additional three clocks (a total of three more than. the
length count) must be supplied in order to complete the
configuration process.
Daisy Chain
The daisy-chain programming mode is supported by Logic
Cell Arrays in all programming modes. In master mode
and peripheral mode, the LCA can act as a source of data
and control for slave devices. For example, Figure 18
shows a single device in master mode, with 2 devices in
slave mode. The master mode device reads the external
memory and begins the configuration loading process for
all of the devices.

Slave Mode
Slave mode, Figure 17, provides the simplest interface for
loading the Logic Cell Array configuration. Data is supplied in conjunction with a synchronizing clock. For each
Low-to-High input transition of configuration clock (CCLK),
the data present on the data input (DIN) pin is loaded into
the internal shift register. Data may be supplied by a
processor or by other special circuits. Slave mode is used
for downstream devices in a daisy-chain configuration.
The data for each slave LCA are supplied by the preceding

ADDRESS
BUS

The data begin with a preamble and a length count which
are supplied to all devices at the beginning of the configuration. The length count represents the total number of
cycles required to load all of the devices in the daisy chain.
After loading the length count, the lead device will load its

DATA
BUS

• IF READBACK IS
ACTIVATED. A
5·1

LDC

t--

,--r-<

"

GENERAL·
PURPOSE
USER I/O
PINS

DIP
RESET

NOTE: RESET OF A MASTE R
DEVICE SHOULD BE ASSE RTED
BY AN EXTERNAL TIMING
CIRCUIT TO ALLOW FOR LCACCLK
VARIATIONS IN CLEAR STATETIME.

"
"
"
"
"
"

• IF READBACK IS
ACTIVATED. A
5·kll RESISTOR IS
REQUIRED IN
SERIES WITH MI

CE

r - - +5V
5kn
OPEN
f',. COLLECTOR

SYSTEM RESET

>-

t-p-

'--

B

REPROGRAM

M2
HOC

OTHER {
110 PINS

-< RESET

A3

L

GENERAL·
PURPOSE
USER 1/0
PINS

r - - DIP

A2

RESET
D/P

0--

I-

LCA
SLAVE #n

-

D2

r-<

OOUT

OTHER {
1/0 PINS

~ 01

ir

5kn

DIN

"--

-

EPROM
OTHER
110 PINS

CCLK

...

A15

GENERAL·
PURPOSE
USER 1/0
PINS

Hl-

M2

--< RCLK

L--

5kn
DOUT

LCA
SLAVE #1

M2

l

MO 1\.41 PWRDWN

CCLK
DIN

.

I I

...

II

"

I

110420A

Figure 18. Master Mode Configuration with Daisy Chained Slave Mode Devices.
All are configured from the common EPROM source. A well defined termination of
SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)

2-79

III

XC206412018 Logic Cell Array

Flip-flop loop delays for the I/O block and logic block flipflops are about 3 ns. This short delay provides very good
performance under asynchronous clock and data
conditions. Short loop delays minimize the probability of a
metastable condition which can result from assertion of
the clock during data transitions. Because of the short
loop delay characteristic in the LCA device, the I/O block
flip-flops can be used very effectively to synchronize
external signals applied to the device. Once synchronized
in the I/O block, the signals can be used internally without
further consideration of their clock relative timing, except
as it applies to the internal logic and routing path delays.

Logic Block Performance
Logic block propagation times are measured from the
interconnect point at the input of the combinatorial logic to
the output of the block in the interconnect area. Combinatorial performance is independent of logic function
because of the table look-up based implementation.
Timing is different when the combinatorial logic is used in
conjunction with the storage element. For the combinatorial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
clock edge provided to the storage element. The delay
from the clock source to the output of the logic block is
critical in the timing of signals produced by storage elements. The loading on a logic block output is limited only
by the additional propagation delay of the interconnect
network. Performance of the logic block is a function of
supply voltage and temperature, as shown in Figure 22 .

Device Performance
The single parameter which most accurately describes the
overall performance of the Logic Cell Array is the maximum toggle rate for a logic block storage element configured as a toggle flip-flop. The configuration for determining the toggle performance of the Logic Cell Array is shown
in Figure 19. The clock for the storage element is provided
by the global clock buffer and the flip-flop output Q is fed
back through the combinatorial logic to form the data input
for the next clock edge. Using this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from
33-70 MHz, depending on the speed grade used.

Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
minimum delay path for a signal.
The single metal segment used for long lines exhibits low
resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch
wi" have the additional impedance of the switch added to
their normal drive impedance.

Actual Logic Cell Array performance is determined by the
critical path speed, including both the speed of the logic
and storage elements in that path, and the speed of the
particular network routing. Figure 20 shows a typical
system logic configuration of two flip-flops with an extra
combinatorial level between them. Depending on speed
grade, system clock rates to 35 MHz are practical for this
logic. To allow the user to make the best use of the
capabilities of the device, the delay calculator in the XACT
Development System determines worst-case path delays
using actual impedance and loading information.

o
K

Q

1---+---+--

General-purpose interconnect performance depends on
the numberof switches and segments used, the pre-sence
of the bidirectional repowering buffers and the overall
loading on the signal path at a" points along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT development system accounts for a" of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of
R-C delays each approximated by an R times the total C
it drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units after the
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly a" of the capacitance is in the
interconnect metal and switches; the capacitance of the
block inputs is not significant. Figure 21 shows an estimation of this delay.

X,Y

-.-------j

110421

Figure 19. Logic Block Configuration for
Toggle Rate Measurement

2-80

COMBINATORIAL CLB

DESTINATION CLB

Q

INPUTS

GLOBAL
CLOCK

II
1104 22

Figure 20. Typical Logic Path

SWITCH
___ /MATRIX~_
CLB

TIMING: INCREMENTAL
IF Rl = R2 = R3 = RAND Cl = C2 = C3 = C

~

~

+R2 (C2 +C3)

+R3C3

THEN CUMULATIVE TIMING
Tl =3RC

T2

= 3RC + 2RC
=5RC

=3RC

T3

= 3RC + 2RC + lRC

GRC + BUFFER

=6RC
1105238

Figure 21. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.

2-81

XC206412018 Logic Cell Array

1.00

0.80

j

w

Cl
Cl

F!;l 0.60

TYPICAL COMMERCIAL
(+ 5.0 V, 25'C)

.

~

•

0:

oZ

TYPICAL MILITARY
0.40

0.20

,

COMMERCIAL 4.75 V
MIN Mll.J1J'£IY i4AV) - - --:
MIN OMMERCIAl 5.25 V
__ ____ - - - - ,
MIN C
____ - - - - - - MIN MILITARY 15;5_VL _ _ .'

.---L.-------------- -------______________________
_
I

.----- -~-----

______ _

L ____ - - -

-55

-40

-20

o

25

40

70

80

100

125

TEMPERATURE (0G)
X1045

Figure 22. Relative Delay as a function of Temperature, Supply Voltage and Processing Variations.

2-82

100
90
80

L

70
60

/

50

/
150

100

50

/

/

/

/

/

/

/
/

/

/

/

20

/

10

V

/

/

/

/

20 CLB OUTPUTS 4
3 LOCAL SEGMENTS
EACH 3

I

/

/
/

,/

/

It'
./

GLOBAL CLOCK
BUFFER

./

V

/

/

L

/

1 110 OUTPUT
(50pF)0.5
0.5

,//

10

9

/

/

/

/

(rnA)

/

I'

/

'/

1

/

/

L

/

/

V

/

/

/

V
2

1

.9
.8

/

.7
.6

/

.5

~

.4

/
I'

/

II

6

/

/

/

7

/

/

2

/

/

/

/

/

30

20

L

,/

(rnW)

V

/

/

30

(1.25 mWIMHz)

/

/

40

(3mWIMHz)

40

/

.3

/

.2

.1
10

2

20

30

40

50

FREQUENCY MHz
(0.4 mWIMHz) /
1 CLB OUTPUT
3 LOCAL
INTERCONNECT

110427

Table 1. Typical LCA Power Consumption By Element

2·83

XC206412018 Logic Cell Array
DEVELOPMENT SYSTEMS

PIN DESCRIPTIONS

To accomplish hardware development support for the
Logic Cell Array, Xilinx provides a development system
with several options to support added capabilities. The
XACT system provides the following:

Permanently Dedicated Pins.

•
•
•
•
•

GND
One or two (depending on package type) connections to
ground. Ail must be connected.

•
•
•
•
•
•

Vee
One or two (depending on package type) connections to
the nominal +5 V supply voltage. Ail must be connected.

Schematic entry
Automatic place and route
Interactive design editing for optimization
Interactive timing calculations
Macro library support, both for standard Xilinx
supplied functions and user defined functions
Design entry checking for consistency and
completeness
Automatic design documentation generation
PROM programmer format output capabilities
Simulation interface support including automatic
netlist (circuit description) and timing extraction
Logic and timing simulation
In-circuit design verification for multiple devices

PWRDWN
A Low on this CMOS-compatible input stops ail internal
activity, but retains configuration. Ail flip-flops and latches
are reset, ail outputs are 3-stated, and ail inputs are
interpreted as High, independent of their actual level.
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
1-MHz clock. During configuration, PWRDWN must be
High. If not used, PWRDWN must be tied to Vcc'
RESET
This is an active Low input which has three functions.

Designing with the XACT Development System

Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins.

Designing with the Logic Cell Array is similar to using
conventional MSI elements or gate array cells. A range of
supported packages, including FutureNet and VI EWlogic,
provide schematic capture with elements from a macro
library. The XACT development system then translates
the schematic description into partitioned Logic Blocks
and 1/0 Blocks, based on shared input variables or efficient
use of flip-flop and combinatorial logic. Design entry can
also be implemented directly with the XACT development
system using an interactive graphic design editor. The
design information includes both the functional specifications for each block and a definition of the interconnection
networks. Automatic placement and routing is available
for either method of design entry. After routing the interconnections, various checking stages and processing of
that data are performed to insure that the design is correct.
Design changes may be implemented in minutes. The
design file is used to generate the programming data
which can be down loaded directly into an LCA in the user's
target system and operated. The program information
maybe used to program PROM, EPROM or ROM devices,
or stored in some other media as needed by the final
system.

If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.
If RESET is asserted after configuration is complete, it
provides a global asynchronous reset of all lOB and CLB
storage elements of the LCA device.
RESET can also be used to recover from partial power
failure. See section on Re-program under "Special Configuration Functions."
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During a Readback, CCLK is a clock input
for shifting configuration data out of the LCA
CCLK drives dynamic circuitry inside the LCA. The Low
time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be "parked High". An
internal pull-up resistor maintains High when the pin is not
being driven.

2-84

DONEIPROG (DIP)
DON E is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of
configuration, the LCA circuitry becomes active in a synchronous order; DONE goes active High one cycle after
the lOB outputs go active.

XTL1
This user 110 pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
I/O Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.

Once configuration is done, a High-to-Low transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.
MO/RTRIG
As Mode 0, this input and M1, M2 are sampled before the
start of configu ration to establish the configuration mode to
be used.

CSO,CS1,CS2,VVRT
These four inputs represent a set of signals, three active
Low and one active High, that are used to control
configuration-data entry in the Peripheral mode.
Simultaneous assertion of all four inputs generates a
Write to the internal data buffer. The removal of any
assertion clocks in the DO-D7 data. In Master mode,these
pins become part of the parallel configuration byte, D4, 03,
D2, D1. After configuration, these pins are userprogrammable 110 pins.

A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.

RCLK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).

M1/RDATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or Vcc' If Readback is ever used, M 1 must use
a 5-kQ resistor to ground or VcC' to accommodate the
RDATA output.

DO-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master mode. After configuration is
complete they are user programmed I/O pins.

As an active Low Read Data, afteJ configuration is
complete, this pin is the output of the Readback data.

AO-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable I/O pins.

User 110 Pins that can have special functions.
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
110 pin.

DIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input.

HDC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.

DOUT
During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.

LDC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.

Unrestricted User 110 Pins.
110
An 110 pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted
I/O pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 40 to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.

2-85

II

XC206412018 Logic Cell Array

j MODE: 

MA~6~~~ER

I

~~~:

I PE=~~~;~L I ,,~o<~~rO~'~r I

. ~<.H.jGH.».

~,:OCl>

,PLCC :P

A6 (0)
A12 (0)
A7 (0)

2
3

2

A8
(0)
A10 (0)
A.
(0)

5
6

4
5
6

•
..<.~HI

b>..

p~ ~A

USER
OPERATION

B6

GNC

3
4
5

B5
AS
B4

110

8

B3
A3
A2

•

8

B1
12

10

14
15
16

110

11
1.
20

G2

22

H2

15
16

23
24

H1

,. ,.

26
27
28

13

,~~.~!?~
15

MO(Hlur

HOC

I
HIG
HIGH

LDC

.OW:

MO

1:::""",'M2

) (LOW)

MO(L

18

18

20

110

J2
K1

RTRJ~HI)

K2
L2
110

20
22

«HIGH"
22

GND

23

23
24

30
31
32
33
34
35

36
«HIGH»

26

..

.

L3
L4
_~5,

L5
K6
L6

38
39

GND

110
,Kg
L9

24
25
26

29
30

41
42
43

28
29

32
33

45 1 K'
46
110

30

~

31

35

l10

,'.

34

37

F11
10

.

35

37
38

38
39
40
41
42

56
)11
57
>10
58
59
60 ! 81

I'}:':::':' CCLK (I) ZZ

40
41
42

44
45
46

62 1 A10
B9
63
64
A.

110

'"

47

66
67

44

46

68

II'

2B

L2 OR IIC
PROG (I)
UL ORlle

..«HIGH".

"11,

110

4.

Vc
<:02

: .~~HI"H~~.

:,01

I'll:
. "',UO

1(0)

CCL

. :::CCLK(I):}:': .

LK(O)
A1
A2

«fIlGH»

A~

A4
A14
AS

:36

110

A8
B7
Al

«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kn INTERNAL PULL-UP DURING CONFIGURATION

Table 2a. XC2064 Pin Assignments
A PLCC in a "PGA-Footprint" socket has a different signal pinout than a PGA device.

2-86

1104

28A

USER
OPERATION

I co

GND

"

"" (01
1

"""

65

Ie,
1M

2

A6 (01
'12 01

...

110

91
',11 91
91

I Cl
I D2

13
14

VC

30
32

~"-

--"'-

18

38

. <.<> 100 ms, or a
non-monotonically rising Vee may require a >1-11S High level on RESET, followed by a >6-11S Low level on
RESET and DIP after Vee has reached 4.0 V.
2. RESET timing relative to power-on and valid mode lines (MO, M1, M2) is relevant
only when RESET is used to delay configuration.
3. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TelH, TelL.
4. After RESET is High, RESET = DIP = Low for 6 lIS will abort to CLEAR.

2-93

I1s

XC206412018 Logic Cell Array
MASTER SERIAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CCLK

(OUTPUT)

SERIAL DATA IN

SERIAL DOlJT

(OUTPUT) _ _ _ _ _...1

' - _ _ _ _ _- - 1 ' - -_ _ _ _ _...1 ' -_ _ _ _ _ _ __
110529

-50

Speed Grade
Description

CCLK2

Data In setup
Data In hold

Symbol
1

2

TDSCK
TCKDS

Min
60
0

Max

-70
Min
60
0

Max

-100
Min
60
0

Units

Max
ns
ns

Notes: 1. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding m:sET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a > 1-j.ls High level on "RESET, followed by a >6-j.ls Low level on RESET and Dip after Vee has
reached 4.0 V.
2. Master-serial-mode timing is based on slave-mode testing.

2-94

MASTER PARALLEL MODE PROGRAMMING SWITCHING CHARACTERISTICS

AO-A15

(OUTPUl)

XXXXXXX

\:_ _ _ _ _ _ _ _ _ _ _ _ _ _...1
f4----~-~

00-07

RCLK
(OUTPUl)

CCLK
(OUTPUl)

OOUT
(OUTPUl)

II

07
BYTE n-1
110433

~~-----

Speed Grade
Description
RCLK

Note:

From address invalid
To address valid
To data setup
To data hold
RCLK high
RCLK low

Symbol

1
2

3
4
5
6

TARC
T RAC
T ORC
T RCO
T RCH
T RCL

-50
Min

Max

-70
Min

0
200
60
0
600
4.0

Max

-100
Min

60
0
600
4.0

Max
0
200

0
200
60
0
600

Units

ns
ns
ns
ns
ns
(.!S

1. CCLK and DOUT timing are the same as for slave mode.
2. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of >100 ms, or a non-monotonically
rising Vee may require a >1-l1s High level on RESET, followed by a >6-l1s Low level on fiESETand DIP" after Vee has
reached 4.0 V.

This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has no hold time requirement

2-95

XC206412018 Logic Cell Array

PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CS2

CCLK (2)
(OUTPUT)

DIN

DOUT(2)
(OUTPUT)
110434

Speed Grade
Description
Controls1
(CSO, CS1,
CS2, WRT)

Symbol

Min

Max
5.0

Active (last active
input to first inactive)

1

TCA

0.25

Inactive (first inactive
input to last active)

2

TCI

0.25

CCLK2
DIN setup
DIN hold

3

Tccc
Toe
TCD

4
5

-70

-50
Min

Notes: 1. Peripheral mode timing determined from last control signal of the logical AND of (CSO,
active or inactive state.

Max

Units

Min

Max

0.25 5.0

0.25

5.0

0.25

0.25

75
50
0

-100

0

liS
75

75
50

50
0

I1s

ns
ns
ns

'CST, CS2, WAf) to transition to

2. CCLK and DOUT timing are the same as for slave mode.

3. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a > l-l.1s High level on 'RESET, followed by a >6-l.1s Low level on RESET and Dff' after Vee has
reached 4.0 V.

2-96

SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS

DIN~

xxx

BITN

~ 0) Tocc --I- @ TCCD:::J

BITN+1
@TCCL

CCLl<

'I

GTCCH
DOUT
(OUTPUT)

BITN-1

0Tcco""A~

)CX)(~______BI_T_N______
1104 35

Speed Grade
Description
CCLK

To DOUT
DIN setup
DIN hold
High time
Low time
Frequency

Symbol
3
1
2
4
5

-70

-50

Tcco
Tocc
Tcco
TCCH
TCCL
Fcc

Min Max

Min

Max

Min Max

65

65
10
40
0.25
0.25 5.0
2

65
10
40
0.25
0.25

5.0
2

-100

10
40
0.25
0.25 5.0

2

Units

ns
ns
ns
~

Ils
MHz

Note: At power-up, VCC must rise from 2.0 Vohs to Vce min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of> 100 ms, or a non-monotonically
rising Vee may require a> 1-iJS High level on J=iESET, followed by a >6-J.LS Low level on RESET and O/f' after Vee has
reached 4.0 V.

PROGRAM READ BACK SWITCHING CHARACTERISTICS
OONE/PROG
(OUTPUT)

-----Ll-----------------------------------0)
I+-~-T OAT

RTRIG

~~~--~hr,,------------------

CCLK(1)
RDATA
(OUTPUT)

VALID
110436

Speed Grade
Description

Symbol

-50

Min Max

RTRIG

PROG setup
RTRIG high

1
2

TORT
TRTH

300
250

CCLK

RTRIG setup
RDATA delay

3
4

TRTCC
TCCRO

100

Notes:

-70

Min

Max

ns
ns

100

100
100

100

1. CCLK and DOUT timing are the same as for slave mode.
2. DONE/l'ROO output/input must be HIGH (device programmed) prior to a positive transition of RTRIG (MO).

2-97

Units

Min Max
300
250

300
250

100

-100

ns
ns

•

Component Selection,
Ordering Information,
& Physical Dimensions
COMPONENT AVAILABILITY (9/91)

XC2064

XC2018

XC3020

XC3030

1-=:+----;:--

XC3042

XC1736A/XC1765-PDSC Plastic S-Pin Mini-DIP
-40°C to S5°C
XC1736AIXC1765-CDSM Ceramic S-Pin Mini-DIP
-55°C to 125°C

COMPATIBLE PACKAGE OPTIONS

A range of LCA devices is available in identical packages
with identical pin-outs. A design can thus be started with
one device, then migrated to a larger or smaller chip while
retaining the original footprint and PC-board layout.

LCA Temperature Options

Symbol

Description

C
I
M

Commercial
Industrial
Mil Temp
Military

B

Temperature

Examples:

O°Cto 70°C
-40°C to 85°C
-55°C to 125°C
MIL-STO-883, Class B

PG84:
PO 100:
PG 132:
PO 160:

ORDERING INFORMATION
Example:

-"~
Toggle
Rate

2064-2018-3020-3030
2018-3020-3030-30423064-3090
2018-3020-3030-3042
3020-3030-3042
3042-3064
3064-3090

Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.

XC2064-70PC68C

I J ]1
L

PC 68:
PC 84:

,._rure
Range

XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more I/O.

Number of Pins

Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out different from a PGA device.

Package Type

2-98

E:XJUNX
PGA PIN-OUTS

1

A '

2

3

4

rA9\ rAiO\ rAi1\

5

6

7

8

11 10 9

9 10 11

~ tAi3\ rA5\ 6.4\ rA9\ fAI\

8

7

6

5

4

3

2

1

®@@@@)~(@@)@

A

A

B 0@@@@8@l~@@8

B

B

8@@~@)S@@@@0 B

®®

c

C

@@

®~ D

D

~®

c
D
E

F

~~~~~~~~~

OOEB
00
00
08

GOO
H
J

K

L

1'O~ V~IEW

®O E
80 F
@@ G
@O H
@O J

Component

00
O@)O@~@O

A

c

A

0@@)@0@l0@)@@@ B
c OOEB @S@
@~ c
D 00
®O D
E 000 1'O~ V~IEW OO® E
F 008
800 F
G 000 Component @O@ G
H 00
Side
@O H
J O

MA~~~~O~"H

~y,~;

I PE~\~~~:Al

MM;,';~O~';OW I P"ttA

MA·~'~~O:'''r

I AS
I AS
165

'13

«HIGH»

USER
OPERATION

\12
Al 101
_M'IO
AB 10
Al0 (0)

I A4
164
I A3
I A2
16.

I/O

162
I C2
161

PWRllWIiI

I'"
I D2
I Dl

,::::,:::.,:::".:::.:

I/O

"2
IE'
I F2
VC
I'"
I G2

l!!

..~~HIGH~>.

I/O

.~

Jl

MallOWl
M2 OW)

I
-",0 HI(;H

M1 lUW,
MO' Him'

M2

K2

HDC HIGH:
I
LUG
lUW)

l3
K'
l4
JS

'.<~HIGH»

I/O

~
(3.Ne

J6

"-ND

~~HI(l~~~

I K7

IS

• '.

I
D6

RESE

'IIIC
I KB
l.
l10
I K.
1"0
10
Kl'

DONE
•.. ~:

~~~i~!~)

MO

MOlU"
(HIGH)

!~~~I~~

KTl2 OR IIC
RESET

F'ROG'fIl
Xl

ORIIC

Hl0
flO
Gl0
Gn

CSOIll
CST II)

(;.
F.

I/O

VC

I

, e.
-Ill

I
~

RClK
I

I
DUlCIO)

CClK

I

a)

Al
A:
.. «HIGH.».

TSC0026

:': Dll
10
Cll
61
"'0

6.,,"

110

ClKII)

\10

""A1S

~

A4

A14

AB
66

AS

"7

sa

I/O

«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kO INTERNAL PUlL·UP DURING CONFIGURATION

2-108

1637 03

PHYSICAL DIMENSIONS - Conforms to MIL-M-38510 Appendix C, Case P-SC.
0.130

± 0.010
1 o - 1 - - - - - - - , . , 0 0 ± 0.012

SOf-------~'1

~

----

1.000 ± 0.010
0.100 TYP

ffi ffi

ffi ffi

:+::+:
'-V '-V

:+::t
'-V '-V

0.100
TYP

I

l-EfH ~
l~fH ~

1.00o

± 0.0 10

I-E~ ~

INDEX PIN

/

TYP.O.o70

•

D:\.08MAX

t:::'\

.~
'-'

/'1:>.

..fZ
10

11

BOTTOM VIEW
NOTE: INDEX PIN MAYOR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES

XC2018: 84-Pin PGA Package
1'05356

STATIC BURN-IN CIRCUITS

30
1.3 k

8.06 k

1.15k

I}]

1.3 k
82
C2
Bl
Cl
02
01
E3
E2
El
F2
F3

i'wfii5WN

G3

Vee

Gl
G2
Fl
Hl
H2
Jl
Kl
J2
Ll

az

"

XC2018
PGA84

CCLK
DOUT
DIN

Vee

DONEIPROG

REsET

1.5 k

1.5k

All
Cl0
Bl1
Cll
010
011
E9
El0
Ell
Fll
F9
G9
Gl1
Gl0
FlO
Hll
Hl0
Jl1
Kl1
Jl0
Kl0

715

4.99k

NOTES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WATT AT 150'C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R

III

TEMPERATURE CHARACTERISTIC.

[II

TSC0026

30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150'C WITH A
TOLERANCE OF 5%.
163705A

2-109

XC2018B Military Logic Cell Array

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

Absolute Maximum Ratings

Limits

Units

Vcc

Supply voltage relative to GND

-0.5 to +7.0

V

V IN

II1Put voltage with respect to GND

-0.5 to VCC +0.5

V

VTS

Voltage applied to three-state output

-0.5 to VCC +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec@ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating
Power Supply Current
Power-Down Supply Current

VOH

Leakage Current
Input High Level TIL
Input Low Level TIL
Input High Level CMOS
Input Low Level CMOS

IlL
V IHT
V ILT
V IHC
VILC

VOL
leco
ICePD

VCC = 4.5 V, IOH = -4.0 rnA
Vcc = 5.5 V, IOL = 4.0 mA
CMOS Inputs, Vin = Vee = 5.5 V
TIL Inputs, Vin = Vec= 5.5 V
Vin=~5.5V,
PWR DWN = OV
Vee = 5.5 V, Vin = Vec and 0 V
Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low

Group A
Subgroups

Min

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

3.7

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

-10
2.0

Max

Units

0.4
10
15
0.5

V
V
mA
rnA
mA

.2 Vcc

jlA
V
V
V
V

7

J..ls
J..ls

10
0.8

.7Vcc

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initializatio n
PWR DWN2
Power Down Supply

TSC0026

T pGW
TpGI

4
5

See Fig. 3

9,10,11
9,10,11

1,2,3

V pD

Table 1. Electrical Performance Characteristics

2-110

6

3.5

V

Conditions
-50
-33
-70
-55°C sTC s+ 125°C Group A
Sym Vee = 5.0 V ±100/0 Subgroups Min Max Min Max Min Max Units

I

Test

I

I

Switching Characteristics, Peripheral Mode Programming
Controls (CS, WRT)3,4
Last Active Input to First Active TCA
First Inactive Input to Last Active TCI

1 See Figure 4
2

9,10,11 0.5
9,10,11 0.5

1.0 0.5
0.5

1.0

CCLK5
DIN Setup
DIN Hold

3
4
5

9,10,11
9,10,11
9,10,11

75

75

Tccc
Toc
Tco

0.5
0.5

1.0

~
~

75

50
5

50
5

50
5

ns
ns
ns

9,10,11 250

250

250

ns

Switching Characteristics, Program Readback 6
RTRIG Setup

TRTH

CCLK,
RTRIG Setup
RDATA Delay

TRTCC 2
TCCRO 3

1 See Fig. 7

9,10,11 100
9,10,11

100

100

9,10,11

238

9,10,11

100
100

ns
ns

178

119

ns

288

288

159

ns

9,10,11

410

302

217

ns

100

Benchmark Patterns7
TPIO + interconnect + 10 (TILO) + T81
Top. Measured on 10 cols.
TPIO + interconnect + 10 (TITO) + T82
Top. Measured on 10 cols.
TPIO + interconnect + 10 (TOLO) + T83
10 (TlTo) +Top.
Measured on 10 cols.
TCKO + 2 (TILO) + TICK +
interconnect

T84

9,10,11

85

62

42

ns

TCIO + TILO + TICI +
interconnect
Tcco + 2 (TILO) + Tlcc +
interconnect
TPIO + interconnect + 10 (TRIO) +
Top, Measured on 10 rows.
TLI + 3 (TIPo) + 4 (Top) + T PL +
interconnect.
Tested on all lOBs.

T85

9,10,11

90

67

41

ns

T86

9,10,11

66

49

38

ns

T87

9,10,11

318

269

183

ns

T88

9,10,11

274

204

141

ns

Table 1. Electrical Performance Characteristics (cont'd)

TSC0026
2-111

II

XC2018B Military Logic Cell Array

Test

Conditions
-33
-50
-70
-55°C :5TC :5+ 125°C Group A
Sym Vee = 5.0 V ±10% Subgroups Min Max Mini Max Minj Max Units

I

Application Guidelines, Switching, CLB7
Logic Input to Output,
Combinatorial

TllO

1 See Fig. 1

N/A

20

15

10

ns

Transparent Latch
Additional for Q Through
For G to Out

TITO
Tolo

2

N/A
N/A

25
13

20
8

14
6

ns
ns

K Clock,
To Output
Logic-Input Setup
Logic-Input Hold

TcKO
TICK
TCKI

9
3
4

N/A
N/A
N/A

10

12
1

ns
ns
ns

C Clock,
To Output
Logic- Input Setup
Logic-Input Hold

Tcco 10
TICC 5
TCCI 6

N/A
N/A
N/A

13

12
6

ns
ns
ns

Logic Input to G Clock,
To Output
Logic-Input Setup
Logic-Input Hold

TclO
TICI
TCII

11
7
8

N/A
N/A
N/A

20

6
9

ns
ns
ns

Set/Reset Direct,
Input A or D to Out
Through F or G to Out
Master Reset Pin to Out
Separation of Set/Reset
Set/Reset Pulse-Width

TRIO 12
TRlo 13
TMRO
TRS
TRPw

N/A
N/A
N/A
N/A
N/A

16
21
35

17
12

9
9

7
7

ns
ns
ns
ns
ns

Flip-Flop Toggle Rate,
Q Through F to Flip-Flop

FClK

N/A

33

50

70

Clock High'

TCH

14

N/A

12

8

7

ns

Clock Low'

TCl

15

N/A

12

8

7

ns

20

15

25

19
9
1

37

2-112

6
1

27
4
5

25
37
55

3
4

22
28
45

Table 1. Electrical Performance Characteristics (Continued)

TSC0026

7
1

8
1

MHz

Test

-70
Conditions
-33
-50
-55°C :'>TC :'>+ 125°C Group A
Sym Vee = 5.0 V ±10% Subgroups Min Max Min Max Min Max Units

I

I

I

Application Guidelines, Switching, lOB'

Pad (Package Pin) to
Input (Direct)

TPID

1 See Fig. 2

N/A

Tu
TpL
TLP
TLW

5
2
3
4

N/A
N/A
N/A
N/A
N/A

12

8

6

ns

1/0 Clock
To Input (Storage)
To Pad-Input Setup
To Pad Input Hold
Pulse Width
Frequency

20

33

50

70

ns
ns
ns
ns
MHz

12
0
12

15

11
6
0
7

8
0

9

Output,
To Pad (Output Enable)

Top

8

N/A

15

12

9

ns

Three-State,
To Pad Begin hi-Z
To Pad End hi-Z

TTHZ
TTON

9
10

N/A
N/A

25
25

20
20

15
15

ns
ns

RESET,
To Input (Storage)
To Input Clock

TRI
TRC

6
7

N/A
N/A

40
35

30
25

25
20

ns
ns

100

ns
ns
ns

Application Guidelines, Switching, Slave Mode Programming'
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

Tcco
T DCC
TCCD
TCCH
TCCL
Fcc

3 See Fig. 6
1
2
4
5

N/A
N/A
N/A
N/A
N/A
N/A

100
10
40
0.5
0.5

1.0
1

100
10
40
0.5
0.5

1.0
1

10
40
0.5
0.5

1.0
1

l1S
l1s
MHz

Application Guidelines, Switching, Master Mode Programming'·RCLK,
From Address Invalid
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK Low

T ARC
T RAC
TDRC
T RCD
T RCH
T RCL

1 See Fig. 5
2
3
4
5
6

N/A
N/A
N/A
N/A
N/A
N/A

60
0
600
4.0

60
0
600
4.0

60
0
600
4.0

N/A
N/A
N/A

1
1
150

1
1
150

1
1
150

0
200

0
200

0
200

ns
ns
ns
ns
ns

l1S

Application Guidelines, Switching, General LCA'
RESET'·
M2, M1, MO Setup
M2, M1, MO Hold
Width (Low)

TSC0026

1 See Fig. 3
TMR
2
TRM
TMRW 3

Table 1. Electrical Performance Characteristics (Continued)

. 2-113

l1S

lJ.S
ns

II

XC2018B Military Logic Cell Array

INPUT (A,B,C,D)

x

x
f4-- CD TILO~

OUTPUT (X,Y)
(COMBINATORIAl)

®

XXX
TITO

OUTPUT (X,Y)
(TRANSPARENT LATCH)

f4---

CD

~

o

TICK

CLOCK (K)

TCKI -

Jf-

f4---

CD

®

Tlcc

CLOCK (C)

J

1-0

TICI

® TclI -

~

CLOCK (G)

Tccl -

r-

I - - G ) TCKO @Tcco @Tclo -

)QO~

OUTPUT (VIA FF)

~I

SET/RESET DIRECT (A,D)

SET/RESET DIRECT (F,G)

1.

@

TRIO

@

T RLO

CLOCK (ANY SOURCE)

Timing is measured at 0.5 Vee levels wilh 50 pF minimum output load.
Input signal conditioning: Rise and fall times 5 6 ns, Amplitude

=0 and 3V

Figure 1. Switching Characteristics Waveforms, CLB

TSC0026

2-114

1637 06

PAD
(PACKAGE PIN)

(IN)

OUTPUT SIGNAL

INPUT
(DIRECT)

L
(1/0 CLOCK)

INPUT
(REGISTERED)

163707

Figure 2. Switching Characteristics, lOB

Vee (VALID)

__-II
__--'I

\

I ,
-. PO
•\.. ____ I '
V

MO/M1/M2

DONEIPROG
(OUTPUT)

USER 1/0

~8TPGW-=1

---t-USER STATE

@ T PGI

r------------------------INITIALIZATION STATE

\ ____---11
16370BA

Figure 3. General LCA Switching Characteristics

TSC0026

2·115

XC2018B Military Logic Cell Array

CS2

CCLK (2)
(OUTPUn

DIN

DOUT
(OUTPUn
1637 09

Figure 4. Peripheral Mode Programming Characteristics

AO---A15

(OUTPUn

VWVVW _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
~

14--~-~

00-07

RCLK

(OUTPUT)

14-----

CD TRCL-----~--

CCLK
(OUTPUn

DOUT
(OUTPUn

07
BYTE n-1
CCLK and DOUT timing are the same as for slave mode.
At power-up, Vee must rise from 2.0 V to Vee min. in less than 10 ms.
1637 10

Figure 5. Master Mode Programming Switching Characteristics

TSC0026

2-116

DIN~

BITN

~ CD TDCC " - @

xxx
TCCD~

BITN+1
@TCCL

CClK

@TeeO,.~

G)TCCH
DOur
(OUTPUT)

BITN-1

xxx' - - - - - BITN

Configuration must be delayed at least 40 ms after Vee min.

1637 11

Figure 6. Slave Mode Programming Switching Characteristics

DON ElPROG
(OUTPUn

____-L/___________________________________ _

II

RTRIG

CClK(1)

RDATA
(OUTPUn

VALID
1637 12

Figure 7. Program Readback Characteristics

XC2018B Data Sheet Notes
Notes:

1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to assure
that you are using the most recently released device performance parameters, please request a copy of the current
revision of this Test Specification from Xilinx.
2. PWR OWN must be active before Vee goes below specified range, and inactive after Vcc reaches specified range.
3. Peripheral mode timing determined from last control signal of the logical AND of (CSO, CS1, CS2, WRT) to transition
to active or inactive state.
4. Configuration must be delayed at least 40 ms after Vcc min.
5. CCLK and DOUT timing are the same as for slave mode.
6. Dip must be high before RTRIG goes High.
7. Testing of the Applications Guidelines is modeled after testing specified by M IL-M-3851 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data
are taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor
correlation between benchmark patterns, device performance, XACT software timings, and the data sheet.

PTE

~: ~~:i:~:t ~~~~oKmW~~~h~ :~r~~: ~~~::a:~~f::::;~~~2150t:se:o:h~~~~:, TClL.

PAD

mode.
10. RESET timing relative to power-on and valid mode lines (MO, Ml, M2) is
relevant only when 1iESET is used to delay configuration.
11.AII timings except TTSHZ and TTSON are measured at 1.5 Vee level with
50 pF minimum load output. For input signals, rise and fall times are
less than 6 ns, with low amplitude = 0 V, and high = 3 V. TTHZ is
determined when the output shifts 10% (of the output voltage swing)
from VOL level or VOH level. The following circuit is used:
TTON is measured at 0.5 Vce level with VIN = 0 for 3·State to active
High, and VIN = Vcc for 3-State to active Low. The following load circuit
is used:
TSC0026

vcc

1 k 1%

50 pF MIN 1 1 k 1%

GND

163713

~VIN

. . I1

~

1k1%

50pF MIN

163714

2-117

XC2018B Military Logic Cell Array

TSC0026

2-118

XC3020B
Military Logic

Celr Array
M

Product Specification. See Note 1.

FEATURES

Part
Number

Logic
Capacity
(gates)

Configurable
Logic
Blocks

User
1/05

Configuration
Program
(bits)

XC3020

2000

64

64

14779

• MIL-STD-883 Class B Processing.
Complies with paragraph 1 .2.1
• Field-programmable gate array
• Low power CMOS static memory technology
• Standard product. Completely tested at factory
Oesign changes made in minutes

in internal static memory cells. On-chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

• Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Placel Route (OS23)
- Oesign Editor (OS21)
- Logic & Timing Simulator (OS22)
- XACTOR In-circuit Verifier (OS24)

DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: Inputl
Output Blocks, Configurable LogiC Blocks and Interconnect. The designer can define individual 1/0 blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC3000 Commercial data sheet for a full description.

ORDERING INFORMATION

T II

XC3020 - 50 PG84 B

50 (50 MHz TOGGLE) - - - - - - - ' -

,. ",,~ro"".
PG84

CCASS '. COLev CO"'U,"'

= CERAMIC PIN GRID ARRAY PACKAGE.

70 (70 MHz TOGGLE)

84-LEAD
CQ100

TSC0085

=

CERAMIC QUAD FLAT PACKAGE.
100 LEAD

1637158

2-119

II

XC3020B Military Logic Cell Array

XC3020 CONFIGURATION PIN ASSIGNMENTS

,..".""", ''1ATION MODE: 

~~,~~~
~

I MA~~~R,;~ER I

PiiiiFfDWN (I)

PiiiiFfDWN (I)

.. ,,'_

vee
M1 (HIGH)
MO LHIGH)
IM2\HI\';H)
HDe (HIGH
(LOW)

ox:

iNiT
GND

w,v,v~

I
I

PER<11P,'oH,E
1>RAL

MASTER-HIGH
<1:1:0>

PiiiiFfDWN (I)
PWR OWN (I)
vee
vee
vee
M1 (LOW) I) I M1 (LOW) (I
M1 (HIGH) I)
MO (LOW) I) I MO (HIGH) I)
MO (LOW)
~ (LOW) IW];;M2 {HI\';H) 1),I,:;;M2 {HI\';H]
HDe HIGH
HDe (HIGH
HDC (HIGH
LOW)
(I .oW)
(LOW
INI!NT
GND
GI D
GND

ox:

ox:

ox:

I

USER
MASTER-LOW
<1:0:0>

PWin5WI\I (I)

I

vee
M1 (LOW) I)
MO (LOW) I)
'{HI\,;H)I)}{
HDe (HIGH)
_OW)

ox:

ND

Rf

RESEl(l)
DONE
fA

DONE
fA

'(I)

DONE
DA!~

P~A eV5~p
B2
F3
J2
L1
K2
K3
L3
K6
J6
l11
K10
J10
K1
J'

rA 6
'AS

DATA 6
lAS

vee

DC IT

vce

DOLIT
CCLK

DATA 6
DATA 5

H10
~10

,G10
G11
F9
F11
E11
)A'IAZ
)ATAzDATA2(
E10
,UAIA .IH'UAIA
UAIA 1 (
D10
RDVis01w
RCiJ(
RCiJ(
C11
rA 0 IJ(DATA 0 (1);iDATA 0 (I)}} B11
DOUT
DOUT
DOUT
(;10
CCLK
CCLK
CCLK
A1
AO
AO
B10
A'
A1
B9
A2
AZ
Al0
A3
A3
A9
A15
A15
B6
A4
A4
B7
A14
A14
A7
~5
A§.
e7
;N[
G
C6
13
A6
A6
AS
12
B5
DATA4
vce
IA3

)ATA4
vee
ITA 3

DATA4
VCC
,'UAIA3(

AS

,,9

A10

14
26
37
39
41
42
44
50
51
61
63
65
66
6;
68
12
73
74
76

PiiiiFfDWN (I)

77
78
79
83
84
85
86

1/0
1/0
1/0
1/0
1/0
1/0
1/0

."
90
91
93
94
97
98
99
100

vee

ROATh
RTRIG (I)
1/0

110
1/0
1/0

GND
XTl2 OR 1/0

RESEi(l)

I'ROGRI\M (I)
1/0

X' L1 Q.R 1/0
1/0
1/0
1/0
1/0

vce

"

(;(;LK (I)ti

va
110
1/0
1/0

VO
110
110
110
GNC

2
3
4

C5

5

A8
A10

A3
A2
B3

8
9
10

A'l.

Ai

~11

OPERATION

va

J/O

110
110
110
110
110
110

REPRESENTS A SOKn TO 100Kn PULL-UP
IN IT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
1637166

TSC0085

2-120

PIN ASSIGNMENTS (Continued)
PGA Pin
Number
62
C2

TCLKIN-IIO

61

NC

XC3020
PWRl:lN

PGA Pin
Number
Kl0

XC3020

Jl0
Kll

DONE-PC[
D7-110
XTL 1(OUT)-6LCKIN-110
D6-110

~

Cl

VO

D2

110

Jll
Hl0

Dl

110

Hll

VO

E3

110

FlO

D5-110

E2

110

Gl0

El

110

Gll

C"SO-IIO
D4-110

F2

110

G9

VO

F3
G3

vee

vee

110

F9
Fll

D3-110

Gl

110

Ell

CST-vo

G2

110

El0

D2-110

Fl

110

E9

110

Hl

110

Dll

NC

H2

110

Dl0

Dl-IIO

Cll

RDYIBUSY-RCCK-IIO

Jl

110

Kl

110

611

DO-DIN-IIO

J2

Ml-JmATA

Cl0

DOUT-IIO

Ll
K2

MO-RTRIG
M2-110

All

CCLK

K3

AO-WS-IIO
Al-CS2-1I0

HDC-IIO

610
69

L2

110

Al0

A2-IIO

L3

I:DC"-IIO

A9

A3-110
NC

K4

110

68

L4

NC

A8

NC

J5

110

66

A1S-110

K5

110

67

M-IIO

L5

NC

A7

A14-1I0

K6

mIT-IiO

C7

AS-IIO

J6
J7

GND
110

C6
A6

A13-110

GND

L7

110

AS

A6-110

K7

1/0

65

A12-1I0

L6

110

C5

A7-110

L8

110

M

NC

K8

110

64

NC

L9

NC

Ll0

NC

A3
A2

All-IIO
AS-IIO

63
Al

A10-1I0
M-IIO

K9

110

L11

XTL2(IN)-110

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are defau~ slew-rate limited.

TSC0085

2-121

II

XC3020B Military Logic Cell Array

XC3020 100·PIN QFP PINOUTS
Pin No.

Pin No.

Pin No.
COFP

XC3020

35

NC

69

NC

36

NC

70

NC

AS·I/O

37

M1-lm

71

1/0

4

A12·1I0

38

NC

Ds·1I0

5

A7·1I0

39

MO·RT

72
73

CSO-1I0

6

NC

40

NC

74

D4-1I0

7

NC

41

M2-1I0

75

110

8

A11-1I0

42

HDC-I/O

76

COFP

XC3020

1

GND

2

A13·1/0

3

COFP

XC3020

9

AS-1I0

43

110

77

Vee
D3-1I0

10

A10-1I0

44

roc-1I0

78

CSf-1I0

11

A9-1I0

45

NC

79

D2-1/0

12

NC

46

NC

80

110

13

NC

47

110

81

NC

14

PWROO

48

110

82

NC

15

110

49

110

83

D1-1I0

16

NC

50

TfJlT-1I0

84

RCCR-ElOS? IRDY -110

17

NC

51

GND

85

DO-DIN-1I0

18

NC

52

110

86

DOUT-1I0

19

110

53

110

87

CCLK

20

110

54

110

88

NC

21

110

55

110

89

NC

22

110

56

110

90

AO-WS"-1I0

23

110

57

110

91

A1-CS2-1I0

24

1/0

58

110

92

NC

25

110

59

NC

93

A2-1I0

26

Vee

60

NC

94

A3-1/0

27

110

61

XTAL2-1I0

95

NC

28

110

62

NC

96

NC

29

1/0

63

"RE""SIT

97

A15-1I0

30

1/0

64

NC

98

A4-1/0

31

110

65

DONE-J'lj

99

A14-1I0

100

As-1I0

32

110

66

D7-1I0

33

110

67

XTAL1-1I0

34

110

68

06-110

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSC0085

2-122

PHYSICAL DIMENSIONS - Conforms to MIL-M-3851 0 Appendix C, Case P-BC.

1.100±O.012

sa

II
TOP VIEW

,

A

B

C

D

E

F

G

H

t\\ r. t\ r. t\ r. t\ r. t\ r. t\ r. t\ r.
'-I--' '- I--' '- I--' '- I--'

(t\ r.

,

,r.t\ ,r. ,r.t\

' I--' '

V '

( t\ r. t\I
,

J

(t\

V

, tl...c, b-.L tl

L

,
, t\ (
Ie DCD
(

t\ ( t\ (
'-I--'

.070 DIAI.OS MAX

10

11

,

r.

~

,

J
T

(1:\

(

V

(t\ ( t\ (

v

V

1.000±O.010

1'b.1 D.1b

"V ' V "
"V ' V "V

1'D.1 D.1tl
I--'

1'b.1

(

I--'

&

Ll:I1tl

,

,

L

'V 'V

,

l' tl.L tl.Ltl
.Ltl1 b.1D
'", '
'V 'V
' ( t\ r.
INDEX PIN
'- 1:\
l' D...c tl-.L b.

K

f'b. r.

'I--'

d'\

'v

t\

V

r:t\r:t\
'-V '-V
r. r.t"\ r.
'-1/ '- V '-

'V 'V
(t\ (

"V

r.t"\ r. t"\ r.

'-v '- v "-

JL':Yi.L ~.L tl.L ~.L :If': DeL De.L DeL De.L tl.t2 ~
'I--'

'-

v '-v '- V '- V ' V '- V '
1.000

± 0.010

v

r--

0.100TYP

NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.

OJA-

OJC -

BOTTOM VIEW

30- 35°CiW
4 - 7°CiW

DIMENSIONS IN INCHES
X1128

TSC0085

84-Pin PGA Package (Cavity Up)

2-123

XC30208 Military Logic Cell Array

PHYSICAL DIMENSIONS (Continued)

_88 r

MARKING

0.580 TO 0.650
CAVITY SIZE

11164
4 X O.020R

BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

T

.:.:J!

0.0500 ±O.OOSO
0.120 MAX

SIDE VIEW

1 - - - - - - - - - 1 . 2 7 5 > 0.020 S Q . - - - - - - - - " ' "

o
'-.PIN'1ID.
TOPSIDE
MARK

DIMENSIONS IN INCHES
LEAD PITCH 0.025 TYPICAL
TOP VIEW .
(DIE FACING DOWN)

e JA = 40-50' CIW
eJC = 5-8' elW

PIN SPACING 0.025 TYPICAL
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS,
TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES (619) 425-3970 CHULA VISTA, CA

X1749

TSC0085

100-Pin CQFP Package

2-124

1:XILINX
STATIC BURN·IN CIRCUITS

Vee

1
30

...

<

1.3k

1.3 k

~

'*-

c

PWRDWN

CCLK
DOUT
DIN

z

Cl

~
...g..
D2

'D1

~

All
Cl0
Bl1

~
010
~

r-ru-

II

'Fi"1

XC3042
PG84

Vee

Vee

F

G9

~
fQ10

~

715

'F1O

~

>

•

'1n1
'HiO
fjff"
i<'iT

~

4

--#-'=.!...

1.5k

W

'"G1
~
~
~

1.3 k

F

>-tr
~
-r,'F2
'""F3

1.5k
j>

<11ll ~ ~ a'i : 1'31!l :fr! ~ ~ ti!;i:fD~~~~~m~

~

<
1.15 k

a.06k

Ml
MO

OONEIPROG
RESET

0

()

NO

::;;::c

19

~c
z~

~I~ ~:l ~~ !q~ ~~

~t;

!::i~ ~~

<0", o~.,....

"'...J ~

~

'J'j'QKl0

4.99k

•

lk;

~~ III

-::!:NOTES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WAn AT 150'C WITH A
BUILD TOLERANCE OF 1% AND A5%
TOLERANCE OVER LIFE.
[[I CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
30 {) RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150'C WITH A
TOLERANCE OF 5%.

illJ

163718

TSC0085

2·125

XC3020B Military Logic Cell Array
STATIC BURN·IN CIRCUITS (Continued)

~

1
30n
.3k

1.3 k

30n

m

8.06k
~~

14

~

~ ~ ml= J~I~I~I~IN- §18118l1G;13l1~1~ISlI~Ic;;18 m
0

PWRDWN

z

"

~
........g.

CCLI<

DOUT

~

~

Vee

Vee

~
~
~

~
~

~

To-fg-

~

~~~} "fa67""""

~
>--fa"

~

Ml

NO I§
'" "''''
0

!!l~;;

0

"fs-

Q

I'-z
"

715n

84

0

;0:"

\l'l:Ie ~l~l~l~l~l~ ~ ~llTTTTlml~l"T~ ~
4.99 k

1k

m~~

Ts~

~
~

..1.-

86

To79Ta#-

~
~
~

~
~

1.5 k 30n

88
87

~

~
~
~

~
26

1.5 k
1.15k

DIN 85

~

........g.

1.3k

.J.

1637188

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 W AT 150·C WITH A
BUILD TOLERANCE OF 1% AND 5%
TOLERANCE OVER LIFE.
~ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
[!J 30-0 RESISTOR IS METAL OXIDE
AND IS RATED FOR 1 W AT
150·C WITH A TOLERANCE OF 5%.
4. USE ON: XC3020-XXCQ100X
5. UNLESS OTHERWISE SPECIFIED,
SOCKET SHALL BE:
ENPLAS
PART NUMBER FPQ-132-0.635-01
OR
WELLS
PART NUMBER CP-l0582

XC3020·CQ100

TSC0085

2-126

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

Absolute Maximum Ratings

Units

Limits

Vee

Supply voltage relative to GNO

-0.5 to +7.0

V

VIN

Input voltage with respect to GNO

-0.5 to VCC +0.5

V

VTS

Voltage applied to three-state output

-0.5 to VCC +0.5

V

T STG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec @ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

•

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating2
Power Supply Current

V OH

Power-Down Supply Current

leePD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TIL
Input Low Level TIL
Input High Level CMOS
Input Low Level CMOS

IlL
IRLL

VOL
leeo

V IHT
V ILT
V IHe
VILe

Conditions
-55°C :<> Te :<> + 125°C
Vee = 5.0 V ±10%

Group A
Subgroups

Limits
Max
Min

Vee = 4.5 V, IOH = -4.0 rnA
Vee = 5.5 V, IOL = 4.0 rnA
CMOS Mode, V 1N = Vee = 5.5 V

1,2,3
1,2,3
1,2,3

TIL Mode, V IN = Vee = 5.5 V
V IN = Vee = 5.5 V,
PWR OWN =OV
Vee =5.5 V, VIN = Vee and 0 V
Measured as an average

1,2,3
1,2,3
1,2,3
1,2,3

-20

Guaranteed
Guaranteed
Guaranteed
Guaranteed

1,2,3
1,2,3
1,2,3
1,2,3

2.0

Input High
Input low
Input High
Input Low

Table 1. Electrical Performance Characteristics

TSC0085

2-127

Units

0.4
1

V
V
rnA

15
0.5

rnA
rnA

20
2.4

~
rnA

3.7

0.8
.7 Vee
.2 Vee

V
V
V
V

XC3020B Military Logic Cell Array

Test

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

Sym

-50
Group A
Subgroup

Min

-70

I Max

Min

I Max

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T pGW
TpGI

PWR DWN3
Power Down Supply

V ccpo

RESEP
M2,M1 ,MO Setup
M2,M1 ,MO Hold
Width (low) abort

TMR
TRM
TMRW

5 See Fig. 1
6

9,10,11
9,10,11

6

~s

7

~s

3.5

3.5

V

9,10,11
9,10,11
9,10,11

1
1
6

1
1
6

~s

9,10,11
9,10,11
9,10,11
9,10,11

0.5
60

0.5
60

~s

1,2,3

2
3
4

6
7

~s
~s

Switching Characteristics, Peripheral Mode Programming'
WSLOW
DIN Setup
DIN Hold
Ready/Busy

TCA
Toc
Tco
TWTRB

1 See Fig. 4
2
3
4

°

60

°

60

ns
ns
ns

Switching Characteristics, Slave Mode Programming'
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

TCCD

Tocc
TCCD
TCCH
TCCL
Fcc

3 See Fig. 5
1
2

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

4
5

100

°

0.5
0.5
•......

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-128

100

ns
ns
ns

1.0
1

~

60

60

1.0
1

°

0.5
0.5

~s

MHz

Test

Sym

Conditions
-55°C:;; Tc:;; +125°C Group A
VCC = 5.0 V ±10% Subgroups

-70

-50
Min I Max

Min I Max

250

Units

Switching Characteristics, Program Readback6 •7
RTRIG Setup

TRTH

1 See Fig. 7

9,10,11

250

CCLK,
RTRIG Setup
RDATA Delay
Clock Low
Clock High

TRTCC
TCCRO
TCClR
TCCHR

2
3
4
5

9,10,11
9,10,11
9,10,11
9,10,11

200
0.5
0.5

ns

100
1.0

ns
ns
ns
ns

200
100
1.0

0.5
0.5

Benchmark Patterns·
TplD + interconnect + 8 (TllO) +
Top' Measured on 8 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOLO + T llO + TOICK +
interconnect
TllO + TECCK + interconnect

TS1

9,10,11

135

86

ns

TS2

Tested on all CLBs

9,10,11

32

21

ns

TS3

Tested on all CLBs

9,10,11

53

34

ns

TS4

Tested on all CLBs

9,10,11

35

23

ns

TOK PO + ToPS - TOPF + TPICK

TS5

Tested on all CLBs

9,10,11

73

53

ns

TCKO + TOlO + T pus + TICK +
interconnect
TCKO + TOlO + Tpus + TICK +
interconnect
TCKO + TOlO + T IO + TICK +
interconnect
TCKO + TOLO + T IO + TICK +
interconnect

TS6

One long line pull-up

9,10,11

73

48

ns

TS7

The other long line
pull-up
No pull-up, lower
long lines
No pull-up, upper
long lines

9,10,11

83

55

ns

9,10,11

47

31

ns

9,10,11

57

38

ns

TS8
TS9

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-129

•

XC3020B Military Logic Cell Array

--.---

I

Test

Sym

Conditions
-55°C $; Tc $; +125°C
Vcc = 5.0 V ±10%

-50
Group A
Subgroups

-70

Min I Max

Min I Max

Units

Application Guidelines, Switching, ClBo
Combinatorial
Reset to CLB output
Reset Direct width
Master Reset pin to CLB out
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
'Clock (High)
'Clock (Low)

N/A
N/A
N/A
N/A

TILO
TRIO
TRPW
TMRO

1 See Fig. 2
9
13

TCKO
TOLO

8

N/A
N/A

TICK
TCKI
TDICK
TCKDI
TECCK
TCKEC
TCH
TCL

2
3
4
5
6
7
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

14
12
30

20

ns
ns
ns
ns

12
11

8
7

ns
ns

12

9
8

8

12
1
8
6
10
0
9
9

ns
ns
ns
ns
ns
ns
ns
ns

8
1
5
4
7
0
7
7

'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Internal BuffersB
Clock Buffer
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
Bidirectional

TGCK

N/A

9

6

ns

TIO

N/A

8

5

ns

Tpus
TpUF

N/A
N/A

34
17

22
11

ns
ns

TBIDI

N/A

6

4

ns

Table 1. Electrical Performance Characteristics (Continued)

TSC0085
2-130

E:XIUNX
Conditions
-55°C ~ Tc ~ +125°C
Vcc =5.0 V ±10%

Sym

Test

-50
Group A
Subgroups Min Max

I

-70
Min

I

Max

Units

Application Guidelines, Switching, 1088,10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN

See Fig. 3
TplDC
TplD

3

N/A
N/A

110 pad-input hold
To 1/0 pad (fast)
1/0 pad output setup
110 pad output hold
'Clock (High)
'Clock (low)

TIKRI
TplCK
TIKPI
TOKPO
TOOK
TaKa
TIOH
Tlol

4
1
2
7
5
6
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

Output
To pad (enabled fast)
To pad (enabled slow)

TOPF
Tops

10
10

N/A
N/A

15
40

9
29

ns
ns

Three-State
To pad begin hi-Z (fast)
To pad valid (fast)

TTSHZ
TTSON

9
8

N/A
N/A

18
20

12
14

ns
ns

Master Reset
To input RI
To output (FF)

TRRI
TRPo

13
14

N/A
N/A

35
50

23
33

ns
ns

1/0 Clock
To 1/0 RI input (FF)
1/0 pad-input setup

5
9
11

5
6

ns
ns

7

ns
ns
ns
ns
ns
ns
ns
ns

20
0

30
0

13

18
10
0
8
8

15
0
9
9

'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-131

•

XC3020B Military logic Cell Array

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C
V cc = 5.0 V ±1 0%

-70

-50
Group A
Subgroups

Min

I

Max

Min

200

0
60
0

I

Max

Units

200

ns
ns
ns
ns

Application Guidelines, Switching, Master Parallel Mode Programming8,l1
RCLK,
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK Low

T RAC
TORC
T RCO
T RCH
T RCL

1 See Fig.6
2
3
4
5

N/A
N/A
N/A
N/A
N/A

0
60
0

600
4.0

Table 1. Electrical Performance Characteristics (Continued)

TSC0085
2-132

600
4.0

~s

r-------illl-I

MO/M1/M2

DONEIPROG
(OUTPUT)

-----.r~'g®'~f-----~®TPGW~

__J__[0 TPG1
INIT
(OUTPUT)

_---,(0TMRW)~-------

USER STATE

-

C_LE_A~R!~S-T-A-T-E---------------JJ'
II
.

CONFIGURE

____________

\

I
r-NOTE3-j

Vee (VALID)

----------------------------------------------~\

Ir~t-v-----

'- ____ .I ~

CCPD
183719

Figure 1. General LeA Waveforms

CLB OUTPUT (X,V)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

CLBCLOCK

@

o

TCl
T01CK

CLBINPUT
(DIRECT IN)

CLBINPUT
(ENABLE CLOCK)

CLBOUTPUT
(FLIP· FLOP)

CLBINPUT
(RESET DIRECT)

CLBOUTPUT
(FLIp· FLOP)
163720

Figure 2. CLB Waveforms

TSC0085

2-133

•

XC3020B Military Logic Cell Array

1/0 BLOCK (I)

1/0 PAD INPUT

110 CLOCK

-®-TPID~-f---t (2) TpICK --4.*'. . . CD TIKPIJ------

----,.

(IK/OK)

14---- @

TIOl

--->14----

1/0 BLOCK (RI)

1/0 BLOCK (0)

@TOp
1/0 PAD OUTPUT
(DIRECT)

1/0 PAD OUTPUT
(REGISTERED)

------------------.. .£0

J---1r-0-~-SON----@-~-"",J

1/0 PAD TS

VO PAD OUTPUT

OKPO

T

--------~(

I

r-163721

Figure 3. lOB Waveforms

CSl/CSO

CS2

\

/

7

\~----------~!---

ws

DO-D7

CCLK

•

I
•

I

'\ _ _ .. I

•
I

\._- .. 1

I

RDY/BUSY
_ ........ _-_ .... _ ... _-_ ... _ .. ___ 1

DOUT

GROUP
OFB CCLKs

I
•

I

__-,X~_--,X~__________

----I

'"------'X'--___L
163722A

Figure 4. Peripheral Mode Waveforms

TSC0085

2-134

DIN

CCLK

DOUT
(OUTPUn
163723

Figure 5. Slave Mode Waveforms

Ao-A15
(OUTPUn

Do-D7

ADDRESS n

ADDRESS n + 1

\:

•

-----------------J.r-----~~-----BYTE n

RCLK
(OUTPUn
,...-----7CCLKs-------~---

CCLK
(OUTPUT)
DOUT
(OUTPUn

D7
BYTE n-1
163724A

Figure 6. Master Parallel Mode Waveforms

TSC0085

2-135

XC3020B Military Logic Cell Array
DONE/PROG
(OUTPUT)

_---<-1___________________________________ _

RTRIG

o TCCLR-~~----

CCLK

RDATA
(OUTPUT)
163725

Figure 7. Program Readback Waveforms

XC3020B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this Test
Specification (TSC 0085) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, Ml, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the INIT of all LCA's is HIGH. WS cannot go active until RDY/SOSY goes HIGH.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38S10/60S. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vce must rise from 2.0 V to Vcc minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = 0 V, and high = 3 V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:

fuC
I
50 pF

vcc

1k

PAD

MIN

1k

GND
163713

12. (continued)
TTSON is measured at 0.5 Vee level with VIN = 0 for 3-State to active High, and VIN = Vee for 3-State to active Low. The
following load circuit is used:

~VIN
~
50pF

. . I1

1k

MIN

163714

TSC008S

2-136

XC3042B
Military Logic CeW Array
M

Product Specification. See Note 1.
FEATURES

Part
Number

Logic
Capacity
(gates)

Configurable
Logic
Blocks

User
110's

Configuration
Program
(bits)

XC3042

4200

144

96

30784

MIL-STD-883 Class B Processing.
Complies with paragraph 1 .2.1
Field-programmable gate array
• Low power CMOS static memory technology
• Standard product. Completely tested at factory
• Design changes made in minutes

in internal static memory cells. On-Chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Placel Route
- Design Editor
- Logic & Timing Simulator
- XACTOR In-circuit Verifier

DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The Logic CeIP"M Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: Inputl
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual 1/0 blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC3000 Commercial data sheet for a full description.

ORDERING INFORMATION
XC3042 -50 PG132 B

Basic Part Number

50 (50 MHz Toggle)
70 (70 MHz Toggle)

TTT________--'J L
T

TSC0117

B = MIL-STD-883, Class B, Fully Compliant

PG132 = Ceramic Pin Grid Array Package, 132·Lead
CQ100 = Ceramic Quad Flat Package 100·Lead
PG84 = Ceramic Pin Grid Array Package, 84-Lead

153726

2-137

II

XC3042B Military Logic Cell Array

PIN ASSIGNMENTS

I-----:OS.,-,LA""V"'"E--.I--..,.,M-:-:AS==T:=ER=--S""'E==R:--I'I--::"P""'ER'""IP,..,.H"'E",-RA"'"L-,--,.M"'""A-"ST=E""'R-'--H"""IG""H"-'-""'M'""'"A"':"':ST==E"'"R--:-LO""W.,.,..-l
<:1:1:1>
<0:0:0>
<1 :0:1>
<1:1 :0>
<1 :0:0>
t"'WH LJwN III
vce
M1 (HIGI- (I)
J.1QJHIGI- (I)
M2 (HIGIHO, : (HIC
LOC (LOW)

I:,'

H:

GND

I

I

PWH OWN III
vcc
M1 (LOW I)
MO (LOW I)
: (LOW
HDC (HIC
LDC (LOW)

PWH DWN (I)PWR.QWI\I(I)
EvvB D'ffi{ill
vce
vce
vcc
M1 [LOW I)
I M1 [HIGH (I) I M1 .LOW:
MO :HlliH I) I MO (LOW, (I,
MO .LOW.
HIGH :1)::,'?M2 :HIGH 1l":O';:O"M2f:!I§I:I WE,
HDI : (HIC
HD(: (HIGH)
HDI . (HIC
[DC (LOW
me (LOW)
me (LOW

I
I

GND

-rn:mlll

GND

l'!ESET

.~(I)

DONE
DATA 7

DOL

~ATA6
It
VCC

I

)OL

.(1)

GND

DOL
CCLK

GNI

GND

P~A cb~p ~~i
B2
F3
J2
L1

K2
K3
L3

GND

J6
L11
l'!ESET (I)
l1ESn (I)
Kl0
DONE
DONE
Jl0
DATA 7
rA 7 (i< Kll
Jl
,TA6DATA6(1,,:::IH10
I.ATi\..S A T A 5 ( 1 i@1 FlO
Gl0
)ATA4
rA4 (1,.< Gll
VCC
VCC
F9
D A T A 3 u A I A3(1
Fll
Ell
DATA 2
rA2(I
El0
IAl
'1\1".1(1
Dl0
RCIJ(
RCIJ(
Cll
,TAO
rAO(I)?:: Bll
DOUT
DOUT
Cl0
c..CLK
CC~
..1\11.
AO
AO
Bl0
Al
Al
B9
A2
A2
Al0
A3
A3
A9
A15
A151:l§
A4
A4
B7
A14
A14
A7

III! II

'Ti\.5. ti

CSO (I):;;;
lATA 4
VCC
:.: '••• lATA3
, ,:: JCSl
,TA2
•
,AlA 1
HL II:lU::;
,TAo
DOUT
CCLK

~s.

c )

GND
A13
A6
A12
A7
All
AB
Al0
.~

A~~L

GND
A13
A6
A12
A7
All
AB
Al0
A'E..

C6
A6
AS
B5
CS
A3
A2
B3
Al

14
26
37
39
41
42
44
5.1
61
63
65
66

A1
C8
B13
B14
C13
B14
D14

H12
M13
P14
N13
M12
67
t"'13
68
Ntl
72
M9
"l3N9
74
N8
76
MB
77 N7
78
P6
79
M6
83 M5
84
N4
B5
N2
86
M3
8f
t"'
90
M2
91
Nl
93
L2
94
Ll
97 B
98
J2
99
Hl
100
H2
1
H3
2
G2
3
Gl
4
t'2
SEl
8
Dl
9D2
10
B1
11
C2

USER
OPERATION
t"'WHLJWNIil
VCC
RTRIG(I)
110
110
110
110
GND
XTL2 OR 110
~(I)
(I)

110
)("
OR IIC
110
110
110
110
VCC
110
110
110
110
110
110
110
C:l K(I)r:?:
110
110
I/O
I/O
110
110
110
I/O
GND
110
110
110
110
110
110
110
110

I i i REPRESENTS A 50 kn TO 100 kn PULL-UP
* INIT IS AN OPEN-DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
X1130

TSC0117

2-138

PIN ASSIGNMENTS (Continued)
84 PGA Pin
Number
B2

XC3042
l'WliDN

84 PGA Pin
Number
K10
J10
K11

XC3042
"RESET

XTL 1(OUT)-BLCKIN-IIO
06-110

C2

TCLKIN-IIO

B1

110

C1
D2

110
110

J11
H10

D1

110

H11

110

E3

110

F10

DS-IIO

E2

110
110

G10
G11

C"SO-VO

E1
F2

110

G9

110

F3
G3

vee

vee

110

F9
F11

D3-110

G1

110

E11

CST-1I0

G2

110

E10

D2-110

F1

110

E9

110

H1

110

D11

110

H2

110

D10

D1-110

J1

110

C11

RDYlllUS'l-RClX-IIO

DONE-l"G"
07-110

D4-1I0

K1

110

B11

DO-DIN-1I0

J2

M1-l'IDi'iTA

C10

DOUT-IIO

L1
K2

MD-RTRIG
M2-110

K3

CCLK
Ao-W5-IIO
A1-CS2-110

HDC-IIO

A11
B10
B9

L2

110

A10

A2-1f0

L3

IIlC"-1/0

A9

A3-VO

K4

110

VO

L4

vo

JS
KS

110
110

LS

110

K6

ll\IlT-IIO

B8
AS
B6
B7
A7
C7

J6
J7

GND
110

C6
A6

110
A1S-VO
A4-VO
A14-110
AS-I/O

GND

L7

110

AS

A13-1I0
A6-110

K7

110

BS

A12-1/0

L6

I/O

CS

A7-1/0

La

va

A4

I/O

Ka

I/O

B4

I/O

L9

va

L10

110

A3
A2

A11-1/0
AS-I/O

B3
A1

A10-1/0
A9-1/0

K9

I/O

L11

XTL2(IN)-1/0

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSC0117

2-139

II

XC3042B Military Logic Cell Array
PIN ASSIGNMENTS (Continued)
COFP
Pin No.

PGA Pin
Number

Function

COFP

Pin No.

PGA Pin
Number

Function

COFP

PGA Pin

Pin No.

Number

Function
110

13

C4

GND

47

F13

110

81

P4

14

Al

PWRDN

48

F14

110

82

P3

110

15

C3

110

49

G13

110

83

M5

Dl-I/O

16

82

110

50

G14

INIT-I/O

84

N4

RCLK-8USY/RDY-1/0

17

83

110

G12

VCC'

P2

1/0·

B4

I/O·

51

H12

GNO

N3

18

C5

110

52

H14

I/O

85

N2

DO-DIN-I/O

I/O'

19

M

110

53

H13

110

86

M3

DOUT-I/O

20

85

I/O

54

J14

110

87

Pl

CCLK

21

C6

110

55

J13

110

88

M4

VCC

22

A5

110

56

K14

110

89

L3

GND

23

86

110

57

24

A6

110

25

26

87

110

J12

110

90

M2

AO-WS-I/O

K13

1/0·

91

Nl

At-CS2-1/0

92

Ml

110

K3

110'

93

L2

A2-1/0
A3-1/0

110

L13

1/0*

C7

GND'

58

K12

110

C8

VCC

59

M14

110

27

A7

110

60

N14

110

94

Ll

28

88

110

61

M13

XTAL2-1/0

95

K2

29

A8

110

62

L12

GNO

96

J3

110

30

A9

110

63

P14

RESET

97

Kl

A15-1I0

31

89

110

64

Mll

VCC

98

J2

M-I/O
A14-1/0

32

C9

110

65

N13

DONE-PG

99

Hl

33

Al0

110

66

M12

07-1/0

100

H2

AS-I/O

810

1/0*

67

P13

XTALl-I/O

1

H3

GND

Cl0

110

34

N12

110 •

35

811

110

P12

110 •

36

812

110

68

Nll

06-1/0

Ct2

1/0*

69

Ml0

110

37

813

Ml-RD

70

Nl0

110

38

Cll

GNO

71

Pl0

110

39

A14

MO-RT

40

012

VCC

41

C13

M2-1/0

42

814

HDC-I/O

C14

1/0·

G3

vee '"

2

G2

A13-1/0

3

Gl

AS-liD

4

F2

A12-1/0

5

El

A7-1/0

6

F3

110

E2

I/O

M9

05-1/0

7

73

N9

CSO-I/O

8

Dl

All-liD

74

N8

04-1/0

9

D2

A8-1I0

75

P7

110

E3

1/0 *

76

M8

VCC

Cl

110 •

10

81

Al0-1/0

72

E12

1/0*

43

013

110

77

N7

D3-11O

11

C2

A9-1/0

44

014

LOG-liD

78

P6

CSl-I/O

12

D3

VCC

45

F12

110

79

M6

D2-1/0

46

E14

110

80

N5

110

M7

GND'

Xl101A

Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
• Indicates unconnected bond pads for the CQFP-1 00 package

TSC0117

2-140

E:XUJNX
PHYSICAL DIMENSIONS -Conforms to MIL-M-38510 Appendix C, Case P-BC.

1 - - - - - - - - 1 . 1 0 0 ± 0.012

sO>------->ltl

jo--.

1.000 ± 0.010
0.1001YP

0.100

rh rh

ffi ffi

A:l

fJ- 'V

,-EfJ-E
-EfJ-E fJ-

1YP

r

;:K;:K
'V 'V

'V

G

1.000

±0.01 o

-EfJ-E

fJ-

l E X PIN

1YP.0.070

t-,

"/C>.

-u~

~

+'

1

II

'-'

+'
1:-,

TA
0.018
± 0.002 DIA

~ f7{f}

LD~.08MAX

'../

5

•

7

10

11

BonOMVIEW

0.050
±0.010

NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
1105350

84-Pin PGA Package (Cavity Up)
1.275 ± 0.020 sa.

I~ ~ ~

LEADFRAME
0.0045 MIN
0.0080 MAX

r

t
0.008 MIN

MARKING

0.580 TO 0.650
CAVITY SIZE

DEP[

4X O.02QR

LEAD PITCH 0.025 TYPICAL
BOTTOM VIEW

o::J~

DIMENSIONS IN INCHES

(LID SIDE UP)
(DIE FACING UP)

9JA

9JC

40-50 0 CIW
= 5_8 0 CIW
=

0.0500 ±O.OO50
0.120 MAX

SIDE VIEW
NarES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS,
TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575.Q610 WEST CALDWELL N.J.
- RISI INDUSTRIES (619) 425-3970 CHULA VISTA. CA.
X1750

TSCOl17

100-Pin CQFP Package (Cavity Down)
2-141

XC3042B Military Logic Cell Array

PHYSICAL DIMENSIONS (Continued)

0.040 X 45°

1

4PLCS

2

3

4

5

6

7

8

9

10

11

12

13

PIN
KOVAR

14

0888888,888888
N88888888888888
"88888888888888
888
888
888
888
888
888
888
+

.1

a

p

TYP 0.070 DIA
± 0.005

0.D1 B ± 0.002 DIA-.J
132 PLCS

L

K

J

H

~

G

888

880

888
888
0888
c 880
888

1.460
± 0.015

888
888

F

E

888888
888888
888888

B

0.070
±0.01 SO

0.645
± 0.006

=~Vr 10-• ---±0iJ.~7'-_===~
._. ~
1.300TYP
IJo-------±10~5------->!

__-..-.,

'

BOTTOM VIEW

~ I "~
W-±0.009

1105388

132·Pin PGA Package (Cavity Down)

TSC0117
2-142

STATIC BURN-IN CIRCUITS
Vee

1
<.<
30

:1'"

IT]
1.3 k

1.3 k

~

8.06 k

..........

..... .0

coco

0

O>~

PWRDWN

CCLK
DOUT
DIN

0

z

Cl

~
C1
~
~
~

;>

A11
C10
B11
C11

~
Efi)

ET1

~
~

>

1.5 k

1.3 k

DiO
DiT""

~
~

f--G3

1.5 k

0

O>~

co '" ...... '" '" '" .0 .0 ()« coco «co «« coco
«co««co«()co««()

~
~

<
1.15 k

iii""
XC3042
PG84

Vee

~
~
~
~
~
~
~
~

~~ M1
~r-- MO

",g

::;:I

~I~
1

.~(@]

Vee

19
...... '" '"
"'-' ...,'"

DONEIPROG
RESET

li-z
S0
~Cl

-'''' ..., ..., -'''' ~:g "'-' -'~~:::-'

",.0 .0 .....

G9

G11
GtQ-'
i1O"
H11"
H1iJ
-m
K11

0

~~

~

..........

COo>

715 ~

JiO
K10

4.99 k

k~

<

JNOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WATT AT 150'C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[[] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
@] 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150'C WITH A
TOLERANCE OF 5%.
163718

XC3042-PG84

TSC0117

2-143

XC30428 Military Logic Cell Array

STATIC BURN-IN CIRCUITS(Continued)

~

1
30n
.3 k

1.3 k

30n

IT]

8.06 k
~~

14

~
~

1.3k

~ ~ mlw ~UJlJN -~1~I~ll~I~I-#

~

M4 ~
1.5'
-+.-k-~rM3

'::; =f~ ;:'

~

.--¥

~
C7

-d

1k

> I."

1.3k

N0I82
01U

'

-.l
X1129

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL RESISTORS ARE METAL FILM
AND ARE RATED FOR 1/8 W AT 150'C WITH A BUILD TOLERANCE OF
1% AND 5% TOLERANCE OVER LIFE.
2. CAPACITOR HAS 10% TOLERANCE, 50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
3. 30-0 RESISTOR IS METAL OXIDE AND IS RATED FOR 1 W AT
150'C WITH A TOLERANCE OF 5%.

XC3042-PG132

TSC0117

2-145

XC30428 Military Logic Cell Array

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

Absolute Maximum Ratings

Limits

Units

Vee

Supply voltage relative to GNO

-0.5 to +7.0

V

VIN

Input voltage with respect to GNO

-0.5 to Vee +0.5

V

VTS

Voltage applied to three-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 see@ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating 2
Power Supply Current

V OH

Power-Down Supply Current

lecPD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TIL
Input Low Level TIL
Input High Level CMOS
Input Low Level CMOS

IlL
IRLL

VOL
leeo

V IHT
V ILT
VIHe
VILC

Conditions
-55°C ~ Te ~ +125°C
Vee = 5.0 V±10%

Group A
Subgroups

Vee = 4.5 V, IOH = -4.0 rnA
Vee= 5.5 V, IOL = 4.0 rnA
CMOS Mode, Yin = Vee = 5.5 V

1,2,3
1,2,3
1,2,3

TIL Mode, Yin = Vec= 5.5 V
Yin = Vee = 5.5 V,
PWR OWN =OV
Vec = 5.5 V, Yin = Vce and 0 V
Measured as an average @
V ee =5.5V
Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low

1,2,3
1,2,3

Table 1. Electrical Performance Characteristics

TSCOl17

2-146

Limits
Min
Max

0.4
1.650

V
V
rnA

11.15
1150

rnA
iJA

20
2.4

iJA
rnA

3.7

1,2,3
1,2,3

-20

1,2,3
1,2,3
1,2,3
1,2,3

2.0

Units

0.8
.7 Vee
.2 Vce

V
V
V
V

E:XJUNX

Test

Condnions
-SsoC:5 TC:5 +12SoC
Vee =S.O V ±10%

Sym

-so
Group A
Subgroup

Min

-70

I Max

Min

JMax

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T PGW
TpGI

PWR DWN3
Power Down Supply

V ccpo

RESET4
M2,M1,MO Setup
M2,M1,MO Hold
Width (low) abort

TMR
TRM
TMRW

S See Fig. 1
6

9,10,11
9,10,11

4

6

7

7

I1S
I1S

3.S

3.S

V

9,10,11
9,10,11
9,10,11

1
1
6

1
1

6

!J.S
!J.S
!J.S

9,10,11
9,10,11
9,10,11
9,10,11

O.S
60
0

O.S
60
0

1,2,3

2
3

6

Switching Characteristics, Peripheral MOde Programming 5
WRTLOW
DIN Setup
DIN Hold
Ready/Busy

TCA
Toc
TCD
TWTRB

1 See Fig. 4

2
3
4

I1S
60

60

ns
ns
ns

Switching Characteristics, Slave Mode Programming 5
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

TCCD
Tocc
TCCD
TCCH
TCCl
Fcc

3 See Fig. S
1

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

2
4
S

Table 1. Electrical Performance Characteristics (Continued)

TSCOl17

2-147

100

100
60
0
O.S
O.S

1.0
1

60
0
O.S
O.S

1.0
1

ns
ns
ns

!J.S
!J.S
MHz

II

XC3042B Military Logic Cell Array

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C Group A
Vcc = 5.0 V ±10% Subgroups

-50
Min

I

-70
Max

Min

I

Max

Units

Switching Characteristics, Program Readback6•7
RTRIG Setup

9,10,11

250

2
TCCRD 3
TCClR 4
TCCHR 5

9,10,11
9,10,11
9,10,11
9,10,11

200

TB1

9,10,11

191

122

ns

TRTH

CCLK,
RTRIG Setup
RDATA Delay
Clock Low
Clock High

1 See Fig. 7

TRTCC

1.2
0.5

250

ns

200
100
2.0

1.2
0.5

100
2.0

ns
ns
Il s
Il S

Benchmark Patterns8
TPID + interconnect + 12 (TILO) +
Top Measured on 12 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOlO + T llO + TDICK +
interconnect
TllO + TECCK + interconnect

TB2

Tested on all CLBs

9,10,11

32

21

ns

TB3

Tested on all CLBs

9,10,11

53

34

ns

TB4

Tested on all CLBs

9,10,11

35

23

ns

TOKPO + Tops - TOPF + TPICK

TBS

Tested on all CLBs

9,10,11

73

53

ns

TCKO + TOlO + T pus + TICK +
interconnect
TCKO + TOlO + Tpus + TICK +
interconnect
TCKO + TOlO + TIO + TICK +
interconnect
TCKO + TOlO + TIO + TICK +
interconnect

Too

One long line pull-up

9,10,11

73

48

ns

TB7

The other long line
pull-up
No pull-up, lower
long lines
No pull-up, upper
long lines

9,10,11

83

55

ns

9,10,11

47

31

ns

9,10,11

57

38

ns

TB8
TB9

Table 1. Electrical Performance Characteristics (Continued)

TSC0117

2-148

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

-50
Group A
Subgroups

Min

I

-70
Max

Min

I

Max

Units

Application Guidelines, Switching, ClB8
Combinatorial
Reset to CLB output
Reset Direct width
Master Reset pin to CLB out
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
'Clock (High)
'Clock (Low)

T llO

1 See Fig. 2

TRIO
T RPW
T MRO

9

TCKO

8

13

2

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

3
4
5
6
7
11
12

9
8

14
15

8

12

N/A
N/A

TOLO
TICK
TCKI
T OICK
TCKOI
TECCK
T CKEC
TCH
TCl

N/A
N/A
N/A
N/A

40

34

12
11

8
7

8

12
1
6
10
0

9
9

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

1
5
4
7
0
7
7

8

ns
ns
ns
ns

'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.

Application Guidelines, Switching, Internal Buffers8
Clock Buffer

T GCK

N/A

9

6

ns

TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups

T IO

N/A

8

5

ns

Tpus
TpUF

N/A
N/A

42
22

36
16

ns
ns

Bidirectional

T BIOI

N/A

6

4

ns

Table 1. Electrical Performance Characteristics (Continued)

TSC0117

2-149

III

XC3042B Military Logic Cell Array

Test

Sym

Conditions
-55°C:.:; Tc:,:; +125°C
Vcc =5.0 V ±10%

-50
Group A
Subgroups

Min

I

-70
Max

Min

I

Max

Units

5

ns
ns

Application Guidelines, Switching, 1088,1.
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN

1/0 Clock
To 1/0 RI input (FF)
1/0 pad-input setup

See Fig. 3
TplDC
TplD

N/A
N/A

3

5
9

6

TIKRI
T plCK
T IKPI
TOKPO
TOOK
T OKO
T IOH
T lol

4
1
2
7
5
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

T OPF
Tops

10
10

N/A
N/A

15
40

9
29

ns
ns

Three-State
To pad begin hi-Z (fast)
To pad valid (fast)

TTSHZ
TTSON

9
8

N/A
N/A

14
20

12
14

ns
ns

Master Reset
To input RI
To output (FF)

TRRI
T RPo

13
14

N/A
N/A

37
55

33
43

ns
ns

I/O pad-input hold
To 1/0 pad (fast)
1/0 pad output setup
1/0 pad output hold
'Clock (High)
'Clock (low)
Output
To pad (enabled fast)
To pad (enabled slow)

6

11

7
20
0

30
0

13

18
15
0
9

10
0
8
8

9

ns
ns
ns
ns
ns
ns
ns
ns

'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
Table 1. Electrical Performance Characteristics (Continued)

TSC0117

2-150

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

-50
Group A
Subgroups

Min

I

-70
Max

Min

200

0
60
0
600
4.0

I

Max

Units

200

ns
ns
ns
ns
Ils

Application Guidelines, Switching, Master Parallel Mode Programming 8,11
RCLK,
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLKLow

T RAC
TDRC
T RCD
T RCH
T RCL

1 See Fig.6
2
3
4
5

N/A
N/A
N/A
N/A
N/A

0
60
0
600
4.0

Table 1. Electrical Performance Characteristics (Continued)

II

TSC0117

2-151

XC3042B Military Logic Cell Array

MO/M1/M2

DONE/PROG
(OUTPUT)

IN IT
(OUTPUT)

r-NOTE3-,
Vee (VALID)

----------------------------------------------------~\

I~t------

•\. ____ J •~ VCCPD
163719

Figure 1. General LCA Waveforms

CLB OUTPUT (X,Y)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

CLB CLOCK

@

o

TCl
TDICK

CLBINPUT
(DIRECT IN)

CLBINPUT
(ENABLE CLOCK)

CLB OUTPUT
(FLIP· FLOP)

CLBINPUT
(RESET DIRECT)

CLB OUTPUT
(FLlP·FLOP)
163720

Figure 2. CLB Waveforms

TSCOl17

2-152

110 BLOCK (I)

-0-TPID~-r----

110 PAD INPUT

- - - - - - t - G ) - 1 -1-P-IC-K------Ir-~------.

1/0 CLOCK
(IKIOK)

14---- @

T 10L - - - ' i 4 - - - -

110 BLOCK (RI)

RESET

110 BLOCK (0)

II

110 PAD OUTPUT
(DIRECT)

110 PAD OUTPUT
(REGISTERED)

------------------£0 TOKPO

)

IIOPADTS

110 PAD OUTPUT
163721

Figure 3. lOB Waveforms

\

/
\~----------~:----

CS2

'.
DO-D7

CCLK

,
'\.

.

...... ,

""

.... .. I

GROUP
OF8 CCLKs

"

:

RDY/BUSY
- - - - - - - - - - - - - - - - - _____ .. 1

DOUT

__~x~__~x~____________~
163722

TSC0117

Figure 4. Peripheral Mode Waveforms

2-153

XC3042B Military Logic Cell Array

DIN

CCLK

=1°'=I0'''~~,," ___B~f' ' ' '~'=j~_"_C _L

DOUT
(OUTPUn

___

r_
-_
_
'

)1\

BIT N -1

BIT N
163723

Figure 5. Slave Mode Waveforms

AO-A1S
(OUTPUn

DO-D7

ADDRESS n

ADDRESS n + 1

\:

CD TRAC

------------------J~-----+~------BYTE n

RCLK
(OUTPUn
~-----------7CCLKs------------~~-----

CCLK
(OUTPUn
DOUT
(OUTPUn

D7
BYTE n-1
1S3724A

Figure 6. Ml'ster Parallel Mode Waveforms

TSC0117

2-154

DONEIPROG
(OUTPUT)

____-LI___________________________________ _

RTRIG

®

T ATCC

Ir-----'\i-'I--

CCLK

RDATA
(OUTPUT)

0

TC C L A - - l , , - - - - - -

VALID
163725

Figure 7. Program Readback Waveforms

XC3042B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this Test
Specification (TSC0117) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. "RESET timing relative to valid mode lines (MO, M1, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the INIT of all LCAs is High. WS cannot go active until RDY/BO'SY goes High.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDi) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vcc must rise from 2.0 V to Vcc minimum in less than 10 ms. Otherwise, delay configuration using "RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = 0 V, and high = 3 V.
TTSHZ is determined when the output shifts 10% (of the output vottage swing) from VOL level or VOH level. The following
circuit is used:

SrC:
I
PAD

50 pF

vcc

1k

MIN

1k

GND
163713

12. (continued)
TTSON is measured at 0.5 V~c level with VIN = 0 for 3-State to active High, and VIN = Vce for 3-State to active Low. The
following load circuit is usea:
'

~VIN
~
50pF

. . I1

'1k

MIN

TSC0117

163714

2-155

•

XC3042B Military Logic Cell Array

TSC0117

2-156

XC3090B
Military Logic Cell™ Array
Product Specification. See Note 1.
FEATURES

Part
Number

Logic
Capacity
(gates)

Configurable
Logic
Blocks

User

XC3090

9000

320

144

MIL-STD-883 Class B Processing.
Complies with paragraph 1.2.1
• Field-programmable gate array
• Low power CMOS static memory technology

II0s

Configuration
Program
(bits)
64160

• Standard product. Completely tested at factory
• Oesign changes made in minutes

in internal static memory cells. On-chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

Complete user control for design cycle.
Secure design process
Complete PC or workstation based
development system
- Schematic entry
- Auto Place! Route (OS23)
- Oesign Editor (OS21)
- Logic & Timing Simulator (OS22)
- XACTOR In-circuit Verifier (OS24)

DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: Input!
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual I/O blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC3000 Commercial data sheet for a full description.

ORDERING INFORMATION

111~

XC3090 - 50 PG175 B

50 (50 MHz TOGGLE) - - - - - - - - ' 70 (70 MHz TOGGLE)

B = MIL·STD·883, CLASS B, FULLY COMPLIANT
PG =CERAMIC PIN GRID ARRAY PACKAGE.
175.LEAD
CQ = CERAMIC QUAD FLAT PACKAGE
164-LEAD
163728A

TSC0097

2-157

II

XC3090B Military logic Cell Array

PIN ASSIGNMENTS
CONFIGURATION MODE:

~'v".'v"

.... V7

I---::S""LA""V""'E--r-:'IM""A""ST=E==R""-S:::E':'R--'--I=-=PE:-:R"'IP:-Hc:'ER::-A:-L~-M-A-:-ST~E:-:R""'_H-::-IG:-CH~-:M"'A'-:S'::cTE~R:-:_L-:0:-W-:-I1G4
<1:1:1>

<0:0:0>

<1:0:1>

<1:1:0>

175
PGA PGA

<1:0:0>

PWR DWN-rl'
J'WR DWN{I)
f5li'lFfDWN(1)
PWRDWN{I)
PWRDWN(I)
,VCC
vcc
vce
VCC
VCC
Ml :HIGH
I M1LOW
I Ml (LOW I
Ml (HIGH
Ml (LOW
MO
OW
MO
OW
MO :HIGH
Me LOW
I ~LHIGH
••• M2 :HIGH
"l,M2, :LOWJM2(HIGH I )(M2(HIGH
,iIM2,(HIGr
H[C :HII
HDC HI'
HDC HI(
HDC HI'
HDC :HI'
C1iC OW
DC OW
DC OW:
DC OW:
DC OW

I:

20
42
G2
G4
GG
G7
7'
83
99
101
103

62
D9
614
815
C15
E14
lG
H15
J14
PIS
R15
R14

104

N13

8'

"RE

VCC

:DI
DOl

"(I)
IN

VCC

De
CCLK

GND

GNI

fie'

-(I)

USER
OPERATION
PWR DWNfIl
VCC
RTRIG(I)
110
110
110
110
GNC
X' L20R 110

Ill]
110
105
14
X'
OR lie
DA~-,AG,lt
DATAG',I}
DAl '"G" I : ' : 109 P12
110
DA"A5(1) ••'
• DATA 5(1)
'DAl 15
Ib
110
11G R'
110
'CSO(I)
• DATA 4 (I) :.:
110
.DAT 14 I) .: 121 R9
: .'. DA"A4(1) .....
123 N9
VCC
VCC
VCC
vce
125 P8
110
: DATA 3
DATA 3
':'::.:: DATA 3
126 R8
110
....... CSl '
131 R7
110
DATA
'., :•• : . DATA.
.:: :.: ••••• :. DATA
•••••: 137 R5
110
::.:., ......:. DP IA
•••• :•• ::.: DAIA
DATA
RC[
RC[
138
P5
110
RDYIB y
...... :.::::::::: D~ r A (I) ......( .... ::.:.:: DATA I ....... : 143 R3
110
.......:.:.DATA
DOL
DOL
DOU
144 N4
110
CCLK
CCLK
CCL~
145 R 2 : ( CCLK (I) Ii
AO
AO
148 P2
110
.WSIl
A'
Al
149 M3
110
:CS2 . .
152 p'
110
A2
A2
153 Nl
110
A,3
A3
15G M i l l O
A15
A15
A4
A4
157 L2
110
A14
A14
16C K2
110
AS
AS
lGl Kl
110
lG4 J3
GND
GND
GND
2
H2
110
A13
A13
3
HI
110
A6
AG
8
F2
110
A12
A12
9
El
110
A7A7
12
Dl
110
All
All
13
CillO
A8
A8
16
E3
110
Al0
Al0
17
C2
110
A9
A9
DONE
• DATA 7

I.... :..... , REPRESENTS A 50 kQ TO 100 kQ PULL-UP
• INIT IS AN OPEN-DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
X1,61

TSC0097

2-158

I:XILINX
PG175 PIN ASSIGNMENTS
PGAPin
Number

XC-3090

PGAPln
Number

XC-3090

PGAPin
Number

XC-3090

PGA Pin
Number

XC-3090

B2

l'WRON

013

110

R14

DONE-l'G"

R3

OO-OIN-I/O

04

TClKIN-I/O

B14

M1-JmATA

N13

07-110

N4

DOUT-IIO

B3

C14

GND

n4

XTAl1 (OUTj-BClKIN-IlO

R2

CClK

B15

MO-l'IT"RlG

P13

P3

014

vee

R13

C15

M2-VO

T13

VO
VO
110

N3
P2

AO-WS-VO '

E14

HDC-VO

N12

110

M3

A1-CS2-VO

C5

VO
VO
VO
VO
VO
110

B16

110

015

AS

110

C16

C6

016

IDC-IIO

P11

F14

T11
R10

~-1I0

P10

07

i/O

G14

1/0

G15

1/0
1/0
1/0

A8

110

G16

T9

B8

H16

R9

C8

VO
VO

110
VO
1/0
1/0
110
VO
VO
VO
VO

N11

C7

VO
VO
VO
VO
VO
VO

OS-itO
VO
VO
VO
VO
110
05-VO

R1

110

1/0
VO
VO

P12

B5

H15

lI'IlT-IlO

D8

C4
B4
M
05

os
B6
A6
B7

A7

,

E15
E16
F15
F16

R12
T12

R11

N10
no

P9

vee

GND

vee

H14

D9

GND

C9

110

J14
J1S

N9

110

vee

GND

N2

1/0

P1

A2-VO

N1

A3-VO

l3

110

M2

VO

M1

A15-VO

L2

M-IIO

l1
K3

110
1/0

K2

A14-1I0

110

K1

AS-1I0

04-VO
VO

J1
J2

VO
VO

vee
GND

N8
P8

D3-VO

J3

GND

H3
H2

A13-VO

vee

B9

110

J16

110

R8

CSi"-1I0

H1

AS-1I0

A9

110

K16

110

TS

110

G1

A10

110

K1S

T7

110

G2

010

1/0
1/0
110

K14

N7

110

G3

110
110
VO

P7

110

F2

A12-VO

A11

110

M16

110

T6

VO
02-110
110

F1

US

VO
VO
VO
110

E1

A7-1I0

B11

M1S

110

E2

N6

110

F3

VO
1/0

C11

110

N16

A12

P16

B12

VO
110

N15

C12

liO

R16

110
VO
VO
VO
110
110

R6

011

110
110

C10
B10

l16

l14

Ri

P6

110

01

A11-1I0

T5

VO

C1

AS-VO

R5

01-110

02

110

P5

ROY/IIDS'i'-l'!C[K-VO

B1

VO

012

110

M14

110

N5

110

E3

A10-VO

A13

110

P15

XTAL2(IN)-IIO

T4

C2

A9-1I0

B13

110

N14

GND

R4

110
1/0

03

vee

C13

110

R15

m=sET

P4

110

C3

GND

A14

110

P14

vee

Unprogrammed lOBs have a default pull-up. This prelients an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
Pins A2, A3, A 15, A 16, T1, T2, T3, T15 and T16 are not connected.
Pin A1does not exist.

TSC0097

2-159

II

XC3090B Military Logic Cell Array

164-PIN CQFP PINOUTS

COFPPin
Number

XC-3090

COFPPin
Number

XC-3090

COFPPin
Number

XC-3090

COFP Pin
Number

XC-3090

20

l'WlIDfl

61

110

103

OONE-PG"

143

DO-DIN-IIO

21

TCLKIN-IIO

62

M1-lmliTA

104

07-1/0

144

DOUT-1I0

22

110

63

GND

105

145

CCLK

23

1/0

64

MO-RTRIG

XTAL1(OUT)BCLKIN-I/O

146

VCC

VCC

106

110

147

GND

24

110

65

25

110

66

M2-1I0

107

1/0

148

AO-WS-1I0

26

1/0

67

HOC-I/O

108

149

A1-CS2-1I0

27

110

68

109

150

28

110

69

110
1/0

VO
06-1/0

151

29

110

70

110

111

VO
1/0

152

110
110
A2-1I0

30

110

71

IDC"-1I0

112

110

153

A3-1I0

31

72

I/O

114

110
1/0

154

73

110
110

113

32

1/0
1/0

155

I/O

33

1/0

74

110

115

05-VO

156

34

110
110
110

75

110
110
110

116

CSO-I/O

157

A15-1/0
A4-1I0

117

110

158

118

110

159

37

110

78

110

160

1/0

79

120

110
110

80

162

110

40

81

lI'IIT-1I0

122

110
04-110
110

161

39

110
110
1/0

119

38

110
110
A14-1I0
A5-1I0

163

110

41

GND

82

VCC

123

VCC

164

GND

42

VCC

83

GND

124

GND

1

VCC

43

84

110
110

125

03-1/0

2

44

110
1/0

126

CST-IIO

3

A13-1/0
A6-1I0

45

110

86

127

VO

4

110

46

110

87

110
110

128

110

5

110

47

110

88

I/O

6

110

89

130

110

7

110

02-1/0

8

91

110
110

131

50

110
110
110

1/0
1/0

129

48

132

110

9

51

110

92

110

133

I/O

10

A12-1I0
A7-1I0
1/0

52

110
1/0

93

110
1/0

134

VO

11

135

I/O

12

110
A11-1I0

95

110
110
1/0

136

110

13

AS-1I0

137

01-110

14

56

110
110
1/0

138

RDY/IIDSYRClR-I/O

15

110
1/0

57

110

98

110

99

XTAL2(IN)-1I0

110

A10-1I0

110

139

16

58

110

110

A9-1I0

59

140

17

100

GND

60

110

101

11ESIT

141

I/O

VCC

110

102

142

35
36

49

53
54
55

76
77

85

90

94
96
97

110

121

Unprogrammed lOBs have a defaun pUll-up.
This Prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSCOO97

2-160

18

VCC

19

GND

1:XllINX
PHYSICAL DIMENSIONS - Conforms to MIL-M-38510 Appendix C, Case P-BC.
TOP VIEW

o

-t---tt--

INDEX (AI)

- - - - + - - - - --++---1- 9 JA =16°CIW
9Jc= 0.5-1.0 °CIW

•
0.025 REF

WE10 METALIC HEATS INK
ELECTRICALLY CONNECTED TO V

PIN KOVAR
0.005 R. TYP.

16

GGGGGGGGGGGGGGG

"'tt----.-

~G0GGGGGG@GGGGG0o

16GGGGGGGGGGGGGGGG
G G G G rr==~====1~~==u---'-'-"-'-"-'-'-""t--.
~GGGG
GGGG
"GGGG
GGGG
aGGGG
GGGG
·GGGG
+
GGGG
·GGGG
GGGG
7GGGG
GGGG
'GGGG
GGGG
sGGGG
GGGG
4GGGG
3GGGG
2G0GG
·GGGG

0.070
± 0.005 TYP DIA

.3

~

-.~~~---

.---~~~-

1.660
± 0.016 SO

P.845

;'0.009

1.
±O.015

DIELECTRIC
COAT

STAND-OFF PIN
4 PLACES

T

R

P

N

110S31C

TSC0097

175-Pin PGA Package (Cavity Down)

2-161

XC3090B Military Logic Cell Array

PHYSICAL DIMENSIONS (Continued)
0.0650 ± 0.0050

DEVITREOUS
SOLDER GLASS

~,~0.120MAX.. ~

BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

SIDE VIEW

144

0.008 MIN
0.013 MAX

104

TOP VIEW

DIMENSIONS IN INCHES

(DIE FACING OOWN)
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS, TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES INC. (619) 425-3970 CHULA VISTA, CA.

8JA = 35-45' CIW
8JC = 3-5' CIW
1105410

164·PIN CQFP Package

TSC0097

2-162

E:XJUNX
STATIC BURN-IN CIRCUITS
Vee

30

4.02k

1]1

1.5k
1.15k

C3
B2
04

715
1.5k

P5
R5
T5

P6
N6
R6
AS
B7
C7
07
A7
AS
B8

C8
08

II

R7
P7
N7

n

Vs.
Vee

V.S
Vee

XC3090
PG 175

T8
R8
P8
N8
N9

P9
R9

T9

An
Bl1
011
Cll
A12
B12
C12
01
A13
B13
C13
A14
013
B14
C14
815

~7\
I~ ~ ~

1.3k

~

Tl0
Nl0
Pl0
RIO
TIt
Rll
NIl
Pl1
T12
R12
P12
N12
Tt3
R13
P13
Tt4
N13
R14
P14
R15

1.3 k

4.99k

Uk

NOlES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WAT 150"0 WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOlERANCE OVER LIFE.
CAPACITOR HAS 10% TOLERANce.
50 V RATING WITH AN X7R
lEMPERATURE CHARACTERISTIC.
30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150"C WITH A
TOLERANCE OF 5%.

@;]

m
TSC0097

2-163

163731A

XC3090B Military Logic Cell Array

STATIC BURN-IN CIRCUITS (Continued)
Vee

4.02k

1k

1.3 k

J.
NOTES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 W AT l5O"C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[IJ CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT l5O"C WITH A
TOLERANCE OF 5%.

III
TSC0097

2-164

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
" released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings

Limits

Units

Vcc

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

Input voltage with respect to GND

-0.5 to Vcc +0.5

V

V TS

Voltage applied to three-state output

-0.5 to V cc +0.5

V

T STG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec @ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

II

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device, These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied, Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability,

Test

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating 2
Power Supply Current

VOH

Power-Down Supply Current

ICCPD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TTL
Input Low Level TTL
Input High LEivel CMOS
Input Low Level CMOS

IlL
IRLl

VOL
Icco

V IHT
V ILT
V IHC
VILC

Conditions
-55°C:o; Tc:O; +125°C
V cc = 5.0 V ±1 0%

Group A
Subgroups

Limits
Min
Max

Vcc = 4.5 V, IOH = -4.0 mA
Vcc = 5.5 V, IOL = 4.0 mA
CMOS Mode, Yin = V cc = 5.5 V

1,2,3
1,2,3
1,2,3

TTL Mode, Yin = V CC = 5.5 V
Yin = VCC = 5.5 V,
PWR DWN = OV
Vcc = 5.5 V, Yin = Vcc and 0 V
Measured as an average

1,2,3
1,2,3
1,2,3
1,2,3

-20

Guaranteed
Guaranteed
Guaranteed
Guaranteed

1,2,3
1,2,3
1,2,3
1,2,3

2.0

Input
Input
Input
Input

High
Low
High
Low

Table 1. Electrical Performance Characteristics

TSC0097

2-165

Units

0.4
3

V
V
mA

15
2.5

mA
mA

20
2.4

JlA
mA

3.7

0.8
.7Vcc
,2Vcc

V
V
V
V

XC3090B Military Logic Cell Array

Test

Conditions
-55°C:s; Tc:s; +125°C
Vee = 5.0 V ±10%

Sym

-50
Group A
Subgroup

Min

-70

I Max

Min

I Max

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T pGW
l:PGI

PWR DWN3
Power Down Supply

V CCPD

RESEP
M2,M1 ,MO Setup
M2,M1 ,MO Hold
Width (low) abort

TMR
TRM
TMRW

5 See Fig. 1
6

9,10,11
9,10,11

4

7

/ls
7

/lS

3.5

3.5

V

9,10,11
9,10,11
9,10,11

1
1
6

1
1
6

/lS
/lS

9,10,11
9,10,11
9,10,11
9,10,11

0.5
60
0

0.5
60
0

/lS

1,2,3

2
3

6

6

/ls

Switching Characteristics, Peripheral Mode Programming'
WSLOW
DIN Setup
DIN Hold
Ready/Busy

TCA
Toc
Tco
TWTRB

1 See Fig. 4
2
3

4

60

60

ns
ns
ns

Switching Characteristics, Slave Mode Programmlng 5
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

Tceo
Tocc
Tcco
TCCH
TCCL
Fcc

3 See Fig. 5
1
2

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

4
5

100
60
0
0.5
0.5

Table 1. Electrical Performance Characteristics (Continued)

TSCOO97
2-166

1.0
1

100
60
0
0.5
0.5

1.0
1

ns
ns
ns
/lS
/lS
MHz

E:XILINX

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C Group A
Vcc = 5.0 V ±10% Subgroups

-50

-70

Min I Max

Mini Max

Units

Switching Characteristics, Program Readback6.7
RTRIG Setup

TRTH

1 See Fig. 7

9,10,11

250

CCLK,
RTRIG Setup
RDATA Delay
Clock Low
Clock High

TRTCC
TCCRD
TCClR
TCCHR

2
3
4
5

9,10,11
9,10,11
9,10,11
9,10,11

200

250

ns

100
2.0

ns
ns
IlS
Ils

200
100
1.2
0.5

1.2
0.5

Benchmark Patterns·
T PID +interconnect +20 (TllO) +
Top. Measured on 8 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOLO + T llO + TDICK +
interconnect
T llO + TECCK + interconnect

TB1

9,10,11

303

194

ns

TS2

Tested on all CLBs

9,10,11

32

21

ns

TS3

Tested on all CLBs

9,10,11

53

34

ns

TB4

Tested on all CLBs

9,10,11

35

23

ns

TOKPO + Tops - TOPF + TPICK

TB5

Tested on all CLBs

9,10,11

73

53

ns

TCKO + TOlO + T pus + TICK +
interconnect
TCKO + TOlO + T pus + TICK +
interconnect
TCKO + TOLO+ T IO + TICK +
interconnect
TCKO + TOLO + T IO + TICK +
interconnect

TB6

One long line pull-up

9,10,11

73

48

ns

TB7

The other long line
pull-up
No pull-up, lower
long lines
No pull-up, upper
long lines

9,10,11

83

55

ns

9,10,11

47

31

ns

9,10,11

57

38

ns

TBa
TB9

Table 1. Electrical Performance Characteristics (Continued)

TSCOO97
2-167

•

XC3090B Military Logic Cell Array

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

-50
Group A
Subgroups Min I Max

-70
Min \ Max

Units

Application Guidelines, Switching, ClB8
Combinatorial
Reset to ClB output
Reset Direct width
Master Reset pin to ClB out
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
'Clock (High)
'Clock (Low)

N/A
N/A
N/A
N/A

TllO

1 See Fig. 2

TRIO
TRPW
T MRO

9

TCKO
Tala

8

N/A
N/A

TICK
TCKI
TOICK
TCKOI
TECCK
TCKEC
TCH
TCl

2
3
4
5
6
7
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

13

40

34

ns
ns
ns
ns

12
11

8
7

ns
ns

9

14
12
12

8
8

12
1
8
6
10
0

ns
ns
ns
ns
ns
ns
ns
ns

8
1
5
4
7
0
7
7

9
9

'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Internal Buffers8
Clock Buffer
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
Bidirectional

TGCK

N/A

9

6

ns

TIO

N/A

8

5

ns

Tpus
TpUF

N/A
N/A

46
22

38
16

ns
ns

T8101

N/A

6

4

ns

Table 1. Electrical Performance Characteristics (Continued)

TSC0097

2-168

Test

Conditions
-55°C S; Tc S; +125°C
Vcc = 5.0 V ±1 0%

Sym

-50
Group A
Subgroups

Min

I

-70
Max

Min

I

Max

Units

Application Guidelines, Switching, IOB8,10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN

T p10c
TplO

3

N/A
N/A

1/0 Clock
To 1/0 RI input (FF)
1/0 pad-input setup
1/0 pad-input hold
To 1/0 pad (fast)
1/0 pad output setup
1/0 pad output hold
'Clock (High)
'Clock (low)

TIKRI
T plCK
TIKPI
ToKPo
TOOK
ToKO
T 10H
T lol

4
1
2
7
5
6
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

TOPF
Tops

10
10

N/A
N/A

15
40

9
29

ns
ns

Three-State
To pad begin hi-Z (fast)
To pad valid (fast)

TTSHZ
TTSON

9
8

N/A
N/A

14
20

12
14

ns
ns

Master Reset
To input RI
To output (FF)

TRRI
T RPo

13
14

N/A
N/A

37
53

33
47

ns
ns

Output
To pad (enabled fast)
To pad (enabled slow)

See Fig. 3
5
9

11

5
6

ns
ns

7

ns
ns
ns
ns
ns
ns
ns
ns

20
0

30
0

13

18
15
0
9
9

10
0
8
8

'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Master Parallel Mode ProgrammingS,11
RClK,
To Address Valid
To Data Setup
To Data Hold
RClK High
RClK low

TRAC
ToRC
T Rco
TRCH
TRcl

1 See Fig.6
2
3
4
5

N/A
N/A
N/A
N/A
N/A

0
60
0
600
4.0

Table 1. Electrical Performance Characteristics (Continued)

TSC0097

2-169

200

0
60
0
600
4.0

200

ns
ns
ns
ns

·I1S

•

XC3090B Military Logic Cell Array

(0TRW)------

. - - -_ _ _UU._____

MO/M11M2

DONE/PROO
(OUTPUT)

INIT
(OUTPUT)

-f0'g0"F-------~®TPGW=-1

___J___~[@TPGI
USER STATE

CONFIGURE

_ _ _ _ _ _C_L_E_AR,......
ST_A_T_E_ _ _ _ _ _ _- ' /

--

u

.

__________________________________________--4~NO~3""'1

\

Vee (VALID)

j

,r-:-.--•
'-----1,

V

CCPD
163719

Figure 1. General LCA Waveforms

CLB OUTPUT (X,Y)
(COMB INATORlAL)

CLB INPUT (A,B,C,D,E)

CLBCLOCK

~==:?,@~2~Tr;:C;-L==~ @
CLBINPUT
(DIRECT IN)

°

TCH

----~

TDICK

CLBINPUT
(ENABLE CLOCK)

CLBOUTPUT
(FLlP·FLOP)

CLB INPUT
(RESET DIRECT)

CLBOUTPUT
(FLlP·FLOP)
1637 20

Figure 2. CLB Waveforms
TSC0097

2-170

VO BLOCK (I)
--=-®-TPIDt-f----

VO PAD INPUT

~

~===~~~~:-

CD

Tp1CK----I·*'·....

CD

@

TIOL---.J+----

T1KP1=:!'I.-------

110 CLOCK
(IKIOK)

1+---VO BLOCK (RI)

•

110 BLOCK (0)

VO PAD OUTPUT
(DIRECT)

1/0 PAD OUTPUT

------------------;(0

OKPO
T

(REGISTERED)

J Ir®"~

IIOPADTS

110 PAD OUTPUT

@p~j r-

----------4(\,.______________'f163721

Figure 3. lOB Waveforms

I

\
CS2

__----JJ

\~-----~:-'--

DO-D7

CCLK

.

,,

\. .. ... 1

"
'\.

GROUP
OFB CCLKs

...... ,:
,

RDY/BuSv

_ •••••••••••••••••••••• 1

DOUT

TSC0097

_~x~_~x~

____________

~

'--~x'--

Figure 4. Peripheral Mode Waveforms

2·171

__x=

163722

XC3090B Military Logic Cell Array

DIN

CCLK

=t(i),=~®,,,J

'J'" ®"~

r-

~I
[F)lIe Directories]
To list the available File Areas, the files
contained in each area, and a shon
description of each file.
T 
mransfer Protocol]
Sets the Transfer Protocol for Uploadsl
Downloads. If set to "None", you will be
prompted for a Transfer Protocol before
each UploadlDownload.
D 
[D)ownload a File]
To download a file from the Bulletin Board.
U 
[U)pload a File]
To upload a file to the Bulletin Board.
FLAG  [FLAG for Download]
To FLAG files for a Batch Download, you
must use Ymodem as your Transfer
Protoool if you use this option.
DB  [DB Download Batch]
To download multiple files at one time, you
must use Ymodem as your Transfer
Protocol if you use this option.
UB  [UB Upload Batch]
To upload multiple files at one time, you
must use Ymodem as your Transfer
Protoool if you use this option.
N 
[N)ew Flies (date)]
To search for files on the Bulletin Board
newer than a specified date.
L 
[L)ocate Flies (name)]
To search for files on the Bulletin Board by
name.
Z 
[Z)lppy DlR Scan]
To search for files on the Bulletin Board by
text. Will search by both file name and file
description.

C 
[C)omment to SYSOp]
To leave a message to the System
Operator.
E 
[E)nter a message]
To send a message.
R 
[R)ead Mes..ges]
To read messages and reply to messages.
K 
[K)IU a M....ge]
To delete a message.
Y 
[Y)our Per. Mall]
To scan the message base for messages
addressed to you.
TS  [TX Txt Srch Msgs]
To find a text string in the message
headers and message contents accessible
to you.

To provide customers with up-tO-date information and an
immediate response to questions, Xilinx provides a 24hour electronic bulletin board. The Xilinx Technical Bulletin Board (XTBB) is available to all registered XACT

GENERAL COMMANDS
General Bulletin Board Commands.

TYPE:
B 
[B)ulletln Ustlnga]
To display the available Bulletins.
G 
[G)oodbye (Hang up)]
To terminate the Bulletin Board session.
H 
[H)elp Functions]
To receive Help Text on any command.
M 
[M)ode (Graphics)]
Toggles between the Graphics Onl
Graphics Off Modes.
P 
[P)age Length Set]
To specify the number of lines the Bulletin
Board displays before it prompts "More?"
X 
[X)pert 0nI0ff]
Toggles between Expen On (no menus)l
Expen Off Modes.
V 
[V)lew Settings]
To display your Bulletin Board Mode
settings.
W 
[W)rlte User Info]
To change your password and other User
Registration Information.
NEWS  [NEWS file display]
To redisplay the text displayed when you
initially logged on.

customers. Users with full privilege can read files on the
bulletin board, download those of interest to their own
systems or upload files to the XTBB. They can also leave
messages for other XTBB users.
4-4

3. Messages are used to communicate with other XTBB
users; they can be general-available to everyone-or
private.

New bulletin board users must answer a questionnaire
when they first access the XTBB. After answering the
questionnaire callers can browse through the bulletin and
general information file areas. A caller with a valid XACT
protection key will be given full user privileges within 24
hours.

The XTBB is based on a bulletin board system called
PCBoard. This is a menu-driven system-you choose
commands from menus to decide what happens next. To
choose a menu command, simply type the highlighted first
letter(s) of the command and press return . Listed
below are some helpful hints for using the XTBB.

The software and hardware requirements for accessing
the Xilinx Technical Bulletin Board are:
Baud Rate
Character Format
Phone Number
Transfer Protocols

9600,4800,2400, or 1200 bps
8 data bits, no parity, 1 stop bit
(408) 559-9327
ASCII, Xmodem, (Checksum,
CRC, 1K), Ymodem

• To perform a sequence of commands, type the first letter
of each command, followed by a space, and press
return. For example, typing FA  [F)ile Directories
A)II] sends you a listing of all file directories.

Information contained on the XTBB is divided into three
general categories: 1. Bulletins, 2. Files and 3. Messages.

• The XTBB has an extensive help section. To get help,
type H  followed by the command in question. A
short explanation ofthe command will be displayed. You
can also type H  inside a command, and get an
explanation of the sub-commands.

1. Bulletins contain tidbits of up-to-date information; they
can be displayed on-screen and can be downloaded.
2. Files can contain just about anything (text, user programs, etc.). XTBB users with full privileges can download files to their own systems or upload files to the
bulletin board.

• For more information, download the XTBBHLP .TXT file
from the General Information area.

•

4-5

Field Applications Engineers

939 N. Plum Grove Rd.
SulteH
Schaumburg, IL 60173
Tel: 708·605·1972
5445 DTC Pkwy.
Penthouse 4
Englewood, CO 80111
Tel: 303·220·7541

61 Sp~ Brook Rd.
Suite 403
Nashua, NH 03060
Tel: 603·891·1096
93 Willow Glen Dr.
Kanata Ontario
Canada K2M 1T8
Tel: 613·592·5522

65 Valley Stream Pkwy.
Suite 140
Malvern, PA 19355
Tel: 215·296·8302

3235 Kifer Rd.
Suite 320
Santa Clara, CA 95054
Tel: 408·245·1361

6115·C Oakbrook Pkwy.
Norcross, GA 30093
Tel: 404·448·4733

X1558

North America
There are 16 Xilinx Field Applications Engineers in the
locations shown above. Additional technical support is
provided by Headquarters Applications.
Dial (408) 879-5199 or (800) 255-7778.

Europe
Each of the Xilinx European sales offices in England and
Germany has resident Field Applications Engineers:
England (tel 44-932-349 401);
Germany (tel 49-89-904 5024).

The world-wide networlk of Xilinx Representatives and
Distributors also gives technical support.

Japan
Xilinx Japan is located in Tokyo and has resident Field
Applications Engineers (tel 81-3-297-9191).
4-6

Programmable Gate Array
Training Courses

The Xilinx Programmable Gate Array Training Courses
are comprehensive classes covering the Logic Cell Array
component architecture and Xilinx development systems.
These courses are intended for design engineers using
Programmable Gate Arrays in their applications who want
to get ''up-to-speed'' as quickly as possible. Three courses
are offered: a four-day course on the XC2000/XC3000
series, a two-day course on the XC4000 series, and a fourday course covering all series.

XC3000 COURSE OUTLINE
DAY1:

DESIGN METHODOLOGY AND THE XACT
DESIGN MANAGER
BASIC ARCHITECTURE
DESIGN ENTRY TOOLS

DAY 2:

DAY 3:

A substantial amount of the class time will be spent
performing lab exercises on the Xilinx Development System
(two students per development system). These
development systems will be available to the students on
the day following the class for optional individual work and
consultations with the instructor(s).

DESIGN IMPLEMENTATION
LOGIC PARTITIONING
AUTOMATIC PLACE'AND ROUTE
LCA CONFIGURATION
DESIGN VERIFICATION

DAY 4:

XACT DESIGN EDITOR (XDE)
LCA ARCHITECTURE DETAILS

XC4000 COURSE OUTLINE

TUITION: Thetuitionfee is$1,OOO per studentforthe fourday courses, and $750 for the XC4000 course.

DAY 1:

THE XACT DESIGN MANAGER (XDM)
XC4000 ARCHITECTURE

ENROLLMENT: To enroll, call the Training Administrator
at Xilinx headquarters at (408) 879-5090 or contact your
local Xilinx sales office.

DESIGN ENTRY TOOLS
ROM/RAM MEMORY COMPILER (MEMGEN)

Class size is limited, so early enrollment is recommended.
Students are not considered to be enrolled until a check,
money order or P.O. for the course tuition is received.
Please mail your payment to:

DESIGN IMPLEMENTATION (PPR)
DAY 2:

CONFIGURATION
DESIGN VERIFICATION

Xilinx, Training Administrator
2100 Logic Drive, San Jose, CA 95124

XACT DESIGN EDITOR (XDE)

Enrollments will be confirmed by letter.

XC3000/XC4000 COURSE OUTLINE

There will be a 25% cancellation fee if you cancel within
two weeks of your scheduled course date. Failure to
cancel at least one week in advance of the scheduled
course date will result in forfeiture of the full course tuition.

DAY 1:

XACT DESIGN MANAGER
XC3000 ARCHITECTURE
DESIGN ENTRY

DAY 2:

PREREQUISITES: Students are assumed to have a
background in digital logic deSign. Forthetwo-day XC4000
class, students should have prior experience with the
XC2000/XC3000 families.

XC3000 IMPLEMENTATION
CONFIGURATION
VERIFICATION

DAY 3:

LOCATION: Courses are held atXilinx corporate headquarters in San Jose, CA. A detailed map, including a list
of nearby hotels, will be included with the enrollment
confirmation letter. For regional and international classes,
contact your local sales office, or the Training Administrator at (408) 879-5090.

XACT DESIGN EDITOR (XDE)
XC4000 ARCHITECTURE
XC4000 DESIGN ENTRY

DAY 4:

XC4000 IMPLEMENTATION
XC4000 CONFIGURATION

4-7

•

Technical Literature

XACT Development System Manuals

User's Guide

The first two binders of this 3-volume set are the LCA
Development System Manuals, providing exhaustive reference information on:

The Xilinx User's Guide, included with every system, is a
binder with several self-contained application notes giving
practical and tutorial information. The following notes are
currently available:

•
•
•
•
•
•
•
•
•

Executive Program
LCA Editor
Macros
Simulator (SILOS)
PROM Formatter
Bit-stream Generator
Demo Board
Place and Route
XNFto LCA
and information on schematic capture

• Introduction
Basic Design Flow
Hierarchical Design and Merging
• Getting Started
Programmable Gate Array Design Flow 1990
Xilinx Tutorial Using Schema 11+
Xilinx Tutorial Using FutureNet DASH-LCA 1990
XiJinx Tutorial Using OrCAD/SDT
XACT Design Editor Tutorial

The third volume provides detailed information on each of
the 2000 and 3000 series XACT macros, including schematics, block count, and examples of typical placements.

• Design Entry
DeSigning LCAs with Boolean Equations
• Design Implementation
Advanced Design Methodology
Fundamentals of Placement and Routing
LCA Configuration and Debugging Hints
Automatic Design Translation with Xilinx Design
Manager
.
• DesignVerificalion
Verification by Readback and Signature Analysis
Simulating Bidirectional I/O Using SILOS
4-8

SECTION 5
Development Systems

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Development Systems

Overview ............................................................................................ 5-1
Design Flow .................................................................................. 5-4
Design Manager ............................................................................ 5-4
Design Entry and XNF Translation ................................................ 5-6
Optimization and Mapping ............................................................. 5-7
Merging .......................................................................................... 5-8
Translating to an LCA File ............................................................. 5-9
Placing and Routing ....................................................................... 5-10
Bitstream Generation ..................................................................... 5-11
Functional Full-timing Simulation ................................................... 5-12
Real-time In-circuit Verification ...................................................... 5-14
Automatic CAE Tools Product Overview ............................................ 5-16
DeSign Flow ................................................................................... 5-16
Platform and Environment Support ................................................ 5-16
Automatic CAE Tools Product Options .......................................... 5-19
Product Briefs
XC-DS310 DASH-LCA Schematic Editor,
Interface and Library ................................................................... 5-20
XC-DS31 DASH Schematic Interface and Library ......................... 5-21
XC-DS343 Mentor Graphics Schematic and
Simulation Interfaces and Library ................................................ 5-22
XC-DS35 OrCAD SDT Schematic Entry Interface
and Design Library ...................................................................... 5-23
XC-DS390 VIEWdraw-LCA Schematic Editor,
Interface and Library ................................................................... 5-24
XC-DS391 VIEWlogic VIEWdraw and VIEWsim
Interfaces and Library ................................................................. 5-25
XC-DS371 Language Entry Package ............................................ 5-26
XC-DS501 XACT DeSign Implementation System ........................ 5-27
XC-DS22 PC-SILOS Simulators .................................................... 5-28
XC-DS290 VIEWlogic Simulator .................................................... 5-29
XC-DS351 OrCAD VST Simulator Interface .................................. 5-30
XC-DS381 Cadence Design Kit ..................................................... 5-31
XC-DS112 and XC-DS113 Serial Configuration PROM
Programmer and Adapter ............................................................ 5-32
Xilinx Development System Support Agreements .............................. 5-33
LCA Macro Library Listings ................................................................. 5-34
Development System Hardware Requirements .................................. 5-40

Xilinx Design FlOw Overview (PC or Workstation)
Step

1

Design Entry

"
Step

2

Design Implementation

"
Step

3

Design Verification

195501A

5-1

Development System Overview

Logic Cell Array Design Flow

STEP 1

Design Entry

XNFNETLlsT
OUTPUT

195502

o

Open development system supports design entry and
simulation on popular CAE systems

o

Interfaces available from Xilinx for PC and workstationbased environments:
o FutureNet, VIEWdraw, OrCAD, Mentor

o
o
o

Standard macro library includes over 100 elements
TTL library includes over 100 elements
ABEL, CUPL, Log/IC, PGADesigner designs may be
merged with schematic input

o

Several other PC and workstation environments are
supported by third-party vendors

o

Xilinx State Machine Compiler provides efficient state
machine implementation for LCA architecture

Schematic entry on your PC/workstation
5-2

EXIUNX
Logic Cell Array Design Flow
STEP 3

STEP 2

Design
Implementation

BITSTREAM
FILE OUTPUT

Design
Verification
195503

Cl Complete system translates design into programmable gate arrays
Cl Partitionsgat~-Ievel design logic into LCA architecture (CLB/IOB), '.'
Cl Automatic IogiC(~ductiGl1 and partitioning removes
unused logic,e.g.unused counter outputs
Cl Logic synttlesissof{ware optimizes design for LeA
.0
architecture

Cl Interfaces available from Xilinx to popular simulators
for logic and full timing simulations
- Me!1tor Graphics
- VIEWlogic
...,. SILOS
. - OrCAQVST
rj LeA user-programmability permits realtime, in-circuit
.debugging
Cl Download cable allows the LCA to be programmed
in-circuilduring debugging
XC-QS28AACTOR orMESA**ln-Circuit Design
Verifier provides additi9nal hardware debugging
capabilities

Cl All progr&rns run onPC/Ar-compatible personal
computers and Apollo, Sun-4, Sun-3; and
DECstation engineeri~ Wor;kstations

o

•
Automated Design Implementation software

Immediate production

"PC/AT is a trademark of IBM Corporation
""MESA is a trademark of Dam 1/0 Inc.

5-3

~XILINX

Design Flow

The Xilinx Design Manager-Simplifies the Design Flow
• Lets you run all Xilinx software from menus
• XMAKE facility automates the translation of a design
into an LCA file, including optimization, mapping and
merging.

• Provides on-line help for all menus, programs and
options.

Xt ...

XMAKE Command
• Automatically invokes all other translation programs as
required to compile a design into an LCA file ready for
placement and routing
• Supports hierarchically structured designs

Extensive On-line Help
The Design Manager contains on-line Help for
• Every menu
• Every program
• Every program option
• Design-flow suggestions

5-4

E:XlUNX

Design
Processing Sequence

Design Manager Menu
Design Entry

Description
Create your design by running your schematic editor
while inside the Design Manager

I

STEP 1
With one mouse click, automatically

Translate

• Translate all schematic pages and PAL designs to
Xilinx format
• Merge PAL designs and state machines into
schematics
• Optimize PAL designs and state machines using
Logic Synthesis

Optimization
& Mapping

• Map all logic into CLBs and lOBs

STEP 2

STEP 3

Place Route

I

Run Automatic Place and Route (APR) program and/
or XACT Design Editor to place/route design

Bitstream
Generation

Run MAKEBITS program to compile design into a
configuration bitstream for an LCA

Verify

Run simulator, e.g., SILOS or VIEWsim, or in-circuit
design verifier, e.g., XACTOR or MESA, to debug
your design
195504

The Xilinx DeSign Manager provides a highly automated environment for converting your designs into
working field-programmable gate-array designs.

ThiS sequence is illustrated -

for a very simple design - on the following pages ...

5-5

II

Design Flow

Step 1: Design Entry and XNF Translation

XMAKE
Schematics

PAL

Designs
State
Machine
Designs

Xilinx
State Machine
Language

Shaded area indicates commands
automatically invoked by execution of
XMAKE in the Design Manager.

IPAD

TITLE
DECODE.PDS
AUTHOR
COMPANY
XILINX
DATE
CHIP
DECODE PAL10H8
; Input Pins
dO d1

IBUF
CLOCK

ao

;Output Pins

Gt.".-i DO

out

PAL1

;Define counter states

Q1

G+----1D1
FILE.
DECODE

OUTPUT LOW
WHEN
COUNT_2

STRING
STRING
STRING
STRING

ZERO
ONE
TWO
THREE

'ld1

'Idl
, dl
, d1

*
*
*
*

IdO'
dO'

Ida'
dO'

EQUATIONS
out ~ ZERO + ONE + THREE

L -______________________________~,~~.~~~ L ________________________~

Schematics can include any numberof
PAL devices created with Boolean
equations and/or state machines

Very simple PAL design included
in schematic at left with PAL1
symbol

-an example of a VHDL-State
description of a traffic light
controller
- (cases omitted for readability)
CHIP traffic YL
OUTPUT LOW
WHEN
COUNT =2

OECODECLB

195406

1954 07

A graphic representation of the CLB containing
the PAL logic. In a typical PAL design, of course,
several CLBs would be used.

A graphic representation of the top-level MAP file. Unused
logic (if any) has been deleted and the remaining logic has
been grouped (mapped) into Configurable Logic Blocks
and I/O Blocks.

5-7

Design Flow

Step 2: Merging
XMAKE

Shaded area indicates commands automatically
invoked by execution of XMAKE in the Design
Manager.

iilll. I. .

n.J CLOCK
00
•••

...

01

NOT2
...

if

OlJTPUT LOW
WHEN
COUNT 2

DECODECLB
1954 09

The merged design contains the CLBs and lOBs for the entire design.

5-8

E:XltlNX
Step 2: Translating to an LeA File
XMAKE
Shaded area indicates commands automatically
invoked by execution of XMAKE in the Design
Manager.

Xilinx
LCA
Translator

LCA

l - - - - - - . - - - -..

To Place
and Route
Page 5-10

Unrouted
Logic Cell Array

File

To Simulator
' - - - - - _ (Unit-delay Simulation)

Page 5-12
1954108

{}

{}

i1
{}

{}

0
{)
{]

0 0 [l o a 0
0 0 0 0 a0 0
0 0 [l 0 0 0 0

[l

a0

G {}0

aa0
0 0 0 o0

G0

[l

{}

~

{}

0 0
0 Q
{)
{}
{} 0 0 0 0 0 o 0 0 G
n 0 0 [) 0 a o 0 [) {}
a
0
a 00 co o;J OOCOO 00 co o;:f -0
{}

0

OU eJ[

II

[
195411

1954 02

Initially (before Place and Route) the LCA design is
unrouted, and the Configurable Logic and 1/0 blocks are
put in random locations.

5-9

Design Flow

Step 2: Placing and Routing the LeA File

LeA

Automatic Place
and Route Program
(APR)
and/or
XACT Design Editor

Unrouted
LCA File

LCA

Placed and Routed
LCAFile
To Simulator
' - - - - - _ Full Timing Simulation
Page 5-12

DS501

1954 12B

00

n

o
1954 18

A simple placed and routed design (closeup of upper-left
corner of 2064PC68).

5-10

The Automatic Place and Route (APR)
program uses sophisticated algorithms to
determine the optimal placement and routing
for a design. The XACT Design Editor, an
interactive graphics-based placement and
routing tool, is available for the experienced
designer who wants to pre-place critical
portions of the design or "tweak" the output of
the APR program.

Step 2: Bitstream Generation

BIT

Configuration
Bitstream
Compiler
(MAKEBITS)

t----------

To In-Circuit
Design
Verification
Page 5-14

DS501
1954 14B

The BIT file contains the binary configuration data that
programs an LCA to perform the design function.

1111111100100000000000111001111001001111
0011111111011111111111000101111011111101
0111111010110111011110111011111110111111
0111011101101111011111110111111101111111
0011111111111111111111111111011111111111
0111001101110111011101111011111110111111
1111111100100000000000111001110001001111

II

0011100011110111110111111111111111111111
0011111110111111111101111110111111111111
0011111111111101111111111111101111101111
0111111011101110111111101111111011111110
0111111010110111011 ...

LCA Configuration Bitstream

5-11

Design Flow

Step 3: Functional and Full Timing Simulation

LCA

XNF

Xilinx
LCA2XNF
Translator
DS50t

SIM

XNF-toSimulator
Translator

CLB-Ievel
XNF File

Simulator
Nellist

Simulator
Stimulus
Definition

Simulator
(SILOS,
VIEWsim,
OrCAD,
Mentor QSim,
etc.)

Input
Patterns
1954 198

'L

I

CLOCK

CLOCK

1954 20

ao

Designer defines design inputs.

{

i
}/
}

"",.",

: LX.:i:·::"·}J''''··{
Q1

NOT2""

/

itf
\

OUTPUT LOW
WHEN
COUNT 2

.. '
DECODECLB

1954 09

LCA designs are simulated at the physical CLB and lOB level with worst-case
timing.

5-12

Step 3: Functional and Full Timing Simulation

Simulation provides for
design analysis under worstcase temperature, voltage, and
process conditions.

CLOCK

01

NOT2

1954 21

Each 1/0 pin and CLB output can be observed with a
simulator driven by input stimuli. The simulator displays
the logic behavior and ac performance of the design in
graphics or text form.

II

5-13

Design Flow

Step 3: Real-time, In-circuit Verification

BIT

HEX

Xilinx PROM
Format Generation
(MAKEPROM)

PROM
Programmer
(Xilinx, Data 1/0, etc.)

Con figuration
Bitstream File
DS501

Xilinx
Download Cable,
Provided with
XACTDesign
Editor

Download Bitstream from PC or Workstation
into LCA for In-circurr Verification
(no PROM programming)

DS501

Xilinx or Data 1/0
In-Circuit

Connect Emulator Pod(s) to
Tar!)et System for Real-time
In-clrcurr Verification

Desi~n

Verifier

DS28 or MESA
1954 15B

5-14

E:XIUNX
In-circuit verification lets you immediately see
how your LeA designs function. ..

Program a PROM ...
TARGET SYSTEM

O

Serial or Parallel

PROM

Programmed with
Configuration
DataforLCA

1954 16A

Use the Download Cable ...
TARGET SYSTEM
Download Cable connects to
LCA control pins on LCA
socket in your target system
Download Cable
connects to
parallel port of
PC or serial port
of workstation

LeA

o
1954 17A

... Or use the Xilinx XACTOR or Data 1/0 MESA Design Verifier

The XACTOR controller (left) can control up to four
emulation pods (center). An emulation header
(right) connects each pod to an LCA socket in the
target system.

5-15

II

Xilinx Automatic CAE Tools
Product Overview

DESIGN FLOW

An important feature of the XACT Development System is
the capability to incorporate deSign changes, frequently
encountered during verification. Small changes can be
made to the schematics and then automatically
incorporated into the existing design with minimal impact
on existing routing and performance. Using this
"incremental design" capability, the designer can develop
"production quality" programmable gate arrays on a PC or
engineering workstation.

The Xilinx Automatic CAE Tools (XACT Development
System) use a 3-step design process:
• Step 1 :

DESIGN ENTRY

• Step 2:

DESIGN IMPLEMENTATION

• Step 3:

DESIGN VERIFICATION

The Xilinx Logic Libraries and XNF Interface Products
support design entry with popular schematic logic drawing
systems supplied by multiple vendors, providing easy
entry to the XACT Development System. Logic entry from
Boolean equations or a variety of state machine language
systems is also supported in the Design Implementation phase.
Logic synthesis, partitioning, and optimization
translate the design specifications into CLBs
unique to the LCA architecture. Subsequent
perform automatic placement and routing
complete the LCA design.

PLATFORM AND ENVIRONMENT SUPPORT
The Xilinx Automatic CAE Tools, XACT, are currently
available for the following platforms:
• IBM PC/AT, PS/2, and compatibles
• Apollo DN4000 Series
• -Sun-4 and SparcStation Series
• Sun-3 Series 960 and above
• DECstation 3100 Series
Xilinx and third-party vendors have developed library and
interface products compatible with a variety of design entry
and simulation environments. Xilinx has provided a
standard interface file specification, XNF, to simplify file
transfers into and out of the XACT Development System.

programs
and lOBs
programs
(APR) to

While completely automatic implementation is desirable
for both low and high-complexity designs, the designer
may prefer an interactive process, especially in highperformance designs. This interactive editing can range
from rerouting a few previously automatically routed nets,
to pre routing critical nets or preplacing CLBs prior to
design completion using APR, to more extensive control
over logic partitioning and placement into CLBs. The
Automatic Place and Route software gives the designer an
option for direct control over specific logic mapped into
CLBs (partitioning) to provide better distribution of logic
signal routing through the LCA device. The XACT Design
Editor, XDE, is extremely versatile, ranging from design
entry to CLB and signal routing manipulations. This
combination of automatic and interactive design editing
capability is a unique feature provided by Xilinx.

Xilinx directly supports the following design environments:
• FutureNet DASH
• VIEWlogic VIEWdraw and VI EWsim
• Mentor Graphics NetED and Qsim
• OrCAD SDT and VST
• SILOS
Several other environments are supported by third-party
vendors.
A collection of over 100 TTL logic macrofunctions is
available for the schematic editors, and is included in the
appropriate packages at no charge.
The XACT Design Manager, XDM, simplifies the selection
of command-line options with pull-down menus and online help text. Application programs ranging from
schematic capture to APR can be accessed from the XDM,
while the sequence of program commands is generated
and stored for documentation prior to execution. The
XMAKE command in the XDM automates the entire
translation, optimization, merging, and mapping process.

Logic simulation or actual in-circuit emulation provides for
functional verification, while timing analysis permits
verification of critical timing paths under worst-case
conditions. The system contains a compiler to generate
bitstream patterns to configure theLCA device according
to the designer's specification. The overall design flow is
illustrated on page 5-17.

5-16

l:XlUNX

r---------,

STEP 1

DESIGN
ENTRY
r ABEL.CU---,
~L. I

0S371

I

I
LOG/IC
I PGADESIG NER. I

STATE
MACHINE
ENTRY

__ .l

L;-_~ll_-,
I
PALASM
ITRANSLAT
L
____ _ OR

_...I

MACRO
&
MSI
LIBRARIES

Jl..1
JI
"I

I

t
LOGIC
SYNTHESIS

~
I

FUTURENET
DASH-LeA

VIEWdrawLCA

DS310-PC1

DS390-PC1

I
OTHER
I
I SCHEMATIC ENTRY I
SYSTEMS
I
I
I MENTOR DS343-AP11
I OrCAD 0S35-PC1 I
I CADENCE 08-381 I
I
I

Lf"oo~ """'""...co. . ; .:-,; ,
I

j-~

II

1

I

}
(
JI

XNFNETLIST

l

I

'I
)

{}
LOGIC REDUCTION
PARTITIONING
& OPTIMIZATION

TRANSLA TlON INTO
CLBS& lOBS

STEP 2

DESIGN
IMPLEMEN TATION
08501

l0
AUTOMATIC
PLACE & ROUTE

{J.
LCA NElLIST

k

~

.... 1 INTERACTIVE
,,~

1"

DESIGN EDITOR

lk: ~~OCK' )J
NET TIMING
REPORT

-l.7
(

XNF NETLIST
ANNOTATED

J

1
•

I

J,.

TRANSLATED & ROUTED
TIMING ANNOTATION

BIT STREAM COMPILER.
MAKEBITS & MAKEPROM

I

-l.7

w..

'---y'

LOGIC
CELL
ARRAY

STEP 3

DESIGN
VERIFI CATION

,

.

LOGIC &
TIMING
SIMULATION

•

I
IN-CIRCUIT DESIGN
VERIFICATION

GATE LEVEL
SIMULATION

•

SERIAL CONFIGURATION
PROM PROGRAMMER
DSl12

t--

I

{}

t---

L::::j

XILINX
SERIAL PROMS

I
X1748

5-17

5-18

Xilinx Automatic CAE Tools Product Overview

Xilinx Automatic CAE Tools Product Options

Step
1

"
Step
2

•
•
•
•
•
•
•
•

Language Entry Package
OASH-LCA Editor and interface
FutureNet DASH Interface
Mentor Graphics NetEd and Qsim Interface
OrCAO SOT Interface
VIEW-LCA Schematic Editor and Interface
VIEWdraw and VIEWsim Interface
Cadence Design Kit

OS371
OS31 0
OS31
OS343
OS35
OS390
OS391
OS381

• XC2000 & XC3000 Series XACT Design
Implementation System

OS501

•
•
•
•

OS22
OS290
OS351
OS112

~,

Step
3

SILOS Simulator and Interface
VIEWsim Simulator and Interface
OrCAO VST Interface
Serial Configuration PROM Programmer

II

5-19

XC-DS310 DASH-LCA
Schematic Editor, Interface
and Library
Step 1 Option

Product Brief

FEATURES
DASH-LCA supports unlimited levels of hierarchy. The
Xilinx DASH-LCA Schematic Library provides the symbol
library and conversion utility to permit designers to enter
LCA designs with the DASH-LCA Schematic Editor. The
Xilinx library provides the logic, 1/0, and macro symbols to
be used in the schematic. A Xilinx conversion utility
converts the schematic into an XNF output file.

• Xilinx only FutureNet DASH-LCA schematic editor
provides easy-to-use hierarchical LCA design
capability
• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, input/output and clock elements

Once partitioned, the design may be placed and routed
with the XC-DS501 XACT Design Implementation
System. The Xilinx symbol library includes symbols to flag
critical data and clock signals which the Automatic
Placement and Routing Program uses to prioritize those
signals for minimum delay.

• Additional 100 7400 TIL library elements. See
page 5-34 for a listing of TIL macros
• User control for flagging critical paths for the
Automated Placement and Routing program
• Converts schematic drawings to a Xilinx Nellist
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
• Runs on PC/AT or compatible personal computers

GENERAL
Schematic entry and automatic partitioning of LCA
designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

3002

5-20

XC-DS31 DASH
Schematic Interface and
Library
Step 1 Option

Product Brief

FEATURES

GENERAL

• Library and translator for users of the DASH Schematic
Designer

Schematic entry and automatic partitioning of LCA
designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, input/output and clock elements

The Xilinx DASH Schematic Designer Library provides the
symbol library and conversion utility to permit designers to
enter LCA designs with the DASH Schematic Designer.
The Xilinx library provides the logic, 1/0, and macro
symbols to be used in the schematic. A Xilinx conversion
utility converts the schematic into an XNF output file.

• Additional one hundred 7400 MSllibrary elements. See
page 5-34 for a listing of all macros.
• User control for flagging critical paths for the
Automated Placement and Routing program
• Converts schematic drawings to a Xilinx Netlist Format
(XNF) output file

Once partitioned, the design may be placed and routed
with the XC-DS501 XACT Design Implementation
System. The Xilinx symbol library includes symbols to flag
critical data and clock signals which the Automatic
Placement and Routing Program uses to prioritize those
signals for minimum delay.

• Output compatibility with XC-DS501 XACT DeSign
Implementation System
• Runs on PC/AT or compatible personal computers,
Sun 3 and Sun 4

Xilinx provides ongoing support for users of the DASH
Schematic Designer Library. For the first year, software
updates are included. After that, the user may purchase
the XC-SC31 Annual Support Agreement to continue to
receive the latest software releases.

5-21

II

XC-DS343 Mentor Graphics
Schematic and Simulation
Interfaces and Library
Step 1 Option

Product Brief

FEATURES

GENERAL

• Mentor Graphics certified interfaces
• The IDEA· Interface Station can be used for
schematic entry and simulation of programmablegate-array designs

Schematic entry and automatic partitioning of LCA
designs shorten logic reduction and product-development
times. Complex designs can be specified schematically
and quickly implemented for full timing simulation and
in-circuit design verification.

• Full timing simulation with post placement/routing
information

The Xilinx DS343 package provides the symbol library
and conversion utility to permit designers to enter LCA
designs with the Mentor Graphics NetED Schematic
Editor. The Xilinx library provides the logic, I/O, macro,
and TTL symbols to be used in the schematic. A Xilinx
conversion utility converts the schematic into an XNF
output file.

• Primitive library includes flip-flops, latches, AND, OR,
XOR, NAND, NOR gates
• Macro library includes over 100 standarcllogic
elements (counters, multiplexers, registers, etc.)
• Additional one hundred 7400 MSllibrary elements
included at no charge. See page 5-34 for a listing of
all macros (available 1H91).

Once partitioned, the design may be placed and routed
with the Apollo-based XC-DS501 XACT Design
Implementation System. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.

• Xilinx Netlist Format (XNF) output is compatible with
XC-DS501 Design Implementation System
• Available on Apollo SR10.1 and Mentor IDEA V7.0

->
->
->
->
->
->
->
->
->
->

[shit.Out) )
I st1. [0, O,O} J:
I st1, [0, O.OJ J;
I stl.[O,O,OJ]:
I st2. [1,0,0] 1:
I st4. [1,1,0]]:
I st4. [1,1,0] J:
I stS, [0,1,0)]:
I st6. [O,l,lJ J:
I st6. [0,1,1] 1;
I at7, [O.l,OJ J:
I st? [O,l,OJ 1:
I stl. [O.O,OJ J;
[sbit,Out] )
I stl, [O,O,OJ 1;
I stl. [0,0,01];
I st1, [O.O,OJ 1:
I st2, (l,O,Oll:
I st3, [0,1,011;
I st3, [0,1,0]);
I st4, [1.1.0)1;

-> (sbit,out) )
I
I
I
I
-> I
-> I

stl,
st1.
stl,
st4,
stS,
st6.

[0,0,01 J;
[0,0,0] J;
[0,0,0] I;
[1,1.0] J;
[O,l,O}];
[0,1 .. 1));

end

Example of State Machine using Xlllnx-ABEL-HDL

'ABEL and ABEL-FPGA are trademarks of Data I/O Corporation

5-26

XC-DS501 XACT
Design Implementation
System
Step 2

Product Brief

FEATURES

The XACT Design Editor (XDE), can then be used to
modify design placement and routing, when required to
meet critical timing requirements. Checks for logic
connectivity and design rule violation are easily performed
using the XDE. All unused internal nodes are automatically
configured to minimize power dissipation.

• Complete system for implementing programmable
gate array designs into LCA architecture
• Accepts Xilinx netlists created from schematic editors,
Boolean equations, or state-machine descriptions
• Automated logic reduction and partitioning removes
unused, disabled logic
• Automated placement and routing of logic minimizes
design cycle time
• Interactive editor for design optimization
• Point-to-point timing calculations forcritical-path
analysis
• Demo board for training ahd trYing out concept designs
• Download cable to transfer configuration programs
from PC or workstation to lCA in target system
• Available on PC/AT, Apollo, Sun-3, Sun-4 and
DECstation computers

Interactive POint-to-pointtimingdelay calculation is provided
for timing analysis and critical-path determination. This
ability enables the user to quickly identify and correct
timing problems while the design is in progress.
A download cable is included with the DS501. It is useful
for transferring configuration programs serially from the
PC orworkstation to an lCA device installed in a system or .
on the demo board. During product development and
verification this capability can be used to save the time
required to write a modified configuration program into
an EPROM.

DESIGN IMPLEMENTATION PROCESS
Designers often describe portions of their deSign, such as
countersandgllJelogic,withschematics,andotherportions
of the design, such as decoders, with Boolean equations.
Automatic Placement and Routing software, APR, permits
designers to merge muHiple modes of design entry into a
single design.

•

The figure on page 5-17 illustrates the design flow from a
design schematic with some glue logic, a 7400-MSI macro,
and a PlD symbol. The design files are merged and
partitioned into ClBs and lOBs.
The AutomatiC Placement and Routing software, APR, is
very flexible. Routing resources can be specified to
eliminate clock skews and minimize rouling delays for
critical paths.

5-27

XC-OS22 PC-SILOS*
Simulators
Step 3 Option

Product Brief

FEATURES

prior to final placement and routing. After a circuit has
been placed, routed and then fully debugged using
in-circuit emulation, worst-case timing may be verified.
This enables the user to select the correct Logic Cell Array
speed grade for a particular application.

• PC-based simulator for LCA-design verification
• Simulates any LCA design, regardless of design input
format (combined logic schematics, Boolean equations, and state machine descriptions)

Network inputs for LCA designs are automatically created
by the XNF2SILO utility. The network includes logic and
routing-delay parameters and set-up and hold times
based upon the selected speed grade operating under
worst-case conditions. Simulation stimuli are created with
a set of clock statements or with an input pattern for either
pad inputs or internal nodes. Simulation results are
available in tabular, plotted and graphic formats. This
flexibility makes the "logic debug" easy for both the circuit
function and timing.

• General-purpose event-driven logic and timing
simulator
• Input automatically generated from XNF file
• Control and observation of any physical circuit node
• Multiple-file input for vectors and commands
• Interactive or batch-mode operation
• Output available in printed or tabular formats
• Simulates logic complexities up to 16,000 gates
• Runs on a PCIAT or compatible personal computer

,-------------------,

GENERAL

I
I

PIC-SILOS is a powerful PC-based simulator that
provides event-driven logic and timing simulation of LCA
designs. Simulation/ is particularly useful for testing
designs or design SErgments as well as for verifying critical
timing over worst-case power supply, temperature and
process conditions.

I
I

XC-DS22
I
I
I

...-_....L.._--, PC-SILOS
SIMULATOR

I

L~~~~~~~~~~~~~~~~~"

Simulation is useful in several stages of the design cycle.
After design entry, simulation may be used to debug logic
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected

300501

·P/C SILOS is a trademark of SimuCad Corp.

5-28

XC-DS290 VIEWlogic
VIEWsim Simulator
Step 3 Option

Product Brief

FEATURES

or design segments as well as for verifying critical timing
over worst-case power supply, temperature and process
conditions.

• PC-based simulator for LCA-design verification
• Simulates any LCA design, regardless of design input
format (combined logic schematics, Boolean equations, and state machine descriptions)

Simulation is useful in several stages of the design cycle.
After design entry, simulation may be used to debug logic
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has
been placed, routed and then fully debugged using
in-circuit emulation, timing simulation may be performed.
This enables the user to select the correct LCA speed
grade for a particular application.

• General-purpose event-driven logic and timing
simulator
• Input automatically generated from XNF file
• Control and observation of any physical Circuit node
• Sophisticated waveform display
• Schematic capture and simulation integrated in one
environment (when using with VIEWdraw)
• Simulates logic complexities of the largest LCAs
• Runs on an PC/AT or compatible personal computer

GENERAL
VIEWsim is a powerful PC-based simulator that provides
event-driven logic and timing simulation of LCA designs.
Simulation is particularly useful for testing designs

Network inputs for LCA designs are automatically created
by the XNF2WIR utility. The network includes logic and
routing-delay parameters and set-up and hold times
based upon the selected speed grade operating under
worst-case conditions. Simulation stimuli are created with
a set of clock statements or with an input pattern for either
pad inputs or internal nodes. Simulation results are
available in tabular, plotted and graphic formats. This
flexibility makes the "logiC debug" easy for both the circuit
function and timing.

II

1111111888888188888888
1111111188888188888888
1111111181888188888888
1111111181888888888888
8111111181888888888888
1111111181888888888888
1111111111888888888888

1111111888888188888888
1111111188888188888888
1111111181888188888888
1111111181888888888888
8111111181888888888888
1111111181888888888888
1111111111888888888888

X1252

5-29

XC-DS351 OrCAD VST
Simulator Interface
Step 3 Option

Product Brief

FEATURES
been placed, routed and then fully debugged using
in-circuit emulation, worst case timing may be verified.
This enables the user to select the correct lCA speed
grade for a particular application.

• Model library and netlisttranslator for users of the
OrCAD VST Simulator
• Supports full timing simulation of routed lCA designs,
and unit-delay simulation of unrouted designs
• Permits simulation of schematics which include PAL
logic defined with PAlASM, ABEL, CUPl, logllC, or
PlDesigner.
• Input compatible with XACT Design Implementation
System
• Runs on a PC/AT or compatible personal computer

Network inputs for lCA designs are automatically created
by the XNF2VST utility from the XNF output of the XACT
Design Implementation System. The network includes
logic and routing delay parameters and setup and hold
times based upon the selected speed grade operating
under worst case conditions.

GENERAL
Simulation is particularly useful for testing designs or
design segments as well as for verifying critical timing over
worst-case power supply, temperature and process
conditions.

r---I
I

Simulation is useful in several stages of the design cycle.
After design entry, simulation may be used to debug logic
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has
197001

1970

5-30

XC-DS381 Cadence
Design Kit
Step 1 and Step 3 Options

Product Brief

FEATURES

GENERAL

• Provides a complete LCA design environment with a
consistent user interface and integration within the
Design Framework* environment

The design flow is managed through the flow diagram
integrated in the Cadence Framework II environment.
Designs are entered with Cadence Composer schematic
entry. Verilog-XL is used to perform functional simulation
before the design is implemented into LCA devices.

• Works with the Amadeus* System Design Series to
create a complete system-design environment

Next, the XACT Development System is activated by
clicking on the Xilinx button on the flow diagram. The
development system partitions the logic into I/O and logic
blocks, places the partitioned blocks, and then routes the
design. The design can be further enhanced for device
utilization and performance by using the interactive tools.
Output files, used for programming a PROM, can be
generated at this point.

• Easy integration into the Cadence composer
schematic-entry, the Verilog-XL** simulation, and
Veritime* timing-analysis environments
• Full simulation models provide for accurate postlayout timing analysis
• Provides a complete set of primitives and macros for
the XC2000, XC3000 and XC4000 families of LCA
devices

After implementing the design into LCA devices, timing
simulation is available via Verilog-XL; Veritime is used for
worst-case timing analysis. In-circuit verification is
performed by downloading the device configuration file
directly into a part. The device is then fully operational.
Incremental design changes can be made quickly and
painlessly at any stage of the design process .

• Supports hard macros for the XC4000 family
• May be used on Sun-4 and HP-Apollo work stations

I~

~ I cancetlo._1 _ I ....
OK

•

XC4000 )1
IIDOWNLOAD

~I

XC4000
llMING
SIMUlJl.llON

CABLE

~~

ii!AiN

I

--'1

I18riIog Stimulus .... Lto:;...t:::;:.':.;;ti:::;:'..;-.v_ _ _ _ _ _ _ _ _ _ _

DuId HetJIsl .... SimUlate

RIIII Options

•

Exec"1IOn

<>_"" • __

<> SimUlate only

~~~~~~~~~~~~~~~

'Design Framework, Amadeus and Veritime are trademarks of Cadence Design Systems, Inc.
"Verilog-XL is a registered trademark of Cadence Design Systems, Inc.

5-31

XC-OS112 and XC-OS113
Serial Configuration PROM
Programmer and Adapter
Step 3 Option

Product Brief

FEATURES

GENERAL

• Programs XC1736, XC1736A, XC1765 Serial
Configuration PROMs

When using Xilinx Serial Configuration PROMs to
configure programmable gate arrays, the designer can
program them with XC-DS 112 Configuration PROM
Programmer.

• Connects to serial port of PC/AT or compatibles
• Operates from PC via software provided with
program-ming unit

The programming unit connects to a serial port of a PC/AT
or workstation and is controlled using the software
included with the XC-DS112.

• Accepts HEX-format data files created by the DS501
XACT Design Implementation System
• Supports 8-pin mini-DIPs directly

Designers compile their LCA designs into a standard HEX
format file using the XACT development system. The
programming software provided with the XC-DS112 is
then used to download the HEX file into the programming
unit and to program a serial PROM.

• Supports 20-pin PLCC packages with optional DSl13
adapters
• Runs on PC/AT-compatible personal computers
Apollo, Sun-4, Sun-3, DECstation engineering
workstations
XC-DS112
PROGRAMMER

PC

(0625 RECEPTACLE)

2
3

[:
+V'-"""""6
GND 7

(0625 PLUG)

•
•

•

•

•

[~o •

TxD (FROM PC)
RxD(TO PC)
34 RTS
CTS
5 DSR
6 GND
7
DCD
820 DTR
2

•
•

XC-DSl12 Interface to PC

5-32

Xilinx Development System
Support Agreements

All Xilinx development systems come with free software
support for one year. To receive software updates, the
customer must become a registered customer by returning the registration card. Registering your software also
places you on the mailing list for XCELL, the Xilinx customer newsletter.

• Free use of the Xilinx Technical Bulletin Board. To
provide customers with up-tO-date information and an
immediate response to questions, Xilinx provides a 24hour electronic bulletin board. The customers who are
current with their support agreements and have full
privileges, can read files on the bulletin board,
download those of interest to their own systems or
upload files to the bulletin board.

Benefits include:
• Free software updates. Customer will receive new
releases of the software programs covered by the
agreement. Customer can enjoy enhanced functionalities, performance and bug fixes free of charge. Xilinx
typically provides about two new update releases per
year that include the necessary diskettes and
documentation required to implement each update.

• Free quarterly technical newsletter. This newsletter
gives updates on hardware and software availability
and revision levels, as well as known software bugs and
work-arounds. In addition, application ideas and user
tips and a list of relevant magazine articles make this a
valuable source of information.

• Toll free applications hot line and local field application
engineering support. Customers can receive expert
help instantly by calling our application hot-line: (408)
879-5199 or (800) 255-7778 and ask for
Applications Engineering.

After the first year, the above benefits are available
through Xilinx annual software support agreements. The
cost of the agreements are typically 12% to 15% of the
original price per year.

•
'99.
5-33

LeA Macro Library Listings

XC 3000

PADS
BPAD
IPAD
OPAD
UPAD

#ClBs
Bidirectional Package Pin Symbol.........................................
Input Package Pin Symbol ....................................................
Output Package Pin Symbol .................................................
Unbonded Die Pad Symbol ...................................................

0
0
0
0

XC2000
#ClBs

o
o
o

o

lOB SCHEMATIC ELEMENTS
TBUF
ACLK
GCLK
IBUF
INFF
INLAT
OBUF
OBUFZ
OUTFF
OUTFFZ
BUF
INV
PULLUP

Internal 3-State Buffer ...........................................................
Auxiliary Buffer ......................................................................
Global Buffer .........................................................................
Input Buffer ........................................................................... .
Input Flip-Flop .......................................................................
Input Latch .............................................................................
Output Buffer ... ......................................................................
Output Buffer with Output Enable ......................................... .
Output Flip-Flop .................................................................... .
Output Flip-Flop with OBUFZ ................................................
Internal non-inverting Buffer ................................................. .
Inverter ................................................................................ ..
Input pull-up Resistor ............................................................

o
o
o

o
o
o

o

o

o

o

o

o

o
o

o

o
o

o

1

o

GENERAL
BRLSHFT4
BRM
C3BIT8, 7 .. 4
C5BIT32, 31 ..9
C3 Square
C5 Square
GADD
GCOMP
GLTGT
GEQGT
GMUX
OSC
GXTL
GOSC
GMAJ
GXOR
GXOR2
GPAR

4-lnput Barrel Shifter ........................................................... ..
Binary Rate Multiplier .......................................................... ..
3-Bit Divide-by-8, 7 .. 4 Shift Register Counter .................... .
5-Bit Divide-by-32, 31 .. 9 Shift Register Counter ................ ..
Divide-by-3 with 50% Duty Cycle ........................................ ..
Divide-by-5 with 50% Duty Cycle ........................................ ..
1-Bit Full Adder ... ................................................................. ..
2-Bit Comparator ................................................................. ..
2-Bit Less Than/Greater Than Comparator ......................... ..
2-Bit Equal/Greater Than Comparator ................................ ..
2-to-1 Mux ....... ...... ............ ...... ............ ..... ..... .......... ....... .......
Crystal Osc ....... .................... .......................... ..... ..... .............
Crystal Osc (XACT: 3020 GXTL20, 2018 GXTL2) ................
Low Frequency Resistor-Capacitor Oscillator ..................... ..
Majority Gate ........ ................................................................ .
Exclusive-OR .........................................................................
Two Exclusive-OR .................................................................
Parity Test (Even = Low) ..................................................... ..
5-34

4

5
2
3
2
2

1
0
0

1

o
o

E:XJUNX
XC 3000
#CLBs

GENERAL (Continued)
HX83
HX85
HX280
HX283
HX518
HX521
HX125
HX240
HX241
HX244
HX245
HX540
HX541
MCOMP
PHFRCOMP
SAR

4-Bit Binary Adder With Fast Carry ........................................ .
4-Bit Magnitude Comparator ...................................................
9-Bit Parity Checker / Generator ............................................ .
4-Bit Binary Full Adder6 ..........................................................
8-Bit Identity Comparator ........................................................
8-Bit Identity Comparator ........................................................
3-State Bus Buffer ...................................................................
Octal Inverting Buffer, 3-State Outputs .................................. .
Octal Non-inverting Buffer, 3-State Outputs .......................... .
Octal Non-inverting Buffer, 3-State Outputs .......................... .
Octal Bidirectional Transceiver .............................................. .
Octal Inverting, 3-State Outputs ............................................. .
Octal Non-inverting, 3-State Outputs ......................................
Magnitude Comparator .......................................................... .
Phase/Frequency Comparator ................................................
Successive Approximation Register ...................................... .

XC2000
#CLBs

6
7
3
6

5

5

o
4
1

o
1

o
o
4
2
9

LATCHES

LD
LDRD
LDSD
LRS
LDM
LDMRD
LDMSD
LDSRD
HX77
HX259
HX373

Data Latch ...............................................................................
Data Latch with Reset Direct ................................................. .
Data Latch with Set Direct ......................................................
Set-Reset Data Latch with Reset Dominant .......................... .
Data Latch with 2-lnput Data Mux .......................................... .
Data Latch with 2-lnput Data Mux with Reset Direct ............ ..
Data Latch with 2-lnput Data Mux with Set Direct ................ ..
Data Latch with Set Direct, Reset Direct ................................ .
2-Bit Latch ...............................................................................
8-Bit Addressable Latch ............ .......................... ....................
Octal Latch with 3-State Outputs .............. ...................... ........

FLIP-FLOPS
FD
FORD
FDSD
FDSRD
FDC
FDCRD
FDCR
FDCS
FDR
FDS
FRS
FSR
FDM
FDMRD
FDMSD

D Flip-Flop ..............................................................................
D Flip-Flop with Reset Direct ................................................ ..
D Flip-Flop with Set Direct ..................................................... .
D Flip-Flop with Set Direct, Reset Direct .............................. ..
D Flip-Flop with Clock Enable .................................................
D Flip-Flop with Clock Enable, Reset Direct .......................... .
D Flip-Flop with Clock Enable, Reset .................................... .
D Flip-Flop with Clock Enable, Set ........................................ .
D Flip-Flop with Reset .............................................................
D Flip-Flop with Set .................................................................
Set-Reset Flip-Flop with Reset Dominant .............................. .
Set-Reset Flip-Flop with Set Dominant .................................. .
D Flip-Flop with 2-lnput Data Mux ..........................................
D Flip-Flop with 2-lnput Data Mux with Reset Direct ............ ..
D Flip-Flop with 2-lnput Data Mux with Set Direct ................ ..

5-35

8
4

•

Macro Lists

XC 3000

FLlP-FLOPS (Continued)
FDMR
FD\MS
FJK
FJKRD
FJKSD
FJKSRD
FJKS
FTO
FTORD
FTOR
FT
FTRD
FTP
FTPRD
FTR
FTS
FT2
FT2R
NDFF
PDFF

#CLBs

D Flip-Flop with 2-lnput Data Mux with Reset ............................ .
D Flip-Flop with 2-lnput Data Mux with Set ................................ .
J-K Flip-Flop ............................................................................... .
J-K Flip-Flop with Reset Direct ................................................... .
J-K Flip-Flop with Set Direct ....................................................... .
J-K Flip-Flop with Set Direct, ResetDirect ................................. .
J-K Flip-Flop with Set ..................................................................
SeH Toggle Flip-Flop ...................................................................
SeH Toggle Flip-Flop with Reset Direct ...................................... .
SeH Toggle Flip-Flop with Reset ................................................ .
Toggle Flip-Flop ..........................................................................
Toggle Flip-Flop with Reset Direct ..............................................
Toggle Flip-Flop with Parallel Enable ......................................... .
Toggle Flip-Flop with Parallel Enable, Reset Direct ....................
Toggle Flip-Flop with Reset ..... ... .... ..... ..... ..... ..... ..... ....... ..... .... ....
Toggle Flip-Flop with Set ............................................................
2-lnput Toggle Flip-Flop ..............................................................
2-lnput Toggle Flip-Flop with Reset ........................................... .
Negative Edge Flip-Flop Primitive .............................................. .
Positive Edge Flip-Flop Primitive ............................................... .

XC2000
#CLBs

1

1
1

DECODERS/ENCODERS
02-4
D2-4E
74-139

1-of-4 Decoder ............................................................................
1-of-4 Decoder with Enable .........................................................
1-of-4 Single Decoder with Enable, Low Output .........................

2
2
2

03-8
D3-8E
74-138
74-42
HX42
HX48
HX138
HX139
HX147
HX148
HX154
HX278

1-of-8 Decoder ............................................................................
1-of-8 Decoder with Enable .........................................................
1-of-8 Decoder with Enables, Low Output ..................................
1-of-10 Decoder with Low Output................................................
4-to-10 Line Decoder...................................................................
BCD to Seven Segment Decoder. ...... ... ..... ..... ..... ....... ..... ...........
1-of-8 Decoder/Demultiplexer .....................................................
1-of-4 Decoder ............................................................................
10-to-4 Line Priority Encoder.......................................................
3-to-8 Line Priority Encoder.........................................................
1-of-16 Decoder/Demultiplexer ...................................................
4-Bit Cascadable Priority Encoder .......... ..... ....... ..... ..... ....... .......

4
4

5
5
5
5
5

2
2
2
4

5
6
7

2

5
9
9
6

MULTIPLEXERS
M3-1
M3-1E
M4-1
M4-1C
M4-1E
74-352

3-to-1
3-to-1
4-to-1
4-to-1
4-to-1
4-to-1

Mux ...................................................................................
Mux with Enable................................................................
Mux ...................................................................................
Mux ...................................................................................
Mux with Enable................................................................
Mux with Enable, Low Output ...........................................

5-36

2

2
2

2
1

3

2

3
3

2

XC 3000

MULTIPLEXERS (Continued)
M4-2
M8-1
M8-1E
74-151
74-152
HX151
HX152
HX153
HX157
HX158
HX257
HX258
HX352

#CLBs

4-to-2 Mux ...................................................................................
8-to-1 Mux
8-to-1 Mux with Enable................................................................
8-to-1 Mux with Enable, Complementary Outputs.......................
8-to-1 Mux with Low Output ........................................................
8 Input Multiplexer. ....... ....... ..... ..... ....... .... ....... .......... ..... ..... ........
8 Input MuHiplexer ... ....... ... ...... ..... ..... ... ..... ....... .... ....... ..... ...........
Dual 4 Input MuHiplexer ....... ..... ..... .......... .... ............. ........... ........
Quad 2 Input Multiplexer .............................................................
Quad 2 Input Multiplexer .............................................................
Quad 2-to-1 Multiplexer with Enable ...........................................
Quad 2-to-1 Inverting Multiplexer ................................................
4-to-1 Data Selector I Multiplexer ................................................

1
4
4

4
4

XC2000
#CLBs

7
7
7
7

5
4
6
4
3
2
2
5

REGISTERS
Data Reg isters
RD4
RD4RD
RD8
RD8RD
RD8CR
HX174
HX273
HX298
HX374
HX377
HX577

4-Bit Data Register ........ ....... ..... ....... .... ..... ..... ............ ..... ....... .....
4-Bit Data Register...................... ................................................
8-Bit Data Register ........ ....... ..... ....... .... ..... ... ............ ....... ..... .......
8-Bit Data Register with Reset Direct ....... ... .... ........ ..... ......... ......
8-Bit Data Register with Clock Enable, Reset .............................
Hex D Register with Master Reset... .... ... ..... .... .......... ..... ............
Octal D Flip-flop... ....... ............ .............. ... ..... ........... ..... ..... ..... .....
Quad 2 Input Flip-flop ..................................................................
Octal D Flip-flops with 3-State Outputs ... ..... ......... ....... ...............
Octal D Flip-flops with Clock Enable...........................................
Octal D Flip-flops with Reset and 3-State Outputs ....... ..... ....... ...

2
2
4
4
4
4
4
4
4
4

4

8

8

4

Serial to Parallel
RS4
RS4RD
RS4C
RS4CRD
RS4CR
74-195
74-194
RS8
RS8RD
RS8R
RS8C
RS8CRD
RS8CR
RS8PR
74-164
HX164
HX166

4-Bit Shift Register ......................................................................
4-Bit Shift Register with Reset Direct ......................................... .
4-Bit Shift Register with Clock Enable .........................................
4-Bit Shift Register with Clock Enable, Reset Direct .................. .
4-Bit Shift Register with Clock Enable, Reset ... ......................... .
4-Bit Serial to Parallel SR with ParEna, MRLow ........................ .
4-8it 8i-Directional SR with ClkEna, ParEna, MRLow .............. .
8-8it Shift Register ......................................................................
8-8it Shift Register with Reset Direct ................................. ,...... ..
8-8it Shift Register with Reset... .... ..... ... ..... ..... ........... .................
8-Bit Shift Register with Clock Enable ..... ... ....... .... ........ ..... .........
8-8it Shift Register with Clock Enable, Reset Direct ...................
8-8it Shift Register with Clock Enable, Reset .............................
8-Bit Shift Register with Parallel Enable, Reset ..........................
8-Bit Serial to Parallel SR with Master Reset Low. ....... ..... .........
8-Bit Serial In-Parallel Out Shift Register........ .... ... ..... ..... ....... ....
Parallel Load 8-Bit Shift Register ... ..... ..... .... .............. ..... ..... .......

5-37

2
2
2
2
2
3

5
4
4
4
4
4
4
4
5

5
6

4

5
12
8
8

8
8
8

•

Macro Lists

XC 3000

XC2000

#CLBs

#CLBs

REGISTERS (Continued)
HX179

4-Bit Parallel Access Shift Register ..... ... ..... ....... .... ........ ......... ....

5

HX194
HX195

4-Bit Bidirectional Universal Shift Register ... ....... ..... ....... ............
4-Bit Parallel Access Shift Register ..... ........ ...... ..... ....... ........ ......

7
3

HX198
HX199
HX595

8-Bit Bidirectional Shift Register ..................................................
8-Bit Shift Register with Clock Inhibit ..........................................
8-Bit Shift Register with 3-State Register Output. ......... ....... ... ....

14
7
9

COUNTERS
Modulo 2
C2BCP
C2BCPRD
C2BCR
C2BCRD
C2BP
C2BR
C2BRD

1-Bit Binary
1-Bit Binary
1-Bit Binary
1-Bit Binary

Counter wI Clock Enable, Parallel Enable .............. .
Counter wI ClkEna, ParEna, Reset Direct .............. .
Counter with Clock Enable, Reset .......................... .
Counter with Clock Enable, Reset Direct... ............. .

1-Bit Binary Counter with Parallel Enable .................................. .
1-Bit Binary Counter with Reset ................................................. .
1-Bit Binary Counter with Reset Direct ....................................... .

Modulo 4
C4BCP
C4BCPRD
C4BCR
C4BCRD
C4JX
C4JXRD
C4JXC
C4JXCRD
C4JXCR

2-Bit
2-Bit
2-Bit
2-Bit
2-Bit
2-Bit
2-Bit
2-Bit
2-Bit

C4JCR

2-Bit Johnson Counter with Clock Enable, Reset... .................... .

Binary Counter with Clock Enable, Parallel Enable ........... .
Binary Counter wI ClkEna, ParEna, Reset Direct .............. .
Binary Counter with Clock Enable, Reset .......................... .
Binary Counter with Clock Enable, Reset Direct ................ .
Expandable Johnson Counter ........................................... ..
Expandable Johnson Counter with Reset Direct ............... .
Expandable Johnson Counter with Clock Enable .............. .
Expandable Johnson Cntr wlClkEna, Reset Dir ................ .
Expandable Johnson Counter with ClkEna, Reset ............ .

3

2
2
2

2
2

2

1

2

Modulo 6
C6JCR

3

3-Bit Johnson Counter with Clock Enable, Reset... .................... .

2

Binary Counter wI ClkEna, Parallel Enable .........................
Binary Counter wI ClkEna, ParEna, Reset Dir ....................
Binary Counter with Clock Enable, Reset ...........................
Binary Counter with Clock Enable, Reset Direct... ..............
Johnson Counter with Clock Enable, Reset... .....................

3
3
3
2
2

.........................
.........................
.........................

Counter with Clock Enable, ResetDir .........................
Counter with Parallel Enable, ResetDir ......................

3
4

Counter wI ClkEna, ParEnaL, MRLow .......................
Counter wI ClkEna, ParEnaL, Reset Low ..................
Counter wI Parallel Enable, Reset Direct ...................

6
7
4

.........................
.........................
.........................
.........................
.........................

Modulo 8
C8BCP
C8BCPRD
C8BCR
C8BCRD
C8JCR

3-Bit
3-Bit
3-Bit
3-Bit
4-Bit

.........................

.........................

5
4
4
4

Modulo 10
C10BCRD 4-Bit BCD
C10BCPRD 4-Bit BCD
74-160
4-Bit BCD
74-162
4-Bit BCD
C10BPRD
4-Bit BCD

5-38

4
7
8
6

l:X1UNX
XC 3000
# CLBs

COUNTERS (Continued)
C10JCR
HX160
HX162
HX168
HX390

XC2000
#CLBs

5

5-Bit Johnson Counter with ClockEnable, Reset........................
Presettable Decade Counter ............ ............ ............ ...................
Presettable Decade Counter with Sync Clear ............ ............ .....
4-Bit BCD Synchronous UplDown Counter .................................
4-Bit Decade Counters with Clear ............ ............ ............ ...........

3
a
10
11
3

6-Bit Johnson Counter with Clock Enable, Reset... .................... .

3

.........................

6

C16BARD4-BitBinary Ripple Counter with Reset Direct ............................ .
C16BCRD 4-Bit Binary Counter wI ClkEna, Reset Direct ...... ,..................... .
C16BCP
4-Bit Binary Counter wI ClkEna, Parallel Enable ........................ .
C16BCPRD 4-Bit Binary Counter wI ClkEna, ParEna, Reset Direct .............. .
74-161
4-Bit Binary Counter wI ClkEna, ParEna, MRLow ...................... .
C16BCPR 4-Bit Binary Counter wI Clock Enable, ParEna, Reset ............... .
4-Bit Binary Counter wI ClkEna, ParEnaL, Reset Low ............... .
74~163
C16BPRD 4-Bit Binary Counter WI Parallel Enable, Reset Direct ............... .
C16BUDRD 4-Bit Binary Up-Down Cntr wI ParEna, ResetDir ......... ,...........,..
C16JCR
a-Bit Johnson Counter with Clock Enable, Reset... .................... .
HX161
Presettable Binary Counter ....................................................... ..
HX163
Synchronous Binary Counter with Sync Clear .......................... ..
HX169
4-Bit Binary Synchronous UplDown Counter ............................ ..
HX393
4-Bit Binary Counters with Clear .................................................
HX590
a-Bit Counter with Register and 3-State Output ......................... .

2
3
5

.........................
.........................
..........................
.........................
.........................
.........................
.........................
.........................
.........................
.........................

4
4

Modulo 12
C12JCR
Modulo 16

5
6
6
7
4
5
4
6
a
7
5
13

6
a
10
5
8
8

.........................

.........................
.........................
.........................
.........................

Modulo 256
C256BCRD 8-Bit Binary Counter with Clock Enable, Reset Direct.. ............. ..
C256BCR
a-Bit Binary Counter with Clock Enable, Reset .......................... .
C256BCP
a-Bit Binary Counter wI ClkEna, Parallel Enable ........................ .
C256BCPRDa-BitCounterwl ClkEna, ParEna, Reset Direct ......................... .
C256FCRD a-Bit Mod 256 Feedback SR wI ClkEna, ResetDir .................... ..
C8UDLD
a-Bit Loadable Up/DownCounter ................................................
C16UDLD 1,6~Bit Loadable UplDown Counter ..............................................

5-39

7

7
8
8
6
9
18

II
9

......... ' ..... .. ,.....
~.

,',

Development System
Hardware Requirements

Xilinx provides an integrated development system for
design and .implementation of LCA devices. The XACT
development system operates on any 386-based or 486based IBM or IBM-compatible PC with 8 Mbytes of
extended memory (RAM), 80 Mbytes of hard-disk space,
and a VGA display. Pre-1991 versions of the XACT
system also operate on 286-based IBM PC/AT or IBM PSI
2 models, but with reduced performance. Some older 286based clones with non-IBM compatible BIOS have been
reported to have problems.

To assure integrity, all Xilinx software is tested on IBM
systems and several compatible systems. LCA
development software includes some of the first DOSbased programs to make extensive use of the ·protected"
mode of the processor. This has exposed protected mode
IBM-incompatibilities of some clones, usually in the BIOS
or Keyboard Controller. Xilinx software includes system
.exercises called PMTEST and PMINFO to help test IBM
compatibility and measure relative performance.
Note that the amount of memory listed above must be
available to XACT, i.e., it does not include the memory
used for other resident programs. Also, the Compaq 386
has only 640 Kbytes of its first megabyte available to any
user.

The XACT development system operates also on a variety
of workstations, like Apollo, DECstation 3100, Sun-3, and
Sun-4. This broad choice of platforms provides the user
with a convenient low-risk low-cost method of logic-design
entry, simulation, LCA generation and verification for
single-chip logic designs of up to 9000 gates. In addition,
several popular PC and workstation CAE vendors have
developed and offer deSign-entry and simulation
programs compatible with the XACT Development
System

PC I/O Ports

The LCA Development System requires several VO ports.
A parallel port is needed for the software execution
protection key. The key must be in place to allow Xilinx
software to execute but is virtually transparent, and the
port can be used simuHaneouslyfor a parallel printer or the
Xilinx download cable. Several printer types are supported
for text or graphic hard copy. Serial COM ports are used for
a mouse and for the Configuration PROM Programmer.

MINIMUM PC REQUIREMENTS
•
•
•
•
•
•
•

386 or 486-based IBM-PC or compatible
One high-density floppy disk drive, 5.25" or 3.5"
80 Mbyte hard disk drive
VGA display
Two RS-232-C serial ports and one parallel port
Mouse
MS-DOS version 3.0 or higher

Part Type

XC2000 Family
XC3020, XC3030
XC3042
XC3064
XC3090

PC Mouse
The Xilinx Development System programs are compatible
with several varieties of mice offered for the PC. These
include Mouse Systems PC Mouse (no device driver
required), Microsoft (serial or parallel), LogiTech C7 and
the FutureNet mouse. The Xilinx software supports any
mouse directly that emulates the PC mouse or has a
device driver that provides Microsoft compatibility and
defines the PC COM port.

Total· Memory Required for
XACT4.1

2.50 Mbytes
3.25 Mbytes
4.00 Mbytes
5.25 Mbytes
6.50 Mbytes

Please note however, only the Mouse System M4 and the
LogiTech C7 will work with the VIEWlogic software,
VIEWdraw-LCA and VIEWsim.

"Total- Extended memory plus 640 Kbytes base memory.

11..

5-40

PC Setup
Sun·3 Requirements
Series 60 and above
• Sun Operating System OS4.1
• 60 Mbytes allocated for Xilinx designs
• 16 Mbytes of RAM
• Color Monitor
• X-Windows
• Openlook or MOTIF

When the system is powered up it uses commands from
the DOS CONFIG.SYS file to install selected device
driver-programs (such as Mouse driver) in memory
and define buffer and file sizes. Examples of these
statements are:
device=C:\lib\msmouse.sys /1
files=10
buffers=20

Sun·4 Requirements
Sun-4 & SparcStation Series
• Sun Operating System OS4.1
• 60 Mbytes allocated for Xilinx designs
• 16 Mbytes of RAM
• Color Monitor
• X-Windows
• Openlook or MOTIF

AfterCONFIG.SYS functions are implemented the system
executes the commands found in the AUTOEXEC.BAT
file. This file contains DOS commands such as:
path=c:\; ... c:\xact;c:\dash-lca; ...
set xact=c:\xact
set grmode=ega

The first line shows the portion of the path established by
the XACT and DASH-LCA installation procedures. These
are the default directories created and used in the Xilinx
installation procedures.

DECstatlon Requirements
DECstation 3100 Series
• Worksystem V2.2
• 60 Mbytes allocated for Xilinx designs
• 16 Mbytes of RAM
• . Color Monitor
• X-Windows
• DEC Windows or MOTIF

See the Xilinx installation instructions and PC manuals for
additional information.

WORKSTATION REQUIREMENTS
The workstation system requirements needed to run
Xilinx software are:
Apollo Requirements
DN4000 or 400 Series
• Apollo Operating System SR10.3
• Mentor Graphics Version 7.0
• 60 Mbytes allocated for Xilinx deSigns
• 16 Mbyes of RAM
• Color Monitor
• X-Apollo Display Manager or MOTIF

II

5-41

I:XILINX
The Programmable Gate Array Company

5-42

SECTION 6
Applications

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Applications

Introduction ......................................................................................... 6-1
Estimating Size and Performance ....................................................... 6-3
Designing with the XC3000 Family ..................................................... 6-7
Designing with the XC2000 Family ..................................................... 6-8
Additional Electrical Parameters ......................................................... 6-9
LCA Performance ................................................................................ 6-11
Delay Tracking .................................................................................... 6-14
Start-up and Reset .............................................................................. 6-15
Metastable Recovery .......................................................................... 6-16
Battery Backup for Logic Cell Arrays .................................................. 6-18
Compact Multiplexer and Barrel Shifter .............................................. 6-19
Majority Logic, Parity ........................................................................... 6-20
Multiple Address Decoding ................................................................. 6-21
Binary Adders, Subtractors and Accumulators ................................... 6-22
Adders and Comparators .................................................................... 6-23
Conditional Sum Adder ....................................................................... 6-26
Building Latches Out of Logic ............................................................. 6-27
Synchronous Counters, Fast and Compact ........................................ 6-28
30 MHz Binary Counter Uses Less than One CLB per Bit .................. 6-29
Up/Down Counter Uses One CLB per Bit ........................................... 6-30
Loadable Up/Down Counter Uses One CLB per Bit ........................... 6-31
30 MHz Counter with Synchronous Reset/Preset ............................... 6-32
Fast Bidirectional Counters for Robotics ............................................. 6-33
40 MHz Presettable Counter ............................................................... 6-34
Asynchronous Preset in XC3000 CLBs .............................................. 6-36
Frequency/Phase Comparator for Phase-Locked-Loops .................... 6-37
Gigahertz Presettable Counter ............................................................ 6-38
83 MHz Presettable Counter or Programmable Delay ........................ 6-40
Serial Pattern Detectors ...................................................................... 6-41
Serial Code Conversion Binary to BCD .............................................. 6-42
Serial Code Conversion BCD to Binary .............................................. 6-43
Corner Bender or 8-Bit Format Converter ........................................... 6-44
100 MHz Frequency Counter .............................................................. 6-45
Megabit FIFO in Two Chips ................................................................ 6-46
State Machines ................................................................................... 6-48
Complex State Machine in One LCA .................................................. 6-49
PS/2 Micro Channel Interface ............................................................. 6-50
DRAM Controller with Error Correction and Detection ........................ 6-52
1962

Applications

Gate Arrays offer maximum flexibility and a high level of
integration, but burden the user with high risk, high cost,
and a long delay fromfinished design to wo rking prototype.
Generating test vectors and worrying about testability is
another price the gate array user has to pay.

INTRODUCTION
The following pages show examples of systems and subsystems solutions using Xilinx Field Programmable Gate
Arrays. Some of these designs have been implemented,
a few are in production, but most are conceptual designs.
These are intended to demonstrate the device
capabilities, to highlight special advantage, to emphasize
the best design methods, and in general to stimulate the
designer's imagination.

Field Programmable Gate Arrays offer a very large
number of flip-flops (128 in the CLBs and another 128 in
the lOBs of the XC3020, a total of 928 in the XC3090).
Unlike the situation with gate arrays, these LCA flip-flops
cannot, or need not be, traded off against logic.
Combinatorial logic coexists with the flip-flops in the form
of function generators. The function generators are
surprisingly versatile pieces 01 logic, unlimited in their
flexibility, limited only by their fan-in of four or five signals.

A Logic Cell Array (LCA) can implement virtually any digital
design. Xilinx offers a software package that covers the
gamut from schematic capture through logic optimization
to automatic place and route and to the generation of a
programming bit stream. The designer can use these tools
and achieve a working LCA design while paying very little
attention to the architectural details of the Logic Cell Array.

When the logic has five inputs or less and is interspersed
with flip-flops driven by a common clock, the LCA devices
are extremely efficient. Certain high fan-in functions like
ALUs tend to be less efficient, and bus-oriented deSigns
must be routed carefully to utilize the long lines of the
3-state drivers of the XC3000-series.

Such an approach, however, will not always achieve the
highest possible performance and the lowest possible
cost. For specific, well-structured deSigns it may pay to
work out a good match with the LCA architecture. This
chapter gives several examples of such solutions. The
XC2000 and XC3000 families of LCA devices have
inherent features different from those of LSTTL MSI
circuits, or PAL devices, or conventional gate arrays.
These four technologies all have different structures,
which lead to different strengths and weaknesses when
they are being used to implement any specific type of logic.

Fortunately, the user normally has some freedom in
structuring the system design. Whenever possible, this
freedom should be used to improve either the performance
or the efficiency of the implementation.
GENERAL TOPICS
Most designers want to estimate density and performance
before they begin an LCA deSign, and some want to know
the definition of equivalent gates. While the data sheets
provide worst-case guaranteed parameters, many
designers need additional information about input and
output characteristics, power consumption, crystal
oscillator design, and the exact interpretation or certain ac
parameters. CLB flip-flops show excellent recovery from
metastable problems, an important concern with
asynchronous interfaces.

TTL-MSI was originally defined to fit into a 16-pin package
and to provide maximum flexibility, so that each standard
part could be used in a myriad of applications. Some
functions are therefore overdesigned (counters and shift
registers have parallel inputs and outputs, when few
applications need both) and some are crippled by the 16pin limitation (notably the up-down counters).
PAL devices suffer from the rigidity of the AND-OR
architecture and from the fixed assignment of flip-flops to
output pins. While the number of inputs is generous, ideal
forwide decoding, the limited number 01 product terms that
can be ORed together makes many designs inefficient
and slow. The number of flip-flops available in PALs is
very limited.

6-1

II

Applications
COMBINATORIAL FUNCTIONS

Using the fast flip-flops and distributed logic in the LCA to
their best advantages, a synchronous presettable counter
of arbitrary length has been demonstrated to run at
40 MHz. This is much faster than any available popular
microprocessor peripheral counter/timer.

The 5-input function generator of the XC3000 family CLBs
offers unlimited flexibility to implement anyone of the more
than 4 billion (232 ) possible functions of up to five variables
in one CLB, all with the same combinatorial delay. The
4-input function generator in the XC2000 family can
implement anyone of the 64K (2 16) possible functions of
four variables. The logic designer should take advantage
of this flexibility while avoiding the possible speed penalty
imposed by the limitation to only five or four inputs. This
may lead to logic partitioning that is different from
traditional design or from MSI or PAL implementation.

State-machine design is another example in which the
creative use of CLB resources can result in a straightforward and easily understood solution.
As explained in the beginning of this chapter, the CLB flipflops are "metastable-resistant;" they resolve metastable
situations typically within a few nanoseconds. Designers
are nevertheless encouraged to avoid asynchronous
designs whenever possible. The combination of very fast
CLB flip-flops with relatively slow and layout-dependent
interconnects can lead to internal decoding spikes and
glitches that cannot be observed with an oscilloscope.
However, they can play havoc with internal asynchronous
logic. The high-speed, low-skew global clock lines and the
individual Clock Enable inputs on each CLB favorsynchronous design approaches that are inherently safer and
more predictable.

Majority logic is just one example in which the CLB excels:
A 5-input majorijy function would use 29 gates when
implemented with 2-input NANOs and inverters, but it fits
into the combinatorial portion of one XC3000-series CLB.
Address decoding is the classical strength of PAL devices.
It is done efficiently in LCA devices if the complete function
includes the combination of several addresses or groups
of addresses.
ALUs consume many LCA-device resources, but adders
or subtractors can be implemented quite efficiently, even
using carry-look-ahead for functions that exceed a width
of eight bits.

SYSTEM DESCRIPTIONS
LCA devices are universal programming building blocks
that are used in a wide variety of systems. An 8-digit
frequency counter implemented in a XC2064 is a simple
illustration. A PS/2 Micro Channel Controller and a DRAM
Controller/Error Corrector demonstrate the versatility of
the LCA in speed-critical applications. Some of the designs are available, as indicated, from Xilinx and may be
obtained by calling the applications hot line.

SEQUENTIAL FUNCTIONS
LCA devices offer an abundance of flip-flops, from 119 in
the XC2064 to 928 in the XC3090. Each CLB flip-flop
(64 in the XC2064, 128 in the XC3020, 640 in the XC3090)
has a "free" combinatorial function generator available as
its input. This simplifies the design of shift registers
and counters.

The purpose of this applications chapter is not to provide
cookbook solutions, but rather to stimulate the imagination, convey ideas and demonstrate that LCA devices offer
a better solution for a large variety of digital designs.

The "Corner Bender" serial-parallel or parallel-serial
converter design, is a two-dimensional shift register array
that fits very efficiently into an XC2064 or half of an
XC3020, wijh 100% utilization of the CLB flip-flops.

6-2

Estimating Size and
Performance
BY DAVE LAUTZENHEISER

INTRODUCTION

If the desired LCA device has enough I/O pins, the next
step is to count the required storage elements. Table 1
shows both logic-block storage elements and 1I0-block
storage elements. Logic-block storage elements should
be considered first, since they are the most flexible. If the
required numberof storage elements is less than the
number of logic storage elements, the desired functions
can probably be performed in the chosen LCA device.

Fileld Programmable Gate Arrays are available in a range
of densities and speed grades. Before committing resources to design implementation, the user should make
an estimate to determine which FPGA best fits the specific
application. Size and performance estimates cannot be
expected to provide exact details, but they provide useful
guidelines for device selection and cost estimates. A
complete design is always the final test for both density
and performance.

In some cases, the I/O-block storage elements can also be
usedto meet storage-element requirements. In particular,
if the number of additional storage elements required
beyond the available logic storage elements is less than
the number of unused I/O pins, then the desired functions
may still fit into the chosen device.

Design-fit estimates can be done in two steps. The first is
a quick I/O and storage element count, with no regard for
performance. The second step counts logic blocks based
on details of the intended circuit, and includes gross
performance estimates, still without regard for routing
delays. Performance estimates should always be
considered "best-case," recognizing that actual system
performance can only be verified on a completed design.

The following two examples illustrate the Step One quick
estimation procedure:

Example 1. An 8·bit microprocessor peripheral.
Function

STEP 1: I/O and Storage Element Fit

Maximum
I/O

Device
XC2064
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090

58
74
64
80
96
120
144

58
100
128
200
288
448
640

58
100
128
160
192
240
288

5
16
4

TOTAL

33

Even the smallest Logic Cell Array, the XC2064, passes
the 110 test. It has 58 user I/O in its 68-pin PLCC package.
Function

I/O
Block
Storage

a

a-bit data bus
5 bus-control signals
16 bits of output
4 bits of output control
2 internal control registers
Interrupt control logic

A quick initial estimate of how a system fits a specific LCA
device can be made by counting the required input and
output pins and internal storage elements. Table 1 lists the
Xilinx XC2000- and XC3000-series Logic Cell Array
devices and their respective I/O and storage element
counts. To estimate a fit, first count the required inputs and
outputs and compare the total with the I/O pin count of the
desired device. If the desired functions require more I/O
than listed for a device, the designer must either select a
larger device or package, or reduce the I/O requirements.

Logic
Block
Storage

I/O requirements

Storage Elements

Control registers (assume 8 bits)
Buffered input shift register
Miscellaneous control logic

16
16
10

TOTAL

42

All of the storage elements can be put into logic storage in
the XC2064. The XC2064 should fit this application,
provided the desired performance can be achieved.

Table 1. 1/0 and Storage Element Summary

6-3

II

Estimating Size and Performance

Example 2. A memory controller for a 32·blt high
performance processor.

32-bit processor data bus
32-bit processor memory bus
32-bit memory bus
32-bit control register
32-bit DMA control
Address multiplexing control
RAS/CAS/Refresh generation
Memory error check and correct
Processor and memory timing

32
32
16 (muxed)

10

With two storage elements per logic block, the XC3042
can provide up to 288 storage elements. Based on this
estimate, the desired functions should fit into the device.
Some caution is indicated for two reasons. First, the I/O
count is very near the limit olthe device. This could cause
some routing congestion in the I/O area, making a higher
pin-count device a better choice. Second, high
performance requires making the best use of device
features. The 32-bit bus may impose critical performance
requirements. Only the XC3064 and XC3090 permit a
32-bit internal bus, based on the number of available Long
Lines. Choosing the XC3064 could address the I/O
requirements as well as the performance needs.

TOTAL

93

STEP 2: Logic Block Requirements

Function

110 Requirements

3

After establishing design fit by counting I/O and storage
elements, it may be necessary to make a more detailed
analysis of the blocks required. The macro-library
summary table in the Development System section of this
data book may be used to determine specifiC CLB counts
for each function to be implemented.

Based onthis I/O count, the XC3042 with 96 pins would be
marginal. An XC3064 with up to 120 I/O pins may be
required.
Function

Storage Elements

32-bit DMA (two 32-bit Counters)
Refresh generation (minimum)
32-bit control reg ister
32-bit processor memory address
Error check and correct
Miscellaneous control
TOTAL

64

The macro list shows the various gates and functions
available with each design library. Each entry in the list
includes the required number of logic blocks to implement
that function. The differences between XC2000 and
XC3000 family block counts are noted. To develop a rough
block count, the designer simply tabulates all of the blocks
required by each of the functional elements in the design.
Figure 1 shows a portion of a schematic and the block
count from the macro list.

10
32
32
44
20

202

CONTROL
REGISTER

REGISTER

SHIFT
REGISTER
OUT

SHIFT
REGISTER
IN

REGISTER
WITH 3-STATE
OUTPUTS

SERIAL DATA

I/O
CPU

AO

A1
READiWRITE

DECODER

CONTROL REGISTER
DECODER
REGISTER
SHIFT REGISTER OUT
SHIFT REGISTER IN
REGISTER IN 3-STATE
TOTAL

RD4
HX138
RD8
RS8PR
RS8
HX374

2CLBs
SCLBs
4CLBs
4CLBs
4CLBs
4CLBs
23 CLBs

Figure 1. Portion of Schematic with Block Count

6-4

113301A

E:XIUNX
In many schematics there are collections of random gates
that need to be considered, along with the higher level
functions such as counters, decoders and multiplexers.
The following technique can be used to estimate the logic
blocks required for random logic. Begin at an output point
and move back along the path collecting gates until the
number of inputs is four for XC2000-family devices, or five
for XC3000-family devices. These gates can be marked in
some way to show that they occupy a single logic block.
Blocks identified by this method are added to the block
count from the macro list analysis. Figure 2 shows an
example of this gate-collecting technique.

Estimating the block count for integrating PLD devices is
more difficult. Each PLD output should be counted as at
least one block. PLD devices using five or fewer of the
inputs, will require only one block per output for the
XC3000 family (four inputs for the XC2000 family). For
complex equations using more than five (or four) inputs, a
conservative estimate is to use three blocks per output pin.
Decisions about the appropriate device can be reviewed
as more information is collected. Block count estimates
which are near the limit of a device, either in block count or
in I/O and storage element count, may suggest use of the
next higher density device.

Q3
Q2
Q1
Qo

CET

TC

CEP

a"

0

Q

o

Q

o

Q

Q3

II
Q

o

1133020

CP

Figure 2. Five CLBs Are Required to Implement a 74161 Binary Counter

6-5

Estimating Size and Performance

ESTIMATING PERFORMANCE

for routing (10 ns) and 8 ns for setup gives a total delay of
48 ns. This should permit operation at a system clock rate
of up to 20 MHz.

After selecting the right LCA device based on logic
resources, an estimation of performance is often the next
step. If the system clock rate is less than 20% of the flipflop toggle rate of the selected device, then the
performance goals can usually be met easily. In cases of
higher system clock rates or very complex functions, a
more detailed analysis may be required.

SUMMARY
The final determination whether a logic device meets the
goals for integration and performance can come only after
the design has been completed. For Field Programmable
Gate Arrays, estimating logic capacity and performance
should precede device selection. If the design fits,
the XACT development system and the simplicity of insystem design verification assures cost-effective and
rapid design implementation.

The macro library for each device family includes the
number of logic-block levels used for each listed function;
the LCA data sheet specifies the block delay for each level.
Some routing delay, which can add 25 - 50%, must be
added to the block delay.

Of course, specifications sometimes change during
execution of a design. Logic changes may result
in different requirements for 1/0 and logic blocks. In
such cases, the Xilinx product line simplifies the migration
to a compatible array that meets the new requirements.

As an example, a circuit might have three levels of blocks
in the path from one clock edge to another. For a device
with 10 ns block delays, this gives 30 nsdelay from the first
clock to the setup required forthe next clock. Allowing 30%

6-6

Designing with the
XC3000 Family
Application Brief BY THOMAS WAUGH
CLOCKING

3-STATE BUFFERS

Global and Alternate Clocks Buffers

Active High 3-state is the same as active Low enable.

There are two high-fan-out, low-skew clock resources.
The global clock originates from the GCLK buffer in the
upper left corner of the chip and the alternate clock
originates from the ACLK buffer in the lower right corner of
the chip.

In other words: A one on the T pin of a TBUF or an OBUFZ
3-states the output, and a zero enables it.
Input/Output Blocks (lOBs)
Unused lOBs should be left unconfigured. They default to
inputs pulled High with an internal resistor.

These resources drive nothing but the K pins (clock pins)
of every register in the device. They cannot drive logic
inputs. In the rare case where this connection is required,
tap a signal off the input to the clock buffer and route it to
the logic inputs.

lOB pull-up resistors cannot be used with lOB outputs,
only on pins that are inputs exclusively.
Configurable Logic Blocks (CLBs)

The global and alternate clocks each have fast CMOS
inputs, called TCLKIN and BCLKIN respectively. Using
these inputs provides the fastest path from the PC board
to internal flip-flops and latches because the signal bypasses the input buffer. CMOS levels on the input clock
signal must be guaranteed.

ClBs have two flip-flops (not latches). They share a
common clock, a common reset, and a common clock~
enable signal.
Asynchronous preset can be achieved by the asynchronous reset, by just inverting D and Q of the flip-flops.

To specify the use of TCLKIN or BCLKIN in a schematic,
connect an IPAD symbol directly to a GCLK or ACL~
symbol. Placing an IBUF between the IPAD and
GClK or AClK will prevent the TClKIN and BClKIN from
being used.

ROUTING RESOURCES
Horizontal Long Lines
The number of Horizontal Long Lines (Hll) per device is
double the number of rows of CLBs.

A/ways use GCLK and ACLK for the highest fan-out
clocks.

The number of TBUFs that drive each Horizontal Long
Line is ohe higher than the number of columns on the
device.

I/O Clocks
There are a total of eight different I/O clocks, two per edge
on each of the four edges.
I/O storage elements can be configured to be latches or
flip-flops. Clocking polarity is programmable per clock line,
not per lOB. A clock line that triggers a flip-flop onthe rising
edge can be an active Low latch Enable (latch transparent) and vice versa.

Part
Name

Rows x
Columns

CLBs

HLL

TBUFs
per HLL

3020
3030
3042
3064
3090

8x8
10 x 10
12 x 12
16 x 14
20 x 16

64
100
144
224
320

16
20
24
32
40

9
11
13
15
17

Crystal Oscillator
Connects to alternate clock buffer, AClK, not to GCLK.

Continued at the bottom 01 next page

6-7

II

Designing with the
XC2000 Fam ily
Application Brief BY THOMAS WAUGH
CLOCKING

CONFIGURABlE lOGIC BLOCKS (ClBS)

Global and Alternate Clocks Buffers

ClBs have one storage element that can be configured as
a flip-flop or a latch.

There are two high-fan-out, low-skew clock resources.
The global clock originates from the GClK buffer in the
upper left corner of the chip and the alternate clock
originates from the AClK buffer in the lower right corner of
the chip.

ClB storage elements have both an asynchronous set and
an asynchronous reset.
ROUTING RESOURCES

The global clock buffer, GClK, drives the Band K pins of
the Configurable logic Block (ClB).

Horizontal long Lines
There is one Horizontal long Line per routing channel.

The alternate clock buffer, AClK, drives the B, C, and K
pins of the Configurable logic Block (ClB). The crystal
oscillator drives the AClK.

There are no internal 3-state buffers on the Chip.
Vertical long Lines

Always use GCLK and ACLK for the highest fan-put
clocks.
I/O Clocks

There are three Vertical long Lines per routing channel,
one general purpose, one for the global clock net and one
for the alternate clock net.

There are four different 1/0 clocks, one per edge.

ClB pins with Direct Access to long Lines
A- Horizontal long Line above the ClB.
B- Global clock buffer, Middle and left Vertical long
Line.
C- Middle and left Vertical long Line.
D- Horizontal long Line below the ClB.
To left Vertical long Line.
y- To Middle Vertical long Line.

I/O flip-flops are positive-edged triggered.

INPUT/OUTPUT BLOCKS (lOBS)

x-

Unconfigured lOB outputs must not be left floating. Configure them as outputs and drive them from internal logic
or leave them unconfigured and pull them up with an
external resistor.

Designing with the XC3000 Family (Continued)
T and I pins ofTBUFs have limited interconnect resources.

ClB Pins with Direct Access to long Lines
AECBCK-

lower Horizontal long Line.
left Middle Vertical Long Line.
left Middle Vertical long Line.
Right Middle Vertical long Line
Rightmost and leftmost Vertical long Lines
(AClK and GClK).
E- Right Middle Vertical long Line.
D- Upper Horizontal long Line.
RD- left Middle Vertical and lower Horizontal
long line.

Never use fewer than four TBUFs per Horizontal long
Line. When using TBUFs for multiplexing applications,
using fewer than four wastes resources. Use ClBs for
multiplexing instead.
Vertical long Lines
There are four Vertical long Lines per routing channel, two
general purpose, one for the global clock net and one for
the alternate clock net.

1976

6-8

Additional
Electrical Parameters
Application Brief
OUTPUTS

The LCA data sheets specify worst-case device
parameters, 100% tested in production and guaranteed
over the full range of supply voltage and temperature.
Some users may be interested in additional data that is not
100% tested and, therefore, not guaranteed. Here are
results from recent bench measurements:

All XC2000/3000 LCA outputs are true CMOS with nchannel transistors pulling down, p-channel transistors
pulling up. Unloaded, these outputs pull rail-to-rail.
DC Parameters

PULL-UP RESISTOR VALUES
lOB Pull-ups
DONE Pull-up
Long Line Pull-up (each)

Output Impedance
Sinking, near ground:
Sourcing, near Vcc:

40 to 150 kO
2toBkO
3to 10 kO

Output Short Circuit Current
Sinking current by the LCA
Sourcing current by the LCA

250
500

110 mA
BOmA

INPUTS
Output short circuit current values are given only to indicated the capability to charge and discharge capacitive
loads. In accordance with industry common recommendations for other logic devices, only one output at a time
may be short circuited, and the duration of this short circuit
to Vcc or ground may not exceed one second. Xilinx does
not recommend a continuous output or clamp current in
excess of 20 mA on anyone output pin. The data sheets
guarantee the outputs only for 4 mA at 320 mV in order to
avoid problems when many outputs are sinking current
simultaneously.

Hysteresis
All inputs, except PWRDN, and XTL2 when configured as
the crystal oscillator input, have limited hysteresis,
typically in excess of 200 mV for TTL input thresholds, in
excess of 100 mV for CMOS thresholds.
Required Input Rise and Fall Times
For unambiguous operation, the input rise time should not
exceed 200 ns; the inputfall time should not exceed 80 ns.
These values were established through a worst-case test
with internal ring oscillators driving all I/O pins except two,
thus generating a maximum of on-Chip noise. One of the
remaining I/O pins was then tested as an input for singleedge response, the other one was the output monitoring
the response. This specification may, therefore, be overly
pessimistic, but, on the other hand, it assumes negligible
PC board ground noise and good Vcc decoupling.

AC Parameters

Fast'

Slow'

Unloaded Output Slew Rate
Unloaded Transition Time
Additional rise time for 812 pF
normalized
Additional fall time for 812 pF
normalized

2.B V/ns
1.45 ns
100 ns
0.12 ns/pF
50 ns
0.06 ns/pF

0.5 V/ns
7.9 ns
100 ns
0.12 ns/pF
64ns
0.08 ns/pF

, "Fast" and "Slow" refer to the output programming option.

There is good agreement between output impedance and
loaded output rise and fall time, since the rise and fall time
is slightly longer than two time constants.

6-9

II

Additional Electrical Parameters

POWER DISSIPATION

T

Vcc
4.5
5.0
5.5
4.5
4.5

LCA power dissipation is largely dynamic, due to the
charging and discharging of internal capacitances. The
dynamic power, expressed in mW per MHz of actual node
or line activity is given below.

V
V
V
V
V

Freq
687 kHz
691 kHz
695 kHz
966 kHz
457 kHz

25°C
25°C
25°C
-30°C
+130°C

Clock line frequency is easy to specify, butthe designerwill
usually have great difficulty estimating the average frequency on other nodes.

CRYSTAL OSCILLATOR

Two extreme cases are:

The on-chip oscillator circuit consists of a high-speed, high
gain inverting amplifier between two device pins, requiring
an external biasing resistor R1 of 0.5 to 1 MQ.

1. Binary counter, where halfthe total power is dissipated
in the first flip-flop.

A series-resonant crystal Y1 and additional phase-shifting components R2, C1, C2 complete the circuit.

2. A shift register with alternating zeros and ones, where
the whole circuit is excercised at the clocking speed.

Fundamental Frequency Operation up to 24 MHz:

Dynamic Power
(mW/MHz)
Output with 50 pF load'
Global Clock (XC3020)
Global Clock (XC3090)
CLB with Local Interconnect
Horizontal Long Line (XC3020)
Horizontal Long Line (XC3090)
Vertical Long Line (XC3020)
Vertical Long Line (XC3090)
Input without Pull-up

C1 = C2 = 34 pF
R2 = 1 kO up to 12 MHz, 8000 to 520 0 for 15 to 24 MHz

Third Overtone Operation from 20 MHz to 72 MHz:

1.9
1.7
3.6
0.36
0.09
0.15
0.08
0.19
0.075

Replace C2 with a parallel resonant LC tank circuit tuned
to = 2/3 of the desired frequency, I.e., twice the crystal
fundamental frequency.
Frequency
(MHz)
L (IlH)
32
35
49
72

• Add 2.5 mW/MHz for every 100 pF of additional load

Example:
XC3020 with

3 outputs at 5 MHz
20 outputs at 0.1 MHz
Global Clock at 20 MHz
10 CLBs at 5 MHz
40 CLBs at 0.2 MHz
16 Vertical Long Lines at 1 MHz
20 Inputs at 4 MHz
Total

C (pF)

LC Tank
Freq (MHz)

60
44
31
18

20.6
24.0
28.6
37.5

R2 (0) C1 (pF)

430
310
190
150

23
23
23
12

Dynamic Power
(mW)
28

4
34
18

3
1
6

Al

94mW

A2

CCLK FREQUENCY VARIATION
C2

Configuration Clock (CCLK) is the internally generated
free-running clock that is responsible for shifting configuration data into and out of the device.

I

--~
-.J

_

L
3AD
OVERTONE
ONLY
115802B

CCLK frequency is fairly stable over Vcc' varying only
0.6% for a 10% change in Vcc' but is very temperature
dependent, increasing 40% when the temperature drops
from 25°C to -30°C.

Crystal Oscillator

6-10

LeA Performance
Application Brief

clock-to-output
routing
logic set-up

·50
12 ns
12 ns
12 ns

clock period
clock frequency

20 ns
17 ns
15.5ns
36 ns
28 MHz 50 MHz 59 MHz 65 MHz

ESTIMATING CLB PERFORMANCE

Since the delays in LCA-based designs are lay-out dependent, the data sheet cannot give all the answers needed to
predict the worst-case guaranteed performance.
The timing calculator in XACT is a better tool, and a
simulation using SILOS, after the design has been routed,
will be the final arbiter for worst-case performance.

3.

Still, most designer want to evaluate the possible performance, well before they have finished the design.
Here are some guidelines for XC3000 family devices:
1. A simple synchronous design-like a shift register,
where a flip-flop feeds a flip-flop in the next vertical or
horizontal CLB through the one level of combinatorial
logic in front of the target flip-flop:
·70
6 ns
1 ns
8 ns

clock-to-output
routing
logic set-up

·50
12 ns
1 ns
12 ns

·100
5 ns
1 ns
7 ns

clock period
clock frequency

25 ns
15 ns
13 ns
11.5 ns
40 MHz 67 MHz 77 MHz 87 MHz

SETUP

CLOCK TO OUTPUT

l-

TCKO

---i

j4--

ClB

clock-to-output
routing
logic delay
routing
logic set-up

·50
12 ns
12 ns
14 ns
1 ns
12 ns

·70
6 ns
6 ns
9 ns
1 ns
8 ns

·100
5 ns
5 ns
7 ns
1 ns
7 ns

clock period
clock frequency

51 ns
30 ns
25 ns
22 ns
20 MHz 33 MHz 40 MHz 45 MHz

·1

lWO·LEVEL

CLOCK TO OUTPUT

--t-

0

INTERCONNECT

____________________

~

~

TeKO

COMBINATORIAL

I-

TILO

~

~

II

SETUP

I--

TICK

--l
CLB

0

____________

·125
4.5 ns
5 ns
5.5 ns
1 ns
6 ns

These numbers assume synchronous clocking from the
global clock lines. Remember, these are all worst-case
numbers, guaranteed over temperature and supply voltage. Nobody should design with typical numbers.

CLB
0

CL~K

TICK

·125
4.5 ns
5 ns
6 ns

An additional level of combinatorial logic plus routing
reduces performance further:

~-

SINGLE LEVEL

·100
5 ns
5 ns
7 ns

Therefore, as a rule of thumb, the system clock rate should
not exceed one third to one half of the specified toggle rate.
Simple designs, like shift registers and simple counters, can
run faster, approximately two thirds of the specified toggle
rate.

·125
4.5 ns
1 ns
6ns

2. A similar design with flip-flops several rows or columns
apart would add routing delay:

I-

·70
6 ns
6 ns
8 ns

0

0

______________________________

0

~

115904

Figure 1. Critical Timing Parameters for Clocked CLB Driving Clocked CLB Directly (Single Level)
and Driving It Through Additional Combinational Logic (Two·Level)

6-11

LCA Performance

16 - 0.7 x 5.7 = 12.0 ns for the 3020-125
17 - 0.7 x 6.0 - 12.8 ns for the 3020-100
20 - 0.7 x 6.5 = 15.4 ns for the 3020-70

DESIGNING FOR HIGHEST DATA TRANSFER RATE
BETWEEN XC3000-FAMILY LCAs

Worst-case analysis of a synchronous data transfer between XC3000-family devices postulates that the sum of
clock-to-output propagation delay of the sending device,
plus the input-to-clock set-up time of the receiving device,
must be less than the clock period.

Under these assumptions, the worst case (shortest) value
for the clock period is:
14.7 + 12.0= 26.7 ns, i.e. max 37.5 MHzforthe302D-125
16.0 + 12.8= 28.8 ns, i.e. max 34.7 MHzforthe302D-100
19.5 + 15.4=34.9 ns, i.e. max 28.6 MHzforthe302D-70

The inherent freedom in clock and signal routing makes it
impossible to give exact values for an unprogrammed lCA
without specifying certain restrictions:

Bypassing the input flip-flop in the lOB and going directly
to the 01 input of the closest ClB is another, non-obvious,
way of improving performance by 8 ns for the 3020-125
device, by 9 ns for the 3020-100 device and by 10 ns for
the 3020-70 device.

On the transmitting lCA, the clock-pin to output-pin propagation delay is minimized if TCLKIN or BClKIN are chosen
as clock inputs. They are CMOS-level only, and offer the
shortest on-chip clock delay.

Ifthis is notlast enough, there are design methods that can
improve the performance. let us assume a -100 device.
The easiest and safest method is to increase the clock
delay on the receiving lCA, thus reducing the apparent
input set-up time. Changing to a direct input (instead of
TClKIN) adds 1.5 ns to the clock delay and subtracts it
from the input set-up time.

The clock-pin to output delay is then
5.7 + 9 = 14.7 ns for the 3020-125
6.0 + 10 = 16 ns for the 3020-100
6.5 + 13 = 19.5 ns for the 3020-70
On the receiving lCA, the input-pin to clock-pin set-uptime
is the specified 1/0 pad input set-up time (parameter TPICK
in the lOB switching characteristic table of the XC3000
family data sheet) minus the actual delay for clock buffering and routing. (See the left column of the following page
for an explanation of the factor 0.7).

More aggressive methods of increasing clock delay inside
or outside the receiving lCA must be used with care, since
they might reduce the "best case" set-up time (fast process, low temperature, high V CC) to a value of less than
zero, i.e., make it a hold time requirement, which, in
conjunction with a best case very fasttransmitting device,
can lead to problems.

Assu ming the same clock buffer choice on the receiver as
on the transmitter, the longest input-pin to clock-pin set-up
time is:

T OKPO ~

o

Q

J4--

lOB

T PICK (SETUP)
TIKPI ";';(H-::::0I.:-::0::")---::::!J',.

lOB
CLOCK

t-- TClKIN -+Figure 2. Critical Timing Parameters for Data Transfer Between LCAs

6-12

115903

T GCLK--t

E:XILINX
INPUT SET-UP TIME ON A XC300D-FAMILY LCA IS
BETTER THAN THE SPECIFICATION.

WHY ARE THERE NO GUARANTEED MIN DELAY
SPECIFICATIONS?

The Xilinx XC3000-Family data sheet specifies a worstcase input set-up time of 17 ns for the -100 speed grade
(parameter #1 on page 2-45), but this is the data input pad
set-up time with respect to the IntemallOB clock, not with
respect to the clock input pad.

IC manufacturers do not usually guarantee minimum
propagation delay values, though some specify a token
min delay of 1 ns. There are compelling reasons:
These shOrt delays are extremely difficult to measure on a
production tester. Even if it were poSSible, the necessary
tester guard-banding might make the result
meaningless.The spread between a conservative worstcase maximum value and a similarly conservative worstcase (best-case?) minimum value would be surprisingly
large. There are five reasons:

Any delay from clock pad to lOB clock must be subtracted
from the specified set-up value in orderto arrive at the true
systems set-up time as seen on the device package pins
(pads) for data and clock. Since the internal clock delay
can be manipulated by the user, Xilinx cannot specify the
systems set-up time.

1.

The shortest possible clock delay from the package pin to
the lOB clock is achieved by selecting the CMOS
compatible clock inputs TCLK or BClK. The guaranteed
max value for their delay is 6 ns (XC3020-100).

Temperature. CMOS propagation delays decrease
approximately 0.3% per degree C.

2. Supply Voltage. CMOS propagation delays are just
about inversely proportional to V00'

Xilinx does not guarantee any shortest values for all these
parameters. An unrealistic worst-worst case analysis
might, therefore, assume two extreme values:

3.

Test Guardband. The max delay test is performed at
a temperature well above TMAX and a supply voltage
well below V00 MIN., The accepted max delay is also
less than the data sheet value. Equally conservative
methods applied at the opposite extremes would give
very short, values. '

4.

Process Variations. lCAs are sorted into a few speed
classes. A part marked -50 might have barely missed
the -70 specification in only Ii few or perhaps only one
parameter. IC manufacturers may sometimes mark
down (call a -70 part a -50 part) in order to adjust
production yield to market demand. This increases the
spread even more.

5.

Process Evolution. As IC technology improves,
smaller geometries reduce not only device size and
cost, but also propagation delay. Tight minimum
specifications wouldbe a hindrance to progress.

17 ns set-up time for a slow data input With an infinitely
fast clock path
6 ns hold time for aninfinitelyfast data input combined
with a slow clock path.
Thatis a meaningless mathematical exercise. In reality, all
these delays track very well over temperature, supply
voltage and processing variations, never deviating more
than 30% from each other's normalized value. When one
parameter is at its absolute max value, any other parameter will be between 70% and 100% of its max value
(see page 6-14). The longest required set-up time forthe
data input with respect to the CMOS compatible clock
input is, therefore, 12,,8 ns (17 ns minus 70% of 6 ns).
What Is the Shortest set-up time, Is there a danger of '
malfunction due toa posltiv,e hold tlm~?
The fastest delay parameter is always longer than 10% of
the specified guaranteed max value for the' fastest
I;lvailable version of this device. The fastest value occurs
at the lowest temperature and highest supply voltage.
The shortest data set-up time with respect to the CMOS
compatible clock input is, therefore, 1.1 ns (10% of 17 ns
minus 6 ns). This is still a positive value, sometimes called
a negative hold time.
There will never be a hold time requirement if the user
selects the CMOS-compatible clock-input option.

6-13

Finally, it can be argued that a proper synchronous design
is insensitive to minimum propagation delay values. When
the,clock skew issmal,I,'( Xilinx clock networks guarantee
extremely small clock skew values, less than 2 ns over a
big chip like the XC3090) the designer can safely ignore
the minimum delay issue. No Xilinx ClB'or lOB input has
a hold time requirement.
In the past, designers have faced far greater uncertainti,es
when they populated PC boards with a variety of SSI, MSI
and PAL devices,each from a different production run,
each with different power dissipation and junction temperature. Such problems do not exist inside the lCA
where delays track, and the temperature is the same for all
elements.

E:XILINX

Delay Tracking
Applications Brief BY PETERALFKE

How much can delays on a chip vary, relative to
each other?

Examples

If I know one delay value exactly, how much
tolerance must I assume for any other delay value
on the same chip?

If one delay is at its maximum value, the other is between
70% and 100% of its maximum value. If one delay is at
50%of its maximum value, the other one can be anywhere
between 71% and 35% of its specified maximum value ..

The figure explains delay tracking, i.e. the correlation
between any two delays, called A and B, onthe same chip.
Delay A is represented on the horizontal axis, delay B on
the vertical axis. 100% represents the guaranteed worstcase maximum value for either of the two delays.

100%

No delay can ever be shorter than 10% of the specified
max value; the horizontal and vertical strips parallel to
both axes, therefore represent impossible combinations.
If the correlation between delay parameters were perfect,
all possible combinations would be on the diagonal line.
If there were no correlation at all, the whole remaining
square would represent valid combinations. Xilinx
assumes a correlation factor of 70%; all possible
combinations thus fall onto the unshaded part of the
square.

B

0%

A

100%

Warning: "Typicals" Are Hazardous to Your Designs
All Xilinx parameter specHications in this data book, shown on the screen and used in any simulator, are worst-case values,
guaranteed over the full range of operating conditions. Delays in all CMOS devices are inevitably longest at the highest
temperature and the lowest supply voltage, and delays are also affected by variations in the manufacturing process.
For a clear description of these delay variations, see Figure 29 on page 2-26. It shows that the ''typical'' delay, exhibited
by an average device at 25°C and 5.0 V, is slightly more than half the worst case delay for a commercial temperature
range product, and is less than half of the worst case military value.
Designers should regard ''typical'' values as meaningless averages, taken under favorable operating conditions. Nobody
should base a design on ''typical'' values, but some manufacturers still use this misleading way to specify device
performance. It should have died 25 years ago.

6-14

Start-Up and Reset

1:XILINX

Application Brief
INTERNAL LOGIC DURING CONFIGURATION

SYNCHRONOUS RESET AFTER CONFIGURATION

During configuration, all I/O pins not used forconfiguration
are 3-stated and all internal flip-nops and latches are held
reset until the chip goes active, Even multiple LCAs
hooked up in a daisy chain will go active simultaneously as
a result of the same CCLK edge. This is well documented.

After configuration is completed, the LCA becomes active
in response to a rising edge of CCLK. All outputs that go
active will do so simultaneously, but they are obviously not
synchronized to the system clock. Some designs might
require a reset pulse synchronous with the system clock to'
avoid start-up problems due to asynchronous timing between the end of internal reset and the system clock.

Not documented. is how the internal combinatorial logi~
comes alive during configuration: As configuration data is
shifted in and reaches its destination, it activates the logic
and also "looks at" the inputs. Even the crystal.oscillator
starts operating as soon as it sees its configuration data.
Since all flip-flops and latches are being held reset, andall
outputs are being held 3-stated, there is no danger in this
"staged awakening" of the chip. The. user. can take
advantage of this to make sure that the chip comes to life
with the internal output 3-state control signal on the output
driver already active before the end of configuration, so
that there is no chance of any output glitch.

The circuit below generates a short global reset pulse in
response to the first system clock after the end of configuration. It consumes one CLB plus one output pin, and it
also precludes the use ofthe LDC pin as I/O.
During Configuration:
.LDC (Low) holds D High, but a is held Low by intemal
reset.
RESET is pulled High by internal and external resistors.

FAST RECOVERY FROM RESET

End of Configuration before first System Clock:

Recovery .from Reset is not specified in our data sheets
because it is very difficuH to measure iii a production
environment

LDC pin goes active High, Qstays Low, D stays High.
RESET is still pulled High by external resistor.
Result of first System Clock after end of Configuration:

Here are benchmark values:
The CLB can be clocked immediately, Le: wit~in 0.2 ns,
after the end of the internal direct reset (rd).

Q is clocked High, which forceS D Low.
Output driv6r goes active Low and forces RESET Low.
This resets the whole Chip until the Low on a
causes RESET to be pulled High again
The wh()le chip has thus been reset by a. short pulse
instigated by system Clock.
..

The CLB can be cloCked no earlier than (worst case) 25 ns
after the release (rising edge) of the extemally applied
Global Reset (acting Low) signal.

ClB

HIGH

-+-1>---+ LOC
lOB

Figure 1. Synchronous Reliet

6-15

1971 01

•

Metastable Recovery
Applications Brief
CLB FLIP-FLOPS RECOVER SURPRISINGLY FAST
FROM METASTABLE PROBLEMS

BY PETER ALFKE & PERRY WU

When an asynchronous event frequency Of approximately 1 MHz Is being synchronized by a 10 MHz clock,
the CLB flip-flop will suffer an additional delay of

A specter is haunting digital design, the specter of metastability. From a poorly understood phenomenon in the
seventies, it has developed into a scary subject for every
designer of asynchronous interfaces. Now Xilinx offers
data and a demonstration kit to help users analyze and
predict the metastable behavior of LCAs.

4.2 ns statistically once per hour
6.6 ns statistically once per year
8.4 ns statistically once per 1000 years
The frequency of occurrence of these metastable delays is
proportional to the product of the asynchronous event
frequency and the clock frequency.

Whenever a clocked flip-flop synchronizes a truly asynchronous input, there is a small but finite probability that
the flip-flop output will exhibit an unpredictable delay. This
happens when the input transition not only violates the
setup and hold-time specification, but actually occurs
within the tiny timing window where the flip-flop "decides"
to accept the new input. Under these circumstances the
flip-flop enters a symmetrically balanced state, called
metastable, (meta = between) that is only conditionally
stable. The slightest deviation from perfect balance will
eventually cause the outputs to revert to one of the two
stable states, butt he delay in doing so depends not only on
the gain bandwidth product of the circuit, but also on the
original balance and the noise level of the circuit; it can,
therefore, only be described in statistical terms.

If, for example, a 100 kHz event is synchronized by a 2
MHz clock, the above mentioned delays (besides being far
more tolerable) will occur 50 times less often.
The mean time between metastable events lasting longer
than a specified duration is an exponential function of that
duration. Two points measured on that line, allow extrapolation to any desired MTBF (mean time between failure).
MTBF
SEC

10 11

The problem forthe system designer is notthe illegal logic
level in the balanced state (it's easy enough to translate
that to either a 0 or a 1), but the unpredictable timing of the
final change to a valid logic state.

10'
10'

1 YEAR

The basic phenomenon is as unavoidable as death and
taxes, but the probability of erroneous operation can be
determined, and the impact of various countermeasures
can be evaluated quantitatively, if two fundamental flipflop parameters are known, i.e., the metastability capture
window, and the metastability recovery rate.

10'

1 MONTH
10'
10'

1 DAY

10·
1 HOUR
10 3

Xilinx has evaluated the XC3020 CLB flip-flop with the help
of a mostly self-contained circuit on the Demonstration
Board that is available to any Xilinx customer.

fDATA = 1 MHz
10'

fCLOCK =10 MHz

10'

The result of this experimental evaluation shows the Xilinx
CLB flip-flop superior in metastable performance to many
popular MSI or PLD devices.

NS
116001A

Metastable MTBF as a Function
of Additional Acceptable Delay

6-16

E:XILINX
MEASURING METASTABLE RECOVERY

Every ns in additional acceptable delay reduces the
frequency of metastable events by a factor 40.

The excellent metastable recovery rate of Xilinx LCA flipflops was measured in a working XC3020-70 on the Xilinx
evaluation board. Since metastability can only be
measured as a statistical event, the device was configured
with eight concurrent detectors:

The MTBF curve was then normalized to a reasonable
combination of clock and asynchronous data rates, using
the generally accepted theory that, everything else being
equal, the frequency of metastable events is proportioned
to the product of the two frequencies at the 0 and ClK
inputs of the flip-flop under test.

Eight D flip-flops are clocked from a common high-speed
source. Their 0 inputs are driven from a common, lower
frequency asynchronous signal. Each flip-flop feeds the
inputs of two more flip-flops, one of them clocked on
the opposite clock edge. This cuts the clock rate for
the experiment in half, from 50 MHz to a more manageable
25 MHz. A comparator detects when 01 differs from
0= 00 = 02.

o

Assuming that the metastable window is 0.1 ns wide; and
the clock is 10 MHz, one data change in 1000 will fall into
the metastable window. A 1 MHz data rate gives an MTBF
of 1 ms for an additional delay of zero. Each additional ns
of acceptable delay increases the MTBF by a factor 40,
see diagram on the previol B and A < B. It can operate LSB first or MSB first,

1
1
1

x

x

A bit-serialldentHy comparator detects only whether the
two operands are equal or not, without determining which
one (if any) is larger. The bit stream can come in LSB or
MSB first, the flip-flop gets set for any difference between
A and B, and stays set until the end of the word, then gets
reset before the beginning of the next word. This "differencedetector" can also be implemented as a latch and
folded into the combinatorial logic.

1

1

x

Figure 4. Serial Adder/Subtracter

0
0
0

0

x

1141 04

1
1
1
1

0
0
0

if the logic is adjusted:

LSB·first: Start with both flip-flops reset
if A > B set Ox, reset Oy
if A < B set Oy, reset Ox
MSB first: Start with both flip-flops reset
if A > Band Oy = 0: set Ox
if A < B and Ox = 0: set Oy
Result in both cases:

1
1

ax

Qy

o
o

o

1
1

1
1

A

1
1

B

0

1

1

0

0
0

CII

Lower
CPn

CGn

Higher
CP11+2

x.

x

1

1

1

x
x

x

x
x

0

1

1

1

1

0

1

1

o

A=B
AB

1

Impossible

1

0
1
0
0

0

Inputs

x
x
x

0

CLOCK _ _ _ _ _---l

1
1

0
0

x

1
1

x

Carryn

0
0
0
0
0
0

0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0

1

x

Outputs

1

1

x

0
0

..

1

x

1

1

x

CP,=1

x
x
x
x

x

Inputs
C.
1
0
0
1

CG,=1

B,

x
x
x
x

x
x

1
1

S.=1

A,

0
0
1
1

x

x

S.=1

B.

0
1
0

1
1

1
1

Outputs

A,.

1-.........-10

A
B
AOOISUBTRACT

The 16-bit adder is a natural extension of the S-bit adder.

Ox

Oy

CGn+2
x

Oy

x
1

CLOCK - - - - - - '

x
x

Figure 5. Serial Magnitude Comparator

6-25

114105

Conditional Sum Adder
Adds 16 Bits in 33 ns
Application Brief BY MATI KLEIN. HEWLETI·PACKARD
This circuit is based on a 1960 paper by J. Sklansky (see
page 6-22). With careful placement and routing the total
delay can be kept below 33 ns.

subscripts denote the binary position (weight). and superscripts describe the assumed input condition:
0: carrry into this position is assumed inactive
'0: carry into the position one lower is assumed inactive
1: carrry into this position is assumed inactive
'1: carry into the position one lower is assumed inactive

The block diagram below shows each CLB and its inputs
and outputs.
27 of the CLBs each generate one function of up to five
variables, 14 of the CLBs each generate two functions of
four variables. In accordance with the original paper all

This design is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778.

A12 B,.A,.B 13
A,.B,.A,.B,.

198801

16-811 Conditional Sum Adder

6-26

Building Latches
Out of Logic
Application Brief
Since the XC3000-series, unlike the XC2000-series, cannot configure its CLB flip-flops into latches, there must be
other ways to design latches. Obviously, the I/O block can
be configured with latches on either the input, the output,
or both. Beyond that, every CLB can form a latch.

can also have two D inputs, each with its own Enable; or
we can have two D inputs, a Select input and an Enable
input; orwe can have an Enable and three D inputs defined
in any arbitrary way. Majority gating could be one way: if
none or one is active, reset the latch; if two or three are
active, set the latch. Or, if none is active, reset; ifoneortwo
are active, hold; if three are active; set. Orwe can assign
positive or negative weights to the D inputs;

The 5-input logic structure permits an amazing diversity of
latch designs; here are several ideas:
With F fed back to close the feedback path, there are four
control inputs left.. They might be called Set, Reset, Data
and Enable, defined such that Sand R are independent of
Enable, but D is activated by it. Any of these four inputs
can be defined as active High or active Low. This results
in 16 different latch designs, all with the same basic
characteristics and the same timing.

Since there are 65,536 different functions of lour
variables, there are many different ways to define a
latch, not counting pin rotations and active-HighlactiveLow variations.
All these latches have the same timing characteristics:
propagation delay from input to output = 14/9 ns for the
50/70 MHz part. Set-up time to the end of Enable, or min.

We can also eliminate D and have two Enables, affecting
Sand R (again 16 different flavors) or we use multiple S
and multiple R, either ORed, or ANDed, or XORed. We

D
END

SET
EN SET

SET 1

SET

RESET

RES 1

RESET

EN RES

RES2

D1
END1
D2
EN02

01
02

SET2

II

01
02

SEL

D3

EN

EN
1142 01A

Figure 1. Latched Logic

6-27

Synchronous Counters,
Fast and Compact
Application Brief BY PETERALFKE
FUllY SYNCHRONOUS 4·BIT COUNTER USES
ONLY TWO ClBS TO COUNT ANY CODE

FUllY SYNCHRONOUS 5·BIT COUNTER USES
ONLY THREE ClBS

This 4-bit counter operates synchronously and has a
Count Enable (Clock Enable) input. Count length, count
direction, and even the code sequence can be selected
through configuration. There are 15!, i.e. more than 1012
different possible sequences. All four outputs are available. This counter cannot be preset to an arbitrary value,
but it can be cleared by an asynchronous input.

Three XC3000-series CLBs can implement a modified
shift-register counter with the following features:

~l~ ~:
~l~ ~::

• Fully synchronous operation
• Count Enable Asynchronous clear
• Count-Modulus defined during configuration: 2 ... 32

ANY SEQUENCE:

• Only one meaningful output, 0 s, but with complete
freedom to define its waveform

BINARY
GRAY
BCD

00 through 04 form a linear shift register counter. The 5-

X3

input combinatorial function FO determines the modulus
(there are no illegal or hang-up states). The 5-input
combinatorial function F1 decodes the counter in any
conceivable way, 65 synchronizes and de-glitches F1.

X3-GRAY
BIQUINARY
ETC.

Examples:

114301

Figure 1. Synchronous 4·B" Counter In 2 ClBs

+ 28 counter with output High at times

T2, 3, T10, T22 through T27

The advantage of a Gray code is its glitch-less decoding,
since only one bit changes on any code transition. A Gray
counter can also be read "on-the-fly" without the wellknown problems of reading a binary counter e.g., on its
transition between 7 and 8, where any code might be read.
DecImal

Binary

Gray

X3 BInary

X3 Gray

0
1
2
3
4
5

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

0010
0110
0111
0101
0100
1100
1101
1111
1110
1010

6
7
8
9

10
11
12
13
14
15

+

19 counter with output Low at times
T9, T12, T15, T18.

~n

*~,*:-.~~'V.,«.:v."-:«~ ,««v."'»»"Y:««':':""'''''''''-:«-''''''''"«'''-:-.~'V.''V.-':''o":.:.:..-.:",..,,~*,,,,,,,*~,,«<.,%%"«<,,.~
...

.....

~

~ Q4~

i

I
~

I

O.
O2

~~

F1

.

g .•

Q.

ENCODED OUTPUT

0

(ANY PATTERN)

'Z7

~

,:

:::-.:;:::::::::;,:::;:;:;:;:;::::;:::::;:;::;:;:;:-.:::::::;:::::::;:::;;:::::;:::::::::;:;;:::::::::;:::::;;:::;:;;:::::::;:::-.:::::::;:;:::::::;::.:;:::::::::::;:::::::;X'...::;:;...~;:;:~;:::::::::::;:::;:::;:::;:::::::~-;:::::::;:::;:::::::;:::::::::::::~:
114401

Figure 2. Synchronous 5·B" Counter In 3 CLBs

6-28

30 MHz Binary Counter Uses
Less Than One CLB per Bit
Application Brief BY PETERALFKE
The least-significant tri-bit thus stops the remaining
counterchainforseven out of eight incoming clock pulses,
allowing ample time forthe CEO-CET ripple-carry chain to
stabilize. Max clock rate is determined by the first tri-bit's
Clock-to-CEO delay (TCKO + TILQ)' plus the CEP input setup time for all other tri-bits (TICK)' plus the routing delay of
the CEP net. In a -70 device this sum can babelow 32 ns.
The higher tri-bits are not speed critical if they propagate
the CET signal in less than eight clock periods, easily
achievable for counters as long as 20 tri-bits, i.e. 60 bits.

Borrowing the concept of Count-Enable Trickle/CountEnable Parallel that was pioneered in the popular 74160
TIL-MSI counter, a fast non-Ioadable synchronous binary
counter of arbitrary length can be implemented efficiently
in the XC3000 series CLBs. For best partitioning into
CLBs, the counter is segmented into a series of tri-bits.
The least significant, i.e. the fastest changing, tri-bit has a
Count-Enable Output (CEO) that is routed to all the CountEnable-Parallel (CEP) inputs of the whole counter.

The two least-significant tri-bits each have a single CE
input; they fit, therefore, in only two CLBs each. The higher
tri-bits have two Count-Enable inputs (CEP and CET) and
require three CLBs.

Each Count-Enable Output from any othertri-bit drives the
next more significant Count-Enable Trickle (CET) input.
The clock causes any tri-bit to increment if all its CountEnable (CE) inputs are active. CEO is active when all three
bits are set and CET is High. CEP does not affect CEO.

ETC

1980 01A

30-MHz Non-Loadable Binary Counter, Expandable up to 60 Bits

III
¥ cer
~ CEP

~

I

~
~CET

,

0

Os

~ CEP

~

L ' m••mmN.v••mNmm•••.••m.w•••••••wN.wm.'•.w.'.m•.•••••

••wN.vNm.w.w.·.w.·.·"

1980 03A

198002A

All More Significant Tri-Bits Use Three CLBs

First and Second Trl-Blts Use Two CLBs Each

6-29

Up/Down Counter Uses
One CLB per Bit
Application Brief BY PETERALFKE
A fully synchronous resettable but non-Ioadable up/down
counter of arbitrary length can be implemented with only
one XC2000 CLB per bit. This design cascades the toggle
information from the least-significant toward the mostsignificant position. Such an architecture reduces the
maximum clock rate for longer counters, from 30 MHz
for 2 bits, to 10 MHz for 8 bits, down to 5 MHz for 16 bits,
assuming a -70 part. This simple design is, therefore,

UP/DOWN

not suited for high-speed clocking, but it generates
fully synchronous outputs, Le., all flip-flops clock on the
same edge.
The better functionality of the XC3000 CLBs can cut the
cascaded toggle-control delay in half by looking at two
counter bits in parallel. This doubles the max frequency for
a given counter size. A 16-bit counter in a -70 part can
count 10 MHz, guaranteed worst case.

-~t-------------4...

I--_ _ _ _-'x"'-----f,-_ _

COUNT
ENABLE

~~~~~E
OUT

--~"---1>--+----....J

IN

D

Q !--'V.........-f--,

1981 01A

r--------------------+CEO

UP/DOWN

- f - . -.......- 1 '

198102A

6-30

Loadable Up/Down Counter
Uses One CLB per Bit
Application Brief BY PETERALFKE
The 5-input function generator of the XC3000 family CLBs
makes it possible to build expandable fully synchronous
/oadab/e up/down counters of arbitrary length using only
two CLBs per two bits, i.e. one CLB per bit.

two counter bits simultaneously. This cuts the effective
ripple delay in half. A 16-bit counter in a -70 part can count
10 MHz, guaranteed worst case.
The CEP/CET speed enhancement cannot be used on updown counters that might reverse their direction of count in
any position. They can, therefore, not guarantee a defined
number of clock periods for the ripple-carry chain to
stabilize.

The basic concept is similar to the non-Ioadable up/down
counter described on the previous page. The function
generator driving the counter flip-flop has two additional
inputs (Parallel Enable and Data). The cascaded toggle
control circuit is moved to a separate CLB which serves

CEI--~-1-----------------------'

UP/DOWN

---+---%----_-----l
I--f-- CEO

L---------------------------~--------------------------_.QB

II
Q

Q

PE----4---r-----------------------------~
1982 01A

6-31

30 MHz Binary Counter with
Synchronous Reset/Preset
Application Brief BY PETER ALFKE
In many applications, design modularity is more important
than highest clock speed and best space efficiency. A
counter design is described here that uses identical CLB
primitives, one CLB per bit. The Count-Enable Trickle/
Count-Enable Parallel concept, introduced by the 74160
family, is changed here to a i-bit block size. Any block
increments only if both Count Enables are High, but the
outgoing Carry (C OUT) is not a function of CEP. The CEP
input thus prevents erroneous counts while the ripple carry
chain is settling.

A shorter counter (six bits or less) drives the CEP net from
the 0 0 output, achieving a 40-MHz speed. A longer
counter generates a 1-in-4 duty cycle on CEP and runs at
30 MHz up to 12 bits long, or at 25 MHz up to 18 bits long
as shown below. To achieve this performance, CEP and
R must be driven by long lines.
Figure 3 shows a variation of the circuit in Figure 2, where
the synchronous Reset input (R) is changed to a synchronous Preset (P). Any counter chain can use a mixture of
these two circuits to preset the counter to an arbitrary
predetermined value.

ETC T0017

RESET--~------+++-----~~-------H4-------~~-----+~
CLOCK--~------+-~----~-4-------r~------~~-----+~

00
1983 01

Figure 1. Long Counter (up to 18 bits)

CEP

CEP
....;.:-:.:.:.:.:.:.:.;.:-:.:.:.:.:.;.:.:-:-:-:.;.:«.:-:.:.:-:-:.:.:-:-:':-:';';';';':':-:-:';':-:';';';':':;:;

~;.!.:-:-:.;.:-:.;.;.:.:-:-:.:v:-:-:.;.:.:-:.:.;.:.:.:.:.;.;.;.:.:.:->:-;.:-:

!----;;;;-COUT

CIN

p

~

CLOCK ---;j;---------------------I>

«~_"««-w.." ~

;l..* .««,...

:-:~' !-:«-.-.:

.. ...."""...."'''.,,.

1

•

COUT

I
!

CLOCK~*~------------------~

*:

.: : ~: !.~o!-X:" 'V: ,. :v.:.«-: :.-: :v;-: :~:*: :. -: - : .w.:>.:.:.«: -:-:-:-:~«-:, «

..''!':'''':-:-''':-y......,.;*:......:.:-:-...»»:.:.:-:.:-:.;-:.:-:.:-:I

1.::::::::::-:*:..

....

*''«'*". .,,

......,'''"."''".",...

Q

Q
1983 03

1983 02

Figure 2. CLB Primitive with Reset, One per Bit

Figure 3. CLB Primitive with Preset, One per Bit

6-32

Fast Bidirectional Counters
for Robotics
Application Brief
The position of a robotics arm is usually determined by
three shaft encoders consisting of up/down pulse generators and counters. At a maximum speed of 5 meters per
second and a resolution of 1 micron, these counters must
resolve 0.2-115 pulses and should have a capacity of at
least 2 million steps. The counters must have an easy
interface to the microprocessor so that the count value can
be read on-the-fly, without ambiguity.

BY PETERALFKE

Communication between these two parts of the counter is
through a carefully controlled mailbox. Whenever the 4-bit
up/down counter reaches plus or minus 8, it sets a carry or
a borrow flip-flop. The shift register counter accepts these
inputs synchronously, with a max delay of 1 115.
When the microprocessor wants to read the counter, it first
disables the interaction between the two parts of the
counter. Then both parts are transferred into 24 output
registers and the counter interaction is enabled again.
This mechanism insures reliable read-out, even if the
counter is oscillating around certain critical values.

The established microprocessor peripheral counters have
severe limitations. They are too short, lack up/down control or quadrature clock inputs, and cannot be read easily.
Now Xilinx suggests a design that packs three 22-bit
counters into one LCA, the XC3020. Max count rate is
8 MHz, and the count values can easily be read on-the-fly.
The counter architecture is somewhat unconventional.
Each counter consists of two parts:

The problem of a traditional up/down counter is that it can
oscillate between two values where all (or most) counter
bits change at the incoming count rate. This makes a reliable microprocessor interface virtually impossible.
In this deSign, the most significant 20 bits of the counter do
not have this problem, and the least-significant four bits
count in a Grey code, where only one bit changes on any
clock transition. Such counters can safely be re.ad on-thefly. This safe and compact design puts one additional
burden on the microprocessor: The two parts of the
counter must be added in software, since they have independent signs.

1. A conventional up/down 4-bit Grey~code counter with a
capacity from -8 to +7. Thiscounter is asynchronous to
the system clock, affected only by the incoming clocks.
2. A 20-bit up/down counter in the form of a 20-bit recirculating shift register, a serial adder/subtractor, and a
carrylborrow flip-flop, This shift register forms the most
significant part of the counter. Synchronous with the
LCA clock, it is easily synchronized to the microprocessor clock. At a 20-MHz clock rate, it recirculates once
and can be incremented, decremented, and also read
or preset, once per microsecond.

Speed can be increased to 20 MHz by changing the partitioning from 4/20 bits to 8/16 bits. The up/down count control can be implemented in several different ways.

II

DATA
BUS

HANDSHAKE
ADDRESS

-~

_ _ _---l
1984 018

Figure 1. Triple 22-Bit Up/Down Counter with Microprocessor Interface

6-33

40 MHz Presettable Counter
Application Brief
A new counter architecture, described here, is used to
implement a very high speed presettable, up-to-40-bit long
binary counter in an XC3020 LCA devices. The design can
easily be modified to implement two 20-bit counters or the
equivalent BCD counters.

BY PETER ALFKE AND PERRY WU

CARRY PROPAGATION

Since a presettable counter only decodes one state, Te,
the deciSion to toggle any of the more-significant bits can
be delayed and thuspipelined without any problem.
The counter is divided into a number of small sections,
each two bits (a di-bit) long, implemented as a synchronous presettable down-counter, with carry-in (=count enable), parallel enable and two data inputs. Terminal count
(0.0) is decoded with an additional input coming from the
next higher section. The least-significant section decodes
the state priorto TC; its output activates the parallel enable
for all counters. The carry function between sections is
pipelined. The carry flip-flop is set when carry-in is active
and the di-bit is in state 00. The carry flip-flop stays set for
only one clock period; its output drives the carry-in function
of the next higher section. As a result ofthis pipelining, the
counter can be made arbitrarily long without any speed
penalty. Note that each di-bit, except the first, makes its
transition n clock pulses later than required by the binary
code sequence (n is the relative position of the di-bit, n=O
for the input di-bit). This code violation has no impact on
TC decoding. This counter can be four times faster than
presently available standard microprocessor peripherals
like the 8254 and 9513. Typical applications are in
instrumentation and communications, for example, as the
frequency-determining counter in a phase-locked-loop
frequency synthesizer.

Traditional counter designs always represent a compromise between two conflicting goals: highest clock speed!
event resolution on one hand, sophisticated features (like
preset to any arbitrary value, or decode any state) on the
other hand.
Asynchronous ripple counters offer highest speed, but
cannot be decoded in one clock period, thus cannot be
made programmable.
Synchronous counters permit decoding and presetting in
one clock period, but payforthis with complex carry logiC.
Carry propagation is always the limiting factor in the
traditional design of presettable synchronous counters,
since the complete carry chain must reach a steady state
before the next incoming clock edge. Brute force parallel
decoding of all previous states becomes unmanageable
beyond eight stages, but cascaded decoding introduces
additional delays. Either approach reduces the inherent
resolution of the counter.
Decoding Terminal Count (TC) to preset the counter again
poses a similar problem. The deSign described here
separates the two functions of the carry chain as follows:

SUMMARY

• One propagates the carry signal from the less-significant to the more-significant bit positions, andcauses the
appropriate flip-flop to toggle.
• One cascades the decoding of the terminal count of the
whole cOjJnter and generates a Parallel Enable signal

Unlike the speed of conventional synchronous counters,
the speed of this design is independent of its length. All
speed-critical paths are single level; their interconnect
delay can be kept below 9 ns, which means that even a
-70 device can count at a 40-MHz rate (worst case).

CASCADED TC DECODING

Lsa

Msa -

The TC decoder must receive inputs from all counter bits,
but only the LSB timing is critical; the more-significant bits
have been stable for many clock periods. TC can, therefore, be decoded in a slow gating chain that starts at the
most-significant end of the counter.

n=2

n=l

n=O
1

1

g
g

.g ~

~

.• .~• • ~

~

o

'Jk 1

0

lHHc. . .

114501

6-34

1145 02

l:XlUNX

o,Hi-+--g

a

CO

CARRY

D,-----;_/

TI

TO
a

CI-CARRY IN
CO _ CARRY OUT
PARALLEL ENABLE (ACTIVE LOW)
TI _ TERMINAL COUNT IN
TO _ TERMINAL COUNT OUT

TERM.
COUNT

PE -

1145048

Any Oi-bit Except the Least Significant

o

PE----~.J

CARRY

DO--'----~-_L.J

PE~T~O~A~U~D~I-Nm~---------------~--------~----r-r-----~-------,

o

CE - CLOCK ENABLE

TERM.
COUNT

RD

PRffi~---------------------------------~----------~~-~

X1554

least Significant Oi-bit

II

PRESET
START/STOP
HIGH
LEAST SIGNIFICANT Ol-BIT

MOST SIGNIFICANT

oI-BIT
1145 03A

Synchronous PreseUable Counter -

6-35

40 Bits In 60 ClBs

40 MHz PreseHable Counter

Since this circuit was first published in mid 1988, several
designers have used it to create fast counters.

In the unlikely case where this might cause a problem,
most TC pipeline flip-flops can be eliminated. They were
inserted to simplify modeling and because they are
available for free.

What is the function of the TC pipeline flip·flop,
formerly called Q3?

Why Is the least significant di·bit different?
The unconventional idea behind this counter design is that
Terminal Count decoding can be "rippled" from the MSB to
the LSB, i.e. against the direction of carries. This is
possible because the high order bits reached theirTC long
before the LSB does.

To achieve a 40-MHz clock rate, the PE signal must be
made as fast as possible. It has to come directly from a flipflop output so that the sumof clock-to-output delay, routing
delay, and input set-up time is kept below 25 ns.
The position of the LSB TC pipeline flip-flop is, therefore,
changed, so that it detects the TC-1 state (in a downcounter, that is state 1).

There is, however, a potential problem when the counter
is being preset to a value with a string of LSB zeros. Let's
assume the worst case where the preset value is all zeros
except a single one in the MSB position:

The flip-flop output is made active Low PE so that the
asynchronous clear input can be used to force the counter
into loading.

When this counter reaches the all-zero Terminal Count,
PE is activated and the counter is preset. This action
should obviously de-activate the TC decoding, but in the
given example a simple ripple decoder would have a very
long delay. It might take 400 ns for the MSB =1 condition
to ripple down through a 40-bit decoding chain. Such a
delay would defeat the concept of the counter, reducing its
max clock rate to 2.5 MHz. A better way must be found to
de-activate TC within 25 ns.

For operation below 30 MHz the least significant di-bit can
be like all the other dibits, but PE must be excluded from
the AND gate generating PE, and the user may want to
adjust the polarity of the last TC pipeline flip-flop to
facilitate the preset function mentioned above.
Where should this design be used?

The TC pipeline flip-flop and the inclusion of PE in the AND
gate that detects TC, reliably de-activate TC and thus PE
one clock after they have been activated. This has one
side effect, however: It makes it iIIegallo presetlhe counter
to very small numbers (less than 10 for a 20-bit counter),
since the TC-pipeline takes that many clock pulses to
become active again.

This counter deSign achieves high performance by using
several logic "tricks". It generates incorrect outputs when
undigested carries sit in the carry flip-flops. That makes
this design useless for any parallel application like DMA
counters.
For the intended application, timebase counters or
frequency synthesizers, this design offers the highest
possible count speed.

ASYNCHRONOUS PRESET IN XC3000 CLBS
The XC3000 CLB lacks the asynchronous preset capability available in the XC2000 CLB. Some designers are
looking for this feature. Here are several solutions:
1.

3.

If asynchronous preset is needed, but no asynchronous clear:

The design can usually be transformed into a synchronous solution where all flip-flop changes occur as a result
of the same clock edge.

Turn the flip-flop upside down, i.e. invert the D input
and the Q output and consider the asynchronous clear
a preset. These inversions of D and Q come for free
in a Xilinx LCA. Note that the flip-flop will now come out
of configuration in the apparent preset state.
2.

If the Circuit really needs asynchronous preset and
clear (or asynchronous data transfer) in a flip-flop, the
problem must be solved on a system level.

Truly asynchronous parallel data transfer into several
clocked flip-flops simultaneously is inherently unreliable
and must be avoided. If, however, the transfer pulse is
synchronized with the clock, it should not be too difficult to
change the design to utilize the clock for loading.

If the circuit needs both asynchronous preset and
clear, chances are that the function can be performed
by a latch. The XC3000 CLB can implement complex
latches in its function generators (see page 6-27).

Asynchronous data transfer was popular in early TTL MSI
circuits designed in the late sixties, e.g., the 7494 and
7496. It is time to get away from the limitations of the past.

6-36

Frequency/Phase
Comparator for
Phase-Locked-Loops
Application Brief BY PETERALFKE
A Phase-Locked-Loop (PLL) manipulates a local voltagecontrolled oscillator (VCO) so that it is in phase with a
reference signal. One popular application is a programmable frequency synthesizer for radio communications.
Here a crystal oscillator is divided down to a low reference
frequency of 5 kHz, for example.

not only to pull in a small phase error, but also to correct a
large frequency error. It may not generate false outputs
when the input is at a mUltiple or fraction of the desired
frequency. The well-known circuit shown in Figure 1
performs this function. It generates "pump-up" pulse when
the VCO frequency is too low, "pump-down" when its too
high. The multiple feedback network assures proper
operation even at large frequency errors.

A programmable divider scales the VCO frequency down
to the same reference frequency. The two counter outputs
are compared to generate a signal that, when required,
modifies the VCO frequency up or down until the two
comparator inputs are not only of the same frequency, but
also in phase.

Figure 2 shows this circuit implemented in two CLBs plus
two lOBs, directly driving the integrator (low pass filter)
controlling the VCO. The LCA solution has been
breadboarded at 10 MHz. It achieved a phase error of less
than 2 ns.

This frequency/phase comparator must have a wide
capture range, i.e. it must generate the appropriate output,

FROMVCO
DIVIDED BYN

FROM

DIVI~g-t---t+--...J
BYN

• FROM
REFERENCE
FREQUENCY

II
1965 01A

Figure 1. Digital Frequency/Phase Detector
FROM

REFERENCE
FREOUENCY

+--+t--....

Toveo
+2..5 V

INTEGRATOR
1985 02A

Figure 2. Frequency/Phase Detector Using Four Blocks

6-37

Gigahertz
Presettable Counter
Application Brief BY PETER ALFKE
smart but slow counter (in the LCA) to achieve the performance of a fast and smart, fully presettable counter.

Some frequency synthesizers for communications, e.g.,
cellular telephone networks, require a clock frequency of
hundreds of megahertz, up to a gigahertz. Obviously, the
LCA cannot operate quite that fast, but with the help of a
2-modulus prescaler, the LCA can implement a fully presettable ultra-fast counter, resolving time in increments of
one clock period, as small as 1 ns at 1 GHz.

The prescaler divides by either n or n + 1, depending on
the state of the control input. In other words, it "swallows"
one additional clock pulse iftold so by the control input. By
keeping the control input active forthe appropriate number
of prescaler output periods, the LCA can fine tune the total
divide ratio to any integer number.

Prescaling is the obvious method to adapt a slow device to
a high clock rate. Simple prescaling by a fixed number,
e.g. 8, 16, or 64, however, reduces not only the clock rate,
but also the resolution. If, for example, the GHz clock of a
phase-locked-loop synthesizer is first divided by 64, then
the whole presettable counter is clocked at this lower rate.
For a 25 kHz channel spacing, the PLL must, therefore,
operate at 25 kHz + 64, i.e. less than 400 Hz. This results
in slow response and might produce excessive phase
jitter.

Well, there are some impossible numbers:
When the prescaler divides by either n or n + 1, then the
system cannot divide by certain numbers below n (n-1).
An 8/9 prescaler has blind spots below 56
A 64/65 prescaler has blind spots below 4,032
A 128/129 prescaler has blind spots below 16,256
This limitation is usually of no practical consequence in a
real design.

A "Pulse Swallowing" 2-modulus prescaler, originally described in 1970 by John Nichols of Fairchild Semiconductor Applications, avoids this drawback. Pulse swallowing
combines a fast but dumb counter (the prescaler) with a

The prescaler-LCA combination can divide by any integer
number higher than the values above.

INPUT

OUTPUT
0.280 ~s
0.285 ~s
0.290 ~s

200 MHz
200·MHz Counter
200 MHz clock, 12-bit

20.475
20.480

presettable time base generator
achieves 5 ns output resolution.

INPUT
450 TO
1000 MHz

~s
~s

OUTPUT
TO 25 kHz
PHASE-LOCKEDLOOP

Gigahertz Counter
450 to 1000 MHz clock, 16-bit

presettable counter achieves
25 kHz channel spacing with a
25 kHz phase comparator frequency.

LeA
198803A

6-38

ri---------------------------------- TC - PE

0 3 -+-';--+-<:1-_

g~

00

~~-----------------------,

+---<:1---

HiGH ---"-II+--IL..-/

00

Do-H:-:::-::-c:----L_.1
PE

X1751

3-Bit Presettable Down Counter with
Pipeline Terminal cpunt, Locking Up on TC

9-Bit Presettable Down Counter with
Decoded Terminal Count (TC)

6-39

X1752

83 MHz Presettable Counter
or Programmable Delay
Application Brief BY BERNARD NEW
FEATURES

The +8/9 prescaler described on page 6-38 can also be
implemented inside the LCA device. For a -125 part,
the highest clock frequency achievable is 83 MHz, i.e.,
the output delay can be programmed with a granularity
of 12 ns.

This design demonstrates the high performance possible
with LCA devices when the user is willing to optimize the
system design to fit the available logic. The high clock
resolution of 83 MHz is partly dueto a system ''trick'' (pulseswallowing), partly due to the inherent flexibility and high
speed of the CLB function generators.

The implementation of the +8/9 prescaler comprises a
simple 3-stage binary counter followed by an extra
ENABLE bit. The ENABLE bit halts the 3-bit counter for
one clock period in the all-ones state, if the DIV9 line was
asserted during the preceding state. The prescaler thus
divides by 9 instead of 8. The MSB is stored in inverted
form such that it provides a rising clock edge at the end of
the count sequence.

A conventional 24-bit presettable counter would be limited
to a clock rate of 13 MHz. This pu Ise-swallowing design is
more than six times faster.

The prescaler can be implemented in two CLBs. One CLB
contains QA and 0c ' and the other 0B and the ENABLE
bit. Q A and ENABLE are critical signals.

°A
°B

~1.

+9

u.l.

:8

f

a.

r

QA

_

DIRECT INTERCONNECT

- + ENABLE

<,,~~~'·.w»mm»>,

!

,----------,

i

X119SA

!

s

I

~

~

DIV9

~

~

Il
•

+819
<83 MHz

COUNTER

3-BIT
COUNTER

TC

!
21-BIT
COUNTER

t.~mh~m.~' '~ ~w W.~'."'~Wh.W.'~ "'~' '~A= _.' ~,

TC

elK

.

.•

•.

<83 MHz
CLOCK

X11968

X1194B

24-Blt Frequency Division
with Pulse-Swallowing Prescaler

Divide by 8/9 Pulse-Swallowing Prescaler

6-40

Serial Pattern Detectors
Application Brief
FIXED PATTERN DETECTOR

BY PETER ALFKE

ously shifted-in pattern, using only one XC3000-seriesCLB per pattern bit. The output of the comparators are
ANDedwith 3-state buffers on a long line. The desired pattern is first shifted through the DIN input into the Y -flip-flop,
and then routed to the DIN input of the next CLB.

This circuit compares a serial bit-stream against a predetermined (configured) pattern. Two bits are compared in
each XC3000-series CLB. The outputs of the comparator
are ANDed in with 3-state buffers on a long line.

When the complete pattern has been shifted in, it is transferred with one clock pulse to the X-flip-flops, using the
lower half of the function generator. Data to be detected is
then shifted in through the DIN input into the Y-flip-flop, and
from there tothe DIN input of the next CLB. The upper half
of the function generator compares the content of Ox and
Oy, and indicates a match on the CLB output. For identity
comparison, these outputs are ANDed through 3-state
buffers driving a long line.

Data is shifted through DIN into the Y -flip-flop, then shifted
through the upper half of the combinatorial array into the
X-flip-flop of the same CLB. From there it is routed to the
DIN input of the next CLB.
The lower half of the combinatorial array compares the
content of the two flip-flops against data supplied on the A
and 0 inputs. A match is indicated on the G output and
routed to a 3-state buffer driving a long line.

This circuit can also be used as a correlator, in which case
the outputs must be summed in a Wallace-type adder.

DYNAMIC PATTERN DETECTOR OR COR RELATOR
This circuit compares a serial bit stream against a previ-

LONG
~----r

LINE

LONG
UNE

II

A

D

'--_-'

DIN
DIN
1147 02

114701

Figure 1. Fixed Pattern Detector

Figure 2. Serial Comparator Finds Pattern Match or
Correlates Patterns

6-41

Serial Code Conversion
Binary to BCD
Application Brief BY PETERALFKE

O'--l

03

02

°1

·1

00

IIII

°3

°2

°1

00

II I I

1
Xl5S2

Figure 1. Binary to BCD (MSB First)

The LCA architectu re with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.
A binary-to-BCD converter requires three CLBs for every
four bits of BCD output i.e., for every digit. Binary data is
shifted in serially, most significant bit first. Each shift thus
doubles the content of the register.
To remain a valid BCD number, a 4-bit number of 5 or
greater must not just be shifted, but must be converted into
the proper BCD representation of its doubled value: A one
is shifted into the next higher decade and the 5 is converted
into a 0, a 6 into a 2, a 7 into a 4, an 8 into a 6, a 9 into an
8. When the binary LSB has been shifted in, BCD data is
available in parallel form.

1-----1 D

SHIFT {

MODIFY

{

O_O
1_2
2_4
3_6
4_8
S_O
6_2
7_4
8_6
9_8

Q,I-.......++

MODIFY LOGIC:

00

-0,

°oXNORO,-02
°0·°3-°3
MODIFY
Xl ....

Xl'"

Figure 2. Binary to BCD converter. Three ClBs
per Four Bits (MSB First)

6-42

Serial Code Conversion
BCD to Binary
Application Brief BY PETER ALFKE
CONVERT/SHiF'f

0'

o

1146 04

Figure 1. BCD to Binary (lSB First)

.t

The LCA architecture with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.

r~

A BCD-to-binary converter requires three CLBs per digit.
BCD data is shifted in, least significant bit first. Once the
complete BCD word has been shifted in, the. conversion
process begins, shifting out binary data, LSB first.

'---

,--CONVERT

MODIFY

r--

Each shift divides the content by two. When the LSB of a
BCD digit is a one, shifting it one pOSition down would give
it a weight of 8 in the lower decade instead of the weight of
5 appropriate for a 10 divided by 2. A value of 3 is therefore
subtracted from the content of the decade whenever a one
is being shifted into it.

~

r--

r~
,--0,--.<
°2-1

.-----'

~

,----

Ii;"-=::
°2-'---

MODIFY

-°,

0 . , - 00
O 2 - 0 , - - ' " - 0 , XOR02

r-D

0,-1

This design can be made smaller and faster by starting the
conversion before the most significant BCD digit is being
shifted in. Since thesec6nverters can be laid out with very
short interconnect delays, they can operate at up to 60%
of the specified toggle frequency, i.e. 42 MHz for the -70
parts.

SHIFT

~U

r--

O'r--

'---

~U
'---

~

-

~U

0 3 - 0 2 - 0 3 AND (0, OR0 2 )
0 ' 0 - ° 3 - 0 3 OR(O,' O2 )

'--114602A

X1247

Figure 2. BCD to Binary converter. Three ClBs
per Four Bits (lSB First)

6-43

II

"Corner Bender" or
a-Bit Format Converter
Application Brief BY PETERALFKE
Pulse Code Modulation (PCM) has become the dominating encoding method in digital telephony. Analog signals
are sampled at 8 kHz and represented by their 8-bit digital
equivalent, using a logarithmic encoding scheme, IJ.-Iaw in
the US and Japan, A-Law in the rest of the world using the
cCln standard.

XC2064

OR

8

1/2 XC3020

These eight bits are usually transmitted serially (the T1
standard time-multiplexes 24 channels on a single wire at
1.544 MHz. The cCln standard time-multiplexes 32
channels at 2.048 MHz.
In the central office or PBX, however, the eight bits
representing one particular sample must be routed
together. The telephone system thus uses a large number
of serial-to-parallel and parallel-to-serial converters, all
operating on 8-bit words, all running synchronously. Eight
S-P converters with eight data inputs and eight data
outputs can easily be combined in one package. Eight
serial data streams are shifted in simultaneously. After
eight clock pulses the eight serial words can be shifted out
in parallel, one word per clock pulse, and new serial bits
can be shifted in simultaneously. It is interesting to note
that the same circuit can also accept parallel words and
shift them out in eight serial streams. The difference
between S-P and P-S is not in the circuit, but in the mind
of the beholder.

OUT

112203

New serial data can be shifted in from one side, while old
parallel data is being shifted out at the opposite side.
There is no need for any of the additional flip-flops required
by the older designs.
After eight clock pu Ises, the mode control is again changed
to A and old data is shifted out on the right side while new
data is shifted in from the left.
This design uses only 64 flip-flops, and a mode-control
signal derived from a divide-by-8 counter. The physical
routing of the input signals can be done on-Chip, but the
eight bottom output pins can be externally combined with
the eight right-hand outputs. in a wired OR.

Such a "Corner Bender" is available as a standard part, the
Plessey MJ 1410 8-Bit Format Converter. Its drawbacks
are high power consumption (max 500 mW) and slow
speed (2.4 MHz guaranteed worst case), a result of its
NMOS heritage.

The deSign fits exactly into one XC2064 or into half of an
XC3020 and can run at up to 50 MHz.

The LCA implementation of a 2-dimensional shift register
is straightforward:
A common clock drives all flip-flops, organized in an 8 x 8
array. In mode A, each flip-flop receives data from its "left"
neighbor; in mode B, each flip-flop receives data from its
neighbor above.
I

For the first eight clock pulses, the array is in mode A,
receiving eight bit streams and right-shifting them into the
array. For the next eight clock pulses, the array is in mode
B, down-shifting the previously received 64 bits.

I
I
I

PHASE A

D

PHASES

1122 02

6-44

100 MHz Frequency Counter
Application Brief
The block diagram below describes a complete 100-MHz
frequency counter in an XC3020 PC84.

BY PETER ALFKE AND NICK CAMILLERI

The high resolution of 100 MHz or 10ns is achieved by
using the divide-by-two flip flop driven by the alternate
clock buffer. This is the simplest and therefore fastest flipflop on the device.

A 32,768-kHz crystal oscillator generates a time base of
two seconds. The frequency to be measured clocks an 8digit BCD counter. At the end of the measuring period of
two seconds the counter content is transferred into four
shift registers, and the counter is then reset before the
beginning of the next measuring period. The shift register
drives a 7 -segment encoderthatfeeds int01he LCD driving
logic, which in turn drives seven 8-bit shift registers nestled
in the lOBs.

The whole frequency counter uses 60 of the 64 CLBs in an
XC3020:
Time Base
BCD Counter
4 Shift Registers
7-Segment Encoder
Leading Zero Suppressor
Control
Segment Conversion/
LCD Driving Logic
Special Clock Generation
Miscellaneous

The oscillator uses three lOBs, since the dedicated crystal
oscillator input is already used as signal input.
The time base is generated by a 16-bit-binary counter
consisting of fou r asynchronously cascaded 4-bit synchronous counters. The control unit eliminates the clock ripple
delay by re-synchronizing the time base output. The eight
counter decades are cascaded asynchronously, each
decade consisting of a synchronous BCD counter.

8CLBs
16 CLBs
16 CLBs
4CLBs
2CLBs
2 CLBs
4CLBs
6CLBs
2 CLBs

This design is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778.

XC3020

fin
(0•.. 100 MHz)

I~-;:-~.::!:.,
:.
,B

I:~ '~~:)JJJJ

~

B-BITSR
FOR"B"

~

8-BITSR
FOR"C"

~
I~

~

8-BIT SR
FOR"D"

~

~

8-BIT SR
FOR"E"

~

8-BIT SR
FOR "F"

~

8-BITSR
FOR"G"

~

FOUR
8-BIT SHIFT
REGISTERS

~

I
~
~

~

!
~

~
~

MSO

4

VOSHIFT+-----,
CLEAR COUNTERS + _ - - - ,

TRANSFER~
ENABLE COUNTER...,

I

I

~--~~~

n

-'

CONTROL
LOGIC

I
l~ J3~~~ ILlIJ TI~~~~E
~

LEADING
ZERO
SUPPRESS

COUNTER

LCD
DRIVING
LOGIC

~

8 DIGIT
LCD
DISPLAY

It-___
I

BA_C_K_PL_AN_E..:..(C_LO_C_K'--)- 4 - - - - - - - - - - f - -

Figure 1. Block Diagram

6-45

1129018

III

Megabit FIFO in Two Chips:
One LCA and One DRAM

~XILINX

Application Brief BY PETER AlFKE AND NICK CAMillERI
A bit-serial FIFO buffer is a general-purpose tool to relieve
system bottlenecks, e.g., in LANs, in communications, and
in the interface between computers and peripherals.
Small FIFOs are usually designed as asynchronous shift
registers, but a larger FIFO with more than 256 locations
is better implemented as a controller plus a two-port RAM,
or as a controller plus a single-port RAM, either SRAM or
DRAM.

This FIFO DRAM controller consists of:

SRAMs are fast and easy to use, but at least four times
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer low-cost data storage, but require complex
timing and address multiplexing, which makes them unattractive in small designs. For FIFOs with more than 256K
capacity, a DRAM offers the lowest cost solution, if the
controller can be implemented in a compact and costeffective way. An XC3020 Logic Cell Array can easily
perform all the control and addressing functions with many
gates left over for additional features.

• A 4-to-1, 10-bit address multiplexer

DIN
IClK
DOUT
OClK

n
n

VO
BUFFER

• An inpuVoutput buffer with synchronizing logic
• A 20-bit Write pointer (counter)
• A 20-bit Read pointer (counter)
• A 20-bit full/empty comparator

• Control and arbitration logic
The Write pointer defines the memory location where the
incoming data is being written, the Read pointer defines
the memory location where the next data can be read. The
identity comparator signals when the FIFO is full or empty.

a

n"
7
n

•

D

RORB
(Read ReadylBusy)
WRRB
(Write ReadylBusy)
FULL
EMPTY

CONTROL
DRAM

10
MUX

WRE

AO-9

RDE

~______________~3~__~__~-+~

WE
Figure 1. Megabit FIFO Controller in an XC3020

6-46

1130 01A

I:XILINX

D--i
= +-1
)D-1

I.

When the Write and Read pointers become identical as a
resuH of a Write operation, the FIFO is full, and further
Write operation must be prevented until data has been
Read out. When the two pointers become identical as a
rasuH of a Read operation, the FIFO is empty and further
Read operation must be prevented until new data has·
been written in. With a single-port RAM,Read and Write
operations must be inherently sequential, and there is no
danger of confusing the full and empty state, a problem
that has plagued some two-port designs.

The RAS/CAS muHiplexing of the 20-bit address is performed without any logic by tiiPpingevery other bit of the
shift register counter and using the 10 outputs before the
incrementing shift as Row address, afterthe incrementing
shift as COlumn address. (The Column address of any
position is ·thus identical with the Row address of the
.following position, but since the binary sequence of a shift
register counter is pseudo-random anyhow, this is no
problem. It's an elegant and efficient triqk).

COMPARATOR

SHIFT-REGISTER-COUNTER

III 1 III III

I
1130 02

Figure 2. Shlft-Reglster-Counter and Free Row-Column

MUX

A straightforward design would use synchronous binary
counters forthe two pointers, but it is far more efficient to
use linear shift-iegister (LSR) counters. Such counters
require far less logic and.are faster since they avoid the
carry propagation problems of binary counters. LSR
counters have t.wo peculiarities: ~hey count in a pseudorandom sequence and they usually skip one state, Le., a
20-bit LSR counter repeats after 220-1 clock pulses. In a
FIFO Controller, both these features are irrelevant, the
address sequence is albifrary, provided both counter
sequence identically.
This design fits two· shift register counter bits in one
XC3000-series CLB and the identity comparator uses the
combinatorial portion of the same CLB.

SHIFT-REGISTER.COUNTER

takes advantage of the DRAM internal refresh counter by
using CAS-before-RAS refresh/address strobes.
Both 20-bit pointers, plus their 20-bit identity comparator,
plus the Row/Column multiplexer thus fit into only
20 CLBsj refresh timer and address multiplexer use another 10 CLBs and the data buffer plus control and arbitration logic take another 23 CLBs, for a total of 53 CLBs, an
easy fit in an XC3020.
This design can easily be modified for 256K DRAMs.
Other variations are: muHiple parallel bits, e.g., byteparallel·. operation,. interrup~-driven control, .. multiplexed
data for multiple parallel-bit storage, and byte parallel
storage with bit-serial I/O. The laltercase requires special
attention when the FIFO is emptied after a non-integer
.number of.bytes had been entered, requiring direc.t communicatiqn between the input Serial-to-Parallel converter.and fhe output PIS converter_
This· applications brief shows that tlie XC3020 can be
programmed to control one or a few DRAMs as a large
FI FO of up to. a megabyte, with data rales up to 16 Mbps
serially or 2 Mbytes per second byte-parallel.

The FIFO controller permits the user·to perform totally
asynchronous Read and Write operations, while it synchronizes communication with the DRAM. The design

This deSign is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778.

III

READ ADDRESS

WRITE ADDRESS

Figure 3. 2.~Bit Slice of Two Counters and Comparator In Two ClBs

6-47

1130 03

State Machines
Application Brief

BY PETERALFKE

SIMPLE STATE MACHINE RUNS AT 30 MHz

State-machine design is a methodology that defines the
contents of all flip-flops for any possible state of the design,
then defines all possible paths that can cause the design
to go from one state to another. In its simplest form this is
just a rigorous way of designing synchronous logic, like
4-bit counters. For complex designs, the state-machine
approach gives the designer a tool to investigate all
possible operating conditions and avoid overlooked hangup states or undesired transitions. LCA devices with their
abundance of flip-flops lend themselves well to statemachine designs.

This simple state machine uses only 11 CLBs. It has up to
16 states, and eight outputs, each decoding/encoding any
combination of states. It performs a 2-way branch from
any state to anyone of two freely assigned states,
(possibly including the present state) determined by
control input C. (AVOid the branch by making both
destination states equal).
This design can also perform an 8-way branch from any
state so programmed to either one of two selected
quadrants (0 .. 3, 4 ... 7, 8 ... 11 or 12 ... 15). Control inputs A,B
then determine the location within the quadrant.

SIMPLE, FAST STATE MACHINES
Using the 5-input function generator of the XC3000-70
family devices as a 32 bit ROM, a state machine with up to
32 states without any conditional jumps uses only 5 CLBs
and operates at up to 50 MHz.

Examples:
• From state @, if C=High, go to ® else go to ®
• From state (j), if C=High, go to ® else stay in (j)
• From state

The five registered CLB outputs drive the five function
generator inputs olthe 5 CLBs in parallel. This implements
a fully programmable sequencer similar to the synchronous counter shown in the left column of page 6-28.

• From state

®, unconditionally go to ®
®, execute the truth-table below
AB

C=Low

C=High

00

@
@
@
@

ffi®

10

For a smaller number of states, some inputs can be used
as conditional jump inputs. Encoding these condition
codes may require an additional level of logic which
reduces the maximum clock rate to 30 MHz.

01

11

®

ACTIVE 4-WAY BRANCH

6CLBs
WITH

COMMON
INPUTS

4CLBs
WITH

COMMON

B

INPUTS

1986 01

30-MHz State Machine, 16 States, 2-Way/B-Way Branch, 8 Outputs

6-48

Complex State Machine
in One LCA
Application Brief BY PETERALFKE
128 arbitrarily defined next states, controlled by the 7-bit
condition code.

Simple and fast state machines can easily be implemented
in an LCA, as shown on the previous page. This page
shows how an external EPROM can be the source of the
next address in a complex state machine. This look-up
table can easily be hidden in the EPROM required to store
the LCA configuration data.

This basic deSign uses no CLBs in the LCA, just lOBs; but
it allows a number of states and a multi-way branch
complexity far in excess of any normal need. The user will
usually reduce the multi-way branch complexity by
assigning identical values to many of the 128 possible next
states.

Assume that an XC3020 is configured in the Master
Parallel mode, where it reads its configuration data out of
a 256K (32K x 8) EPROM, starting at the top address
location 7FFF (32K) through 77FF (about 30K). The remaining 94% of the EPROM can be used as a next-state
look-up table with a capacity of 240 states.

The user has the logic resources of the LCA available to
add features like:
•
•
•
•

The state address is read out of the EPROM, then manipulated (decoded, encoded, etc.) in the XC3020 LCA. The
result is combined with incoming-control information to
generate a new EPROM address. The EPROM can be
considered as having 240 locations, each 128 bytes wide.
Each byte is a potential next-state value, only one of which
will be chosen by the 7-bit condition code.

State decoding/encoding
Stack registers
Loop counters
More sophisticated branch logiC, etc.

This design is straightforward, inexpensive, compact and
very flexible. Its speed is limited by the EPROM access
time, which can be less than 100 ns. For higher speedat a higher cost-the EPROM can be shadowed by fast
SRAMS.

In the simplest case, the EPROM output data is just
latched in the LCA and is fed back as the most-significant
part of the new EPROM address. Since the top 16 address
locations are used for configuration data, the state codes
are limited to 240 different values, 0 ... 239.

27C256
EPROM

STATE
OUTPUTS

The seven control inputs form the seven least-significant
EPROM address bits. For reliable operation with asynchronous control inputs, they must be synchronized in an
input register.

CONDITION
CODES
1987 01

II

This rudimentary state machine can thus have 240
different states, and can jump from any state to anyone of

6-49

PS/2 Micro Channel Interface
Application Brief BY ROB STRANSKY
IBM's general-purpose microcomputer, the Personal
System 2, is available in several models, from the low-end
Model 25 to the high-end Model 80. These thirdgeneration PCs have several innovative features,
including 3-1/2 inch floppy-disk drives, high-resolution
VGA graphics, and a 20-MHz 80386 processor as
the main engine for the Model 80. Among the
most interesting features is the Micro Channel interface,
the bus specification for the interface between the
system and adapter cards. The Micro Channel's
streamlined characteristics and flexibility provide PS/2
designers and users with many advantages over previous
PC architectures.

bus adapter cards. Defined with System Configuration
Utilities, an add-on card's addressing and other optional
configuration data are established and stored in CMOS
battery-backed memory on the main board. Upon powerup, this information is loaded into Programmable Option
Select (POS) registers residing on the adapter cards.
Figure 1 indicates one way in which a Logic Cell Array can
be used for the POS-register section of a Micro-Channel
adapter card. The Micro-Channel interface includes logic
to decode the address, status, and control signals associated with the bus to identify the appropriate POS register
to be accessed. These signals determine if the card is
being addressed, and whether the current operation is a
Read or Write.

One key aspect of this architecture is the ability to configure the system without the need for DIP switches on the

CONTROL
READ
ENABLE

-RD

STATUS
LINES ~

READ!
WRITE
DECODE

EN

WE

GATED
WRITE
STROBES

LATCHES

CARD
SELECT

-

111111

r
...........

POS
REGISTERS
(UP TO B)

I-- I--

~

r

SYSTEM
BIDIRECTIONAL
DATA BUS

1
REGISTER
ADDRESS
INPUTS ~ DECODES

~
1H901A

Figure 1. Micro-Channel-Interface Block Diagram

6-50

l:XiLINX
The Micro Channel specification reserves two P~S registers for the upper and lower bytes of the Adapter Identification (10). Six other byte-wide P~S registers can hold
additional configuration information; some of the bits
within these are specifically dedicated to channel status
information. Some applications will require the use of only
portions of these six registers.
A second key aspect of the Micro Channel architecture is
its ability to arbitrate the bus access of muHiple adapters.
The Micro Channel specification clearly defines the logic
required for this arbitration. Each adapter in the system is
assigned a priority leVel. These levels vary from the
highest priority"-2" to the lowest priority "F". This "-2, -1,
0, 1, 2...A, B, ... F" scheme defines unique priority levels.
The higher levels are primarily used for memory refresh or
error recovery. The lower levels are reserved for the
System Board processor and spares. Themiddle levels
are used for DNA Ports 0-7, typically used for high speed
transfers. The priority level assigned to any adapter is
stored in one of its P~S register nibbles. The arbitration

logic must be very fast in order to grant control of the bus
to the adapter with the highest priority.
As can be seen by the logic in Figure 2, this priority level
(ARB 10 0-3) is driven onto the bus via an open-collector
driver. The logic then turns around and accepts the driven
bus as input. The cycle may repeat a few times before the
adapter with the highest priority level actually gains control
ofthe bus. Forproperoperation each half of the cycle must
complete in 50 ns, a performance that can be achieved in
the 70-MHz LCA devices.

Implementation of the P~S registers, arbitration, logic'and
control sections typically requires only 1/3 to 2/3 of a single
XC2018 or XC3020; the remainder of the LCA is available
for implementing the unique functionality of the specific
adapter, card. Some Xilinx users have developed the
standard interface and stored' it as a recallable macro
function in the Xilinx development system. Applications
including hard disk controllers. communication controllers, and specialized memory controllers have been developed for the PS/2 using Xilinx FPGAs.

COMPLETE LATCH

ARB BUS3

ARB 10-3

ARB 10-2

ARBID·1

>o~~======t:+==I~y_-ARBBUS1

ARB,IO-O

:>o_~===:::=t::ii=3~y_-ABB BUSO

"~~1~~:~:Q~~§~)_____

~
ARB/·ENT

WONCOMPETITION
FOR
CHANNEL

111902A

Figure 2. Local Arbiter Logic

DRAM Controller
with Error Correction and
Detection
Application Note
AN INTRODUCTION TO MEMORY CONTROL AND
ERROR CORRECTION

BYTOMWAUGH

to incorporate error detection and correction into the
memory system. This solution decreases system performance and adds the cost of redundant memory, but prevents parity errors from causing system failures.

The need to design memory controllers for systems that
have a large amount of memory is a common design
challenge that engineers must deal with today. Almost all
large memory systems use dynamic random access
memory (DRAM) because of its density and low cost.
While designing large memory systems with static random
access memory (SRAM), would make the design task
easier, the drive to produce more cost effective products
forces the engineer to design with DRAMs, despite their
inherent drawbacks. The memory cell of a DRAM is a
capacitor that holds a charge corresponding to the value of
the data bit. Since all capacitors leak charge, a DRAM cell
will gradually lose its charge, and its stored value, unless
it is recharged. This recharging, known as refreshing,
must typically be performed once every 2 to 4 ms depending on the DRAM. Refreshing is one of the DRAM
controller's two primary functions. The other function is to
arbitrate between requests for memory read and write
accesses from the system's central processing unit and
requirements for memory refreshes.

OPTIONS FOR DRAM CONTROLLER DESIGN
There are a number of options available to the engineer
designing a memory system that requires DRAM control.
(The following options apply to the deSign of error detection and correction circuits as well.) The simplest option is
a standard off-the-shelf LSI memory controller. The manufacturers of these devices provide an integrated solution to
DRAM control by combining CPU interface logic with the
necessary memory access/memory refresh arbitration on
a single Chip. However, each memory system has unique
timing and protocol requirements, and it is extremely
difficult for these standard parts to accommodate the
requirements of every system. This realization has driven
many DRAM controller manufacturers to incorporate
some degree of programmability into their parts to make
them more flexible. Unfortunately, this has made the parts
more complex, hungrier for power, and more expensive.
Even so, they simply cannot meet every system's requirements without employing external "glue logic."

In addition to its need for periodic refreshing, the DRAM
exhibits another problem that SRAM and other memory
devices do not-greater susceptibility to soft errors. A soft
error is the loss of a data bit in a memory cell in which the
memory cell is not physically damaged. Rewriting the data
in the cell corrects the error. This type of error is different
from a hard errorwhich is caused by a memory cell that has
failed permanently. Soft errors in DRAMs are usually
caused by alpha particles (helium nUClei), which are normally present in the atmosphere, but which are more often
emitted by radioactive impurities in the IC packages of the
DRAMs themselves. If an alpha particle hits a memory
cell, it can corruptthe cell's charge, causing a data bit error.
Most people believe that the likelihood of such an error is
so low that it can be safely ignored. While this may have
been true for the smaller memory systems of the past, it
may no longer be so. The size of some memory systems
today can make the likelihood of soft errors unacceptably
high. The probability of a soft error can be reduced by
device and packaging improvements and by reduction in
signal noise. Another method of dealing with soft errors is

The need to match the DRAM controller to the specific
requirements of the system has forced many engineers to
consider two options for creating their own controllers:
SSIIMSI packages or custom gate arrays. The use of SSI/
MSI is low risk, but wastes space and power; while the use
of the custom gate array provides a highly integrated
solution, but at considerable risk and expense. Nonrecurring engineering costs (NRE), testing and simulation
costs, inventory risk, and a long design cycle make the
custom gate array option unattractive for most designs.
Recent architectural advances in high-density Field
Programmable Logic Arrays have created a third option.
Xilinx's 3000 family of FPGAs brings unprecedented
density to programmable logic, with devices containing as
many as 9000 gates. The 3000-family architecture makes
the devices particularly well-suited to memory-controller
applications.

6-52

WHY IMPLEMENT A DRAM CONTROLLER WITH A
FIELD PROGRAMMABLE GATE ARRAY?

comprising 44 2S6K DRAMs: 32 for data and 12 for the
correction bits. A single LCA device can serve as both the
DRAM controller and the ECC, which performs single- bit
error correction and double-bit error detection. There are
several features of the 3000-family architecture that make
this design possible. These include five inputconfigurable logic blocks (CLBs) with two storage
elements, internal buses, and flexible input/output
blocks (lOBs).

There are several reasons why one would want to design
a DRAM controller with a Logic Cell Array. First, the true
programmability of the LCA device gives the designer the
freedom to design the DRAM controller to the exact
specifications of the memory system. There is no need for
the external "glue logic" often necessary with standard
solutions, because any necessary design tweaking is
implemented internally. The LCA solution has the
advantage of the SSI/MSI or custom gate array solution in
that it can be configured to meet unique system
requirements. There is no loss in integration as with the
SSI/MSI solution, and the cost and risks of the custom gate
array solution can be avoided. Second, the density of the
3000 family of LCAs makes it possible to implement DRAM
control and error detection/correction in a single LCA
device. This is traditionally a two-chip solution using
standard parts: a DRAM controller and a separate error
correction and detection unit. It can of course be
implemented in a single custom gate array, but again with
the earlier caveats. Finally, the CMOS LCA consumes
less power than traditional standard "programmable"
controllers which are typically implemented in NMOS or
bipolar processes.

DESIGN OVERVIEW
The DRAM Controller/ECC uses a 16- MHz clock
synchronized with the processor clock, and sits between
the 8086 microprocessor with its 8288 bus controller and
the system memory (Figure 1). The 8288 decodes the
processor status lines (S2' S1' So) and tells the DRAM
Controller whether it is to perform a Read or Write access
to the memory. (It is also possible to incorporate the bus
controller logic into the larger LCAs). The DRAM
Controller then performs the appropriate access issuing
Row Address Strobe (RAS), Column Address Strobe
(CAS), and Write, if necessary. The Error Checker and
Corrector generates check bits on each Write, and checks
for and corrects errors on each Read. The controller also
signals the 8086 if the memory access requires a Wait
state or if a non-correctable error is detected.

DESIGN EXAMPLE
SYSTEM TIMING

The following design example shows the implementation
of a DRAM controller and an error checker/corrector
(ECC) with an LCA. The example is an 8-MHz 8086-based
system that directly addresses 1 Mbyte of memory

8284
CLOCK
GENERATOR
READY

lcLK

So

~ READY
' - - - - RESET

S1
S2

--

Figures 2a -2c show the timing involved in some of the
different memory cycles. The Word Write (Figure 2a)
requires no wait states as shown. The check bits from
the ECC are written to memory along with the data. The

LeA

8288

I-

BUS

CONTROLLER

I-

MRDC
AMWC
CEN

8086

W
CAS H.L

r-r--

I---

RASo.1

READ
WRITE
HOLD

OUT 0·8

r=:;
r

DEN

6+16=22
256K DRAMS

~

:

CBO·5
(CHECK BITS)

ENABLE

'r-- ,...., ADO·15

MULnBIT
ERROR
WAIT

~

DATA
BITS

J:f
BITS

A16·18

r--'--

BANK 1
(512 KBYTES)

AO·8
CHECK
BITS

BANK SELECT

A19
A16·18

AD()'15

BANKO
(512 KBYTES)

b;
t;;;

DATA BUS

~

r-

TO 8086 NMI

DATA
BITS

1

r-

16

1127 09A

Figure 1. System Overview of DRAM Controller with Error Correction and Detection.

6-53

•

DRAM Controller with Error Correction and Detection

T3

T2

T1

T4

8086
CLOCK

ALE

~___________________________________________

CONTROLLER
CLOCK

RAS

CAS

W

DATA FROM
8086

-------~<~

___________________J)~-----1127 03

Figure 2a. Word Write Timing

T3

T2

TW

TW

T4

TW

8OB6

CLOCK '--____-'

CONTROLLER
CLOCK

----'I
L..-_-.JI

AAS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

L - - -________

CAS

~

W

WAIT
DATA BUS

-.J

~L.__________________________________

ERROR DETECTED
CORRECTED DATA LATCHED
CORRECTED DATA RELEASED
___________<=======~~~===============>~I/O~3:.S~T~AT~E~D~============)
1127 04

Figure 2b. Word Read Timing with Errors Detected.
~
8086
CLOCK

I

n

I

TW

I

u

I

~~Il~~Il~~Il~~Il~__

RAS - - - ,..______________________________________-J

CAS

WAIT ---,..__________________..1

DATA6~~~ --------------~<~________-------------------J»~-----1127

Figure 2c Word Read Timing with No Errors Detected.

6-54

os

E:XIUNX
design, the address is latched into the lOB input flip-flop
with the 8086 ALE. The data from the 8086 can enter the
same input pin andgodirectlytothe ECC circuit via the lOB
direct input-there is no need for external latches.

Read cycle (Figures 2b & 2c) requires a minimum of one
wait state. The insertion of a wait state is unavoidable
because of the time it takes the 120-ns DRAMs to output
the data. If the ECC detects no errors in the data, the WAIT
signal is released and the Read operation is completed. If
an error is detected, the insertion of two more wait states
is required to provide time to correct the error. The
insertion of the two additional wait states affects system
performance, but this is the trade-off for having error
correction, which avoids the fatal system errors that occur
with parity-checking-only solutions.

Another feature of the lOBs is the output flip-flops with
three-state buffer enables. This feature permits bit error
correction using only one 1/0 pin. Figure 4 shows a bitsliced view of how the ECC is accomplished. A memory
Read cycle provides the best example for showing the
capabilities of the lOB structure. During a Read, the lOB
output is 3-stated,permitting the DRAM data on the data
bus to enter the ECC via the lOB direct input. If the ECC
detects a data bit error, it corrects the error and latches the
corrected data word into the output flip-flops of the lOBs.
The data bus is then 3-stated by turning off the DRAM
outputs .. The corrected word, latched in the outputs of the
flip-flops, is then released onto the data bus by enabling
the 3-state buffer. This permits the corrected data to be
read by the8086 at the same time it is being written back
to the DRAM.

DESIGN FOCUS
The 3000-family LCA architecture has a number of features that are essential to the DRAM controllerdesign. The
first such feature is the dual data input paths in the lOBs,
one registered and one direct. This structure permits the
address and data on a multiplexed bus to be latched from
the same I/O pin. Figure 3 is a bit-sliced view of an lOB
used to latch the multiplexed Address/Data bus. In this

,,--------------------

r------t--

,r-<:]--fo---oi----..;.
,, ,, - --- ----I~-1
L ___ .J:

..--;'_ _ _...;D;;;'R;;;;EC;.;.T;;.;;NP..;;.UT'---t_+

OUTPUT ENABLE
CORRECTED DATA OUT

,1+-+-- ~~~~eE~~RRECTORJ
~-+_-

OUTPUT CLOCK

r-------t-gA~M~R~~~ECTOR
r---,

~~~~:~~ECTOR

+_ ~8g~~~"~~A~~ERNAL

,~RE;::G'S::.;.T:;;;ER:::ED:.::;N::..:PU,,-T

'0
,,,

BUFFER

,,
,

OL __ -

IL ___ .J4---

,

'---------L _______________________
_

ALE

1127 OSA

112707

Figure 3. Address and Data Latching
Latching Data off a Multiplexed Address and Data Bus.
The InputlOutput block configuration shown above
illustrates how the direct and registered inputs in the
lOBs can be used to latch a multiplexed addressldata
bus into the LCA. The address is latched into the lOB
flip-flop; the data flows directly into the ECC logic.

Figure 4. Data In and Out Through ECC
The data from the bus goes into the LCA, where it is
corrected in the ECC. The corrected data is then put
back onto the bus via the lOB output flip-flop.

6-55

II

DRAM Controller with Error Correction and Detection

by this block include the row address and column address
strobes (RAS and CAS), the WRITE signal, the WAIT-state
signal for the processor, the HOLD signal that isolates the
processor from the memory, the clock for the refresh
address counter, and the select control for the address

Figure 5 is a block level diagram of the DRAM Controller
and ECC that reside in the LCA. A functional description
of each block follows:
The refresh timer is driven by the 16-MHz clock to provide
a signal that tells the DRAM controller that the memory
needs refreshing. Each of the 256 rows of memory in this
system must be refreshed every 4 ms. The controller
attempts to refresh eight rows every 125~, so that all 256
rows are refreshed in 4 ms. The refreshing technique
employed in this design is a unique combination of burst
and hidden refreshing to show the flexibility of the
LCA-based solution. There is no need to force a system to
conform to the constraints of an oll-the-shelf part. The
Hidden Refresh is performed when the 8086 is doing a
Read from or Write to somewhere other than memory, like
an I/O port. This involves giving the DRAM a refresh
address from the refresh address counter vi a the address
selector and a RAS pulse Low from the timing generator.
The Burst Refresh is performed only if it has not received
its eight required refreshes during the 125-~ refresh
period. When a Burst Refresh is required, thecontrollerwill
isolate the memory from the 8086, insert wait states, and
provide the number of refreshes it needs to complete the
eight refreshes required during the refresh period.

select.
The refresh address counter is an 8-bit counter that provides the 8-bit addresses necessary to refresh the DRAMs.
The address selector selects which address is sent to the
DRAM. During a Read or Write cycle, the timing generator
select control signal tells the address selector to select
the DRAM row address, strobe it with the RAS, and then
select the column address and strobe it with the CAS.
During a refresh, the address selector selects the address
from the refresh address selector and strobes it into the
DRAM with RAS.
During a Write cycle, the error checker/corrector (EGG)
generates six check bits using a modified Hamming code
fo reach 16-bit data word and writes them to memory along
with the data. Use of a modified Hamming code permits
single-bit data correction and double-bit error detection.
During a Read cycle, the ECC compares the check bits
read back from memory with new check bits generated
from the data read back. If the comparison yields a
correctable error, the ECC will correct it. If the error is not
correctable, it will flag the NMI on the processor.

The timing generator, a state machine triggered by Address
Latch Enable (ALE) at the beginning of the processor
cycle, produces all the timing required to perform the
memory accesses and refreshes. The signals generated

DATA BUS

16
TO DRAM DATA

TIMING
GENERATOR

REFRESH TIMER

DO·15

BURST REOUES
HIDDEN REOUES
RESET

CBO-5

TO DRAM DATA

ERROR CHECKER!
CORRECTOR

ECC
CONTROLS

MULTI·BIT ERROR

TO 8086 NMI

W

A19

TO DRAM

RASO,1
CASH.L
FROM
BUS CONTROLLER

MUX CONTROL
16MHz

TO 8086
TO BUS CONTROLLER

WAIT
HOLD

b==£AADDODRR8ESSis3MMUuxxl

INCREMENT
TO DRAM ADDRESS

REFRESH
ADDRESS
COUNTER

A10·18
REFRESH
ADDRESSQ·7

INCREMENT
COUNTER
1127 02A

Figure 5. LCA Block Diagram
Block diagram of the DRAM controller functions implemented in the LeA.

6-56

E:XILINX
Perhaps the most important feature of the LCA architecture for implementing a DRAM Controller is its internal
three-state bus capability. The three-state buffer enables
onto the horizontallonglines allow the designer to implement an internal bus in the LCA. This feature permits the
implementation of the Address Selector without using any
CLBs. Figure 6 shows a bit slice view. The row, column,
and refresh addresses all have access onto the internal
bus, and to the outputs that lead to the DRAMs. By
controlling the three-state enables, only one address is
allowed onto the bus at a time. This feature is essential to
this design, and has many other applications including
performing wired-AND functions and address decoding.

CONCLUSION
Although the bottom-up design of a DRAM controller is a
complex task, it is necessary in cases in which off-the-shelf
controllers do not meet the requirements of the system.
SSI/MSI and custom gate array solutions involve tradeoffs and compromises. Designing a DRAM controller and
ECC with an LCA is a straightforward application and a
good fit for the 3000 family architecture. The Field Programmable Gate Array offers the flexibility necessary to
match the many different memory systems, the integration
desirable for board level designs today, and the cost
effectiveness required to make a competitive product.

INTERNAL BUS

-----,.----------,.----------,.-- !gg::s~
ROW
ADDRESS

COLUMN
ADDRESS

REFRESH
ADDRESS

ROW
ENABLE

COLUMN
ENABLE

REFRESH
ENABLE

LINE

112708

Figure 6. Address Multiplexing Using 3-5tate Enables onto Internal Buses

6-57

The Programmable Gate Array Company

6-58

SECTION 7
Article Reprints

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7 Article Reprints

8

Index

Article Reprints

Build Reconfigurable Peripheral Controllers ....................................... 7-1
Accelerate FPGA Macros with One Hot Approach ............................. 7-8
Reprogrammable Missile: How an FPGA Adds Flexibility
to Navy's Tomahawk ....................................................................... 7-13
Pivoting Monitor Increases Versatility of Workstations ....................... 7-15
Two, Two, Two Chips in One .............................................................. 7-19
LCA Stars in Video .............................................................................. 7-22
Taking Advantage of Reconfigurable Logic ........................................ 7-24
Faster Turnaround for a T1 Interface .................................................. 7-33
Using Programmable Logic Cell Arrays In a Satellite Earthstation ..... 7-35
Programmable Logic Betters the Odds for Bet-Slip Readers .............. 7-40
Building Tomorrow's Disk Controller Today ........................................ 7-44

l':XlUNX

DESIGN APPLICATIONS
By INCLUDING A RAM-BASED PROGRAMMABLE
LOGIC CIRCUIT, ONE CONTROL CARD CAN
READILY HANDLE MULTIPLE INTERFACES.

BUILD RECONFIG-URABLE,
PERIPHERAL CONTROLLERS
uring the design of a computer peripheral, such
as a printer, CRT terminal, disk drive, or other
complex subsystem, decisions are often made
regarding control logic partitioning. In some instances, the peripheral contains all of the control
circuits, and the interface to a host system is
over a standard port, such as an RS-232 or Ii Centronics link. However, the
limited data-transfer speed and signal-control flexibility of those ports often
causes a bottleneck when '{!'iff large amounts of data must be transferred or
complex operations must be controlled.
One solution is to keep the data-intensive portion of the logic in an adapter
board that plugs into the host computer's bus and supply a custom high-speed
link to the peripheral. But using hardwired logic to implement the adapter card
limits the card's flexibility if updated versions of the peripherals are released, or
if a second, relatively different' model is developed. Ideally, one adapter card
should be all that's needed. Simple software updates'(device drivers) that can be
loaded into the card for the specific model peripheral can provide an optimized
interface.'
,
Such aperipheral-control card can readily be developed by taking advantage
of RAM-based programmable logic circuits, such as the logic cell arrays from
Xilinx (see "RAM-based Prqgrammable Logic'~. And the card's function can
be altered in the field with just a new software driver that's loaded when the system boots.
•
Furthermore, if the data is RAM -based, itcan be altered during system operatiorias well. Consequently, if the same card must control multiple printer types,
the' card can be switched between printer drivers in just milliseconds by,reloading the RAM-based programmable logic circuits to reconfigure the interface onthe-fly. Such a controller can be easily modified to support new peripheral devices, and it will never have to be removed from the computer system.
Programmable logic devices based on static RAM memory cells make it possible to implement "soft" hardware-that is, hardware whose functions can be
KENNETH K. HILLEN
Tektronix Inc., Mail Stop 63-356, P.O. Box 1000, Wilsonville, OR 97070;
(503) 685-3904.
BRADLY FAWCETT
Xilinx Inc., 2100 Logic Dr., San Jose, CA 95124; (408) 559-7778.

7-1

Article Reprints

FLEXIBLE PRINTER
CONTROLLER
serCard printer controller from the
Grl\phics Printing and Imaging Divi·
sion of Tektronix. By iniplementing
Bus
interface
the system architecture in that fash·
chip
68020
ion, the card helps designers make
printer changes or add new printers,
still keeping the design cycle very
short because there are less circuits
Printer in the printer to deal with.
----'WaH·state
_chip
genalator
A key ease·of·use feature for laser
8·bil data bus
XC2018
and color thermal printers would be
to have them emulate Adobe Sysdecoder
512.byte
tem's Postscript and Hewlett-PackFIFObuHer
ard's HPGL graphics-description
24-bit
32·blt data bus
addrestbus
languages. To do that, the host system plug-in board includes the emulation capability along with a 68000Pixel
ROM
family microprocessor and a custom
coproceaM
chip that. accelerates the computations needed to prepare an image for
printing. Furthermore, the PCI ATI
Memory
XT bus·compatible card uses one of
RAM and
CPU register r--EEPROM
the smaller Xilinx programmable
-EPROM
gate arrays for the printer interface
logic and a mask-programmed gate
array to control the interface to the
1. IT'S ONLY ASMALL PORTION of the circuitry used on the 6802lHJased
host PC's bus (Fig. 1).
intelligont printer controller, but the reeonfigurable printer output chip gives the board ile
flexibility. Two dedicated custom chips on the card handle the pixel processing and the host·
By 10l\ding the appropriate configsystem bus interfl.e.
uration program into the programmable logic chip, the controller card
changed while it resides in the sys' amounts of data and some special can be used with any of several printtern. The configuration programs control signals to keep their print en· ers. They include monochrome laser
can be loaded automatically at pow· gines busy and ensure optimum per· printers (such as the Canon LBP8),
er·up or on command at any time. formance. Yet to have a custom the Tektronix 4696 (a 120-dot·per·
Both users and manufacturers bene· adapter card for each printer would inch ink-jet color printer with a Cenfit from this flexibility. Microcom· get very expensive, especially if two tronics interface), the Tektronix
puter users can easily change or up· such printers were needed. By pull· 469;lD/DX (a 3OO-dot-per-inch waxgrade peripheral devices without ing out the. common control circuits transfer color printer with a Tekpurchasing a new controller or alter· needed by either printer type and im· tronix Parallel Interface-an en·
ing the internal hardware of the sys· plementing those circuits in both hanced version of the Centronics in·
tern. Equipment manufacturers custom and RAM·based program· terface), and the new Tektronix
don't need to design a new controller mabie logic, system cost can be mini· Phaser CP (a 300-dot-per-inch waxboard for each new peripheral.
mized and users save one card slot in transfer color printer with a synAs a result of the improved flexi· the host system. In addition, because chronous serial interface). The Phability, new peripherals can be the printer has a minimal amount of serCard includes two printer interbrought to the marketplace sooner, logic in it, upgrades to the mecha· face ports so that two printers can be
and the cost of initially developing nism would cost less as well.
connected simultaneously.
the flexible peripheral controller
Considerable processing power is
board is amortized over a larger CONTROLLING PRINTERS
needed in order to interpret the
number of units. The ability to sup·
Consequently, by dividing the con- graphics·description languages, perport future peripherals extends the trol and processing logic that a com· form image processing, and run the
controller's product life. Field up· plex printer needs, the overall. sys- printers. To handle the housekeepdates to the controller can be accom· tem can be made more flexible. The ing and manage the host system in·
plished by distributing new program printer. would contain only the basic terface, a 68020 32-bit processor,
disks to update the logic configura· machine-control circuits and the running at 12 MHz with one wait
tion, as opposed to requiring hard· printing control logic, while the host state, readily h,mdles the control and
computer's plug-in card would con- leaves room for program growth if
ware modifications to the board.
Advanced page printers and color tain all of the data-procf'ssing logic. more complex. tasks must be hanthermal printers require huge This approach was taken by the Pha- dled. To eliminate the bottleneck of

-

I

t

~

~

~

-

.......
.....

IBM PC bus

~~

-

4

....
~

~

1

~

.....

I

7-2

~XIUNX

FLEXIBLE PRINTER
CONTROLLER
converting the page description into
the raster image, a custom graphics
coprocessor tackles all of the computations. The chip is a full-custom IC,
and assists in image generation during line drawing, area filling, and
half-toning operations. Lines can be
drawn at 6 million pixels!s.
During operation, the CPU accepts image description input
streams from the host bus, rasterizes the image into bit-map memory
(with assistance from the coprocessor), and then transfers the bit map
to the printer interface logic. All timing signals are derived from a 24.23
MHz oscillator.
The processor's code and data, and

B

ased on static RAM cells
that hold configuration
data rather than metal
wiring Or some form of
nonvolatil¢)nemQrY, the Xilinx
programmable gate arrays are
high-density CMOS chips that
combine user-programmability
with the flexibility and extensibility of a gate-array architecture.
The general structure of the Xilinx programmable gate arrays,
also known as logic cell arrays
(LCAs), consists of a core area
containing a matrix of configurable logic blocks (see the figure).
Interspersed with the logic blocks
are channels with programmable
interconnections, and surrounding the core area is a ring of programmable 110 cells. The I/O
blocks supply an interface between the external package pin
and the internal logic. Each of the
configurable logic blocks includes
a combinatorial section, storage
elements, and internal routing
and control logic. Programmable
interconnection resources provide the routing paths that connect the I/ 0 and logic blocks in
the desired configuration.
Similar to a microprocessor, the
LCA is a program-driven device.
The configuration program is
loaded automatically from an external memory on power-up or on

the configuration programs for the
programmable logic chip reside in
on-board RAM. That RAM would
typically be loaded from the hostsystern's hard disk. Code updates could
thus be distributed on diskettes,
eliminating the need for a technician
or service person to replace a nonvolatile memory chip from the control
board to upgrade the card. To hold
the control code and the page description, 3 Mbytes Of dynamic RAM
are included on the control card, and
an additional 5 to 8 Mbytes can be
added through a memory-expansion
connector and a daughterboard.
The on-board memory is partitioned into three I-Mbyte blocks-

one holds program code, another
serves as a data buffer, and the third
holds the bit map for A-size, 150-dpi
(dots per inch) printers. The additional memory is required for A- or Bsize, 300-dpi printers. Power-up diagnostics and the bootstrap routine for
downloading from the hard disk are
held in 64 kbytes of EPROM, while a
512-byte electrically-erasable memory holds several parameters that process Postscript files and provide
printer identification information.
A bus interface circuit (BIF), implemented with a 5000-gate maskprogrammed gate array, connects
the controller to the PC bus. The BIF
chip emulates standard LPT (paral-

THE PROGRAMMABLE GATE ARRAYS
command, or is programmed by a
microprocessor as part of system
initialization.
.
Designing with Xilinx programmable gate arrays is similar
to designing with other gate arrays. Users can employ familiar
CAE tools for design entry and
simulation. The Xilinx-specific
software for cell placement and
circuit configuration runs on the
PC! AT and compatibles, as well
as on popular engineering workstations, such as the Apollo and
Sun 3.
Currently, two families of compatible LCA devices are available.
The original XC2000 series includes the 1200-gate XC2064 and
1800-gate XC2018. The secondgeneration XC3000 family has

o

five members, ranging from the
2000-gate XC3020 to the 9000-gate
XC3090. A third family, the
XC4000, is now in development
and should be sampled later this
year. It will offer densities of up
to 20,000 gates.
Because chips in the XC3000 series are now readily available,
they would significantly simplify
the design of a similar printer controller card if it were being done
today. This is because they incorporate on-chip three-state buffers, offer more functionality in
each configurable logic block, and
have improved routing resources.
However, when the controller's
concept was initially started in
1988, only the XC2000 series was
available.

OOrY 00 00

~"bOOi 0 0 0
D

a-rOO
7-3

0

II

Article Reprints

ItlJ.i1H 'UQlle.mult'

FLEXIBLE PRINTER
CONTROLLER
Output
connector 1

CPU

Output
connector 2

1

2. EVEN THOUGH THE PRINTER output-control chip is based on a

programmable logic circuit, off-chip functions, such as three-state buffers, a FIFO-buffer
memory, and a configuration register must be added. This is because the logic array can't
efficiently implement such functions on chip.

lei) and COM (serial) ports on the PC
side, making it possible for existing
applications that drive those ports to
use the printer control card as well.
One avenue to make the printer interface logic flexible enough to support various output devices while occupying a minimal amount of board
space is by incorporating the 1800gate Xilinx XC2018 logic cell array
(LCA) chip. The chip offers enough
gates and in-system malleability to
make the logic flexible. The user-programmable aspect of the LCA also
minimizes design risk and reduces
the design cycle turnaround time. In
addition, because each configuration
program is independent of the others, each printer can be supported
with a separate, optimal interface. In
fact, with the on-the-fly reconfigurability ofthe LCA, two different printers-one monochrome and one color-could be supported simultaneously in near real time without duplicating much circuitry. The correct
configuration program for each
printer is downloaded to the LCA as
that printer is accessed.
In addition to the actual printer interface implemented in the LCA
chip, several other components are
needed to flesh out the support (Fig.
2). The largest component, a 512word-by-9-bit first-iri/first-out memory, buffers the data stream between the CPU and the printer. Each
entry in the FIFO buffer includes 8
bits of data; the ninth bit marks special conditions, such as end-of-Iine
(BOL).

The 68020 CPU writes data into
the FIFO buffer in bursts to minimize the time its spends dealing with
data-output operations. The LCA
reads the data from the buffer, performs any formatting required by
the particular type of printer being
used, and sends the data to the printer. As a result, the CPU can perform

other tasks while the printer receives the data at its own pace.
Signal buffers external to the LCA
are used to isolate the LCA from the
output connectors, as well as give additional drive capability and electrostatic protection for the CMOS chip.
The output signals are buffered with
dual byte-wide transparent latches.
Typically, only one byte-wide set of
latches will be transparent at one
time; the other will be left holding a
value that drives its attached printer
to a quiescent state.
Also external to the LCA chip is a
configuration register. It controls
the downloading of configuration
programs into the LCA. Directly accessible by the 68020 processor, this
register is built with two devices: an
octal flip-flop to drive signals to the
LCA and a three-state buffer to send
signals back to the processor.
The configuration process involves only three signals. The LCA's
Done/Program input is driven low to
initiate an LCA configuration cycle.

Oatafroml-'f--------,
FIFO buffer

1 - - - - - - - Oalalo P11aserCP
FIFO·buffer
readclock --,....~L-;:===:;==i-=------

t-......-....::.:='-------- ClockloPhaserCP
24.23 MHz

400 Hzl----+-i>

1

3. TO IMPLEMENT THE SERIAL interface required for a Phaser CP printer,
blocks such as a parallel-to-serial shift register; various divide chains; a simple state
machine composed of four flip-flops; and control, status, and interrupt registers must be
configured in the LCA.

7-4

E:XIUNX

FLEXIBLE PRINTER
CONTROLLER
The configuration program is then
downloaded to the LCA as a serial bit
stream using one clock and one data
line. The LCA drives the Done/Program line back to the high state to
signal the end of the configuration
process. Downloading a configuration program takes less than 60 ms.
When two printers are connected
to the card, selection of the correct
configuration program is controlled
by the processor; when a printer is to
be accessed, the LCA is configured
for that particular interface. If two
different printers are connected, the
LCA is reconfigured frequently during idle (non-printing) periods to
check each printer's status.
In general, the operation of the
configured LCA chip is similar for all
printer types. The CPU writes data
to the FIFO buffer, and a state machine created in the LCA reads the
data from the buffer and sends it to
the printer. Any necessary data formatting is performed in the LCA.
For example, data bytes are convert-

l

Dataiftput------,
from FIFO buffer
+
Inpullatch

ed to a serial data stream for the
Phaser CP printer.
Logic in the LCA generates all of
the required handshaking and timing signals. CPU interrupts are generated as needed, based on the status
of the printers, FIFO buffer, and the
LCA's internal state machine. Control and status registers that can be
accessed by the CPU also are implemented in the LCA.
To show how the LCA can be configured for various printers, three
specific configurations that each use
about 2/3 of the 74 user-programmable I/O pins in the LCA must be examined. The first configuration
looks at the interface to the Phaser
CP, a 300-dpi wax-transfer color
printer with a serial interface; the
second examines a parallel interface
to the 4693D/DX color printer; and
the third shows a raw video interface
to a bare-bones laser printer.
To control a serial-input printer,
such as the Phaser CP, part of the
LCA must implement a parallel-in I

I

J
'---'f==~--'

ICMYB·to·RGB converter I
From processor

I

~ "'",,-If.----,

l

~

Printer command
register

Eight2:1 multiplexers

11-----..
Data to

24.23 MHz

Clock divider

I

---l
To processor

1

~;==;=:::;;::=;tT- 4693D/DX
Statemachineand3·bit
I
counter
r-- Data strobe

r-r-

l~--+i

----+---+1-1
---l

Chip control registers

1
External control
signals

Status register
Inlerruptregisters

. - - - - _ Status from
4693D/DX

4. FOR APARALLEL INTERFACE to talk to the 4693D/DX printer, the LeA

musl be configured 10 supply an input latch, a cyan-magenla·yellow·black to red-green-blue
converter, several signal multiplexers, a simple clock divider and state machine, and various
control, status, and interrupt registers.

7-5

serial-out shift register that converts the byte-wide data from the
FIFO buffer to a serial format. The
remaining logic configured in the
LCA includes a clock divider to control the shift register, a divider to
generate the data clock to the printer, a clock divider and state machine
to generate the horizontal synchronization (Hsync) signal, and the processor interface and interrupt registers (Fig. 3). All of that logic employs
78 of the 100 logic blocks available in
theXC2018.
The data-clock generator divides
the 24.23-MHz board clock by 10 to
create the 50%-duty-cycle 2.4-MHz
clock that sends the serial data
stream to the printer. This data clock
is further divided by 8 to control the
shift register. On every eighth data
clock, the next byte in the FIFO buffer is loaded into the shift register.
A small state machine composed
of four flip-flops generates the
Hsync signal and enables clocks and
data to be sent to the printer. After
being enabled by the CPU, the state
machine waits for a 400-Hz signal
from the bus interface chip. A 12.5kHz clock is used to sequence the
state machine, which generates an 8
J.Ls Hsync pulse, followed by an 8 J.LS
delay. Then the state machine can
start the data stream. The data stops
when the EOL flag (the ninth bit in
the FIFO memory word) is read from
the FIFO buffer.
With six 8-bit processor interface
registers, the CPU can write control
information and read status information. These registers are mapped
into the CPU's I/O address space;
four are write-only and two are readonly (see the table). The three interrupt registers share the same bit assignments; bits 4 and 5 of the chipcontrol register control the transparent latches for the two printer
connectors.
Because both connectors are driven by the same pins of the LCA device, these bits force one connector's
outputs to a static state (by disabling
the transparent latch) while talking
to the other printer. Bit 7 of the printer control register is toggled to control a serial-status-readback state
machine in the printer. Using this

II

Article Reprints

FLEXIBLE PRINTER
CONTROLLER
control, 16 bits of status information,
identifying such conditions as paper
jams, out-of-paper, and out-of-ribbon, can be read back one at a time
through bit 2 of the printer status
register.
The parallel interface of the
4693D/DX printer requires 79 of the
LCA's logic blocks. To implement
that interface, the main functional
blocks that must be configured in the
LCA include an input-data register, a
data converter, a state machine to
control the data transfer between
the LCA and the printer, and the processor interface and interrupt registers (Fig. 4).
An 8-bit register is used to latch
the data as it comes in from the FIFO
buffer. The ninth bit, which indicates
the EOL condition, goes to the state
machine and interrupt registers. Optionally, the data can be converted
from the cyan-magenta-yellow-black
(CMYB) format generated by the
controller card to the red-green-blue
(RGB) format (some early versions
of the 4693D/DX printer accept only
the RGB format). This straightforward conversion requires only com-

binatoriallogic.
A simple six-state state machine
combined with a 3-bit counter controls the data flow and commands to
the printer. The 24.23-MHz clock is
divided to supply a clock of approximately 5 MHz to the state machine.
The state machine sends data to the
printer by reading it from the FIFO
buffer, then stores it in the input register, converts it to the RGB format
(if required, as determined by a bit in
the chip control register), and asserts the Data Strobe signal.
Data is sent in a streaming modethe machine will keep sending data
to the printer until a byte marked
with an EOL indicator is read from
the FIFO buffer. The transfer of a
command byte to the printer is triggered by loading the printer-command register and setting a bit in the
chip-control register. The state machine controls the command sent to
the printer and waits for the acknowledgement.
The six 8-bit processor interface
registers are similar in function to
those described for the Phaser CP
printer. The chip-control register in-

Data from
AFDbuffer
FIFDbuffer ___
read clock r--4>r---::-:--:-:--~' T
I L... Divide by 8 f--J

=====---''1I--1>_LP.:::ar.:::al::::lel.::.to-:.:se:ri:::al.::Sh=ift~reg:i:::ste::.rJ

24.23MHz-Iher stale outputs as well .. four of the five
condition signals (A -D).
DESIGN

7-9

many-input logic function in one level of logic, an FPGA might require
multiple logic layers due to the limited number of inputs.
The OHE scheme is named so because only one state flip-flop is asserted, or "hot," at a time. Using the
one-hot-encoding method for FPGAs
was originally conceived by HighGate Design-a Saratoga, Calif.based consulting firm specializing in
FPGA designs.
The OHE state machine's basic
structure is simple-first assign an
individual flip-flop to each state, and
then permit only one state to be active at any time. A state machine
with 16 states would require 16 flipflops using the OHE approach; a
highly encoded state machine would
need just 4 flip-flops. At first glance,
OHE may seem counter-intuitive.
For designers accustomed to using
PLDs, more flip-flops typically indicates either using a larger PLD or
even multiple devices.
In an FPGA, however, OHE yields
a state machine that generally requires fewer resources and has higher performance than a binary-encoded implementation. OHE has definite advantages for FPGA designs
because it exploits the strengths of
the FPGA architecture. It usually requires two or less levels of logic between clock edges than binary encoding. That translates into faster
operation. Logic circuits are also
simplified because OHE removes
much of the state-decoding logic-a
one-hot-encoded state machine is already fully decoded.
OHE requires only one input to decode a state, making the next-state
logic simple and well-suited to the
limited fan-in architecture of
FPGAs. In addition, the resulting
collection of flip-flops is similar to a
shift-register-Iike structure, which
can placed and routed efficiently inside an FPGA device. The speed of an
OHE state machine remains fairly
constant even as the number of
states grows. In contrast, a highly
encoded state machine's performance drops as the states grow because of the wider and deeper decoding logic that's required.
To build the next-state logic for

II

Article Reprints

Iliti@"jij4illf,jiu!$j

STATE MACHINE
DESIGN
OHE state machines is simple, lending itself to a "cookbook" approach.
At first glance, designers familiar
with PAL-type devices may be concerned by the number of potential illegal states due to the sparse state
encoding. This issue, to be discussed
later, can be solved easily.
A typical, simple state machine
might contain seven distinct states
that can be described with the commonly used circle-and-arc bubble diagrams (Fig. 1). The label above the
line in each "bubble" is the state's
name, the labels below the line are
the outputs asserted while the state
is active. In the example, there are
seven states labeled State 1-7. The
"arcs" that feed back into the same
state are the default paths. These
will be true only if no other conditional paths are true.
Each conditional path is labeled
with the appropriate logical condition that must exist before moving to
the next state. All of the logic inputs
are labeled as variables A through E.
The outputs from the state machine
are called Single, Multi, and Contig.
For this example, State 1, which
must be asserted at power·on, has a
doubly-inverted flip-flop structure
(shaded region ofFig. 2).
The state machine in the example
was built twice, once using OHE and
again with the highly encoded approach employed in most PAL designs. A Xilinx XC3020-100 2000-gate
FPGA was the target for both implementations. Though the OHE circuit
required slightly more logic than the
highly·encoded state machine, the
one-hot state machine operated 1770

State 2
State 1

Stale 3

State 2

RD

1

4. ONLY AFEW GATES are required by States 2 aud 3 to form simple statetransition logie deeoding. Just two gates are needed by State 2 (top), while four simple gates
are used by State 3 (bottom).

faster (see the table). Intuitively, the
one-hot method might seem to employ many more logic blocks than the
highly encoded approach. But the
highly encoded state machine needs
more combinatorial logic to decode
the encoded state values.
The OHE approach produces a
state machine with a shift-register
structure that almost always outperforms a highly encoded state machine in FPGAs. The one-state design had only two layers of logic between flip-flops, while the highly en·

1

5. LOOKING NEARLY THE SAME as a simple shift rePter. thelogie for
States 5. 6. arul7 is very simple. This is beeause the OHE ..heme eliminates almost all
deeoding logie that preeedes each flip-flop.
DESIGN

7-10

coded design had three. For other
applications, the results can be far
more dramatic. In many cases, the
one-hot method yields a state machine with one layer of logic between
clock edges. With one layer of logic,
a one-hot state machine can operate
at 50 to 60 MHz.
The initial or power-on condition in
a state machine must be examined
carefully. At power-on, a state machine should always enter an initial,
known state. For the Xilinx FPGA
family, all flip-flops are reset at power-on automatically. To assert an initial state at power-on, the output
from the initial-state flip-flop is inverted. To maintain logical consistency, the input to flip-flop also is inverted.
All other states use a standard, Dtype flip-flop with an asynchronous
reset input. The purpose of the asynchronous reset input will be discussed later when illegal states are
covered.
Once the start-up conditions are
set up, the next-state transition logic
can be configured. To do that, first
examine an individual state. Then

STATE MACHINE
DESIGN
leading away from State 4 is
count the number of condivalid whenever the product,
tional paths leading into the
Contig
Slate 2
A"B"C, is true. Consequentstate and add an extra path
ly, State 4 must be ANDed
if the default condition is to
State 7
with the inverse of the prodremlun in the same state.
E
uct, A' B 0 C. In other words,
Second, build an OR-gate
"keep loading the flip-flop
with the number of inputs
with a high until a valid
equal to the number of contransfer to the next state 0cditional paths that were decurs." The default path logtermined in the first step.
6. 8-R FLIP-FLOPS OFFER ANOTHER .
ic uses AND-7 and shares
Third, for· each input of
approach 10 deeoding the ConIig output. They .... also save
the output of AND-6.
the OR-gate, build an ANDlogie bioek.. especially when an output is 8sserIed for along
Configuring the logic to
gate of the previous state •
'sequenee of eontiguona slates.
ha.ndle the remaining states
and its conditional logic. Finally, if the default should remain in logic to perform this function is im- is very simple. State 2, for example,
the same state, build an AND-gate of piemEmted in the gate labeled AND.::! has only One conditional path, which
the present state and the inverse of and thEllogic elements that feed into comes from State 1 whenever the
all possible conditional paths' leav- the inverting input of AND-3 (Fig. 2, product A "B*Cis true. However, the
state machine will immediately
again).
ing the present state.
State4 is the most complex state in branch in one of two wars from State
To determine the number of conditional paths feeding.13tate 1; examine the state-ma,chine example. Howev- 2, depending on the value of D.
the state diagram-State 1 has one er, creating the logic for its next- There's no default logic to remain ill
path from State 7 whenever the vari- state control follows the same basic State 2 (Fig. 4. top). state 3, like
able E is true. Another path is the method as described earlier. To be- States 1 and 4, has a default state,
default condition, which stays in gin with, state 4 isn'tthe initial state, and combines the A, D, State 2, lind
State 1. As a result, there are two so.it uses a normal D-type flip-flop State-3 feedback to control the flipconditional paths feeding State 1. without the inverters. It 'does, how- flop's D input (Fig. 4. bottom).
Next, build a 2-input OR-gate:--Qne ever, have an asynchronous reset inState 5 feeds State 6 unconditioninput for the conditional path from put,three paths into the state, and a ally. 'Note that the state machine
State 7, the other for the default path aefault condition that stays in State waits until variableE is low in State 6
to stay in State 1 (shown as OR-1 in 4. Therefore, a four-input OR-gate before proceeding to State 7. Again,
while in State 7, the state machine
Fig. 2).
feeds the flip-flop (OR-1 in Fig. 3).
The next step is to build the condi-.
The first conditional path comes waits for variable"E to return to true
tional logic feeding the OR-gate. from State 3. FoJlowingthe methods before moving to State 1 (Fig. 5).
Each input into the OR-gate is the established earlieI', an AND of State
logical AND of the previous state 3 and the conditional logic, which is A OUTPUT DEFINITImS
After defining all of the state tranand its conditional logic feeding into ORed with D, must be implemented
State 1. State 7, for example, feeds (AND-2 and OR-3 in Fig. 3). The sitioh logic, the next step is tQ define
State 1 whenever E is true and is im- next conditional path is from State 2, the output logic. The three output
plemented using the gate called which requires an AND of State 2 sighals-Single, Multi, and ContigAND-2 (Fig. 2, again). The second in- and variable D (AND-I, in Fig. 3). each fall into one of three primary
put into the OR-gate is the default Las~ly, the final conditional path output types:
transition that's to remain inState 1. leading into State 4 is from State 1.
1. Outputs asserted during one
In other words, if thEl current state is Again, the State-I output must be state, which is the simplest case. The
State 1, and no conditional paths ANDed with its conditional path'log: QutputsignalSingle, asserted only
leaving State 1 are valid, then the ic-the logical product, A"B'C during State 6, is an example.
state machine should retp.ain.in State (AND·5 andAND-6 in Fig_ 3).
2. Outputs asserted during multi1. Note in the state diagram that two
No\,\?, all that must be .
UNIT'UNDER TEST

(ROM)
CONFIGURATION
FILE #1

II
CONFIGURATION
FILE #2

I
•••

I

CONFIGURATION
FILE #7

MICROPROCESSOR BOARD TESTER
1953 06

Figure 4. In Innovage Microsystem's microprocessor board tester, an LeA is configured forthe appropriate
microprocessor type and selected diagnostic test

7-28

By reconfiguring a 3000-gate XC3030 LCA, an errorcorrection channel designed by Wiltron Co. (Morgan Hill,
CAl can support either of two error checking and correction (ECC) formats, one for Digital Data System (DDS) and
one for Adaptive Data Port (ADP) network configurations.
The circuit is incorporated into several products, including
Wiltron's Model 9966 Digital Services Test Unit for testing
DDS-like services. Use of the LCA also provides insurance
against evolving standards; new LCA configuration programs can be developed if standards for ECC formats and
network configurations change.

when writing data to the tape, and then reprogrammed to
perform a different function when reading from the tape.
Honeywell's Test Instruments Division (Denver, CO) incorporated this scheme in their VLDS (Very Large Data
Storage) recorder. s An XC2064 LCA is configured to perform error code generation in write mode, and then
reconfigured to perform error code checking and correction in read mode. This type of application is especially
cost-effective; about twice the logic would be required to
implement the same functions with traditional logic devices.
A similar strategy can be used in the design of most logic
analyzers, microprocessor in-circuit emulators, and similar test equipment. Each involves the monitoring and
control of nodes within the system being tested. In the
"acquisition mode", the target system is active and a
record of the target's activity is stored in a memory buffer
called trace memory. Trigger and breakpoint logic specifies when tracing begins and ends. A history of the system's operation can then be read from trace memory and
displayed to the user, the "analysis mode". In an LCAbased system, programmable gate arrays could be used
to implement the multiplexer, registers, and comparators
of the trigger and breakpoint logic, interface to the system
undertest, and control the writes to the trace memory while
in acquisition mode. Those same LCAs could bereconfig-

DUAL-PURPOSE HARDWARE
In the examples sited above, programmable gate arrays
are reconfigured to implement internal system diagnostics, adapt a circuit to the external environment, or completely change the· functions of a system. Some logic
designers have taken this concept one step furtherprogrammable gate arrays are reconfigured as part of the
normal operation of the system.
For example, at any given time, a tape recorder can either
read or write, but it never does both simultaneously.
Consequently, a programmable gate array within a digital
tape recorder could be configured to perform one function

ADDRESS

."
y

DATA

"

DATA

y

SYSTEM
UNDER
TEST

INPUT
CAPTURE
lOGIC

...
"

TRIGGER
AND
BREAKPOINT
LOGIC

CONTROL

MEMORY
ADDRESS
GENERATION
+
CONTROL

CONTROL

...
"

PGA

CONTROL

l\.

TRACE
MEMORY

"-

"-

CONTROLLER

y

ACQUISITION MODE
ADDRESS"
y

DATA

"

...

y

USER
INTERFACE
CONTROL

SYSTEM
UNDER
TEST

...

PGA

MEMORY
ADDRESS
GENERATION

TRACE
MEMORY

"
CONTROL"

+

CONTROL

CONTROL

"

.II

"
19S3 07

DATA

CONTROL l\.
CONTROLLER
y

ANALYSIS MODE

Figure 5. An LeA can be reconfigured to support both acquisition mode and analysis mode operations in a logic analyzer.

7-29

II

Taking Advantage of Reconfigurable Logic

RECONFIGURABLE LOGIC EASES DESIGN

ured to control reading trace memory and displaying its
contents when in the analysis mode (Figure 5). For example, Data 110's MESA-1, an in-circuit verifier for LCA
designs, uses LCAs exclusively to implement its logic
(Figure 6).

While not every system requires reconfigurable logic to
implement its digital functions, the design-related benefits
of static-memory-based programmable logic apply to all
deSigns. The ability to reconfigure programmable gate
arrays resident in the target system significantly eases the
debugging process, reducing overall development time
and shortening the product's time-to-market. A download
cable provided with the basic development system allows
configuration programs to be downloaded directly from a
PC to an LCA device resident in the target system; the
actual download operation requires less than 100 milliseconds. Thus, the designer can immediately check the
results of design changes in the target system. Often,
deSign changes can be implemented and tested in just a
few minutes time.

Intel's Development Tools Operation (Hillsboro, OR) used
a slightly different tactic when designing a series of incircuit emulators for derivatives of the 80386 processor.
The emulators contain six LCAs. Four of them comprise
the bus event recognition circuitry used to define and
detect triggers and breakpoints; three of these are largely
filled with comparators, and the fourth holds the breakpoint
state machine. When preparing for an emulation, these
four LCAs can be reconfigured in the system,dependent
on the type of breakpoints and triggers being specified. A
DMA channel is used to download the LCA configuration
programs. A fifth LCA holds the bus interface state machines; as a future product upgrade, Intel designers may
generate another optional configuration program for that
LCA to add additional tracing capabilities.

In essence, Xilinx programmable gate arrays provide a
flexible means of "breadboarding" logiC designs, as well as
a cost-effective means of implementing the logic in the
final product. Temporary modifications to the logic, such
as routing an internal node to an otherwise unused I/O pad,
can be quickly implemented for debugging purposes and
then removed from the production design. Devices are
reusable simply by downloading a new configuration.
There is no lengthy wait for a custom device to be manufactured, and no waste of components as with one-time-

THE ULTIMATE RECONFIGURABLE SYSTEM
A system composed entirely of programmable gate arrays
could be configured to implement any given logic functions. This concept has been incorporated into a new ASIC
design tool that provides real-time in-circuit emulation of
complex ASIC designs. The RPM Emulation System, from
QuickturnSystems Inc. (MountainView,CA), isaworkstation-based design verification tool that combines automatic ASIC netlist conversion software with emulation
hardware based on 9000-gate XC3090 LCAs (See
Figure 6). The RPM Emulation System can be configured
with up to four emulation modules with over thirty XC3090
LCAs each, allowing emulation of ASIC designs of up to
100,000 gates. Once the ASIC design is converted for
emulation, existing complex VLSI devices may be
internally connected to the emulation logic with
Component Adapter boards, orthe design may be plugged
into a target system with an In-Circuit Interface consisting
of cables, an active Pod, and ASIC Plug Adapters. The
netlist conversion software reads the netlist (a variety of
popu lar formats and libraries are supported), partitions the
design for programming each XC3090 LCA, places and
routes the design into the matrix of XC3090 LCAs, and
checks the timing to determine the maximum speed of
correct functional operation. The Control Panel user
interface on the workstation guides the designer through
the emulation set-up and provides the controls for the
integral Logic Analyzer and Stimulus Generator, allowing
quick access to any node in .the design during debugging.
Thus, using the RPM Emulation System, a designer can
emulate and debug the logiC operation of any large digital
design before committing to a custom implementation.

Figure 6. The internal logic of Data I/O's MESA-1 in-circuit
debugger is implemented entirely in Xilinx programmable
gate arrays.

7-30

~XIUNX
programmable solutions; there is not even the inconvenience of long erase times using ultraviolet lights, as with
EPROM-based logic. The designer receives nearly instantaneous feedback on the effects of design modifications.
Furthermore, since the LCA's configuration can be verified
in the target system, extensive simulation is not required;
typically, simulation is used only for critical timing path
analysis under worst-case conditions.

Buffalo Products' design of the More Memory board mentioned above. During testing of the board using various
manufacturers' PC clones, problems caused by incompatibilities in some PC models were corrected as they
were found through reconfiguration of the LCA device.

The ability to implement easily modifications to the logic
enables and encourages experimentation during the design cycle, resuHing in beUer designs. For example, the
use of Xilinx LCAs allowed GTECH Corp. to evaluate
different image sensors during the design of a bet-slip
readerforthe lottery industry" Since there are no standard
architectures or interfaces for image sensors, different
interface logic was required for each sensor type. By
incorporating the sensor interface logic in LCAs, a single
hardware implementation could be reconfigured fOJ each
sensor type, allowing the sensitivity and resolution of each
to be measured under identical conditions.

Similarly, field upgrades can be easily implemented
through changes to LCA configuration programs.
Andromeda Systems (Canoga Park, CAl took full
advantage ofthis capability in their Storage Module Device
Controller, a disk controller for LSI-11 and MicrolVAX
systems. 8 The configuration programs for three XC2064
devices are stored in EEPROM that can be altered using
a service port that connects directly to terminals or
modems. The interfaces to the disk, processor bus,
service port, and cache memory are implemented in the
LCAs (Figure 7). Modifications to the logic, such as
adjusting the caching algorithm to match the requirements
of a particular application, can be made without removing
the disk controller from the system; new LCA configuration
programs can be sent to the controller using a modem.

The flexibility of in-circuit reconfiguration greatly reduces
design risks. The inevitable last-minute bug fixes and
specification changes can be implemented by changing
an LCA's configuration program rather than altering the
hardware. MIA-Com Telecommunications (Germantown,
MD), for example, was able to correct an error in the PCB
layout without changing the board by reconfiguring an LCA
used to implement the channel interface logic within a
satellite earthstation. 7 ThiS flexibility proved critical during

FIELD UPGRADES SIMPLIFIED

In many cases, compatible programmable gate arrays
with a range of densities are available in identical packages. (For example, the 2000-gate XC3020, 3000-gate
XC3030, and 4200-gate XC3042 are all available in 84-pin
PLCC and PGA packages.) So if logic needs exceed the
current LCAdevice, during either initial design ora product

PERIPHERAL
EXPANSION
PORT

CACHE MEMORY
1M BYTE DRAM

DISK
CONTROLLER

CACHE
ADDRESS
MAPPER
Q·BUS
INTERFACE

SMD
INTERFACE

65C802 MIC;ROPRClCESSClR
STATIC
RAM

EEPROM

1953 08

Figure 7. In Andromeda Systems' SMDC disk controller, LCA configurations can be
downloaded to EEPROM through a modem port for easy field upgrades.

7-31

USER
SERVICE
PORT

Taking Advantage of Reconfigurable Logic

SUMMARY

upgrade (due to the addition of new product features, for
example), a higher-density device can be placed in the
same PCB location, with no modifications required to the
circuit board.

The advent of programmable logic that can be reconfigured while resident in a system has freed the designer from
the "hard" nature of traditional logic ICs. With programmable gate arrays, adaptable systems that adjust to
changing environments or varying tasks can be created,
and hardware design is simplified. New system architectures that take advantage of reconfigurable logic will
continue to emerge as programmable gate array densities
and performance levels continue to increase.

The reconfigurable nature of the programmable gate array
also allows for the design of its own in-circuit debugging
tools, such as Xilinx's XACTOR and Data 110's MESA-1
(Figure 8).9 Similar in many ways to microprocessor incircuit emulators, these sophisticated verification tools
provide for easy, fast debugging and testing. Since configuration programs can be downloaded into an LCA at will,
LCA devices in the target system can be replaced or
functionally duplicated by an LCA device in an in-circuit
debugger; LCA activity can then be controlled and monitored by the user.

REFERENCES

1. Loring Wirbel, ''Tek Takes Color Printer to the Office,"
Electronic Engineering Times, Nov. 14, 1988.
2. David Smith, "User-Programmable Chips Take on a
Broader Range of Applications," VLSI Systems DeSign,
July, 1988.

3. Rusty Woodbury, "LCA Stars in Video," ESD: The
Electronic System Design Magazine, Feb., 1987.
4. Cliff Dutton, "Programmable Logic Betters the Odds for
Bet-Slip Readers," ESD: The Electronic System Design
Magazine, Oct., 1987.
5. Tom Liehe, "Two, Two, Two Chips in One," Electronic
Engineering Times, Nov. 17, 1986.
6. Loring Wirbel, "Quickturn Offers ASIC Emulator,"
Electronic Engineering Times, Nov. 14, 1988.
7. Dave Farrow, "USing Programmable Logic Cell Arrays
in a Satellite Earthstation," VLSI Systems DeSign, April,
1987.
8. Jim Reynolds, "Building Tomorrow's Disk Controller
Today," Electronic Products, Dec. 15, 1987.
9. John Novellino, "Development Tool Trouble-Shoots
PGAs in the Target System," Electronic DeSign, Jan. 26,

Figure 8. The reconfigurability of LeAs allows lor the design
of their own in-circuit verification tools, such as the MESA-l
from Data 110.

1989.

7-32

.'"''''.'''''''''''''''''"./1.'''''

ESD:

Faster Turnaround
for a T1 Interface

THE Electronic System Desigfl Magazine

by Carl Erite, Teltrend Inc., S!. Charles, IL

design requirements-high integration, high density, high
performance, low cost, low risk and quick time-to-market.

Important design considerations for an interface system to
a digital T1 network (which carries voice, data, video and
fax traffic at rates up to 56 Kbytes/sec) include conserving
board space, improving throughput and reducing power
consumption. The user interface is achieved via a conventional four-wire loop providing independent transmit and
receive capabilities. In designs that Teletrend Inc. initially
considered for a single-user T1 interface, 5000 gates of
conventional SSIIMSI glue logic were to be integrated
using two custom gate arrays. However, a short development cycle and low market risks were also desired. This
led to a search for an alternative to th time-consuming
process of casting two gate arrays.

The Xilinx devices implement a digital phase-locked loop,
as well as the T1 transmitter and receiver. A Hitachi
microprocessor provides overall intelligence to handle T1
controls, network code manipulation and other tasks.
The dual digital phase-lock loop provides the key function
of the system. Data on the user interface is encoded with
the clock signals, a process that may occur at various
send/receive data rates. Data extraction from the user
interface must be phase-locked and, at the same time,
data must by synchronized with the T1 network clock. A
Xilinx LCA implements the phase-locked loop that synchronizes both the interface and the T1 network.

Upon completing the initial circuit design, a breadboard
was built using CMOS SSI/MSI logic components. After
the breadboard was working, integration path decisions
were needed. Instead of hard-Iooling two custom gate
arrays, designers determined that three standard, programmable Xilinx Logic Cell Arrays (LCAs) met all of the

The second LCA transmits data onto the T1 network.
Here, data transmits serially at 1.544 Mbits/sec in one of
the 24 assigned time slots. A unique data word to be

RECEIVE DATA AT BAUD RATES FROM
1.2K TO 56K ARE PHASE-LOCKED TO
THE RECOVERED BAUD RATE CLOCK
AND TO THE T1 NETWORK CLOCK.
RECEIVE DATA

STANDARD 4 WIRE
USER INTERFACE
FOR SUBSCRIBER
LOOP SERVICE

T1
TRANSMITTER

TRANSMIT
DATA
AT 1.544
MBITS/SEC

r---I
I
I
I
I
I
I

DUAL PHASED·
LOCKED
LOOP
FOR
RECEIVER
T1 NETWORK CLOCK

------LOGIC TO
TRANSMIT
TOUSER

TRANSMIT DATA

CONTROL
MICROPROCESSOR

T1 RECEIVER
WITH8·BIT
CRCERROR
CORRECTION

I---

RECEIVE
DATA
AT 1.544
MBITs/SEC
I
I

L ___ _
T1 SWITCH
WITH ONE
ASSIGNED
TIME SLOT

114812

Figure 7. Teltrend's digital TI interface is built around three user-programmable Xilinx Logic Cell Arrays in lieu of two conventional
gate arrays. One LCA implements a dual digital phase-lock loop around four-wire loop; other LCAs form both the transmitter and
reciever logic circuits, including error correction.

7-33

III

Article Reprints

transmitted is held in the LCA while logic synchronization
determines the start of the first time slot or the beginning
of the data frame. The assigned time slot is found by
counting time slots from the start of a complete frame.
After locating the assigned time slot, data is transmitted
onto the T1 network.

higher performance in critical timing paths and higher
overall device utilization. In all three designs, LCA logic
resource utilization exceeded 95%.
All three designs are flip-flop intensive, involving multiple
counters, shifters, registers and other memory-oriented
functions. The LCAs provide more flip-flops per device
than any other programmable logic alternative. Only a few
simple a-bit registers were implemented externally with
octal devices. Next-generation designs will use Xilinx's
compatible higher density devices to achieve greater logic
density in the same socket.

A third LCA, complementary to the transmitter function,
receives data. It also furnishes complete error correction
for incoming data. Time-slot detection logic determines
the start of data for the assigned channel. Serial data
comes from the T1 network. After the LCA performs 8-bit
error correction, the data passes to the processor and user
interface.

Overall, the ability to enter the original design using the
Xilinx LCA XACT design system ensured that all the
integrated logic functioned as desired before the part was
placed in the system. With a conventional gate array, the
design might still be waiting for silicon, since turnaround
times for production quantity gate arrays typically range
from a to 16 weeks (production quantities).

The first iteration of the design was extracted directly form
the CMOS breadboard schematics using the Xilinx XACT
system running on an IBM PCI AT. The working design for
the first device was completed in two weeks, with some
time-critical elements moved off the Chip. Designs for the
second and third parts took about the same time, but
additional interaction during the design process resulted in

Reprinted with permission from ESD: The Electronic Sys-

tem Design Magazine.

7-34

Using Programmable Logic
Cell Arrays In a Satellite
Earthstation
Dave Farrow, MIA-Com Telecommunications, Germantown, MD

Conventional programmable logic devices (PLDs) include
several interesting variations of latch-based AND-OR
plane architectures in various technologies, all of which
are useful for low-gate-density applications. Typically, a
PLD can replace five to ten SSIIMSI parts.

3 Mbls transmission rate. The earthstation product, called
an OPT (for On-Premises Terminal) is a "small-aperture"
satellite earthstation, permitting efficient employment in a
large number of remote locations, as illustrated in
Figure 1.

A newer digital logic technology with an array architecture
and flexible interconnection offers the programming flexibility of PLDs plus the gate density of low-end gate arrays.
Architecturally, these devices have some similarities to
gate arrays: they contain an internal matrix of logic blocks
and a ring of configurable 110 interface blocks. Unlike
conventional gate arrays, each part is a standard off-theshelf unit that can be programmed by the user. The
configuration program is automatically loaded into an onchip static memory at power-up from either an on-board
EPROM or an external source such as a floppy disk.

Two main components comprise the OPT: an indoor unit
and an outdoor u nit. The outdoor unit includes the antenna
and associated radio-frequency equipment.
At the outset of the design process, the indoor unit was
intended to be contained in a small chassis that could
support three standard-size boards. The boards originally
planned for the system included one board each for
controlling data traffic, transmit functions, receive functions, and demodulation. However, the chassis provided
space for only three boards.
Project goals included the use of an existing proprietary
custom chip design from a previous application. MIA-Com
also investigated whether the design could be fit on only
two boards, by using a gate array. Board design itself was
driven by three primary factors: resource availability, cost,
and schedule. Since reducing the number of required
boards would reduce design time and keep product costs
lower, MIA-Com decided to go with the gate array.

THE EARTHSTATION SYSTEM

MIA-Com recently employed one of these "programmable
gate arrays" in the design of a satellite earthstation, intended to network commercial facsimile operations. The
network handles traffic at 56 kbls, multiplexed into 26
channels and convolutionally encoded, yielding an overall

III
EACH ON·PREMISES
TERMINAL HAS ITS OWN
TRANSMIT FREQUENCY

GROUPS OF ON-PREMISES
TERMINALS SHARE A
RECEIVE FREOUENCY

Figure 1. Satellite System

7-35

UP TO 5,000
ON-PREMISES
TERMINALS

HUB

114807

E:XIUNX
QlY.

DESCRIPTION

ITEM

3

8-BIT SHIFT REGISTER

74HCT164

6

4-BIT COUNTERS

74HCT163

4

DUAL D FLIP-FLOP

74HCT74

2

QUAD 2:1 MULTIPLEXER

74HCT157

1

QUADXOR

74HCT66

1

HEX INVERTER

74HCT04

1

QUAD NOR

74HCT02

port controller and handles base-band X.25 data. Due to
the use of semicustom and programmable technology, the
remaining three functions were all merged onto the other
board, which we call a "satellite channel interface" (see
Figure 2).

1148 08

Table 1. Standard Off·the·Shelf Equivalents to the Logic
Contained In the LCA.

We used a gate array for the transmit function, which
otherwise would have required about 70 chips. For the
receive function, we originally planned to use an existing
full-custom ASIC (previously designed by MIA-Com) for
forward error correction, and an additional 25 SSI/MSI
parts for the receive logic. However, due to chassis
constraints, the high density of components would have
necessitated a multi-layer board for the initial design.
Furthermore, based on previous experience, the likelihood of changes in the design specification was too high
to risk a custom or semicustom solution for the initial
design. Therefore, we originally planned to produce the
high-density boards in quantity and to reduce the cost of
the system at a later date, by first transferring the receive
logic into a gate array and then replacing the expensive
high-density four-layer board with a two-layer board.

The completed design employs a full custom IC, a gate
array, and programmable logic, and subsists on only two
boards. On one board, an Intel processor acts as a traffic·

While the design criteria were being prescribed and boardlevel functionality was being determined, we also investigated the newer programmable gate-array technology.
The programmable part, the Xilinx Logic Cell Array (LCA) ,

2

QUAD OR

74HCT32

3

QUAD AND

74HCT08

1

OCTAL LATCH

74HCT374

1

OCTAL BUFFER

74HCT244

25IC8

TRANSMITIER

KEY

ml

LOGIC-cELL ARRAY

o FULL-CUSTOM CHIP

[ ] GATE ARRAY
114809

Figure 2. Block Diagram of Satellite Channel Interface.

7-36

Article Reprints

UNIQUE WORD SENSE

0:

0

I-

:::;;:5

{ ro,

DATA

O:::l

0:0

"-0

:::;;
w

MAG
DATA

0:

{,~

0

0

:::;;6'"

!i15 ffl

"-~~
0..

DATA
DEMUX-SGN DATA

WR
RD

DEMUX-MAG DATA

KEY:

[J
[J

!ill

DEMULTIPLEXER
DESCRAMBLER
DEMUX-CLK

TIME-DIVISION MULTIPLEXER
(SYNCRONIZATION CIRCUITS)

1148 10

Figure 3. A Schematic of the Digital Systems Incorporated into the LeA.

in-circuit emulator for debugging.

is architecturally similarto a gate array and is supported by
a PC/AT-based workstation.

Our original schematic was based on conventional LS and
HCT parts; it included JK Hip-flops and large counters
(implemented by cascading common 4-bit counters),
rather than gate-level elements. Since that method of
design was inefficient for the LCA, we redesigned the
receive circuit at the gate level and then implemented it in
software via the cell array editor.

We determined that the internal organization of the LCA
fitted the design requirements of the receive function.
Specifically, the LCA provides many more flip-flops than
other programmable logic devices, so that one chip contained enough functionality for our needs. Further, the
LCA provided the required density savings, and its reprogrammability obviated the risks associated with late engineering changes. When engineering management was
presented with the design alternatives, we decided to
prototype a reduced portion of the receive circuit and thus
evaluate the reconfigurable chip.

Using an LCA reduced the amount of hardware overhead
normally associated with LKS and HCTtechnology. It was
not necessary to waste control inputs, to cascade counters, or to determine what to do with unused bits of mUltiplexers. In our design, 25 SSI/MSI gate-equivalents did
not even use up all the resources available in one LCA.
Table 1 indicates the parts thatwe actually employed in the
present design. Putting these functions in the LCA resulted in an 88% utilization of the internal cells, and a 60%
utilization of the I/O cells. Thus it still remains feasible to
add further functionality to the system, with no PCB

To implement the design, M/A-Com acquired the Xilinx
XACT PC-based LCA development system. The system
includes a macro library, with some of the required logic
already defined. After several days of experimenting with
the design tools, it took tiS one day to enter and only two
hours to debug the design. We uses Xilinx's XACTOR

7-37

II

E:XIUNX
changes. We plan to do so in the future. Figure 3 is a
schematic of the circuit placed in the LCA. Since the
design is not 1/0 limited, there was no necessity to multiplex any of the input or output lines; but additional logic
could have been added, should 1/0 multiplexing been
needed. Note also that the descrambling circuit can easily .
be reconfigured, or made more complex. Changing the
descrambler can be achieved merely by reprogramming
the LCA.

The fourth state is entered every time a unique word is
missed; the system stays in the fourth state until the unique
word is found or is missed 11 consecutive times. If the
unique word is found, the system returns to state three; if
it is not found after 11 attempts, then the first state (the
search mode) is initiated again. This method of operation
ensures that the demultiplexer will remain locked even in
the presence of random bit errors in the data stream.
After the unique word is detected, the receiver locks onto
thE! data. The LCA chip then de scrambles the data stream.
The data is originally scrambled by the transmitter to place
a fairly equal number of ones and zeros into the transmitted carrier. If this is not done, the transmitted carrier may
not contain an even distribution of spectral components,
which makes it difficult for a demodulator to acquire the
carrier. The descramblingprocess is merely the reverse
of the 9-bit scrambling procedure.

One criticism leveled againstthe LCA is that it requires 12K
bits of storage space to program the part during power-up.
However, in our design, a 27C64 EPROM (used for a lookup table) was already on the board. A portion of this
EPROM was available to store the LCA configuration
program at no additional cost. Since the 12K bits of
storage space are used to program all the RAM cell
locations in the LCA, adding further functionality to the
LCA would not require more storage space.

Asingle channel is isolated from the others by demultiplexing'the descrambled data stream. The demultiplexing
function is performed through a pair of counters that count
the bits between unique words and tell the demultiplexer
when data is available.

ARCHITECTURE
From the OPT, transmission is executed in the SCPC
(single channel per carrier) mode. All scrambling, encoding, and error-code generation are performed by
M/A-Com's proprietary transmit gate array. The gate array
contains registers, allowing it to be programmed to transmit in different schemes and protocols,including SCPC
mode.
'

Once the incoming data stream has been descrambled
and demuHiplexed, it moves on to the MIA-Com proprietary convolutional decoder, a custom chip where error
detection and correction is done on a per-channel basis.
Decoded data is passed on to a microprocessor for data
extraction.

The OPT receives a TOM (time division multiplexed)
bitstream composed of 56 kbls data channels in a modulated 3-MHz carrier. The bitstream contains a UW (unique
word), and data and parity bits for each channel in each
frame. The received carrier is demodulated by analog
circuitry on the SCI, which passes the digital bitstream to
the LCA.

TESTING THE LeA
To testthe TOM synchronizer, the LCA was loaded via the
Xilinx in-circuit emulator and set into the test bed. We
tested with a satellite simulator and found one design
error. Both isolation and remedy of the fault were simple
to perform, due to the reconfigurability of the part. FauH
location was eased by choosing internal test nodes and
connecting them to 110 pads. This technique made it
possible to find the fault very quickly.

To isolate the UW and lock onto the data, the LCAcontains
several counters and a state machine, configured in TOM
synchronizer. The state machine controls he synchroniztion algorithm, which manipulates the frames.

By using a satellite simulator we were able to insert errors
into the datastream. We measured the. time to lose sync
and the time to acquire sync, and determined that the
ripple counter was a little too slowforthe required function.
Since we were using an in-circuit emulator, it was very
easy to reprogram ,the device. After the design was
debugged, we left the simulator on-line for a week to
ensure a thorough test of the Xilinx part under operational
conditions. Our concern was how well the LeA WOuld
retain its configuration, since this information is stored by
RAM cells. However, in our environment, it performed
flawlessly. '

The TOM synchronizer moves between four states (see
Figure 4). The first state entails acquiring "sync" by
recognizing the unique word in the unsynchronized data
stream. Once the unique word is acquired without errors,
the second state occurs. .The circuit verifies' "sync" by
detecting the unique word again one frame later in the
bitstream. Upon second .detection, the circuit is consid,.
ered in sync, and the synchronizer shifts to the third stat~
the sync state---where data are allowed to proceed as long
as the system detects at least one unique word in every 11
frames.

7-38

Article Reprints

UNIQUE WORD
DETECT

UNIQUE WORD
MISS >1

UNIQUE
WORD MISS

UNIQUE
WORD DETECT

UNIQUE
WORD
DETECT
UNIQUE
WORD MISS

UNIQUE
WORD DETECT

114811

Figure 4. State Machine for the Time-division Multiplexer.

Late into the design cycle we began to add additional
planned functions to the LCA. Because we knew we could
add these extra features, we finished the PCB layout and
ordered PC boards without waiting for the final design.
Then the process of adding putting functions into the LCA
was begun.

basic digital circuitry. For example, designers must be
able to recognize the worst-case timing scenarios of their
networks. Delay and system-speed .considerations can
now be checked with the Xilinx simulator, but at the time of
our design, the Simulator was still in beta test; we calculated the circuit behavior with preliminary timing software.
Since then the simulator has been revised and its present
version would have spotted our timing error.

Normally this time would have been used to design a test
fixture. Instead, another LCA design was created to
support a test implementation. Before the PCB was
delivered, the test fixture simulating the system was built,
primarily around the second Xilinx part. In the process of
building the fixture, we discovered an error in the PCB
layout, even before it was delivered. It was possible to fix
the error by reconfiguring the LCA.

Rather than packing complete design into the front end of
an ASIC development, as is required for conventional gate
arrays, the LCA offers the flexibility to indicate roles forthe
part. Designers can specify the 110 pins for the LCA then
send the PC board to fabrication. While the board is in
fabrication, designers can build into the LCA the gate-level
logic they want and continue to make changes up until, and
even after, the PCB is delivered.

When the board was delivered, a new version of our logic
design had been implemented in the Xilinx LCA, including
the demultiplexing and descrambling functions.

After final product delivery, the on-board logic can still be
reconfigured to match specific customer needs-without
having to cast .custom silicon for a few dozen units or
changing the PC artwork. Great NRE savings are passed
back to the customer. In summary, the LCA has proved to
be an extremely effiCient, useful, and cost-effective extension to our semicustom design capabilities.

OPEN-END DEVELOPMENT

CONCLUSIONS
The flexibility of the Xilinx LCA lowers design costs,
reduces project schedule risks, and reduces inventory
risks. Using the LCA does not require much design
sophistication, but rather a good general knowledge of

Reprinted with permission from VLSI System Design.

7-39

II

ESD:

Programmable Logic
Betters the Odds for
Bet-Slip Readers

THE ElectronIC System DesIQl'l Magazine

by Cliff Dutton, GTECH Corp., Providence, RI

In countries throughout the world, the vitality of the on-line
lottery industry is enhanced by seasonal and special
promotional games. But new games require new bet-slips,
and bet-slip readers must be able to accommodate frequent changes in format. To accomplish this, programmable gate arrays are replacing older, less flexible architectures.

the sensor interface. Similar difficulties hindered direct
comparison of achieved resolution. To accurately evaluate these parameters, each sensor had to be designed into
prototype readers. This involved driver and frame acquisition clock signal generation.
Because lotteries have no standard bet-slip size, as many
"standards" as possible need to be accommodated. Thus,
it was necessary to maintain flexibility in the format of the
target image.

In the development of GTECH's Solid State Reader, many
existing technologies were evaluated, but they imposed
unacceptable limitations on bet-slip processing, restricting
bet-slip formats to rows and columns. Moreover, the
process of reading the coupons was dependent on complex moving parts, and the reading elements were exposed to the external environment.

PROTOTYPING A SYSTEM

The implementation of a prototype system had one goal:
to prove the feasibility of recognizing handmade marks in
an imaging system. Because the volume of readers is
potentially high, component costs were a serious issue.

To maximize flexibility and minimize board space, Xilinx's
(San Jose, CAl Logic Cell Array (LCA) was chosen forthe
Solid State Reader. The LCA, touted by the corilpany as
a "programmable gate array," represents a novel programmabie logic device that is notable for its reprogrammable
architecture. This architecture provides flexibility throughout the product's life span, which allows on-line bet-slips to
be produced with marks in any arrangement. Each bet-slip
reader at every terminal can be configured on-line to read
any bet-slip from an active suite of eight different bet-slips.

BOARD 1 MAIN CPU
COMMUNICATIONS
LINK

PROCESSOR
MEMORY
CONTROL LOGIC

BOARD 3

Figure 1 shows three lottery bet-slips. Some of the
pertinent features of the European Lotto game slip (a)
include strobe marks along the top edge, the OCRB-3
characters (bottom center), and the name and address
field (bottom right). In the sample bet-slip from a lottery in
the U.S. (b), there are no OCR characters or name and
address information. However, there is an area from
which handwritten information must be extracted. Apart
from the different features, the aspect ratios of bet-slips
are not standard. Modem bet-slip processing systems
must be able to read all of the different formats in many
aspect ratios. A format that forgoes the usual row and
column arrangement (c) is also depicted.

BOARD 2
CLOCK
GENERATOR
AND DRIVER
CIRCUITS

ANALOG SIGNAL
CONDITIONING
CIRCUITS

BOARD 4
IMAGE SENSOR BOARD

PRECISION OPTICS

As there are no standard architectures or interfaces for
image sensors, GTECH evaluated many image sensor
approaches. However, direct comparison of sensor performance could not be made in the application environment. For example, comparisons of sensor sensitivity at
the pixel level were impossible due to the differences in
sensor-interface electronics. If degraded sensitivities
were evident, they could derive from either the sensor or

Figure 2. The goal of developing a prototype bet-slip processor (shown above) was to prove that handmade marks could
be recognized in an imaging system. Four boards were
initially developed for this modular design: CPU/memory,
clock-driver, analog amplifier, and sensor mounting.

7-40

E:XILINX
First, a working model was developed. To balance development costs, a set of printed circuit boards based on TTL
logic devices was manufactured. Partitioned functionally,
the board set supported modular design changes. Four pc
boards were initially developed: a CPU/memory board, a
clock-driver board, an analog amplifier board, and a sensor mounting board (Figure 2).

1111111

In the initial design, flexibility did not exist. Even though
modularity protected the design from becoming obsolete,
significant design alterations were required to accommodate different sensors. Because sensor clock signals are
multiphase, new clock generators would be needed for
new sensors. Also, bugs were difficult to find,and circuit
board modifications were required to eradicate such bugs.

I l l l l l 111111 111111 111111 111111 111111
1

.,<,

2 ; \';;:',

:>:;''';L

3

;V',,;;>

4

";;,' 5

, <,<,;0'

6

millmmmmmillmmmmm0mmmmmmmmmmm0mmmmm0mmmm
Kupongendeltager
; Savoolagel I Itlljd

anordnadetipSom-

gO....

~~rIOO1mef

.M
2speHatt

mmm~~~mmm~~~mmm~~~mmm~~~mmm~~~mmm~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~§§~~~~§§~~~~§§~.~~§§~~~~§§~~~~§§~
§~§~~~§~§~~~§~§~~~§~§~~~§~~~~~§~~~~~
§~~~~

§~~~~

§

§~~~~

~;":

Insalspe<

spellaR7;SOkl

InlalTll'lingsdag

......./. ...... 19..... .

•

08

8

16

120

330 OM [)J llf'PAR SYSTEM -

18

19

110

L11

DDD D ~==rA~F~T •

[::. : : : IO~~" , : , :

A11"T I I I

::::, I

Vgte.ta

(a)

•

~

m
m

[i][ij[il[3i]

[i][ij[il[3i]

[i][ij[il[3i]

[i]@[2l§

[i][il[2l§

[iJ[ij[il§

[i][ij[il[3i]

[i][il[2l§

[iHHl§

[l][ij§~

[l][ij§§

[l][ill2l[3i]

[i][ij§~

Z

~
~

i

l'HHl §J

[i][i4][il§J

[i][ij[il§J

[i][ij[il§J

[i][i4][il[3i]

11

[i][ij[il[i5]

[i][ij[2l[il

[i][il[2l[i5]

[i][il[2l[i5]

[i][ij[2l[il

<

[i][ij[illil

[i][ij[il[il

[i][ij[illil

[i][il[il[i5]

[i][il[il[il

[i][ij[ij[il

0[ij[ij[il

0[ij[ij1il

0[ij[il1il

0[ij[ij1il

~

[iJ1il[il[i]

[iJ[il[2l[i]

[iJ[il[il[i]

[iJ[il[il[i]

[iJ[ij[il[i]

•

[iJ[il[il[i]

[iJ[il[il[i]

[iJ[il[il[i]

[l][il[il[i]

[i][il[il[3i]

IEl1IJ

IEl1IJ

IEl1IJ

IEl1IJ

IEl1IJ

•• •

~

~

iii
~

(b)

•

II
(c)
Figure 1. Betting slips for lotteries come in varied shapes and sizes. (a) Shown here are lotto slips from Europe
and (b and c) the United States. Such variety in slip design must be accommodated in the developement of bet-slip readers.

7-41

Article Reprints

Semicustom and full-custom technologies would have
solved all the functional problems, but they lack flexibility.
Because the development of the reader was ongoing, the
commitment to custom implementations was out of the
question. In addition, nonrecurring engineering (NRE)
costs were prohibitive and the devices could not be
adapted to changing sensortechnologies or changing betslip reading requirements.

Finally, the target image aspect ratio was fixed because
the clock generation circuits were implemented in hardware.
Aspect ratios of target images are important because only
necessary information on the image needs to be processed. If the target image is 2:1 and the imaging format is
1:1, for example, then half the image is useless. A better
solution would mirror the aspect ratio of the target image
in the image format.

Xilinx's LCAs permit a two-board set to
without sacrificing functional mbdularity.
counting algorithms can be implemented
Finally, LCAs allow for a multiple-iteration
cycle.

To overcome the limitations of hardwired logic and reduce
board space, several technologies were evaluated. These
included programmable logic arrays (PLAs), field programmable logic devices (FPLDs), semicustom and
fUllcustom devices, and Xilinx's Logic Cell Array (LCA).

be designed
In addition,
in the LCAs.
development

PUTTING A BUG TO REST

Size constraints indicated the necessity for semicustom of
fUll-custom integration, but traditional LSI technologies
violated the flexibility constraint. Although full-custom was
attractive, design costs were prohibitive and did not permit
iterative development. Standard PLDs did not allow for the
variety of register-like functions that the clock generation
logic required.

Initially, the TTL-based system was implemented in four pc
boards. However, it contained a bug. For every horizontal
line, an extra pixel pulse was being supplied. Although this
was confusing to the eye, it was compensated for in
firmware. Because the redesign of the clock driver board
was a significant task, the bug was allowed to live through
many iterations of the development cycle. When the
design of the clock generation circuit was translated into
the LCA, it was a trivial matter to delete a single horizontal
clock pulse and put the bug to rest in an afternoon.

Programmable logic arrays were attractive for some logic
functions and would have been the least costly. However,
PLAs did not allow the multiple register implementation
necessary for clock generation. Thus, the counting algorithms would have remained external to any integration of
the combinatorial logic. Also, although the PLA architecture would have saved board space, it would not have
preserved the functional modularity achieved in the first
implementation. Thus, it would have been impossible to
evolve a PLA-based system in response to changes in
sensor technology. Finally, any required changes would
have to be performed by field replacement. With over
35,000 lottery terminals installed on five continents, this
was unacceptable.

Using the LCA also provided the ability to vary the clock
generation circuitry to evaluate different sensors. Because there is no standard architecture for solid-state
digital imaging devices, clock requirements vary for different sensors. In a standard imaging application, it might be
possible to source the appropriate support chips for each
sensor from the manufacturer. But because development
of the reader involved nonstandard video speeds in a
noninterlaced mode, it was impossible to use standard
support chips. If it had been necessary to develop a clock
driver pc board for every sensor evaluated, it would have
been impossible to evaluate more than one sensor in the
development time. Because LCAs were used, varying
multiphase clocks could be generated for different sensors
under evaluation. Thus, the turnaround time for a design
change in the clock generation circuits was reduced from
one to six weeks to one day.

Field programmable logic devices, an update of the
PLA-style architecture allowing limited reprogrammability,
appeared to provide some of the flexibility needed. If the
problem were merely a straight combinatorial one, FPLDs
could have been used. However, the difficulty in supporting both registers and counting algorithms ruled out their
use.

7-42

E:XIUNX
SINGLE MAIN BOARD
PROCESSOR
MEMORY

The Solid State Reader does not rely on standard video
output. Thus, the 4:3 standard aspect ratio for broadcast
television is not a requirement. All image processing is
internal to the system. Real-time display of the image is
never required. Therefore, only those areas of the sensor
that may contain relevant information need to be required.
Information-bearing areas of a bet-slip vary with the betslip design, so it is helpful to redefine the area olthe sensor
that is acquired for processing.

COMI>fJNICATIONS
LINK

ANALOG
CIRCUITS

Because the clock driver circuitry, the memory addressing
logic, and the frame-grabber logic are all implemented in
the reconfigurable LeA, it is possible to acquire only
certain areas of the image. As each sensor has different
horizontal and vertical clock pulses, this flexibility cannot
be achieved in hardwired logic.

SENSOR
BOARD
IMAGE SENSOR BOARD

PRECISION OPTICS

Figure 3 illustrates the current architecture of the Solid
State Reader. Because of the functions consolidated in
the LeA, the system was reduced from four pc boards to
two. This could have been done using other technologies,
but they would not have preserved the functional modularity of the system. The LeA-based design provides both
size reduction and functional modularity.

114806

Figure 3. GTECH's Solid State Reader uses Logic Cell
Arrays (LCAs) to maximize flexibility and minimize board
space. Frame-grabber, memory addressing, and sensor clock
driver functions are consolidated in the LCA. By reducing the
number of chips, the required number of boards shrinks from
four to two.

Reprinted with permission from ESD: The Electronic
System Design Magazine.

II

7-43

Electronic
Products

Building Tomorrow's Disk
Controller Today

Th'",'"",m"",'",,,'p"'"" "'h""'''"

Jim Reynolds, President, Dave Randall, Chief Engineer, Andromeda Systems, Canoga Park, CA

Reprogrammable logic with a flexible architecture
enables a controller to keep up with today's highcapacity, high-speed disk drives

could be surface mounted onto a 35-in.2 dual-width board.
The only answer appeared to be VLSI custom or semicustom devices like gate arrays. But gate array definition
requires absolute design accuracy, and so a prototype
must be constructed long before custom-tooled ICs can be
specified and manufactured. Paradoxically, the prototype
itself required highly integrated logic.

Computer manufacturers historically have relied on advances in CPU and semiconductor memory technology for
increasing system throughput. At the same time, they
accepted as inevitable the hardware-bound I/O bottleneck. This position is becoming untenable with recent
advances in magnetic disk technologies, which have led to
a proliferation of high-capacity, high-speed drives.

To break thatfrustrating circle, it was necessary to convert
directly from schematic capture to a silicon breadboard of
mu Itiple electrically programmable logic devices (EPLDs).
Because many logic functions would be added to the
prototype after the initial test, EPROM-based PALs were
considered, like the EP1200 from Altera, which licenses
the technology from Monolithic Memories.

Full performance from these drives needs sophisticated
controllers like Andromeda Systems' new Storage Module
Device Controller (SMDC). With a 1-Mbyte data cache
and dynamic read-ahead algorithms, the SMDC dramatically reduces average disk access time and significantly
improves overall system performance (see box, ''The
Storage Module Device ContrOller"). The design and
performance benefitted greatly from using Xilinx's Logic
Cell Arrays (LCAs).

The EP1200 could provide the minimum functionality on
the silicon breadboard, but not the level of device integration for the production circuit board. To implement the
various state machines and other logic of the design, each
target gate array would need three EP1200s. The resulting schematic capture and simulation would then be used
to fabricate the gate arrays for the final product.

Very early in the design, it was clear that its high-performance caching scheme needed more SSIIMSI logic than

CACHE MEMORY
l·MBYTE DRAM

--

i

I
Q·BUS
INTERFACE

CACHE
ADDRESS
MAPPER

J

!

~

I

DISK
CONTROLLER

~

...

1

LCA.1
Q·BUS AND DMA
CONTROLLER

LCA2
CACHE
CONTROLLER

i

!

65C802 MICROPROCESSOR

I

LCA3

STORAGE
MODULE
DEVICE
INTERFACE

S~~~~~s\'g~I~~~~AL ~
CONTROLLER

i

~

STATIC
RAM

PERIPHERAL
EXPANSION
PORT

USER
SERVICE
PORT

EEPROM

114801

Figure 1. On Andromeda Systems' new Storage Module Device Controller, Xilinx Logic Cell Arrays handle the Q-bus interface
and direct memory access (DMA) Control. RAM/data-cache control. and SMD and peripheral expansion port control.

7-44

E:XllII%JX
Fortunately, this circuitous design path was bypassed by
using Xilinx's LCA (see box, "Xilinx's programmable gate
array"). There are two basic differences between LCAs
and other EPLDs. First, the LCA has the flexible architec:ture of a gate array. Second, LCAs employ static memory
to hold the logic configuration data.
The LCAs brought several significant advantages to the
controller design. Since the Xilinx 2064 LCA has 64
configurable logic blocks and the EP1200 only 20, a single
LCA could replace the three target gate arrays, elimination
the fabrication delays and costs of custom tooling.
Figure 2. The user service port can create color bar graphs
that dynamically show various attributes of the data cache,
such as read times, forward block reads, and I/O
completion rates.

Fu rthermore, the position of the LCAs on the board could
be determined before their internal logic configuration was
designed. Other than dedication input and output pins,
only a general idea of the function of each LCA was
needed. The board layout and the internal LCA logic
design could proceed in parallel, greatly reducing development time. Most design changes could be implemented
merely by reprogramming the LCAs. Thus, use of the
LCAs allowed the design to go directly from schematic
capture to a production board, skipping the wire-wrapped
prototype.

Aside from the LSI circuitry, the only other logic on the
SMDC board are TTL bus transceivers, SMD interface
drivers, and a few PALs.
The RAM of the data cache is in Zl Ps. Most of the interface
logic was surface mounted to the board. Despite the
board's small size, these VLSI devices permit several
advanced features.

The first LCA on the SMDC is the Q-bus interface and
direct memory access (DMA) controller(see Fig. 1). All but
5 of the 64 internal logic blocks were used. The LCA holds
the DMA addressing logic, the bus registers, and the
interrupt logic.

,
The SMDC's user service port connects directly to terminals or modems. No special test programs for specific
system environments are needed to commu nicate with the
controller. Users can define drives, assign logical units,
format drives, and do other more esoteric functions.

RAM/data-cache control is the job of the second LCA. It
controls the cache and has the interface between the disk
controller IC and the DMA logic. It signals cache-write
enables, multiplexes memory addresses, and enable
DMA reads and writes.

This port can monitor the operation of the controller while
the drive is in operation. The user can display color bar
graphs that dynamically show various attributes of the data
cache, such as read .Iimes, forward block reads,and I/O
completion rates. Caching parameters can be adjusted,
lelting the user tune the system for optimum performance.

The third LCA controls the SMD port and peripheral
expansion port. The expansion port is just a group of
programmable I/O connections. Since the LCA is programmable, the control logic for the expansion port can be
reconfigured for any desired 110 interface. Thus, this port
provides for future expansions (like adding a tape drive,
optical disk, or extra cache memory) at a fraction of the
cost of a separate controller. Unused logic in this LCA will
permit on-board functions to be added in future microcode
revisions to the controller.

Firmware can alter the configuration data for the LCAs,
modifying the circuit schematic and not the board. Since
the firmware is in EEPROMs, the service purt can accept
microcode upgrades in the field via modem. PROM set
replacement and on-shelf obsolescence are avoided.

II

7-45

Article Reprints

THE STORAGE MODULE DEVICE CONTROLLER

a 1-Mbyte data cache and unique caching algorithms.
Andromeda divides the cache into 1,024 granUles. The
information kept for each 1-Kbyte granule depends on
select criteria, which include:

Designed for LSI-l1 arid MicroNAX IIsystems,
Andromeda System!;' Storage Module Device Controller
(SMDC) for Winchester drives supporfstwo SMD or
SMDE drives at data rates up to 25 Mbits/s.. Another
Andromeda controller, the ESDC, works with the Enhanced Small Device Interface, the ESDI, for Winchesters or floppy-disk drives. Both controllers use the stimdard DU device driver and work with such operation systems as RT-11, TSX+, RSX, RSX-1fM, MicroRSX,
RSTS, MicroRSTS, UHrix, DSM, Unix, and MicroVMS.

The time data is first accessed
The number of times data is read
The time of the most recent read
The size ofthe read.
This information is then entered into an equation that approximates how probable it is that the granule will be requested again soon. Those granules with iow probabilities are designated to be overwritten by the next diskread operation. During cache accesses,' a memorymapper translates logical memory addresses into the. physical address.es of the appropriate granule in much the
same way that the Micro-Vax" memory management
unit would.

The SMDC achieves more performance and flexibility
than did previous generations of disk controllers. It includes data caching, high datactransfer rates, a peripheral expansion port, field-load able microcode, and a
user service port. State-of-the-art VLSI components
and packaging techniques fit the entire controller within
the 35 sq in. of a dual-width Q-bus board (see figure).

PREDICTIVE CACHING

Using Digital Equipment's Mass Storage Control Protocol (MSCP), the SMDC can partition two drives into as
many as 16 logical units with up to 32 Gbytes each. Onboard intelligence comes from a 65C802 microprocessor, and all the processor's code resides in just two
EEPROMs. The majority of the remaining logic is implemented with Xilinx programmable Logic Cell Arrays
(LCAs). Data integrity is ensured by 48-bit error detection and correction logic. An expansion port can be con~
nected to accessory. modules, allowing control of devices· like tape drives, optical disks, or extra cache
memory.

In a novel departure from most caching schemes, the
SMDCcaching mechanism not only looks althe past, but
tries to gaze into the future as well. As the system requests the data that has been pre-fetched into the cache,
the controller retrieves not only the requested data, but
also preemptively reads extra sequential blocks when
specific probability conditions are met. As a result, the
on~board cache's typical hit rate is over 80%. In other
words, the data being sought by the application will be
ready and waiting in the cache over 80% of the time.
Approximately 90% of the disk access time is due more
to average seek times and rotational latency than to the
actual data transfer rate. However, when a cache hit
occurs, the access time depends only on the speed of
the DMA channel responsible for sending the data to the
Q-bus.

The performance of the SM DC is greatly enhanced with

That DMA channel operates as fast as Q-busspecifications allow-to be specific, at a rate of up to 4 Mbytes/s.
Consequently, with the SMDC cache, seek time and rotationallatencyare reduced to zero over 80% of the time.
This reduces the average time for a four-block read from
27 ms to less than 6 ms.
In the majority of computer systems, mass-storage access time is undoubtedly the largest component of
throughput. In this situation, use of the SMDC enormously improves total system performance.
$$$$$
Andromeda Systems' Storage Module Device Controller is available now for $2,195. (The company's ESDI
controller is available for $1 ,995.) For more information,
call Don Talmadge at 818-709-7600, or circle 336 for the
SMDC and 337 for the ESDC.
7-46

IJOBLOCK

XILlNX'S PROGRAMMABLE GATE ARRAY

\

The Xilinx programmable gate array, known as a Logic
Cell Array (LCA), is a high-density CMOS IC that combines
user programmability with the flexibility of a gate array
architecture and the economy and testability of standard
products. Elements of the array include three categories
of configurable elements: I/O blocks, configurable logic
blocks, and programmable interconnections (see figure).

0
-{}
-{}
-{}
-{}
{}:
-j}
-{}

I/O blocks provide an interface between the external
package pin and the internal logic. Each block includes a
programmable input path and output buffer. The array of
configurable logic blocks contains the functional elements
from which the user's logic is constructed. Each array
includes a combinatorial section, storage elements, and
internal routing and control logic. Programmable interconnection resources connect the inputs and outputs of the
I/O blocks and configurable logic blocks into the desire
networks.
An LCA is configured by programming static memory cells
that determine the logic functions and interconnections.
On-chip logic provides for automatic loading of the configuration program at power-up or upon command. A
personal computer-based development software package
generates the configuration program. Other tools include
a simulator, in-circuit, and schematic capture package.

¢;Jg ¢;J

"¢;Jg ¢;Jg

CONFIGURABLE
LOGIC BLOCK~

o

0 0 0
0 oro 0
0 010 0
0 0 0 0
~

INTERCONNECT AREA-----..

1148 02

Reprinted with permission of Electronic Products.

II

7-47

Article Reprints

7-48

SECTIONS
Index

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Index

Index ................................................................................................... 8-1
Sales Office Listing ............................................................................. 8-5

Index

ABEL .......................................................................5-26

component selection ............................................... 2-60

ac parameters .................................................. 2-42. -90

configuration .....................................................•...... 2-79

accumulator .............................................................. 6-22

configuration memory ........................................ 2-2. -63

adder ................•......................... 6-22. -23. -24. -25. -26

corner bender .......................................................... 6-44

alpha particles: ............................................ 2-3. -64; 3~9

cost analysis ............................................................ 1-i 1

alternate buffer ........................................................ 2-42

counter ........... 6-28. -29. -30. -31. -32. -33. -34. -38. -40

applications ............................................................... 6-1

crystal oscillator ............................... 2-13. -23. -70; 6-10

APR .........................................................................5-10

daisy chain ....................................................... 2-20. -76

architecture: ............................................................... 1-4

DASH ......................................................................5-20

barrel shifter ............................................................ 6-19

data integrity .............................................................. 3-8

battery backup ................•........................................ 6-18

data transfer ............................................................ 6-12

BCD-to-binary ......................................... ;............... 6-42

dc parameters .................................................. 2-40. -89

BIOI ......................................................................... 2-42

decoding .................................................................. 6-21

binary-to-BCD ......................................................~ .. 6-43

delay tracking .......................................................... 6-14

bitstream· ................................................................. 5-11

delay variation .................................................. 2-26. -82

buffer characteristics ............................................... 2-42

Design Manager ........................................................ 5-4

bulletin board ............................................................. 4-4

design entry .........................................................5-2. -6

burn-in circuits ........................... 2-109. -125. -143. -163

design flow ................................................. ;.............. 5-1

bus .......................................................................... 2-11

design implementation ....................................... 5-3. -27

Cadence· .................................................................. 5-3'1

design verification ............................................... 5-3.32

capacitive loading ...................................................... 6-9

direct interconnect .............................................:2-9. -70

carry logic ................................................................ 6-22

disk controller .......................................................... 7-44

CCLK frequency ...................................................... 6-10

DONE timing .................................................... 2-17. -23

CLB ......... ;......................... ;................................ 2~5. -65

DRAM controller ............................... ;...................... 6~52

CLB characteristics .......................................... 2-42. -90

EditNet .................................................;.... ;......... 2-7. -66

clear ................................................................. 2-15. -72

electrostatiC discharge ............. ;.................: .......... ,... 3-9

comparator ..............................................................6-23

ESD ...................... ;; ......................................:............ 3-9

8-1

II

Index
FAE addresses .......................................................... 4-6

memory requirements ............................................. 5-40

FIFO ........................................................................ 6-46

Mentor Graphics ...................................................... 5-21

frames .............................................................. 2-16, -72

merging ..................................................................... 5-8

frequency counter ................................................... 6-45

MESA ...................................................................... 5-14

FutureNet ................................................................ 5-20

metastability ............................................................ 6-16

gate capacity ...................................................... 2-1, -63

Micro Channel ......................................................... 6-50

global buffer ............................................................ 2-42

MIL-STD-883 ................................................. 2-105; 3-1

hardware requirements ........................................... 5-40

military ................................................................... 2-103

header .............................................................. 2-16, -72

minimum delay ........................................................ 6-13

hysteresis .................................................................. 6-9

modes ..................................................................... 2-14

initialization ...................................................... 2-14, -74

multiplexer ............................................................... 6-19

interconnect ....................................................... 2-7, -67

newsletter ................................................................. .4-3

interconnect delay ............................................ 2-25, -80

optimization ............................................................... 5-7

lOB ..................................................................... 2-3, -64

OrCAD ..................................................................... 5-23

lOB characteristics ........................................... 2-44, -92

OrCAD simulator ..................................................... 5-30

latches ..................................................................... 6-27

ordering information ......................................... 2-60, -98

latchup ..................................................................... 3-10

oscillator ........................................................... 2-13, -70

LCA2XNF ................................................................ 5-12

output current ............................................................ 6-9

length counter .................................................. 2-16, -72

output slew rate ......................................................... 6-9

library ............................................................... 5-19, -34

package dimensions ................... 2-53 to 59, -99 to -102

literature .................................................................... 4-8

PAL ........................................................................... 5-6

long lines .......................................................... 2-11, -69

parity ....................................................................... 6-20

macros .................................................................... 5-34

PC-SILOS ............................................................... 5-28

majority logic ........................................................... 6-20

performance ............................................ 2-24, -80; 6-11

MakeBits ................................................. 2-17, -72,5-11

peripheral mode .................. 2-14, -20, -49, -75, -77, -96

MakePROM ............................................................. 5-14

PGA pinout.. ..................................................... 2-51, -99

MAP2LCA ................................................................. 5-9

phase comparator ................................................... 6-37

mapping .................................................................... 5-7

pin assignment ................................................. 2-31, -86

master mode ...................................... 2-14, -18, -74, -76

pin description .................................................. 2-29, -84

master parallel mode ....................................... 2-48, -95

pinouts ...................................................... 2-32, -51, -86

master serial mode .......................................... 2-47, -94

platform ................................................................... 5-16

memory cell ................................................ 2-2, -64; 3-8

PLL .......................................................................... 6-37

8-2

postamble ........................................................ 2-17. -72

slave mode .......................... 2-14. -20. -50. -76. -78. -97

power consumption .................. 2-27. -28. -71. -83; 6-10

sockets .................................................................... 3-22

power distribution ...................................... 2-26. -27. -71

soft errors .................................................................. 3-9

power down ............................................ 2-15. -27; 6-18

speed ............................................................... 2-24. -80

preamble .......................................................... 2-16. -72

standby .................................................................. 2-178

prescaler .......................................................... 6-38. -40

start-up ........................................................... 2-15; 6-15

printer controller ........................................................ 7-1

state machine ................................................... 6-48. 7-8

programming .................................................... 2-14. -74

subtractor ................................................................ 6-22

programming flowchart ................................ 2-182. -183

support agreement .................................................. 5-33

programming specs ............................................... 2-181

switching matrix ......................................................... 2-7

PROM programmer ................................................. 5-32

system diagnostics .................................................. 7-24

pull-up resistors ........................................ 2-12. -80; 6-9

TBUF ....................................................................... 2-42

pulse-swallowing .............................................. 6-38. -40

test specifications ...................... 2-110. -127. -146. -165

quality ........................................................................ 3-1

testing ................................................................ 3-1. -12

radiation hardness ................................................... 3-11

thermal resistance ................................................... 3-19

reprogram ........................................................ 2-23. -78

thermal shock ............................................................ 3-4

readback .................................... 2-21. -22. -50. -78. -97

threshold ..................................................... 2-4. -22. -78

reconfigurable logic ................................................. 7-24

tracking .................................................................... 6-14

reconfigure .............................................•......... 7-15. -19

training courses ........................................................ .4-7

reliability .................................................................... 3-1

typical delays ........................................................... 6-14

RESET .................................................................... 6-15

up/down counter ....................................... 6-30. -31. -33

RESET polarity ...................................................... 2-178

users' groups ............................................................. 4-1

RESET timing .................................................. 2-17. -23

video graphics ......................................................... 7-22

schematic editor ...................................................... 5-20

video tape .................................................................. .4-2

selection .................................................................. 2-60

VIEWdraw ............................................................... 5-24

seminars ................................................................... .4-1

VIEWlogic ................................................................ 5-25

serial PROM .......................................................... 2-176

VIEWsim ................................................................. 5-29

set-uptime .............................................................. 6-13

weight ...................................................................... 3-21

shift register counter ................................................ 6-28

wired-AND ............................................, ...,............... 2-12

SiLOS ...................................................................... 5-28

workstations ............................................................ 7-15

simulator .......................................................... 5-12. -28

XACT ....................................................................... 5-27

size estimate ............................................................. 6-3

XC1736A ........................................................ 1-6;2-175

8-3

II

Index
XC1765 .......................................................... 1-6; 2-175

XCELL ....................................................................... 4-3

XC2000 ............................................................ 1-6, 2-63

XDM .......................................................................... 5-4

XC2000 design .......................................................... 6-8

XMAKE ...................................................................... 5-4

XC3000 .............................................................. 1-7; 2-1

XNFMAP ................................................................... 5-7

XC3000 design .......................................................... 6-7

XNFMERGE .............................................................. 5-8

XC4000 ..................................................................... 1-8

xtal oscillator .................................... 2-13, -23, -70; 6-10

8-4

Sales
Offices
HEADQUARTERS

EUROPE

CALIFORNIA (continued)

GEORGIA

KENTUCKY

XILlNX, Inc.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114

XILlNX, Ltd.
Suite 1B, Cobb House
Oyster Lane
Byfleet
Surrey KT14 7DU
United Kingdom
Tel: (44) 932-349401
FAX: (44) 932-349499

Quest-Rep Inc.
9444 Farnham St., Suite 107
San Diego, CA 92123
(619) 565-8797
FAX: 619-565-8990

Novus Group - GA
6115-A Oakbrook Parkway
Norcross, GA 30093
(404) 263-0320
FAX: 404-263-8946

Gen " Marketing, Inc.
8819 Roman Court
Louisville, KY 40291
(502) 491-5250
FAX: 502-491-5250

Norcomp
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
TWX: 510-600-1477
FAX: 408-986-1947

IDAHO (Southwest)

LOUISIANA (Northern)

Thorson Company Northwest
12340 NE 8th St., Ste. 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-9185

Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897

Norcomp
2140 Professional Dr., Ste 200
Roseville, CA 95661
(916) 782-8070
FAX: 916-782-8073

Wasatch-Pro Rep Marketing
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021

COLORADO

ILLINOIS

Luscombe Engineering
616 Kimbark Street
Longmont, CO 80501
(303) 772-3342
FAX: 303-772-8783

Beta Technology Sales, Inc.
1009 Hawthorne Drive
Itasca, IL 60143
(708) 250-9586
FAX: 708-250-9592

CONNECTICUT

Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314-291-7958

XILINX
SALES OFFICES
NORTH AMERICA
XILlNX, Inc.
3235 Kifer Road
Suite 320
Santa Clara, CA 95051
(408) 245-1361
FAX: 408-245-0517
XILlNX, Inc.
15615 Alton Parkway
Suite 280
Irvine, CA 92718
(714) 727-0780
FAX: 714-727-3128
XILlNX, Inc.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
(603) 891-1096
FAX: 803-891 -0890
XI LlNX, Inc.
65 Valley Stream Parkway
Suite 140
Malvern, PA 19355
(215) 296-8302
FAX: 215-296-8378
XILlNX, Inc.
939 North Plum Grove Road
Suite H
Schaumburg, IL 60173
(708) 605-1972
FAX: 708-605-1976

XILlNX, GmbH.
MOnchner Strasse 1
W-8011 Aschheim
Germany
Tel: (49) 89-904·5024
FAX: (49) 89-904-4748
JAPAN
XILINX K. K.
Kyobashi NO.8
Nagaoka Bldg. 8F
20-9 Hatchobori Nichome
Chuo-ku, Tokyo 104
Japan
Tel: (81) 33-2979191
FAX: (81) 33-2979189
BBS: (81) 33-2979195

U.S. SALES
REPRESENTATIVES
ALABAMA
Novus Group, Inc. (Corporate)
2905 Westcorp Boulevard
Suite 120
Huntsville, AL 35805
(205) 534-0044
FAX: 205-534-0186
ARIZONA

Quatra Associates
4645 S. Lakeshore Dr. Ste. 1
Tempe, AZ 85282
(602) 820-7050
FAX: 802-820-7054
ARKANSAS

XI LlNX, Inc.
4141 Blue Lake Circle
Suite 217
Dallas, TX 75244
(214) 960-1043
FAX: 214-960-0927

Bonser-Philhower Sales
689 W. Renner Road, Ste. 101
Richardson, TX 75080
(214) 234·8438
FAX: 214-437-0897
CALIFORNIA
SC Cubed
68 Long Court, Suite 2C
Thousand Oaks, CA 91360
(805) 496-7307
FAX: 805-495-3601
SC Cubed
17862 17th St. #207
Tustin, CA 92680
(714) 731-9206
FAX: 714'731-7801

Lindco Associates, Inc.
Cornerstone Professional Park
Suite C-101
Woodbury CT, 06798
(203) 266-0728
FAX: 203-266-0784
DELAWARE
Delta Technical Sales, Inc.
122 N. York Rd., Ste. 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(301) 644·5700
TWX: 510-600-9460
FAX: 301 -644-5707
FLORIDA
Semtronic Assoc., Inc.
657 Maitland Avenue
Altamonte Springs, FL 32701
(407) 831-8233
FAX: 407-831-2844

Semtronic Assoc., Inc.
3471 N. W. 55th Street
Ft. Lauderdale, FL 33309
(305) 731-2484
FAX: 305-731-1019

Semtronic Assoc., Inc.
1467 South Missouri Avenue
Clearwater, FL 34616
(813) 461-4675
FAX: 813-442-2234

8-5

INDIANA
Gen " Marketing,lnc.
3003 E. 96th St. #102
Indianapolis, IN 46240
(317) 848-3083
FAX: 317-848-1264
Gen " Marketing, Inc.
4803 Oak MastT rail
Ft. Wayne, IN 46804
(219) 436-4485
FAX: 219-436'4485
IOWA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
KANSAS
Advanced Technical Sales
610 N. Mur'Len, Suite B
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641

LOUISIANA (Southern)
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713-789-3072
MAINE

Genesis Associates
128 Wheeler Road
Burlington, MA 01813
(617) 270-9540
FAX: 617-229-8913
MARYLAND
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD21227-1082
(301 )644-5700
FAX: 301-644-5707
MASSACHUSETIS
Genesis AssoCiates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
MICHIGAN
A.P. Associates
810 E. Grand River
PO Box 777
Brighton,MI48118
(313) 229-6550
FAX: 313-229-9356
MINNESOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322
MISSISSIPPI
Novus Group, Inc.
102L Commonwaalth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703

•

Sales Offices
MISSOURI

NEW MEXICO

OKLAHOMA

TENNESSEE

VIRGINIA

Advanced Technical Sales
601 N. Mur-Len, Suite B
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641

Quatra Associates
600 Autumwood Place, S. E.
Albuquerque, NM 87123
(505) 296-6781
FAX: 505-292-2092

Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897

Novus Group, Inc.
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703

Micro Comp, Inc.
8811Timberlake Rd.
Suite 107
Lynchburg, VA 24502
(804) 239-2626
FAX: 804-239-1333

Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314-291-7958

NEW YORK (Metro)

MONTANA
Wasatch-Pro Rep Marketing
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
NEBRASKA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258

Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW YORK
Gen-Tech Electronics

4855 Executive Drive
Liverpool, NY 13088
(315) 451-3480
FAX: 315-451-0988
Gen-Tech Electronics
41 Burning Tree Lane
Rochester, NY 14526
(716) 381-5159
FAX: 716-381-5159"
"Activates Fax

NEVADA
Norcomp
(Excluding Las Vegas)
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
FAX: 408-986-1947

Gen-Tech Electronics
5 Arbutus Lane
Binghampton, NY 13901
(607) 648-8833
FAX: 607-648-4949

Quatra Associates
(Las Vegas)
4645 S. Lakeshore Dr., Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054

The Novus Group, Inc.
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703

NORTH CAROLINA

NORTH DAKOTA
NEW HAMPSHI RE
Genesis Associates
128 Wheeler Road
Burlington, MA 01813
(617) 270-9540
FAX: 617-229-8913

Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322
OHIO

NEW JERSEY (Northern)
Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW JERSEY (Southern)
Delta Technical Sales, Inc.
122 N. York Road, Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920

Bear Marketing, Inc.
3554 Brecksville Road
PO Box 427
Richfield, OH 44286-0427
(216) 659-3131
FAX: 216-659-4823
Bear Marketing, Inc.
240 W. Elmwood Drive
Suite 1012
Centerville, OH 45459-4248
(513) 436-2061
FAX: 513-436-9137

OREGON
Thorson Company Northwest
9600 SW. Oak Street,
Suite 320
Portland, OR 97223
(503) 293-9001
FAX: 503-293-9007
PENNSYLVANIA
Delta Technical Sales, Inc.
122 New York Rd., Ste. 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
Bear Marketing, Inc.
4284 Rt. 8, Suite 211
Allison Park, PA 15101
(412) 492-1150
FAX: 412-492-1155
PUERTO RICO
Semtronic Assoc., Inc.
Mercantile Plaza Building
Suite 816
Hato Rey, PR 00918
(809) 766-0700
FAX: 809-763-8071
RHODE ISLAND
Genesis Associates
128 Wheeler Road
Burlington, MA 01813
(617) 270-9540
FAX: 617-229-8913
SOUTH CAROLINA
The Novus Group, Inc.
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703
SOUTH DAKOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322

Novus Group, Inc.
6115-A Oakbrook Pkwy.
Norcross, GA 30093
(404) 263-0320
FAX: 404-263-8946
TEXAS
Bonser-Philhower Sales
8240 MoPac Expwy.,
Suite 135
Austin, TX 78759
(512) 346-9186
FAX: 512-346-2393
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713-789-3072
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
TEXAS (EI Paso County)
Quatra Associates
600 Autumwood Place SE
Albuquerque, NM 87123
(505) 296-6781
FAX: 505-292-2092
UTAH
Wasatch Pro Rep Marketing
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
VERMONT
Genesis Associates
128 Wheeler Road
Burlington, MA 01813
(617) 270-9540
FAX: 617-229-8913

WASHINGTON
Thorson Company Northwest
12340 NE 8th Place, Ste. 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-9185
WASHINGTON
(Vancouver, WA only)
Thorson Company Northwest
9600 S.W. Oak Street
Suite 320
Portland, OR 97223
(503) 293-9001
FAX: 503-993-9007
WASHINGTON D.C.
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(301) 644-5700
FAX: 301-644-5707
WISCONSIN (Western)
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322
WISCONSIN (Eastern)
Beta Technology Sales, Inc.
9401 Beloit, Suite 409
Milwaukee, WI 53227
(414) 543-6609
FAX: 414-543-9288
WYOMING
Wasatch Pro Rep Marketing
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021

Distributed in North America By
Hamilton/Avnet
Locations throughout
the U.S. and Canada.
1-800-HAM-ASIC
FAX: 408-743-3003

Marshall Industries
Locations throughout
the U.S. and Canada.
(800) 522-0084
FAX: 818-307-6297

Insight Electronics
Locations throughout
the Western & South
Central U.S.
1-800-677-7716
FAX: 619-587-1380

8-6

Phase 1 Technology Corp.
46 Jefryn Blvd.
Deer Park, NY 11729
(516) 254-2600
FAX: 516-254-2693
FAX: 516-254-2695(NY sales)

Nu Horizons
Electronics Corp.
6000 New Horizons Blvd.
Amityville, New York 11701
(516) 226-6000
FAX: 516-226-6262

~Xftl;~n{

'''int,1rtwJ\\.

INTERNATIONAL
SALES
REPRESENTATIVES
AUSTRALIA
ACDIITRONICS
106 Belmore Rd. North
Riverwood, N.S.w. 2210
Sydney, Australia
Tel: (61) 2-534-6200
FAX: (61) 2-534-4910
ACDIITRONICS
Unit 2,17-19 Melrich Road
POBox 139
Bayswater VIC 3153
Australia
Tel: (61) 3-762-7644
FAX: (61) 3-762-5446
ACDIITRONICS
Enterprise Unit 1
Technology Park
Bentley WA 6102
Australia
Tel: (61) 9-472-3232
FAX: (61) 9-470-2303
ACDIITRONICS
20D William Street
Norwood SA 5067
South Australia
Tel: (61) 8-364-2844
FAX: (61) 8-264-2811
AUSTRIA
Eljapex Ges.m .b.H.
Eitnergasse 6
A-1232Wien
Austria
Tel: (43) 1-861531
FAX: (43) 1-861531300
BELGIUM & LUXEMBURG
Rodelco SA
Limburg Stirum 243
1780Wemmel
Belgium
Tel: (32) 2-460-0560
FAX: (32) 2-460-0271
CANADA
(BRITISH COLUMBIA)
Thorson Company Northwest
12340 N.E. 8th Street
Suite 201
Bellevue, WA 98005 USA
Tel: (206) 455-9180
FAX: 206-455-9185
Electro Source
3665 Kingsway, Suite 300
Vancouver, B.C. V5R 5W2
Canada
Tel: (604) 275-2734
FAX: 604-275-2736
CANADA (OnAWA)
Electro Source, Inc.
340 March Road, Suite 503
Kanata, Ontario K2K 2E4
Canada
Tel: (613) 592-3214
FAX: 613-592-4256

CANADA (TORONTO)
Electro Source, Inc.
230 Galaxy Boulevard
Rexdale, Ontario M9W 5R8
Canada
Tel: (416) 675-4490
FAX: 416-675-6871
CANADA (QUEBEC)
Electro Source
6600 T ransCanada Hwy
Suite 420
Point Claire Quebec H9R 4S2
Canada
Tel: (514) 630-7486
FAX: 514-630-7421
DENMARK
Dana Tech AlS
Krogshoejvej 51
DK-2880 Bagsvaerd
Denmark
Tel: (45) 44-3771 10
FAX: (45) 44-37 71 12
Dana Tech AS
Egsagervej 8
DK 8230 Rabyhoej
Denmark
Tel: (45) 86-253100
FAX: (45) 86-253102
FINLAND
Field OY Instrumentarium
Niittyliinpolku 10
SF -00620 Helsinki
Finland
Tel: (358) 0-7571011
FAX: (358) 0-798853
FRANCE
AVNET RTF
1 Bis, rue Marcel Paul
BAt A
l.l.la Bonde
91300 MASSY

France
Tel: (33) 1-60139300
FAX: (33) 1-60139198
AVNET RTF Composant
81 Rue Pierre SEimard
92320 Chatillon
SiS Bageneux France
Tel: (33) 49652700
FAX: (33) 49 65 2738
AVNET RTF Sud-Ouest
Innopolis Hall A
Voie No. 1-BP 404
31314 Labege Cedex

France
Tel: (33) 613921 12
FAX: (33) 61 39 21 40
AVNET RTF Aquitaine
16 Rue F ran90is Arago
li du Phare
33700 Merignac

France
Tel: (33) 56 55 92 92
FAX: (33) 56 34 39 99

AVNET RTF Rh5ne-Auvergne
Parc Cluc du Moulin a Vent
BAt 26
33 Av. du docteur G. Levy
69200 venissieux
France
Tel: (33) 78 00 07 26
FAX: (33) 7801 2057

AVNET RTF Provence COte
D'Azur
8300 Toulon

France
Tel: (33) 94 03 3256
FAX: (33) 94360215
AVNET RTF Ouest
T echnoparc-BAt. E
4 Av. des Peupliers
35510 Cesson Sevigne

France
Tel: (33) 99838485
FAX: (33) 99 83 80 83
AVNET RTF RMne-Alpes
Miniparc - lac des Bealieres
23 Av. de Granier
38240 Meylan

Metronik
Laufamholzstr. 118
8500 Nurnberg 30
Nurnberg
Germany
Tel: (49) 911-544966168
FAX: (49) 911-542936
Metronik
Leiwenstr. 37
7000 Stuttgart 70
Germany
Tel: (49) 711-764033135
FAX: (49) 711-7655181
Metronik
Askaloner Weg 3
W-l000 Berlin 28
Germany
Tel: (49) 30-4011662163
FAX: (49) 30-4011626
Metronik Systeme
GrenzstraBe 26
0-4020 Halle
Germany
Tel: (49) 345-823352
FAX: (49) 345-823-346

France
Tel: (33) 76 90 11 88
FAX: (33) 76 410409
AVNET RTF Nantes
Le Sillon de Bretagne
23e etage-Aile C
8 Av.des ThEibaudieres
44802 Saint Herblain

France

GREECE
Peter Caritato & Assoc. S. A.
Liialliot,31
Athens 11743 Greece
Tel: (30) 1-9020115
FAX: (30) 1-9017024
HONG KONG

France

Excel Associates, Ltd.
Unit No. 2620-2525, Tower I
Metroplaza, Hing Fong Road,
Kwai Fang, N.T.
Hong Kong
Tel: (852) 418-0909
FAX: (852) 418-1600

Tel: (33) 83 531234
FAX: (33) 83 56 70 03

HUNGARY

Tel: (33) 4063 2300
FAX: (33) 40632288

AVNET RTF Est
BP 163
54186 HeiliecourtCedex

GERMANY
Metronik GmbH
Leonhardsweg 2
8025 Unterhaching
Munchen
Germany
Tel: (49) 89-611080
FAX: (49) 89-6116468
Metronik
lum Lonnenhohl 38
4600 Dortmund 13
Germany
Tel: (49) 231-214179
FAX: (49) 231-210799
Metronik
Buckhorner Moor 81
2000 Norderstedt
Hamburg
Germany
Tel: (49) 40-5228091192
FAX: (49) 40-5228093

DatawareElectronic Eng. Ltd.
Eljapex Ges.m.b.H.
22 Angol Street
H-1149 Budapest
Hungary
Tel: (36) 11635081
FAX: (36) 11635867
INDIA
Malhar Corporation
924 County Line Road
Bryn Mawr, PA 19010
USA
Tel: (215) 527-5020
FAX: (215) 525-7805

ISRAEL
E.I.M International Ltd.
2 Hmshiloach Street
P.O. Box 4000
Petach Tiqva
Israel 49130
Tel: (972) 3-92 20812
FAX: (972) 9244857
ITALY
ACSIS S.R.L.
Via Alberto Mario. 26
20149 Milano, Italy
Tel: (39) 2-4390832
FAX: (39) 2-48012289
Silverstar-Celdis
Via Fulvio Testi, 280
20126 Milano
Italy
Tel: (39) 2-66125 1
FAX: (39) 2-66101359
Silverstar-Celdis
Via Collamarini, 22
40139 Bologna, Italy
Tel: (39) 51-538500
FAX: (39) 538831
Silverstar-Celdis.

Via Belle', 26
Fermo-Ascoli PicenoTel: (39) 734-2261
FAX: (39) 734-229330
Silverstar-Celdis
Via Paisiello,30
00162 Roma, Italy
Tel: (39) 6-8848841
FAX: (39) 6-8553228
Silverstar-Celdis
Piazza Adriano 9
10139Torino, Italy
Tel: (39) 11-443275
FAX: (39) 114473306
Silverstar-Celdis

Centro Direzionale BeneUi
Via M. Del Monaco, 16
6100 Pesaro, Italy
Tel: (39) 721-26560
FAX: (39) 721-400896
Silverstar-Celdis
Via Masaccio, 175
50019 Firenze, Italy
Tel: (39) 55-572418
FAX: (39) 55-579575

Silverstar-Celdis
Via Porto Torres, 129
Bari, Italy
Malhar Sales&Service Pvt. Ltd. Te;: (39) 80-5554994
1214 Hal lind Stage
FAX: (39) 80-5551994
Indlranagar
Bangalore 560038
Silverstar-Celdis
India
Piazza Marini 20110
Tel: (91) 812-568772
Lavagna-Genova
FAX: (91 812-542588
Tel: (39) 185-301100
FAX: (39) 185-303100
IRELAND

Metronik
SiemensstraBe 4-6
6805 Heddesheim
Mannheim
Germany
Tel: (49) 6203-4701103
FAX: (49) 620345543

8-7

Memec Ireland Ltd.
Block H Lock Quay
Clare Street
Limerick Eire
Ireland
Tel: (353) 61-411842
FAX: (353) 61-411888

•

Sales Offices
JAPAN

JAPAN (cont'd)

ROMANIA

SOUTH AMERICA (cont'd)

TAIWAN

Okura & Co., Ltd.
&12, Ginza Nichome
Chuo-Ku
Tokyo, 104 Japan
Tel: (81) 3-3566-6364
FAX: (81) 3-3566-2887

Inoware 21, Inc.
TSI Nihonbashi Hamacho
Daini Bldg.
3-38-5, Nihonbashi Hamacho
Chuo-ku, Tokyo, 103 Japan
Tel: (81) 3-5695-1521
FAX: (81) 3-5695-1524

EljapeXiElbatex Ges.m.b.h.
Str. Petre Cretu NrAO
Bucuresti, Rumania
Tel: (40) 65-43-32

Hitech
Divisao de Hiead Sistemas Ltda.
Av. Eng. Louiz Carlos Berrini 801
04571-Brooklin
Sao Paulo, Brazil
Tel: (55) 11-531-9355
FAX: (55) 11-240-2650

Excel Associates, Ltd.
1037 Min Sheng East Road
14FL-l Hai Hwa Bldg.
Taipei
Taiwan RO_C.
Tel: (886) 2-760-2028
FAX: (886) 2-765-1488

SOUTHEAST ASIA

Princeton Technology Corp
2F No 233-1 Bao Chiao Rd.
HsinTien
Taipei, Taiwan RO.C.
Tel: (886) 2-9178856
FAX: (886) 2-9173836

Fuji Electronics CO., Ltd
Ochanomizu Center Bldg.
3-2-12 Hongo. BunkyoOKu
Tokyo, Japan 113
Tel: (81) 3-3814-1411
FAX: (81) 3-3814-1414
Okura Electronics Co., Ltd.
3-6, Ginza 2-chome,
Chuo-ku, Tokyo, 104 Japan
Tel: (81) 3-3564-6871
FAX: (81) 3-3564-6870
Okura Electronics
Service Co., Ltd.
Kyoei Bldg.
5-3, Kyobashi 3-chome,
Chuo-ku, Tokyo, 104 Japan
Tel: (81) 3-3567-6501
FAX: (81) 3-3567-7800
Tokyo Electron Ltd.
P. O. Box 7006
Shinjuku Monolith
3-1 Nishi-Shinjuku 2-chome,
Shinjuku-ku,
Tokyo, 163 Japan
Tel: (81) 3-3340-8193
FAX: (81) 3-3340-8408
Towa Elex Co., Ltd.
Lapore Shinjuku
2-15-2 Yoyogi,
Shibuya-ku, Tokyo, 151
Japan
Tel: (81) 3-5371-3411
FAX: (81) 3-5371-4760
Varex Co" Ltd.
Nippo Shin-Osaka No.2 Bldg.
1-8-33, Nishimiyahara,
Yodogawa-ku,
Osaka, 532
Japan
Tel: (81) 6-394-5201
FAX: (81) 6-394-5449

Fuji Electronics Co., Ltd.
Ochanomizu Center Bldg.,
3-2-12 Hongo, Bunkyo-ku
Tokyo, 113 Japan
Tel: (81) 3-3814-1411
FAX: (81) 3-3814-1414
KOREA
Excel Associates
4FL, Mungdang Bldg.,152-62
Samsung-dong
Kangnam-ku
Seoul, Korea
Tel: (82) 2-563-5277
FAX: (82) 2-563-5279
THE NETHERLANDS
Rodelco BV Electronics
Takkebijsters 2
P.O. Box 6824
4817 BL Breda
The Netherlands
Tel: (31) 76-784911
FAX: (31) 76-710029
NORWAY
BIT Elektronikk AS
Smedsvingen 4
P.O. Box 194
1364 Hvsalstad Norway
Tel: (47) 2-981370
FAX: (47)2-9813 71
POLAND
EljapeXiElbatex Ges.m.b.H
UI. Hoza 29.31 Me
Poland
Tel: (48) 22-21-6531
FAX: (48) 22-55-3434
PORTUGAL
Componenta Componentes
Electronicos LDA
R Luis De Camoes, 128
1300 Lisboa
Portugal
Tel: (351) 1 3621283/4
FAX: (351) 1 3637655

SERBIA
EljapeXiElbatex Ges.m.b.H.
Kapetan Misina 22
11000 Beograd
Serboa
Tel: (038) 11-631-250
FAX: (038) 11-631-250

Excel Associates, Ltd.
Unit No. 2520-2525, Tower I
Metroplaza, Hing Fong Road,
Kwai Fong, N.T.
Hong Kong
SINGAPORE
Tel: (852) 418-0909
Excel Associates, Ltd.
Singapore Representative Office FAX: (852) 418-1600
10 Anson Road #14-02
SPAIN
International Plaza

Singapore 0207
Tel: (65) 222-4962
FAX: (65) 222-4939
SLOVENIA/CROATIA
Eljapex/Elbatex Ges.m.b.H
Stegne 19,PO Box 19
6111?LJUBLJANA
Tel: (061) 191-126-507
FAX: (061) 192-398
SOUTH AFRICA

South African Micro-Electronic
Systems (PTV) Ltd.
2 Rooibok Avenue
Koedoespoort, Pretoria
Republic of South Africa
Tel: (27) 012-736021
FAX: (27) 012-737084

ADM Electronica SA
cfTomas Breten, 50, 3-2
28045 Madrid
Spain
Tel: (34) 1-53041 21
FAX: (34) 1-53001 64
ADM Electronics, SA
Mallorca 1
08014 Barcelona
Spain
Tel: (34) 3426-6892
FAX: (34) 3425-0544
SWEDEN
DIPCOM Electronics AB
P.O. Box 1230
8-16428 Kista
Sweden
Tel: (46) 87522480
FAX: (46) 8751 3649

Interface International Corp.
15466 Los Gatos Blvd., Suite 211
Los Gatos, CA 95032
SWITZERLAND
USA
Fenner Elektronik AG
Tel: (408) 356-0216
Abteilung Bauteile
FAX: (408) 356-0207
GewerbestraBe 10
CH-4450 Sissach
Switzerland
SOUTH AMERICA
Tel:(41)61980000
DTS Ltda.
FAX:
(41) 61985608
Rosas 1444
Santiago
Chile, South America
Tel: (56) 2-699-3316
FAX: (56) 2-697-0991
Reycom Electroniea SRL
Uruguay 362 Peso 8 - Depto. F
1015 Buenos Aires
Argentina, South America
Tel: (54) 1-45-6459/49·7030
FAX: (54) 1-11-1721

8-8

UK
Microcall Ltd.
17 Thame Park Road
Thame
Oxon OX93XD
England
Tel: (44) 844-261939
FAX: (44) 844-261678
Cedar Technologies
The Old Waver Works
Howse Lane
Bicester
Oxon OX68XF
England
Tel: (44) 869-322366
FAX: (44) 869-322373
Avner Acress
Jubilee House
Jubilee Road
Levchworth
Herts SG61QH
England
Tel: (44) 462 482182

1:XILINX
The Programmable Gate Array Company.
2100 Logic Drive, San Jose, CA 95124.

Printed in U.S
Tel. (408) 559-7778 EasyLink 629 16309

1WX. 5106008750 XILINX UQ

FAX (408) 559-71 14

PIN 0010048



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:11:01 13:57:21-08:00
Modify Date                     : 2017:11:01 14:58:25-07:00
Metadata Date                   : 2017:11:01 14:58:25-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:0cfb794b-034d-5043-9a63-84dac56126fa
Instance ID                     : uuid:63fc898c-cee2-ad46-aabd-0208fa9a267e
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 418