1993_AMD_PAL_Device_Handbook 1993 AMD PAL Device Handbook
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PAL® Device Data Book and Design Guide
1993
Advanced
Micro
Devices
Family
Standard
Packages
Part Number
Technology
Features
EE CMOS
GALIII Device Equivalent
tPD
ns
Icc
mA
Page
2-58
10
125
115
115
10
55
UNIVERSAL PAL DEVICES
16V8
PALCE16V8H-5
PALCE16V8H-7
20S,J
20P, J
PALCE 16V8H-1 0
PALCE16V8Q-10
20P,S,J
PALCE16V8H-15
15
PALCE16V8H-25
20P,S,J
25
90
PALCE16V8Q-25
PALCE16V8Z·15
20P, J
20P, J
25
15
55
0.015
25
0.015
25
30
0.015
115
115
Zero-Power
3.3 V Zero-Power
20P,J
20P, J
24P,28J
3.3V
High-Drive
10
PALCE20V8H-5
24S,28J
GAL Device Equivalent
24P,28J
5
7.5
125
PALCE20V8H -7
10
115
15
24P,S,28J
10
55
PALCE20V8H-15
24P,28J
PALCE20V8Q-15
15
15
90
55
PALCE20V8H-25
PALCE20VSQ-25
25
25
55
7.5
220
10
15
180
180
25
180
5
7.5
115
24P,28J
TTL
Varied Term Distribution
PAL22V10-10
PAL22V10-15
AmPAL22V10A
PALCE22V10H·5
28J
PALCE22V10H-7
24P, S, 28J
EECMOS
Varied Term Distribution
PALCE22V10H-10
2-124
2-79
2-135
2-214
115
PALCE20V8Q·10
PAL22V10-7
2-104
0.015
PALLV16V8-10
PALCE16V8HD-15
PALCE20V8H-10
24V10
90
55
20P,J
PALLV16V8Z·25
PALLV16V8Z-30
22V10
15
PALCE16V8Q-15
PALCE16V8Z-25
20V8
5
7.5
90
2-266
2-294
115
10
120
PALCE22V1 OQ·1 0
24P,28J
10
55
PALCE22V10H-15
24P,S,28J
15
90
PALCE22V10Q-15
24P,28J
15
55
PALCE22V1 OH~25
24P, S, 28J
25
90
PALCE22V1oo-25
24P,28J
25
55
PALCE22V10Z·15
PALCE22V10Z-25
24P, S, 28J
Zero Power
15
25
0.015
0.015
2-320
PALLV22V10Z·25
24P, S, 28J
3.3 V Zero-Power
25
0.015
2-331
PALCE24V10H-15
28P, J
28-Pin GAL-Type
15
115
2-345
25
115
PALCE24V10H-25
26V12
PALCE26V12H-15
PALCE26V12H-20
2SP,J
Advanced 22V10 Macrocell
15
20
105
105
2-360
29M16
PALCE29M16H-25
24P,28J
Advanced Macrocell
25
100
2-377
2-432
ASYNCHRONOUS PAL DEVICES
610
PALCE610H-15
24P,28J
PALCE610H-25
20RA10
29MA16
PALCE20RA10H-20
PALCE29MA 16H-25
24P,2SJ
24P,28J
Bold part numbers indicate preliminary.
EECMOS
J-K F/Fs,
15
90
Prog. CLK
Prog. ClK
25
90
20
100
2-236
Prog. CLK,
Advanced Macrocell
25
100
2-399
PAL ® Device Data Book
and Design Guide
1993
A
D VA
NeE
D
M
Ie
ROD
E V
ICE
S
© 1993 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD~ assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.
Trademarks
AMD, HAL, MACH, PAL, PALASM and SKINNYDIP are registered trademarks of Auto Vec, ProPAL and ZPAL are trademarks and FusionPLD is a
service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Your fast time-to-market needs can now be met better than ever with PAL ~ devices from Advanced Micro Devices, Inc. This new data book provides you with a truly diverse selection of lowpower and high-performance CMOS solutions in addition to the highest performing bipolar products in the industry. A number of Application Notes have also been included in order to make this
data book a valuable design guide as well.
For your high-density PLD requirements, please contact an AMD representative for our latest
printing of the MACH~ 1 and 2 or MACH 3 and 4 Family Data Books.
Thanks for selecting AMD. Remember, our partnership helps you gain and keep the competitive
edge. We're not your competition.
~~{k~
Director of Marketing
Programmable Logic
c
III
~AMD
Iv
TABLE OF CONTENTS
Chapter 1
Introduction ................................................... 1-1
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
Selecting the Correct CMOS PLD .................................. 1-10
Commercial PLDs for Industrial Applications .......................... 1-22
Chapter 2
PAL Device Data Sheets ......................................... 2-1
16R8
PAL1SR8 Family ........................................ 2-3
PAL 1SR8-4 Com'l Series ................................. 2-1S
PAL 1SL8-4/5
PAL 1SR8-4/5
PAL 1SRS-4/5
PAL 1SR4-4/5
PAL1SR8-7 Com'l Series ................................. 2-18
PAL 1SL8-7
PAL 1SR8-7
PAL 1SRS-7
PAL 1SR4-7
PAL 1SR8D/2 Com'l Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-20
PAL 1SL8D/2
PAL1SR8D/2
PAL1SRSD/2
PAL1SR4D/2
PAL 1SR8B Com'l Series ................................. 2-22
PAL1SL8B
PAL16R8B
PAL1SRSB
PAl16R4B
PAL 16R8B-2 Com'[ Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24
PAL 16L8B-2
PAL16R8B-2
PAL 16R6B-2
PAL1SR4B-2
PAL 16R8A Com'l Series ................................. 2-26
PAL1SL8A
PAL16R8A
PAL 1SRSA
PAL16R4A
PAL 1SR8B-4 Com'l Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-28
PAL1SL8B-4
PAL1SR8B-4
PAL1SR6B-4
PAL16R4B-4
PAL16R8-10/12 Mil Series ................................ 2-30
PAL 16L8-10/12
PAL16R8-10/12
PAL16R6-10/12
PAL 16R4-1 0/12
Table of Contents
v
l1 AMD
PAL16R8B Mil Series ............ , .......................
PAL16L8B
PAL16R8B
PAL16R6B
PAL16R4B
PAL16R8B-2 Mil Series ..................................
PAL16L8B-2
PAL16R8B-2
PAL16R6B-2
PAL16R4B-2
PAL16R8A Mil Series ....................................
PAL16L8A
PAL16R8A
PAL16R6A
PAL16R4A
PAL 16R8B-4 Mil Series ........ . . . . . . . . . . . . . . . . . . . . . . . . ..
PAL16L8B-4
PAL 16R8B-4
PAL 16R6B-4
PAL 16R4B-4
vi
2-32
2-34
2-36
2-38
16V8
PALCE16V8 Family ..................................... 2-48
PALCE16V8H-5 Com'l ................................ 2-58
PALCE16V8H-7 Com'l ................................ 2-60
PALCE16V8H-10 Com'l ............................... 2-62
PALCE16V80-10 Com'l ............................... 2-64
PALCE16V8H-15/25 0-15/25 Com'l ..................... 2-66
PALCE16V8H-15 Mil .................................. 2-68
PALCE16V8H-20/25 Mil ............................... 2-70
PALLV16V8-10 Com'l ................................... 2-79
PALCE16V8Z Family .................................... 2-95
PALCE16V8Z-15 Com'l, INO .......................... 2-104
PALCE16V8Z-25 Com'l, INO .......................... 2-106
PALLV16V8ZFamily ................................... 2-115
PALLV16V8Z-25INO ................................ 2-124
PALLV16V8Z-30 INO ................................ 2-126
PALCE16V8HO-15 Com'l ................................ 2-135
18P8
AmPAL18P8B/AUNL Com'l ............................. 2-155
20R8
PAL20R8 Family ......................................
PAL20R8-5 Com'l Series ................................
PAL20L8-5
PAL20R8-5
PAL20R6-5
PAL20R4-5
PAL20R8-7 Com'l Series ................................
PAL20L8-7
PAL20R8-7
PAL20R6-7
PAL20R4-7
PAL20R8-10/2 Com'l Series .............................
PAL20L8-10/2
PAL20R8-10/2
PAL20R6-10/2
PAL20 R4-1 0/2
Table of Contents
2-165
2-178
2-180
2-182
AMD
20V8
~
PAL20R8B Com'l Series ................................
PAL20L8B
PAL20R8B
PAL20R6B
PAL20R4B
PAL20R8B-2 Com'l Series ...............................
PAL20L8B-2
PAL20R8B-2
PAL20R6B-2
PAL20R4B-2
PAL20R8A Com'l Series ................................
PAL20L8A
PAL20R8A
PAL20R6A
PAL20R4A
PAL20R8-10/12 Mil Series ...............................
PAL20L8-10/12
PAL20R8-10/12
PAL20R6-10/12
PAL20R4-10/12
PAL20R8-15 Mil Series .................................
PAL20L8-15
PAL20R8-15
PAL20R6-15
PAL20R4-15
PAL20R8B-2 Mil Series .................................
PAL20L8B-2
PAL20R8B-2
PAL20R6B-2
PAL20R4B-2
PAL20R8A Mil Series ...................................
PAL20L8A
PAL20R8A
PAL20R6A
PAL20R4A
2-184
PALCE20V8 Family ....................................
PALCE20V8H-5 Com'l ...............................
PALCE20V8H-7 Com'l ...............................
PALCE20V8H-10 Com'l ..............................
PALCE20V80-10 Com'l ..............................
PALCE20V8H-15/25 0-15/25 Com'l ....................
PALCE20V8H-15 Mil .................... , ............
PALCE20V8H-20/25 Mil ..............................
2-204
2-214
2-216
2-218
2-220
2-222
2-224
2-226
2-186
2-188
2-190
2-192
2-194
2-196
20RA10 PALCE20RA10H-20 Com'l, INO .......................... 2-236
22P10
AmPAL22P1 OB/AUA Com'l .............................. 2-249
22V10
PAL22V10 Family, AmPAL22V10/A ........................
PAL22V10-7Com'l ................................ :.
PAL22V10-10 Com'l .................................
PAL22V10-15 Com'l .................................
AmPAL22V1 OA Com'l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PAL22V10-12 Mil ...................................
PAL22V10-20 Mil ...................................
AmPAL22V10/A Mil ..................................
Table of Contents
2-258
2-266
2-268
2-270
2-272
2-274
2-276
2-278
vii
~AMD
PALCE22V10 Family ...................................
PALCE22V10H-5 Com'l ..............................
PALCE22V10H-7 Com'l ..............................
PALCE22V10H-10 Com'l .............................
PALCE22V10Q-10 Com'l .............................
PALCE22V10H-15/25 0-15/25 Com'l ...................
PALCE22V10H-15/20/25/30 Mil ........................
PALCE22V10Z Family ..................................
PALCE22V10Z-15IND' ....... ; .......................
PALCE22V10Z-25 Com'l, IND .........................
PALLV22V10Z-25IND ..................................
2-286
2-294
2-296
2-298
2-300
2-302
2-304
2-313
2-320
2-322
2-331
24V10
PALCE24V10H-15/25 Com'l ............................. 2-345
26V12
PALCE26V12H-15/20 Com'l .................. '........... 2-360
29M16
PALCE29M16H-25 Com'l ................................ 2-377
29MA16 PALCE29MA16H-25 Com'l .............................. 2-399
610
viii
PALCE610 Family ..................................... 2-424
PALCE610H-15/25 Com'l ............................. 2-432
PALCE610H-20 Mil ..... '............................. 2-434
Chapter 3
MACH Devices ...................... : . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
MACH 1 and 2 Device Families ..................................... 3-3
MACH110-12/15/20 ...................................... 3-7
MACH120-15/20 ......................................... 3-9
MACH130-15/20 ........................................ 3-11
MACH210A-10, MACH21 0-12115/20, MACH210AQ-15/20 ....... 3-13
MACHLV210A-15/20 ................. '.' ................. 3-15
MACH220-12/15/20 ..................................... 3-17
MACH230-15/20 ........................................ 3-19
MACH215-12/15/20 ..................................... 3-21
MACH 3 and 4 Device Families .................................... 3-23'
MACH435-15/20, 0-25 ................................... 3-27
MACH355-15/20 ........................................ 3-29
MACH445-15/20 ........................................ 3-31
MACH465-15/20 ........................................ 3-33
Chapter 4
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Inside AMD's CMOS PLD Technology ................................ 4-3
Military PAL Devices ..........".................................. 4-43
Military ProPAL Devices ........................................ ; 4-52
Electrical Characteristic Definitions ....................... . . . . . . . . .. 4-54
fMAX Parameters ................................................ 4-57
Physical Dimensions ............................................ 4-58
Table of Contents
AMD~
Chapter 5
Design and Testability . .......................................... 5-1
Basic Design with PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
PLD Design Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
PLD Design Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-16
Combinatorial Logic Design .................................. 5-27
Registered Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-40
State Machine Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-60
Testability ............................................. '........ 5-73
Ground Bounce ................................................ 5-92
Metastability .......... : ........................... , ............ 5-95
Latchup ...................................................... 5-97
Converting Bipolar PLD Designs to CMOS .......................... 5-100
High-Speed-Board Design Techniques ............................. 5-107
Minimizing Power Consumption with Zero-Power PLDs .... , ........... 5-135
Designing with the PALCE16V8HD .............................. " 5-138
Chapter 6
Appendices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
Logic Reference Guide ........................................... 6-3
Signal Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-25
Glossary ......................................... , . . . . . . . . . . .. 6-30
Worldwide Application Support .................................... 6-37
Table of Contents
Ix
~
AMD
1
INTRODUCTION
Product Overview
Selecting
the Corre~~
cOMos PLD
0
0
0
0
0
0
0
0
Commercial PLDs for Industrial Ap~ii~~ii~~~
0
0
0:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
000000
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
00000
0
0
0
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000
0
0
0000000000000000000000000000000
Introduction
0
1-3
1-10
1-22
1·1
~AMD
1·2
Introduction
PRODUCT OVERVIEW
Advanced
Micro
Devices
Advanced Micro Devices offers the industry's widest variety of Programmable Logic
Devices (PLDs), implemented in a variety of technologies. In this section, we will briefly
discuss the device families, and look at the various architecture, speed, and power
options. More specific device information can be found in the individual data sheets.
Discussions on some of the special architectural features of many of the devices can
also be found in their respective data sheets.
There are six basic PLD areas addressed by Advanced Micro Devices' PLDs:
•
High-speed PAL® devices
•
Universal PAL devices
•
Industry-standard PAL devices
•
Low-power PAL devices
•
Asynchronous PAL Devices
•
High-density PLDs
The largest application area is that covered by the Programmable ArrayLogic (PAL)
devices. There is a wide variety of PAL devices, ranging from simple devices that
address general logic design problems to more sophisticated devices that deal with
more complex problems.
The area of high-density PLDs is addressed by the MACH® devices which provide a
PLD with thousands of gates and very high performance. The Macro Array CMOS
High-density (MACH) devices are described briefly Chapter 3. Further information on
AMD's MACH product line may be found by obtaining the MACH 1 and 2 Family Data
Book (14051) and the MACH 3 and 4 Family Data Book (17466). MACH design
assistance is available by obtaining the MACH Technical Briefs Manual (15972) and the
MACH Devices Applications Handbook (17020). Development Assistance is available
through the FusionPLDsM Partners Catalog (15585).
Product Overview
1-3
~
AMD
HIGH·SPEED PAL DEVICES
AMD offers the fastest PAL devices on the market today. We were the first to introduce
the PAL device in 1975 and have been the first to market with volumes on all successive
generations. As the market leader in the PLD arena, we fully expect to introduce even
faster devices in the future.
Currently, we have the bipolar TIL PAL16RSfamily of 20-pin devices in 5-ns speed
grade and the PAL20RS family of 24-pin devices, also in 5-ns speed grade, available in
volume production. For extra performance we also have the 16RS family at 4.5 ns, when
packaged with the high-performance 2S-pin PLCC pinout. These families include, both
registered (16R4, 16R6, 16RS, 20R4, 20R6, 20RS) and combinational devices (16LS,
20LS). They are used in a wide variety of applications where performance and space
are critical, often replacing SSIIMSllogic circuits. For applications where the absolute
fastest devices are not needed, other speed grades are offered at a lower cost and/or
lower power consumption.
AMD's Electronically Erasable (EE) CMOS process also provides ~igh-speed universal
PAL devices. The PALCE16VS, PALCE20VS, and PALCE22V10 have a 5-ns version;
most other EE CMOS devices have a 7.5- or 10-ns tPD, while using half or even a
quarter of the power required by their bipolar equivalents.
Table 1·1
High-Speed PAL Devices
Commercial Specifications
Functional Description
Part
Number
Pin
Count
Array Inputs
Array Outputs
bldlr.
dedctd.
reg. fdbk.
reg. comb. macrocell
Prod. Terms
per Output
Spd/Pwr tPD
Options (ns)
fMAX·
(MHz)
lee
(mA)
PAL16L8
20
6
10
-
-
8
-
7
-4
4.5
125
210
PAL16R8
20
-
8
8
8
-
-
8
-5
5
117
210
PAL16R6
20
2
8
6
6
2
PAL16R4
20
4
8
4
4
4
-
7~
PALCE16V8
20
O~
8-10
8-0
-
-
8
7~
H-5
5
142.8
125
PAL20L8
24
6
14
-
8
-
7
-5
5
117
210
PAL20R8
24
-
12
8
8
-
-
8
PAL20R6
24
2
12
6
6
2
-
7~
-
7~
7~
PAL20R4
24
4
12
4
4
4
PALCE20V8
24
O~
12-14
8-0
-
-
8
7~
H-5
5
142.8
125
PALCE24V10
28
0-10
14-16
10-0
-
-
10
7~
H-15
15
45.5
115
PALCE22V10
24
0-10
12
10-0
-
-
10
8-16
H-5
5
142.8
115
PAL22V10
24
0-10
12
10-0
-
10
8-16
-7
7.5
91
220
PALCE610
24
0-16
4
16-0
-
-
16
8
H-15
15
45.5
90
·fMAX is defined as 1/(ts + teo) for the external feedback.
1-4
Product Overview
AMD~
UNIVERSAL PAL DEVICES
Have your design needs included a non-standard mix of inputs and outputs or choosing
a variable number of combinatorial/registered/latched inputs and/or outputs for the given
application? How about stocking only one or two PLOs to reduce your inventory costs?
The solution to your problem is AMO's family of universal PAL devices. We pioneered .
the concept of user-programmable output logic macrocells with the PAL22V10. With this
macrocell, you can configure an output for combinatorial or registered operation and
active-low or active-high polarity. This is what makes the PAL22V10 universal, for it can
substitute for virtually all of the standard 24-pin PAL devices on the market. The
PALCE26V12 is a 28-pin version which provides more inputs and outputs for those
designs that don't quite fit into a PAL22V10.
But we did not stop there. A second new feature pioneered with the PAL22V10 is
variable product term distribution; the 10 outputs on this device are arranged in pairs
with 16, 14, 12, 10 or eight product terms on each output. With up to 16 product terms,
the PAL22V10 can implement far more complex logic functions than can be supported
by other 24-pin devices. No wonder the PAL22V10 is the most popular PAL device on
the market today. And now both faster (7.5 ns, 91 MHz) and reprogrammable low-power
CMOS (7.5 ns at 130 rnA; 15 ns at 55 rnA) versions are available from AMO.
The PALCE16V8 and PALCE20V8 are EE CMOS universal devices that have the
additional capability of directly taking the designs of standard 20- and 24-pin PAL
devices, respectively. They provide a cost-effective means of reducing inventory,
lowering power, and reducing risk. The PALCE24V10 extends this architecture to
28 pins.
The PALCE610 adds to the basic macrocell by providing 16 1/0 macrocells that can be
configured with 0, T, J-K, or S-R flip-flops.
The PALCE29M16 further enhances the macrocell concept. Its macrocell can be an
input or an output macrocell that can be configured three ways: combinatorial, latched or
registered. Sixteen of these macrocells are available in a 24-pin 300-mil package. And
eight of the macrocells can be buried, allowing the connecting pins to be used as
dedicated inputs. The PALCE29M16 also offers variable product term distribution.
For those applications where registers and latches are not needed, the AmPAL 18P8
(20 pins) and AmPAL22P1 0 (24 pins) are ideal. These PAL devices with programmable
polarity can flexibly replace almost all standard 20- and 24-pin combinatorial PAL
devices. As a result, they significantly reduce your inventory. They are available in
several speed-power grades to meet most application requirements.
Product Overview
1·5
~
AMD
Table 1·2
Universal PAL Devices
Commercial Specifications
Functional Description
Array Inputs
Array Outputs
Spd/Pwr tpo
Options (ns)
fMAX·
(MHz)
Icc
(mA)
H-5
H-7
0-10
H-10
0-15
H-15
0-25
H-25 .
5
7.5
10
10
15
15
25
25
142.8
100
66.7
66.7
45.5
45.5
37
37
125
115
55
115
55
90
55
90
7-8
H-5
H-7
0-10
H-10
0-15
H-15
0-25
H-25
5
7.5
10
10
15
15
25
25
142.8
100
66.7
66.7
45.5
45.5
37
37
125
115
55
115
55
90
55
90
10
7-8
H-15
H-25
15
25
45.5
37
90
90
-
10
8-16
H-5
H-7
0-10
H-10
0-15
H-15
Z-15
0-25
H-25
5
7.5
10
10
15
15
-15
25
25
142.8
100
83.3
83.3
50
50
50
33.3
33.3
115
115
55
120
55
90
0.015
55
90
-
-
10
8-16
-7
-10
-15
A
7.5
10
15
25
91
71
50
28.5
220
180
180
180
-
-
10
4
H-20
20
37
90
12-0
-
12
8-16
H-15
H-20
15
20
50
40
105
105
4
16-0
-
-
16
8
H-15
H-25
15
25
45.5
37
90
90
8-16
5
16-8
16
8-16
H-25
25
28.5
100
10
-
-
8
8
-
8
B
A
AL
L
15
25
25
35
B
A
AL
15
25
25
Prod. Terms
per Output
Pin
Count
bldlr.
dedctd.
reg. fdbk.
PALCE16V8
20
0-8
8-10
8-0
-
-
8
7-8
PALCE20V8
24
0-8
12-14
8-0
-
-
8
PALCE24V10
28
0-10
14-16
10-0
-
-
PALCE22V10
24
0-10
12
10-0
-
PAL22V10
24
0-10
12
10-0
PALCE20RA10
24
10
10
PALCE26V12
28
0-12
14
PALCE610
24
0-16
PALCE29M16
24
AmPAL18P8
20
Part
Number
AmPAL22P10
24
10
12
reg. comb. macrocell
-
-
-
-
10
-
·fMAX is defined as 1/(ts + teo) for the external feedback.
1·6
Product Overview
8
-
-
-
-
180
180
90
90
180
180
90
AMD~
INDUSTRY-STANDARD PAL DEVICES
As we have increased speed on the TTL PAL devices, we have also reduced the power
consumption on the slower devices by as much as 75 percent. As a result, both the
industry-standard 20-pin and 24-pin PAL device families are available in a variety of
speed and power grades. This allows the designer to select the optimum performance at
the lowest possible cost and power consumption. These 20-pin and 24-pin devices are
used in applications where the advantages of reduced package count, such as higher
reliability and lower power consumption, improve the overall price-performance of the
end-product. Often these benefits are realized by replacing Schottky, ALS, LS and some
CMOS SSI/MSIIogic circuits with these PAL devices.
Table 1·3
Standard PAL Devices
Commercial Specifications
Functional Description
Part
Number
Pin
Count
Array Inputs
bidir.
dedctd.
Array Outputs
reg. comb. macrocell
reg. fdbk.
-
PAl16L8
20
6
10
-
PAL16R8
20
-
8
8
8
PAl16R6
20
8
6
6
2
Prod. Terms
per Output
Spd/Pwr tPD
Options (ns)
fMAX·
(MHz)
Icc
(mA)
8
-
7
8
15
-
-
-
8
8-2
25
25
90
2
-
7-8
A
25
25
180
180
PAl16R4
20
4
8
4
-
7-8
8-4
35
16
55
PAL20L8
24
6
14
-
-
8
-
7
8
15
-
210
PAL20R8
24
-
12
8
8
-
-
8
8-2
25
25
105
PAL20R6
24
2
12
6
6
2
-
7-8
A
25
25
210
PAL20R4
24
4
12
4
4
4
-
7-8
4
4
·fMAX is defined as 1/(ts + teo) for the external feedback.
Product Overview
1-7
~
AMD
LOW-POWER PAL DEVICES
AMD is the only major supplier of programmable logic devices to offer a broad line of
low-power CMOS devices. And we are the only PLD supplier with such a comprehensive CMOS programmable logic line.
There are two basic types of CMOS PAL devices: those that dissipate essentially no
power when in a quiescent state, and faster devices which draw nominal current even
when quiescent. Devices are thus classified as "zero-power" orl'quarter-power."
Zero-power PAL devices are particularly suited for products that are portable or battery
operated. In a standby mode they consume less than 151lA. Quarter-power CMOS
devices can cut system power consumption 50 percent by replacing equivalent CMOS
PAL devices. The PALLV16V8 and PALLV22V10 are devices designated to operate at
3.3 V for battery-operated applications.
Table 1-4
Low-Power PAL Devices
Functional Description
Part
Number
PALCE16V8
Array Inputs
Commercial Specifications
Array Outputs
Pin
Count
bldlr.
dedctd.
reg. fdbk.
20
0-8
8-10
8-0
reg. comb. macrocell
-
-
8
Prod. Terms
per Output
7-8
PALLV16V8
PALCE22Vl0
24
0-10
12
-
10-0
-
10
PALLV22Vl0
·fMAX is defined as 1/(ts + teo) for the external feedback.
1·8
Product Overview
8-16
Spd/Pwr (PD
Options (ns)
fMAX·
(MHz)
Icc
(mA)
0-10
0-15
Z-15
0-25
Z-25
10
15
15
25
25
66.7
45.5
45.5
37
33.3
55
55
0.015
55
0.015
-10
Z-25
Z-30
10
25
30
66.7
33.3
22
90
0.015
0.015
0-15
Z-15
0-25
Z-25
15
15
25
25
50
50
33.3
33.3
55
0.015
55
0.015
Z-25
25
33.3
0.015
AMD~
ASYNCHRONOUS PAL DEVICES
Currently AMD makes three devices that support asynchronous and bus interface
applications.
The PALCE20RA 10 is optimized for asynchronous applications. It contains ten D-type
flip-flops, driven by a PAL array. Each flip-flop has individually programmable Clock,
Reset and Preset product terms. With such features, this device is well suited to
replacing glue logic in your system.
The PALCE29MA16 combines some of the advantages of the PALCE29M16 with the
advantages of the PALCE20RA 10. It has one dedicated Clock/Latch Enable input as
well as product terms for each of the 16 macrocells to allow individual clocking, asynchronous Reset and asynchronous Preset. It also features variable product term
distribution. To top it off, the PALCE29MA16 is electrically reprogrammable in a plastiC
300-mil package.
The PALCE610 is a general purpose PLD. It has 16 independently-configurable
macrocells. Each macrocell can be configured as either combinatorial or registered. The
registers can be D, T, J-K or S-R type flip-flops. The device has 4 dedicated input pins
and 2 clock pins. Asynchronous clocking is available since each clock pin controls 8 of
the 16 macro cells.
Table 1·5
Asynchronous PAL Devices
Commercial Specifications
Functional Description
Part
Number
Pin
Count
Array Inputs
bldir.
dedctd.
Array Outputs
reg. fdbk.
reg. comb. macrocell
-
PALCE20RA10
24
10
10
PALCE29MA16
24
8-16
5
16-8
PALCE610
24
0-16
4
16-0
Prod. Terms
per Output
Spd/Pwr
Options
tPD
(ns)
f MAX•
(MHz)
Icc
(mA)
-
-
10
4
H-20
20
50
90
-
-
16
4-12
H-25
25
28.5
100
-
16
8
H-15
H-25
15
25
45.5
37
90
90
·fMAX is defined as 1/(ts + teo) for the external feedback.
Product Overview
1·9
Selecting the Correct CMOS PLD-An Overview
of Advanced Micro Devices' CMOS PLDs
Application Note
by Steve Holte, Applications Engineer
INTRODUCTION
The purpose of this application note is to provide a survey of AMD's CMOS PLDs (Programmable Logic Devices). This includes both PAL (Programmable Array
Logic)devicesandthemoregeneralrealmofPLDstowhich
PAL devices be long. With the proliferation of parts the selection ofthe best PLDforyour application may seemdifficult.lfyouareanewPLDuser,thisoverviewwillguideyou
through the wide variety of different device architectures,
speed, and power grades. This tutorial should increase
yourunderstandingofthebasiccharacteristicfeaturesthat
make a device appropriate for a given application.
Figure 1 shows a "CMOS PAL Selection Route Map."
This can be used as a convenient model of the discussion throughout this paper. It can also be used as a reference guide when you are selecting a PLD for a
particular application.
The Benefits of AM D's CMOS PLDs
Before addressing individual products, it is important to
understand why CMOS technology is used in PLDs.
There are two universal benefits of AM D's CMOS PLDs:
electrical erasability and low power.
Electrical Erasability
Because PLDs are programmable, electrical erasability
is probably the most important advantage that CMOS
technology can bring. AMD's electrically-erasable
CMOS has benefits that make it superior to both UVerasable CMOS and bipolar technologies. The most important advantage is the ability to erase the device
electrically in a matter of seconds as opposed to hours
for UV-based technologies, and not at all in the case of
bipolar. The chief benefit to the user is a very high quality
device. This is realized through the ability to erase and
reprogram the device many times at various test points
in the factory. In fact, the quality is so good that programming and post-programming functional rejects are virtually non-existent.
1-10
~
Advanced
Micro
Devices
A second major benefit of electrical erasability is the
ease of reprogramming the device by the user. This
saves time when prototyping, and allows for recoverY of
large volumes of devices that may need to be
reprogrammed for a variety of reasons, such as midproduction bug fixes. Erasure takes place automatically
by the device programmer, and is completely transparent to the user.
Low Power
The most well-known attribute of CMOS is low power
consumption. All PALCE (Programmable Array Logic
CMOS Electrically-Erasable) devices are offered in halfpower versions; they require at most halfthe supply current of their first-generation bipolar counterparts. Some
devices are also offered in quarter-power versions. This
is achieved by taking the latest process technology and
designing to favor even lower power over the fastest
speed possible.
CMOS uses less current than bipolar because most of
the current flow only takes place while the transistors
are actually switching. With bipolar, current flows
through the transistors all the time. AMD's half- and
quarter-power CMOS devices take advantage of this as
much as possible. However, in order to achieve high
speed it is necessary to operate some transistors on the
Chip in the linear region. Because this circuitry is essentially always switching, the power consumption does not
go to zero as it would in a conventional CMOS device.
Lower power requirements are ideal for applications
which have tight power budgets, such as mobile telecommunications. Smaller power supplies also reduce
cost and lowers heat dissipation. This results in smaller
cooling fans, or perhaps no fan at all. It also allows the
system designer to pack everything even tighter since
less empty space is needed for air circulation. This can
make the circuit board fit in a smaller package, again
reducing cost.
Publication# 17402 Rev. A
Issue Date: February 1993
Amendment/O
AMD~
Global Clocks
Individual Macrocell
Clocks & Resets/Presets
&
Resets/Presets
Synchronous
More Output Drive
_-......1'-----.,
16V8HD
15 ns
16V8
5f7 .5/10/15/25 ns
More Inputs
Lower Power
More PTs
& I/Os
22V10Z
15/25 ns
20V8
5f7 .5/10/15/25 ns
16V8Z
15/25 ns
Lower Powe
More PTs & I/Os
22V10
5f7 .511 0/15/25 ns
More PTs, I/Os &
Clocks
More Inputs
More PTs
& I/Os
24V10
15/25 ns
26V12
15/20 ns
More Flexibility
More I/Os
Density
610
15/25 ns
MACW U
Family
10/12/15/20 ns
&
Speed
More PTs & I/Os
29M16
25 ns
17402A-l
More Flexibility Means Choice of:
JK, SR, T & D Flipflops, liP & DIP MacroceJ/s, Latch or Reg. MacroceJ/s
III
Asynchronous Clocking
Figure 1. CMOS PAL Selection Route Map
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1-11
~
AMD
Zero-Power
The Selection Process
Some devices are also offered in zero-standby power
versions. Instead of a/ways operating certain transistors
in the linear region to achieve high speed, this circuitry
can shut down and the device goes into standby mode.
Standby mode is defined as anytime the inputs do not
switch for an extended period of time (typically 50 ns).
When this happens the current consumption will almost
go to zero (Icc < 151lA). The outputs will maintain the
current state held while the device is in standby mode.
When selecting a CMOS PLD, start by determining both
the functional and size requirements for your
application.
When any input switches, the internal circuitry is fully enabled and the power consumption returns to normal.
This feature results in considerable power savings for
operation at low to medium frequencies.
Zero-standby devices are desirable for a number of reasons. In portable and field-installed equipment that rely
on batteries, battery life is extended. In solar powered
systems, fewer solar cells are required.
Functional Requirements
The functional requirements of a given application are
what' determine which device architecture should be
used. The functional criteria include such issues as the
clocking scheme, macrocell flexibility and output drive.
The clocking scheme can be synchronous, where qll
registers within a device use the same clock signal, or
asynchronous, where each register can be clocked individually using any logic signal or combination of logic
Signals available to the device. These two alternatives
are illustrated in Figure 2.
elK
a.
Registers with Synchronous Clocking
17402A-2
b. Registers with Asynchronous Clocking
Figure 2. Basic Clocking Schemes
Macrocell flexibility refers to the ability to configure the
output in various ways. A macrocell (Figure 3) takes the
basic sum-of-products logic and adds functionality
through features like storage elements, optional path
Inputs
AND
OR
controls, polarity, and feedback. This concept will be further illustrated as each device macrocell is explained
throughout the selection process.
Macrocell
Outputs
17402A-3
Figure 3. PLD Block Diagram with the Macrocell Included
1-12
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
AMD~
Size Requirements
The combination of number of inputs and outputs required determines the device size that should be used.
The number of product terms required to implement a
particular design also factor into this decision.
The best approach to selecting the appropriate device is
to begin with the simplest and smallest devices and upgrade as necessary to accommodate your application.
Combinatorial and Synchronous
Applications
Starting from the top of the flow chart in Figure 1 and taking the path for synchronous designs leads one to those
devices best suited for simple state machines, encoders, decoders, muxes, and similar logic applications.
Forthese applications, D-type registered or combinatorial (non-registered) logic is needed. The first choice is
the PALCE16V8, PALCE20V8, or PALCE24V10, depending on the number of inputs or outputs needed.
The macrocells (Figure 4) can be configured to use
combinatorial or D-type registered outputs in any combination. The D-type register operates very simply; data
presented at the D input of the register will be clocked
into the register on the rising edge of the clock signal.
The output can be configured as active low- or active
high-output depending on the requirements of the
downstream devices and the efficiency of the logic.
To
~==~--------------------------------------~11
OE
11
Vee
Adjacent
Macrocell
101------....
00
01
(lOX
)------4~
D
QI------~
01-----------..
From
Adjacent
SG1
Pin
17402A-4
Figure 4. PALCE16V8 Macrocell
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1-13
~
AMD
More Product Terms and I/O's
If the application requires the features of the
PALCE16V8 macrocell, but requires more programma- '
ble gale functions, move further down the flowchart. The
next device, the PALCE22V10 (Figure 5) has varied
product term distribution. The number of product terms
varies among outputs, with up to 16 product terms on
some outputs. In addition, it has global synchronous
preset and asynchronous reset product terms. These
are connected to all macrocells configured as registers,
facilitating easy power-up and system reset. This versatility contributes significantly to the 22V10 being the
world's most popular PAL architecture. When combined
with the PALCE16V8 family, these two device families
will likely handle about 80% of PLD applications.
The PALCE26V12, a 28-pin version of the 22V10 increases versatility by adding more inputs and outputs,
and by adding another global clock. Any macrocell can
use one of the two clocks. This allows'the logic to be partitioned giving greater design flexibility. In addition, registered outputs can be configured as bidirectional pins
on the 26V12.
Since historically most applications in bipolar technology had been done in PAL16R8, PAL20R8, and
PAL22V10 families, these types of applications can
easily have their power lowered with half-, quarter-, and
zero-power versions of the PALCE16V8, PALCE20V8,
or PALCE22V10.
••
•
lIOn
Figure 5. PALCE22V10 Macrocell Diagram
Table 1. Summary of the PALCE16V8 and PALCE22V10 Family Architectures
Macrocell
Type
Device
Dedicated
Inputs
I/O's
Clocks
Product
Terms
PALCE24V10
16V8
14
10
1
7-8
7-8
7-8
PALCE22V10
22V10
12
10
1
8-16
PALCE26V12
22V10
14
12
2
8-16
PALCE16V8
16V8
8-10
8
1
PALCE20V8
16V8
10-12
8
1
1-14
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
AMD~
high-output drive capability. This compares to 24 rnA
low-output and 3.2 rnA high-output drive for other
PALCE16V8 devices. The pALCE16V8HD also has
some unique macrocell features. Because this device is
designed to drive a bus, it can be configured with opendrain outputs. Open-drain (open-collector) configuration is sometimes used in bus applications because it
provides controlled VOH, termination, and wire-NOR
capability. Because the PALCE16V8HD is designed to
take inputs directly from a noisy bus, all inputs have
200 mV input threshold hysteresis to improve noise immunity. The inputs can be configured as direct or
latched, making additional buffering devices unnecessary. Additionally, the macrocell can be configured as
either a 0- or T -type register. The T -type register is more
efficient for counter applications because fewer product
terms are consumed as hold states.
Table 2. Summary of the Speed and Power
Requirements for the PALCE16V8, PALCE20V8,
and PALCE22V10 Families of Devices
Device and Speed Grade
Icc
PALCE16V8H-5
125 mA static
PALCE16V8H-7/-10
115 mA at 25 MHz
PALCE 16V8H-15/-25
90 mA at 15 MHz
PALCE 16V8Q-15/-25
55 mA at 15 MHz
PALCE16V8Z-25
15 IlA in standby mode
PALCE20V8H-5
125 mA static
PALCE20V8H-7/-10
115 mA at 25 MHz
PALCE20V8H-15/-25
90 mA at 15 MHz
PALCE20V8Q-15/-25
55 mA at 15 MHz
PALCE22V10H-5
140 mA at 25 MHz
PALCE22V10H-7
140 mA at 25 MHz
PALCE22V1 OH-1 0
120 mA at 25 MHz
PALCE22V10H-15125
90 mA static
PALCE22V1oo-25
55 mA static
PALCE22V1 OZ-25
15 IlA in standby mode
Complex Functions
For those applications that require 0, T, J-K, or S-R register capability, the PALCE610 (Figure 6) has this flexibility. This device has 16 macrocell outputs and four
dedicated inputs. The J-K, S-R, and T registers allow
easy implementation of counters and larger state
machines.
Bus Applications
For applications that require bus interaction, the
PALCE16V8HD features 64 rnA low-output and 16 rnA
1/016
1/015
1/014
1/013
1/012
1/011
1/010
1109
CLK1
17402A-6
Figure 6. PALCE610 Block Diagram
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1-15
~
AMD
More Flexibility
Moving down to the bottom of the flow chart reveals a
more flexible device than the PALCE610. Applications
that make use of embedded, or buried, registers can
take advantage of the PALCE29M16 (Figure 7). Buried
register operation is very useful when a state machine
uses state bits that do not need to be brought outside the
chip. This allows the pin associated with the macrocell to
be available as an input. Eight of the 16 macrocells have
dual feedback capability. This means that these macrocells have two independent feedback paths: one from
the register and one from the 1/0 pin. The other eight
macrocells have single feedback, where both paths are
available but, only one or the other can be used. Since
almost every pin is an 1/0 pin this device has 29 available inputs to the programmable AND array.
17402A-7
Figure 7. PALCE29M16 Block Diagram
1-16
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
AMD~
The macrocells (Figure 8) can be configured as latches
or registers. Latch operation allows the flip-flop in the
macrocell to become transparent while the latch is enabled. When the latch is disabled, the flip-flop will hold
the current state. This kind of operation is useful in sample and hold applications. Also, the register or latch may
be used with the macrocelJ input pin for synchronizing
signals. The active level of the latch enable, as well as
the clock edge (rising or falling) are both programmable.
Like the PALCE22V1 0, there is varied product term distribution among the macrocells. Also, preload capability
is available using a global product term to define the
preload condition. Preload capability aIJows arbitrary
states to be loaded directly into the register, making it
unnecessary to cycle through long, complex vector sequences to get the device in a particular state. This is
normally only performed by the device programmer
when it performs functional tests. The preload product
term allows preload to be engaged by hand, without the
need for supervoltages (voltages above Vee needed to
engage preload on most PLDs).
~~~~?~----------------------------------~~
OE PTs FOR BANKS {
OF 4 MACROCELLS
COMMON
ASYNCHRONOUS
PRESET
Po
t---------t.,;>o-...----tC>II/OX
I1CLKlLE -
........- t
COMMON
ASYNCHRONOUS
RESET
TOANO ARRAY
:===~
______________
~RX
TOANO ARRAY
17402A-8
Figure 8. PALCE29M16 Macrocell Diagram
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1-17
~
AMD
Asynchronous Applications
Starting at the top of the flow chart again, but this time
taking the path for asynchronous applications, you will
find PALCE20RA10. The PALCE20RA10 is the simplest of the asynchronous devices. Each macrocell
(Figure 9) is clocked individually using one product term
per macrocell. Also, reset, preset, and output enable are
controlled individually with one product term each.
There is also a global output enable pin which is combined with the product term enable to determine if the
output is enabled or disabled.
A dedicated global preload pin allows all registered macroce lis to be preloaded simultaneously using normal
TTL levels.
The PALCE610 has the distinction of bridging the gap
between synchronous and asynchronous registerclocking. The PALCE61 0 macrocells can be clocked via individual product terms for each macrocell, or the
macrocells can be clocked in banks of eight via two dedicated clocks. This is done by using a clock/output enable mux (Figure 10). If the macrocell is configured as
PL
combinatorial or as a synchronous register, output enable/disable is controlled by a product term. If asynchronous register mode is desired, the same product term is
used as a clock and the macrocell is always enabled.
As mentioned above, the PALCE610 can act as a synchronous or asynchronous PAL device. As shown, a
special function product term can be steered to control
either the output enable orthe macrocell clock. In the latter mode, each register can be individually clocked.
If your application requires the basic features of the
PALCE29M 16, except with individual macrocell control,
the PALCE29MA16 (Figure 11) should be considered.
Four product terms in each macrocell are dedicated to
control clocking, output enable, asynchronous reset,
and asynchronous preset. These functions are controlled either globally or in blocks on the PALCE29M16.
A common clock pin and output enable pin are still maintained, but the user has a choice of using eitherthe common control pin or individual macrocell control via the
control product term.
OE
Output
17402A-9
Figure 9. PALCE20RA10 Macrocell Diagram
1-18
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
AMD~
Vee
---------~
CLK-----i
17402A-l0
o Register
Figure 10. PALCE610 Macrocell (Configured as aD-Register)
with the Output Enable/Clock Mux
e~~~~
_____________________________________
~
INDIVIDUAL OE
INDIVIDUAL
ASYNCHRONOUS
PRESET
Po
t---------iI~.....---1<-,;>II/OFx
COMMON
CLKlLE (PIN)
INDIVIDUAL
CLK/IE"
INDIVIDUAL
ASYNCHRONOUS
RESET
TO AND ARRAY ::==~--
__
-----....J
RFx
TO AND ARRAY
17402A-ll
Figure 11. PALCE29MA16 Macrocell
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1-19
~
AMD
MACH Devices
At the bottom of the flow chart, both the synchronous
and asynchronous design paths converge into the
MACH Family. MACH devices extend AMD's PLD offerin~s into t.he rea!m of what is referred to as mid-density.
Mid-density deVices allow multiple smaller PLD designs
to be consolidated into one device. Mid-density covers
replacement of just a couple of smaller PAL devices, all
th.e way up to designs that would traditionally be done
With small gate arrays. These devices span from 900 to
3600 gates, with 32 to 64 macrocells, and are offered in
44- to 84-pin packages.
MACH devices use PAL blocks that are interconnected
using a switch matrix. The members of the families are
differentiated by the number of pins, macrocells, clocks,
and the amount of interconnect. The MACH 1 family has
output macrocells; the MACH 2 family has output and
buned macrocells. All signals, whether registered or
combinatorial can be buried. The basic macrocell, common to both families resembles the PALCE22V10 macroc~1I with the additional choice of using D- or T-type
registers. The MACH210 is illustrated in Figure 12.
1/00-1/07
2
44 x 68
AND Logic Array
and
Logic Allocator
Switch Matrix
44 x 68
44 x 68
AND Logic Array
and
Logic Allocator
AND Logic Array
and
Logic Allocator
OE
OE
2
1/024-1/031
1/016-1/023
CLKo/12,
CLK1/1s
17402A-12
Figure 12. MACH210 Block Diagram
1-20
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
AMD~
Both synchronous and asynchronous versions are
available. The asynchronous 'MACH215 macrocell
looks more like a PALCE20RA10 macrocell, rather than
PALCE22V10 type macrocells. The synchronous devices are better suited to structured designs; the asynchronous MACH215 is better suited for random logic
collection.
All MACH devices have the advantage of fast (10, 12,
15, and 20 ns), predictable timing, which is au nique advantage when compared to other mid-density PLDs.
SUMMARY
Selecting the appropriate PLD for a given application involves matching your requirements with various device
capabilities. Following the guidelines in this article along
with the "CMOS PAL Selection Route Map" makes it
easier.
AMD's wide array of electrically-erasable CMOS PLDs,
combined with strong third party support through our
FusionPLDsM relationships, means an excellent selection of devices, software, and programming hardware.
This gives you a virtual toolbox of solutions for your system logiC requirements, along with the strong technical
support you expect.
Selecting the Correct CMOS PLD-An Overview of Advanced Micro Devices' CMOS PLDs
1·21
COMMERCIAL PLDs FOR INDUSTRIAL
APPLICATIONS
l1
Advanced
Micro
Devices
Customers have expressed an interest in using AMD programmable logic devices over
the industrial temperature range. To serve your need, we recommend the following:
1. Use any standard commercial device from the following family datasheets:
PALCE16V8
PALCE20V8
PALCE22V10
PALCE610
2. Slow down all commercial timing parameters by 20%.
3. Add 20 mA to the commercial Icc.
All s~andard AMD warranties will apply to products used as noted above at Vee of +5 V
±10% over the temperature range of -40°C to 85°C.
This approach will allow you to use broadly available commercial devices to fill your
industrial temperature needs at no price premium. We are able to assure the performance to specification of these products since they are characterized and monitored over
the full military temperature range (-55°C to 125°C).
1·22
Commercial PLDs For Industrial Applications
2
PAL DEVICE DATA SHEETS
PAL 16R8 Family ......................................................... 2-3
PALCE16V8 Family ..................................................... 2-48
PALLV16V8-10 .......................................................... 2-79
PALCE16V8Z Family .................................................... 2-95
PALLV16V8Z Family ................................................... 2-115
AmPAL 18P8B/AUAlL ................................................... 2-155
PAL20R8 Family ....................................................... 2-165
PALCE20V8 Family .................................................... 2-204
PALCE20RA10H-20 .................................................... 2-236
AmPAL22P10B/AUA ................................................... 2-249
PAL22V10 Family/AmPAL22V10A ......................................... 2-258
PALCE22V10 Family ................................................... 2-286
PALCE22V10Z Family .................................................. 2-313
PALLV22V10Z-25 ...................................................... 2-331
PALCE24V10H-15/25 ................................................... 2-345
PALCE26V12-15/20 .................................................... 2-360
PALCE29M16H-25 ..................................................... 2-377
PALCE29MA16H-25 .................................................... 2-399
PALCE610 Family ..................................................... 2-424
PAL Device Data Sheets
2·1
~AMD
2·2
PAL Device Data Sheets
_
COM'L: -4/5f7/B/B-2/A, 012
~
MIL: -10/12/B/B-2/A1B-4
Advanced
Micro
Devices
PAL 16R8 Family
20-Pin TTL Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
As fast as 4.5 ns maximum propagation delay
Popular 20-pln architectures: 16L8, 16R8,
16R6,16R4
•
Programmable replacement for high-speed
TTL logic
•
•
Register preload for testability
Power-up reset for Initialization
•
Extensive third-party software and
programmer support through FusionPLD
partners
•
•
2o-Pln DIP and PLCC packages save space
2B-Pln PLCC-4 package provides ultra-clean
high-speed signals
GENERAL DESCRIPTION
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,
PAL 16R4) includes the PAL 16R8-5/4 Series which provides the highest speed in the 20-pin TTL PAL device
family, making the series ideal for high-performance applications. The PAL 16R8 Family is provided with standard 20-pin DIP and PLCC pinouts and a 28-pin PLCC
pinout. The 28-pin PLCC pinout contains seven extra
ground pins interleaved between the outputs to reduce
noise and increase speed.
The devices provide user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The family allows the systems engineer to implement
the design on-chip, by opening fuse links to configure
AND and OR gates within the device, according to the
desired logic function. Complex interconnections between gates, which previously required time-consuming
layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AN D array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
In addition, the PAL device provides the following
options:
- Variable input/output pin ratio
- Programmable three-state outputs
- Registers with feedback
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state. Registers consist of O-type flip-flops that are
loaded on the LOW-to-HIGH transition of the clock. Unused input pins should be tied to Vee or GND.
The entire PAL device family is supported by the
FusionPLD partners. The PAL family is programmed on
conventional PAL device programmers with appropriate
personality and socket adapter modules. Once the PAL
device is programmed and verified, an additional connection may be opened to prevent pattern readout. This
feature secures proprietary circuits.
PRODUCT SELECTOR GUIDE.
Device
Dedicated
Inputs
Outputs
PAL16La
10
6 comb.
7
7
a
2 comb.
a
7
4 reg.
4 comb.
a
7
2 comb.
PAL16Ra
a
a reg.
PAL16R6
a
6 reg.
PAL16R4
a
Publication# 16492 Rev. B Amendment/O
Issue Date: June 1993
Product Termsl
Output
Feedback
Enable
I/O
-
prog.
prog.
reg.
pin
reg.
I/O
pin
prog.
reg.
I/O
pin
prog.
2-3
~AMD
BLOCK DIAGRAMS
PAL16L8
INPUTS
PROGRAMMABLE
AND ARRAY
(32 x 64)
16492B-1
PAL16R8
elK
INPUTS
PROGRAMMABLE
AND ARRAY
(32 x 64)
16492B-2
2·4.
PAL16R8 Family
AMD~
BLOCK DIAGRAMS
PAL16R6
ClK
INPUTS
PROGRAMMABLE
AND ARRAY
(32 x 64)
16492B-3
ClK
PAL16R4
PROGRAMMABLE
AND ARRAY
(32
x 64)
16492B-4
PAL16R8 Family
2-5
~AMD
CONNECTION DIAGRAMS
Top View
20-Pin PLCC
DIP
(NOTE 1)
w
Vee
11
12
(NOTE 10)
W
I-
01-
~>
~
o (,)
(,)
(NOTE 9)
13
(NOTE 8)
14
(NOTE 7)
18
(NOTE 9)
15
(NOTE 6)
17
(NOTE 8)
16
(NOTE 5)
16
(NOTE 7)
17
18
(NOTE 4)
15
(NOTE 6)
(NOTE 3)
14
(NOTE 5)
GND
(NOTE 2)
9 10 11 12 13
164928-5
164928-6
28-Pin PLCC
18
GND
(NOTE 2)
(NOTE 3)
GND
(NOTE 4)
GND
PIN DESIGNATIONS
11
ClK
GND
I
I/O
(NOTE 1)
Vee
21
(NOTE 10)
GND
(NOTE 9)
o
GND
Vee
Clock
Ground
Input
Input/Output
Output
Output Enable
Supply Voltage
OE
Note:
Pin 1 is marked for orientation.
164928-7
2-6
Note
16L8
16R8
16R6
16R4
1
10
elK
elK
elK
2
19
OE
OE
OE
3
01
01
1/01
1/01
4
1/02
02
02
1/02
5
1/03
03
03
03
6
1/04
04
04
04
7
1105
05
05
05
8
1/06
06
06
06
9
1/07
07
07
1/07
10
Os
Os
I/0s
lias
PAL16R8 Family
AMO~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
T
16
-r-
R 8
-I'""
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUTTYPE _ _ _ _ _ _ _ _-1
-5
"
"r-
P C
t
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (O°C to +7S°C)
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
28-Pin Plastic Leaded Chip
Carrier for -4 (PL 028)
D = 20-Pin Ceramic DIP (CD 020)
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS _ _ _ _ _ _----J
SPEED
-4 = 4.S ns tPD
-S =S ns tPD
-7 = 7.S ns tPD
D= 10 nstpD
VERSION
Blank = First Revision
12 = Second Revision
Valid Combinations
PAL16L8
PAL16R8
-SPC, -SJC, -4JC
PAL 16R6
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of .
specific valid combinations and to check on newly
released combinations.
PAL16R4
PAL16L8-7
PAL16R8-7
PC, JC, DC
PAL16R6-7
PAL16R4-7
PAL16L8D/2
PAL16R8D/2
PC,JC
PAL16R6D/2
PAL16R4D/2
PAL16RS-4/S/7, 0/2 (COm'l)
2-7
~AMD
ORDERING INFORMATION
Commercial Products (MMI Marking Only)
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
_____
T...J.
16
-r-
R 8 B -2 C N
-r-
I'" -I'"
•
_
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _ _-...J
~
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS - - - - - - - '
OPTIONAL PROCESSING
Blank = Standard Processing
PACKAGE TYPE
N = 20-Pin Plastic DIP
(PO 020)
NL = 20-Pin Plastic Leaded
Chip Carrier (PL 020)
J
= 20-Pin Ceramic DIP
(CD 020)
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
SPEED
B = Very High Speed (15 ns-35 ns tpo)
A = High Speed (25 ns-35 ns tpo)
-------------.....1
POWER
Blank = Full Power (155 mA-180 mA Icc)
-2
= Half Power (80 mA-gO mA Icc)
-4
= Quarter Power (55 mA Icc)
Valid Combinations
PAL16L8
PAL16R8
PAL16R6
B. B-2. A.
B-4
CN. CNL. CJ
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Note: Marked with MMllogo.
PAL16R4
2-8
PAL 16R8/B/B-2/A/B-4 (Com'l)
AMD~
ORDERING INFORMATION
APL Products
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options.
APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid
Combination) is formed by a combination of:
PAL
FAMILY TYPE-PAL = Programmable Array Logic
T
16
-r-
R
-r-
8
r-
R
-10 IB'
-r- .r-
NUMBER OF _ _ _ _ _ _ _- - 1
A
L
LEAD FINISH
A = Hot Solder Dip
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _ _- - - l
PACKAGE TYPE
R = 20-Pin Ceramic DIP
(CD 020)
2 = 20-Pin Ceramic
Leadless Chip Carrier
(CL 020)
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS - - - - - - - - - - '
SPEED-----------------~
-10 = 10 ns tPD
-12 = 12nstpD
DEVICE CLASS
IB = MIL-STD-883C Class B
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PAL16L8
PAL16R8
-10, -12
IBRA,/B2A
PAL16R6
PAL16R4
Military Burn-In
Group A Tests
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions
A through E. Test conditions are selected at AMD's
option.
PAL 16R8·1 0/12 (Mil)
Group A tests consist of Subgroups
1, 2, 3, 7, 8, 9, 10, 11.
2·9
~AMD
ORDERING INFORMATION
APL Products (MMI Marking Only)
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination)
is formed by a combination of:
___T
PAL
16
R 8 B -2 M
---~
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _----1
J 1883B
l
PACKAGE TYPE (Per 09-000)
J = 20-Pin Ceramic DIP
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS
OPTIONAL PROCESSING
/8838 = MIL-STD-883, Class 8
(CD 020)
W = 20-Pin Ceramic Flatpack
(CFL020)
L = 20-Pin Ceramic Leadless
Chip Carrier (CL 020)
---------1
SPEED
8 = Very High Speed (20 ns-50 ns tpo)
A = High Speed (30 ns-50 ns tpo)
OPERATING CONDITIONS
M = Military
POWER
81ank = Full Power (180 mA Icc)
-2
= Half Power (90 mA Icc)
-4
= Quarter Power (55 mA Icc)
Valid Combinations
PAL16L8
PAL16R8
PAL16R6
8,
8-2,
A,8-4
MJ/8838,
MW/8838,
MU8838
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Note: Marked with MMllogo.
PAL16R4
Group A Tests
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions
A through E. Test conditions are selected at AM D's
option.
2-10
PAL 16R8B/B-2/A/B-4 (Mil)
Group A tests consist of Subgroups
1, 2, 3, 7, 8, 9, 10, 11.
AMD~
FUNCTIONAL DESCRIPTION
Standard 20-Pin PAL Family
Registers with Feedback
The standard bipolar 20-pin PAL family devices have
common electrical characteristics and programming
procedures. Fourdifferent devices are available, including both registered and combinatorial devices. All parts
are produced with a fuse link at each input to the AND
gate array, and connections may be selectively removed by applying appropriate voltages to the circuit.
Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to
any customized pattern. Extra test words are preprogrammed during manufacturing to ensure extremely
high field programming yields, and provide extra test
paths to achieve excellent parametric correlation.
Pinouts
The PAL 16R8 Family is available in the standard 20-pin
01 P and PLCC pinouts and the PAL 16R8-4 Series is
available in the new 28-pin PLCC pinout. The 28-pin
PLCC pinout gives the designer the cleanest possible
signal with only 4.5 ns delay.
The PAL 16R8-4 pinout has been designed to minimize
the noise that can be generated by high-speed signals.
Because of its inherently shorter leads, the PLCC package is the best package for use in high-speed designs.
The short leads and multiple ground signals reduce the
effective lead inductance, minimizing ground bounce.
Placing the ground pins between the outputs optimizes
the ground bounce protection, and also isolates the outputs from each other, eliminating cross-talk. This pinout
can reduce the effective propagation delay by as much
as 20% from a standard DIP pinout. Design files for
PAL 16R8-4 Series devices are written as if the device
had a standard 20-pin DIP pinout for most design software packages.
Variable Input/Output Pin Ratio
The registered devices have eight dedicated input lines,
and each combinatorial output is an 1/0 pin. The
PAL 16L8 has ten dedicated input lines and six of the
eight combinatorial outputs are 1/0 pins. Buffers for device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GNO.
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. On combinatorial outputs, a product term
controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional
1/0 pin and may be configured as a dedicated input if the
output buffer is always disabled. On registered outputs,
an input pin controls the enabling of the three-state
outputs.
Registered outputs are provided for data storage and
synchronization. Registers are composed of D-type
flip-flops that are loaded on the LOW-to-HIGH transition
of the clock input.
Register Preload
The register on the PAL 16R8 Family can be preloaded
from the output pins to facilitate functional testing of
complex state machine deSigns. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL 16R8 Family
will be HIGH due to the active-low outputs. The Vcc rise
must be monotonic and the reset delay time is 1000 ns
maximum.
Security Fuse
After programming and verification, a PAL 16R8 Family
design can be secured by programming the security
fuse. Once programmed, this fuse defeats read back of
the internal programmed pattern by a device programmer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will
read as if every fuse is programmed.
Quality and Testability
The PAL 16R8 Family offers a very high level of built-in
quality. Extra programmable fuses provide a means of
verifying performance of all AC and DC parameters. In
addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Technology
The PAL16R8-5, -7 and 0/2 are fabricated with AMO's
oxide isolated bipolar process. The array connections
are formed with highly reliable PtSi fuses. The
PAL 16R8B, B-2, A and B-4 series are fabricated with
AMO's advanced trench-isolated bipolar process. The
array connections are formed with proven TiW fuses for
reliable operation. These processes reduce parasitic
capacitances and minimum geometries to provide
higher performance.
PAL16R8 Family
2-11
~AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16L8(-4)
~Vcc
10 1
(24)
0
3
4
7 8
11 12
1516
1920
2324
2728
(23)
31
0
1
.....
\
19
(22)
J
7
~
m--t:c
(25)
8
~rO
J
8
~
L
-=
18
(20)
15
3
(26)
<.
.>
16
1
\
I
~
1
.....
.
~
1
t )--vo-
39
5
>
.~.rO
- (13)
J
.....
I
...
~
<.t--'
48
l
~
I>
\
55
8
~
(4)
56
~
14
(12)
rD GND
-= (11)
13
(10)
~rO GND
-= (9)
J
-:l> .....
...
\
I
~
GND~
.....
GND
...
63
(6)
(15)
40
47
18 9
(5)
-=
(14)
.J
~
\
7
(3)
16 1/°5
(16)
~rD GND
32
b
6
(2)
- (17)
.-J
31
0(1)
17
(18)
rD GND
<.
24
\
5
(28)
GND
ill
- (19)
~
23
4
(27)
GND
(21)
3
4
7 8
11 12
1516
1920
2324
2728
12
(8)
11 19
(7)
31
-=
164928-8
2·12
PAL16R8 Family
AMD~
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16R8 (-4)
2
~Vee
(23 )
elK 1~
(24) .....
0
3
4
7 8
11 12
1516
1920
23 24
2728
31
0
"'"
Q
7
~
~
L./
I-'
15
3
(26)
.>
23
~
..>
~
[.J'
31
5
(28)
Vee
>
L./
(1)
39
..... >~
6
>
(2)
40
<
~
"'"
t...../
47
....>
...
(20)
~
M
~
h
~
h
~
~
~
H
~
~
48
.J
55
8
(4)
~
h
32
0
7
(3)
(21 )
24
...
>
56
~
~
9
(5)
~
GND~
(6)
o
3
4
7 8
11 12
15 16
19 20
23 24
27 28
-=
GND
GND
ill
-= (19)
(18)
GND
ill
-= (17)
(16)
GND
ill
-= (15)
(14)
GND
ill
-= (13)
(12)
GND
ill
-= (11)
(10)
GND
rD
-= (9)
~H
Q
63
08
(22 )
-=
'-
16
~
4
(27)
~~
ill
(8)
~
(7)
31
164928-9
PAL16R8 Family
2·13
~AMD
LOGIC DIAGRAM
DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts
16R6 (-4)
elK
20
~Vee
(23)
too...
1
(24) .....
0
3
4
7 8
11 12
1516
19 20
23 24
2728
31
0
J
6_
7
~
(20).
GND
rO
.". (19)
>
16
>-~
~
23
4
(27)
~
-.
24
31
5
(28)
~
~
(1)
39
....
>
40
........
f--
./
47
7
(3)
.....
>
""'"
t.../
.of
>
56
t~.....
~
63
9
(5)
...
>
GND~
(6)
~
~.
~
~
~
H,
~
H
48
55
8
(4)
~
~
32
Vee D
6
(2)
GND
rO
-= (21)
a
~~
....,
15
3
(26)
19
(22)
:J
\
o
34
78
1112
1516
192023242728
j
(18)
GND
rD
.". (17)
(16)
GND
rD
-= (15)
(14)
GND
rD
.". (13)
(12)
GND
rD
.". (11)
(10)
GND
rO
-= (9)
12
(8)
L
(28)
32
I--
~
Vee D
L-/
(1)
(14)
39
6
(2)
..
~
GND
":" (13)
I"'"
40
GND
":" (15)
'-
'~
........
J
(12)
47
7
(3)
b
<~
~
56
~l
~ .rv
63
18 9
(5)
'=
J
t:t»]
55
8
(4)
GND
rD
(11)
~
48
o
3
4
7 8
11 12
1516
1920
23 24
2728
GND
rD
(9)
'=
1
-+-+H------f-HH-
VT
Output
164928-16
Input to Output Disable/Enable
164928-17
OE to Output Disable/Enable
Notes:
1. VT= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns-3 ns typical.
.
2-40
PAL16R8 Family
"
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/77//
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
XXXXXX
]})
EK
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Output O - -.....- - -.....-~J Test Point
164928-18
Military
Commercial
Specification
tPD, teo
CL
Sl
Closed
tpzx, tEA
Z~
Z~
tpxz, tER
H
H: Opeh
L: Closed
~Z:
L~Z:
Open
Closed
50 pF
5 pF
R1
R2
R1
R2
All but
All but
All but
All but
8-4:
8-4:
8-4:
8-4:
200n
390n
390n
750n
8-4:
8-4:
8-4:
8-4:
800n
1.56 kn
800n
1.56 kn
PAL16R8 Family
Measured
Output Value
1.5 V
H ~Z: VOH-0.5 V
L ~ Z: VOL + 0.5 V
2-41
~AMD
MEASURED SWITCHING CHARACTERISTICS for the PAL 16R8-5
Vee
= 4.75 V, TA = 75°C (Note 1)
5.0
-5
4.5
tPD, ns
4.0
3.5
3.0
-+---+--+---+---t---+--i---I
2
3
5
4
6
7
8
Number of Outputs Switching
164928-12
tpo vs. Number of Outputs Switching
10
8
tPD, ns
6
-5
4
2
o
50
100
150
200
250
CL, pF
tpo vs. Load Capacitance
Vee = 5.25 V, TA
164928-13
= 25°C
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified '
where tpo may be affected.
2-42
PAL16R8-5
AMD~
CURRENT VS. VOLTAGE(I-V) CHARACTERISTICS for the PAL16R8-4/5
Vee
= 5.0 V, TA = 25°C
IOL, rnA
15
--+--+---t---t--tf---t--i'- VOL, V
164928-14
Output, LOW
VOH, V
164928-15
Output, HIGH
h, JlA
20
2
3
VI, V
-100
-150
-200
164928-16
Input
PAL16R8-5
2-43
~AMD
MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-7
=4.75 V, TA = 75°C (Note 1)
Vee
.
7.5
7
tPD, ns
6.5
6-f--+--f.-~--+--+--+---I
2
3
4
5
6
7
8
NUM8ER OF OUTPUTS SWITCHING
164928-12
tPD
VS.
Number of Outputs Switching
tPD, ns
CL, pF
164928-13
tPD
VS.
Load Capacitance
Note:
1.
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where tPD may be affected.
2-44
PAL16R8-7
AMD~
CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-7
Vee
= 5.0 V, TA = 25°C
IOl.mA
15
--+--+----+-+--+-+-+--1- VOL. V
164928-14
Output, LOW
IOH. mA
20
VOH. V
164928-15
Output, HIGH
h.Jl.A
20
2
3
VI. V
-80
164928-16
Input
PAL16R8-7
2-45
~AMD
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Typical Input
Vee
Input
ProgramNerify
Circuitry
164928-29
Typical Output
---------4~--_o
Vee
40n NOM
~~----.--------.-()
Input,
Output
ProgramNerifyl
1/0
Test Circuitry
Pins
Preload
Circuitry
164928-30
2-46
PAL16R8 Family
AMD
jt1
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will be HIGH due to the inverting output
buffer. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation
of the power-up reset and the wide range of ways Vee
Parameter
Symbol
can rise to its steady state, two conditions are required
to ensure a valid power-up reset. These conditions are:
• The
Vee rise
must be monotonic.
• Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
ts
.Input or Feedback Setup Time
tWL
Clock Width LOW
See Switching
Characteristics
4V~--------------------------------------
Vee
Power
Registered
Active-Low
Output
Clock
9-t~
164928-31
Power-Up Reset Waveform
PAL16R8 Family
2-47
_
COM'L: H-5/7/10/15/25, Q-10/15/25
~
MIL: H-15/20/25
PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
Pin, function and fuse-map compatible with all
20-pin GAL devices
Electrically erasable CMOS technology
provides reconflgurable logic and full
testability
High-speed CMOS technology
- 5 ns propagation delay for "-5" version
- 7.5 ns propagation delay for "-7" version
Direct plug-In replacement for the PAL16R8
series and most of the PAL 1OH8 series
Outputs programmable as registered or
combinatorial In any combination
•
•
•
•
•
•
•
•
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pln plastic DIP, PLCC, and
SOIC packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and
functional yields and high reliability
5 ns version utilizes a split leadframe for
Improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. The PALCE16V8 will directly replace the
PAL16R8 and PAL 1OH8 series devices, with the exception ofthe PAL16C1.
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the, very
wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
2-48
feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is
, determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
AMD's FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular
industry-standard deSign tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a deSigner can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
Publication# 16493 Rev. B
Issue Date: June 1993
AmendmentlO
l1
AMD
BLOCK DIAGRAM
11-18
Programmable AND Array
32 x 64
164938-1
CONNECTION DIAGRAMS
Top View
DIP/SOIC
PLCC/LCC
0
Vee
CLKl/o
II
~
1/07
12
II0s
13
1/05
14
1/04
15
1/03
Is
1/02
17
1/01
18
1/00
...£-I
I/0s
1/05
15
1/04
Is
1/03
17
1102
..!F
10 11
CI
z
(!)
PIN DESIGNATIONS
OE
l"-
~
18
9
164938-2
Vee
()
()
>
14
Note: Pin 1 is marked for orientation
ClK
GND
I
1/0
()
13
OE/lg
GND
-=
-oJ
12 13
g
I~ g
0>
0
164938-3
Clock
Ground
Input
InpuVOutput
Output Enable
Supply Voltage
PALCE16V8 Family
2-49
~
AMD
ORDERING INFORMATION
Commercial Products
AMO programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
CE
_ _ _ _ _ _T....J
-r-
16 V 8 H ·5 P CIS
-"-.r-"r-'r-
_
FAMILY TYPE
-
PAL = Programmable Array Logic
TECHNOLOGY ___________________-....J
CE .. CMOS Electrically Erasable
[
OPTIONAL PROCESSING
Blank
ARRAY INPUTS
Standard Processing
PROGRAMMING DESIGNATOR
Blank
NUMBEROF----------------------------~
=
=
Initial Algorithm
14
First Revision
15 .. Second Revision
(Same Algorithm as 14)
OUTPUTTYPE----------------------------~
V - Versatile
NUMBER OF FLIP·FLOPS
-------------~
POWER-----------------------~
H .. Half Power (90 - 125 mA Icc)
Q .. Quarter Power (55 mA Icc)
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
SPEED--------------------------------~
PACKAGE TYPE
-5
-7
-10
-15
-25
P = 20·Pin Plastic DIP (PO 020)
J = 20·Pin Plastic Leaded Chip
Carrier (PL 020)
S = 20·Pin Plastic Gull,Wing
Small Outline Package (SO 020)
..
..
..
..
..
5 ns tPD
7.5 ns tPD
10 ns tPD
15 ns tPD
25 ns tPD
Valid Combinations
Valid Combinations
PALCE16VSH-5
JC
PAlCE16V8H-7
PC,JC
PALCE 16VSH-1 0
PC,JC, SC
PALCE 16VSQ-1 0
PC,JC, SC
PALCE16VSH-15
PC,JC, SC
15
14
15
PALCE 16VSQ-15
PC,JC
Blank,
PALCE16VSH-25
PC, JC, SC
14
PALCE16VSQ-25
PC,JC
2·50
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMO sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE16V8H·517/10/15/25, Q~10/15/25 (Com'l)
AMD~
ORDERING INFORMATION
APL Products (Military)
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination)
is formed by a combination of:
PAL
CE
16 V 8 H -15 E5 IB R A
I-..Ju --
FAMILY TYPE _ _ _ _
PAL = Programmable Array Logic
1L
TECHNOLOGY - - CE = CMOS Electrically Erasable
NUMBER OF _ _ _ _ _ _ _ _ _- - J
LEAD FINISH
A = Hot Solder Dip
PACKAGE TYPE
R = 20-Pin Ceramic DIP (CD 020)
2 = 20-Pin Ceramic Leadless
Chip Carrier (CL 020)
ARRAY INPUTS
OUTPUT TYPE - - - - - - - - - - - - '
V = Versatile
DEVICE CLASS
= Class B
NUMBER OF FLIP-FLOPS _ _ _ _ _ _ _- - J
!8
POWER ---------------------------~
H = Half Power (130 mA Icc)
PROGRAMMING DESIGNATOR
Blank = Initial Release
E4 = First Revision
(Different Algorithm from
Blank)
SPEED
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
Valid Combinations
PALCE16V8H-15
E4
PALCE16V8H-20
Blank,
E4
PALCE16V8H-25
IBRA
IB2A
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Group A Tests
Group A tests consist of Subgroups
1,2,3, ~a ~ 1~ 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STO-883, Test Method 1015, Conditions A through
conditions are selected at AMO's option.
PALCE16V8H-15/20/25 (Mil)
E. Test
2-51
~
AMD
FUNCTIONAL DESCRIPTION
The PAlCE16V8 is a universal PAL device. It has eight
independently configurable macrocells (MCo-MC7).
Each macrocell can be configured as registered output,
combinatorial output, combinatorial 1/0 or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic
array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as
clock (elK) and output enable (OE), respectively, for all
flip-flops.
Unused input pins should be tied directly to Vee or GND.
Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical lOW state.
The programmable functions on the PAlCE16V8 are
automatically configured from the user's design specifi-
cation, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
The user is given two design options with the
PAlCE16V8. First, it can be programmed as a standard
PAL device from the PAl16R8 and PAl10H8 series.
The PAL programmer manufacturer will supply device
codes for the standard PAL device architectures to be
used with the PAlCE16V8. The programmer will program the PAlCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed as
a PAlCE16V8. Here the user must use the PAlCE16V8
device code. This option allows full utilization of the
macrocell.
To
Adjacent
Macrocell
I/OX
*SG1
*/n macrocells MCo and MCl, SG1 is rep/aced by SGO on the feedback multiplexer.
PAlCE16V8 Macrocell
2-52
PALCE16V8 Family
From
Adjacent
Pin
164938-4
AMD
Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial 110, or dedicated input. In the registered output
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MCo and MC7, a macrocell configured
as a dedicated input derives the input signal from an adjacent 110. MCo derives its input from pin 11 (OE) and
MC7 from pin 1 (ClK).
The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO
and SG1) and 16 local bits (SlOo through Sl07 and Sl1 0
through Sl17). SGO determines whether registers will
be allowed. SG1 determines whether the PAlCE16V8
will emulate a PAL 16R8 family or a PAL 1OH8 family device. Within each macrocell, SlOx, in conjunction with
SG1, selects the configuration of the macroce II , and
Sl1x sets the output as either active low or active high
for the individual macrocell.
The configuration bits work by acting as control inputs
forthe multiplexers in the macrocell. There are four mUltiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and
SLOx are the control signals for all four multiplexers. In
MCo and MC7, SGO replaces SG1 on the feedback multiplexer. This accommodates ClK being the adjacent
pin for MC7 and OE the adjacent pin for MCo.
~
use the feedback path of MC7 and pin 11 will use the
feedback path of MCo.
Combinatorial 1/0 in a Non-Registered
Device
The control bit settings are SGO =1, SG1 = 1, and SlOx =
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because ClK and OE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback pathof MC7 and pin 11 will use the
feedback path of MCo.
Combinatorial 1/0 in a Registered Device
The control bit settings are SGO = 0, SG1 = 1 and SlOx =
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The control bit settings are SGO = 1, SG 1 =0 and SlOx =
1. The output buffer is disabled. Except forMCo and MC7
the feedback signal is an adjacent 110. For MCo and MC7
the feedback Signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in
Figure 2.
Table 1. Macrocell Configuration
Registered Output Configuration
The control bit settings are SGO =0, SG1 = 1 and SlOx =
O. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by Sl1 x. The flip-flop is
loaded on the lOW-to-HIGH transition of ClK. The
feedback path is from Q on the register. The output
buffer is enabled by OE.
Combinatorial Configurations
The PAlCE16V8 has three combinatorial output configurations: dedicated output in a non-registered device,
110 in a non-registered device and 110 in a registered
device.
Dedicated Output in a Non-Registered
Device
The control bit settings are SGO = 1, SG 1 = 0 and SlOx =
O. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 15 and 16. Pins
15 and 16 do not use feedback in this mode. Because
ClK and OE are not used in a non-registered device,
pins 1 and 11 are available as input Signals. Pin 1 will
SGO SG1 SLOx Cell Configuration Devices Emulated
Device Uses Registers
0 Registered Output PAL 16RB, 16R6,
0
1
16R4
1 Combinatorial 1/0 PAL16R6,16R4
0
1
Device Uses No Registers
PAL1OHB, 12H6,
0 Combinatorial
1
0
14H4, 16H2, 10LB,
Output
12L6, 14L4, 16L2
PAL12H6,14H4,
1
0
1 Input
16H2, 12L6, 14L4,
16L2
1
1
1 Combinatorial I/O PAL16LB
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output Signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is through a programmable bit Sl1 x which
controls an exclusive-OR gate at the output of the AND!
OR logiC. The output is active high if Sl1 x is 1 and active
low if SL1x is O.
PALCE16V8 Family
2·53
~
AMD
OE--------------,
OE----------------------~
>---~
D
Y)--~
Q
D
Q
elK
Registered Active High
Registered Active Low
Combinatorial 1/0 Active High
Combinatorial 1/0 Active Low
Combinatorial Output Active High
Combinatorial Output Active Low
Notes:
1. Feedback is not available on pins 15
and 16 in the combinatorial output mode.
Adjacent 1/0 pin
2. This configuration is not available on pins 15 and 16.
Note 2
Dedicated Input
Figure 2. Macrocell Configurations
2-54
PALCE16V8 Family
164938-5
AMD
~
Power-Up Reset
Programming and Erasing
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
The PALCE16V8 can be programmed on standard logic
programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure
is automatically performed by the programming hardware. No special erase operation is required.
. Register Preload
The register on the PALCE16V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine· designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Security Bit
A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with
the array during an erase cycle.
Quality and Testability
The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
, Technology
The high-speed PALCE16V8 is fabricated with AMD's
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Electronic Signature Word
An electronic Signature word is provided in the
PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The
signature data is always available to the user independent of the security bit.
PALCE16V8 Family
2-55
~AMD
LOGIC DIAGRAM
4
ClKlI
11
2
15
6 19
0
~
4
7
8
1
1
~
th
10
~
0
ic
~
II
&
~,
\SlO,
>p
7
~
U
~~~l~
iJ." .....
o
0
~
""UlIII
V0 7
.~
11
~
OSlO,
~~
1O
I
8
_~
.n
;c
~r
VCC.,f=t0C
&
>:£:D- ~~
~,
\SlO,
ox
15
,
if
_
-lim
JW
11
3
ox
SGI
~~
10
~
16
.
4
t10
VCC;=tg~
4
~
J
",+SlO.
SGI
-
SGI
~~
'0
~D-
.
...
.:rr. SlO.
-n1-
10
VCC.;:=t0O
4
1 st ~SlO.
w----t
~
11
O""W
31
~
--_.-
~
ox
.A
24
.:n:. SlO,
>t,D- ~
23
4
IZiivCC
1-
VCCFO
ox
Slh
~
~
ox
....
.....
.....
-mL"
SGI31: SlO.
3 4
7 8
11 12 15 16
19 20 23 24 27 28
31
ClK OE
164938-6.
2-56
PALCE16V8 Family
AMD
~
LOGIC DIAGRAM (continued)
o
3 4
7 8
11 12 15 16 19 20 23 24 27 28 31
a.K OE
I
Sl0
ll1.
~
,
>-r~
39
m
- IT
•
~
32
1-
1O
vcc.;;t0o
~il
~..
':
"
=
~-
...
ox
SGI.:rt:.
~~
1Ti
vee;:t~~
~
40
47
•
~ ~
>r~ ~II
\SlO,
II
001
SlO,
1IT
1O
vee.;:t0o
~il
l
~
J l.
Sl0
SGI
.....
~
,
>-r>
55
Ill-1.
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~
ox
.A
48
SlO,
.
~
0: ~ "~
-mI
mb
ox
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~il
1Ti
~
~
.. "
0:
. 1P
~
56
.:rL. SlO,
1O
vee.;:too
l
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ll.2I'"
63
~
rn--t
-mJ 1100
mb
ox
m1.:rL.SlOg
50 k.Q
I
I
I
I
I
.
II Programmlng
ESD
Protection
and
Clamping
Ll2n.!~!l.
-=
____ _
Typical Input
Vee
Vee
> 50 k.Q
Provides ESD
Protection and
Clamping
Preload
Circuitry
Typical Output
Feedback
Input
164938-15
*
Device
Rev Letter
Filter Only Filter and Pullups
PALCE16VSH-10
E,F
I
PALCE16VSH-15
D, E,F,G
H, I
PALCE16VSQ-15
D,G
H
PALCE16VSH-25
D,G
H
PALCE16VSQ-25
D,G
H
2-76
Topside Marking:
AMD CMOS PLD's are marked on the top of the package in the
following manner:
PALCEXXXX
Date Code (3 numbers) Lot 10 (4 characters)- -(Rev. Letter)
The Lot /D and Rev Letter are separated by two spaces.
PALCE16V8 Family
AMD~
POWER-UP RESET
The PALCE16V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
Parameter
Symbol
and the wide range of ways Vec can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
•
•
The Vee rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
Power-Up Reset Time
tPR
Min
ts
Input or Feedback Setup Time
tWL
Clock Width LOW
Power
Registered
Output
Clock
Unit
ns
See Switching Characteristics
Vee
4Vf.
L.
Max
1000
tPR
-.l
ZI
~
tWL
164938-17
Power-Up Reset Waveform
PALCE16V8 Family
2-77
~
AMD
TYPICAL THERMAL CHARACTERISTICS
14 Devices (PALCE16V8H-10/4)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Sjc
Sja
Sjma
Typ.
Parameter Description
Thermal Impedance, Junction to Case
Thermal Impedance, Junction to Ambient
Thermal Impedance, Junction to Ambient with Air Flow
200 Ifpm air
400 Ifpm air
600 Ifpm air
800 Ifpm air
PDIP
PLCC
Unit
25
71
61
55
51
47
22
64
55
51
47
45
°CIW
°CIW
°CIW
°CIW
°CIW
°CIW
15 Devices (PALCE16V8H-7/5)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ.
Parameter Description
Sjc
Thermal Impedance, Junction to Case
Sja
Thermal Impedance, Junction to Ambient
Sjma
Thermal Impedance, Junction to Ambient with Air Flow
200 Ifpm air
400 Ifpm air
600 Ifpm air
800 Ifpm air
PDIP
PLCC
Unit
29
70
64
58
53
23
61
53
47
44
°CIW
X
X
°CIW
°CIW
°CIW
°CIW
°CIW
Plastic ale Considerations
The data listed for plastic S~ are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the Sjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, S~ tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
2·78
PALCE16V8
Family
~
PALLV16V8-10
Advanced
Micro
Devices
Low-Voltage 20-Pin EE CMOS Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
Low-voltage operation, 3.3 V JEDEC
compatible
- Vee = +3.0 V to +3.6 V
Pin, function and fuse-map compatible with all
20-pin GAL devices
Electrically-erasable CMOS technology provides reconfigurable logic and full testability
Direct plug-in replacement for the PAL16R6
series and most of the PAL 1OH6 series
Designed to interface with both 3.3 V and 5 V
logic
•
•
•
•
•
•
•
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and
SOIC packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and functional yields and high reliability
Outputs programmable as registered or combinatorial in any combination
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with
low-voltage, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. The PALLV16V8 will directly replace the
PAL 16R8 and PAL 1OH8 series devices, with the exception of the PAL 16C1.
The PALLV16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equations are programmed into the device through
floating-gate cells in the AN D logic array that can be
erased electrically.
The fixed OR array allows up to eight data product
terms per output for logic functions. The sum of these
Publication# 1n13 Rev. A
Issue Date: June 1993
Amendment/O
products feeds the output macrocell. Each macrocell
can be programmed as registered or combinatorial with
an active-high or active-low output. The output configuration is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
AMD's FusionPLD program allows PALLV16V8 designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accu rate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the Software Reference Guide to PLD Compilers for
certified development systems and the Programmer
Reference Guide for approved programmers.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information Is
~~~!~~~~~~,~IP you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product
2-79
~
PRELIMINARY
AMD
BLOCK DIAGRAM
h -Is
Programmable AND Array
32x 64
1100
OE/lg
1/01
1/02
110a
1/04
liDs
1/05
1/07
17713A-1
CONNECTION DIAGRAMS (Top View)
DIP/SOIC
PLCC
~
elK/I a
Vee
11
1/07
12
lIDs
13
1105
14
1104
L.
VOs
15
1103
15
1/04
Is
110 2
16
V0 3
17
1101
17
1102
Is
OE
2·80
2
1
20 19
•
18
0
Z
CI>
I~
~ ~
Note:
Pin 1 is marked for orientation.
Clock
Ground
Input
Input/Output
Output Enable
Supply Voltage
PALLV16V8-10
lIDs
10 11 12 13
(!)
PIN DESIGNATIONS
Vee
3
~
17713A-2
ClK
GND
I
I/O
~
9
'01:/1 9
....
~
0
b
1100
GND
U
-=
...J
..!:l
17713A-3
AMD~
PRELIMINARY
ORDERING INFORMATION
Commerical Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
J
LV 16 V
---
8 -10
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
LV = Low-Voltage
P C
L
NUMBER OF
ARRAY INPUTS
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J '" 20-Pin Plastic Leaded Chip
Carrier (PL 020)
S '" 20-Pin Plastic Gull-Wing
Small Outline Package (SO 020)
OUTPUT TYPE _ _ _ _ _ _ _ _ _--1
V = Versatile
NUMBER OF FLIP-FLOPS
OPERATING CONDITIONS
C = Commercial (O°C to +7S°C)
--------1
SPEED
-10 = 10 ns tPD
Valid Combinations
Valid Combinations
PALLV16V8-10
I
PC, JC, SC
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALLV16V8-10 (Com'l)
2-81
~
AMD
PRELIMINARY
FUNCTIONAL DESCRIPTION
The PALLV16VS is a low-voltage, EE CMOS version of
the PALCE16VS.
The PALLV16VS isa universal PAL device. It has eight
independently configurable macrocells (MCo-MC7).
Each macrocell can be configured as registered output,
combinatorial output, combinatorial 110 or dedicated input. The programming matrix implements a programmable AN D logic array, which drives a fixed OR logic
array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as
clock (CLK) and output enable (OE), respectively, for all
flip-flops.
Unused input pins should be tied directly to Vcc or GND.
Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALLV16VS are
automatically configured from the user's design specification, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
The user is given two design options with the
PALLV16VS. First, it can be programmed as a standard
PAL device from the PAL16RS and PAL10HS series.
The PAL programmer manufacturer will supply device
codes for the standard PAL device architectures to be
used with the PALLV16VS. The programmer will program the PALLV16VS in the corresponding architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed as a
PALLV16V8. Here the user must use the PALLV16V8
device code. This option allows full utilization of the
macrocell.
To
Adjacent
Macrocell
I/Ox
>-----41~
0
QI-----4
From
Adjacent
Pin
-In macrocells MCo and MC7, SG1 is replaced by SGO on the feedback multiplexer.
Figure 1. PALLV16V8 Macrocell
2-82
PALLV16V8-10
17713A-4
AMD~
PRELIMINARY
Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial liD, or dedicated input. In the registered output
configuration, the output buffer is enabled by the DE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the ~xception of MCo and MCl, a macrocell configured
as a dedicated input derives the input signal from an adjacent liD. MCo derives its input from pin 11 (DE) and
MCl from pin 1 (ClK).
The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO
and SG1) and 16 local bits (SlOo through SlOl and Sl1 0
through Sl17). SGO determines whether registers will
be allowed. SG1 determines whether the PAllV16V8
will emulate a PAL 16R8 family or a PAL 1OH8 family device. Within each macrocell, SlOx, in conjunction with
SG1, selects the configuration of the macrocell, and
Sl1 x sets the output as either active low or active high
for the individual macrocell.
The configuration bits work by acting as control inputs
forthe multiplexers in the macrocell. There are four mUltiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and
SlOx are the control signals for all four multiplexers. In
MCo and MCl, SGO replaces SG1 on the feedback multiplexer. This accommodates ClK being the adjacent
pin for MCl and DE the adjacent pin for MCo.
Registered Output Configuration
The control bit settings are SGO = 0, SG1 = 1 and
SlOx =O. There is only one registered configuration. All
eight product terms are available as inputs to the OR
gate. Data polarity is determined by Sl1 x. The flip-flop is
loaded on the lOW-to-HIGH transition of ClK. The
feedback path is from Q on the register. The output
buffer is enabled by DE.
will use the feedback path of Me? and pin 11 will use the
feedback path of MCo.
Combinatorial 1/0 In a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 1, and
SlOx =1. Only seven product terms are available to
the OR gate. The eighth product term is used to enable
the output buffer. The signal at the liD pin is fed back to
the AND array via the feedback multiplexer. This allows
the pin to be used as an input.
Because ClK and DE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7and pin 11 will use the
feedback path of MCo.
Combinatorial 1/0 in a Registered Device
The control bit settings are SGO = 0, SG1 = 1 and
SlOx = 1. Only seven product terms are available to the
OR gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding liD
signal.
Dedicated Input Configuration
The control bit settings are SGO = 1, SG1 = 0 and
SlOx =1. The output buffer is disabled. Except for MCo
and MCl the feedback signal is an adjacent liD. For MCo
and MCl the feedback signals are pins 1 and 11. These
configurations are summarized in Table 1 and illustrated
in Figure 2.
Table 1. Macrocell Configuration
SGO SG1 SLOx Cell Configuration Devices Emulated
Device Uses Registers
0
1
0
0
1
1
Registered Output
Combinatorial I/O
Device Uses No Registers
1
0
0
Combinatorial
Output
1
0
1
Input
1
1
1
Combinatorial I/O
Combinatorial Configurations
The PAllV16V8 has three combinatorial output configurations: dedicated output in a non-registered device,
I/O in a non-registered device and liD in a registered
device.
Dedicated Output In a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 0 and
SlOx =O. All eight product terms are available to the OR
gate. Although the macrocell is a dedicated output, the
feedback is used, with the exception of MC3 and MC4.
MC3 and MC4 do not use feedback in this mode. Because ClK and DE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1
PAL 16R8, 16R6,
16R4
PAL 16R6, 16R4
PAL 1OH8, 12H6,
"14H4. 16H2. 10L8.
12L6, 14L4. 16L2
PAL 12H6, 14H4,
16H2. 12L6, 14L4,
16L2
PAL16L8
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is through a programmable bit Sl1 x which
controls an exclusive-OR gate at the output of the ANDI
OR logiC. The output is active high if Sl1 x is 1 and active
low if Sl1x is O.
PALLV16V8-10
2-83
~
PRELIMINARY
AMD
OE-----------------------,
OE---------------------,
XJ-----t D
Registered Active Low
Registered Active High
Combinatorial 110 Active Low
Combinatorial 1/0 Active High
Combinatorial Output Active Low
Combinatorial Output Active High
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
Adjacent 1/0 pin
Note 2
2. The dedicated-input configuration is not available
on pins 15 and 16.
Dedicated Input
17713A-5
Figure 2. Macrocell Configurations
2-84
Q
PALLV16V8-10
PRELIMINARY
\ Benefits of Lower Operating Voltage
AMD~
Security Bit
The PALLV16V8 has an operating voltage range of
3.0 V to 3.6 V. Low voltage allows for lower operating
power consumption, longer battery life, and/or smaller
batteries for notebook applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V
significantly reduces power consumption. This directly
translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce
the size and weight of the battery. Thus, 3.3-V designs
facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and provides a less hostile environment for board design. Lower
operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
Power-Up Reset
All flip-flops powerupto a logic LOWforpredictable system initialization. Outputs of the PALLV16V8 will depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
Register Preload
The register on the PALLV16V8 can be pre loaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
The preload function is not disabled by the security bit.
This allows functional testing after the security bit is
programmed.
A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
of the programmed pattern by a device programmer, securing proprietary designs from competitors. However,
programming and verification are also defeated by the
security bit. The bit can only be erased in conjunction
with the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the
PALLV16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent
of the security bit.
Programming and Erasing
The PALLV16V8 can be programmed on standard logic
programmers. It also may be erased to reset a previously configured device back to its unprogrammed
state. Erasure is automatically performed by the programming hardware. No special erase operation is
required.
Quality and Testability
The PALLV16V8 offers a very high level of built-in
quality. The erasability if the device provides a direct
means of verifying performance of all the AC and DC
. parameters. In addition, this verifies complete programmability and functionality of the device to yield. the
highest programming yields and post-programming
function yields in the industry.
Technology
The high-speed PALLV16V8 is fabricated with AMD's
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
This technology provides strong input-clamp diodes,
output slew-rate control, and a grounded substrate for
clean switching.
PALLV16V8-10
2-85
~
PRELIMINARY
AMD
LOGIC DIAGRAM
4
11 12
15
6 19
3 4
7 8 31
elK/IO 1
~i=l
10
L
0
nr>-tD- Ft~=t~*
,
J
SGI
\SlO,
-
o 0
7
11
~
ox
SGO
~i=l
10
l
8
,
J
SlO,
-n1-
10
vcc;:t0o
~
>-tD- ~.
\SlO,
SGI
~ox
15
su,
...
.
3
~II
10
.~
"
Sll,
...
I2QIv cc
10
vee o-joo
v~
>0-
r--lIID
mrJ
"
lox _ _
SGI
~i=l
10
l
16
tIh .
~. ~
10
vee;t~~
,
J
\SlO.
SGI -
>--tD-
23
.:rr. 51.0,
r"ox
[ill! 1105
~
"
Sll •
.A
4
"
---
SGII~
SlO.
~
10
L J
mfi
10
vcc.;=l.0o
~i=l ,
.
>-tD- ~::1}d
24
SGI
31
...
5
\SlO.
-
~I
illL
"
Sll •
ox
SGI
SlO.
17713A-6
3 4
2-86
7 8
11 12 15 16 19 20 23 24 27 28 31
PALLV16V8-10
ClK OE
AMD~
PRELIMINARY
LOGIC DIAGRAM (continued)
3
4
7
8
11 12 15 16 1920
23 24 2728 31
CLK OE
SGl
rtth
~.
56~
63~
VCC~m.+11
R~pl,l'"\&'
>tD- ~
J
~~';)O-"""""'L.i11'J.-..r.1""I/OO
• • •
SLl,
18
SLO,
iTIb
o
11
OX!---
9
'---------<(f- --£I:1) 001 9
o
3
4
7 8
11 12
15 16 19 20
23 24 27 28 31
GND~
17713A-6
(concluded)
PALLV16V8-10
2-87
~
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air ............ O°C to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to + 7.0 V
Supply Voltage (Vee) with
Respect to Ground ........... +3.0 V to +3.6 V
DC Input Voltage ............ -0.5 V to Vee + 0.5 V
DC Output or 110
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latehup Current
(TA = -40°C to 85°C) ................... 100 rnA,
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERICAL operating ranges unless otherwise specified
PRELIMINARY ,
Parameter
Symbol
VOH
VOL
Parameter Description
Output HIGH Voltage
Output LOW Voltage
Min
Test Conditions
= VIH or VIL
= Min
VIN = VIH or VIL
Vee = Min
VIN
IOH
Vee
IOH
IOL
IOL
= -2 rnA
= -100 IlA
= 2 rnA
= 100 ~A
Max
Unit
2.4
V
Vee-O.2 V
V
0.4
V
0.1
V
2.0
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
10
ilL
Input LOW Leakage Current
= Vee, Vee = Max (Note 2)
VIN = 0 V, Vee = Max (Note 2)
VOUT = Vee, Vee = Max
VIN = VIH or VIL (Note 2)
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 2)
VOUT = 0.5 V, Vee = Max (Note 3)
Outputs Open (lOUT = 0 rnA)
Vee = Max, f = 15 MHz
10
IlA
IlA
IlA
-100
IlA
-150
rnA
55
rnA
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Ise
Output Short-Circuit Current
Icc
Supply Current
VIN
-100
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. 110 pin leakage is the worst case of IJL and IOZL (or IJH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-88
PALLV16V8-10 (Com'l)
AMD~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Description
Test Condition
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT= 2.0 V
Typ
Unit
Vcc = 5.0 V, TA = 25°C,
5
pF
f = 1 MHz
8
pF
I
I
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
PRELIMINARY
Parameter
Symbol
Min
Parameter Description
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
tco
Clock to Output
tWL
Clock Width
tWH
Max
Unit
10
ns
7.5
0
ns
7.5
ns
LOW
6
ns
HIGH
6
ns
External Feedback
I 1/(ts+tco)
66.7
MHz
71.4
MHz
fMAX
Maximum
Frequency
(Note 3)
tpzx
OE to Output Enable
10
ns
tpxz
OE to Output Disable
10
ns
Internal Feedback (fCNT)
No Feedback
I 1/(tS+tH)
83.3
MHz
tEA
Input to Output Enable Using Product Term Control
10
ns
tEA
Input to Output Disable Using Product Term Control
10
ns
Notes: ,
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested,' but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALLV16V8-10 (Com'l)
2-89
~
PRELIMINARY
AMD
SWITCHING WAVEFORMS
Input or
Feedback _ _ ___
Input or
Feedback
Combinatorial
Output
VT
~VT
-~""'---VT
17713A-7
Clock - - - - - - - - . . . ; .
Registered
Output _ _ _ _ _ _ _ _.....
17713A-8
Combinatorial Output
Registered Output
Input
tER
Clock
VT
Output
17713A-10
17713A-9
Input to Output Disable/Enable
Clock Width
tpxz
tpzx
VT
Output
17713A-11
OE to Output Disable/Enable
Notes:
1. Vr = 1.5 V for Input Signals and 1.65 V for Output Signals.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns -5 ns typical.
2-90
tEA
PALLV16V8-10
AMD~
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
IllZZ
May
Change
from L to H
Will be
Changing
from L to H
'XXXXXX
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
]})
Does Not
Apply
Center
Line is HighImpedance
"Off" State
CK
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
3.3 V
Output D--""---""---1r.l Test Point
17713A-12
Specification
51
52
CL
R1
R2
Measured
Output Value
tPD, teo
Closed
Closed
1.65 V
tpzx, tEA
Z~
Z~
1.65 V
Z~
tpxz, tER
H
H: Open
L: Closed
~Z:
L~Z:
Open
Closed
H: Closed
L: Open
Z
~
H
~Z:
30 pF
1.6K
Closed
L~Z:Open
5 pF
PALLV16V8-10
1.6K
H ~ Z: VOH - 0.5 V
L ~ Z: VOL + 0.5 V
2-91
~
PRELIMINARY
AMD
ENDURANCE CHARACTERISTICS
The PALLV16V8 is manufactured using AM D's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
parts. As a result,
device can be erased and
reprogrammed - a feature which allows 100% testing at
the factory.
Parameter
Test Conditions
tOR
Min Pattern Data Retention Time
Max Storage Temperature
Max Operating Temperature
20
Years
N
Min Reprogramming Cycles
Normal Programming Conditions
100
Cycles
Min
Unit
10
Years
ROBUSTNESS FEATURES
The PALLV16V8 has some unique features that make
it extremely robust, especially when operating in highspeed design environments. Pull-up resistors on inputs
and I/O pins cause unconnected pins to default to a
known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking
caused by subsequent ringing. A special noise filter
makes the programming circuitry completely insensitive
to any positive overshoot that has a pulse width of less
than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
Vee
>50kn
I
I
I
I
ESD
Protection
and
Clamping
I
.
II Programmmg
L'2n~~!!:
=-
____ _
Typical Input
Vee
Vee
>50kn
Provides ESD
Protection and
Clamping
Preload
Circuitry
=Typical Output
2-92
PALLV16V8-10
Feedback
Input
17713A-14
AMD~
PRELIMINARY
POWER-UP RESET
The PALLV16V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
and the wide range of ways Vee can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
• The Vee rise must be monotonic.
• Following reset, the clock input must not be driven
from LOWto HIGH until all applicable input and feedback setup times are met.
Parameter
Symbol
Parameter Descrlptlo'ns
Min
tPR
Power-Up Reset Time
ts
Input or Feedback Setup Time
twL
Max
Unit
1000
ns
See Switching Characteristics
Clock Width LOW
t
Vee
4V
Power
Registered
Output
Clock
~
tPR
zL{
~~
PALLV16V8·10
j
17713A-15
2·93
~
AMD
9
2-94
GL'.DeVices
_
COM'L:-15/25
PALCE16V8Z FAMILY
Advanced
Micro
Devices
Zero-Power 20-Pin EE CMOS Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
Zero-Power CMOS technology
- 15 J,JA Standby Current
- 15 ns propagation delay for "-15" version
- 25 ns propagation delay for "-25" version
Unused product term disable for reduced
power consumption
Available In Industrial operating range
-
Tc
~
IND: -15/25
=-40°C to +85°C
- Vcc = +4.5 V to +5.5 V
HC- and HCT-Compatible inputs and outputs
Pin, function and fuse-map compatible with all
20-pin GAL devices
Electrically-erasable CMOS technology provides reconfigurable logic and full testability
•
•
•
•
•
•
•
•
•
Direct plug-In replacement for the PAL16R8
series and most of the PAL 10H8 series
Outputs programmable as registered or comblnato rial In any combination
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP and PLCC
packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and functlonal yields and high reliability
GENERAL DESCRIPTION
The PALCE16V8Z is an advanced PAL device built with
zero-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocellsprovide a universal device
architecture. The PALCE16V8Z will directly replace the
PAL 16R8 and PAL1OH8 series devices, with the exception of the PAL 16C1.
The fixed OR array allows up to eight data product terms
peroutputfor logic functions. The sum ofthese products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active- high or active-low output. The output configuration is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
The PALCE16V8Z provides zero standby power and
high speed. At 15 J,JA maximum standby current, the
PALCE16V8Z allows battery powered operation for an
extended period.
AMD's FusionPLD program allows PALCE16V8Z designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
The PALCE16V8Z utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equations are programmed into the device through
floating-gate cells in the AN D logic array that can be
erased electrically.
Publication# 13061 Rev. C
Issue Date: June 1993
Amendment/O
2-95
~AMD
BLOCK DIAGRAM
11-18
Programmable AND Array
32 x 64
OEll9
1/00
1/01
1/02
1/03
1/04
1106
1105
1/07
13061C-l
CONNECTION DIAGRAMS
Top View
DIP
PLCC
12
elK/I 0
Vee
I,
1/07
12
1/0 6
13
1/05
14
1/04
15
1/0 3
16
1/02
17
11O,
18
GND
18
ClK/lo Vee 1/0 7
GND OE/Igi/Oo lID,
1/00
PIN DESIGNATIONS
L>E!l g
ClK
13061C-2
GND
Note:
1/0
Pin 1 is marked for orientation
OE
Vee
2-96
I,
PALCE16V8Z Family
Clock
Ground
Input
InputlOutput
Output Enable
Supply Voltage
AMO
l1
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
_---'T
PAL
CE
16 V 8 Z -15 P
-~-~
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
OPERATING CONDITIONS
I = Industrial (-40°C to +85°C)
= Commercial (0°0 to +75°C)
-----------1
o
PACKAGE TYPE
P = 20-Pin Plastic DIP (PO 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
NUMBER OF FLIP-FLOPS
POWER
Z = Zero Power (15 j.1A Icc Standby)
SPEED
-15 = 15 ns tPD
-25 = 25 ns tPD
Valid Combinations
Valid Combinations
PALCE16V8Z-15
PALCE16V8Z-25
I
I
PI,JI,
PC, JC
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE16V8Z-15/25 (Com'I, INO)
2-97
~AMD
FUNCTIONAL DESCRIPTION
The PALCE16V8Z is the zero-power .version of the
PALCE16V8. It has all the architectural features of the
PALCE16V8. In addition, the PALCE16V8Z has zero
standby power and unused product term disable.
The PALCE16V8Z is a universal PAL device. It has
macrocells
eight
independently
configurable
(MCo-MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial lID
or dedicated input. The programming matrix implements a programmable AND logic array, which drives a
fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input
signal polarity. Pins 1 and 11 serve either as array inputs
or as clock (CLK) and output enable (DE), respectively,
for all flip-flops.
Unused input pins should be tied directly to Vec or GND.
Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE16V8Z are
automatically configured from the user's design specification, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
The user is given two design options with the
PALCE16V8Z. First, it can be programmed as a standard PAL device from the PAL 16R8 and PAL1OH8
series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8Z. The programmer will program the PALCE16V8Z in the
corresponding architecture. This allows the userto use
existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can
be programmed as a PALCE16V8Z. Here the user must
use the PALCE16V8Z device code. This option allows
full utilization of the macrocell.
To
Adjacent
Macrocell
~~~----------------------------------------~1
OE
10~--"'"
11
1
Vcc
:'
>---~a---l
D
00
01
IIOX
Q~----l
From
Adjacent
Pin
~/n macrocells
MCo and MCl, SG1 is replaced by SGO on the feedback multiplexer.
Figure 1. PALCE16V8Z Macrocell
2-98
PALCE16V8Z Family
13061C-4
AMD~
Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial liD, or dedicated input. In the registered output
configuration, the output buffer is enabled by the DE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MCo and MC7, a macrocell configured
as a dedicated input derives the input signal from an adjacent I/O. MCo derives its input from pin 11 (DE) and
MC7 from pin 1 (ClK).
The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO
andSG1) and 16 local bits (SlOothrough Sl07and Sl10
through Sl 17). SGO determines whether registers will
be allowed. SG1 determines whetherthe PAlCE16V8Z
will emulate a PAL 16R8 family or a PAL 1OH8 family device. Within each macrocell, SlOx, in conjunction with
SG1, selects the configuration of the macrocell, and
Sl1 x sets the output as either active low or active high
for the individual macrocell.
The configuration bits work by acting as control inputs
forthe multiplexers in the macrocell. There are four mUltiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and
SlOx are the control signals for all four multiplexers. In
MCo and MC7, SGO replaces SG1 on the feedback multiplexer. This accommodates ClK being the adjacent pin
for MC7 and DE the adjacent pin for MCo.
Combinatorial 1/0 In a Non-Registered
Device
The control bit settings are SGO =1, SG1 = 1, and SlOx =
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the output buffer. The signal at the liD pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because ClK and DE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MCo.
Combinatorial 1/0 in a Registered Device
The control bit settings are SGO =0, SG1 = 1 and SlOx =
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding 1/0
signal.
Dedicated Input Configuration
The control bit settings are SGO =1, SG1 = 0 and SlOx =
1. The output buffer is disabled. Except for MCo and MC7
the feedback signal is an adjacent liD. For MCo and MC7
the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in
.
Figure 2.
Table 1. Macrocell Configuration
SGO SG1 SLOx Cell Configuration Devices Emulated
Device Uses Registers
Registered Output Configuration
The control bit settings are SGO = 0, SG1 = 1 and SlOx =
O. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by Sl1 x. The flip-flop is
loaded on the lOW-to-HIGH transition of elK. The
feedback path is from Q on the register. The output
buffer is enabled by DE.
Combinatorial Configurations
The PAlCE16V8Z has three combinatorial output configurations: dedicated output in a non-registered device,
liD in a non-registered device and liD in a registered
device.
Dedicated Output In a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 0 and SlOx =
O. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feedback is used, with the exception of MC3 and MC4. MC3
and MC4 do not use feedback in this mode. Because
ClK and DE are not used in a non-registered device,
pins 1 and 11 are available as input signals. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MCo.
0
1
0
Registered Output
0
1
1
Combinatorial I/O
1
0
0
Combinatorial
Output
1
0
1
Input
1
1
1
Combinatorial I/O
PAL 16R8, 16R6,
16R4
PAL16R6,16R4
Device Uses No Registers
PAL 1OH8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL 12H6, 14H4,
16H2, 12L6, 14L4,
16L2
PAL16L8
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is through a programmable bit Sl1 x which
controls an exclusive-OR gate at the output of the ANDI
OR logic. The output is active high if Sl1 x is 1 and active
low if Sl1x is O.
PALCE16V8Z Family
2-99
~
AMD
OE - - - - - - - - - - - - - ,
OE - - - - - - - - - - - - . .
elK
Registered Active Low
Registered Active High
Combinatorial 1/0 Active Low
Combinatorial 110 Active High
Combinatorial Output Active Low
Combinatorial Output Active High
Notes:
1. Feedback is not available on pins 15
and 16 in the combinatorial output mode.
2. The dedicated-input configuration is not
available on pins 15 and 16.
Adjacent 1/0 pin
Note 2
Dedicated Input
13061C-5
Figure 2. Macrocell Configurations
2·100
PALCE16V8Z Family
AMD~
Zero-Standby Power Mode
Security Bit
The PALCE16V8Z features a zero-standby power
mode. When none of the inputs switch for an extended
period (typically 50 nS)"the PALCE16V8Z will go into
standby mode, shutting down most of its internal circuitry. The current will go to almost zero (Icc < 15 JlA).
The outputs will maintain the states held before the
device went into the standby mode.
A security bit is provided on the PALCE16V8Z as a
deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also
defeated by the security bit. The bit can only be erased
in conjunction with the array during an erase cycle.
When any input switches, the internal circuitry is fully
enabled and power consumption returns to normal.
This feature results in considerable power savings for
operation at low to medium frequencies. This savings is
illustrated in the Icc vs. frequency graph.
Product-Term Disable
On a programmed PALCE16V8Z, any product terms
that are not used are disabled. Power is cut off from
these product terms so that they do not draw current. As
shown in the Icc vs frequency graph, product-term
disabling results in considerable power savings. This
savings is greater at the higher frequencies.
Further hints on minimizing power consumption can be
found in the Application Note, "Minimizing Power Consumption with Zero-Power PLDs".
Power-Up Reset
All flip-flops powerupto a logic LOWforpredictable system initialization. Outputs of the PALCE16V8Z will depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
Electronic Signature Word
An electronic signature' word is provided in the
PALCE16V8Z device. It consists of 64 bits of programmable memory that can contain user-defined data. The
signature data is always available to the user independent of the security bit.
Programming and Erasing
The PALCE16V8Z can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed
state. Erasure is automatically performed by the programming hardware. No special erase operation is
required.
Quality and Testability
The PALCE16V8Z offers a very high level of built-in
quality. The erasability if the device provides a direct
means of verifying performance of all the AC and DC
parameters. In addition, this verifies complete programmability and functionality of the device to yield the
highest programming yields and post-programming
function yields in the industry.
Technology
Register Preload
The register on the PALCE16V8Z can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
The high-speed PALCE 16V8Z is fabricated with AM D's
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
HC and HCT devices. This technology provides strong
input-clamp diodes, output slew-rate control, and a
grounded substrate for clean switching.
The preload function is not disabled by the security bit.
This allows functional testing after the security bit is
programmed.
PALCE16V8Z Family
2-101
~
AMD
LOGIC DIAGRAM
4
8
11 12 15 6 19
!3 4 27 8 31
elK/IO 1
~ii
10
&
L J\
0
t
SGI
-
SlO
IT
7
~D-
7
Sl17
0:
FTI::~th»
~
~
10
8
3
SlO7
rn
vcc;:t.oi
10
-
&
I
J\SlO,
SGI
r---@l
~D- ~::~»-
.
~W
51.1,
~
~
+~
10
23
~
10
vcc.;=h~
&
>-tD- ~::~
I
--
--
SGI
+ii
10
-
"
~
SlO.
t
10
•
\SlO,
SGI -
<::
V05
vcc~~~
L J
..
llLJ
11
.....-v
24
...,.".
~~
SlI •
.A
5
SlO,
\Slo.
SGI -
16
31
*"
1111
SGI
4
---UiJ V0 7
11
OX
< ....
-
15
V
~
....
m--{k:
I2ii1v cc
vcc~H
~DSlI,
~
~illL
......
WiI
~
11
ox
SGI
SlO,
13061C-6
3 4
2·102
7 8
11 12 -15 16 19 20 23 24 27 28 31
PALCE16V8Z Family
ClJ(
OE
AMD~
LOGIC DIAGRAM (continued)
3 4
7
8
11 12 15 16 19 20
23 24 27 28 31
CLK OE
Wb
.r
~-----------j~========~11r--~;
VCCo-Jg~
10
16
.rn
7
IS 9
'----------<<}-l.------.wl 001 9
3 4
7 8
11 12 15 16 19 20
2324 27 2S 31
GND~
130S1C-S
(concluded)
PALCE16V8Z Family
2-103
~
AMD
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............ -D.5 V to + 7.0 V
DC Input Voltage. . . . . . . . . .. -D.5 V to Vee + 0.5 V
DC Output or I/O
Pin Vottage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latehup Current
(TA = O°C to 75°C) .................. 100 mA
Commercial (C) Devices
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Ambient Temperature (TA)
Operating in Free Air ............ O°C to +75°C
Supply Voltage (Vee) with
Respect to Ground .......... +4.75 V to +5.25 V
Industrial (I) Devices
Operating Case
Temperature (Te)
............ -40°C to +85°C
Supply Voltage (Vee) with
Respect to Ground ............ +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
PRELIMINARY
Parameter
Symbol
VOH
VOL
Min
Parameter Description
Test Conditions
Output HIGH Voltage
VIN = VIH or VIL
Vee = Min
10H
= 6 mA
IoH
= 20 JlA
VIN = VIH or VIL
Vee = Min
IoL
Output LOW Voltage
10l
= 24mA
= 6mA
10l
= 20 JlA
\
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2)
IIH
Input HIGH Leakage Current
ilL
Input LOW Leakage Current
= Vee, Vec = Max (Note 3)
= 0 V, Vee = Max (Note 3)
VOUT = Vee, Vee = Max
VIN = VIH or VIL (Note 3)
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 3)
Vee = Max (Note 4)
VOUT = 0.5 V
f = 0 MHz
Outputs Open (lOUT = 0 mA)
f = 25 MHz
Vee = Max
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Isc
Output Short-Circuit Current
Icc
Supply Current
Max
Unit
3.84
Vee -0.1 V
V
V
0.5
0.33
0.1
2.0
V
V
V
V
___O,~ __
V_
VIN
10
VIN
-10
JlA
JlA
10
JlA
-10
JlA
-150
mA
15
75
mA
-30
JlA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. 110 pin leakage is the worst case of hL and lozL (or I/H and lozH ).
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-104
PALCE16V8Z-15 (Com'l, IND)
AMO~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Condition
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT= 2.0 V
I
I
Typ
Unit
Vee = 5.0 V, TA = 25°C,
5
pF
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
PRELIMINARY
Parameter
Symbol
Parameter Description
tPD
Min
Input or Feedback to Combinatorial Output
Max
Unit
15
ns
ts
Setup Time from Input or Feedback to Clock
10
ns
tH
Hold Time
0
ns
teo
tWL
Clock to Output
Clock Width
tWH
10
ns
LOW
8
HIGH
8
ns
50
MHz
Internal Feedback (teNT)
58.8
MHz
No Feedback
62.5
External Feedback 11/(ts+teo)
ns
fMAx
Maximum
Frequency
(Note 3)
tpzx
OE to Output Enable
15
ns
tpxz
OE to Output Disable
15
ns
tEA
Input to Output Enable Using Product Term Control
15
ns
tER
Input to Output Disable Using Product Term Control
15
ns
1 1/(tWH+tWL)
MHz
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE16V8Z-15 (Com'l, INO)
2-105
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............ -0.5 V to + 7.0 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vec + 0.5 V
DC Output or 110
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current
(TA = O°C to 75°C) .................. 100 rnA
Commercial (C) Devices
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Ambient Temperature (TA)
Operating in Free Air ............ O°C to +75°C
Supply Voltage (Vee) with
Respect to Ground .......... +4.75 V to +5.25 V
Industrial (I) Devices
Operating Case
Temperature (Te)
............ -40°C to +85°C
Supply Voltage (Vee) with
Respect to Ground ............ +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
VIN = VIH or Vil
Vee = Min
Min
IoH
= 6 rnA
IOH = 20 JlA
IOL = 24 rnA
IOL = 6 rnA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2)
ilH
Input HIGH Leakage Current
ill
VIN = VIH or VIL
Vee = Min
IOL = 20 JlA
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2)
Max
Unit
3.84
Vee-O.l V
V
V
0.5
0.33
0.1
2.0
V
V
V
V
0.9
V
VIN = Vee, Vee = Max (Note 3)
10
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 3)
-10
J.LA
J.LA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = Vee, Vee = Max
VIN = VIH or VIL (Note 3)
10
JlA
lozl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or Vil (Note 3)
-10
JlA
Isc
Output Short-Circuit Current
VOUT=0.5 V
-150
rnA
Icc
Supply Current
Outputs Open (lOUT = 0 rnA)
Vee = Max
15
90
rnA
Vee = Max (Note 4)
f = 0 MHz
f = 25 MHz
-30
J.LA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. VO pin leakage is the worst case of liL and IOZL (or I/H and lozH ).
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2·106
PALCE16V8Z·25 (Com'l, INO)
AMO~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Condition
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT= 2.0 V
I
1
,Typ
Unit
Vee = 5.0 V, TA = 25°C,
5
pF
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output (Note 3)
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
teo
tWL
fMAx
25
20
Clock Width
8
ns
ns
8
ns
33.3
MHz
Internal Feedback (teNT)
50
MHz
No Feedback
50
HIGH
Maximum
Frequency
(Note 4)
ns
ns
10
LOW
Unit
ns
0
Clock to Output
tWH
Max
External Feedback 11/(ts+teo)
1 1/(tS+tH)
MHz
tpzx
OE to Output Enable
25
ns
tpxz
OE to Output Disable
25
ns
tEA
Input to Output Enable Using Product Term Control
25
ns
tER
Input to Output Disable Using Product Term Control
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be 2 ns faster.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE16V8Z·25 (Com'l, INO)
2·107
~
AMD
SWITCHING WAVEFORMS
Input or
Input or
Feedback
Combinatorial
Output
VT
Feedback _ _ _---'
€
. VT
-~-VT
Clock - - - - - - - Registered
Output _ _ _ _ _ _ _----'
13061C-7
13061C-8
Combinatorial Output
Registered Output
Input
tER
Clock
VT
Output
13061C-10
13061C-9
, Clock Width
Input to Output Disable/Enable
tpxz
tpzx
VT
Output
13061C-11
OE
to Output Disable/Enable
Notes:
1. Vr = 1.5 V for Input Signals and 2.5 V for Output Signals.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns - 5 ns typical.
2-108
tEA
PALCE16V8Z Family
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
IIIII
May
Change
from L to H
Will be
Changing
from L to H
X'/YYY:i
JJ)
g"
12
1/06
13
1/0 5
14
1/0 4
14
1/05
15
1/0 3
Is
1/04
16
1/0 2
16
1/03
17
1/01
h
1/02
Ie
lIDo
1 '20 19
•
b
9
10 11
~
Cl
~1I9
Z
C)
PIN DESIGNATIONS
OE
-=
1/0 7
174228-2
Vee
~
~
-I
11
GND
ClK
GND
I
I/O
---- --------._--------_._ ..
a
elK/I 0
1/06
12 13
C1>
I~ ~
Note:
Pin 1 is marked for orientation.
Clock
Ground
Input
Input/Output
Output Enable
Supply Voltage
PALLV16V8Z Family
~
174228-3
AMO~
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number.
(Valid Combination) is formed by a combination of:
_----IT ---PAL
LV
16 V 8 Z -25 P
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
LV = Low-Voltage
NUMBER OF
ARRAY INPUTS
OPERATING CONDITIONS
I = Industrial (-40°C to +85°C)
OUTPUT TYPE - - - - - - - - - - - - - '
V = Versatile
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
S = 20-Pin Plastic Gull-Wing
Small Outline Package (SO 020)
NUMBER OF FLIP-FLOPS - - - - - - - - - '
POWER
Z = Zero Power (15 ~ Icc Standby)
SPEED ----------------~
-25 = 25 ns tPD
-30 = 30 ns tPD
Valid Combinations
PALLV16V8Z-25
PALLV16V8Z-30
I PI JI SI
I "
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALLV16V8Z-25/30 (INO)
2-117
~
AMD
FUNCTIONAL DESCRIPTION
The PALLV16V8Z is a low-voltage, EE CMOS version
of the PALCE16V8. In addition, the PALLV16V8Z has
zero standby power and unused product term disable.
The PALLV16V8Z is a universal PAL device. It has eight
independently configurable macrocells (MCo-MC7).
Each macrocell can be configured as registered output,
combinatorial output, combinatorial 1/0 or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic
array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as
clock (CLK) and output enable (OE), respectively, for all
flip-flops.
Unused input pins should be tied directly to Vcc or GND.
Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALLV16V8Z are
automatically,configured from the user's design specification, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
The user is given two design options with the
PALLV16V8Z. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL 1OH8
series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALLV16V8Z. The programmer will program the PALLV16V8Z in the
corresponding architecture. This allows the userto use
existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can
be programmed as a PALLV16V8Z. Here the user must
use the PALLV16V8Z device code. This option allows
full utilization of the macrocell.
To
Adjacent
Macrocell
11
I/Ox
}-----tI.....-t
D
Qt----i
Qt---~I-+-..
1--____
*In macrocells MCo and MC7, SG1 is replaced by SGO on the feedback multiplexer.
Figure 1. PALLV16V8Z Macrocell
2-118
PALLV16V8Z Family
From
Adjacent
Pin
174228-4
AMD~
Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O; or dedicated input. In the registered output
configuration, the output buffer is enabled by the DE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MCo and MC7, a macrocell configured
as a dedicated input derives the input signal from an adjacent I/O. MCo derives its input from pin 11 (DE) and
MC7 from pin 1 (ClK).
The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO
and SG1) and 16 local bits (SlOothrough Sl07and Sl10
through Sl17). SGO determines whether registers will
be allowed. SG1 determines whether the PAllV16V8Z
will emulate a PAL 16R8 family or a PAL 1OH8 family device. Within each macrocell, SlOx, in conjunction with
SG1, selects the configuration of the macrocell, and
Sl1x sets the output as either active low or active high
for the individual macrocell.
The configuration bits work by acting as control inputs
forthe multiplexers in the macrocell. There are four mUltiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and
SlOx are the control signals for all four multiplexers. In
MCo and MC7, SGO replaces SG1 on the feedback mUltiplexer. This accommodates ClK being the adjacent
pin for MC7 and DE the adjacent pin for MCo.
Registered Output Configuration
will use the feedback path of MC7 and pin 11 will use the
feedback path of MCo.
Combinatorial I/O In a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 1, and
SlOx = 1. Only seven product terms are available to the
OR gate. The eighth product term is used to enable the
output buffer. The signal at the va pin is fed back to the
AND array via the feedback muttiplexer. This allows the
pin to be used as an input.
Because ClK and DE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MCo.
Combinatorial I/O in a Registered Device
The control bit settings are SGO = 0, SG1 = 1 and
SlOx =1. Only seven product terms are available to the
OR gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The control bit settings are SGO = 1, SG1 = 0 and
SlOx =1. The output buffer is disabled. Except for MCo
and MC7 the feedback signal is an adjacent I/O. For MCo
and MC7 the feedback signals are pins 1 and 11. These
configurations are summarized in Table 1 and illustrated
in Figure 2.
Table 1. Macrocell Configuration
SGO SG1 SLOx Cell Configuration Devices Emulated
The control bit settings are SGO = 0, SG1 = 1 and
SlOx =O. There is only one registered configuration. All
eight product terms are available as inputs to the OR
gate. Data polarity is determined by Sl1 x. The flip-flop is
loaded on the lOW-to-HIGH transition of ClK. The
feedback path is from Q on the register. The output
buffer is enabled by DE.
0
1
0
a
1
1
1
a
a
1
0
1
1
1
1
Combinatorial Configurations
The PAllV16V8Z has three combinatorial output configurations: dedicated output in a non-registered device,
I/O in a non-registered device· and I/O in a registered
device.
Dedicated Output In a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 0 and
SlOx =O. All eight product terms are available to the OR
gate. Although the macrocell is a dedicated output, the
feedback is used, with the exception of MC3 and MC4.
MC3 and MC4 do not use feedback in this mode. Because ClK and DE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1
Device Uses Registers
Registered Output PAL 16R8, 16R6,
16R4
PAl16R6,16R4
Combinatorial 1/0
Device Uses No Registers
Combinatorial
PAL 1aH8, 12H6,
Output
14H4, 16H2, 10LB,
12L6, 14L4, 16L2
Input
PAl12H6,14H4,
16H2, 12L6, 14L4,
16L2
PAL16L8
Combinatorial 1/0
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is through a programmable bit Sl1 x which
controls an exclusive-OR gate at the output of the AND/
OR logic. The output is active high if Sl1 x is 1 and active
low if SL1x is O.
PALLV16V8Z Family
2-119
~
AMD
OE - - - - - - - - - - - - ,
OE - - - - - - - - - - -......
)-----10
D----i 0
Q
Q
elK
Registered Active Low
Registered Active High
Combinatorial 1/0 Active Low
Combinatorial 1/0 Active High
Combinatorial Output Active Low
Combinatorial Output Active High
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
2. The dedicated-input configuration is not available
on pins 15 and 16.
Figure 2. Macrocell Configurations
2-120
PALLV16V8Z Family
Adjacent 1/0 pin
Note 2
Dedicated Input
174228-5
AMD~
Benefits of Lower Operating Voltage
The PALLV16V8Z has an operating voltage range of
3.0 V to 3.6 V. Low voltage allows for lower operating
power consumption, longer battery life, and/or smaller
batteries for notebook applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V
significantly reduces power consumption. This directly
translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce
the size and weight of the battery. Thus, 3.3-V designs
facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and provides a less hostile environment for board design. Lower
operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
Zero-Standby Power Mode
The PALLV16V8Z features a zero-standby power
mode. When none of the inputs switch for an extended
period (typically 50 ns), the PALLV16V8Z will go into
standby mode, shutting down most of its internal circuitry. The. current will go to almost zero (Icc < 15 JlA).
The outputs will maintain the states held before the
device went into the standby mode.
When any input switches, the internal circuitry is fully
enabled and power consumption returns to normal. This
feature results in considerable power savings for operation at low to medium frequencies. This savings is illustrated in the Icc vs. frequency graph.
Product-Term Disable
On a programmed PALLV16V8Z, any product terms
that are not used are disabled. Power is cut off from
these product terms so that they do not draw current. As
shown in the Icc vs frequency graph, product-term
disabling results in considerable power savings. This
savings is greater at the higher frequencies.
Further hints on minimizing power consumption can be
found in the Application Note "Minimizing Power Consumption with Zero-Power PLDs."
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALL V16V8Z will depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
The preload function is not disabled by the security bit.
This allows functional testing after the security bit is
programmed.
Security Bit
A security bit is provided on the PALLV16V8Z as a
deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also
defeated by the security bit. The bit can only be erased
in conjunction with the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the
PALLV16V8Z device. It consists of 64 bits of programmable memory that can contain user-defined data. The
signature data is always available to the user independent of the security bit.
Programming and Erasing
The PALLV16V8Z can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed
state. Erasure is automatically performed by the programming hardware. No special erase operation is
required.
Quality and Testability
The PALLV16V8Z offers a very high level of built-in
quality. The erasability if the device provides a direct
means of verifying performance of all the AC and DC
parameters. In addition, this verifies complete programmability and functionality of the device to yield the
highest programming yields and post-programming
function yields in the industry.
Technology
The high-speed PALLV16V8Z is fabricated with AMD's
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
This technology provides strong input-clamp diodes,
output slew-rate control, and a grounded substrate for
clean switching.
Register Preload
The register on the PALLV16V8Z can be preloaded
from the output pins to facilitate functional testing of
PALLV16VBZ Family
2-121
~
AMD
LOGIC DIAGRAM
4· 7 8
11 12 15 16 19 20
324 27
8 31
elK/IO 1
r-r~F.l~l------------t;=======V=~='~~~
~~.
u~
13 4
174228-6
3 4
2·122
7 8
11 12 15 16 19 20 23 24 27 28 31
PALLV16V8Z Family
ClK OE
AMD~
LOGIC DIAGRAM (continued)
3 4
7
8
11 12 15 16 19 20 23 24 27 28 31
eLl( OE
SOl
$lO,
~--------< and
28-pin PLCC packages
•
•
Outputs conflgurable as 0 or T flip-flops
Outputs programmable as registered
or combinatorial in any combination
•
Extensive third-party software and programmer
support through FusionPLD partners
•
•
Automatic register reset on power-up
Fully tested for 100% programming and functional yields and high reliability
•
High output-current drive capability
(64 mA 10L)
•
Programmable Totem-Pole or Open-Drain
Outputs
•
•
GENERAL DESCRIPTION
The PALCE16V8HD is the first CMOS PAL device to
combine high-current drive capability with a PAL architecture. The PALCE16V8HD can sink up to 64 rnA for
bus applications. It also has an advanced PAL architecture using a programmable macrocell to help provide a
universal solution.
The PALCE16V8HD utilizes the familiar sum-ofproducts (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently.
Multiple levels of combinatorial logic. can always be
reduced to sum-of-products form, taking advantage of
the very wide input gates available in PAL devices. The
equations are programmed into the device through
floating-gate cells in the AN D logic array that can. be
erased electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The su m of these products
feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is
Publication# 15559 Rev.D
Issue Date: June 1993
Amendment/O
determined by two global bits and one local bit controlling four multiplexers in each macrocell.
The PALCE16V8HD has some additional features that
make it an ideal choice for bus applications. These
include input hysteresis of 200 mV, clean output-switChing Signals, programmable totem-pole or open-drain
output configurations, programmable direct or latched
inputs, and programmable D- or T -type output registers.
AMD's FusionPLD program allows PALCE16V8HD designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accu rate, quality support. By ensu ring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a deSigner can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
2-135
~AMD
BLOCK DIAGRAM
GNOVee
OE/lg
18
17
Is
1/02
1/03
GND
lEll3
14
15
11
elK/lo
99
1/00
1/01
66
Vee
1/04
110s
1/05
1/07
6
Vee
155590-1
CONNECTION DIAGRAMS
Top View
SKINNVDIP
PLCC
0
ClK/lo
Vee
h
1/07
12
lE/13
14
~
I/Os
GND
1/05
15
1/04
Is
Vee
•
o
,...
!D
~~ ~
28 27 26
25
GND
24
1/°5
15
NC
23
1/°4
NC
Vee
1/°3
22
GND
1/03
Is
OE/lg
1102
17
21
20
1/01
18
19
GND
12 13 14 15 16 17 18
1/00
Q)
ili
10
0
0
0
z z
~ C}
o
~
N
~ ~ ~
155590-3
PIN DESIGNATIONS
2-136
2
0
z
14
155590-2
OE
3
0
lE/13
Note:
Pin 1 is marked for orientation.
Vee
4
.....I
18
GND
=
=
=
=
=
=
=
=
-
17
Vee
ClK
lE
GND
I
I/O
NC
-!.'I
Clock
lateh Enable
Ground
Input
Input/Output
No Connect
Output Enable
Supply Voltage
PALCE16V8HD-15
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
T
PAL
CE 16 V 8 HD -15 P C
-r--
~
FAMILY TYPE
---'
PAL= Programmable Array Logic
PROGRAMMING DESIGNATOR
Blank = Initial Release
TECHNOLOGY
CE = CMOS Electrically Erasable
OPERATING CONDITIONS
C = Commercial (OOC to +75°C)
NUMBER OF
ARRAY INPUTS
PACKAGE TYPE
P = 24-Pin Plastic SKINNYDIP (PD 3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
OUTPUT TYPE - - - - - - - - -......
V = Versatile
NUMBER OF FLIP-FLOPS - - - - - - - '
DRIVE
HD = High Output Drive
SPEED
-15 = 15 ns tPD
Valid Combinations
PALCE16V8HD-15
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE16V8HD-15 (Com'l)
2-137
~
AMD
FUNCTIONAL DESCRIPTION
The PAlCE16V8HD is a universal PAL device
with eight independently configurable macrocells
(MCo-MC7). Each macrocell can be configured as a
registered output, combinatorial output, combinatorial
1/0 or dedicated input. The programming matrix implements a programmable AND logic array, which drives a
fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input
signal polarity. Pins 1 and 10 serve either as array inputs
or as clock (ClK) and output enable (DE), respectively,
for all flip-flops.
All inputs to the array can be individually programmed
as either direct or transparent-latch inputs. lE/b is the
latch enable pin. The inputs to the array also have a
minimum of 200 mV of hysteresis.
Unused input pins should be tied directly to Vee or GND.
Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical lOW state.
The programmable functions on the PAlCE16V8HD
are automatically configured from the user's design
specification, which can be in a number of formats. The
design specification is processed by development software to verify the design and create a programming file.
This file, once downloaded to a programmer, configures
the device according to the user's desired function.
1 - - - - - . To Adjacent
11
Macrocell
SlOx
SG1
>-----......-IDfT
elK
(lOX
QI--~
Q~--------~
Sl5x
From
'SG1
"In macrocells MCo and MCl,
SGt is replaced by SGO on the
feedback multiplexer.
Adjacent
Pin
15559D-4
Figure 1. PAlCE16V8HD 1/0 Macrocell
15559D-5
Figure 2. PALCE16V8HD Input Macrocell
2-138
PALCE16V8HD-15
AMD~
Device Configuration
The configuration of the PAlCE16V8HD is controlled by
the configuration control word. It contains 2 global bits
(SGO and SG1) and 48 local bits (SlOa through Sl07,
SUa through Sl h, Sl21 through Sl2a, Sl3a through
Sl37, SL40 through SL47 and Sl5a through Sl57). SGO
determines whether registers will be allowed. SG1 and
the individual SlOx bits select the output macrocell configuration as registered output, combinatorial input,
combinatorial output, or combinatorial 1/0. Sl3x sets
the feedback path to the array as either direct or latched.
SL4x sets the output buffer as either a totem pole or an
open drain. Sl5x sets the register as either a D or T type
flip-flop. At each input pin, Sl2x sets the input as direct
or latched.
Input Pin Configuration Options
Each input pin can be configured as either a direct input
or a transparent latch. The input-pin configuration is set
by the local fuse Sl2x. When Sl2x is unprogrammed,
the input is direct. When Sl2x is programmed, the input
is through a corresponding transparent latch.
The latch is enabled via lEl13. The latches hold data
when lEll3 is low. They are transparent when lElI3 is
HIGH.
I/O Macrocell Configuration Options
Each 1/0 macrocell can be configured as one of the following: registered output, combinatorial output, combinatorialllO, or dedicated input. In the registered output
configuration, the output buffer is enabled by theOE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MCa and MC7, a macrocell configured
as a dedicated input derives the input signal from an adjacent 1/0. MCa derives its input from pin 10 (OE) and
MC7 from pin 1 (ClK). These configurations are summarized in Table. 1 and illustrated in Figure 3.
In the registered configurations all eight product terms
are available as inputs to the OR gate. The flip-flop is
loaded on the lOW-to-HIGH transition of ClK. The output buffer is enabled by OE.
Feedback to the array can be either direct or latched.
Direct feedback is from Q of the register to the productterm array. latched feedback is from Q of the register
through a transparent latch to the product-term array.
lEll3 is the latch-enable signal.
Combinatorial Configurations
The PAlCE16V8HD has three combinatorial output
configurations: dedicated output in a non-registered device, 1/0 in a non-registered device and 1/0 in a registered device.
Dedicated Output in a Non-Registered
Device
In this configuration, the output buffer is always enabled;
therefore all eight product terms are available to the OR
gate. The feedback to the array is from an adjacent 1/0
pin. 1/03 and 1/04 do not have connections to adjacent
macrocells; therefore, MC3 and MC4 do not have feedback to the array in this mode.
Because ClK and OE are not used in a non-registered
device, pins 1 and 10 are available as input signals. Pin
1 will use the feedback path of MC7 and pin 10 will use
the feedback path of MCa.
Combinatorial I/O In a Non-Registered
Device
Only seven product terms are available to the OR gate in
this configuration. The eighth product term is used to enable the output buffer. The signal at the 1/0 pin is fed
back to the AND array via the feedback multiplexer. This
allows the pin to be used as an input.
Because ClK and OE are not used in a non-registered
device, pins 1 and 10 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 10 will use the
feedback path of MCa.
Combinatorial I/O in a Registered Device
The feedback path in each macrocell can be programmed as either direct or latched. The feedback
configuration is set by the local fuse Sl3x. When SL3x
is unprogrammed, the corresponding feedback path is
direct to the array. When Sl3x is programmed, the corresponding feedback path is through a corresponding
transparent latch.
In this configuration only seven product terms are available to the OR gate. The eighth product term is used as
the output enable. The feedback signal is the corresponding 1/0 signal.
The latch is enabled via lElI3. The latches hold data
when lElI3 is lOW. They are transparent when lElI3 is
HIGH.
The output buffer is disabled in this configuration. Except for MCa and MC7 the feedback signal is an adjacent
1/0. For MCa and MC7 the feedback signals are pins 1
and 10.
Registered Output Configurations
There are two registered configurations: D-type and Ttype. Tl:le type is selected by Sl5x.
Dedicated Input Configuration
Pins 16 (19) and 19 (23) do not have connections to adjacent macrocells. The dedicated-input configuration is
not available on these pins.
PALCE16V8HD-15
2-139
~
AMD
Table 1. Macrocell Configuration
SGO
SG1
SLOx
SL5x
Cell Configuration
Device Uses Registers
0
1
0
0
T-Type Registered Output
0
1
0
1
D-Type Registered Output
1
0
0
X
Combinatorial Output
1
0
1
X
Dedicated Input
1
1
1
X
Combinatorial I/O
Device Uses No Registers
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
2-140
Selection is through a programmable bit SL 1x which
controls an exclusive-OR gate at the output of the AND/
OR logiC. The output is active high if SL 1x is 1 and active
low if SL1x is O.
Output Buffer Configurations
The output buffer can be configured as either a totempole output or an open-drain output. This configuration
is set by SL4x . The buffer is a totem-pole output when
SL4x is unprogrammed and an open-drain output when
SL4x is programmed. In the totem-pole configuration,
the output voltage levels are the standard VOH and VOL
levels. In the open-drain configuration, VOL is the standard value. However, VOH will depend on the termination circuitry.
PALCE16V8HD-15
AMD~
OE-----------------------,
}------t
OE -----------------------,
Off Q
D - - - - - t Off
Q
elK
Registered Active High
Registered Active Low
Combinatorial 1/0 Active Low
Combinatorial 1/0 Active High
lE/13
lE/13
Combinatorial 110 Active Low
with Latched Feedback
Combinatorial VO Active High
with Latched Feedback
Note:
1. All output and /10 configurations are valid
as either totem-pole outputs or opencollector outputs.
15559D-6
Figure 3. Macrocell Configurations
PALCE16V8HD-15
2-141
~
AMD
Combinatorial Output Active High
Combinatorial Output Active Low
To
Logic
Array
Combinatorial Output Active Low
with Latched Feedback
Input~.JJ D
or I/O
Pin
LE
Combinatorial Output Active High
with Latched Feedback
Qr
To
Logic
Array
~
<:J
~
L....-_---I
Adjacent I/O pin
Note 3
Latched Input
Dedicated Input
155590-7
Notes:
1. All output and 110 configurations are valid
as either totem-pole outputs or opencol/ector outputs.
2. Feedback is not available on pins 16
and 19 in the combinatorial output mode.
3. The dedicated-input configuration is not
available on pins 16 and 19.
Figure 4. Macroceil Configurations
2-142
PALCE16V8HD-15
AMD~
Power-Up Reset
Electronic Signature Word
All flip-flops power up to a logic LOW for predictable
system initialization. Outputs of the PALCE16V8HD will
depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
An electronic signature word is provided in the
PALCE16V8HD device. It consists of 64 bits of programmable memory that can contain user-defined data.
The signature data is always available to the user independent of the security bit.
Register Preload
The PALCE16V8HD can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erase operation is required.
The register on the PALCE16V8HD can be pre loaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
Security Bit
A security bit is provided on the PALCE16V8HD as a
deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also
defeated by the security bit. The bit can only be erased
in conjunction with the array during an erase cycle.
Programming and Erasing
Quality and Testability
The PAL16V8HD offers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all the AC and DC
parameters. In addition, this helps verify complete
programmability and functionality of the device to yield
the highest programming yields and post-programming
function yields in the industry.
Technology
The high-speed PALCE16V8HD is fabricated with
AMD's advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven
EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong
input-clamp diodes, output slew-rate control, and a
grounded substrate for clean switching.
PALCE16V8HD-15
2-143
~AMD
LOGIC DIAGRAM
SKINNYDIP/Flatpack (PLCC) Pinouts
o
3
•
7
•
11
12
15 16
19
20
23
2.
27
28
31
C~. 1~-----------~~~++-HH+-+HH-++H~~~++~H++-HH+---------------------~----------------,
(2)
~Vee
.rtn,
(28)
ITL+
.r€TI
GND
(25)
.r-tch
tl!d
(2.)
rtch
tl!d
_&
-@) VO.
(23)
!ill Vee
(21)
.r@l GND
(20)
o
3
•
7
8
11
12
15 16
19
20
23
2.
27
28
31
LE OE
CLK
155590-8
2-144
PALCE16V8HD-15
AMD~
LOGIC DIAGRAM (continued)
o
3
4
7
a
11
12
15 18
19 20
23
24
27
28
eLK
LE OE
31
ri=! .
4011111111~~
'~;t>-H-+-+-IIro;T=1 I~:
1l}G
:::::stl -1SLO,
0-~17
~
a
(9)
~1
~ SL~
47
~
0
q.SL4,
(18)
SGl
SLO,
SGl
SLO,
LE
#
SL3,
SL2,
-f"n.
~
i
@~P"
:
a
(10)
":>0---+---/15 VO,
~~==::::::
I
sll,
a
0
LE
~DIT ~
0
LE
:
SL2.
-r-n.
~
i
17
@~1
(11)
0
o
LE
a
•
SL2.
'--------<<}~.10~--------------rHH_++rr~++_H~_+HH_+rh~++~~+_----------------------------------------~
(121
Vcc[ill
o
3
4
7
8
11
12
15 18
19
20
23
24
27
28
31
(13)
155590-8
(concluded)
GlDIill-J..
(14) •
PALCE16V8HD-15
2-145
~AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Ambient Temperature
with Power Applied ............ -55°C to + 125°C
Temperature (TA) Operating
in Free Air ....................... O°C to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ............ +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . .. -0.5 V to Vcc + 0.5 V
DC Output or lID
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . .. 2001 V
Latchup Current
(TA = O°C to 75°C) ..................... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
Totem-pole Configuration
IOH =-16 mA
Vee == Min
VIN = VIH or Vil
VOL
Output LOW Voltage
IOl = 64 mA
Vee = Min
VIN = VIH or Vil
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
Min
Hysteresis (Notes 2 and 3)
Vee = Min
hH
Input HIGH Leakage Current
VIN = 5.25 V, Vee = Max (Note 4)
III
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 4)
IOZH
Off-State Output Leakage
Current HIGH
Your = 5.25 V, Vee = Max
VIN = VIH or Vil (Note 4)
IOZl
Off-State Output Leakage
Current LOW
Your = 0 V, Vee = Max
VIN = VIH or VIL (Note 4)
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 5)
Icc
Supply Current
Outputs Open (lOUT = 0 mA)
Vee = Max, f = 25 MHz
VHYS
Max
Unit
2.4
V
0.5
2.0
V
0.8
200
-30
V
V
mV
10
).LA
-10
).LA
10
JlA
-10
JlA
-150
mA
115
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Hysteresis is the difference between the positive going input threshold voltage and the negative going input
threshold voltage.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is
modified where these parameters may be affected.
4. 110 pin leakage is the worst case of liL and IOZL (or liH and IOZH).
5. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT == 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-146
PALCE16V8HD-15 (Com'l)
AMD~
CAPACITANCE
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT= 2.0 V
I
I
Vee = 5.0 V, TA = 25°C,
f= 1 MHz
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
tPD
Input, I/O, or Feedback to Combinatorial Output
Max
Unit
15
ns
ts
Setup Time from Input, I/O, or Feedback to Clock
10
ns
tH
Register Data Hold Time
0
ns
teo
Clock to Output
twL
tWH
Clock
Width
fMAX
Maximum
Frequency
(Note 3)
10
lLOW
I HIGH
External Feedback 11/(ts + teo)
Internal Feedback (feNT)
11/(twL + tWH)
No Feedback
ns
6
6
ns
ns
50
MHz
66
MHz
83.3
MHz
ns
tSIL
Input Latch Setup Time
4
tHIL
Input Latch Hold Time
6
tlGO
Input Latch Enable to Combinatorial Output
ns
15
ns
Input Latch Enable Width HIGH
15
tlGS
Input Latch Enable to Output Register Setup Time
10
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input Latch
tSLR
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Register
tHLR
Hold Time from Input, I/O or Feedback
Through Input Latch to Output Register
tpzx
DE to Output Enable
15
ns
tpxz
DE to Output Disable
15
ns
tWIGH
ns
ns
ns
15
10
ns
0
ns
tEA
Input, I/O, or Feedback to Output Enable
15
ns
tER
Input, I/O, or Feedback to Output Disable
15
ns
tEAL
Input, I/O, or Feedback to Output Enable
Through Transparent Latch (Note 3)
15
ns
tERL
Input, I/O, or Feedback to Output Disable
Through Transparent Latch (Note 3)
15
ns
Notes:
2. See Switching Test Circuit, page 15, for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE16V8HD-15 (Com'l)
2-147
~
AMD
SWITCHING WAVEFORMS
Input,
~(
,~ V
I/O,or _ _ _--'/\_ _ _ _ _--'Jr\. T
Feedback
~
Input,
VO, or
Feedback
Combinatorial
Output
-~-VT
Clock
ts
tH
~ VT
________________
'~2OCiktco
VT
Registered
Output _ _ _ _ _ _ _ _---'
155590-10
155590-9
Registered Output
Combinatorial Output
Latched
Input
Latched
Input
LE tSLR --f'I1I-~""'LE
Clock-----
Combinatorial
Output _ _--t"-'
Registered
Output _ _ _ _..L.JI'-_ _ _ _ _ _-'-II..M'I'155590-12
155590-11
Latched Input with
Registered Output
Latched Input with
Combinatorial Output
Input
Latched
Latch
Enable
Clock
VTLatched
155590-14
155590-13
Input Latch Enable Width
Clock Width
Notes:
1. VT= 1.5V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns - 5 ns typical.
2-148
PALCE16V8HD-15
AMD~
SWITCHING WAVEFORMS
Input,---~
1/0, or
Feedback - - - - - '
tER
>-+-+H-----f-+-4H- VT
Output
tpxz
tEA
Output
tpzx
>-+-+H-.....;..;;;.;.;...~~-+-4H-
_ _ _ _--L..L..I.:....II
VT
------L~"_1
155590-16
155590-15
Input to Output Disable/Enable
DE
to Output Disable/Enable
Latched _ _ _~
Input,
1/0, or
Feedback - - - - - '
tERL
tEAL
Output
155590-17
Input to Output Disable/Enable
Through Transparent Latch
4 r'
4-1-r'_ _ _"'T""'"I
3
3
Vo
Output Voltage 2
Vo
Output Voltage 2
VTH
I
1
11
_I
I
1
2
3
4
VI
Input Voltage
Notes:
0
I
0
I
I
I
I
1
2
3
4
VI
Input Voltage
155590-18
155590-19
1. Vr= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns - 5 ns typical.
PALCE16V8HD-15
2-149
~
AMD
KEY 10 SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/77//
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
xxxxxx
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
SV
Output 0 - -. . .- - -......-"'") Test Point
15559D-20
Commercial
Specification.
S1
tpo, tpOl, teo
Closed
tpzx, tEA, tEAL
Z~
tpxz, tER, tERl
Cl
R1
Measured
Output Value
1.S V
H: Open
Z ~ L: Closed
SO pF
H ~Z: Open
S pF
1.S V
80n
160n
H ~ Z: VOH - O.S V
L ~Z: Closed
2-150
R2
L ~ Z: VOL + O.S V
PALCE16V8HD-15
AMD~
ENDURANCE CHARACTERISTICS
The PALCE16V8HD is manufactured using AMD's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
Endurance Characteristics
Symbol
Parameter
Min
Unit
Max Storage
Temperature
10
Years
Test Conditions
tOR
Min Pattern Data Retention Time
Max Operating
Temperature (Military)
20
Years
N
Min Reprogramming Cycles
Normal Programming
Conditions
100
Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vcc
ESD
ProgramlVerify
Protection
Circuitry
Typical Input
Vee
Preload
Circuitry
Typical Output
PALCE16V8HD-15
Feedback
Input
15559D·21
2-151
~
AMD
MEASURED SWITCHING CHARACTERISTICS for the PALCE16V8HD-15 (Note 1)
12
11
tPD. ns
10
9
8
o
50
100
150
200
250
300
CL. pF
tPD vs. Load Capacitance
Vee
=5.25 V, TA =25°C
155590-22
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where tPD may be affected.
2-152
PALCE16V8HD-15
AMD~
POWER-UP RESET
The PALCE16V8HD has been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization.
A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
Parameter
Symbol
and the wide range of ways Vec can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
•
•
The Vcc rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions
Min
tPR
Power-Up Reset Time
ts
Input or Feedback Setup Time
Max
Unit
1000
ns
See Switching Characteristics
Clock Width LOW
tWL
4
Power
Registered
Output
Clock
v-jL----------------f~
...
L.I-__ tPR
Vcc
~
II
'\
tWL
155590-23
Power-Up Reset Waveform
PALCE16V8HD-15
2-153
~AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
PALCE16V8HD-15
Parameter
Symbol
Typ.
PLCC
Unit
9jc
Thermal impedance, junction to case
22
17
9ja
Thermal impedance, junction to ambient
70
55
200 Ifpm air
65
47
400 Ifpm air
60
42
600 Jfpm air
56
38
800 Ifpm air
53
36
°elW
°elW
°elW
°elW
°elW
°elW
9jma
Parameter Description
Thermal impedance, junction to
ambient with air flow
SKINNYDIP
Plastic alc Considerations
The data listed for plastic 9jc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the 9jc measurement relative to a specific location on the .
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom centerof the
package. Furthermore, 9jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
2-154
PALCE16V8HD-15
~
_COM'L
Advanced
Micro
Devices
AmPAL 18P88/AL/A/L
20-Pin Combinatorial TTL Prorammable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
As fast as 15 ns maximum propagation delay
Universal combinatorial architecture
Programmable output polarity
Programmable replacement for high-speed
TIL logic
•
Extensive third-party software and programmer
support through FusionPLD partners
20-pin DIP and 20-pin PLCC packages save
space
GENERAL DESCRIPTION
The Am PAL 18P8 utilizes Advanced Micro Devices' advanced oxide-isolated bipolar process and fuse-link
technology. The devices provide user-programmable
logic for replacing conventional SSI/MSI gates and flipflops at a reduced chip count.
The AmPAL 18P8 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to
the desired logic function. Complex interconnections
between gates, which previously required timeconsuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified during prototyping or production.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs. In addition, the PAL device provides the following options:
-
Variable inpuVoutput pin ratio
-
Programmable three-state outputs
Product terms with all fuses opened assume the logical
HIGH state; product terms connected to both true and
complement of any single input assu me the logical LOW
state. Unused input pins should be tied to Vcc or GND.
The entire PAL device family is supported by the
FusionPLD partners. The PAL family is programmed on
conventional PAL device programmers with appropriate
personality and socket adapter modules. See the Programmer Reference Guide for approved programmers.
Once the PAL device is 'programmed and verified an additional fuse may be opened to prevent pattern readout.
This feature secures proprietary circuits.
BLOCK DIAGRAM
AmPAL18P8
Inputs
1/0
1/0
Publication# 05799 Rev. G AmendmentiO
Issue Date: January 1992
1/0
1/0
1/0
1/0
1/0
1/0
OS799G-1
2-155
~
AMD
PRODUCT SELECTOR GUIDE
tpo
Icc
IOL
Family
ns (Max)
mA{Max)
mA{Mln)
Very High-Speed
("B") Versions
15
180,
24
High-Speed
("Ai Versions
25
180
24
High-Speed,
Half-Power
("AL") Versions
25
90
24
Half-Power
("Li Versions
35
90
24
CONNECTION DIAGRAMS
Top View
DIP
PLCC
~ ~
vee
1/0
3
2
1/0
1/0
1/0
110
1/0
1/0
1/0
9
10 11 12 13
(!)
05799G-2
Note:
Pin 1 is marked for orientation.
g
~
05799G-3
PIN DESIGNATIONS
2-156
1/0
1/0
0
Z
1/0
18
1/0
GND
Vee
•
20 19
1/0
1/0
GND
I
1
Ground
Input
Input/Output
Supply Voltage
AmPAL 18P8B/AUAlL
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
AmPAL 18
P
8
ALP C
____J----I -,... -.- -.. . -.. .
_
FAMILY TYPE
AmPAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _ _.....J
L
OPTIONAL PROCESSING
Blank = Standard Processing
P = Programmable Polarity
OPERATING CONDITIONS
C = Commercial (O°C to +7S0 C)
NUMBER OF OUTPUTS _ _ _ _ _ _----J
SPEED --------------~
B = 15 ns tPD
A = 25 ns tPD
Blank = 35 ns tPD
POWER _ _ _ _ _ _ _ _ _ _ _ _ _----J
PACKAGE TYPE
P = 20-Pin Plastic DIP
(PD 020)
J = 20-Pin Plastic Leaded
Chip Carrier (PL 020)
D = 20-Pin Ceramic DIP
(CD 020)
L = Low Power (90 mA Icc)
Blank = Full Power (180 mA Icc)
Valid Combinations
AmPAL18P8
PC, JC, DC
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
AmPAL18P88/ALlA/L (Com'l)
2-157
~
AMD
FUNCTIONAL DESCRIPTION
All parts are produced with a fuse link at each input to the
AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit.
Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any
customized pattern. Information on approved programmers can be found in the Programmer Reference Guide.
Extra test words are pre-programmed during manufacturing to ensure extremely high field programming
yields, and provide extra test paths to achieve excellent
parametric correlation.
Variable Input/Output Pin Ratio
The AmPAL 18P8 has ten dedicated input lines, and all
eight combinatorial outputs are I/O pins. Buffers for device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GND.
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional 110 pin, and may be configured as a dedicated input if the buffer is always disabled.
Programmable Polarity
The polarity of each output can be active-high or activelow, either to match output signal needs or to reduce
product terms. Programmable polarity allows Boolean
2-158
expressions to be written in their most compact form
(true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts.
Selection is through a programmable fuse which controls an exclusive-OR gate at the output of the AND/OR
logic. The output is active high if the fuse is 1 (programmed) and active low if the fuse is 0 (intact).
Security Fuse
After programming and verification, an AmPAL 18P8 design can be secured by programming the security fuse.
Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the
security fuse is programmed, the array will read as if
every fuse is programmed.
Quality and Testability
The AmPAL 18P8 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In
addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Technology
The AmPAL18P8 is fabricated with AMD's advanced
oxide-isolated bipolar process. This process reduces
parasitic capacitances and minimum geometries to pro~
vide higher performance. The array connections are
formed with proven PtSi fuses for reliable operation.
AmPAL 18P88/AUA/L
AMD~
LOGIC DIAGRAM
Inputs (0-35)
ell
1
Zl
4a.,
all01'
12"'4"
,1",St,
2OZ1un
24:r5H17
2eZlla31
3233)435
2-
··
···
r-
,
,.
~~
d:::7
~~
7
0--ti=
,.
....
·
r~6-r
,.,."
,.,.
"
~
~
!:~
<
,.,.
...,
..
r-
n
..... ~
2
rb&r
rE>t&r
rb&r
~b&r
t:~
_
. . .R
2<
....
...,
.,.
....
..... ~
..... ~
~~
3D
~tj
2-
..
....
~~
...,
...
....
2
....
.,
..
...
.
.
';
r-~
;:::~
ct::1
2
14
....
';
r-
~~&r
::tj
';
rH
07
§:=J
51
..
...
...."
51
13
~
rE>t&r
r-
;~
.
II
17
II
7D
12
t:tj
7'
9
.....
,--
50
8
15
.....~
J-J
.7
7
~
16
'<
.....
37
6
17
r-
~
5
~
>
24
4
18
~'-
17
3
~
:>
';
<
<,
4
~
Ii
7
e
I 1Q 11
1213 '" 15
16111811
2Q
21 22 23
242526 27
28 2130 31
11
323334 35
05799G-4
Am PAL 18P8B/AUAlL
2-159
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied ............. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air ............ O°C to +75°C
Supply Voltage with
Respect to Ground ............. -D.5 V to +7.0 V
-Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . . . . . .. -0.5 V to +5.5 V
DC Input Current .............. -30 rnA to +5 rnA
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC 1/0 Pin Voltage ............ -D.5 V to Vce Max
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = -3.2 rnA
VIN = VIH or VIL
Vee = Min
Min
VOL
Output LOW Voltage
IOl= 24 rnA
VIN = VIH or VIL
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
' Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
Max
Unit
V
2.4
0.5
2.0
V
V
0.8
V
VI
Input Clamp Voltage
liN = -18 rnA, Vee = Min
-1.2
V
111-1
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 2)
25
~
III
Input LOW Current
VIN = 0.4 V, Vee = Max (Note 2)
-100
~
Ii
Maximum Input Current
VIN = 5.5 V, Vee = Max
1
mA
lozH
Off-State Output Leakage
Current HIGH
VOUT= 2.7 V, Vee = Max
VIN = VIH or VIL (Note 2)
100
~
lozl
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vee = Max
VIN = VIH or Vil (Note 2)
-250
~
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
-90
mA
Icc
Supply Current
VIN = 0 V, Outputs Open
(loUT = 0 rnA)
Vee = Max
B,A
180
mA
AL
90
mA
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system andlor tester noise are included.
2. liD pin leakage is the worst case of hL and IOZL (or iJH and loZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-160
AmPAL 18P8B/AUA/L (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
YOUTz:
Typ
2.0 V
Vee = 5.0 V
6
TA = +25°C
f .. 1 MHz
9
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
A AL
B
Parameter Description
Min
Max
L
Max
Unit
25
35
ns
15
25
35
ns
15
25
35
ns
tPD
Input or Feedback to
Combinatorial Output
15
tEA
Input to Output Enable
Using Product Term Control
tER
Input to Output Disable
Using Product Term Control
Min
Max
Min
Note:
2. See Switching Test Circuit for test conditions.
AmPAL18P88/AL/A/L (Com'l)
2-161
~
AMD
SWITCHING WAVEFORMS
Input or
Feedback
Input
_ _ _---I
tER
Combinatorial
Output
Output
------'-..1-1.-1
OS799G-S
05799G-6
Input to Output Disable/Enable
Combinatorial Output
Notes:
1. VT= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns-5 ns typical.
2-162
tEA
AmPAL 18P8B/AUA/L
AMD~
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/77//
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
XXXXXX
]})
EK
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Ou1put o--.....- - -.....~~) Test Point
05799G-7
Specification
tPD
tEA
tER
S1
CL
R1
R2
1.5 V
Closed
Z~ H: Open
Z ~ L: Closed
H ~Z: Open
L
~Z:
Measured
Output Value
Closed
50 pF
1.5 V
2000
5 pF
AmPAL 18P8B/AUAlL
3900
H ~ Z: VOH - 0.5 V
L ~ Z: VOL + 0.5 V
2-163
~
AMD
INPUT/OUTPUT EQUIVALENT SCHEMATICS
----------------~--~~c
Input
ProgramlVerify
Circuitry
05799G-8
Typical Input
-----------------4~----~ ~c
40
n NOM
Output
Input.
110
Pins
ProgramlVerifyl
Test Circuitry
05799G-9
Typical Output
2·164
AmPAL 18P88/AUA/L
_
COM'L: -517IB/B-2/A,10/2
~
MIL: -10/12/15/B/A
Advanced
Micro
Devices
PAL20R8 Family
24-Pin TTL Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
As fast as 5 ns maximum propagation delay
Popular 24-pln architectures: 20LS, 20RS,
20R6,20R4
•
•
Power-up reset for Initialization
Extensive third-party software and programmer
support through FusionPLD partners
•
Programmable replacement for high-speed TTL
logic
•
24-pln SKINNYDIP and 2S-pln PLCC packages
save space
GENERAL DESCRIPTION
The PAL20RS Family (PAL20LS, PAL20RS, PAL20R6,
PAL20R4) includes the PAL20RS-5 Series which is
ideal for high-performance applications. The PAL20RS
Family is provided in the standard 24-pin DI P and 2S-pin
PLCC pinouts.
In addition, the PAL device provides the following
options:
The devices provide user programmable logic for replacing conventional SSI/LSI gates and flip-flops at a reduced chip cost.
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state: Registers consist of D-type flip-flops that are
loaded on the LOW-to-HIGH transition of the clock.
Unused input pins should be tied to Vcc or GND.
The family allows the systems engineer to implement
the design on-chip, by opening fuse links to configure
AND and OR gates within the device, according to the
desired logic function. Complex interconnections between gates, which previously required time-consuming
layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products.·The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
-
Variable inpuVoutput pin ratio
Programmable three-state outputs
Registers with feedback
AM D's FusionPLD program allows PAL20RS Family designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuringthatthirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
PRODUCT SELECTOR GUIDE
Device
Dedicated Inputs
Outputs
Product Terms/Output
Feedback
Enable
PAL20La
14
6 comb.
2 comb.
7
7
a
a
7
a
7
I/O
prog.
prog.
PAL20Ra
12
a reg.
PAL20R6
12
PAL20R4
12
6 reg.
2 comb.
4 reg.
4 comb.
Publication# 16490 Rev. B AmendmentlO
Issue Date: June 1993
reg.
reg.
1/0
reg.
1/0
pin
pin
prog.
pin
prog.
2-165
~
AMD
BLOCK DIAGRAMS
PAL20L8
INPUTS
PROGRAMMABLE
AND ARRAY
(40 X 64)
1105
1IC>.3
AS
164908-1
PAL20R8
elK
PROGRAMMABLE
AND ARRAY
(40 X 64)
164908-2
2-166
PAL20R8 Family
AMD~
BLOCK DIAGRAMS
PAL20R6
CLK
INPUTS
PROGRAMMABlE
AND ARRAY
(40 X 64)
PAL20R4
ClK
INPUTS
PROGRAMMABLE
AND ARRAY
(40 X 64)
05
110 a
1/0 7
164908-4
PAL20R8 Family
2-167
~AMD
CONNECTION DIAGRAMS
Top View
SKINNVDIP/FLATPACK
PLCC/LCC
JEDEC: Applies to -5, -7(-12110 mil),
(Note 1)
-10(-15 mil), B-2 Series Only
Vee
11
12
112
13
(Note 9)
14
(NoteS)
15
Is
(Note 7)
17
Is
(Note 5)
19
110
(Note 3)
GND
(Note 2)
(Note 10)
1 28 27 26
•
(Note 6)
25
(NOTE 9)
24
(NOTE 8)
23
(NOTE 7)
22
NC
(Note 4)
111
16490B-6
16490B-5
PLCC
Applies to B and A Series Only
Note: Pin 1 is marked for orientation.
(NOTE 9)
Note
20L8
20R8
20R6
20R4
14
6
(NOTE 8)
1
10
elK
elK
elK
15
7
(NOTE 7)
NC
8
(NOTE 6)
OE
OE
OE
16
9
3
113
01
1/01
1/01
?
10
4
1/02
1/03
6
1/04
7
S
1/05
I/0s
05
Os
9
1/07
10
Os
07
Os
02
03
04
05
Os
07
lIDs
1/02
5
01
02
03
04
2
03
04
05
Os
1/07
(NOTE 4)
16490B-7
LCC
Applies to B and A Series Only
lIDs
§"
w
f-
I
1/0
NC
o
OE
Vee
2-168
I-
~~~~J~~
PIN DESIGNATIONS
ClK
Clock
GND
W
Ground
Input
Input/Output
No Connect
Output
Output Enable
Supply Voltage
NC
(NOTE 9)
(NOTE 8)
(NOTE 7)
(NOTE 6)
(NOTE 5)
(NOTE 4)
PAl20R8 Family
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
PAL
T
20
-,-
R 8-5
-r-
FAMILY TYPE
PAL = Programmable Array Logic
P C
L
OPTIONAL PROCESSING
Blank = Standard Processing
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE - - - - - - - - - - "
R = Registered
L = Active-low combinatorial
1...-__
OPERATING CONDITIONS
C = Commercial (O°C to +7S0C)
NUMBER OF OUTPUTS - - - - - - - - - - '
SPEED
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
PACKAGE TYPE
P = 24-Pin (300 mil) Plastic SKINNYDIP
(PD3024)
J = 2S-Pin Plastic Leaded Chip Carrier
(PL 02S)
D = 24-Pin (300 mil) Ceramic SKINNYDIP
(CD3024)
VERSION - - - - - - - - - - - - - - - 1
Blank = Revision 1
12 = Revision 2
Valid Combinations
PAL20LS-5
PAL20RS-S
PAL20R6-S
PAL20R4-S
PAL20LS-10/2
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult·
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PC,JC
PAL20RS-10/2
PAL20R6-1 012
PAL20R4-1012
PAL20LS-7
PAL20RS-7
PAL20R6-7
PC, JC, DC
PAL20R4-7
PAL20R8-S17, -10/2
2-169
~
AMD
ORDERING INFORMATION
Commercial Products (MMI Marking Only)
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
.
PAL
T
20
-~
R 8 B -2
-,---r
FAMILY TYPE
PAL = Programmable Array Logic
C NS
11
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS - - - - - - - - - '
SPEED
B = Very High Speed (15 - 25 ns tpo)
A = High speed (25 - 35 ns tpo)
L...-_ _ _ _ _
----------------1
POWER
Blank
Full Power (210 mA Icc)
-2 = Half Power (105 mA Icc)
CNS, CFN. CJS
B.A
CNS. CNL, CJS
PAL20R8
PAL20R6
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
B-2
Blank = Standard Processing
PACKAGE TYPE
NS = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
FN = 28-Pin Plastic Leaded
Chip Carrier (PL 028),
JEDEC pinout
NL = 28-Pin Plastic Leaded
Chip Carrier (PL 028).
non.JEDEC pinout
JS = 24-Pin 300 mil Ceramic
SKINNYDIP (CD3024)
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _ _--1
PAL20L8
OPTIONAL PROCESSING
PAL20R4
Note: Marked with MMllogo.
2-170
PAL20R8B/AlB-2
AMD~
ORDERING INFORMATION
APL Products
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of:
20
PAL
FAMILY TYPE
PAL = Programmable Array Logic
J
R 8 -10/B L A
L
LEAD FINISH
A = Hot Solder Dip
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
R = Registered
L = Active-low combinatorial
PACKAGE TYPE
L = 24-Pin (300·mil) Ceramic
SKINNYDIP (CD3024)
3 = 28-Pin Ceramic
Leadless Chip Carrier (CL 028) .
NUMBER OF OUTPUTS
SPEED
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
DEVICE CLASS
IB = Class B
Valid Combinations
PAL20L8
PAL20R8
PAL20R6
-10, -12, -15
IBLA,/B3A
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PAL20R4
Group A Tests
Group A Tests consist of Subgroups:
1,2,3, 7, 8, 9, 10, 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through
Test conditions are selected at AMD's option.
PAL20 R8-1 0/12/15 (Mi I)
E.
2-171
~AMD
ORDERING INFORMATION
APL Products (MMI Marking Only)
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination)
is formed bya combination of:
PAL
T
20
R 8 A
------r--
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
M JS/883B
L
PACKAGE TYPE (Per 09-000)
JS = 24-Pin 300-Mil Ceramic
SKINNYDIP (CD3024)
W
24-Pin Ceramic Flatpack
"(CFL024)
L
28-Pin Ceramic Leadless
Chip Carrier (CL 028)
OUTPUT TYPE - - - - - - - - - - '
R = Registered
L = Active-Low Combinatorial
NUMBER OF OUTPUTS - - - - - - - - - - '
SPEED
B = Very High Speed (20 ns tPD)
A = High speed (30-50 ns tPD)
OPTIONAL PROCESSING
/883B = MIL-STD-883, Class B
' - - - - - - OPERATING CONDITIONS
M = Military
POWER
Blank = Full Power (210 rnA Icc)
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PAL20L8
PAL20R8
PAL20R6
PAL20R4
B,A
MJS/883B,
MW/883B,
MU883B
Note: Marked with MMllogo.
Group A Tests
Group A Tests consist of Subgroups:
1,2,3, 7, 8, 9, 10, 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through E.
Test conditions are selected at AMD's option.
2·172
PAL20R8B/A (Mil)
AMD~
FUNCTIONAL DESCRIPTION
Standard 24-Pin PAL Family
Register Preload
The standard 24-pin PAL family is comprised of four different devices, including both registered and combinatorial devices. All parts are produced with a fuse link at
each input to the AND gate array, and connections may
be selectively removed by applying appropriate voltages to the circuit. Using any of a number of development packages, these products can be rapidly
programmed to any customized pattern. Extra test
words are pre-programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric
correlation.
Variable Input/Output Pin Ratio
The registered devices have twelve dedicated input
lines, and each combinatorial output is an 1/0 pin. The
PAL20L8 has fourteen dedicated input lines, and only
six of the eight combinatorial outputs are 1/0 pins. Buffers for device inputs have complementary outputs to
provide user-programmable input signal polarity.
Unused input pins should be tied to Vee or GND.
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. On combinatorial outputs, a product term
controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional
lID pin, and may be configured as a dedicated input if
the buffer is always disabled. On registered outputs, an
input pin controls the enabling of the three-state outputs.
Registers with Feedback
Registered outputs are provided for data storage and
synchronization. Registers are composed of D-type flipflops that are loaded on the LOW-to-HIGH transition of
the clock input.
The register on the PAL20R8 Family can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
Security Fuse
After programming and verification, a PAL20R8 Family
, design can be secured by programming the security
fuse. Once programmed, this fuse defeats read back of
the internal programmed pattern by a device programmer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will
read as if every fuse is intact.
Quality and Testability
The PAL20R8 Family offers a very high level of built-in
quality. Extra programmable fuses provide a means of
verifying performance of all AC and DC parameters. In
addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Technology
The PAL20R8-5, -7 and 1012 are fabricated with AM D's
oxide isolated process. The array connections are
formed with highly reliable PtSi fuses. The PAL20R8B,
B-2, and A series are fabricated with AMD's trench-isolated bipolar process. The array connections are formed
with proven TiW fuses. These processes reduce parasitic capacitances and minimum geometries to provide
higher performance.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL20R8 Family
will be HIGH due to the active-low outputs. The Vee rise
must be monotonic and the reset delay time is 1000 ns
maximum.
PAL20R8 Family
2-173
~
AMD
LOGIC DIAGRAM
DIP (PLCC) Pinouts
20L8
10 1
(2)
0
3
4
7 8
1112
1516
1920
2324
2728
3132
35 36
24
(28)
j
39
~
(3)
8
~
(27)
l
~
~
3
(4)
"
:r .. ......
22
(26)
16
21
(25)
L
:1
23
4
>
(5)
24
~
..1
.....
~
31
5
.. >
(6)
32
",""r-
" l......
LJ
""1
39
6
(7)
..
..
l.....
.
J
47
""---",""r-
>
48
l
-k
......
55
8
(10)
,
l
L
~
63
9
.>
64
11
(13)
GND
...>
(14)
..
...>
m
l.....
... .-i
71
19 10
(12)
vas
18
(21)
--- ------
17
(20)
<...------
.>
56
(11)
19
(23)
<...------
~
40
-'
7
(9)
201
(24)
0
3
4
7 8
11 12
1516
1920
23 24
2728
31 32
3536
16 I/,,
15
3
(4)
"'"
./
~.
31
...
~
32
.>
39
40
---,........
,......;
,-.. ~
47
7
(9)
~
H
~
H
~
H
10-
-~
6
(7)
~
h
(25)
24
~
5
(6)
(26)
16
23
4
(5)
23
(27)
10-
...
7-
(24)
(23)
(21)
48
....... ~
H
~
H
~
(20)
.
""-
55
8
(10)
>
56
"'"
(19)
63
9
(11)
>
64
"'"
..
t--'
71
19 10
(12)
11
(13)
7-
>
G NO Ii2J---,
(14) ~
.~
~
o
3
4
7 8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39
~
(18)
14 111
(17)
OE
~
(16)
164908-10
PAL20R8 Family
2-175
~
AMD
LOGIC DIAGRAM
DIP (PLCC) Pinouts
20R6
elK
1
(2)
.....
V"
0
3
4
7 8
11 12
1516
1920
2324
2728
3132
35 36
(28)
39
~
J
~
L
3
(4)
22
(26)
:J
I
15
23
(27)
~
16
a
f1l~
........
(25)
23
4
(5)
>
~
~
24
""'"
~
31
5
(6)
~
~
-~
39
~
~
~
""'"
~
47
...
.>
48
""'"
55
8
.,....
...
~
56
--"
63
9
(11)
.,.....
..>
64
,J
~
I-J
71
19 10
(12)
11
(13)
~
~
~
H
...
.>
(14) ~
J
(20)
(19)
15
(18)
14 111
(17)
>
GN D I12l---,
(21)
-~
~
~
(10)
~
h.
(23)
40
--,
7
(9)
~
H
(24)
32
0--.
6
(7)
~
~
o
3
4
78
111215161920232427283132353639
OE
~
(16)
164908-11
2-176
PAL20R8 Family
AMD~
LOGIC DIAGRAM
DIP (PLCC) Pinouts
eLK
1
(2)
20R4
to..
.....
0
3
4
7 8
11 12
1516
1920
23 24
2728
~ Vee
3132
3536
(28)
39
I~
(3)
8
..:
9::!
>
16
~
23
4
(5)
22
(26)
,
24
~
21
(25)
>- ~~
a
(24)
31
5
(6)
.. .>
<
1""1--
32
I--
>--
D--
39
6
(7)
..
~
~
-
40
I--
~
;....J~
47
7
(9)
...>
L..
..:
48
~
~~
(23)
~~
(21)
>-lU ~
(20)
55
8
(10)
->
56
~
63
9
(11)
..
>
64
~
..1.
71
,J 1
19 10
(12)
->
<
11
(13)
->
-r>~ ~
fiil.
(2ii
vcc;:t~~
•
,1 ~L02
~ SGl
40
.ff81
IaX I - - -
(9j'
.r:
...
...
....
=
1.1 -tt
9.. ~
>p ~
0: 1'"
-db
1a
Vcc';oa
. .r:.;
.
•
LOO
SG1
lox
"
~SLOo
(i2)
.L~
10 fi'iI-
.A
<,1'3)
1 1100
(18)
IT
-SG
.f14I
ii7i
.f131
o
(16)
3 4
7 8
11 12 15 16 19 20
2324 27 28 3132 35 36 39
164918-6
(concluded)
PALCE20V8 Family
2-213
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Commercial (C) Devices
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . .. DoC to 75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vcc + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 1/0
Pin Voltage ............... -0.5 V to Vcc + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current
(TA = DoC to 75°C) . . . . . . . . . . . . . . . . . . . .. 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
'
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
IOH =-3.2 rnA
Min
VIN = VIH or Vil
Max
2.4
Unit
V
Vee = Min
VOL
Output LOW Voltage
IOl '" 24 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
hH
Input HIGH Leakage Current
VIN = 5.25 V, Vee'" Max (Note 2)
III
Input LOW Leakage Current
VIN '" 0 V, Vee '" Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
VOUT '" 5.25 V, Vee = Max
VIN '" VIH or Vil (Note 2)
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or Vil (Note 2)
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Ice
Supply Current
(Static)
Outputs Open (lOUT = 0 rnA), VIN = 0 V
Vee = Max
0.5
VIN '" VIH or Vil
V
2.0
V
V --
·O.S·
-30
10
~
-100
~
10
~
-100
~
-150
rnA
125
rnA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of hL and IOZL (or hH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2·214
PALCE20V8H-5 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Descriptions
Test Conditions
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT=2.0V
I
I
Typ
Unit
Vcc = 5.0 V. TA = 25°C.
5
pF
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
(Note 5)
Max
Unit
5
ns
tpD
Input or Feedback to Combinatorial Output
1
ts
Setup lime from Input or Feedback to Clock
3
tH
Hold Time
0
Clock to Output
1
tco
tSKEWR
Skew Between Registered Outputs (Note 4)
twH
Clock Width
HIGH
External Feedback
fMAX
Maximum
Frequency
(Note 3)
ns
4
ns
1
ns
3
LOW
twL
ns
I
1/(ts+tco)
Internal Feedback (tCNT)
No Feedback
I
1/(tWH+twL)
ns
3
ns
142.8
MHz
166
MHz
166
MHz
tpzx
OE to Output Enable
1
6
ns
tpxz
OE to Output Disable
1
5
ns
tEA
Input to Output Enable Using Product Term Control
.2
6
ns
tER
Input to Output Disable Using Product Term Control
2
5
ns
Notes:
2. See Switching Test Circuit for test conditions.
3.
These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Skew testing takes into account pattern and switching direction differences between outputs that have equalloading.
5. Output delay minimums for tpo, teo, tpzx, tpxz, tEA, and tER are defined under best case conditions. Future process
improvements may alter these values therefore, minimum values are recommended for simulation purposes only.
PALCE20V8H-5 (Com'l)
2-215
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Com~erclal
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 0.5 V
DC Output or 1/0
Pin Voltage ............... -0.5 V to Vee + 0.5 V
(C) Devices
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . .. . . . . .. O°C to 75°C
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latehup Current
(TA = O°C to 75°C) . . . . . . . . . . . . . . . . . . . .. 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Min
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 mA
Vee = Min
VOL
Output LOW Voltage
IOL = 24 mA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
VIN = VIH or VIL
Input HIGH Leakage Current
VIN = 5.25 V, Vee = Max (Note 2)
ilL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, Vee = Max
VIN = VIH or VIL (Note 2)
lozl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 2)
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
(Dynamic)
Outputs Open (lOUT = 0 mA)
Vee = Max, f = 25 MHz
Unit
V
V
0.5
VIN = VIH or VIL
IIH
Max
2.4
V
2.0
V
0.8
---_ .. _-
-30
_._-_ .. _----
10
~
-100
~
10
~
-100
~
-150
mA
115
mA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system andlor tester noise are included.
2. 110 pin leakage is the worst case of ItL and 10zL (or I/H and 10zH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-216
PALCE20V8H-7 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Descriptions
Typ
Test Conditions
Input Capacitance
VIN= 2.0V
Output Capacitance
VOUT=2.0 V
I
I
Unit
Vee = 5.0 V, TA = 25°C,
5
pF
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
tPD
Parameter Description
Input or Feedback to Combinatorial Output
I 8 Outputs Switching
I 1 Output Switching
Min
Max
3
7.5
ns
3
7
ns
ts
Setup Time from Input or Feedback to Clock
5
tH
Hold Time
0
tco
Clock to Output
1
tSKEWR
twL
Skew Between Registered Outputs (Note 4)
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 3)
Unit
ns
ns
5
ns
1
ns
LOW
4
ns
HIGH
4
ns
100
MHz
125
MHz
External Feedback
I
1/(ts+tco)
I
1/(tWH+tWL)
Internal Feedback (fCNT)
No Feedback
125
MHz
tpzx
OE to Output Enable
1
6
ns
tpxz
OE to Output Disable
1
6
ns
tEA
Input to Output Enable Using Product Term Control
3
9
ns
tER
Input to Output Disable Using Product Term Control
3
9
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
5. Output delay minimums for tPD, tco, tpzx, tpxz, tEA, and tER are defined under best case conditions. Future process
improvements may alter these values therefore, minimum values are recommended for simulation purposes only.
PALCE20V8H-7 (Com'l)
2-217
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Commercial (C) Devices
Temperature (TA) Operating
in Free Air ..................... DoC to 75°C
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 0.5 V
DC Output or 110
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latehup Current
(TA = DoC to 75°C) ..................... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 mA
Vee = Min
VOL
Output LOW Voltage
IOl = 24 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Noto 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
Min
VIN = VIH or Vil
Input HIGH Leakage Current
VIN = 5.25 V, Vee = Max (Note 2)
IlL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
Your = 5.25 V, Vee = Max
VIN = VIH or Vil (Note 2)
lOll
Off-State Output Leakage
Current LOW
Your = 0 V, Vee = Max
VIN = VIH or Vil (Note 2)
Ise
Output Short-Circuit Current
Your = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
(Dynamic)
Outputs Open (lour = 0 mAl
Vee = Max, f = 25 MHz
Unit
2.4
V
0.5
VIN = VIH or Vil
hH
Max
V
2.0
V
0.8
--
......
10
-30
V
---
~
-10
~
10
~
-10
~
-150
mA
115
mA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. //0 pin leakage is the worst case of hL and lozL (or hH and lozH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-218
PALCE20V8H-10 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT = 2.0 V 1 f = '1 MHz
1 Vee = 5.0 V, TA = 25°C,
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
(Note 4)
Max
Unit
3
10
ns
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
0
Clock to Output
3
teo
tWL
Clock Width
tWH
tMAX
Maximum
Frequency
(Note 3)
7.5
ns
ns
7.5
ns
LOW
6
HIGH
6
ns
66.7
MHz
Internal Feedback (teNT)
71.4
MHz
No Feedback
83.3
MHz
External Feedback
11I(ts+tcO)
11/(twH+twL)
ns
tpzx
OE to Output Enable
2
10
ns
tpxz
OE to Output Disable
2
10
ns
tEA
Input to Output Enable Using Product Term Control
3
10
ns
tER
Input to Output Disable Using Product Term Control
3
10
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Output delay minimums for tPD, tco, tpzx, tpxz, tEA, and tER are defined under best case conditions. Future process
improvements may alter these values therefore, minimum values are recommended for simulation purposes only.
PALCE20V8H-10 (Com'l)
2-219
~
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . .. O°C to 75°C
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with.
Respect to Ground :............ -0.5 V to +7.0 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 0.5 V
DC Output or I/O
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latchup Current
(TA = O°C to 75°C) ..................... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
PRELIMINARY
Parameter
Symbol
Min
Parameter Description
Test Conditions
VOH
Output HIGH yoltage
IOH =-3.2 rnA
Vee = Min
VOL
Output LOW Voltage
IOL = 24 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
VIN = 5.25 V, Vee = Max (Note 2)
IlL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, Vee = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 2)
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
(Dynamic)
Outputs Open (lOUT = 0 rnA)
Vee = Max, f = 15 MHz
VIN = VIH or VIL
Max
Unit
2.4
V
0.5
VIN = VIH or VIL
V
2.0
-30
V
0.8
V
10
~
-10
~
10
~
-10
~
-150
rnA
55
rnA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of hL and IOZL (or I/H and IOZH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-220
PALCE20VSQ-10 (Com'l)
AMD~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
I Vee = 5.0 V, TA = 25°C,
I f = 1 MHz
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
PRELIMINARY
Parameter
Symbol
Parameter Description
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
teo
tWL
Clock Width
fMAX
Maximum
Frequency
(Note 3)
tpzx
OE to Output Enable
tpxz
tEA
tER
Max
3
10
Unit
ns
7.5
ns
0
ns
3
Clock to Output
tWH
Min
(Note 4)
7.5
ns
LOW
6
ns
HIGH
6
ns
66.7
MHz
Internal Feedback (feNT)
71.4
MHz
No Feedback
83.3
External Feedback
11I(ts+teo)
11/(twH+twL)
MHz
2
10
ns
OE to Output Disable
2
10
ns
Input to Output Enable Using Product Term Control
3
10
ns
Input to Output Disable Using Product Term Control
3
10
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modifi9d
where frequency may be affected.
4. Output delay minimums for tPD, teo, tpzx, tpxz, tEA, and tER are defined under best case conditions. Future process
improvements may alter these values therefore, minimum values are recommended for simulation purposes only.
PALCE20VaQ-10 (Com'l)
2-221
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Commercial (C) Devices
Temperature (TA) Operating
in Free Air .................... O°C to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage ............. -0.5 V to Vee + 0.5 V
Static Discharge Voltage .......' .......... 2001 V
Latchup Current
(TA = O°C to +75°C) .................... 100 rnA
Stresses above those listed under Absolute Maximum Rat, ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Min
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 rnA
Vee = Min
VOL
Output LOW Voltage
IOl = 24 mA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
III
Input LOW Leakage Current
= 5.25 V, Vee = Max (Note 2)
VIN = 0 V, Vee = Max (Note 2)
VOUT = 5.25 V, Vee = Max
VIN = VIH or Vil (Note 2)
VOUT = 0 V, Vee = Max
VIN = VIH or Vil (Note 2)
VOUT = 0.5 V, Vee = Max (Note 3)
Outputs Open (lOUT = 0 rnA)
I
Vee = Max, f = 15 MHz
I
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Isc
Output Short-Circuit Current
Icc
Supply Current
Unit
2.4
VIN = VIH or Vil
VIN
Max
= VIH or Vil
V
0.5
V
2.0
_
...
VIN
-30
H
Q
V
0.8
--. ._----
.
- -
V..._.. __
10
~
-10
~
10
~
-10
J.1A
-150
rnA
90
55
rnA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of hL and lozL (or hH and lozH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-222
PALCE20V8H-15/25 Q-15/25 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN =2.0 V
Typ
Output Capacitance
VOUT = 2.0 V If = 1 MHz
I Vee = 5.0 V, TA = 25°C ,
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
-15
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
12
tH
Hold Time
0
teo
fMAX
Clock Width
Maximum
Frequency
(Note 3)
Min
15
Max
25
15
Unit
ns
ns
0
10
Clock to Output
tWL
tWH
-25
Max
ns
12
ns
LOW
8
12
ns
HIGH
8
12
ns
45.5
37
MHz
External Feedback 11/(ts+tcO)
Internal Feedback (fCNT)
No Feedback
11/(tWH+tWL)
50
40
MHz
62.5
41.6
MHz
tpzx
OE to Output Enable
15
20
ns
tpxz
OE to Output Disable
15
20
ns
tEA
Input to Output Enable Using Product Term Control
15
25
ns
tER
Input to Output Disable Using Product Term Control
15
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3.
These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE20V8H-15/25 0-15/25 (Com'l)
2-223
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Military (M) Devices (Note 1)
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Operating Case
Temperature (Te) ........... -55°C to'+125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ....... +4.5 V to +5.5 V
DC Input Voltage ........... -0.5 V to Vee + 1.0 V
Note:
1. Military products are tested at Tc = +25"C, + 125"C and
-55"C, per MIL-STD-883.
DC Output or I/O .
Pin Voltage ............... -0.5 V to Vee + 1.0 V
Static Discharge Voltage ................. 2001 V
Latehup Current
(Te =-55°C to +125°C)
................ 100
Operating ranges define those limits between which the functionality of the device is guaranteed.
rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
DC CHARACTERISTICS over MILITARV operating ranges unless otherwise specified
(Note 2)
.
Parameter
Symbol
Parameter Description
Test Conditions
Min
VOH
Output HIGH Voltage
IOH =-2.0 mA
Vee = Min
VOL
Output LOW Voltage
IOl = 12 mA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
0.8
V
hH
Input HIGH Leakage Current
VIN
10
~
hL
Input LOW Leakage Current
= 5.5 V, Vee = Max (Note 4)
VIN = 0 V, Vec = Max (Note 4)
-10
~
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.5 V, Vee = Max
VIN = VIH or Vil (Note 4)
10
IlA
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or Vil (Note 4)
-10
IlA
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee
(Note 5)
-150
mA
Icc
Supply Current
(Dynamic)
Outputs Open (lOUT = 0 mAl
Vee = Max, f = 25 MHz
130
mA
VIN = VIH or Vil
VIN
2.4
= VIH or Vil
= 5.0 V, TA = 25°C
Max
V
0.5
2.0
-30
Unit
V
V
Notes:
2. For APL products, Group A, Subgroups 1, 2 and 3 are tested per MIL-STD-833, Method 5005, unless otherwise noted.
3.
VIL and V/H are input conditions of output tests and are not themselves directly tested. VIL and V/H are absolute voltages with
respect to device ground and include all overshoots due to system andlor tester noise. Do not attemptto test these values
without suitable equipment.
4. 110 pin leakage is the worst case of liL and lozL (or hH and IOZH ).
5. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. This parameter is not 100%
tested, but is evaluated at initial characterization and at any time the design is modified where Isc may be affected.
2·224
PALCE20V8H·15 (Mil)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN= 2.0 V
Output Capacitance
VOUT = 2.0 V
I Vee = 5.0 V, TA = 25°C,
I f = 1 MHz
Typ
Unit
8
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
-15
Parameter
Symbol
Parameter Description
Min
(Note 5)
Max
Unit
15
ns
tPD
Input or Feedback to Combinatorial Output
3
ts
Setup Time from Input or Feedback to Clock
12
ns
tH
Hold Time
0
ns
Clock to Output
3
teo
tWL
Clock Width
tWH
fMAX
tpzx
Maximum
Frequency
(Note 3)
12
ns
LOW
10
HIGH
10
ns
41.6
MHz
Internal Feedback (teNT)
45.5
MHz
No Feedback
50.0
External Feedback
/1/(ts+teo)
11/(twH+twL)
ns
MHz
OE to Output Enable
3
15
ns
tpxz
OE to Output Disable
3
15
ns
tEA
Input to Output Enable Using Product Term Control (Note 4)
3
15
ns
tER
Input to Output Disable Using Product Term Control (Note 4)
3
15
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL Products, Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
5. Output delay minimums for tpo, teo, tpzx, tpxz, tEA, and tER are defined under best case conditions. Future process
improvements may alter these values therefore, minimum values are recommended for simulation purposes only.
PALCE20V8H-15 (Mil)
2-225
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Military (M) Devices (Note 1)
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Operating Case
Temperature (Te) ........... -55°C to +125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ....... +4.5 V to +5.5 V
DC Input Voltage . . . . . . . . . .. -0.5 V to Vee + 0.5 V
Note:
1. Military products are tested at Tc = +2SOC, +12SOC and
-5SOC, per MIL-STD-883.
DC Output 0 r I/O
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latehup Current
(Tc =-55°C to +125°C) ................ 100 rnA
Operating ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
(Note 2)
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-2.0 rnA
Vee = Min
VOl
Output LOW Voltage
IOL = 12 rnA
Min
VIN = VIH or VIL
Max
Unit
2.4
V
0.5
VIN = VIH or VIL
V
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
IIH
Input HIGH Leakage Current
VIN = 5.5 V, Vee = Max (Note 4)
ilL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 4)
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.5 V. Vee = Max
VIN = VIH or VIL (Note 4)
IOZl
Off-State Output Leakage
Vour = 0 V, Vee = Max
VIN = VIH or Vil (Note 4)
VIL
Current LOW
Isc
Output Short-Circuit Current
Vour = 0.5 V, Vee = 5.0 V. TA = 25°C
(Note 5)
Icc
Supply Current
(Dynamic)
Outputs Open (lOUT = 0 mA)
Vee = Max, f = 25 MHz
2.0
V
.......
-30
_.
. ..
0.8
V
10
~
-10
~
10
~A
-10
~A
-150
mA
130
mA
---
Notes:
2. For APL products, Group A, Subgroups 1, 2 and 3 are tested per MIL-STD-833, Method SODS, unless otherwise noted.
3. V/L and V/H are input conditions of output tests and are not themselves directly tested. V/L and V/H are absolute voltages with
respect to device ground and include all overshoots due to system andlor tester noise. Do not attempt to test these values
without suitable equipment.
4. liD pin leakage is the worst case of ItL and IOZL (or ItH and loZH ).
5. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 Vhas been chosen to avoid test problems caused by tester ground degradation. This parameter is not 100%
tested, but is evaluated at initial characterization and at any time the design is modified where Isc may be affected.
2-226
PALCE20V8H-20/25 (Mil)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
I Vee = 5.0 V, TA = 25°C,
1t = 1 MHz
Unit
8
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
Parameter
Symbol
-20
Parameter Description
Min
-25
Max
Min
Unit
25
ns
Input or Feedback to Combinatorial Output
ts
Setup Time trom Input or Feedback to Clock
15
20
ns
tH
Hold Time (Note 5)
0
0
ns
teo
Clock to Output
tWL
tWH
tMAX
20
Max
tPD
Clock Width
Maximum
Frequency
(Note 3)
20
15
ns
LOW
12
15
HIGH
12
15
ns
External Feedback 11 /(ts+teo)
33.3
25
MHz
Internal Feedback (teNT)
35.7
26.3
MHz
No Feedback
41.7
33.3
11/(tWH+tWl)
tpzx
OE to Output Enable
(Note 3)
tpxz
OE to Output Disable
(Note 3)
tEA
Input to Output Enable Using Product
Term Control (Note 3)
tER
Input to Output Disable Using Product
Term Control (Note 3)
20
ns
MHz
20
ns
18
20
ns
20
25
ns
25
ns
18
Notes:
2. See Switching Test Circuit for test conditions. For APL Products, Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3.
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
PALCE20V8H-20/25 (Mil)
2-227
~
AMD
SWITCHING WAVEFORMS
Input or
Feedback _ _ _- - I
Input or
Feedback
Combinatorial
Output
-~-VT
' - -_ _ _ _---1
,-V_T_ __
Clock
Registered
Output _ _ _ _ _ _ ___
164918-7
164918-8
Registered Output
Combinatorial Output
Input
Clock
tER
tEA
VT
Output
164918-9
164918-10
Clock Width
Input to Output Disable/Enable
tpxz
tpzx
VT
Output
164918-11
OE
to Output Disable/Enable
Notes:
1. VT= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns - 5 ns typical.
·2·228
PALCE20V8 Family
AMD~
KEY TO SWITCHING WAVEFORMS
WAVEFORM
\\\\\
/77//
'lIXXXX
}1) CK
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
KSOOO010-PAL
SWITCHING TEST CIRCUIT
Output o - - - - i l I t - - - - -.....
164918-12
Switching Test Circuit
Military
Commercial
Specification
Sl
CL
tPD, teo
Closed
50 pF
tpzx, tEA
Z~
50 pF
Z~
tpxz, tER
H
H: Open
L: Closed
~Z:
L~Z:
Open
R1
R1
Measured
Output Value
R2
1.5 V
2000.
5 pF
R2
3900.
H-5:
2000.
Closed
PALCE20V8 Family
1.5 V
3900.
7500.
H
~Z:
VOH -0.5 V
L
~ Z:
VOL + 0.5 V
2·229
~
AMD
TYPICAL Icc CHARACTERISTICS
Vee 5.0 V, TA 25°C
=
=
150
125
20VSH-5
100
20VSH-7
,Icc (mA)
75
20VSH-10
20VSH-15125
50
20VSQ-15125
25
O-+----~----~---+----~----+_--~----_r----~--~~--~
o
10
20
30
Frequency (MHz)
40
50
164918-13
Icc vs. Frequency
The selected "typical" pattern utilized 50% of the device resources. Half of the macroce/ls were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for Icc. From this midpoint, a designer may scale the Icc graphs up or down to
estimate the Icc requirements for a particular design.
2-230
PALCE20V8 Family
AMD~
ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using AMD's advanced electrically erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
Endurance Characteristics
Symbol
Parameter
Min
Unit
Max Storage
Temperature
Test Conditions
10
Years
20
Years
100
Cycles
tOR
Min Pattern Data Retention Time
Max Operating
Temperature
N
Min Reprogramming Cycles
Normal Programming
Conditions
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
ESD
ProgramNerify
Circuitry
Protection
Typical Input
Vee
Preload
Circuitry
Typical Output
PALCE20V8 Family
Feedback
Input
164918-14
2·231
~
AMD
ROBUSTNESS FEATURES
The PALCE20V8X-x/5 have some unique features that
make them extremely robust, especially when operating
in high-speed design environments. Pull-up resistors on
inputs and I/O pins cause unconnected pins to default to
a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking
caused by subsequent ringing. A special noise filter
makes the programming circuitry completely insensitive
to any positive overshoot that has a pulse width of less
than about 100 ns for the /5 versions.
Selected /4 devices are also being retrofitted with these
robustness features. See the chart below for device
listings.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION
AND SELECTED 14 VERSIONS·
Vee
Vcc
>50kn
I
I
I
I
I
I
I
ESD
Protection
and
Clamping
.
=
____ _
Programming
LF2n!.~!r
Typical Input
Vee
>50kn
Preload
Circuitry
=
Feedback
Input
Typical Output
164918-15
•
Device
Rev Letter
PALCE20V8H-10
K
PALCE20V8H-15
K,J
PALCE20V80-15
J
PALCE20V8H-25
J
PALCE20V80-25
J
2-232
Topside Marking:
AMO CMOS PLO's are marked on top of the package in the
following manner:
PALCEXXXX
Oatecode (3 numbers) Lot 10 (4 characters)- -(Rev Letter)
The Lot 10 and Rev Letter are separated by two spaces.
PALCE20va Family
AMD~
POWER-UP RESET
The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
Parameter
Symbol
and the wide range of ways Vec can rise to its steady
state, .two conditions are required to insure a-valid
power-up reset. These conditions are:
•
The Vcc rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Min
tPR
Power-Up Reset Time
ts
Input or Feedback Setup Time
twL
Clock Width LOW
Max
Unit
1000
ns
See Switching
Characteristics
Power
. . . - - - tPR ---~
Registered
Output
Clock
164918-16
Power-Up Reset Waveforms
PALCE20V8 Family
2-233
~
AMD
TYPICAL THERMAL CHARACTERISTICS
/4 Devices (PALCE20V8H-10/4)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ.
PLCC
Unit
Sjc
Thermal impedance, junction to case
19
19
°eIW
Sja
Thermal impedance, junction to ambient
73
55
°eIW
Sjma
Parameter Description
Thermal impedance, junction to
ambient with air flow
SKINNYDIP
200 Ifpm air
61
45
400 Ifpm air
53
41
600 Ifpm air
50
38
800 Ifpm air
47
36
°eIW
°eIW
°eIW
°eIW
PLCC
Unit
/5 Devices (PALCE20V8H-7/5)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ.
SKINNYDIP
Parameter Description
Sjc
Thermal impedance, junction to case
18
16
°eIW
Sja
Thermal impedance, junction to ambient
69
51
°eIW
200 Ifpm air
60
42
400 Ifpm air
54
37
600 Ifpm air
50
36
800 Ifpm air
X
X
°eIW
°eIW
°eIW
°eIW
Sjma
Thermal impedance, junction to
ambient with air flow
Plastic S/c Considerations
The data listed for plastic Sjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-floW paths in plastic-encapsulated devices are complex, making the Sjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, Sjc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment.-- -----------------------------
2·234
PALCE20va Family
AMD~
2·235
_COM'L:-20
~
INO: -20
Advanced
Micro
Devices
PALCE20RA10H·20
24-Pin Asynchronous EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
Low power at 90 mA Icc
•
•
As fast as 20 ns maximum propagation delay
and 37 MHz fMAx (external)
Programmable replacement for high-speed
CMOS or TTL logic -
•
TTL-level register preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-pln SKINNVOIP and 28-pln PLCC packages
save space
•
Individually programmable asynchronous
clock, preset, reset, and enable
•
•
Registered or combinatorial outputs
•
•
Programmable polarity
GENERAL DESCRIPTION
The PALCE20RA10 is an advanced PAL device built
with low-power, high-speed, electrically-erasable
CMOS technology. The PALCE20RA10 offers asynchronous clocking for each of the ten flip-flops in the device. The ten macrocells feature programmable clock,
preset, reset, and enable, and all can operate
asynchronously to other macrocells in the same device.
The PALCE20RA10 also has flip-flop bypass, allowing
any combination of registered and combinatorial
outputs.
The PALCE20RA10 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently.
Multple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices. The
BLOCK DIAGRAM
1/00
2-236
equations are programmed into the device through
floating-gate cells in the AND logic array that can be
erased electrically.
AMD's FusionPLD program allows PALCE20RA10 designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools fo r each device:- The -Fu sion PLD -program -also--greatly reduces design time since a deSigner can use a
tool that is already installed and familiar. Please refer to
the PLD Software reference guide for certified development systems and the Programmer reference guide for
approved programmers.
Dedicated
Inputs
1/03
1/05
1/06
1/07
I/0a
Publication# 15434 Rev.D
Issue Date: June 1993
1I0g 154340-1
AmendmentlO
AMD
;r1
CONNECTION DIAGRAMS
Top View
PLCC
SKINNYDIP/FLATPACK
0
PL
~
Vee
10
1/0g
h
-=
.,.
~ g
I/Oa
12
25
1/07
12
1107
13
24
1/06
13
1/06
14
23
1/05
14
1/05
22
NC
15
1/04
16
1/03
17
1/02
la
1/01
19
GND
NC
15
21
1104
16
20
1103
17
19
1/02
1/00
..!!' ..!2'
DE
z IW
0
z o
Q
(!)
15434D-2
0
g
g15434D-3
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
GND
I
1/0
NC
OE
PL
Vee
Ground
Input
Input/Output
No Connect
Output Enable
Preload
Supply Voltage
PALCE20RA1OH-20
2-237
~AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL CE 20
FAMILY TYPE
PAL = Programmable Array Logic
T
TECHNOLOGY
CE = CMOS Electrically Erasable
RA 10 H -20 P C
L
NUMBER OF
ARRAY INPUTS
OPERATING CONDITIONS
I = Industrial (-40°C to +85°C)
C = Commercial (OOC to +75°C)
PACKAGE TYPE
P = 24-Pin 300-mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
OUTPUT TYPE
RA = Registered Asynchronous
NUMBER OF OUTPUTS
POWER
H = Half Power (Icc = 90 mA)
SPEED
-20 = 20 ns tPD
Valid Combinations
PALCE20RA10H-20
2-238
I
Valid Combinations
PC, JC, PI, JI
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE20F:lA10H-20 (Com'l, INO)
Commercial and Industrial Products
Output
15434D-5
Figure 1. PALCE20RA10 Macrocell
FUNCTIONAL DESCRIPTION
The PALCE20RA10 has ten dedicated input lines and
ten programmable I/O macrocells. The Registered
Asynchronous (RA) macrocell is shown in Figure 1. Pin
1 serves as global register preload and pin 13 serves as
global output enable. Programmable output polarity is
available to provide user-programmable output polarity
for each individual macrocell.
Programmable Clock
The clock input to each flip-flop comes from the programmable array, allowing any flip-flop to be clocked
independently if desired.
The programmable functions in the PALCE20RA10 are
automatically configured from the user's design specification, which can be in a number of formats. The design
specificaiion is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
Programmable Preset and Reset
Registered/Active Low
CombinatorlaUActive Low
In each macrocell, two product lines are dedicated to
asynchronous preset and asynchronous reset. If the
preset product line is HIGH, the Q output of the register
becomes a logic 1 and the output pin will be a logic O.lf
the reset product line is HIGH, the Q output of the register becomes a logic 0 and the output pin will be logic 1.
The operation of the programmable preset and reset
overrides the clock.
Combinatorial/Registered Outputs
Registered/Active High
If both the preset and reset product lines are HIGH, the
flip-flop is bypassed and the output becomes combinatorial. Otherwise, the output is from the register. Each
output can be configured to be combinatorial or
registered.
PALCE20RA 1OH-20
Combinatorial/Active High
15434D-6
Figure 2. Macrocell Configurations
2-239
~
AMD
Three-State Outputs
Register Preload
The devices provide a product term dedicated to local
output control. There is also a global output control pin.
The output is enabled if both the global output control
pin is LOW and the local output control product term is
HIGH. If the global output control pin is HIGH, all outputs
will be disabled. If the local output control product term is
LOW, then that output will be disabled.
The register on the PALCE20RA10 can be preloaded .
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transistions from illegal states
can be verified by loading illegal states and observing
proper recovery. Register preload is controlled by a
TTL-level signal, making it a convenient board-level initialization function.
Security Bit
A security bit is also provided to prevent unauthorized
copying of PAL device patterns. Once the bit is programmed, the circuitry enabling verification is permanently disabled, and the array will read as if every bit is
programmed. With verification not operating, it is impossible to simply copy the PAL device pattern on a PAL device programmer. The security bit can only be erased in
conjunction with the entire pattern.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Registered outputs of the
PALCE20RA10 will be HIGH due to the output inverter.
The state of combinatorial outputs will be a function of
the logic.
Programmable Polarity
Quality and Testability
The outputs can be programmed either active-LOW or
active-HIGH. This is represented by the Exclusive-OR
gate shown in the PALCE20RA 10 logic diagram. When
the output polarity bit is programmed, the lower input to
the Exclusive-OR gate is HIGH, so the output is activeHIGH. Similarly when the output polarity bit is
unprogrammed, the output is active-LOW. The programmable output polarity feature allows the user a
higher degree of flexibility when writing equations.
The PALCE20RA10 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and OC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Programming and Erasing
The PALCE20RA10 can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erase operation is required.
2·240
Technology
The high-speed PALCE20RA10H-20 is fabricated with
AMO's advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE
cells. Inputs and outputs are designed to be-compatible--with TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PALCE20RA 1OH·20
AMD~
LOGIC DIAGRAM
DIP (PLCC JEDEC) Pinouts
1
(2)
.......
···
··
a
1 23.5. 1
a
1101112131"'5 '.'71"11 201122232425262128213G31 32333435 3&313831
~D-
<
r-
7
~
...."
..
"
,.""
.
21
23
......
,.• 7
211
311
31
5
(6)
34
35
3J
...
...
...
.
....
<7
•.
50
52
50
..
56
8
(10)
"
57
58
..
...."
......
....
511
9
(11)
17
"
...
(21)
....
(20)
....
(19)
~D~ ~
73
7<
75
71
77
(17)
'"
11
a
1 2 3
4 5 '7
• • 1a 11 12131415 11" 18,. 20 21 2223 242526 27 28 2130 31 3233 '" 35 313738 3D
---I
4-@]
(16)
[12l-,
(i4i
(23)
~,
7.
11
(13)
1
(18)
"
0
(12)
1
:~D
35
....
7
(9)
'"
~
.
33
6
(7)
I'lAII P
~D-
"
17
4
(5)
~
~L~
~ ~I
~D
~~
"'I
~D
~~
~~
"'I
~D~~
"I
~D~~
"1
~D- ~ ~
"'I
~D
~~
1D
3
(4)
_
....
154340-7
PALCE20RA 1OH-20
2-241
~AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
'
Respect to Ground ............. -0.5 V to +7.0 V
Ambient Temperature (TA)
Operating in FreeAir .............. O°C to +75°C
Supply Voltage (Vee)
with Respect to Ground ........ +4.75 V to +5.25 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
(Except Pin 5)
Industrial (I) Devices
DC Input Voltage (Pin 5) ........ -0.6 V to + 11.0 V
Supply Voltage (Vee) with
Respect to Ground .............. +4.5 V to +5.5 V
DC Output or I/O Pin
Voltage .................. -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Operating Case ................ -40°C to +85°C
Operating ranges define those limits between which the functionality of the device is guaranteed.
Latchup Current
(Te = -40°C to +85°C) . . . . . . . . . . . . . . . . .. 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Min
Output HIGH Voltage
IOH =-3.2 mA
VIN = VIH or Vil
Vee = Min
2.4
VOL
Output LOW Voltage
IOl = 8 mAVIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Voltage for ail Inputs (Note 1)
Guaranteed Input Logical HIGH
Vil
Input LOW Voltage
Voltage for ail Inputs (Note 1)
Guaranteed Input Logical LOW
IIH
Input HIGH Leakage Current
VIN
III
Input LOW Leakage Current
VIN = 0 V, Vee
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Ise
Output Short-Circuit Current
Icc
Supply Current
Vec
= Max
2.0
-30
I COM'L
liND
Unit
V
0.4
= 5.5 V, Vee = Max (Note 2)
= Max (Note 2)
VOUT = 5.5 V, Vce = Max
VIN = Vil or VIH (Note 2)
VOUT = 0 V, Vee = Max
VIN = Vil or VIH (Note 2)
VOUT = 0.5 V, Vee = Max (Note 3)
VIN = 0 V, Outputs Open·
(lOUT = 0 mA)
Max
V
V
0.8
V
10
~
-100
~
10
~
-100
~
-150
mA
90
130
mA
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IJL and IOZL (or IJH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
'
2-242
PALCE20RA10H-20 (Com'I, IND)
AMO
;r1
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
\ Inputs
IOE
COUT
Output Capacitance
VOUT = 2.0 V
Typ
Vee = 5.0 V
Unit
5
TA = +25°C
9
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
-20
Parameter
Symbol
Min
(Note 3)
Parameter Description
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP to Clock
7
Hold Time
4
tH
Max
Unit
20
ns
ns
ns
teo
Clock to Output or Feedback
20
ns
tAp
Asynchronous Preset to Registered Output
20
ns
12
ns
tApw
AsynchronoLis Preset Width
tAPR
Asynchronous Preset Recovery Time (Note 4)
tAR
Asynchronous Reset to Registered Output
12
tARW
Asynchronous Reset Width
tARR
Asynchronous Reset Recovery Time (Note,4)
twL
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 5)
ns
20
12
ns
ns
12
ns
LOW
12
HIGH
12
ns
ns
External Feedback
11/(ts + teo)
37
MHz
No Feedback
\1/(tWH + tWL)
41.6
MHz
tpzx
OE to Output Enable
15
ns
tpxz
OE to Output Disable
15
ns
tEA
Input to Output Enable Using Product Term Control
20
ns
tER
Input to Output Disable Using Product Term Control
20
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums are measured under best-case conditions.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where the frequency may be affected.
PALCE20RA10H-20 (Com'l, INO)
2-243
~AMD
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
--~-vr154340-8
Input or
Feedback _ _ _--'
Vr
Clock
Registered
Output _ _ _ _ _ _ _ __
154340-9
Registered Output
Combinatorial Output
Input
Asserting --~I_----Asynchronous
Preset - - - - ' '-----.---'1 ' - - - -
. . I,..---
Registered
-4_---
Output ----~~~~....
Input
Asserting
Asynchronous
Reset
Registered
Output _ _ _"--11;....£."""",,-...1
Clock
tARR
154340-10
Vr
Clock
154340-11
Asynchronous Preset
Asynchronous Reset
Clock
154340-12
Clock Width
OE
Input or
Feedback
tER
Vr
Output
tpxz
tEA
Vr
Output
154340-14
154340-13
Input to Output Disable/Enable
Notes:
1. VT=1.5V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns - 5 ns typical.
2·244
tpzx
PALCE20RA1OH·20
OE
to Output Disable/Enable
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/////
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
xxxxxx
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Output o--+----....-~) Test Point
154340-15
Commercial
Specification
Sl
CL
tPD, teo
Closed
tpzx, tEA
Z~
Z~
tpxz, tER
H: Open
L: Closed
H ~Z: Open
R1
R2
Measured
Output Value
1.5 V
50 pF
1.5V
560n
1.1 kn
H ~Z: VOH -0.5 V
5 pF
L ~ Z: VOL + 0.5 V
L ~Z: Closed
PALCE20RA 1OH·20
2·245
~
AMD
ENDURANCE CHARACTERISTICS
The PALCE20RA10 is manufactured using AMD's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
tOR
N
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
Parameter
Test Conditions
Min Pattern Data Retention Time
Min Reprogramming Cycles
Min
Unit
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
Normal Programming Conditions
100
Cycles
Robustness
The PALCE20RA1OH-20 has been designed with some
unique features that make it extremely robust, even
when operating in high-speed design environments.
Pull-up resistors on the inputs and I/0s cause unconnected pins to default to the HIGH state. Input-clamping
circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A
special noise filter makes the programming circuitry
completely insensitive to any positive overshoot that
has a pulse width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
Vee
>50kn
I
I
I
I
ESD
Protection
and
Clamping
I
II Programmlng
.
-=
L !2n,! £n.!t ____ _
Typical Input
Vee
Vee
>50kn
Provides ESD
Protection and
Clamping
Preload
Circuitry
Typical Output
2·246
PALCE20RA1 OH·20
Feedback
Input
15434D-17
AMD~
POWER-UP RESET
The PALCE20RA1 0 has been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization.
A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
Parameter
Symbol
tPR
and the wide range of ways Vec can rise to its steady
state, two conditions are required to ensure a valid
power-up reset. These conditions are:
•
The Vee rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
Max
Unit
Power-Up Reset Time
1000
ns
Input or Feedback Setup Time
ts
See Switching Characteristics
Clock Width LOW
tWL
Vee
Power
Registered
Output
Clock
154340-18
Power-Up Reset Waveform
PALCE20RA1OH-20
2-247
~
AMD
2-248
-
~
COM'L
Advanced
Micro
Devices
AmPAL22P10B/AL/A
24-Pin Combinatorial TTL Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
As fast as 15 ns maximum propagation delay
•
Universal combinatorial architecture
•
Programmable output polarity
•
Programmable replacement for high-speed
TIL logic
•
Extensive third-party software and
programmer support through FusionPLD
partners
•
24-pln SKINNYDIP and 28-pln PLCC packages
save space
GENERAL DESCRIPTION
The AmPAL22P10 utilizes Advanced Micro Devices'
advanced oxide-isolated bipolar process and fuse-link
technology. The devices provide user-programmable
logic for replacing conventional SSIIMSI gates and f1ipflops at a reduced chip count.
The AmPAL22P1 0 allows the systems engineer to implement the design on-chip, by opening fuse links to
configure AND and OR gates within the device, according to the desired logic function. Complex intercorinec- ,
tions between gates, which previously required
time-consuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified during prototyping or production.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
BLOCK DIAGRAM
I/O
110
outputs. In addition, the PAL device provides the following options:
-
Variable inpuVoutput pin ratio
-
Programmable three-state outputs
Product terms with all fuses opened assume the logical
HIGH state; product terms connected to both true and
complement of any single input assume the logical LOW
state. Unused input pins should be tied to Vcc or GND.
The entire PAL device family is supported by the
FusionPLD partners. The PAL family is programmed on
conventional PAL device programmers with appropriate
personality and socket adapter modules. See the Programmer Reference Guide for approved programmers.
Once the PAL device is programmed and verified an additional fuse may be opened to prevent pattern readout.
This feature secures proprietary circuits.
AmPAL22P10
Inputs
110
110
110
110
110
110
110
110
12984E-1
Publication# 12984 Rev. E
Issue Date: January 1992
AmendmentlO
2-249
~
AMD
PRODUCT SELECTOR GUIDE
tPD
ns (Max)
Family
Icc
mA (Max)
IOL
mA(Mln)
Very High Speed
(liB") Versions
15
210
24
High Speed
("A") Versions
25
210
24
High Speed,
Half Power
("AL") Versions
25
105
24
CONNECTION DIAGRAMS
Top View
PLCC
SKINNYDIP
()
0
z ~ ~ ~
Vee
110
110
110
110
25
110
24
110
23
110
22
NC
110
21
110
110
20
110
110
NC
110
110
110
110
0
12984E-3
12984E-2
Note:
Pin 1 is marked for orientation
PIN DESIGNATIONS
2·250
~ ~
(!)
GND
GND
I
I/O
NC
Vee
()
z z
Ground
Input
InpuVOutput
No Connect
Supply Voltage
AmPAL22P10B/AUA
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
AmPAL 22
P 10 A L P C
____T---' -- -- -- -_
-
r
FAMILY TYPE
Am PAL = Programmable Array Logic
L
OPTIONAL PROCESSING
Blank = Standard Processing
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE - - - - - - - -......
P = Programmable Polarity
OPERATING CONDITIONS
C = Commercial (OOC to +75°C)
NUMBER OF OUTPUTS - - - - - - - - - '
SPEED
B = 15 ns tPD
A = 25 ns tPD
POWER _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
D = 24-Pin 300 mil Ceramic
SKINNYDIP (CD3024)
~
L = Low Power (105 rnA Icc)
Blank = Full Power (210 rnA Icc)
Valid Combinations
AmPAL22P10
Valid Combinations lists configurations planned
to be supported in volume forthis device. Consult
the local AMD sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
Note: Marked with AMD logo.
AmPAL22P10B/ALlA (Com'l)
2-251
~
AMD
FUNCTIONAL DESCRIPTION
All parts are produced with a fuse link at each input to the
AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit.
Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any
customized pattern. Information on approved programmers can be found in the Programmer Reference Guide.
Extra test words are pre-programmed during manufacturing to ensure extremely high field programming
yields, and provide extra test paths to achieve excellent
parametric correlation.
Variable Input/Output Pin Ratio
The AmPAL22P10 has twelve dedicated input lines,
and all ten combinatorial outputs are 1/0 pins. Buffers for
device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GND.
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional 1/0 pin, and may be cO.nfigured as a dedicated input if the buffer is always dISabled.
Programmable Polarity
The polarity of each output can be active-high or activelow, either to match output signal needs or to reduce
product terms. Programmable polarity allows Boolean
2·252
expressions to be written in their most compact form
(true or inverted). and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts.
Selection is through a programmable fuse which controls an exclusive-OR gate at the output of the AND/OR
logiC. The output is active high if the fuse is 1 (programmed) and active low if the fuse is 0 (intact).
Security Fuse
After programming and verification, an AmPAL22P10
design can be secured by programming the security
fuse. Once programmed, this fuse defeats readback of
the internal programmed pattern by a device programmer, securing proprietary designs from competitor~.
When the security fuse is programmed, the array Will
read as if every fuse is programmed.
Quality and Testability
The AmPAL22P10 offers a very high level of built-in
quality. Extra programmable fuses provide a means of
verifying performance of all AC and DC parameters. In
addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Technology
The AmPAL22P10 is fabricated with AMD's advanced
oxide-isolated bipolar process. This process reduces
parasitic capacitances and minimum geometries to provide higher performance. The array connections are
formed with proven PtSi fuses for reliable operation.
AmPAL22P10B/AUA
AMD~
LOGIC DIAGRAM
AmPAL22P10
Inputs (0-43)
• 1 II
..
i.
J
•
".,1
12131'415
"'71'"
fl"""
Mann
"n3D!1
3Ill!Il436
··,
····
H!7:tI31
40"410
7
0--tf=
,.
17
,.
-, ~J)l
.,
...
....
....
~
II
~.
17
II
7
...."..
:!
..
....
..
..
..
...,
"
i
'=:J
..........l
47
1
:Bn
~-/ ... r
.
21
20
19
j
~D~[
51
7
22
~
17
6
.. I
1
;~D~[
"
....""
5
I
~D~l
,.
,.
4
2
1
,.
f3l.
.........
rill
-~D1...
18
~
54
II
i7
"\ :BTJ-l
.,,-/ ... r
II
II
~
17
8
"
1
Ii
II
17
II
II
10
71
9
......,
).:»))"[
16
~
n
,."
74
:B1)1
~
..
...,
7t
10
U
15
r
~
::
-::2
Ii
II
.,
::
11
r-/'"
~
>
1
~D"[
14
13
12984E-4
AmPAL22P10B/AUA
2-253
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Ambient Temperature (TA)
Operating in Free Air ........... , O°C to +75°C
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . . . . . .. -0.5 V to +5.5 V
DC Input Current ............ "
-30 rnA to +5 rnA
Operating ranges define those limits between which the func- '
tionality of the device is guaranteed.
DC I/O Pin Voltage ............ -0.5 V to Vee Max
Static Discharge Voltage
................ 2001 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = -3.2 mA
VIN = VIH or VIL
Vcc = Min
Min
VOL
Output LOW Voltage
IOL = 24 mA
VIN = VIH or VIL
Vcc = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
Max
2.0
Unit
V
2.4
0.5
V
5.5
V
0.8
V
VI
Input Clamp Voltage
IIN= -18 mA, Vee = Min
-1.2
V
IIH
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 2)
25
~
IlL
Input LOW Current
VIN = 0.4 V, Vee = Max (Note 2)
-100
~
Ii
Maximum Input Current
VIN = 5.5 V, Vee = Max
1
mA
loZH
Off-State Output Leakage
Current HIGH
VOUT= 2.7 V, Vee = Max
VIN = VIH or VIL (Note 2)
100
~
loZL
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vcc = Max
VIN = VIH or VIL (Note 2)
-100
~
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vcc = Max (Note 3)
-90
mA
Icc
Supply Current
VIN = 0 V, Outputs Open
(loUT = 0 rnA)
Vee = Max
B,A
210
rnA
AL
105
rnA
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IiL and IOZL (or IiH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-254
AmPAL22P10B/ALlA (Com'l)
AMD
11
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
Parameter Description
Input Capacitance
I
I
COUT
Test Conditions
Pins 1 13
Others
Output Capacitance
VIN = 2.0 V
Typ
Vee = 5.0 V
TA
VOUT = 2.0 V
Unit
11
6
= +25°C
pF
9
f = 1 MHz
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
A,AL
B
Parameter Description
Min
Max
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
15
25
ns
tEA
Input to Output Enable Using Product Term Control
18
25
ns
tER
Input to Output Disable Using Product Term Control
15
25
ns
Note:
2. See Switching Test Circuit for test conditions.
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
;g
Input or
Feedback
VT
-xxmtP~
_ _ _---I
tER
-VT
tEA
Combinatorial
>-+-+++-----+~f-t- VT
Output ----.....&....f....I.-1
12984E-5
Combinatorial Output
12984E-6
Input to Output Disable/Enable
Notes:
1. VT= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times.2 ns-5 ns typical.
AmPAL22P10B/ALlA (Com'l)
2-255
~
AMD
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
\\\\\
May
Change
from H to L
Will be
1//71
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing.
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
xxxxxx
Steady
Changing
from H to L
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Output O--+----......-~l Test Point
12984E-7
Specification
S1
tPD
Closed
tEA
Z~ H:Open
CL
R1
2-256
H ~Z: Open
L ~Z: Closed
Measured
Output Value
1.5 V
50 pF
Z ~ L: Closed
tER
R2
1.5 V
200n
5 pF
AmPAL22P1 OBI AU A
390n
H ~ Z: VOH - 0.5 V
L ~ Z: VOL + 0.5 V
AMD~
INPUT/OUTPUT EQUIVALENT SCHEMATICS
-----------------.---oVCC
Input
ProgramNerify
Circuitry
12984E-8
Typical Input
---------------~I--------o VCC
40QNOM
:>1-......---+---------+__0
Input.
I/O
Pins
Output
ProgramNerify/
Test Circuitry
12984E-9
Typical Output
AmPAL22P10B/AUA
2·257
_
COM'L:-7/10/15
~
MIL: -12/20
Advanced
Micro
Devices
PAL22V10 Family, AmPAL22V10/A
24-Pin TTL Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
•
•
•
As fast as 7.5 ns propagation delay and
91 MHz fMAx (external)
10 Macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to
16 product terms per output for complex
functions
•
•
•
•
Global asynchronous reset and synchronous
preset for Initialization
Power-up reset for initialization and register
preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-Pin SKINNVDIP, 24-pin Flatpack and
28-pln PLCC and LCC packages save space
GENERAL DESCRIPTION
The PAL22V10 provides user-programmable logic for
replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
. The PAL22V1 0 device implements the familiar Boolean
logic transferfunction, the sum of products. The PAL device is a programmable AND array driving a fixed OR
array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two fuses controlling two multiplexers in
each macrocell.
AMD's FusionPLD program allows PAL22V10 designs
to be implemented using a wide variety of popular industry-standard design tools. By working closely with the
FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please referto
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
BLOCK DIAGRAM
11 - 11,
elK/lo
Programmable
AND Array
(44 x 132)
2-258
Publication# 16559 Rev. B
Issue Date: June 1993
AmendmentlO
AMD~
CONNECTION DIAGRAMS
Top View
PLCC/LCC
SKINNYDIP/FLATPACK
CLKllo
11
IIQg
12
1I0a
13
1107
1I0s
1105
1104
14
15
"i
Vee
..!'I :
()
Z
o
CJ)
°
CIO
>00
.::.. ::::.
1/07
13
IIOs
14
15
23
1/°5
NC
22
NC
1/03
Is
19
1/02
1/01
110
17
la
1/00
GND
....J
()
1/°4
1/03
19
1/°2
12 13 14 15 16 17 18
111
..2'
165598-2
.:t- oz
CD
()
Z
.£0
.::..
g165598-3
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
ClK
GND
Clock
Ground
I/O
Input
Input/Output
NC
No Connect
Vee
Supply Voltage
PAL22V10 Family
2-259
~
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
T
FAMILY TYPE
22
V 10 -7 P C
PAL or AmPAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUTTYPE--------------------~
V
= Versatile
NUMBER OF OUTPUTS
----------~
SPEED ------------------------------~
~.
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic SKINNYDIP
(PD3024)
J = 28-Pin Plastic Leaded Chip Carrier
(PL 028)
-7 = 7.5 ns tPD
-10= 10 ns tPD
-15= 15 ns tPD
A= 25 ns tPD
Valid Combinations
PAL22V10-7
PAL22V10-10
PAL22V10-15
PC,JC
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
AmPAL22V10A
2-260
PAL22V10-7/10/15, AmPAL22V10A (Com'l)
~MD~
ORDERING INFORMATION
APL Products
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination)
is formed by a combination of:
PAL
22
V 10
-12 IB L A
J
FAMILY TYPE
PAL or Am PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
~
OUTPUT TYPE - - - - - - - - - - - - - '
V = Versatile
LEAD FINISH
A = Hot Solder Dip
PACKAGE TYPE
L = 24-Pin 300 mil Ceramic
SKINNYDIP (CD3024)
K = 24-Pin Ceramic Flatpack
(CFL024)
3 = 28-Pin Ceramic Leadless
Chip Carrier (CL 028)
DEVICE CLASS
IB = MIL-STD-883C Class B
NUMBER OF OUTPUTS
SPEED --------------------~
-12 = 12 ns tPD
-20 = 20 ns tPD
A = 30 ns tPD
Blank = 40 ns tPD
Valid Combinations
PAL22V10-12
PAL22V10-20
AmPAL22V10A
IBLA, IBKA, IB3A
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
AmPAL22V10
Group A Tests
Group A tests consist of Subgroups
1, 2, 3, 7, 8, 9, 10, 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Method 1015, Conditions A through E.
Test conditions are selected at AMD's option.
PAL22V10-12/20, AmPAL22V10/A (Mil)
2-261
~
AMD
FUNCTIONAL DESCRIPTION
The PAL22V10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to
the desired logic function. Complex interconnections
between gates, which previously required timeconsuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified during prototyping or production.
Product terms with all fuses opened assume the logical
HIGH state; product terms connected to both true and
complement of any single input assume the logical LOW
state.
The PAL22V10 has 12 inputs and 10 I/O macrocells.
The macrocell (Figure 1) allows one of four potential output configurations; registered output or combinatorial
I/O, active high or active low (see Figure 2). The configuration choice is made according to the user's design
specification and corresponding programming of the
configuration bits So - S1. Multiplexer controls initially
are connected to ground (0) through a programmable
fuse, selecting the "0" path through the multiplexer. Programming the fuse disconnects the control line from
GND and it is driven to a high level, selecting the "1"
path.
The device is produced with a fuse link at each input to
the AN D gate array, and connections may be selectively
removed by applying appropriate voltages to the circuit.
Variable Input/Output Pin Ratio
The PAL22V10 has twelve dedicated input lines, and
each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GND.
I/On
-=-
51
50
0
0
1
1
0
1
0
1
Output Configuration
Registered/Active Low
Re istered/Active Hi h
Combinatorial/Active Low
Combinatorial/Active Hi h
o =Unprogrammed fuse
1 = Programmed fuse
166598-4
Figure 1. Output Logic Macrocell Diagram
2·262
PAL22V10 Family
AMD~
Registered Output Configuration
Combinatorial I/O Configuration
a
Each macrocell of the PAL22V1 includes a D-type flipflop for data storage and synchronization. The flip-flop
is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = a), the array
feedback is from of the flip-flop.
a
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(S1 =1). In the combinatorial configuration the feedback
is from the pin.
Combinatorial/Active Low
Registered/Active Low
Combinatorial/Active High
Registered/Active High
165598-5
Figure 2. Macrocell Configuration Options
Programmable Three-State Outputs
Preset/Reset
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional 110 pin, and may be configured as a dedicated input if the buffer is always disabled.
For initialization, the PAL22V10 has Preset and Reset
product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP)
product term is asserted high, the output registers will be
loaded with a HIGH on the next LOW-to-HIGH clock
transition. When the Asynchronous Reset (AR) product
term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock.
Programmable Output Polarity
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is controlled by programmable bit So in the
output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the
design speCification and pin definitions.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL22V10 will depend on the programmed output polarity. The Vee rise
must be monotonic and the reset delay time is 1000 ns
maximum.
.. PAL22V10 Family
2-263
~
AMO'
Register Preload
Quality and Testability
The register on the PAL22V10 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
The PAL22V1 ooffers a very high level of built-in quality.
Extra programmable fuses, test words and test columns
provide a means of verifying performance of all AC and
DC parameters. In addition, this verifies complete
programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry.
Security Fuse
After programming and verification, a PAL22V1 0 design
can be secured by programming the security fuse. Once
programmed, this fuse defeats readback of the internal
programmed pattern by a device programmer, securing
proprietary designs from competitors. When the security fuse is programmed, the array will read as if every
fuse is programmed, and preload will be disabled.
Programming
Technology
The PAL22V10A is fabricated with AMD's Junctionisolated process. The array connections are formed with
highly reliable PtSifuse.
The PAL22V10-15, -10 and -7 are fabricated with
AMD's advanced oxide-isolated bipolar process. This
process reduces parasitic capacitances and minimum
geometries to provide higher performance. The array
connections are formed with PtSi fuses on the -15, and
TiW fuses on the -7 and -10 for reliable operation.
The PAL22V10 can be programmed on standard logiC
programmers. Approved programmers are listed in the
Programmer Reference Guide.
2·264
PAL22V10 Family
AMD~
LOGIC DIAGRAM
SKINNYDIP (PLCC/LCC) Pinouts
IE
(28) Vee
1111111
33
34
48
49
1111111111111111111111111
I I LLIIII II II I II I II II II II II II I I II I III II IILlI I
1I
III II II
IIII I II I II III IIII
III l_li
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16559B-6
PAL22V10 Family
2-265
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air ............ DoC to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -1.2 V to Vee + 0.5 V
DC Output or I/O Pin Voltage . -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliabifity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 mA
VIN = VIH or Vil
Vee = Min
VOL
Output lOW Voltage
IOl = 16 rnA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
VI
Input Clamp Voltage
liN = -18 mA, Vee = Min
IIH
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 2)
III
Input LOW Current
VIN = 0.4 V, Vee = Max
Min
(Note 2)
Ii
Max
2.4
V
0.5
2.0
V
V
0.8
-1.2
25
I Input
I ClK
Unit
-100
-150
V
V
~
J.lA
Maximum Input Current
VIN = 5.5 V, Vee = Max
1
mA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, Vee = Max
VIN = VIH or VIL (Note 2)
100
~
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vee = Max
VIN = VIH or Vil (Note 2)
-100
~
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
-130
mA
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mA)
Vee = Max
220
mA
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system andlor tester noise are included.
2. 110 pin leakage is the worst case of liL and lozL (or I/H and IOZH ).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT
has been chosen to avoid test problems caused by tester ground degradation.
2-266
PAL22V10-7 (Com'l)
=0.5 V
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN =2.0 V
CoUT
Output Capacitance
VOUT= 2.0 V
Typ
I
I
Vee =5.0 V
TA = 25°C
f = 1 MHz
Unit
6
5
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
(Note 3)
Max
7.5
tpo
Input or Feedback to Combinatorial Output
1
ts
Setup Time from Input, Feedback or SP to Clock
5
Hold Time
0
Clock to Output
1
tH
teo
tSKEWR
tAR
Skew Between Registered Outputs (Note 5)
Asynchronous Reset to Registered Output
Unit
ns
ns
ns
6
ns
1
ns
12
8
ns
tARW
Asynchronous Reset Width
tARR
Asynchronous Reset Recovery Time
8
ns
tSPR
Synchronous Preset Recovery Time
5
ns
LOW
4
ns
HIGH
4
ns
91
MHz
twL
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 4)
External Feedback
I
1/(ts + teo)
Internal Feedback (feNT)
No Feedback
I
1/(tWH + tWL)
ns
100
MHz
125
MHz
tEA
Input to Output Enable Using Product Term Control
8
ns
tER
Input to Output Disable Using Product Term Control
7.5
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums are measured under best-case conditions.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
5. Skew is measured with all outputs switching in the same direction.
PAL22V10-7 (Com'l)
2-267
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied ................. -55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air ............ DoC to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage ......... "
-1.2 V to Vee + 0.5 V
DC Output or I/O
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 rnA
VIN = VIH or Vil
Vee = Min
VOL
Output lOW Voltage
IOl=16mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input lOW Voltage
Guaranteed Input logical lOW
Voltage for all Inputs (Note 1)
Min
VI
Input Clamp Voltage
liN = -18 rnA, Vee = Min
IIH
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 2)
III
Input lOW Current
II
Max
2.4
V
0.5
2.0
V
25
~
VIN = 0.4 V, Vee = Max
I Input
-100
IClK
-150
VIN = 5.5 V, Vee = Max
IOZH
IOZl
Off-State Output leakage
Current LOW
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 rnA)
Vee = Max
V
-1.2
(Note 2)
Maximum Input Current
V
V
0.8
Off-State Output leakage
Current HIGH
Unit
JlA
1
rnA
VOUT = 2.7 V, Vee = Max
VIN = VIH or Vil (Note 2)
100
~
VOUT = 0.4 V, Vee = Max
VIN = VIH or Vil (Note 2)
-100
~
-30
-130
rnA
180
rnA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system andlor tester noise are included.
2. 110 pin leakage is the worst case of IJL and lozL (or hH and IOZH ).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-268
PAL22V10-10 (Com'I)'
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN =2.0 V
Cour
Output Capacitance
VOUT=2.0 V
Note:
Typ
I
I
Vcc =5.0 V
TA = 25°C
f = 1 MHz
Unit
6
5
pF
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
(Note 3)
Max
10
Unit
tPD
Input or Feedback to Combinatorial Output
1
ts
Setup Time from Input, Feedback or SP to Clock
7
ns
tH
Hold Time
0
ns
tco
Clock to Output
1
tAR
Asynchronous Reset to Registered Output
7
15
ns
ns
ns
tARw
Asynchronous Reset Width
10
ns
tARR
Asynchronous Reset Recovery Time
8
ns
tSPR
Synchronous Preset Recovery Time
tWL
8
ns
LOW
5
ns
HIGH
5
ns
71
MHz
80
MHz
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 4)
External Feedback
I
1/(ts + tco)
Internal Feedback (fCNT)
No Feedback
I
1/(tWH + tWL)
100
MHz
tEA
Input to Output Enable Using Product Term Control
11
ns
tER
Input to Output Disable Using Product Term Control
9
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums are measured under best-case conditions.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PAL22V10-10 (Com'I)
2-269
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied ................. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air .......... "
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 0.5 V
DC Input Current ............. -30 rnA to +5 rnA
O°C to +75°C
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 1/0
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 mA
VIN = VIH or Vil
Vee = Min
VOL
Output LOW Voltage
IOl = 16 mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
VI
Input Clamp Voltage
liN = -18 mA, Vee = Min
hH
Input HIGH Current
III
Input LOW Current
II
Maximum Input Current
VIN = 5.5 V, Vee = Max
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Min
Max
Unit
V
2.4
0.5
V
V
2.0
0.8
V
-1.2
V
VIN = 2.7 V, Vee = Max (Note 2)
25
~
VIN = 0.4 V, Vee = Max (Note 2)
-100
~
1
mA
VOUT = 2.7 V, Vee = Max
VIN = VIH or Vil (Note 2)
100
~
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vee = Max
VIN = VIH or Vil (Note 2)
-100
~
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
-130
mA
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mA)
Vee = Max
180
mA
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system andlor tester noise are included.
2. /10 pin leakage is the worst case of hL and IOZL (or hH and IOZH ).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-270
PAL22V10-15 (Com'I)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Description
Test Conditions
Input Capacitance
VIN =2.0 V
Output Capacitance
VOUT=2.0 V
Typ
Unit
9
6
5
pF
Vee =5.0 V
TA = 25°C
f = 1 MHz
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
(Note 3)
Parameter Description
Max
Unit
15
ns
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP to Clock
10
ns
tH
Hold Time
0
ns
teo
Clock to Output
10
tAR
Asynchronous Reset to Registered Output
20
ns
ns
tARW
Asynchronous Reset Width
15
tARR
Asynchronous Reset Recovery Time
10
ns
tSPR
Synchronous Preset Recovery Time
10
ns
tWL
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 4)
ns
LOW
6
ns
HIGH
6
ns
50
MHz
External Feedback
I
1/(ts + teo)
Internal Feedback (teNT)
No Feedback
I
1/(tWH + tWL)
80
MHz
83
MHz
tEA
Input to Output Enable Using Product Term Control
15
ns
tER
Input to Output Disable Using Product Term Control
15
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums are measured under best-case conditions.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PAL22V10·15 (Com'l)
2·271
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied ................. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. O°C to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage ............... -0.5 V to +5.5 V
DC Input Current .............. -30 rnA to +5 rnA
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 1/0 Pin Voltage ... -0.5 V to Vee Max
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
IOH m-3.2 mA
Min
VIN .. VIH or VIL
Vee
= 16 mA
VIN = VIH or VIL
Vee = Min
Output LOW Voltage
IOL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
VI
Input Clamp Voltage
liN = -18 mA, Vee
hH
Input HIGH Current
= 2.7 V, Vee = Max (Note 2)
VIN = 0.4 V, Vee .. Max (Note 2)
VIN = 5.5 V, Vee = Max
VOUT = 2.7 V, Vee = Max
Input LOW Current
II
Maximum Input Current
IOZH
IOZl
Off-State Output Leakage
Current HIGH
Off-State Output Leakage
Current LOW
Unit
V
= Min
VOL
ilL
Max
2.4
0.5
2.0
V
0.8
= Min
VIN
= VIH or VIL (Note 2)
VOUT = 0.4 V, Vee = Max
V
V
-1.2
V
25
~
-100
~
1
rnA
100
~
-100
~
-90
rnA
180
rnA
VIN
VIN
= VIH or Vil (Note 2)
=0.5 V, Vee = Max (Note 3)
Isc
Output Short-Circuit Current
VOUT
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mA)
Vee = Max
-30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IiL and IOZL (or IIH and IOZH ).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT
has been chosen to avoid test problems caused by tester ground degradation.
2-272
AmPAL22V10A (Com'I)
=0.5 V
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Description
Test Conditions
Input Capacitance
VIN =2.0 V
Output Capacitance
VOUT=2.0 V
Typ
Unit
11
6
pF
Vee =5.0 V
TA = 25°C
f = 1 MHz
9
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP to Clock
tH
Hold Time
Max
25
Unit
ns
20
ns
0
ns
teo
Clock to Output
15
ns
tAR
Asynchronous Reset to Registered Output
30
ns
Asynchronous Reset Width
25
ns
tARR
Asynchronous Reset Recovery Time
35
ns
tSPR
Synchronous Preset Recovery Time
20
ns
LOW
15
ns
HIGH
15
ns
28.5
MHz
tARW
twL
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 3)
External Feedback
1/(ts + teo)
tEA
Input to Output Enable Using Product Term Control
25
ns
tER
Input to Output Disable Using Product Term Control
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
AmPAL22V10A (Com'I)
2-273
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Military (M) Devices (Note 1) .
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
DC Input Voltage ............... -1.2 V to +7.0 V
DC Output or 1/0 Pin Voltage ..... -0.5 V to +7.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
Ambient Temperature (TA)
Operating in Free Air ............ "
-55°C Min
Operating Case (Te)
Temperature .................. "
125°C Max
Supply Voltage (Vee)
with Respect to Ground ..... +4.50 V to +5.50 V
Note:
1. Military products are tested at Te
and -5SOC, per MIL-STD-883.
=+2SOC, +12SOC,
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
(Note 2)
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-2 mA
VIN = VIH or Vil
Vee = Min
Min
VOL
Output LOW Voltage
IOl = 12 mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
VI
Input Clamp Voltage
liN = -18 mA, Vee = Min
IIH
Input HIGH Current
III
Input LOW Current
= 2.7 V, Vee = Max (Note 4)
VIN = 0.4 V, Vee = Max (Note 4)
Max
0.5
0.8
1.lnput
lCLK
= 5.5 V, Vee = Max
V
V
2.0
VIN
Unit
V
2.4
V
-1.2
V
25
~
-100
-150
~A
Maximum Input Current
VIN
1
mA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, Vee = Max
VIN = VIH or Vil (Note 4)
100
~
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vee = Max
VIN = VIH or Vil (Note 4)
-100
~
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 5)
-130
mA
lee
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mA)
Vee = Max
200
mA
II
-30
Notes:
2. For APL Products, Group A, Subgroups 1,2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted.
3. ViL and V/H are input conditions of output tests and are not themselves directly tested. V/L and V/H are absolute voltages with
respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values
without suitable equipment.
4. 110 pin leakage is the worst case of IlL and IOZL (or I/H and IOZH ).
5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-274
PAL22V10-12 (Mil)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN '" 2.0 V
Output Capacitance
VOUT ... 2.0 V
Typ
I
I
Vee = 5.0 V
TA" 25°C
f = 1 MHz
Unit
6
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
Parameter
Symbol
tPD
ts
tH
Min
Parameter Description
Unit
12
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
10
Hold Time
0
ns
ns
ns
10
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
tARW
Max
ns
20
Asynchronous Reset Width (Note 3)
ns
15
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
10
ns
tSPR
Synchronous Preset Recovery Time (Note 4)
10
ns
LOW
6
ns
HIGH
6
ns
50
MHz
58.8
MHz
tWL
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 4)
External Feedback
I 1/(ts + teo)
Internal Feedback (feNT)
No Feedback
I 1/(twH + tWL)
83.3
MHz
tEA
Input to Output Enable Using Product Term Control (Note 4)
15
ns
tER
Input to Output Disable Using Product Term Control (Note 4)
12.5
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3. tARW and tARR are not directly tested, but are guaranteed by the testing of ts and tAR.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
PAL22V10-12 (Mil)
2-275
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Military (M) Devices (Note 1)
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . .. -55°C Min
DC Input Voltage ............... -0.5 V to +5.5 V
Operating Case (Te)
Temperature .............. ; . . . .. 125°C Max
DC Output or liO Pin Voltage ..... -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.50 V to +5.50 V
DC Input Current . . . . . . . . . . . . .. -30 rnA to +5 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
Note:
1. Military products are tested at Tc
and -55"C, per MIL-STD-883.
= +25" C, + 125" C,
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
(Note 2)
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-2 mA
VIN = VIH or VIL
Vee = Min
Min
Max
VOL
Output LOW Voltage
IOL=12mA
VIN = VIH or VIL
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
VI
Input Clamp Voltage
liN = -18 mA, Vee = Min
-1.2
V
hH
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 4)
25
~
ilL
Input LOW Current
VIN = 0.4 V, Vee = Max (Note 4)
-100
~
II
Maximum Input Current
VIN 0= 5.5 V, Vee = Max
1
mA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V, Vee = Max
VIN = VIH or Vil (Note 4)
100
~
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0.4 V, Vee = Max
VIN = VIH or VIL (Note 4)
-100
~
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 5)
-90
mA
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mA)
Vee = Max
200
mA
2.4
V
0.5
2.0
V
V
0.8
-30
Unit
V
Notes:
2. For APL Products, Group A, Subgroups 1,2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted.
3. \ilL and V/H are input conditions of output tests and are not themselves directly tested. V/L and V/H are absolute voltages with
respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values
without suitable equipment.
4. 110 pin leakage is the worst case of IlL and IOZL (or ItH and lozH ).
5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-276
PAL22V10-20 (Mil)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN =2.0 V
Output Capacitance
VOUT
= 2.0 V
Typ
Unit
9
Vee = 5.0 V
TA = 25°C
f = 1 MHz
pF
6
9
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARV operating ranges (Note 2)
Parameter
Symbol
tPD
Min
Parameter Description
Input or Feedback to Combinatorial Output
Max
Unit
20
ns
ts
Setup Time from Input or Feedback to Clock
17
ns
tH
Hold Time
0
ns
15
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
tARW
ns
25
ns
20
Asynchronous Reset Width (Note 3)
ns
tARR
Asynchrono~s
Reset Recovery Time (Note 3)
20
ns
tSPR
Synchronous Preset Recovery Time (Note 4)
20
ns
tWL
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 4)
LOW
15
ns
HIGH
15
ns
31.2
MHz
External Feedback
I 1/(ts + teo)
Internal Feedback (feNT)
33.3
MHz
tEA
Input to Output Enable Using Product Term Control (Note 4)
20
ns
tER
Input to Output Disable Using Product Term Control (Note ~)
20
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3. tARW and tARR are not directly tested, but are guaranteed by the testing of ts and tAR.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
PAL22V10-20 (Mil)
2-277
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Military (M) Devices (Note 1)
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . .. -55°C Min
DC Input Voltage ............... -0.5 V to +5.5 V
Operating Case (Te)
Temperature . . . . . . . . . . . . . . . . . . .. 125°C Max
DC Output or I/O Pin Voltage ... -0.5 V to Vee Max
Supply Voltage (Vee)
with Respect to Ground ..... "+4.50 V to +5.50 V
DC Input Current . . . . . . . . . . . . .. -30 rnA to +5 rnA
Output Sink Current ............ 100 rnA (Note 6)
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
Note:
1. Military products are tested at Tc
and -5S'C, per MIL-STD-883.
=+2S'C, + 12S'C,
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
(Note 2)
Parameter
Symbol
Min
Max
Parameter Description
Test Conditions
VOl-!
Output HIGH Voltage
IOH =-2 mA
VIN = VIH or Vil
Vee = Min
VOL
Output LOW Voltage
IOl=12mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
VI
Input Clamp Voltage
liN = -18 mA, Vee = Min
hH
Input HIGH Current
VIN = 2.7 V, Vee = Max (Note 4)
25
III
Input LOW Current
' VIN = 0.4 V, Vee = Max (Note 4)
-100
~
II
Maximum Input Current
VIN = 5.5 V. Vee = Max
1
mA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 2.7 V. Vee = Max
VIN = VIH or Vil (Note 4)
100
~
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0.4 V. Vee = Max
VIN = VIH or Vil (Note 4)
-100
~
Isc
Output Short-Circuit Current
VOUT = 0.5 V. Vee = Max (Note 5)
Icc
Supply Current
VIN = 0 V. Outputs Open (lOUT = 0 mA)
Vee = Max
2.4
V
0.5
2.0
V
V
0.8
' -1.2
-30
Unit
V
V
~
-90
mA
180
mA
Notes:
2. For APL Products, Group A, Subgroups 1,2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted.
3. VtL and VtH are input conditions of output tests and are not themselves directly tested. VtL and litH are absolute voltages with
respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values
without suitable equipment.
4. I/O pin leakage is the worst ca
78 of liL and lozL
(or ItH and IozH ).
5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT
has been chosen to avoid test problems caused by tester ground degradation.
2·278
AmPAL22V10/A (Mil)
=0.5 V
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
Parameter Description
Test Conditions
I Pins 1, 13
Input Capacitance
VIN
Typ
= 2.0 V
Vee = 5.0 V
TA = 25°C
f = 1 MHz
1Others
COUT
Output Capacitance
VOUT
= 2.0 V
Unit
11
pF
6
9
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
Std
A
Parameter
Symbol
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
Max
Min
30
25
0
Max
Unit
40
ns
35
ns
ns
0
teo
Clock to Output
20
25
ns
tAR
Asynchronous Reset to Registered Output
35
45
ns
tARW
Asynchronous Reset Width (Note 3)
30
40
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
30
40
ns
tWL
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 4)
LOW
20
30
ns
HIGH
20
30
ns
22
16.5
MHz
External Feedback
1/(ts + teo)
tEA
Input to Output Enable Using Product
Term Control (Note 5)
30
40
ns
tER
Input to Output Disable Using Product
Term Control (Note 5)
30
40
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3. tARW and tARR are not directly tested, but are guaranteed by the testing of ts and tAR.
4. These parameters are not 100% tested, but are calculated at initial charzation ond at any time the design is modified where
frequency may be affected.
5. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
'
AmPAL22V10/A (Mil)
2-279
~
AMD
SWITCHING WAVEFORMS
Input or
Input or
Feedback
Combinatorial
Output
-~-VT
F••
r
t
:~::---"""I:=~:t:~'
Vr
---~teo
VT
Registered
Output _ _ _ _ _ _ _ _......
165598-8
165598-7
Registered Output
Combinatorial Output
Input or
Feedback _ _ _- - I
tER
Clock
Output
----.....L..L..I.-1
165598-10
165598-9
Input to Output Disable/Enable
Clock Width
Input
Input
Asserting
Asynchronous
Reset
Asserting
Synchronous
Preset
=l=
_ _ _ __
ts
Registered
Output _ _ _"'-"'--K.............,
Clock
tARR
Clock
VT
Registered
Output
_ - ' - -_ _ _ _..J
-----------xXffi·
teo
VT
~---;...
\.-.._ _ __
165599-12
165598-11
Asynchronous Reset
Synchronous Preset
Notes:
1. Vr = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns - 4 ns typical.
2-280
PAL22V10 Family
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/////
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
XXXXXX
J1)
EK
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Output D--+----.....--te) Test Point
165598-13
Military
Commercial
Specification
tpo. teo
tEA -
S1
R1
R2
R1
R2
Measured
Output Value
50 pF
300n
All except
-7:
390n
390n
750n
1.5 V
Closed
Z~
Z~
tER
CL
H:Open
L: Closed
H ~Z: Open
L~Z:
Closed
5 pF
-7:
300n
PAL22V10 Family
1.5 V
H ~Z: VOH-0.5 V
L ~Z: VOL + 0.5 V
2·281
~
AMD
MEASURED SWITCHING CHARACTERISTICS for the PAL22V10-10
Vee
= 4.75 V, TA = 75°C (Note 1)
10
9
tpo, ns
8
7+---r-~~-+--~--+---r--+--~~
234
5
6
7
8
9
10
Number of Outputs Switching
bo VS. Number of Outputs Switching
165598-14
13
12
11
10
tpo, ns
9
8
7
0
40
120
80
160
200
el, pF
tpo VS. Load Capacitance
165598-15
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where tPD may be affected.
2-282
PAL22V10-10
AMD~
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
Input
ProgramNerify
Circuitry
165598-16
Typical Input
------------------.-------~
Vee
400 NOM
......I - - -.....--.-_o
~-+-
Input,
liD
Pins
Output
ProgramNerifyl
Test Circuitry
Preload
Circuitry
165598-17
Typical Output
PAL22V10 Family
2·283
~
AMD
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation
of the power-up reset and the wide range of ways Vcc
Parameter
Symbol
can rise to its steady state, two conditions are required
to ensure a valid power-up reset. These conditions are:
•
The Vcc rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOWto HIGH until all applicable input and feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-up Reset Time
1000
ns
ts
Input or Feedback Setup Time
tWL
Clock Width LOW
See Switching
Characteristics
Vcc
Power
Registered
Active-Low
Output
Clock
165598-18
Power-Up Reset Waveform
2-284
PAL22V10 Family
AMD~
2-285
COM'L: H-5/7/10/15/25, Q-10/15/25
_
MIL: H-10/15/20/25/30
Advanced
Micro
Devices
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
•
•
•
•
As fast as 5 ns propagation delay and
142.8 MHz fMAx (external)
Low-power EE CMOS
10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to
16 product terms per output for complex
functions
~
•
•
•
•
•
Global asynchronous reset and synchronous
preset for Initialization
Power-up reset for Initialization and register
preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-pln SKINNYDIP, 24-pln SOIC, 24-pln Flatpack and 28-pln PLCC and LCC packages save
space
5 ns and 7.5 ns versions utilize split lead frames
for Improved performance
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic
for replacing conventional SSI/MSI gates and flip-flops
at a reduced chip count.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AN D array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 t016 across the outputs
(see Block Diagram). The OR sum ofthe products feeds
the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two bits controlling two multiplexers in
each macrocell.
AMD's FusionPLD program allows PALCE22V10 designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accu rate, quality support. By ensu ring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. Th,e FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
BLOCK DIAGRAM
VOo
2-286
1/02
VOs
VOs
V07
VOe
V()g
Publication# 16564 Rev, B
Issue Date: June 1993
Amendment/O
AMD
CONNECTION DIAGRAMS
Top View
PLCC/LCC
SKINNYDIP/SOIC/FLATPACK
Vee
110g
II0a
1/07
1105
13
14
15
1/04
NC
1103
16
17
18
1106
1/02
1/01
1100
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
= Clock
GND = Ground
Input
= Input/Output
NC
= No Connect
Vee
= Supply Voltage
1/06
1105
NC
1/04
1/03
1/02
-=zz=OO
(!J
::::. ::::.
165648-2
1/0
co
1/07
0)000..-0..-
111
ClK
C\J
25
24
23
22
21
20
19
PALCE22V10 Family
165648-3
;t1
~
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
PAL
_____T-l
p~ £.a _V,... 10
H -5
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY--------~
CE
=CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE --------~
V
=
Versatile
NUMBER OF OUTPUTS
P C 15
r
OPTIONAL PROCESSING
Blank = Standard processing
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
14
First Revision
15
Second Revision
(Same Algorithm as 14)
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
PACKAGE TYPE
POWER-------------~
Q = Quarter Power (55 mA Icc)
H = Half Power (90-140 mA Icc)
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
S = 24-Pin Plastic Gull-Wing
Small Outline Package
(SO 024)
SPEED
-5
-7
-10
-15
-25
Valid Combinations
PALCE22V10-5
JC
PALCE22V10H-7
15
PALCE22V10H-10
PALCE22V1OQ-10
PC,JC, SC
PALCE22V10H-15
2-288
PC,JC
PALCE22V10H-25
PC,JC, SC
PALCE22V1oo-25
PC,JC
= 10 ns tPD
= 15 ns tPD
= 25 ns tPD
Valid Combinations
Valid Combinations lists configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Blank,/4
PALCE22V10Q-15
= 5 ns tPD
= 7.5 ns tpD
15
Blank,/4
PALCE22V10H-5/7/10/15/25, Q-10/15/25 (Com'l)
AMD~
ORDERING INFORMATION
APL Products
AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of:
_____T..IAL
~~ ~~ -Y- 10
H -15 E4 IB
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY------------~
L
A
~
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE ----------~
V = Versatile
LEAD FINISH
A = Hot Solder Dip
PACKAGE TYPE
L = 24-Pin 300-mil Ceramic
SKINNYDIP (CD3024)
K = 24-Pin Ceramic Flatpack
(CFL024)
3 = 28-Pin Ceramic
Leadless Chip Carrier
(CL 028)
DEVICE CLASS
!8 = MIL-STD-883C Class B
NUMBER OF OUTPUTS
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
E4
First Revision
POWER--------------------------~
H = Half Power (100 - 150 mA Icc)
SPEED
-15 == 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
-30 = 30 ns tPD
Valid Combinations
PALCE22V10H-15
PALCE22V10H-20
PALCE22V10H-25
E4
Blank,
E4
IBLA,/BKA,
IB3A
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE22V10H-30
Group A Tests
Group A tests consist of Subgroups
1, 2, 3, 7, 8, 9, 10, 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A
through E. Test conditions are selected at AMD's option.
PALCE22V10H-1S/20/2S/30 (Mil)
2-289
~
AMD
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming EE cells to
configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required timeconsuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified during prototyping or production.
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state.
The PALCE22V1 0 has 12 inputs and 10 110 macrocells.
The macrocell Figure 1allows one of four potential output configurations; registered output or combinatorial
110, active high or active low (see Figure 1). The configuration choice is made according to the user's design
. specification and co~responding programming of the
configuration bits So - S1. Multiplexer controls are connected to ground (0) through a programmable bit, selecting the "0" path through the multiplexer. Erasing the
bit disconnects the control line from GND and it is driven
to a high level, selecting the "1" path.
The device is produced with a EE cell link at each input
to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the
circuit. Utilizing an easily-implemented programming al- '
gorithm, these products can be rapidly programmed to
any customized pattern.
Variable Input/Output Pin Ratio
The PALCE22V1 0 has twelve dedicated input lines, and
each macrocell output can be an 1/0 pin. Buffers for device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GND .
I/On
Output Configuration
51
50
0
0
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
Combinatorial/Active High
0= Programmed EE bit
1 = Erased (charged) EE bit
165648-4
Figure 1. Output Logic Macrocell Diagram
2·290
PALCE22V10 Family
AMD
l1
Registered Output Configuration
Combinatorial I/O Configuration
Each macrocell of the PALCE22V10 includes aD-type
flip-flop for data storage and synchronization. The flipflop is loaded on the LOW-to-HIGH transition of the
clock input. In the registered configuration (51 = 0), the
array feedback is from of the flip-flop.
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(51 =1). In the combinatorial configuration the feedback
is from the pin.
a
Combinatorial/Active Low
Reg Istered/Active Low
Combinatorial/Active High
Registered/Active High
165648-5
Figure 2. Macrocell Configuration Options
PALCE22V10 Family
2·291
~
AMD
Programmable Three-State Outputs
Register Preload
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
. device inputs or output feedback. The combinatorial
output provides a bidirectional 110 pin, and may be configured as a dedicated input if the buffer is always
disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is controlled by programmable bit So in the
output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high (So = 1).
Preset/Reset
For initialization, the PALCE22V10 has Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP)
product term is asserted high, the output registers will be
loaded with a HIGH on the next LOW-to-HIGH clock
transition. When the Asynchronous Reset (AR) product
term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Security Bit
After programming and verification, a PALCE22V1 0 design can be secured by programming the security EE bit.
Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the
security bit is programmed, the array will read as if every
bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of
the entire pattern.
Programming and Erasing
The PALCE22V10 can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE22V100ffers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the
highest programming yields and post-programming
functional yields in the industry.
Technology
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PALCE22V10 will
depend on the programmed output polarity. The Vee
rise must be monotonic and the reset delay time is
1000 ns maximum.
2·292
The register on the PALCE22V10 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
The high-speed PALCE22V10 is fabricated with AMD's
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are deSigned to be compatible with
TIL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clear switching.
PALCE22V10 Family
AMD~
LOGIC DIAGRAM
SKINNVDIP/SOIC/FLATPACK (PLCC/LCC) Pinouts
...
ill
(2)
], ,~ t I I T f"V fu? If,,19 2O u 2t 2t 27 28 ,3,1 12, 35
0
I
1111 1111
1111 1111
III
III
36
II I
(28)
3l fu 4t
AR
1111
r-
9
1
1.
-~'
IS
01
2 IlO g
(27)
SP
o
~
':'
I
10
~J
o
20
0 0
01
IS
..
~
(26)
SP
m
'i3i
o
-
-
21
~":'lJ
~
IS
o
33
3
(4)
lJ I
...
I
I
I I I
34
01
o
l.!..J
I
"
48
49
..
-,
0
IS
ta
01
II
o
"
l.!..J
(25)
-@
1/06
(24)
.".
~
L
0 OJ
..
~"tj
o
-ffi]
.,..
~:: 1
J
SP
~
(5)
.".
I
0
19 1105
(23)
IS
rn(6)
~
65
o
-
I
T I
66
l!..J
-
.r82
6
83
II
I
"
I
li! '
~::J
'
(7)
-
0
Q
SP
0
o
-ill]
(21)
-
L...!J
""
I" I
1
)-
~ ,~
~"!
,AAo
IS
:>"'
01
17
(20)
SP
97
7
(9)
I I
I
I
I I J
11 IIII
I I
I
o
~::J..
~'
IS
0
,
110
8
(10)
III
III
II
lL11 i l
122
l.!J
IS
11 II
II
I
o
I
lbJ.
I
r-
130
10
(12)
-
131
.A
[j]
r---<"
(13)
GND
!W---:t
(14)
3
4
7
8
II 12
15 16
19 20
23 24
27 28
31
32
35 36
39 40
43
liL'
IS
.00
lii'
01
o
:IE
(18)
-
~::l
SP
'9
.".
01
, SP 0
II II Jill
16
(19)
oJ.".
~::J
I I
m-
01
SPJ~
II
III
121
(;1)
.".
l..!J
I
98
-{ill 110 0
(17)
':'-
I
...sf'
1
(16)
165648-6
.".
PALCE22V10 Family
2-293
~
AMD
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. O°C to +75°C
Supply Voltage with Respect
to Ground .................... -0.5 V to +7.0 V
Supply Voltage (Vce) with
Respect to Ground ......... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 1.0 V
DC Output or 1/0 Pin
Voltage .................. -0.5 V to Vee + 1.0 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latchup Current (TA
= O°C to +75°C)
...... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
PRELIM NARY
Parameter
Symbol
Parameter Description
Test Conditions
Voo
Output HIGH Voltage
IOH =-3.2 mA
VIN = VIH or Vil
Vee = Min
Min
VOL
Output LOW Voltage
IOL = 16 mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
III
Input LOW Leakage Current
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Max
Unit
V
2.4
V
0.4
V
2.0
0.8
V
VIN = Vce. Vec = Max (Note 2)
10
~
VIN = 0 V. Vec = Max (Note 2)
-100
~
Your = Vee. Vee - Max.
VIN = Vil or VIH (Note 2)
10
~
Off-State Output Leakage
Current LOW
VOUT = 0 V. Vee = Max.
VIN = Vil or VIH (Note 2)
-100
~
Isc
Output Short-Circuit
Current
Vour = 0.5 V. Vee .. Max
(Note 3)
-130
mA
Icc
Supply Current
(Static)
Outputs Open. (lOUT = 0 mA).
Vee = Max
115
mA
Supply Current
(Dynamic)
Outputs Open. (lOUT - 0 mA).
Vec = Max. f = 25 MHz
140
mA
-30
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. 110 pin leakage is the worst case of hL and IOZL (or hH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-294
PALCE22V10H-5 (Com'l)
AMD~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
Unit
5
Vee =5.0 V
TA = 25°C
f = 1 MHz
pF:
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
PRELIMINARY
-5
Parameter Description
Min
Max
Unit
1
5.0
ns
tPD
Input or Feedback to Combinatorial Output
t51
Setup Time from Input or Feedback
3.0
ns
t52
Setup Time from SP to Clock
4.0
ns
tH
Hold Time
0
Clock to Output
1
teo
tS"KEWA
tAA
Skew Between Registered Outputs (Note 3)
Asynchronous Reset to Registered Output
ns
4.0
ns
1
ns
7.5
ns
tARW
Asynchronous Reset Width
4.5
tARR
Asynchronous Reset Recovery Time
4.5
ns
tSPR
Synchronous Preset Recovery Time
4.5
ns
tWL
tWH
Clock Width
LOW
2.5
ns
HIGH
2.5
ns
142.8
MHz
External Feedback
fMAX
Maximum
Frequency
(Note 4)
ns
I
1/(ts + teo)
Internal Feedback (feNT)
I
No Feedback
1/(tWH + tWL)
150
MHz
200
MHz
tEA
Input to Output Enable Using Product Term Control
5.0
ns
tEA
Input to Output Disable Using Product Term Control
5.0
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Skew is measured with all outputs switching in the same direction.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE22V10H-5 (Com'l)
2-295
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. O°C to +75°C
Supply Voltage with Respect
to Ground .................... -0:5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 1.0 V
DC Output or I/O Pin
Voltage .................. -0.5 V to Vee + 1.0 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latchup Current (TA
= O°C to +75°C)
...... 100 rnA
Stresses abOve those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
IOH =-3.2 mA
Min
VIN = VIH or VIL
Max
2.4
Unit
V
Vee = Min
VIN = VIH or VIL
Vee = Min
0.4
V
VOL
Output LOW Voltage
IOL = 16 mA
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Vohage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = Vee, Vee = Max (Note 2)
10
~
ilL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
-100
~
Off-State Output Leakage
10
~
Current HIGH
VOUT = Vee, Vee = Max,
VIN = VIL or VIH (Note 2)
Off-State Output Leakage
VOUT = 0 V, Vee = Max,
-100
~
Current LOW
VIN = VIL or VIH (Note 2)
Output Short-Circuit
Current
-130
mA
TA = 25°C (Note 3)
115
mA
140
mA
IOZH
IOZL
Ise
lee
VOUT = 0.5 V, Vee = Max
Supply Current
(Static)
Outputs Open, (lOUT = 0 mA),
Supply Current
(Dynamic)
Outputs Open, (lOUT
2.0
-30
V
Vee = Max
Vee = Max, f
= 0 mA),
= 25 MHz
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. 110 pin leakage is the worst case of IJL and IOZL (or IJH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-296
PALCE22V10H-7 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
GoUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT= 2.0 V
Typ
Unit
5
Vcc = 5.0 V
TA = 25°C
f = 1 MHz
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-7
Parameter
Symbol
PDIP
Max
Min
Parameter Description
Input or Feedback to Combinatorial Output
1
tS1
Setup Time from Input or Feedback
5
4.5
ns
tS2
Setup Time from SP to Clock
6
6
ns
tH
Hold Time
0
tco
Clock to Output
1
tAR
Skew Between Registered Outputs (Note 3)
Asynchronous Reset Width
tARR
tSPR
fMAX
1
10
ns
ns
4.5
ns
1
ns
10
ns
7
7
Asynchronous Reset Recovery Time
·7
7
ns
Synchronous Preset Recovery Time
7
7
ns
ns
tWL
tWH
7.5
0
5
1
Asynchronous Reset to Registered Output
tARW
1
Unit
tPD
tSKEWA
7.5
PLCC
Min
Max
Clock Width
Maximum
Frequency
(Note 4)
ns
LOW
3.5
3.0
HIGH
3.5
3.0
ns
External Feedback 11/(ts + tco)
100
111
MHz
125
133
MHz
142.8
166
Internal Feedback (tCNT)
I 1/(twH + tWL)
No Feedback
MHz
tEA
Input to Output Enable Using Product Term Control
7.5
7.5
ns
tEA
Input to Output Disable Using Product Term Control
7.5
7.5
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Skew is measured with all outputs switching in the same direction.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE22V10H-7 (Com'l)
2-297
~AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air ............ O°C to +75°C
Supply Voltage with Respect
to Ground .................... -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ......... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 1.0 V
DC Output or 1/0 Pin
Voltage .................. -0.5 V to Vee + 1.0 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Latehup Current (TA
= O°C to +75°C)
...... 100
rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 mA
VIN = VIHor Vil
Vee = Min
VOL
Output LOW Voltage
IOl = 16 mA
VIN = VIH or Vil
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
III
Input LOW Leakage CUrrent
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Min
Max
2.4
Unit
V
0.4
2.0
V
V
0.8
V
VIN = Vee, Vee = Max (Note 2)
10
~
VIN = 0 V, Vee = Max (Note 2)
-100
~
VOUT = Vee, Vee =Max,
VIN = Vil or VIH (Note 2)
10
~
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = Vil or VIH (Note 2)
-100
~
Ise
Output Short-Circuit
Current
VOUT = 0.5 V, Vee = Max
TA = 25° C (Note 3)
-130
mA
Icc
Supply Current
(Dynamic)
Outputs Open, (lOUT = 0 mAl,
Vee = Max, f = 25 MHz
120
mA
-30
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. 110 pin leakage is the worst case of IlL and IOZL (or hH and IOZH).
3. Not more than one output should be tested at a· time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-298
PALCE22V10H-10 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
GoUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT =2.0 V
Vee =5.0 V
TA = 25°C
f = 1 MHz
Typ
Unit
5
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
-10
Min
Parameter Description
Max
Unit
10
ns
tPD
Input or Feedback to Combinatorial Output
t51
Setup Time from Input or Feedback
6
t52
Setup Time from SP to Clock
7
ns
tH
Hold Time
0
ns
ns
teo
Clock to Output
6
ns
tAR
Asynchronous Reset to Registered Output
13
ns
tARW
Asynchronous Reset Width
8
tARR
Asynchronous Reset Recovery Time
8
ns
tSPR
Synchronous Preset Recovery Time
8
ns
tWL
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 3)
ns
LOW
4
ns
HIGH
4
ns
External Feedback 11/(tS + teo)
83.3
MHz
Internal Feedback (teNT)
110
MHz
125
MHz
I 1/(tWH + tWL)
No Feedback
tEA
Input to Output Enable Using Product Term Control
10
ns
tER
Input to Output Disable Using Product Term Control
9
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE22V10H-10 (Com'l)
2-299
~
AMD
PRE LIM I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air .............. O°C to +75°C
Supply Voltage with Respect
to Ground .................... -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ............ +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vee + 1.0 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 1/0 Pin
Voltage .................. -0.5 V to Vee + 1.0 V
Static Discharge Voltage ................. 2001 V
Latchup Current (TA= O°C to +75°C) ...... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
PRELIMINARY
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-3.2 rnA
VIN = VIH or VIL
Vee = Min
VOL
Output LOW Voltage
IOL = 16 rnA
VIN = VIH or VIL
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
hH
Input HIGH Leakage Current
ilL
Input LOW Leakage Current
IOZH
Off-State Output Leakage
Current HIGH
VOUT = Vee, Vee = Max
VIN = VIL or VIH (Note 2)
IOZL
Off-State Output Leakage
Current LOW
Vour = 0 V, Vee = Max
VIN = VIL or VIH (Note 2)
Ise
Output Short-Circuit
Current
VOUT = 0.5 V, Vee = 5 V
TA = 25°C (Note 3)
lec
Supply Current (Static)
VIN = 0 V, Outputs Open
(lOUT = 0 rnA), Vee = Max
Min
Max
Unit
2.4
V
0.4
V
2.0
V
O.B
V
VIN = Vee, Vec = Max (Note 2)
10
VIN = 0 V, Vee = Max (Note 2)
-100
10
JlA
JlA
JlA
-100
JlA
-130
rnA
55
rnA
-30
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. 110 pin leakage is the worst case of ItL and lozL (or I/H and lozH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
Your = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-300
PALCE22V10Q-10 (Com'l)
AMD~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN =2.0 V
COUT
Output Capacitance
VOUT = 2.0 V
Typ
I Vee =5.0 V
I TA=25°C
f 1 MHz
Unit
5
pF
8
=
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
PRELIMINARY
Parameter
Symbol
-10
Parameter Description
Min
tpo
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP to Clock
6
tH
Hold Time
0
Max
Unit
10
ns
ns
ns
6
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
13
ns
ns
tARW
Asynchronous Reset Width
8
ns
tARR
Asynchronous Reset Recovery Time
8
ns
tSPR
Synchronous Preset Recovery Time
8
ns
LOW
4
ns
HIGH
4
ns
83
MHz
110
MHz
tWl
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 3)
External Feedback
I
l/(ts + teo)
Internal Feedback (feNT)
I
No Feedback
l/(tWH + tWl)
125
MHz
tEA
Input to Output Enable Using Product Term Control
10
ns
tER
Input to Output Disable Using Product Term Control
9
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE22V10Q-10 (Com'l)
2-301
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to +125°C
Supply Voltage with Respect
to Ground ................... -0.5 V to +7.0 V
Commercial (C) Devices
DC Input Voltage .......... -0.5 V to Vee + 0.5 V
DC Output or I/O Pin
Voltage .................. -0.5 V to Vee + 0.5 V
Statie Discharge Voltage ................. 2001 V
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. O°C to +75°C
Supply Voltage (Vce) with
IRespect to Ground (H/Q-15) .. +4.75 V to +5.25 V
Supply Voltage (Vee) with
Respect to Ground (H/Q-25) ... , +4.5 V to +5.5 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Latchup Current (TA = O°C to +75°C) ...... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
2.4
Unit
V
VOH
Output HIGH Voltage
IOH =-3.2 rnA
VIN = VIHor VIL
Vee = Min
VOL
Output LOW Voltage
IOL = 16 rnA
VIN = VIH or VIL
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
hH
Input HIGH Leakage Current
VIN = Vee, Vee = Max (Note 2)
10
~
ilL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
-100
~
IOZH
Off-State Output Leakage
Current HIGH
VOUT = Vee, Vee = Max,
VIN = VIL or VIH (Note 2)
10
~
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max,
VIN = VIL or VIH (Note 2)
-100
~
Ise
Output Short-Circuit
Current
-130
rnA
TA = 25°C (Note 3)
90
55
rnA
lec
Supply Current
0.4
2.0
-30
VOUT = 0.5 V, Vee = 5 V
VIN = 0 V, Outputs Open
(lOUT = 0 rnA), Vee = Max
Notes:
k-
V
V
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. 110 pin leakage is the worst case of IJL and IOZL (or IJH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-302
PALCE22V10H-15/25, Q-15/25 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Typ
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Vee = 5.0 V
5
Output Capacitance
VOUT=2.0 V
TA = 25°C
f = 1 MHz
8
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS O\ler COMMERCIAL operating ranges (Note 2)
-25
-15
Parameter
Symbol
Parameter Description
Min
Max
Min
15
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input. Feedback or SP to Clock
10
15
tH
Hold Time
0
0
teo
Clock to Output
10
tAR
Asynchronous Reset to Registered Output
20
Max
Unit
25
ns
ns
ns
15
ns
25
ns
tARW
Asynchronous Reset Width
15
25
ns
tARR
Asynchronous Reset Recovery Time
10
25
ns
tSPR
Synchronous Preset Recovery Time
10
25
ns
8
13
ns
LOW
tWL
tWH
fMAX
Clock Width
Maximum
Frequency
(Note 3)
HIGH
External Feedback
I
1/(ts + teo)
Internal Feedback (teNT)
8
13
ns
50
33.3
MHz
35.7
58.8
MHz
tEA
Input to Output Enable Using Product Term Control
15
25
ns
tER
Input to Output Disable Using Product Term Control
15
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
PALCE22V10H-15/25, 0-15/25 (Com'I)
2-303
~
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .......... -65°C to +150°C
OPERATING RANGES
Military (M) Devices (Note 1)
Ambient Temperature
with Power Applied ............ -55°C to + 125°C
Operating Case
Temperature (Te) ........... -55°C to +125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to+7.0 V
Supply Voltage (Vee)
with Respect to Ground ....... +4.5 V to +5.5 V
DC Input Voltage ......... "
-0.5 V to Vee + 1.0 V
DC Output or 1/0
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Note:
1. 'Military products are tested at Tc
= +25' C, + 12SO C
and -SSOC, per MIL-STD-883.
Static Discharge Voltage ................. 2001 V
Latchup Current (TA
=-55°C to +125°C)
... 100 rnA
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
(Note 2)
Parameter
Symbol
Min
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-2.0 rnA
Vee = Min
VOL
Output LOW Voltage
IOl = 12 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
IIH
Input HIGH Leakage Current
III
Input LOW Leakage Current
= 5.5 V, Vee = Max (Note 4)
= 0 V. Vec = Max (Note 4)
VOUT = 5.5 V. Vee = Max.
VIN = Vil or VIH (Note 4)
VOUT = 0 V. Vee = Max.
VIN = VIH or Vil (Note 4)
VOUT = 0.5 V. Vee = 5 V
TA = 25°C (Note 5)
VIN = 0 V. Outputs Open
I
(lOUT = 0 rnA). Vee = Max
I
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Isc
Output Short-Circuit
Current
Icc
Supply Current
VIN
VIN
= VIH or Vil
Max
2.4
= VIH or Vil
Unit
V
0.4
2.0
V
V
0.8
V
VIN
10
~
VIN
-10
~
10
~
-10
~
-135
rnA
120
rnA
-50
-15/-20
-25/-30
100
Notes:
2. For APLproducts, Group A, Subgroups 1,2 and 3 are tested per MIL-STD-883. Method 5005, unless otherwise noted.
3. V/L and V/H are input conditions of output tests and are not themselves directly tested. V/L and V,H are absolute voltages
with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values
without suitable equipment.
4. //0 pin leakage is the worst case of hL and lozL (or I/H and IOZH).
5. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. This parameter is not 100%
tested, but is evaluated at initial characterization and at any time the design is modified where Isc may be affected.
2·304
PALCE22V10H-15/20/25/30 (Mil)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
GoUT
Typ
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Vee
=5.0 V
TA =25°C
8
Output Capacitance
VOUT .. 2.0 V
f ... 1 MHz
9
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
Parameter
Symbol
-15
Min Max
Parameter Description
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP
to Clock
12
Hold Time (Note 3)
0
tH
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
Min
-20
Max
-25
Min Max
20
15
25
0
-30
Max
30
20
18
15
Min
ns
ns
0
0
Unit
ns
8
15
20
20
ns
20
25
25
30
ns
20
30
tARW
Asynchronous Reset Width (Note 3)
tARR
Asynchronous Reset Recovery Time (Note 3)
15
20
25
30
ns
tSPR
Synchronous Preset Recovery Time
15
20
25
30
ns
tWL
tWH
LOW
8
10
15
15
Clock Width
ns
HIGH
8
10
15
15
ns
Maximum
Frequency
(Note 3)
External Feedback
1/(ts + teo)
50
33.3
26.3
25
MHz
fMAX
Internal Feedback (feNT)
53
15
25
40
32.2
ns
25
MHz
tEA
Input to Output Enable Using Product
Term Control (Note 3)
15
20
25
25
ns
tER
Input to Output Disable Using Product
Term Control (Note 3)
15
20
25
25
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 7, 8, 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
PALCE22V10H-15/20/25/30 (Mil)
2-305
~AMD
SWITCHING WAVEFORMS
Input or
Feedback
e
_Xffi1tPD.
t
'npulo,
~
Clock
VT
-VT
Combinatorial
Output
Registered
Output _ _ _ _ _ _ _ __
165648-8
165648-7
Registered Output
Combinatorial Output
Input
_ _ _---J
tER
Clock
Output
tEA
)-+o-ttJ-~---4i-+-f-f_ _ _ _-L..L.J.'-4
VT
165648-10
165648-9
Input to Output Disable/Enable
Clock Width
Input
Input
Asserting
Asynchronous
Reset
Asserting
Synchronous
Preset
=f'
_ _ _ __
t5
Registered
Output _ _ _""--IOt.....K........_
Clock _ _ _ _ _ _..J
tARR
Clock
VT
Registered
Output
~~V-T----
165648-11
Asynchronous Reset
Notes:
1. Vr
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns - 5 ns typical.
2-306
165648-12
Synchronous Preset
PALCE22V10 Family
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/77//
May
Change
from L to H
Will be
Changing
from L to H
xxxxxx
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Jl)(K
Does Not
Apply
Center
Line is HighImpedance
"Off"State
WAVEFORM
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
Output
O--..----4--~)
Test Point
165648-13
Commercial
Specification
tPD, teo
tEA
S1
CL
R1
R2
300n
All except
H-517:
390n
Closed
Z~ H: Open
50 pF
Military
R1
R2
Measured
Output Value
1.5 V
390n
750n
1.5 V
Z ~ L: Closed
tEA
H ~Z: Open
L ~Z: Closed
5 pF
H-517:
300n
PALCE22V10 Family
H ~Z: VOH-0.5 V
L ~ Z: VOL + 0.5 V
2·307
~
AMD
TYPICAL lee CHARACTERISTICS
Vee
=5.0 V, TA =25°C
150
125
22V10H-7
22V10H-10
100
lee (mA)
22V10H-15
22V10H-25
75
22V10Q-25
50
25
O-r----+-----~--_+----~----+_--~----_+----~----~--~
o
10
20
30
Frequency (MHz)
40
50
165648-14
lee vs. Frequency
The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for Icc. From this midpoint, a designer may scale the Icc graphs up or down to
estimate the Icc requirements for a particular design.
2-308
PALCE22V10 Family
AMD~
ENDURANCE CHARACTERISTICS
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
The PALCE22V10 is manufactured using AMD's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Endurance Characteristics
Symbol
tOR
N
Test Conditions
Parameter
Min Pattern Data Retention Time
Min Reprogramming Cycles
Min
Unit
Max Storage
Temperature
10
Years
Max Operating
Temperature (Military)
20
Years
Normal Programming
Conditions
100
Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
ESD
ProgramNerify
Protection
Circuitry
Typical Input
Vee
=
Preload
Circuitry
Feedback
Input
16564B-15
Typical Output
PALCE22V10 Family
2-309
~AMD
ROBUSTNESS FEATURES
A special noise filter makes the programming circuitry
completely insensitive to any positive overshoot that
has a pulse width of less than about 100 ns for the /5 version. Selected /4 devices are also being retrofitted with
these robustness features. See the chart below for device listing.
The PALCE22V10X-Xl5 devices have some unique
features that make them extremely robust, especially
when operating in high-speed design environments.
Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping
circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION AND SELECTED
14 DEVICES·
Vee
Vee
>50kn
I
I
I
I
I
.
II Programmlng
ESD
Protection
and
Clamping
L'2n.=.~2:.
=-
____ _
Typical Input
Vee
Vee
>50kn
Provides ESD
Protection and
Clamping
Preload
Circuitry
Feedback
Input
165648-16
Typical Output
•
Device
Rev Letter
PALCE22V10H-15
D
PALCE22V10H-25
D
PALCE22V1oo-25
8
Tops/de Marking:
AMO CMOS PLO's are marked on top of the package in the
following manner:
PALCEXXXX
Oatecode (3 numbers) Lot /D (4 characters)- -(Rev Letter)
The Lot 10 and Rev Letter are separated by two spaces.
2-310
PALCE22V10 Family
AMD~
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Vce can rise to its steady state, two conditions are
Parameter
Symbol
tPR
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Max
Unit
1000
ns
Input or Feedback Setup Time
Clock Width LOW
4?
I
Clock
The Vee rise must be monotonic.
•
Power-up Reset Time
tWL
Registered
Active-Low
Output
•
Parameter Description
ts
Power
required to ensure a valid power-up reset. These conditions are:
See Switching
Characteristics
Vee
~14L.1---- tPR
--'
//
9=
165648-17
tWL
Power-Up Reset Waveform
PALCE22V10 Family
2-311
~AMD
TYPICAL THERMAL CHARACTERISTICS
PALCE22V10/4 (PALCE22V10H-15)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ
PLCC
Unit
Sjc
Thermal impedance, junction to case
15
16
Sja
Thermal impedance, junction to ambient
72
54
200 Ifpm air
67
49
400 Ifpm air
60
43
600 Ifpm air
53
37
800 Ifpm air
46
31
°elW
°elW
°elW
°elW
°elW
°elW
Sjma
Parameter Description
Thermal impedance, junction to ambient with air flow
SKINNYDIP
PALCE22V10/5 {PALCE22V1OH-10)
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ
PLCC
Unit
Sjc
Thermal impedance, junction to case
20
18
Sja
Thermal impedance, junction to ambient
73
55
°elW
°elW
°elW
°elW
°elW
°elW
Sjma
Parameter Description
Thermal impedance, junction to ambient with air flow
SKINNYDIP
200 Ifpm air
66
48
400 Ifpm air
61
43
600 Ifpm air
55
40
800 Ifpm air
52
37
Plastic Sic Considerations
The data listed for plastic Sjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the Ojc measurement relativo to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, Sjc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a siml7ar environment.
2·312
PALCE22V10 Family
_
COM'L:-25
~
INO: -15/25
PALCE22V10Z Family
Zero-Power 24-Pin EE CMOS Versatile PAL Device
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
Zero-power CMOS technology
- 15 ~ standby current
- As fast as 15 ns first-access propagation delay
and 50 MHz fMAX (external)
•
10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
•
•
Unused product term disable for reduced power
consumption
Varied product term distribution allows up to 16
product terms per output for complex functions
•
•
Available In Industrial operating range
- Tc = -40°C to +85°C
- Vee = +4.5 V to +5.5 V
Global asynchronous reset and synchronous
preset for Initialization
•
Power-up reset for Initialization and register
preload for testability
•
HC- and HCr-compatible Inputs and outputs
•
•
Electrically-erasable technology provides
reconfigurable logic and full testability
Extensive third-party software and programmer
support through FusionPLO partners
•
24-pln SKINNYOIP and 28-pln PLCC packages
save space
GENERAL DESCRIPTION
The PALCE22V10Z is an advanced PAL device built
with zero-power, high-speed, electrically-erasable
CMOS technology .It provides user-programmable logiC
for replacing conventional zero-power CMOS SSIIMSI
gates and flip-flops at a reduced chip count.
the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active
high or active low. The output configuration is determined by two bits controlling two multiplexers in each
macrocell.
The PALCE22V10Z provides zero standby power and
high speed. At 15 ~ maximum standby current, the
PALCE22V1 OZ allows battery powered operation for an
extended period.
AMD's FusionPLD program allows PALCE22V10Z designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensu ring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces deSign time since a designer can use a
tool that is already installed and familiar. Please refer to
the Software Reference Guide to PLD Compliers for
certified development systems, and the Programmer
Reference Guide for approved programmers.
The ZPAL™ device implements the familiar Boolean
logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 t016 across the outputs
(see Block Diagram). The OR sum of the products feeds
Publication# 15700 Rev.
Issue Date: June 1993
e
Amendment/O
2-313
~AMD
BLOCK DIAGRAM
11·111
CLKllo
15700C-1
CONNECTION DIAGRAMS
Top View
SKINNYDIP/SOIC
0
ClKllo
Vee
11
II0g
12
I/0a
13
14
1/07
1/06
15
16
1/04
17
1/03
la
1/02
Ig
110
1/00
GND
PLCC
1105
~
~-=-d
1/06
1105
NC
1/04
1/03
1/02
1/01
-
0'10 Cl
..-
= Ground
= Input
= Input/Output
= No Connect
= Supply Voltage
PALCE22V10Z Family
0
..-
0
..-
z z -=-~~
"
111
PIN DESCRIPTION
ClK = Clock
2-314
1/07
24
23
22
21
20
16
17
18
Pin 1 is marked for orientation.
Vee
CX)
;:::,
NC
Note:
NC
0'1
Z>;:::,
13
14
15
15700C-2
GND
I
I/O
o
000 0
15700C-3
AMOl1
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of these elements:
_______T...JAL
~.§ ~~ _V,.- 10
Z -15
FAMILY TYPE
PAL = Programmable Array Logic
P
I
l
OPERATING CONDITIONS
I = Industrial (-40 oC to +85°C)
C = Commercial (OOC to +75°C)
TECHNOLOGY-------~
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
S = 24-Pin Plastic Gull-Wing
Small Outline Package
(SO 24)
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE _ _ _ _ _ _ _ _ _ _....J
V = Versatile
NUMBER OF OUTPUTS
POWER _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J
SPEED
-15 = 15 ns tPD
-25 = 25 ns tPD
Z = Zero Power (15 J,LA Icc standby)
Valid Combinations
PALCE22V1 OZ-15
PI,JI, SI,
PALCE22V10Z-25
PC,JC, SC,
PI,JI, SI
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
PALCE22V10Z-15/25 (Com'I, INO)
2-315
~AMD
FUNCTIONAL DESCRIPTION
The PALCE22V10Z is the zero-power version of the
PALCE22V10. It has all the architectural features of the
PALCE22V10. In addition, the PALCE22V1 OZ has zero
standby power and unused product term disable.
The PALCE22V10Z allows the systems engineer to implement the design on-chip, by programming EE cells to
configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required
time-consuming layout, are lifted from the PC board and
placed on Silicon, where they can be easily modified during prototyping or production.
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state.
The PALCE22V10Z has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output configurations; registered output
or combinatorial I/O, active high or active low (see
Figure 2). The configuration choice is made according
to the user's design specification and corresponding
programming of the configuration bits 80-81. Multiplexer controls are connected to ground (0) through a
programmable bit, selecting the "0" path through the
multiplexer. Erasing the bit disconnects the control line
from GND and it floats to Vcc (1), selecting the "1" path.
The device is produced with a EE cell link at each input
to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the
circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to
any customized pattern.
Variable Input/Output Pin Ratio
The PALCE22V10Z has twelve dedicated input lines,
and each macrocell output can be an I/O pin. Buffers for
device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vcc or GND.
Registered Output Configuration
Each macrocell of the PALCE22V1 OZ includes aD-type
flip-flop for data storage and synchronization. The flipflop is loaded on the LOW-to-HIGH transition of the
clock input. In the registered configuration (81 = 0), the
array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(81 = 1). In the combinatorial configuration the feedback
is from the pin.
1---~"""x)4-~~ I/On
Output Configuration
So
So
o
o
o
Registered/Active Low
o
Combinatorial/Active Low
1
Combinatorial/Active High
Registered/Active High
o = Programmed EE bit
1 = Erased (charged) EE bit
1S700C-4
Figure 1. Output Lagle Macrocell
2-316
PALCE22V10Z Family
AMD~
Combinatorial/Active Low
Registered/Active Low
Combinatorial/Active High
Registered/Active High
15700C-5
Figure 2. Macrocell Configuration Options
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
_output provides a bidirectional 1/0 pin, and may be configured as a dedicated input if the buffer is always
disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is controlled by programmable bit So in the
output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high (So = 1).
Preset/Reset
For initialization, the PALCE22V10Z has additional
Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous
Preset (SP) product term is asserted high, the output
registers will be loaded with a HIGH on the next LOW-toHIGH clock transition. When the Asynchronous Reset
(AR) product term is asserted high, the output registers
will be immediately loaded with a LOW independent of
the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Zero-Standby Power Mode
The PALCE22V10Z features a zero-standby power
mode. When none of the inputs switch for an extended
period (typically 50 ns). the PALCE22V10Z will go into
standby mode, shutting down most of its internal circuitry. The current will go to almost zero (Icc < 15 J,JA).
The outputs will maintain the states held before the device went into the standby mode.
PALCE22V10Z Family
2-317
~AMD
When any input switches, the internal circuitry is fully enabled and power consumption returns to normal. This
f~ature results in ~nsiderable power savings for operation at low to medium frequencies. This savings is illustrated in the Icc vs. frequency graph.
Product-Term Disable
On a·programmed PALCE22V10Z, any product terms
that are not used are disabled. Power is cut off from
these product terms so that they do not draw current. As
shown in the lee vs. frequency graph, product-term disabling results in considerable power savings. This savings is greater at the higher frequencies.
Further hints on minimizing power consumption can be
found in the Application Note "Minimizing Power Consumption with Zero-Power PLDs."
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PALCE22V10Z will
depend on the programmed output polarity. The Vee
rise must be monotonic and the reset delay time is
1000 ns maximum.
Register Preload
The registers on the PALCE22V10Z can be pre loaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
2-318
Security Bit
After programming and verification, a PALCE22V10Z
design can be secured by programming the security EE
bit. Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. When
the security bit is programmed, the array will read as if
every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of
the entire pattern.
Programming and EraSing
The PALCE22V10Z can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE22V10Z offers a very high level of built-in
quality.
The erasability of the CMOS PALCE22V10Z allows direct testing of the device array to guarantee 100% programming and functional yields.
Technology
The high-speed PALCE22V10Z is fabricated with
AMD's advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven
EE cells. Inputs and outputs are designed to be compatible with HC and HCT devices. This technology provides
strong input-clamp diodes, output slew-rate control, and
a grounded substrate for clean switching.
PALCE22V10Z Family
AMol1
LOGIC DIAGRAM
SKINNYDIP (PLCC) Pinouts
CLKIIO
...
I
(2)
0
I
~I d
IIII
4
~
TI
II
II
I
II
'F
I I'r
16
III
'r
I
2?
I
12?
IIII
2t 2r 2r I 131'
I
I
IIII
3F
I
,35
1, ,3r
J I II
II
4f,
E!I
(28) Vcc
,4r
Afl
II II
~.
o
~
";
~l
o
20
0
15
0 0
0 I
o
";
I
-r,Ql
21
~
~ ~J
OAflg
o
W.
'"
Fr~ll
0
15
I
1J
I II II I I II IIII III
II
L JJ
I I
IIII IIII
49
1
'"
L...!.J
10
~
~
0 OJ
0 I
oARo
15
o
I I
I
11
I
I
~ ~J
o
I I
>98
I I
I I II
I III
I II
I
II
I II
IIII
I
1
JJ
I
11111111
IIII
IIII
IIII
111
I II
I
I
I
I
II
I
II
I
I
11
r Ir
II
I
15
, I
I
11
16
(19)
0 I
~
';"
..
1
~I
1
~::j'
15
(18)
SP~rh ~
I
II
10
L!.J
III
)-
122
17 I
(20)
Fe~
..
o
I
l
U ..
L!.J
121
m
~"
SP~rh ~
0
SP
I I
II
TO
oARo .......
I
r110
18 I
(21)
-
L..!J
I
1
~
SP
82
97
(23)
.".
10
83
19 110 5
..
L...!.J
II
OARg
f6l.
1
~
SP
66
(24)
'\
o
65
20 I
0 OJ
0 I
SP
48
4
(5)
(II)
(251
L...!.J
34
o
8
(10)
21
p
i!.
SP
33
7
(9)
22 I
(26)
..
SP
2
(3)
m
110 9
I
10
5
(6)
2
(27)
~
SP
(4)
1
10
9
~
III
-
>-
130
~
TIl l
~.
14 110 0
(17)
,~
SP
.:l;-
'9
10
(12)
o
I
131
....
11
(13)
GND
ffi---:L
(14)
--
'"
SP
3
4
7
8
II 12
15 16
19 20
23 24
27 28
31
32
35 36
39 40
43
.../131
(;6)
'II
1S700C-6
":;'
PALCE22V10Z Family
2-319
~
AMD
PRE LIM I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Industrial (I) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Operating Case
Temperature (Te) ............ -40°C to +85°C
Supply Voltage with Respect
to Ground ................... -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ........... +4.5 V to +5.5 V
DC Input Voltage .......... -0.5 V to Vee + 0.5 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 1/0 Pin
Voltage
............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current (Te
= 40°C to +85°C)
..... 100 rnA'
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
PRELIMINARY
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
VIN
= VIH or Vil
= Min
Vee
Min
IOH
IOH
=6 rnA
=20 JlA
Max
Unit
3.84
V
Vcc-
V
0.1
VOL
Output LOW Voltage
VIN
= VIH or Vil
IOl
Vee
= Min
= 16 rnA
0.5
V
IOl = 6 rnA
0.33
V
IOl = 20 JlA
0.1
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Vo~age for all Inputs (Notes 1, 2)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1, 2)
IIH
Input HIGH Leakage Current
III
Input LOW Leakage Current
= Vee, Vee = Max (Note 3)
VIN =0 V, Vee =Max (Note 3)
VOUT = Vee, Vee = Max
VIN = VIH or Vil (Note 3)
VOUT =0 V, Vee = Max
VIN = VIH or Vil (Note 3)
VOUT =0.5 V, Vee = Max (Note 4)
f =0 MHz
Outputs Open (lOUT =0 rnA)
f = 25 MHz
Vee = Max
IOZH
Off-State Output Leakage
Current HIGH
IOZl
Off-State Output Leakage
Current LOW
Isc
Output Short-Circuit Current
Icc
Supply Current
V
2.0
VIN
0.9
V
10
10
JlA
JlA
JlA
-10
JlA
-150
rnA
-10
-30
15
JlA
90
rnA
Notes:
1.
2.
3.
4.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Represents the worst case of HC and HCT standards, allowing compatibility with either.
110 pin leakage is the worst case of IJL and IOZL (or IJH and IOZH).
Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-320
PALCE22V10Z-15 (INO)
AMO~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Condition
Input Capacitance
VIN
Output Capacitance
VOUT
= 2.0 V
= 2.0 V
Typ
= 5.0 V
TA = 25°C
f = 1 MHz
Unit
5
Vee
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
PRELIMINARY
Parameter
Symbol
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback or SP to Clock
10
tH
Hold Time
0
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
tARW
Asynchronous Reset Width
Max
Unit
15
ns
ns
ns
10
ns
20
ns
15
ns
tARR
Asynchronous Reset Recovery Time
10
ns
tSPR
Synchronous Preset Recovery Time
10
ns
tWL
Clock Width
LOW
8
ns
HIGH
8
ns
50
MHz
tWH
fMAX
Maximum
Frequency
(Note 3)
External Feedback
I
1/(ts + teo)
Internal Feedback (br)
No Feedback
I
1/(twH + tWL)
58.8
MHz
62.5
MHz
tEA
Input to Output Enable Using Product Term Control
15
ns
tER
Input to Output Disable Using Product Term Control
15
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE22V10Z-15 (INO)
2-321
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to + 150°C
Commercial (C) DevIces
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . .. -55°C to + 125°C
Supply Voltage with Respect
to Ground .................... -0.5 V to +7.0 V
Ambient Temperature (TA) ....... O°C to +75°C
Supply Voltage (Vcc) with
Respect to Ground ......... +4.75 V to +5.25 V
Industrial (I) DevIces
DC Input Voltage .......... -0.5 V to Vcc + 0.5 V
Operating Case
Temperature (Tc) ............ -40°C to +85°C
DC Output or I/O Pin
Voltage .................. -0.5 V to Vcc + 0.5 V
Static Discharge Voltage ................. 2001. V
Latchup Current (Tc
=-40°C to +85°C)
.... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Supply Voltage (Vee) with
Respect to Ground ........... +4.5 V to +5.5 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
VOH
VOL
Parameter Description
Test Conditions
Output HIGH Voltage
VIN = VIH or Vil
IOH = 6 rnA
3.84
V
Vee = Min
IOH = 20 JlA
Vee0.1
V
VIN = VIH or Vil
IOL = 16 rnA
0.5
V
Vee = Min
IOl = 6 rnA
0.33
V
IOl = 20 JlA
0.1
V
Output LOW Voltage
Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1, 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1, 2)
IIH
Input HIGH Leakage Current
ilL
IOZH
lozl
Max
2.0
Unit
V
0.9
V
VIN = Vec, Vec = Max (Note 3)
10
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 3)
-10
Off-State Output Leakage
VOUT = Vee, Vee = Max
10
JlA
JlA
JlA
Current HIGH
VIN = VIH or Vil (Note 3)
Off-State Output Leakage
VOUT = 0 V, Vec = Max
-10
JlA
Current LOW
VIN = VIH or Vil (Note 3)
-150
rnA
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vec = Max (Note 4)
lec
Supply Current
Outputs Open (lOUT = 0 rnA)
f = 0 MHz
-30
15
JlA
Vee = Max
f=25MHz
120
rnA
Notes:
1.
2.
3.
4.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Represents the worst case of HC and HCT standards, allowing compatibility with either.
110 pin leakage is the worst case of flL and IOZL (or flH and IOZH).
Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-322
PALCE22V10Z-25 (Com'l, IND)
AMO~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Typ
Parameter Description
Test Condition
Input Capacitance
VIN = 2.0 V
Vee = 5.0 V
5
VOUT = 2.0 V
TA = 25°C
f = 1 MHz
8
Output Capacitance
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol
Min
Parameter Description
tpo
Input or Feedback to Combinatorial Output (Note 3)
ts
Setup Time from Input. Feedback or SP to Clock
15
0
tH
Hold Time
teo
Clock to Output
tAR
Asynchronous Reset to Registered Output
Max
Unit
25
ns
ns
ns
15
ns
25
ns
tARW
Asynchronous Reset Width
25
ns
tARR
Asynchronous Reset Recovery Time
25
ns
tSPR
Synchronous Preset Recovery Time
25
ns
tWL
Clock Width
LOW
10
ns
HIGH
10
ns
33.3
MHz
35.7
MHz
tWH
fMAX
Maximum
Frequency
(Note 4)
External Feedback
I
1/(ts + teo)
Internal Feedback (fCNT)
No Feedback
I
1/(twH + tWL)
50
MHz
tEA
Input to Output Enable Using Product Term Control
25
ns
tER
Input to Output Disable Using Product Term Control
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tpo will typically be 5 ns faster.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
PALCE22V10Z-25 (Com'l, INO)
2-323
~AMD
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
-~-vr
15700C-7
15700C-8
Combinatorial Output
Registered Output
Input
_ _ _-..I
tER
Clock
Output
tEA
_ _ _ _--L...6-I.-1
15700C-10
15700C-9
Input to Output Disable/Enable
Clock Width
Input
Input
Asserting
Asynchronous
Reset
Assertirig~
Synchronous
Preset
_ _ _ __
ts
Registered
Output _ _ _"""-liI~"""'JI
Clock
_ _ _ _ _ _..J
tARR
Clock
Vr
Registered
Output
_____
~~~t.co-v-r---1S700C-12
15700C-11
. Asynchronous Reset
Synchronous Preset
Notes:
1. Vr = 1.5 V for Input Signals and 2.5 V for Output Signals.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns-5 ns typical.
2-324
PALCE22V10Z Family
AMD~
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
IIIZI
May
Change
from L to H
Will be
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
xxxxxx
Does Not
Apply
Changing
from H to L
Changing
from L to H
Center
Line is High. Impedance
"Off" State
KSOOOO 1O-PAL
SWITCHING TEST CIRCUIT
Output
Test Point
1-.
Specification
tPD, teo
tEA
tER
51
S2
52
Closed
Closed
Z~H:Open
Z~
Z~
Z ~L:Open
L: Closed
H ~Z: Open
L ~Z: Closed
H: Closed
H ~Z: Closed
L ~Z:Open
15700C-13
CL
R1
R2
30 pF
820n
820n
Measured
Output Value
2.5V
5 pF
PALCE22V10Z Family
2.5 V
H ~ Z: VOH - 0.5 V
L ~ Z: VOL + 0.5 V
2·325
~AMD
TYPICAL Icc CHARACTERISTICS FOR THE PALCE22V10Z-25
Vee = 5.0 V, TA = 25°C
110
90
70
50
30
Icc (mA)
10
0.1
0.Q1
0.1k
1k
10k
100k
1M
10M
30M
50M
Frequency (Hz)
15700C-15
·Percent of product terms used.
Icc vs. Frequency
Graph for the PALCE22V10Z·25
2·326
PALCE22V10Z·25
AMD~
ENDURANCE CHARACTERISTICS
The PALCE22V10Z is manufactured using AMO's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
Endurance Characteristics
Symbol
tOR
N
Parameter
Test Conditions
Min Pattern Data Retention Time
Max Storage Temperature
Min
Unit
10
Years
Max Operating Temperature
20
Years
Min Reprogramming Cycles
Normal Programming Conditions
100
Cycles
ROBUSTNESS FEATURES
The PALCE22V10Z has some unique features that
make it extremely robust, especially when operating in
high speed design environments. Input clamping
circuitry limits negative overshoot, eliminating the possi-
bility of false clocking caused by subsequent ringing. A
special noise filter makes the programming circuitry
completely insensitive to any positive overshoot that
has a pulse width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vcc
I
I
I
I
I
ESD
Input
Protection Transition
and
Detection
Clamping
I
Programming =~~s~~___ _
Typical Input
1
Preload
Circuitry
Feedback Input
Input Transition
Detection
Typical Output
15700C-16
PALCE22V10Z Family
2-327
~AMD
POWER-UP RESET FOR THE PALCE22V10Z-15
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Vee can rise to its steady state, two conditions are
Parameter
Symbol
required to ensure a valid power-up reset. These conditions are:
•
The Vee rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
ts
Input or Feedback Setup Time
twL
See Switching
Characteristics
Clock Width LOW
Power
Registered
Active-Low
Output
4Vf
--'114--'··-
Vcc
tPR
-7--"~
Clock
15700C-18
Power-Up Reset Waveform
2-328
PALCE22V10Z-15
AMD~
POWER-UP RESET FOR THE PALCE22V10Z-25
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Vee can rise to its steady state, four conditions are
required to ensure a valid power-up reset. These conditions are:
Parameter
Symbol
tPR
•
The supply voltage prior to the Vee rise must not
exceed Vee off.
•
The Vcc rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
•
If inputs are not switching at the time of power-up,
an input transition must take place to assure proper
data is set-up in registers or to outputs.
Parameter Description
Max
Unit
Power-Up Reset Time
1000
ns
Input or Feedback Setup Time
ts
twL
See Switching
Characteristics
Clock Width LOW
Vee Off
Supply Voltage Prior to Power-Up
mV
100
Vec
Power
______4_V{ VccOff
Registered
Active-Low
Output
Clock
15700C-19
Power-Up Reset Waveform
PALCE22V10Z-25
2-329
~
AMD
?I
2·330
GL'.
Devices
~
PALL V22V1 OZ-25
Low-Voltage, Zero-Power 24-Pin EE CMOS Versatile
PAL Device
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
Low-voltage operation, 3.3 V JEDEC
compatible
Zero-power CMOS technology
- 15 J..LA standby current
- 25 ns first-access propagation delay
Unused product term disable for reduced
power consumption
Industrial operating temperature range
- Tc =-40°C to +85°C
3.3 V (CMOS) and 5 V (CMOS and TTL)compatible inputs and I/O
Electrically-erasable technology provides
reconfigurable logic and full testability
•
•
•
•
•
•
10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to
16 product terms per output for complex
functions
Global asynchronous reset and synchronous
preset for Initialization
Power-up reset for Initialization and register
preload for testability
ExtenSive third-party software and programmer
support through FusionPLD partners
24-pin SKINNYDIP, 24-pin SOIC and 28-pin
PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10Z is an advanced PAL device built
with low-voltage, zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zero-power
CMOS SSI/MSI gates and flip-flops at a reduced chlp
count.
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active
high or active low. The output configuration is determined by two bits controlling two multiplexers in each
macrocell.
The PALLV22V1 OZ provides high speed at low voltage
and zero standby power. At 15 J..LA maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
AMD's FusionPLD program allows PALLV22V10Z designs to be implemented using a wide variety of popular
industry-standard deSign tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring thatthirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the Software Reference Guide to PLD Compliers for
certified development systems, and the Programmer
Reference Guide for approved programmers.
The ZPAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AN D array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 t016 across the outputs
Publication# 17661
Rev. A
Amendment/O
L..;1.;..;ss.;..;ue;...;D;;.;;a;,;.;;te..;..:..;..Fe;.;;b.;.;ru;.;;;ary~19;.;;9.;;..3_ _ _ _....J
This document contains information on a product under development at Advanced Micro Devices. Inc. The
~~~r:ifh~si~~=:~ ~~~~~ ~~h~~:~~~c:~ this product. AMD reserves the
right to change or discontinue
2-331
~
PRELIMINARY
AMD
BLOCK DIAGRAM
II -111
CLKllo
Programmable AND Array
(44 x 132)
17661A-1
CONNECTION DIAGRAMS
Top View
SKINNYDIP/SOIC
CLKllo
Vee
11
II0g
12
II0s
13
1/07
14
1/05
16
1/04
17
1/03
Is
1/02
Ig
1/01
110
1/00
Note:
Pin 1 is marked for orientation_
o
~
NC
Clock
Ground
Input
Input/Output
No Connect
Vee
Supply Voltage
GND
I
I/O
2-332
OJ
ex>
1/07
24
1/06
23
1/05
NC
1/04
1/03
1/02
22
21
111
17661A-3
17661A-2
PIN DESCRIPTION
ClK
()
~=d~~~~
1/06
15
GND
PLCC
PALLV22V10Z-25
AMD~
PRELIMINARY
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of these elements:
-
PAL LV 22
V
10 Z -25
P
I
L
_______T-' -- -- -FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY------------~
OPERATING CONDITIONS
I
= Industrial (-40°C to +85°C)
PACKAGE TYPE
LV = Low-Voltage
V = Versatile
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
S = 24-Pin Plastic Gull-Wing
Small Outline Package
(SO 024)
NUMBER OF OUTPUTS
SPEED
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE -----------~
-25 = 25 ns tPD
POWER --------------------------------'
Z
= Zero Power (15 JlA Icc standby)
Valid Combinations
PALLV22V10Z-25
PI,JI, SI
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
PALLV22V10Z-25 (IND)
2-333
~
AMD
PRELIMINARY
FUNCTIONAL DESCRIPTION
The PALLV22V10Z is the low-voltage, zero-power version of the PALCE22V1 O. It has all the architectural features of the PALCE22V10. In addition, the
PALLV22V10Z has zero standby power and unused
product term disable.
The PALLV22V10Z allows the systems engineer to implement the design on-chip, by programming EE cells to
configure AND and OR gates within the device, according to the desired logic function. Complex interconnec~
tions between gates, which previously required
time-consuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified during prototyping or production.
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state.
The PALL V22V1 OZ has 12 inputs and 10 1/0 macrocells. The macrocell (Figure 1) allows one of fou r potential output configurations; registered output or
combinatorial 1/0, active high or active low (see Figure
2). The configuration choice is made according to the
user's design specification and corresponding programming of the configuration bits 80 - 81. Multiplexer controls are connected to ground (0) through. a
programmable bit, selecting the "0" path through the
multiplexer. Erasing the bit disconnects the control line
from GND and it floats to Vee (1), selecting the "1" path.
The device is produced with a EE cell link at each input
to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the
circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to
any customized pattern.
Variable Input/Output Pin Ratio
The PALLV22V10Z has twelve dedicated input lines,
and eaeh macrocell output can be an 1/0 pin. Buffers for
device inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to Vee or GND.
Reg.istered Output Configuration
Each macrocell of the PALLV22V1 OZ includes aD-type
flip-flop for data storage and synchronization. The flipflop is loaded on the LOW-to-HIGH transition of the
clock input. In the registered configuration (81 = 0), the
array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(81 = 1). In the combinatorial configuration the feedback
is from the pin.
I/On
Sl
So
0
0
Output Configuration
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
Combinatorial/Active High
o = Programmed EE bit
1 = Erased (charged) EE bit
17661A-4
Figure 1. Output Logic Macrocell
2-334
PALLV22V10Z-25
AMD~
PRELIMINARY
Combinatorial/Active Low
Registered/Active Low
Combinatorial/Active High
Registered/Active High
17661A-5
Figure 2. Macrocell Configuration Options
Programmable Three-State Outputs
Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always
disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is controlled by programmable bit So in the
output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high (So = 1).
Preset/Reset
For initialization, the PALLV22V10Z has additional
Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous
Preset (SP) product term is asserted high, the output
registers will be loaded with a HIGH on the next LOW-toHIGH clock transition. When the Asynchronous Reset
(AR) product term is asserted high, the output registers
will be immediately loaded with a LOW independent of
the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Benefits of Lower Operating Voltage
The PALL V22V1 OZ has an operating voltage range of
3.0 V to 3.6 V. Low voltage allows for lower operating
power consumption, longer battery life, and/or smaller
batteries for notebook applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V
significantly reduces power consumption. This directly
translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce
the size and weight of the battery. Thus, 3.3 V designs
facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and provides a less hostile environment for board design. Lower
operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
PALLV22V10Z·25
2·335
~
AMD
PRELIMINARY
zero-Standby Power Mode
Register Preload
The PALLV22V10Z features a zero-standby power
mode. When none of the inputs switch for an extended
period (typically 30 ns), the PALLV22V10Z will go into
standby mode, shutting down most of its internal circuitry. The current will go to almost zero (Icc < 15 JJ.A).
The outputs will maintain the states held before the device went into the standby mode.
The registers on the PALLV22V10Z can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to
cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can
be verified by loading illegal states and observing proper
recovery.
If a macrocell is used in registered mode, switching pin
ClK/lo will not affect standby mode status for that macrocell. If a macrocell is used in combinatorial mode,
switching pin CLK/lo will affect standby mode status for
that macrocell.
This feature reduces dynamic Icc proportional to the
number of registered macrocells used. If all macrocells
are used as registers, and only ClK/lo is switching, the
device will not be in standby mode but dynamic Icc will
typically be <2 mA. This is because only the ClK/lo
buffer will draw current.
When any input switches, the internal circuitry is fully enabled and power consumption returns to normal. This
feature results in considerable power savings for operation at low to medium frequencies.
Product-Term Disable
On a programmed PALLV22V10Z, any product terms
that are not used are disabled. Power is cut off from
these product terms so that they do not draw current.
Product-term disabling" results in considerable power
savings. This savings is greater at the higher
frequencies.
Further hints on minimizing power consumption can be
found in the Application Note "Minimizing Power Consumption with Zero-Power PLOs."
3.3 V (CMOS) and 5 V (CMOS and TTL)Compatible Inputs and 1/0
Input voltages can be at TTL levels without the device
drawing more current than true 3.3 V CMOS levels. Additionally, the PALLV22V1 OZ can be driven with true 5 V
CMOS levels due to special input and I/O buffer
circuitry.
Security Bit
After programming and verification, a PALLV22V10Z
design can be secured by programming the security EE
bit. Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. When
the security bit is programmed, the array will read as if
every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of
the entire pattern.
Programming and Erasing
The PAlLV22V10Z can be programmed on standard
logiC programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No'special erase operation is required.
Quality and Testability
The PAlLV22V10Z offers a very high level of built-in
quality.
The erasability of the CMOS PALLV22V10Z allows direct testing of the device array to guarantee 100% programming and functional yields.
Technology
The high-speed PALLV22V10Z is fabricated with
AMO's advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven
EE cells. Inputs and outputs are designed to be 3.3 and
5 V device compatible. This technology provides strong
input-clamp diodes, output slew-rate control, and a
grounded substrate for clean switching.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PALLV22V10Z will
depend on the programmed output polarity. The Vcc
rise must be monotonic and the reset delay time is
1000 ns maximum.
2-336
PALLV22V10Z-25
AMD~
PRELIMINARY
LOGIC DIAGRAM
SKINNYDIP (PLCC) Pinouts
CLKIIO
W
1°1l_ _ _ _ _
5=t1§~~ARQWfll1~
J' 21108
~~
20
mI1:2}--Ci!l:::::t:t:t~U +t=f::!±i::i:f±I:::t:f±I::t:f±I=t::t:t:I=t::t:t:I=t:~=t:~=t:~=::!I2--ttlr--i ~
(3)
12
(26)
-=
m(4)
49
16
ill
(9)
110
18
m(11)
-@IIO O
130
19
(17)
1m-
(12)
-
P----""
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31
32
35 36
39 40
..Ii3II 11
(16)
43
17661A-6
PALLV22V10Z·25
2·337
~
AMD
PRE LIM I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature .......... -65°C to +150°C
Industrial (I) Devices
Ambient Temperature with
Power Applied ................ -55°C to +125°C
Operating Case
Temperature (Te) ............ -4O°C to +85°C
Supply Voltage with Respect
to Ground .................... -0.5 V to +7.0 V
Supply Voltage (Vee) with
Respect to Ground ........... +3.0 V to +3.6 V
DC Input Voltage .............. -0.5'V to +5.5 V
DC Output or 1/0 Pin Voltage ..... -0.5 V to +5.5 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage .................. 2001 V
Latchup Current (Te
=-4O°C to +85°C)
.... 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
PRELIMINARY
Parameter
Symbol
VOH
VOL
Parameter Description
Test Conditions
Output HIGH Voltage
VIN = VIH or Vil
IOH =-2 rnA
2.4
V
Vee = Min
IOH = 100 IlA
Vee0.1
V
Output LOW Voltage
VIN = VIH or Vil
Min
Max
Unit
IOl = 2 rnA
0.4
V
IOl = 100 IlA
0.1
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH 2.0
Voltage for all Inputs (Note 1)
5.5
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = Vee, Vee = Max
10
jlA
III
Input LOW Leakage Current
VIN = 0 V, Vee = Max
-10
jlA
Off-State Output Leakage
VOUT = Vee, Vee = Max
10
jlA
Current HIGH
VIN = VIH or Vil (Note 2)
Off-State Output Leakage
VOUT = 0 V, Vee = Max
-10
jlA
Current LOW
VIN = VIH or Vil (Note 2)
-75
rnA
IOZH
IOZl
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
Outputs Open (lOUT = 0 rnA)
f = 0 MHz
-15
15
jlA
Vec= Max
f = 25 MHz
55
rnA
Notes:
1. These are absolute values with respect to device· ground and all overshoots due to system or tester noise are inCluded.
2. 110 pin leakage is the worst case of hL and IOZL (or hH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-338
PALLV22V10Z-25 (IND)
AMO~
PRELIMINARY
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Typ
Parameter Description
Test Condition
Input Capacitance
VIN = 2.0 V
Vee = 3.3 V
5
Output Capacitance
VOUT .. 2.0 V
TA = 25°C
f = 1 MHz
8
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
PRELIMINARY
Parameter
Symbol
Min
Parameter Description
tPD
Input or Feedback to Combinatorial Output (Note 3)
ts
Setup Time from Input, Feedback or SP to Clock
15
tH
Hold Time
0
Max
Unit
25
ns
ns
ns
teo
Clock to Output
15
ns
tAR
Asynchronous Reset to Registered Output
25
ns
tARw
Asynchronous Reset Width
25
ns
tARR
Asynchronous Reset Recovery Time
25
ns
tSPR
Synchronous Preset Recovery Time
25
ns
10
ns
tWL
Clock Width
tWH
fMAX
LOW
HIGH
Maximum
Frequency
(Note 4)
External Feedback
I
1/(ts
+ teo)
Internal Feedback (feNT)
No Feedback
I
1/(twH
+ tWl)
10
ns
33.3
MHz
35.7
MHz
50
MHz
tEA
Input to Output Enable Using Product Term Control
25
ns
tER
Input to Output Disable Using Product Term Control
25
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tpo may be slightly faster.
4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
PALLV22V10Z·25 (INO)
2·339
~
PRELIMINARY
AMD
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
-~-VT
17661A-7
17661A-8
Registered Output
Combinatorial Output
Input
tER
Clock
tEA
Output
------'-J.-I.-1
17661A-10
17661A-9
Input to Output Disable/Enable
Clock Width
Input
Input
Asserting
Asynchronous
Reset
Asserting=f
Synchronous
Preset
_ _ _ __
t5
Registered
Output _ _ _"--11~...¥...x
Clock
tARR
Clock
VT
Registered
Output
------...1
------~xXxx1tco VT
,-----"--_____
17661A-11
Asynchronous Reset
Synchronous Preset
Notes:
1. Vr = 1.5 V for Input Signals and 1.65 V for Output Signals.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns - 5 ns typical.
2-340
17661A-12
PALLV22V10Z-25
AMD~
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/77//
May
Change
from L to H
Will be
Changing
from L to H
XXXXXX
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
J])(K
Does Not
Apply
Center
Line is HighImpedance
"Off" State
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
3.3 V
Output O - -.....- - -....-~J Test Point
17661A-13
Measured
Specification
tPD, teo
tEA
CL
R1
R2
Output Value
H: Closed
L: Open
30 pF
1.6Kn
1.6Kn
1.65 V
H ~Z: Closed
5 pF
Closed
Closed
Z~
Z~
Z~
tER
52
51
H: Open
L: Closed
H ~Z: Open
L
~Z:
Closed
Z
~
1.65 V
L~Z:Open
PALLV22V10Z-25
H ~ Z: VOH - 0.5 V
L ~Z: VOL + 0.5 V
2-341
~
PRELIMINARY
AMD
ENDURANCE CHARACTERISTICS
The PALLV22V10Z is manufactured using AMO's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
Parameter
Test Conditions
tOR
Min Pattern Data Retention Time
Max Storage Temperature
Min
Unit
10
Years
Max Operating Temperature
20
Years
N
Min Reprogramming Cycles
Normal Programming Conditions
100
Cycles
ROBUSTNESS FEATURES
The PALLV22V10Z-25 has some unique features that
make it extremely robust, especially when operating in
high speed design environments. Input clamping
circuitry limits negative overshoot, eliminating the possi-
bility of false clocking caused by subsequent ringing. A
special noise filter makes the programming circuitry
completely insensitive to any· positive overshoot that
has a pulse width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
I
I
I
I
I
ESD
Input
Protection Transition
and
Detection
Clamping
IProgramming
'='
~~s~~___ _
Typical Input
1
Preload
Circuitry
Feedback Input
Input Transition
Detection
Typical Output
17661A-16
2-342
PALLV22V10Z-25
AMD~
PRELIMINARY
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Vcc can rise to its steady state, two conditions are reParameter
Symbol
quired to ensure a valid power-up reset. These conditions are:
•
The Vcc rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
ts
Input or Feedback Setup Time
See Switching
Characteristics
Clock Width LOW
tWL
Vcc
Power
Registered
Active-Low
Output
Clock
2.7VT
'~...L..I-_- tPR
~
ZI
st
tWL
17661A-17
Power-Up Reset Waveform
PALLV22V10Z-25
2-343
~
AMD
~AL'· Devices .
~~
2-344
_
~
COM'L: H-15/25
Advanced
Micro
Devices
PALCE24V10H-15/25
EE CMOS 28-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
&I High speed CMOS technology
- 15 ns propagation delay for "-15" version
- 25 ns propagation delay for "-25" version
• Outputs Individually programmable as
registered or combinatorial
• Programmable output polarity
•
•
Iii
•
•
•
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 28-pin plastic SKINNYDIP and
PLCC packages
Extensive third-party support through
FusionPLD partners
Fully tested for 100% programming and
functional yields and high reliability
GENERAL DESCRIPTION
The PALCE24V1 0 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture.
grammed as registered or combinatorial with an activehigh or active-low output. The output configuration is
determined by two global bits and one local bit controlling four multiplexers in each macrocell.
The PALCE24V10 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased
electrically.
AMD's FusionPLD program allows PALCE24V10 designs to be implemented using a wide a variety of popular industry-standard design tools. By working closely
with the FusionPLD partners, AMD certifies that the
tools provide accurate, quality support. By ensuring that
third-party tools are available, costs are lowered because a designer does not have to buy a complete set of
new tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be pro-
CLK/lo
BLOCK DIAGRAM
OElI,3
1100
Publication# 12222 Rev. E
Issue Date: Juno 1993
1/0,
AmendmentlO
1/05
1/06
lIDs
II0g
12222E-l
2-345
~
AMD
CONNECTION DIAGRAMS
Top View
PLCC
SKINNYDIP
CLKllo
115
11
114
12
\/09
\/Os
\4
14
\/07
\5
15
\/Ce
Vee
Vee
\6
\7
\s
\9
\/05
16
GND
17
\/04
Is
\/0:3
19
\/02
110
\/01
111
\/00
112
OE/113
Vee
Supply Voltage
2-346
21
20
GND
\/°4
T"'"
C\I
(')
0
.C\I
~~~~OOO
-I~
::. ::. ::.
12222E-3
PIN DESIGNATIONS
OE
22
\/°3
o
Note:
Pin 1 is marked for orientation.
Clock
Ground
Input
InpuVOutput
Output Enable
\/Os
\/°7
\/°6
\/05
23
8
9
--
12222E-2
ClK
GND
I
I/O
25
24
PALCE24V10H-15/25
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
FAMILYTYPE
CE
24 V10H-15P C
-_T----I-~ --
PAL= Programmable Array Logic
1L
TECHNOLOGY - - CE = CMOS Electrically Erasable
OPERATING CONDITIONS
C = Commercial (DOC to +75°C)
PACKAGE TYPE
P = 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
NUMBER OF - - - - - - - - - - '
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF FLIP-FLOPS - - - - - - - - '
POWER-------------~
H = Half Power (115 mA Icc)
SPEED
-15
15 ns tPD
-25 = 25 ns tPD
Valid Combinations
PALCE24V10H-15
PALCE24V10H-25
I
I
PC,JC
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE24V10H-15/25 (Com'l)
2-347
~
AMD
FUNCTIONAL DESCRIPTION
The PALCE24V10 is a universal PAL device. It has ten
independently configurable macrocells (MCo .. MCg).
Each macrocell can be configured as a registered output, combinatorial output, combinatorial 110, or dedicated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Pins 1 and 15 serve either as array inputs or as
clock (ClK) and output enable (OE) for all flip-flops.
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PAlCE24V10 are
automatically configured from the user's design specification, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
Unused input pins should be tied directly to Vee or GND.
Product terms with all bits unprogrammed (discon-
IIOx
~----~~D
Q~----~
o·t-------+-....,
Macrocells MC1 - MCa
Vee
IIOx
~---~~D
Q~----...
Ot--------+-.......
Macrocells MCa and MCg
From
Adjacent
Pin
12222E-4
PALCE24V10 Macrocell
2-348
PALCE24V10H-15/25
AMD
Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial 110 or dedicated input. In the registered ~tput
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always disabled.
The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO
and SG1) and 20 local bits (SlOo through SLOg and Sl1 0
through SL19). SGO determines whether registers will
be allowed. SG1 determineswhetherthe output buffer is
user-controlled or in a fixed state. Within each macrocell, SlOx, in conjunction with SG1 , selects the configuration of the macrocell and Sl1 xsets the output as either
active low or active high.
The configuration bits work by acting as control inputs
forthe multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and
SlOx are the control signals for all four multiplexers. In
MCo and MCg, SGO is added on the feedback multiplexer.
l1
cause the macrocell is a dedicated output, the feedback
is not used.
Dedicated Input in a Non-Registered
Device
The control bit settings are SGO = 1, SG1 = 0 and SlOx =
'1. The output buffer is disabled. The feedback signal is
the I/O pin.
Combinatorial I/O in a Non-Registered
Device
The control settings are SGO = 1 , SG 1 = 1 , and SlOx = 1.
Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the 110 pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SGO=0,SG1 =1 and SlOx =1.
Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.
Table 1. Macrocell Configurations
These configurations are summarized in table 1 and illustrated in figure 2.
SGO
If the PAlCE24 V1 0 is configured as a combinatorial device, the ClK and OE pins are available as inputs to the
arraL!!. the device is configured with registers, the ClK
and OE pins cannot be used as data inputs.
0
SG1
SLOx
Cell Configuration
Device has registers
0
1
0
1
1
Registered
Output
Combinatorial 1/0
Device has no registers
Registered Output Configuration
The control bit settings are SGO = 0, SG1 = 1 and SlOx =
o. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by Sl1 x. Sl1 x is an input to
the exclusive-OR gate which is the D input to the flipflop. Sl1x is programmed as 1 for inverted output or 0
for non-inverted output. The flip-flop is loaded on the
lOW-to-HIGH transition of ClK. The feedback path is
from Q on the register. The output buffer is enabled by
OE.
Combinatorial Configurations
The PAlCE24V10 has three combinatorial output configurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Dedicated Output in a Non-Registered
Device
1
0
0
1
0
1
Combinatorial
Output
Dedicated Input
1
1
1
Combinatorial 1/0
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is made through a programmable bit Sl1 x
which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1x is a 0
and active low if Sl1 x is a 1.
The control settings are SGO = 1, SG1 = 0, and SlOx = O.
All eight product terms are available to the OR gate. Be-
PAlCE24V10H-15/25
2-349
~
AMD
OE ____________________
OE--------------------~
a
a
Q
Q
Registered Active Low
~
Registered Active High
Combinatorial 110 Active Low
Combinatorial 1/0 Active High
Combinatorial Output Active Low
Combinatorial Output Active High
Dedicated Input
12222E-5
Figure 2. Macrocell Configurations
2-350
PALCE24V10H-15/25
AMD~
Power-Up Reset
Programming and EraSing
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE24V10 depend
on whether they are selected as registered or combinatorial.lf registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.
The PALCE24V10 can be programmed on standard
logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
Register Preload
The register on the PALCE24V10 Series can be
preloaded from the output pins to facilitate functional
testing of complex state machine deSigns. This feature
allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to
reach a desired state. In addition, transitions from illegal
states can be verified by loading illegal states and observing proper recovery.
Security Bit
A security bit is provided on the PALCE24V10 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also
defeated by the security bit. The bit can only be erased
in conjunction with the array during an erase cycle.
The PAL24V1 0 offers a very high level of built-in quality.
The erasability if the device provides a direct means of
verifying performance of all the AC and DC parameters.
In addition, is verifies complete programmability and
functionality of this device to yield the highest programming yields and post-programming function yields in the
industry.
Technology
The high-speed PALCE24V10 is fabricated with AMD's
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong inputclamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Electronic Signature Word
An electronic signature word is provided in the
PALCE24V10. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independent of the security bit.
PALCE24 V1 OH-15/25
2-351
~
AMD
LOGIC DIAGRAM
~M. '~-i~~~~+H~++HH~+H~++HH~+H~++HH++HH~+HH--------------------'
I,
•
-
~'0l-
~
_ _ _-...,
1,9
vcclil--
12222E-6
2-352
PALe E24 V1 OH-15/25
AMD
.
LOGIC DIAGRAM (continued)
"
"
"
.
I
11
.
:II
"
.. ..
l
-
<1
l@-t
II:!!}-
'IT
r: ~~h
....
~~~
.~
",: ~
>tP ~
'IT
>---t'0
~
",:
>tP ~
.....
"
VCe
SGJ .•
Sle~
":; ..
>fl? ~
...
-
'r'
~
en
~
.0
e,
co
~
l
...
>t1?
-
o
0
~l
CO
10
rt
17
a
0
@
-+-
~
"
,.
.,.
-S w,
n
0'
DC
...
Ii=
~,e
0'
l
~
-Gl 10,
r;;
.r:~
.
"....
'1:-.
~~
..
SlO~
so,]
,e
..
20
"
r
D
"....
.;..
l
·
Slo~
so,J
'0
r: ~
~
·
·
;t1
...
---;rnJ
~~h
~
l
-
~
>t1?
~
D
.
~l
a
10
f-t
..
10,
a
.
m
"
0
.n
.5
12222E-6
(concluded)
PALCE24V10H-15/25
2-353
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Commercial (C) Devices
Temperature (TA) Operating
in Free Air ....................... O°C to +75°C
Supply Voltage with
Respect to Ground ............ -0.5 V to + 7.0 V
Supply Voltage (Vee)
with Respect to Ground ........ +4.75 V to +5.25 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage ............ -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current
(TA = O°C to +75°C) .................... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS
over
COMMERCIAL
operating ranges unless otherwise
speciTIe d
Parameter
Symbol
Test Conditions
Parameter Description
Min
Max
2.4
Unit
VOH
Output HIGH Voltage
IOH =-3.2 rnA
Vee = Min
VOL
Output LOW Voltage
IOl = 24 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
hH
Input HIGH Leakage Current
VIN = 5.25 V, Vee = Max (Note 2)
hL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
-10
~
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, Vee = Max
VIN = VIH or VIL (Note 2)
10
IlA
IOZl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 2)
-10
IlA
Ise
Output Short-Circuit Current
Vee = Max VOUT = 0.5 V (Note 3)
-150
rnA
lee
Supply Current
Outputs Open (lOUT = 0 rnA)
Vee = Max, f = 15 MHz
115
rnA
VIN = VIH or Vil
V
0.5
VIN = VIH or Vil
2.0
-30
V
V
0.8
V
10
~
Notes:
1. These are absolute values with respect to devic~ ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of hL and lozL (or I,H and IOZH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-354
PALCE24V10H-15/25 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Descriptions
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT= 2.0 V If = 1 MHz
I Vee = 5.0 V, TA = 25°C,
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
tPD
-15
Parameter Description
Min
Input or Feedback to Combinatorial Output
15
ts
Setup Time from Input or Feedback to Clock 10
tH
Hold Time
teo
twH
Max
25
ns
6
HIGH
External Feedback
1
1/(ts+tcO)
Unit
ns
ns
0
10
LOW
Clock Width
Min
12
0
Clock to Output
tWL
-25
Max
12
8
ns
ns
6
8
ns
50
41.6
MHz
66
50
MHz
fMAX
Maximum
Frequency
(Note 3)
tpzx
OE to Output Enable (Note 3)
15
20
ns
tpxz
OE to Output Disable (Note 3)
15
20
ns
tEA
Input to Output Enable Using Product Term Control
(Note 3)
15
25
ns
tER
Input to Output Disable Using Product Term Control
(Note 3)
15
25
ns
Internal Feedback (feNT)
No Feedback
1
1/(twH+twL)
83.3
62.5
MHz
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE24V10H-15/25 (Com'l)
2-355
~
AMD
SWITCHING WAVEFORMS
Input or
Feedback _ _ _-'" _ _ _ _ _--'
Input or
Feedback
Combinatorial
Output
-~-VT
Clock
VT
__________
Registered
Output _ _ _ _ _ _ __
~tco
VT
12222E-7
12222E-8
Combinatorial Output
Input
Registered Output
_ _ _ _--J
tER
tpzx
tEA
VT
Output
VT
Output
12222E-9
12222E-10
OE to Output Disable/Enable
Input to Output Disable/Enable
Clock
12222E-11
Clock Width
Notes:
1. Vr
= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns-5 ns typical.
2-356
VT
PALCE24V10H-15/25
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
17171
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
xxxxxx
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
Output
( } - - - - 4 I t - - - - - -. .
12222E-12
Specification
CL
S1
tPD, teo
Closed
tpzx, tEA
Z~
Z~
tpXZ,tER
H: Open
L: Closed
H ~Z: Open
R1
R2
Measured
Output Value
1.S V
SO pF
200n
S pF
L~Z:Closed
PALCE24V10H-15/25
390n
1.S V
H ~Z: VOH-O.S V
L~Z: Va.. + O.S V
2-357
~
AMD
ENDURANCE CHARACTERISTICS
parts. As a result, the device can be erased and
reprogrammed-a feature which allows 100% testing at
the factory.
The PALCE24V10 is manufactured using AMD's advanced electrically erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Endurance Characteristics
Symbol
Parameter
Test Conditions
tOR
Min Pattern Data Retention Time
N
Min Reprogramming Cycles
Max Storage Temperature
Min
10
Unit
. Years
Max Operating Temperature
20
100
Cycles
Normal Programming Conditions
Years
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
ESD
ProgramNerify
Protection
Circuitry
- .
Typical Input
Vee
Preload
Circuitry
Feedback
Input
Typical Output
12222E-14
2-358
PALCE24V10H-15/25
AMD~
POWER-UP RESET
The PALCE24V10 has been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization.
A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
Parameter
Symbol
and the wide range of ways Vcc can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
•
•
The Vcc rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Min
Parameter Description
Power-Up Reset Time
tPR
ts
Input or Feedback Setup Time
twL
Registered
Output
Clock-
4?
Unit
ns
See Switching
Characteristics
Clock Width LOW
Power
Max
1000
Vee
-------I~IIIIII._--
tPR
J
71
~
tWL
12222E-15
Power-Up Reset Waveform
PALCE24V10H-15/25
2-359
~
COM'L: H-15/20
_
Advanced
Micro
Devices
PALCE26V12H-15/20
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
28-pln versatile PAL programmable logic
device architecture
Electrically erasable CMOS technology
provides half power (only 105 rnA) at high
speed (15 ns propagation delay)
14 dedicated Inputs and 121nput/output
macrocelis for architectural flexibility
Macrocells can be registered or combinatorial,
and active high or active low
Varied product term distribution allows up to
16 product terms per output
Two clock Inputs for Independent functions
•
•
•
•
•
Global asynchronous reset and synchronous
preset for Initialization
Register preload for testability and built-In
register reset on power-up
Space-efficient 28-pln SKINNYDIP and PLCC
packages
Center Vee and GND pins to Improve signal
characteristics
Extensive third-party software and
programmer support through FusionPLD
partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular
PAL22V10 architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, the
PALCE26V12 offers many unique advantages.
Device logic is automatically configured according to the
user's design specification. Design is simplified by design software, allowing automatic creation of a programming file based on Boolean or state equations. The
software can also be used to verify the design and can
provide test vectors for the programmed device.
The PALCE26V12 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced
to sum-of-products form, taking advantage of the
very wide' input gates available in PAL devices. The
functions are programmed into the device through
electrically-erasable floating-gate cells in the AND logic
array and the macrocells. In the unprogrammed state,
all AND product terms float HIGH. If both true and
complement of any input are connected, the term will be
permanently LOW.
2-360
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be programmed as registered or combinatorial, active high or
active low, with registered 1/0 possible. The flip-flop can
be clocked by one of two clock inputs. The output configuration is determined by four bits controlling three
multiplexers in each macrocell.
AMD's FusionPLD program allows PALCE26V12 designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces deSign time since a designer can use a
tool that is already installed and familiar. Please refer to
the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide
for approved programmers.
Publication# 16072
Rev. C AmendmentlO
Issue Date: June 1993
AMD~
BLOCK DIAGRAM
110 0
VOl
00 2
1104
1103
110 5
VO e
110 7
1106
V0 11
110 10
1109
16072C-1
CONNECTION DIAGRAMS
Top View
SKINNYDIP
CLK1/10
11
12
CLK2I13
PLCC
~
~
1/011
....J
()
1/010
~
.=
'::i
....J
()
0
.2 ~ ~
II0g
14
II0a
15
1/07
Vee
1/06
16
GND
17
1/05
18
1104
Ig
1/03
110
1/02
111
1101
112
1/00
Note:
Pin 1 is marked for orientation.
~
(Y)
113
14
25
1109
15
VCC
24
23
1/07
Is
22
I/0s
17
21
GND
Is
20
1/05
1/04
19
0
1S072C-2
I/0s
.=
(\j
0
(\j
(Y)
g § g g
1S072C-3
PIN DESCRIPTION
ClK
=Cloek
GND = Ground
= Input
liD
= InpuUOutput
Vee
= Supply Voltage
PAlCE26V12H-15/20
2-361
~
AMD
ORDERING INFORMATION
Commercial Products
AMD commercial programmable logic products are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
PAL
FAMILY TYPE
PAL = Programmable Array Logic
T
CE
--
TECHNOLOGY
CE = CMOS Electrically Erasable
26 V 12 H -15
-~
-:-
-- --
P C 14
1L
OPllONAL PROCESSING
Blank = Standard Processing
PROGRAMMING DESIGNATOR
14 = First Revision
(May require programmer
update)
' - - - OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V= Versatile
PACKAGE TYPE
P = 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
NUMBER OF OUTPUTS
POWER
H= Half Power (105 mA Icc)
SPEED
-15=15nstPD
-20 = 20 ns tPD
Valid Combinations
Valid Combinations
PALCE26V12H-15
PALCE26V12H-20
2-362
I PC JC I
I
•
14
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALCE26V12H-15/20 (Com'l)
AMD~
FUNCTIONAL DESCRIPTION
The PALCE26V12 has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or Vcc. Buffers for
device inputs and feedbacks have both true and complementary outputs to provide user-selectable signal
polarity. The inputs drive a programmable AND logic
array, which feeds a fixed OR logic array.
The OR gates feed the twelve liD macrocells (see Figure 1). The macrocell allows one of eight potential output configurations; registered or combinatorial, active
high or active low, with register or 110 pin feedback (see
Figure 2). In addition, registered configurations can be
clocked by either of the two clock inputs.
The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits 80-83 (see Table 1).
Multiplexer controls initially float to Vcc (1) through a
programmable cell, selecting the "1" path through the
multiplexer. Programming the cell connects the control
line to GND (0), selecting the "0" path.
Table 1. Macrocell Configuration Table
S3
1
Sl
0
So
Output Configuration
0
Registered Output and Feedback,
Active Low
1
0
1
Registered Output and Feedback,
Active High
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
S2
Clock Input
1
CLK1/lo
0
CLKVb
Combinatorial I/O, Active Low
Combinatorial I/O, Active High
OE-1~----------------------~
• When 53 = 1 (unprogrammed) the feedback is selected by 5,.
When 53 ~ 0 (programmed). the feedback is the opposite of
that sefected by 5 l'
16072C-4
Figure 1. PALCE26V12 Macrocell
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes aD-type
flip-flop for data storage and synchronization. The flipflop is loaded on the LOW-to-HIGH edge of the selected
clock input. Any macrocell can be configured as combinatorial by selecting a multiplexer path that bypasses
the flip-flop. Bypass is controlled by bit 81.
Programmable Clock
The clock input for any flip-flop can be selected to be
from either pin 1 or pin 4. A 2:1 multiplexer controlled by
bit 82 determines the clock input.
Registered I/O, Active Low
Registered I/O, Active High
Programmable Feedback
Combinatorial Output, Registered
Feedback, Active Low
A 2:1 multiplexer allows the user to determine whether
the macrocell feedback comes from· the flip-flop or
from the liD pin, independent of whether the output is
registered or combinatorial. Thus, registered outputs
may have internal register feedback for higher speed
(fMAX internal), or 1/0 feedback for use of the pin as a
direct input (fMAX external). Combinatorial outputs may
have liD feedback, either for use of the signal in other
equations or for use as another direct input, or register
feedback.
Combinatorial Output, Registered
Feedback, Active High
1 = Unprogrammed EE bit
0= Programmed EE bit
The feedback multiplexer is controlled by the same bit
(81) that controls whether the output is registered or
combinatorial, as on the 22Vl 0, with an additional control bit (83) that allows the alternative feedback path to
be selected. When 83 = 1, 81 selects register feedback
for registered outputs (81 = 0) and liD feedback for
combinatorial outputs (81 = 1). When S3 = 0, the opposite is selected: liD feedback for registered outputs and
register feedback for combinatorial outputs.
PALCE26V12H-15/20
2-363
~
AMD
Programmable Enable and 1/0
Register Preload
Each macrocell has a three-state output buffer controlled by an individual product term. Enable and disable
can be a function of any combination of device inputs or
feedback. The macrocell provides a bidirectional 1/0 pin
if 1/0 feedback is selected, and may be configured as a
dedicated input if the buffer is always disabled. This is
accomplished by connecting all inputs to the enable
term, forcing the AND of the complemented inputs to be
always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (the
unprogrammed state).
The register on the PALCE26V12 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows direct loading of arbitrary states, thereby making it unnecessary to cycle through long test vector sequences to
reach a desired state. In addition, transitions from illegal
states can be verified by loading illegal states and
observing proper recovery.
Programmable Output" Polarity
" The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.
Selection is controlled by programmable bit So in the
output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin definition and output equation have the same polarity, the
output is programmed to be active high.
Security Bit
After programming and verification, a PALCE26V12
design can be secured by programming the security bit.
Once programmed, this bit defeats read back of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. Programming the security bit disables preload, and the
array will read as if every bit is disconnected. The security bit can only be erased in conjunction with erasure of
the entire pattern.
Programming and Erasing
The PALCE26V12 can be programmed on standard
logiC programmers. It also may be erased to reset a
previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Preset/Reset
Quality and Testability
For initialization, the PALCE26V12 has additional
Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous
Preset (SP) product term is asserted high, the output
registers will be loaded with a HIGH or the next LOW-toHIGH clock transition. When the Asynchronous Reset
(AR) product term is asserted high, the output registers
will be immediately loaded with a LOW independent of
the clock.
The PALCE26V12 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest programming yields and post-programming functional
yields in the industry.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
The high-speed PALCE26V12 is fabricated with AM D's
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TIL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system inttialization. Outputs of the PALCE26V12 will
be HIGH or LOW depending on whether the output is
active low or active high, respectively. The Vee rise must
be monotonic, and the reset delay time is 1000 ns
maximum.
2-364
Technology
PALCE26V12H-15/20
AMD~
Registered Active-High Output,
Register Feedback
Registered Active-Low Output,
Register Feedback
Registered Active-High 1/0
Registered Active-Low 1/0
Registered Outputs
Combinatorial Active-High 1/0'
Combinatorial Active-Low 1/0
Combinatorial Active-Low Output,
Register Feedback
Combinatorial Active-High Output,
Register Feedback
16072C-5
Combinatorial Outputs
Figure 2.PALCE26V12 Macrocell Configuration Options
PALCE26V12H-15/20
2-365
~
AMD
LOGIC DIAGRAM
PALCE26V12
...t::::
11::'
I
4
12
II
.. ..
•1
.. ..
41
41
41
__ A5YNCH
-
,RE5ET
28
113
CLK;/1
~~U-r2
-:::
10
..,
..
2
~~
I
~821~1
~1
...
11
~SO'
---
1.
1.
12
-
JTU- ~2
111
~~ ~
01
I!
082I~a~
1.
II
3
sal!
R11-
....
11
~SO'
II
4 ..
m:noW- ~I
4¥~"
.
52
J>
CLK2113
so
~o
42
-
...
J>
5
14
\
91
~Jf~
..
m
92
R.
SO
91
24
10.
I
93'
~i
1,1 11
23
4Lt~D: ,,~I107
9~~Sl
.
17
Is
At
1
..,
6
91
o
1
~93'
.
...
r;o
/,
111
DA~OOH"""-
8
16
..
l'4
.
4t:¥f~."
p
4
I
12
II
2D
.
'"
m
. .. ..
22
10.
I
1
.1
* When S3
= 1 (unprogrammed) the feedback is selected by St.
When S3 = 0 (programmed), the feedback is the opposite of
AR
9
l~
ClK.
93'
21
.GND
that selected by St.
16072C-6
2·355
PALCE26V12H-15/20
AMD~
LOGIC DIAGRAM (continued)
.. . . .
12
11
.
:M
.. PALCE26V12
. . .. .. ..
5P
elK •
..
rTo'"
L
~
....
-
J11
52
'=t..
r
-=-
-51
RS -
ts1
~
..
20
liDs
1
01
~~~.
o
5P
so
.-
~l ~
I~~~
~
o
10
18
..'
.,
r
1
-~
-
...
Ki~~
,
-
0
1
..
.,
~o
..
-
~t~1
01
5P
""'- 52
0
so
I
_ 51
51
-..
Lc..irwW11
6
~~II0
...
....
o
SP
1
so
,-521~~1
\!
51
..
--- ..
..
-
,
,
....
R2
1
~
dIt;J
14
~2
I
51
'30
13
111
01 so
R3 - 51
5P
52
-
~
..
110
~~
o
..
11
12
so
R4 _ 51
51
"'
11
19
5P
52
'=t-
-~~
o
SP
......
-
.A
-
'41
r1o~ ~1 5
~Lc..i~
SYNCH
'"~"r:"
• When 53 = 1 (unprogrammed) the feedback is selected by 51When 53 = 0 (programmed), the feedback is the opposite of
that selected by 51-
so
00
II
521~7
0 Ro - 51
l,L
b-51
16072C-6
(concluded)
PALCE26V12H-1S/20
2-367
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied ................. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air ... " ........ O°C to +75°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
DC Input Voltage. . . . . . . . . . . . . .. -0.6 V to +7.0 V
DC Output or 1/0,
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Static Discharge Voltage ................. 2001 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
10H = -3.2 rnA
VIN = VIH or VIL
Vee = Min
Min
VOL
Output LOW Voltage
10L = 16 rnA
VIN = VIH or VIL
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
VIN = 5.5 V, Vee = Max (Note 2)
IlL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
loZH
Off-State Output Leakage
Current HIGH
VOUT = 5.5 V, Vee = Max
VIN = VIHor VIL (Note 2)
loZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIHor VIL (Note 2)
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
Icc
Supply Current
VIN= 0 V, Outputs Open (loUT = 0 rnA)
Vee = Max
Max
0.4
2.0
-30
Unit
V
2.4
V
V
0.8
V
10
~
-10
~
10
~
-10
~
-160
rnA
105
rnA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. 110 pin leakage is the worst case of IiL and IOZL (or IiH and loZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-368
PALCE26V12H-15/20 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CaUT
Parameter Description
Test Conditions
Input Capacitance
VIN" OV
Vcc .. 5.0 V
5
Output Capacitance
VOUT" 0 V
TA =+25°C
f .. 1 MHz
8
Typ
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
-15
Parameter Description
Min
-20
Max
Min
Max
Unit
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input, Feedback, or SP to Clock
10
13
ns
tH
Hold Time
0
0
ns
tco
Clock to Output
10
12
ns
tAR
Asynchronous Reset to Registered Output
20
25
ns
15
20
ns
tARW
Asynchronous Reset Width
15
20
tARR
Asynchronous Reset Recovery Time
15
20
ns
tSPR
Synchronous Preset Recovery Time
10
13
ns
LOW
8
10
ns
HIGH
8
10
ns
50
40
MHz
58.8
43
MHz
tWL
Clock Width
tWH
fMAX
Maximum
Frequency
(Note 3)
External Feedback
j
1/(ts + teo)
Internal Feedback (feNT)
ns
tEA
Input to Output Enable Using Product Term Control
15
20
ns
tER
Input to Output Disable Using Product Term Control
15
20
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
PALCE26V12H-15/20 (Com'l)
2-369
~
AMD
SWITCHING WAVEFORMS
Input or
Feedback _ _ ___
Vr
t s -....e-~ tH
Input or
Feedback
Combinatorial
Output
-~-vr
Clock _ _ _ _ _ _ _ _ _
~V:co
Vr
Registered
Output _ _ _ _ _ _ _ __
16072C-8
16072C-7
Combinatorial Output
Registered Output
Input
Clock
tER
tEA
Output _ _ _ _
Vr
--'-J-I,~
16072C-10
16072C-9
Input to Output Disable/Enable
Clock Width
---it-----
Input Asserting
Asynchronous
Reset
, - - - - - Input Asserting
Synchronous
Preset _ _--'
ts
Registered
Outputs _ _ _~~-K"...K.....JI
Clock
Registered
Outputs _ _ _ _ _......~......._
Clock
16072C-11
Asynchronous Reset
Notes:
1. VT= 1.5V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns-5 ns typical.
2-370
16072C-12
Synchronous Preset
PALCE26V12H-15/20
AMD~
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
XXX'tIX
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
JJ)
Does Not
Apply
Center
Line is HighImpedance
·OWState
WAVEFORM
\\\\\
/7111
CK
KSOOOO1 O-PAL
SWITCHING TEST CIRCUIT
Output O--+----...~(e} Test Point
16072C-13
Specification
tpo, teo
tEA
tER
51
CL
Rl
R2
1.5 V
Closed
Z~
H:Open
Z~
L: Closed
H ~Z: Open
L~Z: Closed
Measured
Output Value
50 pF
1.5 V
3000
5 pF
PALCE26V12H-15/20
3900
H ~Z: VOH-0.5 V
L ~ Z: VOL + 0.5 V
2-371
~ AMD '
ENDURANCE CHARACTERISTICS
The PALCE26V12 is manufactured using AMD's advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
toR
N
parts. As a result, the device can be erased and
reprogrammecl-a feature which allows 100% testing at
the factory.
Parameter
Test Conditions
Min Pattern Data Retention Time
Min Reprogramming Cycles
Min
Unit
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
Normal Programming Conditions
100
Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
ESD
ProgramNerify
Protection
Circuitry
Typical Input
Vee
Preload
Circuitry
Feedback
Input
Typical Output
16072C-15
2-372
PALCE26V12H-15/20
AMD~
ROBUSTNESS FEATURES
The PALCE26V12H-15/20 Rev. B has some unique
features that make it extremely robust, especially when
operating in high speed design environments. Input
clamping circuitry limits negative overshoot, eliminating
the possibility of false clocking caused by subsequent
ringing. A special noise filter makes the programming
circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 hs.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION
Vee
Vee
>50kn
ESD
Protection
and
Clamping
I
I
I
I
I
II P rogrammlng
.
-=-
L!'~~~Iy' ______ _
Typical Input
Preload
Circuitry
Typical Output
Device
Rev. Letter
PALCE26V12H-15
B
PALCE26V12H-20
B
Feedback
Input
16072C-15
Tops/de Marking:
AMO CMOS PLO's are marked on top of the package in the
following manner:
PALCExxxx
Oatecode (3 numbers) LOT 10 (4 characters) - - (Rev. Letter)
The Lot 10 and Rev. letter are separated by.two spaces.
PALCE26V12H-1S/20
2-373
~
AMD
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed configuration. This feature is valuable in simplifying state
machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Vee can rise to its steady state, two conditions are
Parameter
Symbol
required to ensure a valid power-up reset. These conditions are:
•
The Vee rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
ts
Input or Feedback Setup Time
tWL
Clock Width LOW
Power
Registered
Active-Low
Output
Clock
See Switching
Characteristics
4?
Vee
'~.....---tPR
~
ZI
~
tWL
Power-Up Reset Waveform
2-374
PALCE26V12H-1S/20
16072C-16
AMD~
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
PALCE26V12-15
Parameter
Symbol
Trp.
SKINNYDIP
PLCC
Parameter Description
Unit
9jc
Thermal impedance, junction to case
19
18
°elW
9ja
Thermal impedance, junction to ambient
65
55
°elW
200 Ifpm air
59
48
400 Ifpm air
54
44
600 Ifpm air
50
800 Ifpm air
50
39
37
°elW
°elW
°elW
°elW
9jma
Thermal impedance, junction to ambi.ent with air flow
Plastic 9lc Considerations
The
The data listed for plastic 9jc are for reference only and are not recommended for use in calculating junction temperatures.
heat-flow paths in plastic-encapsulated devices are complex, making the 9jc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, 9jc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE26V12-15
2-375
~
AMD
2-376
_
~
COM'L: H-25
Advanced
Micro
Devices
PALCE29M16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
semlcustom logic
• High-performance
replacement; Electrically Erasable (EE)
•
technology allows reprogrammabllity
16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
Output Enable controlled by a pin or product
terms
•
Varied product term distribution for Increased
• design
flexibility
Programmable clock selection with two clocks/
• latch enables ([Es) and LOW/HIGH clock/i:E
Register/Latch Preload permits full logic
• verification
High speed (tPD = 25 ns, fMAX= 33 MHz and fMAX
• Internal
= 50 MHz)
Full-function AC and DC testing at the factory
• for high programming and functional yields
•
•
and high reliability
24-Pln 300 mil SKINNVDIP and 2S-pln plastic
leaded chip carrier packages
Extensive third-party software and programmer
support through FusionPLD partners
polarity
GENERAL DESCRIPTION
The PALCE29M16 is a high-speed, EE CMOS Programmable Array Logic (PAL) device designed forgenerallogic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high programming yield, fast programming and excellent reliability. PAL devices. combine the flexibility of custom
logic with the off-the-shelf availability of standard products, providing major advantages over other semicustom solutions such as gate arrays and standard cells,
including reduced development time and low up-front
development cost.
BLOCK DIAGRAM
1/°0
V02
VOl':!
08740G-1
Publication# 08740 Rev. G Amendment/O
Issue Date: June 1993
2-3n
~AMD
GENERAL DESCRIPTION (continued)
The PALCE29M16 uses the familiar sum-of-products
(AND-OR) structure, allowing users to customize logic
functions by programming the device for specific applications. It provides up to 29 array inputs and 16 outputs.
It incorporates AMD's unique inpuVoutput logic macrocell which provides flexible inpuVoutput structure and
polarity, flexible feedback selection, multiple Output Enable choices, and a programmable clocking scheme.
The macrocells can be individually programmed as
combinatorial, registered, or latched with active-HIGH
or active-LOW polarity. The flexibility of the logic macrocells permits the system designer to tailor the device to
particular application requirements.
Increased logic power has been built into the
PALCE29M16 by providing a varied number of logic
product terms per output. Eight outputs have 8 product
terms each, four outputs have 12 product terms each,
and the other four outputs have 16 product terms each.
This varied product-term distribution allows complex
functions to be implemented in a single PAL device.
Each output can be dynamically controlled by a common Output Enable pin or Output Enable product terms
per bank of four outputs. Each output can also be permanently enabled or disabled.
System operation has been enhanced by the addition of
common asynchronous-Preset and Reset prodilct
terms and a power-up Reset feature. The
PALCE29M16 also incorporates Preload and Observability functions which permit full logic verification of
the design.
The PALCE29M16 is offered in the space-saving
300-mil SKINNYDIP package as well as the plastic
leaded chip carrier package.
CONNECTION DIAGRAMS
Top View
SKINNYDIP
CLKlLE
PLCC
Vcc
10
12
I/0Fo
I/OF7
I/OF1
1I0F6
1/00
1/07
1101
110s
1/02
1/05
1103
1/04
I/OF2
I/0Fs
I/OF3
1I0F4
IIOE
11
GND
I/CLKlLE
~
095
~
()
"u.
~~~ ~
I/OF6
1/07
1106
22
21
NC
1/05
1/04
I/OFS
u.MIW
0 Cl
z
~ ::: C)
()
Z
IW-J-u.
...- ~
~
~
~
08740G-3
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLKlLE
Clock/Latch Enable
GND
Ground
I
Input
I/CLKlLE
Input or Clock/Latch Enable
I/O
Input/Output
I/OF
Input/Output with Dual Feedback
NC
No Connection
Vcc
Supply Voltage
2-378
I~
I/OF1
1/0 0
1101
NC
1102
1/03
I/OF2
08740G-2
Note:
0
u.
PALCE29M16H-25
AMD~
ORDERING INFORMATION
Commercial Products
_AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL CE 29 M 16 H ·25 PC 14
_____T"'"
-----r-
r'
FAMILY TYPE
PAL .. Programmable Array Logic
TECHNOLOGY - - - - - - - - '
CE .. CMOS Electrically Erasable
--
L
OPTIONAL PROCESSING
Blank .. Standard processing
PROGRAMMING REVISION
14.. First Revision
(Requires current
programming Algorithm)
NUMBER OF ARRAY INPUTS - - - - - '
TEMPERATURE RANGE
C .. Commercial (O°C to +75°C)
OUTPUT TYPE - - - - - - - - - - '
M .. Advanced Macrocell
NUMBER OF FLIP·FLOPS - - - - - - - - '
PACKAGE TYPE
P .. 24-Pin Plastic SKINNYDIP
(PD3024)
J .. 28-Pin Plastic Leaded Chip
Carrier (PL 028)
POWER - - - - - - - - - - - - - - - '
H = Half Power (100 mAl
SPEED
-25 = 25'ns
Valid Combinations
Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations. '
PALCE29M16H·25 (Com'l)
2·379
~
AMD
FUNCTIONAL DESCRIPTION
Inputs
The PALCE29M16 has 29 inputs to drive each product
term (up to 58 inputs with both TRUE and complement
versions available to the AND array) as shown in the
block diagram in Figure 1. Of these 29 inputs, 3 are
dedicated inputs, 16 are from 8 I/O logic macrocells with
two feedbacks, 8 are from other I/O logic macrocells
with single feedback, one is the l/OE input and one is the
l/CLK/LE input.
Initially the AND-array gates are disconnected from all
the inputs. This condition represents a logical TRUE for
the AND array. By selectively programming the EE cells,
the AND array may be connected to either the TRUE input orthe complement input. When both the TRUE and
complement inputs are connected, a logical FALSE results at the output of the AND gate.
Product Terms
The degree of programmability and complexity of a PAL
device is determined by the number of connections that
form the programmable-AND and OR gates. Each programmable-AND gate is called a product term. The
PALCE29M16 has 188 product terms; 176 of these
product terms provide logic capability and 12 are architectural or control product terms. Among the 12 control
product terms, two are for common AsynchronousPreset and Reset, one is for Observability, and one is for
Preload. The other eight are common Output Enable
product terms. The Output Enable of each bank of four
macrocells can be programmed to be controlled by a
common Output Enable pin or two AND/XOR product
terms. It may be also permanently enabled or permanently disabled.
Each product term on the PALCE29M16 consists of a
58-input AND gate. The outputs of these AND gates are
connected to a fixed-OR plane. Product terms are allocated to OR gates in a varied distribution across the device ranging from 8 to 16 wide, with an average of 11
logiC product terms per output. An increased number of
product terms per output allows more complex functions
to be implemented in a single PAL device. This flexibility
aids in implementing functions such as counters, exclusive-OR functions, or complex state machines, where
different states require different numbers of product
terms.
Common asynchronOUS-Preset and Reset product
terms are connected to all Registered or Latched l/Os.
When the asynchronous-Preset product term is asserted (HIGH) all the registers and latches will immediately be loaded with a HIGH, independent of the clock.
When the asynchronous-Reset product term is asserted
(HIGH) all the registers and latches will be immediately
loaded with a LOW, independent of the clock. The actual
output state will depend on the macrocell polarity selection. The latches must be in latched mode (not transparent mode) forthe Reset, Preset, Preload, and power-up
Reset modes to be meaningful.
Input/Output LogiC Macrocells
The I/O logic macrocell allows the user the flexibility of
defining the architecture of each input or output on an individual basis. It also provides the capability of using the
associated pin either as an input or an output.
The PALCE29M16 has 16 macrocells, one for each I/O
pin. Each I/O macrocell can be programmed for combinatorial, registered or latched operation (see Figure 2).
Combinatorial output is desired when the PAL device is
used to replace combinatorial glue logic. Registers and
Latches are used in synchronous logic applications.
Common IIOE Pin
OE PTs For Banks {
of 4 Macrocells
Common
Asynchronous Preset
P110rP15
CLKIT
I/CLKii:E
Common
Asynchronous Reset
To AND Array
08740G-4
Figure 2a. PALCE29M16 Macrocell (Single FeedbaCk)
2·380
PALCE29M16H·25
AMD~
The output polarity for each macrocell in each of the
three modes of operation is user-selectable, allowing
complete flexibility of the macrocell configuration.
a dynamic I/O controlled by the Output Enable pin or by
two AND-XOR product terms which are available for
each bank of four I/O Logic Macrocells.
Eight of the macrocells (I/OFo-l/OF7) have two independent feedback paths to the AND array (see Figure
2b). The first is a dedicated I/O pin feedback to the AND
array for combinatorial input. The second path consists
-of a direct register/latch feedback to the array. If the pin
is used as a dedicated input using the first feedback
path, the register/latch feedback path is still available to
the AND array. This path provides the capability of using
the register/latch as a buried state register/latch. The
other eight macrocells have a single feedback path to
the AND array. This feedback is user-selectable as
either an I/O pin or a register/latch feedback (see
Figure2a).
1/0 Logic Macrocell Configuration
Each macrocell can provide true inpuVoutput capability.
The user can select each macrocell register/latch to be
driven by either the signal generated by the AND-OR array orthe 110 pin. When the I/O pin is selected as the input, the feedback path provides the register/latch input
to the array. When used as an input, each macrocell is
also user-programmable for registered, latched, orcombinatorial input.
The PALCE29M16H has a dedicated CLKiL'Epin and
an I/CLKlLE pin. All macrocells have a programmable
switch to choose between these two pins as the clock or
latch enable signal. These signals are clock signals for
macrocells configured as registers and latch enable signals for macrocells configured as latches. The polarity of
these CLKlLE signals is also individually programmable. Thus different registers or latches can be driven by
different clocks and clock phases.
The Output-Enable mode of each of the macrocells can
be selected by the user. The I/O pin can be configured
as an output pin (permanently enabled) or as an input
pin (permanently disabled). It can also be configured as
AMD's unique 110 macrocell offers major benefits
through its versatile, programmable inpuVoutput cell
structure, multiple clock choices, flexible Output Enable
and feedback selection. Eight 110 macrocells with single
feedback contain 9 EE cells, while the other eight macrocells contain 8 EE cells for programming the inpuV
output functions (see Table 1).
EE cell S1 controls whether the macrocell will be combinatorial or registered/latched. So controls the output polarity (active-HIGH or active-LOW). S2 determines
whether the storage element is a register or a latch. S3
allows the use of the macrocell as an input registerllatch
or as an output registerllatch. It selects the direction of
the data path through the registerllatch. If connected to
the usual AND-OR array output, the registerllatch is an
output connected to the 1/0 pin. If connected to the I/O
pin, the registerllatch becomes an input registerllatch to
the AND array using the feedback data path.
Programmable EE cells S4 and S5 allow the user to select one of the four CLKlLE signals for each macrocell.
S6 and S7 are used to control Output Enable as pin controlled, two-product-term-controlled, permanently enabled or permanently disabled. Sa controls a feedback
multiplexer for the macrocells with a single feedback
path only.
Using the programmable EE cells So-Sa various input
and output configurations can be selected. Some of the
possible configuration options are shown in Figure 3.
In the unprogrammed state (charged, disconnected), an
architectural cell is said to have a value of "1 "; in the programmed state (discharged, connected to GND), an architectural cell is said to have a value of "0."
1~~~-------------------------4
OE PTs For Banks {
of 4 Macrocells
Common
Asynchr~~~~~
PO
P7
ClKlIT
IIClKlIT
Common
Asynchronous
Reset
To AND Array
~==~----------------I RFX
To AND Array
:---<0------------------------------'
08740G-5
Figure 2b. PALCE29M16 Macrocell (Dual Feedback)
PALCE29M16H·25
2·381
~AMD
Table 1a. PALCE29M16110 Logic Macrocell Architecture Selections
S3
110 Cell
S2
Storage Element
1
Output Cell
1
Register
0
Input Cell
0
Latch
S1
Output Type
So
1
Combinatorial
1
Active LOW
0
RegisterlLatch
0
Active HIGH
S8
Output Polarity
Feedback*
1
RegisterlLatch
0
I/O
·Applies to macrocells with single feedback only.
Table 1b. PALCE29M16 1/0 Logic Macrocell Clock Polarity and Output Enable Selections
S4
S5
Clock Edge/Latch Enable Level
1
1
CLKlLE pin positive-going edge, active-LOW LE
1
0
CLKlLE pin negative-going edge, active-HIGH LE
0
1
I/CLKlLE pin positive-going edge, active-LOW LE
0
0
IICLKlLE pin negative-going edge, active-HIGH LE
S6
S7
1
1
1
0
XOR PT-Controlled Three-State Enable
0
1
Permanently Enabled (Output only)
0
0
Permanently Disabled (Input only)
Output Buffer Control
Pin-Controlled Three-State Enable
Notes:
1 = Erased State (charged or disconnected).
0= Programmed State (discharged or connected).
·Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch is transparent when the LE pin is LOW.
Active-HIGH LE means the opposite.
2-382
PALCE29M16H-25
AMD~
SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please referto the macrocell diagrams in Figure 2. All macrocell architecture cells are
independently programmable).
OB740G-6
08740G-7
Output Registered/Active Low
Output Combinatorial/Active Low
OB740G-B
OB740G-9
Output Registered/Active High
Output Combinatorial/Active High
Figure 3a. Dual Feedback Macrocells
OB740G-11
OB740G-10
Output Registered/Active Low,
I/O Feedback
Output Combinatorial/Active Low,
I/O Feedback
5 0 .0
5 0 =0
51 =0
53= 1
5 8 =0
5 2 =0
5 1 .1
53=1
5 8 =0
OB740G-13
OB740G-12
Output Latched/Active High,
I/O Feedback
Output Combinatorial/Active High,
I/O Feedback
Figure 3b. Single Feedback Macrocells
PALCE29M16H-25
2-383
~AMD
POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
5 0 =1
51- 0
53- 1
5a = 1
52- 1
08740G-14
08740G-15
Output Combinatorial/Active Low,
Register Feedback
Output Registered/Active Low,
Register Feedback
50 = 1
51 =0
53= 1
5a= 1
52=0
08740G-16
08740G-17
Output Combinatorial/Active Low,
Latched Feedback
Output Latched/Active Low,
Latched Feedback
Figure 3b. Single Feedback Macrocells (continued)
S3= 0
Sa = 1 (For, Single Feedback Only)
S2 = 1 RegIster
= 0 Latch
Programmable-AND Array
08740G-18
Input Registered/Latched
Figure 3c.' All Macrocells
2-384
PALCE29M16H-25
AMD~
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. The outputs of the PALCE29M16 depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
LOW if 'programmed as active LOW and HIGH if programmed as active HIGH. If combinatorial is selected,
the output will be a function of the logic.
Preload
To simplify testing, the PALCE29M16 is designed with
preload circuitry that provides an easy method for testing logical functionality. Both product-term-controlled
and supervoltage-enabled preload modes are available. The TTL-level preload product term can be useful
during debugging, where supervoltages may not be
available.
Preload allows any arbitrary state value to be loaded
into the registers/latches of the device. A typical functionaHest sequence would be to verify all possible state
transitions for the device being tested. This requires the
ability to set the state registers into an arbitrary "present
state" value and to set the device's inputs into an arbitrary ''present input" value. Once this is done, the state
machine is clocked into a new state, or "next state,"
which can be checked to validate the transition from the
"present state." In this way any transition can be
checked.
Since preload can provide tne capability to go directly to
any desired arbitrary state, test sequences may be
greatly shortened. Also, all possible states can be
tested, thus greatly reducing test time and development
costs and guaranteeing proper in-system operation.
Observability
The output register/latch observability product term,
when asserted. suppresses the combinatorial output
data from appearing on the I/O pin and allows the observation of the contents of the register/latch on the output
pin for each of the logic macrocells. This unique feature
allows for easy debugging and tracing of the buried state
machines. In addition, a capability of supervoltage observability is also provided.
Security Cell
A security cell is provided on each device to prevent unauthorized copying of the user's proprietary logic design. Once programmed, the security cell disables the
programming, verification, preload, and the observability modes. The only way to erase the protection cell
is by erasing the entire array and architecture cells, in
which case no proprietary design can be copied. (This
cell should be programmed only after the rest of the device has been completely programmed and verified.)
Programming and Erasing
The PALCE29M16 can be programmed on standard
logic programmers. It may also be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming
hardware. No special erasure operation is required.
Quality and Testability
The PALCE29M16 offers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the
highest programming yield and post-programming functional yield in the industry.
Technology
The high-speed PALCE29M16 is fabricated with AMD's
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong inputclamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PALCE29M16H·25
2·385
~AMD
LOGIC DIAGRAM
DIP (PLCC) Pinouts
CLKIlE
(2) 1
0
(3)2
10
(4)3
VOFO
4
8
12
16
20
24
28
32
36
40
44
48
52
sa
~
r~Ll
it .~,-<
-
OUTPUT
MACRO
c-
-
K
r...
rr~
~
J"
""-
OBSERVE
PRODUCT
TERM
23(27)
~--~
.>.>.AI
H.:::II
-
(5) 4
VOF1
-1! -
INPUTI
OllTPllT
MACRO
NPUTI
OllTPUT
MACRO
r-
"""I
~
PRESET
PRODUCT
TERM
K
...
r-t
~
t:
-
>-
....
-~
t--I"""
~r
21 (25)
VOFS
"""
INPUTI
OUTPUT
UACRO
NPUTI
OllTPUT
MACRO
.A
~~
1100
VOF 7
1"""--
~
(S) 5
J
12
,...:22(2S)
K
...
-
..
I-i
I"""
'-~
tJr
20(24)
>-
INPUT!
OllTPUT
MACRO
:....l """
Tl
....
VO]
t-r-I"""
-
INPUTI
OUTPUT
UACRO
K.
~.
'--
~
-r-
'-~-~_1 9(23)
>
~
~
t--
NPUT!
OllTPUT
MACRO
0
VOS
r---
08740G-19
2-386
PALCE29M16H-25
AMD~
LOGIC DIAGRAM
DIP (PLCC) Pinouts
12
-l
INPUT!
OUTPUT
MACRO
'---
16
20
24
28
32
36
40
44
48
~
~s
K
f--t
1"'"1"'"
.................
r-
NPUT!
OUTPUT
MACRO
18(21)
V05
LJ
f-
'"
"'1"""1"'"
........
:-rt
INPUT!
OUTPUT
MACRO
I-<
to.:
'----
...
---t
1"""1"""
r - ....
'>-
...
'
~
........
~
L:
INPUT!
OUTPUT
MACRO
t<
~
.....
+---t
1... .......
r::
1..r'"1"'"
~
...,~
........
rt
INPUT!
OUTPUT
MACRO
NPUT!
OUTPUT
MACRO
1"'"1"'"
~r
16 (19)
VOF 5
.....
t<
~
I-!t
L.--
"""-r-
I~
\
..
.... .........
PRELOAD
PRODUCT TERM
J-
>-
(13l..!1
VOE
V0 4
t---
,...,...
....:1--
-
17(20)
-~
INPUT!
OUTPUT
MACRO
U
(12) 10
VOF3
~~
INPUT!
OUTPUT
MACRO
[J"
~
15(18)
L'OF4
~
....
.
~""r-t--
}
:=
.....
12
16
20
24
28
32
36
40
48
52
RESET
PRODUCT TEAM
14 (17)
11
13(1~
vCLKlLE
~6
08740G-19
(concluded)
PALCE29M16H-25
2-387
~AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to + 150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . .. O°C to 75°C
Supply Voltage with
Respect to Ground ............ ~ -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ....... 4.75 V to 5.25 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or I/O
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current (TA = O°C to + 75°C) ..... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH =-2 mA
VIN = VIH or VIL
Vee = Min
Min
VOL
Output LOW Voltage
IOL = 8 mA
VIN = VIH or VIL
0.5
IOL = 4 mA
Vee = Min
0.33
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
Input HIGH Leakage Current
VIN = 5.5 V, Vee = Max (Note 2)
ilL
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 2)
IOZH
Off-State Output Leakage
Current HIGH
IOZL
Unit
V
V
0.1
IOL = 20 IlA
VIH
Max
2.4
2.0
V
0.8
V
10
jlA
-10
jlA
VOUT = 5.5 V, Vee = Max
VIN = VIH or VIL (Note 2)
10
jlA
Off-State Output Leakage
Current LOW
VOUT = 5.5 V, Vee = Max
VIN = VIH or VIL (Note 2)
-10
jlA
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
-130
mA
lee
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 mAl
Vee = Max
100
mA
-30
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IJL and IOZL (or IiH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-388
PALCE29M16H-25 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CaUl
Parameter Description
Test Conditions
Input Capacitance
VIN= 0 V
Output Capacitance
VOUl= 0 V
I
I
Typ
Unit
Vcc = 5.0 V, TA = 25°C,
5
pF
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS
Registered Operation
Parameter
Symbol
Min
Parameter Description
Max
Unit
25
ns
Combinatorial Output
tPD
Input or I/O Pin to Combinatorial Output
Output Register
15
ns
tsoR
Input or I/O Pin to Output Register Setup
tCOR
Output Register Clock to Output
tHOR
Data Hold Time for Output Register
0
ns
tSIR
I/O Pin to Input Register Setup
2
ns
telR
Register Feedback Clock to Combinatorial Output
tHIR
Data Hold Time for Input Register
15
ns
Input Register
28
6
ns
ns
Clock and Frequency
tCIS
Register Feedback to Output Register/Latch Setup
20
ns
fMAX
Maximum Frequency 1/(tSOR + teoR)
33.3
MHz
fMAXI
Maximum Internal Frequency 1/tels
50
MHz
tcwH
Pin Clock Width HIGH
8
ns
tCWl
Pin Clock Width LOW
8
ns
CLK~>---~---------------------,
r----+,--, tels
tSIR •••
AND-OR
Array
Output
Register
Inp.ut
Register
teOR
I/O
I/O
tSOR
,
----------,'
'"
I/O
' - - - - - - - - - - -.. teIR
tPD - - - - - - - t ! - - - - - + - - - - - - - . - t P D
08740G-20
PALCE29M16H-25 (Com'l)
2-389
~AMD
SWITCHING WAVEFORMS
Combinatorial Input
Combinatorial Output
--------~V-T-08740G-21
Combinatorial Output
Combinatorial Input
Clock
~
~V
_______'_I~~__~__OR_~C-R-~~,=T=======
~
Registered Output
....
VT_ _
08740G-22
Output Register
Registered Input
Clock
Combinatorial Output
08740G-23
Input Register
08740G-24
Clock Width
2-390
PALCE29M16H-25
AMD~
SWITCHING CHARACTERISTICS
L atc h e dO'perarIon
Parameter
Symbol
Min
Parameter Description
Max
Unit
Combinatorial Output
tPD
Input or I/O Pin to Combinatorial Output
25
ns
tpIO
Input or I/O Pin to Output via One Transparent Latch
28
ns
Output Latch
15
tsa..
Input or I/O Pin to Output Latch Setup
tGOL
Latch Enable to Output Through Transparent Output Latch
ns
tHOL
Data Hold Time for Output Latch
0
ns
tSTL
Input or I/O Pin to Output Latch Setup via Transparent Input Latch
18
ns
2
15
ns
Input Latch
tSIL
I/O Pin to Input Latch Setup
tGIL
Latch Feedback, Latch Enable Transparent Mode to Combinatorial Output
tHIL
Data Hold Time for Input Latch
ns
28
ns
6
ns
Latch Enable
tGIS
Latch Feedback to Output Register/Latch Setup
20
ns
tGWH
Pin Enable Width HIGH
8
ns
tGWL
Pin Enable Width LOW
8
ns
AND-OR
r--....I...--,
!~~_____~~~~~ __
tSTL --+-r:-~-t----+---t----;~
I/O
toOL
,,'
tSOL - - - - - - - - - - , '
tPID - - - - - - '
tpm
tPD - - - - - - - - I I - - - - t - - - - - - - . - tPD
08740G-25
Input/Output latch Specs
PAlCE29M16H-25 (Com'l)
2-391
~
AMD
SWITCHING WAVEFORMS
Latched
Input
Latched Transparent
Combinatorial
Input
Combinatorial
Output
08740G-27
LE Width
Latched
Output
08740G-26
Latch (Transparent Mode)
LE
~Latched
Vr ____T_r"""!an_s_p_a_re_n_t___ Input
_
Latch
tGiS
Trans arent
Latched
Outp'ut
Latch
08740G-29
Input and Output Latch Relationship
Latched
Input
Combinatorial
Input
Latched
Output
0874013-28
Output Latch
Latched
Input
Combinatorial
Output
08740G-30
Input Latch
Note:
1. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode after tPTD ns has
elapsed, the corresponding latched output will change tGOL ns after LE goes into the transparent mode. If the combinatorial
input change while LE is in the latched mode and LE goes into the transparent mode before tPTD ns has elapsed, the corresponding latched output will change at the later of the following-tPTD ns after the combinatorial input changes or tGOL ns after
LE goes into the latched mode.
2·392
PALCE29M16H·25
AMD~
SWITCHING CHARACTERISTICS
Reset/Preset, Enable
Parameter
Symbol
Min
Parameter Description
Max
Unit
30
ns
Combinatorial Output
tAPO
Input or I/O Pin to Output Register/Latch ResetlPreset
tAW
Asynchronous ReseUPreset Pulse Width
15
ns
tARO
Asynchronous ReseUPreset to Output RegisterlLatch Recovery
15
ns
tARi
Asynchronous ReseUPreset to Input RegisterlLatch Recovery
12
ns
Output Enable Operation
tpzX
I/OE Pin to Output Enable
20
ns
tpxz
I/OE Pin to Output Disable (Note 1)
20
ns
tEA
Input or I/O to Output Enable via PT
25
ns
Input or I/O to Output Disable via PT (Note 1)
25
ns
tER
Note:
1. Output disable times do not include test load RC time constants.
SWITCHING WAVEFORMS
Combinatorial _ _ _-,. ,._ _ _ _ _ _ _- - - - Asynchronous
vr
ReseUPreset _ _ _- I ' -_ _ _ _ _ _ '___ _ _ __
Reg iste red/Latched
Output
Clock
Output Register/Latch Reset/Preset
08740G-31
Pin 11
Combinatorial/
Registered!
Latched Output
Combinatorial
Asynchronous
ResetlPreset
Clock
.
--t?tAR'F
LtAW~
---
Input Register/Latch Reset/Preset
tpxz
....---I~-t PZX
Pin 11 to Output Disable/Enable
08740G-32
08740G-33
Combinatorial
Input
Combinatorial!
RegisteredlLatched
Output
Input to Output Disable/Enable
PALCE29M16H-25 (Com'l)
08740G-34
2-393
~AMD
KEY TO SWITCHING WAVEFORMS
INPUTS
OUTPUTS
Must be
Steady
Will be
\\\\\
May
Change
from H to L
Will be
///71
May
Change
from L to H
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
WAVEFORM
xxxxxx
Steady
Changing
from H to L
Will be
KSOOOO10
SWITCHING TEST CIRCUIT
Output
o--......~----..
08740G-35
Specification
Switch S1
tPD, teo, tGOl
Closed
tEA, tpzx
tER, tpxz
Cl
R1
R2
Z--+H: open
Z--+L: closed
35 pF
4700
390.0
H--+Z: open
5 pF
1.5 V
1.5 V
H--+Z: VOH -0.5 V
L--+Z: VOL +0.5 V
L--+Z: closed
2-394
Measured Output Value
PALCE29M16H-25
AMD~
PRELOAD
The PALCE29M16 has the capability for product-term
Preload. When the global-preload product term is true,
the PALCE29M16 will enter the preload mode. This feature aids functional testing by allowing direct seUing of
register states. The procedure for Preload is as follows:
•
Set the selected input pins to the user selected
preload condition.
•
Apply the desired register value to the I/O pins.
This sets a of the register. The value seen on the
I/O pin, after Preload, will depend on whether the
macrocell is active high or active low.
Parameter
Symbol
Parameter Description
•
•
•
Pulse the clock pin (pin 1).
Remove the inputs to the I/O pins.
Remove the Preload condition.
•
Verify VoJVOH for all output pins as per programmed pattern.
Because the Preload command is a product term, any
input to the array can be used to set Preload (including
I/O pins and registers). Preload itself will change the values of the I/O pins and registers. This will have unpredictable results. Therefore, only dedicated input pins
should be used for the Preload command.
Min
Rec.
Max
Unit
to
Delay Time
0.5
1.0
5.0
Jls
tw
Pulse Width
250
500
700
ns
tllO
Valid Output
100
500
ns
Inputs
Preload Mode
I/O Pins
~--
to
----.I
elK
- - - - - - - - VIH
Pin 1 (2)
VIL
08740G-37
Preload Waveform
PALCE29M16H-25
2-395
~·AMD
OBSERVABILlTV
The PALCE29M16 has the capability for product-term
Observability. When the global-Observe product term is
true, the PALCE29M16 will enter the Observe mode.
This feature aids functional testing by allowing direct observation of register states.
When the PALCE29M16 is in the Observe mode, the
output buffer is enabled and the I/O pin value will be Q of
the corresponding register. This overrides any OE
inputs.
The procedure for Observe is:
•
Remove the inputs to all the I/O pins.
Parameter
Symbol
•
Set the inputs to the, user selected, Observe
configuration.
•
The register values will be sent to the corresponding I/O pins.
•
Remove the Observe configuration from the selected I/O pins.
Because the Observe command is a product term, any
input to the array can be used to set Observe (including
I/O pins and registers). If I/O pins are used, the observe
mode could cause a value change, which would cause
the device to oscillate in and out of the Observe mode.
Therefore, only dedicated input pins should be used for
the Observe command.
Parameter Description
Min
Ree.
Max
Unh
to
Delay Time
0.5
1.0
5.0
~s
tllO
Valid Output
100
500
ns
Input
Pins
k tD=fe~e MOOe
I/O Pins
tt~l
VIH
VIL
VOH
VOl
-- - -
VIH
elK
Pin 1 (2)
VIL
08740G-38
Observability Waveform
2-396
PALCE29M16H-25
AMD
l1
POWER-UP RESET
The registered devices in the AMD PAL Family have
been designed with the capability to reset during system
power-up. Following power-up, all registers will be reset
to LOW. The output state will depend on the polarity of
the output buffer. This feature provides extra flexibility to
the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and parameter table are shown below. Due to the asynchronous operation of the power-up reset, and the wide
Parameter
Symbol
range of ways Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset.
These conditions are:
•
The Vec rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Min
Max
Unit
10
Il s
Power-Up Reset Time
tPR
ts
Input or Feedback Setup Time
tw
Clock Width
tR
Vee Rise Time
tR
Clock
Ils
500
Power
Registered
Active LOW
Output
See Switching Characteristics
. ---
~t~
tPR
Vee
--~.J
ZI
"=
tw
08740G-39
Power-Up Reset Waveform
PALCE29M16H-25 .
2-397
~AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ.
Parameter Description
9jc
Thermal Impedance, Junction to Case
91a
Thermal Impedance, Junction to Ambient
9jrna
Thermal Impedance, Junction to Ambient with Air Flow
SKINNYDIP
PLCC
Unh
17
11
°CIW
°elW
63
51
200 Ifpm air
60
43
°elW
400 Ifpm air
52
38
°elW
600 Ifpm air
43
34
°elW
800 Ifpm air
39
30
°elW
Plastic 9Jo Considerations
The data listed for plastic 9,c are for reference only and are not recommended for use in calculating junction temperatures. The
heat-floW paths in plastic-encapsulated devices are complex, making the 9,c measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, 9,c tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
2·398
. PALCE29M16H·25
-
~
COM'L: H-25
Advanced
Micro
Devices
PALCE29MA16H·25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
High-performance semlcustom logic
replacement; Electrically Erasable (EE)
technology allows reprogrammability
16 bidirectional user-programmable 110 logic
macrocells for Comblnatorlal/Reglstered/
Latched operation
Output Enable controlled by a pin or product
terms
Varied product term distribution for Increased
design flexibility
Programmable clock selection with common
pin clock!latch enable (IE) or Individual
product term clocklLE with LOW/HIGH clock!
LE polarity
•
Register/Latch Preload permits full logic
verification
1:1 High speed (tPD
•
•
•
=
=
25 ns, fMAX 33 MHz and fMAX
Internal = 50 MHz)
Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
24-pln 300 mil SKINNVDIP and 28-pln plastic
leaded chip carrier packages
Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Programmable Array Logic (PAL) device designed for generallogic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high pro-
gramming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
BLOCK DIAGRAM
CLK/LE
Programmable
AND Array
58x178
08811G-l
Publication# 08811 Rev. G Amendment/O
Issue Date: June 1993
2-399
~AMD
GENERAL DESCRIPTION (continued)
semicustom solutions such as gate arrays and standard
cells, including reduced development time and low upfront development cost.
.
The PALCE29MA16 uses the familiar sum-of-products
(AND-OR) structure, allowing users to customize logic
functions by programming the device for specific applications. It provides up to 29 array inputs and 16 outputs.
It incorporates AMD's unique inpuVoutput logic macrocell which provides flexible input/output structure and
polarity, flexible feedback selection, multiple Output Enable choices, and a programmable clocking scheme.
The macrocells can be individually programmed as
combinatorial, registered, or latched with active-HIGH
or active-LOW polarity. The flexibility of the logic macrocells permits the system designer to tailor the device to
particular application requirements.
Increased logic power has been built into the
PALCE29MA16 by providing a varied number of logic
product terms per output. Of the 16 outputs, 8 outputs
have 4 product terms each, 4 outputs have 8 product
terms each, and the other 4 outputs have 12 product
terms each. This varied product-term distribution allows
complex functions to be implemented in a single PAL
device. Each output can be dynamically controlled by a
common Output Enable pin or Output Enable product
term. Each output can also be permanently enabled or
disabled.
System operation has been enhanced by the addition of
common asynchronous-Preset and .Reset product
terms and a power-up Reset feature. The
PALCE29MA16 also incorporates Preload and Observability functions which permit full logic verification of
the design.
The PALCE29MA16 is offered in the space-saving
300-mil SKINNYDIP package as well as the plastic
leaded chip carrier package.
CONNECTION DIAGRAMS
Top View
SKINNYDIP
CLKlLE
PLCC
Vcc
10
13
I/OF7
I/OFo
I/OF1
I/OFs
1/00
1/07
1101
I/Os
1/05
1/02
1/03
I/OF2
1/00
1/0 1
NC
1/02
1/03
1/04
I/OFs
I/OF4
I/OF3
IIOE
Li'1~ 0 0
0;::. Z
Z
(!)
08811G-2
PIN DESIGNATIONS
CLKlLE
GND
110
1I0F
Clock or Latch Enable
Ground
Input
InpuVOutput
Input/Output with Dual Feedback
Vee
Supply Voltage
NC
No Connection
2-400
PALCE29MA16H-25
1/07
23
22
21
I/OS
NC
1/05
1/04
I/OFS
;::.
Note:
Pin 1 is marked for orientation.
24
20
I/OF2
12
11
GND
I/OFS
I/OF1
.= ~ ~
0
;::.
08811G-3
AMD~
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of these elements:
L
PAL CE 29 MA 16 H -25 P C /4
OPTIONAL PROCESSING
Blank = Standard Processing
FAMILY TYPE
PAL = Programmable Array Logic
T
PROGRAMMING REVISION
14 = First Revision
(Requires current
programming Algorithm)
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF ARRAY INPUTS _ _----I
OUTPUT TYPE - - - - - - - - - ' "
MA = Advanced Asynchronous Macrocell
TEMPERATURE RANGE
C = Com~ercial (OOC to +75°C)
NUMBER OF FLIP-FLOPS - - - - - - - - - - '
POWER-----------------------------~
PACKAGE TYPE
P = 24-Pin Plastic SKINNYDIP
(PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
H = Half Power (100 mA)
SPEED
-25 = 25 ns
Valid Combinations
Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE29MA16H-25 (Com'l)
2-401
~AMD
FUNCTIONAL DESCRIPTION
Inputs
The PALCE29MA16 has 29 inputs to drive each product
term (up to 58 inputs with both TRUE and complement
versions available to the AND array) as shown in the
block diagram in Figure 1. Of these 29 inputs, 4 are
dedicated inputs, 16 are from eight 110 logic macrocells
with two feedbacks, 8 are from other 110 !2g!c macrocells with single feedback and one is the IIOE input.
Initially the AND-array gates are disconnected from all
the inputs. This condition represents a logical TRUE for
the AND array. By selectively programming the EE cells,
the AND array may be connected to either the TRUE input orthe complement input. When both the TRUE and
complement inputs are connected, a logical FALSE results at the output of the AND gate.
Product Terms
The degree of programmability and complexity of a PAL
device is determined by the number of connections that
form the programmable-AND and OR gates. Each programmable-AND gate is called a product term. The
PALCE29MA16 has 178 product terms; 112 of these
product terms provide logic capability and others are architectural product terms. Among the control product
terms, one is for Observability, and one is for Preload.
The Output Enable of each macrocell can be programmed to be controlled by a common Output Enable
pin or an individual product term. It may also be permanently disabled. In addition, independent product terms
for each macrocell control Preset, Reset and CLK/LE.
Each product term on the PALCE29MA16 consists of a
58-input AND gate. The outputs of these AND gates are
connected to a fixed-OR plane. Product terms are allocated to OR gates in a varied distribution across the device ranging from 4 to 12 wide, with an average of 7 logic
product terms per output. An increased number of product terms per output allows more complex functions to
be implemented·in a single PAL device. This flexibility
aids in implementing functions such as counters, exclusive-OR functions, or complex state machines, where
different states require different numbers of product
terms.
Individual asynchronous-Preset and Reset product
terms are connected to all. Registered or Latched lIDs.
When the asynchronous-Preset product term is asserted (HIGH) the register or latch will immediately be
loaded with a HIGH, independent of the clock. When the
asynchronous-Reset product term is asserted (HIGH)
the register or latch will be immediately loaded with a
LOW, independent of the clock. The actual output state
will depend on the macrocell polarity selection. The
latches must be in latched mode (not transparent mode)
for the Reset, Preset, Preload, and power-up Reset
modes to be meaningful.
Input/Output Logic Macrocells
The 110 logic macrocell allows the user the flexibility of
defining the architecture of each input or output on an individual basis. It also provides the capability of using the
associated pin either as an input or an output.
The PALCE29MA16 has 16macrocells, one for each
110 pin. Each 110 macrocell can be programmed for
combinatorial, registered or latched operation (see Figure 2). Combinatorial output is desired when the PAL
. device is used to replace combinatorial glue logic. Registers and Latches are used in synchronous logic
applications. Registers and Latches with product term
controlled clocks can also be used in asychronous
application.
Common
IIOE (PIN)
IndividualOE
Individual
Asynchronous
Preset
PO
J-----t~...,--1ts..z1
IIOx
P70R P11
Common
ClKlLE (PIN)
Individual
ClK! LE
Individual
Asynchronous
Reset
Rx
To AND Array
Figure 2a. PALCE29MA16 Macroceii (Singie Feedbackj
2-402
PALCE29MA16H-25
08811G-4
AMD~
The output polarity for each macrocell in each of the
three modes of operation is user-selectable, allowing
complete flexibility of the macrocell configuration.
Eight of the macrocells (I/OFo-l/OF7) have two independent feedback paths to the AND array (see Figure
2b). The first is a dedicated I/O pin feedback to the AND
array for combinatorial input. The second path consists
of a direct register/latch feedback to the array. If the pin
is used as a dedicated input using the first feedback
path, the register/latch feedback path is still available to
the AND array. This path provides the capability of using
the register/latch as a buried state register/latch. The
other eight macrocells have a single feedback path to
the AND array. This feedback is user-selectable as
either an I/O pin or a register/latch feedback (see
Figure 2a).
Each macrocell can provide true input/output capability.
The user can select each macrocell register/latch to be
driven by either the signal generated by the AND-OR array or the corresponding I/O pin. When the I/O pin is selected as the input, the feedback path provides the
register/latch input to the array. When used as an input,
each macrocell is also user-programmable for registered, latched, or combinatorial input.
The PALCE29MA 16 has a dedicated CLK/LE pin and
one individual CLKlLE product term or macrocell. All
macrocells have a programmable switch to choose between the CLKlLE pin and the CLK/LE product term as
the clock or latch enable signal. These Signals are clock
signals for macrocells configured as registers and latch
enable signals for macrocells configured as latches.
The polarity of these CLK/LE signals is also individually
programmable. Thus different registers or latches can
be driven by different clocks and clock phases.
The Output-Enable mode of each of the macrocells can
be selected by the user. The I/O pin can be configured
as an output pin (permanently enabled) or as an input
pin (permanently disabled). It can also be configu red as
a dynamic I/O controlled by the Output Enable pin or by
a product term.
1/0 Logic Macrocell Configuration
AMD's unique I/O macrocell offers major benefits
through its versatile, programmable inpuUoutput cell
structure, multiple clock choices, flexible Output Enable
and feedback selection. Eight I/O macrocells with single
feedback contain 9 EE cells, while the other eight macroce lis contain 8 EE cells for programming the inpuU
output functions (see Table 1).
EE cell Sl controls whether the macrocell will be combinatorial or registered/latched. So controls the output polarity (active-HIGH or active-LOW). S2 determines
whether the storage element is a register or a latch. S3
allows the use of the macrocell as an input register/latch
or as an output register/latch. It selects the direction of
the data path through the register/latch. If connected to
the usual AND-OR array output, the register/latch is an
output connected to the I/O pin. If connected to the I/O
pin, the register/latch becomes an input register/latch to
the AND array using the feedback data path.
. Programmable EE cells S4 and Ss allow the user to select one of the four CLKlLE signals for each macrocell.
S6 and S7 are used to control Output Enable as pin controlled, product-term controlled, permanently enabled or
permanently disabled. Sa controls a feedback multiplexer for the macrocells with a single feedback path
only.
Using the programmable EE cells So-Sa various input
and output configurations can be selected. Some of the
possible configuration options are shown in Figure 3.
In the erased state (charged, disconnected), an architectural cell is said to have a value of "1"; in the programmed state (discharged, connected to GND), an
architectural cell is said to have a value of "0."
Common
IfOE PIN -------------------I~
Individual OE
Individual
Asynchronous
Preset
PO
1-----I>o-.---K>llfOFx
P3
Common
CLKlLE (PIN)
--_.1
Individual
CLKlLE
Individual
Asynchronous
Reset
To AND Array :===~
To AND Array
_________
_________________
---1 RFx
---.J
:===~
08811G-5,
Figure 2b. PALCE29MA16 Macrocell (Dual Feedback)
PALCE29MA16H-25
2-403
~
AMD
Table 1a. PALCE29MA16110 Logic Macrocell Architecture Selections
S3
1/0 Cell
S2
Storage Element
1
Output Cell
1
Register
0
Input Cell
0
Latch
S1
Output Type
So
1
Combinatorial
1
Active LOW
0
Register/Latch
0
Active HIGH
S8
Output Po larlty
Feedback·
1
RegisterILatch
0
I/O
"Applies to macroce/ls with single feedback only.
Table 1b. PALCE29MA16 1/0 Logic Macrocell Clock Polarity and Output Enable Selections
Clock EdgelLatch Enable Level
S4
S5
1
1
CLKlLE pin positive-going edge, active-LOW LE·
1
0
CLKlLE pin negative-going edge, active-HIGH LE·
0
1
CLKlLE PT positive-going edge, active-LOW LE·
0
0
CLKlLE PT negative-going edge, active-HIGH LE·
56
1
57
1
1
0
0
1
Permanently Enabled (Output only)
0
0
Permanently Disabled (Input only)
Output Buffer Control
Pin-Controlled Three-State Enable
PT-Controlled Three-State Enable
Notes:
1 = Erased State (Charged or disconnected).
o=
Programmed State (Discharged or connected).
"Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch
is transparent when the LE pin is LOW. Active-HIGH LE means the opposite.
2-404
PALCE29MA 16H-25
AMDl1
SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are
independently programmable).
08811G-6
Output Reg Istered/Active Low
08811G-7
Output Combinatorial/Active Low
08811G-8
08811G-9
Output Registered/Active High
Output Combinatorial/Active High
Figure 3a. Dual Feedback Macrocells
SO=1
S1" 0
S3=1
S8'"0
S2=1
08811G-10
Output Registered/Active L,ow, I/O Feedback
08811G-11
Output Combinatorial/Active Low, I/O Feedback
SO=O
S1 =0
S3= 1
S8=0
82=0
08811G-12
Output latched/Active High, I/O Feedback
08811G-13
Output Combinatorial/Active High, I/O Feedback
Figure 3b. Single Feedback Macrocells
PALCE29MA16H·25
2·405
~AMD
SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
SO-1
S1- 0
S3- 1
Sa .. 1
S2- 1
08811-014A
08811-015A
Output Registered/Active Low,
Register Feedback
Output Combinatorial/Active Low,
Latched Feedback
SO-1
S1"0
S3=1
sa" 1
S2=0
08811-016A
Output latched/Active Low,
Latched Feedback
08811-017A
Output Combinatorial/Active Low,
Latched Feedback
Figure 3b. Single Feedback Macrocells (Continued)
S3 =0
Sa .. 1 (FOR SINGLE FEEDBACK ONLV)
S2" 1 REGISTER
=0 LATCH
08811-018A
Programmable-AND Array
Figure 3c. All Macrocells
2-406
PALCE29MA 16H-25
AMD~
Power-Up Reset
All flip-flops power up to a logic LOW for predictable systeminitialization. The outputs of the PALCE29MA16
depend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
LOW if programmed as active LOW and HIGH if programmed as active HIGH. If combinatorial is selected,
the output will be_a function of the logic.
Preload
To simplify testing, the PALCE29MA 16 is designed with
preload circuitry that provides an easy method for testing logical functionality. Both product-term-controlled
and supervoltage-enabled preload modes are
available. The TIL-level preload product term can be
useful during debugging, where supervoltages may not
be available.
Preload allows any arbitrary state value to be loaded
into the registers/latches of the device. A typical functional-test sequence would be to verify all possible state
transitions for the device being tested. This requires the
ability to set the state registers into an arbitrary "present
state" value and to set the device's inputs into an arbitrary "present input" value. Once this is done, the state
machine is clocked into a new state, or "next state,"
which can be checked to validate the transition from the
"present state." In this way any transition can be
checked.
Since preload can provide the capability to go directly to
any desired arbitrary state, test sequences may be
greatly shortened. Also, all possible states can be
tested, thus greatly reducing test time and development
costs and guaranteeing proper in-system operation.
Observability
The output register/latch observability product term,
when asserted, suppresses the combinatorial output
data from appearing on the I/O pin and allows the observation of the contents of the register/latch on the output
pin for each of the logic macrocells. This unique feature
allows for easy debugging and traCing of the buried state
machines. In addition, a capability of supervoltage observability is also provided.
Security Cell
A security cell is provided on each device to prevent unauthorized copying of the user's proprietary logic design. Once programmed, the security cell disables the
programming, verification, preload, and the observability modes. The only way to erase the protection cell
is by erasing the entire array and architecture cells, in
which case no proprietary design can be copied. (This
cell should be programmed only after the rest of the device has been completely programmed and verified.)
Programming and Erasing
The PALCE29MA16 can be programmed on standard
logic programmers. It may also be erased to reset a previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erasure operation is required.
Quality and Testability
The PALCE29MA16 offers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the
highest programming yield and post-programming functional yield in the industry.
Technology
The high-speed PALCE29MA16 is fabricated with
AMD's advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven
EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong
input-clamp diodes, output slew-rate control, and a
grounded substrate for clean switching.
PALCE29MA16H-25
2·407
~
AMD
LOGIC DIAGRAM
SKINNY DIP (PLCC) Pinouts
CLKlLE
(2) 1
0
........
(3) 2
10
r- ........
t
IIOFo
8
12
16
20
24
28
32
36
40
44
48
~
56
K
.A
(4) 3
4
InpuV
Output
Macro
"'-I
....
L-
~
1--1--1
t
L....r-r-
.
..
.OBSERVE
PRODUCT
~
TERM
23 (27)
13
......... L....
-.-r
~
InpuV
Output
MauD
tt
.-:22(26)
IIOF 7
.A
~--,--
--(5) 4
IIOF1
-Ii!
..
....
3;.
~
InpuV K
Output
MauD
....
I-f
..... _L....
~
-r-r-
.
..
~
V-
InpuV
Output
MaUD
~
~
';I
L....,....r-
~r
21 (25)
IIOF s
.... '-'H
Inpuv
~rt Output
MaUD
h
L....--.
...
f-I
L....""'r-
_I-L....
r
~~2Ovb 7 )
24
InpuV
Output
MauD
"1....
' L...._ .....
'-rt~~~K
InpuV
Output
MauD
' -
.....
I-t
'-""'r-
D--~~[J~
,
InpuV
Output
MaUD
"1...
I---
088iiB-i9
2·408
PALCE29MA 16H-25
AMD~
LOGIC DIAGRAM
SKINNY DIP (PLCC) Pinouts
Continued from Previous Page
0
.A
(9) 7
8
1
15
20
24
2.
32
38
40
44
156
K
t
1/02
4
Input!
Output
Macro
'---
....
.,
t---t
-r--
>-r-........ ~ >-1 8 (21)
lJ
Input!
Output
Macro
....
....
V0 5
I--
..... -r-
r- .... 10)8
1/0 3
-~
K
Input!
Output
Macro
'-----
.... -r--
f----.-t.,
r-"-
S-~1 7(20)
1/0 4
>Input!
Output
Macro
~
....
r-"-
[11)9
I/OF2
-l!
Input!
Output
K
Macro
.... r - -
'---
..... r - -
.. -
_.... -
r-1
~
...
>-
"-
Input!
Output
~
Macro
.....
.t -
:A
12) 10 -<
Input!
Output
Macro
'----
----
..
r-t-t
~
.
--~
[t --
r
PRELOAD
PRODUCT
Input!
Output
TERM
Macro
(13)11
I/O
E
IIOF5
....
rt~-- K
/OF3
--roo-
16 (19)
.....
.....
.
J--
::1-
15 (18)
I/OF4
-
....
14(17)
12
.A
::I
13(16)
11
12
16
20
24
28
32
36
40
44
48
52
56
088118-19
(concluded)
PALCE29MA 16H-25
2-409
~AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. DoC to +75°C
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
DC Input Voltage. . . . . . . . . .. -0.5 V to Vcc + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or 110
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Static Discharge Voltage ................. 2001 V
Latchup Current (TA= DoC to +75°C) ...... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
VOH
Output HIGH Voltage
IOH =-2 rnA
VIN = VIH or VIL
Vee = Min
VOL
Output LOW Voltage
IOL = 8 rnA
VIN = VIH or VIL
0.5
IOL =4 rnA
Vee = Min
0.33
Unit
V
2.4
V
0.1
IOL = 20 JlA
V
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.5 V, Vce = Max (Note 2)
10
ilL
Input LOW Leakage Current
VIN = 0 V, Vce = Max (Note 2)
lozH
Off-State Output Leakage
Current HIGH
VOUT = 5.5 V, Vee = Max
VIN = VIH or VIL (Note 2)
10
!lA
!lA
!lA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 5.5 V, Vee = Max
VIN = VIH or VIL (Note 2)
-10
!lA
Isc
Output Short-Circuit Current
VOUT = 0.5 V, Vee = Max (Note 3)
-130
rnA
Icc
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 rnA)
Vec= Max
100
rnA
-10
-30
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2.. //0 pin leakage is the worst case of hL and IOZL (or IrH and IOZH ).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-410
PALCE29MA16H-25 (Corn'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN= 0 V
I Vcc = 5.0 V, TA = 25°C,
5
pF
Output Capacitance
VOUT= 0 V
If = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS
Registered Operation
Parameter
Symbol
Parameter Description
Min
Max
Unit
25
ns
Combinatorial Output
tPD
Input or 1/0 Pin to Combinatorial Output
Output Register - Pin Clock
tSOR
Input or VO Pin to Output Register Setup
tCOR
Output Register Clock to Output
tHOR
Data Hold Time for Output Register
15
ns
15
0
ns
ns
Output Register - Product Term Clock
tSORP
1/0 Pin or Input to Output Register Setup
tcoRP
Output Register Clock to Output
tHORP
Data Hold Time for Output Register
4
ns
29
10
ns
ns
Input Register - Pin Clock
tSIR
1/0 Pin to Input Register Setup
tCIR
Register Feedback Clock to Combinatorial Output
tHIR
Data Hold time for Input Register
2
ns
28
ns
6
ns
Clock and Frequency
tCIS
Register Feedback (Pin Driven Clock) to Output
Registerllatch (Pin Driven) Setup
20
ns
tCISPP
Register Feedback (PT Driven Clock) to Output
RegisterILatch (PT Driven) Setup
25
ns
fMAX
Maximum Frequency (Pin Driven) 1/(tSOR + tCOR)
33.3
MHz
fMAXI
Maximum Internal Frequency (Pin Driven) 1ltcis
50
MHz
fMAXP
Maximum Frequency (PT Driven) 1/(tSORP + tCORP)
30
MHz
fMAXIPP
Maximum Internal Frequency (PT Driven) 1ltclsPp
40
MHz
8
ns
tCWH
Pin Clock Width HIGH
tcW\..
Pin Clock Width LOW
8
ns
tCWHP
PT Clock Width HIGH
12
ns
tCWLP
PT Clock Width LOW
12
ns
PALCE29MA16H-25 (Com'l)
2-411
~
AMD
ClK
r--......pr--... tCIS
------
IsIR ...
AND-OR
Array
--------Output
Register
Input
Register
teOR
,
va
"
1<"':>1--------1",;
VO
.. ~ - - - - - - - - -.. tCIR
VO
tSOR
tpD
110
c: . . . t - - - - - - - t <
-------I----t-------
tpD
08811G-20
Input/Output Register Specs (Pin ClK Reference)
ClK
Inputr:>----------.
Input
Register
-tCORP
,,
VO
,
,
VO
"
tSORP - - - - - - - - - - "
VO
110
tpD - - - - - - - t - - - - t - - - - - - - t p D
08811G-21
Input/Output Register Specs (PT ClK Reference)
2-412
PAlCE29MA 16H-25
AMD~
SWITCHING WAVEFORMS
)j(1iT-
Combinatorial
Input _ _ _ _ _ _ _
~·'~~tPD
""V- - -
Combinatorial
Output
T
08811G-22
Combinatorial Output
Combinatorial
*l'::tSOR--'evtHT-O-R~""':',_~T~~~~===
v
1{v
Input - - - - ,
Clock
.
_,-VT___
Registered
Output
08811G-23
Output Register (Pin Clock)
Combinatorial
Input
~~y.
~~VT
J\
J\ T
. t SORP....
Combinatorial
Input as Clock
''I
)~
V
T
tHORP
teoR
Registered
Output
08811G-24
Output Register (PT Clock)
Registered
~v
Input - - - - ,
~v
I.:-Tt SiR ..... ~ tHIR-::j ,_T____
Clock
Combinatorial
Output
VT
_~VT___
08811G-25
Input Register
PALCE29MA 16H-25
2-413
~AMD
SWITCHING WAVEFORMS
Clock
08811G-26
Pin Clock Width
Combinatorial
Input as Clock
08811G-27
PT Clock Width
2-414
PALCE29MA 16H-25
AMD~
SWITCHING CHARACTERISTICS
Latched Operation
Parameter
Symbol
Parameter Description
Min
Max
Unit
Combinatorial Output
tPD
Input or I/O Pin to Combinatorial Output
25
ns
tPTD
Input or I/O Pin to Output via Transparent Latch
28
ns
Output Latch - Pin LE
15
tsOl
Input or I/O Pin to Output Register Setup
tGOL
Latch Enable to Transparent Mode Output
tHOL
Data Hold Time for Output Latch
0
ns
tSTL
Input or I/O Pin to Output Latch Setup via
Transparent Input Latch
18
ns
ns
15
ns
Output Latch - Product Term LE
tSOLP
Input or I/O Pin to Output Latch Setup
tGOLP
Latch Enable to Transparent Mode Output
4
ns
29
ns
tHOLP
Data Hold Time for Output Latch
10
ns
tSTLP
Input or I/O Pin to Output Latch Setup via
Transparent Input Latch
10
ns
Input Latch - Pin LE
2
tSIL
I/O Pin to Input Latch Setup
tGIL
Latch Feedback, Latch Enable Transparent Mode to
Combinatorial Output
tHIL
Data Hold Time for Input Latch
ns
28
ns
6
ns
Latch Enable
tGIS
Latch Feedback (Pin Driven) to Output Register/Latch
(Pin Driven) Setup
20
ns
tGISPP
Latch Feedback (PT Driven) to Output Register/Latch
(PT Driven) Setup
25
ns
tGWH
Pin Enable Width HIGH
8
ns
tGWL
Pin Enable Width LOW
8
ns
tGWHP
PT Enable Width HIGH
12
ns
tGWLP
PT Enable Width LOW
12
ns
PALCE29MA16H-25 (Com")
2-415
~AMD
AND-OR
r---'----,
~£ll§
Array
__ ________
_
tSTL--~----~~--~------4_--~
VO
tSOL
tPTD
tpD
'"
VO
,-----------~ tGIL
' - - - - - - - tpTD
--------------4-------+-------------~tpD
08811G-28
Input/Output Latch Specs (Pin LE Reference)
IT
INPUT
tSTLP --~--:---~~---t-------+----~
VO
VO
"
t SOLP - - - - - - - - - - - ' ,
tpTD - - - - - - - - - - - "
t PTD
t PD --------------~------+-------------- tpD
08811G-29
Input/Output Latch Specs CPT LE Reference)
2-416
PALCE29MA 16H-25
AMD~
SWITCHING WAVEFORMS
Latched
Input
-------[IPTD-
IT
---~--EVT
Input
-t-G-IS-------- Latch
Combinatorial
Input
Combinatorial
Output
Latched
Output
Transparent
Latched
VT
tP_T_D_~~~
_____________________
IT ___
Tr_~_s~pa_re_n_t_ _ _ _J
_ - - - - Output
Latch
Latched
VT
OBBllG-31
Input and Output Latch Relationship
08811G-30
Latch (Transparent Mode)
Latched
Input
Latched
Input = t v
._T______________________
..-tSTLP
Combinatorial
Input
Combinatorial
Input
~--+--"'"
Combinatorial
Input as LE _ _+-__ 1'-______-'1 "'--_ _ __
Latched
Output
Latched
Output ___-t""
08811G-33
08811G-32
Output Latch (Pin IE)
Output Latch (PT IE)
Latched
Input
LATCHED
TRANSPARENT
08811G-35
Combinatorial
Output
Pin LE Width
08811G-34
Input Latch (Pin 'IT)
Latched
Combinatorial
Input as LE
~v
I
Transparent
v
PT LE Width
Note:
~
--'1:..=tGWLP...;I~tGWHP-..:I~
08811G-36
1. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode after tPTo ns
has elasped, the corresponding latched output will change tGOL ns after LE goes into the transparent mode. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode before tPTD ns has
elapsed, the corresponding latched output will change at the later of the following - tPTD ns after the combinatorial
input changes or tGOL ns after LE goes into the latched mode.
PALCE29MA 16H-25
2-417
~AMD
SWITCHING CHARACTERISTICS
Reset/Preset , Enable
Parameter
Symbol
Min
Parameter Description
Max
Unit
30
ns
tAPa
Input or 1/0 Pin to Output Registerllatch
ResetlPreset
tAW
Asynchronous Reset/Preset Pulse Width
15
ns
tARO
Asynchronous Reset/Preset to Output
Registerllatch Recovery
15
ns
tARI
Asynchronous Reset/Preset to Input
Registerllatch Recovery
12
ns
tARPO
Asynchronous Reset/Preset to Output
Registerllatch Recovery PT ClocklLE
4
ns
tARPI
Asynchronous Reset/Preset to Input
Registerllatch Recovery PT Clock!LE
6
ns
Output Enable Operation
20
tpzx
1I0E Pin to Output Enable
tpxz
IIOE Pin to Output Disable (Note
tEA
Input or 1/0 to Output Enable via PT
tER
Input or 1/0 to Output Disable via PT (Note
1)
1)
ns
20
ns
25
ns
25
ns
Note:
1. Output disable times do not include test load RC time constants.
SWITCHING WAVEFORMS
....-tAW~
Combinatorial
Asynchronous
Reset/Preset
Registered!
Latched
Output
r
Clock _ _ _ _ _ _ _ _ _ _ _'_·__
Vr......
08811G-37
Pin
11
Combinatorial!
Registeredl
Latched
Output
Output Register/Latch Reset/Preset
Combinatorial
Asynchronous
ResetIPreset
Clock
k'AW-t-
----~ ~
~-tA-R-I-~-·-I,---v-rlVr
08811G-38
Combinatorial
Input
Combinatoriall -----"'T""~i-\.I
Registeredl
HH-+...-:..:..........-+++-f vr
Latched _----""""-"""-""""'1
Output
08811G-40
Input Register/Latch Reset/Preset
2·418
08811G-39
Pin 11 to Output Disable/Enable
PALCE29MA16H-25 (Com'l)
Input to Output Disable/Enable
AMD~
KEY TO SWITCHING WAVEFORMS.
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from H to L
Will be
Changing
from H to L
/7777
May
Change
from L to H
Will be
Changing
from L to H
Don't Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
xxxxxx
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
Sl
5V~o---.....,
Output 0 - - - - - 4 1 1 - - - - - _
08811G-41
Specification
Switch S1
tPD, teo, tGOL
Closed
tEA, tpzx
Z~H:
tER, tpxz
open
Z~L:
closed
H~Z:
open
L~Z:
closed
CL
R1
R2
Measured Output Value
1.5 V
1.5 V
35 pF
470Q
5 pF
390Q
H~Z: VOH -0.5 V
L~Z: VOL
PALCE29MA16H·25
+0.5 V
2·419
~AMD
PRELOAD
The PALCE29MA 16 has the capability for product-term
Preload. When the global-preload product term is true,
the PALCE29MA16 will enter the preload mode. This
feature aids functional testing by allowing direct setting
of register states. The· procedure for Preload is as
follows:
Set the selected input pins to the user selected
preload condition.
• Apply the desired register value to the I/O pins.
.. This sets a of the register. The value seen on the
110 pin, after Preload, will depend on whether the
macrocell is active high or active low.
•
Parameter
Symbol
•
•
•
Pulse the clock pin (pin 1).
Remove the inputs to the 1/0 pins.
Remove the Preload condition.
• Verify VaNoH for all output pins as per programmed pattern.
Because the Preload command is a product term, any
input to the array can be used to set Preload (including
I/O pins and registers). Preload itself will change the values of the I/O pins and registers. This will have unpredictable results. Therefore, only dedicated input pins
should be used for the Preload command.
Parameter Description
Min
Ree.
Max
Unit
to
Delay Time
0.5
1.0
5.0
Jis
tw
Pulse Width
250
500
700
ns
tvo
Valid Output
100
500
ns
Inputs
Preload Mode
110 Pins
14---
to
---~
- - - - - - - - VIH
elK
Pin 1 (2)
' - - - - - - - - - - - - VIL
08811G-43
Preload Waveform
2-420
PALCE29MA16H-25
AMD~
OBSERVABILITY
The PALCE29MA 16 has the capability for product-term
Observability. When the global-Observe product term is
true, the PALCE29MA 16 will enter the Observe mode.
This featu re aids functional testing by allowing direct observation of register states.
When the PALCE29MA16 is in the Observe mode, the
output buffer is enabled and the I/O pin value will be Q of
the corresponding register. This overrides any OE
inputs.
The procedure for Observe is:
•
Remove the inputs to all the I/O pins.
Parameter
Symbol
•
Set the inputs to the, user selected, Observe
configuration.
•
The register values will be sent to the corresponding I/O pins.
• Remove the Observe configuration from the selected I/O pins.
Because the Observe command is a product term, any
input to the array can be used to set Observe (including
I/O pins and registers). If I/O pins are used, the observe
mode could cause a value change, which would cause
the device to oscillate in and out of the Observe mode.
Therefore, only dedicated input pins should be used for
the Observe command.
Parameter Description
Min
Rec.
Max
Unit
to
Delay Time
0.5
1.0
5.0
Ils
tllO
Valid Output
100
500
ns
Input
Pins
t= tD =ise~e Mode
~tlOl
VIH
VIL
VOH
I/O Pins
VOL
- - - -
VIH
elK
VIL
Pin 1 (2)
08811G-44
Observability Waveform
PALCE29MA 16H-25
2-421
~
AMD
POWER-UP RESET
The registered devices in the AMD PAL Family have
been designed with the capability to reset during system
power-up. Following power-up, all registers will be reset
to LOW. The output state will depend on the polarity of
the output buffer. This feature provides extra flexibility to
the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and parameter table are shown below. Due to the asynchronous operation of the power-up reset, and the wide
Parameter
Symbol
range of ways Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset.
These conditions are:
•
The Vee rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Min
tPR
Power-Up Reset Time
ts
Input or Feedback Setup Time
tw
Clock Width
tR
Vee Rise Time
~t~~--
Jls
Vee
tPR
----.1.1
ZI
\t
tw
Power-Up Reset Waveform
2-422
Jls
500
tR
Clock
Unit
10
See Switching Characteristics
Power
Registered
Active LOW
Output
Max
PALCE29MA 16H-25
08811G-45
AMD~
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Sjc
Sja
Sjma
Typ
Parameter Description
Thermal impedance, junction to case
PLCC
Unit
17
11
°elW
63
51
°elW
200 Ifpm air
60
43
400 Ifpm air
52
38
600 Ifpm air
43
34
800 Ifpm air
39
30
°elW
°elW
°elW
°elW
Thermal impedance, junction to ambient
Thermal impedance, junction to ambient with air flow
SKINNYDIP
Plastic Sic Considerations
The data listed for plastic Sjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the Sjc measurement relatIve to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, Sjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE29MA16H-25
2-423
_
COM'L: H-15/25
~
MIL: H-20
•
Advanced
Micro
Devices
PALCE610 Family
EE CMOS High Performance Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
•
AMD's Programmable Array Logic (PAL)
architecture
•
Asynchronous clocking via product term or
bank register clocking from external pins
•
Electrically-erasable CMOS technology
providing half power (90 rnA Icc) at high speed
•
•
Register preload for testability
Power-up reset for Initialization
•
Space-saving 24-pln SKINNYOIP and 28-pln
PLCC packages
-15
= 15 ns tPD
-25 = 25 ns tPD
•
Sixteen macrocells with conflgurable 1/0
architecture
•
Fully tested for 100% programming yield and
high reliability
•
•
Registered or combinatorial operation
Registers programmable as 0, T, J-K, or S-R
•
Extensive third-party software and programmer
support through FusionPLO partners
GENERAL DESCRIPTION
The PALCE610 is a general purpose PAL device and is
functionally and fuse map equivalent to the EP610. It
can accommodate logic functions with up to 20 inputs
and 16 outputs. There are 16 I/O macrocells that can be
individually configured to the user's specifications. The
macrocelis can be configured as either registered or
combinatorial. The registers can be configured as 0, T,
J-K, or S-R flip-flops.
The PALCE610 uses the familiar sum-of-products logic
with programmable-AND and fixed-OR structure. Eight
product terms are brought to each macroceli to provide
logic implementations.
The PALCE610 is manufactured using advanced
CMOS EE technology providing high density and low
power consumption. Moreover, it is a high-speed device
having a worst-case tPD of 15 ns. Space-saving 24-pin
SKINNYDIP and 28-pin PLCC packages are offered.
This device can be quickly erased and reprogrammed
providing for easy prototyping. Once a device is programmed the security bit can be used to provide protection from copying a proprietary design.
BLOCK DIAGRAM
1/016
CLK2
2-424
II0a
1107
1/06
lIas
1/012
1/011
1/04
1/03
1/010
1/0g
1/02
1/01
Publication# 12950 Rev. F
Issue Dale: June 1993
CLK1
12950F-1
AmendmenllO
AMD~
CONNECTION DIAGRAMS
Top View
SKINNVDIP
CLK1
PLCC/LCC
Vee
;::
1I0g
()O
....
...J
0 0
0
~'" - 0
»-::.
I
1/01
1/010
1/02
1/011
1/03
1/012
1104
1/013
1105
1/014
1/015
1/06
1/07
1/016
II0a
GND
CLK2
25
24
23
22
21
20
1/0 10
1/° 11
1/° 12
1/° 13
1/°14
1/°15
NC
1/°2
1/°3
1/°4
1/°5
1/°6
1/°7
NC
~-QQ~-
o
::::.
zz ....
(!)(!)o
co
~
12950F-3
12950F-2
Nots:
Pin 1 is marked for orientation
PIN DESIGNATIONS
ClK
GND
I
= Clock
= Ground
= Input
1/0 = Input/Output
NC = No Connect
Vee = Supply Voltage
PAlCE610 Family
2·425
~
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
PAL
CE
610 H -15
T..J
FAMILYTYPE _ _ _ _ _
PAL = Programmable Array Logic
TECHNOLOGY-------------..J
CE = CMOS Electrically Erasable
P C
L
OPERATING CONDITIONS
C = Commercial (O°C to +75°C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
DEVICE NUMBER
610= 600 Gates
POWER _____________________-..J
H = Half Power (90 mA Icc)
SPEED
-15 = 15 ns tPD
-25 = 25 ns tPD
Valid Combinations
PALCE610H-15
PC,JC
PALCE610H-25
2-426
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
PALCE610H-15/25 (Com'l)
AMD~
ORDERING INFORMATION
APL Products
AMO programmable logic products for Aerospace and Defense applications are available with several ordering options. APL
(Approved Products List) products are fully compliant with MIL-STO-883 requirements. The order number (Valid Combination)
is formed by a combination of:
PAL
CE610 H ·20/B L A
t=
FAMILYTYPE _ _ _ _ _T..J
PAL. Programmable Array Logic
TECHNOLOGY------------..J
CE - CMOS Electrically Erasable
DEVICE NUMBER
610 .. 600 Gates
POWER ------------------~
LEAD FINISH
A - Hot Solder ~ip,
PACKAGE TYPE
L - 24-Pin (300 mil) Ceramic
SKINNYOIP (C03024)
3 - 28-Pin Ceramic Leadless
Chip Carrier (CL 028)
DEVICE CLASS
H = Half Power (90 mA Icc)
18
= Class B
SPEED
-20 = ,20 ns tPD
Valid Combinations
PALCE610H-20
I
I8LA,183A
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMO sales office to confirm availability of
specific valid combinations, and to check on
newly released combinations.
Group A Tests
Group A tests consist of Subgroups
1,2,3,~8,~ 1~ 11.
Military Burn-In
Military burn-in is in accordance with the current revision of MIL-STO-883, Test Method 1015, Conditions A through E.
Test conditions are selected at AMO's option.
PALCE610H·20 (Mil)
2·427
~
AMD
FUNCTIONAL DESCRIPTION
The PAlCE610 is a general purpose programmable
logic device. It has 16 independently-configurable macroce lis. Each macrocell can be configured as either
combinatorial or registered. The registers can be 0, T,
J-K, or S-R type flip-flops. The device has 4 dedicated
input pins and 2 clock pins. Each clock pin controls 8 of
the 16 macrocells.
The programming matrix implements a programmable
AND logic array which drives a fixed OR logic array.
Buffers for device inputs have complementary outputs
to provide user-programmable input polarity. Unused input pins should be tied to Vee or ground.
The array uses AMD's electrically erasable technology.
An unprogrammed bit is disconnected and a programmed bit is connected. Product terms with all bits
unprogrammed assume the logical-HIGH state and
product terms with both the TRUE and Complement bits
programmed assume the logical-lOW state.
The programmable functions in the PAlCE610 are
automatically configured from the user's design specifications, which can be in a number of formats. The design specification is processed by development
software to verify the design and create a programming
file. This file, once downloaded to the programmer, configures the design according to the user's desired function.
In The 0 and T configurations, feedback can be either
from Q or the output pin. This allows 0 and T configurations to be either outputs or I/O. In the J-K and S-R configurations, feedback is only from Q: therefore, J-K and
S-R configurations are strictly outputs.
D Flip-Flop
All 8 product terms are available to the OR gate. The 0
input polarity is controlled by an exclusive-OR gate. For
the D flip-flop, the output level is the D-input level at the
rising edge of the clock.
an an+1
D
0
0
0
0
1
1
0
0
1
1
1
1
T Flip-Flop
All 8 product terms are available to the OR gate. The
T input polarity is controlled by an exclusive-OR gate.
For the T register, the output level toggles when the T
input is HIGH and remains the same when the T input is
lOW.
an an+1
T
0
0
0
Macrocell Configurations
0
1
1
The PAlCE610 macrocell can be configured as either
combinatorial or registered. Both the combinatorial and
registered configurations have output polarity control.
The register can be configured as a 0, T, J-K, or S-R
type flip-flop. Figure 1 shows the possible configurations.
1
0
1
1
1
0
Each macrocell can select as its clock either the corresponding clock pin or the ClK/OE product term. If the
clock pin is selected, the output enable is controlled by
the ClK/OE product term. If the ClK/OE product term is
selected, the output is always enabled.
J-K Flip-Flop
The 8 product terms are divided between the J and K inputs. N product terms go to the J input and 8-N product
terms go to the K input, where N can range from 0 to 8.
Both the J and K inputs to the flip-flop have polarity control via exclusive-OR gates. The J-K flip-flop operation
is shown below.
Combinatorial I/O
All 8 product terms are available to the OR gate. The
output-enable function is performed by the elK/OE
product term.
Registered Configurations
There are 4 flip-flop types available: 0, T, J-K and S-R.
The registers can be configured as synchronous or
asynchronous. In the synchronous configuration, the
clock is controlled by the clock input pin. The output enable is controlled by the product term function. In the
asynchronous configuration, the clock input is controlled by the product term. The output is always
enabled.
2-428
PAlCE610 Family
an+1
J
K
an
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
AMD~
Combinatorial
Vee
Vee
CLK------1
CLK----t
o Register
T Register
Vee
----------1
CLK------1
Vee --------~
CLK------1
J-K Reg ister
S-R Register
12950F-4
Figure 1. Macrocell Configurations
PALCE610 Family
2·429
~
AMD
S-R Flip-Flop
The 8 product terms are divided between the Sand R
inputs. N product terms go to the S input and 8-N product terms go to the R input, where N can range from 0 to
8. Both the Sand R inputs to the flip-flop have polarity
control via exclusive-OR gates. The S-R flip-flop operation is shown below.
S
R
an
an+1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
1
0
1
1
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Security Bit
After programming and verification, a PALCE610 design can be secured by programming the security bit.
Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. However,
programming and verification are also defeated by the
security bit. The bit can only be erased in conjunction
with the array during the erase cycle. Preload is not affected by the security bit.
Technology
Not Allowed
Asynchronous Reset
All flip-flops have an asynchronous-reset product-term
input. When the product term is true, the flip-flop will reset to a logic LOW, regardless of the clock and data
inputs.
Power-Up Reset
All flip-flops powerupto a logic LOWforpredictable system initialization. Outputs of the PALCE61 0 depend on
whether they are selected as registered or combinatorial. If registered is selected, the output will be LOW. If
combinatorial is selected, the output will be a function of
the logic. The Vcc rise must be monotonic and the reset
delay time is 1000 ns maximum.
The PALCE610 is manufactured using, AMD's advanced Electrically Erasable (EE) CMOS process. This
technology uses an EE cell to replace the fuse link in bipolar parts, and allows AMD to offer lower-power parts
of high complexity. In addition, since the EE cells can be
erased and reprogrammed, these devices can be 100%
factory tested before being shipped to the customer. Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clear switching.
Programming and Erasing
Register Preload
The PALCE610 can be programmed on standard logic
programmers. It also may be erased to reset a previously configured device back to its virgin state. Bulk
erase is automatically performed by the programming
hardware. No special erase operation is required.
The register on the PALCE610 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle
The PALCE610 has CMOS-compatible outputs. The
output voltage (VOH) is 3.85 V at -2.0 rnA.
2-430
CMOS Compatibility
PALCE610 Family
AMD~
PALCE610 LOGIC DIAGRAM
DIP (PLCC) Pinouts
49
~
C LKI
~
IN PUT
£[
I
(3)
v
11O.~
Macrocell
NODEl
--
(1,2111
r=I
~
0
80
~
Macrocell
I.n
AR
OEICLK
!ill
....
~
89
I
90
v
9
R;:
11O,0W-
Macrocell
Macrocell
NODE2
AR
AR
OEICLK
99
~
I
110 2
NO DE 15
OEICLK
T
100 20
Macrocell
NODE3
~
A
V
11O"W-
~
19
NODE16
A
I
10
~
INPUT
110,
Macrocell
AR
AR
OEICLK
~
NODE14
OEICLK
109 29
A
I
I
110 30
V
W"""
110 12
Macrocell
Macrocell
NODE4
~
NODE13
AR
OEICLK
119
DFJ!' ~ IC
39
A
I
W-
110 13
I
40
120
V
Macrocell
NO DES
Macrocell
AR
AR
OEICLK
129
~
1105
NODE 12
OEICLK
49
A
I
W-
11O ..
I
130 50
V
Macrocell
Macrocell
NODE6
AR
AR
OEICLK
139
~
NODEll
OEICLK
59
A
I
v
IIO,s~
I
60
1140
Macrocell
NODE7
Macrocell
AR
AR
OEICLK
~
NODE10
OEICLK
149 69
A
I
v
11O,.~
1
150 70
Macrocell
NODE8
f-ffij1
110,
Macrocell
NODE9
AR
OEICLK
159
79
A
INP
UTmf
GND
v
liD--.
(14.T5)
i:-
0
8
16
•
24
32
16
39
40
•
24
32
39
I
'""'"'
~
ml
INPUT
CLK2
12950F-5
PALCE610 Family
2-431
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES -
Storage Temperature .......... -65°C to + 150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied ............ -55°C to + 125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
DC Output or
I/O Pin Voltage ............ -0.5 V to Vee + 0.5 V
Static Discharge Voltage
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . .. O°C to +75°C
Supply Voltage (Vee)
with Respect to Ground ..... +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
............... 2001 V
Latehup Current
(TA= O°Cto +75°C) .................... 100 rnA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Max
imum Ratings for extended periods may affect device reliabi
lity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (Note 2)
Parameter
Symbol
Test Conditions
Output HIGH Voltage
VIN = VIH or VIL
Vee = Min
IOH = -4.0 rnA
IOH =-2.0 rnA
VOL
Output LOW Voltage
VIN = VIH or VIL
Vee = Min
IOL = 8.0 rnA
IOL = 4.0 rnA
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
hH
Input HIGH Leakage
Current
VIN = 5.25 V, Vec = Max (Note 2)
10
~
Input LOW Leakage
Current
VIN = 0 V, Vec= Max (Note 2)
-10
~
loZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, Vee = Max
VIN = VIH or VIL (Note 2)
10
~
loZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or VIL (Note 2)
-10
~
Isc
Output Short-Circuit
Current
VOUT = 0.5 V, Vec = Max (Note 3)
-150
rnA
lee
Supply Current
VIN = 0 V, Outputs Open (lOUT = 0 rnA)
Vee = Max
90
rnA
.
IlL
Min
Max
Unit
Parameter Description
VOH
2.4
3.84
V
V
0.5
0.45
2.0
-30
V
V
V
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and tester noise are included.
2. 1/0 pin leakage is the worst case of liL and 10ZL (or liH and 10zH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2-432
PALCE610H-15/25 (Com'l)
AMD~
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
GoUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT= 2.0 V
Typ
Unit
8
Vee = 5.0 V
TA = +25°C
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-15
Parameter
Symbol
Parameter Description
Min
tPD
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
teo
Clock to Output
tWL
tWH
Clock
Width
fMAx
Maximum
Frequency
(Note 3)
-25
Max
Min
15
12
15
0
0
Max
Unit
25
ns
ns
ns
12
8
ns
LOW
6
10
HIGH
6
10
ns
50
76.1
83.3
37
40
50
MHz
MHz
MHz
I
External Feedback
1/(ts + teo)
Internal Feedback (feNT)
No Feedback
1/(twH + tWL)
I
ns
tEA
Input to Output Enable Using Product Term Control
15
25
tER
Input to Output Disable Using Product Term Control
15
25
ns
tAR
Asynchronous Reset to Registered Output
15
25
ns
tARW
Asynchronous Reset Width
tARR
Asynchronous Reset Recovery Time
tSA
Setup Time from Input or Feedback to Clock
(Note 4)
5
8
tHA
Hold Time (Note 4)
5
12
tCOA
Clock to Output (Note 4)
tWLA
Clock
Width
LOW (Note 4)
6
10
HIGH (Note 4)
p
10
ns
Maximum
Frequency
(Notes 3
and 4)
External Feedback
1/(tsA + teoA)
Internal Feedback (feNT)
No Feedback
1/(twLA + tWHA)
50
61.6
83.3
28.6
29.4
50
MHz
MHz
MHz
tWHA
fMAXA
10
15
ns
15
I
ns
ns
ns
27
15
I
ns
25
ns
ns
Notes:
2. See Switching Test Circuit for test conditions.
3.
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
4.
These parameters are measured using the asynchronous product-term clock.
PALCE610H-15/25 (Com'l)
2-433
~
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature ........... -65°C to +150°C
Military (M) Devices (Note 1)
Operating Case
Temperature (Te) ........... -55°C to +125°C
Ambient Temperature
with Power Applied ............. -55°C to + 125°C
Supply Voltage with
Respect to Ground ............. -0.5 V to +7.0 V
Supply Voltage (Vee)
with Respect to Ground ....... +4.5 V to +5.5 V
DC Input Voltage ........... -0.5 V to Vee + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC Output or I/O
Pin Voltage ............... -0.5 V to Vee + 0.5 V
Note:
1. Military products are 100% tested at Tc
and -5SOC, per MIL-STD-883.
, Static Discharge Voltage ................. 2001 V
Latchup Current
(Te = -55°C to + 125°C) ................ 100 rnA
= +2SOC, + 12SOC
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Absolute Maximum
Ratings are for system design reference; parameters given
are not tested.
I
DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified
Parameter
Symbol
VOH
Parameter Description
Test Conditions
Output HIGH Voltage
VIN = VIH or Vil
Vee = Min
Min
I IOH =-2 rnA
IloH=-1 rnA
Val
Output LOW Voltage
IOl = 4 rnA
Vee = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 3)
Vil
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 3)
IIH
Input HIGH Leakage Current
VIN = 5.5 V, Vee = Max (Note 4)
III
Input LOW Leakage Current
VIN = 0 V, Vee = Max (Note 4)
Off-State Output Leakage
Current HIGH
VOUT =5.5 V, Vee = Max
VIN = VIHor Vil (Note 4)
lozl
Off-State Output Leakage
Current LOW
VOUT = 0 V, Vee = Max
VIN = VIH or Vil (Note 4)
Ise
Output Short-Circuit Current
VOUT = 0.5 V, Vee = 5.0 V, TA = 25° C
(NoteS)
Icc
Supply Current
Outputs Open (louT= 0 A)
Vee = Max
loZH
Max
0.5
VIN = VIH or Vil
2.0
V
V
0.8
-30
Unit
V
2.4
3.84
V
10
~
-10
~
10
JlA
-10
JlA
-150
rnA
90
rnA
Notes:
2. For APL products, Group A, Subgroups 1,2 and 3 are tested per MIL-STD-833, Method 5005, unless otherwise noted.
3.
VIL and VIH are input conditions of output tests and are not themselves directly tested. VIL and VIH are absolute voltages with
respect to device ground and include all overshoots due to system andlor tester noise. Do not attempt to test these values
without suitable equipment.
4. 110 pin leakage is the worst case of hL and 10zL (or hH and 10ZH).
5. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. This parameter is not 100%
tested, but is evaluated at initial characterization and at anytime the design is modified where los may be affected.
2-434
PALCE610H-20 (Mil)
AMD
l1
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
CoUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ.
Vee
TA = +25°C
f = 1 MHz
Unit
8
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2)
-20
Parameter
Symbol
tPD
Parameter Description
Input or Feedback to Combinatorial Output
ts
Setup Time from Input or Feedback to Clock
tH
Hold Time
0
teo
Clock to Output
10
tWL
tWH
fMAX
Clock
Width
Maximum
Frequency
(Note 3)
LOW
Min
Max
20
Unit
ns
15
ns
ns
ns
ns
8
HIGH
I
External Feedback
1t'{ts + teal
Internal Feedback (feNT)
No Feedback
1/(tWH + twd
I
8
ns
40
50
62.5
MHz
MHz
MHz
tEA
Input to Output Enable Using Product Term Control
(Note 3)
20
ns
tER
Input to Output Disable Using Product Term Control
(Note 3)
20
ns
tAR
Asynchronous Reset to Registered Output
20
ns
tARW
Asynchronous Reset Width (Note 3)
tARR
Asynchronous Reset Recovery Time (Note 3)
tSA
Setup Time from Input or Feedback to Clock
(Note 4)
8
tHA
Hold Time (Note 4)
10
tCOA
Clock to Output (Note 4)
20
tWLA
tWHA
fMAXA
Clock
Width
Maximum
Frequency
(Notes 3
and 4)
20
ns
20
ns
ns
ns
ns
LOW (Note 4)
8
HIGH (Note 4)
8
ns
35.8
45
52.6
MHz
MHz
MHz
I
External Feedback
1/(tSA + tcOA)
Internal Feedback (teNT)
No Feedback
1/(tWLA + tWHA)
I
ns
Notes:
2. See Switching Test Circuit for test conditions. For APL Products, Group A, Subgroups 9, 10, and 11 are tested per
MIL-STD-883, Method 5005, unless otherwise noted.
3.
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
4. These parameters are measured using the asynchronous product-term clock.
PALCE610H-20 (Mil)
2-435
~
AMD
SWITCHING WAVEFORMS
Vr
Input or
Feedback _ _ _- - I
Input or
Feedback
Combinatorial
Output
-
-~-vr
.....---.. tH
CO
-=
V
Vr :
Ciock _ _ _ _ _ _ _ _.....
Registered
Outp,ut _ _ _ _ _ _ _ __
12950F-6
12950F-7
Registered Output
Combinatorial Output
Input
-----I
tEA
tER
Clock
Output
------'-.L..I.-1
12950F-9
12950F-8
Input to Output Disable/Enable
Clock Width
Input or
Feedback _ _ _- - I
Vr
Product-Term
Clock _ _ _ _ _ _ _ __
Registered
Output _ _ _ _ _ _ _ __
12950F-10
Clock Width Using
Product-Term Clock
Input
Asserting
Asynchronous
Reset
Registered
Output _ _ _L...K~...x...~
tARR
Vr
Clock
12950F-12
Notes:
1. Vr
Asynchronous Reset
= 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns-5 ns typical.
2-436
12950F-11
Registered Output Using
Product-Term Clock
PALCE610 Family
AMD
11
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
\\\\\
May
Change
from Hto L
Will be
Changing
from H to L
/////
May
Change
from L to H
Will be
Changing
from L to H
XXXXXX
1B EK
Don't Care,
Any Change
Permitted
Changing.
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
"Off" State
KSOOOO10-PAL
SWITCHING TEST CIRCUIT
5V
Output D - -.....- - -....--te) Test Point
12950F-13
Commercial
Specification
tPD, teo
tEA
Sl
Closed
35 pF
Z~
H: Open
L: Closed
35 pF
H ~Z: Open
L~ Z: Closed
5 pF
Z~
tER
CL
R1
Military
R2
R1
R2
Measured
Output Value
1.5 V
1.5 V
855n
340n
855n
340n
H ~ Z: VOH - 0.5 V
L ~ Z: VOL + 0.5 V
PALCE610 Family
2-437
~
AMD
ENDURANCE
Symbol
tOR
N
Parameter Description
Test Conditions
Min
Unit
Pattern Data Retention Time
Max Storage Temperature
Max Operating Temperature
10
20
Years
Years
Reprogramming Cycles
Normal Programming Conditions
100
Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vee
ESD
ProgramNerify
Protection
Circuitry
-=
Typical Input
Vee
1
Preload
Circuitry
Feedback
Input
Typical Output
12950F-15
2·438
PALCE610 Family
AMD
11
Power-Up Reset
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are
shown below. Due to the synchronous operation of the
power-up reset and wide range of ways Vcc can rise to
Parameter
Symbol
its steady state, two conditions are required to insure a
valid power-up reset. These conditions are:
•
The Vee rise must be monotonic.
•
Following reset, the clock input must not be driven
from LOWto HIGH until all applicable input and feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-up Reset Time
1000
ns
ts
Input or Feedback Setup Time
tWL
Clock Width LOW
Power
Registered
Output
Clock
See Switching
Characteristics
Vee
4V~
'~~,- _ _-
tPR
~
\\
~
tWL
12950F-16
Power-Up Reset Waveform
PALCE610 Family
2-439
~
AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ
SKINNYDIP
PLCC
Parameter Description
Sjc
Thermal impedance, junction to case
Sja
Thermal impedance, junction to ambient
Sjma
Thermal impedance, junction to
ambient with air flow
Unit
21
20
°elW
72
57
°elW
°elW
°elW
°elW
°elW
200 Ifpm air
64
47
400 Ifpm air
60
44
600 Ifpm air
55
40
800 Ifpm air
49
36
Plastic Sjc Considerations
The data listed for plastic Sjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the Sjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, Sjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
2-440
PALCE610 Family
3
MACH DEVICES
MACH 1 and 2 Device Families ............................................. 3-3
MACH110-12115/20 ........................................................ 3-7
MACH120-15/20 .......................................................... 3-9
MACH130-15/20 ........................ ~ ................................ 3-11
MACH210A-10, MACH210-12115/20, MACH210AQ-15/20 ......................... 3-13
MACHLV210A-15/20 ...................................................... 3-15
MACH220-12115/20 ....................................................... 3-17
MACH230-15/20 ......................................................... 3-19
MACH215-12/15/20 ....................................................... 3-21
MACH 3 and 4 Device Families ............................................
MACH435-15/20, 0-25 ....................................................
MACH355-15/20 .........................................................
MACH445-15/20 .........................................................
MACH465-15/20 ..............................' ...........................
MACH Devices
3-23
3-27
3-29
3-31
3-33
3-1
~AMD
3-2
MACH Devices
-
Advanced
Micro
Devices
MACH 1 and 2 Device Families
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
•
High-performance, high-density,
electrically-erasable CMOS PLD families
•
•
•
900 to 3600 PLD gates
44 to 84 pins In cost-effective PLCC and CQFP
packages
•
32 to 128 macrocells
•
0.8 JlI11 CMOS provides predictable
design-independent high speeds
•
-
•
•
Commercial 10/12/15/20-ns tPD,
80/67/50/40-MHz fMAX
- Military 20-ns tPD, 40-MHz fMAX
Synchronous and asynchronous devices
PAL blocks connected by switch matrix
-
•
Provides optimized global connectivity
Switch matrix integrates blocks into uniform
device
Configurable macrocells
- Programmable polarity
- Registered or combinatorial
- Internal and I/O feedback
- D-type or T-type flip-flops
- Choice of clocks for each flip-flop
- Input registers for MACH 2 family
Extensive third-party software and programmer
support through FusionPLD partners
- Schematic capture and text entry
- Compilation and JEDEC file generation
- Design simulation
- LogiC and timing models
- Standard.PLD programmers
Each MACH product has a factory programming
option available for high-volume applications
PRODUCT SELECTOR GUIDE
Device
MACH 1 Family
Pins
Macrocells
PLD Gates
Max
Inputs
Max
Outputs
Max
Flip-Flops
Speed
(ns)
MACH110
MACH120
MACH130
MACH 2 Family
44
68
84
32
48
64
900
1200
1800
38
56
70
32
48
64
32
48
64
12,15,20
15, 20
15, 20
MACH210
44
64
1800
38
96
128
2400
3600
56
70
32
48
64
64
96
128
10,12,15,20
12,15,20
15, 20
64
1500
38
32
64
12,15,20
MACH220
MACH230
68
84
Asynchronous MACH Device
MACH215
44
GENERAL DESCRIPTION
The MACH (Macro Array CMOS High-density) family
provides a new way to implement large logic designs in
a programmable logic device. AMD has combined an
innovative architecture with advanced electricallyerasable CMOS technology to offer a device with
several times the logic capability of the industry's most
popular existing PAL device solutions at comparable
speed and cost.
Their unique architecture makes these devices ideal for
replacing large amounts of TTL, PAL-device, glue, and
gate-array logic. They are the first devices to provide
such increased functionality with completely predictable, deterministic speed.
The MACH devices consist of PAL blocks interconnected by a programmable switch matrix (Figure 1).
Designs that consist of several interconnected functional modules can be efficiently implemented by
placing the modules into PAL blocks. DeSigns that are
not as modular can also be readily implemented since
the switch matrix provides a high level of connectivity
between PAL blocks. The internal arrangement of
resources is managed automatically by the deSign
software, so that the designer does not have to be
concerned with the logic implementation details.
The MACH family consists of the MACH 1 and MACH 2
series of synchronous devices and the MACH215, an
MACH 1 and 2 Device Families
~AMD
asynchronous device. The MACH 1 and 2 series are
ideal for synchronous subsystems like memory controllers and peripheral controllers. The MACH215 is
appropriate for applications having asynchronous inputs and for collecting random glue logic.
of tools for each new device, but rather can use the tools
with which he or she is already familiar. The MACH
devices can be programmed on conventional PAL
device programmers with appropriate personality and
socket adapter modules.
AMD's FusionPLD program allows MACH device designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide timely, accurate, quality support. This ensures
that a designer does not have to buy a complete new set
MACH devices are manufactured using AMD's state-ofthe-art advanced CMOS electrically-erasable process
for high performance and logic density. CMOS EE
technology provides 100% testability, reducing both
prototype development costs and production costs.
r-----~
Output: Buried
Output: Buried
Macro- I Macro- 1----+11> Macro- I Macro-
•• ~e!l: .:••c~~s: _
•• :e~l~ .:••c~~s: •
PAL Block
PAL Block
t
I
t
Switch Matrix
I
1
PAL Block
PAL Block
. O~tP~t·:· B~ried
·Output : ·B~ri;d·
........- -..... ~ Macrocells
I
I
Macro- I - - -......~i......
~ Macrocells·
cells
I
I
• ••
I
•••
Macrocells·
14051G-1
• Buried macrocell available on MACH 2 devices only.
Figure 1. MACH 1 and 2 Block Diagram
Design Methodology
Design tools for MACH devices are widely available
both from AMD and from third-party software vendors.
AMD provides PALASM software as a low-cost baseline
tool set and works with tools vendors to ensure broad
MACH device support. This allows designers to do
MACH device deSigns using the same tools that
they would use to do PAL device designs, whether
PALASM software or any of the other popular PAL
device design packages.
Design entry is the same as that used for PAL devices.
The basic logic processing steps are the same steps
that are needed to process and minimize logic for any
PAL device. Simulation is available for verifying the
correct behavior of the device. Functional (unit-delay)
simulation of MACH devices is supported in all approved software packages, and other options for
simulating the timing and board-level behavior of the
MACH devices are available. The end result is a JEDEC
file that can be downloaded to a programmer for device
configuration.,
MACH device desian methodoloav differs somewhat
from that of a PAL device due to the automatic design
3-4
fitting procedure that the software performs. DeSigns
written by logic designers-whether by schematic
capture, state machine equations, or Boolean equations-are partitioned and placed into the PAL blocks of
the MACH device. While this procedure is handled
automatically by the software, the software can also
accept manual direction based upon the user's working
knowledge of the design. The overall device utilization
provided by the Fitterwill vary from deSign to design, but
a utilization target of no greater than 70% is recommended. Since a design must be entered and fit in order
to calculate actual utilization, it is best to be conservative
when estimating utilization before starting a design.
AMD recommends allowing the software to decide the
best fit and pin· placement automatically for the first
design iteration to provide the best chance of fitting.
With this approach, large designs can be implemented
incrementally, starting with low device utilization and
building up by adding logic until the device is full. This
generally means that designs are done without any
specific pinout assignments. with the final pinout
decided by the software. While it is possible to pre-place
signals, it is not recommended in most cases. If done
carefully, pre-placement can help the software fit
MACH 1 and 2 Device Families
AMD~
difficult designs; if not done carefully, it may make it
harder for the design to fit. Guidelines on specifying
the initial pinout are provided in the MACH Technical
Briefs book.
The design is partitioned and placed into the MACH
device by the software so as not to affect the performance of the design. With deSigns that do not fit, it is
possible to make some performance tradeoffs to aid in
fitting (for example, by optimizing the flip-flop type or
passing through the device more than once), but those
tradeoffs must be specifically requested, and any
additional delays are entirely predictable.
Once an initial design fits, there may be subsequent
changes to the deSign. This is important if board layout
has already started based on the original pinout. Design
changes make it necessary to refit the design, which
may result in a different pinout. Some deSign changes
may make it impossible to refit the deSign, regardless of
the pinout. The stability of the design and the expected
extent of any changes should therefore be considered
before committing the design to layout. Careful designs
that target about 70% utilization will make future
changes much easier. Higher utilization will make
deSign changes much more difficult to implement. Hints
on designing for change can be found in the MACH
Device Design Planning Guide near the end of this
book, and in the article Designing for Change with
MACH Devices in the Technical Briefs book.
MACH 1 and 2 Device Families
3-5
~AMD
3·6
MACH 1 and 2 Device Families
CONDENSED
_
COM'L: -12/15/20
MIL: -20
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
~
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
44 Pins
32 Macrocells
•
12 ns tPD Commercial
20 nstpD Military
•
66.7 MHz fMAX external Commercial
40 MHz 'MAX external Military
•
381nputs
•
•
32 Outputs
32 Flip-Flops; 2 clock choices
•
2 "PAL22V16" Blocks
•
Pin-compatible with MACH210, MACH215
GENERAL DESCRIPTION
The MACH110 is a memberof AMD's high-performance
EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the
popular PAL22V1 0 with no loss of speed.
The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL
blocks are essentially "PAL22V16" structures complete
with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Publication# C14127 Rev. G AmendmentlO
Issue Date: June 1993
The MACH110 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the number of product terms. The register type decision can be
made by the designer or by the software. All macrocells
can be connected to an I/O cell. If a buried macrocell is
desired, the internal feedback path from the macrocell
can be used, which frees up the liD pin for use as
an input.
3-7
~
CONDENSED
AMD
BLOCK DIAGRAM
10- h.
13-14
1/00-1/015
16,;~
...
16
, ....
1/0
Cells
16
16
, ....
1
2....
Macrocells
DE
44
4,; ...
x 70
AN D Logic Array
and
Logic Allocator
22
Switch Matrix
22
44
x 70
AND Logic Array
and
Logic Allocator
2
...
DE
.2L
Macrocells
16
L...t.
I
16
,
1/0
-,
2~
Cells,
16L
,
16/
11016 - 1/031
3-8
MACH 110-12/15/20
CLK1/Is.
CLKo/12
C14127G-1
CONDENSED
_
~
COM'L:-15/20
MACH120-15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
68 Pins
48 Macrocells
•
48 Outputs
•
48 Flip-flops; 4 clock choices
•
15 ns tPD
•
4 PAL blocks
•
50 MHz fMAX external
•
Pin-compatible with MACH220
•
56 Inputs
GENERAL DESCRIPTION
The MACH120 is a memberof AMO's high-performance
EE CMOS MACH 1 family. This device has approximately five times the logic macrocell capability of the
popular PAL22V10 with no loss of speed.
The MACH120 consists of four PAL blocks interconnected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently.
Publication# C14129 Rev. G AmendmentlO
Issue Date: June 1993
The MACH120 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as O-type or T-type to help reduce the number of product terms. The register type decision can be
made by the designer or by the software. All macrocells
can be connected to an lID cell. If a buried macrocell is
desired, the internal feedback path from the macrocell
can be used, which frees up the lID pin for use as an
input.
3-9
~
CONDENSED
AMD
BLOCK DIAGRAM
12 -13.
16-17
52
x 54
52
x 54
AND Logic Array
AND Logic Array
and
Logic Allocator
and
Logic Allocator
26
~x~
~x~
AND Logic Array
AND Logic Array
and
Logic Allocator
and
Logic Allocator
OEr-__~____,
OEr-__~____~
~~-r+--+~
'------a--c::::::"L.....J
4
<~--~~~_I,------'
12
12
1/036 - 1/047
3-10
1/024 -1/035
MACH120-15/20
CLKo/lo, CLK1/11.
CLK2/14, CLK3/15
C14129G-1
CONDENSED
_ , COM'L:-15/20
MIL: -20
MACH130-15/20
High-Density EE CMOS Programmable Logic
~
Advanced
Micro
De'vices
DISTINCTIVE CHARACTERISTICS
•
•
•
84 Pins
64 Macrocells
15 ns tpo Commercial
20 ns tpo Military
•
50 MHz fMAx external Commercial
40 MHz fMAx external Military
•
70 Inputs
•
•
64 Outputs
64 Flip-flops; 4 clock choices
•
4 "PAL26V16" Blocks with buried Macrocells
•
Pin-compatible with MACH230, MACH435
GENERAL DESCRIPTION
The MACH130 is a memberof AMO's high-performance
EE CMOS MACH 1 family. This device has approximately six times the logic macrocell capability of the
popular PAL22V10 at an equal speed with a lower cost
per macrocell.
The MACH130 consists of four PAL blocks interconnected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently.
Publication# C14131 Rev. F
Issue Date: June 1993
AmendmentlO
The MACH130 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as O-type or T-type to help reduce the number of product terms. The register type decision can be
made by the designer or by the software. All macrocells
can be connected to an I/O cell. If a buried macrocell is
desired, the internal feedback path from the macrocell
can be used, which frees up the 1/0 pin for use as an
input.
3-11
~
AMD
CONDENSED
BLOCK DIAGRAM
12,15
1/016-11031
4
OE
52 x 70
52 x 70
AND Logic Array
and
Logic Allocator
AND Logic Array
and
Logic Allocator
2
26
Switch Matrix
26
52 x 70
52 x 70
AND Logic Array
and
Logic Allocator
AND Logic Array
and
Logic Allocator
OE
OE
1/048 - 1/063
4
4
1/032 -1/047
CLKo/lo, CLK1/11
CLK2/13, CLK3/14
C14131F-1
3-12
MACH130-15/20
CONDENSED
COM'L: -10/12/15/20, Q-15/20
_
MIL: -20
MACH210A-10
MACH21 0-12/15/20
MACH210AQ-15/20
High-Density EE CMOS Programmable Logic
~
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
44 Pins
64 Macrocells
•
38 Inputs; 210A Inputs have built-In pull-up
resistors
•
10 ns tPD Commercial
20 ns tPD Military
•
•
32 Outputs
64 Flip-flops; 2 clock choices
•
80 MHz fMAX external Commercial
40 MHz fMAX external Military
•
4 "PAL22V16" blocks with burled macrocells
•
Pin-compatible with MACH110, MACH215
GENERAL DESCRIPTION
The MACH210 is a memberof AMD's high-performance
EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of
the popular PAL22V1 0 with no loss of speed.
The MACH210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL
blocks are essentially "PAL22V16" structures complete
with product-term arrays and programmable macrocells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
tered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type deciSion can be made by the designer or by the
software. All output macrocells can be connected to an
liD cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the liD pin for use as an input.
The MACH21 0 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in synchronizing signals and reducing setup time requirements.
The MACH210 has two kinds of macrocell: output and
buried. The MACH21 0 output macrocell provides regis-
Publication# C14128 Rev. G AmendmentlO
Issue Date: June 1993
3-13
~
CONDENSED
AMD
BLOCK DIAGRAM
1100-1/07
10-11.
13-14
1/08-1/015
2
44 x 68
44 x 68
AND Logic Array
and
Logic Allocator
AND Logic Array
and
Logic Allocator
4
Switch Matrix
44 x 68
AND Logic Array
and
Logic Allocator
44 x 68
AND Logic Array
and
Lo ic Allocator
DE
DE
1/024-1/031
1/016-1/023
CLKo/12.
CLK1/15
14128G-1
3-14
MACH21 0-1 0/12/15/20, 0-15/20
i.j.N·Ul3JWieh'M·"'eUi
CONDENSED
COM'L: -15/20
~
MACHLV210A-15/20
Advanced
Micro
Devices
High Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
Low-voltage operation, 3.3 V JEDEC
compatible
- Vee = +3.0 V to +3.6 V
10 rnA standby power
44 Pins
64 Macrocells
15 ns tPD
50 MHz fMAX external
•
•
•
•
•
•
38 Inputs with pull-up resistors
32 Outputs
64 Flip-flops; 2 clock choices
4 "PAL22V16" blocks with burled macrocells
Pln-, functlon-, and JEDEC-compatlble with
MACH210
Pin-compatible with MACH110, MACH215
GENERAL DESCRIPTION
The MACHLV210A is a member of AMD's highperformance EE CMOS MACH 2device family. This device has approximately six times the logic macrocell
capability of the popular PAL22V10 at an equal speed
with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of 1/0 pull-up
resistors and low-voltage, low-power operation.
The MACHLV21 OA provides 3.3 V operation with lowpower CMOS technology. At 10 rnA maximum standby
current, the MACHLV21 OA is ideal for low-power
applications.
The MACHLV210A consists of four PAL blocks interconnected by a programmable switch matrix. The four
PAL blocks are essentially "PAL22V16" structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The
switch matrix connects the PAL blocks to each other and
to all input pins, providing a high degree of connectivity
Publication# C17908 Rev. A
Issue Date: June 1993
Amendment/O
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACHLV210A has two kinds of macrocell: output
and buried. The MACHLV210A output macrocell provides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or by
the software. All output macrocells can be connected to
an I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACHLV210A has dedicated buried
which, in addition to the capabilities of
macrocell, also provide input registers or
use in synchronizing signals and reducing
requireme nts.
macrocells
the output
latches for
setup time
3-15
~
CONDENSED
AMD
BLOCK DIAGRAM
1100-1/07
10-11.
13-14,
I/OS-1/01S
8
2
44 x 68
AND Logic Array
and
Logic Allocator
44 x 68
AND Logic Array
and
Logic Allocator
22
4
22
Switch Matrix
44 x 68
AND Logic Array
and
Logic Allocator
44 x 68
AND Logic Array
and
Lo ic Allocator
2
OE
OE
2
1/024-11031
1/016-11023
CLKo!l2.
CLK1/Is
1790SA-1
. 3-16
MACHLV210A-15/20
-
CONDENSED
~
COM'L: -12/15/20
MACH220-12/15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
68 Pins
• 96 Macrocells
•
•
•
12 ns tPD
66.7 MHz fMAX external
56 Inputs with pull-up resistors
•
48 Outputs
• 96 Flip-flops; 4 clock choices
• 8 PAL blocks with burled macrocells
•
Pin-compatible with MACH120
GENERAL DESCRIPTION
The MACH220 is a memberof AMD's high-performance
EE CMOS MACH 2 device family. This device has approximately nine times the logic m,acrocell capability of
the popular PAL22V1 0 with no loss of speed.
The MACH220 consists of eight PAL blocks interconnected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH220 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
Publication# C14130 Rev. G Amendment/O
Issue Date: June 1993
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T -type to help
reduce the number of product terms. The registertype
decision can be made by the designer or by the software. All output macrocells can be connected to an 1/0
cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH220 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing signals and reducing setup time requirements.
3-17
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ClO
1100-1105
1106-11011
11012-11017
11018-11023
12-13,
16-17
:;
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11036-11041
11030-11035
11024-11029
CLKO/IO, CLK1/11
CLK2I14 ; CLK3I15
C14130G-1
CONDENSED
_
~
COM'L:-15/20
MACH230-15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
84 Pins
128 Macrocelis
•
•
15 ns tPD
50 MHz fMAX external
•
70 Inputs
•
•
•
•
64 Outputs
128 Flip-flops; 4 clock choices
8 "PAL26V16" blocks with burled macrocelis
Pin-compatible with MACH130, MACH435
GENERAL DESCRIPTION
The MACH230 is a memberof AMD's high-performance
EE CMOS MACH 2 device family. This device has approximately twelve times the logic macrocell capability
of the popular PAL22V10 with no loss of speed.
The MACH230 consists of eight PAL blocks interconnected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
Publication# C14132 Rev. G Amendment/O
Issue Date: June 1993
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the software. All output macrocells can be connected to an 1/0
cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees
up the 1/0 pin for use as an input.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing signals and reducing setup time requirements.
3-19
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VOO - V07 (Block A)
VOS - 0015 (Block B)
V016 - VOl3 (Block C)
V024 - V031 (Block 0)
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VOS6 - V063 (Block H)
V048 - VOSS (Block G)
V040 - V047 (Block F)
V031 - V039 (Block E)
CLKO/IO, CLKlI11
CLK2I13, CLK3J14
C14132G-1
CONDENSED
_
~
COM'L: -12/15/20
MACH215-12/15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
44 Pins
32 Output Macrocells
•
67 MHz fMAX external
•
3S Inputs with pull-up resistors
•
32 Input Macrocells
•
32 Outputs
•
Product terms for:
64 Flip-flops
4 "PAL22RAS" blocks with burled macrocells
Pin-compatible with MACH110, MACH210
•
-
Individual flip-flop clock
•
•
-
Individual asynchronous reset, preset
•
-
Individual output enable
12 ns tPD
GENERAL DESCRIPTION
The MACH215 is a memberof AM D's high-performance
EE CMOS MACH device family. This device has approximately three times the capability of the popular
PAL20RA10 with no loss of speed.
The MACH215 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL
blocks are essentially "PAL22RAS" structures complete
with product-term arrays and programmable macrocells, individual register control product terms, and input
registers. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Publication# C16751 Rev. C
Issue Date: June 1993
AmendmentiO
The MACH215 has two kinds of macrocell: output and
input. The MACH215 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. Each macrocell has its own dedicated clock,
asynchronous reset, and asynchronous preset control.
The polarity of the clock signal is programmable. All output macrocells can be connected to an 1/0 cell.
The MACH215 has dedicated input macrocells which
provide input registers or latches for synchronizing input
signals and reducing setup time requirements.
3-21
~
CONDENSED
AMD
BLOCK DIAGRAM
VOo-I/O;
VOa-1/01S
Q
Q
T
..j
8/
Output
Macrocells
--I
1
S1
DE
T
8~
I
1/0 Cells
VOCelis
8f I
tnput
Macrocells
I
J
I
I
t
ClK
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8
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/
1
8"
J
S!
Output
Macrocells
OE
8"
J
44x64
AND Logic Array
and
Logic Allocator
I
10-11.
13-14
Input
Macrocells
ClK
,
8" S
8"
J
44x64
AND Logic Array
and
Logic Allocator
22
J
I
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22
Switch Matrix
22
22
44x64
AND Logic Array
and
Logic Allocator
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8
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1
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I
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~
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8,,8,
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~
1/016-1/023
CLKo/12 CLK1/1s
C16751C-1
3-22
MACH215-12/15/20
-
~
Advanced
Micro
Devices
MACH 3 and 4 Device Families
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
•
•
High-performance, high-density
electrically-erasable CMOS PLD families
Predictable design-Independent 15- and 20-ns
speeds
•
High density, pin count
- 3500-10,000 PLD Gates
- 84-208 Pins
- 96-384 Registers
•
Input and output switch matrices increase
ability to hold a fixed pinout
JTAG, 5-V In-circuit programmability on
devices with more than 84 pins
Synchronous and asynchronous modes
available for each macrocell
- Clock generator in each PAL block for
programmable clocks, edges in either mode
- Individual clock, initialization product terms in
asynchronous mode
•
•
•
Central, Input, and output switch matrices
- 100% Routability with 80% Utilization
•
•
Up to 20 product terms per function
96-256 configurable macrocells
- D/T/J-K/S-R Registers, latches
- Synchronous or asynchronous mode
- Programmable polarity
- Reset/preset swapping
•
•
•
XOR gate available
Registered/latched inputs on MACH 4 series
Extensive third-party software and programmer
support thro~gh FusionPLD partners
PRODUCT SELECTOR GUIDE
Device
Pins
Macrocells
PLD
Gates
Max
Inputs
Max
Outputs
Max
Flip-Flops
JTAGI
5 V Prog
Speed
132
96
3500
102
96
96
Y
15,20
84
128
5000
70
64
192
N
15,20,
0-25
MACH 3 Family
MACH355
MACH 4 Family
MACH435
MACH445
100
128
5000
70
64
192
Y
15,20
MACH465
208
256
10,000
146
128
384
Y
15,20
GENERAL DESCRIPTION
The MACH (Macro Array CMOS High-speed/density)
family provides a new way to implement large logic
designs in a programmable logic device. AMD has
combined an innovative architecture with advanced
electrically-erasable CMOS technology to offer a device
with many times the logic capability of the industry's
most popular existing PAL device solutions at comparable speed and cost.
The second-generation MACH devices provide approximately three times the density and register count, and
two times the amount of I/O of the original MACH 1 and
2 families. By increasing the pin count, adding function-
ality, and improving routing, the MACH 3 and 4 families
build upon the strength of the MACH architecture
without sacrificing predictable timing.
Their unique architecture makes these devices ideal for
replacing large amounts of TTL, PAL-device, glue, and
gate-array logic. They are the first devices to provide
such increased functionality with completely predictable, deterministic speed.
The MACH devices consist of PAL blocks interconnected by a programmable central switch matrix
(Figure 1). Designs that consist of several intercon-
MACH 3 and 4 Device Families
3-23
~
AMD
nected functional modules can be efficiently implemented by placing the modules into PAL blocks.
Designs that are not as modular can also be readily
implemented since the central switch matrix provides a
very high level of connectivity between PAL blocks.
The use of input and output switch matrices allows logic
to be implemented independent of pin connections. This
allows greater flexibility when making initial pin assignments for PCB layout, or when trying to maintain the
pinout through design changes. The internal arrangement of resources is managed automatically by the
design software, so that the deSigner does not have to
be concerned with the logic implementation details.
AMD's FusionPLD program allows MACH device designs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide timely, accurate, quality support. This ensures
that a designer does not have to buy a complete new set
of tools for each new device, but rather can use the tools
with which he or she is already familiar. The MACH
devices can programmed on conventional PAL device
programmers. Devices with pin counts greater than 84
have an additional 5-V programming algorithm option
that can be implemented with the devices soldered onto
the board.
MACH devices are manufactured using AMD's state-ofthe-art advanced CMOS electrically-erasable process
for high performance and logic density. CMOS EE
technology provides 100% testability, reducing both
prototype development costs and production costs.
PAL Block
PAL Block
110 Cells
0
~
Q)
0
Macrocells
C>
Logic Allocator
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Output Switch
Matrix
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•••
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Macrocells
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Matrix
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4
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17466A-1
Figure 1. MACH 3 and 4 Block Diagram
3-24
MACH 3 and 4 Device Families
AMD~
Design Methodology
Design tools for all MACH devices are widely available
both from AMD and from third-party software vendors.
AMD provides MACHXLTM software as a low-cost
baseline tool set and works with third-party vendors to
ensure broad MACH device support. MACHXL software
is based on the popular PALASM
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CONDENSED
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~
COM'L: -15/20
MACH355-15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
132 Pins In PQFP
•
96 Macrocells
•
•
15 ns tpo
50 MHz fMAX external
•
102 Inputs with pull-up resistors
•
96 Outputs
•
•
96 Flip-flops
Up to 20 product terms per function, with XOR
•
Flexible clocking
- Four global clock pins with selectable edges
- Asynchronous mode available for each
macrocell
•
JTAG, 5-V programmability
• 6 "PAL33V16" blocks
•
Input and output switch matrices for high
routablllty
•
Fixed, predictable, deterministic delays
GENERAL DESCRIPTION
The MACH355 is a memberof AMO's high-performance
EE CMOS MACH 3 family. This device has approximately nine times the macrocell capability of the popular
PAL22V10, with significant density and functional
features that the PAL22V10 does not provide.
The MACH355 consists of six PAL blocks interconnected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to lID pins.
The MACH355 has macrocells that can be configured
as synchronousor asynchronous. This allows designers
to implement both synchronous and asynchronous logic
together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH355 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Publication# C17467 Rev. A AmendmentiO This document contains information on a product under development at Advanced Micro Devices, Inc. The information is
~I_ss_u_eD_a_te_:_Ju_n..;..8..;..19;.;.9.;..3_ _ _ _ _..J :~t~~~~~~~i~~P you evaluate this product. AMO reserves the right to change or discontinue work on this proposed product
3-29
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66X98
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~
COM'L: -15/20
MACH445-15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
•
100 pins In PQFP
MACH435 with JTAG, 5-V programmability
•
128 Macrocells
•
•
•
15 ns tPD
50 MHz fMAx external
70 Inputs with pull-up resistors
•
•
64 Outputs
192 Flip-flops
-
128 Macrocell flip-flops
64 Input flip-flops
•
Up to 20 product terms per function, with XOR
•
Flexible clocking
-
Four global clock pins with selectable edges
Asynchronous mode available for each
macrocell
•
•
8 "PAL33V16" blocks
Input and output switch matrices for high
routability
•
•
Fixed, predictable, deterministic delays
JEDEC-file compatible with MACH435
GENERAL DESCRIPTION
The MACH445 is a memberof AMD's high-performance
EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the
popular PAL22V10, with significant density and functional features that the PAL22V1 0 does not provide. It is
architecturally identical to the MACH435, with the
addition of JTAG and 5-V programmability capabilities.
The MACH445 consists of eight PAL blocks interconnected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows deSigns to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.
The MACH445 has macrocells that can be configured
as synchronous or asynchronous. This allows designers
to implement both synchronous and asynchronous logic
together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without lOSing the use of that macroce/l for
logic generation.
The MACH445 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Publication# C174S8 Rev. A Amendment/O This document contains information on a product underdevelopment at Advanced Micro Devices, Inc. The information
Issue Date: June 1993
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
' - - - - - - - - - - - - - - - ' product without notice.
3-31
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~
COM'L: -15/20
MACH465-15/20
High-Density EE CMOS Programmable Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
•
208 pins In PQFP
•
Up to 20 product terms per function, with XOR
•
256 macrocells
•
Flexible clocking
•
•
15 ns tPD
50 MHz fMAX external
•
146 Inputs with pull-up resistors
•
128 Outputs
•
384 Flip-flops
- 256 Macrocell flip-flops .
-
128 Input flip-flops
-
Four global clock pins with selectable edges
-
Asynchronous mode available for each
macrocell
•
16 "PAL34V16" blocks
•
JTAG, 5-V programmability
•
Input and output switch matrices for high
routability
•
Fixed, predictable, deterministic delays
GENERAL DESCRIPTION
The MACH465 is a memberof AMO's high-performance
EE CMOS MACH 4 family. This device has approximately 25 times the macrocell capability of the popular
PAL22V10, with significant density and functional
features that the PAL22V10 does not provide.
The MACH465 consists of 16 PAL blocks interconnected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central
switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins.
The MACH465 has macrocells that can be configured
as synchronous or asynchronous. This allows designers
to implement both synchronous and asynchronous logic
Publication# C17470 Rev. A
AmendmentlO
...1;.;;.;ss;.;;.ue;;..D;;;.;a;;.;;te;.;..:..;;.Ju;;.;.n;.;;.8..;.;19;.;;.9;;..3_ _ _ _ _--'
together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH465 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as O-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The registertype decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make Significant design changes
while minimizing the risk of pinout changes.
This document contains Information on a product underdevelopment at Advanced Micro Devices. Inc. The information
~r~~~~d!1t~~~e~~:. evaluate this product. AMD reserves the right to change or discontinue work on this proposed
3-33
~
AMD
CONDENSED
BLOCK DIAGRAM
I/O
110
ClKII
110 L l - - - -.....
110 ~l-------------------~
110 C J - - - - - - - - - - - - - - - - - - ,
I/O L l - - - - . . . ,
1/0
110
~---_C:l
1/0
~--------------~
110
r------------------~ 110
.------L::::l 110
110
1/0
1/0
C17470A-1
3-34
MACH465-15/20
4
GENERAL INFORMATION
Inside AMD's CMOS PLD Technology ......................................... 4-3
Military PAL Devices ...................................................... 4-43
Military ProPAL Devices .................................... . . . . . . . . . . . . . .. 4-52
Electrical Characteristic Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-54
fMAX Parameters ......................................................... 4-57
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-58
General Information
4·1
~
4·2
AMD
General Information
t1
Inside AM D's CMOS PLD Technology
Advanced
Micro
Devices
Application Note
by Bryon Moyer, Applications Manager, Advanced Micro Devices, Inc.
TECHNOLOGY DESCRIPTION
The EE5 process is similar, except that Left is 0.65 J..Lm.
The EE CMOS technology used by AM D in programmable logic is a single-poly, double-metal n-well process. It
has been optimized for high-speed programmable logic
devices, which do not have the same density constraints
that memories have. The basic characteristics of the
EE4 process are:
CMOS PLDs use standard CMOS logic internally, with
the addition of a programmable array. The output buffers of most devices are designed to be compatible with
TTL circuits, and therefore have n-channel enhancement pull-up transistors. Exceptions to this are the zeropower devices and the PALCE610H-15, which have
rail-to-rail switching outputs provided by a p-channel
pull-up in the output buffer.
•
CMOS, n-well
•
Grounded substrate
•
Single-poly, dual metal
•
1.2 J..Lm minimum feature
•
0.8 J..Lm gate length (Lett)
•
180A gate oxide thickness
AMD's CMOS process for programmable logic is simplified by the absence of standard depletion-mode
transistors in the more advanced processes. Depletion
mode transistors are a vestige of NMOS design, and are
not really needed. This results in the elimination of a
mask and implant step, reducing the process cost and
simplifying the structure.
•
90A tunnel oxide thickness
•
1.4 J..Lm contact dimension on wafer
•
3.2 J..Lm metal 1 pitch
•
3.8 J..Lm metal 2 pitch
Transistor Cross-Section
Fi~ure 1 shows a cross-section of a basic inverter. This
is a very straightforwa.rd structure. The gates consist of
poly-silicon; the other connections are made with metal.
Out
In
n-well
p-5ubstrate
16507A-001A
Figure 1. CMOS Inverter Cross-Section
Substrate Voltage
There are two basic substrate configurations for CMOS
PLDs: grounded substrate and floating (or negative)
substrate, as shown in Figure 2. In the first case, the
substrate is connected to ground; no voltage on the chip
Publication# 16507 Rev. A
Issue Date: February 1993
Amendment/O
is more negative than ground. The substrate is directly
hard-wired to the ground pin. In the second case, the
substrate is capacitively coupled to ground. A charge
pump pumps the substrate to a negative voltage,
typically -3 V.
4-3
~
AMD
Input pin
Ground
Thus the· negative substrate has no practical advantages over a grounded substrate, and lacks the
advantages of a grounded substrate. For this reason,
none of AMO's CMOS PLOs use a negative substrate.
Erasable Technology
16507A-002A
a.
n
in
roundin
Any erasable CMOS technology is based upon the
concept of stored charge. The charge is stored on a
transistor with a floating gate-that is, a gate that has no
connection. The transistor actually has two gates: one
that floats, and 0 ne that acts as a control gate. The control gate is used to establish the field across the floating
gate (see Figure 3) .
.. Flo-a-,ti-ng-::......"S-u.,....bs-tr-a--'teL.........,
16507 A-003A
~I
0
b.
Figure 2. Substrate Configurations: a. Grounded;
b. Floating
Control Gate
Floating Gate /
AMO's CMOS process uses a grounded substrate. This
16507A-004A
means that no large charge pump is used to pump the
substrate negative. This technology has several beneFigure 3. Floating-Gate MOS Transistor
fits. Providing effective clamp diodes is easier if the
substrate is grounded; this helps protect against
negative overshoot. A grounded substrate permits
In the programmed state, there is a net deficit of elecquieter operation on boards where the oscillation of a
trons in the floating gate. The resulting positive charge
charge pump can radiate and disturb sensitive circuits.
turns the transistor ON. In the erased state, there are
Also, this approach permits the design of zero-power
enough electrons on the control gate so that the
_ _ _ Rarts that w()LJ!d rlott?_~ p_~~It>.I_~_!t~~harge pump were
negative charge turns the transistor OFF.
constantly running.
-- ---------=-----------------There are two basic ways of transferring the charge onto
the floating gate: a) hot electron injection, and b) tunnelA negative substrate is sometimes used to get speed,
ing. Electrically erasable devices rely on tunneling; howand also makes it more difficult to induce latch-up by
making the substrate more negative than any board
ever, it is useful to compare these two methods.
voltage. However, latch-up is generally an issue only
during power-up on standard boards with standard logic
UV-Erasable Technology
Hot electron injection is used for UV-erasable devices,
drivers. While the device is powering up, the device is
most vulnerable to latch-up because of the many transuch as EPROMs. With this scheme, a bias is set up
between the source and drain of the transistor, and
sients occurring. However, it takes time to pump down
the substrate, so the substrate cannot immediately probetween the control gate and the substrate (see
Figure 4). The channel is pinched off, and a strong curtect against latch-up. This means that the negative
rent flows. Because of the high fields, the electrons are
substrate approach provides no latch-up protection at
hot. The two fields (source-to-drain, and substrate-tothe time when latch-up is most likely.
control-gate) combine to form a field in a diagonal direcThe only signal excursions into negative territory during
tion, but because of the oxide barrier, electrons cannot
cross in that direction. Occasionally, electrons acquire
normal operation will be from overshoot, and overshoot
enough energy to cross the barrier in the shortest direccannot induce latch-up because there is not enough energy. Negative overshoot is discussed in more detail
tion: from the channel to the floating gate. This is
below.
referred to as hot electron injection.
4-4
Inside AMO's CMOS PLO Technology
AMD~
Oxide Barrier
I
Pinched-Off Channel
Depletion Region
p-substrate
16S07A-OOSA
Figure 4. Programming by Hot-Electron Injection
Figure 5 shows the energy band diagram for the gate/
channel interface. Because the fields give the electrons
more energy, more electrons can cross the oxide
barrier. The height of the barrier determines how easily
charge can be transferred across.
Once an electron is on the other side of the oxide, it is on
the floating gate, with no path. It is therefore effectively
trapped, and remains there. During programming, large
fields are set up so that a significant number of electrons
are injected.
manufacturing, limiting the amount of extra quality that
can be provided by the erasability feature.
Electrica"y Erasable Technology
Electrically-erasable devices use Fowler-Nordheim
tunneling as the mechanism for getting charge onto the
floating gate. This is defined roughly as tunneling that
occurs as a result of a field placed across the barrier that
the electrons tunnel through.
Erasing these devices requires exposure to ultraviolet
light. The energy from the ultraviolet light causes the
electrons to cross back over the oxide barrier, erasing
the device. Forthis to happen, the device package must
have a window that lets the ultraviolet light pass through.
Some amount of direct tunneling, or tunneling that occurs without an applied field, is always possible through
any energy barrier. It may be extremely small or significant; the determining factor is the width of the barrier_
Since tunneling electrons are going through the barrier
instead of over it, the height ofthe barrier does not affect
the amount of tunneling.
UV-erasable technology has a few distinct drawbacks.
The fact that the parts require a window to be erased
makes the devices much more expensive. Although
they are usually available in plastic one-timeprogrammable (OTP) packages, they are then not erasable, and have no advantage over fuse technology. In
addition, windowed devices take about 90 minutes to
erase. This limits the number of times that the device
can practically be reprogrammed and tested during
For an electrically-erasable cell, the tunnel oxide is
about one third the thickness of the oxide of a UVerasable part; therefore tunneling occurs at relatively
low fields. Even so, the field used to cause tunneling is
about five times the field used to cause hot-electron injection for UV parts. Note that tunneling is theoretically
possible on a UV part, but a very high field is required,
and the normal electron injection would swamp out any
tunneling that would occur.
Inside AMD's CMOS PLD Technology
4-5
~AMD
;,,--------------.
-Electron Energy
Distribution
Barrier
Height
,/
~\//
Oxide
Barrier
>~
Substrate
Floating Gate
Q)
\
c
\
W
\
\
\
\
\
\
\
\
\
\
\
\
,,
\
,
16507A-OOSA
a.
!
Electron Energy
Distribution ~
,~
I ~
,/
/,/
" ' " \\"\\\\\\\
---------~
--Substrate--
"Hot"
~ Electrons
Oxide
Barrier
---- -
~ ------------------------~
C
\
W
\
Floating Gate
16507A-007A
b.
Figure 5. Energy Band Diagrams: a. Neutral Floating Gate; b. Hot-Electron Injection
Fowler-Nordheim tunneling involves placing a potential
across the barrier, which distorts the band diagram as
shown in Figure 6. The "angle" caused by the applied
potential effectively thins part of the already-thin barrier,
making tunneling easier. It is this tunneling under bias
that is used to program electrically-erasable devices.
Note that by reversing the bias, the tunneling can occur
just as well in the opposite direction. This is what makes
electrical erasure possible.
4-6
Electrical erasure has advantages over UV erasure both
in cost and quality. Because the erasure is electrical, no
expensive window is required in the package. This
makes erasability cost-effective even in high-VOlume
production quantities. In addition, the fast erasure allows AM D to reprogram the device many times, allowing
many more paths to be tested than can be tested in a UV
part. This provides much higher quality, especially in
higher-density devices.
Inside AMD's CMOS PLD Technology
AMD~
Minimal Intrinsic
________ (Direct) Tunneling
Tunnel
Oxide
Barrier
>.
~
Electron Source
Floating Gate
Q)
(Neutral)
c:::
W
16507A-008A
a.
Narrower Barrier;
_________ More Tunneling
eElectron Energy
e-
DiSlribUtiOn~!/
."
Tunnel
Oxide
Barrier
>.
~
Electron Source
Q)
c:::
W
Floating Gate
(Uncharged)
16507A-009A
b.
Electron Energy
DiSlribUtiOn~("/
>.
Reversible
Tunneling Direction
,:
Tunnel
Oxide
Barrier
~
Floating Gate
(Charged)
Q)
c:::
W
Electron Source
16507A-Ol0A
c.
Figure 6. Energy Band Diagrams: a. Direct Tunneling; b. Fowler-Nordheim Charging;
c. Fowler-Nordheim Discharging
Inside AMD's CMOS PLD Technology
4-7
~
AMD
In addition to speed, there are a number of other benefits to this approach. At the most basic level, this
eliminates a poly-silicon layer, simplifying the process.
This reduces costs and improves reliability.
Cell Configuration and Programming
The programming cell is shown in Figure 7. To improve
device speed, the programming cell has been divided
into the programming portion and the data path portion.
- - Program Line
- - - - - Read Line
WordLine _ _
- - - - - Read Transistor
Electron Source - - - - - - - 1
Control Gate _ _
o--~~~~--------~
- - - - - Sense Transistor
- - - - - Source
Floating
Gate
16507A-011A
a.
Program
Word
Line
Program
Transistor
Word
Tunne
Electron
Source
0sX~idleIF~lo~at~in~lgIG~a~te?;;;2D2D5i~I[I~::::::
Read
Line
Floating Gate
Program
Junction
Control Gate
Sense
Transistor .
Read
Transistor
16507A-012A
b.
Figure 7. EE PLD Programming Cell: a. Circuit; b. Cross-Section
The programming half requires long-channel transistors
capable of sustaining high electrical fields; the data path
requires short-channel transistors that are fast. Note
that this does take more space, but in PLDs, the size of
the cell is not a limiting factor as it is. in memories. In a
PLD, the programming array can take up as little as 10%
of the die area, while a memory typically uses more than
90% of the die area for the programming array.
Programming and erasure are complementary procedures in EE technology. However, the sense of programming and the sense of erasing are perhaps
opposite to what one might assume. A cell is considered
to be programmed if there is a charge deficit on the float4-8
ing gate, providing a positive voltage; it is erased if there
is excess charge on the floating gate, generating a
negative voltage. This means that programming a
device only requires turning ON those cells that are
needed, ratherthan turning off all of the cells that are not
needed.
A cell fresh from wafer fabrication has no net positive or
negative charge on the gate. To balance the threshold of
the transistor for reliable turn-on and turn-off, a cell
imp/antis used to center the threshold voltage near 0 V.
Programming and erasing involve either removing electrons from the conduction bands of the poly-silicon gate
or adding excess electrons, providing a net charge that
Inside AM D's CMOS PLD Technology
AMD~
will move the gate voltage solidly on one side or the
other of the threshold voltage.
When programming or erasing the device, a voltage is
applied between the program and control gate nodes.
The direction of the voltage determines whether the cell
is erased or programmed.
When erasing, the control gate is given a positive voltage, and the program node is grouncled. This attracts
electrons from the program transistor across the tunnel
oxide to the floating gate, turning the read transistor
OFF (see Figure 8a).
+
~:
When programming the cell, the program node voltage
is elevated, and the control gate is grounded, reversing
the electron flow, as indicated in Figure 8b. Enough
electrons flow off the floating gate to leave a net positive
charge; this turns the transistor ON.
AMO has modified the programming cell to increase
programming efficiency and has a patent on the resulting circuit. On traditional devices, the source node is
grounded during programming. On AMO's devices, the
source node is raised to the same potential as the control gate, as shown in Figure 9. This increases the
coupling ratio of the cell. The coupling ratio is the percentage of the applied field that appears across the
tunnel oxide. When the source is grounded, the field
across the tunnel oxide is reduced (since there is another capacitor in parallel with the tunnel oxide). By raising the source voltage, more of the field is available for
programming. The coupling ratio can therefore be
thought of as a measure of the programming efficiency;
since the efficiency is higher, lower voltages are
required for programming.
ty_ @~
@\J @
16507A-013A
a.
+
+
16507A-01SA
Figure 9. Source Is at Same Potential as Control
Gate to Improve Coupling Ratio
16S07A-014A
b.
Figure 8. Cell Biasing: a. Charging;
b. Discharging
The split-cell configuration also allows a simpler programming algorithm, since the programmer can take
advantage of the self-limiting nature of programming
and erasure. The split cell places the read cell gate and
the floating cell gate in "parallel" with each other. Therefore the floating cell can be either completely charged
(with a net excess of electrons) or completely discharged (with a net deficit of electrons, or an excess of
holes), as shown in the energy diagrams in Figure 10.
This is simple to do, since the electrons that have
crossed the barrier set up a field that opposes further
tunneling. As more electrons cross the barrier the
opposing field grows strong enough to block more
Inside AMD's CMOS PLD Technology
4-9
~
AMD
electrons from tunneling (Figure 11). Regardless of the
state of the floating cell, the select line will turn on or off
the read transistor; the cell will only be read, however, if
both the read transistor and the the floating transistor
are ON.
Built-in
~Field
m..... --------EJ
/Electrons
Trapped
o
o_\J00
Tunnel
Oxide
Barrier
>~
CD
[f;\
00
fo:\0
0
~ 0
000
Floating Gate
Electron Source
c:
UJ
16507A-016A
a.
Built-in
/'-Field
EJ-------·m
Tunnel
Oxide
Barrier
>~
Electron Source
CD
c:
Floating Gate
UJ
16507A-017A
b.
Figure 10. Stable EE Cell: a. Charged (Erased); b. Discharged (Programmed)
4·10
Inside AMD's CMOS PLD Technology
AMD~
~ Applied Programming Field
E1--------~1±l
~ Built-in Field Growing
I±l.------- E1
Tunneing Electrons __________
Tunnel
Oxide
Barrier
>.
~
Trapped
~Electrons
~
Electron Source
Q)
0 0 00 ®
o ® ® ®®
c
W
Floating Gate
16507A-018A
a.
I
~
/
No Net Field;
Programming Stops
O~------;....+--
-----.
Time
Applied Field
16507A-019A
b.
Figure 11. Self-Limiting Programming and Erasure: a. Energy Band Diagram; b. Fields vs Time
In standard one-transistor cells, the two gates are actually in "series". If the floating gate is charged, then the
transistor is OFF, regardless of the state of the select
line. In order to read the cell, the floating gate has to be
neutralized so that the select line controls the transistor
(Figure 12). If the floating gate were completely dis-
charged, then the transistor would be ON regardless of
the state of the select line. The programming algorithm
is therefore more complicated, since the amount of
charge removed must be monitored to ensure that just
enough charge is removed to neutralize the floatinggate.
Inside AMD's CMOS PLD Technology
4-11
~
AMD
Net Electron
/SurpIUS
Oxide
Barrier
o
®/
(OJ
® ®®-191 ®
0®® (!)0
Substrate
Floating Gate
16507A-020A
8.
/Charge
No Net
Oxide
Barrier
Substrate
Floating Gate
16507A-021A
b.
Figure 12. UV Cell: a. Charged (Programmed) State; b. Neutral (Erased) State
Array Configuration
The discussion above focused on individual cells. These
cells must be hooked together to form a complete array
that is driven by input lines and drives product terms.
There are two configurations used in AMD's EE CMOS
devices (see Figure 13). The configuration in Figure 13b
provides some benefit because the parasitic capacitor
does not couple the input line and the product term, but
both approaches are actively used in designs.
Bit Line
~'
i'---ll
~'
Input Line ol---...
i'---tl
Input Line o - - -...
Floating Gate - - - -
Floating Gate - - - Bit Line
16507A-023A
16507A-022A
a.
.
b.
Figure 13. Two Array Configurations: a. Bit Line at the Drain; b. Bit Line at the Source
4·12
Inside AM D's CMOS PLD Technology
AMD~
PROGRAM INTEGRITY
Reliable programming of PLDs requires the use of wellcalibrated, quality programming equipment. To ensure
that the device is correctly programmed, the correct voltages and times must be applied.
As discussed above, it is impossible to over-charge or
over-discharge the programming cell since the mechanism is self-limiting. This provides more leeway and
makes the programming algorithms less sensitive to
programmer variations. This ultimately provides higher,
more consistent programming yields under real-life
production programming conditions.
However, if the cell is under-programmed or undererased, an insufficient amount of charge might transfer
onto or off of the floating gate. When programming, this
might not turn the read cell ON sufficiently, potentially
slowing down the device. In the case of erasure, the
read cell might be partially ON if it is not completely
erased. This may cause "disconnected" inputs to appear partially connected. Thus it is important to ensure
that the programming pulsewidths are long enough to
provide adequate programming.
If the programming voltages are slightly inaccurate,
CMOS devices often can still be programmed correctly.
However, excessive voltage might cause device damage if breakdown voltages are exceeded. Extremely low
voltages might fail to engage the programming circuitry
completely.
date, we certify programmers that meet strict criteria for
all products through our FusionPLDsM program. AMD
guarantees the performance of any device when programmed on an approved programmer .. For a list of
FusionPLD partners, please refer to the FusionPLD
Catalog.
Data Retention
In an electrically erasable device, the floating cell is programmed by forcing electrons to tunnel through the
tunnel oxide into the floating gate. Ideally, these trapped
electrons mean that the device remains programmed indefinitely. Actually, the charge cannot remain indefinitely, but its lifetime is normally extremely long. The
stability of the program charge is called data retention;
that is, the ability of the device to retain its charge as
programmed.
There are two basic leakage mechanisms: direct tunneling and thermal leakage. These mechanisms occur independent of whether the cell was programmed by
electron injection or tunneling. The amount of direct
tunneling is a function of the potential across the tunnel
oxide, and is generally very low. Leakage is normally
dominated by thermal charge decay.
On one side of the energy barrier, there are electrons
with a distribution of energies (see Figure 14). Some
have enough energy to escape over the top of the barrier. As the temperature is raised, more electrons
achieve the energy required to overcome the barrier.
Because of the need for accurate programming, and for
ensuring that the programming algorithms are up-to-
Thermal Leakage ________
.
.
________
Direct Tunneling
'0
?a\~\e\\...
Trapped Electron
-------- 0 \\ ~EnergY Distribution
Tunnel
Oxide
Barrier
Electron Source
\
\,
,
,,
,, ,
,
,,
,, ,
,,
,,
,,,
,
,,
,,
Floating Gate
16507A-024A
Figure 14. Data Loss Mechanisms
Inside AMD's CMOS PLD Technology
4-13
~AMD
The tendency of the gate to leak can be modelled as an
Arrhenius function, which means the formula forthe programming "decay time" td has the form:
where
Ea is the intrinsic activation energy
T is the temperature in Kelvin
k is Boltzmann's constant
K is a scaling constant.
If we can measure the rate at two known temperatures,
then:
tdl
KeEa/kTl
td2
Ke
E
a/kT2
Note that the constant K drops out, so we need not be
concerned with it's specific value. From this we find that
Ea =
T21ntdl - Tllntd2
kT1T2
This lets us measure Ea, which should be constant for a
given process. The higherthe value of Ea, the longerthe
decay time will be. This is because Ea roughly represents an energy "barrier" that must be overcome for an
electron to leak away. The higher the barrier, the fewer
electrons have the energy to overcome Ea.
Charge leakage can be aggravated by poor quality tunnel oxide. Defects in the oxide provide a lower energy
path for discharging, effectively lowering Ea. Baking a
device accelerates this leakage, and identifies devices
with weak oxide. AM D uses a bake for all EE products to
ensure that the production devices have a high Ea and
therefore good data retention. The average Ea for all devices, including those with weak oxide, is about 0.8 eV.
After eliminating the weak devices by a 250°C 24-hr
bake, the average Ea is about 1.8 eV.
Data retention time depends on the temperature to
which the devices are exposed. The higher the temperature, the shorter the decay time because the electrons
have more energy, and more can leak off the gate.
There are two temperatures that may be of concern for
different reasons: the maximum device storage temperature (150°C) and the maximum operating
temperature (125°C for military). In the first case, the
idea is to know that if a programmed part sits on a shelf
for some period of time before being used, that the program will remain intact forthat time. The second case is
intended to give an idea of how long a device will remain
operational in-system.
Using the equation above to solve for the decay time at
these temperatures, the result is several decades forthe
4-14
storage temperature, and even longer for the operating
temperature. For room temperature, the exponential nature of the function makes the decay time increase to
centuries.
AMD specifies 10 years at the maximum storage temperature (an industry standard for EPROMs and
EEPROMs), and 20 years in-system under worst-case
military conditions. That the calculated numbers are so
much higher builds confidence in the numbers specified. In general, the typical end-of-life failure mechanisms that affect all devices (and which are unrelated to
the EE cells) will cause device wear-out before the
program data is lost.
The integrity of the charge in the electrically erasable
cell also stands up to any electrical fields that exist in
surrounding equipment. For charge to be transferred
off, or onto, the floating gate, a field must be placed
across the oxide. Such a field cannot be generated outside the programming mode; an external field, no matter
how strong, cannot set up the programming mode.
The charge might also be pulled through some other
oxide if the field were large enough. However, to remove
the charge through anything but the tunnel oxide
requires an external field so high that the rest of the device would break down before any cell charge were ever
lost. This would occur on any device, programmable or
not. Therefore any external field strong enough to
remove charge from a floating cell will destroy the rest of
the device first.
Cell Endurance
Anotherfactorthat affects data retention in the long term
is the cell endurance. The endurance is the number of
times the device can been erased and reprogrammed.
Over time, the oxide can wear out, resulting in a gradual
reduction in Ea. This occurs as defects are created in the
oxide. These defects trap electrons; these electrons
then oppose the field that is required for programming.
Given enough trapped charges, the established potentials will be insufficient for programming. This typically
happens after hundreds of thousands of reprogramming
cycles.
The ability to charge up a cell with good data retention
can be measured by the margin voltage. This is the voltage that must be applied to the control gate to counteract the charge on the floating gate. If the gate is highly
charged, a larger margin voltage is needed to overcome
the charge. Thus, put simplistically, a higher margin
voltage indicates beUer cell charging.
Figure 15 illustrates measurements of the margin voltage as the number of program/erase cycles is
increased. By 100,000 cycles, the margin voltage still is
greater than 4 V; for the cell to fail, the margin voltage
must fall to below about 1 V.
Inside AMO's CMOS PLD Technology
AMD~
5.0
4.5
~ 4.0
.r=
->
3.5
3.0
10
1000
100
10000
# Cycles
100000
16507A-025A
Figure 15. Cell Endurance: Margin Voltage Solid After 100,000 Program/Erase Cycles
For EEPROMs, which often are reprogrammed
in-system, it is important to know how many thousands
of times the device can be reprogrammed. However,
most EE PLDs are not intended to be programmed insystem, and probably are programmed very few times.
Most production units are programmed only once by the
user. Prototypes might be programmed tens of times at
most. Therefore we specify a maximum number of
100 erase/reprogram cycles.
This does not imply that the devices are weaker than
EEPROMs; it is just that more extensive testing would
have to be done to justify specifying a larger number.
Since this larger number is not needed, a cost savings is
realized because of the test simplification. Note that the
devices are actually programmed hundreds of times in
testing before they are shipped out, giving outstanding
programming and functional yields; however, the number of erase/reprogram cycles specified refers only to
programming done by the user.
DEVICE CHARACTERISTICS
Power Dissipation
CMOS technology is associated with low power, and indeed, all CMOS PLDs provide lower power than their
bipolar counterparts. However, most PLDs do not provide the zero-standby power that standard CMOS logic
parts provide.
The basic CMOS inverter lowers operating power because at any given time, only one of the two transistors
can be fully ON. The other is OFF and blocks the flow of
DC current. Thus, when the device is in a stable state,
no current can flow. While the device is switching, both
transistors are partially ON, allowing for a transient
current spike. Thls means that power is consumed only
when the device switches. Because a spike occurs for
each transition, the average power consumption is affected by the frequency of operation (see Figure 16).
This type of circuitry is found throughout most of a PLD
circuit. However, one portion of the PLD circuit does not
use a standard CMOS inverter: the programmable array. One of the necessary elements of zero-power
operation is that the output of the inverter have a voltage
swing from ground to Vcc, so-called rail-fa-rail operation. In the array, such a wide swing makes the
propagation delays too long. To speed up the device,
the sense amps that determine the state of a product
term are designed to have a much more limited swing.
This means the sense amps are constantly drawing
power, even when not switching. These are the half- and
quarter-power CMOS PLDs; their power consumption is
still less than that of a bipolar PLD. Since most CMOS
PLDs are used in TTL sockets, the CMOS PLDs work
well.
For designs that require the absolute lowest-power operation, the half- and quarter-power CMOS PLDs are
inadequate. Zero-power PLDs have been designed to
address this range of applications. These devices operate by turning off the sense amps in the array if no
signals switch for a period of time. If the transition detectors at the inputs indicate that some Signal is changing,
then the array is activated to process the incoming data.
In this manner, the average operating power consumption can be reduced, especially at low frequencies, and
the standby power consumption is negligible (less than
15 ~). The only penalty is a small wake-up delay of a
few nanoseconds.
Inside AMD's CMOS PLD Technology
4-15
~AMD
Vee
+
LC
Vout= LOW
-
16507A-026A
The output load can have a dramatic effect on power
dissipation, especially on devices that have many I/O
pins. For an output driving a purely capacitive load, the
power dissipation contributed by the load for one output
is determined by the load capacitance, the frequency at
which the output is switching, and the output voltage
swing (Vs). The output stage will go through a process
of repeatedly charging and discharging the capacitor.
Although the direction of charge flow reverses itself
every other transition, the relative voltage change does
too, so that the power contribution is the same for a
charge and a discharge.
If we consider the case of charging the capacitor, we will
be placing a charge QL on the capacitor that is determined by
a.
Vee
OL = CLVO
whereCL is the load capacitance and Vo is the output
voltage. The current contribution from this is
i
Vout = HIGH
dOL
- dt
dVo
=CL-
16507A-027A
dt
In one half the output transition period tp, the change in
output voltage will be equal to the output swing Vs. This
means that
b.
i
=CL~
tp
2
=2CL~
HIGH
tp
Vout
=2CL Vsfo
LOW
where fo is the frequency at which the output is
switching.
Power
Dissipation
o
16507A-028A
The power dissipation is the product of the current and
the voltage. Since the voltage is changing during the
time that the power is being dissipated, we can approximate by dividing the voltage swing by 2. This gives
P =iv
c.
Figure 16. CMOS Inverter Power Dissipation:
a. VOUT Static LOW; b. VOUT Static HIGH;
c. Dynamic Power Dissipation
=
=
Icc VS VI and Loading
The greatest external contributors to Icc are the input
HIGH level (VIH) and the output load.
As the VIH drops from its ideal level of Vcc, the inverter
starts to draw current. The worst case scenario would
be a VIH at the minimum of 2.0 V, which could contribute
some 5 rnA per input buffer to the power consumption.
4-16
Vs
=2CL vsfoT
2
=2CL V sfo
This means that for a 100-output device (PLD or any
other device) with each output driving 35 pF loads,
where the output swing is 3 V and the output frequency'
is 50 MHz, the power dissipation contributed only by the
load will be about 1.6 W regardless of the power dissipation of the chip itself.
Icc vs Frequency
The operating current increases with frequency for both
standard and zero-power CMOS devices. The
Inside AMD's CMOS PLD Technology
AMD~
device typically draws less than 10 J.1A. Figure 17 shows
typical curves for standard and zero-power devices.
difference is the current at low frequencies. A standard
device typically can draw 35 rnA at 0 MHz; a zero-power
100
50
o
4
8
12
20
16
24
Frequency (MHz)
16507A-029A
a.
110
90
70
50
30
Unear
10
--------- ----- -- ------- --------- -- ---------------- ------ -- -----Log
0.1
Log
0.01
Unear
-+----+----+-----+----+----+---+--+----1
0.1k
1k
10k
100k
1M
10M
Frequency (Hz)
30M
50M
70M
16507A-030A
b.
Figure 17. Icc vs frequency: a. Half-Power Device; b. Zero-Power Device
Inside AMD's CMOS PLD Technology
4-17
~AMD
All but the PALCE16V8 and PALCE20V8 have their Icc
specified at 0 frequency (that is, DC). For compatibility
with existing specifications, the 16V8 and 20V8 have
their Icc specified at a frequency level: 15 MHz for
devices with tpo of 15 ns or slower, and 25 MHz for
10 ns, 7.5 ns, and faster devices.
Icc vs Number of Product-Terms
The number of product terms switching can sometimes
affect Icc. On standard devices, however, the design of
the particular sense amp determines whether the Icc will
increase or decrease with more product terms. therefore it cannot be predicted in general. From a practical
standpoint, the change in Icc due to different numbers of
product terms is negligible.
AM D's zero-power devices have been designed with a
product-term power-down feature that turns off those
product terms not being used. The graph in Figure 18
shows the effects. Because these devices are intended
for low-power and battery-operated use, the substantial
extra power savings can significantly help extend the
time between battery charges.
110
100%50%-
90
25%-
70
50
30
<'
.s
Linear
10
Log
~
0.1
Log
0.01
Linear
-;----+---+---+----+---+---+---1----1
0.1k
1k
- Percent of product terms used
10k
100k
1M
10M
30M
Frequency (Hz)
SOM
70M
16507A-031A
Figure 18. PrOduct-Term Power-Down on Zero-Power Devices
Icc vs Temperature
The amount of current drawn by a device depends on
how much current can pass through the transistors.
Simplistically speaking, the channel of a transistor can
be modelled as a resistor. The resistance is affected by
temperature, since temperature affects the mobility of
electrons. The hotter the device is, the more the molecules are vibrating around, and the harder it is for
electrons to pass through without a collision with a mole4-18
cule; that is, electrons are less mobile in a hot device.
This means that the resistance of the channel is higher,
which in tum means that the device conducts less
current. Therefore Icc is greatest when the device is
cold, and is minimized when the device is hot. A typical
curve is shown in Figure 19. This curve has been
generalized by normalizing the current to the room
temperature current.
Inside AMD's CMOS PLD Technology
AMD~
+20%
+10%
~
O~----------~--=-------~--------~~--------~
80
20
-10%
Temperature (OC)
-20%
16507A-032A
Figure 19. Icc vs Temperature, Normalized to Room Temperature
2
Icevs Vee
P
The variation of Icc with changes in Vee should come as
no surprise; as Vee increases, so does Icc. This means
that the power consumption actually increases roughly
as the square of Vec, since power consumption can be
expressed as
=
Vee Icc
v cc
= Reff
.
where Reft is defined as i~~ This is a simplification, of
course, since Ref! is non-linear, and varies with Vee. A
typical Icc vs Vee curve is shown in Figure 20.
30
20
10
0~--~~--~--~----4---~----4----+--~
o
2
4
6
Vcc(V)
8
16507A-033A
Figure 20. lee vs Vee
Inside AMD's CMOS PLD Technology
4-19
~
AMD
Input/Output Structures
Newer devices have pull-up resistors as shown below.
In these devices, there is also a transistor in series with
the resistor.
The basic input and input/output structures are shown in
Figure 21. The ESD circuits and the programming
voltage detection circuits will be discussed in more
detail later.
Vee
Vee
>50kn
ESD
Protection
and
Clamping
Programming -=Pins Only
----- -- --- -- --- ---- -16507A-034A
a.
Vee
Vee
> 50 kn
[~
Provides ESD Protection
and Clamping
Preload
Circuitry
Feedback
Input
16507A·035A
b.
Figure 21. Equivalent Input/Output Schematics: a. Input with Pull-Up Resistor and Overshoot Filter;
b. Output with Pull-Up Resistor
4-20
Inside AMD's CMOS PLD Technology
AMD~.
I-V curves
Since the input is effectively a capacitor, the impedance
has no real component; the imaginary portion falls with
increasing frequency. A typical device has an input capacitance of 8 pF at 1 MHz. Assuming a capacitance
around 8 pF at higher frequencies, this yields a capacitive reactance of 2.5 KQ at 50 MHz.
Figure 22 shows a typical I-V curve for an input buffer.
Within the range of normal input signals, the input buffer
has extremely high impedance, with diodes and MOS
transistors that turn on when the input is below ground.
On higher speed devices, this has the effect of a highspeed diode capable of clamping negative overshoot on
noisy signals.
II (rnA)
20
2
3
4
5
-20
-40
-60
-80
-100
16507A-036A
Figure 22. I-V Curve for an Input with No Pull-Up Resistor
Inside AMD's CMOS PLD Technology
4-21
~AMD
Figure 23 shows typical 1-V curves for high and low TTLstyle outputs. The impedance of a low output is about
10 Q; a high output has an impedance of about 30 n.
The fact that the impedances are somewhat more symmetric than those found on a bipolar device makes it a bit
easier to terminate long traces accurately.
IOL(mA)
80
VOL (V)
-1.0
-0.8
-0.6
-0.4
.6
1.0
.8
16507A-037A
8.
IOH (rnA)
25
2
3
4
5
VOH(V)
-3
·2
-1
16507A-038A
b.
Figure 23. I-V Curves for 8 TTL-Style Output with No Pull-Up Resistor: 8. Output LOW; b. Output HIGH
4-22
Inside AMD's CMOS PLD Technology
AMD~
loaded to about 50 n when lightly loaded. The n-channel
impedance is lower, at about 10 n.
Figure 24 shows the curves for rail-to-rail switching outputs. The p-channel impedance, when the output is
HIGH ranges from 200 n when extremely heavily
IOL(mA)
+100
VOL (V)
-2
2
6
4
-100
16507A-039A
a.
10H (mA)
+10
VOH (V)
-1
2
3
5
-10
-20
-30
-40
-50
16507A-040A
b.
Figure 24. I-V Curves for a CMOS-Style Output: a. Output LOW; b. Output HIGH
Inside AMD's CMOS PLD Technology
4-23
~
AMD
Open Inputs
Newer devices have input pull-up resistors with a minimum resistance of 50 kil. When unused, these inputs
can be left unconnected. With older devices, an unused
input should be pulled HIGH or LOW. A floating input
may cause no trouble, but there are some potential
concerns.
First, if an input is floating with its voltage near threshold
(1.5 V for a TTL-style device), the input buffer can conduct tens of mA of current. This does not damage the
device, but must be calculated into the power budget. Of
course, as the input moves away from the threshold, the
current decreases. In a noise-free environment, any
floating inputs will generally tend to drift to ground.
The second concern is the fact that the environment is
not usually noise-free. The unused input is not directly
connected to any internal logic, so there should be no
interference between the input and the other logiC. However, if there is noise on an unused input floating near
threshold, internal noise could be generated should the
input buffer start to oscillate. This could disturb some of
the surrounding circuitry as well as the internal ground,
compounding the problem.
On a device without pull-up resistors, an unused 1/0 pin
can be pulled HIGH or LOW by programming it as an
output with constant value 1 orO. The output buffer itself
then acts as the pull-up or pull-down.
Output Drive vs Temperature and Vee
The output drive varies with the temperature just as Icc
does. As the temperature increases, electron mobility
decreases, cutting the drive. Likewise, the drive increases as the temperature decreases. For example, at
75° IOL decreases by about 18% from its room temperature value; IOH decreases by about 7%.
The drive also varies directly with Vee, although the effect is most pronounced on IOH; it increases by about
18% when taken from 5.0 V to 5.25 V. Because a low
output transistor is already ON hard, the little extra bit of
drive that its gate gets as Vee goes to 5.25 V only
increases IOL by about 3%.
There is no explicit current-limiting resistor on the pullup. The resistance of the pull-up channel limits the
current. The fact that this resistance is smaller than what
one might find in a bipolar device contributes the the
more symmetric impedances, but also gives a higher
short-circuit current Ise. The slew-rate-limiting circuit
also limits the drive; slew rate limiting is discussed
below.
benchmark for confirming the guaranteed performance,
but as the application changes the conditions, the actual
system performance may change for the better or
worse.
AC Test Conditions
AC test conditions are sometimes treated differently for
CMOS than they are for bipolar. However, since most of
the CMOS products are designed to work in a TTL
environment, the test conditions that AMD uses generally are the same as those used for bipolar devices. The
resistor network is chosen to match the output drive levels, and the load capacitor is normally 50 pF. JEDEC recently changed the load standards from what had to
date been the industry de facto standard, but for TTL
parts this only affects the resistor values; a 50 pF capacitance is still part of the standard. Note that in the
JEDEC standard, the decision affecting which load to
use depends only on the interface level, not the technology. Thus a" parts intended to operate at TTL levels are
given the same load, whether bipolar or CMOS.
AMD has made two exceptions to the 50-pF load. The
first is forthe zero-power devices, which are designed to
operate at true CMOS levels. The JEDEC load standard
is different for these devices; it has a different resistor
network, and uses a 30-pF capacitor. The second exception is the MACH family: in this density range, a
precedent had been set at 35 pF, prior to the JEDEC
standardization. To be compatible with existing devices,
the MACH devices are measured with 35 pF loads.
tpo vs Temperature
Propagation delays decrease (that is, they speed up) at
colder temperatures for the same reasons that Icc increases. In general, devices at O°C operate about 15%
faster than those at 75°C.
tpo vs Vee
As Vee is increased, more power is available, and the
device can operate faster. However, the effect is less
pronounced than that of temperature. A device operating with a 5.25 V supply runs about 4% faster than one
running with a 4.75 V supply.
tpo vs Loading
The tPD increases as the device load increases, although much of this results from the increase in rise and
fall times of the outputs. For every 50 pF change in load,
roughly a 2- to 5-ns change in the rise and fa" time can
be expected. In addition, as the load increases, more
transient current is switched,. creating more internal
noise. This can slow the speed path inside the Chip.
AC Parameters
AC parameters vary with a number of conditions. The
data sheet specs pick one set of conditions that act as a
4-24
Inside AMD's CMOS PLD Technology
AMO~
Power-Up Reset
Power-up reset is a feature that forces a device to power
up into a known state. Without this feature, the power-up
state is not known. Power-up reset helps make system
initialization and testing simpler.
The ramp rate of Vcc is not critical to the power-up reset
function. However, there are two other requirements:
the supply ramp must be monotonic, and the clock must
be suppressed until power-up is complete.
(Figure 25). The danger in such glitches is that if the timing and voltage are just right, the registers themselves
may think that the device powered down temporarily,
causing them to lose their state. If the glitch is fast
enough, however, the power-up reset circuit may not
notice the glitch, and may think that everything is proceeding just fine. At the end, the registers may be in a
random state. Even if the power glitches low enough for
long enough to shut down all circuits, the power-up
timing must be restarted from the end of the glitch.
The monotonicity requirement basically says that there
should be no low-going glitches in the power-up ramp
T
,
Power OFF ~: .
Registers May Lose State
Time
,
: _____ Power Back ON
Reset Circuit May Not Restart
If Duration Short,
Reset Circuit May Not Notice
16507A-041A
Figure 25. Non-Monotonic Power-Up Can Cause Power-Up Reset To Fail
There is also a requirement that the clock not be running
during power-up (Figure 26a). If the clock is running
while the device is powered up, then, as different parts
of the device-and, indeed, the whole circuit boardturn on, parts of a single device, or different devices,
may be out of synchronization with each other
(Figure 26b). At some point, a part of a device will be ON
enough to start recognizing the clock. It will then start to
sequence as per the inputs it sees. If the inputs are not
stable, the sequence may not be correct. In addition, if
not all parts of the circuit or board recognize the clock at
exactly the same time, some parts will start cycling
before others, and the whole system will be out of
synchronization.
The ot~~r potential (although remote) problem with
clocking during power-up is metastability. If a register
powers ON in time to see the clock edge, its setup time
might have been violated, making the results at the output unpredictable.
Inside AMO's CMOS PLO Technology
4-25
~AMD
4V
Power
Vee
IIr
7
/ /I~
Registered ActiveLow Output
~
\\(,
Clock
-,L
J
16507A-042A
a.
~----Nominal
PartA----,
.. '
.
.. ' •• " - - - - - Part B
:.........
"
I
Time
Threshold
",
Part A
ON
Part A
: - Responds
To Clock
,
Part B
ON
Part B
i-Responds
, To Clock
,
~I~
If Too Short,
Metastability
Possible
16507A-043A
b.
Figure 26. Clocking During Power-Up Reset: a. Correct Operation; b. Free-Running Clock Places Part B
One Clock Cycle Out of Sync with Part A
4-26
Inside AMD's CMOS PLD Technology
AMD~
Powered-Down Characteristics
Some applications place the CMOS PAL device in a
situation where it is itself powered down, but it is driving
or is driven by other devices that are still powered up.
This is especially typical of devices that are talking
directly to a bus (Figure 27).
The characteristics of the device in such a condition
depend on how the power was removed. There are two
ways of removing power:
•
opening up the Vcc line (e.g., if Vcc is fused, and
the fuse blows; Figure 28)
,
•
grounding Vcc (Figure 29)
Bus - Powered Up
I
...--_ _-----' u u u u u
I
u u u u u'--_ _---,
I
I
PLD
Board - Powered Down
16507A-044A
Figure 27. Powered-Down Device with Active Inputs and Outputs
/
Blown Fuse
~~-------------y ~------------~)
les
16507A-045A
Figure 28. Power Down with Vee Open
Inside AMD's CMOS PLD Technology
4-27
~AMD
Vee Effectively
Grounded
I
1
16507A-046A
Figure 29. Power Down with Vee Grounded
16507A-047A
a.
Internal Current
External Current
I'
External Diode
Only Blocks
External Current
IC
On-Chip
Off-Chip
16507A-04SA
b.
Figure 30. Powered-Down Current Paths with P-Channel Pull-Up: a. Vee Grounded; b. Vee Open
4-28
Inside AMD's CMOS PLD Technology
AMD~
It is important to know whether, for a given device, there
is some kind of path from the pin to Vcc when Vee is
lower than the pin voltage. If any current can flow, it is
not necessarily catastrophic, but there can be some effect. If Vce is grounded, then there is a direct path to
ground for any current flowing from the pin to Vee
(Figure 30a). If Vce is open, then the only path from Vee
to ground is through the device itself, and through the
Vee lines of any other devices on the same Vec line
(Figure 30b). In the latter case, the pin is essentially
powering up the device(s) itself; realistically, it cannot
provide enough power to drive the chip, and this could
result in the pin being loaded down.
Most of AMD's CMOS PLDs have no such path when
powered down. Figures 31 and 32 show the I-V curves
of inputs and I/O pins while Vec is open and Vce is
grounded. Figure 31 is for TTL-compatible devices,
which have n-channel pull-ups on the outputs. Figure 32
is for the HC/HCT-compatible zero-power devices and
the PALCE610H-15, which have p-channel pull-ups.
8
6
14
2
0
o
2
4
6
0
2
4
6
VI (V)
16507A-049A
16507A-053A
a.
b.
Figure 31. Power-Down Characteristics of TTL-style CMOS Inputs and Outputs: a. Standard;
b. Older ESD Structure
14
12
10
10
8
8
<'
E
6
::;6
14
4
-=2
2
0
0
0
2
4
6
0
2
4
6
VI (V)
16507A-055A
a.
16507A-056A
b.
Figure 32. Power-Down Characteristics of CMOS-Style Output: a. Vcc Open; b. Vce Grounded
Inside AMD's CMOS PLD Technology
4-29
~
AMD
Note that for most of the TTL-compatible devices, there
is no leakage on the pins. This means that signals on a
pin are not affected by the powered-down device.
Therefore it can be safely connected to an active bus. It
also allows for safe hot insertion, where the device (or
the board that contains the device) is plugged into a
socket that has Vcc applied.
As a result of one of the ESO structures (which are discussed below), some devices do conduct some current
when Vcc is powered down (Figure 31 b). Newer devices do not have this characteristic.
With the HC/HCT-compatible devices, the input structures are the same as for TTL devices, but the outputs
conduct because of the p-channel pull-up. There is a
parasitic diode between the output and Vcc (Figure 33).
This can cause latch-up if the output voltage is higher
than Vcc. Thus it is not recommended that devices with
p-channel outputs be directly connected to a bus if the
device will be powered down while the bus is active.
Hot-insertion of these devices should also be avoided.
Output
p-substrate
16507A-057A
Figure 33. Parasitic Diode In CMOS-Style Outputs
DEVICE INTEGRITY AND ROBUSTNESS
The reliability of AMO's CMOS processes is documented in product and process qualification books. For
EE4 process products generally, the extended life FIT
rate is under 100 and declining. The rate for the devices
with 2000 hours burn-in is around 30; similar devices
with only 1000 hours burn-in have a FIT rate closer to
100. With more burn-in experience, the FIT rate will
decline even further due to the statistics used to calculate FIT rates. The FIT rate calculation is such that with
fewer burn-in hours, a lower confidence factor is applied, giving higher FIT rates on newer products even
when there are no failures.
ESO
Every pin on the devices is protected against electrostatic discharge (ESO), a formal name for static
electricity shocks. Output pins rely on the large output
drivers as protection. Inputs normally do not have large
drivers, so a circuit must be added for input protection.
These input protection circuits also provide clamping
against negative overshoot.
All new devices make use of the structures in
Figures 34a and 34c for ESO protection. Most input pins
4-30
use the circuit in Figure 34a. On pins requiring high voltages, the circuit has been modified as shown in
Figure 34c. Some older devices have the configuration
shown in Figure 34b. Because the active pull-downtransistor is not ON when Vcc is disconnected, it cannot
necessarily hold off the ESO transistors; this causes the
current seen in Figure 31 b. This circuit is no longer being used in new devices.
Noise Generation and Sensitivity
AMO's CMOS PLOs are designed with noise concerns
in mind. This affects both the amount of noise generated by the devices and the way in which the devices
react to externally-generated noise. As more is understood about the nature of system-level noise, new
design techniques are being used to make the devices
quieter and more robust.
Ground Bounce
Ground bounce occurs when many outputs simultaneously switch from HIGH to LOW. This occurs because
of the fact that CMOS devices generally have outputs
that switch very quickly. If left uncontrolled, ground
bou nce can make a device with many outputs unusable.
Inside AMD's CMOS PLD Technology
AMO~
Vee
Vee
r
r
Input
~----.-
-
16507A-058A
Output
- - Causes Ground Bounce
a.
16507A-061A
Vee
Figure 35.
Origins of Ground Bounce
Input
Vee
y
16507A-059A
Any output that is at a static LOW level maintains a VOL
with respect to the chip ground. If the chip ground is
bouncing with respect to the board ground, the LOW
output will track the moving chip ground and will also appearto bounce (see Figure 36). This is sometimes seen
as a glitch by the next device. Even if there is no output
glitch, instances of high ground bounce can slow the
performance of the internal circuits by temporarily starving them of power. In extreme cases, this can interrupt
the internal circuits.
b.
LOW Output
I
VOL
Vee
(/)
.g
Chip Ground
>
I
0
Input
Time
16507A-060A
16507A-062A
c.
Figure 34. ESO Protection: a. Standard;
b. Older Version; c. Supervoltage Pins
Ground bounce is generated by the natural parasitic inductance in the ground lead (see Figure 35). When a
large current surge goes through the inductor, the high
~ induces a voltage that puts the ground level on the
chip at a higher voltage than the ground level seen on
the board.
Figure 36. Symptoms of Ground Bounce
Excess ground bounce can be handled in two ways: by
limiting the amount of ground inductance and by reducing the ~ . Inductance can be reduced by improving
the configuration of the ground pin. On AM D's 28-pin devices with many outputs (PALCE24V10 and
PALCE26V12), the ground pin has been moved from
Inside AMO's CMOS PLO Technology
4-31
~AMD
of the overshoot, and reduces or eliminates ringing.
Figure 39 shows the ESD protection circuit used on
most input pins. Parasitic p-n junction diodes exist between the substrate and the n-type source and drain,
although these diodes are relatively slow. Faster reaction is provided by the n-channel devices themselves.
When the input is too negative, the gate-to-drain voltage
is positive. If the drain is more negative than the threshold voltage, the transistors turn on in the reverse
direction, with the drains acting as a sources. This
happens very quickly and acts as a clamp. This will also
happen on an I/O pin, with the low output driver acting as
the clamp.
the corner to the center of the DIP package, effectively
reducing the inductance by a factor of about four.
Ground bounce is also controlled by limiting the slew
rate of all the output drivers (see Figure 37). This slows
down the fall time and reduces the rate of current
change by as much as 25%.
Overshoot Sensitivity
Overshoot is a form of noise usually generated when
signaltraces act as transmission lines but have not been
adequately terminated. The resulting reflections can
cause significant overshoot, with as much as double the
intended swing applied to the input in the negative or
positive direction.
While it might appear that parts with negative substrate
bias can "tolerate" more negative overshoot, it is really
more accurate to say that these parts allow more negative overshoot, since there is no clamping. If there are
effective input clamps, which are possible with a
grounded substrate, then it will look like the part never
gets as much negative overshoot. This does not mean it
can't handle the overshoot; it means that it is clamping
the overshoot. If you take the part out of the socket, you
will see that when unclamped, the overshoot will
increase dramatically, as illustrated in Figure 40. Since
AMO's devices have a grounded substrate, they are
inherently better equipped to handle negative
overshoot.
Negative Overshoot
Negative overshoot (Figure 38) poses no problems for a
device that has been carefully designed. There is no
detrimental effect as long as no unexpected parasitic
behavior occurs due to the fact that ground is no longer
the most negative voltage. However, the ringing that
usually follows overshoot can slow down system performance, since the system has to wait for the ringing to
subside.
Clamp diodes are useful for stealing the energy present
in the ringing, and cutting the ringing short. A fast clamp
reacts to the overshoot as it occurs, cuts the amplitude
Vee
Output
Figure 37. Output Drivers with Slew-Rate Control
Undershoot
Overshoot
16507A-064A
Figure 38. Definition of Negative Overshoot and Undershoot
4-32
Inside AMD's CMOS PLD Technology
AMD~
Input
tESD Circuit
16507A-065A
a.
-1 V
".
---------------------C>I---------------- --p-substrate
16507A-066A
b.
Figure 39. Negative Overshoot Clamping: a. Circuit Diagram; b. Cross-Section
Inside AMD's CMOS PLD Technology
4-33
~AMD
........................
~ ..........
~
. . .. . . . . .l.,~f..~\
·.. ·· .. ····,f.\.:·· .. ·.l··
~
~ ~
~
J\
-=-
~~
. ...... } ......1......l· ".. ..!..f. . \., ," . . .l:'·.··
······l,··:.;·
l' t: . . . for':'" I
,. . ,.ll ' "
~:
1·:····'-ri"
¥
.... ······i .. · .. J
\
I '..\ ...! .
~
......:~f:~... ".
,i.,. . :.. . :.' t
\,.i I
~1 r
..
······..;:···.:·······
. ····V·
. ··
rd:
~)l:···
¥ i
J
J
\
~!
···········:\l··
....
i
u.. . . . . ..
:=
Ch.1
Timebase
2.000 volts/div
50.0 ns/div
a.
.;..~
l
"':.:.;::i
~::=::.
""..::
.P ~\:.::4
~F==,/l:\
"',;/
\
~
I
~
~j
Ch. 1
Timebase
. 2.000 volts/div
50.0 ns/div
b.
Figure 40. The Effect of Clamping: a. Signal Driving Empty Socket;
b. Signal Driving Same Socket with CMOS PAL Device In It
4-34
Inside AMD's CMOS PLD Technology
AMD~
Positive Overshoot
Large amounts of positive overshoot (Figure 41) can be
a problem on most PLDs, regardless of technology or
vendor. This is because most PLDs are programmed
using supeNoltages, and the pins therefore have supervoltage detectors that turn on the programming or test
circuits, and potentially disable parts of the normal operating circuitry.
If there is too much positive overshoot, the signal can
travel into the programming voltage range, briefly activatingthe programming circuitry. This can result in functional interruptions, such as outputs momentarily
starting to disable or going from HIGH to LOW.
For earlier devices, the problem can only be avoided by
revising the design to reduce the overshoot. A particular
design in a particular device might work, but this might
be because that device has no supervoltage function on
that particular pin. But if you use an alternate source with
different supervoltage pins, the design might not work.
New AMD CMOS devices incorporate a filter, or delay
circuit, that delays the reaction of the programming circuit for about 100 ns. This is enough to reject overshoot
signals, which usually last for less than 30 ns. Positive
overshoot wil not cause any functional interruptions on
devices with this protection (see Figure 42).
Overshoot
Undershoot
16507A-067A
Figure 41. Definition of Positive Overshoot and Undershoot
Super
Voltage
Detect
Circuit
Programming
or Test Input
Data Path
':X)--_.>----l
" ) 0 - - . Programming
or Test Circuitry
16507A-068A
Figure 42. Positive Overshoot Filter
Inside AM D's CMOS PLD Technology
4-35
~AMD
Latch-up is normally triggered by an input or output at a
voltage significantly above Vee or below ground, with
enough current drawn to cause the SCR to turn on. This
condition usually occurs when hot-socketing a vulnerable part; Le., plugging a part into a powered up board or
inserting a board into a powered-up system. When this
happens, the inputs and Vee power up uncontrolled, and
there is a risk of latch-up.
Latch-Up
Latch-up occurs as'a result of parasitic bipolar transistors between the n-channel and p-channel devices (see
Figure 43a). These transistors form a parasitic SCR
(see Figure 43b), which turns ON when triggered, conducting large amounts of current. It is usually impossible
to shut OFF without removing all power from the device.
The amount of current drawn is so high that it can either
overload a power supply or, if the power supply can supply huge amounts of current, destroy the device.
R p-substrate
p-substrate
16507A-069A
a.
Vee
Rn-well
Rp-substrate
16507A-070A
b.
Figure 43. Latchup Mechanism: a. Cross-Sectl,on; b. Equivalent Schematic
TTL-compatible outputs are intrinsically less susceptible to latch-up, since they have no p-channel pull-up.
This accounts for nearly all of AMD's CMOS PLDs;
these devices can be used for hot-insertion.
For true CMOS outputs, the SCR is an intrinsic part of
the CMOS structure and cannot be eliminated. The SCR
4-36
must be made as difficult as possible to turn ON by using
guard rings and very carefully laying out input and output circuits. All of AMD's CMOS devices are guaranteed
to endu re a current pulse of 100 rnA into or out of the pin
without inducing latch-up; most devices can actually
withstand over 500 rnA. Since AM D's zero-power parts
Inside AMD's CMOS PLD Technology
AMD~
and the PALCE610H-15 have true CMOS outputs, hot
insertion is not recommended.
COMPATIBILITY WITH BIPOLAR
Most of the CMOS PLDs are designed to be compatible
with TIL circuits; indeed, many designers have replaced bipolar TTL devices with a CMOS equivalent.
Often this can be done blindly without affecting system
performance. The interface levels are compatible and
should pose no problems. Even the zero-power parts
have been designed with input buffers that can respond
to TIL or CMOS signals.
However, when making such a conversion, some details require attention, especially in cases where a
straight conversion appears not to work.
Ground Bounce
Because CMOS devices generally have higher output
slew rates, designs having many outputs switching at
the same time (particularly if the outputs are heavily
loaded) can cause more ground bounce than that
generated by a comparable TTL device. It is important to
use devices with output slew rate control.
The slew-rate-limiting circuits help minimize the occurrence of conversion problems, but even when the output
slew rate is limited, the signal still can switch more
quickly than that from a TIL output. If a design cannot be
modified to accommodate the faster edge rates, this
ground bounce may make a conversion unfeasible. If
deSign changes are possible, any of the following can be
tried:
•
Limit the number of outputs that can switch at once.
•
•
Reduce the loading on the outputs.
Go to a lower-lead-inductance package (like a
PLCC).
•
Ensure that the ground path on the circuit board has
low inductance.
pear on different pins for different devices, and the
supervoltage functions vary. Thus, overshoot on one pin
of a particular bipolar device might have had no effect.
Once that device is changed (whether to CMOS or any
other device that has no overshoot filter), the new device
might react to the overshoot and cause problems.
The solution is to ensure that all signals are clean and
have minimal overshoot·, making them compatible with
any device. Signal noise reduction can be accomplished
most effectively by contrOlling the impedance of the signal traces and terminating correctly. As an alternative, if
the driving device has extremely fast edge rates, it can
be replaced with a device that has better controlled out'
put slew rates.
Direct JEDEC File Conversions[ from
Bipolar to CMOS
With some CMOS devices (most notably the
PALCE16V8 and PALCE20V8), converting logic from a
bipolar device is particularly simple once the noise issues have been addressed. This can be done in the programmer or by conversion software. It only affects the
JEDEC file; the source file is not required. Generally,
this is recommended only for designs whose source file
is not available. If the source file is available, it is recommended that you change the device type in the source
file, and then recompile to generate a new JEDEC file.
This permits better documentation and revision control,
since the source file is then consistent with the JEDEC
file being used in production.
SUMMARY
By concentrating on the needs of CMOS PLD users,
AM D has developed industry-leading CMOS technology that can provide cost-effective PLDs of unequalled
quality, reliability, and performance. AMD provides
value through:
•
AMD-owned fabs, for better control of quality,
reliability, volume, and costs
•
electrical erasure, for higher quality and lower cost
the highest performance available
Overshoot
The other possible problem when converting from bipolar to CMOS is reaction to signal overshoot in a noisy
system. This is only an issue if the CMOS device has no
overshoot protection. Overshoot sensitivity is not specifically related to CMOS, but results from programming
algorithms being different between the technologies.
This also can occur when changing between bipolar
vendors, or when changing between CMOS vendors. If
the noise on a signal can disturb supervoltage circuitry,
this can be troublesome.
Different devices have different sensitivities; this
accounts for some of the apparent incompatibility. However, the culprit usually is the fact that supervoltages ap-
a
•
•
robust technology that is quiet and yet tolerant of
noise
an extremely broad offering of products; low and
high density, low and zero power
This application note has detailed many of the aspects
of the technology that make it superior to any alternatives. This, together with the information in the individual data sheets, qualification books, and a crew of
applications engineers, should provide answers to your
questions as you make use of AMD's CMOS PLD
technology.
Inside AMD's CMOS PLD Technology
4·37
~AMD
INDEX
charge pump
latch-up protection
negative substrate
noise .................................................................. .
compatibility with bipolar ...................................................... .
ground bounce .......................................................... .
input thresholds .......................................... '............... .
JEDEC file conversion ............................................ : ....... .
overshoot .............................................................. .
contact dimension ........................................................... .
control gate ................................................................ .
coupling ratio ............................................................... .
data retention .............................................................. .
Arrhenius function ........................................................ .
bake .................................................................. .
effect of external fields .................................................... .
thermal leakage ......................................................... .
value of activation energy .................................................. .
depletion mode transistor ..................................................... .
endurance ................................................................. .
ESD ...................................................................... .
powered down .......................................................... .
overshoot clamping ....................................................... .
FIT rates .................................................................. .
floating gate ............................................ '. ................... .
FusionPLD program ......................................................... .
gate length ................................................................ .
gate oxide thickness : ........................................................ .
ground bounce ................. ,............................................ .
ground lead inductance ................................................... .
hot electron injection ......................................................... .
hot insertion ................................................................ .
I-V curves ................................................................. .
impedances ................................................................ .
input pull-ups ............................................................... .
inputs
connection to array ........................................................ .
ESD protection .....................' ..................................... .
floating ................................................................ .
hot insertion ............................................................ .
I-V curves .............................................................. .
impedance ............................................................. .
overshoot clamping ....................................................... .
overshoot filter .......................................................... .
powered down .......................................................... .
pull-up resistors ......................................................... .
state during power-up ..................................................... .
structure ............................................................... .
transition detectors ....................................................... .
TTL, CMOS compatibility .................................................. .
voltage level ................ '............................................ .
4-38
Inside AM D's CMOS PLD Technology
4-4
4-3
4-4
4-37
4-37
4-37
4-37
4-37
4-3
4-4 et seq
4-9
4-13
4-14
4-14
4-14
4-13
4-14
4-3
4-14
4-30
4-30
4-32
4-30
4-4 et seq
4-13
4-3
4-3
4-31,4-37
4-31,4-37
4-4
4-30, 4-36, 4-37
4-21
4-21
4-24
4-12, 4~13
4-30
4-24
4-30
4-21
4-21
4-30,4-32
4-35
4-29
4-24
4-25
4-20
4-15
4-37
4-16
AMD~
INDEX (continued)
inverter
cross-section ............................................................ .
power consumption ....................................................... .
JEDEC file conversion ....................................................... .
JEDEC load standard ........................................................ .
latch-up ................................................................... .
hot insertion ............................................................ .
negative substrate ....................................................... .
relationship to overshoot ................................................... .
Left ••••.•...•••••....•••••....••••..••..•••..••..•.••..••••......•...•••••.
MACH output load ........................................................... .
margin voltage .............................................................. .
metal interconnect ........................................................... .
pitch .................................................................. .
minimum feature ............................................................ .
n-well structure .............................................................. .
noise ..................................................................... .
ground bounce .......................................................... .
overshoot sensitivity ...................................................... .
latch-up ................................................................ .
outputs
as ESD protection ........................................................ .
as overshoot clamp ....................................................... .
behavior due to overshoot ................................................. .
compatibility with TTL, HC/HCT ............................................. .
current limiting .......................................................... .
drive .................................................................. .
floating ................................................................ .
ground bounce .......................................................... .
HC/HCT-compatible ...................................................... .
hot insertion ............................................................ .
I-V curves .............................................................. .
impedance .................... ; ........................................ .
load ........................................................ .- .......... .
power dissipation ......................................................... .
powered down .......................................................... .
pull-up transistors ........................................................ .
rail-to-rail ............................................................... .
rise and fall times ........................................................ .
role in latch-up .......................................................... .
short-circuit current ....................................................... .
slew rate ................................................................'
structure ............................................................... .
TTL-compatible .......................................................... .
overshoot
causes ................................................................ .
clamping ............................................................... .
CMOS vs bipolar ........................................................ .
filter ................................................................... .
negative ............................................................... .
positive ................................... : ............................. .
Inside AMD's CMOS PLD Technology
4-3
4-15
4-37
4-24
4-36
4-30
4-4
4-4
4-3
4-24
4-14
4-3
4-3
4-3
4-3
4-30
4-31
4-32
4-36
4-30
4-32
4-35
4-3,4-37
4-24
4-24
4-24
4-31
4-30
4-30
4-22
4-22
4-24
4-15
4-27
4-3
4-3,4-23
4-24
4-30,4-21
4-36
4-24,4-37
4-20
4-30
4-32
4-3,4-21,
4-30,4-32
4-37
4-35
4-4,4-21,
4-30,4-32
4-35
4·39
~AMD
INDEX (continued)
, relationship to latch-up .................................................... .
overshoot clamping .......................................... '................ .
role of ESD structure ..................................................... .
poly-silicon interconnect ...................................................... .
elimination of second layer ................................................. .
power dissipation ........................................................... .
frequency .............................................................. .
input voltage .... . ................ " ...................................... .
output loading ........................................................... .
product terms ........................................................... .
temperature ............................................................ .
Vcc ................................................................... .
power-up
latch-up '.' .............................................................. .
reset .................................................................. .
power-up reset ............................................................. .
powered-down characteristics .................................................. .
programmable array ......................................................... .
area .................................................................. .
configuration ............................................................ .
power consumption ....................................................... .
programmers ............................................................... .
programming cell ............................... ' ............................. .
data retention ........................................................... .
endurance .............................................................. .
implant ................................................................ .
programming and erasure mechanisms ....................................... .
self-limiting programming .................................................. .
underprogramming, undererasure ........................................... .
propagation delay ........................................................... .
rise and fall times ........................................................ .
reliability .................................................................. .
SeR ................................................................. ~ .... .
substrate .................................................................. .
as source of electrons for UV parts .......................................... .
floating, negative ................................................ ,........ .
grounded .............................................................. .
overshoot clamping ....................................................... .
supervoltages .............................................................. .
transmission lines ........................................................... .
tunnel oxide
cell endurance .......................................................... .
coupling ratio ........................................................... .
data retention .......................................... '................. .
field across ................................................. . ........... .
thickness relative to UV ................................................... .
tunneling ................................................................ " .
direct .................................................................. .
Fowler-Nordheim ........................................................ .
UV-erasable devices ......................................................... .
compared with EE ........................................................'.
yields, programming and functional ............................................. .
4-40
Inside AMD's CMOS PLD Technology
4-4
4-5,4-21,
4-30,4-32
4-30
4-3
4-8
4-15 '
4-16
4-16
4-18
4-18
4-18
4-19
4-4
4-25
4-25
4-27
4-3
4-8
4-12
4-15
4-13
4-8 et seq
4-13
4-14
4-8
4-8 et seq
4-9,4-13
4-13
4-24
4-24
4-30
4-36
4-3
4-4
4-3
4-3
4-33
4-35
4-32
4-14
4-9
4-13
4-6
4-6
4-6
4-6,4-13
4-6
4-4
4-6
4-13
AMOl1
INDEX (continued)
testing to ensure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
zero-power devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
compatibility with TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
hot insertion .............................................................
I-V curves ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . ..
output load ..............................................................
power dissipation .........................................................
product-term power down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
rail-to-rail operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
role of grounded substrate ..................................................
Inside AMO's CMOS PLO Technology
4-6,4-14
4-4, 4-15
4-37
4-37
4-23
4-24
4-15
4-18
4-3,4-15,4-23
4-3
4-41
~AMD
4-42
~
Military PAL Devices
Advanced
Micro
Devices
Advanced Micro Devices' Military Programmable Array
Logic (PAL) devices provide state machine and combinato rial logic solutions processed to military criteria. We
offer the largest number of Standard Military Drawing
PAL products in the industry.
sequence generators, decoders, multiplexers, adders,
memory mapped I/O and much more. These designs go
into radar systems, missile guidance, avionics, airport
graphic terminals, parallel processors, military computer hardware, and product obsolescence solutions,
just to name a few.
Applications for our configurable PAL architectures
include counters, shift registers, accumulators, control
Military PAL Device Menu
Product
Terms/Output
tPD
'MAl(
ns
MHz
Icc
mA
10
10
210
/BRA
/B2A
12
47.6
210
20L, J, W
20
28.5
180
30
20
90
30
20
180
50
13.3
55
10
50
210
12
41.7
210
15
35.7
210
Family
Part Number
Package
Technology
Inputs
110
Outputs
16R8
PAL16L8-10
/BRA
/B2A
TTL
10
6 Comb
2 Comb
7
8
8
2 Comb
8
4 Comb
8 Reg
6 Reg
4 Reg
8
7,8
7,8
PAL16R8-10
PAL16R6-10
PAL16R4-10
PAL16L8-12
PAL16R8-12
PAL16R6-12
PAL16R4-12
PAL16L8B
PAL16R8B
PAL16R6B
PAL16R4B
PAL16L8B-2
PAL16R8B-2
PAL16R6B-2
PAL16R4B-2
PAL16L8A
PAL16R8A
PAL16R6A
PAL16R4A
PAL16L8B-4
PAL16R8B-4
PAL16R6B-4
PAL16R4B-4
20R8
PAL20L8-10
PAL20R8-10
PAL20R6-10
PAL20R4-10
PAL20L8-12
PAL20R8-12
PAL20R6-12
/BLA,/B3A
TTL
14
12
12
12
6 Comb
2 Comb
4 Comb
2 Comb
8 Reg
6 Reg
4 Reg
7
8
7,8
7,8
PAL20R4-12
PAL20L8-15
PAL20R8-15
PAL20R6-15
PAL20R4-15 .
4-43
~
AMD
Military PAL Device Menu (Continued)
Family
Part Number
Package
Technology
Inputs
I/O
Outputs
20R8
PAL20L8B
PAL20R8B
PAL20R6B
PAL20R4B
24JS, W,
28L
TIL
14
12
12
12
6 Comb
2 Comb
8 Reg
6 Reg
4 Reg
2 Comb
4 Comb
Product
Terms/Output
7
8
7,8
7,8
PAL20L8A
PAL20R8A
PAL20R6A
PAL20R4A
tPD
ns
MHz
Icc
mA
20
28.5
210
30
20
210
fMAX
Universal PAL Devices
Family
Part Number
PAL22Vl0-12
22Vl0
Package
Technology
Inputs
110
Product
Terms/Output
Features
/BLA,/BKA
TIL
12
10 Macro
8-16
Varied Term
tPD
ns
12
50
200
31.2
200
30
22
180
40
16.5
180
15
50
120
PALCE22Vl0H-20
20
33.3
120
PALCE22Vl0H-25
25
26.3
100
PALCE22Vl0H-30
30
25
100
15
41.6
130
AmPAL22Vl0A
Distribution
/B3A
AmPAL22Vl0
PALCE22Vl0H-15
PALCE20V8H-15
EE CMOS
EE CMOS
/BLA,/B3A
12
8 Macro
GAL~
8
Device
PALCE20V8H-20
Equivalent
PALCE20V8H-25
16V8
Icc
mA
fMAX
20
PAL22Vl0-20
20V8
MHz
PALCE16V8H-15
/BRA,/B2A
EE CMOS
8
8 Macro
GAL~
Device
Equivalent
8
PALCE16V8H-20
PALCE16V8H-25
20
33.3
130
25
25
130
15
41.6
130
20
33.3
130
25
28.6
130
Asynchronous PAL Device
Family
610
Part Number
Package
Technology
Inputs
Macro
Product
Terms/Output
Clock
Cells
Other
Features
tPD
ns
fMAX
Icc
MHz mA
PALCE610H-20
/BLA,/B3A
EE CMOS
4
16
8
Programmabie
J-K
Flip-Flops
20
35.8
90
MACH Family (Macro Array CMOS High-density)
Technology
Inputs
Output
Macro
Burled
Macros
Product
Terms/Output
tPD
ns
MHz
44COFP
EE CMOS
6
32
20
40
170
EE CMOS
6
64
-
0-12
84COFP
0-12
20
40
220
44COFP
EE CMOS
6
32
32
0-16
20
40
195
Family
Part Number
Package
MACH 1
MACHll0-20
MACH 1
MACH130-20
MACH 2
MACH210-20
4-44
Military PAL Devices
fMAX
Icc
mA
AMD~
Standard Military Drawing Program
Manufacturing and Screening Locations
AMD is an active participant in the Standard Military
Drawing (SMD) Program. The idea behind the SMD
Program is to standardize MIL-STD-883, Class B microcircuits. The advantage to the user is that SMDs are a
cost effective alternative to source control drawings and
are offered as off-the-shelf stocking items by IC manufacturers participating in the program.
MIL-STD-883 Class B products, and orders to source
control drawings, are assembled at our Penang,
Malaysia facility. This facility is qualified by AMD Quality
Department, as well as by many of our customers, to
manufacture non-MIL-STD-883 Class B products. Conformance to MIL-STD-883 requirements is routinely
monitored through audits at the Penang facility.
Standard Military Drawings should always be considered to improve availability over source control drawings. It is standard practice at AMD to convert our 883,
Class B processing to SM Os for all products which we
are approved to supply. AM D then dual marks these devices with both the SMD number and the Generic Part
Number. DESC approved products can then be procured to either part number as standard product through
both OEM and Distributor channels.
Assembly location as well as fabrication and seal date
codes are included in AMD's part marking.
AMD will continue to work closely with DESC, generating new drawings, which will provide a steady flow of advanced
technology
products
to
standardize
specifications.
Example:
2A
92
1T
35
A
P
T
Assermly 10ca. tion code
Shift identity
(1 st shift of week)
Seal week (ww 35)
' - - - - - - - - Seal year (1992)
Fab date code
(1992, 1st qtr.)
Product Introduction Procedures
All new military products released by the Programmable
Logic Products Division must successfully pass
MIL-STD-883 Class B processing prior to new product
announcement. This practice allows us to do checkout
of bonding diagrams, electrical test tapes and burn circuits in a manufacturing environment. Programmability
is checked when applicable. Our Engineering Department reviews electrical data to insure performance and
yields to military data sheet limits are acceptable, prior
to new product release. This procedure allows AMD to
keep manufacturing start-up problems to a minimum on
new product orders.
Assembly Location Codes:
Military PAL Devices
Blank
M
P
Sunnyvale
Manila
Penang
4-45
~
AMD
Standard Military Flow Chart
Screening
Class B
Assembly
Offshore assembly
Internal visual
2010 condo B
100%
Temperature cycling
1010
100%
Constant acceleration
2001 test condo D or' E
Y1 orientation only
100%
Interim electrical
parameter (1)
Per applicable device (1)
specification
TA = 25°C only
100%
*100 Cycles bulk program
and erase (2)
100%
*Bake
48 hr. 150°C
100%
*Post bake electric
TA
= 25°C
100%
Burn In
1015 Condo Cor D
100%
Post electrical parameters
Per applicable device
specification
TA = 25°C only
100%
Percent defect allowable
DC Parameters
PDA = 5% or 1 device
whichever is greater
Final electrical
parameters (hot and
cold extremes)
Per applicable device
specification
100%
1014 Cond, A or B
cond C
100%
Group A lot
5005 Class B
Sample
every lot
Group B inspection lot
Group C
5005 Class B
5005 Class B
Group D
External visual
5005 Class B
2009
Every lot
Every 4 qtrs. of fab
date code
Every 52 weeks
100%
Seal
A) Fine
B) Gross
*EE CMOS Devices
(1) Programming and verification are performed at 25°C only
(2) May be performed at wafer sort.
4-46
Requirements
Military PAL Devices
AMD~
Quality Programs
Group B - Package Related Tests
The Military Product Division quality system conforms to
the following Mil-Standards:
•
QCI is performed in line on each inspection lot.
•
Purpose: To monitor assembly and device package
integrity.
Mil-M-38510, Appendix A, "Product Assurance Program"
Mil-O-9858, "Quality Program Requirements"
Group C - Product/Process Related Tests
Mil-1-45208, "Inspection System Requirements"
•
Group C is performed based on fab date code, at
least every four quarters.
•
Life test data may be used to qualify similar technologies.
•
Purpose: To monitor the reliability of the process and
the parametric performance for each product technology.
Quality Assurance
The Programmable Logic Products Division ensures
outgoing product quality and integrity by performing inspection Lot Group A's and B's per Mil-Std-883 Method
5005, conducting self audits in all areas involved in
screening tests per Method 5004 of MIL-STD-883,
gating all shipments to our customers, and maintaining
a calibration control system in accordance with MilStd-45662.
For products requiring programming prior to AC tests,
testing is performed utilizing MIL-M-38510 slash sheet
sample plans and approved SM 0 sample plans.
Product Qualification/Quality
Conformance Inspection (QCI)
QCI is conducted every 52 weeks using devices
which represent the same package construction and
lead finish.
•
Any device type in the same package type may be
used regardless of the specific part number.
•
Purpose: To monitor the reliability and integrity of
various package materials and assembly processes.
Process Audits
AMD has a quality conformance testing program in accordance with MIL-STD-883, Method 5005. Quality
Conformance Testing provides necessary feedback
.
and monitors several areas:
Process Audits are performed in accordance with
Mil-M-38510, Appendix A, (self audits) by the Quality
Assurance Department.
Electrostatic Discharge Control
Procedures
•
•
Reliability of Product/Processes
Vendor Qualification for Raw Materials
•
Customer Quality Requirements
Maintain Product Qualification
Engineering Monitor on Products/Processes
•
•
Group D - In-Depth Package Related Tests
•
Standard procedures for new product release specify
that AMD, as a minimum, conduct qualification testing
per Company Policy specification on Product Reliability
Qualification (00-021). Once qualified, each package
type (from each assembly line) and device (by technology group as delineated in MIL-M-3851 0) are incorporated into AMD Quality Conformance Inspection
program which utilizes the requirements of MILSTD-883.
When military programs do not require that QCI data be
run on the specific lot shipped, AMD Quality Conformance program allows customers to obtain generic data
on all product families manufactured by AM 0 Generic
Qualification Data enables customers to eliminate
costly qualification and destruct unit charges, and also
improves delivery time by -a factor of eight to ten weeks.
The following product data is available:
AMD fully employs static control procedures throughout
its facilities.
All manufacturing areas where product is processed or
handled including our Reliability Labs, Engineering
Labs, etc., have full static control such as wrist straps,
antistatic smocks, grounded stainless steel tables, conductive mats and ion generators wherever neces~ary.
All product is moved throughout our facilities and
shipped to customers in static shielded containers.
In addition, AMD distributors must demonstrate that
they meet the same stringent standards regarding ESD
handling and control procedures as the factory. Individual distributor locations are audited and approved annually by AM D's Quality Assurance Department.
An ESD identifier is marked on all products per MILSTD-883 1.2.1 b (30). All shipping containers are labeled with an ESD Caution Message. ESD procedures
are continually reviewed, to ensure that our customers
receive only the highest quality product from AMD.
Military PAL Devices
4-47
;t1
AMD
MILITARY ORDERING INFORMATION
APL Products
AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved
Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) is formed
by a combination of:
81035
01
M
L
t
LEAD FINISH
A = Hot Solder Dip
X = Any Lead Finish
PACKAGE TYPE
K = 24 Lead 3/8" x 5/8" Cerpack
L = 24 Lead 1/4" x 1 1/4" SKINNYDIP
R = 20 Lead 1/4" x 1 1/6" DIP
S = 20 Lead 114" x 1/2" Cerpack
2 = 20 Terminal .350 x .350 LCC
3 = 28 Terminal .450 x.450 LCC
DEVICE CLASS
M = Non-JAN level B product, processed to
MIL-STD-883
DEVICE TYPE
~----
DRAWING NUMBER FOR PRODUCT FAMILY
PART NUMBER INTERPRETATION:
When ordering to Military Drawing numbers, the lead finish designator (last letter in part number) is commonly called out as
"X." This is a way of stating that the customer will accept the standard manufacturer's lead finish for the package orders. "X"
is not a lead finish designator in itself, therefore, when product is shipped, the actual lead finish designator will be marked on
the devices.
4-48
Military PAL Devices
AMD~
Military SMDs
Military
Drawing
8103501RA
81035012A
8103501 SA
8103502RA
81035022A
8103502SA
8103503RA
81035032A
8103503SA
8103504RA
81035042A
8103504SA
8103505RA
81035052A
8103505SA
8103506RA
81035062A
8103506SA
8103507RA
81035072A
8103507SA
8103508RA
81035082A
8103508SA
8103509RA
81035092A
8103509SA
8103607RA
81036072A
8103607SA
8103S08RA·
81036082A
8103608SA
8103609RA
81036092A
8103609SA
8103610RA
81 0361 02A
8103610SA
8103612RA
81036122A
8103612SA
8103613RA
81036132A
8103613SA
8103614RA
81036142A
8103614SA
8412901 LA
84129013A
8412901KA
8412902LA
84129023A
8412902KA
8412903LA
AMD Part
Number
Military
Drawing
PAL 1OH8MJ/883B
PAL 1OH8MU883B
PAL 1OH8MW/883B
PAL 12HSMJ/883B
PAL 12HSMU883B
PAL 12H6MW/883B
PAL 14H4MJ/883B
PAL14H4MU883B
PAL14H4MW/883B
PAL 16H2MJ/883B
PAL16H2MU883B
PAL 16H2MW/883B
PAL 16C 1MJ/883B
PAL16C1MU883B
PAL 16C1 MW/883B
PAL 1OL8MJ/883B
PAL10L8MU883B
PAL 1OL8MW/883B
PAL 12LSMJ/883B
PAL12L6MU883B
PAL 12L6MW/883B
PAL 14L4MJ/883B
PAL 14L4M U883B
PAL 14L4MW/883B
PAL 1SL2MJ/883B
PAL 16L2MU883B
PAL 16L2MW/883B
PAL 16L8AMJ/883B
PAL 16L8AMU883B
PAL 16L8AMW/883B
PAL 1SR8AMJ/883B
PAL 16R8AMU8838
PAL16R8AMW/8838
PAL 16R6AMJ/8838
PAL 16RSAMU8838
PAL 16R6AMW/8838
PAL 1SR4AMJ/883B
PAL 16R4AMU883B
PAL 1SR4AMW/883B
PAL 16R8A-2MJ/883B
PAL 16R8A-2MU883B
PAL 16R8A-2MW/8838
PAL 1SRSA-2MJ/883B
PAL 16RSA-2MU8838
PAL 16RSA-2MW/8838
PAL 16R4A-2MJ/8838
PAL 16R4A-2MU883B
PAL 16R4A-2MW/8838
PAL20L8AMJS/8838
PAL20L8AMU8838
PAL20L8AMW/8838
PAL20R8AMJS/883B
PAL20R8AMU8838
PAL20R8AMW/883B
PAL20RSAMJS/8838
84129033A
8412903KA
8412904LA
84129043A
8412904KA
8412905LA
84129053A
8412905KA
8412906LA
84129063A
8412906KA
8412907LA
84129073A
8412907KA
8412908LA
84129083A
8412908KA
8412909LA
84129093A
8412909KA
8412910LA
84129103A
8412910KA
8412911LA
84129113A
8412911 KA
8412912LA
84129123A
8412912KA
850S501RA
85065012A
8506501 SA
8506502RA
85065022A
8506502SA
8506503RA
85065032A
8506503SA
8506504RA
85065042A
8506504SA
5962-8515501 RA
5962-85155012A
5962-8515501 SA
5962-8515502RA
5962-85155022A
59S2-8515502SA
5962-8515503RA
5962-85155032A
5962-8515503SA
5962-8515504RA
5962-85155042A
5962-8515504SA
5962-8515505RA
5962-85155052A
Military PAL Devices
AMD Part
Number
PAL20RSAMU883B
PAL20RSAMW/883B
PAL20R4AMJS/883B
PAL20R4AMU883B
PAL20R4AMW/883B
PAL20L1OAMJS/883B
PAL20L1OAMU883B
PAL20L1OAMW/883B
PAL20X8AMJS/883B
PAL20X8AMU883B
PAL20X8AMW/883B
PAL20X 1OAMJS/883B
PAL20X10AMU883B
PAL20X10AMW/883B
PAL20X4AMJS/883B
PAL20X4AMU883B
PAL20X4AMW/883B
PAL20L8A-2MJS/883B
PAL20L8A-2MU883B
PAL20L8A-2MW/883B
PAL20R8A-2MJS/883B
PAL20R8A-2MU883B
PAL20R8A-2MW/883B
PAL20R6A-2MJS/883B
PAL20R6A-2MU883B
PAL20R6A-2MW/883B
PAL20R4A-2MJS/883B
PAL20R4A-2MU883B
PAL20R4A-2MW/883B
PAL 16L8A-4MJ/883B
PAL 16L8A-4MU883B
PAL 16L8A-4MW/8838
PAL 16R8A-4MJ/8838
PAL 16R8A-4MU8838
PAL 16R8A-4MW/8838
PAL 16R6A-4MJ/883B
PAL 16R6A-4MU883B
PAL 16R6A-4MW/8838
PAL 16R4A-4MJ/8838
PAL 16R4A-4MU8838
PAL 16R4A-4MW/8838
PAL 16L88MJ/883B
PAL 16L88MU8838
PAL 16L88MW/8838
PAL 16R88MJ/8838
PAL16R8BMU8838
PAL 16R8BMW/883B
PAL 16R68MJ/8838
PAL 16R6BMU8838
PAL 16R68MW/8838
PAL 16R48MJ/8838
PAL 16R48MU8838
PAL16R48MW/8838
PAL 16L88-2MJ/8838
PAL 16L88-2MU8838
4·49
~
AMD
Military SMDs (continued)
Military
Drawing
AMD Part
Number
5962-8515505SA
5962-8515506RA
5962-85155062A
5962-8515506SA
5962-8515507RA
5962-85155072A
5962-8515507SA
5962-8515508RA
5962-85155082A
5962-851550SSA
5962-8515509RA
5962-85155092A
5962-8515509SA
5962-8515510RA
5962-85155102A
5962-8515510SA
5962-8515511 RA
5962-85155112A
5962-8515511 SA
5962-8515512RA
5962-85155122A
5962-8515512SA
5962-85155132A
5962-8515513RA
5962-85155142A
5962-8515514RA
5962-85155152A
5962-8515515RA
5962-85155162A
5962-8515516RA
5962-85155172A
5962-8515517RA
5962-85155182A
5962-8515518RA
5962-85155192A
5962-8515519RA
5962-85155202A
5962-8515520RA
5962-8605301 lA
5962-86053013A
5962-8605301 KA
5962-8605302lA
5962-86053023A
5962-8605302KA
5962-8605304lA
5962-86053043A
5962-8605304KA
5962-8S063053A
5962-8605305KA
5962-8605305lA
5962-8680301 lA
5962-86803013A
5962-8680301 KA
5962-8680401 lA
5962-86804013A
PAL 16l88-2MW/8838
PAL 16R88-2MJ/8838
PAL 16R88-2MU8838
PAL 16R88-2MW/8838
PAL 16R68-2MJ/8838
PAL 16R68-2MU8838
PAL 16R68-2MW/883B
PAL 16R48-2MJ/8838
PAL 16R48-2MU8838
PAL 16R48-2MW/8838
PAL 16l8DMJ/8838
PAL 16l8DMU8838
PAL 16lSDMW/8838
PAL 16R8DMJ/8838
PAL 16R8DMU8838
PAL 16R8DMW/S83B
PAL 16R6DMJ/8838
PAL 16R6DMU8838
PAL 16R6DMW/883B
PAL 16R4DMJ/8838
PAl16R4DMU8S3B
PAL 16R4DMW/8838
PAL 16l8-12182A
PAL 16lS-1218RA
PAL 16RS-12/82A
PAL 16RS-12/8RA
PAL 16R6-12/82A
PAL 16R6-12/8RA
PAL 16R4-12/82A
PAl16R4-12/8RA
PAL 16l8-1 0/82A
PAL 16l8-1 0/8RA
PAL 16R8-1 0/82A
PAl16R8-10/8RA
PAL16R6-10/82A
PAL16R6-10/8RA
PAL 16R4-1 0/82A
PAL 16R4-1 0/8RA
AmPAl22V10Al8lA
AmPAl22V10Al83A
AmPAl22V10Al8KA
AmPAl22V10/8lA
AmPAl22V10/83A
AmPAl22V10/8KA
PAl22V10-20/8lA
PAl22V10-20/83A
PAl22V10-20/8KA
PAl22V10-12183A
PAl22V10-1218KA
PAl22V10-1218lA
PAl20RA 1OMJS/S838
PAl20RA 1oMU8838
PAl20RA 1OMW/8838
PAL 18l4MJS/8838
PAL 18l4MU8838
4-50
Military
Drawing
5962-8680401 KA
5962-8680402lA
5962-86804023A
5962-8680402KA
5962-8680403lA
5962-86804033A
5962-S680403KA
5962-8680404lA
5962-86804043A
5962-S680404KA
5962-8680405lA
5962-86804053A
5962-S680405KA
5962-8680406lA
5962-86804063A
5962-8680406KA
5962-8753001 lA
5962-87530013A
5962-8753001 KA
5962-8753002LA
5962-87530023A
5962-8753002KA
5962-S753003lA
5962-87530033A
5962-S753003KA
5962~S753004lA
5962-S7530043A
5962-8753004KA
5962-S7671 01 lA
5962-87671013A
5962-8767101 KA
5962-8767102lA
5962-87671023A
5962-8767102KA
5962-8767103lA
5962-87671033A
5962-8767103KA
5962-8767104lA
5962-87671043A
5962-8767104KA
5962-8767107LA
5962-87671073A
5962-8767108lA
5962-87671083A
5962-8767109lA
5962-87671093A
5962-8767110lA
5962-87671103A
5962-8767111 lA
5962-87671113A
5962-8767112LA
5962-87671123A
5962-8767113lA
5962-87671133A
5962-S767114lA
Military PAL Devices
AMD Part
Number
PAL18l4MW/883
PAL 12l1OMJS/8838
PAL12L10MU8838
PAL12l10MW/8838
PAL14l8MJS/8838
PAL14l8MU8838
PAL14l8MW/8838
PAL 16l6MJS/8838
PAL16l6MU8838
PAL 16l6MW/S838
PAL20L2MJS/8838
PAL20L2MU8838
PAl20L2MW/883B
PAl20C1 MJS/8838
PAL20C1 MU8838
PAL20C1 MW/8838
PAl20S 1OMJS/8838
PAl20S10MU8838
PAl20S10MW/8838
PAl20RS10MJS/8838
PAl20RS10MU8838
PAL20RS 1OMW/8838
PAl20RSSMJS/8S38
PAl20RS8MU8838
PAL20RSSMW/8838
PAl20RS4MJS/8838
PAl20RS4MU8838
PAl20RS4MW/8838
PAl20l88MJS/8838
PAl20l88MU8838
PAL20l88MW/8838
PAL20R88MJS/8838
PAL20R88MU8838
PAl20R88MW/8838
PAl20R68MJS/8838
PAL20R68MU8838
PAL20R68W/8838
PAL20R48MJS/8838
PAl20R48MU8838
PAL20R48MW/8838
PAL20l8-15/8lA
PAL20L8-15/83A
PAL20R8-15/8lA
PAl20R8-15/83A
PAl20R6-15/8lA
PAL20R6-15/83A
PAL20R4-15/8LA
PAL20R4-15/83A
PAl20l8-1218lA
PAl20lS-12183A
PAl20R8-12/8LA
PAl20R8-12/83A
PAL20R6-12/8lA
PAl20R6-12/83A
PAl20R4-12/8lA
AMD~
Military SMDs (continued)
Military
Drawing
Military
Drawing
AMD Part
Number
5962-87671143A
5962-8767115LA
5962-87671153A
5962-8767116LA
5962-87671163A
5962-8767117LA
5962-87671173A
5962-8767118LA
5962-87671183A
5962-8851501 RA
5962-88515012A
5962-8851501 SA
5962-8851502RA
5962-88515022A
5962-8851502SA
5962-8851503RA
5962-88515032A
5962-8851503SA
5962-8851504RA
5962-88515042A
5962-8851504SA
5962-89839012A
5962-8983901 RA
5962-89839022A
PAL20R4-12/83A
PAL20L8-10/8LA
PAL20L8-10/83A
PAL20R8-1 0/8LA
PAL20R8-10/83A
PAL20R6-10/BLA
PAL20R6-1 0/83A
PAL20R4-10/BLA
PAL20R4-101B3A
PAL 16L8B-4MJ/883B
PAL 16L8B-4MU883B
PAL 16L8B-4MW/883B .
PAL 16R8-4MJ/883B
PAL 16R8B-4MU883B
PAL 16R8B-4MW/883B
PAL 16R6B-4MJ/883B
PAL 16R6B-4MU883B
PAL 16R68-4MW/883B
PAL 16R48-4MJ/8838
PAL 16R4B-4MU8838
PAL 16R4B-4MW/883B
PALCE16V8H-25E41B2A
PALCE16V8H-25E4IBRA
PALCE 16V8H-20E4/B2A
5962-8983902RA
5962-89839032A
5962-8983903RA
5962-89840013A
5962-8984001 LA
5962-89840023A
5962-8984002LA
5962-89840033A
5962-8984003LA
5962-89841013A
5962-8984101 KA
5962-8984101 LA
5962-89841023A
5962-8984102KA
5962-8984102LA
5962-89841043A
5962-8984104KA
5962-8984104LA
5962-89841053A
5962-8984105KA
5962-8984105LA
5962-9169501 M3A
5962-9169501 MLA
Military PAL Devices
AMD Part
Number
PALCE16V8H-20E4IBRA
PALCE 16V8H-15E41B2A
PALCE 16V8H-15E41BRA
PALCE20V8H-25E41B3A
PALCE20V8H-25E4IBLA
PALCE20V8H-20E41B3A
PALCE20V8H-20E4IBLA
PALCE20V8H-15E41B3A
PALCE20V8H-15E4IBLA
PALCE22V10H-301B3A
PALCE22V10H-30IBKA
PALCE22V10H-30IBLA
PALCE22V10H-20E4IB3A
PALCE22V10H-20E4IBKA
PALCE22V10H-20E4IBLA
PALCE22V10H-251B3A
PALCE22V10H-25IBKA
PALCE22V10H-25IBLA
PALCE22V10H-15E4/B3A
PAL.CE22V10H-15E4/BKA
PALCE22V10H-15E4/BLA
PALCE610H-201B3A
PALCE610H-20/BLA
4·51
Military ProPAL™ Devices
The Advantages
An important service that AMD's Programmable Logic
Division offers is ProPAL devices, the programming of a
customer's PAL devices during the manufacturing cycle, saving aerospace customers significant time and
money. We offer full 883, SMD, programmed products.
Not only were we the first to offer this service, we by far
have the most expertise in managing your programmed
business.
The pre-programming of PAL devices for the customer
offers a number of advantages, most of which increase
the parts' reliability. Unlike a blank generic device, a
ProPAL device undergoes a more thorough testing
process. Listed below are just a few of the many
advantages.
Although the price of the ProPAL device is higher than
that of its unprogrammed counterpart, the added value
provided to the user more than offsets the cost. In this
era of cost-cutting and the need to get the most from
each dollar spent, Pro PAL devices make it possible for
the customer to save money over the life of the project.
Below are just a few examples of where cost savings
can be recognized.
Cost Reduction Areas:
• The more thorough testing significantly increases
the long term reliability of the device. System failures
and resulting rework costs, owing to a defective PAL
device, can easily be 50 times the purchase price of
the component.
•
The customer does not have to purchase and maintain costly programming and test facilities. He can
concentrate on what he does best. .. design systems
to aid in defense of our nation and allow AM D to do
what we do best. .. produce and test Programmable
LogiC Devices.
'
•
The parts are programmed prior to burn-in; weak
parts are likely to fail to accept a program and be rejected on the spot.
As volumes go up, the customer's production line
won't be constrained by his programming and labeling capacities or throughput time.
•
Programmed devices then must pass 25°C DC,
functional and AC electrical tests prior to burn-in and
DC, functional and AC electrical tests after burn-in,
at temperature extremes, per M5004.
Inventories can be reduced. The customer no longer
needs to store extra product for programming fall-out
or human error.
•
Improve lead time of manufacturing. The customer
will no longer need to plan on internal time to program or label devices.
Enhanced Reliability
•
•
•
In the design environment, the pattern undergoes
fault simulation with> 90% coverage, providing a
high testability. (Some patterns do not allow 90%
fault coverage. In those cases the customer will be
notified.)
4-52
Military ProPAL™ Devices
AMD~
ProPAL Device Flow for Products with Existing
Mil Shell Programs
Marketing/Sales
Receives Masters (Programmed devices, Floppy disk or
Mag tape) from customer and forwards them
to Spec Writing.
Military Programming Process Summary
(per current Revisions of MiI-Std-BB3 and Mil-M-3B51 0)
Assembly
100% program to
customer bit pattern
Initial Electrical Test
(2S°C)
100% DC/FunctionaVAC
at 2SoC, MS004
I
Spec Writing
Prepares and submits documentation packet to engineering.
Packet contains PICS, master and blanks.
Initiates Process Spec.
I
Electrical Test
(2S°C)
I
Engineering
Generates prototypes, fuse file and post functional tests on
Auto VecHA •
Method 101S, Condition
CorD
Burn-In
PDA
-
100% DC/FunctionaVAC
at 2SoC per MS004
-
Group A DC/Functional/
AC at 2SoC per MSOOS
-
5% (DC only)
-
Resistance to solvents,
solderability, bond pull
-
MSOOS
Solder Dip
Mark
I
Lot B Test
Spec Writing
Sends prototypes and Approval form to customer via Sales.
Electrical Test
(+ 12SoC &-SS°C)
I
100% DC/FunctionaV
AC, MS004
Group A DC/Functional/
AC, MSOOS
Customer
Verifies prototypes and returns Approval form to AMD.
Hermiticity
I
External Visual
Data Review/Pack/Ship
-
100% Fine/Gross Leak
per Method 1014
Method 2009
Spec Writing
Checks Approval form for customer acceptance
of prototypes.
(
I
NO
Accept
I
YES
Engineering
Reviews and completes documentation packet.
Release bit pattern and test programs to Production.
AMD is the proven technology leader in PAL devices
and has numerous years of experience in programming
customer patterns. Currently several major customers
are using ProPAL devices and several major programs
are being converted to ProPAL devices. Factory programming of your PAL device products is another service of the Military Programmable Logic's long-term
partnership with and commitment to the worldwide Military and Aerospace market. For more information on
Military ProPAL devices contact your local AMD sales
office.
I
Spec Wrltlng/QA
Reviews and releases Process Spec to Production.
Military ProPALTM Devices
4·53
Electrical Characteristic Definitions
Parameter
Symbol
Parameter Name
Parameter Definition
tAPR
Asynchronous Preset Recovery Time
The minimum time after the asynchronous
preset becomes inactive to the next input clock
triggering edge.
tAPW
Asynchronous Preset Width
The minimum pulse width required for the
asynchronous preset signal.
tH
Hold Time
The minimum time a valid data level is held
after clock triggering edge.
tHP
Hold Time for Preload
The minimum delay time for data to remain
stable after the preload signal becomes inactive.
This only applies to TTL-level preload.
tSRR
Synchronous Reset Recovery Time
The minimum time between the synchronous
reset going inactive and the next input clock
triggering edge.
ts
Setup Time, Input or Feedback to Clock
The minimum time a valid data level of input or
feedback is stable before the next clock
triggering edge.
tsp
Data Setup Time for Preload
The minimum time for input data to be stable
prior to the preload signal becoming inactive.
This only applies to TTL-level preload.
tWH
Clock Width High
The minimum width of the clock high from rising
edge to the next falling edge. In some cases,
simultaneous minimum clock widths (both high
and low) will exceed the minimum period of the
device.
tWL
Clock Width Low
The minimum width of the clock low from falling
edge to the next rising edge. In some cases,
simultaneous minimum clock widths (both high
and low) will exceed the minimum period of the
device.
twp
Preload Pulse Width
The minimum pulse width required to preload the
registers. This only applies to TTL-level preload.
tAP
Asynchronous Preset to Output
The maximum time required to preset the
register output after the preset signal is asserted.
tAR
Asynchronous Reset to Output
The maximum time required to reset the register
output after the reset signal is asserted.
Timing
4-54
AMD~
Parameter
Symbol
Parameter Definition
Parameter Name
Timing
tco
Clock to Register Output
The maximum time it takes to obtain a valid data
level on the output pin after an input clock
triggering edge is applied.
tCR
Input or Feedback to Registered
Output from Combinatorial
Configuration; Output Mux Select
1 to 0
The minimum time from input or feedback to
registered output as output mux selection changes
from combinatorial to registered output 1 to 0).
tEA
Output Enable Time, Clock to Output
The minimum delay between when an input is
asserted and the output switches from a highimpedance state to HIGH or LOW logic state.
tER
Output Disable Time, Input to Output
The minimum delay between when an input is
asserted and the output switches from a HIGH or
LOW logic state to a high-impedance state.
tF
Fall Time
The minimum time for a signal to fall from 80% to
20% of its stabilized high value.
tPD
Propagation Delay, Input or Feedback
to Combinatorial Output
The time fora signal to propagate from input or
feedback to output.
tPR
Power-up Reset Time
The minimum time for a registered output signal to
be reset after the power is applied.
tpxz
Output Disable Time, OE to Output
The minimum delay between when a dedicated
enable signal is asserted and the output switches
from a HIGH or LOW logic state to be a highimpedance state.
tpzx
Output Enable Time, OE to Output
The minimum delay between when a dedicated
enable signal is asserted and the output switches
from a high-impedance state to a HIGH or LOW
logic state.
tR
Rise Time
The minimum time for a signal to rise from 20% to
80% of its stabilized high value.
tAC
Input or Feedback to Combinatorial
Output from Registered Configuration;
Output Mux Select 0 to 1
The minimum time from input or feedback to
combinatorial output mux selection changes from
registered to combinatorial output (0 to 1).
Supply Voltage, Positive Potential
The voltage required across supply and ground
terminals of a TTL or CMOS integrated circuit.
VI
Input Clamp Voltage
The maximum input clamp voltage limit on every
input pin.
VIH
High-Level Input Voltage
The minimum high-level input voltage that is
guaranteed to represent a high logic level.
VIL
Low-Level Input Voltage
The maximum low-level input voltage that is
guaranteed to represent a low logic level.
VOH
High-Level Output Voltage
The minimum high logic level guaranteed for all outputs.
VOL
Low-Level Output Voltage
The minimum low logic level guaranteed for all outputs.
Voltage
Vec
Electrical Characteristic Definitions
4-55
~AMD
Parameter
Symbol
Parameter Name
Parameter Definition
Supply Current, Corresponding to Vcc
The maximum current into the Vcc terminal of a
TTL or CMOS integrated circuit.
II
Input Current with Maximum Input
Voltage
The maximum current into an input pin when the
input voltage is applied to the input pin.
IIH
High-Level Input Current
The maximum current into an input pin when a logichigh level is applied to the input pin.
III
Low-Level Input Current
The maximum current into an input pin when a logiclow level is applied to the input pin.
IOH
High-Level Output Current
The maximum current into an output pin to
guarantee an output logic-high level.
IOl
Low-Level Output Current
The maximum current into an output pin to
guarantee an output logic-low level.
Isc
Output Short-Circuit Current
The current into an output when that output is
short-circuited to ground (0.5 V).
lozH
High-Level Leakage Current
The maximum current into a high-impedance state
output p!n when a high logic level is applied to the
output pin.
lozl
Low-Level Leakage Current
The maximum current into a high-impedance state
output pin when a low logic level is applied to the
output pin. ,
Input Capacitance
The input pin capacitance at a specified voltage and
frequency.
Output CapaCitance
The output or 1/0 pin capacitance at a specified
voltage and frequency.
TA
Operating Free Air Temperature
The ambient homogeneous temperature of the
environment during operation.
Tc
Operating Case Temperature
The maximum chassis temperature during operation.
fMAX
Maximum External Frequency
The fMAX, External is the maximum clocking frequency
with external feedback. It is the reciprocal of the clock
period (ts +tco).
fMAX
Maximum Internal Frequency
The fMAX, Internal is the maximum clocking frequency
with internal feedback. An internal counter is used to
determine'1cNT."
fMAX
Maximum Frequency without
Feedback
The fMAX, No Feedback is the maximum clocking frequency
with no feedback. It is the reciprocal of the sum of the
data setup time (ts) and the data hold time (th).
Current
Icc
Miscellaneous
CIN
COUT
4·56
Electrical Characteristic Definitions
fMAX
Parameters
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the input setup time for the external signals (ts + tco). The reciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed device. This fMAX is designated '1MAX external."
The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated '1MAX internal". A simple internal counter is a
good example of this type of design, therefore, this parameter is sometimes called '1cNT."
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (ts + tH). However, a lower limit for the period of each fMAX type is the
minimum clock period (tWH + tWl.). Usually, this minimum
clock period determines the period for the third fMAX,
designated '1MAX no feedback."
fMAX external and fMAX no feedback are calculated parameters. fMAX external is calculated from ts and teo, and
fMAX no feedback is calculated from tWL and tWH. fMAX internal is measured.
ClK
r-------------
I
I
-----~
I
I
I--l-....I
lOGIC
REGISTER
I
I
I
I
I
~-------------------~
I. .
1 - - - - - ts
(SECOND
CHIP)
••-- teo ---t"~lioIa.r- ts -.t
---"'~"'I
fMAX External; 1/(ts + teo)
ClK
ClK
r-------------
I
I
lOGIC
-----~
REGISTER
I
I
I
I
I
I
I
~-------------------~
fMAX Internal (feNT)
r-------------
I
I
I
I
lOGIC
-----~
I
I
I
REGISTER J.----il~......
I
I
I
I
I
I
~-------------------~
I~.~---ts----~~~I
fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL)
fMAX Parameters
4-57
PHYSICAL DIMENSIONS*
CD 020
20·Pin Ceramic DIP (measured in inches)
I"
.045
.065
..'1
..975
935.
.100
Bse
.005
MIN
.300
TOP VIEW
:~60~~.
sc
1.015
~.060
.125
.200
~
.008
.Q18
--+l~
94
0
1050
L·400
.014
.026
MAX
-.l
g~~~1o
613193 as
END VIEW
SIDE VIEW
CD3024
24·Pin 300 mil Ceramic SKINNYDIP (measured in inches)
,..
1.235
... ,
1.280
~~:~~
::: :~~ :]J!~~
-'I~
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.065
.100
BSe
TOP VIEW
.005
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.300
BSe
:~6g~~.,f·
.008
.018
1.015
060
.125
.200
.014
.026
I
SIDE VIEW
"For reference only. BSC is an ANSI standard for Basic Space Centering.
4-58
Physical Dimensions
I
.400
I
t---MAX~
06850F
613193 CD3024
COO9ae
END VIEW
AMD~
CFL024
24·Pin Ceramic Flatpack (measured in inches)
.050
sse
+
I
f
i
i
1
I
.015
.022
:~~:
.58 o
.63 o
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.250
.320
j
I[ . - .250
.320
Physical Dimensions
.026
.045
096750
CJ16
614/93 ae
4-59
~
AMD
CL020
20-Pin Ceramic Leadless Chip Carrier (measured in inches)
.~::J
.100-11
INDEX CORNER
.020 X 45° REF.
(OPTIONAL)
T
1
.320
MAX
.320
MAX
J
PLANE2~1
PLANE 1
TOP VIEW
073180
CJ46 CL 020
614193 ae
BOTTOM VIEW
4-60
Physical Dimensions
AMD~
CL028
28-Pin Ceramic Leadless Chip Carrier (measured in inches)
'054~
.040 X 45 0 REF.
INDEX CORNER
.020 X 45 0 REF.
(OPTIONAL)
.088
(OPTIONAL)
:~~6-1
.442
--. tl
MAX
~:~~
.458
PLANE2~
PLANE 1
TOP VIEW
.022L
028
.
r
065951
CJ45 CL 028
6/7/93 ae
.045L
BonOMVIEW
Physical Dimensions
4·61
~
AMD
PD 020
20·Pin Plastic DIP (measured in inches)
I"
1.010
1.040
--I
~~~::~~]j
- . I I..005 '
MIN.
-.I I+.045
.065
.090
.no
TOP VIEW
:~60~mNMW·l.015
~.060
.120
.160
I
I
Q:'--..
--..
7°
.014
.022
SIDE VIEW
~.330---.J
.430
07522C
CM73 PD020
12118/91 e de
END VIEW
PD3024
24·Pin 300 mil Plastic SKINNYDIP (measured in inches)
I"
--I
1.150
1.270
~~~~:~:~::~ll~~~
.030
MIN
.045
.065
.090
.110
.005
MIN
TOP VIEW
:~6~0~1.015
.125
.160
- . .060
I
--.J~
.014
.022
SIDE VIEW
4·62
.008
.015
o·
T
~
.330 ____
.430
END VIEW
Physical Dimensions
I
07089F·OO2
CM74 PD3024
617193 ae
AMD
l1
PD3028
28·Pin 300 mil Plastic SKINNYDIP (measured in inches)
I_
.030
.065
-I
1.375
1.400
.045
.065
.090
.005
MIN
.1'10
TOP VIEW
:~6~0~~1.015
.120
.160
.
--. .060
I
-.j~
O'
T
.014
.022
SIDE VIEW
END VIEW
PL020
20·Pin Plastic Leaded Chip Carrier (measured in inches)
.042
.020
MIN
.050
~Ioo.IooI.I.RE.I.I.F~ 1.
.042
.056
n 1 r " 8..........
T·
350
.356
.
!o4-_ _ . 385
.395
026
032
3
06970D
Bve PL 020
112192e de
1
TOP VIEW
SIDE VIEW
Physical Dimensions
4-63
~
AMD
PL028
28·Pin Plastic Leaded Chip Carrier (measured in inches)
.042
.020
MIN
.050
m
'04_~
____~__R_E_F__~
:~~~
1.
T·
026
032
.485 .450
.495 .456
14-"450~
06751F
BV8PL028
12131191 e de
.456
...._ _ _ .485
.495
TOP VIEW
SIDE VIEW
SO 020
20·Pin Plastic Gull.Wing
Small Outline Package (measured in inches)
.045
.055
TOP VIEW
t. Jtr-ll-----I~b ~.0091
I I ---r .0125
"1 JL8°
-.I k- T
.016
- :::
.035
END VIEW
4·64
Physical Dimensions
15683A
BJ10 SO 020
214/92 c de
AMD~
50024
24·Pin Plastic Gull·Wing
Small Outline Package (measured in inches)
.045
.055
===~
~
---ll-.0138
.0192
h
---r
0926
.1043
.0040
.0118
END VIEW
SIDE VIEW
Physical Dimensions
093109
10117/91
9J10 e de
4-65
~
4-66
AMD
IIilt+iAi3,1
5
DESIGN AND TESTABILITY
Basic Design with PLDs .................................................... 5-3
PLD Design Basics ................................................ 5-8
PLD Design Methodology .......................................... 5-16
Combinatorial Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 5-27
Registered Logic Design ........................................... 5-40
State Machine Design ............................................. 5-60
Testability .............................................................. 5-73
Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-92
Metastability ............................................................ 5-95
Latchup .......................................... ~ . . . . . . . . . . . . . . . . . . . .. 5-97
Converting Bipolar to CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-100
High-Speed-Board Design Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-107
Minimizing Power Consumption with Zero-Power PLDs .......................... 5-135
Designing with the PALCE16V8HD .......................................... 5-138
Design and Testability
5-1
~
5-2
AMD
Design and Testability
.~
Basic Design with PLDs
Advanced
Micro
Devices
INTRODUCTION
The Programmable Array Logic device, commonly
known as the PAL device, was invented at Monolithic
Memories in 1978. The concept for this revolutionary
type of device sprang forth as a simple solution to the
short comings of discrete TTL logic.
WHAT OTHER IMPLEMENTATIONS ARE
POSSIBLE?
There are essentially four alternatives to programmable
logic:
•
Discrete Logic
The successfully proven PROM technology which
allowed the end user to ''write on silicon" provided the
technological basis which made this kind of device not
only possible, but very popular as well.
•
Gate Arrays
•
Standard Cell Circuits
•
Full Custom Circuits
The availability of design software made it much easier
to design with programmable logic. As designers were
freed from the drudgery of low-level implementation
issues, new complex designs were easier to implement,
and could be completed more quickly.
Discrete Logic
This chapter outlines some basic information essential
to those who are unfamiliar with Programmable Logic
devices (PLDs). The information may also be useful to
those who are current users of programmable logic. The
specific issues which need to be addressed are:
•
What is a PLD?
•
What other implementations are possible?
•
What advantages do PLDs have over other
implementations?
Discrete logic, or conventional TIL logic, has the
advantage of familiarity; hence its popularity. It is also
quite inexpensive when only unit cost is considered. The
drawback is that the implementation of even a simple
portion of a system may require many units of discrete
logic. There are "hidden" costs associated with each unit
that goes into a system, which can render the overall
system more expensive.
Designing with discrete chips can also be very tedious.
Each design decision directly affects the layout of the
board. Changes are difficult to make. The deSign is also
more difficult to document, making it harder to debug
and maintain later. These items all contribute to a long
design cycle when discrete chips are used extensively.
WHAT IS A PLD?
Gate Arrays
In general, a programmable logic device is a circuit
which can be configured by the user to perform a logic
function. Most "standard" PLDs consist of an AND array
followed by an OR array, either (or both) of which is
programmable. Inputs are fed into the AND array, which
performs the desired AND functions and generates
product terms. The product terms are then fed into the
OR array. In the OR array, the outputs of the various
product terms are combined to produce the desired
outputs.
Gate arrays have been increasing in popularity. The
attractiveness of this solution lies in the device's
flexibility. By packing the functions into the device, a
great majority of the available silicon is actually used.
Since such a device is customized for an application, it
would seem to be the optimum device for that
application.
PAL Devices
The PAL device has a programmable AND array
followed by a fixed OR array (Figure 1). The fact that the
AND array is programmable makes it possible for the
devices to have many inputs. The fact that the OR array
is fixed makes the devices small (which means less
expensive) and fast.
However, one also pays substantial development costs,
especially in the case of a design which needs changes
after silicon has already been processed. Even though
the unit costs are generally quite low for gate arrays, the
volumes required to make their use worthwhile excludes
them as a solution for many designers. This fact, added
to the long design cycle and high risk involved, make this
solution practical for only a limited number of designers.
5-3
,
~AMD
15
14
13
12
11
10
1~ 1~ 1~ 1~ 1~ 1~
"--
'V'
Fixed OR Array
~
~
Programmable AND Array
03 02 01 00
-$-
+
Indicates Programmable Connection
101730-1
Indicates Fixed Connection
Figure 1. PAL Device Array Structure
Standard Cell Circuits
Standard cell circuits are quite similar to gate arrays,
their main advantage being that they consist of a
collection of different parts of circuits which have
already been debugged. These circuits are then
assembled and collected to perform the desired
functions. This can ideally lead to reduced turn around
from conception to implementation, and a much more
efficient circuit.
The drawback is that even though the individual
components of the circuit have been laid out, a complete
layout must still be performed to arrange the cells.
Instead of just customizing the metal interconnections,
as is done in a gate array, the circuit must be developed
from the bottom up. Development costs can be even
higherthan for gate arrays, and despite the standard cell
5·4
concept, turn around time often tends to be longer than
planned. Again, the volume must be sufficiently high to
warrant the development costs.
Full Custom Circuits
Full custom designs require that a specific chip be
designed from scratch to perform the needed functions.
The intent is to provide a solution which gives the
designer exactly what is needed for the application in
question; no more and no less. Ideally, not a square
micron of silicon is wasted. This normally results in the
smallest piece of silicon possible to fit the needs of the
design, which in turn reduces the system cost.
Understandably, though, development costs and risks
for such a design are extremely high, and volumes must
be commensurately high in order for such a solution to
be of value.
Basic Design with PLDs
AMD~
WHAT ADVANTAGES DO PLDS HAVE
OVER OTHER IMPLEMENTATIONS?
As user-programmable semicustom circuits, PLDs
provide a valuable compromise which combines many
of the benefits of discrete logic with many of the benefits
of other semicustom circuits. The overall advantages
can be found in several areas:
•
Ease of design
•
Performance
•
Reliability
•
Cost savings
Ease of Design
The support tools available for use in designing with
PLDs greatly simplify the design process by making the
lower-level implementation details transparent. In a
matter of one or two hours, a first time PLD user can
leam to design with a PAL device, program it, and
implement the design in a system.
The design support tools consist of deSign software and
a programmer. The design software is used in
generating the design; the programmer is used to
configure the device. The software provides the link
between the higher-level design and the low-level
programming details.
All of the available deSign software packages perform
essentially the same tasks. The deSign is specified with
relatively high-level constructs; the software takes the
design and converts it into a form which the programmer
uses to configure the PLD. Most software packages
provide logic simulation, which allows one to debug the
design before actually programming a device. The
high-level design file also serves as documentation of
the design. This documentation can be even easier to
understand than traditional schematics.
Many PLD users do not find it necessary to purchase a
programmer; it is often quite cost effective and
convenient to have either the manufacturer or an
outside distributor do the programming for them. For
deSign and prototyping, though, it is very helpful to have
a programmer; this allows one to implement designs
immediately.
The convenience of programmable logic lies in the
ability to customize a standard, off-the-shelf product.
PLDs can be found in stock to suit a wide range of speed
and power requirements. The variety of architectures
available also allows a choice of the proper functionality
for the application at hand. Thus, a design can be
implemented using a standard device, with the end
result essentially being a custom device. If a design
change is needed, it is a simple matterto edit the original
deSign and then program a new device, or, in the case of
reprogrammable CMOS devices, erase and reprogram
the old device.
Board layout is vastly simplified with the use of
programmable logic. PLDs offer great flexibility in the
location of inputs and outputs on the device. Since
larger functions are implemented inside the PLD, board
layout can begin once the inputs and outputs are known.
The details of what will actually be inside the PLD can be
worked out independently of the layout. In any cases,
any needed design changes can be taken care of
entirely within the PLD, and will not affect the PC board.
Performance
Speed is one of the main reasons that deSigners use
PAL devices. The PAL devices can provide equal or
better performance than the fastest discrete logic
available. Today's fastest PAL devices are being
developed on the newest technologies to gain every
extra nanosecond of performance.
Performance cannot come strictly at the expense of
power consumption. Since PLDs can be used to replace
several discrete circuits, the power consumption of a
PLD may well be less than that of the combined discrete
devices. As more PLDs are developed in CMOS
technology, the option for even lower power becomes
available, including zero standby power devices for
systems which can tolerate only minute standby power
consumption.
Reliability
Reliability is an area of increasing concern. As systems
get larger and more complex, the increase in the amount
of circuitry tends to reduce the reliability of the system;
there are "more things to go wrong." Thus, a solution
which inherently reduces the number of chips in the
system will contribute to higher reliability. A
programmable logic approach can provide a more
reliable solution due to the smaller number of devices
required.
With the reduction in units and board space, PC boards
can be laid out less densely, which greatly improves the
reliability of the board itself. This also reduces crosstalk
and other potential sources of noise, making the
operation of the system cleaner and more reliable.
Basic Design with PLDs
5-5
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AMD
Cost
For any design approach to be practical, it must be cost
effective. Cost is almost always a factor in considering a
new design or a design change. But, the calculation of
total system cost can be misleading if not all aspects are
considered. Many of the costs can be elusive or difficult
to measure. For example, it is difficult to quantify the
cost of market share lost due to late product
introduction.
The greatest savings over discrete design are derived
from the fact that a single PLD can replace several
discrete chips. Board space requirements can drop 25%
or more when PLDs are used. The relationship between
the various alternatives is summarized in Figure 2.
Cost
Weeks
Months
Years
Development Time
10173D-2
Figure 2. Development Cost vs. Time for Alternative Logic Implementations
5-6
Basic Design with PLDs
AMD~
Another economic benefit of the use of PLDs is that
when one PAL device is used in several different
designs, as is often the case, the user has not
committed that device to anyone of the particular
designs until the device has been programmed. This
means that inventory can be stocked for several
different designs in the form of one device. As
requirements change, the parts can be programmed to
fit the need. And in the case of reprogrammable CMOS
devices, one is not committed even after programming.
One final subtle cost issue is derived from the ease with
which a competitor can copy a deSign. PLDs have a
unique feature called a security bit, whose purpose is to
protect a design from being copied. By using secured
PLDs extensively in a system, one can safely avoid
having one's system easily deciphered. The added
deSign security provided by this feature can buy extra
market time, forcing competitors to do their own original
design work rather that copying the designs of others.
By assuming some of the attributes of gate arrays,
programmable logic provides the cost savings of any
other semicustom device, without the extra engineering
costs, risks, and design delays. Reliability is also
enhanced as quality increases and board complexity
decreases.
The design tasks are greatly simplified due to the design
tools which are now available. Design software and
device programmers allow top-down high-level designs
with a minimum of time spent on actual implementation
issues. Simulation allows some design debug before a
device is programmed.
For all of these reasons, programmable logic has
become, and will continue to be, the deSign
methodology of choice among digital systems
designers.
Summary
Programmable logic provides the means of creating
semi-custom designs with readily available standard
components. There is a wide variety of PLDs; PAL
devices are most widely used, and perform well for basic
logic and some sequencing functions.
Basic Design with PLDs
5-7
PLD Design Basics
INTRODUCTION
This section is intended as a beginner's introduction to
PLD design, although experienced users may find it a
good review. We will take a step-by-step approach
through two very simple designs to demonstrate the
basic PLD design implementation process. Through this
. effort, you will be introduced to the concept of device
programming.
A
C ---t------1
D
F --t-----\
G ---+-----1
M
N
As can be seen from the figure, there will be six separate
functions involving a total of twelve inputs. It is important
to bear in mind that programmable logic provides a
convenient means of implementing designs. With a real
design, some work would be required before this pointto
conceptualize the deSign, but due to the simplicity of
these circuits, we are already in a position to start the
implementation.
5-8
E
L
---t----~
---t-----I
D------+-- 0
P
R
10173D-3
Figure 1. The Basic Logic Gates
Building the Equations
We will start by generating Boolean equations. The first
function to be generated is an inverter. This is specified
according to Figure 1 as:
B
The first example we will try is a very simple
combinatorial circuit consisting of all of the basic logic
gates, as shown in Figure 1. This will be helpful forthose
designs where you are integrating random logic into a
PAL device to save space and money.
B
l-------+-- H
Q --t-----I
We will take no significant shortcuts for these examples,
even though there may be times when we could. In this
way, you can gain a better understanding of exactly
what is happening as you implement your design.
Constructing a Combinatorial
Design-Basic Gates
l---~-
I
J
K
By "beginner," we mean a logic designer who is just
beginning to use programmable logic. You may have a
lot of experience with discrete digital logic, or you may
have just graduated from college. We assume a basic
understanding of digital logic. Some computer
experience is helpful, but not essential.
We will talk about device programming, describing all of
the steps that are necessary to program a PLD.
However, due to the wide variety of programmers
available, we will not get down to the level of detail that
, tells you exactly which buttons to push. Although we will
get as close as we can, we must defer the details to your
programmer manual.
--~------~ ~o-------+--
= fA
Here the "equal" sign (=) is used to assign a function to
output B. The slash (/) is used to indicate negation.
Thus, this equation may be read:
B is TRUE if NOT A is TRUE
The next function is a simple AND gate. As shown in
Figure 1, we can write:
E
= C*D
Here we use the "equal" sign again, but this time we
have introduced the asterisk (*) to indicate the AND
operation. This equation may be read:
E is TRUE if C AND D are TRUE
PLD Design Basics
AMO;t1
The third function is an OR gate, which may be written:
H = F + G
The "plus" sign (+) is used to specify the OR operation
here. Because of the sum-of-products nature of logic as
implemented in PLDs, it is often easy to place product
terms on separate lines, which improves the readability.
We may rewrite this equation as:
H
=
I(x *
I(X +
Y)
Y)
Ix + IY
= Ix * IY
=
We may generate our NAND function by writing:
L
= I (I *
J
*
K)
or, if preferred,
II
L
+ IJ
F
+
+ G
IK
This equation may be read:
Likewise the NOR function may be specified as:
H is TRUE if F OR G is TRUE
o
I
+
For the moment, we will assume that we have
active-HIGH outputs on our device. The functions we
have generated so far have essentially been
active-HIGH functions. At times we wish to generate
active-LOW functions; the next two functions are
active-LOW functions that we wish to implement in an
active-HIGH device.
When we talk in terms of an active-HIGH or an
active-LOW device, the real question is whether there is
an extra inverter at the output. An active-HIGH device
has an AND-OR structure; an active-LOW device has
an AND-OR-INVERT structure which inverts the
function at the output (see Figure 2).
(M
N)
or
o = 1M * IN
Finally, an exclusive-OR (XOR) gate may be specified
either as:
R
=
P :+: Q
where :+: represents the XOR operation, or more
explicitly as:
R
= P * IQ
+ Ip * Q
We have now specified all of the functions in terms of
their Boolean equations. The equations are
summarized in Figure 3.
a. AND-OR Structure
B
IA
E
C
H
inverter
*
D
F
AND gate
OR gate
+ G
L
II
NAND gate
+ IJ
+ IK
0
b. ANO-OR-INVERT Structure
10173D-4
Figure 2. Active HIGH vs. Active LOW
R
1M * IN
P * IQ
+ Ip * Q
NOR gate
XOR gate
Figure 3. BaSic Gates Equations
NAND and NOR gates could be generated very simply
in an active-LOW device, because we would just have to
generate AND and OR functions, and let the output
inverter generate their complements. However, given
that we wish to implement these functions in an
active-HIGH device, we must invoke DeMorgan's
theorem, as follows:
PLD Design Basics
5-9
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AMD
very wide gates, which can be cumbersome to draw. To
save space, the product terms are drawn as horizontal
lines with a small AND gate symbol at one end to
indicate the function being performed.
Understanding the Logic Diagram
A portion of a logic diagram is shown in Figure 4.
The logic diagram shows all of the logic resources
available in a particular device. In each device, inputs
are provided in true and complement versions, as
shown in Figure 4. These drive what are often called
"input lines," which are the vertical lines in the logic
diagram. These input lines can then be connected to
product terms. The name "product term" is really just a
fancy name for an AND gate. However, PLDs provide
)}::.:.:.,.:.:.: ,.:.:. '.:.'
..... ::.:. .:.:.:.:.:.:.:....:.: I.:.:.',:,:,',:,',:,'
l
48 -t-\::::::.:.:t.I:.t:.:I:.-r:.:
. :.:.:.t:.:-.:.:.:.:.:.:.:.t:.:i.:
.. -...
":':"1":"':"':':"':':'
Although you really do not need to be concerned with
the actual implementation of these functions inside the
PAL device, you may be curious. Figure 5 shows how
the inverter and the AND gate are implemented. An 'X'
indicates a connection. A product term that is not used is
indicated by an 'X' in the small AND gate.
.... , .. .:.:..... :.:.:.:.: ...... ,.:.:.:.:... :.....:.: ........... ,.:.:.:
~:~==~;~==:t1=::j-.
~
I.:.:.:.:.:"':':':" . .
I~:.:;~t~:~=.:.:.:W.-+-·.I-..-I. . .:.o=t--,
4. .
:.l-.:.:.-:.:.:.:.:.:.:.+:
....
P+oduct
-D-J
49
arm
50-rrt-t--t--t-t-t--t+--+-f--H-t-+---J-+-I-J--U-ll-lQ--I1D-13
51---rtTt--t~Hr--rt--~--+4--~--~~+--+~~-I~
< .... :::..
<.....
\
\
\
\
9
\
o 123
456 7
8 9
1213
1617
2021 24252627 28293031
12
11
\
\
Input Lines
True and
Complement Inputs
10173D-5
Figure 4. A Portion of a Logic Diagram
5-10
PLD Design Basics
AMD~
...
~
A
Y"
E
c
-cr:
....
B
...
~.
D
Y""
10173D-6
Figure 5. Implementation of NOT, AND Gates
Building the Design File
Simulating the Gates
Once the design has been conceptualized, the design
file must be generated.
After you have verified that your design file is correct, it
is time to verify that the design itself is correct. This is
done by simulating the design. Simulation provides a
way for you to see whether your design is working as
you expect it to. You provide a series of commands, or
events, which are then simulated by the software. If
requested, the software can tell you if the simulation
matches what you expect, and, if not, where the
problems are.
We now know exactly what our functions are going to
be. We have twelve inputs, six outputs, and the NAND
function requires three product terms. Note that if we
had specified:
L = I
(I * J * K)
instead of:
L
II
+ IJ
+ IK
forthe NAND gate, it would not be as obvious how many
product terms would be needed.
We are now in a position to create the design file. The
design entry varies with the software package used.
You must consult the manuals supplied with the
software for design entry format.
Generating a JEDEC File
Once the design file has been entered, you can
assemble the design to get a JEDEC file. We have two
purposes here: to make sure there are no basic
mistakes in the file, and to generate a JEDEC file for
programming. Again, how this is done is determined by
the software.
The simulation section is the last part of the design file. It
is not required, but is invariably helpful both in
debugging the design, and in generating what can
eventually be used as a portion of a test vector
sequence.
The simulator also converts the simulation results into
test vectors, and appends the vectors to the JEDEC file.
This file can be used with programmers that provide
functional tests.
Constructing a Registered DesignBasic Flip-Flops
Next we will do a very simple registered design: we will
be designing all of the basic flip-flop types (Figure 6). We
will conceptualize the design by reviewing briefly the
behavior of the D-type flip-flop. We will then present the
results for T, J-K, and S-R flip-flops.
PLD Design Basics
5-11
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AMD
The devices we will be using in the examples only have
D-type flip-flops. Thus, we will be emulating the other
flip-flops with D-type flip-flops.
D - I I - - - - - - - - + _ DT
ClR
b. DT= 0
I
ClK
o
0
~t>
Co
OT
po
DC
o
I
I
Co
IT
.-1> po
TC
T
T
D
c. DT:= 0
101730-8
I
J
Figure 7. Registered vs. Combinatorial Equations
Co
JKT
po
JKC
.-t>
K
"
K
I
S
Co
SRT
po
SRC
-t>
R
R
I
PR
101730-7
Figure 6. Basic Flip-Flops
Building the 0-Type Flip-Flop Equations
A D-type flip-flop merely presents the input data at the
output after being clocked. Its basic transfer function
can be expressed as:
DT :
=
We can also generate the complement signal (named
DC) with the statement:
DC : = ID
I
S
D
where we have used pins DT (D True) and D as shown in
Figure 6.
As shown in Figure 6, we want to add synchronous
preset and clear functions to the flip-flops. This can be
done with two input pins, called PR and ClR. To add
these functions to the true flip-flop signal, we add IClR
to every product term and add one product term
consisting only of PR. Likewise, for the complement
functions, we add IPR to every product term, and add
one product term consisting only of ClR. With these
changes, the equations now looks like:
DT '= D * ICLR
+ PR
DC
'=
+
ID
* IpR
CLR
In this way, when clearing the flip-flops, the active-HIGH
flip-flops have no product terms true, and go lOW; the
active-lOW flip-flops have the last product term true,
and will therefore go HIGH. The reverse will occur for
the preset function.
Note the use of ':=' here instead of '='. This indicates that
the output is registered forthis equation. The difference
is illustrated in Figure 7.
5-12
OT
ClK
I
J
0
PlD Design Basics
AMD~
There is still one hole in this design: what happens if we
preset and clear at the same time? As it is right now,
both outputs will go HIGH. This makes no sense since
one signal is supposed to be the inverse of the other. To
rectify this, we can give the clear function priority over
the preset function. We can do this by placing lelR on
every product term for the true flip-flop signal. The
results are shown as follows:
DT
D * /CLR
+ PR * /CLR
DC
/D * /PR
+ CLR
The same basic procedure can be applied to all of the
other flip-flops. The equations are shown in Figure 8.
EQUATIONS
;emulating all flip-flops with D-type flip-flops
DT := D * /CLR
+ PR * /CLR
DC := /D
+ CLR
TT := T *
+ /T *
+ PR *
TC := T *
+ /T *
+ CLR
*
/PR
;output is D if not clear
;or 1 if preset and not clear at the same time
;output is /D if not preset
iOr 1 if clear
/TT * /CLR
TT * /CLR
/CLR
igo HI if toggle and not clear
istay HI if not toggle and not clear
igo HI if preset and not clear at the same time
/TC * /PR
TC * /PR
igo HI if toggle and not preset
istay HI if not toggle and not preset
go HI if clearing
JKT:= J * /JKT * /CLR
+ /K * JKT * /CLR
+ PR * /CLR
;go HI if J and not clear
;stay HI if not K and not clear
;go HI if preset and not clear at the same time
JKC:= /J * /JXC * /PR
+ K * /JKC * /PR
+ CLR
;go HI if not J and not preset
;stay HI if not K and not preset
;go HI if clear
SRT:= S * /CLR
+ /R * SRT * /CLR
+ PR * /CLR
SRC:= R * /PR
+ /S * SRC * /PR
+ CLR
;go HI if set and not clear
;stay HI if not reset and not clear
;go HI if preset and not clear at the same time
igo HI if reset and not preset
;stay HI if not set and not preset
;go HI if clear
Figure 8. Flip-Flop Equation Section
Building the Remaining Equations and
Completing the DeSign File
Notice that in some Of the equations above, the output
signal itself shows up in the equations. This is the way in
which feedback from the flip-flop can be used to
determine the next state of the flip-flop. An equivalent
logic drawing of the TT equation is shown in Figure 9.
PLD Design Basics
5-13
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AMD
ClK ----------------------------~
ClR
T
l--+------I D
Qt-tI--- IT
PR - - - - - - - - - 1 - - - - 1
IT!1:= T* [Z!I] * IClR
+ T* [fIT) * IClR
10173D-9
+ PR*/ClR
Figure 9. Feedback In the Equation for TT
We are now in a position to complete the design file. You
must follow the instructions included with your software
.
package to complete the file.
Simulating the Flip-Flops
After processing the design and correcting any
mistakes, we can run the simulation.
The file can now be simulated in the same manner as
the basic gates design.
10173D-10
Figure 10. A Connector Must Be Provided
Between the Computer and the Programmer
Programming a Device
~ft~r simulating the
design, and verifying that it works, it
time to program a device. There are several steps to
programming, but the exact operation of the
programmer naturally depends on the type of
programmer being used. We will be as explicit as we can
here, but you will need to refer to your programmer
manual for the specifics.
IS
The first thing that must be done after turning the
programmeron is to select the device type. This tells the
programmer what kind of programming data to expect.
The device type is usually selected either from a menu
or by entering a device code. Your programmer manual
will have the details.
Next a JED EC file must be downloaded. To transfer the
JEDEC file from the computer to your programmer, you
will need to provide a connection, as shown in Figure 10.
5-14
If your programmer can perform functional tests, and
you wish for those tests to be performed, you should
download the JEDEC file containing the vectors;
otherwise, you should download the JEDEC file without
vectors.
To download data, the programmer must first be set up
to receive data. The programmer manual will tell you
how to do this.
Communication must be set up between the computer
and the programmer. Whichever communication
program is installed must be invoked. This is used to
transmit the JEDEC file to the programmer. Follow the
instructions for your program to accomplish the
next steps.
PLD Design Basics
AMD~
Before actually sending the data, you must verify the
correct communication protocol. Check to make sure
you know what protocol the programmer is expecting;
then set up the baud rate, data bits, stop bits, and parity,
to match the protocol.
Once the protocol has been set up the JEDEC file must
be downloaded.
.
Enter the name of the JEDEC file you wish to use. The
computer will then announce that it is sending the data,
and tell you when it is finished. Note that just because it
says it has finished sending data does not mean that the
data was received. Your programmer will indicate
whether or not data was received correctly.
Once the data has been received, the programmer is
ready to program a device. Place a device in the
appropriate socket, and follow the instructions for your
programmer to program the device. This procedure
programs and verifies the connections in the device,
and, if a JEDEC file containing vectors was used, will
perform a functional test.
The programmer will announce when the programming
procedure has been completed. You may then take the
device and plug it into your application.
If you have actually programmed one of the examples
that we created above, you naturally don't have a board
into which you can plug the device. If you do have a lab
setup, you may wish to play with the devices to verify for
yourself that the devices perform just as you expected
them to.
You will find much more detail on many issues that were
not discussed in this section in the remaining sections of
this handbook. This section should have provided you
with the basic knowledge you need to understand the
remaining design examples in this book, and to start
your own designs.
PLD Design Basics
5-15
PLD Design Methodology
Programmable logic devices (PLDs) are used in digital
systems design for implementing a wide variety of logic
functions. These logic functions range from simple
random logic replacement to complex control
sequencers. Programmable logic devices offer the
multiple advantages of low cost, high integration, ease
of use, and easier design debugging capability not
available in other systems design options. In the
following discussion we will detail the PlD design
process.
Most PlDs have an AND-OR array structure with
programmable connections in either or both of the
arrays. A programmable array implies that the
connections can be programmed by the user. The .
popular PAL (Programmable Array Logic) devices have
a programmable AND array and a fixed OR array. PAL
devices are used for a wide variety of combinatorial and
registered logic functions. In this discussion we will also
examine the various design constraints to be
considered when selecting the correct architecture for a
given application.
tables. Occasionally Karnaugh maps and state
diagrams are also used. The design file is then
assembled to produce the "JEDEC"file. The JEDEC file
gets its name from the fact that it is an approved JEDEC
standard for specifying the state of every connection on
the device. Simulation can then be performed. If the
design is correct, the JEDEC file is downloaded into a
device programmer for programming the connections
on the device. The device can then be plugged into the
PC board where it will function. The entire procedure
can often be performed with the designer never having
to leave the desk. Most programmers interface to
personal computers, so that the design file can be
edited, assembled, simulated, and downloaded, and the
device programmed, all in one place.
All digital logic can be efficiently reduced to two
fundamental gates, AND and OR, provided both true
and complement versions of all input signals are
available. Such logic is generally built around what is
known as the sum-ot-products (AND-OR) torm.
Programmable logic devices are ideal for implementing
such two-stage logic in the AND and OR arrays.
Various process technologies offer many design
options for PlDs. The connections in the programmable
arrays can be fuse-based, commonly used in both ECl
and TTL bipolar technologies, E/EEPROM cell based in
UV-EPROM and EEPROM CMOS technologies, and
RAM cell-based in CMOS RAM technology. The
selection of technology is mostly dependent upon the
system speed and power constraints. Most design
engineers are familiar with these constraints, which not
only dictate the technology of PlDs but also all of the
other logic used in a system.
Designing with PlDs involves the use of design
software and a device programmer (Figure 1). The
design software eliminates the need to identify every
connection to be programmed for implementing the
desired sum-of-products logic. The design process
begins with the creation of a design file which specifies
the desired function. The function is typically
represented by its sum-of-products form and can be
derived directly from the timing diagram and/or truth
5-16
JEOEC
FLE
101730-11
Figure 1. PLDs are Designed Using Software and a
Device Prog rammer
The first stage in a PlD design process (Figure 2) is the
conceptualization of a design problem; the second is the
selection of the correct device; the third is the
implementation of the deSign, which also includes
simulating the deSign with test vectors; and finally, the
PLD Design Methodology
AMD~
actual programming and testing on a system board. We
will take a simple design example and go through the
various stages of this design process.
Conceptualize A
Design Problem
!
Select Device
!
Implement
Design
!
We will take the example of a simple address decoder
circuit required for a 68000 microprocessor. The
microprocessor has 24 address lines along with
separate read and write signals. It requires some ROM
to store the boot-up code as well as some RAM for
storing and executing programs. The purpose of the
address decoder circu itry is to select one of the memory
addresses at a time. The RAMs and ROMs are assigned
addresses on the 68000 microprocessor address
space. The Address decoder circuit has to select one of
the RAMs or ROMs for a specific range of addresses,
called the address space. This selection is
accomplished by asserting the specific chip-select
signal for the RAM or ROM when the microprocessor
accesses one of the addresses in the address space.
There is additional circuitry in a typical microprocessor
system for addressing 1/0 devices (such as disk
controllers). These devices also require that chip-select
signals be asserted when the microprocessor
addresses them. Figure 3 shows an example address
map for a 68000 microprocessor.
Program PLD
!
Test PLD
PROM 1
OOOOOO-OFFFFF
PROM 2
100000-1FFFFF
DRAM 1
200000-2FFFFF
DRAM 2
300000-3FFFFF
DRAM 3
400000-4FFFFF
DRAM 4
500000-5FFFFF
-----------
!
-----------
-----------
Plug PLD
Into Board
101730-12
600000-6FFFFF
Figure 2. Programmable Logic Device Design
Process
101730-13
Figure 3. Memory Address Map
Conceptualizing a Design
The first step in the PLD design process is also required
for any SSI/MSI design. An advantage of PLDs is that at
this stage the designer needs to be concerned only with
the required logic function. With SSI or MSI, various
device logic limitations must be accounted for before the
design can be started. Clearly a designer needs to
develop a brief and complete functional description,
based upon the system design requirements.
PLD Design Methodology
5-17
~
AMD
±
Top
Reset
Button •
Bottom
_INIT
Interface
Logic
RW
~
RESET
ROMCS1
.J
I
ROMCS2
AS
I
I
RAMCS
A21,A22,A23
DRAM
Controller
/
M68000
Microprocessor
/2
PROM1
A22,A23
PROM2
H
DRAM1
~
DRAM2
H
rl
DRAM3
DRAM4
rr-
Read
}
Only
~
r----.
r----.
r----.
Read &
Write
DO-16
101730-14
Figure 4. Microprocessor to Memory Interface
Figure 4 show the circuit diagram. The address signals
from the 68000 microprocessor are inputs to the
interface logic block. The outputs generated are
ROMCS1, ROMCS2 and RAMCS. The generation of
signals for selecting device lias is similar and is not
shown here for the sake of simplicity. Other system
inputs to the interface are the address strobe signal
generated by the 68000 microprocessor as well as the
read/write signal. The truth table for generating the
outputs is shown in Table 1. This truth table is derived
from the memory address map and the functional
description of the design.
Table 1. Truth Table for Chip-Select Signals
Addresses Hex
Size
A23
A22
A21
Signal
OOOOOO-OFFFFF
1 MB
a
a
a
ROMCS1
1
ROMCS2
1
a
RAMCS
1
1
RAMCS
depends upon the functional nature of the problem.
Sometimes timing and logic considerations can also
dictate the use of registers; this will be discussed later.
Registers are usually not required for such simple
combinatorial functions such as encoders, decoders,
multiplexers, demultiplexers, adders, and comparators.
However, registers are required for functions such as
counters, timers, control signal generation, and state
machines. No registers are required for this simple
address decoding example.
The best choice for our combinatorial design would be a
PAL device. The task now is to select a PAL device for
implementing the desired function. General device
selection considerations are listed below. These items
are applicable to most designs.
100000-1FFFFF
1 MB
200000-2FFFFF
1 MB
300000-3FFFFF
1 MB
a
a
a
a
400000-4FFFFF
1 MB
1
0
0
RAMCS
• Number of I/O pins
500000-5FFFFF
1 MB
1
0
1
RAMCS
• Device speed
• Number of output pins
• Device power requirements
Device Selection Considerations
The first task for the designer is to identify the design
problem and classify it as a combinatorial function or a
registered function, depending upon whether or not
registers are required. In most cases, this decision
5-18
• Number of input pins
• Number of registers (if any)
• Number of product terms
• Output polarity control
P.LD Design Methodology
AMD~
-
Address
Decoding
Time
Memory Access Time
Address
Decoding - - Time
:1::~~~_-_1_0_n_s~~~~~~_""'_".I_"~~~~~~~===-- ::: :: ==========:":14=====~_1o_ns_-_-_-_-_-_::~I
ReadlWrite Cycle Time
101730-15
Figure 5. System Timing Requirements
The first resource that must be provided in a PLD is the
numberof pins needed forthe basic logic function. This
consists of the number .of input and output pins. Many
PLDs have internal feedback, which allows the
generated output signal to be reused as an input. The
same feedback also allows the pin to be used as a
dedicated input, if required. This is especially useful for
fitting various designs with different input/output
requirements on the same device. The I/O pin capability
of certain PLDs can also be very useful for certain bus
applications.
hold a signal stable forthe long durations required by the
addressed peripheral or memory. However, this slows
the initial response or access time of the device since
the chip select must wait for the setup time before the
rising edge of the clock cycle. Devices without registers
provide fast access time but hold the signal valid only as
long as the input conditions are valid. In most address
decoders, the address signals are- kept asserted by the
microprocessor until the read/write cycle is completed.
lnthis case, the registers are not required for holding the
signals asserted.
The task is as simple as counting the number of input,
output and I/O pins required by the design and picking a
PLD which has the requisite number of pins.
The remaining two general design considerations are
the number of product terms and output polarity. We will
discuss these two as we implement the design in the
next section.
The next selection issue is the device speed. The most
important timing consideration for combinatorial PLDs is
the propagation delay (tPD) of signals from the input to
the output of the device. For registered PLDs, the
important timing consideration is the device clocking
frequency. This clocking frequency is in turn determined
by sum of the register setup time (ts), and
clock-to-output propagation delay (teo). Most systems
impose some timing restrictions on the internal logic
functions. These restrictions will determine the
necessary tPD (for combinatorial devices) or fMAX (for
registered devices).
In our design example, the PLD will primarily perform
address decoding. The critical system timing constraint
is determined by the read/write cycle time of the
microprocessor and the memory access time available
(Figure 5). Most microprocessors allow anywhere from
10 to 35 ns for address decoding. That is, 10 ns - 35 ns
after the address is available, the correct memory
chip-select signal should be asserted. In our design
example, the available cycle time of 240 ns and memory
access time of 220 ns leaves barely 10 ns for address
decode time. We can check the propagation delay and
select the appropriate speed device for our design,
which is tPD = 10 ns.
.
We have already briefly discussed the types of
applications where registers are needed. Sometimes
the consideration of system timing can affect whether or
not registers are needed. Devices with registers can
Implementing a Design
Implementing a design (Figure 6) requires the creation
of a design file. The design file contains three types of
'
information.
• Basic bookkeeping information
• Design syntax
• Simulation syntax
Once the design file is complete, it is then assembled
and simulated. Once it passes assembly and
Simulation, the resultant JEDEC file is downloaded to a
device programmer for configuring the device.
Design Syntax
In this example, as shown in Figure 6, there are two
options available to the designer for expressing the
design. The first is through traditional Boolean logic
equations; the second is through a state machine
syntax. The Boolean logic equations are the only option
for combinatorial designs and can also be efficient for
some registered deSigns. The Boolean equations can
be derived from a combination of the functional
description, the truth table and/or the timing diagrams
(Figure 7). The state machine approach is ideal for large
registered control designs, and can be derived from the
functional description, state table, state diagram and/or
the timing diagram (Figure 8).
PLD Design Methodology
5·19
~
AMD
Functional
Description
Assemble
Design File
101730-17
Figure 7. Writing Boolean Logic Equations
10173D-16
Figure 6. Implementing a Design
5-20
PLD Design Methodology
AMD~
.------------------------~
Functional
Description
State Table
Assemble
Design File
10173D-18
Figure 8. State Machine Description
Boolean Logic Equations
Boolean
equations are used to represent the
~um-of-pr?ducts logic form. The Boolean equations are
Ideally sUited for representing the two-level AND-OR
logic available in most PLDs.
A conventional approach to the design is to convert the
design problem to its discrete logic implementation.
~uch random SSI and MSI logic can be easily
Implemented in PLDs. This usually involves converting
to sum-of-products Boolean logic form. This approach
?an be a chore, and much effort can be saved by
Imple':Tlenting a design with PLDs in a sum-of-products
form right from the start. This essentially means that the
designer does not have to design around the limitations
of fixed SSI and MSI functions. A direct implementation
of a design in sum-of-products form in a PLD can also
yield a faster circuit.
Boolean equations can be directly derived from the truth
table or timing diagram (Figure 7). The truth table is
used more often in simple combinatorial designs. The
timing diagram method is used more often in registered
control 'deSigns. We will first discuss the truth table
method and then discuss the details of the timing
diagram method.
In addition to specifying the logic function, the Boolean
in the design file help document the design.
There IS no need to draw out an equivalent schematic.
This allows design modularity; the schematic can just
show a bloc~ for a particular PLD. Separate supporting
documentation (the design file) provides the details
without cluttering the drawing.
equati~ns
PLD Design Methodology
5-21
~
AMD
truth table is based upon the functional description of the
design, and is derived from the address map (Figure 3)
and the truth table (Table 1).
Truth-Table-Based Design
The requirements for our particular design example can
be easily converted to a truth table format (Table 2). This
Table 2. Truth Table for the Address Decoder
Output Generated
A23
A22
A21
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
1
IN IT
1
1
1
1
1
1
There are three additional input signals in this design
example. The first, RW, is generated by the
microprocessor, and distinguishes between read and
write cycles. Since the ROM data is only for reading, the
ROMCS1 and ROMCS2 signals are asserted only when
RW is high (when the microprocessor attempts to read
the ROM) and are not asserted for the write cycle. On
the other hand, RAMCS is generated for both read and
write cycles and the state of signal RW is "don't care."
The second additional signal, AS, is the address strobe
signal generated by the microprocessor, and is asserted
only when the address lines carry a valid address. All of
the chip select signals need to be gated with the AS
Signal to ensure that they are only generated for valid
addresses, and no spurious chip selects are generated.
The last signal is the INIT Signal, which is a system
initialization signal. This signal is used to initialize the
microprocessor for a ''warm boot," and none of the chip
selects is allowed when this INIT signal is asserted.
Writing Boolean equations from the above logic is very
straight forward. The output signal names, along with
their polarity, are assigned to sum-of-product equations,
which are based upon inputs and their polarities.
AS
0
0
0
0
0
0
RW
1
1
X
X
X
X
ROMCSl
0
ROMCS2
1
RAMCS
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
0
The equations are derived directly from the truth tables.
Each one of the AND equations uses up one product
term of the device as shown in Figure 9. One device
selection consideration is to ensure that all the outputs
have sufficient product terms to accommodate the
desired function.
This brings us to the issue of output polarity. Suppose
we had to generate active-HIGH outputs. In that case
the output equations for the ROMCS1 signal would be:
ROMCSl = /A23
+ /A22 * /A21 * INIT */AS
*
RW
If the device has active-LOW outputs only, this
equation's output polarity needs to be inverted to be
able to fit the device. Using DeMorgan's theorem for
Boolean logic we get:
/RCMCSl = A23
+ A22 + A21 +
/INIT
+ AS +
/RW
This equation requires a large number of product terms
(six). Some signals are efficient and use fewer product
terms in their true form, while others are more efficient in
their inverted form. The device selection issues of
product terms and output polarity also apply to
registered designs.
Timing-Diagram-Based Design
IA23
IROMCS2 = IA23
lRAMCS = IA23
+ IA23
+ A23
+ A23
IROMCSl
=
* IA22 *
* IA22 *
* A22 *
* A22 *
* IA22 *
* IA22 *
IA21 * INIT
A21 * INIT
IA21 * INIT
A21 * INIT
IA21 * INIT
A21 * INIT
* lAS * RW
* lAS * RW
* lAS
*
lAS
* lAS
* lAS
Figure 9. The Implementation In Boolean
Equations
5-22
Until now, we have discussed a PLD design using truth
tables as the primary design vehicle. In this section we
will attempt a design using a timing diagram as a design
vehicle.
Earlier in the address decoder design we mentioned the
INIT Signal. This IN IT signal essentially an initialization
signal for the entire system. The INIT signal is used
internally (via feedback) for disabling the chip selects
during initialization. Externally it can be used to initialize
PLD Design Methodology
AMO~
other system signals. This INIT signal is generated from
a RESET switch connected to the inputs of the device as
shown in Figure 10.
Most experienced designers understand the tradeoffs
for device selection. They implicitly go through the steps
of design conceptualization and device selection,
explained earlier. They typically draw a block around the
logic being designed, with the previous knowledge that it
would fit a PLD which has sufficient inputs, outputs, las
and product terms.
RESET
Switch
Top
Bottom
Vee
:>
.~
RESET:±:
f
">
.~
TOP
Bottom
PAL Device
Debounce
Circuit
10173D-20
SODOM
Figure 11. Timing Diagram for the
Oebounce Switch
10173D-19
Figure 10. RESET Switch for System Initialization
To avoid unwanted initialization, the RESET switch
must be debounced. That is, we want the INIT signal to
remain HIGH until the switch actually contacts the
bottom side. Once the bottom side is hit, INIT should be
asserted active LOW. Once asserted, it should stay
LOW and not change until the top side is hit again. The
timing requirements of the debounce circuitry are shown
in Figure 11. Signals TOP and BOnOM are inputs to
the programmable logic device. These signals are
activated when the RESET switch touches the top and
the bottom contacts, respectively.
We can formulate the equations by looking at the timing
requirements of the debounce circuitry shown in
Figure 11. The idea is to identify the key elements of this
timing diagram. The arrows in Figure 11 showthe critical
events. The first arrow shows the normal state of all the
pins when the RESET switch is not asserted.
Subsequent arrows show each event in the timing of the
INIT signal, depending upon the movement of the
switch.
The logic level of the signals at each critical event
carries useful logic information for deriving Boolean
equations. This logic information for each event is
converted into direct Boolean equations as shown in
below. For example, at instant 1 the INIT signal remains
HIGH as long as the TOP signal remains LOW; this is
converted to INIT = ITOP * BOnOM.
1. Normal state
INIT
2. Switch travels
from TOP to BOTTOM
INIT
INIT
3. Switch contacts
BOTTOM
/INIT
4. Switch travels
from BOnOM to TOP
/INIT
BOTTOM
=
/TOP
= TOP * BOTTOM *
/BOTTOM
*
/INIT
TOP
*
5. Normal State Again
We can combine the two active-LOW events into one
equation:
/INIT
/BOTTOM
+ /INIT * BOTTOM
PLD Design Methodology
*
TOP
5-23
~AMD
Minimizing, this becomes:
/INIT
=
/BOTTOM
+ / INIT * TOP
This can also be done by way of a truth table and
Karnaugh map.
Table 3. Truth Table of INIT Logic
TOP
BOTTOM
1
1
1
1
1
1
a
a
a
a
INIT1
INIT+
1
a
a
a
a
a
a
a
1
1
a
a
a
a
1
1
1
1
X
X
1
Here TOP or BOTTOM will be LOW if contacted. Note
that both TOP and BOTTOM can not be contacted at the
same time. The truth table of Table 3 yields the
Karnaugh map shown in Figure 12. Grouping the zeros
(because we are using active-LOW outputs) yields the
Boolean equation identical to the one derived from the
timing diagram.
Most experienced deSigners understand the tradeoffs
for device selection. They implicitly go through the steps
of design conceptualization and device selection,
explained earlier. They typically draw a block around the
logic being designed, with the previous knowledge that it
would fit a PLD which has sufficient inputs, outputs, lOs
and product terms.
Simulation
Design simulation is an integral part of the design
process, as shown in Figure 13. The purpose is to
exercise all of the inputs and test the response of
outputs to verify that they will work as desired in the
system. These are essentially test vectors which
designate the state of every input on the device; the
outputs are then checked for an appropriate response.
The simulation test vectors identify any flaws in the
design equations which could affect the logical
operation of the devices programmed. Thus, the
simulation vectors serve as a design debugging tool.
(fOP
IBOTTOM
IRESET
00
01
11
Simulate the
Design with
Simulation Vectors
10
o
10173D-21
Fix
Errors
No
-----e:
Figure 12. Karnaugh Map of INIT Signal Logic
There is essentially no difference between the truth
table and timing diagram techniques for writing Boolean
logic. Also, a careful analysis will indicate that we
implicitly assumed a truth table in the timing diagram
example. Some designers prefer to make a separate
truth table (at least in the first few PLD designs), while
others prefer to design directly from timing diagrams.
While the truth table method allows a more optimal
utilization of product terms, the timing diagram method
is easier to visualize as it retains the design perspective.
In both cases the logic should be minimized by the
design software to ensure that the deSign is testable.
Download JEDEC
File to the Device
Programmer
Program
the PLD
10173D-22
Figure 13. Device Simulation and Programming
5-24
PLD Design Methodology
AMD~
Simulation test vectors will eventually make up part of a
larger set of test vectors called '1unctional test vectors".
These functional test vectors are used to exercise a real
device after programming to identify any individual
devices which are defective. Other means of identifying
defective devices, such as signature analysis, are also
available. In this section we will strictly focus on
simulation vectors.
Simulation is included in the design file along with the
logic equations. There is little standardization in these
simulation expressions among various PLD design
software packages, although most of them rely on test
vectors to exercise the logic.
The simulation vectors or events can be directly derived
from the truth table and the timing diagram of the design.
The logic level and functions of all Signals can be
expanded and rewritten in a test vector form by the
software. For example, the truth table for the address
decoder example discussed earlier can be easily
rewritten as shown in Table 4.
Table 4. Truth Table Used to Derive Simulation Vectors
A23
A22
A21
TOP
BOTTOM
AS
RW
ROMCS1
ROMCS2
RAMCS
INIT
0
0
0
0
0
0
0
0
1
H
H
H
H
H
H
0
0
1
1
0
0
H
H
H
0
1
1
1
1
H
0
0
1
1
1
1
H
H
H
H
0
0
1
1
0
0
0
0
1
1
H
H
H
H
H
0
H
H
0
0
1
1
1
1
0
0
1
1
0
H
H
H
H
H
1
1
1
1
1
0
0
0
0
0
0
H
H
H
H
H
0
0
1
1
0
0
H
H
H
H
H
L
H
H
1
1
1
1
1
0
0
1
1
1
1
1
0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
0
0
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
0
1
1
X
X
0
1
1
1
1
1
These are essentially the simulation vectors which will
allow us to define the inputs to the device and check the
outputs of the device.
The simulator then interprets the design file and
generates the output logic levels and/or waveforms,
which can be checked by the deSigner.
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
Once the simulation is complete, the design file can be
assembled to generate the JEDEC file. In the
proceeding discussions we have assumed prior
knowledge of the design file assembly. The procedure
for assembly varies with different software packages.
PLD Design Methodology
5-25
~
AMD
Device Programming and Testing
Once the design simulation is completed, the final step
is device programming and testing (Figure 14).
Programmers are available from a variety of vendors. It
is important to note that Advanced Micro Devices, Inc.,
qualifies programmers upon verifying that the
algorithms used by the programmers are correct and
that other basic criteria are met. When purchasing a
programmer, check that the programmer is qualified for
the devices you intend to use.
There are two types of programmers available:
menu-driven or device code based. The menu-driven
programmer directly indicates the part type being
programmed, whereas the latter type requires the user
to enter the device code before programming.
Once the JEDEC fuse file has been downloaded, the
programmer can program the device; the PLD is then
ready for use. The programmer also verifies the
connections after the programming cycle. Programmers
also provide the capability of reading a previously
programmed device and creating duplicates of that
device.
Testing PLDs
Download JEDEC
File to Device
Programmer
The testing of PLDs can be performed by the device
programmer or by other test equipment. For a
manufacturing environment, where high yields are
required, device testing is critical. After testing is
complete, the device security bit may be programmed, if
desired, to secure the design from copying.
Program
OPLD~
Performed by
Device
/
Test PLD with
Simulation and
Other Test Vectors
I
I
Programmers
Test
PLD
10173D-23
Figure 14. Device Programming and Testing
5-26
PLD Desig n Methodology
Combinatorial Logic Design
INTRODUCTION
In this section we will take a detailed look at several aspects of combinatorial logic design. Most combinatorial
design applications can be easily segmented into five
major fields.
•
•
•
•
•
co}
Encoder
C1
Encoded
Outputs
Encoders and Decoders
Multiplexers
10173D-24
Comparators
Figure LA Block Diagram of an Encoder
Adders and Arithmetic Logic
Latches
Table 1. Truth Table of a Typical Encoder
We will not only focus on the design methodology for
these functions, but will also explore further functionspecific PLD selection requirements. Generalized
designs will be developed, which can be customized
later to suit specific system applications. Ways of optimizing the design will also be discussed.
Encoders and Decoders
Two of the most important functions required in digital
design are encoding and decoding. The encoding and
decoding of data are used extensively in digital communications as well as in peripherals. Both these areas use
various complex encoding and decoding techniques.
Most of these techniques are extensions of the simple
encoding and decoding techniques often used in other
digital designs. In this discussion we will focus on simple
encoding and decoding techniques. More complex
techniques will be discussed later.
Encoders
A binary code of n bits can be used to represent 2n distinct pieces of coded data. A simple combinatorial
encoder is a circuit which generates n bits of output information based upon one of the 2n unique pieces of
input data information. This encoding of information is
controlled by other independent control signals in a typical digital circuit.
An illustration of a typical encoder is shown in Figure 1.
The deSign methodology typically followed is based on
truth tables (Table 1), from which the Boolean equations
are directly derived forthe design. The same generic device selection considerations discussed in the section
on PAL device design methodology apply for encoder
and decoder deSigns.
Inputs
Outputs
A
8
C
D
CO
C1
1
a
0
0
0
1
0
0
0
a
1
0
0
0
0
1
L
L
H
H
L
H
L
H
The Boolean equations can then be optimized using
Karnaugh maps or the software minimizer.
The resulting Boolean equations are:
el
/A
+ /A
eo
/A
+ /A
*
*
B
/B
*
*
/B
/B
* /e
* /e
e
* /e
*
*
/D
D
*
*
/D
D
A Priority Encoder
Let us take another look at the encoder example of Table 1. In this example it is assumed that only one of the
inputs A, B, Cor D is asserted HIGH at anyone time. If
two of the inputs are asserted HIGH simultaneously, a
conflict would be created. To resolve this, a priority
needs to be assigned to each of the inputs. Such a priority assignment is used to select a particular element
when several inputs are asserted simultaneously. Each
input is assigned a priority with respect to the other inputs. The output code generated is the code assigned to
the highest priority input asserted.
Thus, a priority encoder is a combinatorial circuit block
similar to a general encoder, except that the inputs are
assigned a priority. Such priority encoders are used
often in state machine applications, where they detect
Combinatorial Logic Design
5·27
~
AMD
the occurrence of the highest priority event. They are
also used for microprocessor interrupt controllers,
where they detect the highest priority interrupt. Another
use for priority encoders is in bus control, where they are
used in arbitration schemes for allowing selective access to the bus.
The model of a priority encoder is shown in Figure 2. The
four input signals are A, B, C and D. These are to be encoded as LL, LH, HL and HH outputs. Let us assign
priority to Dover C, Cover B, and B over A. The next
design step would be to modify the truth table (Table 2)
to reflect these priorities.
The Boolean equations, directly derived from the truth
table, are:
Cl
/A
+ /A
+
+
co
/A
+ /A
+
+
*
*
*
*
B
/B
B
* /e
*
/B
/B
* C
* /C
*
*
*
*
/C
/C
C
*
*
*
/D
D
/D
D
/D
D
/D
D
These equations can be further optimized by the design
software to the following:
Cl
Cl
D
D
+
/C
+
C
*
B
A
B
C
Although a priority encoder is a purely combinatorial
function, output registers are frequently used to hold the
output signal stable for longer durations.
CO
Priority
-Encoder
C1
Decoders
D
10173D-25
Figure 2. A Four-Input Priority Encoder
Block Diagram
Table 2. Priority Encoder Truth Table
Inputs
Outputs
A
8
C
0
CO
1
0
1
a
1
0
0
0
L
0
0
0
0
0
0
0
1
X
X
X
1
X
X
0
0
0
5-28
1
X
1
C1
L
L
H
H
H
H
L
H
H
H
Priority
L
Assignments
H
L
A decoder performs the reverse function of an encoder.
It converts an n-bit code to one of its 2n unique items. It is
a combinatorial circuit designed such that at most one of
its several outputs will be asserted based upon the
unique input codes.
A decoder may have as many outputs as there are possible binary input selection combinations. As shown in
the truth table (Table 3), only one output may be asserted at any time. When a new combination is applied,
another output is asserted and the original output is returned to its non-asserted state.
Combinatorial Logic Design
AMD~
Table 3. The Truth Table of an Active-LOW 4-to-16 Decoder
Input Select Lines
Output Lines
A
B
C
D
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
02
1
1
0
1
1
1
1
01
1
0
03
1
1
1
04
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The Boolean logic equations can be directly derived
from the truth table shown in Figure 5. The procedure is
the same as explained in the previous section on PLD
design methodology. The Boolean equations derived
are shown in Figure 3.
/QO
/Ql
/Q2
/Q3
/Q4
/Q5
/Q6
/Q7
/Q8
/Q9
/Ql0
/Qll
/Q12
/Q13
/Q14
/Q15
/D
/D
/D
/D
/D
/D
/D
/D
D
D
D
D
D
D
D
D
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/e
/e
/e
/e
.e
e
e
e
/e
/e
/e
/e
e
e
e
e
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/B
/B
B
B
/B
/B
B
B
/B
/B
B
B
/B
/B
B
B
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
05
1
1
1
1
1
/A
A
/A
A
/A
A
/A
A
/A
A
fA
A
fA
A
/A
A
Figure 3. Decoder Boolean Logic Equations
Probably the most commonly used decoders are the address decoders required by most microprocessors and
bus interfaces. These also constitute the most common
application of PLDs in digital designs. The design considerations for address decoders have been covered
earlier in the PLD Design Methodology section. Laterwe
will develop a general Boolean equation for an address
decoder circuit when we discuss range decoders.
OS
1
1
1
1
1
1
1
0
1
1
1
1
1
1
07
1
1
1
1
1
1
1
OS
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
09 010 011 012 013 014 015
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
a 1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
Encoder/Decoder Device Selection
Considerations
The general device selection considerations are listed
below. Based upon the number of inputs and outputs required, a device can be selected.
•
•
•
•
•
•
•
•
Number of Input Pins
Number of Output Pins
Number of I/O Pins
Device Speed
Device Power Requirements
Number of Registers
Number of Product Terms
Output Polarity Control
Encoders typically require a large number of inputs and
fewer outputs, whereas decoders typically require a
large number of outputs and fewer inputs.
Notice from the truth table that there is no combination
of inputs that will send all the outputs to their non-asserted state. Many designs actually need to be able to
make all outputs inactive. This can be done simply by
putting enable lines in all of the output AND gates. Many
such design modifications can be easily added once the
basic Boolean equations have been derived, instead of
redoing the truth table.
Another important device selection consideration for encoders and decoders is the number of product terms
required for a design. A careful selection of code values
Combinatorial Logic Design
5-29
~
AMD
(and priority assignments in priority encoders) can often
reduce the required number of product terms. This can
sometimes determine whether or not a design fits a device successfully. Figure 4 shows the truth tables of two
simple partial 3-to-2 encoders. The product terms required for the two designs are different due to the
different assignment of encoded bits.
Inputs
Outputs
Inputs
Outputs
A
B
C
X1
XO
A
B
C
X1
XO
~
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
Xl
XO
0
/A * /B * C
/A * /B *
Ic
Xl
XO
/A * B *
+ IA */B *
A * IB *
+ /A * IB *
Table 4. Truth Table for a Three-to-One
Multiplexer
Select
Inputs
A
11CO
11C1
11C2
01Y
0
0
0
0
1
1
0
0
1
1
0
0
0
1
X
X
X
X
X
X
0
1
X
X
X
X
0
1
0
1
0
1
0
1
C
IC
C
10173D-26
X
X
Deriving the Boolean equation from this truth table is a
straight forward task. In this case no further minimization is possible. The Boolean equation is:
IOlY
IC
Output
B
+
+
IB
*
/A
*
/B
B
*
A
/A
*
*
IIlCO
/IlCl
IIlC2
*
The equations derived in the above example can be
easily generalized forother multiplexers. The symbol for
a general 2n-inputs-to-one-output multiplexer is shown
in Figure 5 where n select lines are used.
Figure 4. Two Encoders with Different Product
Term Requirements
Anotherway of looking at a decoder is as a logic function
which, depending upon the select code applied, connects one data input to the selected outputs. Also known
as a demultiplexer, a decoder essentially connects an
input to one of 2n outputs based upon n select code bits.
The reverse logic function, which combines data from
multiple sources to an output signal, is called a multiplexer and is discussed next.
10
11
Inputs
. Multiplexer
Y Output
Multiplexers
A multiplexer (sometimes referred to as a data selector)
is a special combinatorial circuit, widely used in digital
design. It is designed to gate one of several inputs to a
single output. The input selected for connection to the
output is controlled by a separate set of select inputs.
The traditional use of a multiplexer is for ''time division
multiplexing" in data communication, when gating several data lines to a single data transmission line for short
intervals of time. The data received is then demultiplexed by using a demultiplexer.
The design methodology employed for multiplexer design is the truth-table approach. As an example, we can
look at a three in put-to-one-output (3:1) multiplexer,
which uses two select Signals A and B. Based on these
two select bits, the data on one of the three inputs is sent
to the output. The truth table is shown in Table 4.
5-30
SO
S1
Sn-1
10173D-27
Input Select Lines
Figure 5. General Model of a 2n-to-1 Multiplexer
Combinatorial Logic Design
AMD~
The Boolean equations are:
Comparators
n=2
A comparator is a combinatorial circuit designed primarily to compare the relative magnitude of two binary
numbers. Table 5 shows the truth table for a two-bit comparator.
Y
/Sl
+ /Sl
+ Sl
+ Sl,
*
*
*
*
IsO
so
ISO
so
*
(IO)
*
*
(Il)
(I2)
*
Table 5. Truth Table for a Comparator
(I3)
Inputs
n=3
Y
= /S2
+ /S2
+ /S2
+ /S2
+ S2
+ S2
+ S2
+ S2
*
*
*
*
*
*
*
*
/Sl
/Sl
Sl
Sl
/Sl
/Sl
Sl
Sl
*
*
*
*
*
*
*
*
ISO
so
ISO
so
ISO
so
ISO
SO
*
*
*
*
*
*
*
*
(IO)
(Il)
(I2)
(I3)
(I4)
(IS)
(I6)
(I7)
Multiplexer Device Selection
Considerations
Multiplexers typically require more inputs than outputs,
so the devices with a large number of inputs and VOs are
usually more useful. Careful consideration must also be
given to the number of product terms available on
each output.
Several multiplexers are often used simultaneously to
route multiple address and data bits, under the control of
the same select lines. In such cases, multiple devices
can be cascaded when the number of inputs and outputs exceeds device limits. Cascading is also possible
for large multiplexers that do not fit in a single device. In
such cases, the select bits should also be judiciously selected for each PLD, to minimize the number of
product terms.
Outputs
EQl lES
8
A
GTR
A>B
A2
A1
82
81
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
0
1
A=B AB). Based on this truth table,
the equations for the three output signals EOL, LES and
GTR can be easily derived. These equations can then
be optimized by using Boolean algebra, Kamaugh
maps, or the minimization routine available with the
software.
Another common trick for designing a multiplexer is to
connect a number of outputs together and control the
output enables using the select bits to multiplex data.
Timing considerations for such designs include the output enable and disable times, which should be carefully
selected to avoid output contentions.
Combinatorial Logic Design
5·31
~AMD
+ (An: +: IBn)
An-2 * IBn-2
The final Boolean equations are:
EQL
LES
* IB2 * IBI
IA2* IAI
+ IA2
*
Al* IB2
* Bl
* B2
*
+ A2* IAI
Al
* B2
*
+ A2
*
IA2
* IAI
*
+ IA2
* IAI
*
+ IA2
* IAI
*
+ IA2
*
A
*
+/A2
Al
*
*
+ A2 */AI
* B2
=
= IAI
+ IA2
+ IA2
GTR
*
*
*
=
IA2
+
+
+
+
+
A2
A2
A2
A2
A2
*
*
*
*
*
*
IAI
+ IA2
+ IA2
*
*
*
=
IB2
IAI
IB2
B2
B2
B2
B2
*
*
*
Bl
Bl
*
*
*
*
*
IB2
IB2
IB2
IB2
IB2
*
B2
*
*
*
*
*
Bl
Bl
+
+
+
Bl
+ (An :+: IBn)
IBI
(A2 :+: /B2)
IBI
Bl
IBI
Bl
B2
Al
IAI
Al
IAI
Al
Al
IB2
Al
*
*
*
*
*
*
IBI
IBI
IBI
Bl
Bl
IBI
* IBI
* IBI
IB2
Comparator Device Selection
Considerations
The number of product terms needed is directly related
to the number of bits compared. For LES (less than) and
GTR (greater than) functions, the number of product
terms required depends upon the number of bits in the
two operands compared, as well as their value. The LES
and GTR equations can be written as follows:
LES
GTR
B2
* IA2
+ (B2 :+: IA2)
* Bl*/Al
A2
* IB2
+ (A2 :+: /B2)
*
LES
Bn
*
*Bn-l * IAn-l
* (Bn -1 : + : IAn -1 )
*Bn-2 * IAn-2
+
+
+
GTR
5-32
The values of the comparands themselves affect the
number of product terms used. When the comparison is
made with comparands which are power-of-two numbers, the number of product terms required can be
reduced drastically. This essentially relies on the fact
that when the lower bits of a comparand are all zeros
only the highest bit needs to be compared, requiring
only one product term. For example, in a two-bit comparator, if A1 is zero and A2 is one, the equation for the
greater-than function becomes very simple and requires
only one product term:
+ (Bn :+: IAn)
(B2 :+: IA2)
* (Bn -1 : + : I An -1) ...
* Bl
*
I Al
An
* IBn
+ (An: +: IBn)
*An-l
*
=
GTR
/B2
The general equation for the GTR signal can also be
simplified when comparing a number B to a fixed powerof-two comparand A with p least significant zeros.
GTR
/An
+ (Bn : +: I An)
+ (Bn :+: IAn)
*(An-l:+:/Bn-l) ...
* Al * IBI
As is obvious from these equations, comparators require exclusive-OR functions. They can be efficiently
implemented in devices that offers exclusive-OR functions but, can still be implemented in those devices that
do not.
000010000...
p
=
n
These equations can then be extended for a general
comparison of n-bit comparands as follows:
*
The total number of product terms required for an n-bit
comparison is 2n-1. Comparators required a large numberof product terms so, devices that offer many product
terms can be used very effectively.
A
Al*/Bl
* (An-I: +: IBn-I)
00
1
= IBn */Bn-l ... */Bp+l
*/Bp
This general GTR equation can also be considered as
an equation for comparing a number to a range of numbers extending from zero to number A. In fact, this trick
is used very often by many system designers for address decoder functions. In the PLD design
methodology section the ROMCS1 signal is one such
signal that is generated for the address range from
(000000) hexto (OFFFFF) hex. Forthis design n=23, the
comparand A=(OFFFFF + 1)=1 00000, and p=21. Substituting in the general equation we get the same
address decoder Boolean logic equation.
ROMCSI
=
IBn-l
Combinatorial Logic Design
IA23
* IA22* IA21
AMD~
As such designs require few product terms and no XOR
gates, they are efficiently implemented on standard
combinatorial PlDs. A general form of range comparators with two boundary comparands will be
discussed later.
The third output signal is the EQl signal. The EQl
Boolean equation tells us whether the two numbers are
identical. Such information is useful not only in address
decoders, but also in digital signal processing designs.
This equation requires a large number of product terms.
A closer examination reveals that it is essentially an exclusive-OR function.
EQL
EQL
/A2 * /B2 * (/A1 * /B1 + Al * B1)
+ A2 * B2 * (/A1 * /B1 + Al * B1)
(A1:*:B1)* (A2:*:B2);Exclusive-NOR
; function
Inverting this:
/EQL
= (A1:+:B1) + (A2:+:B2); Exclusive-OR
; function
This equation can be extended to give a general equation for equal-to comparison for two n-bit comparands.
/EQL
(An :+: Bn)
+ (An-1 :+: Bn-1)
+ (An-2 :+: Bn-2)
+ (An-3 :+: Bn-3)
let us analyze these equations further. The lES and
GTR outputs indicate whether one number is greater
than or less that another. In fact, these equations can
also be judiciously combined to get a comparison of a
range of numbers such as A>X>B. Such range comparisons are very useful for address decoder circuits.
Range Decoders
Range decoders implemented as address decoders are
one of the most commonly used applications of PlDs in
digital systems. A good example is the address decoder
illustrated earlier. Range decoders compare a number
(address) to a given range of comparands (addresses).
One way to arrive at the range decoder Boolean equations is to use the. traditional truth table approach.
Another way is to use the Boolean equations generated
earlier in the comparator section for greater-than and
less-than functions. To decode a range of three-bit numbers from B to A, we must compare another number X
such that A>X>B. The Boolean equations for the GTR
(A>X) and lES (B 1
1 -> 2
2 -> 3
3 ->4
4 -> 5
5 -> 6
6 -> 7
7 -> 8
8 -> 9
9 -> 0
0
0
0
0
0
0
0
1
1
0
02 01
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
00
1
0
1
0
1
0
1
0
1
0
AMD~
A good example of a modulo counter is a BCD counter.
Such a counter is useful in applications where the computer's outputs are generated using a decimal system.
While a four-bit binary counter can count to sixteen, the
BCD counter terminates the count at the modulus of 10.
Modulo counters can be designed in a variety of ways.
One direct way is to use the truth table to implement a
count to a modulus and directly derive the equations
from it. The truth table for a BCD count (from zero to
nine) is shown in Table 4.
A state diagram for the BCD counter is shown in Figure 8. For active-LOW outputs, the Boolean equations
can be derived directly from the truth table and optimized using Karnaugh maps or the software minimizer.
The Boolean equation for 03 is:
/Q3 :=
+
+
+
+
+
+
+
+
+
+
+
+
+
Now let us consider what happens if the device accidentally powers up in one of the count values from ten to fifteen. These are illegal counts (states) and, for a good
design, a mechanism must be built into the equations to
allow it to recover back into a legal state. What we actually need is to consider the truth table in Table 5 in conjunction with the one in Table 4 for deriving the Boolean
equations.
Table 5. Truth Table for Illegal State Recovery to
Count Zero
Present State
Next State
03
02
01
00
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
10 ->
11 ->
12 ->
13 ->
14 ->
15 ->
0
0
0
0
0
0
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/Q3
/Q3
/Q3
/Q3
/Q3
/Q3
/Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/Q2
/Q2
/Q2
/Q2
Q2
Q2
Q2
/Q2
/Q2
/Q2
Q2
Q2
Q2
Q2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/Ql
/Ql
Ql
Ql
/Ql
/Ql
Ql
/Ql
Ql
Ql
/Ql
/Ql
Ql
Ql
*
*
*
*
*
*
*
*
*
*
*
*
*
*
/QO
QO
/QO
60
/QO
QO
/QO
QO
/QO
QO
/QO
QO
/QO
QO
The equation can be reduced to the following:
/Q3 :=
/Q3
*
/Q2
+ /Q3 * /Ql
+ /Q2 * QO
+ Q3 * Ql
+ Q3 * Q2
Similar Boolean equations can be generated for 02,
012 and QO.
Figure 9 shows the circuit diagram of a loadable dual
BCD counter.
Figure 8. State Sequence of a BCD Counter Showing Illegal State Recovery
Registered Logic Design
5-47
~
AMD
CEB
LDB
----
Four-Bit
BCD
Count
'--
DO
Input
Buffers
01
02
-
00
-
04
05
06
07
01
02
03
03
Four-Bit
BCD
Count
CEA
LDA
A
101 73D-43
Clock
Figure 9. Circuit of a Dual BCD Counter
Modulo Counter Device Selection
Considerations
We have illustrated a counter that counts from zero to a
fixed modulus. The same technique can be applied for a
counter which counts down from a maximum power-oftwo numberto a fixed modulus, or even counter which
counts from one modulus to another. The important considerations will be the number of product terms used.
a
The registered PLDs used for modulo counters are similar to the ones selected for other counters. Since the
counts used are binary, devices with J-K, T-type flipflops, or XOR gates will help optimize the number of
product terms used. The product term usage also depends upon the modulus selected. Generally, a powerof two or a multiple-of-two modulus will require fewer
product terms.
Another factor for flip-flop selection is the illegal states.
D-type flip-flops are generally belter suited for illegal
state recovery than the J-K or T-type flip-flops. This is
because when no product term is asserted, the D-type
flip-flops reset to zero. Designers using J-K or T-type
flip-flops must design-in illegal state recovery.
Certain devices allow the use of a synchronous RESET
product term for modulo counters. The idea is to use the
minimal number of product terms to build a binary
counter that counts up to a power-of-two number. However, this counter is RESET to zero using the synchronous RESET product term when the desired modulus is
reached. It then begins counting afresh from zero, and
the procedure is repeated. Similar operation can also be
achieved with a synchronous PRESET product term for
a down counter.
5-48
Using synchronous RESET and PRESET product terms
allows the counter to recover from illegal states. Notice
that the logic product terms in the counter are designed
for a complete binary count. If the counter powers up in
any illegal state (as shown in Figure 10), it will continue
the count until the terminal count and then, return to
zero, where the correct modulo count will begin. This illegal state recovery will take an unpredictable numberof
clock cycles, and you may wish to design a more systematic recovery system.
Cascading Modulo Counters
For large modulo counters, the technique of generating
Boolean equations from the truth tables is very tedious
and time consuming. Another approach for designing
modulo counters is to divide it into two smaller modulo
counters. In addition to simplifying the design, this approach usually helps optimize the number of product
terms.
As an example, a modu10-360 counter can be directly
implemented with nine register bits. However, instead of
implementing this as a straight 9-bit counter, we can implement this as two counters: one four-bit counter
(counting from zero to 14) and another five-bit counter
(counting from zero to 23). Together, the two counters
count up to 360. The terminal count output, MOUT, is
asserted when the count reaches 360, as shown in
Figure 11.
The design requires nine inputs, nine outputs, one clock
pin, one LOAD pin, one RESET and one MOUT (module
output Signal) pin. Note that no extra flip-flops or pins
were ne'eded. Obviously, the count values of this
counter are not the same as a straight modu10-360
counter. Actually, this is what contributes to the optimization of the number of product terms used.
Registered Logic Design
AMD~
Synchronous
Reset Product
Term Asserted
Figure 10. A BCD Counter Using Synchronous RESET Product Term
024
(4) (3) (2) (1) (0)
015
(3) (2) (1) (0)
D
~
5,
A (8:4)
load
RST
:~:~:~
A (3:0)
Modulo 24
5 Bits
4,
,
~
elK
-
Modulo 15
4 Bits
r--~
AmPAl22V10
10173D-45
Figure 11. A Modulo-360 Counter
Registered Logic Design
5-49
~
AMD
decoding circuitry. This combinatorial circuit modifies
the counter bits and generates output signals in the
manne~ required for peripheral timing and control. Since
these circuits require extra combinatorial logic, they are
not very efficient. They are also more susceptible to hazards and output glitches.
Counters with Encoding
Until now, we have discussed counters that generate binary output sequences. Most peripherals require a predetermined sequence of control signals. Custom control
sequences can be generated by decoding the binary sequence with combinatorial logic. Figure 12 shows a general model of a counter with combinatorial output
combinatorial~
Logic
1
Control
Inputs
••
I
,-......",.
~
_
Next
State
Decoder
Clr
k
Output
Decoder
v
••
•
FlipFlops
••
•
•
•
Outputs
1
10173046
Figure 12. Counter with an Output Decoder
It is possible to have a different output coding for a fourbit counter, as shown in Table 6. This code, called Gray
code, allows only one output bit to toggle for each new
count value. This code can be easily derived from a fourbit binary counter code (also shown in Table 6) using an
output decoder.
Table 6. Generating Gray Code from a
Binary Code
Binary Code
X3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5-50
X2
0
0
O.
0
1
1
1
1
0
0
0
0
1
1
1
1
Gray Code
X1
XO
G3
G2
G1
GO
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
We can derive the Boolean equations forthe combinatorial output decoder from the truth table. The equations
are:
G3
G2
GI
X3
X3 :+: X2
X2 :+: Xl
GO
Xl :+: Xo
A more efficient and easier technique for generating
control signals is to implement the decode circuitry before the registers. This alternative is shown in Figure 13.
This essentially generates a non-standard counter with
state values that are not a binary progression. It can be
considered as a counter where the product terms for a
binary count and encoding the outputs have been
combined.
Many different codes can be generated using such tech- :
niques. We will limit ourselves to the ones that are most
commonly used: Gray-code counters and Johnson
counters.
0
0
1
1
0
Registered Logic Design
AMD~
Combinatorial
logic
ClK
.r...c;;--r---,._____r-1r--,
Control _ _ _ _
Inputs
Next
State
Decoder
I
I
I
Output
"PRE"
:
Decoder I--'."'----.....-t-l~
FlipFlops
••
•
Outputs
10173D-47
Figure 13. Counter with Combined Next State Generation and Output Encoding Circuit
Gray-Code Counters
Gray-code counters are often used in digital designs for
control timing functions. The primary advantage of
Gray-code counters stems from the characteristic that
only one output bit changes value for every clock cycle.
These output signals can be easily decoded using a
combinatorial decoder without any risk of hazards.
Gray-code counters are used extensively as system
clocks, since the different output bits provide different
clock pulses, without the risks of hazards. Gray-code is
also used in high-speed data communication applications, where data is transmitted from one part of the system to another, and where the erro~ susceptibility
increases with the number of bit changes between adjacent numbers in a sequence. These are also used for
such specialized applications as shaft encoders and
real-time process control.
Table 7. Truth Table for a Four-Bit Gray-Code
Counter
Present State
Next State
X3
X2
X1
XO
X3
X2
X1
XO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
The implementation of a Gray-code counter is very simple. A truth table can be derived from the transition table
as is done for a binary counter. The Boolean equations
can then be directly derived from the truth table. The
truth table for the Gray-code counter is shown in
Table 7.
Registered Logic Design
5-51
~AMD
The Boolean logic equations for a Gray-code counter
are:
X3
+
+
+
+
+
+
+
/X3
X3
X3
x3
X3
x3
X3
x3
/X3
/x3
/X3
/X3
/X3
X3
X3
x3
+
+
+
+
+
+
+
/X3
/X3
/X3
/X3
X3
X3
X3
X3
'=
+
+
+
+
+
+
+
X2
Xl
,=
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X2
X2
X2
X2
X2
/X2
/X2
/X2
/X2
X2
X2
X2
X2
X2
X2
X2
* /XI
* /XI
* /XI
* Xl
* Xl
/X2
/X2
/X2
X2
X2
X2
x2
/X2
/XI
Xl
Xl
Xl
/XI
Xl
Xl
Xl
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
XO
/X3 * /X2 *
+ /X3 * /X2 *
+ /X3 * X2 *
+ /X3 * X2 *
+ x3 * X2 *
+ X3 * x2 *
+ X3 * /X2 *
+ X3 * /X2 *
Johnson Counters
Xl
Xl
/XI
Xl
Xl
Xl
/XI
/XI
/XI
/XI
Xl
/XI
/XI
Xl
Xl
/XI
/XI
Xl
Xl
* /XO
* /XO
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
XO
XO
/XO
/xO
XO
XO
/XO
/XO
XO
XO
/XO
/xO
XO
XO
XO
XO
/XO
/XO
XO
XO
/XO
/XO
/XO
* XO
* /XO
* XO
* /XO
* XO
* /XO
* xo
A Johnson counter is part of a family of counters known
as "ring counters." These counters are used for special
applications where code symmetry is desired. Ring
counters are also often used for timing purposes, since
all the outputs are essentially a 'series of pulses. This
code symmetry also allows use of the fewest possible
product terms with a D-type register. Devices that provide a small amount of logic per cell, can implement
Johnson counters very easily.
Johnson counters are also known as circular-shift
counters. The sequence for a five-stage Johnson
counter is shown in Table 8. As can be seen in the truth
table, the counter first fills up with 1's from left to right
and then it fills up with zeros again. Note from the output
sequence that only one of the Johnson counter bits
changes for every clock period, like the Gray-code
counter. One major advantage of the Johnson counter is
that it can be readily decoded with small two-input
NAND gates and hence is suitable for high-speed
applications.
5-52
Note that the five-stage sequence has a table of 10 legal
states and 22 illegal states (Table 9).ln general, an n-bit
Johnson counter will produce a modulus of 2n. Figure 14 shows the state diagram of the five-bit counter.
Table 8. Five-Bit Johnson Counter Truth Table
Legal States
Next State
Present State
04 03
02
01
00
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
04 03
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
02
01
00
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
The implementation of a Johnson counter is relatively
straight-forward, and is the same regardless of the number of stages. When D-type flip-flops are used, the Q
output of each flip-flop is connected to the D input of the
following stage. The single exception is the Q output of
the last stage, which is complemented and connected to
the D input of the first stage.
Table 9, Illegal States for a Five-Bit
Johnson Counter
Illegal States
Next State
Present State
04 03
02
01
00
0
0
0
0
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
Registered Logic Design
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
1
04 03
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AMD~
Shift Registers
A Shift Register is a special digital circuit often used as a
primary building block in digital computer systems. It is
closely related to a ring counter. Its fundamental usage
is for temporary data storage and bit-wise data manipulation for advanced arithmetic and multiplication operations. Shift registers are also frequently used in
communications, for converting parallel byte-wide data
from the microprocessor to a serial data bit-stream for
transmission. Shift registers are also used in graphics
systems for serializing parallel data for use by the display mqnitor. A number of examples of video shift registers are included in the graphics section.
The fundamental purpose of a shift register (Figure 16)
is to shift data from one flip-flop to another. There are
several types of shift registers. They are classified by
the way in which incoming data is received (parallel or
serial), and how outgoing data is transmitted (parallel or
serial).
Figure 14. State Diagram of a Five-Bit Johnson
Counter
One disadvantage of the counter is the number of invalid
(or illegal) states. The invalid states increase exponentially with the length of the counter. The bigger the
counter becomes, the greater are its chances of entering an illegal state. Johnson counters are very susceptible to illegal states, and can "hang up" very easily. Noise
or improper use can cause this counter to end up in an
illegal state. Therefore, a design with illegal state recovery circuitry is always recommended.
Figure 15 shows a nine-bit Johnson counter that can be
derived by directly extending the design of a five-bit
Johnson counter.
In the following example, we will discuss a simple universal shifter that provides both serial and parallel input
and output functions. Depending upon the control signals 10 and 11, the data is shifted from one flip-flop to another in the left or the right direction. These inputs also
control when the new parallel data is loaded onto the
registers. When shifting left or right, serial data can be
received and transmitted on serial pins LlRO and RILO.
Since the flip-flop outputs appear on the output pins at
all times, the parallel output data is always available.
The truth table is shown in Table 10.
The Boolean logic equations can be directly derived
from the truth table, and are shown Figure 17.
Shift registers can be modified to suit various system design requirements. This universal shift register can be
used for serial in/serial out, parallel in/parallel out, serial
in/parallel out and parallel in/serial out functions.
CLK---.------~------~------~------*-------.-----~~----~~----~
10173D-49
Figure 15. Block Diagram of a Nine-Bit Johnson Counter
Registered Logic Design
5-53
~AMD
Clock
Parallel Data In
Control
Signals
Left Signal Data
In and Out (L1RO)
Right Serial Data
Out and In (RILO)
Shift Register
00 01 02 03 04 05 06 07
10173D-50
Parallel Data Out
Figure 16. A Shift Register Block Diagram
Table 10. The Truth Table for a Universal Shift Register
07
06
05
04
03
02
01
00
11
10
07
RILO
06
D7
06
07
05
D6
05
06
04
D5
04
05
03
D4
03
04
02
D3
02
03
01
D2
01
02
00
D1
00
01
L1RO
DO
0
0
1
0
1
5-54
Registered Logic Design
a
1
1
;Retain Data
;Shift Right
;Shift Left
;Load Data
AMD~
Equations
/QO
.=
+
:+:
+
/Ql
.=
+
:+:
+
/Q2
.=
+
:+:
+
/Q3
.=
+
:+:
+
/Q4
.=
+
:+:
+
/Q5
.=
+
:+:
+
/Q6
.=
+
:+:
+
/Q7
.=
+
:+:
+
/Il*/IO*/QO
/Il*IO*Q1
Il*/IO*/LIRO
Il*IO*/DO
HOLD QO
SHIFT RIGHT
SHIFT LEFT
LOAD DO
/Il*/IO*/Ql
/Il *10* /Q2
I1*/IO*/QO
Il*IO*/Dl
;HOLD Q1
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D1
/Il * /10* /Q2
/11 *10* /Q3
11*/IO*/Q1
11 *10* /D2
;HOLD Q2
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D2
/Il*/IO*/Q3
/11 *10* /Q4
11* /10* /Q2
I1*IO*/D3
;HOLD Q3
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D3
/I1*/IO*/Q4
/11*IO*/Q5
Il* /10* /Q3
11*IO*/D4
;HOLD Q4
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D4
/11 * /10* /Q5
/11* IO*/Q6
11*/IO*/Q4
11* IO*/D5
;HOLD Q5
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D5
/11*/IO*/Q6
/11 *10* /Q7
11 * /10* /Q5
I1*IO*/D6
;HOLD Q6
;SHIFT RIGHT
;SHIFT LEFT
;LOAD D6
/11*/IO*/Q7
/11 *10 * /RILO
Il*/IO*/Q6
I1*IO*/D7
;HOLD Q7
;SHIFT RIGHT
;SHIFT LEFT
; LOAD D7
/LIRO = /QO
LIRO.TRST = /11*10
;LEFT IN RIGHT OUT
/RILO = /Q7
RILO.TRST = Il*/IO
;RIGHT IN LEFT OUT
Figure 17. Boolean Logic Equations for an Octal Shift Register
Registered Logic Design
5-55
~AMD
Barrel Shifters
In most data processing systems, some form of data
shifting or rotation is necessary. In typical computer systems, the shifter is located at the output of the ALU, and
usually requires a single-cycle shift and add function
(Figure 18). For such applications as floating-point arithmetic or string manipulation, ordinary shift registers are
inefficient, since they require n clock cycles for an
n-bitshift.
and the Boolean equations are then written based upon
the truth tables. An eight-bit barrel shifter requires at
least eight data inputs, eight registered data outputs.
three control lines to specify the shift distance, a clock
input and an output enable that controls the three-state
buffer on the register output.
Figure 19 shows the block diagram for an eight-bit registered barrel shifter, while Table 11 shows the truth table.
The registered barrel shifter requires a total of 14 inputs
and 8 outputs.
Input Oata Bus
07 06 05 04 03 02 01 00
Register
RST
SO
S1
S2
ClK
File
OE
07 06 05 04 03 02 01 00
10173D-52
Figure 19. Block Diagram of an Eight-Bit Barrel
Shifter
Shift
Oistance--......
Table 11. Truth Table for an Eight-Bit Barrel
Shifter
S2
0
0
0
0
1
1
1
1
ClK---~
OE----"'-A
Output Oata Bus
SO
0
1
0
1
0
1
0
1
07
07
06
05
04
03
02
01
00
06
06
05
04
03
02
01
00
07
05
05
04
03
02
01
00
07
06
04 03
04 03
03 02
02 01
01 00
00 07
07 06
06 05
05 04
02
02
01
00
07
06
05
04
03
01
01
00
07
06
05
04
03
02
CO
00
07
06
05
04
03
02
01
Gray-Code, Johnson Counter and Shift
Register Device Selection Considerations
10173D-51
Figure 18. Typical ALU Architecture
A specialized shift register, called a "barrel shifter," is
used to shift (or rotate) data by any number of bits in a
single clock cycle. The name "barrel shifter" is used because of the circular nature of the shift operation. The
storage registers on the output of the shifter are used in
this architecture to pipeline the data operation, increasing throughput. The three-state buffer on the output registers is also useful for providing an interface to the
data bus.
The design of a barrel shifter proceeds in the same manner as a regular shift register. The truth table is drawn,
5-56
S1
0
0
1
1
0
0
1
1
Gray-code counters, Johnson counters and shift registers are not very logic-intensive; the number of product
terms required is minimal. The D-type flip-flops provide
the most efficient implementations, allowing these designs to be easily implemented in most PAL devices.
Since Gray-code counters are often used as system
clocks, very high speed PAL devices provide the highest
resolution clocks.
Barrel shifters are very logic-intensive and require many
product terms, since data from all the inputs needs to be
accessible at any output. Registered PLDs with a large
number of product terms are ideal for barrel shifters.
Large barrel shifters can also be partitioned into a number of PLDs.
Registered Logic Design
AMD~
Asynchronous Registered Designs
Until now, we have discussed strictly synchronous registered designs, where a common system clock is used.
In asynchronous registered designs, a common clock is
not used. The register clock may be generated by the
output of another register, or by a logical combination of
various other signals. Such designs are usually slow for
such applications as timing generation, because when
the output of one register is used to clock another, multiple delays are encountered before all the register outputs stabilize. On the other hand, designs can be very
fast for asynchronous applications such as bus arbitration and control, where a fast response to a bus signal
can be provided without waiting for a common systemclock.
Combinatorial hazard conditions can cause false clocking of registers, destroying the logic intended by the designer. The designer also needs to worry about race
conditions when clocking a number of register simultaneously. Careful design analysis is strongly recommended before implementing any asynchronous
design.
Ripple counters are probably the easiest examples of
such asynchronous designs. Figure 31 shows the logic
diagram of a five-bit binary ripple counter. These counters clearly have the advantage of design simplicity. The
output from one stage is fed as the clock to the next
stage. However, this results in a slower counting rate,
since the clock signals need to propagate through all
five registers before the next count is reached.
Although asynchronous designs are easierto visualize,
they present larger problems in implementation.
CK
RESET
r-------- -1
I
I
I
I
I
I
I
I
I
T
III
T
III
hiV
RO
S
Q
a
r--
ROY S
Q
a
LJ
LJ
r-
T
I
III
RO v
RD Y S
S
a
Q
Q
a
11
RD
S
Q
a
LJ
LJ
LJ
SET
r-
L___ -<= }:==-=-~_~ ___ ~ __~_____ J 02
I
I
Extra Circuit Required
For Modulo 20 Counter
01
00
10173D-53
Figure 20. A Five-Bit Ripple Counter
Figure 20 shows the implementation of a modul0-20
counter that is RESET when output bits 04 and 02 are
both HIGH. Since the RESET is implemented with a
product term, the extra AND gate shown can be implemented directly within the PAL device.
Asynchronous Designs Device Selection
Considerations
The device selection for asynchronous designs is easy.
As the clock signals require logic, only PLDs that allow
implementations of Boolean logic on the clock signals
are useful.
Registered Logic Design
5-57
~
AMD
OTHER APPLICATIONS OF REGISTERED
PLDs
Registered PLDs are used for a number of miscellaneous applications that are not covered by the synchronous and asynchronous design applications discussed
up to now. One such application is as a frequency
divider.
•
Frequency dividers
•
Addressable Registers
Frequency Dividers
Standard synchronous counters provide the basic capability of dividing an input frequency. A single register of a
PAL device will let us divide by two.
If we stack these registers, a binary counter provides
symmetrical division by 2, 4, 8, 16, etc. This divider has
been a standard for years, and the PAL device has always been on excellent choice for such applications.
One unique application of PAL devices is for dividing inputfrequencies by odd numbers. This has been done
historically by designing a counter that cycles an odd
number modulo, and decoding the specific states of the
counter. The disadvantage of this approach is that the
output is not symmetrical and the duty cycle is not 50%.
Let us examine a simple divide-by-five counter. This
counter can be implemented using three flip-flops that
start at zero and reset at four, resulting in a five-state
counter. Table 12 shows the outputs of the three individual flip-flops.
Table 12. Truth Table for a Five-Bit Counter
Present State
Next State
02
Q1'
00
0
0
0
0
0
0
1
1
0
0
1
02 01
00
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
State zero to one.
State one to two.
State two to three.
State three to four.
State four to zero.
TheBoo~anequ~~nsare:
Q2
Ql
QO
5-58
:= /Q2
:= /Ql
:= /Q2
* Ql
* QO
* /QO
* QO
+ Ql
iMSB bit
* /QO
iLSB bit
The waveforms for this divider are shown in Figure 21.
Notice that the 02 output goes HIGH for one state and
that this output is one fifth of the input frequency, but it is
a 20% duty cycle. 01 is active for two states; it provides
the same frequency, but with a 40% duty cycle. If we
want a 50% duty cycle, we are going to have to divide a
state in half.
To provide the 50% duty cycle, the two edges should be
evenly spaced in the count sequence, one edge in the
middle of state two and one at the beginning of state
zero. The first edge can be formed by logically "ANDing"
state_2 with the falling edge of the clock. The second
edge can be formed by decoding state zero.
edge_l =/ clock * /Q2 * Ql * /QO
iedge between
istates two and
ithree
edge_2= /Q2 */Ql */Ql iedge at state
izera
The logical "OR" of these two equations will provide the
needed rising edges. To provide a clean output, this signal should clock another output register.
The next step in the design is to pick the appropriate
PAL device to fit this design. Our biggest concern is that
we need the capability of clocking the counter at one
speed and the output flip-flop at another. To do this, we
cannot use a PAL device that has a dedicated clock pin;
we need an architecture that allows programmable
clocks.
The clock signal requires two product terms (one for
each edge). Another technique is to use the independent asynchronous SET and asynchronous RESET product terms of the output register. A HIGH on the SET
product term asserts the register output, and a HIGH on
the RESET product term unasserts the register output.
Due to the asynchronous nature of the product terms
some adjustment in timing is required. The SET product
term is asserted when instate 0 (02=0, 01 =0 and
00=0), and the RESET product term is asserted when
between states two and three.
OUTPUT.SET = /clock * /Q2 * Ql * /QO
iset between
istates 2 & 3
OUTPUT.RESET = /Q2 */Ql * /QO
ireset at
istate zero
Registered Logic Design
AMD~
I_ State 0 _I
.
1 State 3 1 State 4 1 State 0 1 State 1 1
,. State 1 -1,. State 2 -,.
-,. -- -
00
01
02
Output
Set
Reset
101730-54
Figure 21. Waveform for a Frequency Divider
Addressable Registers
Addressable registers are commonly-used MSI functions, often implemented in PAL devices. Addressable
registers are used as building blocks for digital computers. Depending upon the address input one of the many
flip-flops in the register retain their previous values.
Registered Logic Design
5·59
State Machine Design
INTRODUCTION
What Is a State Machine?
State machine designs are widely used for sequential
control logic, which forms the core of many digital systems. State machines are required in a variety of applications covering a broad range of performance and
complexity; low-level controls of microprocessor-toVLSI-peripheral interfaces, bus arbitration and timing
generation in conventional microprocessors, custom
bit-slice microprocessors, data encryption and decryption, and transmission protocols are but a few examples.
A state machine is a digital device that traverses through
a predetermined sequence of states in an orderly fashion. A state is a set of values measured at different parts
of the circuit. A simple state machine can consist of PALdevice based combinatorial logic, output registers, and
buried (state) registers. The state in such a sequencer is
determined by the values stored in the buried and/or
output registers.
Typically, the details of control logic are the last to be
settled in the design cycle, since they are continuously
affected by changing system requirements and feature
enhancements. Programmable logic is a forgiving solution for control logic design because it allows easy modifications to be made without disturbing PC board layout.
Its flexibility provides an escape valve that permits design changes without impacting time-to-market.
A majority of registered PAL device applications are sequential control designs where state machine deSign
techniques are employed. As technology advances,
new high-speed and high-functionality devices are being introduced which simplify the task of state machine
deSign. A broad range of different functionality-and-performance solutions are available for state machine design. In this discussion we will examine the functions
performed by state machines, their implementation on
various devices, and their selection.
A general form of a state machine can be depicted as a
device shown in Figure 1. In addition to the device inputs
and outputs, a state machine consists of two essential
elements: combinatorial logic and memory (registers).
This is similar to the registered counter designs discussed previously, which are essentially simple state
machines. The memory is used to store the state of the
machine. The combinatorial logic can be viewed as two
distinct functional blocks: the next state decoder and the
output decoder (Figure 2). The next state decoder determines the next state of the state machine while the output decoder generates the actual outputs. Although they
perform two distinct functions, these are usually combined into one combinatorial logic array as in Figure 1.
Combinatorial Logic ,
Next
State
Decode
Device
Inputs
S~
r
Output,
Decode
r---r----••
•
r-----
Outputs
Memory
-
••
•
1
101730-55
Figure 1. Block Diagram of a Simple State Machine
5-60
State Machine Design
AMDll
Combinatorial Logic
Combinatorial Logic
Inputs
-..
r
Next State
Decoder
(Transition
Function)
~
••
•
Memory
(Registers)
~
•••
Output
Decoder
(Output
Decode
Function)
••
•
-
Outputs
1
10173D 56
Figure 2. State Machine, with Separate Output and Next State Decoders
The basic operation of a state machine is twofold:
State Machine Applications
1. It traverses through a sequence of states, where
the next state is determined by next state decoder,
depending upon the present state and input conditions.
State machines are used in a number of system control
applications. A sampling of a few of the applications,
and how state machines are applied, is described
below.
2. It provides sequences of output signals based
upon state transitions. The outputs are generated
by the output decoder based upon present state
and input conditions.
As sequencers for digital signal processing (DSP) applications, state machines offer speed and sufficient
functionality without the overkill of complex microprocessors. For simple algorithms, such as those involved
in performing a Fast Fourier Transform (FFT), a state
machine can control the set of vectors that are multiplied
and added in the process. Forcomplex DSP operations,
a programmable DSP may be better. On the other hand,
the programmable DSP solution is not likely to be as fast
as the dedicated hardware approach.
Using input signals for deciding the next state is also
known as branching. In addition to branching, complex
sequencers provide the capability of repeating sequences (looping) and subroutines. The transitions from
one state to another are called control sequencing and
the logic required for deciding the next states is called
the transition function (Figure 2).
The use of input signals in the decision-making process
for output generation determines the type of a state machine. There are two widely known types of state machines: Mealy and Moore (Figure 3). Moore state
machine outputs are a function of the present state only.
In the more general Mealy-type state machines, the outputs are functions of both the state and the input signals.
The logic required is known as the output function. For
either type, the control sequencing depends upon both
states and input signals.
Most practical state machines are synchronous sequential circuits that rely on clock signals to trigger the state
transitions. A single clock is connected to all of the state
and output edge-triggered flip-flops, which allows a
state change to occur on the riSing edge of the clock.
Asynchronous state machines are also possible, which
utilize the propagation delay in combinatorial logic for
the memory function of the state machine. Such machines are highly susceptible to hazards, hard to design
and are seldom used. In our discussion we will focus
solely on sequential state machines.
Consider the case of a video controller. It generates addresses for scanning purposes, using counters with
various sequences and lengths. Instead of implementing these as actual counters, the sequences involved
can be "unlocked" and implemented, instead, as state
machine transitions. There is an advantage beyond
mere economy of parts. A count can be set or initiated,
then left to take care of itself, freeing the microprocessor
for other operations.
In peripheral control the simple state machine approach
can be very efficient. Consider the case of run-Iengthlimited (RLL) code. Both encoding and decoding can be
translated into state machines, which examine the serial
data stream as it is read, and generate the output data.
Industrial control and robotics offer further areas where
simple control functions are requ ired. Such tasks as mechanical positioning of a robot arm, simple decision
making, and calculation of a trigonometric function, usually does not require the high-power solution of microprocessors with stacks and pointers. Rather, what is
required is a device that is capable of storing a limited
number of states and allows simple branching upon
conditions.
State Machine Design
5-61
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Outputs
Inputs
St~
Next State
Decoder
r
--••
•
Output
Decode
Registers
~
•••
1
••
•
Output s are Functions
of Stat e and Inputs
a. Mealy State Machines
Outputs
Inputs
,.......
r
Next State
Decoder
---
Output
Decode
~
••
•
Registers
~
•••
1
b. Moore State Machines
••
•
Output s are Functions
of Stat eOnly
10173D-57
Figure 3. The Two Standard State Machine Models
Data encryption and decryption present similar problems to those encountered in encoding and decoding for
mass media, only here it is desirable to make the
scheme not so obvious. A programmable state machine
device with a security Bit is ideal for this because memory is internally programmed and cannot be accessed
by someone tampering with the system.
Functions Performed
All the system design functions performed by controllers
can be categorized as one of the following state machine functions:
•
Arbitration
I!I
Event monitoring
•
Multiple condition testing
•
Timing delays
•
Control signal generation
State Machine Theory
Let us take a brief look at the underlying theory for all sequentiallogic systems, the finite state machine (FSM),
or simply state machine.
Those parts of digital systems whose outputs depend on
their past inputs as well as their current ones can be
modeled as finite state machines. The "history" of the
machine is summed up in the value of its internal state.
When a new input is presented to the FSM, an output is
generated which depends on this input and the present
state of the FSM, and the machine is caused to move
into new state, referred to as the next state. This new
state also depends on both the input and present state.
The structure of an FSM is shown pictorially in Figure 2.
The internal state is stored in a block labeled "memory."
As discussed earlier, two combinatorial functions are required: the transition function, which generates the
value of the next state, and the output function, which
generates the state machine output.
Later we will take a design example and illustrate how
these functions can be used when designing a state
machine.
5-62
State Machine Design
AMD~
State Diagram Representation
The behavior of an FSM may be specified in graphical
form as shown in Figure 4. This is called a state diagram,
or state transition diagram. Each bubble represents a
state, and each arrow represents a transition between
states. Inputs that cause the transitions are shown next
to each transition arrow.
a. Moore Machine
b. Mealy Machine
101730-60
Figure 6. Output Generation
For this notation, there is a specification uncertainty as
to which signals are outputs orinputs, as they both occur
on the drawing next to the arrow in which they are active.
This is usually resolved by separating the input and output Signals names with a line (Figures 4 and 6). Sometimes an auxiliary pin list detailing the logic polarity and
input or output designations is also used.
101730-58
Figure 4. State Machine Representation
Control sequencing is represented in the state transition
diagram as shown in Figure 5. Direct control sequencing
requires an unconditional transition from state A to state
B. Similarly conditional control sequencing shows a
conditional transition from state C to either state D or
state E, depending upon input signal 11.
a. Direct Control
Sequencing
State transition diagrams can be made more compact
by writing on the transitions not the input values that
cause the transition, as in Figure 4, but a Boolean expression defining the input combination or combinations
that cause this transition. For example, in Figure 7,
some transitions have been shown for a machine with
inputs START, X1. and X2. In the transition between
states 1 and 2, the inputs X1 and X2 are ignored (that is,
they are "don't cares") and thus do not appear on the
diagram. This saves space and makes the function
more obvious.
b. Conditional Control
Sequencing
101730-61
101730-59
Figure 5. Control Sequencing
Figure 7. State Transition Diagram with
Mnemonics
For Moore machines the output generation is represented by assigning outputs with states (bubbles) as
shown in Figure 6. Similarly, for Mealy machines conditional output generation is represented by assigning
outputs to transitions (arrows). as was shown in
Figure 4. More detail on Mealy and Moore output generation is given later.
There can be a problem with this method if one is careless. The state transitions in figu re 8 show what can happen. There are three input combinations, (10, 11, 12, 13) =
{1 011}. {11 01} and {1111}, which make both (110 * 112 +
13) and (10 * 11 + 10 * 12) true. Since a transition to two
next states is impossible, this is an error in the
State Machine Design
5-63
~AMD
specification. It must either be guaranteed that these input combinations never occur, or the transition conditions must be modified. In this example, changing (10· 11
+ 10· 12) to (10 • 11 + 10· 12) • 113 would solve the problem.
10173D-62
Figure 8. State Diagram with Conflicting Branch
Conditions
State Transition Table Representation
A second method for state machine representation is
the tabular form known as the state transition table,
which has the format shown in Table 1. Listed along the'
top are all the possible input bit combinations and internal states. Each row gives the next state and the next
output; thus, the table specifies the transition and output
functions. However, this type of table is not suitable for
specifying practical machines in which there is a large
number of inputs, since each input combination defines
a row of the table. For example, with 10 inputs, 1024
rows would be required!
Table 1. A State Transition Table
Present
State
SO-Sn
Inputs
10-lm
Next State
SO-Sn
Outputs
Generated
OO-Op
Flowcharts
Another popular notation is based on flowcharts. In this
notation, states are represented by rectangular boxes,
and alternative state transitions are determined by
strings of diamond-shaped boxes. The elements may
have multiple entry points, but in general have only one
exit. The state name is written as the first entry in the
rectangular state box. Any Moore outputs present are
written next in the state box, with a caret (A) following
those that are unregistered. The state code assignment,
if it is known, is written next to the upper right corner of
the state box. Decision boxes are diamond or hexagonal
shaped boxes containing either an input Signal or a logic
expression. Two exits labeled "0" and "1" lead to either
another decision box, a state box, or a Mealy output.
5-64
The rounded oval is used for Mealy machine outputs.
Again, a caret follows those outputs that are unregistered. All the boxes may need to be expanded to accommodate a number of output signals or a larger
expression.
The use of these symbols is shown in Figure 9. Each
path, through the decision boxes from one state to another defines a particular combination or set of combinations of the input variables. A path does not have to
include all input variables; thus, it accommodates "don't
cares." These decision trees take more space than the
expressions WOUld, but in many practical cases, state
machine controllers only test a small subset of the input
variables in each state and the trees are quite manageable. Also, the chain of decisions often mirrors the designer's way of thinking about the actions of the
controller. It is important to note that these tests are not
performed sequentially in the FSM; all are performed in
parallel by the FSM's state transition logic.
A benefit of this method of specifying transitions is that
the problem of Figure 8 can be avoided. Such a conflict
would be impossible as one path cannot diverge to'define paths to two states.
This flowchart notation can be compacted by allowing
more complex decisions, when there is no danger of
conflicts due to multiple next states being defined, Expressions can be tested, as shown in Figure 1Oa, or multiple branches can extend from a decoding box, as in
Figure 1Ob. In the second case, it is convenient to group
the set of binary inputs into a vector, and branch on different values of this vector.
The three methods of state machine representation
state diagrams, state tables, and flowcharts
are all equivalent and interchangeable, since they all describe the same hardware structure. Each style has its
own particular advantages. Although most popular, the
state transition diagrams are more complex for problems where state transitions depend on many inputs,
since the transition conditions are written directly on the
transition arrows. Although cumbersome, the state tables allow the designer tight control over signal logic.
Flowcharts are convenient for small problems where
there are not more than about ten states and where up to
two or three inputs or input expressions are tested in
each state. For larger problems, they can become
ungainly.
Once a state machine is defined, it must be implemented on a device. Software packages are then used
to implement the design on a device. The task is to convert the state machine description into transition and
output functions. Software packages also account for
device-specific architectural variations and limitations,
to provide a uniform user interface.
State Machine Design
AMDl1
Some software packages accept all three different state
machine representations directly as design inputs.
However, the most prevalent design methodology is to
convert the three state machine design representations
to a simple textual representation. Textual representations are accepted by most software packages although
the syntax varies.
Since the most common of all state machine representations is the state transition diagram representation, we
will use it in all subsequent discussions. Transition table
and flowchart representation implementations will be
very similar.
,....._....&._.......NN.., - (X". y".Z"', ...)
(X, y,Z .... )
State
Name
State Code
Asyn
S ync
Moore Output
10173D-63
Figure 9. Flowchart Notation
10173D-64
a. Testing Expressions
b. Multiway Branch
Figure 10. Using Flowcharts
State Machine Design
5-65
~AMD
State Machine Types: Mealy & Moore
With the state machine representation clarified, we can
no~ return to the generic sequencer model of Figure 1,
which has been labeled (Figure 11) to show the present
st~t~ (PS), next state (NS), and output (OB, OA). This
wlllillustr~te how Mealy and Moore machines are implemented with most sequencer devices that provide a single combinatorial logic array for both next state and
output decode functions. There are four ways of using
the sequencer, two of which implement Moore machines and two Mealy. First, let us look at the
Mealy forms.
The ~tandard Mealy form is shown in Figure 12, where
the signals are labeled as in Figure 11 to indicate which
registers and outputs are used. The register outputs PS
are fed back into the array and define the present state.
The combinatorial logic implements the transition function, which produces the next state flip-flop inputs NS,
and the output function, which produces the machine
output OB. This is the asynchronous Mealy form.
Combinatorial Logic
~
Device
Inputs
Next
State
Decode
Output
Decode
~
r--••
•
-
~
r
~
Memory
(Registers)
••
•
I
08
Outputs
OA
Prese nt State
PS
10173D-65
Figure 11. Generic Model of an FSM
Inputs
~
Transition
Function
Next
State
NS
Register
(State
Memory)
Output
Function
--
08
Outputs
A
Present State
PS
Clock
Figure 12. Asynchronous Mealy Form
An alternative Mealy form is shown in Figure 13. Here
the outputs are passed through an extra output register
(OA) and thus, do not respond immediately to input
changes. This is the synchronous Mealy form.
5-66
State Machine Design
10173D-66
AMD~
Output
Function
In puts
Transition
Function
Next
State
NS
r----+
Register
r-----
f---+
Register
OA
Outputs
/'
A
Present State
PS
Clock
101730-67
Figure 13. Synchronous Mealy Form
Transition
Function
In puts
.---
Next
State
NS
Output
Function
Register
(State
Memory)
~
08
Outputs
/'
Present State
PS
10173D-68
Clock
Figure 14. Asynchronous Moore Form
In puts
r----+
Transition
Function
Next
State
NS
Register
OA
Outputs
A
Pre sent State
PS
Clock
101730-69
Figure 15. Synchronous Moore Form
The standard Moore form is given in Figu re 14. Here the
outputs 08 depend only on the present state PS. This is
the asynchronous Moore form. The synchronous Moore
form is shown in Figure 15. In this case the combinatorial logic can be assumed to be the unity function. The
outputs (08) can be generated directly along with the
present state (PS). Although these forms have been described separately, a single sequencer is able to realize
a machine that combines them, provided that the required paths exist in the device.
State Machine Design
5-67
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In the synchronous Moore form, the outputs occur in thestate in which they are named in the state transition diagram. Similarly, in the asynchronous Mealy and Moore
forms the outputs occur in the state in which they are
named, although delayed a little by the propagation delay of the output decoder. This is because they are combinatorial functions of the state (and inputs in the Mealy
case).
However, the synchronous Mealy machine is different.
Here an output does not appear in the state in which it is
named, since it goes into another register first. It appears when the machine is in the next state, and is thus
delayed by one clock cycle. The state diagram in Figure 16 illustrates all the possibilities on a state transition
diagram.
•
•
•
Number of inputs/outputs
-
I/O flexibility
-
Number of output registers
Speed
Intelligence/functionality
-
Number of product terms
Type of flip-flops
Number of state registers
Number of II0s
The number of inputs, outputs and I/O pins determine
the Signals that can be sampled or generated by a state
machine.
Synchronous
Mealy Output
Available
Timing and Speed
The timing considerations for sequencer design are
similar to those for registered logic design. A system
clock cycle forms the basic kernel for evaluating control
function behavior. Forthe most part, all input and output
functions are specified in relationship to the positive
edge. Registered outputs are available after a period of
time teo, the clock-to-output propagation delay. Asynchronous outputs require an additional propagation delay (tPD) before they are valid.
Asynchronous
Moore Output
Available
101730-70
Figure 16. State Diagram Labelling for Different
Output Types
As a matter of notation, Moore outputs are often placed
within the state bubble and Mealy outputs are placed
next to the path or arrow that activates them.
The relationship of Mealy and Moore, synchronous and
asynchronous outputs to the states is shown in
Figure 17.
5-68
Device Selection Considerations
There are three major criteria for selecting the correct
state machine device for a design:
For the circuit to operate reliably, all the flip-flop inputs
must be stable at the flip-flop by the minimum set-up
time (ts) of the flip-flops before the next active clock
edge. If one of the inputs changes after this threshold,
then the next state or synchronous output could be
stored incorrectly; the circuit may even malfunction. To
avoid this, the clock period (tp) must be greater than the
sum of the set-up time of the flip-flops and the clock to
output time (ts + teo). This determines the minimum
clock period and hence the maximum clock frequency,
fMAX, of the circuit. Metastability and erroneous system
operation may occur if these specifications are violated.
The timing relationships are shown in Figure 18. In each
cycle there are two regions: the stable region, when all
signals are steady, and the transition region, when the
machine is changing state and Signals are unstable. The
active clock edge causes the flip-flops to load the value
of the new state that has been set up at their inputs.
State Machine DeSign
-t
AMD~
Clock
State
Input
Registered
Moore Input
Registered
Mealy Output
Asynchronous
Moore Output
Asynchronous
Mealy Output
On+2
__~____-J)(~_________
OT!n__________
State n
J)(~____~r-o__
n_+_1________
~)(~
__T-0
__
n_+_2____
State n + 2
State n + 1
101730-71
Figure 17. State Machine Timing Diagram
Clock
~------tp ------~~----
Input
Registered
Output
Asynchronous
Output
State
X
n
~D~
X
X
n+ 1
X
n+2
)C
X
n+3
101730-72
Figure 18. Timing Diagram for Maximum Operating Frequency
State Machine Design
5-69
~AMD
At a time after this, the present state and output flip-flop
outputs will start to change to their new values. After a
time has elapsed, the slowest flip-flop output will be stable at its new value. Ignoring input changes for the moment, the changes in the state register cause the
combinatorial logic to start generating new values for
the asynchronous outputs and the inputs to the flipflops. If the propagation delay of the logic is tpo, then the
stable period will start at a time equal to the sum of the
maximum values of teo, and tpo.
Asynchronous Inputs
The timing of the inputs to an asynchronous state machine is often beyond the control of the designer and
may be random, such as sensor or keyboard inputs, or
they may come from another synchronous system that
has an unrelated clock. In either case no assumptions
can be made about the times when inputs can or cannot
00
Clock
arrive. This fact causes reliability problems that cannot
be completely eliminated, but only reduced to acceptable levels.
Figure 19 shows two possible transitions from state "51"
(code 00) either back to itself, orto state "52" (code 11).
Which transition is taken depends on input variable "A"
which is asynchronous to the clock. The transition function logic for both state bits B1 and B2 include this input.
The input A can appear in any part of the clock cycle. For
the flip-flops to function correctly, the logic for B1 and B2
must stabilize correctly before the clock. The input
should be stable in a window ts (setup time) before the
clock and tH (hold time) after the clock. If the input
changes within this window, both the flip-flops may not
switch, causing the sequence to jump to states 01 or 10
which are both undefined transitions. This type of erro~
neous behavior is called an input race.
_/
Input
11
81
82
101730-73
Figure 19. Asynchronous Input Cascading Race
5-70
State Machine Design
AMD~
A solution to this problem is to change the state assignment so that only one state variable depends on the
asynchronous input. Thus, the 11 code must be
changed to 01 or 10. Now, with only one unsynchronized flip-flop input, either the input occurs in
time to cause the transition, or it does not, in which case
no transition occurs. In the case of a late input, the machine will respond to it one cycle later, provided that the
input is of sufficient duration.
There is still the possibility of an input change violating
the setup time of the internal flip-flop, driving it into a metastable state. This can produce system failures that can
be minimized, but never eliminated. The same problem
arises when outputs depend on an asynchronous input.
Very little can be done to handle asynchronous inputs
without severely constraining the design of the state machine. The only way to have complete freedom in the
use of inputs is to convert them into synchronous inputs.
This can be done by allocating a flip-flop to each input as
shown in Figure 20. These synchronizing flip-flops are
clocked by the sequencer clock, and may even be the
sequencer's own internal flip-flops. This method is not
foolproof, but significantly reduces the chance of metastability occurring.
Functionality
The functionality of different devices is difficult to compare since different device architectures are available.
The number of registers in a device det~rmines the
number of state combinations possible. However, all the
possible state combinations are not necessarily usable,
since other device constraints may be reached. The
numberof registers does give an idea of the functionality
achievable in a device. Other functionality measures include the number of product terms and type of flip-flop.
One device may be stronger than another in one of
these measures, but overall may be less useful due to
other shortcomings. Choosing the best device involves
both skill and experience.
In order to give an idea of device functionality, we will
consider each of the architecture options available to
the designer and evaluate its functionality.
Ao
-
I
Input
Register
A
f--
Combinatorial
Logic
rI'
L..--
Clock
~
---
Output
Register
So
r-.
A
State
Register ~
/'\..
1
10173D-74
Figure 20. Input Synchronizing Register
PAL Devices as Sequencers
A vast majority of state machine deSigns are implemented with PAL devices. Early versions of software required the user to manually write the sum-of-products
Boolean equations for using PAL devices. Second generation software allows one to specify the design in
"state machine syntax," and handles the translation to
sum-of-products logic automatically. PAL devices implement the output and transition functions in sum-ofproducts form through a user-programmable AND array
and a fixed OR array.
PAL devices deliver the fastest speed of any sequencer
and are ideally suited for simple control applications
characterized by few input and output signals interacting within a dedicated controller in a sequential manner.
The number of flip-flops in a typical PAL device range
from 8 to 12, which offer potentially more than one thousand state values. Since some of the flip-flops are used
for outputs, and the number of product terms is limited,
the usable numberof states is reduced drastically. Generally, up to about 35 states can be utilized.
State Machine Design
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PAL Device Flip-Flops
PAL device based sequencers implement small state
machine designs, which have a relatively large number
of output transitions. Since the output registers change
with most state transitions, they can be used simultaneously as state registers, once the state values are carefully selected. Most PAL devices are used for sm.all state
machines, and efficiently share the same register for
output and state functions. High-functionality PAL device based sequencers provide dedicated buried state
registers when sharing is difficult.
As a state machine traverses from one state to another,
every output either makes a transition (changes logic
level) or holds (stays at the same logic level). Small state
machine designs require relatively more transitions and
fewer holds. As designs get larger, state machines statistically require relatively fewer transitions and more
holds.
5-72
Most PAL devices provide D-type output registers. Dtype flip-flops use up product terms only for active transitions from logiC LOW to HIGH level, and for holds for
logic HIGH level only. J-K, S-R, andT-type flip-flops use
up product terms for both LOW-to-HIGH and HIGH-toLOW transitions, but eliminate hold terms. Thus, D-type
flip-flops are more efficient for small state. ~achine ~e
signs. Some PAL devices offer the capability of .conflguring the flip-flops as J-K, S-R or T-types, which are
more efficient for large state machine designs since they
require no hold terms.
Many examples of PAL-device-based sequencers can
be found in system time base functions, special counters, interrupt controllers, and certain types of video display hardware.
PAL devices are produced in a variety of technologies
for multiple applications, and provide a broad range of
speed-power options.
State Machine Design
~
Testability
Advanced
Micro
Devices
INTRODUCTION
With digital logic design, it is all too easy to design a circuit which
merely implements a specified function. When production starts
it is suddenly found that the circuit cannot be tested, or perhaps
that tests cannot be performed economically. Dealing with this
situation can, at the very least, have a negative impact on the
introduction of the system into the marketplace.
Potential headache can be avoided by taking test issues into
consideration during the initial design. Instead of just designing a
circuit which implements a specified function, which is the bare
minimum that must be accomplished, that function needs to be
implemented in a manner which can be tested.
The purpose of this section is to establish the notion of testability
and its importance, and then to provide ways of avoiding the most
common untestable circuits. The issues will be discussed primarily in the context of logic design in PLD's, although they are also
relevant for general logic design.
In addition, test vectors will be reviewed. Various kinds of vectors
are mentioned, and the general tools available for vector generation will be summarized.
Defining Testability -
These are, of course, the age-old issues of controllability and
observability, which are as important for digital logic circuits as
they are for so many other kinds of systems. If any portion of a
circuit is uncontrollable or unobservable, then the testability of the
entire circuit is compromised.
Figure 1 shows a couple of completely untestable circuits. The
integrity of the top input in Figure 1 a can never be verified. No
matter whether it is shorted to ground, to V ,or whether it is
functioning correctly, the output will be the sa~e. That is to say,
any faults on the top input cannot be observed at the output.
The circuit in Figure 1 a would appear pretty useless as is. It is
possible, however, that instead of being directly grounded, the
second input may be driven by some distant signal, possibly on
a different PC board, which happens to be a a logic low. If you
cannot bring this line to a logic high, then it might as well be
grounded.
The circuit in Figure 1b essentially has no input. This circuit can
be thought of as a latch, but there is no way to change its logic
state. Therefore, it is completely uncontrollable.
A Qualitative Look
A completely testable design is one in which any and all device
faults can be systematically detected.
a. Unobservable
First note that the issue is one of devices, not designs. The design
itself must work as specified; that is the main job of the design
engineer. Once the design is implemented in a device, the issue
is how to test the device to make sure that the design has been
correctly implemented. Throughout this paper, then, it will be
assumed that a particular design works as is; we will just be
addressing its testability.
The easiest and most effective means of testing a circuit is
through a systematic series of tests. A random set of tests may
also do well, but does not yield much information regarding the
testability of a circuit itself. No number of random (or systematic)
vectors can test an inherently untestable circuit.
In order to be able to perform a systematic test sequence, every
part of the circuit under test must be accessible, so that it can be
controlled. Only then can each node be forced high or low as
needed. This is essentially a requirement of complete control/ability of the circuit.
In order to be able to detect faults every part of the circuit must
also be visible to the outside world, so that the results of each test
can be observed. In this manner, each node can be inspected to
determine its logic level. This requires complete observability.
Publication# 14099 Rev. A
Issue Date: February 1992
'Amendment/O
b. Uncontrollable
14099-001A
Figure 1_ Untestable Circuits
Quantifying Testability
In theory, if we want to quantify the testability of agiven circuit, we
might first attempt to make a list of all possible things that could
go wrong with a circuit (no matter how unlikely), and then verify
that all such "faults" can be tested, in all combinations and
permutations. But for a circuit of any significance whatsoever, it
will rapidly become apparent that this is not a practical solution.
What we need instead is a measure which can give an empirically
reliable indication of the testability of a circuit, or of the quality of
a given set of tests. There are several different such measures
but the most popular of these is the single stuck-at faults model:
Testability
5-73
~AMD
There are several ways of analyzing circuits for single stuck-at
faults. For very large circuits, various testability analysis schemes
have been developed. However, for smaller circuits, especially of
the size that would be put into a PLD, the more common method
uses simulation.
Simulating Single Stuck-At Faults
A given circuit is first simulated. The quality of the simulation is
important; the more complete the simulation the better. A thorough simulation can then serve as a benchmark test sequence
later. In this way, the fault simulation procedure also allows us to
measure the quality of a given simulation, or set of tests, in
addition to the testability of the circuit.
The results of the simulation are recorded. Next, one node in the
circuit is modeled with a "stuck-at" fault - either stuck-at-one
(SA 1) or stuck-at-zero (SAO), as shown in Figure 2. The circuit is
now resimulated. H the simulation results of the modified circuit
are different from the simulation results of the good circuit, then
the fault was detected. If not, then we have a faulty circuit which
appears to operate correctly.
Needless to say, this process of analyzing the testability of a
circuit is not done all by hand; software aids are used. There are
many different kinds of programs that run on many different kinds
'Of systems, ranging from pes to workstations to mainframes.
Some of them are standalone programs; others are integrated
into larger overall environments. Their specific capabilities also
vary, but in general, they can simulate a given circuit with a given
set of vectors; analyze the test coverage that the vectors provide
for the circuit; and generate new tests, either from scratch or by
improving on the coverage of a few manually generated "seed"
vectors. Most can also point out potential problems areas of a
circuit, such as race conditions and logic hazards.
STUCK-AT-ONE (SAl)
Finally, one frequently asked question is "So what if there is a fault
that can never be detected. Who cares?" Theoretically, this
question is not unreasonable. However, most companies will not
feel comfortable telling a customer "We only tested haH of the
system, but if anything goes wrong with the otherhaH, you'll never
notice it." In addition, as will be seen, many untestable circuits
occur as a result of poor design practices.
STUCK-AT-ZERO (SAO)
Testability issues for sequential circuits have implications far
beyond the test bed. Indeed, failure to take these issues into
account can greatly affect the normal performance of a system.
The key for state machines is controllability. The challenge is to
make all elements of the circuit controllable, both for testing and
for general functionality.
14099-002A
Designing Testable Combinatorial Circuits
Figure 2. Single "Stuck-At" Faults
This procedure is repeated for each node, one node at a time
(hence the name "single" stuck-at faults). The nodes are modeled
with both SA1 and SAO faults, so that for N nodes, we will have
2N simulations. If of those 2N simulations, D of them produced
simulation results different from those of the original circuit, then
we say that this simulation tested this circuit with a test coverage
of D/(2N)*100%. Whereas this specifically tests only for single
faults, experience shows that it is also a good test for mUltiple
stuck-at faults.
Undetected Faults
Why are some of the faults not detected? For simple combinatorial logic, there are two basic reasons: either the simulation was
not complete enough to find the fault, or the circuit itself cannot be
tested for the fault. So when an undetected fault is located, the
first step taken is to add vectors to the simulations which will
exercise the node being tested. By doing this, we gradually
improve the quality of the simulation, and thus the quality of the
test sequence that we can use in production.
5-74
It is possible that certain nodes will have undetectable faults for
which no new vectors can be added. These are the result of an
untestable design. It is the joint job of the test and design
engineers to generate a test sequence that is as complete as
possible. It is the design engineer's responsibility to provide a
circuit which is testable. If both of these responsibilities are
carried out, the result will be a testable circuit which can be tested
with an exhaustive test sequence. This will yield the highest
quality system. Note, however, that the overall responsibility is
shared between the design and test engineers.
All of the previous procedures dealt mostly with the ways in which
existing circuits are treated. However, if a finished circuit is found
to be untestable, then it must be redesigned for testability. An
easier approach is to design for testability from the beginning.
Unfortunately there is no direct recipe for a testable design. There
are, however, many common ways of making a circuit untestable.
Most of this section is devoted to pointing out such problems.
The simplest kind of problem is redundant logic. Figure 3a shows
one such circuit. It has a purely redundant product term. H the
output of either of the product terms is stuck low, for any reason,
then as long as the other product term is good, the fault will never
be visible at the output.
This may initially look like a benefit, since we have what we could
call a "primary" circuit with a "backup." One can cover up some of
the failures of the other (but not all failures). If this kind
redundancy is truly desired, this is not the way to achieve it. When
you ship out thi$ circuit, you do not know if you really have a
working primary and backup. The primary may already be malfunctioning; since it was never tested, you will never know. If you
want useful, reliable redundancy, test circuitry must be added, as
in Figure 3b, so that each part of the circuit can be independently
tested.
Testability
of
AMol1
Figure 4 shows another redundant circuit. Although the product
terms are not identical, the larger AND gate is really redundant.
Any stuck-low faults at the output of this gate are not detectable.
~~"B.A'B'A"
FANS OUT
RECONVERGES
14099-OO5A
Figure 5" Reconvergent Fanout
a. A Purely Redundant Circuit
A
one condition. In other words, there is no way that we can
guarantee that,that node is operating correctly.
BACKUP
It is worth analyzing this circuit a bit more closely. This will give
some insight into the kinds of analyses that are necessary when
evaluating circuits and generating tests, and into the ways in
which untestable nodes are created.
PRIMAR~~
= A"B"PRIMARY
+ A"B"BACKUP
A
b. Testable Redundant Circuit
8---+--I
14099-003A
C
Figure 3. Making Redundancy Testable
14099-00SA
ReconvergentFanout
Figure 6. A Reconvergent Circuit with an Untestable Node
Redundant logic is a special case of what is called reconvergent
fanout. This is a term that refers to circuits that have inputs
If we wish to prove that the node in question is not stuck high, then
we must force it low and prove that we were successful in doing
so. Thus we have two requirements: forcing the node low, and
seeing the logic low on the output -controlling and observing the
node.
C
~~
C'D'E. D'E. D'E
splitting up, going through independent logic paths, and then
reconverging to form a single output, as shown in Figure 5. When
this happens, it is very easy to introduce untestable nodes. It may
not be easy to identify where such nodes are.
First we raise input C high to force the node to a logic low
condition, as in Figure la. This satisfies our controllability requirement. Next we need to provide a way to propagate this logic low
to the output (Figure lb). This is referred to as sensitizing a path
to the output. The first step is to get the logic low past the AND
gate. But if either input A or B is low, then the output of the AND
gate will be low regardless of the node being tested. Thus we must
force both A and B to a logic high, so that if there is a low on the
output of the AND gate, we will know for sure that it came from the
node we are testing. This is shown in Figure lc.
Figure 6 is an example of a reconvergent circuit. The inputs are
shared between two different product terms, which are eventually
summed. This circuit appears harmless enough, but it turns out
that the node indicated by "SA 1" cannot be tested for a stuck-at-
Next we wish to get the logic low through the OR gate to the
output. To do this, we must insure that the second OR input is
always low; if it is high, then the output of the OR gate will be high
regardless of the node being tested. If we can keepthe lower OR
14099-004A
Figure 4. Circuit with a Redundant 3-input AND Gate
A
=1
B
= 1---+_-I
C
=1
a. Controllability: Forcing the Node Low
c. Propagating Past the AND Gate
=1
8 = 1---+--1
A
C = 1
b. Observability: Sensitizing a Path to the Output
d. Propagating Past the OR Gate Sets Up an
Impossible Condition
14099-007A
Figure 7. Analyzing Testability
Testability
5-75
l1AMD
A
input low, then if the node we are testing was sucessfully forced
into a low condition, then the output will be low. Otherwise the
output will be high. This can be seen in Figure 7d.
-4-------,
B - t.......- - - - t
c
How do we keep the lower OR input low? Sy making the output
of the lower AND gate low, which can be done by setting one of
its inputs low. However, we have already required that all of the
inputs be high. Thus we have required a set of conditions that
cannot be met. One of three things will result:
1. The lower AND gate has both inputs high, and therefore keeps
the lower OR input high. In this case, we may have been
successful in forcing the node under test low, but we cannot
see it at the output.
2. We bring input S low, allowing the lower OR input to go low.
However, now the output ofthe upper AND gate will always be
low. So we will see a low at the output, but we cannot be sure
exactly where the low came from.
3. We bring input C low, allowing the lower OR input to go low.
However, now we are no longer forcing the node under test
low.
So we can either force the node low, but cannot see the low at the
output; or, we can see a low at the output but cannot be sure of
its source; or, we cannot force the node itself low. In any case, we
will never be able to guarantee that the node under test is not
stuck high.
Note that the two "independent logic blocks" which generate the
signals that eventually reconverge are testable by themselves;
they are just AND gates. It is only when we hook them together
via the OR gate that the overall circuit becomes untestable. Thus
Figure 9* A Messy Reconvergent Circuit
addition to this, there is again a stuck-at-one fault that cannot be
tested.
Circuits like this can result from the design iteration process, as
a designer tries to debug a circuit. Sy adding this and that,
eventually the circuit works. Sut it is a mess, has poor timing
characteristics, and is untestable. A little analysis of the logic itseH
shows that:
the bottom output is
(A+ B) = A*S
thus the middle output is
(A"B) =A+ B
which makes the top output
the testability of individual portions of a circuit does not guarantee
that the entire circuit will be testable when the testable pieces are
all connected.
(A*S*C + C*(A + B)) = (A*S*C + A*S*C)
= (A"B)
=A+B
We can minimize this circuit using the following steps:
A*S"c + S*C = A*Soc + S*C + A*S*S (by consensus)
= A*Soc + S*C + A*S
= A*S + S*C
_Thus the node we were trying to test is really not needed in the
logic. The resultant circuit is shown in Figure 8, and is completely
testable.
Not all reconvergent circuits are so simple. Figure 9 shows a more
complicated reconvergent circuit. Here some signals have to
travel through several levels of logic to reach their final destination. This introduces considerable skew into the circuit, and will
produce glitches on the outputs during certain transitions. In
A
S
~.
=A*S
+ S*C
That is, the top two outputs are actually the same, and the third
output is just the inverse of the top two. As convoluted as the
original circuit looks, the logic itseH is actually trivial. So if three
outputs are really needed for some reason, we can generatethem
independently, as in Figure 10a. If only two outputs are needed,
it is even easier. Figures 1Db and 1Dc show two possibilities.
These circuits are much easier to understand, their timing characteristics are better, and they are completely testable.
The Importance of Minimization
The common factor behind all of the untestable circuits we have
examined is the fact that all of them were not minimal. Sy
minimizing the logic, we made the circuits testable. This is true in
general: UNMINIMIZED LOGIC CANNOT BE FULL Y TESTED.
C
14099-00BA
Figure 8. The Minimized Circuit is Testable
5-76
Testability
AMOl1
A_----t""""\
B -+-+----L..-/
= I(A'B)
x=
B
A'B
+ IB'A
= I(A'B)
= I(/A +/8)
a. A Glitchy Circuit
A
a. A Cleaner 3·0utput Version
B
:I-~_/(A.BJ
~_/(IA'I8J
C
b. A Clean. Fast 2-0utput Version
u
x
b. Waveform for the Glitchy Circuit
A
C
B
00
01
11
10
c. A Slower 2-0utput Version.
14099-010A
Figure 10. Simplifying the Circuit of Figure 9.
c. "Gap' in the Karnaugh Map Indicates a Logic
Hazard
'ery often, especially when designing with PLDs, an attempt is
lade to minimize logic only to the point where it fits into a
articular PLD. Any further minimization is considered an acaemic waste of time. This is a grave misconception. Getting rid of
II extra product terms, and eliminating all extra literals on the
3maining product terms has real value. Failing to do so will result
1 untestable nodes in the circuit.
~inimizing is not always enjoyable, since hand techniques are
sually too tedious, and Karnaugh maps are essentially useless
)r more than four or five inputs. However, computers have long
,een used to minimize logic. In particular, PALASM® software
lersion 2.22 and later) has a minimization routine which can
linimize logic automatically before assembly.
.ogic Hazards
)ne occasional side effect of minimization can be the introduction
If glitches into a circuit. Figure 11 a shows such a "glitchy" circuit.
-he waveform in Figure 11 b shows that under steady-state
onditions, as long as inputs A and C are high. the output is high
egardless of B. However, as Bchanges from high to low, causing
1e top product term to shut off and the bottom one to turn on. the
werter adds a bit of delay to the path that will turn on the lower
Iroduct term. Thus the top term may shut off before the bottom
Ine gets a chance to turn on. In this case, we have two logic low
ignals going into the OR gate, giving a Iowan the output. As soon
lS the lower product term turns on, the output goes back high, but
14099-011A
Figure 11. Examining a Glitchy Circuit
not before the appearance of the high-low-high glitch.
Figure 11 c shows the Karnaugh map for this circuit. It is minimal,
but there are two product terms which do not overlap; they are
"adjacent" in one location. These represent the two AND gates in
the circuit diagram. The arrows indicate the troublesome transition: when A and C are high, and when B changes from high to low
or the reverse. We can intuitively think of this as a "gap" between
the two adjacent product terms, in which a glitch may occur.
Note that glitching is not a certainty. It is called a hazard because
in certain situation, given certain timing situations, there is a
chance that a glitch will occur .
Note also that the glitch is not really caused by the minimization
process itself, but is caused by these "gaps" in the Karnaugh map.
Unminimized logic with such gaps may also be glitchy.
A PROM is a good example of such a circuit. PROMs can be used
to implement any logic function of their inputs. However, regardless of the function, it is implemented in acompletely unminimized
fashion, using complete minterms. So even a function as simple
as the one in Figure 12 (which could be implemented using a
single product term, grouping all 1's into a single cell) is implemented with each 1 in its own cell. Thus there is a gap between
every cell, meaning that every transition is a potential glitch.
Testability
s-n
~AMD
PROMs are notoriously glitchy, and it is for this reason that the
output of a PROM is actually undefined until its access time has
elapsed.
If we go back tothe Karnaugh mapin Figure 11c, we see that we
can eliminate the gap-and the glitch-by adding aproductterm
which overlaps both existing product terms and covers the gap.
This is shown in Figure 13a, with the resultant circuit shown in
Figure 13b.
input. But if we isolate just that portion which corresponds to th
test input being high, which is the normal operating mode (se
Figure 14c), it looks exactly like the map of Figure 13a. Of cours
we should expect this, since we do not want the addition of ate!
circuit to affect the basic function.
Thus, in general, these types of glitches can be eliminated first b
adding some redundant logic to get rid of the gaps in th
Karnaugh map, and then by adding a test input to make the circu
testable.
This circuit is no longer glitchy. Unfortunately, it is also no longer
testable, since we hxave added in a redundant product term that
Z
Yoo
W
00
0
01
0
11
0
10
0
01
11
CD CD
CD CD
CD Q)
CD CD
10
0
0
~mP--
•
0
0
14099-012A
TEST ~
= A'B'ITEST
: !!;oITEST
a. A Testable. Glitch-Free Circuit
Figure 12. In a PROM, Every Transition Can Glitch
cannot be tested (try it yourself). In order to have a circuit that is
both testable and glitch·free, we must add a test input to the circuit
which we can use to shut off the outside gates, isolating the
middle gate for testing (Figure 14a). When the circuit is operating
normally, the extra input is kept at a logic high condition, where it
does not interfere with the basic logic function.
A
C
B 00
A
C
TE ST Boo
00 0
01
01
0
0
0
11
0
0
V1
1"
10
l'
0
1
~.L
J
0
11
1\.1....1
10
0
0
b. Karnaugh Map
a. A Redundant Product Term Can
Eliminate the Glitch
'~l'~X_AO.
.
.
C
+ IB'C
+ A'C
b. A Glitch·Free. but Untestable Circuit
c. Karnaugh Map Showing Non-Test-Mode Portion
14099-013A
Figure 13. Eliminating Glitches
Figure 14. Making a Glltch·Free Circuit Testable
The Karnaugh map for this circuit is shown in Figure 14b. Note
that all product terms overlap, but now the circuit is minimal. The
size of the Karnaugh map has doubled, since we added another
5-78
14099-014,
Testability
AMD~
Using Output Enable
Most state machine PLDs are equipped with an enable pin for
disabling the outputs. This is a key feature when the circuit board
is to be tested in a bed-of-nails tester. When the devices driven
by by the PLD are tested, it is recommended that the PLD be
disabled so that there is no output level contention. Since the
enable pin is usually grounded to keep outputs permanently
enabled, it can instead be made available for use during testing.
Note that for combinatorial devices, there is generally no output
enable pin. The disabling feature is instead implemented through
a product term. This feature is called programmable three-state.
Designing the part such that the outputs can be disabled during
bed-of-nails testing is also encouraged for these combinatorial
designs.
The user must be especially aware of the observability of outputs
with programmable output three-state. In Figure 15, input B
controls both the basic circuit logic and the three-state control
logic. Therefore, any function which involves B in a LOW state will
not be observable, since the output will not be on. Figure 16a.is
a simplified representation of a register whose output cannot be
observed because the three-state buffer is disabled when the
output is LOW. Likewise, the circuitry in Figure 16b cannot be
observed when the flip-flop output is HIGH. The user must make
sure that an output will not be disabled when the results of a test
are to be observed.
A------------r-~
B
J-----------~
a. LOW state observable
c---...---t~
D
b. HIGH state unobservable
10483A-171
14099-015A
Figure 16. Untestable registered output with
programmable three-state
Figure 15. Untestable combinatorial circuit
with programmable three-state
Testability
5-79
~AMD
Designing Testable Sequential Circuits
Latches
The design of sequential circuits involves considerations above
and beyond those required for simple combinatorial circuits.
Latches and oscillators are circuits which appear combinatorial,
but which use feedback to introduce sequential properties. State
machines use flip-flops and feedback to generate what can be
complex sequential circuits.
A combinatorial logic circuit which uses positive feedback is a
latch. The simplest possible latch is shown in Figure 19a. The_
output is fed back as an input in its TRUE form. This means, of
course, that the output will stay at its present level; hence the
name "latch."
Feedback
Whereas combinatorial circuits depend only on the conditions of
present inputs, sequential circuits depend on both present conditions and past behavior to determine future behavior. This is
made possible primarily by feedback. Feedback takes an output
signal and routes it back for use as an input to the same circuit,
as shown in Figure 17. We now have a situation where an output
depends on itself; this can introduce new testability problems.
a. Completely Uncontrollable
b. Cannot Set Output HIGH
14099-016A
Figure 17. Logic with Feedback
Most sequential circuits (under varying circumstances also called
state machines, finite state machines, and sequencers) make
use of flip-flops as memory elements. These memory elements
serveto remembera past condition (called a state) sothat afuture
decision can be made based on it. This state is then fed back as
input. With PLDs, the flip-flops and combinatorial logic are contained within a single device, as shown in Figure 18.
c. Cannot Reset Output LOW
14099-018A
Figure 19. Uncontrollable Latches
The circuit as shown is clearly not useful, since it will always
remain in its power-up state. If another input is added, as in Figure
19b, a HIGH output could be made to go LOW by setting the
RESET input LOW. However, once the output goes LOW, there
is no way to make it go HIGH again. Likewise, the circuit could be
modified as in Figure 19c. Now a LOW output can be made HIGH
by setting the SET input HIGH. However, once HIGH, the output
can never be made to go back LOW.
FLlPFLOPS
14099-017A
Figure 18. Structure of a Sequential PLD
Of course, the effects of feedback may have to be considered
even when there are no flip-flops. The circuit in Figure 17 has
feedback, but has no flip-flops. Such a circuit will either function
as a latch or as an oscillator, as will be seen.
Controllable latches
For a latch to be useful, it must be completely controllable. The
previous latches cannot be completely controlled. In order for a
latch to be controllable, it must have both SET and RESET
controls, as shown in Figure 20.
Before we look into the special needs of circuits with feedback,
bear in mind that all of the testability criteria discussed for
combinatorial logic still hold. The blocks of combinatorial logic
shown in Figures 17 and 18 must be testable by themselves.
What we will discuss here are issues which must be considered
in addition to the issues involving combinatorial logic.
5-80
Testability
SET~
RESET~
14099-019A
Figure 20. A Controllable Latch
AMD~
In PLDs, a latch can be detected by simplifying the logic for each
function. If an output is a function of itself in TRUE form, then it is
a latch. To be controllable,
A
B
• productterms containing the feedback should have at least one
other direct input in the product (providing RESET control).
C
• there should be at least one product term with no feedback
(providing SET control).
o
x
The circuit in Figure 21a provides an example. At first it is not
immediately obvious that the circuit is a latch, but when the logic
is simplified, we see that indeed it is. It is controllable since it has
both SET and RESET controls. H the logic were as shown in
Figures 21 b or21 c, the latch would be uncontrollable under some
circumstances.
= A
+ B'Y
=A
Latch hazards
+ B'(C + O'X)
.. A
+ B'C
The circuit of Figure 20 can be generalized to have several inputs
on both the set and reset controls. Such a circuit is shown in
Figure 22. In this case, we have two inputs on the set AND
gate. If the two set inputs A and B change from 0 and 1 to 1 and
0, respectively, then there will be a glitch or a false latch at the
output if both inputs were 1 at some time during the transition
(Figure 22). For this transition, it is important to make sure that
the 1-0 transition be made before the 0-1 transition to avoid
anomalous output behavior. Merely delaying one input will not
help, since it will delay both rising and falling transitions.
] SET
+ B'O'X
LJ
RESET
8.
latch with SET and RESET
B
The simplest solution to this problem is the use of an edge-
o
x = B'Y
a. Circuit
+ B'O'X
L.J
RESET
A
b. latch with RESET Only
B
A
C
B
C
X
x=
L....._ _ _ _~_ -
-
-
____
...
EXPECTED
b. Glitch and False Latch
A + Y
= A
+ S'C
+ X
14099-021A
] SET
Figure 22. A Latch with More Complex SET logic
c. Latch with SET Only
14099-020A
Figure 21. More Complex Latches
triggered flip-flop to synchronize the signals. This will eliminate
any such glitches. If a flip-flop cannot be used, it is possible to
delay reaction to a "11 n condition to make sure that such a
condition is not transitory. A circuit that accomplishes this is
This delay circuit will delay the effect of an "11 n input by an extra
Testability
5-81
Ir1 AMD
shown in Figure 23a. This is relatively efficient in that only one
delay circuit is required regardless of the number of inputs used
on the set con~rol (within the limits of the size of the AND gate).
It will require an extra output on a PAL device.
DELAY
GATE
A
B
Because we have introduced redundancy, the circuit must be
modified to be testable. If the circuit is implemented in a
combinatorial PAL device, then programmable three-state can be
used to test the circuit, as shown in Figure 23b. By enabling
output X, the redundant circuit can be observed without regard to
V. Then, to test V, output X is disabled and then the pin is used
as an input to drive the circuitry for V directly. This provides a
simple means of testing the circuit, but it only works if pin X can
be measured and driven. The complete circuit is shown in Figure
24a.
Hnode X is not so accessible, then additional circuitry and test
inputs must be added. In the worst case, if node X is completely
--+-f--4--~_
--+-~--~
N -
......- - - - 1
TEST - - - - - - I
SET CONTROL
AND GATE
a. Circuit Which Delays "11 ... 1" signals
TEST
~ ==±:!===:J ~
------I
C-----r-~--_/.:..--
Y
x
a. Complete Latch Circuit
~ =::t::!::=:=t j J - - - - -
Y
To control X _TEST1 - - - - - - - - - - ,
independently ,.
of A and B. ~TEST2 _-;::====~
b. Testable Delay Circuit
14099-022A
Figure 23. Delay Circuit
TEST3 --+--l-I--~
propagation delay. However, it also provides a window of one
propagation delay which will screen out any transitory "11"
conditions that occur within that window. This allows up to one
propagation delay's worth of skew between inputs during a
transition from "01" to "10."
/'--jr.==:t=~==f--
To MUX X
to output"
directly
'"
A
B -
.........+--~
TEST4
C
Y
----~
b. Circuit if Node X is Completely Inaccessible
A
B
F
C
Y
c. Latch Circuit Behavior
Figure 24. A Testable Glitch-Free Latch
5-82
Testability
14099-023A
AMD~
inaccessible, the resulting testable circuit is shown in Figure 24b.
Note that although the three-state capability is not needed, the
circuit requires two extra gates, and, worst of all, four test inputs.
an oscillator out of standard logic or PLDs will not yield a very
predictable, accurate oscillator; where these circuits occur, it is
usually by accident.
Figure 24c shows the behavior of either of the testable glitch-free
latches.
An oscillatory circuit may not always be obvious. It also may not
oscillate all of the time. The oscillator shown in Figure 26 is
uncontrollable; it always oscillates. However, just as we can
design controllable latches, we can also design controllable
oscillators (on purpose or by accident). This means that there
may be an oscillator hidden in the circuit which will sometimes
oscillate and sometimes be stable. Such a circuit is shown in
Figure 27a.
Transparent latches
Many designers like to use PLDs to design standard D-type
''transparent" latches. A D-type latch is a very simple circuit,
shown in basic form in Figure 25a. As it turns out, however, this
is a glitchy circuit of the type discussed in the combinatorial
section. The problem is compounded in this case, since, given the
right timing, the glitch can actually be latched; the glitching
problem is no longer transitory. If this type of circuit is desired, it
must be designed to be both glitch-free and testable; the resultant
circuit is shown in Figure 25b.
---;===[)------=r- x ==
A"S"Z
A"S"D"E
+ A*S"C"/x
)------+--if--- Y
---""':::;--L../
= C"/X
+
+
+
DATA---------r~
GATE
OUT
Z
IA·C
IS"C
C"/O"IV
C"E·IV
= D"E
+ Y
=
a. Complete Circuit
D"E
+/A*C
+ IS"C
+ C"/Z
OUT = GATE"DATA
+ IGATE"OUT
x=
A*S"O"E
+ A*S"C"/X
a. Glitchy
TERM 1
TERM 1
b. The Equation for X
14099-026A
Figure 27. A Conditional Oscillator
Detecting oscillators
The oscillator in the circuit is not obvious. But if we simplify the
logic completely, we can see that output X depends on IX; output
Y depends on N; and output Z depends on IZ. Since the outputs
are fed back to themselves in COMPLEMENT form, the circuit
constitutes an oscillator.
OUT = GATE"DATA*ITEST
+ IGA TE"OUT*/TEST
+ DATA"OUT
b. Glitch·Free and Testable
14099-024A
Figure 25. 0-Type Transparent Latches
Oscillators
Circuits whose outputs are fed back in TRUE form are latches. If
the outputs are fed back in COMPLEMENT form, then the circuit
is an oscillator. A simple oscillator circuit is shown in Figure 26.
14099-02SA
Figure 26. A Simple Oscillator
Latches are very often useful in circuits; oscillators rarely are.
Crystals and other specialized oscillators are useful when it is
necessary to generate a clock signal, for example. Trying to build
This circuit will sometimes be stable. If we examine the logic
function determining X, we see that it has two product terms,
shown in Figure 27b. Term 1 is independent of IX; term 2 is
dependent on IX. If inputs A, B, D, and E are all TRUE, then term
1 becomes TRUE, and the output stays HIGH regardless of the
status of the rest of the circuit. It is thus stable. However, if signals
D andlor E are LOW, then term 1 will be FALSE. If, at the same
time, input C is HIGH, then, as long as the output X is LOW, term
2 will be TRUE, making the output HIGH (which makes the
product term FALSE, which makes the output LOW, etc.). That is,
the circuit oscillates.
In this manner, we can identify the conditions under which a
conditional oscillator will oscillate. The mere presence of an
oscillator is usually an indication that the circuit needs to be
changed. It may be that the circuit only oscillates underconditions
that could never possibly exist. One must be very certain of the
impossibility of such a condition, however, if a conditional oscillator is to be tolerated. In addition, a thorough test sequence will
usually expose a circuit to conditions that it may never encounter
in a real system. Thus oscillators may interfere with the test
process even if they do not disrupt the system.
Testability
5-83
~AMD
Using a Programmable Clock
When using the programmable clock on an asynchronous device,
caution must be exercised with data setup. Refer to Figure 28a,
where A and B are primary inputs. One setup time (t s) after signal
A goes active, signal B goes active, clocking signal A into the
register. In Figure 28b, B is a primary input but signal A is fed back
from another register. In this case it may be harder to ensure that
the proper setup time is allowed before signal B is asserted,
possibly causing improper information to be clocked into the
register.
This is a simplified scenario. It does not take into account the
product term on the clock, which can be programmed with a
combination of any of the array inputs. A complex clock term can
be a hidden source of frequently-violated setup time when feedback terms are used. Always be aware of which input or
combination of inputs and feedbacks will clock each register, and
calculate setup time backwards from the last input which will
assert the clock term. This is the best and probably the easiest
method for determining when data must be made available at the
input of the register.
o
This is an important testability issue because with a programmable clock, the tester may no longer be in control of the clock
timing. Automatic test equipment is capable of handling the
timing for dedicated clock pins, but the programmable clock
feature does not allow the tester the lUXUry of a single controlled
clock pulse.
D
a
A
a
c
B
A _ _ _ _ _--'
B
A----+-+------I
...
----------1
B-----~-
c--------...J
c--------+-+----b. Using feedback to drive the clock
a. Using an input to drive the clock
14099-027A
Figure 28. Using a programmable clock
5-84
Testability
AMD~
Designing Testable State Machines
input pin and potentially one product term on some outputs; this
can affect the choice of device for the design.
State machines have their own set of controllability issues. These
essentially boil down to the concepts of initialization and illegal
states.
To provide initialization in an otherwise complete design when
Boolean equations are being used:
State machine Initialization
The nature of a state machine is that there is a well-defined
sequence of states through which the machine will traverse as it
operates. This implies the existenc~ of a '1irst~ state. Of co~rse,
these initial states vary from design to design. One obvIous
problem is the fact that many flip-flops - especially older varieties - do not power up in a predictable state.
Power-up Initialization
Flip-flops that truly power up into a random state must be
initialized explicitly. Lately, however, flip-flops have become
available which have "power-up reset". This allows the flip-flops
to power up into a predictable state every time. This is helpful
when the power-up state also happens to be the initial state. But
even if it is not the initial state, a predictable initialization sequence
can bring the state machine into its start-up state.
• determine the start-up state.
• assign each bit as being initialized active or inactive, based on
the desired start-up state.
• if a bit is to be initialized inactive, add "'IN IT" to every product
term for that bit.
• if a bit is to be initialized active, add one product term consisting
solely of "INIT."
Here we have assumed that the initialization pin has been called
"IN IT. " "Active" would mean HIGH for an active high device; LOW
for an active low device. "Inactive" is just the reverse.
The equation in Figure 29a can be. init~alized inacti~~ ~s s~0v.:n
in Figure 29b, or active as shown In Figure 29c. Initialization IS
accomplished by asserting the INIT pin and clocking once. This
"cookbook" approach is very reliable.
ao:= 01'02
+ 02"03
Unfortunately, such initialization schemes rely on th~ ability of the
device to initialize itself when being powered up. If the system
needs to be re-initialized, it will have to be completely turned off
and then turned on again. Anyone who has had to turn off a
computer in order to reboot will know that this is not an elegant
way of re-initializing. By building initialization into the design, a
means of performing a "warm boot" is provided. It is for this
reason that initialization must be considered along with all other
aspects of the design.
a. Uninitializable
00: = 01'02"INIT
+ 02"03"INIT
b. Initialized Inactive
00:= 01'02
+ 02"03
+ INIT
Some devices have mechanisms specifically designed for initializing a state machine. These are usually in the form of global
preset and reset product terms. By programming the conditions
for initialization onto such terms, the device can be re-initialized
at any time.
c. Initialized Active
14099-028A
Figure 29. Designing In Initialization
Including Initialization In a design
Some of the simpler devices do not have specific provisions for
initialization. However, the need is still present in these devices;
here the initialization should be included in the design. This is a
very simple process; it can be added in after all of the other design
details have been worked out. Adding initialization will use up one
PALASM software also makes it possible to design state machines with a special syntax which essentially allows the state
diagram to be transferred directly into a design file. For devices
which have no dedicated initialization features, the initialization
branches should be explicitly built into the state diagram. The
software then performs the remainder of the processing needed.
Testability
5-85
~AMD
Illegal states
A state machine is formed by using a set of flip-flops to remember
states, and assigning a code to each state. Since there are 2"
different codes that can be assigned to a group of n flip-flops,
there is a good chance that some codes may not be used. For
example, if a state machine is to have 6 states, 2 flip-flops will not
be sufficient; 3 are needed. But 3 flip-flops allow 8 states, which
will result in 2 unused states (see Figure 30).
14099-030A
Figure 31. Using Initialization to Recover
14099-029A
Figure 30. Illegal States
Assuming that the state machine has been designed correctly,
there is no reason why these extra states should ever be entered;
therefore they are called "illegal" states. Unfortunately, situations
do occur, thanks to noise and other unpredictable occurrences,
which result in the state machine being in an illegal state. When
this happens, the immediate need is to return to a normal
sequence of states: there must be a predictable means of getting
from any illegal states into a legal state.
Illegal state recovery is a controllability issue which actually
affects functionality more than it affects testability. But the concepts used for functionality and testing are so closely related that
it is worth treating here.
14099-031A
Figure 32. Cycling Back to a Legal State
which eventually leads back to a legal state. In these cases,
merely clocking enough times will cause the machine to recover.
Recovering from Illegal states
The drawback here is that one does not know ahead of time how
many clock cycles will be needed. This necessitates some builtin way of knowing just when a legal state has been re-entered.
And once that state has been reached, further cycling may be
needed to get to a point where operation can resume.
There are three basic ways to get out of an illegal state:
Designing-In one-step recovery
• re-initialize
• make sure that one can continue clocking until the machine
recovers
• design the machine such that the start-up state is reached from
any illegal state in one clock cycle, independent of any conditional inputs
The most predictable way of dealing with illegal states is to
provide a one-step path back to a legal state. Depending on the
state desired, more or less work may be involved to do this. For
PAL devices, we can consider three cases:
Of course, re-initializing will take the machine back into its startup state from any state, legal or illegal (Figure 31). The disadvantage here is that outside control is needed to force initialization.
Very often, a path will exist which eventually takes the state
machine back into a normal sequence (Figure 32). These paths
are not usually designed in; they just happen to be there. In fact,
if D-type flip-flops are used, it is surprisingly difficult to get a
"closed" set of illegal states (that is, a set such that once one of
the illegal states is entered, the machine will forever remain in
illegal states) by accident. In most cases, there will be a path
5-86
• all illegal states go to state 00 ... 0
• all illegal states go to one state other than 00 ... 0
• each illegal state goes to some legal state
The cause of poor illegal state recovery can be illustrated conceptually with Karnaugh maps (although realistically, Karnaugh
maps are often not used). When calculating the equations for a
particular bit, it is tempting to use Don't Care cells from the
Karnaugh map (Figure 33) to simplify the logic. The success of
illegal state recovery depends on how these Don't Care cells are
treated.
Recovering Into state 00 ...0
Testability
AMD~
0102
00
01
Q3 Q4
11
10
00
X
0
X
X
01
X
0
0
X -
11
0
1
X
X
10
0
X
X
X
J
oJ
J
trated conceptually with a Karnaugh map. It must first be decided
which legal state will be entered, and the resultant value of each
state bit. The Don't Care cells for each bit are then filled with the
corresponding next state bit value; if the next state for a bit is to
be1, then Don't Care cells are filled w~h 1's for that bit's Karnaugh
DONT CARE
CELLS CORRESPOND
TO ILLEGAL STATES
01
14099-032A
Figure 33. Illegal State
his is the simplest case; it is illustrated in Figure 34. It is
ccomplished by not using any illegal states to generate the logic
)r any of the b~s. Since most PAL devices have only Ootype flipops, a bit will go HIGH only as a result of legal states. Any illegal
tates will cause all bits to be LOW.
his prOCedure does not work when J-K or T-type flip-flops are
sed. In fact, it is deadly. Whereas a Ootype flip-flop defaults to
OW, J-K and T-type flip-flops hold their present state as a
a. State Diagram
1
X
X
X
0
~
X
X
1
1
~
X
0
0
0
1
b. Karnaugh Map for Bit On
18
a. State Diagram
0
0
0
~
0
0
Ir;- l:J' lo
0
0
0
0
CD
0
X
X
~ 0) r-..!
X
0
I\...
X
X
0
X
X
0
C.
oeD
b. Karnaugh Map
14099-033A
Bit On Recovers to, 0
(1
0
Figure 34. Recovering to State 0 ... 0
efault. Thus if illegal states are not considered in the transfer
mctions, an illegal state will cause the state machine to be locked
p in that state.
CD
1"
1
1
1
3
1
Ie 1
1
II
1
0
0
0
1
~
d. Bit On Recovers to 1
tecoverlng Into one fixed state
14099-034A
Figure 35. Recovering to a State Other Than 0 ... 0
his case is shown in Figure 35a. The procedure can be iIIus-
Testability
5-87
~AMD
map; the procedure for a O-b~ is analogous. The equations are
now taken by including either all Don't Care cells if filled with 1's,
or none of them if filled with O's. This procedure is illustrated in
Figures 35b, c, and d.
When Karnaugh maps are not used, the same result can be
obtained by explic~ly considering all illegal states. When calculating the Boolean equations for:
• a bit that will be 0 after recovery,
included.
no illegal
states should be
• a bit that will be 1 after recovery, all illegal states should be
included.
When J-Kflip-flops are used, then the transfer function for either
J or K - but not both - will include all illegal states .
• H a bit is to be HIGH after recovery, J should account for all
illegal states; K should account for none.
a. State Diagram
• H a bit is to be LOW after recovery, K should account for all
illegal states; J should account for none;
This must be done explicitly for J-K flip-flops even if state 0... 0 is
the recovery state.
1(1
1
1
1
0
0
0
1
1 "",1
1
1(1
When T-type flip-flops are used, there is no easy way out; any
recovery must be explicitly designed-in as part of the original
function.
0
0
~
b. Karnaugh Map
Recovering Into Any Legal State
The third case allows one to fill in the Don't Care cells of a
Karnaugh map in such a way that some legal next state is always
reached in one clock cycle, but such that the 1's and O's are placed
to keep the logic functions simple. This is shown in Figure 36. The
disadvantage here is that since different illegal states result in a
different legal state, some additional cycling may be required to
allow operation to resume.
14099-035J
Figure 36. Recovery Such That Logic Functions Are As
Simple As Possible
When Karnaugh maps are not used, this can be implemented
more simply by explicitly including the illegal states as part of the
complete state diagram.
5-88
0
Testability
AMD~
·esting Illegal state recovery
)ne of the difficulties of designing illegal state recovery into a
ircuit is the fact that it is difficult to test. Because the state is
legal, it is impossible to force the circuit into such a state. The use
If register preload circumvents this problem. With preload, any
tate - legal or illegal - can be loaded into the register. If an
legal state is loaded, then the circuit can be tested to verify that
orrect recovery does indeed occur.
o
The use of preload must be considered carefully with devices
having programmable asynchronous preset and reset features. If
these are driven by feedback from an output, then situations can
occur where preloading one state immediately causes a preset or
reset to the opposite state (Figure 37). There are two alternatives:
either avoid pre loading such states, or include a control input in
the preset and/or reset product terms which can disable the
feature when testing.
o
P Q
P Q
R
Cannot Preload 1
Stable
R
R
Cannot Preload 0
Stable
Stable Case: Can preload any state
Other Cases: Preloading any state will cause PRESET
or RESET to opposite state.
14099-036A
Figure 37. Preloading Registers with PRESET and RESET
Testability
5-89
~AMD
Using Test Vectors
Digital systems are generally tested by applying a sequence of
test vectors. A test vector is a group of signals which are applied
(forced) and measured (sensed) on a device or a board. The
vector thus defines all inputs and expected outputs for a given
test. As we have noted, the sequence of tests performed greatly
affects the quality of the overall tests, as measured by the fault
coverage.
In general, we can talk in terms of three kinds of vectors.
Simulation (or application) vectors, functional test vectors and
signature test vectors.
Simulation vectors are generated during the design process.
Their main purpose is to help the designer verify that the design
has been correctly implemented. They represent the way in which
the circuit was intended to operate. When PALASM software (or
almost any other PLD design software package) is used, simulation may be performed prior to programming a device. The
software simulates the operation of the circuit, and then generates vectors from the simulation, adding the vectors to the JEDEC
file. These vectors can then be used for testing by programmers
that have the capability of performing functional tests.
While simulation vectors may be adequate for verifying that the
design is operating as expected, they generally do not provide
very extensive test coverage. For this reason, we distinguish
functional test vectors from simulation vectors.
It is very difficult to generate a complete set of functional test
vectors by hand; computer programs are generally used instead.
The simulation vectors are often used as a basis for generating
a more comprehensive set of functional test vectors; in this
capacity, the simulation vectors serve as seed vectors. There are
many programs which perform this function although many of the
programs require larger computers and take a long time to run.
AMD also generates functional test vectors for patterns that are
used in ProPAL devices.
quality. If complex internal feedback is used in a particular design,
then some manual test generation may still be needed to improve
the test coverage. 80th of these programs support the use of
register preload for initializing states.
While functional vectors provide more extensive tests, they may
not exercise the circuit in the manner in which it was meant to be
used. Thus, for example, a conditional oscillator in a circuit (as
discussed previously) may not be a problem during simulation,
since the conditions causing oscillation are not thought to be
possible by the designer. However, the functional vectors will take
all situations (some of which may not be physically possible) into
account in the tests. Thus more subtle design problems may
become apparent when functional test vectors are generated.
Signature vectors are random vectors which are first applied to a
device which is known to be good in order to generate a "signa·
ture". This same set of vectors is then applied to a device 01
unknown quality; if the same signature results, the device is said
to be good; if a different signature results, then the device is
assumed to be faulty.
Signature vectors can vary greatly in the quality ottesting they can
provide. Since they are generated with no knowledge of the circu~
being tested, many more vectors must be used to perform a gooC
test. The quality of the test depends on the circuit being tested, the
number of vectors used, the speed with which the tests are
applied, and the algorithm used to generate the vectors. The
tester must also be able to apply a preload sequence to device~
that have registers; otherwise two devices may power up into twe
different states. In that case, both devices will generate differen
signatures even if both are good devices.
Quality signature testing can be very cost effective, since ne
advance knowledge of a device pattern is needed. This reduce!
the amount of resources that must be dedicated to test vecto
generation.
The different types of vectors are summarized in Table 1 below
Programs have been developed to generate vectors for use in
testing PLDs. These programs use the programming information
in the JEDEC file to generate tests.
On most patterns, they can generate test sequences of high
TYPE OF VECTOR
PURPOSE
GENERATED BY:
Simulation
(Application)
Used for verifying whether or not
a design will operate as expected
when implemented.
Sequence defined by the design engineer,
usually by hand. Actual vectors generated
by design software, placed in the JEDEC file.
Functional
Used for verifying that
a device is operating
correctly.
Usually generated by a computer program.
The simulation vectors can
be used as seed vectors
Signature
Used for verifying that a device
is operating correctly without
functional vectors.
The tester generates the
test sequence during the test.
Table 1. Test vectors
5-90
Testability
AMD~
UMMARY
This can be done by simplifying each combinatorial logic block to
see whether any signal ultimately depends on itself.
Ie time to start considering ways of testing a circuit is before the
'cuit has been designed. The key to testability lies in the way the
'cuit is implemented.
lsic combinatorial logic can be made completely testable sim( by minimizing logic. It is not even necessary to analyze the
'cuit for redundancy or reconvergent fanout; automatically
inimizing all logic will eliminate any occurrences.
here a sequential circuit is generated from simple feedback
lths in the logic, the circuit must be analyzed as a combinatorial
·cuit. All combinatorial logic must be included to determine
lether the circuit is a latch or an oscillator. If a latch is desired,
,hould be completely controllable. If an oscillator is found, it is
obably not desired, and will generally indicate a mistake in the
Isign. If a conditional oscillator is to be tolerated, one must be
re that the oscillation conditions can never occur, and that the
st procedure will not cause oscillation.
general, combinatorial circuits should be analyzed completely
. the presence of latches and oscillators (wanted or unwanted).
When the sequential nature of a circuit is derived through the use
of flip-flops to generate a state machine, the two key issues are
initialization and illegal state recovery. A combination of device
features and careful circuit design will yield circuits that can
behave predictably even in unexpected situations.
It is important to analyze the testability of a circuit before committing it too far. Thus any changes can be made early on. In
particular, if the test analysis software points out any logic
hazards in your circuit, you can easily remedy them by modifying
the design.
These simple steps, taken early in the design phase, can help
avoid later redesigns, and ultimately provide a higher quality
system.
Finally, the ultimate test quality depends also on the quality ofthe
test sequence used for production, functional test vectors and
high quality signature tests will provide you with the highest
confidence in the quality of your system .
Testability
5·91
~
Ground Bounce
Advanced
Micro
Devices
INTRODUCTION
Mechanism
The development of fast PAL devices has increased the
importance of analog considerations the digital designer
has been able to overlook in the past. One of these is
ground bounce. Ground bounce refers to the ringing on
an output signal when one or more outputs on the same
device are being switched from HIGH to LOW. This
ringing can be in excess of 3 V. The system cannot consider the data valid until the ringing settles to below the
VIL of the receiving devices. The ringing in a fast device
can last so long that a slower device with less ground
bounce could actually be a faster solution.
Figure 1 shows a schematic of an output driver and load
including parasitic elements. The load capacitor is
charged to the HIGH-level voltage. When the transistor
turns on, the capacitor discharges into the transistor and
lead impedance. The resultant RLe circuit will have a
damped ringing (Figure 2). The peak amplitude depends on the edge rate of the switch and the RLC values, while the frequency of the ringing and the rate of
decay depend only on the RLC values.
The phenomenon of ground bounce is associated with
the inductance and resistance of the ground connection
in the integrated circuit. As there is always some inductance and resistance, ground bounce cannot be totally
eliminated; however, it can be reduced to a level tolerable to the system.
This article will discuss the mechanism of ground
bounce in CMOS circuitry and the utilization of slew-rate
control used by AMD to keep ground bounce down to
reasonable limits.
The ringing caused by a single output switching is normally below the LOW-threshold voltage. However, the
voltage at the ground pad of the device is proportional to
the number of outputs switching simultaneously. In addition, the voltage at the ground pad is coupled to any
LOW output through its output transistor. Therefore, if
enough outputs switch, ringing on the ground pad will be
coupled to LOW outputs, causing the detection of false
HIGHs.
Most PAL devices used today have relatively low output
drive current: 16 mA or 24 mA. It is tempting to think that
the low current level will somehow limit the switching en-
Vee
2.0V
1.0 V
0.5V
1
2.0V
1
Quiescent
Output
1.0 V
0.5V
13090-001A
Figure 1. Simplified Schematic of an Output Driver
5-92
13090-002A
Figure 2. Ground Bounce
AmendmenllO
AMD~
ergy and therefore ground bounce. Actually, even a lowpower transistor can pass a relatively large current. The
transistor I-V curve in Figure 3a shows that a MOS transistor designed for 16 rnA at 0.5 V will pass 90 rnA at 3.0
V. Figure 3b shows the VII path when the output transistor switches between HIGH and LOW. Notice that the
transistor switches from 3.5 V at 0 rnA to 3.0 V at 90 rnA.
If eight outputs were to switch simultaneously, 90 rnA X
8, or 720 rnA, would flow through the ground lead.
This sudden current surge is actually self-limiting. As the
ground-pad voltage rises due to the high current
change, the internal Vos and the available gate bias voltage are reduced, lowering the drive current. However,
the ringing can still exceed 3 V.
Controlled Edge Rate
The parameters that influence ground bounce are the
inductances and resistances of the device, the capacitance of the load, and the edge rate. Of these, the only
one that the chip manufacturer can directly control is the
edge rate.
Turning on the output-driver transistor is equivalent to
switching the charged load capaCitor to ground. This
can be represented by a step-voltage source in series
with the capacitor (Figure 4a). Slowing down the rate
that the output transistor can tum on changes the voltage source from a step to a ramp (Figure 4b). With a
90
90
10 (rnA)
10 (rnA)
16
16
0.5
3.0
Vos (Volts)
0.5
5.0
13090-003A
3.0
5.0
Vos (Volts)
13090-OO4A
3b. The Path Followed as the
Transistor Switches between the
HIGH and LOW Levels
3a. The DC Curve of an
Output Driver Transistor
Figure 3.
13090-OO5A
4a. Equivalent Circuit of an Output Driver
Transistor with a Capacitive Load
13000-OOSA
4b. Output Driver Circuit
with Slew-Rate Limiting
Figure 4.
Ground Bounce
5-93
~AMD
shallower slope, less energy is available for ringing and
the ground-bounce amplitude is reduced.
A Spice simulation (Figure 5) illustrates the effect. The
device without risetime control will have a very high
charging current with a large di/dt: 2.1 X 107 Ns.
Risetime control reduces the di/dt about 25%. This will
result in a corresponding reduction in the voltage that
can develop across the ground inductance.
AMD has a proprietary technique that slows the edge
rate of the output transistor, thereby reducing the amplitude of the ringing. Slowing down the fall time will add
about a nanosecond to the output delay, but the system
speed will still be greatly increased. On a high-capacitance load, a non-edge-rate-controlled device could ring
for more than 25 ns. The additional delay required to allow for the ringing would be intolerable.
System Ground Bounce Solutions
There are some things that the system designer can do
to reduce the ground bounce to a tolerable level.
1) Use AMD PAL devices that incorporate edge rate
control. This the first line of defense against ground-
bounce-related problems, and the most effective.
2) Use shorter lead packages. The bonding wires in a
PLCC are 1/4 the length of the ground bonding wire in a
DIP. The inductance is reduced proportionally. Any reduction in inductance will reduce the amplitude of the
ringing.
Some devices have center power and ground pins. The
ground pin will be substantially shorter and have a proportionately reduced inductance. This will reduce the
coupling between outputs. A good example is the
PALCE26V12.
3) Reduce capacitive loading. Capacitive loading in any
system should be reduced as much as possible. This
may involve consideration of the transmission line characteristics of the layout.
4) Limit the number of outputs switching simultaneously.
If the load naturally has high-capacitance such as a bus
or memory board WOUld, ground bounce can be reduced
by limiting the number of outputs that can switch simUltaneously in a single device. Many system designers
consider 4 to be an acceptable upper limit.
4
60
3
2
VOUT
(Volts) 1
40
I GND
(rnA)
20
·1
o
·2
1
2
3
4
5
6
7
8
9 1011 12 131415
Time (ns)
Sa. Without Risetime Control
4
13090-007A
60
3
2
VOUT
(Volts) 1
40
I GND
(rnA)
20
-1
o
·2
Time (ns)
Sb. With Risetime Control
Figure S. Effect of Risetime Control
S-94
Ground Bounce
13090-008A
~
Metastablility
Advanced
Micro
Devices
INTRODUCTION
A significant number of digital systems must deal with inputs not synchronized to their own internal clocks.
These asynchronous signals can arise from any of the
various asynchronous protocols, such as are often used
in bus designs; they can be the result of trying to share
signals from systems with different clocks; or they may
be the response of a system user, who is of course not
synchronized with the system. The result can be metastability, a problem which can plague unwary designers.
It is not a newly discovered phenomenon, but is normally dealt with somewhat qualitatively, and, unfortunately, is usually ignored as much as possible.
Data
ts
Clock
...JX'--___
Causes of Metastability
Outputs_ _ _ _ _ _ _ _ _ _ _
The flip-flop setup time is the parameter that is most
often at the root of metastability. The setup time is basically a requirement that data be made available at the
. input to the flip-flop before the clock signal arrives. The
data must not only be there, but must also be stable.
In a PAL device, the use of an array for the data adds to
the setup time. The data passes through the array on its
way to the flip-flop (Figure 1). The clock signal, on the
other hand, goes directly from the clock pin to the flipflop. Its path is much shorter than the data path. The
setup time is therefore essentially a requirement that the
data signal must be given more time to get to the flip-flop
before the clock signal.
If the published setup time is satisfied, the data arrives at
the flip-flop well before the clock, and the output to the
flip-flop will change as desired (Figure 2). If the setup
time is violated, then no guarantee can be made about
what the output will do. The output may be normal, since
the published setup time is a worst-case number. However, if the timing between the clock and data is just
right, the output will be unstable for some time before it
Figure 2. Output response when the setup time Is
satisfied
Data
Clock
_~_ _----I(VVV
Outputs_ _ _ _ _ _ _ _,1\V1\vv\o...
1\ n
Figure 3. Possible output response when the
setup time Is violated
D
Q
settles into some state. Neither the time the output remains unstable nor the final state is predictable (Figure
3). This condition is metastability.
Ways of Dealing with Metastability
Buffer
Figure 1. The clock and data paths In a
PAL device
Amendment/O
The most common way of dealing with this problem is to
synchronize the inputs with an extra flip-flop (Figure 4).
If the first flip-flop goes metastable, hopefully the delay
between clock pulses will allow the ringing to die down
5-95
arbitration schemes, use synchronization not because
synchronization itself is necessary, but because it provides the only convenient way to store data. This unfortunately takes a system that is inherently asynchronous
and adds some synchronizing elements in the middle.
Extra Flip-Flop for Synchronization
0
Q
a
D
~
Q
a
Summary
Figure 4. Dual synchronizer
before clocking into the next flip-flop. This improves the
chances of having good data in the second flip-flop.
This method is not without its costs. Each extra stage of
flip-flop means an extra clock delay of the data which
m!Jst be absorbed by the system. Moreover it is not foolproof. The possibility of metastability is reduced, but not
eliminated. A flip-flop can go metastable if the preceding
stage does not recover quickly enough.
The best way to avoid metastability is to avoid synchronization when possible. Many applications, such as bus
5·96
Metastability can occur in a number of different kinds of
asynchronous systems, usually due to the inability to
guarantee that the setup time of the flip-flops will be satisfied. In standard synchronous systems, where the
setup time (along with all other timing requirements) is
specifically designed in, metastability will never be a
problem.
In some situations, metastability is caused by the need
to interface systems with different clocks. In this case, it
will never be possible to completely eliminate the possibilityof metastability. Instead, the designer must take
steps to reduce the probability of a system failure due to
metastability.
Metastability
~
Latchup
Advanced
Micro
Devices
_atchup Circuit
--------,
.atchup is caused by an SCR (Silicon Controlled Rectifier) circuit.
~abrication of CMOS integrated circuits with bulk silicon process~g creates a parasitic SCR structure. The behavior of this SCR
~ similar in principle to a true SCA. These structures result from
he multiple diffusions needed for the formation of complemenary MOS transistors in CMOS processing. The SCR structure
:onsists of a four layer device formed by diffused PNPN regions.
-hese four layers create parasitic bipolar transistors illustrated in
:igure 1.
&ih
NWELL
Vcc
RpSUB
GND
14105-001A
ill
8
..
Figure 1
0
igure 2a shows a typical CMOS inverter layout with the schelatic of the parasitic bipolar SCR structure. Figure 2b is a cross
ectional representation of the CMOS inverter, again with the
chematic of the bipolar SCR structure.
•
14105-OO2A
Figure 28
Vcc
Vss
RpSUB
0
ACTIVE DIFFUSION - PTYPE
ACTIVE DIFFUSION - N TYPE
N-WELL
POLYSILICON GATE
METAL INTERCONNECT
CONTACT
PSUB
14105-OO3A
Figure 2b
Publication# 14105 Rev. A
Issue Date: January 1990
Amendment/O
Latchup
5-97
~AMD
Any CMOS diffusion can become part of the parasitic SCR
structure, since all of these parts are interconnected through the
bulk silicon substrate resistance. Other parasitic resistors shown
result from doped regions of the semiconductor. The magnitude
to which the resistors resist current flow depends upon geometric
size and doping level.
As illustrated in Figure 1, the complementary PNP and NPN
transistors are cross-coupled, having common base-collector
regions. The vertical PNP device, M1, has its base composed of
the N-well diffusion while the emitter and collector are formed
from P-type source-drain and substrate regions, respectively.
The lateral bipolar transistor, M2, base is the P substrate with
emitter and collector junctions formed from N-type source-drain
and N-well diffusions, respectively.
Latchup Conditions
Under normal bias conditions the SCR conducts only leakage
current and the SCR structure is in the blocking state. However,
as current flows across any of the parasitic resistors, a voltage
drop is developed, turning on the parasitic bipolar base-emitter
junction. The forward bias condition of this junction allows
collector current to flow in the bipolar transistor. This collector
current flows across the base-emitter resistor of the complementary bipolar transistor, creating a voltage sufficient to turn on the
transistor.
A regenerative loop is now created between the complementary
bipolar transistors such that current conduction becomes selfsustaining. Even after removal of the stimulus that triggered this
action, the current conduction can continue. This region of
operation is a high-current, low-resistance condition characteristic of a four layer PNPN structure. This is referred to as latch up.
Once initiated, the excessive latchup current can permanently
damage an integrated circuit by fusing metal lines or destroying
junctions.
Causes Of Latchup
Latchup may be initiated in numerous ways. Just the critica
causes frequently encountered in a system environment will bE
discussed. These include power up, supply overvoltage, anc
overshoot/undershoot at device pins.
Power-Up
Caution must be exercised when powering up CMOS ICs to avoic
driving device pins before the supply voltage has been applied te
the circuit. Placing a device or board in a "hot socket" will creatE
this situation. When subjected to hot socket insertion, voltagE
conditions at the device pins are uncertain such that the inpu
diodes may be forward biased. Forward biasing the input diode!
with a delayed or uncontrolled application of Vee could cause thE
device to latch up. Advanced Micro Devices' CMOS circuits haVE
substantial immunity to hot-socket power up, but since thi!
condition is uncertain, and difficult to characterize, test, an<
guarantee, it should be avoided.
Supply Overvoltage
Supply levels exceeding the absolute maximum rating can causl
a CMOS circuit to latch up. Elevated supply voltage may causl
internal junctions to break down, producing substrate curren
capable of triggering latch up. Latchup is just one of the reason~
overvoltage should be avoided; other undesirable effects ma;
result from this.
Overshoot/Undershoot
Generally the I/O pins experience the noisiest electrical environ
ment. Fast switching signals with a large capacitive load ma'
overshoot, creating a transient forward bias condition at the 1/(
junction. These junction diodes are illustrated in Figures 3 and ~
Typically this is where latchup is most likely to be induced. Prope
design of the input and output buffers is essential to minimize th
risk of latchup due to overshoot.
Vee
TO INPUT
GATE
P + NWELL DIODE
N + PSUB DIODE
PSUB
Vss
PSUB
14105-OO4A
Figure 3
5-98
14105-005
Figure 4
Latchup
AMD
resting For Latchup
Idvanced Micro Devices characterizes the latchup sensitivity of
s devices before they are released to the market. Testing is done
, such a way as to completely cover every possible latchup
ondition, including Vcc overvoltage, pin overcurrent, and pin
vervoltage.
rcc
Overvoltage Test
·he Vee overvoltage test is applied to all power (Vee) pins. The
3st is performed at the highest guaranteed operating temperaJre of the device. All inputs and I/Os acting as inputs are tied to
round or Vcc depending on the device logic, and outputs and V
)s acting as outputs are floating (open).
ree max is applied to the Vee pin. A positive high voltage pulse
; then applied to the Vee pin and returned to Vee max. The
ccurence of latchup is detected if the voltage across the device
; less than Vcc max, and the current through the device is greater
lan the normal DC operating current.
~
Vce depending on the device logic, and outputs and I/Os acting
as outputs should be floating (open). Vee max is applied to the
Vee pin.
One pin is tested at a time. A three-state output under test should
be disabled. A non-three-state output type under test should be
a logic High when applying a positive current and a logic Low
when applying a negative current. An VO pin should be placed
into the input mode.
A high current pulse is then applied to the pin under test. The
magnitude of the pulse is stepped untillatchup is induced. Both
positive and negative currents are tested. Latchup is observed as
described previously. The sensitivity of the device is the worst
case sensitivity found on any pin of the device.
Pin Overvoltage Test
The pin overvoltage test is performed on current-limited inputs.
Current-limited inputs are inputs which present a resistor-like (or
otherwise "limited") current characteristic for input voltages in the
range (GND - 5 V) < Yin < (Vec + 5 V).
'In Overcurrent Test
·he pin overcurrent test is performed on every output, I/O pin, and
on-current-limited input pin. Non-current-limited inputs are
,puts which present a diode-like (or otherwise "infinite") current
haracteristic for input voltages in the range (GND - 5 V) < Yin <
IIcc +5V).
·he pin overcurrent test is performed at the highest guaranteed
perating temperature of the device. Input pins and I/O pins
.cting as inputs (which are not under test) are tied to ground or
The pin overvoltage test is performed at the highest guaranteed
operating temperature of the device. Input pins and I/O pins
acting as inputs (which are not under test) are tied to ground or
Vcc depending on the device logic, and outputs and VOs acting
as outputs are floating (open). Vee max is applied to the Vee pin.
One pin is tested at a time. Both positive and negative voltage
pulses are applied to the pin under test. latchup is observed as
described previously. The sensitivity of the device is the worstcase sensitivity found on any pin of the device .
Latchup
5-99
~
Converting Bipolar PLD
Designs to CMOS
Advanced
Micro
Devices
Application Note
by Bryon Moyer
The world learned about programmable logic through
the use of bipolar PLDs. As PAL device designs proliferated, bipolar fuse technology was the only productionworthy vehicle for implementing the programming
feature. As CMOS floating-gate technology was
adapted to programmable logic, CMOS has increasingly become the technology of choice for new system
designs. By using CMOS, bipolar speeds can be attained with lower power consumption. Electrical
erasability joins a number of other reasons why designers now prefer CMOS.
Today bipolar PLDs are being purchased largely to supply those designs that were done before CMOS was viable. Many systems makers are now looking for ways to
convert their production systems to CMOS. The intent is
always to have a seamless, "engineeringless" transition, or as close to that as possible. Few companies
have access to the engineers that designed a system
five years earlier. The purpose of this application note is
to discuss issues that may arise when converting a
socket from a bipolar PLD to its CMOS equivalent.
•
Overshoot
•
Ground bounce
In addition, the issue of checksum consistency will be
addressed where there is a chance of the checksum
changing as a result of a conversion.
Table 1. Bipolar/CMOS Direct Equivalents
Bipolar
Device
The conversion issues discussed apply to devices from
any manufacturer; the specific solutions apply primarily
to AMD PAL devices. In particular, this article focuses
on conversion where there is a direct CMOS architecture counterpart to the bipolar device, as shown in
Table 1. For bipolar architectures where an exact
CMOS equivalent is not available, or when using other
CMOS architectures, additional logic design work may
be needed. For more information on the CMOS architectures available, please refer to the application note
Selecting the Correct CMOS PLD.
There are a number of specific areas that need to be discussed for those designs that may have an easy architectural conversion, but more difficult electrical
conversion. They are:
•
Floating unused input pins
•
Edge rates, termination, and layout
5-100
CMOS
Bipolar
Device
PAL16R8
PAL20R8
PAL16L8
PAL20L8
PAL16R4
PAL20R4
PAL16R6
PAL20R6
Equivalent
PAL10L8
PAL12L10
PAL10H8
PAL 14L8
PAL12L6
PALCE16V8
PALCE20V8
PAL16L6
PAL12H6
PAL18L4
PAL14L4
PAL14H4
PAL20L2
PAL22V10
PAL16L2
In theory, when converting from a bipolar device to a
CMOS device, either of the two should work in the socket. In practice this is true for most designs, especially
those that have been well adapted for high-speed signals. Most designs will not require that you take any
special actions. It is only with more sensitive designs
that one may have some applications issues to deal
with.
CMOS
Equivalent
PALCE22V10
PAL20RA10 PALCE20RA10
PAL16H2
Floating Unused Input Pins
No input to a digital device likes to see its value kept at
the threshold voltage for any length of time. These in-·
puts expect a high or low signal level; the input signal
should switch quickly and smoothly from one state to another, passing cleanly through the threshold voltage. If
an input lingers too long at threshold, the input transistors will be in the active region, and, essentially being
high-gain amplifiers, may oscillate as they decide
whether they should be high or low.
On a PAL device, this oscillation will not typically cause
any first-order problems on unused pins. However,
since this oscillation involves the rapid switching of a lot
of current, it could generate internal ground noise, and
affect other internal circuits.
Bipolar devices tend to pull unused input pins to a high
state. Many designers count on this to give their unused
pins a default level, although it is not a recommended
practice. Despite pull-up capability (typically 50 kn 100 kn effective), a standard TTL input will only pull up
to at most a diode drop above threshold, as shown in
Figure 1. In the presence of noise, the input can start to
move across threshold and cause some disturbances.
Publication# 1n64
Rev. A
Issue Date: April 1993
Amendment/O
AMD~
It is therefore always better to tie an unused pin high or
low on the board.
ill
17764A-3
b. No Current If Pull-Up Used
1.4 V --> 2.1 V
S.ov
1n64A-1
Figure 1. A Typical Bipolar Input.
All Voltages Are Nominal.
1n64A-4
When tying a pin high or low, a resistor is not needed.
However, many designers feel safer putting in a currentlimiting resistor to protect the system if there is an accidental short on the pin. In addition, the resistor allows
the pin t() be used later without needing to break the pu 11up or pull-down connection.
It often makes no difference whether an unused input is
tied high or low. However, when using a device with internal pull-up capability, tying high can save some
power. If an input has a pull-up and is tied low, then up to
100 J..lA will be expended through the input. In addition,
care must be taken to make sure that VIL is not exceeded when tying an unused pin low through a resistor.
The external resistor will form a voltage divider with any
on-chip pull-up. With a 50-kn. internal pull-up, a 10-kn.
pull-down will bias the input at 0.8 V (maximum VIL) if
Vee is 5.0 V. This is the maximum pull-down that should
be left intact if the input has a built-in pull-up.
c. Pull-Down Forms a Voltage Divider
Figure 2. External Pull-Up/
Pull-Down Configurations
Traditional CMOS devices have absolutely no pull-up or
pull-down, so the pin is truly floating. Therefore it is completely at the mercy of leakage and noise as it seeks out
some default level. Recent CMOS PAL devices from
AMD have pull-up resistors that provide a default high
level. The input will be pulled to about a diode drop below Vee, giving sufficient noise margin. The minimum
effective pull-up resistance is 50 kQ, so it is still a high
impedance input. Thus it is still a good idea to tie such an
unused pin high for maximum noise immunity. The
equivalent input schematic on the data sheet will indicate whether or not the product has built-in pull-up
resistors.
1n64A-2
a. Current Flows if Pull-Down Used
Converting Bipolar PLD Designs to CMOS
5-101
~
AMD
Typical Input
Typical Output
1n64A-5
Figure 3. Input Pull-Up Resistors as Shown In the Datasheet
This discussion applies primarily to unused input pins.
There actually are three basic kinds of pin on a PLD: input, output, and 110. If an output pin is unused and has
no three-state capability, then the output will be high or
low, and does not need any external pull-up or pulldown. If the pin is an 110 pin, or an output with threestate, then the action taken depends on the default state
of the unused 110 pin. Most software packages configure unused 110 pins as inputs; in this case, the I/O pin
should be treated just like an input. If the I/O pin is configured like an output, then no extra action is needed.
Note that PALASM software normally configures unused I/O pins as inputs; in the case of MACH devices,
however, the software gives the option of configuring
unused 110 pins as outputs instead.
•
If the original design has unused pins tied directly
to Vee or ground, then the new device can simply
be dropped into the old socket.
•
If the original design has unused pins tied high
through a resistor, then the new device can simply
be dropped into the old socket.
•
If the original design has unused input pins tied low
through a pull-down resistor:
-
if the replacement part has no internal pull-up resistors, drop the CMOS part into the socket
if the replacement part has internal pull-up resistors (as indicated in the data sheet), and the
board's pull-down is less than about 10 kn, then
drop the CMOS part into the socket
What To Do
What action you take when converting from bipolar to
CMOS depends on the original design.
5-102
Converting Bipolar PLD Designs to CMOS
AMD~
-
if the replacement part has pull-up resistors (as
indicated in the data sheet), and the board's pulldown resistor is greater than 10 kO, then either
remove the pull-down resistor when using the
new CMOS part or replace it with a smaller resistor.
• . If the original design has unused pins that are
floating, be sure to use one of AMD's newer
CMOS devices that have pull-up resistors built in.
single line may severely impact the DC loading on
the drivers.
•
Too many vias (feedthroughs): each of these is a
discontinuity. While some vias may be necessary
for routing, use as few as possible. Do not route
between an outside layer and an inside layer on
multilayer boards.
•
Headers, sockets, and other components that act
as discontinuities: these should be used as sparingly as pOSSible, since they can cause reflections,
excessive EMI, and add to the inductance of the
line.
•
Poorly decoupled Vee and ground: this can sabotage the best attempts at termination. Good termination relies on a solid ground system, and any
noise being carried on the Vee or ground can
make its way onto signals. It can also make an
otherwise perfect termination ineffective, causing
reflections.
Edge Rates, Termination, and Layout
Sensitivity
Edge rates are important when converting from bipolar
to CMOS. While there are exceptions, CMOS devices
tend to have faster edge rates than their bipolar equivalents. The edge rates determine whether or not a signal
needs termination. The faster the edge rate is, the more
a PCB trace looks like a transmission line, which can
generate reflections that impact system performance.
More information on these issues is available in the Application Note High-Speed Board Design Techniques.
With slow edge rates, long traces can be fabricated with
no need for termination. As edge rates speed up, even
short traces will need termination. There is no standard
cutoff, and the need for termination will depend on many
variables. These include PC board materials, layout, the
number and kind of other components on the line, and
the amount of noise that the design can tolerate. If a design is marginal with respect to edge rate sensitivity,
then any changes in the edge rate of the component in
that socket can affect the behavior of the system.
As an example, the maximum unterminated line length
for a particular trace may be 2"-4" with a 1.5-ns rise-time
device, but 4"-7" with a 3-ns rise-time device. If a particular trace is 5" long, it is within the window for the
slower device, and might work. But this definitely qualifies as marginal. If a replacement device has a 1.5-ns
rise time, then this 5" line is now outside the allowable
window for the faster device, and will require
termination.
Design sensitivity to edge rates is also affected by layout. The following items can contribute to increased
noise in a system, and therefore may make it harder to
replace one device with another that has a faster edge
rate.
•
•
90 0 corners: these are impedance discontinuities.
Use two 45 0 corners instead. The ideal is to have a
rounded corner.
Long unterminated stubs: these can introduce reflections onto a line that may be otherwise terminated at the end. Keep the stubs shorter than the
maximum critical line length. If they must be
longer, then they will have to be individually terminated. Note that multiple DC terminations on a
What To Do
When converting from bipolar devices to CMOS devices
in a given deSign, the following considerations apply,
depending on how the original PAL device output is
terminated.
•
If the original design has parallel-terminated lines,
then conversion should pose no problem.
•
If the original design has series-terminated lines,
then the conversion will likely pose no problems.
Series-terminated lines tend to be a bit more delicate to design; parallel-terminated designs are
generally more robust, but cause greater power
.
dissipation.
.• If the original design has no termination, but the
CMOS device has a slower edge rate than the bipolar device (as in the case of the 1O-ns 22V10, for
example), then the conversion should pose no
problem.
•
If the original design has no termination and the
CMOS device has a faster edge rate than the bipolar device, then your action depends on the length
of the trace. No absolute rule can be given, but the
following rules of thumb should generally be safe:
-
if the line is longer than about 5 inches, add
termination.
-
if the line is shorter than 2 inches, the direct conversion will likely work.
-
if the line is between 2 and 5 inches, try the direct
conversion, but be prepared to add termination if
noise proves to be excessive.
In general, terminate if you feel that it will save you future
headaches.
Converting Bipolar PLD Designs to CMOS
5-103
~AMD
AMO's CMOS PLO Technology. Even in the presence of large amounts of negative overshoot, no
anomalous behavior has been observed in AMD's
CMOS products. Negative overshoot should pose
no conversion problem.
Overshoot
A design that is well terminated will likely have very little
overshoot. As reflections grow, overshoot increases in
both the positive and negative direction (note that
"negative overshoot" is sometimes called "undershoot",
although this is technically a misnomer). The effects of
overshoot on inputs to a PAL device differ depending on
whether it is positive or negative overshoot.
•
Negative overshoot: AMD's CMOS devices on
EE4 technology or later (comprising all of the bipolar-equivalent devices being manufactured today)
are able to clamp negative overshoot effectively.
Details can be found in the Application Note, Inside
•
Positive overshoot: this can be an issue if the
CMOS device used in the replacement has no
positive overshoot filter. Not all PLD manufacturers
use overshoot filters, but all of AMD's bipolarequivalent CMOS devices are being given overshoot filters; with these filters, positive overshoot
will pose no conversion problems. The equivalent
input schematic in the data sheet will indicate
whether or not a device has overshoot filters.
Typical Input
Typical Output
17764A-5
Figure 4. Overshoot Clamping and Filters as Shown in the Datasheet
5-104
Converting Bipolar PLD Designs to CMOS
AMD~
try it, but observe ground and signal conditions
closely to see if any design modifications will be
needed.
Ground Bounce
CMOS devices of any kind have a reputation of causing
more ground bounce than their bipolar counterparts.
While this is changing on AMD's fastest devices, it is
generally true on many devices. The actual amount of
ground bounce encountered will depend on the output
loading and the number of outputs switching. The more
current being switched, whether due to more outputs or
heavier loads, the greater the ground bounce may be.
AMD's newer CMOS devices have a special design that
uses a split leadframe, as conceptualized in Figure 5.
This technique allows for CMOS devices with less
ground bounce than their bipolar equivalents. This
means that faster CMOS devices will be possible without ground bounce making them unusable.
Vee or
Ground Pin
In the last case, design changes may be difficult to accomplish, depending on the amount of ground bounce,
the design flexibility, and the availability of engineering
resources. Such changes will likely require more substantial board changes than a simple conversion would
require, and may not be feasible. If deSign changes are
possible, however, the following are some things to try.
•
Reduce the loading on the outputs.
•
If using DIP packages, switching to PLCC packages instead may help. PLCC packages have
shorter, more uniform, lower-inductance leads, and
offer lower ground bounce.
•
Keep the board-level ground inductance as low as
possible to make sure that board-level ground
bounce does not exacerbate any internal chip
ground bounce.
•
Try to reduce the numberof outputs switching.
This may be difficult in many designs, but a good
candidate for this would be a state machine. If the
existing state bit assignment has transitions that
switch many outputs at once, try redoing the state
bit assignment so that fewer simultaneous transitions occur. Please refer to the Application Note,
Basic Design with PLDs for more information on
tailoring state machines.
•••
Inside
Package
Keeping Consistent Fuse Checksums
Noisy
Line
17764A-6
Figure 5. Conceptualization of Split Vee and
Ground Leads
What To Do
When converting from bipolar to CMOS, the following
ground bounce considerations apply.
•
If the CMOS replacement part has a split
leadframe design (as indicated in the data sheet),
then there will likely be no conversion issue (the
PALCE22V1 OH-7 is presently the best example of
this).
•
If the outputs in the design are lightly loaded, then
there will likely be no conversion issue. While the
amount of loading that can be tolerated will vary
from design to design, outputs with 75-100 pF or
greater should be considered heavily loaded.
•
If the deSign has few outputs switching at a time,
then there will likely be no conversion issue.
•
If many outputs switch at a time, or if the loads are
heavy, the conversion may work just fine anyway;
As shown in Table 1 ,direct bipolar conversions can only
be made between 16XX families and the 16V8; 20XX
families and the 20V8; the bipolar and CMOS 22V10s;
and the bipolar and CMOS 20RA10s. In the last two
cases, the architectures are identical, and there will be
no fuse checksum inconsistencies between the bipolar
and CMOS versions.
Note that there are actually two checksums in a JEDEC
file: the fuse checksum and the transmission checksum.
Only the fuse checksum reflects the array contents specifically, and is usually the only one of interest. Transmission checksum changes will occur if anything at all in
the JEDEC file changes-even a comment; this may not
reflect any functional change to the pattern, and can
generally be ignored. For more information on checksums, please refer to JEDEC Standard 3.
In the case of the 16R8 families and the 20R8 families,
individual bipolar architectures are converted to a single
universal CMOS architecture: the 16V8 and 20V8, respectively. The CMOS devices have extra architecture
bits that determine the macrocell configuration. For example, the 16V8 can be configured differently to emulate a 16R4 or a 16L8 (as well as other arChitectures).
Converting Bipolar PLD Designs to CMOS
5-105
~AMD
Because of this, the CMOS equivalent will generally
have a different fuse checksum from the bipolar original.
If all outputs on a device are used, then converting from
bipolar to CMOS will give a consistent CMOS checksum, regardless of which software performs the conversions (of course, this checksum will be different from the
original bipolar one). However, if some outputs are not
used, then software defaults generally determine how
the unused architecture bits are set. Different software
programs may have different defaults; therefore they
may generate different checksums forthe same design.
Note that it is also possible to perform these conversions
directly through cross-programming with no apparent
change in checksum. However, this is not recommended as a long-term conversion mechanism, since it
makes the production file being used inconsistent with
the original source file. Cross-programming does not
change the source file or the original JEDEC file.
What To Do
To convert designs with unused outputs, the following
procedure is recommended if a consistent checksum is
needed. The solution shown below uses PALASM syntax; similar equations can be specified in any PLD
compiler.
5-106
1. Obtain the original source file. If the original source
file is unavailable, then disassemble the JEDEC
file to obtain a sou rce file.
2. Change the device type in the source file from the
original bipolar device type to the 16V8 or 20V8, as
appropriate.
3. For each unused output, add a "dummy" equation
as follows:
for a combinatorial output, add
= GND
= GND
OUTPUT.TRST
/OUTPUT
for a registered output, add
/ OUTPUT : = GND
4. Recompile the design.
Summary
Converting from bipolar to CMOS PLDs is generally a
painless process. Most designs can convert easily. The
more robust the original design, the easier the conversion will be. For those designs that do not convert as
easily, there are steps that can be taken to make the
conversion successful. These steps can often result in a
design that is cleaner and more robust than the original.
Converting Bipolar PLD Designs to CMOS
High-Speed-Board Design Techniques
Advanced
Micro
Devices
Application Note
INTRODUCTION
The most important factor in the design of many systems today is speed. 25-MHz processors are common;
40- and 50-MHz processors are becoming readily available. The demand for high speed results from: a) the requirement that systems perform complex tasks in a time
frame considered comfortable by humans; and b) the
ability of component manufacturers to produce highspeed devices. An example of a) is the large amount of
information that must be processed to perform even the
most rudimentary computer animation. Currently, Programmable Array Logic (PAL) devices are available with
propagationdelaysof 4.5ns. Whilethismig htseemf ast, itis
notthepropagationdelaythatcreatesthepotentialforproblems,butratherthefastedgeratesneededtoobtainthefast
propagationdelays.lnthefuture, muchfasterdeviceswill
becomeavailable,withcorrespondinglyfasteredgerates.
Designing high-speed systems requires not only fast
components, but also intelligent and careful design. The
analog aspect of the devices is as important as the digital. In high-speed systems, noise generation is a prime
concern. The high frequencies can radiate and cause interference. The corresponding fast edge rates can result in ringing, reflections, and crosstalk. If unchecked,
this noise can seriously degrade system performance.
This application note presents an overview of the deSign
of high-speed systems using a PC-board layout. It
covers:
•
the power distribution system and its effect on boardnoise generation,
•
transmission lines and their associated design rules,
• crosstalk and its elimination, and
II electromagnetic interference.
1. POWER DISTRIBUTION
The most important consideration in high-speed board
design is the power distribution network. For a noisefree board, it is necessary to have a noise-free power
Publication# 16356 Rev. A
Issue Date: February 1993
~
AmendmentiO
distribution network. Note that it is just as important to
develop a clean Vcc as it is to get a clean ground. For AC
purposes, which is what this application note mainly discusses, Vcc is ground.
The power distribution network also must provide a return path for all signals generated or received on the
board. This is often overlooked because the effect of the
return path is less apparent at lower frequencies. Many
designs work even when the nature of the return path is
ignored.
1.1 Power Distribution Network as a
Power Source
1.1.1
The Effect of Impedance
Consider a 5" x 5" board with digital ICs and a power
supply of +5.0 V. The goal is to deliver exactly +5.0 V to
the power pins of every device on the board, regardless
of its position relative to the power source. Furthermore,
the voltage at the pins should be free of line noise ..
A power source with these characteristics would be
schematically represented as an ideal voltage source
(Figure 1a), which has zero impedance. Zero impedance would ensure that the load and source voltages
would be the same. It also would mean that noise signals would be absorbed because the noise generators
have finite source impedance. Unfortunately, this is only
an ideal.
Figure 1b illustrates a real power source with associated
impedances in the form of resistance, inductance, and
capacitance. These are distributed over the power distribution network. Because of the network's impedance,
noise signals can add to the voltage.
The design goal is to reduce the power distribution network impedances as much as possible. There are two
approaches: power buses and power planes. Power
planes generally have better impedance characteristics
than power buses; however, practical considerations
might favor buses.
5-107
~
AMD
Vee
r--------~--_u
V+ ..........................................................................................
Load
a)
Vee
V+
16356A-001A
b)
Figure 1. The Power Source. a) Ideal Representation; b) More Realistic Representation
::::::::::::::{~
t{~ff:'
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tmm
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:.......
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41
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. . .:..: .....
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U8:
....
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11:,","
:9.:.:.:.'.:.••.:.•:.:.:.::.:••:.::.:.
II
b)
a)
16356A-002A
Figure 2. 'Power Distributions System. a) Power Buses; b) Power Planes
1.1.2 Power Buses vs Power Planes
Two power-distribution schemes are shown in Figure 2.
A bus system (Figure 2a) is composed of a group of
traces with the various voltage levels required by the
system devices. For logic, these are typically +5 V and
ground. The number of traces required for each voltage
level varies from system to system. A power-plane sys-
5-108
tern (Figure 2b) is composed of entire layers (or sections
of layers) covered with metal. Each voltage level requires a separate layer. The only gaps in the metal are
those needed for placing pins and signal feed-throughs.
Early designs favored buses because of the expense of
devoting entire levels to power distribution. The power
High-Speed-Board Design Techniques
AMD~
A capacitor, which is ideally represented in Figure 3a, is
more realistically represented by Figure 3b. Resistance
and inductance are the result of the construction of the
plates and the leads necessary to build the capacitor.
Because the parasitic components are effectively in series with the capacitance, they are called equivalent-series resistance (ESR) and equivalent-series inductance
(ESL).
bus shares layers with the signal lines. The bus must
supply power to all devices, while leaving room for the
signal traces; therefore, buses tend to be long, narrow
ribbons. This results in a relatively small cross-sectional
area with a small resistance.
Although the resistance is small, it is significant. Even a
small board can have 20 to 30 devices on it. If each device on a 20-device board sinks 200 rnA, the total current would be 4 A. A bus resistance of only 0.125.Q has a
0.5 V drop. With a 5 V power supply, the last device on
the bus might receive only 4.5 V.
Thus the capacitor is a series resonant circuit for which
fR =
As an example, the 10 JlF capacitors used forthe boardpower connections are typically made with rolls of metal
foils separated by an insulating material (Figure 5). This
results in large ESLs and ESRs. Because of the large
ESLs, fR is generally less than 1 MHz. They are good filters for 60-Hz noise, but not good for the expected
1OO-MHz and higher switching noise.
On a bus, currents are restricted to paths defined by the
bus. Any line noise generated by a high-speed device is
introduced to other devices on that power bus. On the
board in Figure 2a, noise generated by U9 is sent to U7
by the bus.
On the power plane, the noise currents are distributed
because the current path is not restricted. This, along
with lower impedance, makes power planes quieter
than power buses.
The ESL and ESR result from the construction of the capacitor and dielectric material used, ratherthan from capacitance value. The high-frequency reject capabilities
cannot be improved by replacing a capacitor with a
larger one of the same type. The impedance of a large
capacitor is smaller than that of a small capaCitor at frequencies below the fR of the small capacitor. But at frequencies above fR, the ESL dominates and there is no
difference between the impedance of the two capacitors
(Figure 4b). This is because only the capacitance has
changed; unless the construction is changed, the ESL
remains essentially unchanged. To improve high-frequency filtering, one must replace the capacitor with a
type that has a lower ESL.
1.1.3 Line Noise Filtering
The power plane alone does not eliminate line noise.
Since all systems gener~te enough noise to cause problems, regardless of the power distribution scheme, extra
filtering is required. This is done with bypass capacitors.
Generally, a 1 JlFto 10 JlF capacitor is placed across the
power input to the board, and 0.01 JlF to 0.1 JlF capacitors are placed across the power and ground pins of
every active device on the board.
Since the g<;>al is to filter out any AC component on the
power supply, it might seem initially that the largest possible capacitor is the best, minimizing the impedance as
much as possible. However, this does not take into account that real capacitors do not have ideal
characteristics.
.
nc
As shown in Figure 4a, it is capacitive at frequencies below fR, and inductive at frequencies above fRo As as result, the capacitor is more a band-reject filter than a
high-frequency-reject filter.
Because the power plane fills an entire layer, the only
area constraints are the dimensions of the board. The
resistance of a power plane is a small fraction of that of a
power bus supplying the same numberof devices. Thus
a power plane is more likely than a bus to supply full
power to all the devices.
The bypass capacitor acts as a filter. The larger capac itor (== 10 JlF) is placed across the power input of the
board to filter lower frequencies (like the 60-Hz line frequency) that usually are generated off the board. Noise
generated on the board by the active devices have harmonics in the range of 100 MHz and higher. A bypass
capacitor is placed across each chip and generally is
much smaller (== 0.1 JlF) than the capacitor across the
board.
_I_
I
Various types of capacitors are available for specific frequencies and applications. Table 1 gives a small overview of some available device types.
a)
16356A-003A
Figure 3. a) Ideal Representation of a Capacitor
b) Parasitic Components added to Emulate
Real Conditions
High-Speed-Board Design Techniques
5-109
~
AMD
§:
§:
u
u
N
N
FR
FR
(Freq.)
a}
b)
(Freq.)
16356A-004A
.
Figure 4. a} Capacitor Impedance Versus Frequency;
b) the Effect of Lowering Capacitance While Using the Same Type of Construction (Constant ESL)
Metal Foil
Insulation
Metal Foil
16356A-005A
Figure 5. Internal Construction of a
Large (> IlF) Capacitor
The lowest ESL capacitors often are made with non-ferromagnetic materials, which have a low voltage-capacitance product. Thus it is difficult to make large
capacitors with practical breakdown voltages to prevent
board failure. However, because of better filtering characteristics, larger values might not be needed. Figure 6
compares a 0.01 IlF capacitor of type COG (non-ferromagnetic) to a 0.1 IlF capacitor of another type. Note
that the 0.01 IlF capacitor gives better filtering at higher
frequencies.
The capacitor graphs imply that anyone capacitor has a
limited effective frequency operating range. Because
systems have both high- and low-frequency noise, it is
desirable to extend this range. This can be done by putting a high-capacitance, low-ESL device in parallel with
a lower-capacitance, very-Iow-ESL device. Figure 7
shows that this can significantly increase the effective
filtering frequency range.
1.1.4 Bypass Capacitor Placement
After the filter capacitors have been chosen, they must
be placed on the board. Figu re 8a shows the standard
placement for boards with slow device speeds. The capacitor is placed near the top of the device to help ensure its accessibility. While simple for layout, this does
not give the best high-speed performance.
Note that the Vcc capacitor connection is quite close to
the chip's Vec connection, but the ground connection is
far away. Because noise is not uniform on a power
plane, the capacitor is not filtering noise at the chip
leads; it is only filtering noise near the chip.
Table 1. Bypass Capacitor Groups
Type
Range of Interest
Application
Electrolytic
1 IlF to> 20 IlF
Commonly used at power-supply connection
on board.
Glass-Encapsulated Ceramic
0.01 IlF to 0.1 IlF
Used as bypass capacitor at the chip. Also
often placed in parallel with electrolytic to
widen the filter bandwidth and increase the
rejection band.
Ceramic-Chip
0.01 IlF to 0.1 IlF
COG
< 0.1 IlF
Primarily used at the Chip.
Also useful where low profile is important.
Bypass for noise-sensitive devices. Often
used in parallel with another ceramic chip
to increase rejection band.
5-110
High-Speed-Board Design Techniques
AMD~
100.000
10.000
9:
0.01 J.LF
COG
1.000
N
0.100
0.010
0.001
0.1
1.0
10.0
100.0
1K
Frequency (MHz)
16356A-006A
Figure 6. Frequency Response of X7R and COG Type Construction
,,
I
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,
I
,
I
,
o
I
,
x
I
,
I
,
I
I
I
I'"
,
,
Frequency
16356A-007A
Figure 7. Frequency Response of Two Capacitors in Parallel
a)
b)
16356A-008A
Figure 8. a) Typical Placement of Bypass Capacitors;
b) Preferred Placement of Bypass Capacitors
High-Speed-Board Design Techniques
5-111
~
AMD
Better performance can be obtained by ensuring that
the chip and the capacitor contact the Vee and ground
planes at the same point. Because the capacitor size is
different from that of the chip, it is necessary to run two
traces from the Vee and ground plane contact pOints to
the capacitor, as shown in Figure 8b. These "lead extensions" are placed on a non-power plane and should be
kept as short as possible. It is generally best to place the
capacitor on the opposite side of the board, directly under the Chip. A surface-mount chip capacitor works well
here.
Note that the "lead extension" traces from the capaCitor
to the power pins take up space that could have been
used for signal-line routing. However, putting extra effort into routing the signal lines now could prevent much
noise-reduction work later on.
For devices with multiple Vee and ground pins, how best
to bypass depends on the device. In particular, it depends on whether the power pins are connected internally. On some devices, such as the PAL 16R8-4 series,
the ground pins are connected by a common ground
bus. On these devices, it is only necessary to bypass
one ground pin to one Vee pin. If the power is kept separated internally, the separate Vee pins must be
decoupled individually. In general, it is best to contact
the device's manufacturer for specifiC recommendations.
.
1.2 Power Distribution Network as a
Signal Return Path
One of the more surprising functions of the power network is the provision of a return path for all signals in the
system, whether generated on or off the board. Designs
that accommodate this aspect of the power distribution
system eliminate many high-speed noise problems.
1.2.1 The Natural Path of the Signal-Return Line
Of greatest concern in high-speed design is the energy
generated at the signal switching edges. Each time a
signal switches, AC current is generated. Current requires a closed loop. As illustrated schematically in Figures 9a and 9b, the return path needed to complete the
loop can be supplied by the ground or Vee. The loop can
be represented by Figure 9c.
Vee
Signal Current Loop
GND
a)
Vee
Signal Current Loop
GND
b)
Signal Current Loop
ACGND
ACGND
c)
16356A-009A
Figure 9. Current Loop of a Signal on the Board.
a) Through Vee; b) Through Ground; c) The Equivalent AC Path
5-112
High-Speed-Board Design Techniques
AMD~
of least impedance is the path bringing the signal-return
line closest to the signal line. If it can, the signal return
follows the signal line as closely as possible, resulting in
the smallest loop. In multiple layer boards, "as closely as
possible" usually means in a ground or Vcc plane above
or below the signal trace. In a two-layer board, this
means the closest ground or Vcc trace.
1.2.2 Bus vs Planes for a Signal Return Path
16356A-O 1OA
Figure 10. Inductance Increases as the Signal and
Return Path are Separated
Current ioops have inductance and can be thought of as
single-turn coils. They can aggravate ringing, crosstalk,
and radiation. The current-loop inductance and associated problems increase with loop size. Minimizing the
size of the loop minimizes these problems.
AC return signals have an entire plane in which to
choose a path, but they take the path of least impedance
(not necessarily least resistance) to the current. Impedance also includes inductance and capacitance. Metal
has very little resistance; therefore, the impedance is
primarily inductive. Because impedance increases with
inductance, the path of least impedance is the path with
the smallest inductance.
Ifthe signal line goes from A to B on a random path, the
natural return path is not necessarily a straight line, as
would be dictated for least resistance. As noted in Figure 10, the inductance of a signal line and its return line
increases with the separation of the two paths. The path
Return
Signal \.
Plane '"
Figure 2a shows that a power bus has a fixed path. The
return signal must follow this path, whether optimal or
not. Unless the signal lines are purposely laid out near
the power buses and oriented to minimize loop size,
there will probably be large loops. If the layout of a board
using buses for power distribution is not thought out
carefully, it can result in a configuration that generates
much noise.
The power plane imposes no natural restrictions on current flow. Thus the return signal can follow the path of
least impedance, which is the path closest to the signal
line. This results in the smallest possible current loops,
which makes it the preferred solution for high-speed
systems.
Although power planes have an advantage over buses,
the benefits they provide can be defeated by the designer. Any break in the natural path of the return signal
forces it to go around the break, increasing the loop size
(Figure 11). Be careful about cuts in the ground and
power planes.
1.3 Layout Rules With Power
Distribution Considerations
The following layout rules will help you take advantage
of power planes and avoid pitfalls.
Break In
Return Signal
Plane
Current forced around
break, increasin~ L
16356A-011A
Figure 11. The Increase in Loop Size Due to a Break in the Power Plane
High-Speed-Board Design Techniques
5-113
~AMD
a. Be Careful with Feedthroughs
Cuts in the power plane tend to show up at feedthroughs or vias., These are necessary for traces to
cross sides of the board and to connect components
and connectors to the board. They are surrounded by
small gaps where the power planes are etched away to
avoid shorts in the signal lines. If the vias are close and
the etchings wide, they might touch and form a barrier to
any return path. This can occur with backplane connectors and device sockets.
For example, this can occur on the connectors on VME
backplanes. The 104-pin connector has vias that can
block the signal return. All the return signals are forced
to the edge of the board. Not only are the loops longer,
but the edge is shared by all the return signals; as we will
see, this can result in crosstalk (Figure 12).
b. Ground cables Sufficiently
Current loop considerations are also applicable for cables going off the board. Every Signal should be a twowire pair: one for the signal, and one for the return. The
two lines should be kept next to each other to minimize
the loop size. Figures 13a and 13b illustrate poorer configurations. Figure 13c illustrates the proper configuration.
c. Separate Analog and Digital Power Planes
High-speed analog devices tend to be sensitive to digital
noise. For example, amplifiers can amplify switching
noise, making it appear as spikes. Thus on boards with
analog and digital functions, the power planes are commonly separated; the planes are tied together at the
power source. This causes a problem for devices using
both types of signals (such as DACs or voltage comparators). The signal lines must cross the plane boundaries. These boundaries force the return path to the
power source before returning to the driver.
The solution is to place jumpers across the ground
planes where signals cross (Figure 14). The jumper provides a bridge across the break for the return signal; this
helps minimize the current loop.
nal 'A'
Return Path 'A"
nal'S'
Common Return
Path for A and S
16356A-012A
Figure 12. Common Paths of Signal Return Due to Vias
5-114
High-Speed-Board Design Techniques
AMDl1
...:.r--
~
,.,.
-0
~
,.,.
-
"
,.,.
~
-0
~
,.,.
-0
,.,.
~
-0
~
,.,.
~
-0
,.,.
~
~
~
a)
1
~
b)
-
L..-
16356A-O 13A
c)
Figure 13. Connector Configuration. a) Insufficient Grounds; b) Enough Grounds but Grounds lumped
Together Resulting In Larger Current Loops; c) Grounds.Evenly Distributed Among Signal Lines
Digital Ground
Analog Ground
~__---=====--"-/_-IA; Signal
W
Ground Bridge
to Complete
Current Loop
16356A-014A
Figure 14. Jumper Between Analog- and Digital-Power Planes for Signal·Return Path
d. Avoid Overlapping Separated Planes
When separate power-planes are used, do not overlap
the power plane of the digital circuitry and the power
plane of the analog circuitry. The analog and digital
power planes are separated to isolate the currents from
each other. If the planes overlap, there is capacitive coupling, which defeats isolation.
High-Speed-Board Design Techniques
5·115
~AMD
To ensure separation, take a board and cut between the
separated planes. Then inspect the newly-exposed
edges of the board. No metal should be showing, except
where traces or connections are specifically designed to
cross the boundary.
e. Isolate Sensitive Components
Certain devices, such as phase-locked loops, are particularly sensitive to noise interference. They require a
higher degree of isolation.
Good isolation can be achieved by etching a horseshoe
.in the power planes around the device (Figure 15). All
signals used by the device enter and leave through the
narrow gap at the end of the horseshoe. Noise currents
on the power plane must go around the gap and do not
come close to the sensitive part.
When using this technique, ensure that all other signals
are routed away from the isolated section. The noise
signals generated by these lines can cause the interference this technique was designed to avoid.
f. Place Power Buses Near Signal Lines
Sometimes, the designer must use two-layer boards
and is forced to use power buses instead of planes.
Even then it is possible to control loop size by placing the
buses as close as possible to the signal lines. The
ground bus could follow the most sensitive signals on
the other side ofthe board (Figure 16). The loop for that
signal is the same as it would be if the load used power
planes.
2. Signal Lines as Transmission Lines
Controlling the relationship between the signal line and
AC ground takes advantage of the return signal's tendency to take the path of least impedance. Another advantage is the constant impedance along the signal line .
Such signal lines are called controlled-impedance lines,
and they provide the best medium for signal transmission on the board.
GS.-----.. ,/
~
NoiseSensitive
Corresponding {
Signal
Lines
==~~~~~q~~========9
Gap in Power
Planes
Ground
Plane
Device
Isolated
Ground Plane
16356A-015A
Figure 15. Isolation of Noise Sensitive Components
'-------"~. D dl~_gn.
D""@D""'~~' D"":~
:.II!:::
:::
D
Signal Line
:{
DDD
16356A-016A
Figure 16. Providing the Optimum Signal-Return Path with a Bus-Power Distribution System
5-116
High-Speed-Board Design Techniques
AMDl1
However, when the signal delay is greater than a significant portion of the transition time, the signal line must be
treated as a transmission !ine. An improperly terminated
transmission line is subject to reflections, which distort
the signal. The signal at the load end of the line can resemble ringing (Figure 17), slowing down the system. It
can also cause false clocking, destroying system functionality.
A controlled-impedance signal line can be modeled as
shown in Figure 18. Inductance and capacitance are
evenly distributed along the length of the line. Their units
are henrys per unit length and farads per unit length, respectively.
lossless signal line, Zo is an AC resistance; i.e., Zo appears to the driver as a pure resistor. Its units are ohms
(il), and it is equal to
where
Lo = Signal Line Inductance in henrys per unit length
Co = Signal Line Capacitance in farads per unit length
The propagation delay also depends on Lo and Co. It has
units of time per unit length, and it is equal to
tpD
=
YLOCo
From the model, we can derive two important parameters: impedance (Zo), and propagation delay (tpo). On a
o ---- -- -- -- ----- _\ ---- --- --- -- -- --- ---- -- --- --- ----------- a)
16356A-017A
b)
Figure 17. Reflections on a Signal Line. a) at the Driver; b) at the Load
16356A-O 18A
Figure 18. Transmission Line
Transmission Line Categories
Given that the designs discussed in this paper are for
printed circuit boards, the possible types of signal lines
fall into one of two categories: stripline and microstrip
(Figure 19). The stripline has the signal line sandwiched
between two power planes. This technique theoretically
offers the cleanest signals because the signal line is
shielded on both sides. However, the lines are hidden;
there is no easy access to the signal lines. Microstrip
has the signal line on an outer layer. The ground plane is
to one side of the signal line. This technique allows easy
access to the signal line.
High-Speed-Board Design Techniques
5-117
~AMD
Example
The dimensions of the trace and board are restricted by
certain rules. Generally, the vendor sells the board with
1 oz of copper, so the metal thickness is about 1 mil. The
trace width should be between 8 and 15 mils. Signal
lines thinner than 8 mils tend to be harder to control. Signal lines thicker than 15 mils tend to have excess capaCitance. A typical value is 10 mils. The layer
separation is determined by the required board thickness and the number of layers to be used. For this example, 30 mils is adequate.
T
h
~
a)
Based on these assumptions, it is possible to calculate
the parameters for a typical signal line: width = 10 mils,
thickness = 1 mil, separation = 30 mils, and eR =5.
h
~
f5
--rb)
87
In
5 98 * 03
+ 1.41
0.8 * .001 + .01
67.0
16356A-019A
tpD
Figure 19. Signal Line Construction on a Circuit
Board. a) Stripline; b) Microstrip
= 1.017 VO.456 * 5 + 0.67
1000
~
tpD = 1.
Co
4h
0.67nw (0.8 + ~)
n
w
o17Un ns / It
1000 tpD pF/ft
Zo
LO =
2
ZoCo pH/ft
*~
67.05
pF/ f t
26.1 pF/ft
LO
For Stripline
ns/ft
1.75 n
The parameters Co, Lo, Zo, and tPD can be determined
from the physical dimensions of the signal line and the
dielectric properties of the board material. They are discussed below.
Zo = ~ In
67.05
2
*
26.1 pH/ft
117 nH/ft
Distributed Load Calculations
The calculations above are for a signal line with a
lumped load at the end of the trace (Figure 20). If the
load is distributed along the signal line (Figure 21), the
capacitance of the load devices is also distributed along
the line and adds to the line capacitance. This changes
the signal-line parameters Zo and tPD. The new parameters are derived from the original values based on the
added capacitance, el, in farads per unit length:
For Microstrip
5.98h
In
0.8w
+
tpD = 1.017 VO.457eR+ 0.67
~1
t
ns/ft
+ cL
Co
Co
1000 tpD pF/ft
Zo
2
LO =
Zo
.
Co pHI ft
eR is the relative dielectric constant of the board material. A common material is epoxy-laminated fiberglass,
which has an average eR of 5.
5-118
n
High-Speed-Board Design Techniques
ns/ft
AMD~
16356A·020A
Figure 20. Transmission Line with a Lumped Load
Figure 21. Transmission Line with a Distributed Load
Distributed loading is common in memory banks. The input capacitance on these devices can range from 4 pF to
12 pF. The following example uses 5 pF. The physical
size of memory devices usually permits placing two of
them per inch. The distributed added capacitance is
then:
C = _ _--...:.5--=-p_F _ _
L
0.5 in *~
12 in
120 pF/ft
The new values of Zo and tPD, based on distributed
loading, are:
67 05 n
_ / 1 + 12 0 pF / f t
26.1 pF/ft
'V
28.34
n
tpD = 1.75 ns/ft
*
.v
1
+
120 pF/ft
26.1 pF/ ft
4.14 ns/ft
With this distributed load, the impedance has been
greatly reduced, and the signal is now much slower.
Reflections
The source generates a signal with an energy content
determined by Zo n. Even though the line is seen as a
resistance, the signal line does not dissipate energy.
The energy in the Signal must be dissipated by the load
impedance (ZL), as shown in Figure 20.
The maximum transfer of energy from source to load requires that the load impedance equal the source impedance. For the entire Signal to be transferred to ZL, ZL
must equal Zoo If they are not equal, some of the signal
energy is dissipated, and the rest is reflected back toward the source. The source generator output then adjusts to compensate for the "new" load.
The waveform of the signal at the load can be thought of
as the sum of the originally generated signal and the reflection from the load. The appearance of the waveform
depends on the mismatch of the load and line impedances and the ratio of the signal-transition time (tR) to
the propagation delay of the line (t), tR/t. If the transition
time is significantly longer than the propagation delay of
the line, the reflection reaches the source when the
original signal has changed only a small amount. The
generator compensates for the "new" load and transmits
the corrected signal with little signal disturbance. The
signal at the load then has a small overshoot.
If the propagation delay of the line is long enough for the
reflection to reach the source after the signal has
changed a significant percentage, the generator must
change significantly to compensate for the load. The
load reflects the new transition, which results in the ringing shown in Figure 17.
The amount of overshoot usually varies proportionally
with the signal-line length until the signal-line delay is
equal to the transition time. At this point, the overshoot
can be as much as the original transition, effectively
doubling the swing of the transition.
A signal line long enough to produce significant reflections acts like a transmission line. The point at which the
signal line is considered a transmission line depends on
the amount of tolerable distortion. A liberal rule of thumb
is to consider a signal line a transmission line when the
transition time of the original signal is less than four
times the propagation delay of the signal (Figure 22);
that is, when tAlt ~ 4.
Hlgh-Speed-Board Design Techniques
5-119
~
AMD
Original Signal
at Source
t
I+--+t--
t < --E
4
Signal
at Load
16356A-022A
Figure 22. Minimum Delay Between Original and Reflected Signal Which
Results in a Transmission LIne
A more conservative rule is to consider the signal line a
transmission line when tN't is less than eight times the
propagation delay. Generally, the larger the transition
time is in relation to the propagation delay of the signal
line, the cleaner the resultant signal.
For older devices with 5 ns transition times, signal lines
shorter than 8.6" do not have to be treated as transmission lines. For newer, high-speed devices, even a twoinch line is a transmission line. Practically all signal lines
are transmission lines on boards with high-speed devices.
From this it is possible to determine what length of the
microstrip line discussed above must be treated as a
transmission line. On available devices, tR ranges from
5 ns (especially those using bipolar technology) to 1 ns
(newer bipolar and CMOS devices). The rise times and
corresponding signal-line lengths are shown in Table 2
for the example given above.
If the transmission line has the distributed load in the example above, then the minimum transmission-line
length must be reconsidered. As shown in Table 3, a
four-inch line is a transmission line when tR = 5 ns. If
tR =1 ns, a signal line smaller than one inch is a transmission line.
Table 2
Example:tR and Corresponding Transmission-Line
Length for tR = 4
Table 3
Example: tR and Corresponding Transmission-Line
Length with Lumped and Distributed Loads
for
't'
5-120
tR (ns)
5
Line Length (inch)
8.6 .
4
6.9
5.1
3
2
3.4
1
1.7
..!B
=
4
l'
tR (ns)
5
3
2
1
Line Length (inch)
Lumped Load
Distributed Load
8.6
3.6
5.1
2.17
3.4
1.4
0.75
1.7
High-Speed-Board Design Techniques
AMDl1
Quantifying Reflections
Given that the signal line is long enough to be considered a transmission line, the size of the reflected signal
depends on the difference between Zo and ZL The numerical indicator of the percentage, orthe original signal
that is reflected, is called the reflection coefficient (KR).
KR is equal to:
The input impedance of the load is greater than 100 kn.
This is so much greater than Zo (67 0), that KR at the
load is practically equal to one. KR at the source is:
K
8.3 - 67
8.3 + 67
R -
= -0.78
The percentage of the original signal reflected
back is 100 * KR.
Referring back to the open load:
The driver generates a signal switching from 3.5 V to 0.2
V. Since the driver-output impedance and ZO make up a
voltage divider, the generated signal is:
Zo
00
-
00
+ Zo
Ll v =
KR = - - -
Zo
1
=
=
oo+
3. 5 V)
+
Zo
---
=
Zo
2.84
Zo
Zs
(0.2 V - 3.5 V)
50 + 8
For an shorted load:
KR
(0. 2 V -
50
v
The resultant Signal at the source is:
Vs =
.-1
Foropen and shorted loads, the entire signal is reflected
without attenuation .. KR is negative for the shorted load.
This indicates that the reflected signal is inverted from
the original.
With a printed-circuit board, it is possible to estimate the
expected type of mismatch. Zo typically ranges from 30
n to 150 o. Input impedances range from 10 kO (for bipolar devices) to over 100 kO (for CMOS devices). Output impedances can be very low. A CMOS PAL device,
such as the PALCE16V8, has a typical-output LOW voltage of 0.2 Vat 24 rnA for about 8 o. The output-HIGH
impedance is about 50 0, which is closer to the expected Zoo
Consider the microstrip line derived earlier, with a
CMOS device as its load. The following discussion
shows what happens on the HIGH to LOW transition.
The driver's output impedance (Zs) is:
3.5 V - Llv
=
3.5 V - 2.84 V
= .066 v
When the signal reaches the load, VL changes by
-2.84 V from the original transmission and a further
-2.84 V from the reflection. Since VL originally was 3.5
V, it is now -2.19 V.
At the start, Vs = 0.66 V. The reflected signal returns to
the source. Some of it is reflected perthe source KR. VS
is equal to the sum of the original signal, the reflected
signal, and the second reflected signal. The second reflection is equal to:
vR = -.78 * -2.84
2.21 V
vs= 0.66 v+ -2.84 v+ 2.21
-0.035
V
v
The second reflection goes to the load. When it arrives,
vL = -2.19 + 2.21
+ 2.21
= 2.24
=~"'8.3Q.
24 rnA
A more accurate numbercan be obtained from an actual
IN curve of the output.
The signal continues like this, bouncing back and forth,
getting smaller each time. This is illustrated in the lattice
diagram in Figure 23. The lines at the left and right are
the voltage at the source and load, respectively. The angled lines show the value of the transmitted signal and
the reflections.
Hlgh-Speed-Board Design Techniques
5-121
~AMD
Vs
O.66V
-2.19V
-O.04V
Time
I
2.24V
O.59V
-1.21 V
O.26V
1.5
16356A-023A
Figure 23. Lattice Diagram Representation of a Reflected Signal
The same information in the time domain is shown in
Figure 24. The top part of the Figure shows the source;
the bottom shows the load signal. Note that it takes five
complete cycles forthe signal strength to drop below the
input threshold. Propagation delays are typically frolll
2 nslft to 5 nslft. With tPD = 3 nslft and a 6-inch line, the
delay across the line is about 1.5 ns. The signal can be
safely considered valid at about 13.5 ns after the original
transition.
To understand this, look at the nature of the input and
output impedances of the PAL devices. As noted above,
input impedances tend to be high. Bipolar is in the 10 kn
range, while CMOS is in the 100 kQ range. Output drivers tend to have low impedance.
would be too much for most systems. A technique is
There are two schemes for termination: reduce ZL to Zo
to eliminate load reflections, or increase Zs to Zo to eliminate secondary reflections at the source. ZL can be reduced by placing a resistor in parallel with the
load-parallel termination; Zs can be increased by placing a resistor in series with the source and the line-series termination.
needed to eliminated, or at least reduce, the reflections.
Since the reflections are eliminated when ZL = Zo, it is
necessary to change ZL to equal Zoo
Parallel termination is shown in Figure 25a. Because of
the extremely high input resistance of most devices, RL
can be made equal to Zoo
TERMINATION
The amount of reflections shown in the last example
5-122
High-Speed-Board Design Techniques
AMD~
3
~
n;
2
c:
.!2l
C/)
~
:J
o
o
C/)
-1
Time (Unit Delay)
a)
-
3
~
n;
2·
Input
---- -- ---- ------- --- ----- ------ ------- ---- ------ -----r------,---- -.,------- --------- -- Threshold
c:
CI
U5
"0
n:l
.9
0
-1 .
I
I
I
I
I
I
I
2t
4t
6t
8t
lOt
J
I
II
I
I
12t
-2
16356A-024A
Time (Unit Delay)
b)
Figure 24_ Time Representation of a Reflected Signal; a) at the Source b) at the Load
Vee
a)
b)
Zs
RT
~
Dnver
I
Zo
c)
d)
e)
16356A-025A
Figure 25. a) Parallel Termination; b) Thevenin Equivalent;
c) Active Termination; d) Series Capacitor; e) Series Termination
High-Speed-Board Design Techniques
5-123
~
AMD
This scheme has one disadvantage: the current drain is
high forthe HIGH-output state. For a 50-0 termination, it
can be as much as 48 rnA. Most drivers are rated for an
IOH of 3.2 rnA. This is clearly above the level that the device can support and still maintain an adequate VOH.
Terminating to Vcc can help, since IOL is usually higher
than IOH. However, most CMOS devices designed for
board-level applications have drivers rated for an IOL of
24 rnA or less. This is still below the level that can support and maintain an adequate VOL for a low-impedance
transmission line.
RL = Zoo This half-transition tracks down the transmission line until it is reflected at the load, which is unterminated. Since the reflection causes the original
half-transition to double, it brings the signal at the load to
its final value (Figure 27a). The reflection then travels
back up the line, completing the transition all along the
line (Figure 27b).
The current can be reduced considerably by using two
resisters, as shown in Figure 25b. The resistors form a
voltage divider with the Theveninvoltage equal to:
Vs
a)
_ ~"'------"'vee * R2
Rl + R2
V TH -
The Thevenin resistance is equal to:
_ Rl
*
R2
Rl
+
R2
RTH -
--=.._----!e.
Although this is a good solution, there is higher powersupply current because the resistors are between Vee
and ground.
Another approach to reducing load current is to reference the resistor to a positive voltage between VOH and
VOL (Figure 25c). The current flow from 3 V to 2.5 V
through a 50-0 resistor is considerably less than the
flow from 3 V to ground through the same resistor. This
does not present any signal problems, because the DC
voltage reference is AC ground. However, it is difficult to
find a terminating voltage source that can switch from
sinking current to sourcing current fast enough to respond to the transitions.
Another technique is to replace the original terminating
resistor with a resistor and capacitor series-RC network
(Figure 25d). The resistor is equal to Zoo The capacitor
can be on the order of 100 pF; the exact value is not important. At these frequencies, the capacitor is an AC
short but it blocks DC. Thus the driver does not see the
DC loading effect of RL. This technique is referred to as
AC termination.
,-
b)
Figure 26. a) Series Termination;
b) Voltage Divider formed by Series Termination
This can be illustrated by putting a series terminating resistor on the unterminated microstrip example considered earlier. A 59-0 resistor (6S0 - 90) is placed in
series with the driver. For a LOW to HIGH transition, the
signal at the source is:
~V
= (0.2 v - 3.5 V)
Zs + Zo + 59 0
(0 . 2
8 Q
v +
3. 5 V)
67 Q
+
Zo
*
67 Q
59 Q
-1. 65 V
Vs = 3.5 v
+
3.5 V -
~v
1. 65 V
Techniques that terminate at the load are designed to
eliminate the first reflection. An alternate approach is to
increase Zs to equal Zo by placing a resistor in series
with the source (Figure 25e). When added to Zs, this resistor makes the new source impedance look like Zoo
1. 85 V
If the load is effectively an open circuit, then a -1.65 V
reflection returns. When the reflected signal reaches the
source, no new reflections occur because Zs is matched
to Zo by RT. Vs is 1.85 V - 1.65 V = 0.2 V.
This type of termination works best with a lumped load
because the voltage divider formed by the Zs and Zo attenuates the signal (Figure 26 a and b). The original
transition is cut in half by this voltage divider, since Zs +
The reflection at the load causes VL to equal 0.2 V when
the original signal arrives. Vs does not equal 0.2 V until
the reflected signal returns, in this example, 3 ns later
(Figure 27).
5-124
High-Speed-Board Design Techniques
AMD~
3
2
o
o
1'[
Time (Unit Delay)
a)
3
2
o
I
I
o
1'[
Time (Unit Delay)
.
2'[
16356A-027A
b)
Figure 27. a) Signal at Source; b) Signal at Load end
This can be a risky approach if the load is distributed
along the line, since those loads not at the end of the line
will see some intermediate voltage until the reflection
cleans them up on its return to the source. In addition,
this technique adds the delay of the return trip because
the signal cannot be considered valid until the device
closest to the driver has a valid input. The input to the
device closest to the driver becomes valid upon the re- ,
turn of the reflection. The delay is longer than indicated
in the last example because the added capacitance of
the distributed load reduces Zo and increases tPD.
Despite this drawback, series termination is successfully used with DRAM drivers, even when the DRAMs
are distributed along the signal line. The risk of the signal spending time near threshold and the extra delay are
reduced by choosing RT so that the resultant Zs is
slightly less than Zoo The voltage swing at the line is
larger, and the voltage level is closer to VOL, below the
input threshold. If the line is terminated with 20 n, Vs
becomes:
Vs
=
=
3.5 V
(0.2 v - 3.5 V)' Zo
+ --------~
Zs + Zo + 20
3.5 V + (0.2 V - 3.5 V) * 67
8
+ 67
+ 20
n
=
n
n
n
Because the termination is not an exact match, some
ringing occurs. However, if the ringing is below a tolerable level, it can be used successfully. The designer
must decide on the compromise. Furthermore, the high
capacitance of memory lines often swamps out the
ringing.
Often, an exact match is not possible because of the differences between the HIGH- and LOW-output impedances. The output impedance of TTL-compatible
devices is different for HIGH and LOW levels. For example, the PALCE16V8 is 8 n when LOW, and about 50 n
when HIGH. This complicates the choice of a terminating resistor because no single value is ideal for both
cases. A compromise value must be chosen that results
in acceptable results in both transition directions.
Layout Rules for Transmission Lines
The controlled impedance signal line is the best practical medium for signal transfer on a board, and proper
termination helps ensure proper noise-free operation.
However, it is still possible to generate noise with an inefficient layout. The following layout rules further enhance board operation.
n
1.17 V
High-Speed-Board Design Techniques
5-125
~
AMD
1. Avoid Discontinuities
Discontinuities are pOints where the impedance of the
signal line changes abruptly; they cause reflections. The
formula for KR is as valid here as it as at the end of the
line. Because they cause reflections, they should be
avoided. Discontinuities can be at sharp bends on the
trace or at vias through the board.
At bends on the trace, the cross-sectional area increases, and Zo decreases. It is possible to compensate
for the bend by cutting the trace as shown in Figure 28.
The cut is chosen so that the resulting diagonal is equal
to the trace width. This minimizes the delta in cross-sec-
tional area, as well as the discontinuity. Using two 45°.
bends makes use of the same concept and is a common
way of smoothing out bends. A smooth circular arc
would be ideal but is harderto generate with many tools.
Vias take signals through the board to the other side
(Figure 29). The vertical run of metal between layers is
an uncontrolled impedance, and the more of these there
are, the greater is the overall amount of uncontrolled impedance in the line. This contributes to reflections. Also,
the 90° bend from horizontal to vertical is a discontinuity
that generates reflections. If vias cannot be avoided,
use as few as possible.
w
a)
b)
w
w
w
w
c)
d}
16356A-028A
Figure 28. Reducing Discontinuity. a) Corner on PC Board Trace which Causes Discontinuity; Solved:
b) by Shaving the Edge; c) by 45° Corner; d) by Using Curves
5-126
High-Speed-Board Design Techniques
AMD~
Uncontrolled
Impedance
I.-------------------x--------------------·~I
a)
T
1
16356A-029A
b)
Figure 29. a) Excessive Number of Vias; b) Preferred Solution
Note that changing from an outer layer to an inside layer
(or vice versa) generates an impedance change, since
the design effectively is changed from stripline to microstrip (or vice versa). While it is theoretically possible to
change geometries to compensate and keep impedances the same, it is very difficult to do so in production.
The best results are obtained if outside signals remain
outside, and inside signals remain inside.
2. Do Not Use Stubs or Ts
When laying out the signal lines, it is often convenient to
run stubs or Ts to the devices, similar to Figure 30a.
Stubs and Ts can be noise sources. If long enough, they
are transmission lines with the main line as the source
and are subject to the same type of reflections.
The signal lines should avoid long stubs and Ts. As long
as the stubs are very short, a single line can be used with
a single termination at the end, although Zo must then be
derated to account forthe distributed load. Given the example in Figure 30a, if the stubs are too long, the Signal
line could be made into two signal lines, as shown in Figure 30b. Both are transmission lines and require terminating; however, this is preferable to terminating each
long stub individually.
High-Speed-Board Design Techniques
5-127
~AMD
y 1 Y1 Y1 Y11
I
1 Y1 Y
a)
<
0
0
0
0
0
0
0
0
0
0
0
,0
b)
:
16356A-030A
Figure 30. a) Stubs off of Transmission Line; b) Preferred Solution
Noise Source
[>~~--"I---[>-
C Tracc
Noise Receiver
a)
Noise Source
Trace
~
Noise Receiver
t----O Trace
c)
b)
16356A-031A
Figure 31. a) Capacitive Crosstalk; b) Equivalent Circuit; c) Solution
3. Crosstalk
Crosstalk is the unwanted coupling of signals between
traces. It is either capacitive or inductive. Crosstalk can
be handled effectively by following a few simple rules.
3.1 Capacitive Crosstalk
-Capacitive crosstalk refers to the capacitive coupling of
signals between Signal lines. It occurs when the lines
are close to each other for some distance.
5-128
The circuit representation in Figure 31 shows two Signal
lines, called the noise source and the noise receiver. Because of capacitance between the lines, noise on the
source can be coupled onto the receiving line. This occurs in the form of current injected into the receiving line.
In a transmission line, the current sees Zo in both directions, and propagates both ways, until it can be dissipated across the source and load. The voltage spike this
causes on the line is determined by Zoo When the current
High·Speed-Board Design Techniques
AMD~
pulse gets to Zs and ZL, it dissipates across these resistors with a voltage proportional to the impedance. If
there is an impedance mismatch at the source or load,
reflections occur. In the case of an unterminated load,
the voltage spike across ZL can be very large. Terminating the load can significantly reduce the voltage noise
seen at the input of the next device.
Capacitive crosstalk can also be reduced by separating
the traces. The farther apart the signal traces are, the
less the capacitance, and the smaller the crosstalk.
Space constraints on the board may put limits on how far
apart the signal lines can be placed. An alternate approach is to put a ground trace between adjacent-signal
lines, as shown in Figure 32. The signal is now coupled
to ground, not to the adjacent-signal line.
Note that the ground trace must be a solid ground. If it is
only connected to the ground plane at the trace ends,
the trace has a relatively high impedance. For good
grounding, the ground trace should be connected to the
ground plane with taps separated a quarter wavelength
(A/4) of the highest frequency component of the signal.
16356A-032A
Figure 32. Isolating Traces with a Ground Trace
The wavelength is the distance the signal travels in a
single period or:
It
=
vel
*
Perio'd
=_1
* __
1_
tpD
freq
With digital signals, the highest significant frequency
harmonic of interest is usually assumed to be 1httR.
Consider an example where tR = 1.25 ns (possible for
PAL 16R8-4 devices). The upper-frequency component
is:
f MAX = _ _~1,---_ _
l.25 ns
* n
255 MHz
The distributed load delay for our example in section 2'
was 4.14 ns/ft. A. is equal to the period divided by tPD.
It =
1
255 MHz
* _--=1"---_ *
12 in
4.14...Qg
ft
ft
1l. 4 in
1t/4 =~
4
= 2.8 in
3.2 Inductive Crosstalk
Inductive crosstalk can be thought of as the coupling of
signals between the primary and secondary coils of an
unwanted transformer (Figure 33). The transformer
windings are the current loops on the board (or system).
These can be either artificial loops inadvertently created
by inefficient layout (Figure 34a) or natural loops resulting from the combination of the signal path and the signal return path (Figure 34b). Artificial loops are
sometimes hard to locate, but can be eliminated as
shown in Figure 34c.
The amount of unwanted signal coupled to the load depends on the proximity and size of the loops, as well as
the impedance of the affected load. The amount of energy transferred increases as the loops become larger
and get closer together. The size of the signal seen at
the load, on the secondary loop, increases with the load
impedance.
3.2.1
Loop Size and Proximity
The inductance of a loop (L) increases with loop size.
When two loops interact, one will have a primary inductance (LP) and the other will have a secondary inductance (LS), as shown in Figure 33b. Because the signal
lines are not purposely designed to be transformers, the
coupling is loose; however, it can create interference on
the secondary loop.
For maximum isolation, the ground trace must have
taps to the ground plane no more than 2.8 inches apart.
High-Speed-Board Design Techniques
5-129
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16356A-033A
b)
a)
Figure 33. a) Inductive Crosstalk; b) Transformer Equivalent
C?(
......... , It;>
~, ,
~
,,
'
''
,,
C?: :
,
I
I
~ (,-,' ~
a)
,.
I
~ 11:;>
',_/) ~
c)
b)
16356A-034A
Figure 34. a) Artificial Loops; b) Schematic Equivalent; c) Solution
16356A-035A
a)
b)
c)
Figure 35. a) Common Return Path; b) Loop; c) Autotransformer Equivalent Circuit
If portions of the return paths of two signal lines coincide,
the resulting loops might form an auto-transformer (Figure 35 a and c). An example of this is the VME-backplane example discussed above. Ensuring that each
signal has its own return path can eliminate this source
of crosstalk.
3.2.2 Load Impedance
If inductive crosstalk comes about due to artificial loops,
the solution is to open the loops. Unfortunately, locating
the loops can often be a challenge. If the crosstalk is
generated by natural signal/return-signal loops, then
5-130
clearly the loop cannot broken. But by keeping the load
impedance low, the effect of the crosstalk can be minimized. Figure 36 shows a simplified schematic representation of a secondary "natural" loop with a load. Here
Zs is the intrinsic impedance of the secondary loop. Note
the series current (is). Because the impedances are in
series, is is the same everywhere in the loop. With a constant is, the voltage drop is largest across the largest impedance. On an unterminated line, this usually is the
load at the end of the line; i.e., at the input of the receiving device.
Hlgh-Speed-Board Design Techniques
AMD~
Zs
4.1 Loops
Signal Line
fg--r--i-S "M..------='-----1
§
Ground Return Path
f
Current loops are an unavoidable part of every design.
RIN = 10 ill to 100 kn They act as antennae. Minimizingthe effects of loops on
or greater
16356A-036A
Figure 36. Series Inductive Loop
Large noise signals are most unwanted at the inputs,
where noise signals should be minimaL If the maximum
signal is developed across the largest impedance, the
signal developed at the input can be reduced by terminating the signal line at the receiver end, which reduces
RIN to RT.
RT is usually in the 30 .n to 150 .n range. This reduction
in RIN is at least two orders of magnitude. The voltage
drop across RIN is reduced accordingly. The exact drop
is difficult to predict because it depends on the value of
Zs , which is difficult to determine. But reducing RIN by
orders of magnitude should have a significant effect.
3.3 Crosstalk Solutions Summary
The following steps summarize the ways in which the effects of crosstalk can be minimized.
1. The effect of both capacitive and inductive crosstalk
increases with load impedance. Thus all lines susceptible to interference due to crosstalk should be
terminated at the line impedance.
2.. Keeping the signal lines separated reduces the energy that can be capacitively coupled between signal
lines.
3. Capacitive coupling can be reduced by separating
the signal lines by a ground line. To be effective, the
ground trace should be connected to the ground
plane every Al4 inches.
4. For inductive crosstalk, the loop size should be reduced as much as possible. Where possible, loops
should be eliminated.
5. For inductive crosstalk, avoid situations where signal
return lines share a common path.
4. ELECTRO-MAGNETIC INTERFERENCE
(EMI) .
EMI is becoming more critical with speed. High-speed
devices are naturally more susceptible to interference.
They accept fast glitches, which slower devices ignore.
Even if the board or system is not susceptible, the FCC
in the United States, along with VDE and CCITT in
Europe, places severe limitations on the high-frequency
noise (both radiated and line noise) that the board can
generate.
The designer can reduce EMI through shielding, filtering, eliminating current loops, and reducing device
speed where possible. Although shielding is outside the
scope of this article, all the other issues are discussed
as follows.
EMI means minimizing the number of loops and the antenna efficiency of the loops. Do not create artificial
loops; and keep the natural loops as small as possible.
1. Avoid artificial loops by ensuring that each signal line
has only one path between any two points.
2. Use power planes whenever possible. Ground
planes automatically result in the smallest natural
current loop. When using ground planes, ensure that
the signal-return line path is not blocked.
If power buses are necessary, have the fast-signal
lines run either over or next to a power bus.
4.2 Filtering
Filtering is standard for power lines. It can also be used
on signal lines, but is recommended only as a last resort,
when the source of the signal noise cannot be
eliminated.
Three options are available for filtering: bypass capacitors, EMI filters, and ferrite beads. Bypass capacitors
are discussed in section 1. EMI filters are commercially
available filters; they are available over a wide frequency range. Ferrite beads are ferrite ceramics that
add inductance to any wire within their proximity. They
are used as high-frequency suppressors.
4.2.1 EMf Filters
EMI filters are commercially manufactured devices designed to attenuate high-frequency noise. They are
used primarily to filter out noise in power lines. They act
to isolate the power outside the system (referred to as
the line) from the power inside the system (referred to as
the load). Their effect is bi-directional: they filter out
noise going into, and coming out of, the device or board.
EMI filters consist of combinations of inductors and capacitors. In general, the configuration to use depends on
the impedance of the nodes to be connected. A capacitor should be connected to a high-impedance node; an
inductor should be connected to a low-impedance node.
EM I filters are available in variations of the following
configurations: feedthrough capacitor, L-Circuit, PI-Circuit, and T-Circuit.
•
•
The feedthrough capacitor's only component is a capacitor (Figure 37a). It is a good choice when the impedances connected to the filter are high. Note that it
provides no high-frequency current isolation between nodes.
The L-Circuit has an inductoron one side of a capacitance (Figure 37b). It works best when the line and
load have a large difference in impedance. The inductive element is connected to the lowest
impedance.
High-Speed-Board Design Techniques
5-131
~AMD
•
The PI-Circuit has an inductor surrounded by two capacitors (Figure 37c). PI filters are best when the line
and load impedances are high and when high levels
of attenuation are needed.
• The T-filter has inductors on either side of the capacitor in a T fashion (Figure 37d). It is a good choice
when both line and load impedances are low.
LC filters are rated according to insertion loss, which is
the amount of signal lost due to the insertion of the filter.
Insertion loss is usually stated in decibels. Filter manu"-~r--",,,
0
I
facturers provide graphs of their filters over prescribed
frequency ranges.
4.2.2 Ferrite Noise Suppressors
Ferrite noise suppressors are ferrite ceramics placed in
proximity to the conducting material. They are available
as beads for single wires and clamps for cables. When
using beads, the wire is placed through a hole in the
bead (Figure 38a). When using clamps, the ferrite material is clamped around the cable (Figure 38b). Clamps
are popular with ribbon cable.
0
b)
a)
0
I
ml5'
I
~
0
I
d)
c)
16356A-037A
Figure 37. LIne-Noise Filters. a) Capacitor; b) LC Filter; c) PI Filter; d) T Filter
a)
b)
Figure 38. a) Ferrite Bead; b) Ferrite Clamp
5-132
High-Speed-Board Design Techniques
AMD~
Ferrite suppressors work by adding inductance in series
with the line (Figure 39). Ferrite manufactures supply
graphs similar to those in Figure 40, which shows the
added impedance as a function of frequency. The system designer must determine the insertion loss. The formula is:
where Zs = Source Impedance
ZL = Load Impedance
ZF = Ferrite Impedance
Figure 39. Ferrite Filter Equivalent Circuit
1000
9:
CD
100
u
c:
CIl
"0
CD
a.
.§
10
1
1M
10M
100M
Frequency (Hz)
1G
16356A·040A
Figure 40. Frequency Response of Ferrite Filter
Ferrite suppressors add inductance to the line without
adding DC resistance. This makes an ideal choice for
line-noise suppressors on the Vcc pins of devices.
Because ferrite beads are small and easy to handle,
they can sometimes be used in signal lines to suppress
high-frequency noise signals. This is not recommended
for two reasons: first, it masks the cause of most problems; second because it might affect the edge rates of
the signal. However, when the board is already laid out,
ferrite beads can be used on noisy signal lines as a last
resort.-
4.3 Device Speed
Faster devices, by definition, have shorter transition
times. Because shorter transition times have more energy in the high-frequency range, faster devices can
generate more high-frequency noise.
Figure 41 a is an outline of the Fou rier transform of a
square wave (Figure 41 b). There are two corners of interest: 1IntL(this frequency is determined by the period
of the signal) and 1/ntf (determined by the transition time
of the signal; this is also the frequency we used in determining the wavelength in the discussion on capacitive
coupling). After 1/ntf, the curve drops off very rapidly.
For practical purposes, 1/7ttf is the highest significant
frequency component of the signal.
The less energy a device generates in a given frequency
range, the less noise can be radiated in that range.
Hlgh-Speed-Board Design Techniques
5-133
~
AMD
a)
1
1ttL
1
1
: 1ttR or 1ttF
,,
b)
Figure 41. a) Single Pulse; b) Fourier Transform of Pulse
For example, the PAL 16R8-4 series has a typicaltransition time of 2 ns. It can be as short as 1.25 ns. The frequency component of the edge is:
f
= _ _~1L-_ _
1t * 1.25 ns
254 MHz
The output signal has a high-frequency component of
254 MHz, regardless of the clock frequency.
Because of the high-frequency component, the board
might require extra filtering and possibly shielding in order to comply with EMI emissions restrictions required
by regulatory agencies.
If the system speed requirements are high enough (for
example, clock rates over 80 MHz), devices this fast
must be used, and the extra effort required to meet compliance is justified. However, if a slower device can meet
system requirements, it should be used. By virtue of the
longer transition time, the slower device generates less
energy at the higher frequencies. In general, try to use
devices that are fast enough to meet the system requirements, but no faster.
SUMMARY
While faster technologies provide the theoretical possibility of faster systems, extra care must be taken to turn
5-134
16356A-041 A
this possibility into reality. The largest noise components can be eliminated by addressing the fOllowing:
•
•
integrity and stability of power and ground;
termination and careful layout of transmission lines
to eliminate reflections;
• termination and careful layout to reduce the effects
of capacitive and inductive crosstalk;
• noise suppression for compliance with radiation
regulations.
There are many other second-order issues that could be
addressed, but that are beyond the scope of the application note. Some references for additional information
aie listed below.
1. Sherman lee, Mark McClain, Dave Stoenner.
"Am29000 32-Bit Streamlined Instruction Processor
Memory Design Handbook," Advanced Micro Devices Inc., Sunnyvale, CA, Appendix A, Memory Array loading Calculations.
2. William R. Blood Jr. "ECl Systems Design Handbook," Motorola Semiconductor Products Inc.,
Mesa, AZ, May, 1983 (Fourth Edition) Chapters 3
and 7.
3. Ramo, Whinnery, and Van Duzer, "Fields and
Waves in Communications Electronics," John Whilley & Sons, 1965, Chapter 1.
Hlgh-Speed-Board Design Techniques
~
Minimizing Power Consumption
with Zero-Power PLDs
Advanced
Micro
Devices
Application Note
by Shawn D. Worsell, Senior Applications Engineer
Zero-Power Programmable Logic Devices (PLDs) are
advanced PAL devices designed with ultra low-power,
high-speed, electrically-erasable CMOS technology.
ZPAL1M devices provide zero-standby power and high
speed for a variety of applications. At 15 JlA maximum
standby current, Zero-Power devices allow battery powered operation for an extended period of time. ZeroPower CMOS devices can significantly reduce system
power consumption by replacing equivalent CMOS and
TTL devices.
ZPAL devices are available in the following configurations: the industry-standard 20-pin PALC E16V8Z family
and the AMD-patented 24-pin PALCE22V1 OZ family.
The PALCE16V8Z family is functionally compatible with
all CMOS half- and quarter-power PALCE16V8 devices
and will directly replace the bipolar PAL16R8 and
PAL 10H8 series devices with the exception of the
PAL16C1.
The PALCE22V10Z family is functionally compatible
with all 24-pin 22V1 0 devices, and it provides user-programmable logic for replacing conventional low-power
CMOS SSI/MSI gates and flip-flops ata reduced chip
count.
POTENTIAL APPLICATIONS
ZPAL devices may be used in any application where a
standard 22V1 0 or 16V8 device would be used. DeSigns
that are currently in a 20V8 will also fit in the 24-pin
22V10 device. In addition, they are ideal for low-frequency or low-duty-cycle environments such as line
card and peripheral applications, where low power consumption is a priority. Laptop computers and other battery-operated or backed-up equipment, such as
hand-held meters and portable communication units,
would benefit from the Zero-Power devices.
The PALCE16V8Z and PALCE22V10Z feature a zerostandby power mode. When none of the inputs switch
for an extended period, the device will go into standby
mode, shutting down most of its internal circuitry, causing the current consumption to drop to almost zero
(15 JlA). The outputs will maintain the states held before
the device went into the standby mode. When any input
switches, the internal circuitry is fully enabled, and
power consumption returns to normal.
Since all of the features which cause the device to be a
Zero-Power PLD are internal, the 16V8Z and the
22V10Z PAL devices are pin-for-pin and JEDEC-file
compatible with existing devices of the same families.
Publication# 16948 Rev. A
Issue Date: June 1992
Amendment/O
HINTS ON MINIMIZING POWER
CONSUMPTION
The quintessential feature of the ZPAL device's current
reducing operation is the "sleep mode." When the device is inactive for a period of time, certain portions of the
PLD can be disabled or "put to sleep" by the presence of
input transition detection circuitry. Any switching delays
of about 50 nanoseconds or more, forthe entire device,
will place the PLD in sleep mode. This means that none
of the inputs, including the clock, can be switching in
order to utilize the Significant power saving features.
Therefore, during the deSign phase, special attention
must be given to every signal that is being transferred to
the device, so that the sleep mode feature may be engaged as much as possible. Refer to Figure 1 for ZPAL
device features.
Inputs
Transition Detectors
Input Buffer
Programmable AND Array
OR Plane
Array Latches
Macrocells,
Output Buffers
Transition Detectors
liD Pins
16948A-001A
Figure 1. ZPAL Device Features
5-135
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AMD
As sleep mode is asserted, all outputs will latch to the
state they were in when the last input transition occurred. This state will be held as long as the device is
asleep.
When an input does experience a transition, the device
will ''wake up." The wake-up delay associated with the
initial transition is included in the determined propagation delay of the device. Therefore, there are no extra
system delays to consider when the device utilizes the
standby feature, since it quickly returns to full operation.
However, if a designer is more interested in high speed,
such as a burst mode application, a typical propagation
delay would be closer to 5 nanoseconds faster while the
device is awake.
The inputs and I/O pins are monitored by an input transition detection circuit. Any transition on any pin, including
noise spikes, will disengage the sleep mode. Thus, during the design phase, care should be taken to ensure
that al/ circuitry associated with the Zero-Power device
is as quiet as possible.
Effects of Frequency
The sleep mode benefits are best realized in combinatorial applications since sequential functions will be
powered·up with every edge of the clock. However, significant power savings can still be realized when the
clock is stopped or operating at a modest rate. For instance, when used in an application with a 5-MHz clock
(200-ns period), the power consumption of the ZPAL
device will be reduced by 50% from the consumption at
the maximum frequency.
The designer must also be careful when considering the
true operating frequency. If the fastest input is 1 MHz,
but there are two inputs 90 degrees out of phase, even
though a transition occurs on each input every half-cycle
(500 ns); there is a transition on some input every quarter cycle (250 ns). Thus, the effective frequency is doubled, and the 2-MHz point should be used to calculate
the power consumption. This is not as important when
the signal in question is greater than 10 MHz, since with
a 50% duty cycle the part would never enter sleep mode.
Another way of realizing power savings is by decreasing
the duty cycle of the clock and input signals. Dynamic
Icc is a function of duty cycle and frequency. The two are
mutually exclusive. As previously mentioned, at a frequencyof 10 MHz with a 50% duty cycle, the part would
always be powered up. However,if the duty cycle was
decreased to 20%, a 10-MHz Signal would cause the
part to shut down for 30 nanoseconds (80-50 ns),
thereby reducing the Dynamic Icc of the device.
Referring to the typical Icc versus Frequency Graphs of
the corresponding data sheets, will clearly indicate the
power savings that may be realized by optimizing the
ZPAL device's operating frequency.
5-136
Effects of Product Terms
To further reduce power consumption, unused product
terms are permanently disabled during programming.
Each product term has a Sense Amp Off (SAOFF) bit,
which will be programmed when the corresponding
product term is unused, thereby shutting off the sense
amp to save power. Note that the SAOFF bit is automatically configured and has no effect on the JEDEC file, so
the designer does not even have to think about it. A
typical power savings of approximately 300 J.lA per unused product term will be achieved. Thus, a logic design
that utilizes a minimum number of product terms will
result in the maximum amount of power savings.
Inverting simplified logic by using DeMorgan's theorem
and changing the output polarity is one way that a designer may easily reduce product term reqUirements.
For example, in the equation
z=X+y
the "OR" function denoted by the "+" sign, requires two
product terms, one for each variable. However, if both
sides of the equation are inverted to become
fZ=/(X+Y)
using DeMorgan's theorem yields
/(X+Y) = /X*/Y
Here the "AND" function denoted by the "*" sign does
not use the second product term, because one product
term is shared by both variables. The resultant equation
is now
fZ=/X*/Y
and by switching the output polarity, the logic behaves
the same way as it was originally intended as well as
reducing a product term requirement.
The choice of output polarity itself does not save power,
but if chosen wisely, it may help to reduce product term
usage. It should also be noted, however, that switching
output polarity will also invert the Synchronous Preset
(SP) and Asynchronous Reset (AR) functions at the
output of the register of a 22V10.
1/0 Characteristics
The output stage of the Zero-Power PAL devices consist of a P-channel pull-up transistor and an N-channel
pull-down transistor, a true CMOS output with rail-torail switching. A P-channel pull-up is better for lowpower applications than an N-channel transistor, since
P-channel outputs can be driven up to the Vcc level.
This ensures that the following input buffer draws no
current. The same amount of current is available for
both high and low outputs with a P-channel pull-up,
unlike the unequal, although slightly faster N-channel
transistor used in other PLD products.
Minimizing Power Consumption with Zero-Power PLDs
AMol1
These devices are capable of driving and being driven
by either TTL or CMOS devices. They are compatible
with both HC and HCT standard specifications as illustrated in Table 1.
Table 1
Parameter
HC
HCT
ZPAL
VIH
3.15 V
2.0V
2.0V
VIL
0.9V
0.8 V
0.9V
Va..@6mA
0.33 V
0.33 V
0.33 V
Va..@20~
0.1 V
0.1 V
0.1 V
VOH@6mA
3.84 V
3.84 V
3.84 V
VOH@
20~
ously, it is important to ensure that the ground path on
the circuit board has low inductance, and to reduce the
loading on the outputs. The lower-lead-inductance
PLCC package will also reduce the possibility of ground
bounce since the bonding wires are 1/4 the length of
a DIP's bond wires.
Effects of Loading
Power dissipation of the outputs is greatly affected by
the load. To minimize power dissipation, ZPAL device
loads should have no DC components. If termination is
required, an AC terminator like the one in Figure 2
should be used to eliminate DC power drain.
VOPinT:
Vcc-0.1 V Vcc -0.1 V Vcc -0.1 V
One minor disadvantage of true CMOS outputs is the
intrinsic SCR circuit that is developed in the CMOS
structure and cannot be eliminated. The SCR has been
made as difficult as possible to turn on by using guard
rings and carefully laying out all input and output circuits.
An excess current of 100 rnA would be required on an
individual pin to induce "latch-up". However, there is a
potential to latch-up a ZPAL device through hot-socket
insertion. If there is a possibility of the device or board
being instantly powered-up, design care must be taken.
Effects of Reducing 1/0 Switching
Since each input will draw up to a maximum of 5 rnA
each time it switches, additional power savings are possible by reducing the number of inputs used. A CMOS
transistor pair only draws current when it is switching or
floating in an intermediate region, so unused inputs
should be externally tied either HIGH or LOW. The number of outputs switching will also affect the amount of
current consumption. Therefore, minimizing output
switching will also help to reduce the amount of current
required.
The potential for ground bounce problems will also be
reduced by limiting the number of outputs switching.
Built-in slew-rate-limiting circuits will help to slow down
the fast CMOS falling edges that contribute to ground
bounce. A fall rate of 1.25 V/ns is typical of the faster
N-channel pull-down transistor, while a slower rise rate
of 1 V/ns can be expected from the P-channel pull-up. If
most of the outputs are required to switch simultane-
JC
16948A-002A
Figure 2. Typical AC Terminator
The capacitance should generally be kept as low as
possible since the output stage will go through a process
of constantly charging and discharging the capacitor.
The formula for current consumption due to loading is
i
= CLVsjO
where i is the current, CL is the capacitive load, Vs is the
voltage swing, and to is the frequency at which the output is switching. Therefore, current is consumed every
high transition since the capacitor has to recharge.
SUMMARY
ZPAL devices provide zero-standby power and high
speed for a variety of applications. Zero-Power CMOS
devices can significantly reduce system power consumption by replacing equivalent CMOS and TTL devices. Since all of the featu res which cause the device to
be a Zero-Power PLD are internal, the 16V8Z and the
22V10Z PAL devices may be used in any application
where a standard 22V1 0 or 16V8 device would be used.
With a little extra attention given to the particular design
involving a Zero-Power PAL device, a designer can realize significant system power savings.
Minimizing Power Consumption with Zero-Power PLOs
5-137
~
Designing with the PALCE16V8HD
Advanced
Micro
Devices
Application Note
The PALCE16V8HD is a High Drive PLD that combines
the popular PALCE16V8 architecture with 64-mA current drivers. It has application anywhere a reasonably
complicated function must control a high-current signal
line. Examples of this are control signals for buses such
as the VME bus, combination decoder and LED driver,
3 V translator, and control lines for memory.
device. The extra device increases part count and increases total propagation delay.
The PALCE16V8HD is an ideal replacement forthe pair
of devices. First, it combines the full functionality of a
PAL device and 64-mA current sink capability into one
device. Second, it provides input latches to store information. Third, it provides the choice of either totem-pole
oropen-drain output drivers. Finally, it has a minimum of
200-mV hysteresis on all input and 1/0 pins for increased noise immunity. The macrocell is shown in
Figure 1.
Previously, this problem was solved by using a programmable device, such as a PAL device, followed by a
highcurrent driver. The drawback to this solution is that it
requires two devices to perform the functionality of one
~==~------------------------------------~11
Vcc
1 01-----, To Adjacent
00
Macrocell
01
SLOx
SG1
I/OX
From
Adjacent
Pin
·SG1
a)
1ssnA-1
·'n macrocells MCo and MC7
SGt is replaced by SGO on ,the feedback multiplexer.
b)
Figure 1. a) PALCE16V8HD 1/0 Macrocell; b) PALCE16V8HD Input Macrocell
5-138
AmendmentlO
AMD~
The purpose of this application note is to guide the engineer in using the PALCE16V8HD high drive-current
PAL device. What follows is a discussion of its features
and hints on how to maximize their benefits.
Input Latches
ently in the state opposite the desired initialized state.
An example is shown below.
OUT!. T
=
A*B*OUTl * /OUT2
iapplication
iequations
+ /A*/B*/OUT1*
All inputs to the device (including 1/0 pins) can be programmed as a transparent latch. The latch enable (LE)
signal is pin 4 (pin 5 for PLCC). The latches are transparent when LE is HIGH and latched when LE is LOW.
Input latches provide a convenient way to speed up data
transfer while providing storage at the same time. With
latches, the new data is available instantaneously,
while with registers, the data is not available until the
next clock edge. The input-latch setup time is also short
because the product-term array is bypassed. The register-setup time is 10 ns, while the latch-setup time is only
4 ns. This last feature makes it possible to capture signals which tend to occur late in the clock cycle.
The PALCE16V8HD is designed so that the transparent
latch does not add extra delay to the signal. This makes
the PALCE16V8HD faster than the usual PAL device
and input latch combination.
/OUT2
+ INIT LOW*OUTl
+ INIT_HIGH*/OUTl
;
"
itoggles to
iLOW if HIGH
itoggles to
iHIGH if LOW
Output Driver Configurations
The output macrocells can be independently configured
as either totem-pole outputs or open-drain outputs. In
the totem-pole configuration the driver has an n-channel
pull-down transistor and an n-channel pull-up transistor.
The output-LOW voltage is typically 0.3 V and the output-HIGH voltage is typically 3.5 V. In the open-drain
configuration, the n-channel pull-up transistor off. The
output-LOW voltage is the same as in the totem-pole
configuration. The output-HIGH voltage is determined
by the termination voltage and the load on the signalline.
Totem-Pole Output Configuration
Register Configurations
The output registers can be configured as either D-type
or T-type flip-flops. The D-type register's Q output is
equal to the D input at the rising edge of the clock. The
T-type registers output toggles when the corresponding
T input is HIGH and maintains the current state when the
T input is LOW. The T-type register's action is also determined at the rising edge of the clock signal.
The D-type register has the advantage of simplicity. It is
straight forward and the easiest to determine the desired results.
In many applications, such as counters, the T-type flipflop requires fewer product terms. If the application is
large enough, this can mean the difference between fitting or not fitting on the part.
T-type flip-flops tend to reduce the number of product
terms required in sequential applications such as counters and state-machines. They are not optimal for all applications. For example, to load data takes two product
terms with a T-type flip-flop and only one product term
with a D-type flip-flop. Because the PALCE16V8HD can
be configured as either type, it has a wider range of application than either one alone.
Note that because there is no global initialization function, deSigners should be sure that T-type flip-flops have
a direct way of being initialized. This can most easily be
done by ensuring that there is at least one LOAD product term. A LOAD product term is one that can be activated with no other product term active, and which will
have the flip-flop toggle only if the flip-flop state is pres-
The totem-pole output driver conforms to TTL specifications. Because the pull-up transistor is n-channel, the
output-HIGH voltage is 1 to 1.5 volts below Vcc, even
under zero-load conditions. If rail-to-rail swings are required, VOH can be raised by terminating the output with
a resistor to Vee.
Open-Drain Outputs
The open-drain configuration has two types of applications. The first is as a switch to apply power to devices
such as a small lamp or even a small motor. The second
is as an active-LOW signal source on a signal line with
multiple asynchronous drivers. Because the pull-up
transistor is always off, the risk of device damage due to
contention is eliminated. If the output structure were totem-pole only, the state of the output would have to be
set internally and then the output would be enabled. The
open-drain structure eliminates this extra complexity.
An example of asynchronous signals on one line is the
bus requestforVME buses. For open-drain outputs, the
request line simply goes LOW. Simultaneous requests
must be handled by an arbiter, but there is no risk of circuit damage due to bus contention.
Output Terminations
The anticipated applications for the PALCE16V8HD include relatively long signal-line lengths. At the rise and
fall times of this device (2 to 3 ns), the signal lines resemble transmission lines. The transmission line's propensity for reflections requires the use of terminating
techniques. It is beyond the scope of this article to pre-
Designing with the PALCE16V8HD
5-139
~
AMD
sent a detailed discussion of transmission lines, but we
will discuss some of the more popular termination techniques that lend themselves well to high-drive devices.
Those interested in studying transmission lines in more
detail are encouraged to check out the references at the
end of this application note.
Terminating Totem-Pole Outputs
The most effective termination is a resistor at the load
end of the signal line that is equal to the line impedance
(Figure 2a). Because the input impedance of all PLDs is
greater than 10 kn, this is effectively an exact match.
Because parallel termination increases the DC load, the
output will be degraded for both VOH and VOL. The IN
curves for the device (Figure 3) can be used with a load
line to determine the degraded output levels. The
dashed lines indicate simple termination to Vcc or
ground.
RT
RTh = R1
~VBias
II
R2
VTh=Vee~
R1+ R2
c)
b)
a}
Vec
Vee
d)
e)
16677A-2
Figure 2. Termination Alternatives: a) Parallel; b) Active; c) Th~venln; d) AC; e) Multiple Drivers
0
2
VOH (Volts)
3
4
5
6
0
100n
-20
75n
50n
--o_ _ _zo-..JRT
a)
b)
VSias
c)
16677A-6
Figure 6. Termination for Open-Collector Outputs:
a) Single Driver; b) Multiple Drivers; c) Alternative If Load Exceeds
If multiple drivers are used, terminating resistors should
be placed at both ends of the signal line as in Figure 6b.
The DC load is the parallel combination of the loads at
both ends of the signal line, effectively doubling the DC
load.
The DC current load can be reduced by connecting the
terminating resistors to a bias voltage that is less than
Vcc as in Figure 6c. Because the PAL device provides
no pullup in the open-collector configuration, VSIAS is
VOH; therefore VSIAS must be high enough to ensure a
valid logic HIGH to all the device inputs on the signal
line.
signal line. In addition, series-terminated signals can
hover at a mid-range until reflections cause them to settle to their final value. The mid-range is usually dangerously close to the input thresholds of most devices.
One technique that increases the devices tolerance to
noise is hysteresis. Hysteresis moves the input threshold in the direction that requires a larger signal. For ex-'
ample, when the input signal crosses the threshold on a
positive transition, the threshold moves lower (Figure 7).
The input signal would have to move lower to cross the
new threshold. Therefore, even a noisy Signal will cause
a single croSSing per transition, not the multiple crossings that might occur without hysteresis.
Hysteresis
Buses tend to operate in a noisy environment. Voltage
spikes from crosstalk can be expected on almost every
5-142
10L
Designing with the PALCE16V8HD
AMD~
v
Input Signal
--- ----------- --- ---- '~~~t~~~~
--Th~~~h~ld-
Threshold
Crossings
a)
v
Input Signal
Single
Threshold
Crossing ~
I
-- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -_ .. _Threshold
b)
166nA-7
Figure 7. Response to Noisy Inputs:
a) Device with no Input Hysteresis; b) Device with Input Hysteresis
The PALCE16V8HD comes with a minimum of 200 mV
hysteresis. Therefore, if the noise occurs when the input
signal level is at the exact middle of the threshold range,
the device can tolerate 200 mV peak-to-peak of noise
before detecting multiple transitions.
ing current. Because there is less current in anyone
ground pin, there is less energy available to generate
ground bounce. Slew rate limiting reduces the current
surge in the ground pin. Together these features keep
ground bounce down to a tolerable level.
Ground Bounce
The following table shows ground-bounce data measured underworst-case conditions: a" eight macroce"s in
the registered configuration and seven outputs switching simultaneously. The measured pin is in the LOW
state during the test. The test was performed with the
fo"owingACtest load:80nto Vec, 160ntoground, and
50 pF to ground.
An issue that is associated with high-current CMOS is
ground bounce. This phenomenon is usually first noticed as a pulse or ringing on a LOW output. If these
pulses are large enough they can generate false clocking or false data. The design of the PALCE16V8HD
takes ground bounce into consideration so that it is
minimized.
The PALCE16V8HD has two features which make it resistant to ground bounce: multiple ground pins and slew
rate limiting. The multiple ground pins share the switch-
Note that the maximum transient VOL is 1.3 V, which
shows that ground bounce on the PALCE16V8HD is
equal to, or better than, ground bounce on devices with
only 24-mA drive current capability.
Designing with the PALCE16V8HD
5-143
~
AMD
transistors, which will not conduct or cause latchup
when the output signal is higher than Vec.
Ground Bounce Peak Voltage with
Seven Outputs Switching
LOW Pint
Peak Voltage
23
22
20
19
16
1.2V
1.1 V
1.0 V
1.1 V
1.2 V
1.3 V
1.3 V
1.2 V
15
14
13
. Hot socketing has two manifestations that concern us
here: signal and ground connected before Vee, or signal
. and Vee connected before ground. If ground and signal
lines are connected to the device before Vce is, the effect on the device is similar to that presented by the
power-down situation; the device inputs and outputs do
not conduct current.
Power Supply Considerations
There are two special situations which should be considered for devices used in bus applications: power
down with live signals and "hot-socketing." Disabling
Vce of certain sections of a system is a common technique for power conservation. The devices on the disabled board should be able to tolerate live signals on the
input and I/O pins while power is down. "Hot-socketing,"
the technique of inserting or removing boards while
power is applied, is never recommended; however, almost every system is subjected to it at one time or another. The PALCE16VSHD can withstand the stresses
brought about by power shutdown and hot socketing.
During power shutdown, Vee is either open or shorted to
ground. The PALCE16VSHD has n-channel pull-up
0
2
VI/O Volts
4
3
5
When the ground pin is open with Vee and the inputs or
outputs connected, the pull-up transistors conduct. This
is because a solid ground is necessary to establish the
proper bias voltages to allow the output transistors to
turn off. If ground is floating the output transistors are biased on.
Figure Sa shows the IN curves on an I/O pin with Vec on
and ground open. The driver starts to conduct at 4 Vand
crosses 0 V at -110 rnA. It is interesting to note that
there is also conduction at the input pins (Figure Sb).
The ESD structure is a totem-pole configuration resembling an output driver; therefore, the ESD-protection
transistor also conducts when ground floats.
If the ground is disconnected for only a second or two,
the device will not be damaged.
6
0
0
0
20
20
40
40
«
2
VI Volts
3
4
5
6
«
E 60
E 60
~
.::-
80
80
100Y
100 t
120
120
a)
b)
16677A-8
Figure S. IN Curves when Ground is Disconnected: a) I/O Pin; b) Input
5-144
Designing with the PALCE16VSHD
AMD~
SUMMARY
•
The PALCE16V8HD incorporates a number of features
which make it ideal for applications involving high-current signal lines such as bus control lines.
The output drivers generate fast signals (2-ns to 3-ns
rise and fall times). At these edge rates transmission
line terminating procedures should be used.
•
The drivers can be individually programmed as
either totem-pole or open drain. For open-drain outputs, the terminating voltage determines VOH.
•
All input pins have a minimum of 200 mV hysteresis.
This allows the PALCE16V8HD to operate more
robustly in noisy environments such as buses.
•
The PALCE16V8HD incorporates slew-rate limiting
and multiple grounds. This reduces ground bounce
to levels more common in low-power devices.
•
The PALCE16V8HD has n-channel pullup transistors. Therefore, it is resistant to latchup caused by
signals on input and I/O pins while Vce is off, or by
hot -socketing.
•
•
There are input latches on every input and I/O pin.
The latches allow the earlier capture of data, which
effectively shortens the cycle time in many applications. The use of the latch does not add any extra delay. Thus the PALCE16V8HD is faster than the PLD
device and external latch combination.
The PALCE16V8HD macrocell can be programmed
as either D-type or T-type flip-flops. The T-type flipflops can reduce product-term usage in many applications. Larger counters and state-machines can
often be built with T-type flip-flops than with D-type
flip-flops.
Designing with the PALCE16V8HD
5-145
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AMD
5-146
6
APPENDICES
Logic Reference
Guide ........................................ . . . . . . . . . . . .. 6-3
Signal Polarity
Glossary ............................................................... 6-25
Worldwide Application
S~pp~rt' :::::::::::::.................................
.................................
Appendices
6-30
6-37
6-1
~AMD
6·2
Appendices
~
Logic Reference Guide
Advanced
Micro
Devices
INTRODUCTION
Throughout this data book and design guide we have
assumed that you have a good working knowledge of
logic. Unfortunately, there always comes a time when
you are called on to remember something which can
only be found in that logic textbook which you threw
away years ago.
This section is intended to provide a quick review and
reference of the basic principles of digital logic. We will
cover three general areas:
•
Basic logic elements
~
==D==D-
NOT
AND
OR
101730-
Figure 1. Schematics Symbols for the Three
Fundamental Gates
• Basic storage elements
•
The standard schematic symbols used to represent
these gates are shown in Figure 1.
Binary numbers
Throughout the text, we will use the notation that was
used throughout this book. If you are unfamiliar with the
syntax, you will probably find it easy to understand as
you read; if you wish for a more detailed explanation of
the symbols, please refer to the Basic Design with PLDs
section where they are defined.
As this is a logic reference only, we cannot take on
lengthy discussions, nor can we train you in the basic
principles of digital logic if you have not previously been
trained. In such a case, we must refer you to your
favorite logic textbook.
The AND and NOT functions can be combined into the
NAND function. This is equivalent to an AND gate followed by an inverter, as shown in Figure 2a. Likewise,
the OR and NOT gates can be combined into the NOR
function, as shown in Figure 2b. Each of these gates is
functionally complete; any logic function can be expressed solely as a function of NAND or NOR gates.
a. The NAND Function
BASIC LOGIC ELEMENTS
In this section, we will discuss the concepts surrounding
combinatorial logic functions.
b. The NOR Function
The Three Basic Gates
There are three basic logic gates from which all other
combinatorial logic functions can be generated. These
functions are NOT, AND, and OR. A truth table indicating these functions is shown in Table 1. Since they can
be used to generate any function, they are said to be
functionally complete.
Table 1. Truth Table for the NOT, AND, and OR
Functions
A
B
fA
A*B
a
a
a
1
1
1
0
0
0
1
1
1
0
0
1
a
A+B
0
101730-
Figure 2. The NAND and NOR Functions
Precedence of Operators
Logic functions may be created with any combination of
the three basic functions. How those functions are expressed affects the evaluation· of the function. The
normal order of evaluation is:
NOT, AND, OR
Evaluation proceeds in order from left to right.
1
1
1
6-3
~
AMD
This order may be altered by inserting parentheses in
the function. The contents of the parentheses will always be evaluated before the rest of the expression,
from left to right.
Some example functions are evaluated in Table 2.
Table 2. Using Parentheses to Change the Order of Evaluation
8
0
1
0
1
A
0
0
1
1
C
0
1
0
1
A*B+/A*
C+D
0
0
0
0
1
1
A*B+/A*
(C+D)
0
1
0
1
1
1
1
Commutative,· Associative, and
Distributive Laws
A*(B+/A)*
C+D
0
0
1
1
A*(B+/A)*
(C+D)
0
0
0
1
Duality
The AND and OR functions are commutative and assoCiative. This means that the operands can appear in any
order without affecting the evaluation of the function.
This is illustrated in Tables 3 and 4.
The two distributive laws give an example of the concept
of duality. This principle states that:
Any identity will also be true if the following substitutions
are made:
* for +
+ for *
1 for 0
o for 1
Table 3. Commutativity
A
0
0
1
1
8
0
1
0
A*B
0
0
1
B*A
0
A+B
0
B+A
0
0
0
0
1
1
1
1
1
1
1
1
Table 4. Associativity
C
0
A
0
0
8
0
1
1
1
a
1
1
1
1
(A*B)*C A*(B*C)
0
0
0
0
a
0
1
1
(A+B)+C A+(B+C)
0
0
1
1
1
1
1
1
Thus, it is only necessary to prove the first of the distributive laws; the second one will then be true by duality.
Note that duality is not required to prove the second law;
it can also be proven by truth table or by logic
manipulation.
Manipulating Logic
Logic functions may be manipulated by the use of
Boolean algebra. The logic functions may be expressed
in one of the two canonical forms, or by using a simplified expression.
There are actually two distributive laws; one of them resembles standard algebra more than the other. These
two laws state that:
A*(B+C)
(A*B) + (A*C)
A+(B*C) = (A+B) * (A+C)
6-4
Logic Reference Guide
AMD~
Canonical Forms
There are two fundamental canonical forms: sum-otminterms and product-ot-maxterms. The former is by far
the most widespread. These are special cases of what
are more generally referred to as sum-ot-products and
product-ot-sums forms. Minterms and maxterms are
products and sums of the variables involved in a function. Each particular combination of noninverted and
inverted variables in a product or su m is given a minterm
or maxterm number, as shown in Table 5. Within each
minterm or maxterm, the individual variables are referred to as literals.
'
For the case of sum-of-minterms form, the expression
for a function may be found by ~Ring the minterms
which correspond to the 1's in the function's truth table.
Likewise, the product-of-maxterms expression may be
found by ANDing the maxterms which correspond to the
O's in the truth table. This is illustrated in Figure 3.
Table 5. Mlnterms and Maxterms
Table of Minterms for Three
Variables
Minterm
/x*Iy*/z
/x*/y·z
/x*y*/z
/x*y·z
x·/y·/z
x·/y·z
x·y*/z
x·y·z
Name
Maxterm
Name
mO
m1
m2
m3
m4
m5
m6
m7
x+y+z
x + y +/z
x +/y + z
x +/y + /z
/x+y+z
/x+y+/z
/x+ly+z
/x+/y+/z
MO
M1
M2
M3
M4
M5
M6
M7
Conversi.on Between Canonical Forms
It is a simple matter to convert between canonical forms.
Given a truth table for a function F, there are four different representations that can be used:
•
Table of Maxterms for Three
Variables
One can convert back and forth between these representations by using the rules shown in Table 6.
Sum-of-minterms form of F
•
Product-of-maxterms form of F
•
Sum-of-minterms form of IF
•
Product-of-maxterms form of IF
Logic Reference Guide
6-5
~AMD
Minterml
Maxterm
Number
B
0
0
0
0
1
1
1
1
0
0
0
C
y
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
x
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
10
1
1
1
1
0
0
15
A
0
1
2
3
4
5
6
7
8
9
a. Truth Table
x =
=
= /A */B * /C *
+
+
+
+
+
+
y
x = M1*M4*M6*M10*M11*M12*M13*M14*M15
mO+m2+m3+m5+m7+m8+m9
LIn (0,2,3,5,7,8,9)
/A
/A
/A
/A
A
A
*/B
*/B
* B
* B
*/B
*/B
* C *
* C *
* /C *
* C *
* /C *
* /C *
nM
= (A+B+C+/O)
;mO
;m2
/0
/0
0
0
0
/0
0
* (A+/B+C+D)
* (A+/B+/C+O)
* (/ A+B+/C+O)
* (/A+B+/C+/O)
* (/ A+/B+C+O)
* (/A+/B+C+/O)
* (/A+/B+/C+O)
* (/A+/B+/C+/O)
;~3
;m5
;m7
;m8
;m9
mO+m1+m2+m3+m4+m7+m8+m9
2.m (0,1,2,3,4,7,8,9)
= /A */B * /C *
+
+
+
+
+
+
+
/A
/A
/A
/A
/A
A
A
*/B
*/B
*/B
* B
* B
*/B
*/B
*
*
*
*
*
/C
C
C
/C
C
* /C
* /C
y
;mO
;m1
;m2
;m3
;m4
;m7
;m8
;m9
/0
0
/0
0
/0
0
*
*
*
*
*
* /0
* 0
b. The Sum-of-Minterms Expression
(1,4,6,10,11,12,13,14,15)
= M5*M6*M10*M11*M12*M13*M14*M15
= nM (5,6,10,11,12,13,14,15)
= (A+/B+C+/O)
* (A+/B+/C+O)
* (/ A+B+/C+O)
* (/A+B+/C+/O)
* (/A+/B+C+O)
* (/ A+/B+C+/O)
* (/A+/B+/C+D)
* (/A+/B+/C+/O)
;M5
;M6
;M10
;Mll
;M12
;M13
;M14
;M15
c. The Product-of-Maxterms Expression
Figure 3. Finding the Canonical Form from the Truth Table
6-6
;M1
;M4
;M6
;M10
;Mll
;M12
;M13
;M14
;M15
Logic Reference Guide
AMO;t1
Table 6. Conversion of Forms Table
Desired Form
Given Form
Minterm
Expansion of F
Minterm
expansion
of F
-
Maxterm
expansion
of F
Minterm numbers
are those numbers
not on the Maxterm
list of F
Maxterm
Expansion of F
Maxterm numbers
are those numbers
not in the Minterm
list of F
-
Inverted Minterm
Expansion of F
List Minterms not
present in F
Minterm numbers
are the same as
Maxterm numbers
of F
Simplifying Logic
Inverted Maxterm
Expansion of F
Maxterm numbers
are the same as
Minterm numbers
ofF
List Maxterms not
present in F
There are four basic postulates, two of which are the
commutative and distributive laws which were discussed above. From these postulates, it is possible to
derive nine basic theorems. The postulates and theorems are listed in Table 7.
Canonical forms are convenient in that it is easy to derive and convert them. However, the representation is
bulky, since all variables must appear in each sum or
product. These expressions can be simplified by applying the basic laws and theorems of Boolean algebra.
Table 7. Postulates and Theorems of Boolean Algebra
Postulate 1
(A)
(B)
Postulate 2
(A)
(B)
Postulate 3
(A)
(B)
Postulate 4
(A)
(B)
Theorem 1
(A)
(B)
x
+ FALSE
X*TRUE = x
=
X
x
+ !X = TRUE
= FALSE
X * !X
x + Y
= Y
x*y = y*x
x
x
*
(y
+
Z)
+
x
=
(x*y)
X + X
X * X
=
=
X + TRUE = FALSE
X*FALSE = FALSE
(A)
(B)
X + (y + Z)
X * (y*Z) =
Theorem 5
(A)
(B)
!
!
Theorem 6
(A)
(B)
X +
X *
Theorem 7
(A)
(B)
(x*y) + (x*!y) = X
(X + y) * (X + !y)
Theorem 8
(A)
(B)
X + (lX*Y) = X + Y
X * (IX + Y) x*y
Theorem 9
(A)
(B)
Theorem 3
Theorem 4
(A)
!
(IX)
(x*Z)
(X + X)
X
X
(B)
Theorem 2
+
+ (y*Z) = (X + y) *
=
(X + y)
(X * y)
X
=
=
(X * y)
(X + y)
=
(X + y) + Z
(x*y) * Z
!X * !y
!X + !y
=
=
(x*y) + (lX*Z)
(X + Y) * (IX
X
X
=
X
+ (y*Z) = (x*y) + (lX*Z)
+ Z) * (Y + Z) = (X + Y) *
Notice that each theorem and postulate (with the exception of theorem 3) has two forms. This is a result of the
duality principle; once one form of a theorem is established, the dual representation follows immediately.
Theorem 3 has no dual because it does not involve any
of the elements that have duals (+, *, 1, or 0).
(IX
+
Z)
As the logic expression is simplified, it no longer contains minterms (or maxterms), since some of the
minterms and literals are being eliminated. What was a
sum-of-minterms (product of maxterms) representation
is now simplified to a sum-of-products (product of
sums).
Logic Reference Guide
6-7
~
AMD
dIf dr
---...----..---".-- Values of A
DeMorgan's Theorem
Once an expression has been simplified, it is no longer
possible to invert the function by using Table 6. Inverting
simplified logic requires DeMorgan's theorem:
f
A
C
B
00
01
11
10
/(x*y) = /x + /y
/(x + y) = /x*/y
ValuesolB
Moving to an
Adjacent Cell
Changes the
Value of one
Variable only,
This is theorem 5 in Table 7.
There is one shortcut which can be used. The effect of
inversion can be accomplished by inverting all literals
and then using the dual representation. For example,
given the expression
[l
Values of C
10173D-
/(A*/B + A*C + /A*B*D)
we can invert to obtain:
/A*B
+ /A*/C + A*/B*/D
(/A + B)*(/A + /C)*
(A + /B + /D)
Groups Can
WrapAround
Figure 4. A Karnaugh Map for Three Variables
;step one,
invert
literals
;step two,
take dual
This expression must still be simplified to obtain a sumof-products representation, but this shortcut eliminates
, some of the early steps.
Karnaugh Maps: Minimizing Logic
Simplifying by hand by using algebraic manipulation can
be a tedious and error-prone procedure. When only a
few variables are' used (generally less than 5 or 6),
Karnaugh maps (also called K-maps) provide a simpler
graphical means of simplifying logic. K-maps not only allow for logic simplification, but for logic minimization,
where an expression has a minimal number of product
terms (or sum terms) and literals.
A Karnaugh map consists of a box which has one cell for
each minterm. These cells are arranged so that only one
literal is inverted when moving from one cell to an adjacent cell. The headings placed by each row and column
indicate the polarities of the literals for that row or column. The literals themselves are indicated in the top left
corner of the map. An example of a Karnaugh map for
three variables is shown in Figure 4.
The truth table for a function is then transferred to the
K-map by plaCing the 1's and D's in the appropriate cells.
Since each cell differs from its neighbor only in the polarity of one of the literals, 1's in adjacent cells can be
combined by theorem 7a, which says that
x*y + x*/y
= x
In this manner, two product terms are combined into
one. This procedure can conceptually be repeated to allow groupings of two, four, eight, or any group of
adjacent cells whose size is a power of two. A cell may
appear in more than one group. Just enough groups are
found to include all of the 1'So The groups should be as
large as possible.
This process provides a minimal sum of products. The
product-of-sums form can be obtained by grouping D's
instead of 1's and inverting the header for each cell.
The two functions from Figure 3 have been placed into
K-maps in Figure 5. The groups are then used as individual product terms. When reading the product terms
from the map, the only literals which will appear in the
product term are the ones whose values are constant for
each cell in the group. If that value is 1, then the noninverted form of the literal is used. If the value is 0, then
the inverted form of the literal is used.
For active-LOW functions, the same procedure is used,
except that the D's are grouped instead of the 1'so The
active-LOW version of the functions from Figure 3 are
derived in Figure 6.
Hand simplification and minimization is not needed as
frequently today as in the past, since software is now
available for handling these logic manipulations. Most
software can perform logic simplification and minimization automatically.
6-8
Logic Reference Guide
AMD~
A*S*/C
S*/C*D
y
x
X
Y
IA*/S*ID
IA*ID
+ IC*ID
+ IA*/S*/C
+ A*S*/C
+ A*/C*ID
+ S*/C*D
+ IA*C*ID
10173D-
Figure 5. Using a K-map to Minimize the Functions in Figure 3
A
S
C
00
D
IS*D
1
00
o
o
10
x
1
I
V1
~,
01
1
11
reo
10
1
C*D
01
0
1
0.)
0
1
0
A*C
IX = C*D
10
1
~
o~
V
A*/S*D
V
A*C
0
y
IY =
+ IS*D
+ A*C
+ IA*S*/C*ID
IA*S*D
COD
+ A*D
+ IA*S*D
+ A*/S*D
10173D-
Figure 6. Finding Inverse Functions
Logic Reference Guide
6-9
~
AMD
Comparison and Equivalence: the XOR
and XNOR Gates
~D-XOR
The Exclusive-OR (XOR) and Exclusive-NOR (XNOR)
gates are two special gates which are relatively common. These gates have schematic symbols as shown in
Figure 7a. They are actually compound gates, and can
be generated by AND, OR, and NOT gates using the
functions:
==:}D-
x :+: y = x*/y + Ix*y
x :*:y = x*y + Ix*/y
;XOR gate
;XNOR gate
The XOR and XNOR functions are actually inverses of
each other; that is,
XNOR
101730-
a. Schematic Symbols
A
B
A:+:B
A:*:B
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
1
b. XOR and XNOR Truth Table
x :+: y = I(x :*: y)
The truth tables for these gates are shown in Figure 7b.
Note that the XOR function is true if and only if the operands are different. For this reason, it is useful as a
comparator. The XNOR function is true if and only if its
operands are the same; therefore it is used as an
equivalence indicator.
Figure 7. The Exclusive-OR and Exclusive-NOR
Functions
Some basic properties of the XOR and XNOR functions
are listed in Table 8.
Table 8. Properties of the XOR and XNOR Functions
XNOR
XOR
x :+: 0 =x
x:*:O=/x
x :*: 1 = x
x :*: x = 0
x :*: Ix = 1
x .*. y = y :*: x
x:*:y:*:z = (x :*: y) :*: z)
= x :*: (y :*: z)
x :*: y =Ix :*: Iy
I (x :*: y)
= Ix :*: y
= x :*: Iy
=x :+: y
x :*: y = x* y + Ix*ly
x :*: x* y = Ix + y
x :*: Ix*y =Ix * Iy
x + (y :*: z) ::: (x + y) :*: (x + z)
Ix + (y :*: z) = (x*y) :*: (x*z)
:+ 1 =Ix
:+: x = 0
:+: Ix = 1
:+: y =y :+: x
:+: y = :+: z = (x :+: y) :+: z
= x :+: (y :+: z)
x :+: y =Ix :+: Iy
I (x :+: y)
= Ix :+: y
= x :+: Iy
= x :+: y
x :+: y = x* Iy + Ix*y
x :+: x* y = x*ly
x :+: Ix*y = x + y
x* (y :+: z) = (x*y) :+: (x*z)
Ix*(y :+: z) = (x + y) :+: (x + z)
x
x
x
x
x
When deriving equations from a Karnaugh map, XOR
and XNOR functions can usually be identified by their
characteristic pattern. Exactly what the operands are
mayor may not be obvious for more complicated functions. Some examples are shown in Figure 8.
The XOR gate can be used as an "UNLESS" operator. In
other words, the function, A = X :+: Y can be
interpreted as:
"A will have the same value as X UNLESS Y is true."
This can be helpful when trying to derive a logic equation
for a function which can be described in words.
6-10
Logic Reference Guide
AMD~
P
P
0
R
00
J
r-....
00
01
0
R
1
0
10
0
11
10
0
~
0
0
1
'-.,...I
11
01
1
1
0
1
0
00
01
0
'-.....I
r-....
S
r-....
1
11
1
10
00
01
0
0
11
0
10
1
"-.,...I
,...........
1'"1'
0
1
0
0
0
'-.....I
1
0
1
0
'-"
~
'-.,...I
'-.,...I
0
K
J
J
+
/P·/O·/R
P·O·/R
/P·O·R
P·/O·R
((/P·/O) + (P·O))*/R
((/p·O)+(p·/O))·R
(P:·:O)·/R
(P:+:O)·R
/(P:+:O)*/R
(P:+:O)*R
=
(P:+:O):·:R
+
+
+
+
+
I
1
K
/P·/O·S
+ p·O·S
+ p·/O·/S
((/p·/O) + (p·O))·S
+
p·/O·,S
I
101730-
Figure 8. Finding XOR and XNOR Functions In Karnaugh Maps
Basic Storage Elements
Storage elements provide circuits with the capability of
remembering past conditions or events. The prototypical storage element is just a pairof cross-coupled NAND
gates, as shown in Figure 9. These elements are normally called flip-flops.
Flip-flops can also be characterized by their con'trol
scheme. There are fourtypesof flip-flops, each of which
can be unclocked or clocked:
•
S-R
• J-K
• D
• T
The discussion below will be divided between unclocked and clocked flip-flops. Each of the four flip-flop
types will be treated for each section.
Unclocked Flip-Flops-Latches
10173D-
An S-R latch can be built out of NOR gates as shown in
Figure 10, and behaves according to the truth table in
Table 9. "S' stands for 'set' and 'R' stands for 'reset,' as
suggested by the truth table.
Figure 9. Basic Storage Element
In general, there are two primary classes of flip-flops:
•
Unclocked flip-flops, or latches
•
ClockedfJip-flops
S-R Latches
Clocked flip-flops are sometimes referred to as registers, although technically speaking, a register is a bank
of several flip-flops with a common clock signal.
Note that the latch actually has two outputs, which are
complementary. These are referred to as Q and O. If
both Sand R are raised at the same time, then both Q
and 0 will be HIGH; although this is physically possible,
it does not make sense if Q and Q are to be complementary signals. Thus, this condition is not allowed.
Logic Reference Guide
6-11
;t1
R
AMD
-I----~
D-.._--+-
a
s
D-..--+--o
1
R
I
a
I
1
I
S ---11- - - 1
L_....;. _ _ _ _ _ _ _ .J
101730-
Figure 10. An S-R Latch
There are some applications where it is desirable forthe
input data to be effective only when another signalusually called a control signal-is active. The circuit of
Figure 10 can be modified to give an S-R latch with a
control input,'as shown in Figure 13. The operation of
this circuit is summarized in Table 10 and Figure 14.
The S-R latch is somewhat restrictive, since both inputs
cannot be HIGH at the same time. The other latch types
are based on the S-R latch, but have additional logic
which removes the input restrictions.
Table 9. S-R Latch Truth Table
5
0
0
1
1
s
R
0
1
0
Q+
0
Not allowed
a
0
1
R
The transfer function for this latch can be derived with a
Karnaugh map, as shown in Figure 11. By choosing
either 1 's or D's, we can obtain two representations:
a
101730-
a. Q+ = S+/R*Q
b. /Q+ = R+/S*/Q
s a
R
00
01
a
a
a
1
Figure 12. S-R Latch Behavior
s a
a
R
1
00
a
01
r---.
1
0
1
a
0
s-r---r-'"
c
R-t----L-..J
~
11
X
10
1
X
11
X
X
10
1
1
r-1
101730-
a. 0+
=S + iR·Q
b. iO+ = R + /S·/O
Figure 11. Karnaugh Map for an S-R Latch
Waveforms illustrating the operation of the S-R latch are
shown in Figure 12.
6-12
101730-
Figure 13. Adding a Control Input to an S-R Latch
Table 10. Truth Table for an S-R Latch with a
Control Input
S
X
0
0
1
1
Logic Reference Guide
R
X
C
Q+
a
a
1
1
1
1
a
a
1
0
1
0
1
Not allowed
AMD~
s
R
c
a
101730-
Figure 14. Behavior of an S-R Latch with a Control Input
0-Type Latches (Transparent Latches)
A single-input latch can be formed by adding some logic
to the controlled S-R latch in Figure 13; this gives rise to
the D-type latch in Figure 15. This latch is often called a
transparent latch, since data on the input passes right
through to the output as long as the control input is
HIGH. If the control input is set LOW, then the latch
holds whatever data was present when the control went
LOW. With this type of latch, the control is usually called
a gate.
The behavior of the D-type latch is shown in Table 11
and Figure 16.
The basic transfer function for a D-type latch can be derived from the Karnaugh map in Figure 17.
D
G
a
101730-
Figure 16. 0-Type (Transparent) Latch Behavior
0+ = D*G + O*/G
10+ = ID*G + 10*IG
10
10
r----------,
I
I
D
S
G
a
a
C
I
I
IL _ _ _ _ _ _ _ _ _ _ .JI
Q
U
a
G
101730-
Figure 15. A 0-Type (Transparent) Latch
0
0+
Table 11. Truth Table for a D-Type Latch
~
I
~
a. 0+
I
=O*G + O*/G
a
o
1
0
10+
b. /0+
=/O*G + /O*/G
101730-
Figure 17. Karnaugh Maps for a D-Type Latch
Logic Reference Guide
6-13
~
AMD
If realized exactly as the transfer function indicates, the
result is actually a glitchy circuit.
J-K Latches
Another two-input latch can be derived from the S-R
latch as shown in Figure 18. This is called a J-K latch,
and operates in the same manner as an S-R latch, except that the condition where both inputs are HIGH is
now allowed. The truth table is shown in Table 12; the
waveforms are shown in Figure 19.
~
---u101730-
There are still some potential problems here forthe case
where J and K are both HIGH. If J and K are left HIGH for
too long, the output may change more than one time; if
left HIGH forever, the output will oscillate. Thus, J and K
should not be asserted for a time longer than the propagation delay of the latch. There are also potential race
conditions if J and K are not asserted and removed at
exactly the same time. If one of the inputs is raised
slightly ahead of the other, it may give the output time to
react, giving the wrong output once the second input is
raised. The same problem can occur if one input is lowered slightly before the other. This is illustrated in
Figure 20.
There are several ways to derive transfer functions for
J-K latches. Two can be derived directly from Kamaugh
maps, as shown in Figure 21 ; the others are not as obvious, and make use of the XOR gate described before.
The basic transfer functions are listed in Table 13.
Table 13. Transfer Functions for a J-K Latch
Figure 18. A J-K Latch
0+
=
+
Table 12. Truth Table for a J-K Latch
J
K
0
1
0
1
0
0
1
1
= 0
/0+
0+
:+: (J* /0
+ K*O)
= /0
:+: (/J*/O
+ /K*O)
/0+
Q
a
/0+
0+
Q+
0
1
J * /0
/K*O
= /J* /0
+ K*Q
= /0
:+: (J*/O
+ K*O)
= 0
:+: (/J*/O
+ /K*O)
J
K
Q
101730-
Figure 19. Behavior of a J-K Latch
6-14
Logic Reference Guide
AMD~
J
K
Q
Expected
Levels
a. Falling Edge Race Conditions
J
K
Q
-----r----
...
...
Expected
Levels
b. Rising Edge Race Conditions
J
K
Q
I-
-I
tPD OF Latch
•••
~
~
xxxx
c. Possible Oscillation
10173D-
Figure 20. Hazards Inherent in a J-K Latch
Logic Reference Guide
6~15
~
J
AMD
a
J
0
K
00
r-------,
a
0
I
o
K
T
00
01
11
10
10
a
a
-EJ=
T
I
a
L. _ _ _ _ _ _ _ .J
01
11
I
I
II
_
Q
101730-
Figure 22. A T-Type Latch
Table 14. The Truth Table for a T-Type Latch
T
/0+
a. Q+ = J*/O + /K*O
b. /0+
=/J*/O + K*O
101730-
Figure 21. Karnaugh Maps for a J-K Latch
T-Type Latches
T-type latches are formed by connecting the J and K inputs of a J-K latch together to form a single input. as
shown in Figure 22. This latch has two possible functions: hold the present state or invert the output. as
summarized in Table 14. 'T' stands for 'trigger' or
'toggle' depending on who you talk to. That is, when T is
HIGH. a change at the output is triggered; or. put another way, raising T causes the output to toggle.
T
a
:?j-------,r~
o
a
1
10
This Latch also has the problem that if T is left HIGH for
too long, the output will oscillate. However. since there is
only one input, the race condition problems of the J-K
latch have been eliminated. Unfortunately. this comes at
the cost of initialization. There is now no way to get the
output into a fixed state without knowing what the
previous state was. Thus. this device is not very useful
without some kind of initialization circuit.
The general waveforms for a T-type latch are shown in
Figure 23.
...
~ ~
~ ... 'llIXX
~
tPD OF Latch
F!gure 23. Behavior of a T-Type Latch
6-16
Logic Reference Guide
101730-
AMD~
From the Karnaugh map in Figure 24, we can generate
the following transfer functions:
T
Q+ = T*/Q
+ /T*Q
/Q+ = T*Q
+ /T*/Q
Q+ =Q:+:T
Q+ = /Q:+: /T
/Q+
/Q+
T
Q
o
o
'1
0
0
00
a. 0+ = T*/O + /T*O
The clock provides two basic advantages. It removes
the hazards inherent in the J-K and T flip-flops, since all
inputs will have settled by the time the clock edge arrives, and only one transition is possible for each clock
edge. The clock also allows the design of synchronous
systems, where all signals are coordinated with other
signals. The entire system is then regulated by the
clock.
/Q :+: T
Q: +: /T
Q
o
b. /0+
sit ion is. detected. A device is classified as positive
edge-triggered or negative edge-triggered, depending
on whether it responds to the rising or falling edge of the
clock signal, respectively. The behavior to a clocked
S-R flip-flop is illustrated in Figure 25.
= T*O + /T*/O
10173D-
Figure 24. Karnaugh Maps for a T-Type Latch
Clocked Flip-Flops
Latches can be modified by adding a clock input. The
purpose of the clock is to delay any output changes until
the clock signal changes. Whereas latch control inputs
(such as the gate) are level-sensitive, clock inputs are
generally edge-sensitive (or edge-triggered), meaning
that output transitions can occur only when a clock tran-
The basic behavior of the four flip-flops types does not
change with the addition of a clock; the output changes
are merely made to wait forthe clock edge. Thus, the basic transfer equations for most of the flip-flops are the
same. We can indicate the clocked nature of the flipflops by using the "registered" assignment ':=' instead
of'=.'
0-Type Flip-Flops
This is the only flip-flop type whose basic transfer characteristic changes, because the clock input replaces the
gate input. Thus the transfer equations become:
Q+:= D/Q+ := /D
That is, whatever data appears on the input will be transferred to the output after the next clock edge. The input
is not changed in any way.
Logic Reference Guide
6-17
~
AMD
The simplicity of this flip-flop makes it the most widely
used flip-flop. However, functions are sometimes more
conveniently expressed using J-K flip-flops, or using
T-type flip-flops. If we replace the D signal with the
transfer function for one of the other flip-flop types, we
can then emulate that flip-flop type in the D-type flip-flop.
This is equivalent to taking a latch and placing a clocked
D-type flip-flop after the latch output for synchronization.
Figure 26 illustrates how each flip-flop can be emulated
in a D-type flip-flop. The standard schematic symbols for
the flip-flop types are also shown.
Table 15 summarizes the transfer functions for all of the
flip-flop types. These functions can directly be used to
emulate a particular flip-flop type in a D-type flip-flop.
This can be particularly useful since D-type flip-flops are
available in most registered PLDs.
s
R
Clock
Op
On
10173D-
Figure 25. Behavior of a Clocked S-R Flip-Flop for Positive (Qp) and Negative
(Qn) Edge-triggered S-R Flip-Flops
6-18
Lagle Reference Guide
AMD~
0
a
a
Clock
a. Clocked 0-Type Flip-Flop
r------------------,I
J
I
I
K
Clock
J
K
a
0
a
I
I
I
I
a
a
J
a
a
K
a
a
T
a
I
L __________________ JI
b. Clocked J-K Flip-Flop
r------------------,I
T
I
I
I
I
a
0
a
I
I
I
T
a
Clock
I
a
a
I
L __________________ JI
c. Clocked T-Type Flip-Flop
r------------------,I
5
R
Clock
I
I
5
a
T
a
0
a
I
I
L __________________ JI
a
5
a
a
R
a
101730-
d. Clocked 5-R Flip-Flop
Figure 26. Clocked Flip-Flops. All can be Emulated with a D-Type Flip-Flop
Logic Reference Guide
6-19
~
AMD
Table 15. Clocked Flip-Flop Transfer Functions
D-Type
0+
0+
0+
J-K-Type
0+
0+
T-Type
S-R-Type
0+
0+
0+
'-
/0+
/0+
D
,- J*/O
+ /K*O
,- 0
:+: (J*/O
+ K*O)
,= /0
:+: (/J*/O
+ /K*O)
:= T*/O
+IT*O
.= O:+:T
.= /0 :+: IT
.- S
+ /R*O
/D
/J* /0
K*O
:= /0
:+: (J*/O
+ K*O)
'- 0
:+: (/J*/O
+ /K*O)
= T*/O
+ IT*'O
.- /0 :+:T
,-
+
/0+
/0+
/0+:
/0+
/0+
/0+
Binary Numbers
The concept of a number is taken for granted by most
people. And most people equate numbers in general
with the decimal system, with which we are most familiar, However, there is nothing particularly special about
the decimal system; the choice of system is actually
rather arbitrary. History has chosen the decimal system
for most humans.
For electronic systems, the binary system is more appropriate. It makes possible arithmetic and logical
calculations that would be much more difficult-likely
impractical-if implemented directly in a decimal system. Closely related to the binary system are the octal
and hexadecimal systems, which will also be discussed
here. Arithmetic is normally performed using binary
numbers in a computer. Octal and hexadecimal representations are generally used as a way to "abbreviate"
what might otherwise be lengthy binary numbers. This
will be seen when conversion is discussed below.
There are several terms which must be defined before
proceeding further. A number is an abstract entity
which is used to describe quantity, There are· many
ways of representing a number. Normally, the representation is designed around a base. The number is
expressed as a sum of multiples of the powers of the
base. Thedecima! system is a base-10 system, meaning that 10 is used as the base, The binary system is
base-2; the octal system is base-8; and the hexadecimal
system is base-16, The binary, octal, and hexadecimal
systems are closely related because 8 and 16 are both
powers of 2. When different bases are being used, a
number will often be followed by its base in subscript, to
indicate exactly what the base is. For example, the
6-20
,-
.- o :+:IT
'- R
+ /S*/O
decimal number25would be written 2510 if its base were
in doubt.
A number can thus be expressed in terms of some base
x as follows:
anXn+an_1X n- 1 + ... +alx1+aoxo+a-lx- 1 + ..•
+a-rnX- rn (1)
The numbers an ... a-m are called digits. The value of
each digit can range from 0 to x-1. Each digit is represented by a symbol, called a numeral. X numerals are
required to represent a number in base x. The most familiar numerals are the symbols '0,' '1,· .. .'9.' There are
ten of them, since they are used for the decimal system.
For binary numbers, only '0' and '1' are used; for octal
numbers, the numerals '0' through '1' are used, Hexadecimal numbers are more difficult, since sixteen
numerals are required. Therefore, the numerals '0'
through '9' are used to represent the quantities 010
through 910; the letters A through F are used to represent the quantities 1010 through 1510.
The number expressed by equation 1 is normally represented as a string of digits:
anan-l .•• alaO . a-l ... a-rn
The digits representing negative powers of the base are
separated from those representing non-negative powers by a point. In the decimal system, this is referred to
as a decimal point; in the binary system. it is referred to
as a binary point.
There are two basic classes of manipulation which will
be discussed: conversions between bases and arithme- .
tic within a base.
Logic Reference Guide
'AMD~
Here we see that the fraction will repeat, since we have
already multiplied 0.6 earlier. Thus
Converting Between Bases
Base-2 <-> Base-1 0
Converting a binary number to a decimal number is
accomplished by using equation 1 directly.
Example:
Converting 110100.0112 to decimal:
y
0.162510 = 0.00101001100110011 ... 2
For mixed numbers, it is necessary to calculate the
whole and fractional portions separately. Thus, for example, we know that
61.162510 = 111101.0010100110011 ... 2
110100.011
1.25 + 1.24 + 0.23 + 1.22+ 0.2 1+ 0.20+ 0.2-1+
1.2-2 +
1-2..,3
32 + 16 + 4 +.25 + .125
52.375
These are actually general procedures which can be
used to convert a decimal number into any base, and
vice versa.
Examples:
When converting whole numbers from decimal to binary, the decimal number is repeatedly divided by 2.
Integer division is used, so the quotients are "rounded
down" to the next integer. The remainders form the digits of the number. The least significant digit is the first
one calculated.
321.548 = 209.687510
Example:
2. Converting 106.1037510 to octal:
Converting 6110 to binary:
61/2 = 30
30/2 = 15
15/2 = 7
7/2 = 3
3/2 = 1
1/2 = 0
remainder = 1
remainder = 0
remainder = 1
remainder = 1
remainder = 1
remainder = 1
LSB
1. Converting 321.548 to decimal:
Y
= 3.8 2 + 2-8 1+ 1-80+ 5-8-1+ 4.8-2
= 192+16+1+.625+.0625
= 209.6875
106/8 = 13
13/8 = 1
118 = 0
LSB
remainder = 2
remainder = 5
remainder = 1
MSB
Thus, the whole portion is 1518.
MSB
6110 =1111012
When converting a decimal fraction into a binary fraction, the decimal number is multiplied by 2. This results
in a whole number and a fraction. The whole number is a
digit; the procedure is repeated on the new fraction. This
procedure is repeated until the fractional portion is zero.
If the procedure does not terminate, then the result is a
repeating fraction. The first digit calculated is the most
significant digit.
0.10375.8 = 0.83
0.83.8 = 6.64
0.64.8 = 5.12
0.12.8 = 0.96
0.96.8 = 7.68
0.68-8 = 5.44
whole
whole
whole
whole
whole
whole
portion
portion
portion
portion
portion
portion
=0
=6
=5
=0
=7
=5
MSB
At this point we have enough significant digits. We could
continue either until the procedure terminated, or until
the pattern started repeating. However, those last digits
are not likely to be significant. Thus, we can approximate by saying that...
106.1037510=152.0650758
Example:
3. Converting 31 F.A216 to decimal:
Converting .162510 to binary:
0.1625.2 = 0.3250
0.3250.2 = 0.65
0.65.2 = 1.3
0.3.2 = 0.6
0.6.2 = 1.2
0.2.2 = 0.4
0.4.2 = 0.8
0.8.2 = 1.6
0.6.2 = 1.2
whole
whole
whole
whole
whole
whole
whole
whole
whole
portion
portion
portion
portion
portion
portion
portion
portion
portion
=0
=0
=1
=0
=1
=0
=0
=1
=1
MSB
Y
= 31F.A216
= 3.162+ 1.161 + 15.160+ 10.16-1+2.16-2
= 768 + 16 + 15 + 0.625 + 0.0078125
= 799.6328125
31F.A216= 799.632812510
4. Converting 7689.10085410 to hexadecimal:
7689/16 = 480
480/16 =30
30/16 = 1
1/16 = 0
Logic Reference Guide
remainder = 9
remainder = 0
remainder = E
remainder = 1
LSB
MSB
6·21
~·AMD
Examples:
Thus, the whole portion is 1 E0916.
0.100854.16 = 1.613664
0.613664.16 = 9.818624
0.818624.16 = 13.097984
0.097984.16 = 1.567744
0.567744.16 = 9.083904
0.083904.16 = 1.342464
whole
whole
whole
whole
whole
whole
portion
portion
portion
portion
portion
portion
=1
=9
=D
=1
=9
=1
MSB
1. Convert 7324.348 to binary:
7
3
2
3
4
4
011 100
111 011 010 100
Thus 7324.348 = 111011010100.01112
Again, we likely have enough digits atthis point. The exact fraction could be either very long or a long repeating
pattern. For our purposes, we can approximate the
overall result as:
2. Convert 1A2.3F516 to binary:
1
A
2
0001 1010 0010
3
F
5
. 0011 1111 0101
Thus 1A2.3F516= 110100010.0011111101012
7689.10085410 = 1E09.19D19116
Binary Arithmetic
Binary <-> Octal, Hexadecimal
Converting between the binary-related systems is very
easy. The procedure consists of dividing the binary digits into groups, and replacing each group with an
appropriate digit. For this reason, octal and hexadecimal numbers are often used to shorten long binary
numbers.
To convert from binary to octal, group the digits by three,
starting on each side of the binary point, and then convert each group of three digits into its corresponding
octal digit. Leading and trailing zeroes may have to be
added to the left of the whole portion and the right of the
fractional portion, respectively, to make complete
groups of three binary digits.
Example:
Converting 11011010110101.0010011012 to octal:
Divide into groups of three digits:
011 011
3
3
010
2
110 101
6
5
001
001
101
1
1
5
Thus 11011010110101.0010011012 = 33265.1158
To convert from binary to hexadecimal, the digits are divided into groups of four digits, and then given their
corresponding hexadecimal digits. Again, leading and/
or trailing zeroes may be needed.
Example:
Converting 100101011101100.1101100012 to hexadecimal:
Divide into groups of four digits:
0100 101 0 111 0 11 00
4
A
E
C
.
One's Complement Representation
The one's complement of a binary number can be calculated by inverting all of the bits of the number. Fractions
are handled exactly the same way, although this is convenient only for fixed-point arithmetic. Floating-point
arithmetic requires other methods, which will not be discussed here.
Example:
Finding the one's complement of 110111.0101 :
110111.0101
001000.1010 (Inverting each bit)
Thus, the one's complement of 110111.0101
001000.1010.
D
8
0000
1111
8
To convert from octal or hexadecimal to binary, merely
expand each digit into its corresponding binary
representation.
is
The sign of a number is determined by the most significant bit. If the MSB is 0 the number is positive; if the MSB
is 1 , then the number is negative. Zero is represented by
all bits being zero. However, one normally thinks of zero
as being its own complement. But if we take the one's
complement of zero,
11011000 1000
Thus 100101011101100.1101100012 = 4AEC.D8816
6-22
Positive binary arithmetic is very simple, and completely
analogous to decimal arithmetic. However, if we are restricted to positive numbers, then we are also restricted
to addition. We need a means of representing negative
numbers. Using a dash '-' is unacceptable for representation in a computer. There are two general schemes
which can be used. In binary systems, they are referred
to as 15 complement and 25 complement representation, although they can be generalized for any base
system as diminished-radix complement and radix complement representation.
we see that 1111 is another representation of zero.
Thus, in an eight-bit representation, positive numbers
range from 00000001 to 01111111; negative numbers
range from 10000000 to 11111110. Note that there are
just as many negative numbers as positive numbers.
Logic Reference Guide
AMD~
This eight-bit code allows us to represent the numbers
.
from -127 to +127.
When performing addition with one's complement numbers, it is important to watch for overflow results.
Whenever an overflow occurs, a correction must be
made by adding 1 to the result.
In some cases, the results of an operation will not be
meaningful, since the intended result cannot be represented .. For instance, in the eight-bit system above,
adding 127 to 127 will give a meaningless result, since
254 cannot be represented in this system. Thus, the operation must be evaluated to ensure that the result is
meaningful.
Add 3 + 2:
+
3
+
2
---5
result meaningful
Add 7 + 7 (14 cannot be represented):
0111
....:...+_---=-01..:...1:....:,1
1110
7
_+_ _7
-1
result
meaningless
Subtract 3 from 7:
+
Examples:
All examples will use 4-bit systems. Thus, the range of
representable numbers is from -7 to +7.
0011
0010
0101
0111
1100
10011
+1
0100
7
~
4
overflow - add 1,
discard overflow
bit
Subtract 5 from 2:
+
0010
101 0
1100
2
....:.+_---'-5:.,.
-3
result meaningful
Subtract 6 from -5 (-11 cannot be represented):
1010
+,!....-_1.,:..::0=0...:...1
10011
+1
0100
-5
±--=.2..
4
overflow - add 1,
discard overflow bit
result meaningless
Subtract 5.25 from 3.5 (fixed point; requires 6 bits):
0011.10
+ 1010.10
1110.00
3.5
+ -5.25
-1.75
result meaningful
Subtract 7 from 7:
+
Logic Reference Guide
0111
1000
1111
7
. . :.+_ _
-..:...7
0
one of the
representations of 0
6-23
~
AMD
The advantage of one's complement code is the fact
that it is easy to compute the complement. However, the
fact that there are two representations for zero is a problem. In addition, the results of subtraction frequently
have to be adjusted for overflow by adding 1.
Two's Complement Representation
The two's complement of a binary number is more difficult to calculate. It is generated by taking the one's
complement, and then adding 1. Any overflow is discarded. Fractions are again handled in the same way,
although 1 is added to the least significant bit.
Examples:
Add 3 + 2:
+
110111.0101
001000.1010
+1
001000.1011
+
+
is
+
7
7
--=2
result meaningless
0111
1101
10100
7
-3
---4
+
overflow - discard
overflow bit
0010
1011
1101
2
+
-5
---=3
result meaningful
Subtract 6 from -5 (-11 cannot be represented):
The sign of a number is again determined by the most
significant bit. If the MSB is 0 the number is positive; if
the MSB is 1, then the number is negative. Zero is represented by all bits being zero. In this case, if we take the
two's complement of zero, we get:
1011
+
1010
------:--:10::-"1""!"0~1
-5
+
-6
---5
overflow - discard
overflow bit result
meaningless
Subtract 5.25 from 3.5 (fixed point; requires 6 bits):
0011.10
+ 1010.11
1110.01
(overflow is discarded)
giving only one representation for zero.
3.5
+ -5.25
-1.75
result meaningful
Subtract 7 from 7:
Thus, in an eight-bit representation, positive numbers
range from 00000001 to' 01111111; negative numbers
range from 10000000 to 11111111. This means that
there is one more negative number than there are positive numbers. So this eight-bit code allows us to
represent the numbers from -128 to +127.
Addition is handled in the same fashion as with one's
complement code, except that when an overflow occurs, the overflow bit is disregarded. No correction must
be made to the results. .
+
0111
1001
10000
7
-7
--0
+
overflow - disregard
overflow bit
The benefits of two's complement lie in the fact that
there is only one representation for zero, and the fact
that the results of operations never need adjusting due
to overflow. The disadvantage is the fact that it is harder
to generate the two's complement of a number.
After any operation, one must still make sure that the results are meaningful.
6·24
0111
0111
1110
Subtract 5 from 2:
001000.1011.
0000
1111
+1
0000
result meaningful
Subtract 3 from 7:
+
(take one's
complement)
Thus, the two's complement of 110111.0101
3
+
2
---5
Add 7 + 7 (14 cannot be represented):
Example:
Finding the two's complement of 110111.0101 :
0011
0010
0101
Logic Reference Guide
Signal Polarity
The polarity of signals, simple as it seems, turns out to
be a potentially confusing issue. With such phrases as
positive and negative logic, active HIGH, and active
LOW, and with one person saying "asserted," another
saying "active," and another saying "enabled," all of
which mayor may not be well defined, it is very difficult
to explain the relationships between signals. This can
also make the generation of the design file more difficult.
outputs. The possibilities are shown in Table 2. As an
example, if a signal X is to go LOW only when inputs A
and B are HIGH, and this function is to be implemented
in an active-HIGH device, then from the third row of Ta- (
ble 2, declare the output pin as X in the design file, and
use the equation:
In an attempt to sidestep the ambiguities in the language, this discussion contains tables instead of vague
descriptions. The tables list the various possibilities. If
you know what you want, you should be able to find how
to specify your equations from the tables. The issues of
input signal polarity, output signal polarity, and feedback
signal polarity are treated separately.
Feedback Polarity
x
=
/ (A*B)
Input Pin Polarity
Using feedback combines some of the polarity issues of
inputs with some of the polarity issues of outputs. It is
more difficult to use a simple example forthis type of circuit. In Table 3, an output is assumed to be fed back to
itself. The basic principles can be extended to any output feeding back to any other output. The waveform
shows the output level that is considered to be "TRUE,"
or "active."
.
.
Table 1 shows the relationships between the input pin
names and the use of the input in a Boolean equation.
As an example of how this table can be used, if you have
a signal called IA on your schematic, and you wish for
the output to go HIGH when both IA and B are HIGH,
then from the second row of Table 1, declare the pins as
IA and B in the design file, and use the equation:
As an example, if the equation for a pin IX has to contain
the inverse of the output, the output signal is to be active
when HIGH, and an active-LOW device is to be used,
then from the sixth row of Table 3, declare the output pin
as IX in the design file, and specify the Boolean
expression as:
Ix :
x = IA*B
The basic function A *B has been used throughout for
the purpose of illustration. The same procedure holds
regardless of the waveforms being used or generated.
=
f
(A,
X)
meaning that the Boolean equation uses X as an
input term.
Output Pin Polarity
The issue of output polarity is slightly more complicated
because of the issue of active-HIGH and active-LOW
Signal Polarity
6·25
;r1
AMD
Table 1. Input Pin Polarity
Desired
Waveform
Schematic
A
:8:8:8:8-
x
X
x
x
S
I
L
~
A
~
S
I
L
X
~
A
~
L
S
I
X
n
A
~
S
Boolean
Equation
~
X
X
6-26
Input Pin
Definition
I
L
~
Signal Polarity
A,S
X = A'S
lA, S
X = IA'S
A,S
X = IA'S
lA, S
X =A*S
AMD~
Table 2. Output Pin Polarity
Desired
Waveform
Schematic
x
:8:=E}-x
:=E}-x
x
:8-
A
S
Output Pin
Definition
Boolean
Equation
Device
Restriction
X
X
X = A*S
Active-HIGH
Devices
~
~
X
~
A
~
S
~
X
~
A
~
S
~
X
n
A
~
S
~
X
~
Signal Polarity
IX = I(A*S)
IX
IX
IX = A*S
X = I(A*S)
X
X
X = I(A*S)
IX = A*S
IX
IX
IX = I(A*S)
X = A*S
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
6·27
~
AMD
Table 3. Feedback Signal Polarity
Output Pin
Definition
Boolean
Equation
xJL
X
X
X=f(A,X)
IX = If(A,X)
xJL
X
X
X = f(A,/X)
IX = If(A,IX)
XLJ
X
X
X=If(A,X)
IX = f(A,X)
XLJ
X
X
X=If(A,/X)
IX = f(A,/X)
Desired
Waveform
Schematic
Device
Restriction
-po-
Ar-
X
--~
po-
Ar-
X
--~
po-
A-
-
---
X
~
po-
Ar-
6-28
X
---
~~
Signal Polarity
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
AMD~
Table 3. Feedback Signal Polarity (continued)
Schematic
Ar--
~
X
~
"""--
Ar--
A-
-
A-
-
x
~
~>
-
t
-
~
"-
Output Pin
Definition
xJL
IX
IX
Boolean
Equation
IX = f(A,IX)
X =1f(A,IX)
xJL
IX
IX
IX =f(A,X)
X = If(A,IX)
x---U-
IX
IX
IX = If(A,IX)
X = f(A,IX)
X
~>
r----
Desired
Waveform
It
x
x---U-
Signal Polarity
IX
IX
Device
Restriction
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
Active-LOW
Devices
Active-HIGH
Devices
IX = If(A,X)
X = f(A,IX)
Active-LOW
Devices
6-29
Glossary
Advanced
Micro
Devices
10KH (adj.) A family of ECl devices. Circuits are
temperature compensated. See also: ECl, 100K, temperature compensation.
100K (adj.) A family of ECl devices. Circuits are both
temperature and voltage compensated. They have
lower power dissipation and higher speed than their
10KH counterparts. See also: ECl, temperature compensation, voltage compensation, power dissipation,
10KH.
A
active high (adj.) See polarity.
active low (adj.) See polarity.
B
BCD (n.) Binary Coded Decimal. Decimal numbers in
4-bit binary.
binary (adj.) Having only two possible states, which can
be variously called on/off, I/O, true/false, high/low, etc.
bipolar (adj.) One of the two basic types of transistor. In
logiC design, used for TTL, ECl, and 12 l families. See
also: TTL, ECl, Fl, MOS.
bistable (adj.) Describes a system which has 2 stable
states. Any other state is unstable, and will eventually
change to one of the stable states. A flip-flop ,is the most
common electronic bistable circuit. See also: flip-flop,
astable, monostable.
ALS (adj.) Advanced l~w-power Schottky TTL family.
Characterized as a lower power version of the AS
family, and actually faster and lower power than the lS
family. See also: AS, lS, TTL, Schottky TTL.
bit 1. (n.) Binary Digit. One unit of binary information
2. (n.) A measure of the storage capacity of a memory
chip. See also: binary.
AND 1. (adj.) One of the three elementary logic functions. Result of the AND operation is true if and only if all
operands are true. 2. (v.t.) To perform the AND
operation.
blank (adj.) Describes the state of a program~able c~1I
after manufacturing, and before any programming, or, In
the case of an erasable device, after erasure. Opposite
of "programmed". See also: programmable cell, programmed, program, erase.
, AS (adj.) Advanced Schottky TTL family. High-speed
versions of the standard Schottky TTL family. Generally
use oxide isolated technology for very high speed. See
also: Schottky TTL, TTL, oxide isolation.
buffer (n.) A logic gate which performs the logic identify
function; i.e., the input is passed through unchanged.
Used to isolate various parts of a system, or to provide
voyage or current amplification.
assertive high (adj.) Same as "active high". See
polarity.
assertive low (adj.) Same as "active low". See polarity.
astable (adj.) Describes a system which has no stable
state. Such a system will oscillate. Astable circuits can
be used to generate timing and synchronizing clock signals. See also: bistable, monostable.
asynchronous 1. (adj.) Describes a sequential logic
system wherein operations are not synchronized to a
common clock. 2. (adj.) Describes signals whose behavior and timing are completely unrelated to a particular clock. Such signals can either be random or based on
another clock which has a different frequency. 3. (adj.)
Describes a communication protocol whereby the timing of various operations is not determined by a system
clock, but rather by events whose relationships are
known, but whose exact timing cannot be precisely predicted. See also: sequential, clock, synchronous.
6-30
C
chip (n.) A single piece of semiconductor material which
contains an integrated circuit. Sometimes called a die if
not in a package. See also: integrated circuit, die,
package.
clock 1. (adj.) A signal used to synchronize the operation of a system. 2.(adj.) An input to a clocked flip-flop.
The flip-flop will not change state until an appropriate
pulse appears at the clock input. 3. (n.) A circuit which
generates a clock signal. 4. (v.t.) To pulse the clock
signal or the clock input of a clocked flip-flop. See also:
flip-flop, clocked flip-flop.
clocked flip-flop (n.) A flip-flop that does not change
state until a clock signal is received. See also: flip-flop,
unclocked flip-flop, clock.
CMOS (n., adj.) Complementary MOS. A type of circuit
which makes use of both N-channel and P-channel
AMD~
MOS transistors. Many CMOS logic circuits consume
no power when not actually switching. See also: MOS,
NMOS, PMOS, standby power.
combinational (adj.) See combinatorial.
combinatorial (adj.) Refers to a logic circuit which implements logic functions of present input signals only.
Also called combinational. See also: sequential. .
complement 1. (adj). Refers to a signal which is identical to some reference Signal, except that it is of opposite
polarity. Opposite of '1rue". 2. (v.t.) To invert. See also:
true, polarity, invert.
complementary (adj.) Refers to logic device outputs
which implement identical logic functions, but with
opposite polarities. Used on some PlDs and ECl devices. See also: polarity, PlD, ECL.
D
decimal (adj.) Based on the number 10.
die (n.; plural: dice) Same as a chip, particularly before
being placed in a package. See also: chip, package.
digit (n.) Any number from 0 to 9.
DIP (n.) Dual In-line Package. The most common integrated circuit package. It is rectangular in shape, with
widths ranging from .300 inch to .900 inch, and has vertical leads along the length. See also: integrated circuit,
package.
disable 1. (v.t.) To turn off a three-state output. 2. (v.t.)
To inhibit another function, such as "disabling the clock".
See also: three-state, enable.
download 1. (v.t.) To pass data from one machine to a
less complex machine. 2. (n.) The act of downloading
data. See also: upload.
E
Eel (n., adj.) Emitter Coupled Logic family. An extremely high-speed family of bipolar logiC and memory
devices. See also: bipolar.
EE cell (E2 cell) (n.) A floating gate cell which can be
both programmed and erased with electrical signals.
EEPROM (n.) Electrically Erasable Programmable
Read-Only Memory. A nonvolatile read-only memory
device which can be erased and reprogrammed, both
with special electrical signals. See also: program, erase,
EPROM, PROM, ROM, RAM, nonvolatile.
enable 1. (v.t.) To turn on a three-state output. 2. (adj.)
By itself, usually refers to a pin which is used to enable a
three-state output. Also called "output enable". 3. (adj.)
Used with other function names, indicates a qualifier or
inhibitor of the function. For example, "clock enable" is a
function which qualifies the clock function. 4. (v.t.) To
allow a signal which has been disabled to function; for
example, "enabling the clock" removes any restraint
. which may disable the clock signal. See also: threestate, disable.
EPROM (n.) Erasable Programmable Read-Only Memory. A non-volatile read-only memory device which can
be erased and reprogrammed. Erasure is accomplished
by exposing the die to ultraviolet light for a period of
time. Die must be packaged in a windowed package to
allow erasure. See also: program, erase, EEPROM,
PROM, ROM, RAM, non-volatile, windowed package.
erase 1. (v.t.) To return a programmed device to its
blank state. Opposite of "program". 2. (v.t.) To return an
individual programmable cell to its blank state. See also:
blank, programmable cell, program.
•
ESD (n.) Electrostatic Discharge. The natural physical
event of the transferring of electrical charges. If uncontrolled, ESD can destroy or degrade both CMOS and bipolar semiconductor devices with inadequate on-chip
protection circuitry and/or insufficient packaging and
handling protection. See also: ESDS Device, CMOS,
bipolar.
ESDS Device (n.) Electrostatic Discharge Sensitive Device. A device which is sensitive to damage at certain
levels of ESD. Three classes exist at ESD levels of up to
1999 V, to 3999 V and above 4000 V. See also: ESD.
F
finite state machine (FSM) (n.) A machine which can
be in one of a finite number of states. Often used for logic
circuits which sequence through various states. Such a
circuit is referred to as sequential. See also: sequential.
flip-flop (n.) A bistable digital circuit. The simplest variety is called an S-R flip-flop. Other types are J-K,T, and
D-type. May be unclocked or clocked. See also: bistable, unclocked flip-flop, clocked flip-flop.
floating gate (n.) A gate on an MOS transistor which is
not connected to anything. Used to store charge; forms
the basis of UV cells and EE cells. See also: MOS, gate,
UV cell, EE cell.
FPGA 1. (n.) Field Programmable Gate Array. A highdensity PlD with multiple levels of logic and programmable interconnect. 2. (n.) Field Programmable Gate
Array. An array of logic gates whose configuration can
be programmed by the customer. The gates are often
NAND gates, but can also be NOR gates. See also:
gate, program, NAND, NOR.
FPlA (n.) Field Programmable Logic Array. See PLA.
FPlS (n.) Field Programmable Logic Sequencer. A programmable logic device which is intended for sequencing or state machine applications. See also: finite state
machine.
Glossary
6·31
~AMD
functionally complete (adj.) Refers to a logic operation
or group of operations from which any complex logic
function can be built. The NAND and NOR operators are
functionally complete. See also: NAND, NOR.
fuse (n.) As used in programmable logic, usually refers
to a lateral metal link fuse. See also: lateral fuse.
fuse map (n.) A graphic representation of the contents
of a PLD. The state of each connection (fuse or other
programmable cell) is represented, usually with "X" indicating an intact connection, and ,,_If indicating an open
connection. See also: PLD, programmable cell.
G
gate 1. (n.) A fundamental logic element. The elementary gates provide NOT, AND, and OR logic functions.
2. (n.) The control terminal of a gated D-type latch. See
also: latch, gated latch.
gate array (n.) A logic device which consists of an array
of logic gates (usually NAND) which can be interconnected during fabrication. A custom metallization pattern is used to configure the desired functions. See also:
gate, NAND, metallization.
gate equivalency (n.) A rough measure of the complexity of a digital logic integrated circuit. Indicates the approximate number of discrete logic gates that would be
needed to implement the same function. See also: gate.
gated latch (n.) Generally refers to an unclocked D-type
flip-flop which has a control signal called a gate. When
the gate is "open", the flip-flop output follows the data input. When the gate is "closed", the output holds its current state. Also called a transparent latch. See also: flipflop, unclocked flip-flop, gate, latch.
H
HAL ~ device (n.) Hard Array Logic device. A version of
a PAL device which is configured during fabrication with
a custom metallization pattern. HAL is a registered
trademark of Advanced Micro Devices. See also: PAL
device, metallization.
Invert (v.t.) To perform the logical NOT function on a
digital signal. To reverse the polarity of a digital signal.
See also: polarity, NOT.
Inverter (n.) A logic gate which performs logical inversion, or the NOT operation. See also: gate, NOT.
I/O (Input/Output) 1. (n.) The methods and equipment
used to pass information into and/or out of a system or
device. 2. (adj.) On a programmable logic device, a pin
which can function as an input and/or an output.
J
JEDEC 1. (n.) Joint Electronic Device Engineering
Council. A council which creates, approves, arbitrates,
and/or oversees industry standards for electronic
devices. 2. (adj.) In programmable logic, refers to a
computer file containing information about the
programming of a device. The file format is a JEDECapproved standard. Used for downloading to programmers. See also: program, programmer, download.
junction Isolation (n.) A bipolar integrated circuit fabrication technique which uses P~N functions to isolate
transistors. This is the original integrated circuit technology, and is being supplanted by oxide isolation in places
where speed is critical. See also: oxide isolation,
bipolar.
K
Karnaugh map (K-map) (n.) A graphic tool for minimizing sum-of-products or product-of-sums logic functions.
Useful for up to six logic variables. See also: sum-ofproducts, product-of-sums.
L
latch 1. (n.) A type of flip-flop. Means different things to
different people. In general, an unclocked flip-flop.
Sometimes used to refer specifically to a gated D-type
flip-flop. 2. (v.t.) To capture a signal in a latch. See also:
flip-flop, unclocked flip-flop, gate, gated latch.
latch up (v.t.) To enter the latch-up condition. See also:
latch-up.
J2L (ilL) (n., adj.) Integrated Injection Logic. A less common bipolar logic design technique which, when used, is
found primarily in portions of LSI and VLSI circuits. See
also: bipolar, LSI, VLSI.
latch-up (n.) A condition in which a circuit draws uncontrolled amounts of current, and certain voltages are
forced, or "latched-up" to some level. Used especially in
reference to CMOS devices, which can latch up if the
operating conditions are violated. See also: CMOS,
latch up.
Integrated circuit (n.) An electronic device which has
many transistors and other semiconductor components
integrated onto one piece of silicon. Often abbreviated
IC.
lateral fuse (n.) A thin metal link which is disconnected
when programmed. Connected in the blank state, disconnected in the programmed state. Usually just called
a "fuse". See also: program, programmed, blank.
6-32
Glossary
AMD~
LCC (n.) Leadless Chip Carrier. A ceramic integrated
circuit package having no leads. Connection is made to
metal contacts which are flush with the package. See
also: integrated circuit, lead, package.
lead (n.) [led] A metal conductor which provides a connection from the inside of an integrated circuit package
to the outside world for soldering or other mounting
techniques. See also: integrated circuit.
logic array (n.) Generally an array of programmable
cells which attach inputs to logic gates of a specified
type. See also: program, gate, programmable cell.
logic simulation (n.) A means whereby a logic design
can be evaluated on a computer before actually being
built. The computer simulates the behavior of the components to predict the behavior of the overall circuit.
LS (adj.) Low-power Schottky TTL family. Lower power
version of the standard Schottky TTL family. See also:
TTL, Schottky TTL.
LSI (adj.) Large-Scale Integration. A rough measure of
the complexity of a digital circuit. Characterized as having 100-5000 gate equivalents for logic chips, or 1 K16 K bits for memory chips. See also: gate equivalent,
bit, VLSI, SSI, MSI.
M
macrocell (n.) Typically the output cell of a PLD, containing a flip-flop and path multiplexers.
maxterm (n.) A sum in the canonical product-of-sums
form. Each maxterm contains every input variable, in
either true or complemented form. See also: product-ofsums, true, complement~
metallization (n.) The process of connecting the various elements of an integrated circuit or printed circuit
board by placing a layer of metal overthe entire waferor
board, and then selectively etching away unwanted
metal. A photolit~ographic mask defines the pattern of
connections. See also: integrated circuit, wafer, printed
circuit board.
mlnterm (n.) A product in the canonical sum-of-products form. Each minterm contains every input variable,
either in true or complemented form. See also: sum-ofproducts, true, complement.
monolithic (adj.) In the electronics industry, refers to a
circuit which has been integrated onto one semiconductor chip. Integrated circuits are monolithic by definition.
See also: integrated circuit.
monostable (adj.) Describes a system which has 1 stable state. Any other state is unstable, and will eventually
change to the stable state. The most common monostable circuit is a "one-shot". See also: bistable, astable.
MOS (n., adj.) Metal-Oxide-Semiconductor transistor.
One of the two basic types of transistor. In logic design,
used for NMOS, PMOS, and CMOS families. See also:
NMOS, PMOS, CMOS, bipolar.
MSI (adj.) Medium-Scale Integration. A rough measure
of the complexity of a digital logic circuit. Characterized
as having 10-100 gate equivalents. See also: gate
equivalent, SSI, LSI, VLSI.
N
NAND (adj.) Not AND. A commonly used logic gate
which is equivalent to an AND gate followed by an
inverter. The NAND logic operation is functionally complete.See also: gate, inverter, functionally complete,
AND.
negative logic (n.) A physical implementation of logic
wherein a low voltage level represents a logic 1, or
"true", and a high voltage level represents a logic 0, or
'1alse". See also: positive logic, polarity.
NMOS (n., adj.) N-channel MOS. A type of circuit which
makes exclusive use of N-channel MOS transistors.
See also: MOS, PMOS, CMOS.
non-volatile (adj.) Refers to memory devices which do
not lose their contents when power is removed. See
also: volatile.
NOR (adj.) Not OR. A logic gate which is equivalent to
an OR gate followed by an inverter. The NOR logic operation is functionally complete. See also: gate, inverter,
functionally complete, OR.
NOT (adj.) One of the three elementary logic functions.
Unary operation whose result is true if and only if the operand is false.
o
OR 1. (adj.) One of the three elementary logiC functions.
Result of the OR operation is false if and only if all operands are false. 2. (v.t.) To perform the OR operation.
OTP (adj.) One-Time Programmable. Refers to programmable devices which are UV-erasable, but which
are not packaged in windowed packages. As a result,
there is no way to erase the device, making it programmable only once. See also: program, erase, UV-erasable, windowed package.
oxide Isolation (n.) A bipolar integrated circuit fabrication technique which uses silicon oxide to isolate transistors. This results in higher speed and density. See
also: junction isolation, bipolar.
Glossary
6-33
~AMD
p
package (n.) The encasement which protects a die and
provides convenient electrical contact to the die. Materials used are generally ceramic or plastic compounds.
There are a variety of shapes and sizes. See also: die.
PAL~
device (n.) Programmable Array Logic device. A
PLD which implements logic via a programmable AND
logic array driving a fixed OR logic array. PAL is a registered trademark of Advanced Micro Devices. See also:
program, logic array, sum-of-products, PLD, AND, OR.
PLA (n.) Programmable Logic Array. A programmable
logic device which implements sum-of-products logic
via programmable AND logic array driving a programmable OR logic array. See also: program, logic array,
sum-of-products, AND, OR.
a
PLCC (n.) Plastic Leaded Chip Carrier. A molded plastic
integrated circuit package with leads shaped like a "J"
(J-leads).lntended for surface mounting. See also: integrated circuit, lead, surface mounting, package.
PLD (n.) Programmable Logic Device. Generic term for
a logic device whose function can be configured by the
customer after purchase. See also: program.
PMOS (n., adj.) P-channel MOS. A type of circuit which
makes exclusive use ot P-channel MOS transistors.
See also: MOS, NMOS, CMOS.
polarity (n.) Specifies the sense of "active" and "inactive", or '1rue" and "false" in a digital signal. "Active high"
represents '1rue" as a high signal; "active low" represents ''true'' as a low signal.
positive logic (n.) A physical implementation of logic
wherein a high voltage level represents a logic 1, or
''true'', and a low voltage level represents a logic 0, or
''false''. See also: negative logic, polarity.
power dissipation (n.) The amount of electrical power
used by a device. Calculated as the product of the operating voltage and current. Measured in watts (W) or milliwatts (mW), as appropriate. Sometimes incorrectly
used to refer to the operating current only.
printed circuit board (PC board, PCB) (n.) A board for
assembling electrical components. Component connections are made by metal traces which have been fabricated through a metallization process. See also: trace,
metallization.
product-of-sums (PaS) (adj.) A representation of a
logic function where the input signals are individually inverted (if necessary), then ORed together to form sums
which are ANDed together. Any combinatorial logic
function can be represented in product-ot-sums form.
See also: sum-of-products, combinatorial, AND, OR.
6-34
product term (pterm, p-term) (n.) An AND gate in a
PLD which implements sum-of-products logic. See also:
sum-of-products, PLD, AND, gate.
product term sharing (n.) See product term steering.
product term steering (n.) A means whereby product
terms in a PAL device can be routed to one of two device
outputs, instead of being dedicated only to one output.
Sometimes called "product term sharing". See also:
product term, PAL device.
program 1. (v.t.) As used in programmable logic, to
configure a blank device so that it can perform some desired function. Applies to memory and logic devices.
Opposite of "erase". 2. (v.t.) To change an individual
programmable cell from a blank state to a programmed
state. See also: blank, programmable cell, programmed, erase.
programmable cell (n.) Any of a variety of cells which
can be altered by applying certain electrical signals.
Various types are lateral and vertical fuses, UV cells, E2
cells, and even RAM .cells. All but RAM cells are nonvolatile. See also: lateral fuse, vertical fuse, UV cell, E2
cell, RAM cell, non-volatile, volatile.
programmed (adj.) Describes the state of a programmable cell or device after programming. OPPOSite
"blank".
programmer (n.) A device or machine used for configuring, or "programming", PLDs or PROMs. See also:
program, PLD, PROM.
PROM (n.) Programmable Read-Only Memory. A nonvolatile memory device whose contents are programmed by the customer. Once programmed, it cannot
be erased. Also functions as a PLD with a fixed AND
logic array which drives a programmable OR logic array.
See also: program, erase, EEPROM, EPROM, ROM,
RAM, non-volatile, AND, OR, logic array.
R
RAM (n.) Random-Access Memory. Sometimes called
read/write memory. A type of memory device which can
be written to and read at any time. Such memory is volatile. Actually a misnomer, since most types of memories
can be accessed randomly. The distinguishing feature
is the fact that RAM is designed specifically to be written
to in normal usage. See also: ROM, volatile.
RAM cell (n.) A cell which is used make one bit of volatile memory in a RAM. Can also form the basis of a programmable logic connectivity array. See also: RAM,
volatile.
Glossary
AMD
;t1
ROM (n.) Read-Only Memory. A nonvolatile memory
device which has its contents defined when manufactured. No changes can be made to the memory
contents. See also: PROM, EPROM, EEPROM, RAM,
nonvolatile.
common clock. 2. (adj.) Describes signals whose behavior and timing are synchronized to a clock. 3. (adj.)
Describes a communication protocol whereby the timing of various operations is determined by a system
clock. See also: sequential, clock, asynchronous.
S
T
Schottky TTL (adj.) Family of TIL devices which make
use of Schottky diodes for higher speed. See also: TI~.
security fuse (n.) A PLD feature which allows a user to
"secure" the PLD after programming. This prevents subsequent copying of the contents of the PLD. See also:
PLD, program.
semlcustom (adj.) Refers to a circuit which has been
partially designed by the device vendor, and partially designed, or configured, by the customer. Primary types
are PLDs, gate arrays, and standard cell circuits. See
also: PLD, gate array, standard cell.
sequential (adj.) Refers to a logic circuit whose operation depends both on present input signals and previous
operations, or states. Requires some kind of memory
(usually flip-flops) for remembering past states. See
also: flip-flop, combinatorial.
SSI (adj.) Small Scale Integration. A rough measure of
the complexity of a digital logic circuit. Characterized as
having less than 10 gate equivalents. See also: gate
equivalent, MSI, LSI, VLSI.
standard cell (n.) A method of designing semicustom or
full custom circuits whereby predefined cells are
brought together to provide the specified function. Unlike gate arrays, all· fabrication steps are customized,
instead of just the metallization step. See also: semicustom, gate array, metallization.
standby power (n.) The power consumed by a device
when none of the device inputs are switching. Usually
used in reference to CMOS devices, many of which consume practically no standby power. See also: CMOS.
sum-of-products (SOP) (adj.) A representation of a
logic function where the input signals are individually inverted (if necessary), then ANDed together to form
products which are ORed together. Any combinatorial
logic function can be represented in sum-of-products
form. See also: product-of-sums, combinatorial, AND,
OR.
surface mounting (n.) A printed circuit board assembly
technique whereby the integrated circuit packages are
placed on the board with no leads protruding through to
the other side. Packages can thus be mounted on both'
sides of the board. See also: printed circuit board, lead,
through-hole mounting.
synchronous 1. (adj.) Describes a sequential logic system wherein all operations are synchronized to a
temperature compensation (n.) A circuit feature which
allows some electrical characteristics to remain relatively constant with some variation in operating
temperature.
three-state (adj.) A type of logic device output which
can be in one of three-states: HIGH, LOW, and OFF, or
High-Z (high impedance). When enabled (on), performs
as a normal binary output. When disabled (off), acts as
an open pin. See also: enable, disable, binary.
through-hole mounting (n.) A printed circuit board assembly technique whereby the leads of the various components extend through holes in the board. These leads
are then soldered from the opposite side of the board.
See also: printed circuit board, lead, surface mounting.
trace 1. (n.) During logic simulation, the behavior of a
signal or group of signals. The results can sometimes be
stored in a "trace file" on disk for later analysis. 2. (n.) A
thin layer of metal on a printed circuit board which provides connections between components. Performs the
function of a wire. See also: logic simulation, printed circuit board.
transparent latch (n.) See gated latch.
TRI-STATE$ (adj.) See three-state. TAl-STATE is a
registered trademark of National Semiconductor Corp.
true (adj.) Refers to a signal which is identical to some
reference signal, with the same polarity. Opposite of
"complement". See also: complement, polarity.
TTL (adj.) Transistor-Transistor Logic family. The most
widely used family of bipolar logic devices. The name refers to the particular circuit design technique used. See
also: bipolar.
u
unclocked flip-flop (n.) A flip-flop that changes state as
soon as the appropriate controls are applied.See also:
flip-flop, clocked flip-flop.
upload 1. (v.t.) To pass data from one machine to a
more complex machine. 2. (n.) The act of uploading
data. See also: download.
UV cell (n.) A floating gate cell which can be erased by
exposure to ultraviolet (UV) light. See also: floating
gate, erase.
Glossary
6-35
~AMD
UV-erasable (adj.) Refers to devices or programmable
cells which can be erased when exposed to ultraviolet
(UV) light for a period of time. See also: programmable
cell, erase.
v
vertical fuse (n.) A transistor arranged such that the
emitter and base are shorted together when programmed. Disconnected in the blank state, connected
in the programmed state. See also: program, programmed, blank.
VLSI (adj.) Very Large Scale Integration. A rough measure of the complexity of a digital circuit. Characterized as
having 5000 or more gate equivalents for logic chips, or
16K or more bits for memory chips. See also: gate
equivalent, bit, SSI, MSI, LSI.
6-36
volatile (adj.) Refers to memory devices which lose
their contents when power is removed. See also: nonvolatile.
voltage compensation (n.) A circuit feature which allows some electrical characteristics to remain relatively
constant with some variation in the supply voltage.
W
wafer (n.) A round slice of very pure silicon which is
used in the fabrication of integrated circuits. Several
circuits can be built on one wafer. See also: integrated
circuit.
windowed package (n.) A package which has a quartz
window in the lid directly overthe die. This makes it possible to expose the die to ultraviolet light for erasing the
device.See also: erase, die, package.
Glossary
Worldwide Application Support
Advanced
Micro
Devices
The Worldwide Application Support Group is dedicated
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problems which might occur when the design reaches
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6-37
~
AMD
AMD~
~AMD
AMD~
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the industry. For specific testing details, contact your local AMD sales representative. The company assumes no responsibility for the use of any
circuits described herein.
~
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RECYCLED &
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10 1993 Advanced Micro Devices, Inc.
101730
6/18/93
BAN·SOM-7/93
Printed in USA
Family
Part Number
Standard
Packages
STANDARD PAL DEVICES
16RS
Technology
tPD
ns
Icc
mA
Page
TTL
4.5
210
2-3
PAL16LS-4
PAL16RS-4
PAL16R6-4
PAL16R4-4
28J
PAL16LS-5
PAL16RS-5
PAL16R6-5
PAL16R4-5
20P,J
5
210
PAL16LS-7
PAL16R8-7
PAL16R6-7
PAL16R4-7
20P, J, D
7.5
1S0
20P, J
10
180
20N, J, NL
15
180
PAL16LSB-2
PAL16R8B-2
PAL16R6B-2
PAL16R4B-2
PAL16LSA
PAL16R8A
PAL16R6A
PAL16R4A
25
90
25
180
PAL16L8B-4
PAL16R8B-4
PAL16R6B-4
PAL16R4B-4
35
55
PAL16L8D/2
PAL16RSDI2
PAL16R6D/2
PAL16R4D/2
PAL16L8B
PAL16R8B
PAL16R6B
PAL16R4B
20RS
I
PAL20LS-5
PAL20R8-5
PAL20R6-5
PAL20R4-5
24P,2SJ
5
210
PAL20L8-7
PAL20R8-7
PAL20R6-7
PAL20R4-7
24P, 28J,
240
7.5
210
PAL20L8-10/2
PAL20R8-10/2
PAL20R6-10/2
PAL20R4-10/2
24P,2SJ
10
210
24NS, 28NL,
24JS
15
210
PAL20L8B-2
PAL20RSB-2
PAL20R6B-2
PAL20R4B-2
25
105
PAL20L8A
PAL20R8A
PAL20R6A
PAL20R4A
25
210
PAL20L8B
PAL20R8B
PAL20R6B
PAL20R4B
2-121
1SP8
AmPAL18P8B
AmPAL18PSAL
AmPAL1SPSA
AmPAL1SP8L
20P,J
15
25
25
35
180
90
1S0
90
2-155
22P10
AmPAL22P10B
Am PAL22P 1OAL
AmPAL22P10A
24P,2SJ
15
25
25
180
90
180
2-249
ADVANCED
MICRO
DEVICES, INC.
901 Thompson Place
P.D. Box 3453
Sunnyvale,
California 94088-3453
(408) 732-2400
TWX: 910-339~9280
TELEX: 34-6306
APPLICA TlONS HOTLINE &
LITERATURE ORDERING
USA (800) 222-9323
USA (408) 749-5703
JAPAN 011-81-3-3346-7561
UK & EUROPE 44-(0)256-811101
TOLL FREE
USA (800) 538-8450
FRANCE 0590-8621
GERMANY 0130-813875
ITALY 1678-77224
RECYCLED &
RECYCLABLE
Printed in USA
BAN-80M-6/93-0
10173D
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