1993_Altera_Data_Book 1993 Altera Data Book

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Data Book

August 1993

Data Book
August 1993

A-DB-0793-01

Altera, MAX, and MAX+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation:
AHDL, MAX+PLUS II, PL-ASAP2, PLD5-HPS, PL5-ADV, PLS-ES, PLS-FLEX8, PL5-FLEX8/HP, PLS-FLEX8/SN, PLS-HPS, PLS-STD, PLS-WS/HP,
PL5-WS/SN, PLSM-5K, PLSM-7K, PLSM-8K, PLSM-ADE, MCMap, Turbo Bit, Classic, FLEX, FLEX 8000, MAX 5000, MAX 5000A, MAX 7000, FastTrack,
EP330, EP61O, EP610A, EP610T, EP91O, EP910A, EP9lOT, EP181O, EP181OT, EP1830, EPM5016, EPM5032, EPM5064, EPM5128, EPM5128A, EPM5130,
EPM5192, EPM5192A, EPS448, EPS464, EPM7032, EPM7032V, EPM7064, EPM7096, EPM7128, EPM7160, EPM7192, EPM7256, EPF8282, EPF8282V,
EPF8452, EPF8820, EPF81188, EPF81500, EPB2001. Product design elements and mnemonics are Altera Corporation copyright.
Altera Corporation acknowledges the trademarks of other organizations for their respective products or services mentioned in this document,
specifically: Tango, TangoPLD, and TangoSchematic are trademarks of Accel Technologies, Incorporated. AADELAY, AAMAX, ATGEN are trademarks
of Acugen Software, Incorporated. PAL and PALASM are registered trademarks of Advanced Micro Devices, Incorporated. PILOT is a trademark of
Advin Systems Incorporated. Susie is a trademark of Aldec, Incorporated. Verilog is a registered trademark and Concept, Composer, Leapfrog,
RapidSIM, Synergy, SystemPGA, Verilog-XL, and VHDL-XL are trademarks of Cadence Design Systems, Incorporated. Data I/O and FutureNet are
registered trademarks and ABEL and ABEL-FPGA are trademarks of Data I/O Corporation. Exemplar Logic and CORE are registered trademarks of
Exemplar Logic, Inc. F5-High Density and FS-PALibrary are trademarks of Flynn Systems Corp. Hilo is a trademark of GenRad. Intergraph, ACE,
ACEPlus, AdvanSIM, AdvanSIM-1076, DLAB, and Synovation are trademarks of Intergraph. HP is a registered trademark of Hewlett-Packard
Company. IBM and AT are registered trademarks and IBM PC-AT, IBM PC-XT, PS/2, and Micro Channel are trademarks of International Business
Machines Corporation. ISDATA and LOG/iC are registered trademarks of ISDATA GmbH. SmartModel is a registered trademark of Logic Modeling
Incorporated. CUPL is a trademark of Logical Devices, Incorporated. X Windows System is a trademark of Massachusetts Institute of Technology.
Mentor Graphics is a registered trademark and AutoLogic, Design Architect, PLDSynthesis, QuickSim, and QuickSim II are trademarks of Mentor
Graphics Corporation. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. MINC and PLDesigner are registered
trademarks and PLDesigner-XL is a trademark of Minc Incorporated. Motif is a registered trademark of Open Software Foundation, Incorporated.
OrCAD is a trademark of OrCAD Systems Corporation. Motive is a trademark of Quad DeSign. CADAT, System Expert, and Visula are trademarks of
Racal-Redac. SPARCstation is a trademark of SPARC International, Inc. and is licensed exclusively to Sun Microsystems, Inc. Sun and OpenWindows
are trademarks of Sun Microsystems, Inc. Synopsys is a registered trademark and FPGA Compiler, DC/Pro, DC/Expert, and VSS Simulator are
trademarks of Synopsys, Inc. VHDL Designer, Viewlogic, ViewPLD, Viewsim, and Viewdraw are registered trademarks and Viewsim/PLD is a
trademark of Viewlogic Systems, Incorporated.
Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its
customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is
current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty. Testing
and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by
government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the
contrary, Altera assumes no liability for Altera applications assistance, customer's product design, or infringement of patents or copyrights of third
parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other
intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are
used.
Altera's products are not authorized for use as critical components in life support devices or systems without the express written approval of the
president of Altera Corporation. As used herein:
1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a
Significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of
the life support device or system, or to affect its safety or effectiveness.
Products mentioned in this document are covered by one or more of the following u.s. patents: 4,020,469; 4,609,986; 4,617,479; 4,677,318; 4,713,792;
4,774,421; 4,831,573; 4,864,161; 4,871,930; 4,899,067; 4,899,070; 4,903,223; 4,912,342; 4,930,107; 4,969,121; 5,045,772; 5,066,873; 5,091,661; 5,097,208;
5,111,423; 5,121,006; 5,128,565; 5,138,576; 5,144,167; 5,162,680; 5,166,604; 5,200,920; 5,220,214; 5,220,533; 5,237,219; and certain foreign patents. Additional
patents pending.

lit

~.,

Printed on Recycled Paper

About this Data Book
I August 1993
This data book provides comprehensive information about Altera's
FLEX 8000, MAX 7000, MAX 5000 jEPS464, Classic, Configuration EPROM,
and EPS448 devices and MAX+PLUS II development tools. For information
on Micro Channel EPLDs and the MCMap development system, refer to
the Altera Micro Channel Adapter Handbook.
For immediate assistance on technical questions, call:
Altera Applications Hotline
(800) 800-EPLD

For information on product availability, pricing, and order status, contact
your local Altera representative or distributor listed in Sales Offices,
Distributors & Representatives in this data book.
If you have questions that cannot be answered by the local representative
or distributor call:

Altera Marketing
(408) 894-7000

or contact Altera by:
Fax
(408) 248-6924

I Altera Corporation

Page iii

Contents
I August 1993
About this Data Book ...................................................................................... iii
Product Index ................................................................................................... ix

Section 1

Introduction ........................................................................................................ 1
Altera Corporation is a leading manufacturer of easy-to-use, highdensity programmable logic devices. These devices can be configured
and programmed in-house for a wide variety of end-uses. This section
contains an introduction to Altera device technology and a component
selection guide.

Section 2

FLEX 8000 .............................................................................................. 27
Altera's SRAM-based Flexible Logic Element MatriX (FLEX) 8000
family combines the benefits of EPLDs and FPGAs. The fine-grained
architecture and high register count of FPGAs is combined with the
high system speed and predictable interconnect delays of EPLDs to
make FLEX 8000 the ideal programmable logic family for a wide
range of applications. This section includes information on the EPF8282,
EPF8282V, EPF8452, EPF8820, EPF81188, and EPF81500 devices.

Section 3

MAX. 7000 ......................................................................................................... 67
The MAX 7000 family uses an enhanced second-generation MAX
architecture. These EPROM- and EEPROM-based devices have logic
densities up to 5,000 usable gates, pin counts up to 208, and in-system
speeds up to 125 MHz. This section includes information on the
EPM7032, EPM7032V, EPM7064, EPM7096, EPM7128, EPM7160,
EPM7192, and EPM7256 devices.

Section 4

MAX 5000/EPS464 ............................................................................... 147
The MAX 5000/EPS464 family includes devices with up to 192
macrocells (3,750 usable gates) in packages with up to 100 pins. With
the highest logic-to-pin ratio of any high-density PLD family,
MAX 5000 and EPS464 devices are ideal for replacing multiple PAL
and TTL devices in applications requiring significant amounts of
buried logic and minimum board space. This section includes
information on the EPM5016, EPM5032, EPM5064, EPS464, EPM5128,
EPM5128A, EPM5130, EPM5192, and EPM5192A devices.

I Altera Corporation

Page v

I Contents
Section 5

Classic .................................................................................................. 233
The industry-standard Classic family of devices offers high-speed,
low-power logic integration with pin-to-pin logic delays (tpD ) as low
as 7.5 ns and internal counter rates as high as 125 MHz. Classic devices
have logic densities up to 48 macrocells (900 usable gates) in packages
with up to 68 pins. This section includes information on EP330, EP61O,
EP610A, EP610T, EP610 MIL-STD-883-compliant, EP910, EP910A,
EP910T, EP1810, EP1810T, and EP1810 MIL-STD-883-compliant
devices.

Section 6

3.3-Volt ................................................................................................ 299
Many circuit designs require not only higher performance and
integration, but also lower power consumption. This section includes
information on the 3.3-V EPM7032V and EPF8282V devices, both of
which meet the low-power requirements of 3.3-V applications such as
notebook computers and personal communicators.

Section 7

Function-Specific ................................................................................. 319
This section contains information on Altera's function-specific devices,
including EPS448 Stand-Alone Microsequencer (SAM) EPLDs used
for implementing high-performance controllers, user-configurable
Micro Channel devices, and Configuration EPROMs used for
configuring FLEX 8000 devices.

Section 8

Military .................................................................................................349
Altera's military devices are manufactured in proven EPROM,
EEPROM, and SRAM technologies, providing an optimum
combination of reliability, speed, density, and low power consumption.
Altera offers military devices that meet military-temperature-range,
MIL-STD-883B, and DESC requirements. This section discusses military
product availability and the MIL-STD-883B qualification process.

Section 9

MPLD .................................................................................................... 355
Altera's Mask-Programmed Logic Devices (MPLDs) allow a design
engineer to trade off flexibility and cost throughout the life of a
design. The designer can prototype with ceramic devices, ramp up
initial production with lower-cost plastic versions of the devices, and
move into high-volume production with MPLDs. This seamless
transition through technologies can dramatically increase profit over
the life of a product. This section describes the process of converting
programmable logic devices to MPLDs.

I Page vi

Altera Corporation

Contents

Section 10

Device Operation ................................................................................. 363
Altera's advanced device architecture and sophisticated
MAX+PLUS II development system give customers device
performance that is consistent from simulation to application.
Regardless of which device is chosen, systems should be designed
with care to obtain maximum performance with minimum difficulties.
This section includes information on device operating requirements,
FLEX 8000 device configuration, and timing specifications for Altera
devices.

Section 11

Development Tools .............................................................................. 435
Altera's state-of-the-art MAX+PLUS II development system supports
the Classic, MAX 5000/EPS464, MAX 7000, and FLEX 8000 device
families. Designs can be entered with schematic capture, the Altera
Hardware Description Language (AHDL), waveforms, and standard
CAE tools. Logic synthesis and minimization automatically optimize
the logic of a design. Design verification and timing analysis can be
performed with MAX+PLUS II or with standard CAE tools. This
section describes MAX+PLUS II features and provides a selection
guide for various product configurations and add-on products.

Section 12

General Information ............................................................................. 465
This section includes information on device quality and reliability;
Altera's quad flat pack (QFP) socket and carrier; device package
outlines; ordering codes; technical support; and Altera sales offices,
distributors, and representatives.

Section 13

Glossary ............................................................................................... 539

Section 14

Index ..................................................................................................... 549

IAltera Corporation

Page vii

Product Index
I August 1993

Components
Classic devices
EP330 .......................................................... 245
EP610 .......................................................... 249
EP610 MIL-STD-883-Compliant ............. 265
EP610A ....................................................... 257
EP610T ........................................................ 261
EP910 .......................................................... 269
EP910A ....................................................... 275
EP910T ........................................................ 279
EP1810 ........................................................ 283
EP1810 MIL-STD-883-Compliant ........... 295
EP1810T ...................................................... 291
Configuration EPROM devices
EPC1064 ..................................................... 341
EPC1213 ..................................................... 341
FLEX 8000 devices
EPF8282 ........................................................ 58
EPF8282V ................................................... 313
EPF8452 ........................................................ 56
EPF8820 ........................................................ 54
EPF81188 ...................................................... 52
EPF81500 ...................................................... 50
Mask-Programmed Logic Devices ................. 357
MAX 5000/EPS464 devices
EPM5016 .................................................... 161
EPM5032 .................................................... 167
EPS464 ........................................................ 219
EPM5064 .................................................... 175
EPM5128 .................................................... 181
EPM5128A ................................................. 189
EPM5130 .................................................... 193
EPM5192 .................................................... 203
EPM5192A ................................................. 211
MAX 7000 devices
EPM7032 ...................................................... 83
EPM7032V .................................................. 303
EPM7064 ...................................................... 93
EPM7096 ...................................................... 99
EPM7128 .................................................... 107

IAltera Corporation

MAX 7000 devices (cant.)
EPM7160 .................................................... 117
EPM7192 .................................................... 127
EPM7256 .................................................... 137
Micro Channel devices (EPB2001) ................. 339
SAM devices (EPS448) ..................................... 321

Development Tools
MAX+PLUS II ................................................... 437
PLAESW-xxxx .................................................. 452
PLDS-HPS ......................................................... 450
PLS-ADV ........................................................... 450
PLS-ES ................................................................ 450
PLS-FLEX8 ......................................................... 450
PLS-HPS ............................................................ 450
PLS-STD ............................................................. 450
PLS-WS /HP ...................................................... 450
PLS-WS/SN ...................................................... 450
PLSM-5K ............................................................ 450
PLSM-7K ............................................................ 450
PLSM-8K ............................................................ 450
PLSM-ADE ........................................................ 450
PLSM-TA ........................................................... 450
PLSM-WS/HP .................................................. 450
PLSM-WS /SN ................................................... 450
programming hardware
FLEX Download Cable ........................... .454
PL-ASAP2 (Altera Stand-Alone
Programmer) ......................................... 454
PLM- & PLE-prefix adapters ................. .454
PL-MPU (Master Programming Unit) .. .453
PLP5 & PLP6 (Logic Programmer
cards) ...................................................... 453

QFP Carrier, Development Socket & Tools
PL-EXTx (QFP device extraction tool) .......... 486
PL-SKT/Qxxx (development socket) ........... 480
QFP carrier ........................................................ 480
QFP carrier removal tool ................................ .483
Page ix

Contents
I August 1993

Section 1

Introduction
Introduction ........................................................................................................ 3
Component Selection Guide .......................................................................... 17

IAltera Corporation

Page 1

Introduction
IAugust 1993, ver. 1

Data Sheet

Programmable Logic Devices (PLDs) are digital, user-configurable
integrated circuits (ICs) used to implement custom logic functions. PLDs
implement any Boolean expression or registered function using the generic
logic structures in the devices. In contrast, off-the-shelf logic ICs, such as
TTL devices, provide a specific logic function and cannot be modified to
meet individual circuit-design requirements.
PLDs were once viewed only as an alternative to discrete logic and custom
or semi-custom devices such as ASICs and gate arrays. In recent years,
however, PLDs have become the preferred choice. As PLD costs have
decreased through high-volume manufacturing and the use of aggressive
process technologies, PLD manufacturers have been able to offer devices
with higher integration, higher performance, and lower cost per function
than most discrete and custom devices.
Programmable logic encompasses all digital logic circuits configured by
the end-user, including simple 20-pin PAL/GAL devices, Field
Programmable Gate Arrays (FPGAs), function-specific PLDs, Complex
PLDs (CPLDs), and Erasable Programmable Logic Devices (EPLDs). PLDs
are offered in many different architectures, and a variety of memory
technologies for configuring the devices. Figure 1 shows where Altera's
general-purpose devices fit into the programmable logic device market.

Figure 1. Altera General-Purpose Logic Oevices

IAltera Corporation

Page 3

Data Sheet I

Introduction

Altera PLDs

Altera offers four families of general-purpose PLDs: FLEX 8000, MAX 7000,
MAX 5000 /EPS464, and Classic. These families use either sum-of-products
architecture or look-up table (LUT) architecture. Each architecture offers
advantages for implementing and fitting logic into a device and for meeting
performance requirements. Altera uses three different memory technologies
in its devices: EPROM, EEPROM, and SRAM. The Classic, MAX 5000/
EPS464, and MAX 7000 families use sum-of-products architecture and
EPROM or EEPROM technologies. The FLEX 8000 family uses an LUT
architecture and SRAM technology. See Table 1.

Table 1. Altera Device Architecture & Technology
Device Family

Architecture

Technology

FLEX 8000

Look-Up Table

SRAM

MAX 7000

Sum-ot-Products

EPROM, EEPROM

MAX 5000/EPS464

Sum-ot-Products

EPROM

Classic

Sum-ot-Products

EPROM, EEPROM

MAX 7000, MAX 5000/EPS464, and Classic devices are targeted for
combinatorially intensive logic designs. These families provide logic
densities ranging from 150 to 5,000 usable gates, and pin counts ranging
from 20 to 208 pins. The FLEX 8000 family provides logic density from
2,500 to 24,000 usable gates and pin counts from 84 to 304 pins (see
Figure 2). In FLEX 8000 devices, the high performance, predictable
interconnect delays and ease-of-use of EPLDs are combined with the high

Figure 2. Pin Count &Density in Altera Device Families

304

208

Pins
100

900

3,800

5,000

24,000

Usable Gates

Page 4

Altera Corporation

IData Sheet

Introduction

register counts, low standby power, and in-circuit reconfigurability of
FPGAs, making these devices the ideal solution for high-density, registerintensive designs.
The EPROM- and EEPROM-based Classic and Multiple Array MatriX
(MAX) devices are non-volatile erasable devices. EPROM devices are
erased with UV light, while EEPROM devices are erased electrically.
SRAM-based FLEX 8000 devices can be configured in-circuit during powerup. They consume low power and offer a high degree of flexibility to
support different application requirements.
All Altera device families use CMOS process technology, which provides
lower power dissipation and greater reliability than bipolar technology.
To facilitate continual improvement, Altera migrates products to advanced
process technologies as soon as these technologies become viable and can
support reliable manufacturing. Currently, Altera offers devices built on
an advanced 0.65-micron technology.
For high-volume production, Altera offers Mask-Programmed Logic
Devices (MPLDs) as low-cost alternatives to high-density PLDs. MPLDs,
which are masked versions of programmable logic devices, offer a unique
tum-key approach that eliminates the engineering-intensive tasks required
for custom and semi-custom devices. The quick turn-around for MPLD
conversion guarantees fast time-to-market.

Altera Device
Architectures

The following descriptions of Altera's device families identify the key
features and benefits of each family.

Classic Family
Industry Standard,
Low Density

Altera's original family of EPLDs is the Classic family, with densities up to
900 usable gates and pin counts up to 68 pins. Composed of single arrays of
globally interconnected logic, the industry-standard Classic family offers a
low-cost solution for low-density applications. Some devices in the Classic
family offer a unique" zero-power mode," which allows these devices to
draw only microamps of current at standby, making them ideal for lowpower applications.

MAX 5000/EPS464 Family
Lowest Cost,
Medium Density

IAltera Corporation

MAX 5000 jEPS464 EPLDs provide a comprehensive, cost-effective solution
for designs intensive in combinatorial logic. The MAX 5000 architecture
uses several Logic Array Blocks (LABs) connected by a Programmable
Interconnect Array (PIA) to pack up to 3,750 usable gates and 100 pins into
a single device. This family also features a high logic-to-pin ratio, making it
ideal for buried-logic-intensive designs, such as state machines.

Page 5

Introduction

Data Sheet

MAX 7000 Family
Highest Performance,
High Density

The MAX 7000 family is the fastest, high-density programmable logic
family in the industry, with up to 5,000 usable gates. Based on a secondgeneration MAX architecture, these devices support counter frequencies
as high as 125 MHz and propagation delays as fast as 7.5 ns. With pin
counts up to 208 pins, MAX 7000 devices offer a high pin-to-Iogic ratio,
making them ideal for 1/ O-intensive designs. MAX 7000 devices also offer
a programmable speed/power control, so that each macrocell can be
configured for high-speed or low-power operation. Thus, speed-critical
sections of a design can be programmed to run at the fastest speed, while
the remainder operates at low power.

FLEX 8000 Family
Highest Density,
Register-Intensive

FLEX 8000 programmable logic represents a new type of programmable
logic architecture, combining the high register counts of FPGAs with the
fast, predictable interconnect of EPLDs. FLEX 8000 devices provide up to
24,000 usable gates, 2,266 flipflops, and 304 pins. The SRAM-based
FLEX 8000 family features low standby power and in-circuit
reconfigurability, making it ideal for such applications as PC add-on cards,
battery-powered instruments, and multi-purpose telecommunication cards.
Figure 3 shows the architecture evolution of AHera devices and illustrates
how the interconnect structure has evolved to maintain high performance
at even the highest densities.

Figure 3. Altera Architecture Evolution
Classic

MAX 5000

DID
o

':"'.":::',,","",,
i".,<,··.,',·,.,. · ,.".,·',.· ".,.,'" . .'". '·"••.
, ,., .
,""-." '::""";""
"

Global
Interconnect

Page 6

... [J

0
0

Programmable
Interconnect
Array

FLEX 8000

MAX 7000

DD
DD
DD
DO

DO
DO
DD
DO

Enhanced
Programmable
Interconnect
Array

...

FastTrack
Interconnect

Altera Corporation

joata Sheet

Advantages of
Programmable
Logic

Introduction

Designers generally develop a logic circuit with three distinctly different
device options: discrete logic devices (TTL, CMOS, etc.), custom or semicustom devices (gate arrays and ASICs), or programmable logic devices.
The best choice is the option that can meet the most design requirements.
Table 2 lists a number of important requirements, and ranks the three
device options according to how effectively they meet these requirements.

Table 2. Oevice Options Ranking
Requirement
Speed
Density
Cost
Development Time
Prototyping & Simulation Time
Manufacturing Time
Ease of Use
Future Modification
Inventory Risk
Development Tool Support

PlD

•
•
•
•
•
•
•
•
•
•

Discrete
logiC
0
0
0

•
•
•
•
•

Custom
Device

•
•
• (1)
0

0
0
0
0
0

•

Notes:
(1)
•
•

Advantages of
Altera
Programmable
Logic

Cost-effective only in high-volume production
= very effective
= adequate
= poor

Altera programmable logic devices not only offer the general benefits of
PLD technology, but other advantages as well. These advantages-based
on innovative architectures, aggressive technologies, and the MAX+PLUS II
programmable logic development environment-are:

Higher performance
High-density logic integration
Greater cost-effectiveness
Shorter development cycles

Higher Performance
Performance is a function of process and architecture. Altera devices are
manufactured on state-of-the-art CMOS processes, which offer the fastest
possible delays. Altera devices are also designed with continuous
interconnection schemes, which provide fast, consistent signal delays
throughout the device.
IAltera Corporation

Page 7

Introduction

Data Sheet

High-Density Logic Integration
Designers often seek the highest possible logic integration for the designs
they develop, usually to reduce board space and cost. Also, existing
designs often undergo secondary development cycles that aim to reduce
cost by integrating more logic into fewer devices. In both cases,
programmable logic devices with high logic integration capability offer an
excellent solution. Altera devices, which range in density from 300 to
24,000 usable gates, can easily integrate existing logic, whether it be a few
or a few hundred discrete logic devices, PLDs, FPGAs, or even custom
devices. This high integration capability provides higher performance and
reliability, as well as lower system cost.

Greater Cost-Effectiveness
Altera continually strives to refine product development and manufacturing
processes. The expertise accumulated over more than a decade of leadership
has made both process technologies and the manufacturing flow highly
efficient, and has enabled the company to offer the most cost-effective,
highest-performance programmable logic available.

Short Development Cycles with MAX+PLUS II Software
Time is the most precious resource for many design engineers. Large sums
of money are wasted on projects that are not completed on schedule and
therefore miss a window of opportunity. Consequently, the shorter the
development cycle, the better. Altera's fast, intuitive, and easy-to-use
MAX+PLUS II software can shorten the development cycle considerably.
Design entry, processing, verification, and device programming together
take only a few hours, potentially allowing several complete design
iterations in one day. Figure 4 illustrates a typical PLD development cycle
in the MAX+PLUS II development environment. Times shown are
representative of a relatively sophisticated 10,OOO-gate logic design.
MAX+PLUS II enables designers to target different Altera device families
without further modification to a design. The software automatically
partitions and optimizes the design for the selected architecture. See
"MAX+PLUS II Development Tools" later in this data sheet.

Figure 4. Development Cycle for Altera Devices
Device
Programming
less than
1 hour

Page 8

5t030
minutes

2 hours

less than
2 minutes

•

Altera Corporation

IData Sheet
Architecture
Basics

Introduction

The basic building block of all Altera general-purpose devices is the logic
cell. It contains combinatorial logic and a programmable flipflop that can
emulate D, T, JK, and SR functionality or can be bypassed for purely
combinatorial operation. Logic cells in Classic, MAX 5000/EPS464, and
MAX 7000 devices are called macrocells; in FLEX 8000 devices, they are
called logic elements (LEs). Complete details on macro cells and logic
elements are available in the individual device family data sheets in this
data book.
Signals enter the device via dedicated inputs or I/O pins configured as
inputs. Inputs to each logic cell are supplied by the input pins and other
logic cells. Signals drive out of the device via the I/O pins. Outputs of logic
cells are available as inputs to other logic cells, or may be driven out of the
device via II 0 pins. A continuous interconnect structure provides
connections between logic cells and between pins and logic cells. This
structure ensures consistent, predictable delays across all densities- and
architectures.
Altera device data sheets contain timing models for precise calculation of
all worst-case timing delays. This calculation is possible because of the
continuous routing structure of the devices. In contrast, a segmented
routing structure, such as that found in FPGAs, provides connections by
linking a series of short routing segments. This series of connections
introduces unpredictable delays and signal skew, preventing the use of
timing models for device performance estimates.

EPLD
Architecture

IAltera Corporation

Altera Classic, MAX 5000 /EPS464, and MAX 7000 EPLDs implement logic
using a sum-af-products structure. Each macrocell contains a set of wideinput AND-gates (called product terms or p-terms), an OR-gate, and a
programmable register for sequential functions (see Figure 5). For specific
details on each EPLD family's macrocell structure, refer to the appropriate
data sheet in this data book.

Page 9

Data Sheet I

Introduction

Figure 5. Typical EPLD Macrocell
from
Inputs

from
I/O

from
Macrocells

EPROMor~~~~~~~~~~~

I/O Output Enable

EEPROM
Cell

Preset

Programmable
Flipflop

Clear

Global Clock

'----------......y----------~
Logic Array

Combinatorial Functions
A product term is an n-input AND gate, where n is the number of possible
inputs. Figure 6 shows three different representations of the same logic
function: Circuit A is presented in traditional logic notation; Circuit B has
been modified to a sum-of-products notation; and Circuit C is written in
AND-array notation.

Figure 6. AND-Array Notation (Part 1 of 2)
EPLD schematics frequently use a 1-input AND-gate notation as shorthand for n-input
AND gates. A dot represents a connection between an input (vertical wire) and one of the
inputs to an n-input AND gate. The absence of any dots on the input to the AND gate
indicates an unused AND gate whose output is at a logic O.

Circuit A: Typical Circuit

1'~::~'j('
1 = NOT

12
13

::
Page 10

* 12 * 113 + 11 * 14

0
Altera Corporation

I Data Sheet

Introduction

Figure 6. AND-Array Notation (Part 2 of 2)
Circuit B: Circuit A with
Complementary Output
Buffers

* 12 * 113 + 11 * 14

12 13 14

Circuit C: Circuit B with
8-lnput AND Gates in
AND-Array Notation

12 13 14

Outputs of the product terms are tied to the inputs of an OR gate to
compute the sum. Since all combinatorial logic can be reduced to a sum-ofproducts expression, the generic AND-OR array of Circuit C can produce
any Boolean function. (The actual product terms in AHera devices are
much wider than the 8 inputs shown.)
Product terms can also be used to generate complex control signals for use
with the programmable register (Clock, Clear, Preset, and Clock Enable) or
the Output Enable signal for the I/O pins. These signals are called array
control signals.
To support programmable inversion and complex functions, the output of
the OR gate feeds one input to a two-input XOR gate (see Figure 5). This
architectural feature allows the software to generate inversions wherever
necessary, without wasting macrocells for simple functions. Figure 7 shows
an OR function that requires six product terms in its current form. By using
the programmable XOR gate and De Morgan's inversion, the OR function
can be transformed into a NAND function using a single product term:
A+B+C+D+E+F

/(/A*/B*/C*/D*/E*/F)

This inversion from OR to AND translates the equation and reduces the
number of fixed OR terms required in the logic array. MAX+PLUS II
software automatically applies De Morgan's inversion and other logic
synthesis techniques to optimize the use of the logic array.

IAltera Corporation

Page 11

Data Sheet

Introduction

Figure 7. Logic Minimization with De Morgan's Inversion

~· :~:P
1~~~entation
De Morgan's
Inversion

Logic 1

A
B

D
E
F

MAX 5000 and MAX 7000 macro cells support very complex combinatorial
functions. They provide allocatable product terms, called expander product
terms, that can be used for functions requiring more product terms than
are normally found in a macrocell. The MAX 5000 architecture supports
shareable expander product terms, called shared expanders, that feed back
into the logic array to support two levels of logic. The MAX 7000 architecture
provides shareable expanders as well as parallel expanders. Parallel
expanders are product terms that are shared between adjacent macrocells.
They allow the MAX+PLUS II software to increase the effective number of
inputs to the OR gate in the sum-of-products. See the family device data
sheets in this data book for more detailed information on shared and
parallel expanders.

Sequential Functions
Programmable flipflops in the macrocells are used to implement sequential
functions. MAX 5000 EPLD flipflops can also be configured as flowthrough latches. If the flipflop is not required for macrocelliogic, it can be
bypassed. Most macrocell flipflops also have an asynchronous Clear and
Preset that allows emulation of most TTL functions.
In all Altera EPLDs except the EP330, each internal flipflop can be clocked
from a dedicated global Clock pin (Le., a Clock pin whose signal does not
pass through the logic array), any input or I/O pin, or any internal logic

Page 12

Altera Corporation

I Data Sheet

Introduction

function. For each flipflop, a multiplexer selects either a pin or productterm source for the Clock.
EPLD flipflops are positive-edge-triggered with data transitions that occur
on the rising edge of the dedicated global Clock. When the Clock is driven
by a product term, flipflops can be configured for either positive- or
negative-edge-triggered operation. In addition, product-term Clocks allow
gated Clock and Clock Enable logic to be implemented. Global Clock
signals have faster Clock-to-output delay times than internally generated
product-term Clock signals. In MAX 7000 devices, a Clock Enable signal
can synchronize groups of registers on asynchronous control signals.

I/O Pins
The EPLD I/O control block contains a tri-state buffer controlled either by
a macrocell product term or by a dedicated input pin. The I/O pins can be
configured as inputs, outputs, or bidirectional pins. Most EPLDs have dual
feedback, i.e., the macro cell feedback is decoupled from the I/O pin
feedback. With the dual feedback feature, a buried function can be
implemented in the macrocell while the 1/ 0 pin is used simultaneously as
an input. This ability ensures that logic in an EPLD is not wasted due to
I/O pin requirements. Applications that require bus-oriented functions or
many buried flip flops-such as counters, shift registers, and state
machines-are easily accommodated by the programmable I/O control
block.

Routing
Routing resources in product-term-based devices connect the input and
I/O pins to macro cells and also provide a macrocell-to-macrocell path.
Most of the Classic devices and the smallest MAX 5000 devices are fully
interconnected, ensuring a global routing path for all signals. Higherdensity EPLDs use a Programmable Interconnect Array (PIA) that routes
only the signals necessary for a specific function. By providing optimized
routing resources, Altera's high-density EPLDs do not suffer the speed
and die-size penalty typically incurred in globally routed high-density
devices.

FLEX
Architecture

IAltera Corporation

The FLEX 8000 architecture implements logic with a large matrix of logic
elements (LEs). Each LE contains a four-input look-up table (LUT) to
compute any function of four variables, and dedicated carry and cascade
chains to support complex combinatorial functions. The LE also contains a
programmable register for sequential logic functions (see Figure 8). The
fine-grained structure of the LE makes FLEX 8000 devices ideal for registerintensive applications.

Page 13

Data Sheet I

Introduction

Figure B. FLEX BODO Device Logic Element Architecture
Cascade-In

Carry-In

r·.···.·.·---·····.·----------------.------·.-.· ... · ... __ ...... .

DATA1-~: ~

LEOut

DATA2 -~:
LUT
DATA3
L _ _-----'
DATA4
..................................................................

'--------'

CLRN
LABCTRL 1 - - - - - I
LABCTRL2 - - - - - I
Clock
Select
LABCTRL3 - - - - - I
LABCTRL4 - - - - - I
Cascade-Out

Carry-Out

Combinatorial Functions
Combinatorial functions are implemented with the four-input LUT and
two dedicated high-speed data paths (carry chain and cascade chain) in the
LE. The carry chain supports very fast carry generation for arithmetic
functions and counters, while the cascade chain supports wider-input
functions such as multiplexers and decoders.

Sequential Functions
Programmable flipflops are used for sequential functions such as counters,
state machines, and shift registers. Flipflops can be clocked from a dedicated
global Clock pin, any input or I/O pin, or any internal logic function.
Although flipflops in FLEX 8000 devices are positive-edge-triggered, the
FLEX architecture supports programmable inversion on all control signals
that allows negative-edge triggering for any Clock source.

I/O Pins
I/O pins can be configured as input, output, or bidirectional pins. A
register associated with each I/O pin can be used as an input or output
register. The FLEX architecture also provides a tri-state buffer associated
with each 1/ 0 pin that can be controlled by a dedicated input pin, any I/O
pin, or intemallogic.

Page 14

Altera Corporation

IData Sheet

Introduction

Routing
Routing in the FLEX architecture is provided by the FastTrack Interconnect,
a continuous interconnect structure consisting of horizontal and vertical
routing paths. This global routing structure allows LEs to communicate
with each other and with a wide variety of I/O pins, providing high
performance and low-skew interconnect of all signals in FLEX 8000 devices.

MAX+PLUS II
Development
Tools

Altera achieves maximum device performance and density not only with
advanced processes and innovative logic architectures, but also through
state-of-the-art design tools. The MAX+PLUS II programmable logic
development software provides an architecture-independent design
environment that supports designs for Altera's general-purpose
programmable logic device families, ensuring easy design entry, quick
processing, and uncomplicated device programming.
Using MAX+PLUS II, designers no longer need to master the complexities
of device architectures. MAX+PLUS II translates their design---created
with familiar design entry tools, such as schematic capture or a high-level
behavioral language-into the format required by the target architecture.
Since intimate architectural knowledge is built into Altera development
tools, designers do not need to manually optimize their design, and are
thus able to complete their designs much more rapidly. With MAX+PLUS II,
users can take a logic circuit from design entry to device programming in a
matter of hours. Design processing is typically completed in minutes,
allowing several complete design iterations in a single day.

Design Entry, Design Processing & Device Programming
MAX+PLUS II offers a full spectrum of logic design capabilities (see
Figure 9). Designers are free to combine text, graphic, and waveform
design entry methods while creating single- or multi-device hierarchical
designs. The MAX+PLUS II Compiler performs minimization and logic
synthesis, fits the design into one or more devices, and generates
programming data. Design verification with functional and timing
simulation and delay prediction for speed-critical paths is available, as
well as multi-device simulation across multiple device families. Altera and
a number of programming hardware manufacturers offer hardware for
programming the devices.

IAltera Corporation

Page 15

I Introduction

Data Sheet I

Figure 9. MAX+PLUS II Design Environment
Design Entry

Design Processing

Verification & Programming

Graphic
Design Entry
Text Design
Entry

EDIF
LPM
Others

Timing
Simulation
Functional
Simulation

MAX+PLUS /I Compiler

Waveform
Design Entry

Design-Rule
Checking

Hierarchical
Design Entry

Logic
Synthesis &
Fitting

Standard CAE Design Entry:
Cadence
Mentor Graphics
OrCAD
Synopsys
Viewlogic
Others

Multi-Device
Partitioning
Automatic
Error
Location

Multi-Device
Simulation

S
JJ

Timing
Analysis

EDIF
Verilog
VHDL
Others

Standard CAE
Design Verification:
Cadence
Mentor Graphics
Logic Modeling
Synopsys
Viewlogic
Others

Device
Programming

Access to Various Platforms & Other CAE Tools
Altera is committed to enable designers to work in the logic development
environments most familiar to them. MAX+PLUS II interfaces to a wide
variety of other CAE tools-provided by companies such as Cadence,
Mentor Graphics, OrCAD, Synopsys, and Viewlogic-via EDIF, LPM,
Verilog, and VHDL. The MAX+PLUS II Compiler runs on both PC and
workstation platforms, making MAX+PLUS II the industry's only platformindependent, architecture-independent programmable logic design
environment. The ACCESS alliance, which Altera has formed with many
CAE tool vendors, guarantees smooth interfaces between Altera products
and the products of the ACCESS partners, and ensures timely support of
Altera devices with these tools.

The Logical
Alternative

I Page 16

The advanced architectures and processing technologies used in Altera
devices provide the greatest performance and highest density available in
programmable logic devices. The sophisticated, highly integrated
MAX+PLUS II development environment gives the designer the tools with
which to extract this superior performance and density. Together, Altera
devices and Altera development tools are the logical choice for all
programmable logic designs.

Altera Corporation

Component
Selection Guide
I August 1993, ver.

Introduction

Data Sheet

This selection guide lists devices available from Altera:

o
o
o

o
o

FLEX 8000 devices
Configuration EPROMs
MAX 7000 devices
MAX 5000 /EPS464 devices
Classic devices
3.3-Volt devices
Function-specific devices
SAM devices
Micro Channel devices
Military-qualified devices
Classic devices
MAX 5000 devices
MAX 7000 devices
FLEX 8000 devices

For detailed information on these products, refer to the appropriate sections
in this data book. For a list of all Altera products, refer to the Product Index.
For information on Altera's programmable logic development systems, see
the MAX+PLUS II Selection Guide.

I Altera Corporation

Page 17

I Component Selection Guide

Data Sheet

Table 1 provides information on the FLEX 8000 family of register-intensive,
high-density, programmable logic devices. These devices combine the
fine-grained architecture and high register count of FPGAs with the high
speed, predictable interconnect delays, and ease-of-use of EPLDs. FLEX 8000
devices are fabricated on CMOS SRAM technology.

FLEX 8000
Devices

Table 1. FLEX 8000 Devices
Device

See Note (1)

Package Temp. Speed Technology Flipflops
(2)
(3) Grade

Logic Dedicated
Elements Inputs

Number
of Pins

1/0

EPF8282

L, T

-2

SRAM

282

208

64, 74

EPF8282

L, T

C, I

-3

SRAM

282

208

64, 74

84, 100

EPF8452

L,G, Q C

-2

SRAM

452

336

64,116

84, 160
84, 160

EPF8452

L,G,Q

EPF8820

G,R,S C

EPF8820

G,R,S C, I

C, I,M

84,100

-3

SRAM

452

336

64,116

-2

SRAM

820

672

116,148 160,192,208,225 (4)

-3

SRAM

820

672

116,148 160,192,208,225

EPF81188 G,R

-2

SRAM

1188

1008

180

232,240

EPF81188 G,R

C,I,M

-3

SRAM

1188

1008

180

232,240

EPF81500 G,R

-2

SRAM

1500

1296

177,204 240, 288, 304 (5)

EPF81500 G,R

C, I

-3

SRAM

1500

1296

177,204 240,288,304

Notes to tables 1 through 8 are listed on page 23.

Configuration
EPROMs

Table 2 provides information on Configuration EPROMs, which are serial
EPROMs that are used to configure FLEX 8000 devices.

Table 2. Configuration EPROMs for FLEX 8000 Devices
Device

Package Temp.
(2)
(3)

EPC1064

P,L,

EPC1213

P,L

Description

T C,I,M 64K x 1-bit serial EPROM for configuring FLEX 8000 devices
C,I,M 213K x 1-bit serial EPROM for configuring FLEX 8000 devices

Number
of Pins
8,20,32
8,20

Notes to tables 1 through 8 are listed on page 23.

Page 18

Altera Corporation

Component Selection Guide I

I Data Sheet

MAX 7000
Devices

Table 3 provides information on the MAX 7000 family of high-density,
high-speed, I/O-intensive, general-purpose programmable logic devices.
These devices range from fast 7.5-ns PAL/GAL integrators to high-speed
programmable alternatives to gate arrays. MAX 7000 devices are fabricated
on CMOS EPROM and EEPROM technologies.

Table 3. MAX 7000 Devices
Device

Package
(2)

See Note (1)

Temp. Speed t PD1
(3) Grade (ns)

f CNT
(MHz)

Technology Meells Oed.
(FFs) Inputs

Number
of Pins

1/0

EPM7032 L,Q, T

-7

7.5

125.0

EEPROM

EPM7032 L,Q, T

-10

100.0

EEPROM

EPM7032 L,Q, T

C, I

-12

90.9

EEPROM

EPM7032 L,Q, T

C,I

-15

76.9

EEPROM

EPM7032 L

-15T 15

76.9

EEPROM

7.5 125.0

EEPROM

48,64

68, 84, 100 (6)

EEPROM

48,64

68,84,100
68,84,100

EPM7064 L,G,Q

-7

EPM7064 L,G,Q

-10

EPM7064 L,G,Q

-12

90.9

EEPROM

48,64

EPM7064 L,G,Q

C,I

-15

76.9

EEPROM

48,64

68,84,100

EPM7096 L,G,Q

-7

7.5

125.0

EEPROM

48,60,72

68,84,100

EPM7096 L,G,Q

-10

100.0

EEPROM

48,60,72

68,84,100

EPM7096 L,G,Q

-12

90.9

EEPROM

48,60,72

68,84,100

EPM7096 L,G,Q

C, I

-15

76.9

EEPROM

48,60,72

68,84,100

100.0

EPM7096 J, L, G, Q

-2

71.4

EPROM

48,60,72

68,84,100

EPM7096 J, L, G, Q

-3

62.5

EPROM

48,60,72

68,84,100

EPM7096 J, L, G, Q

C,I

68,84,100

EPM7128 L,G,Q

-10

EPM7128 L,G,Q

-12

EPM7128 L,G,Q

-15

EPM7128 L,G,Q

C,I

-20

62.5

EPM7160 L,G,Q

-12

90.9

EEPROM

EPM7160 L,G,Q

-15

76.9

EEPROM

EPM7160 L,G,Q

C,I

-20

62.5

EEPROM

EPM7192 G,Q

-12

90.9

EEPROM

EPM7192 G,Q

-15

76.9

EEPROM

EPM7192 G,Q

C,I,M -20

62.5

EEPROM

EPM7256 G,W,M

-20

62.5

EPM7256 G,W,M

C,I,M -25

50.0

EPROM

48,60,72

100.0

EEPROM

128

48,64,80,96 68,84,100,160

90.9

EEPROM

128

48,64,80,96 68,84,100,160

76.9

EEPROM

128

48,64,80,96 68,84,100,160

EEPROM

128

48,64,80,96 68,84,100,160

160

60,80,100

84, 100, 160

160

60,80,100

84, 100, 160

160

60,80,100

84, 100, 160

192

120

160

192

120

160

192

120

160

EPROM

256

128, 160

160, 192, 208 (7)

EPROM

256

128, 160

160,192,208

Notes to tables 1 through 8 are listed on page 23.

I Altera Corporation

Page 19

I Component Selection Guide

Data Sheet

Table 4 provides information on the MAX 5000/EPS464 family of low-cost
programmable logic devices for tasks ranging from 20-pin address decoders
to 100-pin custom LSI peripherals. These devices combine the speed, easeof-use, and familiarity of PAL devices with the density of programmable
gate arrays. MAX 5000/EPS464 devices are fabricated on CMOS EPROM
technology.

MAX 50001
EPS464

Devices

Table 4. MAX 5000lEPS464 Devices
Device

Package
(2)

See Note (1)

Temp.
(3)

Speed
Grade
-15

t PD1

f CNT Technology Macrocells
(Flipflops)

Dedicated
Inputs

1/0

Number
of Pins

(ns)

(MHz)

100.0

EPROM

20
20

EPM5016

D,P,S

EPM5016

D,P,S

C, I

-17

83.3

EPROM

EPM5016

D,P,S

C, I

-20

62.5

EPROM

EPM5032

0, P,J,L

-15

76.9

EPROM

EPM5032

0, P,J,L

-17

71.4

EPROM

EPM5032

0, P,J,L

C, I

-20

62.5

EPROM

EPM5032

0, P, J, L

C,I,M

-25

50.0

EPROM

EPS464

J, L,

a
J, L, a

-20

66.7

EPROM

-25

50.0

EPROM

EPM5064

J, L

-1

50.0

EPROM

EPM5064

J,L

C, I

-2

40.0

EPROM

EPM5064

J,L

C,I,M

33.3

EPROM

EPM5128

J, L, G

-1

50.0

EPROM

128

EPM5128

J, L, G

C, I

-2

40.0

EPROM

128

EPM5128

J, L, G

C,I,M

33.3

EPROM

128

68
68

EPS464

EPM5128A J, L, G

-12

111.1

EPROM

128

EPM5128A J, L, G

-15

83.3

EPROM

128

EPM5128A J, L, G

-20

66.7

EPROM

128

EPM5130

J, L, G, 0, W C

-1

50.0

EPROM

128

48,64

84, 100

EPM5130

J, L, G, 0, W C

-2

40.0

EPROM

128

48,64

84, 100

EPM5130

J, L, G, 0, W C,I,M

33.3

EPROM

128

48,64

84, 100

EPM5192

J, L, G

50.0

EPROM

192

EPM5192
EPM5192

-1

J, L, G

-2

J, L, G

C,I,M

40.0

EPROM

192

33.3

EPROM

192

EPM5192A J, L, G,O

-15

83.3

EPROM

192

84, 100

EPM5192A J, L, G,O

-20

66.7

EPROM

192

84,100

Notes to tables 1 though 8 are listed on page 23.

Page 20

Altera Corporation

I Data Sheet

Component Selection Guide

Classic Devices

Table 5 provides information on the Classic family of programmable logic
devices, which offer the industry's most comprehensive solution to highspeed, low-power logic integration. These devices provide tpD as low as
7.5 ns and internal counter rates as high as 125 MHz. Classic devices are
fabricated on CMOS EPROM and EEPROM technologies.

Table 5. Classic Devices
Device

Package
(2)

See Note (1)
Temp.
(3)

Speed
Grade

t PD1
(ns)

(MHz)

f eNT

Technology Macrocells
(Flipflops)

Dedicated
Inputs

1/0

Number
of Pins

EP330

P,S

-12

100.0

EPROM

, EP330

P,S

-15

83.3

EPROM

EP610

P, L,S

-15

83.3

EPROM

24,28

EP610

P, L,S

C, I

-20

62.5

EPROM

24,28

EP610

D, P,L,S

-25

40.0

EPROM

24,28

EP610

D,P,L,S

C, I

-30

33.3

EPROM

24,28

EP610

D, P,L,S

C, I,M

-35

28.6

EPROM

24,28

EP610A

P, L,S

-7

7.5

125.0

EEPROM

24,28

EP610A

P, L,S

-10

100.0

EEPROM

24,28
24,28

20
20

EP610A

P, L,S

-12

83.3

EEPROM

EP610A

P,L,S

-15

71.4

EEPROM

24,28

EP610T

P, L,S

-15

83.3

EPROM

24,28

EP610T

P,L,S

-20

62.5

EPROM

24,28

EP610T

P, L,S

-25

40.0

EPROM

24,28

EP910

D, P, J, L

-30

33.3

EPROM

40,44

EP910

D, P, J, L

C, I

-35

28.6

EPROM

40,44

EP910

D, P, J, L

C, I,M

-40

25.0

EPROM

40,44

EP910A

-10

100.0

EEPROM

EP910A

-12

83.3

EEPROM

EP910A

-15

71.4

EEPROM

EP910T

P,L

-30

33.3

EPROM

40,44

EP1810

-20

50.0

EPROM

EP1810

C, I

-25

40.0

EPROM

EP1810

J, L, G

-35

28.6

EPROM

EP1810

J, L, G

C,I,M

-45

22.2

EPROM

68
68

EP1810T

-20

50.0

EPROM

EP1810T

C, I

-25

40.0

EPROM

EP1810T

-35

28.6

EPROM

Notes to tables 1 though 8 are listed on page 23.

I Altera Corporation

Page 21

I Component Selection Guide

3.3-Volt
Devices

Data Sheet I

Table 6 provides information on Altera's general-purpose programmable
logic devices for 3.3-V applications. These devices are ideal for low-power
systems, such as battery-operated instruments and notebook computers.
The 3.3-V devices are fabricated on CMOS EEPROM and SRAM
technologies.
See Note (1)

Table 6. 3.3-Volt Devices
Package
(2)

Device

EPM7032V (8) L, T

Temp.
(3)

Speed
Grade

Technology

-12

EEPROM
EEPROM

EPM7032V

L, T

-15

EPM7032V

L, T

C, I

-20

Flipflops

Logic Cells

Dedicated
Inputs

1/0

Number
of Pins

EPF8282V (9) L, T

-3

SRAM

282

208

64, 74

84, 100

EPF8282V

C,I

-4

SRAM

282

208

64, 74

84, 100

L, T

FunctionSpecific
Devices

EEPROM

Table 7 provides information on the user-configurable Stand-Alone
Microsequencer (SAM) devices, ideal for implementing high-performance
controllers. SAM devices feature 448 words of on-chip reprogrammable
microcode EPROM, a 15 x 8 stack, a loop counter, and prioritized multiway control branching. SAM devices are based on CMOS EPROM
technology.

Table 7. SAM Devices
Device

Package
(2)

EPS448 D,P,L

Temp. Speed f eye Technology Microcode
(3) Grade (MHz)
EPROM
448 x 36

Branch
EPLD
(P·Terms)

-25A

EPROM

768

EPS448 D,P,L

-25

EPROM

448 x36

EPS448 D,P,L

C,I,M -20

EPROM

448 x 36

EPS448 D,P,L

-16

EPROM

448 x36

768

Stack Inputs Outputs Number
of Pins
16

15 x 8

768

15 x 8

768

15 x8
15 x 8

Table 8 gives information on the Micro Channel programmable logic
device, which provides a user-configurable interface for PS/2 Micro Channel
Bus adapter cards. Basic interface functions are integrated into the EPB2001,
which is 100% compatible with Micro Channel AC timing and DC output
drive specifications. The EPB2001 is based on CMOS EPROM technology.

I Page 22

Altera Corporation

Data Sheet

Component Selection Guide

Table 8. Micro Channel Device
Device
EPB2001

Package Temp.
(2)
(3)

Technology

EPROM

Description
Single-chip interface adapter for PS/2 Micro Channel

Number
of Pins

Notes to Tables 1 though 8:
(1)
(2)

(3)

(4)
(5)
(6)
(7)
(8)
(9)

Preliminary data is shown for some parameters. Consult individual device data sheets in this data book for more
information or contact Altera for the most current device information.
Package configurations (contact Altera for current availability of device package options):
D: Ceramic dual in-line package (CerDIP)
P:
Plastic dual in-line package (PDIP)
J:
Ceramic J-Iead chip carrier (JLCC)
L:
Plastic J-Iead chip carrier (PLCC)
G: Ceramic pin-grid array (PGA)
S:
Plastic small-outline integrated circuit (SOIC)
Q: Plastic quad flat pack (PQFP)
W: Windowed ceramic quad flat pack (CQFP).
T:
Plastic thin quad flat pack (TQFP)
M: Metal quad flat pack (MQFP)
R: Power quad flat pack (RQFP)
B:
Ball-grid array (BGA)
Operating temperature:
C: Commercial (0° C to 70° C)
I:
Industrial (-40° C to 85° C)
M: Military (-55° C to 125° C)
The 192-,208-, and 225-pin package options of the EPF8820 provide 1481/0 pins.
The 288- and 304-pin package options of the EPF81500 provide 204 I/O pins.
The 84- and 100-pin package options for the EPM7064 provide 64 I/O pins.
The 192- and 208-pin package options for the EPM7256 provide 160 I/O pins.
The EPM7032V is a 3.3-V version of the EPM7032.
The EPF8282V is a 3.3-V version of the EPF8282.

I Altera Corporation

Page 23

I Component Selection Guide
MilitaryQualified
Devices

Data Sheet I

Tables 9 though 12 provide information on Altera's military-qualified
Classic, MAX 5000, MAX 7000, and FLEX 8000 devices. For more information
on Altera's military-qualified devices, consult Military Products in this data
book.

See Note (1)

Table 9. Military-Qualified Classic Devices
Device

Package
(2)

Assurance t PD1 fCNT
Level (3) (ns) (MHz)

Technology Macrocells
(Flipflops)

Dedicated 1/0
Inputs

Number
of Pins

Altera
Military
Drawing (4)
02D-00522

EP610

8838

28.6

EPROM

8947601 LA

DESC

28.6

EPROM

EP1810

8838

25.0

EPROM

8946901YC

DESC

25.0

EPROM

1/0

Number
of Pins

Altera
Military
Drawing (4)
02D-00828

Table 10. Military-Qualified MAX 5000 Devices
Device

Package
(2)

Assurance t pD1 fCNT
Level (3) (ns) (MHz)

02D-00782

See Note (1)
Technology Macrocells
(Flipflops)

Dedicated
Inputs

EPM5032

8838

50.0

EPROM

9061102XA

DESC

50.0

EPROM

EPM5128

8838

40.0

EPROM

128

02D-01015

EPM5128

8838

33.3

EPROM

128

02D-01015

8946801 XC

DESC

33.3

EPROM

128

EPM5130

G,W

8838

40.0

EPROM

128

100

02D-01413

EPM5130

G,W

8838

33.3

EPROM

128

100

02D-01413

DESC

40.0

EPROM

128

100

9314401MZC G

DESC

33.3

EPROM

128

100

9314402MYA W

DESC

40.0

EPROM

128

100

9314401MYA W

DESC

33.3

EPROM

128

100

EPM5192

8838

33.3

EPROM

192

02D-01359

9206202MZC G

DESC

40.0

EPROM

192

9206201MZC G

DESC

33.3

EPROM

192

9314402MZC G

I Page 24

Altera Corporation

Data Sheet

Component Selection Guide

Table 11. Military-Qualified MAX 7000 Devices (Under Development)
Device
EPM7192

Package
(2)

Assurance
Level (3)
8838

t PD1 f CNT

Technology

(ns) (MHz)
20

66.6

See Note (1)
Macrocells
(Flipflops)

Dedicated
Inputs

1/0

Number
of Pins

192

120

160

Dedicated
Inputs

1/0

Number
of Pins

EEPROM

Table 12. Military-Qualified FLEX 8000 Devices (Under Development)
Device

Package
(2)

Assurance Speed Grade Technology
Level (3)

Flipflops

See Note (1)
Logic
Elements

EPF8452

8838

-3

SRAM

452

336

116

160

EPF81188

8838

-3

SRAM

1188

1008

180

232

Notes to Tables 9 though 12:
(1)

(2)

(3)

(4)

All military-qualified devices are rated to military temperatures (-55° C to 125° C). Preliminary data is shown for
some other parameters. Consult individual device data sheets in this data book for more information, or contact
Altera for the most current device information.
Package configurations:
D: Ceramic dual in-line package (CerDIP)
G: Ceramic pin-grid array (PGA)
W: Ceramic quad flat pack (CQFP)
Product assurance levels:
883B:
Processed to MIL-STD-883, current revision.
DESC:
DESC Standard Military Drawing (SMD). Consult Altera or DESC for availability.
All Military Product Drawings (MPDs) are prepared in accordance with the appropriate military specification
format. When a Source Control Drawing (SCD) is necessary, the appropriate MPD is required for proper SCD
preparation.

I Altera Corporation

Page

251

Notes:

Contents
I August 1993

Section 2

FLEX 8000
FLEX 8000 Programmable Logic Device Family ......................................... 29
EPF81500 ............................................................................................... 50
EPF81188 ............................................................................................... 52
EPF8820 ................................................................................................. 54
EPF8452 ................................................................................................. 56
EPF8282 ................................................................................................. 58

I Altera Corporation

Page 27

FLEX 8000
Programmable Logic
Device Family
I August 1993, ver. 3

Features

Data Sheet

o
o
o
o

o
o
o

o
o
o
o

High-density, register-rich programmable logic device family
2,500 to 24,000 usable gates
282 to 2,252 registers
Fabricated on a 0.8-micron CMOS SRAM technology
In-circuit reconfigurable
FastTrack continuous routing structure for fast, predictable
interconnect delays
Available in a variety of packages with 84 to 304 pins (see Table 1)
Input/output registers on all I/O pins
Dedicated carry chain that can implement fast adders and counters
Dedicated cascade chain for efficient implementation of high-speed,
high-fan-in logic functions
Low power consumption (less than 1 rnA in standby mode)
Programmable output slew-rate control to reduce switching noise
Built-in Joint Test Action Group (JTAG) Boundary-Scan test circuitry
on selected devices
3.3-V operation provided by EPF8282V devices (see the 3.3-Volt
Programmable Logic Devices Data Sheet in this data book)
Software design support and automatic place-and-route with Altera's
MAX+PLUS II development system for PC, Sun SPARCstation, and
HP 9000 Series 700 platforms

Table 1. FLEX 8000 Device Features

Feature

EPF8282
EPF8282V

EPF8452

EPF8820

EPF81188

EPF81500

Available Gates (1)

5,000

8,000

16,000

24,000

31,000

Usable Gates (1)

2,500

4,000

8,000

12,000

15,500

Flipflops

282

452

820

1,188

1,500

Logic Elements

208

336

672

1,008

1,296

Maximum User 1/0

120

152

184

208

JTAG BST Circuitry

Yes

84-pin PLCC
1OO-pin TOFP

84-pin PLCC
160-pin POFP
160-pin PGA

160-pin ROFP
192-pin PGA
208-pin ROFP
225-pin BGA

232-pin PGA
240-pin ROFP

240-pin ROFP
288-pin PGA
304-pin ROFP

Packages (2)

Notes:
(1)
(2)

Devices with 24,000 usable gates (48,000 available gates) are under development.
Contact Altera for information on package availability. Ball-grid array (BGA) packages are under development.

I Altera Corporation

Page 29

I FLEX 8000 Programmable Logic Device Family

General
Description

Data Sheet

Altera's Flexible Logic Element MatriX (FLEX) family combines the benefits
of both EPLDs and FPGAs. The fine-grained architecture and high register
count of FPGAs are combined with the high speed and predictable interconnect delays of EPLDs to make FLEX 8000 the ideal programmable logic
family for a wide range of applications. Logic is implemented in FLEX 8000
devices with compact 4-input look-up tables (LUTs) and programmable
registers, while high performance is provided by a fast, continuous network
of routing resources.
FLEX 8000 devices provide a large number of storage elements for
applications such as digital signal processing, wide data-path manipulation,
and data transformation. These devices are an excellent choice for bus
interfaces, TTL integration, coprocessor functions, and high-speed
controllers. The high-pin-count packages can integrate multiple 32-bit
buses into a single device. Table 2 shows typical functions and performance
for FLEX 8000 devices.

Table 2. FLEX 8000 Performance

Application

Logic Elements Used

-2 Speed Grade

-3 Speed Grade

16-bit prescaled counter

133 MHz

115 MHz

16-bit loadable counter

68 MHz

45 MHz

16-bit up/down counter

68 MHz

45 MHz

24-bit accumulator

48 MHz

32 MHz

16-line-to-1-line multiplexer

14 ns

17 ns

All FLEX 8000 device packages provide four dedicated inputs for
synchronous control signals with large fan-outs. Each I/O pin has an
associated register on the periphery of the device. When used as outputs,
these registers provide fast Clock-to-output times; as inputs, they provide
quick setup times.
The logic and interconnections in the FLEX 8000 architecture are configured
with CMOS SRAM cells. FLEX 8000 devices are configured at system
power-up, with data stored in a configuration EPROM device or provided
by a system controller. Altera offers the EPC12l3 and EPCl064 serial
Configuration EPROMs, which configure FLEX 8000 devices via a serial
data stream. Configuration data can also be stored in an industry-standard
32K x 8-bit or larger EPROM or downloaded from system RAM. After a
FLEX 8000 device has been configured, it can be reconfigured in-circuit by
resetting the device and loading new data. Because the reconfiguration
requires less than 100 ms, real-time changes can be made during system
operation.

I Page 30

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family

Altera's MAX+PLUS II development system can be used to create FLEX 8000
logic designs with any combination of graphic, text, and waveform design
entry. Full simulation, worst-case timing analysis, and functional testing
are available for design verification. MAX +PLUS II also provides an
EDIF 2 a a and EDIF 2 9 a netlist interface for additional design entry and
simulation support with industry-standard CAE tools. In addition,
MAX+PLUS II can export Verilog and VHDL netlist files.

Functional
Description

The FLEX 8000 architecture incorporates a large matrix of compact building
blocks called logic elements (LEs). Each LE contains a 4-input LUT that
provides combinatorial logic capability and a programmable register that
offers sequential logic capability. The fine-grained structure of the LE
provides highly efficient logic implementation.
LEs are grouped into sets of eight to create Logic Array Blocks (LABs).
Each FLEX 8000 LAB is an independent structure with common inputs,
interconnections, and control signals. The LAB architecture provides a
coarse-grained structure for high device performance and easy routing.
Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group
of eight LEs is combined into an LAB; LABs are arranged into rows and
columns. The 1/ a pins are supported by 1/ a elements (IOEs) located at the
ends of rows and columns. Each IOE contains a bidirectional I/O buffer
and a flipflop that can be used as either an input or output register.

I Altera Corporation

Page 31

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Figure 1. FLEX 8000 Device Block Diagram
liD Element -

IDE

=:-~

Logic
Element (LE)

I
I

A
Signal interconnections within FLEX 8000 devices and to and from device
pins are provided by the FastTrack Interconnect, a series of fast, continuous
lines that run the entire length and width of the device. IOEs are located at
the end of each row (horizontal) and column (vertical) FastTrack
Interconnect path.

Logic Element

I Page 32

The logic element (LE) is the smallest unit of logic in the FLEX 8000
architecture, with a compact size that provides efficient logic utilization.
Each LE contains a 4-input look-up table (LUT), a programmable flipflop,
a carry chain, and a cascade chain. Figure 2 shows a block diagram of the
LE.

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Figure 2. FLEX 8000 Logic Element (LE)
Cascade-In

Carry-In

DATA1-~: ~

LEOut

DATA2 -~:
LUT
DATA3:
L -_ _ _ L-_ _-----l
DATA4
:________________________________________________________________,
CLRN
LABCTRL 1 - - - - I
LABCTRL2 - - - - IL - -_ _-----l

Clock
Select
LABCTRL3 - - - - - - I
LABCTRL4 - - - - - - I

Cascade-Out

Carry-Out

The LUT is a function generator that can compute any function of four
variables. The programmable flipflop in the LE can be configured to
emulate D, T, JK, or SR operation. The Clock, Clear, and Preset control
signals on the flipflop can be driven by dedicated input pins, generalpurpose 1/ 0 pins, or any internal logic. For purely combinatorial functions,
the flipflop is bypassed and the output of the LUT goes directly to the
output of the LE.
The FLEX 8000 architecture provides two dedicated high-speed data paths,
the carry and cascade chains, that connect adjacent LEs without using local
interconnect paths. The carry chain supports high-speed counters and
adders; the cascade chain implements wide-input functions with minimum
delay. Cascade and carry chains connect all LEs in an LAB and all LABs in
the same row. Heavy use of carry and cascade chains can reduce the
routing resources available for implementing other logic. Therefore, carry
and cascade chains are recommended only for use in speed-critical portions
of a design.

Carry Chain
The carry chain provides a very fast (less than 1 ns) carry-forward function
between LEs. The carry-in signal from a lower-order bit moves forward
into the higher-order bit via the carry chain, and feeds into both the LUT
and the next portion of the carry chain. This feature allows the FLEX 8000
architecture to implement high-speed counters and adders of arbitrary
width. The MAX+PLUS II Compiler can create carry chains automatically
during design processing; designers can also specify carry chain logic
manually during design entry.

I Altera Corporation

Page 33

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Figure 3 shows how an n-bit full adder can be implemented in n+ 1 LEs by
using the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register is typically bypassed for simple adders, but
can be used for an accumulator function. Another portion of the LUT and
the carry chain logic generate the carry-out signal, which is routed directly
to the carry-in signal of the next-higher-order bit. The final carry-out signal
is routed to an LE, where it can be used as a general-purpose signal. In
addition to mathematical functions, the carry chain logic supports very
fast counters and comparators.

Figure 3. Carry Chain Operation
Carry-In
r· .... •-.................. -.... .. -................... -..... ,.-- .. "' .. -.......... -.. -............. -.. -" .................... ... ........................... "':-.....';
<
~
"'~

!
A1
B1

~~l~S_1____~

1
!.

r.········..·······..·......··..·····..···..·..·......·..······..·..·..·..·..·......··..·..
A2
B2

LUT

:.: ..........

·1.·

I-'---t----=S=2____~

,;~, •• ,.,........ ;.,................., ....... , •• ~ •• c.... ;~;;"; •• ~.; •• :., •.bggj

•••
An

Carry-Out

I Page 34

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Cascade Chain
With the cascade chain, the FLEX 8000 architecture can implement functions
that have a very wide fan-in. Adjacent LUTs can be used to compute
portions of the function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical OR
(via De Morgan's inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a function,
with a delay of approximately 1 ns per LE. The MAX+PLUS II Compiler
can create cascade chains automatically during design processing; designers
can also specify cascade chain logic manually during design entry.
Figure 4 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. These examples show functions of 4n variables
implemented with n LEs. The LE delay is approximately 6 ns; the cascade
chain delay is 1 ns. With the cascade chain, 9 ns is needed to decode a 16-bit
address.

Figure 4. Cascade Chain Operation
AND Cascade Chain

OR Cascade Chain

j····'···············~:·· ·-~········-'······:·iE1·1

0[3 .. 0]

0[3 .. 0 ] ,
....:..-:....--......
..,

"'.!.
'"

;

•••

:.,' ••. c•• Co ......,~ •• , ........ ,; ".'.,;.' C,.:••• c,. ;.".,~~.{~.~.~.j

0[7 ..4]

••
•
0[(4n-1 ) ..4(n-1 )]

••
•
0[(4n-1 ) ..4(n-1)}

Logic Element Operating Modes
The FLEX 8000 logic element can operate in one of four modes, shown in
Figure 5, each of which uses LE resources differently. In each mode, seven
of the ten available inputs to the LE-the four data inputs from the LAB
local interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE-are directed to different
destinations to implement the desired logic function. The three remaining

I Altera Corporation

Page 35

I FLEX 8000 Programmable Logic Device Family

Data Sheet I

inputs to the LE provide Clock, Clear, and Preset control for the register.
MAX+PLUS II software automatically chooses the best mode for each
application. Design performance can also be enhanced by structuring
designs for the appropriate operating mode.

Figure 5. FLEX 8000 Logic Element Operating Modes
Normal Mode
LEOut

Carry-In
DA~1--+-----~----~
DATA2-+--------1
4-lnput
LUT
DATA3
DATA4 -----+-----1

CLRN
Cascade-Out

Arithmetic Mode
Cascade-In

LEOut

Carry-In

DATA1-~--.---r-----1
DATA2 --+--*-+--CLRN

Carry-Out

Up/Down Counter Mode

Carry-In

Cascade-In

DATA1 (ENA)
DATA2 (UfD)

1----._._...

LE Out

DATA3 (DATA)
CLRN

DATA4 (!LOAD)

Clearable Counter Mode

--~===~~~~--~
Carry-In

DATA1 (ENA)
DATA2 (!CLR)

LE Out

DATA3 (DATA)
CLRN

DATA4 (!LOAD)

I Page 36

-~===~~~:::!--~

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Normal Mode
The Normal mode is suitable for general logic applications and wide
decode functions that can take advantage of a cascade chain. In Normal
mode, four data inputs from the LAB local interconnect and the carry-in
are the inputs to a 4-input LUT. The MAX +PLUS II Compiler automatically
selects the carry-in or the DATA3 signal as an input that is physically
controlled by a configurable SRAM bit. The LUT output can be combined
with the cascade-in signal to form a cascade chain through the cascade-out
signal. The LE Out signal-the data output of the LE-is either the
combinatorial output of the LUT and cascade chain, or the Q output of the
programmable register.
Arithmetic Mode

The Arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT provides
a 3-bit function; the other generates a carry bit. As shown in Figure 5, the
first LUT uses the carry-in signal and two data inputs from the LAB local
interconnect to generate a combinatorial or registered output. For example,
in an adder, this output would be the sum of three bits: A, B, and carry-in.
The second LUT uses the same three signals to generate a carry-out signal,
thereby creating a carry chain. The Arithmetic mode also supports a
cascade chain.
Up/Down Counter Mode

The Up IDown Counter mode offers counter enable, synchronous up I
down control, and data loading options. These control signals are generated
by the data inputs from the LAB local interconnect, the carry-in signal, and
output feedback from the programmable register. Two 3-input LUTs are
used: one generates the counter data, the other generates the fast carry
look-ahead bit. A 2-line-to-l-line multiplexer provides synchronous loading.
Data can also be loaded asynchronously with the Clear and Preset register
control signals, without using the LUT resources.
Clearable Counter Mode

The Clearable Counter mode is similar to the Up I Down Counter mode,
but supports a synchronous Clear instead of the up I down control. The
Clear function is substituted for the cascade-in signal in the Up IDown
Counter mode. Two 3-input LUTs are used: one generates the counter
data, the other generates the fast carry look-ahead bit. Synchronous loading
is provided by a 2-line-to-l-line multiplexer, the output of which is ANDed
with a synchronous Clear. This Clear function is substituted for the
cascade-in signal that is available in the Up IDown Counter mode.

I Altera Corporation

Page 37

I FLEX 8000 Programmable Logic Device Family

Data Sheet I

Clear/Preset Logic Control
Logic for the programmable register's Clear and Preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. See
Figure 6. The Clear function is controlled by DATA3, LABCTRL1, and
LABCTRL2 i the Preset function is controlled by DATA3 and LABCTRLl.
The MAX+PLUS II Compiler automatically selects the best control signal
implementation during compilation. Since the Clear and Preset functions
are active low, the Compiler automatically assigns a logic high to an
unused Clear and/ or Preset. Preset control can also be provided by using
a Clear and inverting the output of the register. Inversion control is
available for the inputs to both LEs and IOEs; therefore, if a register is
cleared by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used to implement other logic.

Figure 6. Logic Element Clear & Preset Logic
Clear Logic
VCC
LEOut
DA~3----------~~

LABCTRL1 - - - -___--1
LABCTRL2 - - - - - - - 1

Preset Logic

VCC

DATA3
LABCTRL 1 - - - - - - - - 1 . . . - /
LEOut

CLRN

Logic Array
Block

Page 38

A Logic Array Block (LAB) consists of eight LEs, their associated carry and
cascade chains, LAB control signals, and the LAB local interconnect. The
LAB provides the coarse-grained structure of the FLEX 8000 architecture
for efficient routing with high device utilization and high performance.
Figure 7 shows a block diagram of the FLEX 8000 LAB.

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Figure 7. Logic Array Block (LAB)
Dedicated
Inputs

Row Interconnect

Data signals enter the LAB local interconnect from either the row
interconnect or the dedicated inputs. The outputs of all eight LEs are also
driven back into the LAB local interconnect via local feedback lines. Each
LE in the LAB can drive signals out to the rest of the device via both row
and column interconnect paths.

I Altera Corporation

Page 39

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Each LAB provides four control signals that can be used in all eight LEs.
Two of these signals can be used as Clocks, the other two for Clear /Preset
control. The LAB control signals can be driven directly from a dedicated
input pin, an 1/0 pin, or any internal signal via the LAB local interconnect.
The dedicated inputs are typically used for global Clock, Clear, or Preset
signals because they provide synchronous control with very low skew
across the device. If logic is required on a control signal, it can be generated
in one or more LEs in any LAB and driven into the local interconnect of the
target LAB. Programmable inversion is available for all four LAB control
signals.

FastTrack
Interconnect

In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal and vertical routing paths that traverse the entire FLEX 8000
device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of routing
paths, increasing the delays between logic resources and reducing
performance.

The LABs within FLEX 8000 devices are arranged into a matrix of columns
and rows. Each row of LABs has a dedicated row interconnect that routes
signals both into and out of the LABs in the row. The row interconnect can
then drive 1/0 pins or feed other LABs in the device. Each column of LABs
has a dedicated column interconnect that routes signals out of the LABs in
the column. The column interconnect can then drive I/O pins or feed into
the row interconnect to route the signals to other LABs in the device. A
signal from the column interconnect, which can be either the output of an
LE or an input from an 1/ 0 pin, must transfer to the row interconnect
before it can enter an LAB. Table 3 summarizes the FastTrack Interconnect
resources available in each FLEX 8000 device.

Table 3. FLEX 8000 FastTrack Interconnect Resources
Rows

Channels per Row

Columns

Channels per Column

EPF8282,
EPF8282V

168

Device

EPF8452

168

EPF8820

168

EPF81188

168

EPF81500

216

Figure 8 shows the interconnection of four adjacent LABs, with row,
column, and local interconnects, as well as the associated cascade and
carry chains.

I Page 40

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family

Figure B. FLEX BODO Oevice Interconnect Resources
Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2,3, etc.) position within the device.

Column
Interconnect

LAB Local
Interconnect
I

cascade&
Carry Chain

A
','"

IDE

Dedicated
Inputs

In addition to the general-purpose I/O pins, FLEX 8000 devices have four
dedicated input pins. These dedicated inputs provide low-skew devicewide signal distribution, and are typically used for global Clock, Clear,
and Preset control signals. The signals from the dedicated inputs are
available as control signals for all LABs and I/O elements in the device.
The dedicated inputs can also be used as general-purpose data inputs for
nets with large fan-outs because they can feed the local interconnect of
each LAB in the device.

110 Element

Figure 9 shows the I/O element (lOE) block diagram. Signals enter the
FLEX 8000 device from either the I/O pins that provide general-purpose
input capability or the four dedicated inputs that are typically used for
fast, global control signals. The 10Es are located at the ends of the row and
column interconnect.

I Altera Corporation

Page 41

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Figure 9. I/O Element (IDE)
Numbers in parentheses are for the EPF81500 device.
1/0 Controls
4 (10)

to Row or Column 4 - - 1 - - - - - - + - - - - - 1
Interconnect

Programmable
Inversion
6(12)

from Row or Column
Interconnect

1/ 0 pins can be used as input, output, or bidirectional pins. Each 110 pin
has a register that can be used either as an input register for external data
that requires fast setup times, or as an output register for data that requires
fast Clock-to-output performance. The MAX+PLUS II Compiler uses the
programmable inversion option to automatically invert signals from the
row and column interconnect when appropriate.
The output buffer in each 10E has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A faster slew rate
provides a speed increase of up to 1 ns, but may introduce more noise into
a system than a slow slew rate. The fast slew rate should be used for speedcritical outputs in systems that are adequately protected against noise.
Designers can specify the slew rate on a pin-by-pin basis during design
entry or assign a default slew rate to all pins on a global basis.
The Clock, Clear, and Output Enable controls for the 10Es are provided by
a network of 110 control signals. These signals can be supplied by either
the dedicated input pins or internal logic. The 10E control-signal paths are
designed to minimize the skew across the device. All control-signal sources
are buffered onto high-speed drivers that drive the signals around the
periphery of the device. The I/O control signals can be configured to
provide up to four Output Enable signals (ten in the EPF81500), and up to
two Clock or Clear signals.

I Page 42

Altera Corporation

I Data Sheet

JTAG BoundaryScan Testing

FLEX 8000 Programmable Logic Device Family

The Joint Test Action Group (JTAG) Boundary-Scan Test (BST) architecture
in the EPF8282, EPF8282V, EPF8820, and EPF81500 FLEX devices makes it
possible to isolate a device's internal circuitry from its I/O circuitry. The
JTAG boundary-scan testing offers the capability to efficiently test
components on circuit boards with tight lead spacing.
Only five device pins are needed to either force or observe data signals on
the 1/ 0 pins of FLEX 8000 devices that comply with the JT AG IEEE Std
1149.1-1990 specification. Serial data is shifted into boundary-scan cells in
the device; observed data is shifted out and externally compared to expected
results. Boundary-scan testing offers efficient PC board testing, providing
an electronic substitute for the traditional"bed of nails" test fixture. The
JTAG BST architecture also supports interconnect fault testing and device
functionality testing that are not available in other test systems. For detailed
information on JTAG boundary-scan testing, refer to the JTAG IEEE Std
1149.1-1990 specification.
The JTAG BST-capable FLEX 8000 devices implement the mandatory
SAMPLE, EXTEST, and BYPASS JTAG BST instructions. When a device is
operating inJTAG BST mode, four I/O pins are used as the TDI, TDO, TMS,
and TCLK JTAG pins. A dedicated active-low Reset pin, nTRST, initializes
the JTAG BST circuitry. When the nTRST pin is driven low, the JTAG BST
circuitry is reset and the device functions normally. Table 4 summarizes
the functions of each of the JTAG BST pins.

Table 4. JTAG Pin Descriptions
Pin

I Altera Corporation

Name

Description

TDI

Test data input

Serial input pin for instructions and test data.

TDO

Test data output

Serial data output pin for instructions and test data.
The signal is tri-stated if data is not being shifted
out of the device.

TMS

Test mode select

Serial input pin to select the JTAG instruction
mode. TMS should be driven high during usermode operation.

TCLK

Test clock input

Clock pin to shift the serial data and instructions in
and out of the TDI and TDO pins, respectively.
TCLK is also used to shift serial instruction data
into the TMS pin.

nTRST

Test reset input

Active-low input to asynchronously initialize or
reset the boundary-scan circuit. When nTRST is
driven low, the boundary-scan circuit is reset, and
the device operates in user mode.

Page 43

I FLEX 8000 Programmable Logic Device Family

Data Sheet I

Figure 10 shows the IOE of FLEX 8000 devices with JTAG BST registers.
Each IOE has six registers that connect to internal data signals via the
OUTJ, INJ, and OEJ signals. In an IOE that does not have JTAG BST
registers (as shown in Figure 9), these signals are connected to the tri-state
buffer's input, output, and Output Enable controls, respectively. The control
signals for the JTAG BST registers are generated internally from the TMS
and TCLK inputs.

Figure 10. I/O Element with JTAG Architecture
SDO

1/0 Controls
OEJ

to Row or 4 - 1 - - - - - - - + - - - - 1
Column
Interconnect
Input Registers

from Row
or Column
Interconnect

SlewRate
Control

SOl

!.---

SHIFT

UPDATE

MODE

CLOCK

liD Element Circuitry

JTAG Circuitry

The JTAG BST registers shown in Figure 10 also exist for dedicated input
and configuration pins in FLEX 8000 devices. However, only some of these
pins provide output and Output Enable signals.
JTAG boundary-scan testing can be used either before or immediately
after a FLEX 8000 device is configured. An Enable/Disable option bit for
JTAG BST operation is set during device configuration.

I Page 44

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

The JTAG BST operation is controlled by a Test Access Port (TAP) Controller
that drives three registers: a 3-bit instruction register that directs the flow
of test data; a 1-bit bypass register; and a large boundary register located
among the IOEs on the periphery of the FLEX 8000 device. The boundary
registers for the EPF8282 and EPF8282V devices contain 273 bits; for the
EPF8820, 465 bits; and for the EPF81500, 645 bits.
Figure 11 illustrates the JTAG BST register control functions. The instruction
register is loaded and data is serially clocked through the TDI and TDO
pins to perform testing.

Figure 11. JTAG Register Control
TOO

TDI--------------------~----~t_~~--L-~~

Instruction
Register

, - - - - - - , UPDTIR
CLKIR
SHFTIR
TAP
UPDTDR
TMS ------.
Controller
CLKDR
nTRST ------.
SHFTDR
TCLK ------.

Bypass
Register

•••
Boundary-Scan
Register

Table 5 describes the SAMPLE, EXTEST, and BYPASS test instruction
modes. For additional information on JTAG boundary-scan testing for
FLEX 8000 devices, contact Altera Applications at (800) 800-EPLD.

Table 5. JTAG Boundary-Scan Instruction Modes
Mode

I Altera Corporation

Opcode

Description

SAMPLE

101

Allows a snapshot of the signals at the device pins to be
captured and examined while the device is operating
normally. This mode also allows data to be loaded into
update registers while the device is operating normally.

EXTEST

000

Allows the external circuitry and board-level interconnections
to be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.

BYPASS

111

Enables the 1-bit bypass register between the TDI and TDO
pins, which allows the SST data to pass through the selected
device synchronously to adjacent devices while the device is
operating normally.

Page 45

I FLEX 8000 Programmable Logic Device Family
Timing Model

Data Sheet

The continuous, high-performance FastTrack Interconnect routing resources
ensure predictable performance and accurate simulation analysis. This
predictable performance stands in marked contrast to that of FPGAs,
which use a segmented connection scheme and hence have unpredictable
performance. Timing simulation and delay prediction are available with
the MAX+PLUS II Simulator and Timing Analyzer, or with industrystandard CAE tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with O.l-ns resolution. The Timing Analyzer provides point-topoint timing delay information, setup and hold time prediction, and
system-level performance analysis.
The FLEX 8000 timing model in Figure 12 shows the delays that correspond
to various paths and functions in the circuit. This model contains three
distinct parts: the LE; the IOE; and the interconnect, including the row and
column FastTrack Interconnect, LAB local interconnect, and carry and

FiglJre 12. FLEX 8000 Timing Model
Dedicated Input
L::)

tOIN

f - - - - - - - - l..
~1

tOINROW

1--.-------,

IOE

1/0 Pin

Notes:
(1)
(2)

Carry chain connection between LEs in the same LAB
Cascade chain connection between LEs in the same LAB

I Page 46

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

cascade interconnect paths. Each parameter shown in Figure 12 is expressed
as a worst-case value in the "Internal Timing Characteristics" tables in this
data sheet. Hand-calculations that use the FLEX 8000 timing model and
these timing parameters can be used to estimate FLEX 8000 device
performance. Timing simulation or timing analysis after compilation is
required to determine final worst-case performance.

Generic Testing

Each FLEX 8000 device is functionally tested and guaranteed. Complete
testing of each configurable SRAM bit and all logic functionality ensures
100% configuration yield. AC test measurements for FLEX 8000 devices
are made under conditions equivalent to those shown in Figure 13. Multiple
test patterns can be used to configure devices during all stages of the
production flow.

Figure 13. FLEX 8000 AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast groundcurrent transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.

I Altera Corporation

.------vcc
4640
Device
Output

to Test
System

2500
Device input
rise and fall
times < 3 ns

Page 47

I FLEX 8000 Devices

Preliminary Information

Absolute Maximum Ratings
Symbol

Data Sheet I

See Operating Requirements for Altera Devices in this data book.

Parameter

Min

Conditions

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

lOUT

DC output current, per pin

-25

T STG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Symbol

Parameter

I MAX

Maximum DC Vee or GND current

Maximum Power dissipation

EPF81500 EPF81188

EPF8820

EPF8452

EPF8282

Unit

1250

1000

850

500

400

6.9

5.5

4.7

2.75

2.2

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

Max

Unit

5.25

V
V

vee
VI

Input voltage

Vee

Output voltage

Vee

Ambient temperature

°C

tR
tF

Input rise time

Input fall time

DC Operating Conditions
Symbol

With respect to GND

4.75

Supply voltage

For commercial use

Note (2)

Parameter

Max

Unit

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TIL output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

leeo

Vee supply current (standby)

Capacitance
Symbol

Conditions

= -4 mA DC
IOL = 8 mA DC
VI = VeeorGND
Va = VeeorGND
V I = GND, No load,

2.4

10H

V
V

-10
-40

0.45

f.lA

Note (3)

500

Conditions

Min

f.lA
f.lA

Note (4)
Parameter

= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz

C IN

Input capacitance

VIN

C OUT

Output capacitance

V OUT

I Page 48

Min

Typ

V IH

Max

Unit

Altera Corporation

Preliminary Information

Data Sheet

FLEX 8000 Devices

Notes to tables:
(1)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to

(2)

-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Operating conditions: Vee = 5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
Typical values are for TA = 25° C and Vee = 5.0 V.

(3)
(4)

Capacitance is sample-tested only.

Figure 14 shows the maximum output drive characteristics of FLEX 8000

I/O pins.
Figure 14. FLEX 8000 Maximum Output Drive Characteristics
200

ci.
~
~

..s

IOL
150

~
~

()

Vee = 5.0 V
Room Temp.

100

'5
c..
'5

..9

V 0 Output Voltage (V)

I Altera Corporation

Page 49

I FLEX EPF81500 Device

Preliminary Information

EPF81500 Internal Timing Characteristics

Parameter

Conditions

EPF81500-2

EPF81500-3

Min

Max

Unit

tOUTSU

Setup time for output register

2.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register

4.0

5.0

tOUT

Combinatorial time for I/O output

3.0

4.0

tOUTCLR

Clear time for output register

4.2

5.2

txz

Valid to Z time for 10E

tzx

Z to valid time for 10E

= 35 pF

= 5 pF
= 35 pF

EPF81500 I/O Element Input Timing Parameters

Symbol

Parameter

Conditions

3.0

4.0

3.0

4.0

EPF81500-2

EPF81500-3

Min

Max

t lN8U

Setup time for input register

2.8

tlNH

Hold time for input register

tlNCO

Clock-to-output time for input register

2.0

Max

Unit
ns
ns

3.0

tIN

Input pad and buffer delay

1.8

2.8

tlNCLR

Clear time for input register

2.2

3.2

EPF81500-2

EPF81500-3

Min

EPF81500 Logic Element Timing Parameters

Symbol

Parameter

Conditions

Max

Unit

t LE8U

Setup time for LE register

2.8

3.7

tLEH

Hold time for LE register

t LECO

Clock-to-output time for LE

3.7

4.0

tLE

Combinatorial time for LE

5.6

6.0

tLECLR

Clear time for LE register

4.0

4.3

tLEPRE

Preset time for LE register

4.0

4.3

t CICO

Carry-in to carry-out time

0.7

1.1

tCGEN

Carry generation time

2.6

3.3

tCASC

Cascade-in to cascade-out time

1.1

2.0

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

I Page 50

Note (1)

EPF81500 I/O Element Output Timing Parameters

Symbol

Data Sheet

1.8

2.7
4.6

ns
ns

5.0

Altera Corporation I

I Data Sheet

Preliminary Information

EPF81500 Interconnect Timing Parameters

Symbol
tLABCASC

tLABCARRY

Parameter

Conditions

FLEX EPF81500 Device

EPF81500-2

EPF81500-3

Min

Max

Unit

Cascade time between LEs in different
LABs

Max
0.5

0.9

Carry time between LEs in different

0.5

0.6

LABs
tCOL

Column interconnect routing delay

3.0

tOIN

Dedicated input pad delay

3.0

4.0

t LOCAL

LAB local interconnect delay

tOINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

EPF81500 External Reference Timing Characteristics

Symbol
t1

Parameter
liD pin to liD pin via row, LE, and

1.0

4.0

5.0

EPF81500-2

EPF81500-3

Min

Note (2)

Note (3)

Conditions
C1 = 35 pF

Max

Unit

column

liD pin to liD pin via row, LE, and row

Notes to tables:
(1)

(2)
(3)

Internal timing parameters cannot be measured explicitly. The values in these tables are worst-case delays based on
testable and guaranteed external parameters. These internal parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
The tROW and tOINROW delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
External reference timing characteristics are factory-tested, guaranteed worst-case values. A representative subset of
signal paths is tested to approximate typical device applications.

I Altera Corporation

Page 51

FLEX EPF81188 Device

EPF81188 Internal Timing Characteristics

Data Sheet

Note (1)

EPF81188 I/O Element Output Timing Parameters

Symbol

Parameter

Conditions

EPF81188-2

EPF81188-3

Min

Max

Unit

tOUTSU

Setup time for output register

2.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register C1 = 35 pF

4.0

5.0

tOUT

Combinatorial time for I/O output

3.0

4.0

tOUTCLR

Clear time for output register

4.2

5.2

txz

Valid to Z time for 10E

C1 = 5 pF

3.0

4.0

tzx

Z to valid time for 10E

C1 = 35 pF

3.0

4.0

EPF81188-2

EPF81188-3

Min

EPF81188 I/O Element Input Timing Parameters

Symbol

Parameter

Conditions

Max

t lNSU

Setup time for input register

2.8

tlNH

Hold time for input register

t lNCO

Clock-to-output time for input register

2.0

ns
ns

Max

Unit
ns
ns

3.0

tIN

Input pad and buffer delay

1.8

2.8

t lNCLR

Clear time for input register

2.2

3.2

EPF81188-2

EPF81188-3

Min

EPF81188 Logic Element Timing Parameters
Symbol

Parameter

Conditions

Max

Unit

t LESU

Setup time for LE register

2.8

3.7

tLEH

Hold time for LE register

t LECO

Clock-to-output time for LE

3.7

4.0

tLE

Combinatorial time for LE

5.6

6.0

tLECLR

Clear time for LE register

4.0

4.3

tLEPRE

Preset time for LE register

4.0

4.3

t CICO

Carry-in to carry-out time

0.7

1.1

tCGEN

Carry generation time

2.6

3.3

tCASC

Cascade-in to cascade-out time

1.1

2.0

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

Page 52

1.8

2.7
4.6

ns
ns

5.0

Altera Corporation I

I Data Sheet

FLEX EPF81188 Device

EPF81188 Interconnect Timing Parameters

Symbol

Parameter

Conditions

EPF81188-2

EPF81188-3

Min

Max

Unit

tLABCASC

Cascade time between LEs in different
LABs

Max
0.5

0.9

tLABCARRY

Carry time between LEs in different
LABs

0.5

0.6

tCOL

Column interconnect routing delay

3.0

to/N

Dedicated input pad delay

3.0

4.0

t LOCAL

LAB local interconnect delay

tOINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

EPF81188 External Reference Timing Characteristics

Symbol

Parameter

I/O pin to I/O pin via row, LE, and
column

I/O pin to I/O pin via row, LE, and row

1.0

4.0

5.0

EPF81188-2

EPF81188-3

Min

Note (2)

Note (3)

Conditions
C1 = 35 pF

Max

Unit

Notes to tables:
(1)

(2)
(3)

Internal timing parameters cannot be measured explicitly. The values in these tables are worst-case delays based on
testable and guaranteed external parameters. These internal parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
The tROW and tDINROW delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
External reference timing characteristics are factory-tested, guaranteed worst-case values. A representative subset of
signal paths is tested to approximate typical device applications.

I Altera Corporation

Page 53

I FLEX EPF8820 Device

Preliminary Information

EPF8820 Internal Timing Characteristics

Note (1)

EPF8820 I/O Element Output Timing Parameters

Symbol

Data Sheet I

Parameter

EPF8820-2

Conditions

Min

Max

EPF8820-3

Min

Max

Unit

tOUTSU

Setup time for output register

2.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register C1 = 35 pF

4.0

5.0

tOUT

Combinatorial time for I/O output

3.0

4.0

tOUTCLR

Clear time for output register

4.2

5.2

txz

Valid to Z time for 10E

C1 = 5 pF

3.0

4.0

tzx

Z to valid time for 10E

C1 = 35 pF

3.0

4.0

EPF8820-2

EPF8820-3

EPF8820 I/O Element Input Timing Parameters

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

t lNSU

Setup time for input register

2.8

tlNH

Hold time for input register

tlNCO

Clock-to-output time for input register

2.0

3.0

tIN

Input pad and buffer delay

1.8

2.8

tlNCLR

Clear time for input register

2.2

3.2

EPF8820-2

EPF8820-3

EPF8820 Logic Element Timing Parameters

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

t LESU

Setup time for LE register

2.8

3.7

tLEH

Hold time for LE register

t LECO

Clock-to-output time for LE

3.7

4.0

tLE

Combinatorial time for LE

5.6

6.0

tLECLR

Clear time for LE register

4.0

4.3

tLEPRE

Preset time for LE register

4.0

4.3

t CICO

Carry-in to carry-out time

0.7

1.1

tCGEN

Carry generation time

2.6

3.3

tCASC

Cascade-in to cascade-out time

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

Page 54

2.0

1.1
2.7

1.8
4.6

ns
ns

5.0

Altera Corporation I

Data Sheet

Preliminary Information

EPF8820 Interconnect Timing Parameters

Symbol

FLEX EPF8820 Device

EPF8820-2

Parameter

Conditions

Min

Max

EPF8820-3

Min

Max

Unit

tLABCASC

Cascade time between LEs in different
LABs

0.5

0.9

tLABCARRY

Carry time between LEs in different
LABs

0.5

0.6

tCOL

Column interconnect routing delay

3.0

tDIN

Dedicated input pad delay

3.0

4.0

t LOCAL

LAB local interconnect delay

tDINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

EPF8820 External Reference Timing Characteristics

Symbol
t1

Parameter
liD pin to liD pin via row, LE, and

1.0

4.0

5.0

EPF8820-2

EPF8820-3

Note (2)

Note (3)

Conditions
C1 = 35 pF

Min

Max

Unit

Min

column

liD pin to liD pin via row, LE, and row

Notes to tables:
(1) Internal timing parameters cannot be measured explicitly. The values in these tables are worst-case delays based on
testable and guaranteed external parameters. These internal parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
(2) The tROW and tDINROW delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
(3) External reference timing characteristics are factory-tested, guaranteed worst-case values. A representative subset of
signal paths is tested to approximate typical device applications.

Altera Corporation

Page

551

I FLEX EPF8452 Device

Preliminary Information

EPF8452 Internal Timing Characteristics

Note (1)

EPF8452 I/O Element Output Timing Parameters

Symbol

Data Sheet I

Parameter

EPF8452-2

Conditions

Min

Max

EPF8452-3

Min

Max

Unit

tOUTSU

Setup time for output register

2.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register C1

tOUT

Combinatorial time for liD output

tOUTCLR

Clear time for output register

txz

Valid to Z time for IDE

tzx

Z to valid time for IDE

= 35 pF

Symbol

Parameter

Conditions

5.0

3.0

4.0

4.2

5.2

3.0

4.0

3.0

4.0

EPF8452-2

EPF8452-3

= 5 pF
= 35 pF

EPF8452 I/O Element Input Timing Parameters

4.0

Min

Max

Min

Max

Unit

t lNSU

Setup time for input register

2.8

tlNH

Hold time for input register

tlNCO

Clock-to-output time for input register

2.0

3.0

tIN

Input pad and buffer delay

1.8

2.8

tlNCLR

Clear time for input register

2.3

3.3

EPF8452-2

EPF8452-3

EPF8452 Logic Element Timing Parameters

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

t LESU

Setup time for LE register

2.8

3.7

tLEH

Hold time for LE register

t LECO

Clock-to-output time for LE

3.7

4.0

tLE

Combinatorial time for LE

5.6

6.0

tLECLR

Clear time for LE register

4.0

4.3

tLEPRE

Preset time for LE register

4.0

4.3

t CICO

Carry-in to carry-out time

0.7

1.1

tCGEN

Carry generation time

2.6

3.3

tCASC

Cascade-in to cascade-out time

1.1

2.0

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

Page 56

1.8

2.7
4.6

ns
ns

5.0

Altera Corporation I

I Data Sheet

Preliminary Information

EPF8452 Interconnect Timing Parameters
Symbol

FLEX EPF8452 Device

EPF8452-2

Parameter

Conditions

Min

Max

EPF8452-3

Max

Unit

tLABCASC

Cascade time between LEs in different
LABs

0.5

Min

0.9

tLABCARRY

Carry time between LEs in different
LABs

0.5

0.6

tCOL

Column interconnect routing delay

3.0

tOIN

Dedicated input pad delay

3.0

4.0

t WCAL

LAB local interconnect delay

tOINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

EPF8452 External Reference Timing Characteristics

Symbol
t1

Parameter
I/O pin to I/O pin via row, LE, and

1.0

4.0

5.0

EPF8452-2

EPF8452-3

Note (2)

Note (3)

Conditions
C1 = 35 pF

Min

Max

Min

Max

Unit

column

I/O pin to I/O pin via row, LE, and row

Notes to tables:
(1)

(2)
(3)

I Altera Corporation

Page 57

I FLEX EPF8282 Device

Preliminary Information

EPF8282 Internal Timing Characteristics

Parameter

EPF8282-2

Conditions

Min

Max

EPF8282-3

Min

Max

Unit

tOUTSU

Setup time for output register

2.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register C1 = 35 pF

4.5

6.0

tOUT

Combinatorial time for I/O output

3.5

5.0

tOUTCLR

Clear time for output register

4.8

6.3

5.0

ns
ns

txz

Valid to Z time for 10E

C1 = 5 pF

3.5

tzx

Z to valid time for 10E

C1 = 35 pF

3.5

5.0

EPF8282-2

EPF8282-3

EPF8282 I/O Element Input Timing Parameters
Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

t/NSU

Setup time for input register

2.8

t/NH

Hold time for input register

t/NCO

Clock-to-output time for input register

2.0

3.0

tIN

Input pad and buffer delay

1.8

2.8

t/NCLR

Clear time for input register

2.3

3.3

EPF8282-2

EPF8282-3

EPF8282 Logic Element Timing Parameters
Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

t LESU

Setup time for LE register

2.5

3.7

tLEH

Hold time for LE register

t LECO

Clock-to-output time for LE

3.3

4.0

tLE

Combinatorial time for LE

5.0

6.0

tLECLR

Clear time for LE register

3.6

4.3

tLEPRE

Preset time for LE register

3.6

4.3

t CICO

Carry-in to carry-out time

0.7

1.1

tCGEN

Carry generation time

2.3

3.3

2.0

tCASC

Cascade-in to cascade-out time

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

Page 58

Note (1)

EPF8282 I/O Element Output Timing Parameters
Symbol

Data Sheet

1.1
1.6

2.7
4.1

ns
5.0

Altera Corporation I

Preliminary Information

Data Sheet

EPF8282 Interconnect Timing Parameters

FLEX EPF8282 Device I

EPF8282-2

EPF8282-3

Max

Unit

tLABCASC

Cascade time between LEs in different
LABs

0.5

0.9

tLABCARRY

Carry time between LEs in different
LABs

0.5

0.6

tCOL

Column interconnect routing delay

2.5

tOIN

Dedicated input pad delay

3.0

4.0

t LOCAL

LAB local interconnect delay

tOINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

Symbol

Parameter

Conditions

Parameter

110 pin to liD pin via row, LE, and
column

110 pin to I/O pin via row, LE, and row

Max

Min

1.0

3.0

3.5

4.2

EPF8282-2

EPF8282-3

Note (2)

EPF8282 External Reference Timing Characteristics

Symbol

Min

Note (3)

Conditions
C1 = 35 pF

Min

Max

Min

Max

Unit

Notes to tables:
(1)

(2)
(3)

Internal timing parameters cannot be measured explicitly. The values in these tables are worst-case delays based on
testable and guaranteed external parameters. These internal parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
The tROW and tDINROW delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
External reference timing characteristics are factory-tested, guaranteed worst-case values. A representative subset of
signal paths is tested to approximate typical device applications.

Altera Corporation

Page 591

I FLEX 8000 Programmable Logic Device Family

Calculating
FLEX 8000
Supply Current

Data Sheet I

The V cc supply current for FLEX 8000 devices, Icc, can be calculated with
the following equation:
Icc = ICCSTANDBY + ICCoUTPUT + ICCACTIVE
Typical ICCSTANDBY values are shown as ICCD in the "DC Operating
Conditions" table earlier in this data sheet. The IccoUTPUT value, which
depends on the device output load characteristics and switching frequency,
can be calculated using the guidelines given in Operating Requirements for
Altera Devices in this data book. The ICCACTIVE value depends on the switching
frequency and the application logic. This value can be calculated on the
basis of the relationship that each LE typically consumes 150 J,.lA/MHz.
The following equation shows the general formula for calculating ICCACTIVE:
IcCACTIVE = 150

J..lA
x Fx Nx s
MHzeLE

In this equation, F is the maximum operating frequency in MHz; N is
number of LEs used in the device; and s is the percentage of LEs that switch
on each Clock edge. Altera recommends that designers use a value of .
12.5% for s (s = 0.125), which is based on a 16-bit counter in which 2 out of
16 (12.5%) of the bits switch on each Clock edge.
Figure 15 shows the relationship between Icc and operating frequency for
LE utilization values ranging from 100 to 750 LEs.

Figure 15. FLEX 8000 Icc VS. Operating Frequency
1000

750 LEs

.s
c

800

600
500 LEs

::J

c..
c..

400

::J
CJ)

250 LEs

()

200
100 LEs

fMAX (MHz)

I Page 60

Altera Corporation

I Data Sheet

Configuration &
Operation

FLEX 8000 Programmable Logic Device Family I

The FLEX 8000 architecture supports several configuration schemes to
load a design into the device(s) on the circuit board. This data sheet
summarizes the device operating modes and available device configuration
schemes; refer to Application Note 33 (Configuring FLEX 8000 Devices) in
this data book for detailed descriptions of device configuration options,
device configuration pins, and information on configuring FLEX 8000
devices, including sample schematics, timing diagrams, and configuration
parameters.

Operating Modes
The FLEX 8000 architecture uses SRAM technology that requires
configuration data to be loaded whenever the circuit powers up and
begins operation. The process of physically loading the SRAM programming
data into the device is called configuration. During initialization, which
occurs immediately after configuration, the device resets registers, enables
I/O pins, and begins to operate as a logic device. The configuration and
initialization processes together are called "command mode"; normal
device operation is called "user mode."
The SRAM technology allows FLEX 8000 devices to be reconfigured incircuit by loading new programming data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a
device pin, loading different programming data, reinitializing the device,
and resuming user-mode operation. The entire reconfiguration process
requires less than 100 ms and can be used to dynamically reconfigure an
entire system. In-field upgrades can be performed by distributing new
configuration files.

Configuration Schemes
The configuration data for a FLEX 8000 device can be loaded with one of
six configuration schemes, chosen on the basis of the target application.
Both active and passive schemes are available. In the active configuration
schemes, the FLEX 8000 device functions as the controller, directing the
loading operation, controlling external EPROM devices, and completing
the loading process. The Clock source for all active configuration schemes
is an oscillator on the FLEX 8000 device that operates atup to 6 MHz. In the
passive configuration schemes, an external controller guides the
FLEX 8000 device, which operates as a slave. Table 6 shows the source of
data for each of the six configuration schemes.

I Altera Corporation

Page 61

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Table 6. Configuration Schemes
Configuration Scheme

MAX+PLUS II
Development
System

Acronym

Data Source

Active Serial

Active Parallel Up

APU

Altera Configuration EPROM
Parallel EPROM

Active Parallel Down

APD

Parallel EPROM

Passive Serial

Serial data path

Passive Parallel Synchronous

PPS

Intelligent host

Passive Parallel Asynchronous

PPA

Intelligent host

FLEX 8000 devices are supported by Altera's MAX+PLUS II development
system. MAX+PLUS II also supports the Altera Classic, MAX 5000/EPS464,
and MAX 7000 device families.
Designs can be entered as logic schematics with the Graphic Editor; as state
machines, truth tables, conditional logic, and Boolean equations with the
Altera Hardware Description Language (AHDL); or as waveforms with
the Waveform Editor. Logic synthesis and minimization automatically
optimize the logic of a design. MAX+PLUS II also provides automatic
design partitioning into multiple devices from the same family. Design
verification and timing analysis are performed with the built-in Simulator
and Timing Analyzer. Errors in a design can be automatically located and
highlighted in the original design files.
MAX+PLUS II software runs on 386- and 486-based PCs, as well as Sun
SPARCstations and HP 9000 Series 700 workstations. It gives designers the
tools to create complex logic designs quickly and efficiently. MAX+PLUS II
provides an EDIF netlist interface for additional design entry and simulation
support with popular CAE tools from Cadence, Intergraph, Logic Modeling,
Mentor Graphics, Synopsys, Viewlogic, and others. MAX+PLUS II also
exports Verilog and VHDL netlist files for use with other industry-standard
design verification tools.
Altera's FLEX 8000-compatible programming hardware includes the Altera
Logic Programmer card, the Master Programming Unit (MPU), and various
device adapters. The MPU supports continuity checking to ensure adequate
electrical contact between the adapter and the device. Configuration EPROM
device adapters are shipped with a special downloading cable that allows
users to configure FLEX 8000 devices in-circuit with Altera programming
hardware and the MAX+PLUS II Programmer. For more information on
programming hardware, see Altera Programming Hardware in this data
book. Further details about the MAX+PLUS II development system are
available in the MAX+PLUS II Programmable Logic Development System &
Software Data Sheet in this data book.

I Page 62

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Device Pin-Outs

Tables 7 and 8 show the pin names and numbers for each device package.

Table 7. FLEX 800084-, 100- & 160-Pin Package Pin-Outs (Part 1 of 2)
Pin Name
nSP (1)

84-Pin Plee
EPF8452

84-Pin Plee
EPF8282

100-Pin TQFP
EPF8282

160-Pin PGA
EPF8452

160-Pin PQFP
EPF8452

120

MSELO (1)

117

MSELl (1)

nSTATUS (1)

C13

nCONFIG (1)

A15

nWS

F13

nRS

RDCLK

DCLK (1)

100

P14

nCS

015

E15

RDYnBUSY

125

CLKUSR

CONF _DONE (1)

N13

ADD17

ADD16

ADD15

ADD 14

ADD13

ADD12

ADDl1

ADD10

ADD9

ADD8

101

ADD7

102

ADD6

103

ADDS

104

ADD4

105

ADD3

106

ADD2

109

ADDl

110

ADDO

123

I Altera Corporation

Page 63 I

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Table 7. FLEX 800084-, 100- & 160-Pin Package Pin-Outs (Part 2 of 2)
Pin Name

84-Pin Plee
EPF8452

84-Pin Plee
EPF8282

1DO-Pin TQFP
EPF8282

16D-Pin PGA
EPF8452

16D-Pin PQFP
EPF8452

DATA7

144

DATA6

P10

150

DATA5

R12

152

DATA4

R13

154

DATA3

P13

157

DATA2

R14

159

DATAl

N15

DATAO

K13

TDI (2)

TDO (2)

TCLK (2)

TMS (2)

nTRST (1)

Dedicated
Inputs

12,31,54,73

VCC

GND

52
12,31,54,73

3,23,53,73

C3,014,N2,R15 5,36,85,116

17,38,52,59,80 17,38,59,80

6, 20, 37, 56, 70,
87

B2, C4, 03, 08,
21,41,53,67,
012, G3, G12,
80,81, 100, 121,
H4, H13, J3, J12, 133,147, 160
M4, M7, M9,
M13, N12

5,26,47,68

2, 13, 30, 44, 52,
63,80,94

C12, 04, 07, 09,
013, G4, G13,
H3, H12, J4, J13,
L 1, M3, M8, M12,
M15, N4

5,26,47,68

13,14,28,46,
60,75,93,107,
108, 126, 140,
155

No Connect
(N.C.)

2, 3, 38, 39, 70,
82,83,118,119,
148

Total User I/O
Pins

116

Notes:
(1)
(2)

Dedicated configuration pin (not available as a user I/O pin).
If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.

I Page 64

Altera Corporation

I Data Sheet

FLEX 8000 Programmable Logic Device Family I

Table B. FLEX BODO 192-, 20B-, 232- & 240-Pin Package Pin-Outs (Part 1 of 2)
Pin Name
nSP (1)
MSELO (1)
MSELI (1)
nSTATUS (1)
nCONFIG (1)
nWS
nRS
RDCLK
DCLK (1)
nCS
CS
RDYnBUSY
CLKUSR
CONF _DONE (1)
ADD17
ADD16
ADDIS
ADD14
ADD 13
ADD12
ADDl1
ADDIO
ADD9
ADDS
ADD7
ADD6
ADDS
ADD4
ADD3
ADD2
ADDI
ADDO

I Altera Corporation

192-Pin PGA
EPF8820

208-Pin QFP
EPF8820

232-Pin PGA
EPF81188

240-Pin QFP
EPF81188

R15
T15
T3
83
C3
C5
85
C11
C15
813
A16
A8
A10
815
R5
U3
T5
U4
R6
T6
R7
T7
T8
U9
U10
U11
U12
R12
U14
U15
R13
U16

207
4
49
108
103
114
116
137
158
145
148
127
134
153
43
42
41
40
39
35
33
31
29
25
23
21
19
14
13
11
10
9

C14
G15
L15
L3
R4
P1
N1
G2
C4
E2
E3
K2
H2
G3
R15
T17
P15
M14
M15
M16
K15
K17
J14
J15
H17
H15
F16
F15
F14
D15
817
C15

237
21
40
141
117
133
137
158
184
166
169
146
155
160
58
56
54
47
45
43
36
34
32
29
27
25
18
16
14
7
5
3

Page 65

I FLEX 8000 Programmable Logic Device Family

Data Sheet

Table B. FLEX BODO 192-, 20B-, 232- & 240-Pin Pac~age Pin-Outs (Part 2 of 2)
Pin Name

192-Pin PGA
EPF8820

208-Pin OFP
EPF8820

232-Pin PGA
EPF81188

240-Pin OFP
EPF81188
205

DATA7

H17

178

DATA6

G17

176

203

DATA5

F17

174

200

DATA4

E17

172

198

DATA3

G15

171

196

DATA2

F15

167

194

DATAl

E16

165

191

DATAO

C16

162

189

TDI (2)

R11

TDO (2)

129

TCLK (2)

TMS (2)

nTRST (1)

Oedicated
Inputs

A5, U5, U13,
A13

17,36, 121,
140

VCC

C8, C9, C10,
03,04,09,
014,015, G4,
G14, L4, L14,
P4, P9, P14,
R8, R9, R10,
R14

5,6,26,27,
E4, E8, E10,
48, 55, 69, 87, E14, F5, F13,
102,119,131, H4, H5, H13,
141, 159, 173, H14, K5, K13,
191,206
L4, L14, M5,
M13, N8, N10,
P12, R14, U1

19,20,41,42,
64, 65, 66, 81,
99,114,116,
128,140,150,
162,172,186,
202,220,235,
236

GND

C4, D7, 08,
D10, 011, H4,
H14, K4, K14,
P7, P8, P10,
P11

15,16,37,38,
60,78,96,
109,110,120,
130,142,152,
164,182,200

A1, 06, E11,
E7, E9, G4,
G5, G13, G14,
J5, J13, K4,
K14, L5, L13,
N4, N7, N9,
N11, N14

8,9,30,31,
52, 53, 72, 90,
108, 115, 129,
139,151,161,
173,185,187,
193,211,229

1,2,3,50,51,
52,53,104,
105,106,107,
154,155,156,
157,208

61,62, 119,
120,181,182,
239,240

148

180

No Connect
(N.C.)

Total User liD
Pins

C1, C17, R1,
R17

10,51,130,
171

Notes:
(1)
(2)

I Page 66

Dedicated configuration pin (not available as a user I/O pin).
Available as a user I/O pin if device is not configured to use JTAG BST circuitry.

Altera Corporation

Contents
[AugUst 1993

Section 3

MAX 7000
MAX 7000 Programmable Logic Device Family ......................................... 69
EPM7032 EPLD .................................................................................... 83
EPM7032-15T EPLD ............................................................................ 89
EPM7032V EPLD Overview ............................................................... 91
EPM7064 EPLD .................................................................................... 93
EPM7096 EPLD .................................................................................... 99
EPM7128 EPLD .................................................................................. 107
EPM7160 EPLD .................................................................................. 117
EPM7192 EPLD .................................................................................. 127
EPM7256 EPLD .................................................................................. 137

Altera Corporation

Page 671

MAX 7000
Programmable Logic
Device Family

I August 1993, ver. 1

Data Sheet

Features ...

High-performance, erasable CMOS devices based on secondgeneration Multiple Array MatriX (MAX) architecture
Complete EPLD family with logic densities up to 10,000 available
gates (5,000 usable gates). See Table 1.
Fast, 7.5-ns pin-to-pin logic delays with up to 125-MHz counter
frequencies (including interconnect)
Programmable power-saver mode for up to 50% power reduction in
each macrocell
Programmable Security Bit for total protection of proprietary designs
Configurable expander product-term distribution allowing up to 32
product terms in each macrocell
44 to 208 pins available in J-Iead, pin-grid array (PGA), and quad flat
pack (QFP) packages, including 1-mm thin quad flat pack (TQFP)
High pin-to-logic ratio with user-defined 1/ 0 options for pin-intensive
applications such as 32-bit microprocessor interface logic
Enhanced Programmable Interconnect Array (PIA) that provides a
fast, fixed delay from any internal source to any destination in the
device
Advanced macrocell to efficiently place logic for optimum speed and
density
Programmable flipflops providing individual Clear, Preset, Clock,
and Clock Enable controls
Independent clocking of all registers from array or global Clock signals
3.3-V operation and advanced power management features provided
by EPM7032V device

o
o
o
o
o
o
o
o
o
o
o
o

Table 1. MAX 7000 Device Features

Feature

1,200

2,500

3,600

5,000

6,400

7,500

10,000

Usable Gates

600

1,250

1,800

2,500

3,200

3,750

5,000

Macrocells

128

160

192

256

Max. User liD

100

104

124

164

tpD (ns)

7.5

tASU (ns)

tco (ns)

4.5

fCNT (MHz)

125

90.9

125

100

90.9

62.5

Available Gates

EPM7032 EPM7032V EPM7064 EPM7096 EPM7128 EPM7160 EPM7192 EPM7256

Altera Corporation

Page 691

I MAX 7000 Programmable Logic Device Family

... and More
Features

o
o

General
Description

Data Sheet

Software design support featuring Altera's MAX+PLUS II development
system on 386- or 486-based PCs, Sun SPARC stations, or HP 9000
Series 700 workstations
Programming support with Altera's Master Programming Unit (MPU)
and programming hardware from other manufacturers
EDIF, Verilog, VHDL, and other interfaces providing additional design
entry and simulation support with popular CAE tools from vendors
such as Cadence, Data I/O, Exemplar, Intergraph, Mentor Graphics,
OrCAD, Synopsys, and Viewlogic

The MAX 7000 family of high-density, high-performance CMOS EPLDs is
based on Altera's second-generation MAX architecture. Fabricated on
advanced O.8-micron CMOS EEPROM and EPROM technologies, the MAX
7000 family provides 600 to 5,000 usable gates, pin-to-pin delays as low as
7.5 ns, and counter speeds up to 125 MHz.
The MAX 7000 architecture supports 100% TTL emulation and highdensity integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple programmable logic devices ranging from PALs, GALs, and
22V10s to MACH, pLSI, and FPGA devices. With speed, density, and I/O
resources comparable to commonly used masked gate arrays, MAX 7000
EPLDs are also ideal for gate-array prototyping. MAX 7000 EPLDs are
available in a wide range of packages, including plastic J-Iead chip carrier
(PLCC); ceramic pin-grid array (PGA); and the following quad flat pack
(QFP) packages: ceramic (CQFP), metal (MQFP), plastic (PQFP), or thin
(TQFP). See Table 2.

Table 2. MAX 7000 Pin Count & Package Options
Pin EPM7032
Count
44

PLCC,

EPM7032V EPM7064
PLCC, TQFP

Note (1)

EPM7096

EPM7128

EPM7160

EPM7192

EPM7256

PQFP, TQFP

PLCC

84
100

PQFP

160

PQFP

PQFP, PGA

192

PGA

208

CQFP, MQFP

Note:
(1)

Contact Altera for information on available device packages.

Page 70

Altera Corporation

I Data Sheet

MAX 7000 Programmable Logic Device Family

MAX 7000 EPLDs use CMOS EEPROM or EPROM cells to implement logic
functions within the device. The user-configurable MAX 7000 architecture
accommodates a variety of independent combinatorial and sequential
logic functions. EPLDs can be reprogrammed for quick and efficient
iterations during design development and debug cycles. Each EEPROMbased device is guaranteed for 100 program and erase cycles. Each EPROMbased device is guaranteed for 25 program and erase cycles.
MAX 7000 EPLDs contain from 32 to 256 macro cells that are combined into
groups called Logic Array Blocks (LABs). Each macrocell has a
programmable-AND / fixed-OR array and a configurable register that provides
independent programmable Clock, Clock Enable, Clear, and Preset
functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and highspeed parallel expander product terms to provide up to 32 product terms
per macrocell.
The MAX 7000 family provides programmable speed/ power optimization.
Speed-critical portions of a design can run at high speed/ full power, while
the remainder runs at reduced speed/low power. This speed/power
optimization feature enables the user to configure one or more macrocells
to operate at 50% or less power while adding only a nominal timing delay.
The MAX 7000 EPLD family is supported by Altera's MAX+PLUS II
development system, a single integrated package that offers schematic,
text, and waveform design entry; compilation and logic synthesis;
simulation; and programming software. MAX+PLUS II provides EDIF,
VHDL, Verilog, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and workstationbased CAE tools. MAX+PLUS II runs on 386- and 486-based PCs, Sun
SPARC stations, and HP 9000 Series 700 workstations.

Functional
Description

The MAX 7000 architecture includes the following elements:

o
o
o
o

Logic Array Blocks
Macrocells
Expander product terms (shared and parallel)
Programmable Interconnect Array
II 0 control blocks

In addition to these basic elements, the MAX 7000 architecture includes
four dedicated inputs that can be used as general-purpose inputs or as
high-speed, global control signals (Clock, Clear, and two Output Enable
signals) for each macrocell and II 0 pin. Figure 1 shows a portion of the
MAX 7000 architecture.

I Altera Corporation

Page 71

MAX 7000 Programmable Logic Device Family

Data Sheet

Figure 1. MAX 7000 Architecture

:
•

to
LAB B

8 to 161/0
pins per LAB

to
1/0 Control Block

Logic Array Blocks
MAX 7000 architecture is based on the concept of linking small, highperformance, flexible logic array modules called Logic Array Blocks (LABs).
Multiple LABs are linked together via the Programmable Interconnect
Array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells. All inputs to each LAB, except the global control signals, are
fed by 36 signals from the PIA. LABs consist of macrocell arrays, as shown
in Figure 1.

Macrocells
The MAX 7000 macrocell, shown in Figure 2, can be individually configured
for both sequential and combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select matrix,
and the programmable register.

Page 72

Altera Corporation

I Data Sheet

MAX 7000 Programmable Logic Device Family I

Figure 2. MAX 7000 Macrocell
Logic Array

......... " .. -_ ..................... -" .. .

':
4+--~+----4----+-~~.

Global
Clear

Global
Clock

Parallel Logic
Expanders
~ (from other
macrocells)

............;.... ·•. t .. ·..... J

to I/O
Control
Block

to PIA
Programmable
Interconnect
Signals

16 Expander
Product Terms

Combinatorial logic is implemented in the logic array, which contains five
product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell's register Clear, Preset, Clock, and Clock Enable control
functions. One product term per macrocell can be inverted and directly fed
back into the logic array. This "shareable" product term can be connected
to any other product term within the LAB. Based on the logic requirements
of the design, MAX+PLUS II automatically optimizes product-term
allocation.
In registered functions, each macrocell flipflop can be individually
programmed to emulate D, T, JK, or SR operation with programmable
Clock control. If necessary, the flipflop can be bypassed for combinatorial
operation. During design entry, the user specifies the desired flipflop type
and MAX+PLUS II selects the most efficient flipflop operation for each
registered function to minimize the resources needed by the design.

I Altera Corporation

Page 73

I MAX 7000 Programmable Logic Device Family

Data Sheet

Three clocking modes are available for each programmable register:

A register can be clocked by the dedicated global Clock pin (GCLK). In
this mode, the flipflop is positive-edge-triggered, and offers the fastest
Clock-to-output performance.

A register can be clocked by an array Clock implemented with a
product term. In this mode, the flipflop can be configured for positiveor negative-edge-triggered operation. Array Clocks allow any signal
source within the device or gated logic functions to clock the flipflop.

A register can be clocked by a global Clock pin and enabled by a
product term. The register is enabled when the Clock Enable (ENA)
input is high. Each flipflop can be activated individually while taking
advantage of the fast Clock-to-output delay of the global Clock pin.

Each register also supports asynchronous Preset and Clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product terms that drive the
Preset and Clear are active-high, active-low control is provided when the
signal is inverted within the logic array. In addition, each register Clear
function can be individually driven by the active-low dedicated global
Clear pin (GCLRn).

Expander Product Terms
Although most logic functions can be implemented with the five product
terms available in each macrocell, some logic functions are more complex
and require additional product terms. Instead of using another macrocell
to supply the needed logic resources, the MAX 7000 architecture offers
both shared and parallel expander product terms (If expanders") that provide
additional product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest possible
logic resources to obtain the fastest possible speed.
Each LAB has up to 16 shareable expanders, which can be viewed as a pool
of uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable expander
can be used and shared by any or all macrocells in the LAB to build
complex logic functions. Shareable expanders can also be cross-coupled to
build additional buried flipflops, latches, or input registers. A small delay
(tSEXP) is incurred when shareable expanders are used. Figure 3 shows
how shareable expanders can feed multiple macrocells.

Page 74

Altera Corporation

I Data Sheet

MAX 7000 Programmable Logic Device Family

Figure 3. Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.

Macrocell
Product-Term
Logic

-------------... ---......... ~ ........ j
.....................................

Product-Term Select Matrix

.........•
Macrocell
Product-Term
Logic

Parallel expanders are unused product terms from macrocells that can be
allocated to a neighboring macrocell to implement fast, complex logic
functions. With parallel expanders, up to 20 product terms can directly
feed the macrocell OR logic-5 product terms provided by the macro cell
and 15 parallel expanders provided by neighboring macrocells in the LAB.
The MAX+PLUS II Compiler can automatically route a set of up to 5
parallel expanders to the necessary macrocells. Up to 3 sets of 5 parallel
expanders can be routed to a single macrocell. Each set of 5 expanders
incurs a small, incremental timing delay (tPEXP). For example, if a macrocell
requires 14 product terms, the Compiler uses the 5 dedicated product
terms within the macrocell and allocates 2 sets of parallel expanders; the
first set includes 5 product terms and the second set includes 4 product
terms, increasing the total delay by 2 x t pEXP .
Two groups of 8 macrocells within the LAB (macrocells 1 to 8 and 9 to 16)
form 2 chains to lend or borrow parallel expanders. A macrocell borrows
parallel expanders from lower-numbered macrocells. For example,
macroce1l8 can borrow parallel expanders from macroce1l7, from macrocells
7 and 6, or from macro cells 7, 6, and 5. Within each group of 8, the lowestnumbered macrocell can only lend parallel expanders, and the highestnumbered macrocell can only borrow them. Figure 4 shows how parallel
expanders can be borrowed from a neighboring macrocell.

Altera Corporation

Page

751

I MAX 7000 Programmable Logic Device Family

Data Sheet

Figure 4. Parallel Logic Expanders
These unused product terms in a macrocell can be allocated to a neighboring macro cell.
from
previous
macrocell
............ - ..... -_ .. ------------------------

--------_ ...... _-----_ .. _------_.
Preset i

Clear

Macrocel/
Product-Term
Logic

to next
macrocell

Programmable Interconnect Array
Logic is routed between LABs on the Programmable Interconnect Array
(PIA). This global bus is a programmable path that routes any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
110 pin feedbacks, and macrocell feedbacks feed the PIA and route across
the entire device. Only the signals required by each LAB are actually
routed from the PIA into the LAB. Figure 5 shows how the PIA signals are
routed into the LAB. An EPROM or EEPROM cell controls one input to a
2-input AND gate, which selects a PIA signal to drive into the LAB.
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000 PIA has a fixed delay. The PIA thus
eliminates skew between signals, and makes timing performance easy to
predict.

I Page 76

Altera Corporation

I Data Sheet

MAX 7000 Programmable Logic Device Family

Figure 5. PIA Routing

to LAB

PIA Signals

I/O Control Blocks
The I/O control block, shown in Figure 6, allows each I/O pin to be
individually configured for input, output, or bidirectional operation. All
I/O pins have a tri-state buffer that is controlled by one of two global
active-low Output Enable pins (OEln and OE2n) or directly connected to
GND or vee. When the tri-state buffer control is connected to GND, the
output is tri-stated (high impedance) and the I/O pin can be used as a
dedicated input. When the tri-state buffer control is connected to vee, the
output is enabled.
MAX 7000 architecture provides dual I/O feedback, in which macrocell
and pin feedbacks are independent. When an I/O pin is configured as an
input, the associated macro cell can be used for buried logic.

Figure 6. I/O Control Block
vee
OE1n
OE2n

OE Control

GND

from Macrocell
to PIA

I Altera Corporation

Page 77

MAX 7000 Programmable Logic Device Family

Programmable
Speed/Power
Control

Data Sheet I

The MAX 7000 family offers a power-saver mode that supports low-power
operation across user-defined signal paths or the entire device. This feature
allows total power dissipation to be reduced by up to 50%, since most logic
applications require only a small fraction of all gates to operate at maximum
frequency.
The designer can program each individual macrocell in a MAX 7000 EPLD
for either high-speed (Turbo Bit on) or low-power (Turbo Bit off) operation.
As a result, speed-critical paths in the design can run at high speed, while
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal additional timing delay (tLPA) for the t LAD, t IO t LAC'
t ACV tEN' and t SEXP parameters.

Design Security

All MAX 7000 EPLDs contain a programmable Security Bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
since programmed data within EPROM or EEPROM cells is invisible. The
Security Bit that controls this function, as well as all other program data, is
reset when an EPLD is erased.

Timing Model

MAX 7000 EPLD timing can be analyzed with MAX+PLUS II software,
with a variety of popular industry-standard CAE simulators and timing
analyzers, or with the timing model shown in Figure 7. MAX 7000 devices
have fixed internal delays that allow the user to determine the worst-case
timing for any design. MAX +PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for systemlevel performance evaluation.

Figure 7. Timing Model
1 - - - - - - - - - - - - + 1 Output Delays
too
Register
Delays

txz
tzx

tsu
tH
tpRE
tCLR

tRO
tCOMB

Page 78

Altera Corporation

Data Sheet

MAX 7000 Programmable Logic Device Family

Timing information can be derived from the timing model and parameters
for a particular EPLD. External timing parameters can be calculated from
the sum of internal parameters and represent pin-to-pin timing delays.
Figure 8 shows the internal timing relationship for internal and external
delay parameters. See Application Brief 100 (Understanding EPLD Timing) in
this data book for more information.
Figure 8. Switching Waveforms (Part 1 of 2)
tR & tF<3 ns.
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
measured at 1.5 II.

Combinatorial Mode

Input Pin

1/0 Pin

==1~---+;----------------
:_t"y-__ :

====:X

~--~~----------------

i~!

PIA Delay

Shared Expander
Delay

--------~x~~:-------------------
i,fsExP'i
------------~x~-+i------------------!-tLAC' tLAO- !

Logic Array
Input

--------------~x~

______~:----------'!
:-

------

t pEXP

Parallel Expander
Delay

----------------------~X~~:
tCOMB-i

Logic Array
Output

---------------------------------,X~~---

Output Pin

---------------------------'--*==
Array Clock Mode

tF-i t-

tR-i i-tACH---i i-tACL-i
Input or I/O Pin

~!
:

Clock into PIA

Clock into
Logic Array
Clock at
Register
Data from
Logic Array

tiN

1~!
____~i-_t_~_A-~V.

I Altera Corporation

\<-!- - - - -

\'______...JI,-------~\'_

_____

\'____~/'-------

!-t,C -! ,....-------,

---------'-!----11

\"---__--.J/

--------,~~*,-----,1'------tRo-l

:-tpIA-:

!.- tCLR ' tpRE--i

:+--tplA

-----------~--~'~~X~--~----~-x===

!--too - :
i-too--:
--------~'--~X~--------~--t

Page

791

I MAX 7000 Programmable Logic Device Family

Data Sheet

Figure 8. Switching Waveforms (Part 2 of 2)
Global Clock Mode
Global
Clock Pin
Global Clock
at Register

\'----

Data or Enable
(Logic Array Output)

Generic Testing

MAX 7000 EPLDs are fully functionally tested and guaranteed. Complete
testing of each programmable EEPROM or EPROM bit and all internal
logic elements ensures 100% programming yield. AC test measurements
are taken under conditions equivalent to those shown in Figure 9.
Test patterns can be used and then erased during early stages of the device
production flow. EPROM-based EPLDs in one-time-programmable
windowless packages also contain on-board logic circuitry to allow
verification of function and AC specifications during this production flow.

Figure 9. MAX 7000 AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast groundcurrent transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, it can create significant
reductions in observable noise immunity.

MAX+PLUS II
Development
System

I Page 80

..-----vcc
464Q

Device
Output

to Test
System

250Q

Device input
rise and fall
times < 3 ns

MAX 7000 EPLDs are supported by the MAX+PLUS II development
system, a completely integrated environment for design entry, compilation,
verification, and programming. MAX+PLUS II software is available for
386- and 486-based PCs, as well as Sun SPARCstations and HP 9000 Series
700 workstations. All platforms include more than 300 74-series
macro functions and the Altera Hardware Description Language (AHDL),
which supports state machine, Boolean equation, conditional logic, and
truth table entry methods. MAX+PLUS II also provides highly automated
compilation, automatic multi-device partitioning, timing simulation and
analysis, automatic error location, device programming and verification,
and a comprehensive on-line help system.
Altera Corporation

I Data Sheet

MAX 7000 Programmable Logic Device Family

In addition, MAX+PLUS II imports and exports industry-standard EDIF
200 and 2 9 0 netlist files for a convenient interface to industry-standard
PC- and workstation-based CAE tools from vendors such as Cadence,
Data 1/ 0, Exemplar, Intergraph, Mentor Graphics, OrCAD, Synopsys, and
Viewlogic. MAX+PLUS II also exports Verilog or VHDL netlist files to
support simulation with the Cadence Verilog-XL simulator or various
VHDL simulators. For further details about MAX+PLUS II and other CAE
tools, see the MAX+PLUS II Programmable Logic Development System &
Software Data Sheet and CAE Software Support in this data book.

Device
Programming

All MAX 7000 EPLDs can be programmed on 386- or 486-based PCs with
an Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity checking
to ensure adequate electrical contact between the adapter and the device.
See Altera Programming Hardware in this data book for more information.
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text or Waveform Editor to test the
programmed device. For added design verification, designers can perform
functional testing to compare the functional behavior of a MAX 7000 EPLD
with the results of simulation. This feature requires a device adapter with
the "PLM-" prefix.
Data I/O and other programming hardware manufacturers also provide
programming support for Altera devices. See Programming Hardware
Manufacturers in this data book for more information.

QFP Carrier &
Development
Socket

[Mtera Corporation

MAX 7000 devices in 100-plus pin QFP packages are shipped in special
plastic carriers to protect the fragile QFP leads. The carrier is used with a
prototype development socket and special programming hardware
available from Altera. This carrier technology makes it possible to program,
test, erase, and reprogram a device without exposing the leads to mechanical
stress. For detailed information and carrier dimensions, refer to the QFP
Carrier & Development Socket Data Sheet in this data book.

Page 81

Notes:

EPM7032 EPLD
Features

High-performance, erasable CMOS EPLD based on second-generation
MAX architecture
600 usable gates
Combinatorial speeds with tpD = 7.5 ns
Counter frequencies up to 125 MHz
Advanced O.B-micron CMOS EEPROM technology
Programmable I/O architecture with up to 36 inputs or 32 outputs
32 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing 32 product
terms in a single macro cell
Available in 44-pin packages (see Figure 10):
EIAJ-standard plastic quad flat pack (PQFP)
l.O-mm thin quad flat pack (TQFP)
Plastic J-lead chip carrier (PLCC)
Low-cost "T" version available (See "EPM7032-15T EPLD" in this
data sheet).

o
o

Figure 10. EPM7032 Package Pin-Out Diagrams
Package outlines not drawn to scale.

i§ ~ ~

Pin34

I/O

GND

5 4

1 44 4342 41 40

I/O

vee

I/O

vee

I/O

EPM7032

GND

I/O
I/O -L--,,;--n---rr-,,----,,;--n---rr-rr-n-rr-,,-J -.

I/O

~~~~~8~~~~~
C!l >

44-Pin QFP

General
Description

I Altera Corporation

44-Pin J-Lead

The Altera EPM7032 is a high-performance, high-density CMOS EPLD
based on Altera's second-generation MAX architecture. See Figure 1l.
Fabricated on a O.B-micron EEPROM technology, the EPM7032 provides
in-system speeds of 125 MHz and propagation delays of 7.5 ns. The
EPM7032 architecture supports 100% TTL emulation and allows the

Page 83

Data Sheet

EPM7032 EPLD

integration of 55I, M5I, and custom logic functions. It can replace multiple
20- and 24-pin PLDs. The EPM7032 can accommodate designs with up to
36 inputs or 32 outputs.

Figure 11. EPM7032 Block Diagram

I
I
1
:=;;~;~===========~i=:===========;;~;~i::===========:i=i:===========~-'

Pin numbers without parentheses are for the PLCC packages. Pin numbers in parentheses are for OFP packages.
INPUT/GCLK (37) 43
INPUT/GCLRn (39) 1

:~:~~;~::~ :::: 4:

•. ;('>':::;,',: :'::~','~~:~;

.----'--'--..,

MACROCELL 32

(42)

(18)

(43)

(19)

(44)

(20)

(1)

(21)

(2)

(22)

(3)

(23)

(5)

(25)

(6)

(7)

1/0

(26)

(27)

PIA

(8)

(28)

(10)

(30)

(11)

(31)

(12)

(32)

(13)

(33)

(14)

(34)

(15)

(35)

Page 84

Altera Corporation

I Data Sheet

EPM7032 EPLD

Figure 12 shows the output drive characteristics of EPM7032 1/ 0 pins.

Figure 12. Typical EPM1032 Output Drive Characteristics
150

ci.
~ 120
~

.s
c
~

Vee = 5.0 V
Room Temp.

()

"5
0..
"5

..9

Va Output Voltage (V)

Figure 13 shows typical supply current versus frequency for the EPM7032.

Figure 13. EPM1032 Icc vs. Frequency
200r----------------------------,

Icc for the EPM7032-12 and EPM7032-15 is calculated with the
following equation:
Icc =(O.9x MCroN) + (0.55 x MCroFF ) + [(0.018 x MC) x fMAXi

180

Vee = 5.0 V
Room Temp.

160

Icc for the EPM7032-7, EPM7032-10, and EPM7032-15T is
~140
calculated with the following equation:
~
«
120
Icc = (2.2 x MCroN) + (0.55 x MC roFF ) + [(0.018 x MC) x fMAXi E

Turbo for EPM7032-7,
EPM7032-10, and
EPM7032-15T

-; 100

The parameters for this equation are:
MC roN = number of macrocel/s used with Turbo Bit on
MC roFF = number of macrocells used with Turbo Bit off
MC
= total number of macrocells used in the design
(MC roN + MC roFF)
fMAX
= highest Clock frequency to the device
This measurement provides an Icc estimate based on typical
conditions (Vcc =5.0 \I, room temperature) using a typical
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB and no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual
pattern in the device and the environmental operating
conditions.

I Altera Corporation

·u«

~ 60

,90.9MHz

~ Turbo for
EPM7032-12 and
Non-Turbo
EPM7032-15

~5.5 MHz

100

125

150

Frequency (MHz)

Page 85

EPM7032 EPLD

Data Sheet I

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Min

Max

Unit

vee

Supply voltage

Parameter

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

300

lOUT

DC output current, per pin

Power dissipation

Conditions

-25

1500

T STG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

Input fall time

Max

Unit
V

DC Operating Conditions
Symbol

For commercial use

Notes (2), (3)

Parameter

Conditions

Speed
Grade

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

VO H

High-level TTL output voltage

2.4

10H =-4 mA DC

V
V

VOL

Low-level output voltage

10L = 8 mA DC

0.45

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

JlA
JlA

lee1

Vee supply current

V 1= GND, No load

-12, -15

(low-power mode, standby)

Note (4)

-7, -10, -15T

Vee supply current

V 1= GND, No load,

-12, -15

(low-power mode, active)

f = 1.0 MHz, Note (4) -7, -10, -15T

100

Min

Max

Unit

lee2

Capacitance
Symbol

Note (5)
Parameter

Conditions

CIN

Input capacitance

V I N = 0 v, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

Page 86

Altera Corporation

I Data Sheet

EPM7032 EPLD

AC Operating Conditions

Note (3)

External Timing Parameters

Symbol

Parameter

EPM7032-7

EPM7032-10 EPM7032-12

Conditions Min Max Min

Max

Min

Max

EPM7032-15

Min

Max Unit

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

C1 = 35 pF

7.5

4.5

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

Array clock setup time

tAH
t AC01

Array clock hold time

tACH
t ACl

Array clock high time

Array clock low time

tCNT

Minimum global clock period

tCNT
t ACNT

Max. int. global clock freq.
Minimum array clock period

t ACNT
tMAX

Array clock to output delay

C1 = 35 pF

7.5

C1 = 35 pF

ns
ns

12
5

8
5

10
4

6
11

ns
MHz

125.0

Max. int. array clock freq.

Note (4)

125.0

100

90.9

76.9

MHz

Maximum clock frequency

Note (6)

166.7

125

100

MHz

Parameter

90.9

ns
ns

Note (4)

100

EPM7032-7

76.9
11

Internal Timing Parameters

Symbol

EPM7032-10 EPM7032-12

Conditions Min Max Min

Max

Min

Max

EPM7032-15

Min

Max Unit

tiN

Input pad and buffer delay

0.5

ns
ns

tlO

1/0 input pad and buffer delay

t SEXP
t pEXP
t LAO

Shared expander delay

Parallel expander delay

0.8

Logic array delay

t LAC

Logic control array delay

too

Output buffer and pad delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu

tH
t RO

tCOMB

Combinatorial delay

tiC

Array clock delay

tEN
t GLOB

Global control delay

ns
ns

=35 pF
=5 pF

ns
ns

4
4

ns
ns

tpRE

tCLR

tplA
t LPA

Prog. Interconnect Array delay

Low power adder

I Altera Corporation

Note (7)

Page 87

I EPM7032 EPLD

Data Sheet

Notes to tables:
(1)
(2)
(3)

(4)
(5)
(6)
(7)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee = 5.0 V.
Operating conditions: Vee = 5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5.0 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee =5.0 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. The OEln pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
The fMAX values represent the highest frequency for pipelined data.
The t LPA parameter must be added to the t LAO' t LAC' tIC' t ACLr tEN' and t SEXP
parameters for macrocells running in low-power mode.

Product Grade

Availability
EPM7032-7, EPM7032-10,

Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C)

EPM7032-12, EPM7032-15

Military Temp.

(-55° C to 125° C)

Consult factory

EPM7032-12, EPM7032-15

New SpeedGrade Ordering
Codes

Speed-grade codes for EPM7032 devices have changed. The following
table provides the new codes, which indicate the actual propagation delay
times.

Old Speed Grade

I Page 88

New Speed Grade

EPM7032-1

EPM7032-10

EPM7032-2

EPM7032-12

EPM7032-3

EPM7032-15

Altera Corporation

EPM7032-15T EPLD
Features

Low-cost version of the EPM7032. See "EPM7032" in this data sheet
for more information.
High performance 32-macrocell EPLD
Combinatorial speeds with tpD = 15ns.
Counter frequency as high as 76.9 MHz
Pin, function, and programming-file compatible with the EPM7032.

AC Operating Conditions (Part 1 of 2)
External Timing Parameters Note (1)
Symbol
Parameter

Conditions

Min

= 35 pF

Max

Unit

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

= 35 pF

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

Array clock setup time

Array clock hold time

tAH
t AC01

Array clock to output delay

= 35 pF

ns
15

tACH
t ACl

Array clock high time

6.5

Array clock low time

6.5

tCNT

Minimum global clock period

tCNT
t ACNT

Max. internal global clock frequency

t ACNT
tMAX

ns
ns
ns

Note (3)

76.9

Max. internal array clock frequency

Note (3)

76.9

MHz

Maximum clock frequency

Note (4)

83.3

MHz

Minimum array clock period

I Altera Corporation

MHz
13

Page 89

I EPM7032·15T EPLD

Data Sheet

AC Operating Conditions

(Part 2 of 2)

Internal Timing Parameters Note (1)
Symbol

Conditions

Parameter

Min

Max

Unit

tIN

Input pad and buffer delay

tlO
t SEXP

I/O input pad and buffer delay

Shared expander delay

t pEXP

Parallel expander delay

t LAO

Logic array delay

t LAC

Logic control array delay

too

Output buffer and pad delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu
tH
t RO

tCOMB

Combinatorial delay

tIC

Array clock delay

tEN
t GLOB

Global control delay

tpRE

tCLR

tplA
t LPA

Prog. Interconnect Array delay
Low-power adder

=35 pF

=5 pF

Note (5)

ns
ns
ns

Notes to tables:
(1) Operating conditions: Vee = 5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
(2) Typical values are for TA = 25° C and Vee = 5.0 V.
(3) Measured with a device programmed as a 16-bit counter in each LAB.
Icc is measured at 0° C.
(4) The fMAX values represent the highest frequency for pipelined data.
(5) The tLPA parameter must be added to the tLAD, tLAC' t ACV tEN, tIC, and t SEXP parameters for macrocells running in low-power
mode.

Product
Availability

I Page 90

Product Grade
Commercial Temp.

(0° C to 70° C)

Availability
EPM7032-15T

Altera Corporation

EPM7032V EPLD Overview
Features

3.3-V version of the popular EPM7032 EPLD
Combinatorial speeds with tpD = 12 ns
Counter frequencies up to 90.9 MHz
Innovative power-saving features
30% to 50% power savings over 5-V operation
Power-down mode controlled by a power-down pin to allow
zero power consumption during periods of inactivity
Programmable power-saver mode for up to 50% power reduction
during active operation, configurable for each macrocell
Advanced O.8-micron CMOS EEPROM technology
Programmable 1/ 0 architecture allowing up to 36 inputs or 32 outputs
32 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Independent clocking of all registers from array or global Clock signals
Available in 44-pin plastic reprogrammable packages (see Figure 14):
1.0-mm thin quad flat pack (TQFP)
J-lead chip carrier (PLCC)

For detailed
information, refer
to "EPM 7032 V"
in the 3.3-Volt
Devices Data
Sheet in this data
book.

o
o

Figure 14. EPM7032V Package Pin-Out Diagrams
Package outlines not drawn to scale.

5 4

1 44 4342 41 40

~
36

110

vee

110

35
34

110

EPM7032V

110

GND

110

GND

110

vee

110
110

110

vee

EPM7032V

110

GND

110

18 19 20 21 22 23 24 25 2627 28

~~~~~g~~~~~
Cl >

44-Pin J-Lead

I Altera Corporation

~ ~ ~ ~ ~

g
>

~ ~ ~ ~ ~

Pin 23

44-Pin QFP

Page 91

Notes:

EPM7064 EPLD
Features

Preliminary
Information

o
o

High-performance, erasable CMOS EPLD based on second-generation
MAX architecture
1,250 usable gates
Combinatorial speeds with tpD = 7.5 ns
Counter frequencies up to 125 MHz
Advanced 0.8-micron CMOS EEPROM technology
Programmable I/O architecture with up to 68 inputs or 64 outputs
64 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing 32 product
terms in a single macrocell
Available in the following packages (see Figure 15):
84-pin plastic J-Iead chip carrier (PLCC)
100-pin EIAJ-standard plastic quad flat pack (PQFP)

Figure 15. fPM7064 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Tables 3 and 4 in this data sheet for pin-out
information.

1/0

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

vee
1/0
1/0
1/0
1/0
1/0
GND

110
110
110
1/0
1/0

110

vee
1/0
1/0

110
110
1/0
GND

84-Pin J-Lead

General
Description

Altera Corporation

1/0
1/0
GND

1/0
1/0
1/0
1/0
1/0

vee
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0

100-Pin QFP

The Altera EPM7064 is a high-performance, high-density CMOS EPLD
based on Altera's second-generation MAX architecture. See Figure 16.
Fabricated on a 0.8-micron EEPROM technology, the EPM7064 provides
counter speeds of 125 MHz and propagation delays of 7.5 ns. The EPM7064
architecture supports 100% TTL emulation and allows the integration of

Page 931

I EPM7064 EPLD

Preliminary Information

Data Sheet

55I, M5I, and custom logic functions. It can replace multiple 20- and 24-pin
PLDs. The EPM7064 can accommodate designs with up to 68 inputs or 64
outputs.

Figure 16. EPM7064 Block Diagram
INPUT/GCLK ~
INPUT/GCLRn c::>---------_t_---_,
INPUT/OE1n c : : > - - . . - - - - - H - - - - -.......
INPUT/OE2n c::>---++-----t+------1H-t+-----t-+-------,

+-----++--------,

12to 16
110 pins

12t016

Figure 17 shows the output drive characteristics of EPM7064I/O pins.

Figure 17. Typical EPM7064 Output Drive Characteristics
150

ci.
~

120

.s
~

Vcc =5.0V
Room Temp.

'5
a.
'5

60
45
30

Va Output Voltage (V)

I Page 94

Altera Corporation

I Data Sheet

Preliminary Information

Absolute Maximum Ratings
Symbol

EPM7064 EPLD

See Operating Requirements for Altera Devices in this data book.

Parameter

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

300

lOUT

DC output current, per pin

Power dissipation

Conditions

-25

1500

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

0
-40

°C

Case temperature

For military use

-55

°C

tR
tF

Input rise time

125
40

Input fall time

DC Operating Conditions
Symbol

Notes (2), (3)

Parameter

Conditions

Typ

Max

Unit

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage
Low-level output voltage

10L = 8 mA DC

Input leakage current

V I = Vee or GND

loz

Tri-state output off-state current

Vo = Vee or GND

lee1

Vee supply current
(low-power mode, standby)

V 1= GND, No load

Vee supply current
(low-power mode, active)

V I = GND, No load,
f = 1.0 MHz, Note (4)

Capacitance

2.4

10H =-4 mADC

VOL

lee2

Min

-10
-40

0.45
10

Note (4)

Note (5)

Symbol

Parameter

Conditions

Min

Max

Unit

CIN

Input capacitance

V I N = 0 v, f = 1.0 MHz

COUT

Output capacitance

VOUT= 0 V, f= 1.0 MHz

I Altera Corporation

Page 95

I EPM7064 EPLD

Preliminary Information

AC Operating Conditions
Symbol

Data Sheet

Note (3)

Parameter

Conditions Min Max Min

Max

Min Max Min

7.5

Max Unit
15

7.5

t pD1

Input to non-registered output

tpD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

C1 = 35 pF

4.5

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU
tAH
t AC01

C1 = 35 pF

6
4

ns
ns

Global clock low time

Array clock setup time

Array clock hold time

Array clock to output delay

7.5

C1 = 35 pF

tACH
t ACl

Array clock high time

Array clock low time

tCNT

Minimum global clock period

fCNT

Max. internal global clock
frequency

t ACNT
f ACNT

Minimum array clock period

f MAX

Symbol

10
4

12
5

5
10

15
6

6
11

125.0

Max. internal array clock
frequency

Note (4)

125.0

100

90.9

76.9

MHz

Maximum clock frequency

Note (6)

166.7

125

100

MHz

100

Conditions Min Max Min

Max

76.9

Note (4)

Parameter

90.9

ns
ns

Min

Max

MHz
13

Min

Max Unit

tIN

Input pad and buffer delay

0.5

tlO
t SEXP

I/O input pad and buffer delay

0.5

Shared expander delay

t pEXP

Parallel expander delay

0.8

t LAO

Logic array delay

t LAC

Logic control array delay

too

Output buffer and pad delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu
tH
t RO

tCOMB

Combinatorial delay

tIC

Array clock delay

tEN

tGLOB

Global control delay

tpRE

tCLR

tplA
t LPA

Prog. Interconnect Array delay

I Page 96

Low power adder

=35 pF

=5 pF

Note (7)

ns
ns

Altera Corporation

Preliminary Information

Data Sheet

EPM7064 EPLD

Notes to tables:
(1)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee =5.0 V.
Operating conditions: Vee =5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5.0 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee =5.0 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample tested only. The OEln pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
.
The f MAX values represent the highest frequency for pipelined data.
The t LPA parameter must be added to the t LAD, t LAC' tIC' tACV tEN' and t SEXP parameters
for macrocells running in low-power mode.

(2)
(3)

(4)
(5)
(6)
(7)

Product
Avai labi Iity

New SpeedGrade Ordering
Codes

Pin-Out
Information

Device Qualification
Commercial Temp.

EPM7064-10, EPM7064-12, EPM7064-15

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

Speed-grade codes for EPM7064 devices have changed. The following
table provides the new codes, which indicate the actual propagation delay
times.
Old Speed Grade

New Speed Grade

EPM7064-1

EPM7064-10

EPM7064-2

EPM7064-12

EPM7064-3

EPM7064-15

Tables 3 and 4 provide pin-out information for the EPM7064 packages.

Table 3. EPM7064 Dedicated Pin-Outs
Dedicated Pin
GCLK
GCLRn
OEln
OE2n
GND
VCC

No Connect (N.C.)

I Altera Corporation

Availability

(0° C to 70° C)

84-Pin J-Lead
83
1
84
2
7,19,32,42,47,59,72,82
3,13,26,38,43,53,66,78

100-Pin QFP
89
91
90
92
13,28,40,45,61,76,88,97
5,20,36,41,53,68,84,93
1,2,7,9,24,26,29,30,51,
52,55,57,72,74,79,80

Page

971

I EPM7064 EPLD

Preliminary Information

Data Sheet

Table 4. EPM7064 I/O Pin-Outs

I Page 98

LAB

84-Pin
J-Lead

100-Pin
QFP

LAB

84-Pin
J-Lead

100-Pin
QFP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

22
21
20
18
17
16
15
14
12
11
10
9
8
6
5
4
44
45
46
48
49
50
51
52
54
55
56
57
58
60
61
62

16
15
14
12
11
10
8
6
4
3
100
99
98
96
95
94
42
43
44
46
47
48
49
50
54
56
58
59
60
62
63
64

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

41
40
39
37
36
35
34
33
31
30
29
28
27
25
24
23
63
64
65
67
68
69
70
71
73
74
75
76

39
38
37
35
34
33
32
31
27
25
23
22
21
19
18
17
65
66
67
69
70
71
73
75
77
78
81
82
83
85
86
87

B
B
B
B
B
B
B
B
B
B
B
B
B
B
B

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

79
80
81

Altera Corporation I

EPM7096 EPLD
o

Features

o
Preliminary
Information

o
o

High-density, erasable CMOS EPLD based on second-generation MAX
architecture
1,800 usable gates
Combinatorial speeds with tpD = 7.5 ns
Counter frequencies up to 125 MHz
Advanced O.8-micron CMOS EEPROM technology
Programmable 110 architecture providing up to 76 inputs or 72 outputs
96 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Available in the following packages (see Figure 18):
68- and 84-pin plastic J-Iead chip carrier (PLCC)
100-pin EIAJ-standard plastic quad flat pack (PQFP)

Figure 18. EPM7096 Package Pin-Out Diagrams

Package outlines not drawn to scale. See Tables 5 and 6 in this
data sheet for pin-out information.

I-=>I-t::>a.:>:J

~~~~

1/0

vee
1/0
1/0
1/0
1/0
1/0
GND

1/0
1/0
1/0
1/0
1/0
1/0

vee
110
110
1/0
1/0
1/0
GND

74
73

1/0
1/0

GND

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

1/0
1/0
1/0
1/0

110

vee
1/0
1/0
1/0
1/0
1/0
1/0
GND

1/0
1/0
1/0
1/0
1/0

~~~~~~~~~~g~~~~~~

Pin 1

m~~~~vMN~~~~~~~~~

1/0

vee
1/0
1/0
1/0

10
11
12

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

110
GND

1/0
1/0
1/0
1/0

vee

1/0
1/0
1/0
1/0

EPM7096

GND

1/0
1/0
GND

1/0
1/0
1/0
1/0

vee
1/0

110
1/0
1/0
GND

1/0
1/0
1/0
1/0

EPM7096

~~~~g~~~g~~~~~~~g
>

84-Pin J-Lead

General
Description

I Altera Corporation

(!»

C!)

68-Pin J-Lead

Pin 51

100-Pin QFP

The Altera EPM7096 is a high-density, high-performance CMOS EPLD
based on Altera's second-generation MAX architecture. See Figure 19.
Fabricated on a O.8-micron EEPROM technology, the EPM7096 provides
1,800 usable gates, counter speeds of 125 MHz, and propagation delays of
7.5 ns. The EPM7096 architecture supports 100% TTL emulation and allows
high integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple programmable logic devices ranging from PALs, GALs, and
Page 99

I EPM7096

Preliminary Information

EPLD

Data Sheet

22V10s to MACH devices and FPGAs. The EPM7096 can accommodate
designs with up to 76 inputs or 72 outputs.

Figure 19. EPM7096 Block Diagram
INPUT/GCLK
INPUT/GCLRn
INPUT/OE1n
INPUT/OE2n

c:::>---------.......- - - - - - . - - - - - - - ,
c:::>---------.-r-----.......+---------,

81012
1/0 pins

81012

Page 100

81012

Altera Corporation

I Data Sheet

Preliminary Information

EPM7096 EPLD

Figure 20 shows the output drive characteristics of EPM70961/ a pins.
Figure 20. EPM7096 Output Drive Characteristics
150

c.i.
~

120

S
~

Vee = 5.0 V
Room Temp.

:;
0

"5
a.
"5

..9

V0 Output Voltage (V)

Figure 21 shows typical supply current versus frequency for the EPM7096.
Figure 21. EPM7096 Icc vs. Frequency
Icc is calculated with the following equation:
Icc =(0.91 x MG roN) + (0.48 x MGroFF ) + [(0.0053 x MG) x

200

fMAXi

The parameters for this equation are:
MGroN = number of macrocells used with Turbo Bit on
MG roFF = number of macrocells used with Turbo Bit off
MG
total number of macrocells used in the design
(MG roN + MG roFF)
fMAX
= highest Glock frequency to the device
This measurement provides an Icc estimate based on typical
conditions (Vcc =5.0 V, room temperature) using a typical
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB with no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual
pattern in the device and the environmental operating
conditions.

Vee =5.0V
Room Temp.

180
160

c.i.
~

«E

140
120

-; 100

'u«

80
60
40
20

100

Frequency (MHz)

I Altera Corporation

Page 101

I EPM7096

Preliminary Information

EPLD

Absolute Maximum Ratings
Symbol

Data Sheet

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

400

lOUT

DC output current, per pin

2000

-25

Power dissipation

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

Max

Unit

4.75

5.25

V
V

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

For military use

-55

85
125

°C

Case temperature

tR
tF

Input rise time

Input fall time

DC Operating Conditions

°C

Notes (2), (3)
Max

Unit

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

10H =-4 mA DC

VOL

Low-level output voltage

10L = 8 mA DC

0.45

IJA

Symbol

Parameter

Conditions

Input leakage current

V I = Vee or GND

Tri-state output off-state current

Vo = Vee orGND

lee1

Vee supply current
(low-power mode, standby)

V I = GND, No load

lee2

Vee supply current
(low-power mode, active)

V I = GND, No load,
f = 1.0 MHz, Note (4)

-10
-40

IJA

Note (4)

Note (5)
Parameter

Symbol

Typ

2.4

102

Capacitance

Min

Conditions

Min

Max

Unit

CIN

Input capacitance

V IN = 0 V, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

I Page 102

Altera Corporation

I Data Sheet

EPM7096 EPLD

Preliminary Information

AC Operating Conditions

Note (3)

External Timing Parameters
Symbol
Parameter

EPM7096-7 EPM7096-10 EPM7096-12

Conditions Min Max Min

Max

Min

Max

EPM7096-15

Min

Max Unit

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

C1 = 35 pF

7.5

4.5

ns
ns
8

Array clock setup time

tAH
t AC01

Array clock hold time

tACH
t ACL

Array clock high time

Array clock low time

tCNT

Minimum global clock period

fCNT
t ACNT

Max. int. global clock frequency
Minimum array clock period

f ACNT
f MAX

Array clock to output delay

C1 = 35 pF

7.5
4

12
5

15
6

ns
ns

5
10

ns
13

76.9

Note (4)

125.0

Max. int. array clock frequency

Note (4)

125.0

100

90.9

76.9

MHz

Maximum clock frequency

Note (6)

166.7

125

100

MHz

Parameter

100

90.9
10

Internal Timing Parameters
Symbol

EPM7096-7 EPM7096-10 EPM7096-12

Conditions Min Max Min

Max

Min

Max

MHz
13

EPM7096-15

Min

Max Unit

tIN

Input pad and buffer delay

0.5

tlO

1/0 input pad and buffer delay

0.5

t SEXP

Shared expander delay

t pEXP

Parallel expander delay

0.8

t LAO

Logic array delay

t LAC
too

Logic control array delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

Output buffer and pad delay

C1 = 35 pF

C1 = 5 pF

tsu

tH
t RO

tCOMB

Combinatorial delay

tiC

Array clock delay

tEN

tGLOB
t pRE

Global control delay

tCLR

tplA
t LPA

Prog. Interconnect Array delay

Low power adder

I Altera Corporation

Note (7)

ns
ns
ns

Page 103

I EPM7096

Preliminary Information

EPLD

Data Sheet

Notes to tables:
(1)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vcc =5.0 V.
Operating conditions: Vcc =5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
Vcc =5.0 V ± 10%, TA =-40° C to 85° C for industrial use.
Vcc =5.0 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. The OEln pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
The fMAX values represent the highest frequency for pipelined data.
The t LPA parameter must be added to the t LAD, t LAC! tIC' t ACV tEN' and t SEXP parameters
for macrocells running in low-power mode.

(2)
(3)

(4)
(5)
(6)
(7)

Product
Availability

Product
Replacement
Guide

Pin-Out
Information

Commercial Temp.

(0° C to 70° C)

EPM7096-10, EPM7096-12, EPM7096-15

Industrial Temp.

(-40° C to 85° C)

EPM7096-15

Military Temp.

(-55° C to 125° C) Consult factory

The following table shows which EEPROM EPM7096 devices should be
used as replacements for the earlier EPROM EPM7096 devices.

EEPROM Device

EPROM Device
EPM7096

EPM7096-15

EPM7096-2

EPM7096-15

EPM7096-3

EPM7096-15

Tables 5 and 6 provide pin-out information for the EPM7096 packages.

Table 5. EPM7096 Dedicated Pin-Outs

68-Pin J-Lead

84-Pin J-Lead

OEln

OE2n

Dedicated Pin
GCLK
GCLRn

100-Pin QFP

GND

6, 16, 26, 34, 38,
48,58,66

7,19,32,42,47,
59,72,82

13, 28, 40, 45, 61,
76,88,;97

VCC

3, 11, 21, 31, 35,
43,53,63

3, 13, 26, 38, 43,
53,66,78

5,20,36,41,53,
68,84,93

6,39,46,79

9, 24, 37, 44, 57,
72,85,96

No Connect (N.C.)

I Page 104

Availability

Product Grade

Altera Corporation

I Data Sheet

Preliminary Information

EPM7096 EPLD

Table 6. EPM7096 I/O Pin-Outs (Part 1 of 2)

I Altera Corporation

LAB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

68-Pin 84-Pin 100-Pin
J-Lead J-Lead OFP

15
14

7
6
4
3

9
8

11
10

2
1

9
8

100
99
98
95

4
33

4
41

94
39

30
-

37
36

38
35
34
33

29
28

35
34

32
31

30
29
27
26

25
-

31
30

68-Pin 84-Pin 100-Pin
J-Lead J-Lead OFP

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

22
21
19
18

25
24

19
18

23
22

17
16

B
B

21
20
18

15
14
12
11

14
36

17
44

10
42

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

43
46
47
48

48
49

40
41

50
51

49
50

51
52
54
55

54
55

Page 105

I EPM7096

EPLD

Data Sheet I

Preliminary Information

Table 6. EPM7096 I/O Pin-Outs (Part 2 of 2)

I Page 106

LAB

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

F
F

LAB

65
66
67
68
69
70
71
72
73
74
75
76

78
79
80

59
60
62
63

60
61

50
51

62
63

64
65

52
54

64
65
67

66
67
69
70

E •

68-Pin 84-Pin 100-Pin
J-Lead J-Lead QFP

70
71

74
75
77
78

60
61

74
75

79
80

F
F

76
77

81
82
83
86

Altera Corporation

EPM7128 EPLD
o

Features

High-density CMOS EPLD based on second-generation MAX
architecture
2,500 usable gates
Combinatorial speeds with tpD = 10 ns
Counter frequencies up to 100 MHz
Advanced 0.8-micron CMOS EEPROM technology
Programmable I/O architecture with up to 100 inputs or 96 outputs
128 advanced macro cells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Available in the following packages (see Figure 22):
84-pin plastic J-Iead chip carrier (PLCC)
100- and 160-pin plastic quad flat pack (PQFP)

o
o

Figure 22. EPM7128 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Tables 7 and 8 in this data sheet for pin-out information.
I-

I-

t-=:lt-=>

::lo...=>o...

o...za..z

~&~~...JO

()C\I...J ....

~~~~a~~~~~g~ga~~~~~~~

1/0

74
73
72
71

vee
1/0
1/0
1/0
1/0

110
GND

1/0
1/0
1/0
1/0
1/0
1/0

66
65
64
63
62
61
60
59
58
57
56
55
54

vee
1/0
1/0
1/0

EPM7128

110
110
GND

1/0

Pin 121.

_UIIU11nnnu_.J

Pin 1

110
GND

1/0
1/0
1/0
1/0
1/0

vee
1/0
1/0
1/0

110
110
1/0
GND

110
1/0

EPM7128

110
1/0
1/0

~~~~~~~~~~~~~~~~~~~~~

~~~~~8~~~~8~~~~~~~~~8
>
C!I>
(!)
>

84-Pin J-Lead

General
Description

I Altera Corporation

Pin 31

Pin 81

Pin 51 Pin 41

100-Pin QFP

160-Pin QFP

The Altera EPM7128 is a high-density, high-performance CMOS EPLD
based on Altera's second-generation MAX architecture. See Figure 23.
Fabricated on a 0.8-micron EEPROM technology, the EPM7128 provides
2,500 usable gates, counter speeds of 100 MHz, and propagation delays of
10 ns. The EPM7128 architecture supports 100% TTL emulation and allows
high integration of SSI, MSI, and LSI logic functions. With 128 macro cells,

Page 107

I EPM7128 EPLD

Data Sheet

the EPM7128 implements complete system-level designs. It easily integrates
multiple programmable logic devices such as PALs, GALs, and 22VIOs.
With its high performance and density, the EPM7128 provides FPGA
density with PAL performance. The high density and high 1/ 0 pin count
make the EPM7128 appropriate for prototyping gate arrays. The EPM7128
can also accommodate both logic- and 1/ O-intensive designs.
Figure 23. EPM7128 Block Diagram
INPUT/GCLK
INPUT/GCLRn c::::;>----------..+------.......+-------,
INPUT/OE1n
INPUT/OE2n

8to 12
1/0 pins

8to 12
110 pins

I .;;3:,.6~:~z:;:z:;:z:;:~~~~-+~ I/O
I'"
Control

8to 12
1/0 pins

Macrocells
81 to 88

Block

8 to 12
1/0 pins

8to 12
110 pins

8to 12

I Page 108

8to 12

Altera Corporation

I Data Sheet

EPM7128 EPLD

Figure 24 shows the output drive characteristics of EPM7128 II a pins.
Figure 24. EPM7128 Output Drive Characteristics
150

ci.
~ 120

.s
c

~
~

Vcc=S.OV
Room Temp.

S
a.
S

...9

Vo Output Voltage (V)

Figure 25 shows typical supply current versus frequency for the EPM7128.
Figure 25. EPM7128 Icc vs. Frequency
Icc is calculated with the fol/owing equation:
Icc = (0.91 x MG roN) + (0.48 x MG roFF ) + [(0.0053 x MG)x fMAXi
The parameters for this equation are:
MG roN = number of macrocel/s used with Turbo Bit on
MG roFF = number of macrocel/s used with Turbo Bit off
MG
= total number of macrocel/s used in the design
(MG roN + MG roFF)
fMAX
= highest Glock frequency to the device

200r------------------------------,
180
160

Vcc = 5.0 V
Room Temp.

ci. 140
~

«E 120
"Q;' 100
>

This measurement provides an Icc estimate based on typical
()
conditions (Vcc = 5.0 I/, room temperature) using a typical
...9
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB with no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual pattern
in the device and the environmental operating conditions.

80
60
40
20

90 100

Frequency (MHz)

I Altera Corporation

Page 109

I EPM7128 EPLD

Data Sheet

Absolute Maximum Rating
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

800

lOUT

DC output current, per pin

-25

Power dissipation

4000

T STG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

Max

Unit

4.75

5.25

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

Input fall time

Max

Unit

DC Operating Conditions
Symbol

Notes (2), (3)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

VO H

High-level TTL output voltage

10H=-4 mADC

VOL

Low-level output voltage

10L = 8 mA DC

0.45

!lA
!lA

2.4

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

lee1

Vee supply current
(low-power mode, standby)

V I = GND, No load

Vee supply current
(low-power mode, active)

V I = GND, No load,
f = 1.0 MHz, Note (4)

lee2

Capacitance
Symbol

100

Note (4)

Note (5)
Parameter

Conditions

Min

Max

Unit

CIN

Input capacitance

VIN=OV, f=1.0MHz

COUT

Output capacitance

Vour= 0 V, f= 1.0 MHz

I Page 110

Altera Corporation

I Data Sheet

EPM7128 EPLD

AC Operating Conditions

Note (3)

External Timing Parameters
Symbol

Parameter

EPM7128-10 EPM7128-12

Conditions Min
C1 = 35 pF

Max Min

Max

EPM7128-15

EPM7128-20

Min

Max

Max Unit

tpD2

I/O input to non-reg. output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl

Global clock low time

tASU

Array clock setup time

tAH

Array clock hold time

tAC01

Array clock to output delay

tACH

Array clock high time

tACl

Array clock low time

tCNT

Minimum global clock period

fCNT

Max. int. global clock freq.

tACNT
f ACNT

Minimum array clock period
Max. int. array clock freq.

Note (4)

100

90.9

76.9

62.5

MHz

f MAX

Maximum clock frequency

Note (6)

125

100

83.3

MHz

Parameter

8
0
C1 = 35 pF

4
12

10
5

100

90.9

Conditions Min

Max Min

8
13

76.9

EPM7128-10 EPM7128-12

Max

20
8

6
11

5
15

5
10

ns
12

16
62.5

ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz

EPM7128-15

EPM7128-20

Min

Max

ns
ns

0
8

C1 = 35 pF

Note (4)

0
5

Internal Timing Parameters
Symbol

tpD1

Input to non-reg. output

Max Unit

tIN

Input pad & buffer delay

tlO

I/O input pad & buffer delay

tSEXP

Shared expander delay

tpEXP

Parallel expander delay

0.8

tLAD

Logic array delay

tLAC

Logic control array delay

too

Output buffer & pad delay

tzx

Output buffer enable delay

=35 pF
=5 pF

txz

Output buffer disable delay

tsu

tRD

tCOMB

Combinatorial delay

tIC

Array clock delay

tEN

tGLOB

Global control delay

tpRE

tCLR

tplA

Prog. Interconn. Array delay

tLPA

Low power adder

I Altera Corporation

Note (7)

Page 111

I EPM7128 EPLD

Data Sheet

Notes to tables:
(1)
(2)
(3)

(4)
(5)
(6)
(7)

Product
Availability

New SpeedGrade Ordering
Codes

I Page 112

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee = 5.0 V.
Operating conditions: Vee =5.0 V ± 5%, TA =0° C to 70° C for commercial use.
Vee =5.0 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee =5.0 V ± 10%, Te =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. The OE In pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
The fMAX values represent the highest frequency for pipelined data.
The t LPA parameter must be added to the t LAD, t LAO t 10 t ACV tEN' and t SEXP parameters
for macrocells running in low-power mode.

Product Grade
Commercial Temp.

(0° C to 70° C)

Availability
EPM7128-10, EPM7128-12,
EPM7128-15, EPM7128-20

Industrial Temp.

(-40° C to 85° C)

EPM7128-20

Military Temp.

(-55° C to 125° C)

Consult factory

Speed-grade codes for EPM7128 devices have changed. The following
table provides the new codes, which indicate the actual propagation delay
times.

Old Speed Grade

New Speed Grade

EPM7128-1

EPM7128-10

EPM7128-2

EPM7128-12

EPM7128-3

EPM7128-15

EPM7128-4

EPM7128-20

Altera Corporation

I Data Sheet

Pin-Out
Information

EPM7128 EPLD I

Tables 7 and 8 provide pin-out information for the EPM7128 packages.
Table 7. EPM7128 Dedicated Pin-Outs

Dedicated Pin
GCLK

84-Pin J-Lead

100-Pin QFP

160-Pin QFP

139

141

OEln

140

OE2n

GCLRn

7, 19, 32, 42, 47,
59,72,82

13, 28, 40, 45, 61,
76,88,97

17, 42, 60, 66, 95,
113,138,148

VCC

3, 13, 26, 38, 43,
53,66,78

5, 20, 36, 41, 53,
68,84,93

8, 26, 55, 61, 79,
104,133, 143

No Connect (N.C.)

I Altera Corporation

142

GND

1, 2, 3, 4, 5, 6, 7,
34,35,36,37,38,
39, 40, 44, 45, 46,
47,74,75,76,77,
81,82,83,84,85,
86,87,114,115,
116,117,118,119,
120,124,125,126,
127,154,155,156,
157

Page 113

I EPM7128 EPLD

Data Sheet

Table 8. EPM7128 I/O Pin-Outs (Part 1 of 2)

I Page 114

LAB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C

84-Pin 1DO-Pin 16D-Pin
QFP
J-Lead QFP
-

160

11
10

2
1

159
158
153
152

100
99

151
150

149
147
146
145

6
5

96
95

4
-

94
27

144
41

30
29

25
24

33
32
31
30

23
22

29
28

25
24

19
18

27
25
24
23

84-Pin 1DD-Pin 16D-Pin
J-Lead QFP
QFP

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

20
19
18
16

B
B

18
17

14
12
11
10
9

8
7

13
12
11
10

14
41

6
39

9
59

37
35

58
57
56
54

B
B

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

37
36

15
14
-

34
33

53
52

51
50
49
48

31
30

Altera Corporation

I Data Sheet

EPM7128 EPLD I

Table 8. EPM7128 I/O Pin-Outs (Part 2 of 2)
MC
65
66
67
68
69
70
71

I Altera Corporation

LAB

84-Pin 100-Pin 160-Pin
J-Lead
OFP
OFP

LAB

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

88
89
90
91

44
46

63
64
65
67

73
74
75
76

48
49

47
48

68
69

78
79
80
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

50
51

70
71
72
73

52
63

52
65

78
100

101
102
103
105

67
69

G
G

67
68

70
71

106
107

73
74

108
109
110
111

112

84-Pin 100-Pin 160-Pin
J-Lead OFP
OFP

55
56

56
57

58
59

92
93

94
96
97
98

60
61

62
63

F
F

H
H

99
121

74
75

79
80

122
123
128
129

81
82

130
131

79
80

85
86

132
134
135
136

137

Page 115

Notes:

EPM7160 EPLD
o

Features

o
o

High-density, erasable CMOS EPLD based on second-generation MAX
architecture
3,200 usable gates
Combinatorial speeds with tpD = 12 ns
Counter frequencies up to 90.9 MHz
Advanced O.8-micron CMOS EEPROM technology
Programmable I/O architecture with up to 104 inputs or 100 outputs
160 advanced macro cells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Available in plastic packages (see Figure 26):
84-pin plastic J-Iead chip carrier (PLCC)
100- and 160-pin plastic quad flat pack (PQFP)

Figure 26. EPM7160 Package Pin-Out Diagrams

Package outlines not drawn to scale. See Tables 9 and 10 in
this data sheet for pin-out information.

Pin 121

Pin 1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

110

vee
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0

vee
1/0

110
1/0
1/0
1/0
GND

1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0

General
Description

Altera Corporation

vee
110
110
1/0
1/0

110
1/0
GND
1/0
1/0
1/0

EPM7160E

110
1/0

Pin 81

Pin 51

Pin 31

84-Pin J-Lead

100-Pin QFP

160-Pin QFP

The AHera EPM7160 is a high-density, high-performance CMOS device
based on Altera's second-generation MAX architecture. See Figure 27.
Fabricated on a O.8-micron EEPROM technology, the EPM7160 provides
3,200 usable gates, counter speeds of 90.9 MHz, and propagation delays of
12 ns. The EPM7160 architecture supports 100% TTL emulation and allows
high integration of SSI, MSI, and LSI logic functions. With 160 macrocells,
the EPM7160 implements complete system-level designs. It easily integrates
multiple programmable logic devices such as PALs, GALs, and 22V10s.
With its high performance and density, the EPM7160 provides FPGA
Page 1171

EPM7160 EPLD

Data Sheet I

density with PAL performance. The high density and high I/O pin count
also make the EPM7160 appropriate for prototyping gate arrays. The
EPM7160 can accommodate both logic- and I/O-intensive designs.

Figure 27. EPM7160 Block Diagram
INPUT/GCLK
INPUT/GCLRn
INPUT/OE1n
INPUT/OE2n

c>----------.------..-----.....,
c>---------H------.+-----,

6to 10

1/0 pins

110 pins

6to 10

110 pins

6to 10

61010

1/0 pins

6to 10

61010

1/0 pins

61010

110 pins

61010

Page 118

6to 10

Altera Corporation

I Data Sheet

EPM7160 EPLD

Figure 28 shows the output drive characteristics of EPM7160 I/O pins.

Figure 28. EPM7160 Output Drive Characteristics
150

ci.
~

120

1:5
---------.-t-------.+------,

10110 pins

10 1/0 pins

10110 pins

10 1/0 pins

10110 pins

Page 128

Altera Corporation

I Data Sheet

EPM7192 EPLD

Figure 32 shows the output drive characteristics of EPM7192I/O pins.

Figure 32. EPM7192 Output Drive Characteristics
150

ci.
~ 120
~

-S
1:
~

V cc =5.0V
Room Temp.

:;
0
+-'

::J

..9

Output Voltage (V)

Figure 33 shows typical supply current versus frequency for the EPM7192.

Figure 33. EPM7192 Icc vs. Frequency
1000~-----------------------------.

Icc is calculated with the fol/owing equation:
Icc = (1.5 x MC TON) + (0.48 x MC TOFF ) + [(0.0088 x MC) x
fMAX]
The parameters for this equation are:
MCTON = number of macrocel/s used with Turbo Bit on
MC TOFF = number of macrocel/s used with Turbo Bit off
MC
= total number of macrocel/s used in the design
(MC TON + MC TOFF)
fMAX
= highest Clock frequency to the device

900

Vcc = 5.0 V
Room Temp.

800

ci. 700
~
~ 600

-S
Q)

13
«

500
400

~ 300

This measurement provides an Icc estimate based on typical
conditions (Vcc = 5.0 V, room temperature) using a typical
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB with no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual
pattern in the device and the environmental operating
conditions.

Altera Corporation

200
100

100

Frequency (MHz)

Page 129

EPM7192 EPLD

Data Sheet I

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

800

lOUT

DC output current, per pin

Power dissipation

-25

TSTG

Storage temperature

No bias

-65

TAMS

Ambient temperature

Under bias

-65

Junction temperature

Under bias

4000

150

°C

135

°C

150

°C

Min

Max

Unit

4.75

5.25

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

Input fall time

Max

Unit
V

DC Operating Conditions
Symbol

Notes (2), (3)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee +0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

2.4

IOH =-4 mA DC

VOL

Low-level output voltage

IOL = 8 mA DC

Input leakage current

V I = Vee or GND

-10
-40

loz

Tri-state output off-state current

Vo = Vee orGND

leC1

Vee supply current
(low-power mode, standby)

V 1= GND, No load

lee2

Vee supply current
(low-power mode, active)

V I = GND, No load,
f = 1.0 MHz, Note (4)

Capacitance
Symbol

V
V

0.45

130

135

Note (4)

Note (5)
Parameter

Conditions

Min

Max

Unit

CIN

Input capacitance

V IN = 0 V, f = 1.0 MHz

COUT

Output capacitance

VOUT= 0 V, f= 1.0 MHz

I Page 130

Altera Corporation

I Data Sheet

EPM7192 EPLD

AC Operating Conditions

Note (3)

External Timing Parameters
Symbol

Parameter

EPM7192-12

Conditions

Min

Max

EPM7192-15

EPM7192-20

Min

Max

Unit

t pD1

Input to non-registered output

t pD2

liD input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

Array clock setup time

C1 = 35 pF

tAH
t AC01

Array clock hold time

tACH
t ACl

Array clock high time

Array clock low time

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency

f ACNT
f MAX

Array clock to output delay

ns
20

8
13

ns
MHz

Note (4)

90.9

Max. internal array clock frequency

Note (4)

90.9

76.9

62.5

MHz

Maximum clock frequency

Note (6)

125

100

83.3

MHz

EPM7192-12

EPM7192-15

EPM7192-20

Min

Minimum array clock period

Internal Timing Parameters
Symbol

Parameter

76.9

ns
ns

5
15

ns
12

C1 = 35 pF

Conditions

Max

62.5
13

Max

Unit

tIN

Input pad and buffer delay

tlO

liD input pad and buffer delay

ns
ns

t SEXP

Shared expander delay

t pEXP

Parallel expander delay

t LAO

Logic array delay

t LAC

Logic control array delay

too

Output buffer and pad delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

C1 = 35 pF

C1 = 5 pF

tsu

tRD

ns
ns
1

tCOMB

Combinatorial delay

tIC

Array clock delay

tEN

tGLOB

Global control delay

tpRE

ns
ns

tCLR

t plA

Prog. Interconnect Array delay

t LPA

Low power adder

Altera Corporation

Note (7)

Page 131

EPM7192 EPLD

Data Sheet I

Notes to tables:
(1)
(2)
(3)

(4)
(5)
(6)
(7)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee = 5.0 V.
Operating conditions: Vee = 5.0 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5.0 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee =5.0 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. The OEln pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
The fMAX values represent the highest frequency for pipelined data.
The tLPA parameter must be added to the tLAD, t LAC' t let t ACLt tEN' and tSEXP parameters
for macrocells running in low-power mode.

Product Grade
Commercial Temp.

(0° C to 70° C)

Availability
EPM7192-12, EPM7192-15, EPM7192-20

Industrial Temp.

(-40° C to 85° C)

EPM7192-20

Military Temp.

(-55° C to 125° C)

Consult factory

MI L-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:
(1)

New SpeedGrade Ordering
Codes

Page 132

MIL-STD-883-compliant product specifications are provided in this data book and
in Military Product Drawings (MPDs). However, only MPDs should be used to
prepare Source Control Drawings (SCDs). MPDs are available from Altera Marketing
at (408) 894-7000.

Speed-grade codes for EPM7192 devices have changed. The following
table provides the new codes, which indicate the actual propagation delay
times.

Old Speed Grade

New Speed Grade

EPM7192-1

EPM7192-12

EPM7192-2

EPM7192-15

EPM7192-3

EPM7192-20

Altera Corporation

I Data Sheet

Pin-Out
Information

EPM7192 EPLD I

Tables 11 and 12 provide pin-out information for the EPM7192 packages.
Table 11. EPM7192 Dedicated Pin-Outs
160-Pin PGA

160-Pin QFP

GCLK

139

GCLRn

141

OEln

140

142

Dedicated Pin

OE2n

1 Altera Corporation

GND

C4, C6, C11 , 07, 09, 013, 3,18,32,47,57,64,66,
G4, H12, J4, M7, M9,
81,96,111,126,138,
M13, N4, N11
143,148

VCC

C5, C7, C9, C10, C12, 03, 10,25,40,55,56,65,74,
G12, H4, J12, M3, N5, N7, 89,103,118,133,137,
144,155
N9,N12

No Connect (N.C.)

A1, A2, A14, A15, R1, R2, 1,11,39,54,67,82,110,
R14, R15
120

Page 1331

EPM7192 EPLD

Data Sheet

Table 12. EPM7192 I/O Pin-Outs (Part 1 of 2)

Me
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

I Page 134

LAB

160-Pin 160-Pin
PGA
OFP

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

M12

156

P11

154

R9
D15

145
33

E15

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

P12
P10

153
152

R12
N10

151
150

R11

149

R10
P9

147
146

E14
F15

30
29

F13
G14

28
27

F14

G13
G15

24
23

H13

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

L14

8
8
8
8
8
8
8
8

160-Pin 160-Pin
PGA
OFP

M14
-

M15
N14

N15
P15

7
-

6
5
-

4
2

8
8
8
8
8
8
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E

N13

160

P14
P13

R13
812
-

813
-

C13
814

159
158
-

157
45
-

43
42

C14
D12

41
38

815

D14
C15
-

E13

36
35
-

LAB

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

H14

A13

160-Pin 160-Pin
PGA
OFP

J13

H15
J15

19
17

J14
K15

16
15

K13

L15
K14

L13
D8

13
12
-

9
60

C8
89

58
53

A10
810

52
51

A11

811
A12

49
48

Altera Corporation

Data Sheet

EPM7192 EPLD

Table 12. EPM7192 I/O Pin-Outs (Part 2 of 2)

LAB

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J

I Altera Corporation

160-Pin 160-Pin
PGA
OFP

A7
A6

63
68

B7
A5

69
70

A4
B5

72
73

04
H2

75
100

101

H3
J3

102
104

K1
J2

105
106

107

K3
L1

108
109

112

LAB

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

160-Pin 160-Pin
PGA
OFP

B3
C3

78
79

B2
B1

80
83

C1
02

85
86

113

114

L3
P1

115
116

M2
N2

117
119

121

N3
P3

122
123

124

Me
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

LAB
I

160-Pin 160-Pin
PGA
OFP

E2
F2

91
92

I
I

E1
G3

93
94

G1
G2

97
98

I
I

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

125

127

M4
R5

128
129

P5
R6

130
131

132

N6
R7

134
135

136

Page 1351

Notes:

EPM7256 EPLD
o

Features

o
o
o
o

High-density, erasable CMOS EPLD based on second-generation MAX
architecture
5,000 usable gates
Combinatorial speeds with tpD = 20 ns (Higher speed versions
under development)
Counter frequencies up to 62.5 MHz
Advanced 0.8-micron CMOS EPROM technology
Programmable I/O architecture with up to 164 inputs or 160 outputs
256 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Available in the following packages (see Figure 34):
192-pin pin-grid array (PGA)
208-pin power quad flat pack (RQFP)
208-pin metal quad flat pack (MQFP)

Figure 34. EPM7256 Package Pin-Out
Diagrams
Package outlines not drawn to scale. See Tables 13
and 14 in this data sheet for pin-out information.

EPM7256

1 2

9 10 11 12 13 14 15 16 17

192-Pin PGA

General
Description
1

Altera Corporation

Pin 105

Pin 53

208-Pin QFP

The Altera EPM7256 is a high-density, high-performance CMOS EPLD
based on Altera's second-generation MAX architecture. See Figure 35.
Fabricated on a 0.8-micron EPROM technology, the EPM7256 provides
5,000 usable gates, counter speeds of 62.5 MHz and propagation delays of
Page 1371

EPM7256 EPLD

Data Sheet I

20 ns. The EPM7256 architecture supports 100% TTL emulation and allows
high integration of SSI, MSI, and LSI logic functions. With 256 macrocells,
the EPM7256 implements complete system-level designs. It easily integrates
multiple programmable logic devices ranging from PALs, GALs, and
22V10s to MACH devices and FPGAs. The high density and high I/O pin
count make the EPM7256 appropriate for prototyping gate arrays. The
EPM7256 can accommodate both logic- and 1/ O-intensive designs.

Figure 35. EPM7256 Block Diagram

i~~~" ~: : ~ ~ : : : : : : : : : : : : : : : ti!~: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ~;TI~ ~ : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ~U~ : : : : : : : : : : : : =- J- -'
..

to LAB A through LAB H

10m

to LAB I through LAB P

10 1/0 pins

10 I/O pins

Macrocelis
17 to 24
10 I/O pins

I.....~-----"""+~

Macrocelis
25 to 32

36
10110 pins

36
10 I/O pins

10 1/0 pins

36
Macrocelis
10 ;~. 201 to 208

10 I/O pins

PIA

IO++------+l~ I

10110 pins

36
10 1/0 pins

10 I/O pins

36
10 I/O pins

I.....~-----"""+*I

Macrocelis
89 to 96

10110 pins

~~~~10
10

36
10 1/0 pins

10110 pins

Page 138

Altera Corporation

I Data Sheet

EPM7256 EPLD

Figure 36 shows the output drive characteristics of EPM7256I/O pins.

Figure 36. EPM7256 Output Drive Characteristics
75

ci.
~

.s
c

Vee =5.0V
Room Temp.

=:;
()

S
0.
S

..9

Va Output Voltage (V)

Figure 37 shows typical supply current versus frequency for the EPM7256.

Figure 37. EPM7256 Icc vs. Frequency
Icc is calculated with the following equation:
Icc = (1.7x MC roN) + (0.59 x MC roFF ) + [(0.015 x MC) x fMAXi

1000,--------------------,
900

The parameters for this equation are:
MC roN = number of macrocells used with Turbo Bit on
MC roFF = number of macrocells used with Turbo Bit off
MC
total number of macrocells used in the design
(MC roN + MC roFF)
fMAX
highest Clock frequency to the device
This measurement provides an Icc estimate based on typical
conditions (Vcc = 5.0 I/, room temperature) using a typical
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB with no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual
pattern in the device and the environmental operating
conditions.

800

ci.
~

Vee = 5.0 V
Room Temp.

700

« 600

.s
Q)

500
400

~ 300
200
100

100

Frequency (MHz)

Altera Corporation

Page 1391

I EPM7256 EPLD

Data Sheet

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

800

lOUT

DC output current, per pin

Power dissipation

-25

4000

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Min

Max

Unit
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

Input fall time

Max

Unit

DC Operating Conditions
Symbol

Notes (2), (3)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

10H =-4 mA DC

VOL

Low-level output voltage

10L = 8 mA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

Vo = Vee or GND

-40

lee1

Vee supply current
(low-power mode, standby)

VI = GND, No load

Vee supply current
(low-power mode, active)

V I = GND, No load,
f = 1.0 MHz, Note (4)

lee2

Capacitance
Symbol

2.4

/lA
/lA

40
150

155

Note (4)

Note (5)
Parameter

Conditions

CIN

Input capacitance

V IN = 0 V, f = 1.0 MHz

COUT

Output capacitance

VOUT= 0 V,

I Page 140

V
0.45

f= 1.0 MHz

Min

Max

Unit

Altera Corporation

I Data Sheet

EPM7256 EPLD

AC Operating Conditions

Note (3)

External Timing Parameters
Symbol

Conditions

Parameter

EPM7256-20

EPM7256-25

Min

Max

Unit

Max

tpD1

Input to non-registered output

tpD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

Array clock setup time

tAH
t AC01

C1 = 35 pF

ns
15

ns
ns

6
25

C1 = 35 pF

ns
ns

0
12

C1 = 35 pF

Array clock hold time
Array clock to output delay

tACH
t ACl

Array clock high time

12.5

Array clock low time

12.5

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency
Minimum array clock period

f ACNT
f MAX

Note (4)

62.5

Max. internal array clock frequency

Note (4)

62.5

MHz

Maximum clock frequency

Note (6)

83.3

62.5

MHz

EPM7256-20

EPM7256-25

Min

Internal Timing Parameters
Symbol

Conditions

Parameter

MHz

Max

Unit

tIN

Input pad and buffer delay

tlO
t SEXP

1/0 input pad and buffer delay

Shared expander delay

t pEXP

Parallel expander delay

t LAO

Logic array delay

t LAC
too

Logic control array delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu

tH
t RO

Output buffer and pad delay

=35 pF
=5 pF

Combinatorial delay

Array clock delay

tEN

tGLOB
tpRE

Global control delay

tCOMB
t,C

tCLR

tplA
t LPA

Prog. Interconnect Array delay

Low power adder

Altera Corporation

Note (7)

Page 141

I EPM7256 EPLD

Data Sheet

Notes to tables:
(1)
(2)
(3)

(4)
(5)
(6)
(7)

Product
Availability
New SpeedGrade Ordering
Codes

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee =5.0 V.
Operating conditions: Vee =5.0 V ± 5%, TA =0° C to 70° C for commercial use.
Vee =5.0 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee =5.0 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit loadable, enabled, up/down counter programmed into
each LAB. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. The OEln pin (high-voltage pin
during programming) has a maximum capacitance of 20 pF.
The f MAX values represent the highest frequency for pipelined data.
The t LPA parameter must be added to the t LAD, t LAc, tIC' t ACV tEN' and t SEXP parameters
for macrocells running in low-power mode.

Product Grade
Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C)

EPM7256-25

Military Temp.

(-55° C to 125° C)

Consult factory

Speed-grade codes for EPM7256 devices have changed. The following
table provides the new codes, which indicate the actual propagation delay
times.

Old Speed Grade

I Page

142

Availability
EPM7256-20, EPM7256-25

New Speed Grade

EPM7256-2

EPM7256-20

EPM7256

EPM7256-25

Altera Corporation

I Data Sheet
Pin-Out
Information

EPM7256 EPLD I

Tables 13 and 14 provide pin-out information for the EPM7256 packages.
Table 13. EPM7256 Dedicated Pin-Outs
Dedicated Pin
GCLK

Note (1)

192-Pin PGA

208-Pin MQFP, RQFP

184

GCLRn

182

OEln

183

OE2n

181

GND

C7, C13, 04, 08, 010,
G14, H4, K14, L4, P8,
P10, P15, R4, R11

VCC

5,23,41,63,74,83,85,
C5, C11, 07, 011, 014,
G4, H14, K4, L14, P3, P7, 107,125,143,165,179,
P11, R5, R14
186,191

No Connect (N.C.)

14,32,50,72,75,82,94,
116,134,152,174,180,
185,200

1,2,51,52,53,54,103,
104,105,106,155,156,
157,158,207,208

Note to tables:
(1)

1 Altera Corporation

CQFP pin-out information differs from the MQFP and RQFP pin-out information
given in this table. Contact Altera Applications for CQFP pin-out information.

Page 1431

I EPM7256 EPLD

Data Sheet I

Table 14. EPM7256 I/O Pin-Outs (Part 1 of 3)
Me

LAB

1
2

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

4
5
6
7
8

9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

I Page 144

192-Pin 208-Pin
PGA
MQFP&
RQFP

U17

153

R16

154

P14
U16

159
160

R15
U15

161
162

T15

163

U14
U13

164
166

T14
A14

167
92

0
0
0

B12

B13
A15

95
96

D
D

B14
A16

97
98

C14

0
0
0

B16
B15

100
101

A17

102

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
E

192-Pin 208-Pin
MQFP&
PGA
RQFP

N17

141

M16

142

M15
P17

144
145

N16
R17

146
147

P16

148

T17
N15
-

149
150
-

T16
U12

151
168

R13

169

U11
T13

170
171

E
E

T11
T12

172
173

E
E

R12

175

U10
R10

176
177

E
E

T10

178

LAB

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

192-Pin 208-Pin
MQFP&
PGA
RQFP

B17

108

C15

109

C17
C16

110
111

017
015

112
113

E17

114

016
E15

115
117

F16
J16

118
130

J15

131

K17
J14

132
133

K16
K15

135
136

L17

137

L16
M17

138
139

L15

140

Altera Corporation I

I Data Sheet

EPM7256 EPLD I

Table 14. EPM7256 I/O Pin-Outs (Part 2 of 3)

LAB

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
J
J
J
J
J
J
J
J
J
J
J
J
J
J

192-Pin 208-Pin
PGA
MQFP &
RQFP

E16

119

F17

120

F15
G16

121
122

G15
G17

123
124

H17

126

H15
J17

127
128

H16
J2

129
27

K1
J4

25
24

K2
K3

22
21

L2
M1

19
18

Altera Corporation

LAB

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

192-Pin 208-Pin
MQFP&
PGA
RQFP

C10
A10

81
84

A11
810

86
87

A12

811
A13

89
90

C12
F3

91
38

E2
G2

36
35

G3
G1

34
33

H3
J1

30
29

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

LAB

192-Pin 208-Pin
PGA
MQFP&
RQFP

196

U7
T6

195
194

I
I

T7
R6

197

193
192

190

U8
R8

189
188

I
I

T8
89

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

187
78

A9
A8

76
73

A7
88

71
70

87
A5

68
67

Page 1451

I EPM7256 EPLD

Data Sheet I

Table 14. EPM7256 I/O Pin-Outs (Part 3 of 3)

I Page 146

LAB

192-Pin
PGA

193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

208-Pin
MQFP&
RQFP

R3
U2

206
205

P4
U3

204
203

202
201
199

U4
U5
-

T4
81

198
49

C1
03

47
46

01
C2

45
44

E3
02

42
40

LAB

192-Pin
PGA

208-Pin
MQFP&
RQFP

209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

M3
P1

13
12

N2
R1

11
10

T1
N3

8
7

T2
A4

6
65

85
A3

62
61

84
A2

60
59

82
83

57
56

Altera Corporation

Contents
I August 1993

Section 4

MAX 5000/EPS464
MAX SOOO /EPS464 Programmable Logic Device Family ........................ 149
EPMS016 EPLD .................................................................................. 161
EPMS032 EPLD .................................................................................. 167
EPMS064 EPLD .................................................................................. 17S
EPM5128 EPLD .................................................................................. 181
EPMS128A EPLD ............................................................................... 189
EPMS130 EPLD .................................................................................. 193
EPMS192 EPLD .................................................................................. 203
EPMS192A EPLD ............................................................................... 211
EPS464 EPLD ...................................................................................... 219

I Altera Corporation

Page 147

MAX 5000/EPS464
Programmable Logic
Device Family
I August 1993, ver. 1

Data Sheet

Features

o
o
o

Advanced Multiple Array MatriX (MAX) 5000/EPS464 architecture
combining speed and ease-of-use of PAL devices with density of
programmable gate arrays
Complete family of high-performance, erasable 0.8-micron CMOS
EPROM EPLDs for designs ranging from fast 20-pin address decoders
to 100-pin LSI custom peripherals (see Table 1)
Second-generation MAX 5000A devices on 0.65-micron CMOS EPROM
process providing higher performance
Fast, l2-ns combinatorial delays and 1l1.1-MHz counter frequencies
Configurable expander product-term distribution allowing more than
32 product terms in a single macrocell
20 to 100 pins available in DIP, J-Iead, PGA, SOIC, and QFP packages
Programmable registers providing D, T, JK, and SR flipflop
functionality with individual Clear, Preset, and Clock controls
Programmable Security Bit for total protection of proprietary designs
Software design support featuring Altera's MAX+PLUS II
development system on 386- or 486-based PCs, Sun SPARC stations,
and HP 9000 Series 700 workstations
Programming support with Altera's Master Programming Unit (MPU)
or programming hardware from other manufacturers
EDIF, Verilog, VHDL and other interfaces providing additional design
entry and simulation support with popular CAE tools from vendors
such as Cadence, Data I/O, Exemplar, Intergraph, Mentor Graphics,
OrCAD, Synopsys, and Viewlogic

Table 1. MAX 5000/EPS464 Device Features
Feature
Avail. Gates
Usable Gates
Macrocelis
LABs
Expanders

EPM5016 EPM5032 EPS464 EPM5064 EPM5128 EPM5128A EPM5130 EPM5192 EPM5192A
1,200

2,500

5,000

7,500

300

600

1,250

2,500

3,750

128

192

256

128

256

384

'600

global

PIA

Max. User 1/0

68,84

t pD (ns)

t ASU (ns)

tco (ns)

100

76.9

66.7

111.1

83.3

Routing

fCNT (MHz)

I Altera Corporation

Page 149

I MAX 5000/EPS464 Programmable Logic Device Family

General
Description

Data Sheet I

The MAX 5000 /EPS464 family combines innovative architecture and
advanced process technologies to offer optimum performance, flexibility,
and the highest logic-to-pin ratio of any general-purpose programmable
logic device family. Fabricated on an advanced CMOS EPROM technology,
the MAX 5000 /EPS464 family includes three types of devices-MAX 5000,
MAX 5000A, and EPS464--each described in this data sheet.
The MAX 5000/EPS464 architecture supports 100% TTL emulation and
high-density integration of multiple SSI, MSI, and LSI logic functions. For
example, an EPM5192 can replace over 100 7400-series devices; it can
integrate complete subsystems into a single package, saving board area
and reducing power consumption. MAX 5000 /EPS464 EPLDs are available
in a wide range of packages: windowed ceramic and plastic dual in-line
(CerDIP and PDIP), windowed ceramic and plastic J-Iead chip, carrier
GLCC and PLCC), windowed ceramic pin-grid array (PGA), plastic smalloutline integrated circuit (SOIC), and windowed ceramic and plastic quad
flat pack (CQFP and PQFP) packages. See Table 2.
MAX 5000/EPS464 EPLD densities range from 16 to 192 macrocells that
are combined into groups called Logic Array Blocks (LABs). Each macro cell
has a programmable-AND / fixed-OR array and a configurable register that
provides D, T, JK, or SR operation with independent programmable Clock,
Clear, and Preset functions. To build complex logic functions, each macrocell

Table 2. MAX 5000/EPS464 Device Pin Count & Package Options
Pin EPM5016
Count
CerDIP

EPM5032

Note (1)

EPS464 EPM5064 EPM5128 EPM5128A EPM5130

EPM5192 EPM5192A

JLCC

PLCC
PQFP

PLCC
-

PDIP
SOIC

CerDIP
PDIP
JLCC/PLCC

JLCC/PLCC JLCC/PLCC JLCC/PLCC

100

PGA
CQFP

JLCC/PLCC JLCC/PLCC
PGA
PGA

PGA

PGA
PQFP

PQFP

Note:
(1)

Contact Altera for information on available device packages.

I Page 150

Altera Corporation

I Data Sheet

MAX 5000/EPS464 Programmable Logic Device Family I

can be supplemented with shareable expander product terms (" expanders")
to provide more than 32 product terms per macrocell.
The MAX 5000/EPS464 family is supported by Altera's MAX+PLUS II
development system, a single integrated package that offers schematic,
text, and waveform design entry; compilation and logic synthesis;
simulation; and programming software. MAX+PLUS II provides EDIF,
VHDL, Verilog, and other netlist interfaces for additional design entry and
simulation support from other industry-standard PC- and workstationbased CAE tools. MAX+PLUS II runs on 386- and 486-based PCs, Sun
SPARCstations, and HP 9000 Series 700 workstations.

MAX 5000 EPLDs
Developed on a O.8-micron CMOS EPROM process, these first-generation
MAX EPLDs offer pin-to-pin logic delays as fast as 15 ns and counter
frequencies as high as 100 MHz. MAX 5000 devices range from the
16-macrocell EPM5016 to the 192-macrocell EPM5192.

MAX 5000A EPLDs
MAX 5000A EPLDs are developed on an advanced 0.65-micron CMOS
EPROM technology. Produced on a state-of-the-art process, MAX 5000A
devices offer pin-to-pin delays as fast as 12 ns and counter frequencies as
high as 111 MHz. MAX 5000A EPLDs are fully pin-, function-, and
programming-file-compatible with their MAX 5000 counterparts.

EPS464 EPLDs
The EPS464 is an advanced general-purpose EPLD based on the MAX 5000
architecture. It has 64 enhanced macro cells and 256 shared expanders, all
of which are routed globally to implement complex projects. Full global
routing makes the EPS464 a high-performance device, capable of 66-MHz
counter frequencies. The programmable I/O pins and dedicated inputs
can implement up to 36 inputs or 32 outputs. The EPS464 is available in
44-pin JLCC, PLCC, and PQFP packages. For a functional description and
other information, see "EPS464 EPLD" later in this section.

I Altera Corporation

Page 151

MAX 5000/EPS464 Programmable Logic Device Family

Functional
Description

Data Sheet I

This section provides a functional description of MAX 5000 and MAX SOOOA
EPLDs, which have the same architecture. MAX 5000 devices have the
following architectural features:

o
o
o

Logic Array Blocks
Macrocells
Clocking options
Expander product terms
Programmable Interconnect Array
1/ 0 control blocks

MAX 5000 architecture is based on the concept of linking high-performance,
flexible logic array modules called Logic Array Blocks (LABs). Multiple
LABs are linked together via the Programmable Interconnect Array (PIA),
a global bus that is fed by all 1/ 0 pins and macrocells. In addition to these
basic elements, the MAX 5000 architecture includes 8 to 20 dedicated
inputs, each of which can be used as a high-speed, general-purpose input,
or one of which can be used as a high-speed global Clock for registers.

Logic Array Blocks
MAX 5000 EPLDs contain 1 to 12 LABs. The EPM50l6 and EPM5032 have
a single LAB, while the EPM5064, EPM5128, EPM5128A, EPM5130,
EPM5192, and EPM5192A contain multiple LABs. Each LAB consists of a
macrocell array and an expander product-term array. See Figure 1. The
number of macrocells and expanders in the arrays varies with each device.

Figure 1.
MAX 5000
Architecture

8to 20
dedicated
inputs

•:

PIA in
multi-LAB -------devices only

••
•

PIA

I/O

';L,..."..-,~-,..--~~r----'I Control
Block

• 4 to 16
• I/O pins
• per LAB

Feedback from
liD pins to LAB
(single-LAB
devices only)
to all other LABs

I Page 152

Altera Corporation

I Data Sheet

MAX 5000/EPS464 Programmable Logic Device Family

Macrocells are the primary resource for logic implementation. Additional
logic capability is available from expanders, which can be used to
supplement the capabilities of any macrocell. The expander product-term
array consists of a group of unallocated, inverted product terms that can be
used and shared by all macrocells in the LAB to create combinatorial and
registered logic. These flexible macrocells and shareable expanders facilitate
variable product-term designs without the inflexibility of fixed productterm architectures. All macrocell outputs are globally routed within an
LAB via the LAB interconnect, and also feed the PIA to provide efficient
routing for high-fan-in designs. The outputs of the macrocells also feed the
I/O control block, which consists of groups of programmable tri-state
buffers and I/O pins. In the EPM5064, EPM5128, EPM5128A, EPM5130,
EPM5192, and EPM5192A, multiple LABs are connected by a Programmable
Interconnect Array (PIA).

Macrocells
The MAX 5000 macrocell consists of a programmable logic array and an
independently configurable register (see Figure 2). The register can be
programmed to emulate D, T, JK, or SR operation, as a flow-through latch,
or bypassed for purely combinatorial operation. Combinatorial logic is
implemented in the programmable logic array, in which three product
terms that are ORed together feed one input to an XOR gate. The second
input to the XOR gate is controlled by a single product term that can
implement active-high or active-low logic. The XOR gate is also used for
complex XOR arithmetic logic functions and for De Morgan's inversion.

Figure 2. MAX 5000 Macrocell
Output Enable ...

...

~~ Global Clock
(one per LAB)

Preset

Programmable
Register

§ph ~~~7~i~
/

Array Clock

to 1/0
Control
Block

Clear

~f--

Macrocell Feedback

1/0 Feedback

•••

8 or 20
Dedicated
Inputs

24 Programmable
Interconnect Si gnals
(multi-LAB devices only)

I Altera Corporation

L~ • • • L~

32 or 64
Expander
Product Terms

"
Page 153

I MAX 5000/EPS464 Programmable Logic Device Family

Data Sheet

The output of the XOR gate feeds the programmable register or bypasses it
for combinatorial operation.
Additional product terms-called secondary product terms-are used to
control the Output Enable, Preset, Clear, and Clock signals. Preset and
Clear product terms drive the active-low asynchronous Preset and
asynchronous Clear inputs to the configurable flipflop. The Clock product
term allows each register to have an independent Clock and supports
positive- and negative-edge-triggered operation. Macrocells that drive an
output pin can use the Output Enable product term to control the activehigh tri-state buffer in the I/O control block. These secondary product
terms allow exact emulation of 74-series macrofunctions.
The MAX 5000 macrocell configurability makes it possible to efficiently
integrate complete subsystems into a single device.

Clocking Options
Each LAB supports either global or array clocking. Global clocking is
provided by a dedicated Clock signal (eLK) that offers fast Clock-to-output
delay times. Since each LAB has one global Clock, all flipflop Clocks
within the LAB can be positive-edge-triggered from the eLK pin. If the eLK
pin is not used as a global Clock, it can be used as a high-speed dedicated
input.
In the array clocking mode, each flipflop is clocked by a product term. Any
input pin or intemallogic can be used as a Clock source. Array clocking
allows each flipflop to be configured for positive- or negative-edge-triggered
operation, giving the macrocell increased flexibility. Systems that require
multiple Clocks are easily integrated into MAX 5000 EPLDs.
Each flipflop in an LAB can be clocked by a different array-generated
Clock; however, global and array clocking modes cannot be mixed in the
same LAB.

Expander Product Terms
While most logic functions can be implemented with the product terms
available in each macrocell, some logic functions are more complex and
require additional product terms. Instead of using additional macrocells to
supply the needed logic resources, the MAX 5000 architecture uses shared
expander product terms that provide additional product terms directly to
any macrocell in the same LAB. These expanders help ensure that logic is
synthesized with the fewest possible logic resources to obtain the fastest
possible speed.

I Page 154

Altera Corporation

I Data Sheet

MAX 5000/EPS464 Programmable Logic Device Family I

Each LAB has 32 shared expanders (except for the EPM5032 LAB, which
has 64). The expanders can be viewed as a pool of uncommitted product
terms. The expander product-term array (see Figure 3) contains unallocated,
inverted product terms that feed the macrocell array. Expanders can be
used and shared by all product terms in the LAB. Wherever extra logic is
needed (including register control functions), expanders can be used to
implement the logic. These expanders provide the flexibility to implement
register- and product-term-intensive designs for MAX 5000 EPLDs.

Figure 3. Expander Product Terms
Expander product terms are unallocated logic that can be used and shared by all
macrocells in an LAB. Sharing allows efficient integration of complex combinatorial
functions.
to Macrocell Array

D•••

D-

6···
8 or 20
Dedicated
Inputs

•••

24 Programmable
Interconnect Signals
(multi-LAB devices only)

Macrocell
Feed backs

I···~
32 or 64
Expander
Product Terms

Expanders are fed by all signals in the LAB. One expander can feed all
macrocells in the LAB or multiple product terms in the same macrocell.
Since expanders also feed the secondary product terms of each macro cell,
complex logic functions can be implemented without using additional
macrocells. Expanders can also be cross-coupled to build additional
flipflops, latches, or input registers. A small delay (tSEXP) is incurred when
shared expanders are used.

Programmable Interconnect Array
The higher-density MAX 5000 devices-EPM5064, EPM5128, EPM5128A,
EPM5130, EPM5192, and EPM5192A-use a Programmable Interconnect
Array (PIA) to route signals between the various LABs. The PIA, which is
fed by all macrocell and 110 pin feedbacks, routes only the signals required
for implementing logic in an LAB. While the routing delays of channelbased routing schemes in masked or field programmable gate arrays
(FPGAs) are cumulative, variable, and path-dependent, the MAX 5000
PIA has a fixed delay. The PIA thus eliminates skew between signals, and
makes timing performance easy to predict.

I Altera Corporation

Page 155

I MAX 5000/EPS464 Programmable Logic Device Family

Data Sheet I

I/O Control Blocks
Each LAB has an I/O control block that allows each I/O pin to be
individually configured for input, output, or bidirectional operation. See
Figure 4. The I/O control block is fed by the macrocell array. A dedicated
macrocell product term controls a tri-state buffer, which drives the I/O
pad.

Figure 4. I/O Control Block
The decoupled liD control block features dual feedback to maximize flexibility of device
pins.
OE Control (from Macrocell Product Term)
from Macrocell Array
Macrocell Feed back
I/O Pin Feed back

Each 1/ 0 pin in a MAX 5000 device provides dual feedback, i.e., a feedback
path both before and after the tri-state buffer. Since the tri-state buffer
decouples the I/O pins from the macro cells, all registers within the LAB
can be "buried." Thus, I/O pins can be configured as dedicated input,
output, or bidirectional pins. Using an I/O pin as an input in single-LAB
devices reduces the number of available expanders by two. In multi-LAB
devices, I/O pins feed the PIA directly.

Design Security

All MAX 5000 EPLDs contain a programmable Security Bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
since programmed data within EPROM cells is invisible. The Security Bit
that controls this function, as well as all other program data, is reset when
an EPLD is erased.

Timing Model

MAX 5000 EPLD timing can be analyzed with MAX+PLUS II software,
with a variety of other industry-standard CAE simulators and timing
analyzers, or with the timing model shown in Figure 5. MAX 5000 EPLDs
have fixed internal delays that allow the user to determine the worst-case
timing for any design. MAX +PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis.

I Page 156

Altera Corporation

I Data Sheet

MAX 5000/EPS464 Programmable Logic Device Family I

Figure 5. Timing Models
Design performance can be predicted with these timing models and the device
performance specifications.
Single-LAB EPLDs

~ Input
Delay

tIN

Output
Delay

too
txz
tzx
1/0
Delay
t lO

Multi-LAB EPLDs

~ Input
Delay
tiN

Output
Delay

too
txz
tzx
PIA
Delay
tplA

Timing information can be derived from the timing model and parameters
for a particular EPLD. External timing parameters are calculated with the
sum of internal parameters and represent pin-to-pin timing delays. Figure 6
shows the internal timing relationship for internal and external delay
parameters. For more information on EPLD timing, refer to Application
Brie/IOO (Understanding EPLD Timing) in this data book.

I Altera Corporation

Page 157

MAX 5000/EPS464 Programmable Logic Device Family

Figure 6. Switching Waveforms
In multi-LAB EPLDs, liD
pins that are used as
inputs traverse the PIA.

Data Sheet

Input Mode

!--tlN - !

Input Pin

===1

:--tIO - :

1/0 Pin

tR & tF <3 ns.
Inputs are driven at
3 V for a logic high and
oV for a logic low.
AI/ timing characteristics
are measured at 1.5 V.

Expander Array
Delay
Logic Array
Input

--------------~x~------~l---------

Logic Array
Output

______________________~x~~I-------

Output Pin

__________________________.~t====

tCOM8-i

1+ too+i

Array Clock Mode

tR-i

Clock Pin
Clock into
Logic Array

i - tACH

-Y

i~!

tF -+i 1-

i--tACL-i

\'--!- - - - - - - - -

(,----------,,\-------------'1

\-------

:-t1c-i

Clock from
Logic Array

------------~V~------~\~----~I
i- tsu-+i- tH -!

Data from
Logic Array

tRO ' tLATCH

--------~X

-+:

X~----~t~----------:+-- tCLR ' tpRE -! i- tFD

i- tFD-i

--------------~.--~*,----------~x===
:+--tpIA-i

__________________________-----'x~-----------Global Clock Mode

tF-i iGlobal
Clock Pin

\,-!---------

Global Clock
at Register

\'-----

Data from
Logic Array

Output Mode
Clock from
Logic Array

L~%"A~~~
Output Pin

Page 158

j'----""""'I\,--,_ _ _ _ _-',j
. tRO

\'------

too.

=d-!-i:.:

x=;K

!~!

X,--------,j,

X'--:--______
!~:

Hi9h-~~~dance ~(r-----

Altera Corporation

Data Sheet

Generic Testing

MAX 5000/EPS464 Programmable Logic Device Family I

MAX 5000 EPLDs are fully functionally tested and guaranteed. Complete
testing of each programmable EPROM bit and all internal logic elements
ensures 100% programming yield. AC test measurements are taken under
conditions equivalent to those in Figure 7.

Figure 7. AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous
transitions of multiple outputs should
be avoided for accurate measurement.
Threshold tests must not be performed
under AC conditions. Large-amplitude,
fast ground-current transients normally
occur as the device outputs discharge
the load capacitances. When these
transients flow through the parasitic
inductance between the device ground
pin and the test system ground,
significant reductions in observable
noise immunity can result.

r-----vcc
4640
(1500)
to Test

2500
(820)
Device input
rise and fall
times < 3 ns

Numbers in parentheses are for the
EPM5016.

Test patterns can be used and then erased during early stages of the device
production flow. EPROM-based EPLDs in one-time-programmable
windowless packages also contain on-board logic test circuitry to allow
verification of function and AC specifications during this production flow.

MAX+PLUS II
Development
System

MAX 5000 EPLDs are supported by the MAX+PLUS II development
system, a completely integrated environment for design entry, compilation,
verification, and programming. MAX+PLUS II software is available for
386- and 486-based PCs, Sun SPARCstations, and HP 9000 Series 700
workstations. MAX+PLUS II provides more than 300 74-series
macrofunctions and the Altera Hardware Description Language (AHDL),
which supports state machine, Boolean equation, conditional logic, and
truth table entry methods. MAX+PLUS II also provides highly automated
compilation, automatie multi-device partitioning, timing simulation and
analysis, automatic error location, device programming and verification,
and a comprehensive on-line help system.
In addition, MAX+PLUS II imports and exports industry-standard EDIF
2 a a and EDIF 2 9 a netlist files for a convenient interface to industrystandard CAE tools from vendors such as Cadence, Data I/O, Exemplar,
Intergraph, Mentor Graphics, OrCAD, Synopsys, and Viewlogic.
MAX+PLUS II also exports Verilog and VHDL netlist files that support
simulation with other industry-standard simulators. For further details

I Altera Corporation

Page 159

I MAX 5000/EPS464 Programmable Logic Device(Family

Data Sheet I

about MAX+PLUS II and other CAE tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and CAE
Software Support in this data book.

Device
Programming

All MAX 5000 EPLDs can be programmed on 386- and 486-based PCs with
an Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity checking
to ensure adequate electrical contact between the adapter and the device.
For more information, see Altera Programming Hardware.
MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text or Waveform Editor to test a
programmed device. For added design verification, designers can perform
functional testing to compare the functional behavior of a MAX 5000 EPLD
to the results of simulation. (This feature requires a device adapter with the
"PLM-" prefix.)
Data I/O and other programming hardware manufacturers also offer
programming support for Altera devices. For more information, see
Programming Hardware Manufacturers.

QFP Carrier &
Development
Socket

I Page 160

MAX 5000 devices in QFP packages with 100 or more pins are shipped in
special plastic carriers to protect the fragile QFP leads. Each carrier can be
used with a prototype development socket and special programming
hardware available from Altera. This carrier technology makes it possible
to program, test, erase, and reprogram devices without exposing the leads
to mechanical stress. For detailed information and carrier dimensions,
refer to the QFP Carrier & Development Socket Data Sheet.

Altera Corporation

EPM5016 EPLD
Features

o
o
o
o
o

High-speed, single-LAB MAX 5000 EPLD
tpD as fast as 15 ns
Counter frequencies up to 100 MHz
Pipelined data rates up to 100 MHz
16 individually configurable macrocells
32 shareable expander product terms ("expanders") allowing 36
product terms in a single macrocell
24-mA output drivers to allow direct interfacing to system buses
Programmable I/O architecture allowing up to 16 inputs or 8 outputs
Available in 20-pin, windowed ceramic and plastic one-timeprogrammable (OTP) packages (see Figure 8):
Dual in-line (CerDIP and PDIP)
Small-outline integrated circuit (plastic sorc only)

Figure B. EPM5016 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT

INPUT

INPUT/elK

INPUT

I/O

I Altera Corporation

INPUT
INPUT
I/O

I/O

vee

I/O

GND

vee

I/O

GND

I/O

INPUT

20-Pin DIP

General
Description

INPUT
INPUT/elK

I/O

INPUT

20-Pin SOIC

The Altera EPM5016 is a MAX 5000 EPLD optimized for speed. It can
integrate multiple SSI and MSI TTL and CMOS logic devices. In addition,
the EPM5016 can replace any 20-pin PAL or PLA device with logic left over
for further integration. The EPM5016 contains 16 macro cells; the expander
product-term array provides 32 expanders. The I/ 0 control block contains
8 bidirectional I/O pins that can be configured for dedicated input,
dedicated output, or bidirectional operation. All I/O pins feature dual
feedback for maximum pin flexibility. See Figure 9.

Page 161

EPM5016 EPLD

Data Sheet

Figure 9. EPM5016 Block Diagram
11

INPUT

,..........,

INPUT

,...--,
~

,..........,

.---...
~

INPUT/CLK 2
INPUT

I
N

,...--,
~

INPUT

E
R

MACROCELL2

MACROCELL4

MACROCELL6

MACROCELL8

0
N
N
E

C
T

MACROCELL 1

MACROCELL3

MACROCELL5

MACROCELL 7

..........

..........
..........

..........

I/O
Control
.......... Block I-----tl~--!<

MACROCELL 10

MACROCELL9

MACROCELL 12

MACROCELL 11

MACROCELL 14

MACROCELL 13

I-----.---i<_/l 17

MACROCELL 16

MACROCELL 15

32 Expander Product-Term Array

Figure 10 shows the output drive characteristics of EPM5016I/O pins and
typical supply current (Icd versus frequency for the EPM5016.

Figure 10. EPM5016 Maximum Output Drive Characteristics &Icc vs. Frequency
180
200
150

ci.
~
~

160

120

ci.
~

S
~

S
Q)

:::J

()

..9

...9

Vee = 5.0 V
Room Temp.

120

Vee =5.0V
Room Temp.

Vo Output Voltage (V)

Page 162

100 Hz 1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 100 MHz

Maximum Frequency

Altera Corporation

Data Sheet

EPMS016 EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

200

lOUT

DC output current, per pin

Power dissipation

-25

1000

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit

Recommended Operating Conditions
Symbol

Note (2)

Parameter

Conditions

Min

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

°C

Input rise time

100

Input fall time

100

DC Operating Conditions
Symbol

4.75 (4.5) 5.25 (5.5)

-40

V
V

Notes (2), (3), (4)

Parameter

Conditions

Min

Typ

Max

Unit

V'H

High-level input voltage

2.0

Vee + 0.3

V'L
V OH

Low-level input voltage

-0.3

0.8

High-level TTL output voltage

10H = -12 mA DC

VOL

Low-level output voltage

10L = 24 mA DC

Input leakage current

V, = Vee or GND

loz

Tri-state output off-state current

Vo =V ee orGND

lee1

Vee supply current (standby)

V, = Vee or GND, Note (5)

lee3

Vee supply current (active)

V, = Vee or GND, No load,

2.4

0.5

-10

IlA

-40

IlA

110(150)

115(175)

Min

Max

Unit

f = 1.0 MHz, Note (5)

Capacitance
Symbol

Parameter

Conditions

C'N

Input capacitance

v, N = 0 V, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

Altera Corporation

Page 1631

I EPM5016 EPLD

Data Sheet

AC Operating Conditions

Note (4)

External Timing Parameters
Symbol

EPM5016-15 EPM5016-17 EPM5016-20

Parameter

Conditions
=

Min Max Min Max Min Max Unit

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

35 pF

ns
ns
13

tCH

Global clock high time

tCl
t ASU

Global clock low time

Array clock setup time

tAH
t AC01

Array clock hold time

Array clock to output delay

tACH
t ACl

Array clock high time

Note (6)

Array clock low time

35 pF

ns
18

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (5)

f ACNT

Max. internal array clock frequency

Note (5)

100

83.3

62.5

MHz

f MAX

Maximum clock frequency

Note (7)

100

83.3

62.5

MHz

10
100

Minimum array clock period

Internal Timing Parameters
Symbol

12
83.3

Note (8)

16
62.5

ns
MHz

EPM5016-15 EPM5016-17 EPM5016-20

Parameter

Conditions

Min Max Min Max Min Max Unit

tIN
tlO
t EXP

Input pad and buffer delay

1/0 input pad and buffer delay

Expander array delay

tLAD
t LAC

Logic array delay

Logic control array delay

Output buffer and pad delay
Output buffer enable delay

txz

Output buffer disable delay

tsu
t LATCH

tRD

tCOMB
tH

Combinatorial delay

tIC

Array clock delay

tICS
tFO

Global clock delay

Feedback delay

tpRE

tCLR

I Page 164

= 35 pF

too
tzx

= 5 pF

ns
ns

Altera Corporation

Data Sheet

EPM5016 EPLD

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

Product
Ava ilabil ity

Altera Corporation

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in parentheses are for military- and industrial-temperature-range versions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
Measured with a device programmed as a 16-bit counter. Icc measured at 0° C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and tACL parameters must be swapped.
The fMAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Availability

Product Grade
Commercial Temp.

(0° C to 70° C)

EPM5016-15, EPM5016-17, EPM5016-20

Industrial Temp.

(-40° C to 85° C)

EPM5016-20

Military Temp.

(-55° C to 125° C)

Consult factory

Page 165

Notes:

EPM5032 EPLD
Features

o
o
o

High-speed, single-LAB MAX 5000 EPLD
tpD as fast as 15 ns
Counter frequencies up to 77 MHz
Pipelined data rates up to 83 MHz
32 individually configurable macro cells
64 shareable expander product terms ("expanders") allowing 68
product terms on a single macro cell
Programmable 1/ 0 architecture allowing up to 24 inputs or 16 outputs
A vailable in 28-pin windowed ceramic and plastic one-timeprogrammable (OTP) packages (see Figure 11):
Dual in-line (CerDIP and PDIP)
J-Iead chip carrier (JLCC and PLCC)

Figure 11. EPM5032 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT

INPUT

INPUTleLK

INPUT

1/0

110

1/0

INPUT

GND

INPUT

1/0

I/O

110

I/O

I Altera Corporation

26
25

1/0

110

INPUT

I/O

INPUT

28-Pin DIP

General
Description

INPUT

vee

I/O

110

vee

1/0

()
()

EPM5032

I/O

INPUT

1/0

0
0

28-Pin J-Lead

The Altera EPM5032 EPLD is a MAX 5000 EPLD optimized for speed. It
can integrate multiple SSI and MSI TTL and CMOS logic devices. In
addition, the EPM5032 can replace multiple 20-pin PAL or PLA devices
with logic left over for further integration. The EPM5032 contains 32
macrocells; the expander product-term array provides 64 expanders. The
1/ 0 control block contains 16 bidirectional 1/ 0 pins that can be configured
for dedicated input, dedicated output, or bidirectional operation. All I/O
pins feature dual feedback for maximum pin flexibility. See Figure 12.

Page 167

EPM5032 EPLD

Data Sheet

Figure 12. EPM5032 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-Iead packages.
15 (22)

INPUT

(8)

16 (23)

INPUT

INPUT/ClK 2

(9)

27 (6)

INPUT

13 (20)

28 (7)

INPUT

14 (21)

MACROCEll4
MACROCEll6
MACROCEll8
MACROCELL 10
MACROCELL 12
MACROCEll14
MACROCELL 16

(10)

(11)

MACROCEll5

(12)

MACROCEll7

(13)
(16)

I
N

T
E
R
C
0
N
N

E
C
T

MACROCELL9

MACROCELL 11

10 (17)

MACROCELL 13

MACROCELL 15

I/O

Control
Block

11 (18)
12 (19)

MACROCELL 17

MACROCELL 20

MACROCElL 19

MACROCELL 22

MACROCELL 21

19 (26)

MACROCELL 24

MACROCELL 23

20 (27)

MACROCELL 26

MACROCELL 25

23 (2)

MACROCELL 28

MACROCELL 27

24 (3)

MACROCELL 30

MACROCELL 29

25 (4)

MACROCELL 32

MACROCELL 31

26 (5)

MACROCELL 18

17 (24)
18 (25)

64 Expander Product-Term Array

Page 168

Altera Corporation

I Data Sheet

EPM5032 EPLD I

Figure 13 shows the output drive characteristics of EPM5032 II 0 pins and
typical supply current (Icd versus frequency for the EPM5032.

Figure 13. EPM5032 Maximum Output Drive Characteristics & Icc vs. Frequency
240
100

ci.
~

200
80

()

"5
a.
"5

160

V0 Output Voltage (V)

I Altera Corporation

100 Hz 1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 100 MHz

Maximum Frequency

Page 169

EPM5032 EPLD

Data Sheet

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

300

lOUT

DC output current, per pin

Power dissipation

-25

T8TG

Storage temperature

No bias

TAMB

Ambient temperature

Under bias, Note (2)

Junction temperature

Under bias, Note (2)

1500

-65

150

°C

-65 [-55]

150 [125]

°C

150 [175]

°C

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Min

Conditions
Note (3)

4.75 (4.5) 5.25 (5.5)

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

100

Input fall time

100

Max

Unit

DC Operating Conditions
Symbol

V
V

Notes (4), (5)

Parameter

Conditions

Min

Typ

2.0 [2.2]

Vee +0.3

-0.3

0.8

V ,H

High-level input voltage

V ,L

Low-level input voltage

VO H

High-level TTL output voltage

IOH = -4 mA DC

VOL

Low-level output voltage

IOL = 8 mA DC

Input leakage current

loz

Tri-state output off-state current

V, =V ee orGND
Vo =V ee or GND

IlA

lee1

Vee supply current (standby)

V I = Vee or GND, Notes (3), (6)

120

150 (200)

lee3

Vee supply current (active)

V, = Vee or GND, No load,
f = 1.0 MHz,Notes (3), (6)

125

155 (225)

Min

Max

Unit

Note (2)

2.4

-10
-40

0.45

IlA

Capacitance
Symbol

Parameter

Conditions

C,N

Input capacitance

Y,N = oV,f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

Page 170

Altera Corporation

I Data Sheet

EPM5032 EPLD

AC Operating Conditions

Note (5)

External Timing Parameters
Symbol

EPM5032-15 EPM5032-17 EPM5032-20 EPM5032-25

Conditions Min Max Min Max Min Max Min Max Unit

Parameter

tpD1
t PD2

Input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t Asu

Global clock low time

Array clock setup time

tAH
t AC01

Array clock hold time

Array clock to output delay

tACH

Array clock high time

Note (7)

35 pF

I/O input to non-registered output

9
0
C1

tACl

Array clock low time
Minimum global clock period

fCNT

Max. internal global clock frequency Note (6)

tACNT
f ACNT
f MAX

Minimum array clock period

15
6

8
13

76.9
13

11
16

ns
20

ns
MHz

62.5

9
14

71.4

18
7

0
12

0
10

35 pF

0
10

35 pF

tCNT

Max. internal array clock frequency

Note (6)

76.9

71.4

62.5

MHz

Maximum clock frequency

Note (8)

83.3

71.4

62.5

MHz

Internal Timing Parameters
Symbol
tIN
t/O
t ExP
t LAO
t LAC
too
tzx
txz
tsu
t LATCH
t Ro
tCOMB
tH
tIC
tICS
t Fo
tpRE
tCLR

Note (9)

Parameter

EPM5032-15 EPM5032-17 EPM5032-20 EPM5032-25

Conditions Min Max Min Max Min Max Min Max Unit

Input pad and buffer delay

I/O input pad and buffer delay

Expander array delay

Logic array delay

Logic control array delay
Output buffer and pad delay

C1 = 35 pF

C1 = 5 pF

Output buffer enable delay
Output buffer disable delay
Register setup time

Flow-through latch delay

Combinatorial delay

Array clock delay

Global clock delay

Feedback delay

I Altera Corporation

Page 171

EPM5032 EPLD

Data Sheet

Notes to tables:
(1)
(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in brackets are for MIL-STD-883-compliant versions only.
Numbers in parentheses are for military- and industrial-temperature-range versions,
as well as for MIL-STD-883-compliant versions.
Typical values are for TA = 25° C and Vcc =5 V.
Operating conditions: Vcc = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
VCC =5 V ± 10%, TA =-40° C to 85° C for industrial use.
VCC =5 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a device programmed as a 32-bit counter. Icc measured at 0° C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and tACL parameters must be swapped.
The fMAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Product Grade
Commercial Temp.

Availability

(0° C to 70° C)

EPM5032-15, EPM5032-17, EPM5032-20,
EPM5032-25
EPM5032-25

Industrial Temp.

(-40° C to 85° C)

Military Temp.

(-55° C to 125° C) EPM5032-25

MIL-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:
(1)

Page 172

Altera Corporation

EPS464 EPLD Overview
Features

o
o

For detailed
information, refer
to "EPS464 EPlD"
in this data sheet.

o
o

High-performance, globally-routed, general-purpose EPLD
Combinatorial speeds as fast as 20 ns
Counter frequencies up to 67 MHz
Pipelined data rates up to 71 MHz
64 enhanced macrocells and 256 shared expander product terms
(" expanders"); ideal for custom waveform generation and state
machine designs
Programmable registers providing D, T, JK, and SR flipflops with
individual Clear, Preset, and Clock controls
Powerful macrocell architecture optimized for:
Modulo-n binary and Gray-code counters
Complex state machines
Multiple product-term JK flipflops for waveform generation
Phase comparator and Clock oscillator functions
Noise-resistant input buffers with 250-mV hysteresis and quiet output
buffers for noise immunity and reliable operation
Programmable Security Bit for total protection of proprietary designs
Programmable I/O support for up to 36 inputs or 32 outputs
Available in 44-pin windowed ceramic and one-time-programmable
(OTP) packages (see Figure 14):
J-lead chip carrier (JLCC and PLCC)
Quad flat pack (plastic PQFP only)

Figure 14. EPS464 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Table 11 in this data sheet for OFP pin-out
information. Windows in ceramic packages only.

5 4

1 44 4342 41 40

o
EPS464

Pin 23

Pin 12

44-Pin J-Lead

I Altera Corporation

44-Pin QFP

Page 173

Notes:

EPM5064 EPLD
Features

o
o
o
o

o
o

High-density, 64-macrocell, general-purpose MAX 5000 EPLD
High-speed multi-LAB architecture
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 63 MHz
128 shareable expander product terms ("expanders") allowing over
32 product terms in a single macrocell
Programmable II 0 architecture allowing up to 36 inputs or 28 outputs
Available in 44-pin windowed ceramic and one-time-programmable
(OTP) J-lead chip carrier packages (JLCC and PLCC). See Figure 15.
Easy integration of 10 standard PALs in 1f2 square inch of board space

Figure 15. EPM5064 Package Pin-Out Diagram
Package outline not drawn to scale. Windows in ceramic packages only.

44 43 42 41

I/O
I/O
I/O

GND

INPUT

vee

I/O

vee
INPUT
INPUT/elK
INPUT
GND

I/O
I/O

EPM5064
18 19 20 21 22 23 24 25 26 27 28

~ ~ ~ ~ ~ ~ ~
(!)

~ ~ ~

44-Pin J-Lead

General
Description

The Altera EPM5064 EPLD is a user-configurable, high-performance
MAX 5000 EPLD that serves as a high-density replacement for 74-series
SSI and MSI TTL and CMOS logic. In addition, the EPM5064 can integrate
multiple 20- and 24-pin low-density PLDs. For example, the EPM5064 can
integrate the logic contained in over 10 standard 20-pin PALs.
The EPM5064 consists of 64 macro cells equally divided into 4 Logic Array
Blocks (LABs) with 16 macrocells. Each LAB also contains 32 expander
product terms. The EPM5064 has 8 dedicated input pins, one of which can
be used as a global system Clock that provides enhanced Clock-to-output

I Altera Corporation

Page 175

EPM5064 EPLD

Data Sheet

delays. The device has 281/ 0 pins that can be configured for input, output,
or bidirectional operation. AlI 1/0 pins feature dual-feedback for maximum
pin flexibility. Two of the LABs have 81/ 0 pins, ensuring high speed for 8bit bus functions; the other two LABs have 61/0 pins. See Figure 16.

Figure 16. EPM5064 Block Diagram
c:J

INPUT c:::)

11 INPUT ..........

~INPUT

r::::::

-::::::: INPUT

LAB A

~
7'"

17
18
19
20
22
23

MACROCELL4
MACROCELL5
MACROCELL6

LAB D

MACROCELL 56
MACROCELL 55

....-

f---+
1"-

----.

MACROCELL 53

f-~

MACROCELL 52
MACROCELL 51
MACROCELL 50

7to 16

MACROCELLS

+ +

g
~
~
~
~
~

MACROCELL 19

MACROCELL 18

MACROCELL 21
MACROCELL 22
MACROCELL 23

f---+
I+-

~
f-;:>-::
~
r-~
r-7"
~
f-"""

40
39
38
37

57 to 64

LABC

MACROCELL 38
MACROCELL 37
MACROCELL 36

MACROCELL 20

MACROCELL 54

MACROCELL 49

Programmable
Interconnect
Array
(PIA)

r-~
r-~

f-7'<

MACROCELLS

MACROCELL 17

:::...::

Global Clock

MACROCELL3

LAB B

7'"

Dedicated Inputs

MACROCELL2

:::...::

! ,

MACROCELL 1

~
~
~
~

12 INPUT c:::)
13 INPUT

INPUT

, - , INPUT/CLK 34

.--+

MACROCELL 35
MACROCELL 34
MACROCELL 33

MACROCELL 24

MACROCELLS

39 to 48

r-7"

r-~

~
f-;;;:;
~
f-~
f-7"
~
r-"""

28
27
26
24

25 to 32

Page 176

Altera Corporation

I Data Sheet

EPM5064 EPLD

Figure 17 shows the output drive characteristics of EPM5064I/O pins and
typical supply current (Icd versus frequency for the EPM5064. The high
integration density of the EPM5064 can greatly reduce system power
requirements.

Figure 17. EPM5064 Maximum Output Drive Characteristics & Icc vs. Frequency
200r--------------------------.
100
IOL

ci.
~

E.
E

~
~

E.
Q)

~--------------

"5
a.
"5

Vee = 5.0 V
Room Temp.

150

V0 Output Voltage (V)

I Altera Corporation

100 Hz 1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 100 MHz

Maximum Frequency

Page 177

EPM5064 EPLD

Data Sheet

Absolute Maximum Ratings
Symbol

See Operating Requirements for A/tera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

400

lOUT

DC output current, per pin

Power dissipation

-25

2000

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

Note (2)

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

°C

4.75 (4.5) 5.25 (5.5)

For commercial use

V
V

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

100

Input fall time

100

Max

Unit

DC Operating Conditions
Symbol

Notes (3), (4)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

lee3

Vee supply current (active)

= -4 mA DC
10L = 8 mA DC
V I =Vee or GND
V 0 =Vee or GND
V I =Vee or GND, Notes (2), (5)
V I =Vee or GND, No load,
f = 1.0 MHz,Notes (2), (5)
10H

2.4

-10
-40

0.45

flA

125 (200)

135 (225)

Min

Max

Unit

Capacitance
Symbol

Parameter

CIN

Input capacitance

COUT

Output capacitance

Page 178

Conditions

= 0 V, f = 1.0 MHz
V OUT = 0 V, f = 1.0 MHz

V IN

Altera Corporation

Data Sheet

EPM5064 EPLD

AC Operating Conditions

Note (4)

External Timing Parameters
Symbol

Conditions

EPM5064-2

EPM5064

Min Max Min Max Min Max Unit

= 35 pF

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

12.5

tCl
t ASU

Global clock low time

12.5

Array clock setup time

= 35 pF

ns
ns

tAH
t AC01

Array clock hold time
Array clock to output delay

tACH
t ACl

Array clock high time

Note (6)

tCNT

Minimum global clock period

fCNT
t ACNT
f ACNT

Max. internal global clock frequency Note (5)

Max. internal array clock frequency

Note (5)

33.3

MHz

f MAX

Maximum clock frequency

Note (7)

62.5

MHz

30
14

25
40

50
20

EPM5064-1

Conditions

Minimum array clock period

Parameter

ns
35

Note (8)

= 35 pF

Array clock low time

Internal Timing Parameters

EPM5064-1

Parameter

Symbol

30
33.3

EPM5064-2

ns
MHz

EPM5064

Min Max Min Max Min Max Unit

tIN

Input pad and buffer delay

tlO
t EXP

I/O input pad and buffer delay

Expander array delay

t LAo

Logic array delay

t LAC

Logic control array delay

Output buffer and pad delay
Output buffer enable delay

txz

Output buffer disable delay

tsu

tLATCH
t RO

Flow-through latch delay

tCOMB
tH

Combinatorial delay

tIC

Array clock delay

tICS
t FO

Global clock delay

Feedback delay

tpRE

tCLR
tplA

Prog. Interconnect Array delay

= 35 pF

too
tzx

Altera Corporation

= 5 pF

3
4

Page 1791

Data Sheet

EPM5064 EPLD

Notes to tables:
(1)
(2)
(3)
(4)

(5)
(6)
(7)
(8)

Product
Availability

Page 180

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in parentheses are for military- and industrial-temperature-range versions.
Typical values are for TA = 25° C and Vcc =5 V.
Operating conditions: Vcc =5 V ± 5%, TA =0° C to 70° C for commercial use.
Vcc =5 V ± 10%, TA =-40° C to 85° C for industrial use.
Vcc = 5 V ± 10%, Tc = -55° C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 0° C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and tACL parameters must be swapped.
The fMAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Availability

Product Grade
Commercial Temp.

(0° C to 70° C)

EPM5064-1, EPM5064-2, EPM5064

Industrial Temp.

(-40 0 C to 85° C)

EPM5064

Military Temp.

(-55° C to 125° C)

EPM5064

Altera Corporation

EPM5128 EPLD •
Features

High-density, 128-macrocell, general-purpose MAX 5000 EPLD
High-speed multi-LAB architecture
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
256 shareable expander product terms ("expanders") allowing over
32 product terms in a single macrocell
Programmable 1/ 0 architecture allowing up to 60 inputs or 52 outputs
A vailable in 68-pin windowed ceramic and plastic one-timeprogrammable (OTP) packages·(see Figure 18):
J-Iead chip carrier (JLCC and PLCC)
Pin-grid array (ceramic PGA only)

o
o
o
o

Figure 18. EPM5128 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Tables 3 and 4 in this data sheet for pin-out
information. Windows in ceramic packages only.
:5
()
t-i==:1-

o=>=>=>o=>

~~~~~~~~~~a~~~~~~
mro~w~VMN~m~~~~~~w

I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O

vee

I/O
I/O
I/O
I/O
I/O
I/O

0
EPM5128
~romo~NMv~w~oomO~NM
NNNM~M~MMMM~Mvv~v

~~~~~~~~~~~~~~~~~

68-Pin J-Lead

General
Description

I/O
I/O
I/O
I/O
I/O
I/O

vee

48
47
46
45
44

I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O

000000000
K00000000000
J 00
00
H00
00
00 EPM5128 00
G

F roVo'l
\:::.J\:::.J

Bottom

View

\:::.J\:::.J

00
00
00
00
c 00.
00
800000000000
A 0000000000
E

10 11

68-Pin PGA

The Altera EPM5128 EPLD is a user-configurable, high-performance
MAX 5000 EPLD that provides a high-density replacement for 74-series
SSI and MSI TTL and CMOS logic. For example, a 74161 counter uses only
3% of the EPM5128 EPLD. The EPM5128 can replace over 60 TTL MSI and
SSI components and integrate multiple 20- and 24-pin low-density PLDs.
The EPM5128 consists of 128 macrocells equally divided into 8 Logic Array
Blocks (LABs) with 16 macrocells. Each LAB also contains 32 expander
product terms. The EPM5128 has 8 dedicated input pins, one of which can
be used as a global system Clock. The EPM5128 contains 52 I/O pins that

I Altera Corporation

Page 181

EPM5128 EPLD

Data Sheet

can be configured for input, output, or bidirectional operation. Four of the
LABs have 8 I/O pins; the other 4 have 5 I/O pins. See Figure 19.
Figure 19. EPM5128 Block Diagram
Numbers without parentheses are for J-/ead packages. Numbers in parentheses are for PGA packages.
1

(B6) INPUT/CLK

(A6)

INPUT

(A5)

32 (L4)

INPUT ~
INPUT

(B4)

(A4)

(B3)

(A3)

(A2)

10 (B2)
11 (Bl)

~ INPUT (A7) 68

c::::::

34 (L5)

.----. INPUT (A8) 66

~ INPUT (L6) 36

c:::>

c::J

~ +

LABA

(B8)

MACROCELL2

MACROCELL 119

1-::::..:

(A9)

MACROCELL3

MACROCELL 118

(B9)

MACROCELL4

~
~
~
~

.......

r--.
.......

13 (Cl)
14 (D2)
15 (Dl)
17 (El)

~
~
~
~

::::..:

~?<

(Bl0) 61

I-~

(Bl1) 60

MACROCELL 114

MACROCELL8

MACROCELL 113

I-E

(Cl0) 58

MACROCELLS

MACROCELL 101

(Dll) 57

....-

MACROCELL 100

1-::::..:

MACROCELL 97

MACROCELL 7

•+

MACROCELL 17
MACROCELL 18

......

MACROCELL 19
MACROCELL 20
MACROCELL 21

1"-

19 (Fl)
21 (Gl)
22 (H2)
23 (HI)

~
7""
~
~
~

:::..:::

MACROCELL33

MACROCELL 34
MACROCELL 35

~
~

MACROCELL 36
MACROCELL 37

......

MACROCELLS

24 (J2)
25 (Jl)
26 (Kl)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)

Page 182

7":

~
~
~
~
~
~
~

:::..:::

LABG

MACROCELL 99
MACROCELL 98

I-~
~~

(Dl0) 56
(Ell) 55
(Fl1) 53

(FlO) 52

••

102to 112
LAB F

MACROCELL85

....-

-........

•+

MACROCELL 84

I-~

MACROCELL 83

~?<

MACROCELL 82

1-:::".:

MACROCELL 81

(GIl) 51
(Hll) 49
(Hl0) 48

(Jll) 47

I-~

(Jl0) 46

I-~

(Kll) 45

MACROCELLS

38 to 48
LAB D

(Cl1) 59

MACROCELLS

Programmable
Interconnect
Array
(PIA)

22 to 32
LABC

•

121 to 128

MACROCELLS

18 (F2)

(Al0) 62

1-:::".:

LABB
7""

I-~

MACROCELL 115

MACROCELL6

9 to 16

12 (C2)

MACROCELL 117

I-~

MACROCELL 116

MACROCELL5

::::..:

LAB H

MACROCELL 120

MACROCELL 1

~
~
7""

Dedicated Inputs
Global Clock

INPUT (K6) 35

•

86 to 96

MACROCELL 49

LAB E

MACROCELL 72

MACROCELL 50

MACROCELL 71

MACROCELL 51

MACROCELL 70

1-::::..:

(Ll0) 43

MACROCELL 69

I-E

(L9)

MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55

---.
.--

..---+

MACROCELL 68
MACROCELL 67
MACROCELL 66

MACROCELL 56

MACROCELL 65

MACROCELLS

57 to 64

73 to 80

I-~
~~

I-~
I-~

(Kl0) 44

(K9)

(L8)

(K8)

(L7)

Altera Corporation

I Data Sheet

EPM5128 EPLD I

Figure 20 shows the output drive characteristics of EPM5128 II 0 pins and
typical supply current (lcd versus frequency for the EPM5128.

Figure 20. EPM5128 Maximum Output Drive Characteristics &Icc vs. Frequency
400~-------------------------.

100

IOL

ci.
~

S
~
~

200

t5
«

()

..!:?

..9

Vee = 5.0 V
Room Temp.

()

"5
0..
"5

300

100

Vo Output Voltage (V)

I Altera Corporation

100 Hz

1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 50 MHz

Maximum Frequency

Page 183

I EPM5128 EPLD

Data Sheet

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.
Conditions

Parameter

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

I MAX

DC Vee or GND current

-2.0

lOUT

DC output current, per pin

Power dissipation

-25

TSTG

Storage temperature

No bias

TAMB

Ambient temperature

Under bias, Note (2)

Junction temperature

Under bias, Note (2)

7.0

500

2500

-65

150

°C

-65 [-55]

135 [125]

°C

150 [175]

°C

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

100

Input fall time

100

DC Operating Conditions
Symbol

Note (3)

4.75 (4.5) 5.25 (5.5)

V
V

Notes (4), (5)

Parameter

Conditions
Note (2)

Min

Typ

Max

Unit

2.0 [2.2]

Vee + 0.3

-0.3

0.8

V IH

High-level input voltage

V IL

Low-level input voltage

V OH

High-level TTL output voltage

VOL

Low-level output voltage

10L ::: 8 mA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

!J.A

lee1

Vee supply current (standby)

V I = Vee or GND, Notes (3), (6)

150

225 (300)

lee3

Vee supply current (active)

V I = Vee or GND, No load,
f = 1.0 MHz, Notes (3), (6)

155

250 (350)

Min

Max

Unit

10H = -4mA DC

2.4

V
V

0.45

!J.A

Capacitance
Symbol

Parameter

Conditions

CIN

Input capacitance

V IN = OV,f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

I Page 184

Altera Corporation

I Data Sheet

EPM5128 EPLD

AC Operating Conditions

Note (5)

External Timing Parameters
Symbol

EPM5128-1

Parameter

Conditions

EPM5128-2

EPM5128

Min Max Min Max Min Max Unit

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

12.5

tCl
t ASU

Global clock low time

12.5

Array clock setup time

C1 = 35 pF

Array clock hold time
Array clock to output delay

C1 = 35 pF

tACH
t ACl

Array clock high time

Note (7)

C1 = 35 pF

tAH
t AC01

ns
ns

Array clock low time

ns
35

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (6)
Minimum array clock period

f ACNT

Max. internal array clock frequency

Note (6)

33.3

MHz

f MAX

Maximum clock frequency

Note (8)

62.5

MHz

Internal Timing Parameters
Symbol

25
40

50
20

Note (9)

Parameter

EPM5128-1

Conditions

30
33.3

EPM5128-2

ns
MHz

EPM5128

Min Max Min Max Min Max Unit

Input pad and buffer delay

1/0 input pad and buffer delay

Expander array delay

Logic array delay

t LAC

Logic control array delay

too
tzx

Output buffer and pad delay

txz

Output buffer disable delay

tsu

tLATCH
t RO
tCOMB
tH
t,C

Flow-through latch delay

Combinatorial delay

t,N
t,O
t EXP
t LAO

C1 = 35 pF

Output buffer enable delay

C1 = 5 pF

13
12

ns
ns
ns

Array clock delay

t,CS
t Fo

Global clock delay

Feedback delay

tpRE

tCLR
tplA

I Altera Corporation

Page 185

EPM5128 EPLD

Data Sheet I

Notes to tables:
(1)
(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in brackets are for MIL-STD-883-compliant versions.
Numbers in parentheses are for military- and industrial-temperature-range versions,
as well as for MIL-STD-883-compliant versions.
Typical values are for TA = 25° C and Vcc =5 V.
Operating conditions: Vcc =5 V ± 5%, TA = 0° C to 70° C for commercial use.
VCC =5 V ± 10%, TA =-40° C to 85° C for industrial use.
VCC =5 V ± 10%, Tc =-55° C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 0° C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and tACL parameters must be swapped.
The f MAX values represent the maximum frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Product Grade

Availability

Commercial Temp.

(0° C to 70° C)

EPM5128-1, EPM5128-2, EPM5128
EPM5128

Industrial Temp.

(-40 0 C to 85 0 C)

Military Temp.

(-55 0 C to 1250 C)

EPM5128

MIL-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:
(1)

Pin-Out
Information

Tables 3 and 4 provide pin-out information for the EPM5128.
Table 3. EPM5128 Dedicated Pin-Outs

Dedicated Pin
INPUT/CLK
INPUT
GND

vec

Page 186

68-Pin J-Lead
1
2,32,34,35,36,66,68
16,33,50,67
3,20,37,54

68-Pin PGA
86
A6,L4,L5,L6,K6,A8,A7
87, E2,G10, K5
85, E10, G2, K7

Altera Corporation I

I Data Sheet

EPM5128 EPLD

Table 4. EPM5128 I/O Pin-Outs (Part 1 of 2)

I Altera Corporation

LAB

68-Pin
J-Lead

68-Pin
PGA

LAB

68-Pin
J-Lead

68-Pin
PGA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

4
5
6
7
8
9
10
11

A5
84
A4
83
A3
A2
82
81

C2
C1
D2
D1
E1

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

12
13
14
15
17

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

18
19
21
22
23

F2
F1
G1
H2
H1

24
25
26
27
28
29
30
31

J2
J1
K1
K2
L2
K3
L3
K4

Page 187 I

I EPM5128 EPLD

Data Sheet

Table 4. EPM5128 I/O Pin-Outs (Part 2 of 2)

LAB

68-Pin
J-Lead

68-Pin
PGA

LAB

65
66
67
68
69
70
71
72
73
74
75
76

E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

38
39
40
41
42
43
44
45

L7
K8
L8
K9
L9
L10
K10
K11

52
53
55
56
57

F10
F11
E11
010
011

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

78
79
80
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

I Page 188

68-Pin
J-Lead

68-Pin
PGA

46
47
48
49
51

J10
J11
H10
H11
G11

58
59
60
61
62
63
64
65

C10
C11
B11
B10
A10
B9
A9
B8

Altera Corporation I

EPM5128A EPLD
Features

High-density, second-generation MAX 5000 EPLD developed on an
advanced 0.65-micron CMOS EPROM process
Higher-speed upgrade for existing EPM5128 designs
High-speed multi-LAB architecture
tpD as fast as 12 ns
Counter frequencies up to 111 MHz
256 shareable expander product terms ("expanders") allowing over
32 product terms in a single macrocell
Programmable 110 architecture allowing up to 60 inputs or 52 outputs
High-density replacement for 74-series SSI and MSI TTL and CMOS
logic
A vailable in 68-pin windowed ceramic and plastic one-timeprogrammable (OTP) packages (see Figure 21):
J-Iead chip carrier (JLCC and PLCC)
Pin-grid array (ceramic PGA only)

Preliminary
Information

o
o

Figure 21. EPM5128A Package Pin-Out Diagrams
Package outlines not drawn to scale. See Tables 3 and 4 in this data sheet for package
pin-out information. Windows in ceramic packages only.
~

I--~I-

=:t::J::J

o::J

~~~~~~~~~~a~~~~~~
1/0
1/0
1/0

110
1/0
1/0

GND
1/0
1/0
1/0

vee
1/0
1/0
1/0
1/0
1/0
1/0

0
EPM5128A

~rereg~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~

68-Pin J-Lead

General
Description

I Altera Corporation

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

1/0
1/0
1/0
1/0
1/0
1/0

vee
1/0
1/0
1/0

J
H

GND

1/0
1/0
1/0
1/0
1/0
1/0

GG00GG0GG
0GG00GGGGGG
0G
GG
0G EPM5128A GG
GG
GG
Bottom
GG
GG
View
GG
GG
GG
GG
GGe
GG
GGG00GG0GGG
OGG00GGGGG
1

10 11

68-Pin PGA

The Altera EPM5128A EPLD is a user-configurable, high-performance
MAX 5000 EPLD that is pin-, function- and programming-file-compatible
with the EPM5128. For a description of the device architecture, see
"EPM5128 EPLD" in this data sheet.

Page 189

EPM5128A EPLD

Preliminary Information

Absolute Maximum Ratings

vee

See Operating Requirements for Altera Devices in this data book.

Parameter

Symbol

Data Sheet I

Supply voltage

DC input voltage

I MAX

DC Vee or GND current

lOUT

DC output current, per pin

Power dissipation

Min

Max

Unit

With respect to GND

Conditions

-2.0

7.0

Note (1)

-2.0
-25

7.0

500

2500

T STG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit

Recommended Operating Conditions
Symbol

Conditions

Parameter

Min

4.75 (4.5) 5.25 (5.5)

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

100

Input fall time

100

Max

Unit
V

DC Operating Conditions
Symbol

Note (2)

For commercial use

Notes (3), (4)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V 1L

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

10H = -4 mA DC

VOL

Low-level output voltage

10L = 8 mA DC

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

V I = Vee or GND, Notes (2), (5)

lee3

Vee supply current (active)

V I = Vee or GND, No load,

V
V

2.4
0.45

V I = Vee or GND

-10

IlA

Va =Vee orGND

-40

IlA

150

225 (300)

155

250 (350)

Min

Max

Unit

f = 1.0 MHz, Notes (2), (5)

Capacitance
Symbol

Parameter

Conditions

CIN

Input capacitance

VIN = OV, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

Page 190

Altera Corporation

I Data Sheet

Preliminary Information

AC Operating Conditions

Note (4)

External Timing Parameters
Symbol

EPM5128A EPLD

Parameter

Conditions

EPM5128A-12

EPM5128A-15

EPM5128A-20

Min

Max

Unit
ns

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu
tH

Global clock setup time

tC01
tCH

Global clock to output delay
Global clock high time

4.5

tCl
t ASU

Global clock low time

4.5

Array clock setup time

Array clock hold time

tAH
t AC01

C1 = 35 pF

Global clock hold time

0
C1 = 35 pF

Array clock to output delay

ns
ns

0
7

C1 = 35 pF

ns
16

tACH
t ACL

Array clock high time

4.5

Array clock low time

4.5

tCNT

Minimum global clock period

fCNT
t ACNT
f ACNT

Max. internal global clock frequency Note (5)

Max. internal array clock frequency

Note (5)

111.1

83.3

66.7

MHz

f MAX

Maximum clock frequency

Note (6)

111.1

100.0

71.4

MHz

EPM5128A-12

EPM5128A-15

EPM5128A-20

Min

111.1

Symbol

83.3

Note (l)

Parameter

Conditions

Min

Max

ns
15

66.7
12

Minimum array clock period

Internal Timing Parameters

Max

ns
MHz

Max

Unit

tIN

Input pad and buffer delay

2.5

tlO
t EXP

I/O input pad and buffer delay

2.5

Expander array delay

tLAD
t LAC

Logic array delay

Logic control array delay

too
tzx

Output buffer and pad delay

ns
ns

txz

Output buffer disable delay

tsu
t LATCH

0.5

t RO

0.5

tCOMB
tH

Combinatorial delay

tiC

Array clock delay

tiCS
tFD

Global clock delay

Feedback delay

0.5

tpRE

tCLR
t p1A

Prog. Interconnect Array delay

= 35 pF

Output buffer enable delay

I Altera Corporation

= 5 pF

0.5

1
7

ns
ns

Page 191

EPM5128A EPLD

Preliminary Information

Data Sheet I

Notes to tables:
(1)

(2)
(3)
(4)

(5)
(6)
(7)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in parentheses are for military- and industrial-temperature-range versions.
Typical values are for TA == 25° C and Vee == 5 V.
Operating conditions: Vee == 5 V ± 5%, TA == 0° C to 70° C for commercial use.
Vee == 5 V ± 10%, TA == -40° C to 85° C for industrial use.
Vee == 5 V ± 10%, Tc == -55° C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 0° C.
The fMAX values represent the maximum frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Product Grade

Availability
Consult factory

Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

MIL-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:
(1)

Page 192

Altera Corporation

EPM5130 EPLD
o

Features

o
o

o
o
o

High-density, l28-macrocell, general-purpose MAX 5000 EPLD
128 macrocells optimized for pin-intensive applications, easily
integrating over 60 TTL MSI and SSI components
High-speed multi-LAB architecture
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
High pin count for 16- or 32-bit data paths
256 shareable expander product terms (" expanders") allowing over
32 product terms in a single macrocell
20 high-speed dedicated inputs for fast latching of 16-bit functions
Fast Clock-to-output delays for bus-oriented functions
Programmable I/O architecture allowing up to 84 inputs or 64 outputs
in 100-pin packages, or up to 68 inputs or 48 outputs in 84-pin packages
Available in windowed ceramic and one-time-programmable (OTP)
packages (see Figure 22):
84-pin J-Iead chip carrier GLCC and PLCC)
100-pin pin-grid array (ceramic PGA only)
100-pin quad flat pack (CQFP and PQFP)

Figure 22. EPM5130 Package Pin-Ollt Diagrams
Package outlines not drawn to scale. See Tables 5 and 6 in this data sheet for pin-out information. Windows in ceramic
packages only.
'"

I-~I-I-

1-1-1-

~~~~~~~~~~~~~~~~~~~~~
liD
110
110
110
110
110
1/0
GND
GND
1/0
1/0

vee
vee
1/0

110
1/0
1/0
1/0
1/0
1/0
110

EPM5130

9 10 11 12 13

Pin 31

84-Pin J-Lead

I Altera Corporation

1DO-Pin PGA

Pin 51

1DO-Pin QFP

Page 193

I EPM5130 EPLD

Data Sheet I

General
Description

The Altera EPM5130 EPLD is a user-configurable, high-performance
MAX 5000 EPLD optimized for pin-intensive designs. It provides a highdensity replacement for 74-series SSI and MSI TTL and CMOS logic. A
single EPM5130 EPLD can quickly integrate multiple 20- and 24-pin lowdensity PLDs and high-pin-count subsystems, such as custom DMA
controllers. In addition, it can handle a 32-bit data path application with
enough 1/ a to allow the required control signals to be implemented.
The EPM5130 consists of 128 macro cells equally divided into 8 Logic Array
Blocks (LABs), each containing 16 macrocells and 32 expander product
terms. Expander product terms can be used and shared by all macrocells in
the device to ensure efficient use of device resources. Because the LAB is
very compact, the high speeds required by most I/O subsystems are
maintained. See Figure 23.
The EPM5130 has 20 dedicated input pins that allow high-speed input
latching of 16-bit functions. One of these inputs can be configured as a
global Clock to provide enhanced Clock-to-output delays for bus-oriented
functions. The EPM5130 also has 64 I/O pins, 8 in each LAB, that can be
configured for input, output, or bidirectional operation. Dual feedback on
the 1/ a pins provides the most efficient use of device pin resources.

Page 194

Altera Corporation

EPM5130 EPLD

Data Sheet

Figure 23. EPM5130 Block Diagram
Numbers without parentheses are for J-/ead packages; numbers in parentheses are for PGA packages; numbers in
brackets are for OFP packages.
6 (C7)

"c:::; INPUT [36] (N4) 59

[1] INPUT/CLK

(A10) [78]

INPUT

INPUT [37] (M5) 60

(B9)

[79]

INPUT

INPUT [38] (N5) 61

1 (A9)

[80]

INPUT ~

14 (A8)

[83J

INPUT

INPUT [42J (M7) 65

5 (B7)

[84]

INPUT

INPUT [43] (L7) 66

7 (A7)

[2]

INPUT

INPUT [44] (N7) 67

(C6)

[5]

INPUT

INPUT [47] (L8) 70

1 (A5)

[6]

INPUT~

22 (B5)

[7]

INPUT~

LAB A
(B13) [8]
(C12) [9]
3 (A13) [10]
4 (B12) [11]
5 (A12) [12]
(B11) [13]
(A11) [NC]
8 (B10) [NC]

24 (B4) [15]
25 (A3) [16]
26 (A2) [17]
27 (B3) [18]
28 (A1) [21]
29 (B2) [NC]
30 (B1) [NC]

•

~
~

MACROCELL4

MACROCELL 7

~
7<:

""'"

MACROCELL 119
MACROCELL 118

MACROCELL6

1...011........

MACROCELL 113
MACROCELLS

•t

•

MACROCELL 19

MACROCELL 103
MACROCELL 102

,..

33 (02) [26]
34 (01) [27J
[28]

36 (E1) [29]
39 (F1)

[NC]

40 (G2) [NC]

~
~
~
~
~
~

"'"

45 (H3) [32]
46 (J1)

[33]

MACROCELL 35

47 (J2)

[34]

48 (K1) [35]
49 (K2) [NC]
50 (L1)

Altera Corporation

[NC]

"'JIll"

MACROCELL 37

MACROCELL98

J+-

•t

MACROCELL 87
MACROCELL 86
MACROCELL85

.......

MACROCELL 84

f---+

MACROCELL 83
MACROCELL 82

MACROCELLS

•t

•

MACROCELL 51

MACROCELL 53
MACROCELL 54
MACROCELL 55

(E13) 96

[74]

(F11) 95

[73]

(G13) 92

[72J

(G11) 91

~
~

;;;;;;:

~
~

r-~

1-;:;

[NCJ (G12) 90
[NC] (H13) 89
[71]

(J13) 86

[70]

(J12) 85

[69]

(K13) 84

[68]

(K12) 83

[67]

(L13) 82

[64J

(L12) 81

~
7<

~
~
~

~7<

"'"

[NC] (M13) 80
[NC] (M12) 79
[63]

(N13) 78

[60J

(M11) 77

[59]

(N12) 76

[58]

(N11) 75

[57]

(M10) 74

[56]

(N10) 73

89 to 96
LABE

MACROCELL 72

MACROCELL 71

MACROCELL 50

MACROCELL 52

""'"

(E12) 97

[75J

LAB F

MACROCELL 88

MACROCELL81

7<:

[76J

105 to 112

MACROCELL 40

MACROCELL 49

"'"

MACROCELL 36

MACROCELL 39

~
~
~

[NC] (012) 99

[77] (013) 98

MACROCELLS

MACROCELL 34

MACROCELL 38

MACROCELL 99

MACROCELL 97

Programmable
Interconnect
Array
(PIA)

~
;;;;:
;;;;:
~
~
~
~

MACROCELL 100

f---+

I+-

MACROCELL 33

41 to 48

42 (G1) [31]

MACROCELL 24

LAB 0
41 (G3) [30]

MACROCELL 101

....-

MACROCELL 23

[NC] (C13) 100

LABG

MACROCELL 104

MACROCELL 21
MACROCELL 22

121 to 128

MACROCELL 20

25 to 32

MACROCELL 115
MACROCELL 114

MACROCELL 18

LABC
31 (C2) [22]

L.....a...

MACROCELL 117
MACROCELL 116

MACROCELLS

32 (C1) [25]

I+-

MACROCELL8

MACROCELL 17

LABH

MACROCELL 120

MACROCELL5

~
;;;;;;:
;;;;;;:
~
~
~

Global Clock

MACROCELL3

INPUT [48] (N9) 71
INPUT [49] (M9) 72

•~

Dedicated Inputs

MACROCELL2

9to 16

23 (A4) [14]

MACROCELL 1

LABB

35 (E2)

INPUT [41] (N6) 64

MACROCELL 70

L..........
~

I+~

MACROCELL 69
MACROCELL 68
MACROCELL67
MACROCELL 66

MACROCELL 56

MACROCELL 65

MACROCELLS

57 to 64

73 to 80

~
~

;;;;:
~
~

[NC] (M4)

[NC] (N3)

[55]

(M3)

[54]

(N2)

[53]

(M2)

[52]

(N1)

[51]

(L2)

[50]

(M1)

Page 195

I EPM5130 EPLD

Data Sheet

Figure 24 shows the output drive characteristics of EPM5130 1/ a pins and
typical supply current (Icd versus frequency for the EPM5130.

Figure 24. EPM5130 Maximum Output Drive Characteristics & Icc vs. Frequency
500
100

ci.
~
~

400
80

ci.
~

S
1:
~

~ 300

Vee = 5.0 V
Room Temp.

S
0)

S
a.
S

100

V0 Output Voltage (V)

200

..2

Vee = 5.0 V
Room Temp.

Page 196

100 Hz

1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 50 MHz

Maximum Frequency

Altera Corporation

I Data Sheet

EPM5130 EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

500

lOUT

DC output current, per pin

Power dissipation

-25

TSTG

Storage temperature

No bias

T AMB

Ambient temperature

Under bias, Note (2)

Junction temperature

Under bias, Note (2)

2500

-65

150

°C

-65 [-55]

135 [125]

°C

150 [175]

°C

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

4.75 (4.5) 5.25 (5.5)

Note (3)

vee

Supply voltage

Input voltage

0
0

Output voltage

Operating temperature

For commercial use

Operating temperature

Case temperature

Input rise time

Input fall time

DC Operating Conditions
Symbol

Vee

°C

For industrial use

-40

°C

For military use

-55

125

°C

100

Max

Unit

2.0 [2.2]

Vee + 0.3

-0.3

0.8

Notes (4), (5)

Parameter

Conditions
Note (2)

Min

Typ

V IH
V IL

High-level input voltage

V OH

High-level TTL output voltage

10H = -4 mA DC

VOL

Low-level output voltage

10L = 8 mA DC

Input leakage current

VI =V ee orGND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

!-LA

lee1

Vee supply current (standby)

V I = Vee or GND, Notes (3), (6)

175

250 (325)

lee3

V ce supply current (active)

V I = V cc or GND, No load,

180

275 (375)

Min

Low-level input voltage

2.4

0.45

!-LA

f = 1.0 MHz,Notes (3), (6)

Capacitance
Symbol

Max

Unit

CIN

Input capacitance

Parameter

V I N = 0 V, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

I Altera Corporation

Conditions

Page 197

EPM5130 EPLD

Data Sheet

AC Operating Conditions

Note (5)

External Timing Parameters
Symbol

EPM5130-1

Parameter

Conditions

EPM5130-2

EPM5130

Min Max Min Max Min Max Unit
25

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

C1 == 35 pF

C1 = 35 pF

12.5

Global clock low time

12.5

Array clock setup time

tAH
t AC01

Array clock hold time

Array clock to output delay

C1 = 35 pF

tACH
t ACL

Array clock high time

Note (7)

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (6)

f ACNT

Max. internal array clock frequency

Note (6)

33.3

MHz

f MAX

Maximum clock frequency

Note (8)

62.5

MHz

Array clock low time

Internal Timing Parameters

25
14

Note (9)

EPM5130-1

Parameter

Conditions

33.3
25

EPM5130-2

ns
ns

25
40

ns
35

Minimum array clock period

Symbol

ns
MHz

EPM5130

Min Max Min Max Min Max Unit

tIN
t/O
t EXP

Input pad and buffer delay

I/O input pad and buffer delay

Expander array delay

tLAD
t LAC

Logic array delay

Logic control array delay

Output buffer and pad delay
Output buffer enable delay

txz

Output buffer disable delay

tsu

tLATCH
tRD

Flow-through latch delay

tCOMB
tH

Combinatorial delay

tIC

Array clock delay

tICS
tFD

Global clock delay

Feedback delay

tpRE

tCLR
tplA

Prog. Interconnect Array delay

= 35 pF

too
tzx

Page 198

= 5 pF

3
4

ns
ns

Altera Corporation

Data Sheet

EPM5130 EPLD I

Notes to tables:
(1)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in brackets are for MIL-STD-883-compliant versions only.
Numbers in parentheses are for military- and industrial-temperature-range versions,
as well as for MIL-STD-883-compliant versions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee =5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee = 5 V ± 10%, Te = -55° C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 0° C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and tACL parameters must be swapped.
The fMAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)

Product
Availability

Availability

Product Grade
Commercial Temp.

(0° C to 70° C)

EPM5130-1, EPM5130-2, EPM5130

Industrial Temp.

(-40° C to 85° C)

EPM5130

Military Temp.

(-55° C to 125° C)

EPM5130

M IL-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:
(1)

Pin-Out
Information

Tables 5 and 6 provide pin-out information for the EPM5130.
Table 5. fPM5130 Dedicated Pin-Outs

Dedicated Pin

100-Pin PGA

100-Pin QFP

INPUT

2,5,6,7,36,37,
38, 41 , 42, 43, 44,
47, 48, 49, 78, 79,
80,83,84

AS, A7, A8, A9,
A10, B5, B7, B9,
C6, L7, L8, M5, M7,
M9, N4, N5, N6, N7
N9

9, 10, 11, 14, 15,
16, 17, 20, 21, 22,
59, 60, 61, 64, 65,
66,67,70,71,72

GND

19, 20, 39, 40, 61,
62,81,82

B8, C8, F2, F3,
H11, H12, L6, M6

12, 13,37,38,62,
63,87,88

vee

3,4,23,24,45,46, A6, B6, F12, F13,
H1, H2, M8, N8
65,66

18, 19, 43, 44, 68,
69,93,94

INPUT/eLK

Altera Corporation

84-Pin J-Lead

Page 199

I EPM5130 EPLD

Data Sheet

Table 6. EPM5130 I/O Pin-Outs (Part 1 of 2)

I Page 200

LAB 84-Pin 1DO-Pin 1DO-Pin
J-Lead PGA
QFP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

8
9
10
11
12
13
-

B13
C12
A13
B12
A12
B11
A11
B10

1
2
3
4
5
6
7
8

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

22
25
26
27
28
29
-

C2
C1
D2
D1
E2
E1
F1
G2

31
32
33
34
35
36
39
40

84-Pin 1DO-Pin 1DO-Pin
J-Lead PGA
QFP

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B

14
15
16
17
18
21

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

A4
B4
A3
A2
B3
A1
B2
B1

23
24
25
26
27
28
29
30

30
31
32
33
34
35
-

G3
G1
H3
J1
J2
K1
K2
L1

41
42
45
46
47
48
49
50

Altera Corporation I

I Data Sheet

EPM5130 EPLDj

Table 6. EPM5130 I/O Pin-Outs (Part 2 of 2)

LAB

65
66
67
68
69
70
71

E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E

73
74
75
76
77

78
79
80
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

I Altera Corporation

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

84-Pin 1DO-Pin 1DO-Pin
J-Lead PGA
QFP
50
51
52
53
54
55
-

M1
L2
N1
M2
N2
M3
N3
M4

51
52
53
54
55
56
57
58

64
67
68
69
70
71
-

L12
L13
K12
K13
J12
J13
H13
G12

81
82
83
84
85
86
89
90

LAB

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

84-Pin 1DO-Pin 1DO-Pin
J-Lead PGA
QFP
56
57
58
59
60
63
-

N10
M10
N11
N12
M11
N13
M12
M13

G11
G13
F11
E13
E12
013
012
C13

91
92
95
96
97
98
99
100

73
74
75
76
77

73
74
75
76
77
78
79
80

Page 201 I

Notes:

EPM5192 EPLD!
Features

High-density, 192 macro cell, general-purpose MAX 5000 EPLD, easily
integrating complete logic boards into a single package
High-speed multi-LAB architecture
tpD as fast as 25 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
384 shareable expander product terms (" expanders") offering flexibility
for register and combinatorial logic expansion
Programmable 110 architecture allowing up to 72 inputs or 64 outputs,
and I/O tri-state buffers that facilitate connections to system buses
A vailable in 84-pin windowed ceramic and plastic one-timeprogrammable (OTP) packages (see Figure 25):
J-Iead chip carrier aLCC and PLCC)
Pin-grid array (ceramic PGA only)

o
o
o

Figure 25. EPM5192 Package
Pin-Out Diagrams
Package outlines not
drawn to scale. See
Table 7 and 8 in this
data sheet for pin-out
information. Windows in
ceramic packages only.

()

I-PI-I-

0=>=>=>=>00

~~~~~~~~~~~~~aa~~~~~~
1/0
1/0

110
1/0
1/0
1/0
GND
GND
1/0
1/0
1/0
1/0

vee
1/0
1/0
1/0
I/O
1/0

110

o
EPM5192

1/0

110

1/0
1/0
1/0
1/0
1/0
1/0

110
1/0

vee
1/0
1/0
1/0
1/0
GND
GND
1/0
1/0
1/0
1/0
1/0
1/0

84-Pin J-Lead

General
Description

Altera Corporation

10 11

84-Pin PGA

The Altera EPM5192 is a user-configurable, high-performance MAX 5000
EPLD that provides a high-density replacement for 74-series SSI and MSI
TTL and CMOS logic. It can replace over 100 TTL SSI and MSI components
and integrate the logic of over 20 22V10 devices. The EPM5192 consists of
192 macrocells equally divided into 12 Logic Array Blocks (LABs), each
with 16 macro cells and 32 expanders. These compact LABs maintain high
performance and efficient use of device resources. The EPM5192 has 8
dedicated input pins, one of which can be used as a global Clock. It can mix
global and array clocking, facilitating easy integration of multiple
subsystems. The EPM5192 contains 641/0 pins that can be configured for
input, output, or bidirectional operation, providing an interface to highspeed, bus-oriented applications. See Figure 26.
Page 2031

Data Sheet

EPM5192 EPLD

Figure 26. EPM5192 Block Diagram
Numbers without parentheses are for J-/ead packages. Numbers in parentheses are for PGA packages. Numbers in
brackets are for EPM5192A OFP packages.

c::

(A6) [91] INPUT/CLK ~
INPUT.:::'

41 (K6) [39]

INPUT ~

c::

42 (J6) [40]

INPUT ~

~ INPUT [41] (J7) 43

(M) [96]
6

(B4) [97]

(A3) [98]

(A2) [99]

(B3) [100]

10 (A1) [1]
11 (B2)[5]

7"':

13 (B1) [7]
14 (C1) [8]
15 (02) [9]

MACROCELL 183

MACROCELL3

MACROCELL 182

MACROCELL6

MACROCELL4

~
7"':

MACROCELL5

~
~

--.

MACROCELL 181

f+......
..

"""'-

MACROCELL 7

20 (F2) [14]
21 (F3) [15]

~
~
~

"'"

MACROCELLS

9TO 16

185TO 192

MACROCELL 19
MACROCELL 20

..-

r----.

23 (G1)[17]
25 (F1) [20]
26 (H1)[21]

~
~
~

"'"

MACROCELL 35
MACROCELL 36
MACROCELLS

27 (H2) [22]
28 (J1) [23]
29 (K1) [24]
30 (J2) [25]

~
7"
~

"""

MACROCELL 52
MACROCELLS

..-

32 (K2) [27]
33 (K3) [31]
34 (L2) [32]
35 (L3) [33]
36 (K4) [34]
37 (L4) [35]
38 (J5) [36]

7"':

.....
..

Programmable
Interconnect
Array
(PIA)

MACROCELL 67
MACROCELLS

MACROCELL 146
MACROCELL 145
MACROCELLS

...

....

r----.

MACROCELL 131
MACROCELL 130
MACROCELL 129

[76] (A11) 73

""
~
~

[75] (C10) 72
[74] (B11) 71
[73] (C11) 70
[72] (010) 69

"""

[67] (E11) 65
[66] (F11) 64

~
~

[65] (F9)

[64] (G9) 62
[61] (F10) 59
[60] (H11) 58

LAB H

MACROCELL 116
MACROCELL 115
~

..-

MACROCELL 114

MACROCELL 113
MACROCELLS

~
~

"""

[59] (H10) 57
[58] (J11) 56
[57] (K11) 55
[56] (J10) 54

117T0128

t t

LABG

MACROCELL 104

~
~

MACROCELL 85
MACROCELL 87

MACROCELL 98

:::..:

MACROCELL 88

MACROCELL 97

MACROCELLS

89 TO 96

105 TO 112

MACROCELL 82

MACROCELL 103

MACROCELL 83

MACROCELL 102

MACROCELL 86

[71] (011) 68
[70] (E9) 67

133 TO 144

•

MACROCELL 84

""
~

MACROCELLS

~
~

[81] (B9) 75

[77] (B10) 74

LAB I

MACROCELL 132

MACROCELL 81

[83] (A9) 77
[82] (A10) 76

LABJ

MACROCELL 68

::".:

[84] (B8) 78

149T0160

MACROCELL 66

69 TO 80

31 (L1) [26]

f+-

MACROCELL 65

LAB F

~
~
~
~

[85] (A8) 79

MACROCELLS

MACROCELL 147

MACROCELL 51

MACROCELL 161

MACROCELL 148

MACROCELL 50

53 TO 64

MACROCELL 162

MACROCELL 49

LAB E

[86] (B6) 80

165 TO 176

MACROCELL 34

""
~

LAB K

MACROCELL 163

....

MACROCELL 33

;><;

MACROCELL 164

37 TO 48

22 (G3) [16]

MACROCELL 178
MACROCELL 177

MACROCELL 18

LAB 0

MACROCELL 179

MACROCELLS

21 TO 32

;><;

MACROCELL 180

MACROCELL8

MACROCELL 17

LABC
17 (E3) [11]

LAB L

MACROCELL 184

MACROCELL2

MACROCELLS

16 (01)[10]

Dedicated Inputs
Global Clock

INPUT [42] (L7) 44

MACROCELL 1

LABB
12 (C2) [6]

INPUT [89] (C7) 83

~. -,

LABA
(C5) [95]

Page 204

INPUT [90] (C6) 84

(A5) [92]

-+
....
.......

*..
r--"""'"

MACROCELL 101
MACROCELL 100
MACROCELL 99

~
7"
~
~
~
~

"""

[55] (K10) 53
[51] (L11) 52
[50] (K9) 51
[49] (L10) 50
[48] (L9)

[47] (K8) 48
[46] (L8)

[45] (L6)

Altera Corporation

I Data Sheet

EPM5192 EPLD I

Figure 27 shows the output drive characteristics of EPM5192 I/O pins and
typical supply current (Icd versus frequency for the EPM5192.

Figure 27. EPM5192 Maximum Output Drive Characteristics & Icc vs. Frequency
500
100

c.i.
~

400
80

c.i.
~

S
C

<'
S

Vee = 5.0 V
Room Temp.

::;

"i5

200

()

..9

Vee = 5.0 V
Room Temp.

"5
0..
"5

300

100

Va Output Voltage (V)

I Altera Corporation

1 kHz

10 kHz

100 kHz 1 MHz 10 MHz 50 MHz

Maximum Frequency

Page 205

I EPM5192 EPLD

Data Sheet I

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.
Conditions

Parameter

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

500

lOUT

DC output current, per pin

Power dissipation

-25

TSTG

Storage temperature

No bias

T AMB

Ambient temperature

Under bias, Note (2)

Junction temperature

Under bias

2500

-65

150

°C

-65 [-55]

135 [125]

°C

150

°C

Max

Unit

Recommended Operating Conditions
Symbol

Conditions

Parameter

Min

4.75 (5.5) 5.25 (5.5)

Note (3)

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

TA
TA

Operating temperature

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

100

Input fall time

100

DC Operating Conditions
Symbol

For commercial use

Notes (4), (5)

Parameter

Conditions
Note (2)

Min

Max

Unit

Vee + 0.3

-0.3

0.8

High-level input voltage

V IL

Low-level input voltage

V OH

High-level TTL output voltage

10H = -4 mA DC

VOL

LOW-level output voltage

10L = 8 mA DC

Input leakage current

VI =V ee orGND

-10

loz

Tri-state output off-state current

lee1

Vo =V ee orGND
V I = Vee or GND, Notes (3), (6)

-40

Vee supply current (standby)

lee3

Vee supply current (active)

V I = Vee or GND, No load,

Typ

2.0 [2.2]

V IH

2.4

0.45

/lA

250

360 (435)

270

380 (480)

Min

Max

Unit

f = 1.0 MHz, Notes (3), (6)

Capacitance
Symbol

Parameter

Conditions
= 1.0 MHz
= 0 V, f = 1.0 MHz

CIN

Input capacitance

V 1N = 0 v, f

COUT

Output capacitance

V OUT

I Page 206

Altera Corporation

Data Sheet

EPM5192 EPLD I

AC Operating Conditions

Note (5)

External Timing Parameters
Symbol

EPM5192-1

Parameter

Conditions

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

tsu

Global clock setup time

EPM5192-2

EPM5192

Min Max Min Max Min Max Unit

C1 = 35 pF

55
25

ns
ns
ns

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

12.5

tCl
t A5U

Global clock low time

12.5

Array clock setup time

Array clock hold time

tAH
t AC01

C1 = 35 pF

tACH
t ACl

Array clock high time

Note (7)

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (6)

f ACNT

Max. internal array clock frequency

Note (6)

33.3

MHz

f MAX

Maximum clock frequency

Note (8)

62.5

MHz

20
40

Parameter

EPM5192-1

Conditions

14
25

Note (9)

Minimum array clock period

Symbol

C1 = 35 pF

Internal Timing Parameters

Array clock to output delay

Array clock low time

ns
20

ns
30

33.3
25

EPM5192-2

ns
MHz

EPM5192

Min Max Min Max Min Max Unit

tIN

Input pad and buffer delay

tJO
t EXP

liD input pad and buffer delay

Expander array delay

t LAO

Logic array delay

t LAC

Logic control array delay

too

Output buffer and pad delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu
t LATCH

t RO

tCOMB
tH

Combinatorial delay

tiC

Array clock delay

tiCS
tpo

C1 = 35 pF

C1 = 5 pF

13
12

ns
ns

Global clock delay

Feedback delay

tpRE

tCLR
tplA

Altera Corporation

Page 2071

I EPM5192 EPLD

Data Sheet
Notes to tables:

(1)
(2)
(3)
(4)
(5)

(6)
(7)
(8)
(9)

Product
Availability

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in brackets are for MIL-STD-883-compliant versions only.
Numbers in parentheses are for military- and industrial-temperature-range versions,
as well as for MIL-STD-883-compliant versions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee =5 V ± 5%, TA =0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40 0 C to 85 0 C for industrial use.
Vee = 5 V ± 10%, Te = -55 0 C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 00 C.
This parameter is measured with a positive-edge-triggered Clock at the register. For
negative-edge clocking, the tACH and t ACL parameters must be swapped.
The f MAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Availability

Product Grade
Commercial Temp.

(0 C to 70° C)

EPM5192-1, EPM5192-2, EPM5192

Industrial Temp.

(-40 0 C to 85° C)

EPM5192

Military Temp.

(-55° C to 125° C)

EPM5192

MIL-STD-883-Compliant

Note (1)

See Military Products in this data book.

Note:

(1)

Pin-Out
Information

Tables 7 and 8 provide pin-out information for the EPM5192.
Table 7. EPM5192 Dedicated Pin-Outs

Dedicated Pin
INPUT/eLK
INPUT
GND

vee

I Page 208

84-Pin J-Lead

84-Pin PGA

1
A6
A5,K6,J6,J7, L7,C7,C6
2,41,42,43,44,83,84
18,19,39,40,60,61,81, A7, 87, E1, E2, G10, G11,
K5,L5
82
3,24,45,66

85, E10, G2, K7

Altera Corporation

I Data Sheet

EPM5192 EPLD

Table 8. EPM51921/0 Pin-Outs (Part 1 of 2)

LAB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

4
5
6
7
8
9
10
11

C5
A4
B4
A3
A2
B3
A1
B2

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

0
0
0

22
23
25
26

G3
G1
F1
H1

0
0
0
0
0
0
0
0
0
0
0
0
0

I Altera Corporation

84-Pin 84-Pin
J-Lead PGA

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B

12
13
14
15

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E

84-Pin 84-Pin
J-Lead PGA
C2
B1
C1
02

27
28
29
30

H2
J1
K1
J2

LAB

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

16
17
20
21

01
E3
F2
F3

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

F
F
F

84-Pin 84-Pin
J-Lead PGA

F
F
F
F

31
32
33
34
35
36
37
38

L1
K2
K3
L2
L3
K4
L4
J5

F
F

F
F
F
F

Page 209 I

I EPM5192 EPLD

Data Sheet

Table 8. EPM51921/0 Pin-Outs (Part 2 of 2)

LAB

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G

46
47
48
49
50
51
52
53

L6
L8
K8
L9
L10
K9
L11
K10

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J

64
65
67
68

F11
E11
E9
011

I Page210

84-Pin 84-Pin
J-Lead PGA

LAB

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

54
55
56
57

J10
K11
J11
H10

161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

84-Pin 84-Pin
J-Lead PGA

69
70
71
72

010
C11
B11
C10

LAB

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

84-Pin 84-Pin
J-Lead PGA
58
59
62
63

H11
F10
G9
F9

I
I

I
I
I
I

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

73
74
75
76
77
78
79
80

A11
B10
B9
A10
A9
B8
A8
B6

Altera Corporation I

EPM5192A EPLD
o

Features

o
o
Preliminary
Information

o
o

High-performance, second-generation MAX 5000 EPLD developed
on an advanced 0.65-micron CMOS EPROM process
High-speed upgrade for existing EPM5l92 designs
High-speed multi-LAB architecture
tpD as fast as 15 ns
Counter frequencies up to 83.3 MHz
384 shareable expander product terms (" expanders") offering flexibility
for register and combinatorial logic expansion
Programmable II 0 architecture allowing up to 72 inputs or 64 outputs
High-density replacement for 74-series SSI and MSI TTL and CMOS
logic
Available in windowed ceramic and plastic one-time-programmable
(OTP) packages (see Figure 28):
84-pin J-lead chip carrier (JLCC and PLCC)
84-pin pin-grid array (ceramic PCA only)
100-pin quad flat pack (plastic PQFP only)

Figure 28. EPM519ZA Package Pin-Out Diagrams
Package outlines not drawn to scale. See Tables 9 and 10 in this data sheet for pin-out information. Windows in ceramic
packages only.
'"0
I-PI-I-

o::l::l::>::Joo

~~~~~~~~~~~~~~ffi~~~~~~
74
73

I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O

vee
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

EPM5192A

~~~~~~~~~~~~~~~~~g~~~

~~~~~~~~~~~~~~~~~~~~~

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

vee
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O

0@@@@@@@@@@
K@@@@@@@@@@@
J @@
@@@
@@
H @@
@@
G@@@ EPM5192A @@@
@@@ Bottom @@@
View
@@@
@@@
o @@
@@
C @@.
@@@
@@
s@@0@0@0@00@
A 0@0@0@0@000
L

EPM5192A

10 11

Pin3!

84-Pin J-Lead

General
Description
I

Altera Corporation

84-Pin PGA

Pin5!

100-Pin QFP

The Altera EPM5l92A EPLD is a user-configurable, high-performance
MAX 5000 EPLD that is pin-, function- and programming-file-compatible
with the EPM5l92. For a description of the device architecture, see
"EPM5l92 EPLD" in this data sheet.
Page 211

I EPM5192A EPLD

Preliminary Information

Absolute Maximum Ratings
Symbol

Data Sheet

See Operating Requirements for Altera Devices in this data book.

Parameter

Min

Conditions

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

500

25
2500

I MAX

DC Vee or GND current

lOUT

DC output current, per pin

Power dissipation

-25

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit

Recommended Operating Conditions
Symbol
vee

Parameter
Supply voltage

Min

Conditions

4.75 (4.5) 5.25 (5.5)

Note (2)

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

100

Input fall time

100

DC Operating Conditions
Symbol

Notes (3), (4)
Max

Unit

V IH

High-level input voltage

Parameter

2.0

Vee + 0.3

V IL

Low-level input voltage

0.8

V OH

High-level TIL output voltage

-0.3
2.4

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

lee3

Vee supply current (active)

Conditions

= -4 mA DC
= 8 mA DC
V I =Vee or GND
V 0 =Vee or GND
V I =Vee or GND, Note (5)
V I =Vee or GND, No load,
f = 1.0 MHz, Note (5)
10H

Min

Typ

V
V

0.45
10

10L

-10

V
/lA

/lA

180

225

200

245

Min

Max

Unit

-40

Capacitance
Symbol

Parameter

Conditions

= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT

I Page 212

Altera Corporation

Data Sheet

AC Operating Conditions

Note (4)

External Timing Parameters
Symbol

EPM5192A-15 EPM5192A-20

Parameter

Conditions
=

Min

Max

Min

Max

Unit

t pD1

Input to non-registered output

tpD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Global clock low time

ns
ns

35 pF

0
C1

0
7

35 pF

ns
ns
ns

Array clock setup time

tAH
t AC01

Array clock hold time

tACH
t ACl

Array clock high time

Array clock low time

Array clock to output delay

35 pF

ns
16

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (5)

f ACNT

Max. internal array clock frequency

Note (5)

83.3

66.7

MHz

f MAX

Maximum clock frequency

Note (6)

100.0

71.4

MHz

83.3

Minimum array clock period

Internal Timing Parameters
Symbol

EPM5192A

Preliminary Information

15
66.7

Note (7)

Parameter

ns
MHz

EPM5192A-15 EPM5192A-20

Max

Unit

tiN

Input pad and buffer delay

tlO
t ExP

1/0 input pad and buffer delay

Expander array delay

tLAD
t LAC
too
tzx

Logic array delay

Conditions

Min

Logic control array delay
Output buffer and pad delay

C1 = 35 pF

Output buffer enable delay

Max

Min

txz

Output buffer disable delay

tsu
t LATCH

Flow-through latch delay

tRD
t COM8

Combinatorial delay

C1 = 5 pF
2

tiC

Array clock delay

tiCS

Global clock delay

tFD
tpRE

Feedback delay

tCLR
t plA

Prog. Interconnect Array delay

Altera Corporation

ns
ns

Page 213

I EPM5192A EPLD

Preliminary Information

Data Sheet

Notes to tables:
(1)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
Numbers in parentheses are for military- and industrial-temperature-range versions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee =5 V ± 10%, Te =-55° C to 125° C for military use.
Measured with a 16-bit counter programmed into each LAB. Icc measured at 0° C.
The f MAX values represent the maximum frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

(2)
(3)
(4)

(5)
(6)
(7)

Product
Ava ilabil ity

Availability

Product Grade
Commercial Temp.
Industrial Temp.
Military Temp.
MIL-STD-883-Compliant

(0° C to 70° C)
(-40° C to 85° C)
(-55° C to 125° C)
Note (1)

Consult factory
Consult factory
Consult factory
See Military Products in this data book.

Note:
(1)

Pin-Out
Information

Tables 9 and 10 provide pin-out information for the EPM5192A.
Table 9. EPM5192A Dedicated Pin-Outs

Dedicated Pin
INPUT/eLK

I Page 214

84-Pin J-Lead
1

84-Pin PGA
A6

100-Pin QFP
91

INPUT

2,41,42,43,44,
83,84

A5, K6, J6, J7, L7,
C7, C6

39,40,41,42

GND

18, 19, 39, 40, 60,
61,81,82

A7, 87, E1, E2,
G10, G11, K5, L5

2,3,4,12,13,28,
29, 30, 37, 38, 52,
53, 54, 62, 63, 78,
79,80,87,88

vee

3,24,45,66

85, E10, G2, K7

18, 44, 68, 69, 93,
94

Altera Corporation

Preliminary Information

Data Sheet

EPM5192A I

Table 10. EPM5192A I/O Pin-Outs (Part 1 of 3)

I Altera Corporation

LAB 84-Pin 84-Pin 1~O-Pin
J-Lead PGA
QFP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

4
5
6
7
8
9
10
11

C5
A4
84
A3
A2
83
A1
82

95
96
97
98
99
100
1
5

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

16
17
20
21

01
E3
F2
F3

10
11
14
15

84-Pin 84-Pin 1~O-Pin
J-Lead PGA
QFP

LAB

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

12
13
14
15
-

C2
81
C1
02

6
7
8
9

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

22
23
25
26

G3
G1
F1
H1

16
17
20
21

Page 215 ]

Preliminary Information

EPM5192A EPLD

Data Sheet I

Table 10. EPM5192A I/O Pin-Outs (Part 2 of 3)

MC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

I Page 216

LAB 84-Pin 84-Pin 100-Pin
J-Lead PGA
QFP
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E

27
28
29
30

H2
J1
K1
J2

22
23
24
25

46
47
48
49
50
51
52
53

L6
L8
K8
L9
L10
K9
L11
K10

45
46
47
48
49
50
51
55

G
G
G
G
G
G
G

LAB 84-Pin 84-Pin 100-Pin
J-Lead PGA
QFP

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

31
32
33
34
35
36
37
38
-

L1
K2
K3
L2
L3
K4
L4
J5

26
27
31
32
33
34
35
36

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

54
55
56
57
-

J10
K11
J11
H10

56
57
58
59

Altera Corporation I

I Data Sheet

Preliminary Information

EPM5192A

Table 10. EPM5192A I/O Pin-Outs (Part 3 of 3)

MC
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

I Altera Corporation

LAB 84-Pin 84-Pin 100-Pin
J-Lead PGA
QFP

58
59
62
63

H11
F10
G9
F9

60
61
64
65

69
70
71
72

D10
C11
811
C10

72
73
74
75

I
I
I

K
K
K

LAB 84-Pin 84-Pin 100-Pin
J-Lead PGA
QFP

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J

64
65
67
68

F11
E11
E9
D11

66
67
70
71

177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

L
L
L
L

73
74
75
76

A11
810
89
A10
A9
88
A8
86

81
82
83
84
85
86

78
79
80
-

L
L
L
L
L
L

76
77

Page 217 I

Notes:

EPS464 EPLD
Features

High-performance, globally-routed, general-purpose EPLD
Combinatorial speeds as fast as 20 ns
Counter frequencies up to 67 MHz
Pipelined data rates up to 71 MHz
64 enhanced macrocells and 256 shared expander product terms
("expanders"); ideal for custom waveform generation and state
machine designs
Programmable registers providing D, T, JK, and SR flipflops with
individual Clear, Preset, and Clock controls
Powerful macrocell architecture optimized for:
Modulo-n binary and Gray-code counters
Complex state machines
Multiple product-term JK flipflops for waveform generation
Phase comparator and Clock oscillator functions
Noise-resistant input buffers with 250-mV hysteresis and quiet output
buffers for noise immunity and reliable operation
Programmable Security Bit for total protection of proprietary designs
Programmable II 0 support for up to 36 inputs or 32 outputs
Available in 44-pin windowed ceramic and one-time-programmable
(OTP) packages (see Figure 29):
J-Iead chip carrier (JLCC and PLCC)
Quad flat pack (plastic PQFP only)

o
o

Figure 29. EPS464 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Table 11 in this data sheet for aFP pin-out
information. Windows in ceramic packages only.
f- ff-::l::l

=> a..

0...::>

~'C ~a: w
~ 52~

() w...J cr....J

~~~~gg~ga~~
6

5 4

Pin 1

1 4443424140

1/0

vee
1/0
1/0

I/O
I/O

1/0

GND

EPS464

1819202122232425262728

~~~~~8~~~~~
(!)

44-Pin J-Lead

I Altera Corporation

Pin 23

Pin 12

44-Pin QFP

Page 219

I EPS464 EPLD

General
Description

Data Sheet

The EPS464 is an general-purpose EPLD based on the MAX 5000
architecture. It combines innovative architecture and an advanced
fabrication process to offer optimum performance and flexibility. Fabricated
on a 0.8-micron CMOS EPROM technology, the EPS464 has 64 enhanced
macrocells and 256 shared expanders, all of which are globally routed to
implement complex designs.
The EPS464 provides an integrated solution for a wide range of applications.
Because the EPS464 architecture supports 100% TTL emulation, it can
integrate multiple SSI, MSI, and LSI logic functions into one device. It is
also ideal for synchronous timing and waveform-generation applications,
such as TV Ivideo synchronization signals (e.g., NTSC, PAL, SECAM,
HDTV), CCD timing controllers, high-performance state machines, and
memory controllers. Each output can generate customized waveforms to
meet various system requirements.
The EPS464 has 32 I/O pins that can be independently configured for
input, output, or bidirectional operation. It also has 4 dedicated input pins
that can be programmed as general-purpose inputs or as system-wide
control signals (Clock, Clear, Preset, and Output Enable) for eachmacrocell
and I/O pin. The EPS464 input pins have input protection circuitry to
prevent electrostatic discharge (ESD) damage and to reduce the possibility
of latch-up. The input pins also provide input hysteresis to prevent spurious
switching due to noisy inputs. The outputs are designed to minimize
output switching noise, offering quiet and reliable operation.
The EPS464 advanced macrocell structure can integrate complex logic
functions, with over 100 product terms available to anyone macro cell.
Each of the 64 internal flipflops can be programmed for D, T, JK, or SR
operation. JK and SR flipflops are well-suited for pattern-generation
applications, since simple set and reset operations can be used to define the
transitions of output waveforms.
The EPS464 is supported by Altera's MAX+PLUS II development system,
a single integrated package that offers schematic, text, and waveform
design entry; compilation and logic synthesis; simulation and timing
analysis; and programming. MAX+PLUS II provides EDIF, VHDL, Verilog
and other netlist interfaces for additional design entry and simulation
support from other industry-standard PC- and workstation-based CAE
tools. The system runs on 386- and 486-based PCs, Sun SPARC stations,
and HP 9000 Series 700 workstations.

I Page 220

Altera Corporation

Data Sheet

Functional
Description

EPS464 EPLD

The EPS464 is a 64-macrocell EPLD optimized for timing and waveform
synthesis applications. Thirty-two macro cells are connected to I/O pins;
the other 32 macrocells are available for buried logic and state machine
registers (see Figure 30). The high logic density and large number of
macrocells allow designers to create multiple counters inside the EPS464
and to add state machines and combinatorial logic to enhance design
integration.

Figure 30. EPS464 Block Diagram

Numbers without brackets are for J-/ead packages. Numbers in brackets are for QFP packages.
GClRn/lNPUT
GOEn/lNPUT

[39]
[40]

~~~~~~:~:T

:: :~:~

=~~~!:=i~~==========:~:::~==========:---'
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
MACROCELL 41
MACROCELL 42
MACROCELL 43
MACROCELL 44
MACROCELL 45
MACROCELL 46
MACROCELL 47
MACROCELL 48
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
MACROCELL 57
MACROCELL 58
MACROCELL 59
MACROCELL 60
MACROCELL 61
MACROCELL 62
MACROCELL 63
MACROCELL 64

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-

t!ll

Global

Bus

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-

+111

MACROCELL 1

[42]

MACROCELL 2

[43]

MACROCELL 3

[44]

MACROCELL 4

[1]

MACROCELL 5

[2]

MACROCELL 6

[3]

MACROCELL 7

[5]

MACROCELL 8

[6]

MACROCELL 9

[7]

MACROCELL 10

[8]

MACROCELL 11

[10]

MACROCELL 12

[11]

MACROCELL 13

[12]

MACROCELL 14

[13]

MACROCELL 15

[14]

MACROCELL 16

[15]

MACROCELL 17

[35]

MACROCELL 18

[34]

MACROCELL 19

[33]

MACROCELL 20

[32]

MACROCELL 21

[31]

MACROCELL 22

[30]

MACROCELL 23

[28]

MACROCELL 24

[27]

MACROCELL 25

[26]

MACROCELL 26

[25]

MACROCELL 27

[23]

MACROCELL 28

[22]

MACROCELL 29

[21]

MACROCELL 30

[20]

MACROCELL 31

[19]

MACROCELL 32

~24

[18]

All EPS464 macrocells are fed by a global bus, which supports 66-MHz
system speeds and eliminates placement-dependent interconnect delays
between device resources.
I

Altera Corporation

Page 221

I EPS464 EPLD

Data Sheet I

The EPS464 uses CMOS EPROM cells to configure all combinatorial and
sequential logic functions in the device. It is user-configurable to
accommodate a variety of independent logic blocks typically used in
waveform generation and random-logic integration applications. The
EPLDs can be erased for quick and efficient iterations during development
and debug cycles.
EPS464 architecture includes the following elements:

o Macrocells
o Expander product terms
o 1/ 0 control block
Macrocells
The EPS464 macro cell, shown in Figure 31, consists of three functional
blocks: a product-term array, a product-term select matrix, and a
programmable register.

Figure 31. EPS464 Macrocell
Global Bus

Global Clear

Global Clock

Global

Array OE
Array Preset

Programmable
Register

Array Clear

Dedicated
Inputs

Combinatorial logic is implemented in the product-term array, which
consists of five product terms. Four product terms feed the product-term
select matrix; the fifth feeds one input of an XOR gate, making it possible to
implement active-high or active-low logic. The XOR gate is also used to
build complex arithmetic logic functions and to perform De Morgan's

I Page 222

Altera Corporation

I Data Sheet

EPS464 EPLD I

inversion, which reduces the number of product terms required for a
design.
Based on the logic requirements of the design, the product-term select
matrix individually directs the macrocell's product-term resources to the
four-input OR gate, the Clock, Clear, or Preset controls on the programmable
register, the Output Enable controls on the 1/ 0 pins, or up to four expander
product terms. The product-term select matrix can also connect vee or GND
to the control resources to permanently enable or disable logic functions.
Each programmable register can be configured as a D, T, JK, or SR flipflop
and is positive-edge-triggered. Register types can be specified by the
designer or by the MAX+PLUS II software, which automatically selects the
most efficient flipflop type to implement a given logic function. The register
can also be bypassed for fast combinatorial operation.
The macrocell's register control functions (Clock, Clear, and Preset) can be
driven from product terms or from the dedicated input pins. Selection is
made on an individual basis, ensuring efficient macrocell resource
utilization. Connecting these control functions directly to the dedicated
input pins GPREn, GCLRn, and GCLK guarantees fast operation. These control
functions can also be generated with product terms to provide additional
design flexibility.

Expander Product Terms
Although most logic functions can be implemented with the product terms
available in each macrocell, some complex logic functions may require
additional product terms. Rather than using additional macrocells to supply
the needed logic resources, the EPS464 architecture uses shared expander
product terms to provide additional product terms directly to any macrocell.
These expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
The EPS464 provides up to 256 logic expanders, which are inverted product
terms that feed back into the global bus. Expanders are fed by all signals in
the EPS464. Expanders can be used and shared by all product terms in the
EPS464 to build complex logic functions, allowing the software to factor
logic expressions and combine product terms efficiently. If the expanders
are not used for combinatorial logic, they can be cross-coupled to build
additional flipflops, latches, or input registers. This flexibility allows
designers to fully use the silicon resources packed into each EPS464 device.
A small delay (tSEXP) is incurred when shared expanders are used.

I Altera Corporation

Page 223

I EPS464 EPLD

Data Sheet

I/O Control Block
The I/ 0 control block consists of a user-configurable I/ 0 control function
for each I/O pin. The EPS464 has 32 I/O pins, each of which can be
configured for input, output, or bidirectional operation. Each macrocell
that feeds an I/O pin has a tri-state buffer between the macrocell output
and the 1/ 0 pin. The EPS464 provides dual feedback, with feedback paths
before and after the tri-state buffer; if an 1/0 pin is configured as an input,
the associated macrocell is not wasted and can be used for buried logic.
The Output Enable for each tri-state buffer can be controlled by the dedicated
active-low global Output Enable input (GOEn), or by a product term within
the macrocell.
Figure 32 shows the output drive characteristics of EPS464 I/O pins and
typical supply current (Icd versus frequency for the EPS464 EPLD.

Figure 32. EPS464 Maximum Output Drive Characteristics &Icc vs. Frequency
200 , - - - - - - - - - - - - - - - - ,

150

ci.
~

«
..s

ci.
~

100

~
::J
o
"5
c..
"5

..s

Vee = 5.0 V

150

= 25° C

100

Vee =5.0V

()

Vo Output Voltage (V)

= 25° C

1 kHz

10 kHz 100 kHz 1 MHz 10 MHz 70 MHz

Maximum Frequency

Design Security

The EPS464 contains a programmable Security Bit that controls access to
the data programmed into the device. If the Security Bit is programmed, a
proprietary design implemented in the device cannot be copied or retrieved.
This feature provides a high level of design security, since programmed
data within EPROM cells is invisible. The Security Bit that controls this
function, as well as all other program data, is reset when the device is
erased.

Timing
Model

Timing in the EPS464 EPLD can be analyzed with MAX+PLUS II software,
with a variety of popular industry-standard CAE simulators and timing
analyzers, or with the timing model shown in Figure 33. The actual values
for each parameter given in the" AC Operating Conditions" table in this

I Page 224

Altera Corporation

I Data Sheet

EPS464 EPLD

data sheet. The EPS464 has fixed internal delays that allow the user to
determine the worst-case timing for any design. The individual delays are
predetermined and are not dependent on routing or layout considerations.
For complete timing information, MAX+PLUS II provides a timing
simulator with O.l-ns resolution, delay prediction for point-to-point delay
calculation, and a detailed timing analyzer.
Figure 33. EPS464 Timing Model

tsu

Output
Delay

too

tpRE

txz
tzx

tCLR
tRD
tCOMB

Figure 34 shows the switching waveforms for EPS464 devices.
For more information, see Application Brief 100 (Understanding EPLD Timing)
in this data book.

I Altera Corporation

Page 225

EPS464 EPLD

Data Sheet

Figure 34. EPS464 Switching Waveforms
tR & tF < 3 ns. Inputs are
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.

Input Mode

Input Pin

==1----.;....1-----------------====*_____.__________________
------,x I
.
--------------~x~______~I--------________________________~x~I~-----_________________1+
:_t,o_:

1/0 Pin

l-tExp-~

Expander Array
Delay

: - tLAC, tLAD-:

Logic Array
Input

tCOMB-i

Logic Array
Output

too +-i

Output Pin

.~c==

Array Clock Mode
Clock Pin

Clock into
Logic Array

-! ! - tACH ---i i - tACL-i
:

tIN

i-V

tF-i 1-

\L-1_ _ _ __

\'--__---11

\'------

: - tLAc--i
Clock from
Logic Array

------------~V~----~\~----~I
:+ tsu -.:- tH-:

Data from
Logic Array

--------~*

tRo-+i

*~----~x.~-----------

i-tFO-i

i-fcLR,tpRE-1

i-tFO

--------------~.--~x~--------~x===

Global Clock Mode

tR-i

Global
Clock Pin
Global Clock
at Register

i~:

tF-i i-

\,-1_________

:-tGLOB

l l V~----~\,--------~I
!

Data from
Logic Array

i-tCH-i i-tCL---i

tsu: tH :

\'------

=i~-*~---------------Output Mode

Clock from
Logic Array
Data from
Logic Array

Output Pin

Page 226

--------II. tRO

. too.

~-i-!:.:

\~------~I

x=:=x

\~----

X~_ __

!.!si
!~!
__________~*=======~~~~~~i).-lH~i9~h-~~~t;~~d~a~n~ce~K==========

Altera Corporation

I Data Sheet

Generic Testing

EPS464 EPLD

EPS464 EPLDs are fully functionally tested and guaranteed. Complete
testing of each programmable EPROM bit and all internal logic elements
ensures 100% programming yield. AC test measurements are performed
under conditions equivalent to those shown in Figure 35.

Figure 35. AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous
transitions of multiple outputs should
be avoided for accurate measurement.
Threshold tests must not be
performed under AC conditions.
Large-amplitude, fast ground-current
transients normally occur as the
device outputs discharge the load
capacitances. When these transients
flow through the parasitic inductance
between the device ground pin and the
test system ground, significant
reductions in observable noise
immunity can result.

MAX+PLUS II
Development
System

.------vcc
892Q
Device
Output

to Test
System

347(1
Device input
rise and fall
times < 3 ns

EPS464 EPLDs are supported by the MAX+PLUS II development system, a
completely integrated environment for design entry, compilation,
verification, and programming. MAX+PLUS II software is available for
386- and 486-based PCs, Sun SPARCstations, and HP 9000 Series 700
workstations. All platforms include more than 30074-series macrofunctions
and the Altera Hardware Description Language (AHDL), which supports
state machine, Boolean equation, conditional logic, and truth table entry
methods. MAX+PLUS II also provides highly automated compilation,
automatic multi-device partitioning, timing simulation and analysis,
automatic error location, device programming and verification, and a
comprehensive on-line help system.
In addition, MAX+PLUS II imports and exports industry-standard
EDIF 2 0 a and 2 9 a and other netlist files for a convenient interface to
industry-standard CAE tools from vendors such as Cadence, Data I/O,
Exemplar, Intergraph, Mentor Graphics, OrCAD, Synopsys, and Viewlogic.
MAX+PLUS II also exports Verilog and VHDL netlist files that support
simulation with other industry-standard simulators. For further details
about MAX+PLUS II and other CAE tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and CAE
Software Support in this data book.

I Altera Corporation

Page 227

I EPS464 EPLD

Device
Programming

Data Sheet

EPS464 EPLDs can be programmed on an IBM PS/2, PC-AT, or compatible
computer with an Altera Logic Programmer card, the Master Programming
Unit (MPU), and the appropriate device adapter. The MPU performs
continuity checking to ensure adequate electrical contact between the
adapter and the device.
MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text or Waveform Editor to test a
programmed device. For added design verification, designers can perform
functional testing to compare the functional behavior of a EPS464 to the
results of simulation. To use this feature, you must use the device adapter
with the "PLM-" prefix.
Data I/O and other programming hardware manufacturers also offer
programming support for Altera devices. For more information, see

Programming Hardware Manufacturers.

I Page 228

Altera Corporation

I Data Sheet

EPS464 EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

With respect to GND

-0.5

7.0

Vpp

Programming supply voltage

Note (1)

-1.0

13.0

DC input voltage

-0.5

5.5

I MAX

DC Vee or GND current

400

rnA

lOUT

DC output current, per pin

Power dissipation

-25

rnA

2000

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-55

125

°C

Min

Recommended Operating Conditions
Symbol

Parameter

Conditions

Max

Unit

4.75

vee

Supply voltage

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

°C

tR
tF

Input rise time

100

Input fall time

100

Max

Unit

DC Operating Conditions
Symbol

For commercial use

Notes (2), (3)

Parameter

Conditions

Min

Typ

V IH
V IL

High-level input voltage

2.0

Vee + 0.3

Low-level input voltage

-0.3

0.8

VO H

High-level TTL output voltage

IOH = -4 rnA DC

VOL

Low-level output voltage

IOL = 4 rnA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

Vo =V ee orGND

-40

iJ,A

lee1

Vee supply current (standby)

V I = Vee or GND, Note (4)

100

120

rnA

lee3

Vee supply current (active)

V I = Vee or GND, No load,

105

125

rnA

Min

Max

Unit

2.4

0.4

iJ,A

f = 1.0 MHz, Note (4)

Capacitance
Symbol

Parameter

Conditions

C IN

Input capacitance

V I N = 0 V, f = 1.0 MHz

C OUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

I Altera Corporation

Page 229

I EPS464 EPlD

Data Sheet

AC Operating Conditions

Note (3)

External Timing Parameters
Symbol

EPS464-20

Parameter

Conditions

Min

Max

Unit

tpD1
t pD2

Input to non-registered output

tsu
tH

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl
t ASU

Array clock hold time

tAH
t AC01

C1 = 35 pF

Max

EPS464-25

I/O input to non-registered output

C1 = 35 pF

Global clock low time

Array clock setup time

. Array clock to output delay

tACH
t ACl

Array clock high time

Array clock low time

tCNT

Minimum global clock period

fCNT
t ACNT

Max. internal global clock frequency Note (4)

f ACNT

Max. internal array clock frequency

Note (4)

66.7

MHz

f MAX

Maximum clock frequency

Note (5)

71.4

MHz

15
66.7

Minimum array clock period

Internal Timing Parameters
Symbol

Parameter

Min

Max

ns
MHz

EPS464-20

Conditions

ns
20

Note (6)

EPS464-25

Min

Max

Unit

tIN

Input pad and buffer delay

tiD
t EXP
t LAO
t LAC

I/O input pad and buffer delay

Expander array delay

Logic array delay

Logic control array delay

too
tzx
txz

Output buffer and pad delay

tsu
t RO

tCOMB
tH

Combinatorial delay

tGLOB
t FO
tpRE

Global control delay

Feedback delay

tCLR

C1 = 35 pF

Output buffer enable delay
Output buffer disable delay

= 5 pF
4

I Page 230

5
1
1

1
10

ns
ns
ns

Altera Corporation

I Data Sheet

EPS464 EPLD

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)

Product
Availability

Pin-Out
Information

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA = 25° C, Vee = 5 V.
Operating conditions: Vee =5 V ± 5%, TA = 0° C to 70° C for commercial use.
Measured with a device programmed as four 16-bit counters. Icc measured at 0° C.
The fMAX values represent the highest frequency for pipelined data.
For information on internal timing parameters, refer to Application Brief 100
(Understanding EPLD Timing) in this data book.

Product Grade
Commercial Temp.

(0° C to 70° C)

EPS464-20, EPS464-25

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

Table 11 provides pin-out information for the EPS464 QFP package.
Table 11. EPS464 QFP Pin-Outs

Pin
1
2
3
4
5
6
7
8
9
10
11

I Altera Corporation

Availability

Function

12
13

I/O

I/O
I/O

I/O

GND

15
16
17
18
19
20
21
22

I/O

I/O
I/O
I/O
I/O
VCC
I/O

1/0

I/O

23
24
25
26
27
28
29
30
31
32

I/O

I/O
I/O
GND
VCC
I/O
I/O
I/O

Function
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O

Function

Pin
34
35
36
37
38
39
40
41
42
43
44

I/O
I/O
GND
INPUT/GCLK
INPUT/GPREn
INPUT/GCLRn
INPUT/GOEn
VCC
I/O
I/O
I/O

Page 231

Notes:

Contents
I August 1993

Section 5

Classic
Classic Programmable Logic Device Family ............................................. 235
EP330 EPLD ........................................................................................ 245
EP610 EPLD ........................................................................................ 249
EP610A EPLD ..................................................................................... 257
EP610T EPLD ..................................................................................... 261
EP610 MIL-STD-883-Compliant EPLD ........................................... 265
EP910 EPLD ........................................................................................ 269
EP910A EPLD ..................................................................................... 275
EP910T EPLD ..................................................................................... 279
EP1810 EPLD ...................................................................................... 283
EP1810T EPLD ................................................................................... 291
EP1810 MIL-STD-883-Compliant EPLD ......................................... 295

I Altera Corporation

Page 233

Classic
Programmable Log,ic
Device Family

I August 1993, ver. 1

Data Sheet

Features

o
o

o
o
o
o
o
o

Complete EPLD family with logic densities up to 1,800 available gates
(900 usable gates). See Table 1.
Multiple 20-pin PAL and GAL replacement and integration
Device erasure and reprogramming with advanced, non-volatile
EEPROM and EPROM technology
Fast pin-to-pin logic delays as low as 7.5 ns and internal counter
frequencies as high as 125 MHz
20 to 68 pins available in DIP, J-Iead, PGA, and SOIC packages
Programmable Security Bit for total protection of proprietary designs
100% generically testable to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual Clear and Clock controls
Software design support featuring Altera's MAX+PLUS II development
system on 386- and 486-based PC, Sun SPARC station, and HP 9000
Series 700 workstation platforms
Programming support with Altera's Master Programming Unit (MPU)
and programming hardware from other manufacturers
EDIF, Verilog, VHDL, and other interfaces available for additional
design entry and simulation support from other standard CAE tools

Table 1. Classic Device Features

Feature

EP330

EP610,
EP610T (1)

EP610A

EP910,
EP910T

EP910A

EP1810,
EP1810T (1)

Available Gates

300
150

600
300

600

900
450

1,800

8
18

12
100

15 (35)
83.3 (28.6)

7.5

30
33.3

20 (45)

100

50 (22.2)

Usable Gates
Macrocells
Max. User liD

t pD (ns)
feNT (MHz)

300
16

125

900
48

Note:
(1)

Numbers in parentheses are for MIL-STD-883B-compliant versions of the EP610 and EP1810. For more information,
refer to the EP61 0 MIL-STD-883B-Compliant EPLD and EP1810 MIL-STD-883B-Compliant EPLD data sheets in this
data book.

I Altera Corporation

Page 235

I Classic Programmable Logic Device Family

General
Description

Data Sheet

The Altera Classic family offers the industry's most comprehensive solution
to high-speed, low-power logic integration. Fabricated on advanced CMOS
technologies, these devices also have turbo-only and high-performance
versions, all of which are described in this data sheet.
Classic EPLDs support 100% TTL emulation and can easily integrate
multiple PAL- and GAL-type devices with densities ranging from 150 to
900 usable gates. The Classic family provides pin-to-pin logic delays as low
as 7.5 ns and counter frequencies as high as 125 MHz. Classic EPLDs are
available in a wide range of packages, including ceramic and plastic dual
in-line (CerDIP & PDIP), ceramic and plastic J-Iead chip carrier (JLCC &
PLCC), ceramic pin-grid array (PGA), and plastic small-outline integrated
circuit (SOIC) packages.
The Classic family uses sum-of-products logic, which provides a
programmable-AND I fixed-OR structure that can implement logic with up
to eight product terms. The basic building block of the Classic EPLD, the
macro cell, can be individually programmed for D, T, SR, or JK flipflop
operation or for combinatorial operation. In addition, macrocell registers
can be individually clocked either by a global Clock or by any input or
feedback path to the AND array in all Classic devices except the EP330.
Altera's proprietary programmable 110 architecture allows the designer
to program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to simultaneously implement a variety of logic functions.
In comparison to equivalent bipolar devices, the CMOS EEPROM and
EPROM technologies of Classic EPLDs can reduce active power
consumption without sacrificing performance. This reduced power
consumption makes the Classic family well-suited for a wide range of lowpower applications. Classic devices are 100% generically tested and are
easily erased electrically or with ultraviolet light. Designs and design
changes can be implemented quickly, eliminating the need for postprogramming testing.
The Classic family is supported by Altera's MAX +PLUS II development
system, an integrated software package that offers schematic, text, and
waveform design entry; compilation and logic synthesis; simulation; and
programming capabilities. MAX+PLUS II provides EDIF, VHDL, Verilog,
and other netlist interfaces for additional design entry and simulation
support from other industry-standard PC- and workstation-based CAE
tools. The MAX+PLUS II development system runs on 386- and 486-based
PCs, Sun SPARCstations, and HP 9000 Series 700 workstations.

I Page 236

Altera Corporation

I Data Sheet

Classic Programmable Logic Device Family I

Turbo-Only "T" EPLDs
Altera offers Classic EPLDs in which the Turbo Bit is permanently turned
on (designated by a "T" suffix in the ordering code). These devices are
available in plastic one-time-programmable (OTP) packages and provide a
low-cost, high-speed solution to logic designs. They are completely pin-,
function-, and programming file-compatible with their non-turbo
counterparts. "T" devices have no non-Turbo mode.

High-Performance "A" EPLDs
For the highest performance in the Classic family, Altera offers the EP610A
and EP91OA. Fabricated on a O.8-micron CMOS EEPROM process, these
devices offer tpD delays as low as 7.5 ns and counter frequencies as high as
125 MHz. These EPLDs are reprogrammable, plastic-packaged devices
that are completely pin-, function-, and programming file-compatible with
their EPROM counterparts. "A" devices have no zero-power option.

Functional
Description

The Classic EPLD architecture consists of the following elements:

o
o
o
o

Macrocells
Programmable registers
Output Enable/Clock selection
Feedback selection

Macrocells
The Classic macro cell, shown in Figure I, can be individually configured
for both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an OR gate for combinatorial
logic implementation. An additional product term is used for asynchronous
Clear control of the internal register (asynchronous Clear is not available in
the EP330); another product term implements either an Output Enable or a
logic-array-generated Clock. Inputs to the programmable-AND array come
from both the true and complement signals of the dedicated inputs,
feedbacks from 1/ 0 pins that are configured as inputs, and feedbacks from
macrocell outputs. Signals from dedicated inputs are globally routed and
can feed the inputs of all device macrocells. The routing of feedback signals
from macrocells and I/O pins configured as inputs is controlled by the
feedback multiplexer (feedback MUX).

Altera Corporation

Page 237

I Classic Programmable Logic Device Family

Data Sheet

Figure 1. Classic Macrocell
For additional information on feedback MUX configurations, see Figure 3.

vee

Feedback Array

OE/CLK Select

;·,·············:,:···oe·;/

Programmable
Register

...
to Feedback Array~

Asynchronous Clear
(not available in EP330)

The eight product terms of the programmable-AND array feed the 8-input
OR gate, which then feeds one input to an XOR gate. The other input to the
XOR gate is connected to a programmable bit that allows the array output to
be inverted. Altera's MAX+PLUS II software uses the XOR gate to implement
active-high or active-low logic, or uses De Morgan's inversion to reduce
the number of product terms to implement a function.

Programmable Registers
To implement registered functions, each macrocell flipflop can be
individually programmed for D, T, JK, or SR operation (EP330 EPLDs have
D flipflops only). If necessary, the flipflop can be bypassed for combinatorial
operation. During design compilation, MAX+PLUS II selects the most
efficient flipflop operation for each registered function to minimize the
logic resources needed by the design. Registers have an individual
asynchronous Clear function controlled by a dedicated product term
(asynchronous Clear is not available in the EP330). Registers are cleared
automatically during power-up.

Output Enable/Clock Selection
Figure 2 shows the two operating modes (Mode 0 and 1) provided by the
Output Enable/Clock selection multiplexer (OE/CLK MUX). This
multiplexer, which is controlled by a single programmable bit, can be

I Page 238

Altera Corporation

I Data Sheet

Classic Programmable Logic Device Family

Figure 2. DE/eLK Select Multiplexer
In Mode 0, the register is clocked by the global Clock signal. The output is enabled by the
logic from the product term.

Mode 0:
OE = Product-Term-Controlled
ClK = Global

DE-Select Multiplexer

vee

1.-." ..•..•• , ........... ,

AND
Array

Data

CLRN

Macrocel/
Output Buffer

In Mode 1, the output is permanently enabled and the register is clocked by the product
term, which allows gated clocks to be generated. (Not available in EP330 EPLDs.)

Mode 1:
OE = Enabled
ClK = Product Term

vee

OE-Select Multiplexer

AND
Array

Data

CLRN

Macrocel/
Output Buffer

individually configured for each macrocell. In Mode 0, the tri-state output
buffer is controlled by a single product term. If the output of the AND gate is
high, the output buffer is enabled. If the output is low, the output buffer
has a high-impedance value. In this mode, the macrocell flipflop is clocked
by its global Clock input signal. (The EP330 supports only Mode 0.)
In Mode 1, the Output Enable buffer is always enabled, so the macrocell

flipflop can be triggered by an array Clock signal generated by the
OE/CLK product term. This mode allows flipflops to be individually
clocked by any of the terms on the AND array. With both true and complement
signals in the AND array, the flipflop can be configured to trigger on a rising
or falling edge. This product-term-controlled Clock configuration also
supports gated Clock structures.

I Altera Corporation

Page 239

I Classic Programmable Logic Device Family

Data Sheet

Feedback Selection
Each macrocell in a Classic EPLD provides array feedback selection that is
controlled by the feedback MUX. This feedback selection allows the user to
feed either the macrocell output or the 110 pin input associated with the
macrocell back into the AND array. The macrocell output can be either the Q
output of the programmable register or the combinatorial output of the
macro cell. Different Classic EPLDs have different feedback MUX
configurations. See Figure 3. The EP330, EP610, EP610A, EP91O, and EP910A
have a global feedback configuration: either the macro cell output (Q) or
the 110 pin input (1/ 0) can feed back to the AND array so that it is accessible
to all other macrocells.

Figure 3. Feedback MUX Configurations
Global Feedback MUX

=t+
....
=f+1/0

GIObal+
___

EP330
EP610
EP610A

Quadrant Feedback MUX

EP610T
EP910
EP910A

Dual Feedback MUX

QUadrant+ -t+
Q QU~~~::: :1'- __-----'I: ~
-i+....J
L____

EP1810
EP1810T

I/O

EP1810
EP1810T

EP1810 EPLDs have two feedback configurations: quadrant and dual.
Most macrocells in EP1810 EPLDs have a quadrant feedback configuration:
either the macrocell output or I/O pin input can feed back to other
macrocells in the same quadrant. Selected macrocells in EP1810 EPLDs
have a dual feedback configuration: the output of the macrocell feeds back
to other macrocells in the same quadrant, and the 1/0 pin input feeds back
to all macrocells in the device. If the associated I/O pin is not used, the
macro cell output can optionally feed all macrocells in the device. In this
case, the output of the macrocell passes through the tri-state buffer and
uses the feedback path between the buffer and the I/O pin.

Design Security

Classic EPLDs contain a programmable Security Bit that controls access to
the data programmed into the device. When this bit is programmed, a
proprietary design implemented in the device cannot be copied or retrieved.
This feature provides a high level of design security, since programmed
data within EPROM or EEPROM cells is invisible. The Security Bit that
controls this function, as well as all other program data, is reset when an
EPLD is erased.

Turbo Bit

Many Classic EPLDs contain a programmable Turbo Bit to control the
automatic power-down feature that enables the low-standby-power mode
(IeCl). When the Turbo Bit is turned on, the low-standby-power mode is
disabled. All AC values are tested with the Turbo Bit turned on. When the
device is operating with the Turbo Bit turned off (non-turbo mode), a non-

I Page 240

Altera Corporation

I Data Sheet

Classic Programmable Logic Device Family

turbo adder must be added to the appropriate AC parameter to determine
worst-case timing. The non-turbo adder is specified in the" AC Operating
Conditions" tables for each Classic device that supports the turbo mode.

Timing Model

Classic EPLD timing can be analyzed with MAX+PLUSII software, with a
variety of popular industry-standard CAE simulators and timing analyzers,
or with the timing model shown in Figure 4. Classic EPLDs have fixed
internal delays that allow the user to determine the worst-case timing for
any design. MAX+PLUS II software provides timing simulation, point-topoint delay prediction, and detailed timing analysis for system-level
performance evaluation.

Figure 4. Timing Model
If the register is bypassed, the delay between the logic array and the output buffer is zero.

Output
Delay

1 - - -.... , Register

tsu

I--_.---.J

too
txz
tzx

I/O
~ Delay
t ,O

Feedback
Delay
tFD

Timing information can be derived from the timing model and parameters
for a particular EPLD. External timing parameters can be calculated from
the sum of internal parameters and represent pin-to-pin timing delays.
Figure 5 shows the internal timing relationship for internal and external
delay parameters. For more information on EPLD timing, refer to Application
Brief 100 (Understanding EPLD Timing) in this data book.

I Altera Corporation

Page 241

I Classic Programmable Logic Device Family

Data Sheet I

Figure 5. Switching Waveforms

=tiN +

Input Mode

tR& tF<3 ns.

Inputs are driven at
3 Vfor a logic high and
Vfor a logic low.
AI/ timing characteristics
are measured at 1.5 V.

I/O Pin

------~x~~-------------------------------12!-.:

Input Pin

tLAD + too
t,O + tIN + tLAD + too

tpD1
tpD2 =

---------,x~~·

______________________~______
tLAD

LogicArray Input

-------------,~.:~.------0-L-R------~!--------------------

Logic Array Output

------------------------~~~--~-----------

Output Pin

too

________________________________

~x~

_______

Array Clock Mode
tR

Clock Pin

tACH
: :
:~:_-'-=-'-'--------.;

t ACl

-/r-;'-------;N

tF-+: :--

: tIN :

Clock into Logic Array

tiC

.•
~----=-=--------.;

Clock from Logic Array
:

tAsu

r---

V
:tAH:

Data from Logic Array

!
.'

tFD

Global Clock Mode

~\+-

Global Clock Pin

Global Clock at Register

Data from Logic Array

tF ..

tCl

====x~

____

~x~-------------------------------

Output Mode
Clock from Logic Array

Data from Logic Array

-----------II: too :
~------:

\'--___----11

x:=xi

txz:

:.......,.tz-x--.-------

____________~X=====~·==~j,==~KC===
~~

Output Pin

High Impedance
Tri-State

Page 242

Altera Corporation

Data Sheet

Generic Testing

Classic Programmable Logic Device Family

Classic EPLDs are fully functionally tested and guaranteed. Complete
testing of each programmable EPROM or EEPROM bit and all internal
logic elements ensures 100% programming yield. AC test measurements
are taken under conditions equivalent to those shown in Figure 6.
Test programs can be used and then erased during early stages of the
device production flow. EPROM-based EPLDs in one-time programmable
windowless packages also contain on-board logic test circuitry to allow
verification of function and AC specifications during this production flow.

Figure 6. AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast groundcurrent transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.

. - - - - - - - - VCC

8550
(1500)
Device
Output

3400
(820)

to Test
System

C1 (includes
JIG capacitance)

Device input
rise and fall
times < 3 ns

Numbers in parentheses are for the EP330.

MAX+PLUS II
Development
System

Classic EPLDs are supported by the MAX +PLUS II development system, a
completely integrated environment for design entry, compilation,
verification, and programming. MAX+PLUS II software is available for
386- and 486-based PCs, as well as Sun SPARC stations and HP 9000 Series
700 workstations. All platforms include more than 300 74-series
macrofunctions and the Altera Hardware Description Language (AHDL),
which supports state machine, Boolean equation, conditional logic, and
truth table entry methods. MAX+PLUS II also provides highly automated
compilation, automatic multi-device partitioning, timing simulation and
analysis, automatic error location, device programming and verification,
and a comprehensive on-line help system.
In addition, MAX+PLUS II imports and exports industry-standard
EDIF 2 0 0 and EDIF 2 9 0 netlist files for a convenient interface to industrystandard CAE tools from vendors such as Cadence, Data I/O, Exemplar,
Intergraph, Mentor Graphics, OrCAD, Synopsys, and Viewlogic.
MAX+PLUS II also exports Verilog and VHDL netlist files for use with
other CAE simulation tools such as the Cadence Verilog-XL simulator. For
more details, see the MAX+PLUS II Programmable Logic Development System
& Software and CAE Software Support data sheets in this data book.

I Altera Corporation

Page 2431

I Classic Programmable Logic Device Family

Device
Programming

Data Sheet

Classic EPLDs can be programmed on 386- and 486-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU), and
the appropriate device adapter. The MPU performs continuity checking to
ensure adequate electrical contact between the adapter and the device.
The MAX+PLUS II software can use waveform- or text-format test vectors
created with the MAX+PLUS II Waveform or Text Editor to test a
programmed device. For added design verification, designers can perform
functional testing to compare the functional behavior of a Classic EPLD to
the results of simulation. (This feature requires a device adapter with the
"PLM-" prefix.) See the Altera Programming Hardware Data Sheet for more
information.
Data I/O and other programming hardware manufacturers also offer
programming support for Altera devices. See the Programming Hardware
Manufacturers data sheet in this data book for more information.

I Page 244

Altera Corporation

EP330 EPLOi
Features

High-performance, 8-macrocell Classic EPLD
Combinatorial speeds with tpD = 12 ns
Counter frequencies up to 100 MHz
Pipelined data rates up to 125 MHz
Low power; Icc = 45 mA (typical)
Macrocell flipflops can be individually programmed for registered or
combinatorial operation
Available in 20-pin, one-time-programmable (OTP) plastic packages
(see Figure 7):
Small-outline integrated circuit (SOle)
Dual in-line package (PDIP)
Direct replacement for 20-pin PAL/GAL devices

Figure 7. EP330 Package Pin-Out Diagrams
Package outlines not drawn to scale.
INPUTleLK

INPUTleLK

vee

Corporation

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

I/O

INPUT

1/0

INPUT

1/0

INPUT

1/0

INPUT

1/0
INPUT

20-Pin

I Altera

1/0

INPUT

GND

General
Description

vee

INPUT

sOle

GND

INPUT

20-Pin DIP

The Altera EP330 EPLD is a high-speed, low-power device that is a direct
replacement for GAL 16V8 and most 20-pin PAL programmable logic
devices. The EP330 has 8 macrocells, 10 dedicated input pins, and 8 I/O
pins (see Figure 8). Each macrocell can access signals from the global bus.
The global bus consists of the true and complement forms of the device
inputs and the macrocell outputs. Pin 1 can be used as the global Clock for
registers in the device or as a dedicated input for combinatorial logic.

Page 245

EP330 EPLD

Data Sheet

Figure 8. EP330 Block Diagram
1 INPUT/CLK

Global
Bus

.....
.....
.....
.....
.....
.....
.....
.....

MACROCELL 1
MACROCELL2

MACROCELL3

MACROCELL4

MACROCELL5

MACROCELL6

MACROCELL 7

MACROCELL8

Figure 9 shows the maximum output drive characteristics of EP330 I/O
pins and typical supply current {lcd versus frequency for the EP330
EPLD.

Figure 9. EP330 Maximum Output Drive Characteristics & Icc vs. Frequency
55
160
50

ci.
~

120

E-

V ee =5.0V

~
::J

TA = 25° C

«
E-

Vee = 5.0 V

TA = 25° C

·u

"5
a.
"5

()

..9
20
0.5

V0 Output Voltage (V)

Page 246

10 kHz

1 MHz

100 MHz

Maximum Frequency

Altera Corporation

Data Sheet

EP330 EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for A/tera Devices in this data book.

Parameter

Min

Conditions

Max

Unit

vee

Supply voltage

With respect to G N D

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

14.0

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-160

160

lOUT

DC output current, per pin

-50

Power dissipation

800

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

tR
tF

Input rise time

Note (2)

Input fall time

Note (2)

Max

Unit
V

DC Operating Conditions
Symbol

Notes (3), (4)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

lee3

Vee supply current (active)

= -12 mA DC
IOL = 24 mA DC
VI = VeeorGND
Vo = VeeorGND
IOH

2.4

V
V

-10
-10

0.5

IlA

V I = Vee or GND, No load,
Note (5)

rnA

= Vee or GND, No load,

Min

Max

Unit

f = 1.0 MHz, Note (5)

Capacitance

Note (6)

Symbol

Parameter

Conditions

= 0 V,

f = 1.0 MHz

C IN

Input capacitance

V IN

C OUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

C eLK

Clock pin capacitance

V IN

Altera Corporation

= 0 V,

f = 1.0 MHz

Page 2471

I EP330 EPLD

Data Sheet

AC Operating Conditions

Note (4)
EP330-12

Symbol

Parameter

Conditions

Min

= 35 pF

Max

EP330-15

Min

Max

Unit

t pD1

Input to non-registered output

t pD2

liD input to non-registered output

tpzx

Input to output enable

tpxz

Input to output disable

tlO

I/O input pad and buffer delay

EP330-12

EP330-15

= 5 pF,

Note (7)

Global Clock Mode
Symbol

Conditions

Parameter

Min

Max

Min

Max

Unit
MHz

f MAX

Maximum frequency

125

100

tsu

Setup time

Hold time

ns
ns

Note (8)

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

10
100

Note (5)

ns
10

12
83.3

ns
ns
MHz

Notes to tables:
(1) Minimum DC input is -0.3 V. During transitions, inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods
less than 20 ns under no-load conditions.
(2) For all Clocks: tR and tF = 20 ns.
(3) Typical values are for TA = 25° C and Vee =5 V.
(4) Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5 V ± 10%, TA =-40° C to 85° C for industrial use.
(5) Measured with a device programmed as an 8-bit counter. Icc measured at 0° C.
(6) Capacitance measured at 25° C. Sample-tested only. Pin 11 (high-voltage pin during programming) has maximum
capacitance of 20 pF.
(7) Sample-tested only for an output change of 500 m V.
(8) The fMAX values represent the highest frequency for pipelined data.

Product
Availability

I Page 248

Product Grade

Availability

Commercial Temp.

(0° C to 70° C)

EP330-12, EP330-15

Industrial Temp.

(-40 0 C to 85° C)

EP330-15

Altera Corporation

EP610 EPLD
o

Features

o
o
o

High-performance, 16-macrocell Classic EPLD
Combinatorial speeds with tpD = 15 ns
Counter frequencies up to 83 MHz
Pipelined data rates up to 83 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
Pin-, function-, and programming file-compatible with Altera's
EP61OA, EP610T, and EP610 MIL-STD-883-compliant devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages (see Figure 10):
24-pin small-outline integrated circuit (plastic SOIC only)
24-pin dual in-line package (CerDIP and PDIP)
28-pin plastic J-Iead chip carrier (PLCC)

Figure 10. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.

:::J

~
CLK1

VCC

INPUT
I/O

VCC

CLK1

INPUT

INPUT
I/O

I/O

INPUT

I/O

24-Pin SOIC

General
Description

I Altera Corporation

~
26
25

1/0

I/O
I/O
I/O

I/O

CLK2

c..

I/O

GND

I/O

(.)
(.)

I/O

INPUT

I/O
I/O

I/O

I:::J

(.)
(.)

(.)

I/O

INPUT

c..

INPUT

GND

CLK2

24-Pin DIP

EP610
12

:::J

c..

<.9

(!)

I:::J

(.)

c..
~

28-Pin J-Lead

The EP610 has 16 macro cells, 4 dedicated input pins, 16 I/O pins, and 2
global Clock pins (see Figure 11). Each macro cell can access signals from
the global bus, which consists of the true and complement forms of the
dedicated inputs and the true and complement forms of either the output
of the macrocell or the 110 input. CLOCKl is a dedicated Clock input for the
registers in macrocells 9 through 16. CLOCK2 is a dedicated Clock input for
registers in macrocells 1 through 8.

Page 249 I

I EP610 EPLD

Data Sheet

Figure 11. EP610 Block Diagram
Numbers without parentheses are for DIP and sOle packages. Numbers in parentheses are for J-Iead packages.
2 (3)

INPUT

1 (2)

CLOCK1

•

c=>

(4)

MACROCELL9

(5)

MACROCELL 10

(6)

MACROCELL 11

(7)

MACROCELL 12

(8)

MACROCELL 13

(9)

MACROCELL 14

(10)

MACROCELL 15

(12)

MACROCELL 16

.....
.....
.....
.....
.....
.....
.....
.....

...

Global
Bus

•

.........
......
......

INPUT

23 (27)

CLOCK2 13 (16)

MACROCELL 1

22 (26)

MACROCELL2

MACROCELL3

20 (24)

MACROCELL4

19 (23)

MACROCELL5

18 (22)

MACROCELL6

17 (21)

MACROCELL7

16 (20)

(25)

15 (18)

MACROCELL8

...

INPUT

14 (17)

Figure 12 shows the maximum output drive characteristics of EP610 I/O
pins.

Figure 12. EP610 Maximum Output Drive Characteristics
EP610-15 & EP610-20 EPLDs

EP610-25, EP610-30 &EP61 0-35 EPLDs

200

ci
~
~

80 -

150

Vee =5.0V

"E
~

"5
0.
"5

Vee

TA = 25° C

100

= 5.0 V

= 25° C

...9
0.45

V0 Output Voltage (V)

I Page 250

0.45

V0 Output Voltage (V)

Altera Corporation

I Data Sheet

EP610 EPLD I

Figure 13 shows the typical supply current (Icd versus frequency of all
EP610 devices.

Figure 13. EP610 Icc vs. Frequency
100.------------------------=~

ci.
~

1.0

Vee = 5.0 V
TA = 25° C

()

0.1
1 KHz

10 KHz 100 KHz 1 MHz 10 MHz 80 MHz

Maximum Frequency

I Altera Corporation

Page 251

I EP610 EPLD

Data Sheet

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-175

175

lOUT

DC output current, per pin

Power dissipation

-25

1000

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Note (2)

Parameter

Conditions

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

°C

4.75 (4.5) 5.25 (5.5)

For commercial use

V
V

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

Note (3)

100 (50)

Input fall time

100 (50)

Max

Unit
V

DC Operating Conditions
Symbol

Notes (2), (4), (5)

Parameter

Conditions

Speed
Grade

Min

Typ

V IH
V IL

High-level input voltage

2.0

Vee +0.3

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VO H
VOL

10H = -4 mA DC

2.4

High-level CMOS output voltage

10H = -2 mA DC

3.84

Low-level output voltage

10L = 4 mA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

Vo = VeeorGND

-10

lee1

Vee supply current

V I = Vee or GND, No

(non-turbo, standby)

load, Notes (6), (7)

lee2

Vee supply current
(non-turbo, active)

lee3

Vee supply current
(turbo, active)

I Page 252

V
V
V

0.45

flA

150

flA

10 (15)

-15, -20

90 (115)

-25, -30, -35

60 (75)

VI = VeeorGND, No
. load, f = 1.0 MHz
Note (7)

Altera Corporation

I Data Sheet
Capacitance

EP610 EPLD

Note (8)

Symbol

Parameter

Min

Conditions

Max

= 0 V, f = 1.0 MHz
= OV, f = 1.0MHz
= 0 V, f = 1.0 MHz

Unit

CIN

Input capacitance

VI N

COUT

Output capacitance

V OUT

CCLK

Clock pin capacitance

VI N

AC Operating Conditions: EP610-15 and EP610-20

Note (5)
EP610-15

Symbol

Parameter

Conditions

Input to non-registered output

tpzx

Input to output enable

tpxz

Input to output disable

C1 = 5 pF, Note (10)

tClR

Asynchronous output clear time

tlO

I/O input pad and buffer delay

I/O input to non-registered output

Symbol

Parameter

Conditions

Non-Turbo
Adder

Note (9)

Unit

EP610-15

EP610-20

= 35 pF

Global Clock Mode

EP61 0-20

Min Max Min Max

C1 = 35 pF

tpD1
t PD2

Min Max Min Max

Non-Turbo
Adder

Note (9)

Unit
MHz

f MAX

Maximum frequency

83.3

62.5

tsu
tH

Input setup time

Input hold time

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

Note (11)

Symbol

Conditions

16
62.5

83.3

EP610-15

Parameter

12
Note (7)

Array Clock Mode

EP610-20

Min Max Min Max

MHz

Non-Turbo
Adder

Note (9)

Unit
MHz

f MAX
t A5U

71.4

55.6

Input setup time

tAH

Input hold time

Clock high time

Clock low time

tACH
t ACl
tAC01
t ACNT
f ACNT

Maximum frequency

Note (11)

Clock to output delay

Minimum clock period

MHz

Internal maximum frequency

I Altera Corporation

Note (7)

71.4

55.6

Page 253

I EP610 EPLD

Data Sheet

AC Operating Conditions: EP610-25, EP610-30, and EP610-35

Note (5)

EP610-25

Symbol

Parameter

Conditions

EP610-30

EP610-35

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

C1 = 35 pF

Unit

t pD1

Input to non-registered output

t pD2

lID input to non-registered output

tpzx

Input to output enable

t pxz

Input to output disable

C1 = 5 pF,
Note (10)

tClR

Asynchronous output clear time

C1 = 35 pF

flO

lID input pad and buffer delay

EP61 0-25

EP610-30

EP610-35

Globa/Clock Mode

Symbol

Parameter

Conditions
Note (11)

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

Unit

f MAX

Maximum frequency

47.6

41.7

37.0

MHz

tsu

Input setup time

Input hold time

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

MHz

Note (7)

Array Clock Mode

Symbol

40.0

33.3

EP610-25

Parameter

Conditions

28.6

EP61 0-30

EP61 0-35

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

Unit
MHz

f MAX

Maximum frequency

47.6

41.7

37.0

t ASU

Input setup time

tAH

Input hold time

tACH

Clock high time

t ACl

Clock low time

t AC01

Clock to output delay

t ACNT

Minimum clock period

f ACNT

Internal maximum frequency

MHz

I Page 254

Note (11)

Note (7)

40.0

33.3

28.6

Altera Corporation

Data Sheet

EP610 EPLD

Notes to tables:
(1)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. For
EP61O-15 and EP610-20 EPLDs: maximum Vpp is 14.0 V.
(2) Numbers in parentheses are for military~ and industrial-temperature-range versions.
(3) For EP610-15 and EP610-20 EPLDs: tR and tp = 40 ns. For EP61O-15 and EP61O-20
Clocks: tR and tp = 20 ns.
(4) Typical values are for TA = 25° C and Vee =5 V.
(5) Operating conditions: Vee =5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee =5 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee =5 V ± 10%, Te =-55° C to 125° C for military use.
(6) When the Turbo Bit is not set (non-turbo mode), an EP610 EPLD will enter standby
mode if no logic transitions occur for 100 ns (after the last transition).
(7) Measured with a device programmed as a 16-bit counter. Icc measured at 0° C.
(8) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated clock inputs only. For EP610-25, EP610-30, and EP610-35 EPLDs: Pin 13
(high-voltage pin during programming) has a maximum capacitance of 50 pF;
CIN, COUT' and CeLK = 20 pF.
(9) See "Turbo Bit" earlier in this data sheet.
(10) Sample-tested only for an output change of 500 m V.
(11) The fMAX values represent the highest frequency for pipelined data.

Product
Availability

Availability

Product Grade

EP61 0-15, EP61 0-20, EP61 0-25,

Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C)
(-55° C to 125 C)

EP61 0-30, EP61 0-35

Military Temp.

EP61 0-20, EP61 0-30, EP61 0-35
EP61 0-35

Note (1)

Note:
(1)

Altera Corporation

Only military-temperature-range devices are listed. MIL-STD-883-compliant product
specifications are provided in the EP610 MIL-STD-883-Compliant EPLD Data Sheet in
this data book and in Military Product Drawings (MPDs). However, MPDs should
be used to prepare Source Control Drawings (SCDs) and are available from Altera
Marketing at (408) 894-7000. (For more information on MPDs and SCDs, see the
Military Products Data Sheet in this data book.)

Page 2551

Notes:

EP610A EPLD
o

Features

Preliminary
Information

o
o
o

Highest-performance, 16-macrocell Classic EPLD
Combinatorial speeds with tpD = 7.5 ns
Counter frequencies up to 125 MHz
Pipelined data rates up to 142.9 MHz
Fabricated on advanced O.8-micron CMOS EEPROM technology
Programmable I/O architecture with up to 20 inputs or 16 outputs
Pin-, function-, and programming file-compatible with Altera's EP610,
EP610T, EP610 MIL-STD-883-compliant, and EP630 devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in reprogrammable plastic packages (see Figure 14):
24-pin small-outline integrated circuit (SOle)
24-pin dual in-line package (PDIP)
28-pin J-Iead chip carrier (PLee)

Figure 14. EP610A Package Pin-Out Diagrams

Package outlines not drawn to sea/e.
CLK1

VCC

INPUT
CLK1
INPUT

INPUT

VCC

110

1/0

INPUT

1/0

110

1/0

110

1/0

1/0
1/0

INPUT

INPUT
CLK2

GND

24-Pin SOIC

General
Description

I Altera Corporation

INPUT

CLK2

26
25

1/0
1/0

1/0

EP610A

=>
a.
~

24-Pin DIP

1/0

INPUT

GND

0
0

1/0

0
0

=>
a.

(.)

1/0

1/0
1/0

=>
a.

1/0

zC)

'"
::i
0

=>
a.
~

28-Pin J-Lead

The Altera EP610A EPLD is a high-speed, EEPROM-based version of the
EP610 device. Fully compatible with EP610 devices, the EP610A offers
enhanced performance for existing EP610 designs with no additional
design modifications. For information on EP610A architecture, refer to
Figure 11 earlier in this data sheet.

Page 2571

I EP610A EPLD

Preliminary Information

Absolute Maximum Ratings
Symbol

Data Sheet

See Operating Requirements for Altera Devices in this data book.
Min

Max

Unit

vee

Supply voltage

Parameter

With respect to GND

Conditions

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-175

175

lOUT

DC output current, per pin

-25

Power dissipation

1000

T STG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

Input fall time

Max

Unit
V

DC Operating Conditions
Symbol

Notes (2), (3)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VOL

Low-level output voltage

IOL = 8 mA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

lee3

Vee supply current (active)

V I = Vee or GND, No load,
f = 1.0 MHz, Notes (4), (5)

Capacitance
Symbol

V
V

0.45

105

130 (180)

Min

Max

Unit

Note (6)
Parameter

Conditions
= 0 V, f

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT = 0 V, f

I Page 258

2.4

IOH = -4 mA DC

1.0 MHz

Altera Corporation

Preliminary Information

Data Sheet

AC Operating Conditions

Parameter

t pD1

Input to non-registered output

tpD2

I/O input to non-registered output

EP610A-12

EP610A-15

Conditions Min Max Min Max Min Max Min Max Unit
C1 = 35 pF

7.5

tpzx

Input to output enable

7.5

Input to output disable

C1 = 5 pF,
Note (7)

7.5

tClR

Asynchronous output clear time

C1 = 35 pF

7.5

Global Clock Mode

EP610A-7

Parameter

EP61OA-10

EP610A-12

EP610A-15

Conditions Min Max Min Max Min Max Min Max Unit

f MAX

Maximum frequency

142.9

125

100

83.3

tsu

Input setup time

Input hold time

tCH

Clock high time

3.5

tCl

Clock low time

3.5

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

Note (8)

Symbol

125.0

EP610A-7

Parameter

6
10

8
Note (4)

Array Clock Mode

EP61OA-10

t pxz

Symbol

MHz

ns
8

100

83.3

71.4

EP610A-10

EP610A-12

EP610A-15

ns
ns
MHz

Conditions Min Max Min Max Min Max Min Max Unit

f MAX

Maximum frequency

142.9

125

100

83.3

t ASU

Input setup time

tAH

Input hold time

tACH

Clock high time

3.5

t ACl

Clock low time

3.5

t AC01

Clock to output delay

t ACNT

Minimum clock period

f ACNT

Internal maximum frequency

Altera Corporation

Note (3)
EP610A-7

Symbol

EP610A EPLD

Note (8)

Note (4)

125.0

100

83.3

71.4

MHz

ns
ns
ns
MHz

Page 2591

I EP610A EPLD

Preliminary Information

Data Sheet

Notes to tables:
(1)
(2)
(3)

(4)

(5)
(6)

(7)
(8)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use;
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use; Vee = 5 V ± 10%, Te = -55°
C to 125° C for military use.
Measured with a device programmed as a 16-bit counter. lee measured at 0° C.
Actual Ice should be verified during operation because this measurement is sensitive
to the operating conditions and the actual pattern in the device.
Numbers in parentheses are for military and industrial temperature versions.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated Clock inputs only. CLK2 (high-voltage pin during programming) has a
maximum capacitance of 20 pF.
Sample-tested only for an output change of 500 m V.
The fMAX values represent the highest frequency for pipelined data.

Figure 15 shows the output drive characteristics of EP610A I/O pins.

Figure 15. EP610A Maximum Output Drive Characteristics
150

ci.
~
~

120

.s
~

Vee

= 5.0 V

Room Temp.

:;
0

S
0S
0
..9

45
30

Vo Output Voltage (V)

Product
Availability

I Page 260

Product Grade
Commercial Temp.

(0° C to 70° C)

Availability
EP610A-7, EP610A-10, EP610A-12,
EP610A-15

Industrial Temp.

(-40 0 C to 85° C)

EP610A-15

Military Temp.

(-55 0 C to 125° C)

Consult factory

Altera Corporation

EP610T EPLD
o

Features

o
o

High-performance, 16-macrocell Classic EPLD
Combinatorial speeds with tpD = 15 ns
Counter frequencies up to 83 MHz
Pipelined data rates up to 83 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
Pin-, function-, and programming file-compatible with Altera's EP610,
EP61OA, and EP610 MIL-STD-883-compliant devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in low-cost, one-time-programmable (OTP) packages (see
Figure 16):
24-pin small-outline integrated circuit (SOIC)
24-pin dual in-line package (PDIP)
28-pin J-lead chip carrier (PLCC)

Figure 16. EP610T Package Pin-Out Diagrams

()
()

:::l

Q
Q

;E;

26
25

I/O

Package outlines not drawn to scale.
CLK1

VCC

INPUT
CLK1
INPUT
I/O

INPUT

I/O
I/O

VCC

I/O

INPUT

I/O

INPUT

GND

CLK2

24-Pin SOIC

General
Description

I Altera Corporation

:::l

I/O

c..

;E;
3

c..

I/O

INPUT

INPUT
GND

CLK2

24-Pin DIP

EP610-xxT
12

c..

·u
«

1.0

()

..2

0.1
1 kHz

10 kHz 100 kHz 1 MHz 10 MHz 80 MHz

Maximum Frequency

Product
Availability
I Page 264

Product Grade

Availability
EP610-15T, EP610-20T, EP610-25T

Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

Altera Corporation

EP610 MIL-STD-883-Compliant EPLD
Features

o
o
o
o
o
o

High-performance, 16-macrocell Classic EPLD
Combinatorial speeds with tpD = 35 ns
Counter frequencies up to 28.5 MHz
Pipelined data rates up to 37 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
Pin-,function-, and programming file-compatible with Altera's EP610
devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or 5R flipflops, or
for combinatorial operation
Available in 24-pin windowed ceramic dual in-line packages (CerDIP)
(see Figure 18)

Figure 18. EP610 MIL-STD-883-Comp/iant Package Pin-Out Diagram
Package outlines not drawn to sea/e.
CLK1

VCC

INPUT

1/0

110

1/0

I/O

INPUT

GND

CLK2

24-Pin DIP

General
Description

I Altera Corporation

The Altera EP610 MIL-STD-883-compliant EPLD can implement up to 600
equivalent gates of 55I and M5I logic functions. This device complies with
the military standard operating requirements listed in MIL-STD-883B. For
information on the device architecture, output drive characteristics, and
supply current versus frequency graphs, refer to Figures 11, 12, and 13,
respectively, earlier in this data sheet.

Page 265

EP610 MIL-STD-883-Compliant EPLD

Absolute Maximum Ratings
Symbol

Data Sheet

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

-2.0

7.0

Vpp

Programming supply voltage

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-175

lOUT

-25

175
25

DC output current, per pin

Power dissipation

1000

With respect to GND

T STG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-55

125

°C

Junction temperature

Under bias

150

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.5

5.5

Input voltage

Vee

Output voltage

Vee

Case temperature

-55

125

°C

tR
tF

50
50

Input fall time

Min

Max

Unit

2.0

Vee + 0.3

-0.3

0.8

For military use

Input rise time

DC Operating Conditions
Symbol

Note (1)

Parameter

V IH

High-level input voltage

V IL

Low-level input voltage

VO H

High-level TTL output voltage

V OH

High-level CMOS output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

ICC1

V CC supply current

Conditions
Note (2)

= -4 mA DC, Note (3)
IOH = -2 mA DC, Note (3)
IOL = 4 mA DC, Note (3)
VI = VeeorGND
V 0 = V ec or GND
V I = V CC or GND, No load, Note (4)
IOH

2.4
3.84

-10
-10

V
V
V

0.45

IlA

900

IlA

140

(non-turbo, standby)
ICC2

ICC3

= V CC or GND, No load, f = 1.0 MHz,

V CC supply current

(non-turbo, active)

Note (4)

= V CC or GND, No load, f = 1.0 MHz,

V CC supply current

(turbo, active)

Note (4)

Page 266

Altera Corporation

I Data Sheet
Capacitance

EP610 MIL-STD-883-Compliant EPLD

Note (5)

Symbol

Parameter

Conditions
=

C IN

Input capacitance

V IN

C OUT

Output capacitance

V OUT

CCLK

Clock pin capacitance

V IN

AC Operating Conditions
Symbol

0 V, f

Min

1.0 MHz

Max

Unit

Max

Unit

Note (1)

Parameter

Conditions

Min

t pDl
t pD2

Input to non-registered output

C1 = 35 pF

I/O input to non-registered output

Notes (6), (7)

tpzx
t pxz

Input to output disable

tClR

Asynchronous output clear time

Input to output enable

= 5 pF, Notes (2), (6), (7), (8)
= 35 pF, Notes (6), (7)

Global Clock Mode
Symbol

Parameter

Conditions

f MAX

Maximum frequency

Notes (6), (9), (10)

tsu

Input setup time

Notes (6), (7)

Input hold time

tCH

Clock high time

tCl

Clock low time

tCOl

Clock to output delay

tCNT

Minimum clock period

Notes (2), (11)

fCNT

Internal maximum frequency

Note (11)

Min

Max

Unit

37.0

MHz

Note (6)

Note (2)

ns
20

ns
MHz

28.5

Array Clock Mode
Symbol

Parameter

Conditions

Min

Max

Unit

f MAX

Maximum frequency

Notes (6), (9), (10)

37.0

t ASU

Input setup time

Notes (2), (6), (7)

tAH

Input hold time

tACH
t ACl
t AC01

Clock low time
Clock to output delay

Notes (6), (7)

t ACNT

Minimum clock period

Notes (2), (11)

f ACNT

Internal maximum frequency

Clock high time

I Altera Corporation

Notes (2), (7)

MHz

28.6

MHz

Page 267

EP610 Mll-STD-883-Compliant EPlD

Data Sheet

Notes to tables:
(1)
(2)
(3)
(4)
(5)

(6)

(7)

(8)
(9)
(10)
(11)

Product
Availability

Screening and characterization of AC delay parameters are conducted at 10 MHz or
less. Operating conditions: Vee = 5 V DC ± 10%, Tc = -55° C to 125° C
These devices may not be tested, but are guaranteed to the limits specified in the
Absolute Maximum Ratings table.
Tested at maximum operating temperature only.
Tested with non-output loading using a data pattern specified by the device
manufacturer. Data path is correlated to a 16-bit counter.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated inputs only. Pin 13 (high voltage pin during programming) has a
capacitance of 50 pF.
All array-dependent delays are specified for an XOR pattern. This pattern includes
two product terms and two pure inputs; all other product terms in the macrocell are
held low by one EPROM pull-down. Other patterns may result in longer delays.
Delays for patterns involving only one product term (such as t pxz) are specified for
an xOR-like pattern in which only one pure input switches at a time.
-When in non-turbo mode, a non-turbo adder of 30 ns (maximum) is added to this
parameter to determine worst-case timing. Parameters may not be tested in nonturbo mode, but are guaranteed to the limits specified. Devices operating in nonturbo mode require one input or I/O transition to guarantee that the device will
enter the correct power-up state.
Not tested directly, but guaranteed by testing t pD .
The fMAX values represent the highest frequency for pipelined data.
Not tested directly, but derived from tsu.
Specified with device programmed as a 16-bit counter with no output loading.

Product Grade
MIL-STD-883-Compliant

Availability

(-55 C to 125 C)
0

EP610 MIL-STD-883, Note (1)

Note:
(1)

Page 268

Only military-temperature-range devices are listed. MIL-STD-883-compliant product
specifications are provided in this data sheet and in Military Product Drawings
(MPDs). However, MPDs should be used to prepare Source Control Drawings
(SCDs) and are available from Altera Marketing at (408) 894-7000. (For more
information on MPDs and SCDs, see the Military Products Data Sheet in this data
book.)

Altera Corporation

EP910 EPLD
Features

o
o
o

High-performance, 24-macrocell Classic EPLD
Combinatorial speeds with tpD = 30, 35, and 40 ns
Counter frequencies up to 33 MHz
Pipelined data rates up to 41 MHz
Programmable I/O architecture with up to 36 inputs or 24 outputs
Pin-, function-, and programming file-compatible with Altera's EP910A
and EP910T EPLDs
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or 5R flipflops, or
for combinatorial operation
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages (see Figure 21):
44-pin J-Iead chip carrier (JLCC and PLCC)
40-pin dual in-line package (CerDIP and PDIP)

Figure 21. EP910 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
f--

f--

INPUT

2 1 44 43 4241 40

INPUT

14
1/0

CLK1

~~~~§~~~~~~

INPUT
INPUT

1/0

NC
1/0
1/0

1/0

110

1/0

1/0
1/0

1/0

110

EP910

1/0

INPUT
18192021 22232425262728

~~~~~~§~~~~
~~~

~~~

44-Pin J-Lead

General
Description

I Altera Corporation

40-Pin DIP

The Altera EP910 EPLD can implement up to 900 equivalent gates of 55I
and M5I logic functions. The EP910 has 24 macrocells, 12 dedicated input
pins, 241/0 pins, and 2 global Clock pins (see Figure 22). Each macrocell
can access signals from the global bus, .which consists of the true and
complement forms of the dedicated inputs and the true and complement
forms of either the output of the macrocell or the I/O input. CLOCKl and
CLOCK2 are the dedicated Clock inputs for the registers in macrocells 13
through 24 and 1 through 12, respectively.

Page 269

Data Sheet I

EP910 EPLD

Figure 22. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-Iead packages.
2 (3)

INPUT

3 (4)

INPUT

4 (5)

INPUT

1 (2)

CLOCK1

(6)

(7)

(8)

(9)

,.--

c::::::>
c::::::>
c::::::>
c::::::>

9 (10)

•

MACROCELL 13

r-r--

MACROCELL 16

MACROCELL 14
MACROCELL 15

MACROCELL 17

(11)

I--

MACROCELL 18

(12)

f--t-t-t-t-t--

MACROCELL 19

(13)

(14)

(15)

(16)

(18)

17 (19) INPUT
18 (20) INPUT
19 (21) INPUT

....
......
......

....
....
....
.. ..
~

t-t-t--

MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24

c::::::>
c::::::>
c::::::>

...

•

38 (42)

INPUT

37 (41)

CLOCK2 21 (24)

MACROCELL3
MACROCELL4

r---

33 (36)

MACROCELL5

I--

32 (35)

MACROCELL6

f--f---

30 (33)

MACROCELL7
MACROCELL8
MACROCELL9
MACROCELL 10
MACROCELL 11
MACROCELL 12

35 (38)
34 (37)

f---~
f---~
f---~
r--~

r--i<

CJ
CJ
CJ

...
...

39 (43)

INPUT

36 (40)

MACROCELL2

...

INPUT

r-r-r--

MACROCELL 1

Global
Bus

CJ
CJ
CJ
CJ

...
...

(34)

29 (32)
28 (31)
27 (30)
26 (29)
25 (28)
INPUT 24 (27)
INPUT

23 (26)

INPUT

22 (25)

Figure 23 shows the output drive characteristics of EP910 I/O pins and
typical supply current (Icd versus frequency for the EP910 EPLD.

Figure 23. EP910 Maximum Output Drive Characteristics and Icc vs. Frequency
100

ci
~

= 5.0 V
TA = 25° C
Vee

"5
a.
"5

r----------------:::::;;IIOI

Vee =5.0V
= 25° C

1.0

..9

..9
0.1
0
0.45

Vo Output Voltage (V)

Page 270

1 kHz

10 kHz 100 kHz 1 MHz 10 MHz 40 MHz

Maximum Frequency

Altera Corporation

I Data Sheet

EP910 EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for A/tera Devices in this data book.

Parameter

Min

Conditions

Max

Unit

7.0

vee

Supply voltage

With respect to GND

-2.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-250

250

-25

1200

lOUT

DC output current, per pin

Power dissipation

T STG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Note (2)

Parameter

Conditions

4.75 (4.5) 5.25 (5.5)

vee

Supply voltage

Input voltage

Note (2)

Vee

Output voltage

Vce

Operating temperature

°C

For commercial use

V
V

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

Note (3)

Input fall time

DC Operating Conditions
Symbol

100 (50)

Max

Unit
V

Notes (2), (4), (5)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

10H = -4 mA DC

2.4

V OH

High-level CMOS output voltage

10H = -2 mA DC

3.84

VOL

Low-level output voltage

10L = 4 mA DC

Input leakage current

VI = VeeorGND

-10

loz

Tri-state output off-state current

Va = VeeorGND

-10

lee1

Vee supply current
(non-turbo, standby)

V I = Vee or GND, No load,
Notes (6), (7)

lec2

Vee supply current
(non-turbo, active)

V I = Vee or GND, No load,

f = 1.0 MHz, Note (7)
45

80 (100)

lee3

Vee supply current
(turbo, active)

I Altera Corporation

V
V
V

0.45

I1A

150

I1A

Page 271

I EP910 EPLD
Capacitance

Data Sheet

Note (8)

Max

Unit

C IN

Input capacitance

V I N = 0 V, f = 1.0 MHz

C OUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

CCLK

Clock pin capacitance

V I N = 0 V, f = 1.0 MHz

Symbol

Parameter

AC Operating Conditions

Symbol

Min

Conditions

Note (5)
EP91 0-30

Parameter

Conditions

EP91 0-35

EP910-40

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

Unit

tpD1

Input to non-registered output

t pD2

lID input to non-registered output

tpzx

Input to output enable

t pxz

Input to output disable

C1 = 5 pF,
Note (10)

tClR

Asynchronous output clear time

tlO

lID input pad and buffer delay

C1 = 35 pF

= 35 pF

Global Clock Mode

Symbol

EP910-30

EP91 0-35

EP91 0-40

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

Unit

41.7

37.0

32.3

MHz

tsu

Input setup time

Input hold time

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

MHz

Parameter

f MAX

Maximum frequency

Conditions
Note (11)

Note (7)

Array Clock Mode

Symbol

33.3

28.6

EP91 0-30

Parameter

Conditions
Note (11)

25.0

EP91 0-35

EP91 0-40

Non-Turbo
Adder

Min Max Min Max Min Max Note (9)

Unit

f MAX

Maximum frequency

33.3

31.3

29.4

MHz

t ASU

Input setup time

tAH

Input hold time

tACH

Clock high time

t ACl

Clock low time

ns
ns

t AC01

Clock to output delay

t ACNT

Minimum clock period

f ACNT

Internal maximum frequency

I Page 272

Note (7)

33.3

28.6

MHz

25.0

Altera Corporation

I Data Sheet

EP910 EPLD

Notes to tables:
(1)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature versions.
(3) For all Clocks: tR and tp = 100 ns (50 ns for military and industrial temperature
versions).
(4) Typical values are for TA = 25° C and Vee = 5 V.
(5) Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA =-40° C to 85° C for industrial use.
Vee = 5 V ± 10%, Te = -55 C to 125° C for military use.
(6) When the Turbo Bit is not set (non-turbo mode), an EP910 EPLD will enter standby
mode if no logic transitions occur for 100 ns (after the last transition).
(7) Measured with a device programmed as a 24-bit counter. Icc measured at 0° C.
(8) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated Clock inputs only. Pin 21 (high-voltage pin during programming) has a
maximum capacitance of 60 pF.
(9) See "Turbo Bit" earlier in this data sheet.
(10) Sample-tested only for an output change of 500 m V.
(11) The fMAX values represent the highest frequency for pipelined data.
0

Product
Availability

I Altera Corporation

Product Grade
Commercial Temp.

(0 0 C to 70° C)

Availability
EP910-30, EP91 0-35, EP91 0-40

Industrial Temp.

(-40 0 C to 85 0 C)

EP91 0-35, EP91 0-40

Military Temp.

(-55 0 C to 1250 C)

Consult factory

Page 273

Notes:

EP910A EPLD ;
Features

Preliminary
Information

o
o
o
o
o
o

Highest-performance, 24-macrocell Classic EPLD
Combinatorial speeds with tpD = 10 ns
Counter frequencies up to 100 MHz
Pipelined data rates up to 125 MHz
Fabricated on advanced O.8-micron CMOS EEPROM technology
Programmable I/O architecture with up to 36 inputs or 24 outputs
Pin-, function-, and programming file-compatible with Altera's EP910
and EP910T EPLDs
Programmable Clock option for independent docking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in a reprogrammable plastic 44-pin J-lead chip carrier (PLCC)
package (see Figure 24)

Figure 24. EP910A Package Pin-Out Diagram
Package outline not drawn to scale.

2 1 44 43 4241 40

I/O

EP910A
18192021 22232425262728

44-Pin

General
Description

I Altera Corporation

J-Lead

The Altera EP910A EPLD is a high-speed, EEPROM-based version of the
EP910 device. Fully compatible with EP910 devices, the EP910A offers
enhanced performance for existing EP910 designs with no additional
design modifications. For information on the device architecture, refer to
Figure 22 earlier in this data sheet.

Page 275

I EP910A EPLD

Preliminary Information

See Operating Requirements for Altera Devices in this data book.

Absolute Maximum Ratings
Symbol

Data Sheet

Parameter

Min

Conditions

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-250

250

lOUT

DC output current, per pin

-25

Power dissipation

1200

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

Input fall time

DC Operating Conditions

Notes (2), (3)
Max

Unit

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-D.3

0.8

V OH

High-level TTL output voltage

Symbol

Parameter

Conditions

IOH = -4 mA DC

Min

Typ

V IH

2.4

VOL

Low-level output voltage

IOL = 8 mA DC

Input leakage current

V I = Vee or GND

-10

loz

Tri-state output off-state current

V 0 = Vee or GND

-40

lee3

Vee supply current (active)

V I = Vee or GND, No load,
f = 1.0 MHz, Notes (4), (5)

CapaCitance
Symbol

120

0.45

180 (255)

Max

Unit

Note (6)
Parameter

Conditions
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT

Page 276

V
V

Min

Altera Corporation

I Data Sheet

Preliminary Information

AC Operating Conditions

EP910A EPLD

Note (3)
EP910A-10

Symbol

Parameter

Conditions

tpD1

Input to non-registered output

tpD2

liD input to non-registered output

tpzx

Input to output enable

tpxz

Input to output disable

C1 = 5 pF, Note (7)

tClA

Asynchronous output clear time

C1 = 35 pF

Symbol

EP91OA-10

Parameter

Conditions

EP910A-15

Min Max Min Max Min Max Unit

C1 = 35 pF

Global Clock Mode

EP910A-12

EP910A-15

Min Max Min Max Min Max Unit

f MAX

Maximum frequency

125

100.0

83.3

MHz

tsu

Input setup time

Input hold time

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

tCNT

Internal maximum frequency

Note (8)

Note (4)

Array Clock Mode
Symbol

Parameter

Conditions

MHz

100

83.3

71.4

EP91OA-10

EP910A-12

EP910A-15

Min Max Min Max Min Max Unit

tMAX
t ASU

125

100

83.3

MHz

Input setup time

tAH

Input hold time

tACH
t ACl

Clock high time

Clock low time

Maximum frequency

Note (8)

t AC01

Clock to output delay

t ACNT

Minimum clock period

t ACNT

Internal maximum frequency

I Altera Corporation

Note (4)

100

83.3

71.4

MHz

Page 277

Preliminary Information

EP910A EPLD

Data Sheet

Notes to tables:
(1)
(2)
(3)

(4)

(5)
(6)
(7)
(8)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee::::: 5 V ± 5%, TA::::: 0° C to 70° C for commercial use.
Vee::::: 5 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee::::: 5 V ± 10%, Tc = -55° C to 125° C for military use.
Measured with a device programmed as a 24-bit counter. Icc measured at 0° C.
Actual Icc should be verified during operation because this measurement is sensitive
to the operating conditions and the actual pattern in the device.
Numbers in parentheses are for military and industrial temperature versions.
Capacitance measured at 25° C. Sample-tested only. CLK2 (high-voltage pin during
programming) has a maximum capacitance of 20 pF.
Sample-tested only for an output change of 500 mY.
The fMAX values represent the highest frequency for pipelined data.

Figure 25 shows the maximum output drive characteristics of EP910A 1/0
pins.

Figure 25. EP910A Maximum Output Drive Characteristics
150

ci.
~ 120
~

.s
c

Vcc =5.0V
Room Temp.

::;
()

"5
a.
"5

..9

60
45
30

v0 Output Voltage (V)

Product
Availability

Page 278

Availability

Product Grade
Commercial Temp.

(0° C to 70° C)

EP91 OA-1 0, EP910A-12, EP910A-15

Industrial Temp.

(-40° C to 85° C)

EP910A-15

Military Temp.

(-55° C to 125° C)

Consult factory

Altera Corporation

EP910T EPLD
Features

o
o

o
o
o

High-performance, 24-macrocell Classic EPLD
Combinatorial speeds with tpD = 30 ns
Counter frequencies up to 33 MHz
Pipelined data rates up to 41 MHz
Programmable 1/ 0 architecture with up to 36 inputs or 24 outputs
Pin-, function-, and programming file-compatible with Altera's EP910
and EP910A EPLDs
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flip-flops, or
for combinatorial operation
Available in low-cost, one-time-programmable (OTP) plastic packages
(See Figure 26):
44-pin J-lead chip carrier (PLCC)
40-pin dual in-line package (PDIP)

Figure 26. EP910T Package Pin-Out Diagrams
Package outlines not drawn to scale.

4 3

2 1 44 43 4241 40

EP910-30T
18 19 20 21 2223 24 25 2627 28

44-Pin J-Lead

General
Description

I Altera Corporation

40-Pin DIP

Altera's EP910T EPLD is a low-cost, high-performance version of the
EP910 device. The EP910T operates in a turbo mode that is optimized for
high-speed applications. The Turbo Bit in the device, which is preset at the
factory, is permanently turned on. For information on EP910T architecture,
refer to Figure 22 earlier in this data sheet.

Page 279

I EP910T EPLD

Data Sheet I

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-250

250

lOUT

DC output current, per pin

-25

Power dissipation

1200

T STG

Storage temperature

No bias

--65

150

°C

TAMS

Ambient temperature

Under bias

--65

135

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

4.75

5.25

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Input rise time

Note (2)

100

Input fall time

100

Max

Unit

DC Operating Conditions
Symbol

Notes (3), (4)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VO H

High-level CMOS output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

lee3

Vee supply current (active)

= -4 mA DC
10H = -2 mA DC
10L = 4 mA DC
V I = Vee or GND
V 0 = Vee or GND
V I = Vee or GND, No load,
10H

2.4

3.84

-10
-10

0.45

IlA

115

Min

Max

Unit

Note (5)

Capacitance
Symbol

V I = Vee or GND, No load,
f = 1.0 MHz,Note (5)

Note (6)
Parameter

Conditions
= 0 v,f = 1.0 MHz
= 0 V, f = 1.0 MHz
= 0 V,f = 1.0 MHz

C IN

Input capacitance

V IN

C OUT

Output capacitance

V OUT

C eLK

Clock pin capacitance

V IN

I Page 280

Altera Corporation

IData Sheet

EP910T EPLD

AC Operating Conditions

Note (4)
EP910-30T

Symbol

Parameter

Conditions

Min

Max

Unit

t pD1

Input to non-registered output

tpD2

I/O input to non-registered output

tpzx
t pxz

Input to output enable
Input to output disable

C1 = 5 pF, Note (7)

tClR

Asynchronous output clear time

C1 = 35 pF

t,o

I/O input pad and buffer delay

C1 = 35 pF

Global Clock Mode

Symbol

EP910-30T

Parameter

Conditions

Min

Max

Unit

f MAX

Maximum frequency

tsu

Input setup time

Input hold time

ns
ns

Note (8)

41.7

MHz

tCH

Clock high time

tCl

Clock low time

tC01

Clock to output delay

tCNT

Minimum clock period

fCNT

Internal maximum frequency

33.3

Note (5)

Array Clock Mode

Symbol

MHz

EP910-30T

Parameter

Conditions

Min

Max

Unit

f MAX

Maximum frequency

33.3

MHz

t ASU

Input setup time

tAH

Input hold time

tACH
t ACl
t AC01

Clock high time

Clock low time

Clock to output delay

t ACNT

Minimum clock period

f ACNT

Internal maximum frequency

Note (8)

Note (5)

33.3

MHz

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for
periods less than 20 ns under no-load conditions.
For all Clocks: tR and tp = 100 ns.
Typical values are for TA = 25° C and Vee = 5 V.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Measured with a device programmed as a 24-bit counter. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for dedicated Clock inputs only. Pin 21
(high-voltage pin during programming) has a maximum capacitance of 60 pF.
Sample-tested only for an output change of 500 m V.
The fMAX values represent the highest frequency for pipelined data.

IAltera Corporation

Page 281

Data Sheet

EP910T EPLD

Figure 27 shows the maximum output drive characteristics of EP910T I/O
pins and typical supply (Icd current versus frequency for the EP910T
EPLD.

Figure 27. EP910T Maximum Output Drive Characteristics & Icc vs. Frequency
100 . - - - - - - - - - - - - - - - - - : : : : : ; . . ,

ci.
~

E-

Turbo
ci.

'E
~

:;
"S
0"S

..9

E-

Vec =5.0V
TA = 25° C

()

Vee = 5.0 V
TA = 25° C

U
«

1.0

()

...!:?

0.1
0

1 KHz

Product
Availability

Page 282

10 KHz 100 KHz 1 MHz 10 MHz 40 MHz

Maximum Frequency

V0 Output Voltage (V)

Product Grade

Availability

Commercial Temp.

(0° C to 70° C)

EP910-30T

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

Altera Corporation

[
Features

EP1810 EPLD
o

High-performance, 48-macrocell Classic EPLD
Combinatorial speeds with tpD = 20,25,35, and 45 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Programmable I/O architecture with up to 64 inputs or 48 outputs
Pin-, function-, and programming file-compatible with Altera's
EP1810T and EP1810 MIL-STD-883-compliant devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in 68-pin windowed ceramic and one-time-programmable
plastic packages (see Figure 28):
Pin-grid array package (ceramic PGA only)
J-Iead chip carrier GLCC and PLCC)

o
o

Figure 28. EP1810 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Table 2 in this data sheet for PGA package
pin-out information. Windows in ceramic packages only.

I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
ClK1/INPUT
VCC
ClK2!INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O

68-Pin PGA

General
Description

I Altera Corporation

10 11

o
EP1810

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
ClK4/INPUT
VCC
ClK3/INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O

~~~~~~~~~~~~~~~~~
(!)

68-Pin J-Lead

The Altera EP1810 EPLD offers LSI density, TTL-equivalent speed, and
low power consumption. The EP1810 has 48 macrocells, 16 dedicated
input pins, and 481/ a pins (see Figure 29). The EP1810 is divided into four
quadrants, each containing 12 macrocells. Of the twelve macrocells in each
quadrant, 8 have quadrant feedback and are "local" macrocells. (See
"Feedback Selection" earlier in this data sheet for more information.) The
remaining 4 macrocells in the quadrant are" global" macrocells. Both local
and global macrocells can access signals from the global bus, which consists

Page 283

Data Sheet

EP1810 EPLD

Figure 29. EP1810 Block Diagram
Numbers in parentheses are for J-/ead packages. Numbers without parentheses are for PGA packages.
Quadrant A
2 (F1)
3 (G2)
4(G1)
5 (H2)
6(H1)
7 (J2)
8 (J1)
9 (K1)
10 (K2)
11 (L2)
12 (K3)
13 (L3)

7<::1--

~I-~I-~I-~I--

MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5

~r----

MACROCELL7
MACROCELL8

. : IM£fWCELt.9,·
.....

~~
~~

·~~RQdELt.10·.,';

:M"Cflqq~·l1~'
J~

INPUT

17 (L5)

INPUT/CLK1

::=.

19 (L6)

INPUT/CLK2 ::::::-

20 (K7)

INPUT

<::

21 (L7)

INPUT

<::

26 (L10)
27 (K10)
28 (K11)
29 (J10)
30 (J11)

7<::

....

·'MAQRp\"

MACROCELL20

32 (H11)

:::..::: ~ _

MACROCELL21
MACROCELL22

..
..

33 (G10)

MACROCELL23

34 (G11)

:::..::: -

MACROCELL24

31 (H10)

60 (A2)

~~
~~

59 (A3)

f.....-:::..:::

64 (C1)
63 (C2)

58 (83)
57(A4)

INPUT

56 (84)

~ INPUT

55 (A5)

INPUT

54 (85)

.....

<::

.....

~ INPUT/CLK4 53 (A6)

.....

c:::J

.....

~ ~

'E
~

.......,.....

~o
~
~ ......-----

++. . '---- +- _
...J

INPUT/CLK3 51 (A7)
INPUT

50 (87)

~ INPUT

49 (A8)

INPUT

48 (88)

....

..r--..
§ n~' ~[::~: ~~
,r

,. . -

~ ~'§§~J_'~~
::::"":

61 (82)

'.~~

....

66 (01)

"
<::

Quadrant B

25 (L9)

<::

::=.

c=:::
INPUT c=:::

~>=!==:'.

r---~

67 (E2)

16 (K5)

24 (K9)

62 (81)

MACROCELL41

M"eROCEI.l39
MACAocEt;t38 .
~A<;:;

47 (A9)
46 (89)
45 (A10)
44 (810)
43 (811)
42 (C11)
41 (C10)

r---- ~::::"":

40 (011)

~:::..:::~

39 (010)

,---- ::::"":

38 (E11)

r---r----

37 (E10)

36 (F11)

Global Macrocells
Local Macrocells

of the true and complement forms of the dedicated inputs and the true and
complement forms of the feedbacks from the global macrocells.
The EP1810 also has four dedicated inputs (one in each quadrant) that can
be used as quadrant Clock inputs. If the dedicated input is used as a Clock
pin, the input feeds the Clock input of all registers in that particular
quadrant.
Page 284

Altera Corporation

IData Sheet

EP1810 EPLD

Figure 30 shows the output drive characteristics of EP1810 I/O pins and
typical supply current (Icd versus frequency for the EP1810 EPLDs.

Figure 30. EP1810 Maximum Output Drive Characteristics & Icc vs. Frequency
Output Drive Characteristics of EP181 0-35 &
EP181 0-45 EPLDs

Output Drive Characteristics of EP181 0-20
and EP1810-25 EPLDs
200

c.i.

«
g

c.i.

150

«
g

::;

o
"5
0o"5

Vee = 5.0 V
= 25° C

~ 100

::;

Vcc = 5.0 V
= 25° C

"5
0"5

~~--

0.45 1

V0 Output Voltage (V)

ICC vs. Frequency of EP1810 EPLDs

Turbo Mode

100

c.i.

«g

Vee

·u
«

= 5.0 V
= 25° C

1.0

()

.2
0.1

10 kHz

100 kHz

1 MHz

10 MHz

60 MHz

Maximum Frequency

I Altera Corporation

Page 285

Data Sheet I

EP1810 EPLD

Absolute Maximum Rating
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Max

Min

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-300

300

lOUT

DC output current, per pin

-25

Power dissipation

TSTG

Storage temperature

No bias

Ambient temperature

Under bias

TAMS

Recommended Operating Conditions
Symbol
vee

1500

-65

150

°C

-65

135

°C

Min

Max

Unit

Note (2)
Conditions

Parameter

4.75 (4.5) 5.25 (5.5)

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

tR
tF

Input rise time

Note (3)

Max

Unit
V

Input fall time

DC Operating Conditions
Symbol

Note (2), (4), (5)

Parameter

Conditions

Speed
Grade

Min Typ

V IH
V IL

High-level input voltage

2.0

Vee + 0.3

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

V OH

High-level CMOS output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

lee2

Vee supply current

= -4 mA DC
10H = -2 mA DC
10L = 4 mA DC
V I = Vee or GND
V 0 = Vee or GND
V I = Vee or GND, 10 = 0,

-20, -25

150

(non-turbo, standby)

Notes (6), (7)

-35, -45

150

= Vee or GND, No load,
= 1.0 MHz, Note (7)
V I = Vee or GND, No load,
f = 1.0 MHz, Note (7)

-20, -25

-35, -45

30 (40)

-20, -25

180

225 (250)

-35, -45

100

180 (240)

Vee supply current
(non-turbo, active)

lee3

Vee supply current
(turbo, active)

Page 286

2.4

10H

V
V

3.84
-10
-10

0.45

Altera Corporation

I Data Sheet
Capacitance

EP1810 EPLD

Note (8)

Symbol

Parameter

Conditions
=

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT

CClK

Clock pin capacitance

V IN

0 V, f

AC Operating Conditions: EP1810-20, EP1810-25

Symbol

1.0 MHz

Conditions
C1

Unit

Note (5)
EP1810-20

Parameter

Max

1.0 MHz

EP1810-25

Non-Turbo
Adder

Min Max Min Max

Note (9)

Unit

t pD1

Input to non-registered output

tpD2

1/0 input to non-registered output

tsu

Global clock setup time

Global clock hold time

35 pF

tC01

Global clock to output delay

tCH

Global clock high time

tCl

Global clock low time

t ASU

Array clock setup time

ns
ns

35 pF

tAH

Array clock hold time

t AC01

Array clock to output delay

tCNT

Minimum global clock period

fCNT

Maximum internal frequency

Note (7)

f MAX

Maximum clock frequency

Note (10)

Symbol

Parameter

Conditions

MHz

62.5

MHz

EP1810-20

EP1810-25

Non-Turbo
Adder

Min Max Min Max

Note (9)

35 pF

Internal Timing Parameters

Min

1.0 MHz

External Timing Parameters

Unit

t,N

Input pad and buffer delay

tlO

1/0 input pad and buffer delay

t LAO
too
tzx
txz

Logic array delay
Output buffer and pad delay

C1 = 35 pF

C1 = 5 pF, Note (11)

Output buffer enable delay
Output buffer disable delay
Register setup time

t,C
t,CS
t FO
tCLR

Array clock delay

tsu

10
10

Global clock delay

Feedback delay

-25

Altera Corporation

Page 2871

I EP1810 EPLD

Data Sheet

AC Operating Conditions: EP1810-35, EP1810-45

Note (5)

External Timing Parameters
Symbol

EP1810-35

Conditions

Parameter
C1

EP1810-45

Non-Turbo
Adder

Min Max Min Max

Note (9)

35 pF

Unit

30
30

35
40

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl

Global clock low time
Array clock setup time

15
11

0
30

t ASU

12
10

tAH

Array clock hold time

t AC01

Array clock to output delay

tCNT

Minimum global clock period

tCNT

Maximum internal frequency

Note (7)

28.6

22.2

0
0

MHz

tMAX

Maximum clock frequency

Note (10)

33.3

MHz

EP1810-35

EP1810-45

Non-Turbo
Adder

Min Max Min Max

Note (9)

tIN
t/O
tLAD
too
tzx
txz
tsu
tH
t,C
t,CS
tFD
tCLR

35 pF

35
35

Internal Timing Parameters
Symbol

Parameter

Conditions

Unit

Input pad and buffer delay

I/O input pad and buffer delay

19
9

28
11

30
0

ns
ns

Logic array delay
Output buffer and pad delay

= 35 pF

Output buffer enable delay
Output buffer disable delay

C1 = 5 pF, Note (11)

10
28

0
30

Global clock delay

Feedback delay

-30

Page 288

Array clock delay

Altera Corporation

I Data Sheet

EP1810 EPLD

Notes to tables:
(1)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to
-2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions.
(2) Numbers in parentheses are for military and industrial temperature versions.
(3) For all Clocks: tR and tF = 100 ns (50 ns for military and industrial temperature
versions).
(4) Typical values are for TA = 25° C and Vee = 5 V.
(5) Operating conditions: Vee = 5 V ± 5%, TA =0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee = 5 V ± 10%, Tc = -55° C to 125° C for military use.
(6) When the Turbo Bit is not set (non-turbo mode), an EP910 EPLD enters standby
mode if no logic transitions occur for 100 ns (after the last transition).
(7) Measured with a device programmed as four 12-bit counters. Icc measured at 0° C.
(8) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for
dedicated Clock inputs only. Pin 21 (high-voltage pin during programming) has a
maximum capacitance of 60 pF.
(9) See "Turbo Bit" earlier in this data sheet.
(10) Sample-tested only for an output change of 500 m V.
(11) The fMAX values represent the highest frequency for pipelined data.

Product
Availability

Product Grade
Commercial Temp.

(0° C to 70° C)

Availability
EP1810-20, EP1810-25, EP1810-35,
EP1810-45

Industrial Temp.

(-40° C to 85° C)

EP1810-25, EP1810-45

Military Temp.

(-55° C to 125° C)

EP1810-45, Note (1)

Note:
(1)

I Altera Corporation

Only military-temperature-range devices are listed. MIL-STD-883-compliant product
specifications are provided in "EP1810 MIL-STD-883-Compliant EPLD" in this data
sheet and in Military Product Drawings (MPDs). However, only MPDs should be
used to prepare Source Control Drawings (SCDs). MPDs are available from Altera
Marketing at (408) 894-7000.

Page 289

I EP1810 EPLD

Pin-Out
Information

Data Sheet

Table 2 provides pin-out information for EP1810 devices in the PGA
package.

Table 2. EP1810 PGA Pin-Outs

I Page 290

Function

I/O

F10

GNO

I/O

B10

I/O

F11

I/O

INPUT

110

B11

I/O

110

VCC

INPUT

I/O

INPUT

CLK4/INPUT

I/O

G10

I/O

INPUT
I/O

CLK3/INPUT

C10

I/O

G11

I/O

INPUT

C11

I/O

K10

I/O

K11

I/O

A10

I/O

H10

I/O

010

I/O

H11

I/O

011

I/O

INPUT

I/O

CLK1/INPUT

INPUT

I/O

J10

I/O

CLK2/INPUT

INPUT

E10

I/O

J11

I/O

INPUT

VCC

E11

I/O

INPUT

I/O

INPUT

GNO

I/O

L10

I/O

Altera Corporation

EP1810T EPLD
Features

o
o
o
o
o

High-performance, 48-macrocell Classic EPLD
Combinatorial speeds with tpD = 20 ns, 25 ns, and 35 ns
Counter frequencies up to 50 MHz
Pipelined data rates up to 62.5 MHz
Programmable I/O architecture with up to 64 inputs or 48 outputs
Pin-, function-, and programming file-compatible with Altera's EP1810
and EP1810 MIL-STD-883-compliant devices
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in 68-pin one-time-programmable (OTP) plastic J-Iead chip
carrier (PLCC) (see Figure 31)

Figure 31. EP1810T Package Pin-Out Diagram
Package outline not drawn to sea/e.

1/0
1/0
1/0
1/0
INPUT
INPUT
INPUT
ClK1/1NPUT
VCC
ClK2IINPUT
INPUT
INPUT
INPUT

60
59
58
57
56
55
54
53

1/0
1/0
1/0

vee

51
50

ClK3/INPUT
INPUT
INPUT
INPUT
1/0
1/0
1/0
1/0

49
48

110

EP1810-xxT

1/0
1/0
1/0
1/0
INPUT
INPUT
INPUT
ClK4/INPUT

45
44

~~~~~~~~~~~~~~~~~
(!)

68-Pin J-Lead

General
Description

Altera Corporation

The Altera EP1810T EPLD is a low-cost, high-performance version of the
EP1810 device. The EP1810T operates in a turbo mode that is optimized for
high-speed applications. The Turbo Bit in the device, which is preset at the
factory, is permanently turned on. For information on EP1810T architecture,
refer to Figure 29 earlier in this data sheet.

Page 291

I EP1810T EPLD

Data Sheet

See Operating Requirements for Altera Devices in this data book.

Absolute Maximum Ratings

Min

Max

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

13.5

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-300

300

rnA

lOUT

DC output current, per pin

-25

Power dissipation

Symbol

Conditions

Parameter

Unit

rnA

1500

T STG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Min

Max

Unit

4.75

5.25

V
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

vee

Supply voltage

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

tR
tF

Input rise time

Note (2)

Max

Unit

Input fall time

DC Operating Conditions
Symbol

Notes (3), (4)

Parameter

Conditions

Speed
Grade

Min Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

VO H

High-level TTL output voltage

V OH

High-level CMOS output voltage

VOL

Low-level output voltage

= -4 rnA DC
10H = -2 rnA DC
10L = 4 rnA DC
V I =Vee or GND
V 0 =Vee or GND
V I =Vee or GND, No load,

2.4

10H

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current
(standby)

Note (5)

lee3

Vee supply current

(turbo, active)

-35T

=Vee or GND, No load,
= 1.0 MHz, Note (5)

3.84

V
0.45

-10

IlA

-10

IlA

-20T, -25T

180

250

rnA

-35T

120

215

rnA

-20T, -25T

180

250

rnA

120

215

rnA

Max

Unit

Capacitance Note (6)
Symbol

Conditions

Parameter

= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz

Min

C IN

Input capacitance

V IN

C OUT

Output capacitance

V OUT

C eLK

Clock pin capacitance

V IN

Page 292

Altera Corporation

I Data Sheet

EP1810T EPLD

AC Operating Conditions

Note (4)

External Timing Parameters

Symbol

EP1810-20T EP1810-25T EP1810-35T

Parameter

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

Conditions

Min Max Min Max Min Max Unit

C1 = 35 pF

tsu

Global clock setup time

ns
ns

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCl

Global clock low time

t ASU

Array clock setup time

tAH
t AC01

Array clock hold time

Array clock to output delay

tCNT

Minimum global clock period

fCNT
f MAX

Internal maximum frequency

Note (5)

28.6

MHz

Maximum frequency

Note (7)

62.5

MHz

C1 = 35 pF

Internal Timing Parameters

Symbol
tIN
t lO
tLAD
too
tzx
txz
tsu
tH
tIC
tICS
tFD
tCLR

C1 = 35 pF

ns
ns

EP1810-20T EP1810-25T EP1810-35T

Parameter

Conditions

Min Max Min Max Min Max Unit

Input pad and buffer delay

1/0 input pad and buffer delay

Logic array delay
Output buffer and pad delay

= 35 pF

= 5 pF, Note (8)

Output buffer enable delay
Output buffer disable delay
Register setup time

Array clock delay

Global clock delay

ns
ns

Feedback delay

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for
periods less than 20 ns under no-load conditions. For EP1810-20T and EP1810-25T EPLDs: maximum Vpp is 14.0 V.
For EP181O-20T and EP1810-25T Clocks: tR and tF = 20 ns.
Typical values are for TA = 25° C and Vee =5 V.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Measured with a device programmed as four 12-bit counters. Icc measured at 0° C.
Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for dedicated Clock inputs only. For
EP181O-35T EPLDs: Pin 19 (high-voltage pin during programming) has a maximum capacitance of 160 pF.
The fMAX values represent the highest frequency for pipelined data.
Sample-tested only for an output change of 500 mV.

I Altera Corporation

Page 293

I EP1810T EPLD

Data Sheet

Figure 32 shows the output drive characteristics of EP1810T I/O pins and
typical supply current (Icd versus frequency for the EP1810T EPLD.

Figure 32. EP1810T Maximum Output Drive Characteristics &Icc vs. Frequency
Output Drive Characteristics of
EP1810-20T & EP1810-25T EPLDs

Output Drive Characteristics of EP181 0-35T EPLDs

200

ci.

ci.
~

~ 150

<
g
c

()

~
~

= 5.0 V

= 25° C

()

"5
a.
"5

I"""""'I'!"'--_ _

0.45

Vee

Vee = 5.0 V
TA = 25° C

~ 100
~

"5
0.
"5
o

<
g

0.45 1

Va Output Voltage (V)

Icc VS. Frequency of All EP1810T EPLDs

100 c-

Turbo Mode

ci.
~

<
E-

10-

Vee =5.0V

·u«>

TA = 25° C
1.0 c-

()

.2
0.1 f-

10 kHz

100 kHz

1 MHz

10 MHz

60 MHz

Maximum Frequency

Product
Avai labil ity
Page 294

Product Grade

Availability

Commercial Temp.

(0° C to 70° C)

EP1810-20T, EP1810-25T, EP1810-35T

Industrial Temp.

(-40° C to 85° C)

Consult factory

Military Temp.

(-55° C to 125° C)

Consult factory

Altera Corporation

EP1810 MIL-STD-883-Compliant EPLD
Features

o
o
o
o
o

High-performance, 48-macrocell Classic EPLD
Combinatorial speeds with tpD = 45 ns
Counter frequencies up to 22.2 MHz
Pipelined data rates up to 33.3 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
Pin-, function-, and programming file-compatible with Altera's EP1810
and EP1810T devices
Programmable Clock option for independent docking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in 68-pin windowed ceramic pin-grid array (PGA) packages
(see Figure 33):

Figure 33. EP1810 Package Pin-Out Diagram
Package outline not drawn to scale. See Table 3 in this data sheet for PGA package
pin-out information.

10 11

68-Pin PGA

General
Description

Altera Corporation

The Altera EP1810 MIL-STD-883-compliant EPLD offers LSI density,
TTL-equivalent speed, and low power consumption. This device is a
version of the EP1810 that complies with the military standard operating
requirements listed in MIL-STD-883B. For information on the device
architecture, output drive characteristics, and supply current versus
frequency graphs, refer to Figures 29 and 30 earlier in this data sheet.

Page 2951

I EP1810 MIL-STD-883-Compliant EPLD
Absolute Maximum Ratings
Symbol

Data Sheet

See Operating ReqUirements for Altera Devices in this data book.
Conditions

Parameter

Min

Max

Unit
V

vee

Supply voltage

-0.5

7.0

Vpp

Programming supply voltage

-0.5

13.5

DC input voltage

Vee + 0.5

I MAX

DC Vee or GND current

-0.5
-400

400

lOUT

DC output current, per pin

-25

Power dissipation

2000

With respect to GND

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-55

125

°C

Junction temperature

Under bias

150

°C

Max

Unit
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

vee

Supply voltage

4.5

5.5

Input voltage

Vee

Output voltage

Vee

Case temperature

-55

125

°C

Input rise time

Input fall time

50
50

DC Operating Conditions
Symbol

For military use

Note (1)
Min

Max

Unit

V IH

High-level input voltage

Parameter

Conditions

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VO H
VOL

10H = -4 mA DC, Note (2)

2.4

High-level CMOS output voltage

10H = -2 mA DC, Note (2)

3.84

Low-level output voltage

10L = 4 mA DC, Note (2)

V
V
V

Input leakage current

VI = VeeorGND

-10

0.45
10

loz

Tri-state output off-state current

Vo = VeeorGND

-10

IJ.A

lee1

Vee supply current

V I = Vee or GND, No load, Note (3)

900

IJ.A

Vee supply current

VI = Vee or GND, No load, f = 1.0 MHz,

(non-turbo, active)

Notes (3), (4)

240

V
IJ.A

(non-turbo, standby)
lee2

lee3

V ce supply current

VI = Vee or GND, No load, f = 1.0 MHz,

(turbo, active)

Note (4)

I Page 296

Altera Corporation

EP1810 MIL-STD-883-Compliant EPLD

Data Sheet

Capacitance

Note (5)

Symbol

Parameter

Conditions
=

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT

CClK

Clock pin capacitance

V IN

AC Operating Conditions

0 V, f

Min

1.0 MHz

Max

Unit

Max

Unit

Note (1)

External Timing Parameters
Symbol

Parameter

t pD1

Input to non-registered output

t pD2

1/0 input to non-registered output

Conditions
C1

Min

35 pF, Notes (6), (7)

tsu

Global clock setup time

Notes (6), (7)

Global clock hold time

Note (4)

tC01

Global clock to output delay

C1 = 35 pF, Note (7)

ns
ns

0
25

tCH

Global clock high time

tCl

Global clock low time

t ASU

Array clock setup time

Notes (6), (7)

tAH

Array clock hold time

Notes (6), (7)

t AC01

Array clock to output delay

tCNT

Minimum global clock period

Note (7)

fCNT

Maximum internal frequency

Note (8)

22.2

f MAX

Maximum clock frequency

Notes (6), (7), (9), (10)

33.3

tpzx

Input to output enable

Notes (6), (7)

t pxz

Input to output disable

35 pF, Notes (6), (7)

5 pF, Notes (6), (7), (11), (12)

ns
MHz
MHz

Notes to tables:
(1)

Screening and characterization of AC delay parameters are conducted at 10 MHz or less. Operating conditions:
Vcc =5VDC±10%, Tc =-55°Cto125°C
(2) Tested at 25° C and 125° Conly.
(3) Tested at 25° Conly.
(4) Tested with non-output loading using a data pattern specified by the device manufacturer. Data path is correlated to
four 12-bit counters.
(5) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for dedicated inputs only. Pin 13 (high
voltage pin during programming) has a capacitance of 50 pF.
(6) All array-dependent delays are specified for an XOR pattern. This pattern includes two product terms and two pure
inputs; all other product terms in the macrocell are held low by one EPROM pull-down. Other patterns may result
in longer delays. Delays for patterns involving only one product term (such as t pxz) are specified for an xOR-like
pattern in which only one pure input switches at a time.
(7) When in non-turbo mode, a non-turbo adder of 30 ns maximum (40 ns for tASU ) is applied. Parameters may not be
tested in non-turbo mode, but are guaranteed to the limits specified. Devices operating in non-turbo mode require
one input or I/O transition to guarantee that the device will enter the correct power-up state.
(8) Not tested directly, but guaranteed by testing tCNT or t ACNT.
(9) The fMAX values represent the highest frequency for pipelined data.
(10) Not tested directly, but derived from tsu.
(11) May not be tested, but is guaranteed to the limits specified in the table under Absolute Maximum Ratings.
(12) Sample tested only for an output change of 500 mY.

Altera Corporation

Page

29!]

I EP1810 MIL-STD-883-Compliant EPLD
Product
Availability

Data Sheet

Availability

Product Grade
MIL-STO-883-Compliant

EP1810 MIL-STO-883, Note (1)

(-55° C to 125° C)

Note:
(1)

Pin-Out
Information

Table 3 provides pin-out information for the EP1810 Military-STD-883Compliant EPLD.
Table 3. EP1810 MIL-STD-883-Comp/iant PGA Pin-Outs

Page 298

Function

Function
INPUT

I/O

F10

GNO

1/0

B10

1/0

F11

1/0

INPUT

1/0

B11

1/0

VCC
INPUT

INPUT

1/0

CLK4/1NPUT

1/0

G10

1/0

INPUT

CLK3/1NPUT

C10

I/O

G11

I/O

1/0

INPUT

C11

1/0

K10

1/0

K11

1/0

A10

1/0

H10

1/0

I/O

1/0

010

1/0

H11

1/0

I/O

011

1/0

INPUT

1/0

CLK1/1NPUT

INPUT

1/0

J10

1/0

CLK2/1NPUT

INPUT

E10

1/0

J11

1/0

INPUT

VCC

E11

1/0

INPUT

1/0

I/O

INPUT

GNO

I/O

L10

1/0

Altera Corporation

Contents
I

August 1993

Section 6

3.3-Volt
3.3-Volt Programmable Logic Devices ....................................................... 301
EP7032V EPLD ................................................................................... 303
EP8282V EPLD ................................................................................... 313

Altera Corporation

Page 2991

3.3-Volt Programmable
Logic Devices
I August 1993, ver. 1

Introduction

Data Sheet

Many circuit designs demand not only higher performance and higher
integration, but also lower power consumption. This requirement is
especially important in electronics products such as notebook computers
and personal communicators, which must consume less power to extend
the life of a battery. The recent proliferation of 3.3-V microprocessors and
support hardware also illustrate the need for low-power Ies.
Altera has long been a pioneer in providing low-power programmable
logic. The Classic family provided the first "zero-power" EPLDs, and
MAX 7000 devices offered the first user-programmable power-saver mode.
Altera remains at the forefront of the low-power programmable logic field
by offering new 3.3-V programmable logic devices. This data sheet provides
information on Altera's 3.3-V devices:

o
o

I Altera Corporation

EPM7032V (MAX 7000 device family)
EPF8282V (FLEX 8000 device family)

Page 301

Notes:

EPM7032V EPLD
Features ...

Preliminary
Information

o
o
o
o
o
o
o

3.3-V version of the popular EPM7032 EPLD
Combinatorial speeds with tpD = 12 ns
Clock frequencies up to 90.9 MHz
Innovative power-saving features
30% to 50% power savings over 5-V operation
Power-down mode controlled by a power-down pin to allow
zero power consumption during periods of inactivity
Programmable power-saver mode for up to 50% power reduction
during active operation, configurable for each macro cell
Advanced 0.8-micron CMOS EEPROM technology
Programmable II 0 architecture allowing up to 36 inputs or 32 outputs
32 advanced macrocells to efficiently implement registered and
complex combinatorial logic
Configurable expander product-term distribution allowing up to 32
product terms in a single macrocell
Programmable registers configurable as D, T, JK, and SR flipflops
with individual Clear, Preset, Clock, and Clock Enable controls
Independent clocking of all registers from array or global Clock signals
Available in 44-pin plastic packages (see Figure 1):
J-Iead chip carrier (PLCC)
l.O-mm thin quad flat pack (TQFP)

Figure 1. EPM1032V Package Pin-Out Diagrams
Package outlines not drawn to sea/e.

Pin 1
6

5 4

1 44 4342 41 40
1/0

1
1/0

1/0

GND

1/0

vee

110
110

1/0

1/0
1/0

1/0

EPM7032V

vee

EPM7032V

1/0

GND

1/0
1/0 -'----n-"--..."....,rr-rr-n-......r-rr-n-,,.-!

1/0

1819202122232425262728

~ ~ ~ ~ ~
(!l

44-Pin J-Lead

Altera Corporation

~ ~ ~ ~ ~

Pin 23

44-Pin QFP

Page 3031

IEPM7032V EPLD

... and More
Features

Data Sheet

o Pin-, function-, and programming-file-compatible with 5-V EPM7032
devices

o Software design support featuring Altera's MAX+PLUS II development
system on PC, Sun SPARCstation, and HP 9000 Series 700 platforms

o Programming support from Altera's Master Programming Unit (MPU)
or programming hardware from other manufacturers

General
Description

The general characteristics of the EPM7032V are identical to those of the
5-V EPM7032, with the exceptions noted in this data sheet. See the
MAX 7000 Programmable Logic Device Family Data Sheet in this data book for
complete information on MAX 7000 EPLDs.
The EPM7032V is a high-performance MAX 7000 EPLD that meets the low
power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment. Fabricated on
a 0.8-micron EEPROM technology, the EPM7032V provides in-system
speeds up to 125 MHz and propagation delays of 12 ns. Its architecture
supports 100% TTL emulation and can integrate SSI, MSI, and custom
logIC functions. The EPM7032V can replace multiple 20- and 24-pin PLDs.
It is available in 44-pin reprogrammable PLCC or TQFP packages and can
accommodate designs with up to 36 inputs and 32 outputs.
The EPM7032V provides a unique power-down mode that is ideal for
power-sensitive applications. A dedicated power-down pin allows the
device to be powered down to a near-zero-power consumption level.
While in power-down mode, all intemallogic and external I/O signals of
the EPM7032V maintain the state just prior to the assertion of the powerdown pin. When this pin is released, the device resumes normal operation.
The EPM7032V also provides programmable speed and power
optimization. Speed-critical portions of a design can run at high speed and
full power, while the remainder runs at reduced speed and low power.
This feature enables the user to configure individual macrocells to operate
at up to 50% less power while adding only a nominal timing delay.

Power
Management

The 3.3-V operation of the EPM7032V offers power savings of 30% to 50%
over the 5-V operation of the EPM7032. Power-saving features of the
EPM7032V include a programmable power-saver mode and a powerdown mode.

Programmable Speed/Power Control
All MAX 7000 devices, including the EPM7032V, offer a power-saver
mode that supports low-power operation across user-defined signal paths
or the entire device. This feature can reduce total power dissipation by up
to 50%, since most logic applications require only a fraction of all gates to
operate at maximum frequency.

I Page 304

Altera Corporation

I Data Sheet

EPM7032V EPLD

The designer can program each individual macrocell in the EPM7032V for
either high-speed (Turbo Bit on) or low-power (Turbo Bit off) operation.
As a result, speed-critical paths in the design can run at high speed, while
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal additional timing delay (tLPA) for the t LAD , t LAC , tIC'
tACIt tEN' and t SEXP parameters.

Power-Down Mode
The EPM7032V provides a power-down mode that allows the device to
consume near-zero power (typically 50 J.lA). The power-down mode is
controlled externally by the dedicated power-down pin (PDn). When PDn is
asserted (Le., brought to ground), the power-down sequence latches all
inputs, internal logic, and output pins of the EPM7032V, preserving their
present state. Output pins maintain their present low, high, or tri-state
(high-impedance) value while in power-down mode. Once in powerdown mode, any or all of the inputs, including Clocks, can be toggled
without affecting the frozen state of the device. Since internal latches are
used to ensure that the proper state exists during power-down mode, the
external inputs and Clocks must meet certain setup and hold time
requirements. See Figure 2 and the "Power-Down Timing Parameters and
Chip-Enable Timing Parameters" tables, later in this data sheet.

Figure 2. Power-Down Mode Switching Waveforms
The switching waveforms for the EPM7032V are identical to those of the 5-V EPM7032 in
all modes except for the additional power-down mode shown here.
tR & tF < 3 ns. Inputs are driven at 3 V for a logic high and a V for a logic low. All timing
characteristics are measured at 1.5 V.
Inputs or
I/O Inputs

==1

Data Valid 1

X Data Valid 1 X

't
"t
! - ISUPD-!-; IHPD

i, t pD1 ,

Combinatorial
Output

~: ,

1:::

Combinator~1

! tsu !tGCSUPD! tGCHPD

:---:-:~

Global or
Array Clock

: t ACSUPD : t ACHPD

:....-tco-+~

Registered
Output

I Altera Corporation

--------~X~'

Data Valid 2

tISTCE~!
,!
:_tCE_'
:' tpD1
Output Data 1

Output Data 2

: - - - t C E - : t u:

!~:

t ACSTCE :

! tco

________D_ru_a_1________________~~

Page 305

I EPM7032V EPlD

Data Sheet

When the PDn signal is brought high, the device is enabled, and the
combinatorial outputs respond to the present input conditions within the
specified chip-enable delay (tCE )' Registered outputs respond to Clock
transitions within tCE' Clocking the device during the chip-enable sequence
can cause the data to change internal to the chip if a Clock transition occurs
during certain intervals of the chip-enable or chip-disable sequences. All
Clocks should be gated to prevent Clock transitions during the Clock setup
time (tGCSUPD or tACSUPD) and during the chip-enable setup time (tGCSTCE
or tAcsTCE)' as shown in Figure 2. All registers in the EPM7032V provide
Clock Enable control for simple access to disable Clocks. If output signals
must be frozen in a high-impedance state during power-down, the
associated Output Enable signal must be asserted, the system Clock must
be removed, and the PDn pin must be asserted. To reactivate the device, the
sequence is reversed. For some systems, it may be more appropriate to
switch the order of the Clock and Output Enable controls.
All power-down/ chip-enable timing parameters are computed from
external input or I/O pins, with the macrocell Turbo Bit turned on, and
without the use of parallel expanders. For macrocells in low-power mode
(Turbo Bit off), the low-power adder tLPA must be added to the powerdown/ chip-enable timing parameters, which include the data paths tLAD,
t LAC ' tIC' tACIt tACH' and t SEXP ' For macrocells that use parallel expanders,
tpEXP must be added. For data or Clock paths that use more than one logic
array delay, the worst-case data or Clock delay also must be added to the
respective power-down! chip-enable parameters. Actual worst-case timing
for data and Clock paths can be calculated with the MAX+PLUS II Simulator
or Timing Analyzer, or other industry-standard CAE verification tools.

Design
Security

All MAX 7000 devices, including the EPM7032V, contain a programmable
Security Bit that controls access to the data programmed into the device.
When this bit is programmed, a proprietary design implemented in the
device cannot be copied or retrieved. This feature provides a high level of
design security, since programmed data within EEPROM cells is invisible.
The Security Bit that controls this function, as well as all other program
data, is reset when the device is erased.

Generic Testing

The EPM7032V is functionally tested and guaranteed. Complete testing of
each programmable EEPROM bit and all internal logic elements ensures
100% programming yield. AC test measurements are taken under the
conditions equivalent to those shown in Figure 3.
Test patterns can be used and then erased in the EPLD during early stages
of the device production flow.

I Page 306

Altera Corporation

I Data Sheet

EPM7032V EPLD

Figure 3. EPM7032V AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous
transitions of multiple outputs should
be avoided for accurate measurement.
Threshold tests must not be performed
under AC conditions. Large-amplitude,
fast ground-current transients normally
occur as the device outputs discharge
the load capacitances. When these
transients flow through the parasitic
inductance between the device ground
pin and the test system ground, it can
create significant reductions in
observable noise immunity.

.-----VCC

to Test
System

C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns

Figure 4 shows the output drive characteristics of EPM7032V I/O pins.

Figure 4. Typical EPM7032V Output Drive Characteristics
Vcc =3.3V
Room Temp.

ci.
~
;;(

.s
~

IOL

()

S
a.
S

..9

v0 Output Voltage (V)

I Altera Corporation

Page 3071

IEPM7032V EPLD

Data Sheet

Figure 5 shows typical supply current versus frequency for the EPM7032V.

Figure 5. EPM7032V Icc vs. Frequency
Icc is calculated with the following equation:
Icc = (0.98 x MCTON) + (0.42 x MC TOFF ) + [(0.006 x MC) x
fMAX]
The parameters for this equation are:
MCTON = number of macroce/ls used with Turbo Bit on
MC TOFF = number of macrocells used with Turbo Bit off
MC
total number of macrocells used in the design
(MC TON + MC TOFF)
fMAX
highest Clock frequency to the device
This measurement provides an Icc estimate based on typical
conditions (Vcc = 3.3V, room temperature) using a typical
pattern of a 16-bit loadable, enabled, up/down counter in each
LAB and no output load. Actual Icc should be verified during
operation since this measurement is sensitive to the actual
pattern in the device and the environmental operating
conditions.

IPage 308

Vcc =3.3V

Room Temp.

ci. 40
~

.s«

()

..9
10

100

Frequency (MHz)

Altera Corporation

I Data Sheet

EPM7032V EPLD

Absolute Maximum Ratings
Symbol

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

5.6

DC input voltage

Note (1)

-2.0

5.6

I MAX

DC Vee or GND current

300

lOUT

DC output current, per pin

-25

Power dissipation

1000

TSTG

Storage temperature

No bias

-65

150

°C

TAMB

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit
V

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

vee

Supply voltage

3.0

3.6

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Input rise time

Input fall time

Max

Unit
V

DC Operating Conditions
Symbol

Notes (2), (3)
Conditions

Parameter

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

IOH =-0.1 mA DC

Vee- O.2

VOL

Low-level output voltage

IOL = 4 mA DC

Input leakage current

VI = Vee or GND

-10
-10

V
V

0.45

!-LA

loz

Tri-state output off-state current

V 0 = Vee or GND

!-LA

I ceo

Vee supply current
(standby, power-down mode)

Note (4)

150

!-LA

lee1

Vee supply current
(standby, low-power mode)

V I = GND, No load,
Note (4)

lee2

Vee supply current
(active, low-power mode)

VI = GND, No load,

f = 1.0 MHz, Note (4)

Min

Max

Unit

Capacitance

Note (5)

Symbol

Parameter

Conditions

CIN

Input capacitance

V I N = 0 V, f = 1.0 MHz

COUT

Output capacitance

V OUT = 0 V, f = 1.0 MHz

I Altera Corporation

Page 309

I EPM7032V EPLD
AC Operating Conditions

Data Sheet

Note (3)

External Timing Parameters
Symbol
Parameter

EPM7032V-12 EPM7032V-15 EPM7032V-20

Conditions

Min

C1 = 35 pF

Max

Unit

Max

Min

Max

Min

t pD1

Input to non-registered output

t pD2

I/O input to non-registered output

tsu

Global clock setup time

Global clock hold time

tC01

Global clock to output delay

tCH

Global clock high time

tCL

Global clock low time

t ASU

Array clock setup time

tAH

Array clock hold time

t AC01

Array clock to output delay

tACH

Array clock high time

t ACL

Array clock low time

tCNT

Minimum global clock period

fCNT

Max. internal global clock frequency

t ACNT

Minimum array clock period

f ACNT
f MAX

C1 = 35 pF

4
C1 = 35 pF

4
6

ns
20

8
13

76.9

ns
ns

5
15

ns
12

ns
16

62.5

ns
MHz

Note (4)

90.9

Max. internal array clock frequency

Note (4)

90.9

76.9

62.5

MHz

Maximum clock frequency

Note (6)

125

100

83.3

MHz

Internal Timing Parameters
Symbol
Parameter

EPM7032V-12 EPM7032V-15 EPM7032V-20

Conditions

Min

Max

Min

Max

Min

Max

Unit

tIN

Input pad and buffer delay

tlO
t SEXP

I/O input pad and buffer delay

Shared expander delay

t pEXP

Parallel expander delay

t LAO

Logic array delay

t LAC
too

Logic control array delay

tzx

Output buffer enable delay

txz

Output buffer disable delay

tsu

tH
t RO

tCOMB

Combinatorial delay

tIC

Array clock delay

ns
ns

Output buffer and pad delay

=35 pF
=5 pF

tEN

tGLOB
t pRE

Global control delay

tCLR

tplA

Prog. Interconnect Array delay

t LPA

Low power adder

I Page 31 0

Note (7)

Altera Corporation

Data Sheet

EPM7032V EPLD

Power-Down/Chip-Enable Timing Parameters
Power-Down Timing Parameters
Symbol
Parameter

EPM7032V -12 EPM7032V-15 EPM7032V-20

Min

tlSUPD

Input or liD input setup time before power down

t lHPD

Input or liD input hold time after power down

tGCSUPD

Global clock setup time before power down

tGCHPD

Global clock hold time after power down

tACSUPD

Array clock setup time before power down

tACHPD

Array clock hold time after power down

t HPD

Minimum high pulse width of power-down pin

800

t LPD

Minimum low pulse width of power-down pin

800

tpDOWN

Power down delay

Max

Min

Max

Unit

800

900

800
800

Chip Enable Timing Parameters
Symbol
Parameter

Max

900
800

900

EPM7032V-12 EPM7032V-15 EPM7032V-20

Max

Unit

tlSTCE

Input or liD input stable after chip enable

Min

Max
60

Min

Max
60

Min

tGCSTCE

Global clock stable after chip enable

tACSTCE

Array clock stable after chip enable

tCE

Data stable after chip enable

700

800

Notes to tables:
(1) Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to Vee + 2 V for
periods shorter than 20 ns under no-load conditions during normal operation.
(2) Typical values are for TA = 25° C and Vee = 3.3 V.
(3) Operating conditions: Vee =3.3 V ± 10%, TA = 0° C to 70° C for commercial use.
Vee =3.3 V ± 10%, TA =-40° C to 85° C for industrial use.
(4) Measured with a 16-bit load able, enabled, up I down counter programmed into each LAB.
Icc is measured at 0° C .
(5) Capacitance measured at 25° C. Sample-tested only. The OEln pin (high-voltage pin during programming) has a
maximum capacitance of 20 pF.
(6) The fMAX values represent the highest frequency for pipelined data.
(7) The t LPA parameter must be added to the t LAD' tLAC, tIC' tACV tEN' and tSEXP parameters for macrocells running in lowpower mode.

Product
Availability

Altera Corporation

Product Grade

Availability

Commercial Temp.

(0° C to 70° C)

EPM7032V-12, EPM7032V-15,
EPM7032V-20

Industrial Temp.

(-40 0 C to 85 0 C)

Consult factory

Military Temp.

(-55 0 C to 1250 C) Consult factory

Page 311

Notes:

EPF8282V Device
Features

0
0

0
0
0
0

0
0
0
0
0
0
0

3.3-V version of the EPF8282 device
High-density, register-rich programmable logic device
1,250 gates, 282 registers
781/0 pins and 4 dedicated inputs
Fabricated on a O.8-micron CMOS SRAM technology
In-circuit reconfigurable
FastTrack continuous routing structure for fast, predictable
interconnect delays
Available in plastic packages (see Figure 6):
84-pin J-Lead chip carrier (PLCC)
100-pin thin quad flat pack (TQFP)
Input/ output registers on all I/O pins
Dedicated carry chain that can implement fast adders and counters
Built-in cascade chain for efficient implementation of high-speed,
high-fan-in logic functions
Low power consumption (less than 1 rnA in standby mode)
Programmable output slew-rate control to reduce switching noise
Built-in Joint Test Action Group (JTAG) Boundary-Scan test circuitry
Software design support and automatic place-and-route with Altera's
MAX+PLUS II development system for PC, Sun SPARCstation, and
HP 9000 Series 700 platforms
Pin-, function-, and programming-file-compatible with 5-V EPF8282
devices

Figure 6. EPF8282V Package Pin-Out Diagrams
""

1-1-1-

I-~I-I-

1-1-1-

=:l::J::Joo::J::J:::::l::J0 o:::t::J::J

~~~~~~~~~~~~~aa~~~~~~
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND
GND
1/0
1/0

vee
vee
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

0
EPF8282V

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

vee
vee
1/0
1/0
GND
GND

1/0
1/0
1/0
1/0
1/0
1/0
1/0

EPF8282V

~~~~~~~~~~~;~~~~~~~~~

~~~~~~~~~~~~8g~~~~~~~
~~~CDCD~~~~»~~~

84-Pin J-Lead

Pin 31

Pin 51

1~O-Pin QFP

~A_lt_e_ra_C
__
or~p_o_ra_t_io_n___________________________________________________________
P~

I EPF8282V Device

Data Sheet I

General
Description

The general characteristics of the EPF8282V are identical to those of the 5-V
EPF8282, with the exceptions noted in this data sheet. For detailed
information on FLEX 8000 devices, refer to the FLEX 8000 Programmable
Logic Device Family Data Sheet in this data book.

Generic Testing

Each FLEX 8000 device is functionally tested and guaranteed. Complete
testing of each configurable SRAM bit and all intemallogical elements
ensures 100% configuration yield. AC test measurements for 3.3-V
FLEX 8000 devices are made under conditions equivalent to those shown
in Figure 7. Multiple test patterns can be used to configure devices during
all stages of the production flow.

Figure 7. FLEX 8000 AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous
transitions of multiple outputs should
be avoided for accurate measurement.
Threshold tests must not be performed
under AC conditions. Large-amplitude,
fast ground-current transients normally
occur as the device outputs discharge
the load capacitances. When these
transients flow through the parasitic
inductance between the device ground
pin and the test system ground, it can
create significant reductions in
observable noise immunity.

I Page 314

.------- vee
703n
Device
Output

to Test
System

8.06 kn
Device input
rise and fall
times < 3 ns

Altera Corporation

Preliminary Information

Data Sheet

Absolute Maximum Ratings
Symbol

EPF8282V Device

See Operating Requirements for Altera Devices in this data book.

Parameter

Conditions

Min

Max

Unit
V

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

600

lOUT

DC output current, per pin

Power dissipation

TSTG

Storage temperature

-25
No bias

-65
-65

2.2

150

°C

135

°C

150

°C

Min

Max

Unit

With respect to GND

3.0

3.6

Vee

For commercial use

a
a
a

TAMS

Ambient temperature

Under bias

Junction temperature

Under bias

Recommended Operating Conditions
Symbol
vee

Supply voltage

Input voltage

Output voltage

Ambient temperature

Vee

°C

Input rise time

Input fall time

DC Operating Conditions

Note (2)

Typ

Max

Unit

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

Symbol

Parameter

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

leeo

Vee supply current (standby)

Capacitance

Conditions

= 0.1 mA DC
10L = 4 mA DC
VI = VeeorGND
Vo = VeeorGND
V I = GND, No load,

Min

Vee- 0 .2

10H

V
V

0.45

-10

IlA

-40

IlA

Note (3)

300

Conditions

Min

IlA

Note (4)

Symbol

Conditions

Parameter

Max

Unit

C IN

Input capacitance

VIN=OV,f= 1.0 MHz

C OUT

Output capacitance

V OUT =

a V, f

Altera Corporation

= 1.0 MHz

Page 3151

Preliminary Information

EPF8282V Device

Internal Timing Characteristics

Note (5)

I/O Element (IDE) Output Timing Parameters
Symbol

Data Sheet I

Parameter

Conditions

EPF8282V-3

EPF8282V-4

Min

Max

tOUTSU

Setup time for output register

3.0

tOUTH

Hold time for output register

tOUTCO

Clock-to-output time for output register C1

tOUT
tOUTCLR

= 35 pF

Unit
ns
ns

8.1

10.8

Combinatorial time for I/O output

6.3

9.0

Clear time for output register

8.4

11.1

txz

Valid to Z time for 10E

tzx

Z to valid time for 10E

= 5 pF
= 35 pF

I/O Element (IDE) Input Timing Parameters
Symbol

Max

Parameter

Conditions

6.3

9.0

6.3

9.0

EPF8282V-3

EPF8282V-4

Min

Max

Unit

t lNSU

Setup time for input register

4.5

tlNH

Hold time for input register

t lNeo

Clock-to-output time for input register

3.0

4.5

tIN

Input pad and buffer delay

2.7

4.2

t lNCLR

Clear time for input register

3.3

4.8

EPF8282V-3

EPF8282V-4

Min

Logic Element (LE) Timing Parameters
Symbol

Parameter

Conditions

Max

Unit

t LESU

Setup time for LE register

3.8

5.6

tLEH

Hold time for LE register

tLECO

Clock-to-output time for LE

5.0

6.0

tLE

Combinatorial time for LE

7.5

9.0

tLECLR

Clear time for LE register

5.4

6.5

tLEPRE

Preset time for LE register

5.4

6.5

tCICO

Carry-in to carry-out time

1.1

1.7

tCGEN

Carry generation time

3.5

5.0

tCASC

Cascade-in to cascade-out time

1.7

3.0

tcsu

Carry-in to register setup time

tCOUT

Carry-in to LE out delay

Page 316

2.4
6.1

ns
ns

3.6
7.0

Altera Corporation I

Preliminary Information

Data Sheet

Interconnect Timing Parameters
Symbol
tLABCASC

Parameter

Conditions

EPF8282V Device

EPF8282V-3

EPF8282V-4

Min

Cascade time between LEs in different

Max

Unit

0.8

1.4

0.8

0.9

LABs
tLABCARRY

Carry time between LEs in different
LABs

tCOL

Column interconnect routing delay

3.8

tOIN

Dedicated input pad delay

4.5

6.0

t WCAL

LAB local interconnect delay

tOINROW

Dedicated input routing delay

tROW

Row interconnect routing delay

External Reference Timing Characteristics

Symbol
t1

Parameter
liD pin to liD pin via row, LE, and

1.5

4.5

5.3

6.3

EPF8282V-3

EPF8282V-4

Min

Note (6)

Note (7)

Conditions
C1 = 35 pF

Max

Unit

column

liD pin to liD pin via row, LE, and row

Notes to tables:
(1)
(2)
(3)
(4)
(5)

(6)
(7)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 Vor overshoot to 7.0 V for
periods shorter than 20 ns under no-load conditions.
Operating conditions: Vee = 3.3 V ± 5%, TA = 0° C to 70° C for commercial use.
Typical values are for TA = 25° C and Vee = 3.3 V.
Capacitance is sample-tested only.
Internal timing parameters cannot be measured explicitly. The values in these tables are worst-case delays based on
testable and guaranteed external parameters. These internal parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
The tROW and tDINROW delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
External reference timing characteristics are factory-tested, guaranteed worst-case values. A representative subset of
signal paths is tested to approximate typical device applications.

Altera Corporation

Page 317

Notes:

Contents
I

August 1993

Section 7

Function-Specific
EPS448 SAM EPLD: Stand-Alone Microsequencer .................................. 321
Micro Channel EPLDs: User-Configurable Micro Channel Interface .... 339
Configuration EPROMs for FLEX 8000 Devices ....................................... 341

Altera Corporation

Page 319

EPS448 SAM EPLD
Stand-Alone Microsequencer

August 1993, ver. 4

Features

User-configurable Stand-Alone Microsequencer (SAM) EPLD for
implementing high-performance controllers
DOn-chip reprogrammable microcode EPROM up to 448 words deep
o 15 x 8-bit stack
o Loop counter
o Prioritized multiway control branching
o 8 general-purpose branch-control inputs and 16 general-purpose
control outputs
o Cascadable to expand the number of outputs or states
o Low-power CMOS technology
o Available in 28-pin windowed ceramic and one-time-programmable
(OTP) plastic packages (see Figure 1):
Dual in-line (CerDIP and PDIP)
J-Iead chip carrier (plastic PLCC only)
o Clock frequencies up to 25 MHz
o High-level support with SAM+PLUS design tools that include Altera
State Machine Input Language (ASMILE), Assembly Language (ASM),
SAM Design Processor (SDP), and SAMSIM functional simulator

Figure 1. EPS448 Package Pin-Out Diagrams
F15

F14

F13

F12

F11

F10

eLK
vee

F09

Package outlines not drawn to scale.
Windows in ceramic packages only.

26
25

16
17

F15

GND

F14

F07

F13

F06

F12

F11

F08

F05
10

F04

Faa

F03

F01

F02

28-Pin DIP

I Altera Corporation

nRESET

General
Description

Shee~

Data

EPS448
12

II)

~-=~~~~~~--~~

Each address location between 192 and 255 accesses 4 unique 36-bit
instructions. Each of these four instructions corresponds to a different
possible next state. (The extensions .0, .1, .2, and .3 are added to
distinguish the four states.) These 64 addresses make up the multiway
branch locations, and are used to perform single-Clock, 4-way branching.
Whenever the next-state address falls within the multiway branch locations,
the branch-control logic makes the necessary 1-of-4 selection based on the
next-state address and user-defined input conditions.

Page 324

Altera Corporation

I Data Sheet

EPS448 SAM EPLD: Stand-Alone Microsequencer I

Branch-Control Logic Block
The branch-control logic block is the key to the high-performance
sequencing ability of the EPS448 EPLD. This block determines the next
state to be clocked into the pipeline register, based on the current status of
the pipeline register, the counter, the stack, and the eight input pins.
The branch-control logic is divided into two segments: the address
multiplexer and the branch-select logic. See Figure 4.

Figure 4. Branch-Control Logic
Zero Flag
from Counter

Opcode
3

Q-Field ~
D-Field

Next-State Address

Address
Multiplexer

Top-of-Stack ~

Inputs (10 to 17) ~

Branch-Select
Logic

1-of-4 Branch Select

768 Product
Terms

The address multiplexer provides the next-state address to the microcode
memory. The next-state address can come from the Q-field, the D-field, or
the top-of-stack. The selection is based on the instruction in the pipeline
register and the condition of the zero flag from the counter.
The branch-select logic is a programmable logic block with 768 product
terms, 16 inputs, and 4 outputs. It is used to perform a 2-, 3-, or 4-way
branch based on user-defined input conditions. When the next-state address
falls within the multiway branch range of memory-i.e., any address
greater than 191-the branch-select logic performs the necessary 1-of-4
selection. When the next-state address is less than 192, no selection is
required and the branch-select logic is turned off.
The conditions controlling the multiway branch are defined by the user in
a simple IF-THEN"-ELSE format, as shown in the following example:
IF
ELSEIF
ELSEIF
ELSE

I Altera Corporation

(cond3)
(cond2 )
(cond1)

THEN
THEN
THEN

select201.3
select 201.2
select 201.1
select 201.0

Page 325

I EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

The conditions are prioritized so that if the first condition (i.e., cond3) is
met, then microword 201. 3 is selected and clocked into the pipeline
register, regardless of the results of cond2 and condl. If no conditions are
met, then microword 201 . 0 is clocked into the pipeline resister.
The three conditional expressions are user-defined. They can contain any
logical equation that is based on the inputs and can be reduced to four
product terms, as shown in the following example:
cond1

11 * /12 * /I4
+ 13 * /14 * /15 * /16 * /17
+ 10
+ 12 * /I4 * /IS

A unique set of 12 product terms is present in each of the 64 available
multiway branch locations for a total of 768 product terms. Figure 5 shows
how each set is used to select the appropriate instruction.

Figure 5. Branch Logic in a Multiway Branch Location
Programmable Logic
prioritY

Encoder
Select.3

~~-4+---++---H~-++---H---++---H--~
~~~+---++---H---++---H---++---H--~

Select.O
Inputs

The EPS448 EPLD is designed so that the number of available product
terms is always sufficient for a design. Prioritization provides an effective
product-term count of more than 12 per location. A tradeoff between the
number of product terms and the number of possible branches can be
made simply by placing identical state information in 2 locations, as
shown in Figure 6.

I Page 326

Altera Corporation

EPS448 SAM EPLD: Stand-Alone Microsequencer I

Data Sheet

Figure 6. Multiway Branching vs. Product-Term Needs
3-Way Branch

4-Way Branch

~G
G"G)C
3

IA * 18 * Ie

Stack
The EPS448 stack is a Last-In First-Out (LIFO) arrangement that consists of
15 x 8-bit words. The top of stack can be selected by the branch-control
logic as the next-state address or popped into the counter. Values can be
pushed onto the stack from either the D-field in the pipeline register or
from the counter. Therefore, subroutines, nested loops, and other iterative
structures can be implemented efficiently. The logic levels on the 8 dedicated
input pins can also be pushed onto the stack to allow external address
specification in a dispatch function or to externally load the counter. See
Figure 7.

Figure 7. Stack

Inputs

to Counter or
Branch Control Logic

The pushing or popping of the stack occurs on the leading edge of the
Clock. The stack is "zero-filled" so that a pop from an empty stack resets all
8 bits to zero. On the other hand, a push to a full stack writes over the topof-stack, leaving the other 14 values unchanged.

Loop Counter
The EPS448 EPLD contains an 8-bit loop counter, called count register
(CREG), that is useful for controlling timing loops and determining branchcontrol functions. The CREG is a down counter that can be loaded directly
from the D-field of the pipeline register or from the top-af-stack. The value
of the CREG can be saved and restored by pushing and popping it to and
from the stack. See Figure 8.

I Altera Corporation

Page 327

I EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

Figure 8. Loop Counter (CREG)
D-Field

Instruction

Stack Hold Decrement

---..~,

Zero Flag

to Stack

The CREG is loaded or decremented on the leading edge of the Clock. It
stops decrementing once it reaches zero, thereby preventing roll-over. A
zero flag indicates when the counter has reached zero. This flag is used
with the LOOPNZ command to control program flow. (See "Instruction Set"
later in this data sheet.) Single-instruction delay loops are easily constructed,
and nested loops or delays of arbitrary length can be generated in combination with the stack.

Output Enable
Control

Each microcode word contains an Output Enable bit (i.e., the E-field) that
enables all outputs when E = 1, and causes high impedance when E = O.
This bit is accessible through instruction set commands provided with
SAM+PLUS software. This Output Enable capability allows EPS448 EPLDs
to be vertically cascaded to increase the number of states.

nRESET Pin

The nRESET pin acts as a master Reset for the EPS448 EPLD, causing it to
empty the stack, clear the counter, and load the microword at address a
into the pipeline register. The nRESET signal is useful for system reset or
for synchronizing several horizontally or vertically cascaded EPS448
devices.
The nRESET signal must be held low for at least three rising Clock edges to
reset the EPS448 EPLD. Allowing nRESET to go high before the third rising
Clock edge causes the EPS448 device to enter an undefined state.
The outputs of the startup address (00 Hex) appear at the pins after the
fourth rising Clock edge after nRESET goes low, and are maintained until
the third rising Clock edge after nRESET returns to high.
When the EPS448 EPLD is operating in noisy environments, a glitch on the
nRESET pin during one setup cycle (tSUR) before the Clock edge may cause
it to enter an undefined state. To prevent this effect, a capacitor of at least
0.1 ~F should be connected from the nRESET input to GND.

I Page 328

Altera Corporation

I Data Sheet

Horizontal &
Vertical
Cascading

EPS448 SAM EPLD: Stand-Alone Microsequence_d

EPS448 EPLDs, like memory- and bit-slice devices, can be cascaded to
provide greater functionality (see Figure 9). If an application requires more
output lines, two or more EPS448 devices can be cascaded horizontally.
Likewise, if an application requires more states, two or more EPS448
EPLDs can be cascaded vertically. In either case, no delay is incurred. The
user can also simultaneously cascade EPS448 devices horizontally and
vertically. The SAM+PLUS development software automatically
implements horizontal cascading when a design specifies more than the 16
available outputs. However, vertical cascading requires the designer to
make certain tradeoffs to split the design. Refer to Application Brief 65
(Vertical Cascading of EPS448 SAM EPLDs) in the 1992 Applications
Handbook for more information.

Figure 9. Horizontal and Vertical Cascading
Vertical Cascading

Horizontal Cascading
Inputs

Clock

Control
Outputs

(N)
Clock

Control Outputs (2N)

Instruction Set

The instruction set used to enter designs for the EPS448 EPLD consists of a
compact assortment of powerful commands for efficient implementation
of multiway branching, subroutines, nested FOR-NEXT loops, and dispatch
functions. These instructions are used only with Assembly Language
(ASM) design entry.
Each command in the instruction set is described and illustrated in this
section. In the following descriptions, labelA and labelB represent
arbitrary labels located in the ASM file. These symbolic labels are converted
into 8-bit absolute addresses by the SAM+PLUS software. (SAM+PLUS
allows the designer to use the high-level Assembly Language without
worrying about the actual values that are placed in the various fields.) The
parameter constant is any 8-bit number (0 to 255 decimal, 0 to FF
hexadecimal) that represents an address, a mask, or a constant.
For simplicity, it is assumed that the sample destination labels in the
following descriptions are not in the multiway branch block. See "Multiway
Branching" later in this data sheet.

I Altera Corporation

Page 329 ]

I EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

CONTINUE

This command causes execution to continue with the next sequential
instruction in the ASM file. In this example, the current address is 44, and
CONTINUE instructs SAM+PLUS to go to address 45 in the ASM file.

JUMP labelA

This instruction causes execution to branch to the indicated location. In
this example, address 44 contains the instruction JUMP labelA; labelA is
located at address 73. The next instruction comes from labelA.

~O
Stack

(Push)

labelB~

.--..@Stack

CALL labelA RETURNTO labelB

This instruction pushes the address of labelB onto the stack and makes
labelA the next-state address. CALL labelA without the RETURNTO
command makes labelB default to the next instruction in the ASM file. In
this example, the address location 44 contains the instruction CALL 1 abe lA;
labelA is located at address 73. The instruction pushes the address of the
next instruction (45) onto the stack and causes the next instruction to come
from address 73. The RETURN instruction at address 75 returns the execution
to address 45. The CALL command is typically used to call a subroutine.
RETURN

(Pop)

This command causes the address of the next instruction to come from the
top-of-stack and pops that value off the stack. In this example, the instruction
at address 44 calls the subroutine at address 73 and pushes the value 45
onto the stack. The RETURN instruction at address 75 pops the value 45 off
of the top-of-stack and causes execution to continue with address 45.
RETURN is most frequently used to return from a subroutine.

[

44=!3

~ ~

const~O
Counter
(Load)

1
31abeiA

I Page 330

LOADC constant GOTO labelA

This command loads the counter with the specified value and then executes
the instruction at labelA. If GOTO is not included in the instruction, labelA
defaults to the next instruction in the ASM file. In this example, the
instruction LOAOC 17 3D GOTO labelA is located at address 44. This command
specifies that the decimal value 173 is loaded into the counter and that the
next state comes from labelA at address 73. LOADC is typically used to load
the counter before entering a FOR-NEXT loop or a wait-state generator.
Altera Corporation

I Data Sheet
labelB
42

EPS448 SAM EPLD: Stand-Alone Microsequencer

N-1 ----. N
Counter

Counter

2. const

----'6

43
[

,3labelA

6
Counter
(Load)

I Altera Corporation

This command decrements the counter if it is not zero and then jumps to
the instruction specified at labelA. If GOID is not included in the instruction,
labelA defaults to the next instruction in the ASM file. In this example,
the instruction at address 44 is DECNZ GOTO labelA, where labelA is
located at address 73. The counter is decremented if it is not zero and the
next instruction comes from address 73. DECNZ is typically used to
conditionally decrement the counter.

PUSHLOADCconstantGOTOlabelA
Stack
(Push)

Stack
(Pop)

This instruction jumps to one of two addresses based on the value of the
zero flag, and decrements the counter if it is not already zero. If it is zero
(i.e., zero flag = I), the next instruction comes from labelA. If it is not zero
(i.e., zero flag = 0), the next instruction comes from labelB. If the ONZERO
instruction is not included, labelA defaults to the next instruction in the
ASM file. In this example, the instruction at address 44 is LOOPNZ labelB
ONZERO labelA, where labelB is located at address 42 and labelA at
address 73. If the counter is not at zero, the instruction at address 42 is
executed and the counter is decremented. If the counter is already at zero,
the instruction at address 73 is executed and the counter remains at zero.
LOOPNZ is typically used to implement FOR-NEXT loops.

Counter
(Load)

LOOPNZlabelBONZEROlabelA

DECNZ GOTO labelA

N-1-'@

This instruction pushes the current value of the counter onto the stack,
loads a new value into the counter, and jumps to labelA. If the GOTO
instruction is not included, labelA defaults to the next instruction in the
ASM file. In this example, the instruction at address 44 is PUSHLOADC 153D
GOTO labelA, where labelA is located at address 73. The value in the
counter is pushed onto the stack, the decimal value 153 is loaded into the
counter, and the next instruction comes from address 73. PUSHLOADC is
useful for implementing FOR-NEXT loops.

PO PC GOTO 1 abe lA
This command pops the top-of-stack into the counter and jumps to labelA.
If the GOID instruction is not included, labelA defaults to the next instruction
in the ASM file. In this example, the instruction at address 44 is POPC GOTO
labelA, where labelA is located at address 73. The current value at the
top-of-stack is removed from the stack (i.e., popped) and loaded into the
counter. The next instruction comes from address 73. POPC is typically
used with the PUSHLOADC instruction to implement nested FOR-NEXT loops.

Page 331

EPS448 SAM EPLD: Stand-Alone Microsequencer

const

-----'0

PUSH constant GOTO labelA

Stack
(Push)

Input

Data Sheet I

- r \ Stack

This command pushes the value of the constant onto the stack and jumps
to labelA. If the GOTO instruction is not included, labelA defaults to the
next instruction in the ASM file. In this example, the instruction at address
44 is PUSH 34D GOTO labelA, where labelA is located at address 73. The
decimal value 34 is pushed onto the stack and the next instruction comes
from address 73. PUSH is typically used to store a value on the stack.
PUSHI GOTO labelA

~\.J (Push)

This instruction pushes the eight inputs (I7 to IO) onto the stack. If the
GOTO instruction is not included, labelA defaults to the next instruction in
the ASM file. In this example, the instruction at address 44 is PUSHI GOTO
labelA, where labelA is located at address 73. At the leading edge of the
Clock, the eight inputs are pushed onto the stack. Typically, address 73
would have a RETURN instruction that would cause execution to jump to
the address represented by the recently pushed input pins, implementing
a dispatch function. This instruction can also be used to load the counter
with an externally specified variable. To do so in this example, address 73
would have a POPC instruction.

constlh
Input~
,

Stack
(Push)

~DJ.

Stack
(Pop)

const

731abeiA

Counter
(Load)

Page 332

ANDPUSHI constant GOTO labelA

This command pushes the eight inputs (I7 to IO) onto the stack. It is
identical to the PUSHI GOTO labelA command, except that the inputs are
first bit-wise ANDed with a constant to allow the masking of irrelevant
inputs. If the GOTO instruction is not included, labelA defaults to the next
instruction in the ASM file. In this example, the instruction at address 44 is
ANDPUSHI 34D GOTO labelA, where labelA is located at address 73. At
the leading edge of the Clock, the eight inputs are masked with the decimal
constant 34 and pushed onto the stack. The next instruction comes from
address 73. ANDPUSHI is an advanced instruction typically used to branch
to an externally specified resource or to externally load the counter.
POPXORC constant GOTO labelA

This instruction pops the top-of-stack, bit-wise XORs it with a constant,
loads the results into the counter, and jumps to labelA. If the GOTO
instruction is not included, labelA defaults to the next instruction in the
ASM file. In this example, the instruction at address 44 is POPXORC 25D
GOTO labelA, where labelA is located at address 73. The top-of-stack is
popped off the stack, XORed with decimal 25, and the result is loaded into
the counter. The next state comes from address 73. POPXORC is an advanced
instruction typically used to compare the inputs against a known value
and then branch on the basis of the result.

Altera Corporation

I Data Sheet

EPS448 SAM EPLD: Stand-Alone Microsequenc!ij

Table 1 summarizes the effects of each instruction on the address
multiplexer, the stack, and the counter.

Table 1. Instruction Set Summary
Instruction

Definition

Next-State
Address

Effect on
Stack

Effect on
Counter

CONTINUE

Continue with next instruction

labelA

None

Hold

JUMP

Jump to a label

labelA

None

Hold

CALL

Call subroutine

labelA

labelB

Hold

RETURN

Return from subroutine

labelA

Pop

Hold

LOADC

Load CREG

labelA

None

Constant

LOOPNZ

Loop/decrement CREG on non -zero value

labelA or

None

Decrement

labelB
DECNZ

Decrement CREG on non -zero value

labelA

None

Decrement

PUSHLOADC

Push CREG to stack and load CREG

labelA

CREG

Constant
Stack

POPC

Pop stack to CREG

labelA

Pop

PUSH

Push constant to stack

labelA

Push

Hold

PUSHI

Push inputs to stack

labelA

Inputs

Hold

ANDPUSHI

Push masked inputs to stack

labelA

Inputs (ANDed)
Constant

Hold

POPXORC

XOR stack with constant and send result to
CREG

labelA

Pop

Stack XOR
Constant

Multiway
Branching

Multiway branching provides an added dimension to the capabilities of
the instruction set. For example, a JUMP labelA to an address within the
multiway branch block forces the branch-select logic to decide which of
the four words to send to the pipeline register. This selection is based on
user-defined functions of the inputs. See Figure 10.

Figure 10. Jumping to a Multiway Branch Address

I Altera Corporation

Page

3331

EPS448 SAM EPLD: Stand-Alone Microsequencer

Data Sheet

Any of the 13 available commands can be enhanced with multiway
branching. For example, location 44 in Figure 10 can be a CALL to a
subroutine, and address 201 can contain the starting instruction for 4
unique subroutines. The routine that is actually executed depends on the
user-defined condition of the inputs. The following ASM code can be used
to implement this example:
44D:
[output Spec] CALL ROUTINE1;
201D:
ROUTINE1:
IF
cond1
THEN
ELSEIF
cond2
THEN
THEN
ELSEIF
cond3
ELSE

[out
[out
[out
[out

1]
2]
3]
4]

JUMP
JUMP
JUMP
JUMP

102D;
73D;
53D;
34D;

Design Security

The EPS448 EPLD contains a programmable design Security Bit that controls
access to the data programmed into the EPLD. If this Security Bit is used, a
proprietary design implemented in the EPLD cannot be copied or retrieved.
It provides a high level of design control because programmed data within
EPROM cells is invisible. The Security Bit, along with all other program
data, is reset by erasing the EPLD.

Functional
Testing

The EPS448 EPLD is fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal logic
elements, thus ensuring 100% programming yield. AC test measurements
are performed under the conditions shown in Figure 11.

Figure 11. EPS448 AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast
ground-current transients normally occur
as the device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test
system ground, significant reductions in
observable input noise immunity can
result.

,..-----VCC

4270
Device
Output

2700

to Test
System

C1 (includes
JIG capacitance)

Device input
rise and fall
times < 3 ns

Since the EPS448 EPLD is erasable, Altera can use and then erase test
programs during early stages of production flow. This ability to use
application-independent, general-purpose tests is called generic testing
and is unique among user-defined LSI logic devices. EPS448 EPLDs also
contain on-board test circuitry to allow verification of function and AC
specifications after they are packaged in windowless packages.

I Page 334

Altera Corporation

EPS448 SAM EPLD: Stand-Alone Microsequencer I

Data Sheet

Figure 12 shows the output drive characteristics of EPS448 I/O pins and
typical supply current versus frequency for the EPS448 EPLD.

Figure 12. EPS448 Output Drive Characteristics and Icc vs. Frequency
100

ci.
~

100

«
E'E

ci.
~

()

"5
a.
"5

Vcc =5.0V
TA = 25° C

~
~

I-----~
VCC = 5.0 V
TA = 25° C

EO)

()

..!:?

1 kHz

10 kHz 100 kHz 1 MHz 10 MHz 25 MHz

Maximum Frequency

Vo Output Voltage (V)

Figure 13 shows EPS448 timing and reset timing waveforms.

Figure 13. EPS448 Switching Waveforms
If nRESET is held low for more than three Clock
edges, then the outputs associated with the boot
address (00 Hex) will remain at the pins until the
third Clock after nRESET goes high.

Timing Waveforms
_tCYC_.
tF --.l i - tCl - . :_ tCH--l
Clock

i;
i

i_tsu-i

Input 10 to 17

~:.alid Input

'------"

i - tH
·X'--.- - - - - - - ! - - - - -

i-tco-i
Output FOto F15

X;-;---~----

i-tez-i
:
Output FO to F15

i_tcz_i

:)~igh-Impedancei
.

Tri-State

f-'----

Reset Timing Waveforms
Clock

-i

!-- tSUR

tHR-i i Vr-'-.;....~- - - - - + - - ' - - - - - - - - " teo -:
tco

nRESET ~

Output FO to F15

==x

Invalid Output

i- -l 'X===F:: ;(=OO:=)=~~
t

Counter and
stack cleared

I Altera Corporation

Page 335

EPS448 SAM EPLD: Stand-Alone Microsequencer

Parameter

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

Vpp

Programming supply voltage

Note (1)

-2.0

14.0

DC input voltage

-2.0

7.0

I MAX

DC Vee or GND current

-250

250

lOUT

DC output current, per pin

-25

Power dissipation

1200

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-10

°C

Min

Max

Unit

Recommended Operating Conditions
Symbol

Note (2)

Parameter

Conditions

vee

Supply voltage

4.75 (4.5)

5.25 (5.5)

Input voltage

Vee

Output voltage

Vee

Operating temperature

For commercial use

°C

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

500 (100)

Input fall time

500 (100)

Max

Unit
V

DC Operating Conditions
Symbol

See Operating Requirements for Altera Devices in this data book.

Absolute Maximum Ratings
Symbol

Data Sheet

Notes (2), (3), (4)

Parameter

Conditions

Min

Typ

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

V OH

High-level CMOS output voltage

VOL

Low-level output voltage

Input leakage current

loz

Tri-state output off-state current

lee1

Vee supply current (standby)

= -8 mA DC
IOH = -4 mA DC
IOL = 8 (4) mA DC
V I = Vee or GND, Note (5)
Vo = VeeorGND
No load, V I = Vee or GND,

lee3

Vee supply current (active)

No load, 50% duty cycle,

IOH

V
V

2.4
3.84

-10
-10

0.45

IlA

95 (120)

140 (200)

Note (6)

f = 1.0 MHz,
V I = Vee or GND, Note (6)

Page 336

Altera Corporation

Data Sheet

Capacitance

EPS448 SAM EPLD: Stand-Alone

Microsequence~

Note (7)

Symbol

Parameter
=

CIN

Input capacitance

V IN

COUT

Output capacitance

V OUT

CCLK

Clock pin capacitance

V IN

CRST

nRESET pin capacitance

AC Operating Conditions

Min

Conditions
0 V, f

0 V, f

1.0 MHz

0 V, f

1.0 MHz

Unit

Note (3)
EPS448-25A EPS448-25

Symbol

Max

Parameter

Conditions
=

EPS448-20

EPS448-16

Min Max Min Max Min Max Min Max Unit
25

Maximum frequency

tCYC

Minimum clock cycle

tsu

Input setup time

16.5

Input hold time

tco

Clock to output delay

tcz

Clock to output disable or enable

tCl

Global clock low time

tCH

Global clock high time

tSUR
tHR

nRESET setup time

16.5

nRESET hold time

35 pF

MHz

fCYC

62.5

16.5

Notes to tables:
(1)
(2)
(3)

(4)
(5)
(6)
(7)

Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for
periods less than 20 ns under no-load conditions.
Numbers in parentheses are for military and industrial temperature versions.
Operating conditions: Vee = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
Vee = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
Vee = 5 V ± 10%, Tc = -55° C to 125° C for military use.
Typical values are for TA = 25° C, Vee = 5 V.
For 1.0 < VI < 3.8, the nRESET pin can supply up to 200 /-lA.
This condition applies when the present state is a single-way branch location.
Capacitance is measured at 25° C. Sample-tested only.

Product
Availability

Commercial Temp.

(0° C to 70° C)

Industrial Temp.

(-40° C to 85° C) EPS448-20
(-55° C to 125 C) EPS448-20

Military Temp.

Altera Corporation

Availability

Product Grade

EPS448-16, EPS448-20, EPS448-25, EPS448-25A
0

Page 337

Notes:

Micro Channel EPLD
User-Configurable
Micro Channel Interface
I August 1993, ver. 2

Features ...

Data Sheet

D
D
D
D
D

100% Micro Channel-compatible architecture eliminates design debug
problems and allows faster board design time.
30-mA power-supply current conserves limited board power for
memory, I/O, and other essential ICs.
25-ns address decoding supports high-speed, zero "wait-state" data
transfers.
Programmable POS register I/O gives the designer a choice of POS
bits accessible on board.
Multiple I/O or address decode ranges (up to 8 per chip-select output)
provide multiple addressing options for the designer's board.

See Figure 1.

Figure 1. Micro Channel Bus
Control
Address Bus
Data Bus

Arbitration Bus

EPB2001

Chip
Selects
Programmable
POS I/O Lines

Altera Corporation

NMI
Memory/
I/O Control

Page 3391

Data Sheet I

Micro Channel EPLDs

... and More
Features

o
o
o
o
o

lU?

Page 340

8 programmable chip-select outputs eliminate the need for extra
address decoder PLDs and glue logic ICs.
24 Micro Channel address inputs support full address decoding from
the Micro Channel bus.
24-mA current drive outputs eliminate extra buffer ICs.
Channel-check interrupt support enables the board to use bus NonMaskable Interrupts for fast CPU interrupt response.
Altera's MCMap Development System simplifies Micro Channel design
and eliminates design errors.
See the Micro Channel Adapter Handbook for more information.

Altera Corporation I

.---------------------------------------------------

Configuration EPROMs
for FLEX 8000 Devices
I August 1993, ver. 2

Features

Data Sheet

o
o

o
o
o

Family of serial EPROMs designed to configure FLEX 8000 devices
Available in compact, one-time programmable (OTP) 8-pin plastic
dual in-line (PDIP) and 20-pin plastic J-Iead chip carrier (PLCC)
packages (see Figure 1); 32-pin thin quad flat pack (TQFP) packages
under development
Simple 4-wire interface to FLEX 8000 devices for ease of use
Low current during configuration (15 rnA) and near-zero standby
current (100 ~A)
Software design support with Altera's MAX +PLUS II development
system for IBM PC, Sun SPARCstation, and HP 9000 Series 700
platforms
Programming support with Altera's Master Programming Unit (MPU)
and programming hardware from other manufacturers, including Data

I/O

Functional
Description

In SRAM-based devices, configuration data must be reloaded each time
the system initializes, or whenever new configuration data is desired.
Altera's serial-memory Configuration EPROMs store configuration data
for the SRAM-based Altera FLEX 8000 devices.

Figure 1. Configuration EPROM Package Pin-Out Diagrams
Package outlines not drawn to sea/e.

0
0

DCLK
DATA
DCLK

OE
nCS

VCC

N.C.

VCC

N.C.

nCASC

N.C.

GND

(/)

nCASC

DATA

The control signals for Configuration EPROMs (DCLK, nCS, OE) interface
directly to the FLEX 8000 device control signals. A FLEX 8000 device can
control the entire configuration process by retrieving the configuration
data from the Configuration EPROM without an external intelligent
controller. Configuration usually occurs automatically at system powerup.
The OE and nCS pins work together to control the tri-state buffer on the
DATA output pin, and to enable the address counter in the Configuration
EPROM. When OE is driven low, the device resets the address counter and
tri-states the DATA pin. When the OE pin is driven high again, the device is
Page 342

Altera Corporation

I Data Sheet

Configuration EPROMs for FLEX 8000 Devices

controlled by the nes pin. If nes is held high after the OE reset pulse, the
counter is disabled, and the DATA output pin is tri-stated. When nes is
driven low, the counter is enabled and the DATA output pin is enabled. The
nes pin can then be held either high or low to control the output and
counter. When OE is driven low again, regardless of the state of nes, the
address counter is reset and the DATA output pin is tri-stated. Upon powerup, the address counter is automatically reset. Table 2 describes the pin
functions of Altera Configuration EPROMs.

Table 2. Configuration EPROM Pin Functions
Pin Name

8-Pin PDlP
Pin Number

20-Pin PLCC
Pin Number

Pin Type

Description

DATA

Output

Serial data output.

DCLK

Input

Clock input. Rising edges on DCLK increment the
internal address counter and cause the next bit of
data to be presented on DATA. The counter is
incremented only if the OE input is held high and the
nCS input is held low.

Input

Output Enable (active high) and Reset (active low). A
low logic level resets the address counter. A high
logic level enables DATA and permits the address
counter to count.

nCS

Input

Chip-Select output (active low). A low input allows
DCLK to increment the address counter and enables
DATA.

nCASC

Output

Cascade-Select output (active low). This output goes
low when the address counter has reached its
maximum value. nCASC is usually connected to the
nCS input of the next Configuration EPROM in a
daisy-chain, so the next DCLK clocks data out of the
next Configuration EPROM.

GND

Ground

A 0.2-11F decoupling capacitor must be placed
between the vcc and GND pins.

vcc

7,8

18,20

Power

Power pin

Single-Device
Configuration

I Altera Corporation

The active serial (AS) configuration scheme uses a serial Configuration
EPROM (e.g., EPC1213) as a data source for a FLEX 8000 device. The
Configuration EPROM presents its data to the FLEX 8000 device in a serial
bit-stream. Figure 3 shows a typical circuit in which the FLEX 8000 device
controls the configuration process and uses a serial Configuration EPROM
as the data source. For additional information, refer to Application Note 33
(Configuring FLEX 8000 Devices).

Page 343

I Configuration EPROMs for FLEX 8000 Devices

Data Sheet

Figure 3. Active Serial Configuration

vee

The nCONFIG pin on the FLEX 8000 device in Figure 3 is connected to Vee,
so the device automatically configures itself at system power-up. The
system can monitor the nSTATUS pin to ensure that configuration occurs
correctly. Immediately after power-up, the FLEX 8000 device pulls the
nSTATUS pin low and releases it within 100 ms. Once released, the opendrain nSTATUS pin is pulled up to Vee by an external 1.0-kQ pull-up
resistor. If an error occurs during configuration, the FLEX 8000 device
pulls the nSTATUS pin low, indicating that configuration was unsuccessful.
The DCLK signal, which is driven by the FLEX 8000 device, clocks sequential
data bits from the Configuration EPROM. While the SRAM data is being
loaded, the FLEX 8000 device holds the open-drain CONF_DONE pin at
GND, indicating that data is loading. A 24-bit program-length counter
within the FLEX 8000 device stores the program length, i.e., the total
number of configuration bits. Once the terminal count value for the
configuration data (i.e., the last configuration data bit) has been reached,
the FLEX 8000 device releases the CONF_DONE pin, which is subsequently
pulled up to Vee by an externall.O-kQ pull-up resistor. The resulting high
input on the nCS pin causes the Configuration EPROM to tri-state its DATA
output, electrically removing the Configuration EPROM from the circuit.
After it releases the CONF_DONE pin, the FLEX 8000 device uses it as an
input for monitoring the configuration process. When the FLEX 8000
device senses a high logic level on CONF_DONE, it completes the initialization
process and enters user mode. Figure 4 shows the timing associated with
the AS configuration process and the order of transitions on the control
signals.
Worst-case values for the timing parameters shown in Figure 4 are given in
the "Timing Parameters" table later in this data sheet.

I Page 344

Altera Corporation

I Data Sheet

Configuration EPROMs for FLEX 8000 Devices

Figure 4. Single-Device Configuration Timing Waveforms
nCS/CONF_DONE

DCLK

DATA

itcszx i
:~

i:-t

tcss-i
:.-:
:-tCSH
csxz

In the circuit shown in Figure 3, the nCONFIG pin on the FLEX 8000 device
is tied to the Output Enable (OE) input of the Configuration EPROM; both
are tied to Vcc. A high logic level on the nCONFIG input automatically
starts the configuration. The output of the serial Configuration EPROM is
enabled by a high input on its OE pin. If an error occurs during circuit
configuration, the FLEX 8000 device pulls and holds the nSTATUS pin low,
indicating a configuration error. External circuitry is used to monitor the
nSTATUS pin and take appropriate action if configuration fails. This circuitry
must assert a high-Iow-high pulse on the nCONFIG pin to reconfigure the
device after the error. The same circuitry can also be used to begin
reconfiguring the FLEX 8000 device at any time after system power-up.
The FLEX 8000 device's built-in Auto-Restart Configuration on Frame Error
option bit allows the device to automatically reconfigure itself if it encounters
an error during configuration. If this option bit is turned on, a configuration
error causes the FLEX 8000 device to pull the nSTATUS pin low for 10 internal
Clock cycles and then release it. This 1- to 3-f..ls pulse on the nSTATUS pin
provides an external indication that reconfiguration is about to begin. It
also can be used to reset the Altera Configuration EPROM.
Figure 5 shows a circuit that uses the Auto-Restart Configuration on Frame
Error option. The nSTATUS pin is connected to the OE input on the Altera
Configuration EPROM so that the error-reset pulse on nSTATUS resets the
internal address counter on the Configuration EPROM and prepares it to
reconfigure the FLEX 8000 device. The nCONFIG input is also available to
initiate a reconfiguration cycle externally. Since the nSTATUS pin is pulled
low and then released whenever configuration begins, it resets the
Configuration EPROM before reconfiguration. During device operation, if
Vcc drops below the power-on reset (POR) threshold for the FLEX 8000
device, nSTATUS is pulsed and the Configuration EPROM is reset in the
same way to provide automatic reconfiguration. Timing for the circuit in
Figure 5 is identical to the timing shown in Figure 4 for the AS configuration
scheme (the error-reset pulse on nSTATUS is not shown).

I Altera Corporation

Page 345

I Configuration EPROMs for FLEX 8000 Devices

Data Sheet

Figure 5. Active Serial Oevice Configuration with Automatic Reconfiguration on
Error
FLEX 8000

MAX+PLUS II
Support

The MAX+PLUS II development system provides programming support
for Altera Configuration EPROMs. MAX+PLUS II software automatically
generates a Programmer Object File (.pof) for every FLEX 8000 device in a
project. By default, each FLEX 8000 device in a multi-device project has a
dedicated serial Configuration EPROM. MAX+PLUS II selects the
appropriate Configuration EPROM to most efficiently store the data for
each FLEX 8000 device.
The POF includes a preamble, cyclic redundancy check (CRC), and
synchronization data that allow it to be used in a serial bitstream. The POF
is programmed into the Configuration EPROM with MAX+PLUS II and a
Configuration EPROM programming adapter. A number of other
programming hardware manufacturers, including Data I/O, support
programming of Configuration EPROMs. See the Altera Programming
Hardware and Programming Hardware Manufacturers data sheets in this data
book.

I Page 346

Altera Corporation

I Data Sheet

Configuration EPROMs for FLEX 8000 Devices

Absolute Maximum Ratings

See Operating Requirements for Altera Devices in this data book.

Parameter

Symbol

Conditions

Min

Max

Unit

vee

Supply voltage

With respect to GND

-2.0

7.0

DC input voltage

Note (1)

-2.0

7.0

I MAX

DC Vee or GND current

lOUT

DC output current, per pin

Power dissipation

25
100

-25

TSTG

Storage temperature

No bias

-65

150

°C

TAMS

Ambient temperature

Under bias

-65

135

°C

Junction temperature

Under bias

150

°C

Max

Unit

4.75

5.25

Vee

°C

Recommended Operating Conditions
Parameter

Symbol

Conditions

vee

Supply voltage

With respect to GND

Input voltage

Note (1)

Output voltage

Operating temperature

Min

For commercial use

Operating temperature

For industrial use

-40

°C

Case temperature

For military use

-55

125

°C

Input rise time

Input fall time

DC Operating Conditions

Notes (2), (3)
Min

Max

Unit

V IH

High-level input voltage

2.0

Vee + 0.3

V IL

Low-level input voltage

-0.3

0.8

V OH

High-level TTL output voltage

VOL

Low-level output voltage

IOL = 4 mA DC

Input leakage current

VI =V ee orGND

loz

Tri-state output off-state current

Vo =V ee orGND

Symbol

Parameter

Conditions

2.4

IOH = -4 mA DC

0.45

-10

JlA

-10

JlA

Typ

Max

Unit

Supply Current
Symbol

Parameter

leeo

vee supply current (standby)

lee1

Vee supply current
(during configuration)

IAltera Corporation

Conditions
DCLK

= 8 MHz

Min

100

JlA

Page 347

I Configuration EPROMs for FLEX 8000 Devices
Capacitance

Parameter

Conditions

Min

Max

Unit

= 0 V, f = 1.0 MHz
V OUT = 0 V, f = 1.0 MHz

Input capacitance

COUT

Note (4)

Symbol
CIN

Data Sheet

V IN

Output capacitance

Timing Parameters
Symbol

Conditions

Parameter

Min

Max

Unit

tOEZX

high to DATA output enabled

tCSZX

nCS low to DATA output enabled

tCSXZ

nCS high to DATA output disabled

tcss

nCS low setup time to first DCLK rising edge

tCSH

nCS low hold time aftemcLK rising edge

tosu

100

Data setup time before rising edge on DCLK

tOH

Data hold time after rising edge on DCLK

tco

DCLK to DATA out delay, Note (5)

tCK

Clock period

fCK

Clock frequency

tCl

DCLK low time

tCH

DCLK high time

txz

low ornCS high to DATA output disabled

tOEW

pulse width to guarantee counter reset

tCAse

Last DCLK + 1 to nCASC low delay

tCKXZ

Last DCLK + 1 tODATA tri-state delay

tCEOUT

nCS high to nCASC high delay

100

ns
75

MHz

160

ns
ns
ns
50

100

ns
ns

Notes to tables:
(1)
(2)
(3)
(4)
(5)

Product
Availability

Package
Outlines
I Page 348

Product Grade

Availability

Commercial Temp.

(0° C to 70 C)

EPC1213, EPC1064

Industrial Temp.

(-40 0 C to 85° C)

Consult factory

Military Temp.

(-55 0 C to 1250 C)

Consult factory

See the Package Outlines Data Sheet in this data book for dimensions of the
Configuration EPROM 8-pin PDIP and 20-pin PLCC packages. For package
outlines of the 32-pin TQFP Configuration EPROM, contact Altera
Applications at (800) 800-EPLD.
Altera Corporation

Contents
I August 1993

Section 8

Military
Military Products ........................................................................................... 351

I Altera Corporation

Page 349

Military Products
I August 1993, ver. 3

Introduction

Data Sheet

Altera's military devices are manufactured in proven EPROM, EEPROM,
and SRAM technologies, providing an optimum combination of reliability,
speed, density, and low power consumption. Altera offers military devices
that meet military-temperature-range, MIL-STD-883B, and DESC
requirements. This data sheet discusses the following topics:

o
o
o

Product
Availability

Product availability
MIL-STD-883B qualification flow
Source control drawings

Tables 1 and 2 provide information on military-temperature-range,
MIL-STD-883B-qualified, and DESC devices. For more information on
Altera's military products, contact Altera Marketing at (408) 894-7000. For
detailed device information, refer to the appropriate data sheets in this
data book.

Table 1. Altera Military-Temperature-Range Devices
Device

Max

Unit

tpD1

Package (1)

Symbol

EP610

D, J

EP910

D, J

EP1810

G,J

tpD1

EPM5032

D, J

tpD1

EPM5064

tpD1

30,35

EPM5128

G,J

tpD1

30,35

EPM5130

G,J,W

tpD1

30,35

EPM5192

G, J

tpD1

EPM7192

tpD1

15,20

EPF8452

EPF81188

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

D, J

f MAX

MHz

EPS448

Note:
(1)

I Altera Corporation

Package configurations:
D: Ceramic dual in-line package (CerDIP)
J:
Ceramic J-lead chip carrier GLCC)
G: Ceramic pin-grid array (PGA)
W: Ceramic quad flat pack (CQFP) in QFP carrier
Page 351

I Military Products

Data Sheet

Table 2. Altera MIL-STD-8838-Qualified & DESe Devices
Device

Package

Symbol

Max

Unit

Altera Military
Drawing

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

020-00522

5962-8947601 LA

020-00782

5962-8946901 YC

020-00828

5962-9061102XA

020-01015

Note (2)

Note (1)
EP610

tpD1

EP1810

tpD1

EPM5032

tpD1

EPM5128

tpD1

EPM5128

tpD1

EPM5130

tpD1

EPM5130

tpD1

EPM5130

tpD1

EPM5130

tpD1

EPM5192

tpD1

EPM5192

tpD1

EPM7192

tpD1

15,20

EPF8452

G
G

EPF81188

DESC Order
Number

020-01015

5962-8946801 XC

020-01413

5962-9314402MZC

020-01413

5962-9314401 MZC

020-01413

5962-9314402MYA

020-01413

5962-9314401 MYA

020-01359

5962-9206202MZC

020-01359

5962-9206201 MZC

C.F.

Notes:
(1)

(2)

Package configurations:
D: Ceramic dual in-line package (CerDIP)
G: Ceramic pin-grid array (PGA)
W: Ceramic quad flat pack (CQFP) in QFP carrier
DESC number pending

MIL-STD-BB38
Qualification
Flow

I Page 352

Figure 1 shows the process flow for qualifying Altera devices to
MIL-STD-883B specifications.
MIL-STD-883B-compliant device specifications are provided in Military
Product Drawings (MPDs) that are available on request from Altera
Marketing. An MPD is prepared in accordance with the appropriate military
specification format and is used for preparing Source Control Drawings
(SCDs).

Altera Corporation

I Data Sheet

Military Products

Figure 1. MIL-STD-8838 Qualification Flow
Sort

Final Test

Pre Burn-In Test 25° C
(DC, Program, Function &
ACTests)

Burn-In
(Method 1015/C or D,
160 hrs., min 125° C)

Post Burn-In Test 25° C
(DC, Function,
PDA < 5% & AC tests)

Assembly

Erase

Qualification Complete
:------------------------------------------------------------------------._--_!

I Altera Corporation

Page 353

I Military Products

Data Sheet

Source Control
Drawings

Source Control Drawings (SCDs) are generated for Altera's commercial
devices that are or will be qualified for MIL-STD-883B. SCDs are also used
for document control. An SCD should be based on a Military Product
Drawing (MPD) provided by Altera. When an MPD is not available, the
user should contact Altera's Marketing Department for current data. Altera
MPDs contain information on the scope, reference documents, MIL-STD883B requirements, quality assurance provisions, and preparation of
delivery for devices. Characteristics of device screening-such as bum-in
testing, AC/DC electrical properties, timing waveforms, and package
dimensions-are also detailed in MPDs. These specifications may differ
from those for Altera's commercially rated devices. Altera will not approve
an SCD until the described MPD requirements are met.
Figure 2 shows the process flow for generating an SCD for Altera's military
products.

Figure 2. Source Control Drawing (SCD) Generation Flow

Begin
SCD process

Obtain military
product data from
Altera Marketing

Edit SCD
Use current data
to generate
customer drawing

Submit customer
drawing to
Altera for review
Altera ships
military product to
SCD specifications

I Page 354

Altera Corporation

Contents
I August 1993

Section 9

MPLD
MPLDs: Mask-Programmed Logic Devices ............................................... 357

I Altera Corporation

Page 355

MPLDs
Mask-Programmed Logic Devices

I August 1993, ver. 2

Features

Data Sheet I

o
o

o
o
o
o
o
o

General
Description

Masked versions of Altera programmable logic devices
Reduced cost for high-volume production
Available for high-density MAX 5000 devices, MAX 7000 devices, and
FLEX 8000 devices
Pin-, function-, and timing-compatible with original device
Conversion process handled by Altera
Fast turn-around to reduce time-to-market
Test vectors generated by Altera
Low power consumption
N-to-l option combines multiple Altera programmable devices into a
single MPLD

Altera Mask-Programmed Logic Devices (MPLDs) provide a masked
alternative to programmable logic devices. By using a generic CMOS
process and removing all programmable cells, Altera passes considerable
savings on to customers who anticipate high-volume production. The
combination of Altera programmable logic devices and MPLDs provides
the best of both worlds: the fast time-to-market offered by programmable
devices, and the low cost and low risk offered by MPLDs. See Figure 1.

Figure 1. MPLD
Economics
~

As volumes increase
during production, a
design can move from
erasablelreconfigurable
devices to MPLDs.

EPM5192JC

Development &Proto typing
with Reprogrammable
Devices

Initial Production with
Low-Cost Plastic Devices

>
~

EPM5192LC

MPM5192LC

Stable Design, HighVolume Production with
Masked Devices

Relative Volume

I Altera Corporation

Page 357

I MPLDs: Mask·Programmed Logic Devices

Data Sheet I

Altera handles the programmable logic device-to-MPLD conversion so
that no redesign effort is required. Altera guarantees that the MPLD meets
the worst-case AC and DC parameters of the original Altera programmable
logic device. In addition, Altera automatically generates test vectors with
98% fault coverage.

MPLD
Compatibility

An Altera MPLD is guaranteed to be pin-, function-, and timing-compatible
with the original programmable logic device. This guarantee ensures that
the MPLD can replace the original Altera device, while providing lower
cost and maintaining the production flow.

Pin compatibility guarantees that both the pin-out and DC specifications of
the MPLD match those of the original device. In addition, the MPLD
typically consumes less power than the equivalent programmable device,
depending on the design and operating conditions.
Functional compatibility is ensured because the logic within the
programmable logic device (e.g., product terms, programmable flipflops,
etc.) is mapped directly to specially designed elements within the MPLD.
Altera employs a proprietary logic synthesis program that uses the
Simulator Netlist File (.snf) generated by Altera's MAX+PLUS II software.
The SNF describes the final synthesis, placement, and routing of the
original design. The conversion process pays special attention to the wide
fan-in of product terms and the wide fan-out of registers commonly found
in programmable logic applications.
An MPLD is guaranteed to meet the worst-case timing parameters of the
corresponding programmable logic device, as specified in the device data
sheet. If a worst-case analysis of the design implementation in the
programmable has been performed, the same analysis will hold for the
MPLD. Therefore, the timing of the original design and the overall system
are maintained when the programmable device is replaced with an MPLD.

Design for
Testability

Unlike ASIC designs, which require time-consuming test vector generation,
Altera programmable logic devices do not require test vectors: the devices
are fully tested before they are shipped and are verified at programming
time.
MPLD designs include a scan-based testing method that parallels the
testability of Altera programmable logic devices. This patented test
methodology allows Altera to create test vectors with 98% fault coverage
for all "stuck-at" and open faults. This high fault coverage is maintained
regardless of whether synchronous or asynchronous design techniques are
used.

I Page 358

Altera Corporation

I Data Sheet

MPLDs: Mask-Programmed Logic Devices

The built-in design-for-testability in MPLDs frees the design engineer
from the burden of creating a testable design and test vectors. In fact,
customer-provided simulation vectors are optional for MPLD conversions.

N-to-1 MPLD
Conversion
Option

Many applications use multiple Altera programmable logic devices on a
single board for both prototyping and production. In some applications, it
may be desirable to perform prototyping with multiple programmable
devices, then shift to a single-device implementation for high-volume
production. Altera's MPLD conversion program provides this capability
with the "N-to-l" conversion option, which combines a multi-device design
into a single MPLD. The N-to-l conversion offers the benefits of developing
with multiple programmable logic devices, even when production
constraints require a high-density, single-device solution.
The N-to-l MPLD conversion works in conjunction with the design
partitioning feature inMAX+PLUS II software. Partitioning allows a design
engineer to create a large design without concern for design size or fitting
constraints. MAX+PLUS II automatically partitions the design and fits
each portion into a separate programmable device. Multiple programmable
devices can be used for design prototyping while simulation and timing
analysis can be completed on the top-level design.
The N-to-l MPLD option provides a single MPLD that is function- and
timing-compatible with the original multi-device solution. The package
type and pin-out are determined by the application's requirements. A
wide range of packages is available.

Quick,
Seamless
Conversion

One of the principal objectives of Altera's MPLD conversion program is to
minimize the design engineer's time and resource investment in the
conversion. The engineer simply submits design files created with
MAX+PLUS II software and Altera delivers MPLDs within weeks of the
design sign-off.
The MPLD conversion flow chart (see Figure 2) shows how easily a
programmable Altera device can be converted into an MPLD. The MPLD
Conversion Information & Order Forms workbook, which can be obtained
from an Altera representative, provides the instructions and forms needed
to submit a design for quotation. The design engineer submits the design
files and the workbook's Checklist, Information Form, and Questionnaire to
Altera. Altera then performs a design evaluation and returns a price quote
for the conversion.

I Altera Corporation

Page 359 I

I MPLDs: Mask·Programmed Logic Devices
Figure 2. MPLO
Conversion Flow

Data Sheet

Customer

Altera

Submit Design Packet

Evaluation

Review

Conversion
(5 weeks;
6 weeks for
N-to-1 MPLDs)

}

Prototype
Evaluation

Prototype Sign-Off

}
I Page 360

Production
(10 to 12 weeks)

Altera Corporation

I Data Sheet

MPLDs: Mask-Programmed Logic Devices I

After the customer submits an order for the Design Conversion Cost
(DCC), an Altera engineer reviews the design and submits a Final Design
Sign-Off Form for customer approval. This form describes the specifications
of the MPLD in detail. After the final design has been signed off, Altera
begins the design conversion.
The design conversion includes netlist translation, logic synthesis, testability
insertion, Automatic Test Vector Generation (ATVG), fault grading, timing
analysis, place-and-route, post-route timing analysis, design validation,
and the prototype manufacturing. The entire conversion process, from
final design sign-off to prototype delivery, takes less than 5 weeks (6 weeks
for N-to-1 conversion). Production quantities are delivered 10 to 12 weeks
after the customer returns the Prototype Sign-Off Form.

Conclusion

I Altera Corporation

The two most important design goals faced by engineers today are reducing
time-to-market and minimizing system cost. The combination of Altera
programmable logic devices and MPLDs provides a solution that fills
these needs, allowing a company to take a product to market quickly,
lower the end-product cost, and reduce the risks associated with ASIC
design.

Page 361

Notes:

Contents
I August 1993

Section 10

Device Operation
Operating Requirements for Altera Devices ............................................. 365
Application Note 33 (Configuring FLEX 8000 Devices) .......................... 383
Application Brief 100 (Understanding EPLD Timing) ............................ .419

I Altera Corporation

Page 363

Operating Requirements
for Altera Devices
IAugust 1993, ver. 5
Introduction

Data Sheet

Altera devices combine unique programmable logic architectures with
advanced CMOS processes to provide exceptional performance and
reliability. To maintain the highest possible performance and reliability of
Altera devices, system designers must consider the following operating
requirements:

o
o

Operating
Conditions

Operating conditions
Pin voltage levels
Output loading
Power-supply management
Thermal analysis
Reduction of heat build-up
Device erasure

Altera devices are rated according to a set of defined parameters, which
must be considered when a device is implemented in a system. These
parameters are provided in each device data sheet and include absolute
maximum ratings, recommended operating conditions, and DC and AC
operating conditions.

Absolute Maximum Ratings
Absolute maximum ratings define the limits of the conditions that a
particular Altera device can withstand. These values are based on
experimental evidence of device behavior, as well as theoretical modeling
of breakdown and damage mechanisms. These ratings are stress ratings
only. Functional operation of the device at these conditions or at conditions
above those indicated in the "Recommended Operating Conditions" table
in a device data sheet is not implied. For example, lOUT is the absolute
current capacity and not the drive capability of an output pin. The output
source and sink currents are given as 10H and 10L in the "DC Operating
Conditions" section of each data sheet.
Operating an Altera device at conditions listed in the Absolute Maximum
Ratings" table in a device data sheet for extended periods of time may
impair device reliability. Operating the device at conditions that exceed
these ratings may cause permanent damage to the device.
U

I Altera Corporation

Page 365

I Operating Requirements for Altera Devices

Data Sheet

Recommended Operating Conditions
The functional operation limits for an Altera device, given in the
"Recommended Operating Conditions" table in a device data sheet, specify
limits under which all AC and DC parameters are guaranteed. These
parameters may also be expressed differently in other rating sections. For
example, the Vcc range specified in this table is the range over which the
AC and DC operating conditions are guaranteed. The Vee range specified
in the "Absolute Maximum Ratings" table is the power-supply level beyond
which the device will be damaged.

DC Operating Conditions
The steady-state voltage and current values expected from an Altera
device are provided in the "DC Operating Conditions" table in a device
data sheet. This information includes input voltage sensitivities (VIH' V IL ),
output voltage (VOH, VOL), current capability (lOH' IoL)' and input and
output leakage currents (II' Ioz). The values are guaranteed for DC operation
under the conditions specified in each device data sheet.

AC Operating Conditions
The external and internal timing parameters for an Altera device are given
in the" AC Operating Conditions" table(s) in a device data sheet. These
parameters are determined under the conditions specified in the
"Recommended Operating Conditions" table. The external timing
parameters are guaranteed pin-to-pin delays when the device is operating
under these conditions.
Timing parameters are specified as either maximum or minimum values.
A maximum value indicates that the delay will not exceed the specified
time. Setup, hold, and pulse width times are expressed as minimum values
that the system must provide to ensure reliable device operation.

Pin Voltage
Levels

Device pins can be exposed to dangerous voltages during handling or
device operation. During handling, pins can be exposed to high-voltage
static discharges that cause electrostatic discharge (ESD) damage. During
operation, power-supply spikes on the vee and GND pins or errant logic
levels elsewhere in the system can produce logic level stress with voltages
on the order of magnitude of Vee (0 V to 15 V). To minimize these hazards,
the user must observe the precautions specified for the following conditions:

o
o
o

I Page 366

Pin connections
Latch-up
Hot-socketing
Electrostatic discharge

Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices

Pin Connections
During project compilation, MAX+PLUS II software generates a device
utilization report, called a Report File (.rpt), that provides information on
the pin-outs and connectivity of the device(s) used in the project. The
Report File includes a pin-out diagram that shows the user signal pins, vee
and GND pins, and reserved pins.
The vee and GND pins should be tied to the Vee or GND planes on the
printed circuit board (PCB) respectively. Dedicated input pins used in a
design and 110 pins configured as inputs should always be driven by an
active source. 110 pins configured as bidirectional pins should always be
driven whenever the 1/ 0 pin is used as an input.
Unused dedicated input and I/O pins are marked in the Report File as GND
and RESERVED, respectively. Unused dedicated inputs should be tied to
the GND plane. Otherwise, these pins may "float" in an indeterminate
state, possibly increasing DC current in the device and introducing noise
into the system. Since reserved I/O pins are driven by active signals
representing the buried logic present in the logic cell associated with that
particular pin, reserved I/O pins should remain unconnected. Tying a
reserved 1/ 0 pin to either Vee or GND creates contention that may
damage the output driver on the device.
For proper operation, signals on the input and output pins must be in the
following range:
GND:::; (VIN or VOUT) :::; Vee

Latch-Up
Parasitic bipolar transistors, which are present in the fundamental structure
of CMOS devices, may be paths for dangerous currents in the device.
Typically, the base-emitter and base-collector junctions of these transistors
are not forward-biased, so the transistors are not turned on. Figure 1 shows
a cross-section of a CMOS wafer and primary parasitic transistors. To
ensure that all junctions remain reverse-biased, the P-type substrate is
connected to the most negative voltage available on-chip (GND), and the
N-type well structure is connected to the most positive voltage on-chip
(Vee)·

I Altera Corporation

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I Operating Requirements for Altera Devices

Data Sheet

Figure 1. Parasitic Bipolar Transistors in CMOS
vee

GND

P-Substrate

Figure 1 also shows the parasitic resistors that occur in the CMOS structure.
Generally, these resistors are of no concern as long as currents do not flow
through the structure laterally. However, I-R drops may occur in the
structure if any of the associated diodes turn on. These diodes may be
initially turned on by power-supply or I/O pin transients that exceed the
limits of GND and Vee. These transients can be induced by signal ringing
and other inductive effects in the system.
Catastrophic failure can occur if these parasitic structures begin to conduct,
since the effect is regenerative and reinforces itself until potentially
destructive currents flow. This silicon-controlled rectifier (SCR) effect is
called "latch-up." As the current flows through the parasitic transistor, the
I-R drop through the resistor increases, further forward-biasing the baseemitter junction. The cycle continues until the current is limited by drops
in the primary current path. At this point, this current may have reached a
level that permanently damages internal circuitry.
Altera devices have been designed to minimize the effects of latch-up,
caused by power-supply and I/O pin transients. Under recommended
operating conditions, all devices are guaranteed to withstand input voltage
extremes of between GND -1 V and Vee + 1 V, as well as input currents of
100 rnA or less that are forced through the device pins.

IV?

To minimize the chances of inducing latch-up during power-up,
GND should be applied to the device first, then Vee, and finally
the inputs. The power should be removed from the device in the
reverse order: first, the inputs are removed, then Vco and finally
GND.

Simultaneous application of inputs and Vee to the device, which may
occur as a power supply rises during power up, should be safe as long as
Vee meets the maximum rise time. The designer should ensure that the
inputs cannot rise faster than the supply at the Vee pin(s).

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Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices

Hot-Socketing
Latch-up frequently occurs when electrical subsystems are plugged into
active hardware, i.e., "hot-socketed." When a subsystem is plugged into
active hardware, the logic levels often appear at the subsystem's logic
devices before the power supply can provide current to the Vee and GND
grid of the subsystem board. This condition may lead to latch-up.
Increasing the length of the Vee and GND connections can reduce the
chances of latch-up during hot-socketing. If metal "fingers" are used for
the board connection, the Vee and GND fingers at the card edge should be
longer than the logic connections. This difference in length causes the
power supply to appear at the device before the logic levels, and is usually
sufficient to prevent latch-up. Off-the-shelf connectors with longer Vee
and GND connections can provide similar results.
Implementing the circuitry shown in Figure 2 also provides protection
against latch-up during hot-socketing. The diode structure provides a
"clamp" level on the input voltage, preventing it from swinging more than
one diode-drop away from a power-rail (-0.6 V to Vee + 0.6 V). The series
resistor also reduces the possibility of latch-up by restricting the current to
the device input and clamp diodes. This circuitry provides the maximum
protection against latch-up, but is usually required only if the input on the
device is tied directly to the edge connector. Device inputs that are driven
by other circuit elements in the subsystem are generally safe from latch-up,
since these elements provide a natural delay before the logic levels are
established.

Figure 2. Hot-Socket Protection
Board
VCC

1N4148

Board Edge
Connector

Device
Pin

100 Q

Altera
Device

1N4148

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I Operating Requirements for Altera Devices

Data Sheet

Electrostatic Discharge
Electrostatic discharge (ESD) resulting from improper device handling can
cause device failure that may not manifest itself for a long period of time.
Although ESD damage may result in immediate device failure, it more
frequently affects the long-term reliability of the device.
Device handling during the programming cycle increases exposure to
potential static-induced failure. During normal activity, the human body
can generate voltages of up to tens of kilovolts (kV). Wearing ground
straps during device handling and grounding all surfaces that come in
contact with components reduces the likelihood of damage. Synthetic
materials used in clothing can store large amounts of static electricity and
may also cause ESD.
Altera devices include special structures that reduce the effects of ESD at
the pins. Figure 3 shows a typical input structure for an Altera device.
Diode structures and specialized field-effect transistors shunt harmful
voltages to ground before destructive currents can flow. Most Altera
devices can withstand ESD voltages greater than 2 kV, but all devices are
guaranteed to withstand ESD voltages greater than 1 kV.

Figure 3. Altera Device Input Protection Structure
Diffused Resistor
Input

Substrate
(GND)

Output Loading

Output loading is typically resistive and/or capacitive. During
development, the designer should ensure that the target device can supply
both the current and speed necessary for the loads.

Resistive Loading
Resistive loading exists whenever a device output sinks or sources a
current in a steady state. Examples of resistive loading include devices
with TTL inputs, terminated buses, and discrete bipolar transistors.
Output current capabilities (lOH and IOL), which are functions of output
voltages (VOH and Vod, are given in the data sheet for each device. In a DC
condition, output current capabilities determine the maximum resistivity

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I Data Sheet

Operating Requirements for Altera Devices I

of a load while still maintaining the necessary output voltage. If the system
requires higher currents, such as those necessary to drive an LED or a
relay, a high-current buffer or a discrete current switch must be used.
Short-circuit conditions-where IOH and IaL exceed the absolute maximum
rating (IoUT)-can permanently damage the device.

Capacitive Loading
The" AC Operating Conditions" table in a device data sheet specifies an
output capacitance condition (C1) for parameters relating to external
performance. For most Altera devices, C1 is 35 pF for active signals and
5 pF for high-impedance parameters.
Device packages and board-level trace capacitance contribute the majority
of loading capacitance. (An insignificant amount of the total capacitance
on output buffers is attributable to the gate capacitance of CMOS device
inputs.) The specified 35-pF load condition is a representative value for
most CMOS circuits. For applications in which a device drives a higher
capacitance, performance decreases as the capacitive load increases.
Device sockets are a source of both capacitive and inductive loading. Once
a system is finalized for production, sockets should be removed if possible,
and the devices should be mounted directly onto the PCB. Direct board
mounting reduces both the capacitive load and noise from socket contacts.
To ensure the highest circuit performance, the capacitance on device
outputs should be minimized. Since wiring traces on the PCB, device input
pins, and device packaging all contribute to the total capacitance, the
following guidelines should be observed:

Board layout should ensure that signals run perpendicular to each
other to provide a minimum capacitive coupling effect. Also, signal
traces should be kept as short as possible.

A high-current buffer should be used to speed the signal to all
destinations for networks in which a single source drives many loads.

The lack of Vee and GND planes or excessive trace lengths may cause
problems with radiated coupling of noise into logic signals and
transmission-line effects on signal quality. These ringing and noise elements
on logic levels can lead to circuit reliability problems. When recommended
layout practices cannot be implemented to prevent transmission-line
problems, a small series resistance (10 Q to 30 Q) can be used to reduce the
magnitude of undershoot and overshoot on signal edges. This resistance
dampens the ringing that can occur on long board traces and prevents false
triggering.

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I Operating Requirements for Altera Devices

Power-Supply
Management

Data Sheet

Although Altera devices are designed to minimize noise generation and
susceptibility, they-like all CMOS devices-can be sensitive to fluctuations
in power supply and input lines. To minimize the effect of these fluctuations,
the system designer must pay special attention to:

o
o
o
o

Vee and GND planes
Decoupling capacitors
Vee rise time
Current dissipation

Vee & GND Planes
The system designer can minimize power-supply noise or "ground bounce"
by providing separate Vee and GND planes for every PCB, thus ensuring
a near-infinite current-sink capability, noise protection, and shielding for
logic signals on the board. If an entire plane cannot be provided, the widest
possible GND and Vee traces should be created throughout the entire
board. Logic-width traces should not be used to carry the power supply.
Although Vee and GND planes tend to increase the capacitive load of the
traces, they significantly reduce system noise, and dramatically increase
system reliability.

Decoupling Capacitors
Each vcc and GND pin should be connected directly to the Vee and GND
planes in the PCB. Each pair of vcc and GND pins should be decoupled with
a O.2-~F power-supply decoupling capacitor,located as close as possible to
the Altera device. For devices with a very large number of vcc and GND
pins-Le., more than 8 pairs of each-it may not be necessary to provide a
decoupling capacitor for every pair. Decoupling requirements are based
on the amount of logic used in the device, the frequency of operation, and
the output switching requirements. As the number of II OS and the switching
frequency increase, more decoupling capacitance is required. The ideal
solution is to provide a capacitor for every vcc/GND pair, which will
decouple the device for any logic utilization or operating frequency. For
less dense or slower designs, a reduction in the number of capacitors may
be acceptable. For example, the EPM7192 has 14 vcc/GND pairs. In general,
8 decoupling capacitors are sufficient for most designs. Decoupling
capacitors should have a good frequency response, like that in monolithicceramic capacitors.
Every PCB should also have a large-capacity, general-purpose, electrolytic
capacitor network to stabilize the power supply. A 100-~F capacitor should
be placed immediately adjacent to the location where the power-supply
lines come into the PCB. If a transformer or regulator is used to change the
voltage level, the capacitor should be placed immediately after the final
stage that develops the device's Vee supply. This capacitor provides a

I Page 372

Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices

beneficial leveling effect that supplies extra current when a large number
of nodes switch simultaneously in a circuit. However, the larger the power
supply capacitor, the longer the time required to bring the maximum Vee
to the operating leveL The size of the capacitor must not force the Vee rise
time to violate the maximum rise time discussed next in /IVcc Rise Time. "

Vee Rise Time
When power is applied to an Altera device (with the exception of the
EPS448 device), the device initiates a Power-On Reset (POR), typically as
Vee approaches 1.5 V to 2.0 V. The POR event occurs only if Vee reaches
the recommended operating range within a certain period of time (specified
as a maximum Vee rise time). Slower rise times can cause incorrect device
initialization and functional failure. The maximum Vee rise times for
Altera devices are provided in Table 1.

Table 1. Maximum Vee Rise Time for Allera Devices
Device Family

Time

Classic

50 ms

MAX 5000/EPS464

10 ms

MAX 7000

10 ms

FLEX 8000

10 ms

EPS448

50 ms

The POR time is the time required after Vcc reaches the recommended
operating range to clear device registers, configure I/O pins, and release
tri-states. Once this initialization is complete, the device is ready to begin
logic operation. The POR time is typically no more than 50 ms.

Current Dissipation
Every Altera device is designed to consume the least possible amount of
power while providing high performance. Since these two design goals
can conflict with each other, Altera devices and software tools allow
designers to monitor and control the current with built-in device features.
MAX 7000 macrocells can be individually configured for high performance
or low power during design entry. Turning the macrocell's Turbo Bit on
allows the macrocell to function in a high-performance mode at the specified
device ratings. If the Turbo Bit is turned off, the macro cell' s built-in powersaving mode trades higher performance for lower current consumption.
MAX 7000 devices operating in low-power mode consume less current.
The supply current (led can be reduced by as much as 50%, depending on

I Altera Corporation

Page 373

I Operating Requirements for Altera Devices

Data Sheet I

the design and operating frequency. Most MAX 7000 device data sheets
provide a graph that shows the relationship between Icc and frequency.
For a device with the Turbo Bit option, the graph provides two curves;
one showing Icc versus frequency when all macrocells have their Turbo
Bits turned on, the other when all macrocells have the Turbo Bits off. Since
most designs use a combination of Turbo and non-Turbo macrocells, a
formula that accounts for this ratio and the frequency of operation is also
provided with the graph. The values shown in the graph and formula are
measured with no output loads and represent only the current necessary
for device operation.
Many Classic devices also have a Turbo Bit option. A Classic device
operating in low-power mode enters a standby mode after 100 ns of
inactivity (i.e., when no inputs or outputs have changed). An input signal
transition "wakes" the device, which then performs normally until the
next standby mode period. However, the signal incurs an additional
delay-specified as the non-Turbo delay adder in device data sheets-as it
wakes and propagates through the device.

Thermal
Analysis

A critical element of system reliability is the capacity of electronic devices
to safely dissipate the heat generated during operation. The thermal
characteristics of a circuit depend on the device and package used, the
operating temperature, the operating current, and the system's ability to
dissipate heat.
Thermal analysis should be completed early in the design process to help
identify potential heat-related problems in the system and prevent the
system from exceeding the device's maximum allowed junction
temperature. To perform a thermal analysis, the designer must:
1.
2.
3.

Estimate power consumption of the application.
Calculate the maximum allowed power for the device and package.
Compare the estimated and maximum allowed power values.

In most applications, the power dissipated is significantly lower than the

maximum allowed. However, this type of analysis should be performed
for all projects. Several steps that can correct temperature-related problems
are described later in this data sheet.

Estimating Power Consumption
The following formula should be used to estimate the maximum supply
current (Icd:
Estimated maximum Icc = no-load Icc + DCOUT + ACOUT

I Page 374

Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices I

The no-load Icc can be obtained from the Iccversus-frequency graph
provided in the device data sheet. Since this value is "unloaded," it is
necessary to add the DCoUT from steady-state outputs and the AC OUT
current from frequently switching outputs. DC OUT depends on the number
of steady-state outputs, the logic levels they drive, and the resistive load on
each output, as shown in the following formula:

DC OUT
In this formula, d is the number of DC outputs, VOn is the DC output
voltage of output n, Rn is the resistive load driven by output n.
AC OUT depends on the capacitive load on each output and the frequency at
which each output switches, as shown in the following formula:

AC OUT
In this formula, a is the number of AC outputs, C n is the capacitive load on
output n, Vn is the voltage swing of output n, and fn is the switching
frequency of output n.
The estimated maximum Icc is used together with the following formula
to estimate the maximum power (PEST):
PEST =

I.li?

estimated maximum Icc x Vee
The actual Icc should be measured after the project is completed
to verify PEST'

Calculating Maximum Allowed Power for the Device &Package
The following formulas are used to calculate the maximum allowed power
(PMAX) for a device:
_ 150 0 C - T AMB
PMAX8JA

_ 150 0 C - T CASE

or P MAX-

8JC

The maximum allowable power is dependent on the maximum allowable
junction temperature of the silicon, the ambient temperature of operation,
and the package's thermal resistance (8) when configured in the system.
The maximum junction temperature is specified as 150 0 C. The ambient
temperature depends on the application. The worst-case P MAX value is

I Altera Corporation

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I Operating

Requirements for Altera Devices

Data Sheet

estimated using the formula with SJAI the junction-to-ambient thermal
resistance. SJA is a measure of the worst-case thermal resistance for a device
in still air, with convection cooling only. If forced-air flow and heat-sinking
are used to dissipate heat, the designer should use the junction-to-case
thermal resistance, SJO to calculate PMAX for a device. SJC is a measure of
the lowest possible thermal resistance.
Tables 2 through 5 provide SJA and SJC values for AHera devices.
Table 2. Thermal Resistance of Classic Oevices

Pin Count

Package

EP330

PDIP
SOIC

68
88

19
17

EP610
EP610A
EP610T

CerDIP
PDIP
SOIC

60
55
77

10
18
17

JLCC
PLCC

90
74

12
13

EP910
EP910A

CerDIP
PDIP

40
49

12
23

EP910T

JLCC
PLCC

67
58

5
10

EP1810
EP1810T

JLCC
PLCC
PGA

47
44
38

12
13
6

Device

I Page 376

SJA

(0 C/W)

SJC

(0 C/W)

Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices

Table 3. Thermal Resistance of MAX 5000/EPS464 Devices
Device

Pin Count

Package

EPM5016

CerDIP
PDIP
PLCC
SOIC

62
61
C.F.
C.F.

10
27
C.F.
C.F.

EPM5032

CerDIP
PDIP
JLCC
PLCC
SOIC

44
48
69
59
C.F.

12
19
9
10
C.F.

EPM5064

JLCC
PLCC

62
52

15
9

EPM5128

JLCC
PLCC
PGA

39
44
32

11
12
2

EPM5128A

JLCC
PLCC

C.F.
C.F.

EPM5130

JLCC
PLCC

30
35

C.F.
11

100

COFP
POFP
PGA

50
50
26

11
10
4

EPM5192

JLCC
PLCC
PGA

30
35
27

4
11
2

EPM5192A

JLCC
PLCC

C.F.
C.F.

EPM5192A

100

COFP
POFP

C.F.
C.F.

JLCC
PLCC
POFP

68
52
C.F.

5
9
C.F.

EPS464

SJA

(0 C/W)

SJC

(0 C/W)

Note:
C.F. Consult Factory

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I Operating Requirements for Altera Devices

Data Sheet

Table 4. Thermal Resistance of MAX 7000 Oevices
Device

Pin Count

Package

9JA

(0 C/W)

9JC

(0 C/W)

EPM7032

PLCC
PQFP
TQFP

52
C.F.
C.F.

9
C.F.
C.F.

EPM7032V

PLCC
TQFP

C.F.
C.F.

EPM7064

PLCC

EPM7096

EPM7128

EPM7160

EPM7192
EPM7256

PLCC

100

PQFP

JLCC
PLCC

48
44

12
12

JLCC
PLCC

30
55

C.F.
11

100

CQFP
PQFP

50
50

11
10

PLCC

100

PQFP

C.F.

160

PQFP

PLCC

100

PQFP

160

PQFP

160

PGA
PQFP

20
40

7
7

192

PGA

208

CQFP
MQFP
RQFP

20
17
C.F.

6
8
C.F.

Note:
C.F. Consult Factory

I Page 378

Altera Corporation

I Data Sheet

Operating Requirements for Altera Devices

Table 5. Thermal Resistance of FLEX 8000 Devices
Device
EPF8282
EPF8282V
EPF8452

EPF8820

EPF81188

Pin Count

Package

OJA

(0 C/W)

OJC

(0 C/W)

PLCC

100

TOFP

C.F.

100

PGA
TOFP

C.F.
C.F.

PLCC

160

POFP
PGA

40
20

7
6

160

POFP
PGA

40
C.F.

7
C.F.

192

PGA

208

POFP
ROFP

232

PGA

240

MOFP
ROFP

40
C.F.

7
C.F.

20
C.F.

2
C.F.

Note:

c.F. Consult Factory

Comparing Maximum Allowed Power & Estimated Power
To avoid reliability problems, the system designer should compare the
values calculated for maximum allowed power and estimated power. The
estimated power should be the smaller of the two values. If the estimated
power exceeds the maximum allowed power, refer to "Reduction of Heat
Build-Up" next in this data sheet for suggestions on how to reduce power
requirements for a design.

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I Operating Requirements for Altera Devices

Reduction of
Heat Build-Up

Data Sheet

The following actions reduce power dissipation, and thus heat build-up,
for an application.
1.

Use available low-power features of the device. Classic devices and
individual MAX 7000 macrocells can be configured for low-power
operation, with only a nominal increase in propagation delay, by
turning the Turbo Bit off. All macrocells in the MAX 7000 device that
do not need to run in high-performance mode should be set to lowpower mode.

Choose a different device package. A ceramic or higher-pin-count package
can be used. Ceramic packages dissipate more heat than plastic
packages. Also, packages with higher pin counts can dissipate more
heat through the connection to the PCB.

Use forced-air cooling and/or heat-sinking. Forced-air cooling improves
the efficiency of convection cooling, reducing the surface temperature
of the device. A heat sink connected to a device significantly increases
heat dissipation by radiating heat via the metal mass.

Slow the operation in portions of the circuit. Icc is proportional to the
frequency of operation. Slowing parts of a circuit lowers the Icc and
hence reduces the power. Altera devices provide global or array Clock
sources for all registers. Signals that do not require high-speed
operation can use a slower array Clock that significantly reduces the
system power consumption.

Reduce the number of outputs. DC and AC current is required to support
all I/O pins on the device. Reducing the number of I/O pins may
reduce the current necessary for the project, and thereby reduce the
power.

Reduce the amount of circuitry in the device. Power depends on the
amount of internal logic that switches at any given time. Reducing the
amount of logic in a device reduces the current in the device. The same
effect may be achieved by using a larger device, which also provides
increased heat dissipation and maintains a single-device solution.

I Page 380

Choose a different device family. The MAX 7000 family provides more
power-saving features than the MAX 5000 family. The Classic family
provides power-saving features at low density.

Modify the design to reduce power. Identify areas in the design that can
be revised to reduce the power requirements. Common solutions
include reducing the number of switching nodes and/or required
logic, and removing redundant or unnecessary signals. For assistance
in locating less obvious changes, contact Altera Applications at
(SOO) SOO-EPLD.
Altera Corporation

I Data Sheet

Device Erasure

Operating Requirements for Altera Devices

Altera Classic, MAX 5000/EPS464, EPS448, and MAX 7000 devices use
non-volatile, reprogrammable EPROM or EEPROM memory cells to retain
the configuration data so that the configuration data does not need to be
reloaded when the system powers up. EPROM and EEPROM memory-cell
technologies have similar programming characteristics, but different erasure
mechanisms.
Altera's EPROM-based devices are available in both plastic and ceramic
packages. Plastic packages for EPROM devices are one-time-programmable
(OTP) devices; windowed ceramic packages allow erasure by exposure to
UV light. Altera EPROM-based devices begin to erase when exposed to
lights with wavelengths shorter than 4,000 A. Since fluorescent lighting
and sunlight fall into this range, an opaque label must be placed over the
device window to ensure long-term reliability. To completely erase a
device, it must be exposed to UV light with a wavelength of 2,540 A.
Devices should be erased for one hour by an eraser system with a power
rating of 12,000 IlW /cm 2 . Altera devices may be damaged by long-term
exposure to high-intensity UV light.
Altera guarantees that its EPROM-based devices can be programmed and
erased at least 25 times, provided the recommended erasure exposure
levels are used. Most devices can be reliably erased and reprogrammed
many more times beyond this guaranteed minimum.
Altera's EEPROM-based devices are available in reprogrammable plastic
packages. (The EPM7192 is also available in a windowless ceramic PGA
package.) EEPROM cells are electrically erasable and therefore do not have
an erasure window. These EEPROM-based devices are erased immediately
before being programmed, and can be erased and reprogrammed at least
100 times. Most devices can be reliably erased and reprogrammed many
more times beyond this guaranteed minimum.

I Altera Corporation

Page 381

Notes:

Configuring FLEX 8000
Devices
I August 1993, ver. 2

Introduction

Application Note 33

The architecture of Altera's Flexible Logic Element MatriX (FLEX) devices
supports several different configuration schemes for loading a design into
one or more devices on the circuit board. This application note provides
complete details on all aspects of FLEX 8000 device configuration, including
sample schematics and timing information.
This application note should be used together with the FLEX 8000
Programmable Logic Device Family Data Sheet and the Configuration EPROMs
for FLEX 8000 Devices Data Sheet in this data book. If appropriate, illustrations
in this application note show devices with generic "FLEX 8000" and
"Configuration EPROM" labels to indicate that they are valid for all
FLEX 8000 devices and Altera Configuration EPROMs. All timing parameters shown in figures and tables apply to all FLEX 8000 device speed
grades.
The following topics are discussed:

FLEX 8000 Device Operating Modes .................................................. 383
Overview of Configuration Schemes .................................................. 384
o Choosing a Configuration Scheme ...................................................... 385
o FLEX 8000 Device Configuration Schemes ........................................ 387
Active Serial Configuration .......................................................... 387
Active Parallel Up & Active Parallel Down
Configuration ......................................................................... 390
Passive Parallel Synchronous Configuration ............................ 394
Passive Parallel Asynchronous Configuration .......................... 396
Passive Serial Configuration ...................................................... .400
DIn-Circuit Reconfiguration ................................................................... 404
o Configuration Control Features .................................. ~ ...................... .405
o MAX+PLUS II Configuration & Programming Support ................ .411
o Configuration Reliability ...................................................................... 417

FLEX 8000
Device
Operating
Modes
I Altera Corporation

The FLEX architecture uses SRAM cells to store the configuration data for
the device. These SRAM cells must be loaded each time the circuit powers
up and begins operation. The process of physically loading the SRAM
programming data into the FLEX 8000 device is called configuration. After
configuration, the FLEX 8000 device resets its registers, enables its I/O
pins, and begins operation as a logic device. This reset operation is called
initialization. Together, the configuration and initialization processes are
called command mode; normal in-circuit device operation is called user mode.
Page 383

I Configuring FLEX 8000 Devices

Application Note 33 I

SRAM technology allows FLEX 8000 devices to be reconfigured in-circuit
by loading new configuration data. Real-time reconfiguration can be
performed by forcing the device into command mode with a dedicated
device pin, loading different configuration data, reinitializing the device,
and resuming user-mode operation. The entire process requires less than
100 ms, and can be used to dynamically reconfigure FLEX 8000 devices
during system operation.
Existing systems that incorporate FLEX 8000 devices can be updated by
installing new data in the system. Such in-field upgrades can be as simple
as copying a new configuration file to a hard disk, or inserting an EPROM
programmed with new configuration data into the circuit.
Device configuration can occur either automatically at system power-up
or under the control of external logic. Initialization can be controlled by the
internal oscillator in the FLEX 8000 device or by an external Clock signaL
Dedicated device configuration pins can be used to control when
configuration and initialization begin. This range of command-mode control
features provides excellent flexibility for designs implemented in FLEX 8000
devices.

Overview of
Configuration
Schemes

The configuration data for a FLEX 8000 device can be loaded with one of
six configuration schemes, which you choose on the basis of the target
application. Both active and passive schemes are available. In an active
configuration scheme, the FLEX device guides the configuration operation,
controlling external memory devices and the initialization process. The
Clock source for all active configuration schemes is an internal oscillator in
the FLEX 8000 device that typically operates in the range of 2 to 6 MHz. In
a passive configuration scheme, an external controller guides the configuration of the FLEX 8000 device, which operates as a slave. Table 1 shows
the source of data for each of the six configuration schemes.

Table 1. Configuration Schemes

Configuration Scheme

I Page 384

Acronym

Data Source

Active Serial

Altera Configuration EPROM

Active Parallel Up

APU

Parallel EPROM

Active Parallel Down

APD

Parallel EPROM

Passive Serial

Serial data path

Passive Parallel Synchronous

PPS

Intelligent host

Passive Parallel Asynchronous

PPA

Intelligent host

Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices I

Each FLEX 8000 device has a different size requirement for its configuration
data, based on the number of SRAM cells in the device. Table 2 shows the
amount of data, expressed in both bits and Kbytes, necessary to configure
each FLEX 8000 device. You can use this table to calculate the data space
(i.e., data storage resources) required in a parallel or serial data source for
a system that incorporates FLEX 8000 devices.
Table 2. FLEX 8000 Device Data-Size Spaces

Device

Data Size (bits)

Data Size (Kbytes)

EPF8282, EPF8282V

40,000

EPF8452

64,000

EPF8820

128,000

EPF81188

192,000

EPF81500

250,000

Active Configuration
In an active configuration scheme, the FLEX 8000 device controls the entire
configuration process and generates the synchronization and control signals
necessary to configure and initialize itself from an external memory. The
active serial (AS) configuration scheme uses an Altera Configuration
EPROM to store the configuration data. The active parallel up (APU) and
active parallel down (APD) configuration schemes use a parallel-format
memory such as a 32K x 8-bit EPROM as the data source.

Passive Configuration
In a passive configuration scheme, the FLEX 8000 device is incorporated
into a system with an intelligent host that controls the configuration
process. The intelligent host transparently selects a serial or parallel data
source, and the data is presented to the FLEX 8000 device on a common
data bus. In this type of system, the configuration data can be stored in a
mass-storage medium, such as a hard disk. With passive configuration
schemes, new configuration data is easily installed by supplying a new
configuration file on a diskette or tape.

Choosing a
Configuration
Scheme

I Altera Corporation

The best configuration scheme for a particular application depends on
many factors, such as the presence of an intelligent host in the system, the
need to reconfigure in real-time, and the need to periodically install new
configuration data. Available board space is also a consideration for configuration schemes that use parallel or serial EPROMs to store configuration
data.

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I Configuring FLEX 8000 Devices'

Application Note 33

The following guidelines can help you decide which configuration scheme
is most appropriate for your application:

For fast time-to-market, the easiest and quickest configuration schemes
to implement are the three active configuration schemes: active serial
(AS), active parallel up (APU), and active parallel down (APD). These
configuration schemes require no external intelligence. The FLEX 8000
device is typically configured automatically at system power-up. If
the FLEX 8000 device senses a power failure, it automatically triggers
a reconfiguration cycle.

For fast prototyping and development work, the passive serial (PS)
configuration scheme, together with the FLEX Download Cable,
provides the quickest means of iterative design analysis. The
MAX +PLUS II Programmer can directly download configuration data
to a FLEX 8000 device on the prototype circuit board.

If a FLEX 8000 device is incorporated into a system with an intelligent
host, you can use this host to control the configuration process in one
of the passive configuration schemes: passive parallel asynchronous
(PPA), passive parallel synchronous (PPS), or passive serial (PS). The
configuration data can be stored in a mass-storage medium, such as a
hard disk, thereby reducing the number of ICs required for the system.
The FLEX 8000 device configuration can also be synchronized with
any other system resources that must be initialized.

In applications that require real-time device reconfiguration-such as
data transformation filters, video formatters, and encryption/
decryption circuits-the best choice is one of the passive configuration
schemes. Reconfigurability allows you to reuse the logic resources
within the FLEX 8000 device, instead of designing redundant or
duplicate circuitry into your systems. Passive configuration schemes
easily support the multiple sources of configuration data that may be
required for real-time configuration. However, these schemes require
more external circuitry. The FLEX 8000 device must rely on an intelligent host to retrieve and load new configuration data, and cannot
perform any of the tasks required for reconfiguration.

If field upgrades are anticipated, passive configuration schemes offer
the ability to easily install new configuration data. New configuration
files can be supplied to end users on diskette or tape. (In active
schemes, a new EPROM must be inserted into the system.)

You can also use multiple configuration schemes during system operation.
If you choose a single configuration scheme, you can simply hard-wire the
three configuration scheme selection pins (nSP, MSEL1, and MSELO) to
their necessary levels (Vee or GND). If you use multiple configuration

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Altera Corporation

I Application Note 33

Configuring FLEX 8000

DeVic~

schemes, you can drive these selection pins with some controlling logic or
connect them to a port on an intelligent host. For example, you can
configure a FLEX 8000 device with an AS configuration scheme to load its
"start-up" configuration data, then dynamically change the configuration
scheme selection bits to select a different configuration scheme, and provide
a different configuration data source.

FLEX 8000
Device
Configuration
Schemes

The following sections describe each configuration scheme in detail:

o
o
o
o
o
o

Active serial (AS)
Active parallel up (APU)
Active parallel down (APD)
Passive parallel synchronous (PPS)
Passive parallel asynchronous (PPA)
Passive serial (PS)

In-circuit reconfiguration, device configuration option bits, device
configuration pins, and the source of data for each configuration scheme
are described later in this application note.

Active Serial Configuration
The active serial (AS) configuration scheme uses an Altera-supplied serial
Configuration EPROM (e.g., EPC1213) as a data source for FLEX 8000
devices. The Configuration EPROM presents its data to the FLEX 8000
device in a serial bit-stream. Figure 1 shows a typical circuit in which the
FLEX 8000 device controls the configuration process and uses a serial
Configuration EPROM as the data source.

Figure 1. Active Serial Device Configuration
FLEX 8000

vee

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I Configuring FLEX 8000 Devices

Application Note 33

The nCONFIG pin on the FLEX 8000 device in Figure 1 is connected to Vee,
so the device automatically configures itself at system power-up. The
system can monitor the nSTATUS pin to ensure that configuration occurs
correctly. Immediately after power-up, the FLEX 8000 device pulls the
nSTATUS pin low and releases it within 100 ms. Once released, the opendrain nSTATUS pin is pulled up to Vee by an external l.O-kn pull-up
resistor. If an error occurs during configuration, the FLEX 8000 device
pulls the nSTATUS pin low, indicating that configuration was unsuccessful.
The DCLK signal, which is driven by the FLEX 8000 device, clocks sequential
data bits from the Configuration EPROM. While the SRAM data is being
loaded, the FLEX 8000 device holds the open-drain CONF_DONE pin at
GND, indicating that data is loading. A 24-bit program-length counter
within the FLEX 8000 device stores the program length, i.e., the total
number of configuration bits. Once the terminal count value for the
configuration data (i.e., the last configuration data bit) has been reached,
the FLEX 8000 device releases the CONF_DONE pin, which is subsequently
pulled up to Vee by an externall.O-kW pull-up resistor. The resulting high
input on the nCS pin causes the Configuration EPROM to tri-state its DATA
output, electrically removing the Configuration EPROM from the circuit.
After it releases the CONF_DONE pin, the FLEX 8000 device uses it as an
input for monitoring the configuration process. When the FLEX 8000
device senses a high logic level on CONF_DONE, it completes the initialization
process and enters user mode. Figure 2 shows the timing associated with
the AS configuration process and the order of transitions on the control
signals.

Figure 2. Active Serial Configuration Timing Waveforms

nCS/CONF_DONE

DCLK

DATA

fcss--+!

:.- tcsxz

I Page 388

i- tCSH

Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

Table 3 provides values for the AS timing parameters.

Table 3. Active Serial Configuration Timing Parameters
Symbol
tOEZX
tcszx
tcSXZ
tCH
tCL
tosu
tOH
tco
tOEW
tcss
tCSH

Parameter

Min

OE high to DATA output enabled
nCS low to DATA output enabled
nCS high to DATA output disabled
DCLK high time
DCLK low time

Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK

80
80
50
0

nCS low to first DCLK rising edge
nCS low hold time after DCLK rising edge

Unit

50
50
50
250
250

100
100
0

ns
ns
ns
ns
ns
ns

DCLK to DATA out
OE low pulse width to guarantee counter reset

Max

ns
ns
ns
ns

In the circuit shown in Figure I, the nCONFIG pin on the FLEX 8000 device
is tied to the Output Enable (OE) input of the Configuration EPROM; both
are tied to Vcc. A high logic level on the nCONFIG input automatically
starts the configuration. The output of the serial Configuration EPROM is
enabled by a high input on its OE pin. If an error occurs during circuit
configuration, the FLEX 8000 device pulls and holds the nSTATUS pin low,
indicating a configuration error. External circuitry is used to monitor the
nSTATUS pin and take appropriate action if configuration fails. This circuitry
must assert a high-low-high pulse on the nCONFIG pin to reconfigure the
device after the error. The same circuitry can also be used to begin
reconfiguring the FLEX 8000 device at any time after system power-up.
The FLEX 8000 device's built-in Auto-Restart Configuration on Frame Error
option bit allows the device to automatically reconfigure itself if it encounters
an error during configuration. If this option bit is turned on, a configuration
error causes the FLEX 8000 device to pull the nSTATUS pin low for 10 internal
Clock cycles and then release it. This 1- to 3-~s pulse on the nSTATUS pin
provides an external indication that reconfiguration is about to begin. It
also can be used to reset the Altera Configuration EPROM.
Figure 3 shows a circuit that uses the Auto-Restart Configuration on Frame
Error option. The nSTATUS pin is connected to the OE input on the Altera
serial Configuration EPROM so that the error-reset pulse on nSTATUS
resets the internal address counter on the Configuration EPROM and
prepares it to reconfigure the FLEX 8000 device. The nCONFIG input is also
available to initiate a reconfiguration cycle externally. Since the nSTATUS
pin is pulled low and then released whenever configuration beginS, it

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I Configuring FLEX 8000 Devices

Application Note 33

resets the Configuration EPROM before reconfiguration. If Vcc drops
below the power-on reset (POR) threshold for the FLEX 8000 device
during device operation, nSTATUS is pulsed and the Configuration EPROM
is reset in the same way to provide automatic reconfiguration. Timing for
the circuit in Figure 3 is identical to the timing shown in Figure 2 for the AS
configuration scheme (the error-reset pulse on nSTATUS is not shown).
Figure 3. Active Serial Oevice Configuration with Automatic Reconfiguration on
Error
FLEX 8000

The Altera serial Configuration EPROMs are designed for performance
that is compatible with the setup and hold time requirements of FLEX 8000
devices. Refer to the Configuration EPROMs for FLEX 8000 Devices Data
Sheet in this data book for complete details on timing and circuitry. Details
on device programming are given in "Programming a Serial Configuration
EPROM" later in this application note.

Active Parallel Up &Active Parallel Down Configuration
In the active parallel up (APU) and active parallel down (APD) configuration
schemes, the FLEX 8000 device generates sequential addresses that drive

the address inputs to an external PROM. The PROM then returns the
appropriate byte of data on the data pins DATA [7 .. 0] . Sequential addresses
are generated until the FLEX 8000 device has been completely loaded. The
CONF_DONE pin is then released and pulled high externally, indicating
that configuration has been completed. The counting sequence can be
ascending (OOOOOH to 3FFFFH) for APU configuration or descending
(3FFFFH to OOOOOH) for APD configuration.
Figure 4 shows a typical circuit with a FLEX 8000 device and a parallel
EPROM for APU or APD configuration. In this circuit, the nCONFIG input
to the FLEX 8000 device is connected to a system-wide, active-low Reset

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I Application Note 33

Configuring FLEX 8000 Devices

signaL The nCONFIG pin can be tied to Vcc (as shown in Figure 1) to start
configuration automatically at system power-up; however, the systemwide Reset allows you to explicitly control the time at which configuration
begins. The nCONFIG pin must be held low to meet the minimum low
pulse width requirement for tCFG (see Table 4 later in this application note).

Figure 4. Active Parallel Device Configuration with a 256-Kbyte EPROM
FLEX 8000

256-Kbyte
EPROM

vee

System Reset - - - - - - . . J
(active low)

DATA[7,.OII+-----~~___1DATA[7 .. 0]

ADD[17 .. 0]

RDCLK

Figure 5 shows the timing associated with the circuit in Figure 4. The highlow-high pulse on the nCONFIG pin starts the configuration process. The
nSTATUS pin is pulled low for up to 100 ms, and the CONF_DONE pin is
pulled down to GND. Once the CONF_DONE pin is low, address generation
begins. The low logic level on the CONF_DONE pin also enables the output of
the EPROM. In an APU configuration scheme, the first address generated
is OOOOOH; in an APD configuration scheme, it is 3FFFFH.
The configuration events in Figure 5 are based on the RDCLK signal rather
than the DCLK signaL The RDCLK signal, a Clock signal that is generated by
dividing the DCLK signal by eight, is used to frame the data bytes supplied
by the parallel EPROM. In the APU and APD configuration schemes, the
FLEX 8000 device generates the DCLK signal internally and uses it to
serialize the incoming data words. On each pulse of the RDCLK signal, the
FLEX 8000 device latches an 8-bit byte, and the following eight pulses on
DCLK convert that 8-bit value into a serial data stream. The RDCLK signal is
available as an output pin during configuration. (In user mode, the RDCLK
pin is available as an I/O pin.) You can monitor this signal to ensure that
the parallel EPROM observes the data setup and hold time requirements
for the FLEX 8000 device.

I Altera Corporation

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I Configuring FLEX 8000 Devices

Application Note 33

Figure 5. Active Parallel Up Configuration Timing Waveforms
A rising edge on RDCLK increments the address counter ADDR[17..0j, which is driven
out to the parallel EPROM. The parallel EPROM then sends the addressed byte of
configuration data to the FLEX 8000 device.
nCONFIG

nSTATUS

-t+: : ;+tSTATUS
+: itCF2ST
-..j

:-:---tCF2CO

RDCLK

ADDR[17 .. 0)

DATA[7 .. 0)
;--tCF2AV

-i

:-tosu

A new address is presented on the ADD [ 17 .• 0] pins a short time (teA V)
after a rising edge on RDCLK. Table 4 shows the timing parameters for the
APU and APD configuration in Figure 4. Before the subsequent rising edge
on RDCLK, the external parallel EPROM must present valid data soon
enough to meet the t DSU setup time for the data. This subsequent rising
edge on RDCLK latches data, based on the address generated by the
previous Clock cycle. EPROMs with access times faster than 500 ns should
be used to guarantee the data setup time.

Table 4. Active Parallel Up & Down Configuration Timing Parameters
Symbol

Parameter

Min

Max

Unit

Ils
Ils

tCF2ST

nCONFIG low to nSTATUS low

t CFG

nCONFIG low pulse width

tSTATUS

nSTATUS low pulse width

2.5

tCF2CO

nCONFIG low to CONF _DONE low

tCF2AV

nCONFIG high to first valid address

tCAV

RDCLK rising edge to address valid

tOH

Data hold time after rising clock edge (RDCLK)

tosu

Data setup time before rising clock edge

1
3.5

Ils
Ils
Ils
Ils

(RDCLK)

Once the terminal count value for the FLEX 8000 device configuration data
is reached, the FLEX 8000 device releases the CONF_OONE pin. The CONF_OONE

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I Application Note 33

Configuring FLEX 8000 Devices

pin is pulled up to Vee via the pull-up resistor, and the FLEX SOOO device
disables the output on the EPROM. Since the DATA [7 .. 0] pins on the
EPROM are tri-stated after configuration, the corresponding DATA [7 •• 0]
pins on the FLEX SOOO device are available as I/O pins during user-mode
operation.
All FLEX SOOO devices provide IS address lines, which are sufficient to
uniquely decode up to 256 Kbytes of data, much more than the largest
FLEX SOOO device requires. See Table 2.
Although the IS address lines limit FLEX SOOO devices to addressing
256 Kbytes of data, you can use a larger EPROM device (e.g., 512 Kbytes,
1 Mbyte, 2 Mbytes, etc.) by masking in the necessary offset addresses. In
larger EPROMs, the FLEX SOOO device configuration information is treated
as a separate "page" in the EPROM, and can be placed on any convenient
boundary. However, some additional logic is required to provide the
offset address.
Figure 6 shows how you can use an Altera EP330 device as a decoder that
asserts the necessary page-offset address onto the address bus during
configuration. The EP330 allows the IS-bit address generated by the
FLEX SOOO device to select one of four 256-Kbyte "pages" in the EPROM.
The EP330 should monitor the nSTATUS and CONF_DONE signals to ensure
that errors are handled correctly. The inputs to the EP330 must be systemlevel control signals that select the appropriate page in the EPROM to be
loaded into the FLEX SOOO device, and control when the configuration
actually occurs. Timing for the circuit in Figure 6 is identical to the timing
shown in Figure 5.
'

Figure 6. Active Parallel Device Configuration with Offset Address Generation Circuitry
"1"
"0"

vee

1-Mbyte
EPROM

"0"= UP
"1"= DOWN

vee

1.0 kn

l+--+-----~-~DATA[7 .. 0]
1----+----......,..~._JADD[17 .. 0]

ADD[19 .. 18]

I Altera Corporation

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I Configuring FLEX 8000 Devices

Application Note 33

The active parallel configuration schemes can generate addresses in either
an ascending or descending order, depending on your system requirements.
Counting up (APU configuration) is appropriate if the FLEX 8000 configuration data is stored at the beginning of an EPROM, or if the configuration
data has been placed at some known offset in an EPROM larger than 256
Kbytes. Counting down (APD configuration) is appropriate if the low
addresses are not available, e.g., if the CPU code must use the beginning of
the EPROM or if the EPROM is also used to store other information that is
expected to increase as an application evolves. The changing nature of the
data size is characteristic of basic I/O system (BIOS) and boot PROMs.
Figure 7 shows an example of a BIOS EPROM memory map, in which the
FLEX 8000 configuration data is placed at the top of the memory space in
an APD configuration.

Figure 7. Typical BIOS EPROM Memory Map
00000
10000
30000
50000

Boot Code
Video Driver
Tape Driver
Monitor Code

60000
;;

FAOOO
FFFFF

EPF81188 (down)
Configuration Data

Passive Parallel Synchronous Configuration
In a passive parallel synchronous (PPS) configuration scheme, the FLEX 8000

device is tied to an intelligent host. With PPS configuration, data can be
driven directly onto a common data bus between the host and the FLEX 8000
device. The DCLK, CONF_OONE, nCONFIG, and nSTATUS signals are connected
to a port on the host. Although you can drive the DCLK signal from the
system Clock, you must have precise control of any interrupts that can
influence the internal counting of the FLEX 8000 devices. This precise
control is required because the FLEX 8000 device latches data on the rising
edge of the DCLK signal, and the next eight falling edges of the DCLK signal
serialize the latched data. New data is latched on every eighth rising edge
of the DCLK signal until the FLEX 8000 device is completely configured.
Figure 8 illustrates PPS configuration of a FLEX 8000 device. In this circuit,
the CPU generates a byte of configuration data and directs the FLEX 8000

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I Application Note 33

Configuring FLEX 8000 Devices I

device to latch and serialize the data by strobing a high pulse on the DCLK
input. In Figure 8, no specific source is shown for the data bus DATA [7 .. 0] ,
which is typically driven by a dedicated data latch. A microcontroller host
usually has byte-wide ports that can be used for this data bus. If the host is
a CPU or intelligent logic, a dedicated data register can be implemented
with an octal latch. Depending on the capability of the host and the
memory space implementation in the system, you can use an external
memory instead to drive the data onto the system data bus. This type of
external memory usage requires the memory to hold the data on the bus
while the host executes the commands to direct the FLEX 8000 device to
latch and serialize the data. However, not all processors can accommodate
this type of operation.

Figure B. Passive Parallel Synchronous Device Configuration
FLEX 8000
"1"
"1 "
"0"

CPU

nS/P

vee

MSELO

1.0 kn

MSEL1

vee

1.0 kn
~--~'---~--~nSTATUS
f--------------I~

1/0 Port

nCONFIG

DATA{7.•0]·I+-,"~-

Figure 9 shows the timing for the PPS configuration scheme. The CPU
generates Clock cycles and data; eight DCLK cycles are required to latch and
serialize each 8-bit data word. A new data word must be present at the
DATA [7 •. 0] inputs upon every eighth DCLK cycle.

Figure 9. Passive Parallel Synchronous Configuration Timing Waveforms
:-tCF2CK-:

nCONFIG

--1.

.
i

nSTATUS

/CLK.:

itCH!

Ninth DCLK edge latches
next byte of data ~

DCLK

tDH

DATA[7 .. 0]

-i :+-

tDSU - :

I Altera Corporation

!+-fcL

-----------7~i~:k~------------------~\:+-

Page 395

I Configuring FLEX 8000 Devices

Application Note 33

Table 5 shows the timing parameters associated with PPS configuration.

Table 5. Passive Parallel Synchronous Configuration Timing Parameters
Parameter

Symbol

Min

Max

Unit

tCF2CK

nCONFIG high to first rising edge on DCLK

Ils

tosu

Data setup time before rising edge on DCLK

tOH

Data hold time after rising edge on DCLK

tCH

DCLK clock high time

tCL

DCLK clock low time

tCLK

DCLK period

f MAX

DCLK maximum frequency

160

ns
6

MHz

Passive Parallel Asynchronous Configuration
With the passive parallel asynchronous (PPA) configuration scheme, a
FLEX 8000 device in a system can be configured in parallel with the rest of
a board. The FLEX 8000 device accepts a parallel byte of input data, then
serializes the data with its internal synchronization Clock. The device is
selected with the nCS and CS chip select pins, so multiple devices can
reside on the same data bus. The ability to select individual FLEX 8000
devices allows multiple devices to be configured in parallel by a single
intelligent host.
This efficient handshaking allows an intelligent host to simultaneously
configure multiple FLEX 8000 devices or other configurable portions of the
system. Figure 10 illustrates PPA configuration of a FLEX 8000 device. A

Figure 10. Passive Parallel Asynchronous Device Configuration with
Dedicated Ports
FLEX 8000
Microcontroller

1.0 kQ

1/0 Port

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Altera Corporation

I Application

Configuring FLEX 8000 Devices I

Note 33

micro controller is used as the intelligent host to ensure that sufficient
dedicated 1/ 0 ports are available to drive all control signals and the data
bus to the FLEX 8000 device. The chip select signals cs and nCS are both
used to select the device. However, you can also tie nCS to GND and
control chip selection with the CS pin only (or vice-versa), thus saving one
bit in the 1/ 0 port.
Figure 11 shows the timing for the PPA configuration scheme. The CPU
presents an 8-bit data word to the FLEX 8000 device, and indicates that the
word is valid by strobing a low pulse on the nWS input. The FLEX 8000
device senses the rising edge of the nWS signal, latches the data on the
DATA [7 .. 0] inputs, and uses its internal oscillator to serialize the 8-bit
data word.

Figure 11. Passive Parallel Asynchronous Timing Waveforms
nCONFIG

nSTATUS

DATA[7 .. 0]

~~--~:~bY~te~"~o"J: '--"-----.J
i- tDSU -! !
i-f-tcssu

:-tCF2WS ----..j

nCS

:-t

~-r----------~r------------~

nWS

RDYnBSY

The CPU must poll the RDYnBUSY signal to establish when the FLEX 8000
device is ready to receive more data. RDYnBUSY falls immediately after the
rising edge of the DCLK signal that latches data, indicating that the device is
busy. While the FLEX 8000 device processes the data byte, RDYnBUSY
remains low. On the eighth falling edge of DCLK, RDYnBUSY returns to Vco
indicating that another byte of data can be latched. Table 6 shows the
timing parameters associated with PPA configuration.
As an alternative to polling the RDYnBUSY signal, the CPU can determine
the status of the FLEX 8000 device by strobing a low pulse on the nRS input
to the FLEX 8000 device. This strobe causes the FLEX 8000 device to
present the RDYnBUSY status on the bidirectional pin DATA7 so that the CPU
1

Altera Corporation

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I Configuring FLEX 8000 Devices

Application Note 33

Table 6. Passive Parallel Asynchronous Configuration Timing Parameters
Symbol

Parameter

Min

Max

Unit

tCF2WS

nCONFIG high to first nWS rising edge

tosu

5
50

Ils

Data setup time before rising edge on nWS

tOH

Data hold time after rising edge on nWS

tcssu

Chip selected delay before rising edge on nWS
nWS low pulse width

50
500

twsp
t WS2B

nWS rising edge to RDYnBSY low

t BUSY

RDYnBSY low pulse width

tRDY2WS

RDYnBSY rising edge to nWS falling edge

tWS2RS

nWS rising edge to nRS falling edge

tRS2WS

nRS rising edge to nWS falling edge

t RS07

nRS falling edge to DATA 7 valid with RDYnBSY

Ils

50
500
500

ns
ns
ns

signal

can determine device status from the data bus, instead of using an additional
port on the CPU for the RDYnBUSY signal. This low pulse on nRS must occur
only during the corresponding high pulse (inactive) on the nWS signal. The
timing waveforms in Figure 12 show how the nRS pin can be used to poll
the status of the device with the bidirectional pin DATA7 of the circuit
shown in Figure 10. The timing parameters given in Table 6 also apply to
Figure 12.

Figure 12. Passive Parallel Asynchronous Timing Waveforms Using nRS &
DATA7
nCONFIG

nSTATUS

:--- tosu ---l

DATA[6 .. 0]

----~~C:===:~--~====r-:-tcssu-.i
_ _ _ _ _--'1

nCS
: tOH

nWS

i twsp :

U-'
7:

~tRS2WS
~Ii---------

l-tRS07

nRS

tWS2RS - :

~i4}-:-'- - ' ; - - - - '

, !

DATA?

I Page 398

--------------~iij
\

i- tBUSY - '

--'-\-1.--_-_-_-_-_-_-..-->\------'1

i-I

Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices I

The circuit in Figure 10 takes advantage of the architecture of a microcontroller host. Figure 13 shows an alternative to this circuit, in which a
CPU serves as the intelligent host and the FLEX 8000 device is treated more
as a memory than as a port. The nWS and nRS inputs to the FLEX 8000
device are driven by the CPU's memory read/write control pins; the
DATA [7 .• OJ inputs to the FLEX 8000 device are driven directly by the
system data bus. As in Figure 10, the nSTATUS and nCONFIG control signals
must be driven by an intelligent I/O port, but the cs and nCS chip select
signals are decoded from the address bus and not driven from an 1/a port
on the CPU. This address decoding scheme allows the CPU to write to the
FLEX 8000 device as a memory. A small programmable logic device, such
as the Altera EPM7032, is ideal for quickly decoding a wide address and
selecting the FLEX 8000 device.

Figure 13. Passive Parallel Asynchronous Device
Configuration with Address Decoding
FLEX 8000
vee

1.0 kQ

CPU

vee

1/0 Port

nWS~--------------4-~
nRSr---------------~~

ADDRESS

I--""--~

DATA~~~----------~----------------~

PPA configuration is useful when multiple FLEX 8000 devices are
configured simultaneously. The CPU reads a byte of configuration data
from the disk or from memory, and then writes it to the FLEX 8000 device.
The CPU then polls the RDYnBUSY signal (or the DATA7 pin via the nRS
input) to determine when another data byte can be written. Timing for this
circuit is identical to the timing shown in Figure 12, although tcssu, the
minimum chip select delay before the rising edge of nWS, must increase to
account for the time required to decode the address.
The configuration process is generally controlled with a precise order of
steps, so the timing constraints are minimal. The following steps show the
typical control sequence executed by the CPU:

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I Configuring FLEX 8000 Devices
1.
2.
3.
4.

5.
6.

Application Note 33

Pull the nCONFIG pin to GND, hold it for 10 ~s, then pull it up to Vcc.
Read the next byte of configuration data from an EPROM or a mass
storage device such as a hard disk.
Generate the address of the FLEX 8000 device.
Perform a memory write cycle to the FLEX 8000 device address using
the stored configuration data byte.
Poll the RDYnBUSY signal. When it goes high, transfer the next byte of
configuration data by repeating steps 2 through 4.
Repeat steps 2 through 5 until the FLEX 8000 device pulls the
CONF_DONE net high, which indicates that configuration is complete.

Passive Serial Configuration
The passive serial (PS) configuration scheme uses an external controller to
configure the FLEX 8000 device with a serial bit-stream. The FLEX 8000
device is treated as a slave device with a 5-wire interface to the external
controller. The external controller can be one of the following:

The MAX+PLUS II Programmer, used together with the PL-MPU
Master Programming Unit, an appropriate device adapter, and the
FLEX Download Cable.

An intelligent host such as a microcontroller or a CPU. This type of PS
configuration is similar to the PPA and PPS configuration schemes,
but uses a bit-wide serial data path instead of a byte-wide parallel data
path.

Passive Serial Configuration with the FLEX Download Cable
Passive serial (PS) configuration uses the MAX+PLUS II Programmer and
Altera programming hardware as the external controller. The Altera FLEX
Download Cable can connect any Configuration EPROM programming
adapter, which is installed on the PL-MPU Master Programming Unit, to a
single target FLEX 8000 device in the prototype system. The FLEX Download
Cable provides a 5-wire connection between the FLEX 8000 device and the .
programming adapter. Configuration data is taken from the SRAM Object
File (.sof) generated automatically during project compilation and
downloaded by the MAX+PLUS II Programmer. Once the device is
configured, the programming hardware is tri-stated and electrically
removed from the circuit. This type of PS configuration allows you to
perform multiple design iterations rapidly.
Figure 14 shows how the FLEX Download Cable interfaces to the target
FLEX 8000 device. The 10-pin male header on the circuit board has two
rows of five pins, spaced on O.l-inch centers, that connect to the
configuration pins on the FLEX 8000 device. Standard 10-pin IDS-type
male headers are readily available to provide the target board connections.

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Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices I

Figure 14. Passive Serial Device Configuration with the FLEX Download Cable
FLEX 8000
"0"
"0"
"1"

vee
1.0 kn

vee

nS/P
MSELO
MSEL1

1.0 kn

Isolation
Resistor
(Optional)

vee

1.0 kn

......---+---._--1
.-----1~

r-----.J\)'V\r--....

nSTATUS
nCONFIG

DATAO 14----+___.

(Optional)

vee
1.0kn

DCLKi4---t-+-...

'-------'-----'

to User
Circuit

Pin 1

to-Pin Male
Header

vee

Shield

GND

A 10-pin female plug on one end of the FLEX Download Cable is connected
to the 10-pin male header on the circuit board; the other end of the FLEX
Download Cable is connected to a Configuration EPROM programming
adapter. See Figure 15. Timing for PS configuration is identical to the
timing for bit-wide PS configuration shown later in this application note.

Figure 15. FLEX Download Cable Signals & Positions

Receptacle
for Pin t

Header Pin Connections:

I Altera Corporation

DeLK

GND

N.C.

Page 401

I Configuring FLEX 8000 Devices

Application Note 33 I

When a FLEX 8000 device is configured via the FLEX Download Cable, the
DCLK, eONF_DONE, neONFIG, DATAO, and nSTATUS pins on the cable are
connected directly to the pins of the same names on the FLEX 8000 device.
The vee and GND pins must be tied to the system power planes. These vee
and GND pins supply power to the optical isolation circuitry in the
programming adapter; they do not supply power to the target FLEX 8000
device. Refer to the FLEX 8000 Programmable Logic Device Family Data Sheet
in this data book for device pin numbers.
The DCLK, eONF_DONE, neONFIG, and nSTATUS pins on the FLEX 8000
device are dedicated configuration pins. Since they are not available as
user I/O pins, they do not require isolation from the rest of the circuit.
However, a system must include pull-up resistors that pull these pins up
to Vee, as shown in Figure 14. These resistors allow you to remove the
FLEX Download Cable after configuration is complete without introducing
any noise from floating inputs.
The DATAO pin is available as an I/O pin during user-mode operation, and
may require isolation, depending on how it is used. During configuration,
the DATAO pin on the FLEX 8000 device acts as an input, and is driven by
the programming hardware. If the DATAO pin is an output pin during user
mode, the signal that it drives does not need to be buffered. However, if the
DATAO pin is an input or bidirectional pin during user mode, contention
may occur between the user-mode signal and the FLEX Download Cable
during configuration.
If the signal that drives the DATAO pin during user mode is tri-stated
during configuration and initialization, no conflict occurs. However, if this
signal is active during configuration, the DATAO input pin must be isolated
from the active source. You can isolate the DATAO pin by inserting a tri-state
buffer between the DATAO pin and the rest of the network that it drives.
This tri-state buffer must be controlled by external logic.
If you cannot use active isolation, placing a 550-0 resistor between the
user-mode signal and the DATAO pin should provide adequate isolation.
The FLEX Download Cable is driven by 12-mA drivers, which supply
sufficient current to mask any signals that may be present at the other end
of the resistor. Resistive isolation may not be suitable for very-high-speed
circuits. Actual in-circuit performance should be evaluated in the laboratory
to ensure that this isolation scheme does not affect other portions of the
circuit.

The No Connect (N.C.) pins shown in Figure 15 are reserved, and should
not be tied to any data or power signals. The header should be placed as
close as possible to the FLEX 8000 device.
For additional information on passive serial configuration with the FLEX
Download Cable, refer to "Configuring a FLEX 8000 Device In-System

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Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

with MAX +PLUS II & the FLEX Download Cable" later in this application
note.
Bit-Wide Passive Serial Configuration
The passive serial (PS) configuration scheme provides a bit-wide passive
interface for device configuration. No handshaking is provided in any PS
configuration. Therefore, the FLEX 8000 device must be configured at 2
MHz or less. Figure 16 shows how a bit-wide PS configuration is
implemented. Data bits are presented on the DATAO input, with the least
significant bit of each byte of data presented first. The DCLK is strobed with
a high pulse to latch the data. This serial data loading continues until the
CONF_DONE pin goes high, indicating that the device is fully configured.
The data source can be any source that the host can address.

Figure 16. Bit-Wide Passive Serial Device Configuration
FLEX 8000
"0"
"0"
"1 "

Host

1.0 ill

vee

I/O Port

Figure 17 shows the timing for bit-wide PS configuration.

Figure 17. Bit -Wide
Passive Serial Timing
Waveforms

nCONFIG

:.r .!

tCF2CK!:.

CFG

nSTATUS

-:
:-fSTATUS
:-tCF2ST
:

tCLK

:"-tCF2CD

DCLK

DATA

I Altera Corporation

Page 403

I Configuring FLEX 8000 Devices

Application Note 33

Table 7 gives the timing parameters for bit-wide PS configuration.

Table 7. Passive Serial Configuration Timing Parameters
Symbol

In-Circuit
Reconfiguration

Parameter

Min

Max

Unit

tCF2CO

nCONFIG low to CONF _DONE low

Ils

tCF2ST

nCONFIG low to nSTATUS low

t CFG

nCONFIG low pulse width

Ils
Ils

tSTATUS

nSTATUS low pulse width

tCF2CK

nCONFIG high to first rising edge on DCLK

tosu

Data setup time before rising edge on DCLK

tOH

Data hold time after rising edge on DCLK

tCH

DCLK high time

tCL

DCLK low time

tCLK

DCLK period

2
2.S
S
SO
0
2S0
2S0
SOO

Ils
Ils
ns
ns
ns
ns
ns

After a FLEX device has entered the user mode, you can choose to replace
the configuration data pattern inside a FLEX 8000 device at any time. In
this process, called in-circuit reconfiguration, new configuration data is
selected using one of three methods, depending on the configuration
scheme:

In a passive configuration scheme, a different file can be downloaded
from a mass-storage system.

In the AS configuration scheme, multiple sets of configuration data
can be stored in one or more serial Configuration EPROMs. Each set of
data is used in succession.

In the APU and APD configuration schemes, new configuration data
is selected by externally multiplexing a different EPROM source onto
the data path or by providing offset address generation circuitry to
select a different page within the same EPROM.

Because the SRAM cells used to configure the functionality of the FLEX
architecture are volatile, they can be reprogrammed without removing the
FLEX 8000 device from the circuit board.
The nCONFIG input controls device reconfiguration. In the active configuration schemes shown in Figures 1 and 3, the nCONFIG pin is tied to
Vcc to force the FLEX 8000 device to automatically configure itself at
system power-up. In the PPA and PPS configuration schemes, controlling
logic is used on the nCONFIG input to determine when the configuration
starts, as shown in Figures 8, 10, and 13. However, all configuration

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Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices I

schemes allow you to connect the nCONFIG pin to a port on an intelligent
host, which can be used to control the configuration process. If nCONFIG is
held low, the configuration process can be delayed as necessary. For
example, the nCONFIG pin can be held low during system initialization and
then pulled high when it is appropriate to configure the FLEX 8000 device.
At any time during system operation, regardless of the current state of the
FLEX 8000 device, the nCONFIG pin can be used to restart the configuration
process. When nCONFIG is driven low and then high again, the device
resets itself and prepares for configuration. In an active configuration
scheme, the FLEX 8000 device immediately starts retrieving data from the
external EPROM; in a passive configuration scheme, it prepares to receive
the data from the intelligent host. An example of a reset pulse on nCONFIG
in an APU configuration scheme is shown in Figure 5 earlier in this
application note. This nCONFIG timing applies to all configuration schemes
whenever the device is reconfigured.
All latched and registered data in the device is lost during reconfiguration,
so any counter values or the current state of the device should be stored
either in the intelligent host's storage system or in some external circuitry,
such as an Altera EPLD. The entire reconfiguration process requires about
100 ms. The system resumes normal operation after the FLEX 8000 device
releases the CONF_DONE pin, indicating that initialization is complete.

Configuration
Control
Features

Within a FLEX 8000 device, the configuration and initialization processes
can be controlled with two types of built-in resources:

Device configuration option bits
Device configuration pins

This section provides detailed information on configuration option bits
and pins. The usage of various options and pins is discussed in the
descriptions of individual configuration schemes earlier in this application
note. Some configuration pins and options can also be used together to
provide additional configuration and initialization control.

Device Configuration Option Bits
FLEX 8000 devices have device configuration option bits that allow you to
control device behavior during configuration. Table 8 describes all
FLEX 8000 device option bits and their availability in different configuration
schemes. You can set these options on a device-by-device basis during
design entry in the MAX+PLUS II Graphic, Text, or Waveform Editor with
the FLEX 8000 Individual Device Options dialog box, which is accessible
from the Chip to Device dialog box on the Assign menu. (In MAX+PLUS II
for workstations, the Chip to Device dialog box is available on the
Compiler's Device menu. ) You can also enter default device option settings

I Altera Corporation

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Configuring FLEX 8000 Devices

Application Note 33

for an entire project in the MAX+PLUS II Compiler with the FLEX 8000
Device Options dialog box, which is accessible from the Device Options
dialog box (Device menu).

Table B. FLEX BODO Device Configuration Option Bits (Part 1 of 2)
Device
Option
UserSupplied
Start-Up
Clock

Configuration
Scheme
All

Auto-Restart AS,APU,APD
Con fig u ration
on Frame
Error

Option Usage

All

Enable
AS, APU, APD,
DCLK Output PPA
In User
Mode

Page 406

Modified Configuration
(Option On)

After a FLEX 8000 device is
configured, it must be initialized
over the course of 10 Clock
cycles. The user can choose the
source of the Clock.

In the AS, APU, APD, and PPA
configuration schemes, the
internal FLEX 8000 device
oscillator supplies the initialization Clock.

If a data error occurs when a
FLEX 8000 device is configured
with an active configuration
scheme, the user can choose how
to restart the configuration.

The configuration process halts
and the user must externally
direct the device to restart the
configuration process. If a
configuration error occurs, the
nSTATUS pin is driven and held
low until the nCONFIG pin is
externally pulled low and then
high again.

Directs the device to automatically restart the configuration
process. The nSTATUS pin is
driven and held low for 10 Clock
cycles and is then released. The
nSTATUS pin subsequently pulls
up to Vee, indicating to any
external circuitry that the reconfiguration process has started.

In an AS configuration scheme,
the external nCONFIG reset
pulse resets the Configuration
EPROM if the nCONFIG pin on
the FLEX 8000 device is tied to
the Output Enable pin on the
Configuration EPROM.

In an AS configuration scheme,
the nSTATUS reset pulse automatically resets the Configuration EPROM if the nSTATUS
pin on the FLEX 8000 device is
tied to the Output Enable pin on
the Configuration EPROM.

Directs the device to release the
Output Enable override on the
tri-state buffer before releasing
the Clear signal on registered
logic cells and peripheral registers during initialization.

Directs the device to release the
Clear sigllal on registered logic
cells and peripheral registers
before releasing the Output
Enable .override on the tri-state
buffer during initialization.

Release
Clears
Before TriStates

Default Configuration
(Option Off)

During configuration, the 1/0 pins
on the device are tri-stated by an
Output Enable override. The user
can choose the order in which the
tri-states are released and the
registered logic cells and
peripheral registers are cleared
during initialization.
FLEX 8000 devices drive the

The user provides the Clock on
the CLKUSR pin. This type of
Clock can be used to fully
synchronize initialization for
multiple FLEX 8000 devices.
The maximum user-supplied
In the PS and PPS configuration Clock frequency is 6 MHz, and
schemes, the internal oscillator the Clock should have a 50%
is disabled, so external circuitry duty cycle.
must provide the initialization
Clock on the DCLK pin.

Disables the DCLK pin when the
device operates in user mode
in all active configuration schemes after device configuration and
and the PPA configuration
initialization have been
completed.
scheme. The DCLK signal can
range from 2 to 6 MHz in
frequency. The user can choose
whether to enable the DCLK signal
during user mode. The duty cycle
and frequency of the DCLK signal
are not guaranteed.
DCLK signal during configuration

Enables the DCLK pin when the
device operates in user mode
after device configuration and
initialization have been
completed.

Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

Table B. FLEX BODO Oevice Configuration Option Bits (Part 2 of 2)
Device
Option
Disable
Start-Up
Time-Out

Configuration
Scheme
All

Option Usage

Default Configuration
(Option Off)

The CONF_DONE pin, a bidirectional open-drain pin, is held at
GND by the FLEX 8000 device
during configuration. Once
configuration is complete, the
CONF_DONE pin is released and
the FLEX 8000 device treats the
pin as an input pin. In most appl~
cations, the CONF_DONE pin is
pulled up to Vee via a 1.0-kn
resistor. This low-to-high transition
directs the FLEX 8000 device to
begin initialization. The user can
enable or disable the time-out
error checking that determines
whether CONF_DONE goes high
within 10 Clock cycles.

If the CONF _DONE pin does not
go high within 10 Clock cycles
after being released by the
device, the device drives the
nSTATUS pin low at the end of
the configuration cycle,
indicating an error condition.

Modified Configuration
(Option On)
If the CONF_DONE pin does not
go high within 10 Clock cycles
after being released by the
device, the device continues to
wait for CONF _DONE to go high.
To delay initialization, the
CONF_DONE node can be held
low externally after the
FLEX 8000 device has released
the CONF _DONE pin, if, for
example, the user wishes to
control the time required for the
FLEX 8000 device to enter user
mode.

Device Configuration Pins
FLEX 8000 devices include control pins that modify the sequence and
timing of the configuration and initialization processes, and provide a
variety of configuration options. Some configuration pins have the same
effect regardless of the selected configuration scheme; others are specific to
a particular configuration scheme. Table 9 summarizes the functionality of
each configuration pin.

Table 9. Pin Functions (Part 1 of 2)
Pin
Name

User Configuration
Mode
Scheme

Note (1)

Pin
Type

nSP

n/a

All

Input

MSELl

n/a

All

Input

Description
Serial/Parallel selection input. A low input selects a serial configuration
scheme; a high input selects a parallel configuration scheme.
2-bit configuration scheme selection inputs that are used in conjunction with
nSP to select the configuration scheme. The bit patterns of nSP: MSEL1: MSELO

MSELO

are associated with the following configuration schemes:
000 =
00 1 =
010 =
011 =
nSTATUS

n/a

I Altera Corporation

All

Bidirectional
Open Drain

AS
Reserved
PS
Reserved

100 =
101 =
110 =
111 =

APU
PPS
APD
PPA

Command mode status output. The FLEX 8000 device drives the nSTATUS pin
low immediately after power-up, then releases it within 100 ms. The nSTATUS
pin must be pulled up to Vee with a 1.0-kn resistor. If an error occurs during
configuration, nSTATUS is pulled low again by the FLEX 8000 device.

Page 407

Configuring FLEX 8000 Devices

Application Note 33

Table 9. Pin Functions (Part 2 of 2)
Pin
Name

User Configuration
Scheme
Mode

Pin
Type

Description

nCONFIG

nla

All

Input

Configuration control input. A low input resets the FLEX 8000 device. A low-tohigh transition starts a configuration cycle.

nWS

1/0

PPA

Input

Write Strobe input. A low-to-high transition causes the FLEX 8000 device to
latch a byte of data on the DATA [7 .. 0 1 pins.

nRS

1/0

PPA

Input

Read Strobe input. A low input directs the FLEX 8000 device to place the
RDYnBUSY signal on the DATA7 pin.

RDCLK

1/0

APD,APU

Output

Divide-by-8 of DCLK output. Used internally to serialize an 8-bit data stream in
the byte-wide APU or APD configuration scheme.

DCLK

(2)
(3)

AS
PPS,PS

Output
Input

Clock source for external PROM devices.
Clock input from external host.

nCS
cs

1/0

PPA

Input

Chip Select inputs. A low input on nCS and a high input on cs selects a specific
FLEX 8000 device for configuration. If only one of the chip selects is used, the
other must be tied to its active level (e.g., nCS would be tied to GND).

RDYnBUSY

1/0

PPA

Output

Ready output. A high output indicates that the FLEX 8000 device is ready to
accept another byte of data. A low output indicates that the device is not ready
to receive data.

CLKUSR

1/0

All

Input

Optional user-supplied Clock input. Synchronizes the initialization process.

CONF_DONE

nla

All

Bidirectional
Open Drain

Status output. Driven low by the FLEX 8000 device during the configuration
process.

Input

Status input. A high input directs the device to execute the initialization process
and enter user mode.
The CONF_DONE net must be pulled up to Vee with a 1.0-kn resistor.
The CONF_DONE pin may be actively driven low by an external source to delay
the FLEX 8000 device initialization process. This feature is useful when the
configuration process will be completed some time before actual operation is
necessary.

ADD17 to
ADDO

1/0

APD,APU

Outputs

Address outputs. Driven by the FLEX 8000 device to uniquely address up to
256 Kbytes of external configuration memory devices.

DATA7to
DATAO

1/0

APD, APU,
PPA,PPS

Inputs

Data inputs. Byte-wide configuration data is presented to the FLEX 8000 device
on all 8 data pins.

DATAO

AS,PS

Input

Data input. Bit-wide configuration data is presented to the FLEX 8000 device
on the DATAO pin.

DATA7

PPA

Output

In the PPA configuration scheme, the DATA7 pin presents the RDYnBSY signal
after the device receives an nRS strobe. Using the DATA7 pin may be more
convenient than using the RDYnBSY output pin.

Notes:
(1)

(2)

(3)

The maximum number of dual-purpose configuration pins that can be used as I/O pins in user mode varies in
different configuration schemes:
AS:
3 pins
APU: 29 pins
APD: 29 pins
PS:
2 pins
PPS:
9 pins
PPA: 15 pins
The internally-generated DCLK signal used to configure FLEX 8000 devices with the AS, APU, APD, and PPA
configuration schemes is available during user-mode operation if the Enable DCLK Output in User Mode configuration
option bit is turned on. The DCLK signal can range from 2 to 6 MHz in frequency; the duty cycle and frequency are
not guaranteed.
An externally-generated DCLK signal is used to configure FLEX 8000 devices with the PS and PPS configuration
schemes. After configuration has finished, the external host can continue to drive the DCLK signal during user-mode
operation.

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Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

Seven of the device pins are dedicated to the configuration process and
cannot be used as I/O pins in user mode. Other configuration pins are
dual-purpose pins that also can be used as I/O pins when the device
operates in user mode. You can choose whether to use each dual-purpose
pin as an 1/ 0 pin in user mode, and whether to force a dual-purpose pin to
tri-state (Le., drive a high-impedance logic level).
You can specify these settings for each pin on a device-by-device basis
during design entry in the MAX+PLUS II Graphic, Text, or Waveform
Editor with the FLEX 8000 Individual Device Options dialog box that is
accessible via the Chip to Device dialog box on the Assign menu. (In
MAX+PLUS II for workstations, the Chip to Device dialog box is available
on the Compiler's Device menu.) You can also enter default pin settings for
an entire project in the MAX+PLUS II Compiler with the FLEX 8000
Device Options dialog box that is accessible via the Device Options
dialog box (Device menu). Turning on the Reserve option for a specified pin
in either dialog box prevents the pin from being used as an I/O pin during
user mode; turning on the Tri-State option forces the pin to tri-state. A
reserved pin should not be connected to any circuitry on the target board
unless it is also tri-stated. Otherwise, the reserved pin will drive an unknown
logic level that may cause logic contention with other signals on the board.
The nSTATUS, nCONFIG, CONF_DONE, and CLKUSR device configuration pins
are available to monitor the configuration process and control how the
device loads data, initializes, and enters user-mode operation. These pins
can be used together with configuration option bits to provide additional
configuration and initialization control.
nSTATUSPin
The nSTATUS pin is an open-drain bidirectional pin. When the FLEX 8000
device powers up, it pulls this pin low and then releases it within 100 ms.
During configuration, the nSTATUS pin can be polled externally to verify
that the FLEX 8000 device is being configured. If an error occurs during
configuration, the nSTATUS pin is pulled and held low. After the pin is
pulled low, configuration must be restarted.
Configuration is restarted with a high-low-high pulse on the nCONFIG pin.
As an alternative, if the Auto-Restart Configuration on Frame Error option bit
is turned on, the FLEX 8000 device can restart the configuration
automatically when an error is detected. If this option bit is turned on, the
nSTATUS pin is pulled low for a few microseconds and then released,
indicating that the reconfiguration cycle has started. See Figure 3 earlier in
this application note for an example of an AS configuration scheme that
supports auto-reconfiguration.

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Page 409

I Configuring FLEX 8000 Devices

Application Note 33 I

If Vee falls below an acceptable level during user-mode operation, the
nSTATUS pin is pulled and held low, indicating an error condition. See
"Configuration Reliability" later in this application note for more details.

nCONFIG Pin

The nCONFIG pin is a dedicated input that is used to start a configuration
cycle. In most applications, the nCONFIG pin is tied to Vee, directing the
FLEX 8000 device to immediately start configuration in an active
configuration scheme, or to prepare immediately for configuration in a
passive configuration scheme.
When the nCONFIG pin is held at GND, the FLEX 8000 device is reset and
ready to start configuration. Configuration begins only after the pin is
pulled up to Vee. The nCONFIG pin can thus be held low to delay the
configuration process, and prevent data from loading until the desired
time.
If an application requires a FLEX 8000 device to be reconfigured after
system power-up, the nCONFIG pin must be tied to some external intelligent
circuitry that monitors and controls that configuration process, as described
in "In-Circuit Reconfiguration" earlier in this application note.

The CONF_DONE pin is an open-drain bidirectional pin that reflects the
configuration status. When a FLEX 8000 device is ready to begin loading
data, the CONF_DONE pin is pulled to GND and remains at GND while the
data is loading, indicating that the FLEX 8000 device is being configured.
After the last configuration data byte has been read, the CONF_DONE pin is
released and pulled to Vee by an external pull-up resistor, indicating that
configuration is finished. The FLEX 8000 device interprets this low-to-high
transition on the CONF_DONE signal as the command to initialize and enter
the user mode.
If the CONF_DONE pin does not pull up to Vee within ten Clock cycles of the
final configuration data byte, the FLEX 8000 device detects an error
condition, aborts the initialization process, and drives and holds the nSTATUS
pin low. If the nSTATUS pin is low, it indicates either that an error has
occurred in the application circuit, or that the configuration data-stream is
corrupt.

The CONF_DONE pin can also be used to control the initialization process.
You can disable error checking on the CONF_DONE net by turning on the
device's Disable Start-Up Time-Out configuration option bit, so that the
failure of CONF_DONE to pull to Vee does not cause an error condition. The
CONF_DONE network can then be driven by some external logic, and held
low until initialization is desired.

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Altera Corporation

Configuring FLEX 8000 Devices I

I Application Note 33
CLKUSRPin

The CLKUSR pin can coordinate the initialization of multiple FLEX 8000
devices or synchronize the configuration of a FLEX 8000 device with other
application logic in the system. In most applications, the FLEX 8000 device
uses its internal oscillator (available externally as DCLK) to complete the
initialization. After ten Clock cycles, the device enters user mode. You can
turn on the User-Supplied Start-Up Clock configuration option bit and
supply these ten Clock cycles on the CLKUSR pin to ensure that the device
enters the user mode precisely when desired. Since the internal oscillators
on all FLEX 8000 devices are not guaranteed to have the same frequency,
you can use the CLKUSR pin to synchronize multiple FLEX 8000 devices in
the same system.

MAX+PLUS II
Configuration &
Programming
Support

The MAX+PLUS II software can generate four different types of configuration files for FLEX 8000 devices, as shown in Table 10. During project
compilation, MAX+PLUS II automatically generates a POF and an SOF for
each FLEX 8000 device. If necessary, you can generate a TTF or Hex File, as
well as different POF(s), after compilation with the Combine Programming
Files command (File menu) in the MAX+PLUS II Programmer or Compiler.

Table 10. FLEX 8000 Device Programming Files
File Type

Filename
Extension

File
Format

File Utilization

SRAM Object File

.sof

Binary

Downloaded directly into the FLEX 8000 device with the
MAX+PLUS II Programmer using the FLEX 8000 Download
Cable and Altera programming hardware.

Programmer
Object File

.pof

Binary

Programmed into an Altera Configuration EPROM. The POF
contains the configuration data, as well as the header, CRC, and
pad bytes for configuring the FLEX 8000 device in an AS
configuration scheme.

Hexadecimal (IntelFormat) File

.hex

ASCII text Programmed into an industry-standard parallel EPROM. The
Hex File contains the configuration data, as well as the header,
CRC, and pad bytes for programming a parallel EPROM that
configures a FLEX 8000 device in an APU or APD configuration
scheme.

Tabular Text File

.ttf

ASCII text A comma-separated version of the Hex File, used as source
code in high-level programming languages. The TTF can be
included in the source code for an intelligent host that configures
the FLEX 8000 device in a PPA, PPS, or bit-wide PS configuration scheme. It can also be converted into an equivalent
binary format that is directly loaded (LSB first) into the FLEX
8000 device.

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I Configuring FLEX 8000 Devices

Application Note 33

Together, the MAX+PLUS II Programmer and Altera programming
hardware provide the following capabilities:

o A POF can be programmed into an Ahera serial Configuration EPROM
for an AS configuration scheme.

An SOF can be downloaded via the FLEX Download Cable for incircuit PS configuration of a FLEX 8000 device.

Programming & Configuration Files
This section provides information on the characteristics of each type of
configuration file. The process of creating different configuration files is
described in "Combining & Converting Programming Files" later in this
application note.
SRAM Object File

The SRAM Object File (.sof) is used during passive serial configuration
when the data is downloaded directly into the FLEX 8000 device in-system
with the MAX+PLUS II Programmer, the FLEX Download Cable, and
Altera programming hardware. MAX+PLUS II automatically inserts the
necessary header, formatting, and synchronization bits into the data stream
when it downloads an SOF into a FLEX 8000 device. See "Configuring a
FLEX 8000 Device In-System with MAX+PLUS II & the FLEX Download
Cable" later in this application note for more information.
If configuration files are needed for other configuration schemes,
MAX+PLUS II uses the data in SOF(s) to generate the appropriate POF(s),
a TTF, or a Hex File.

Programmer Object File

The Programmer Object File (.pof) is used to program Altera serial
Configuration EPROMs for an AS configuration scheme. MAX+PLUS II
automatically generates a POF for every FLEX 8000 device in a project. In a
multi-device project, each FLEX 8000 device has a dedicated serial
Configuration EPROM. MAX+PLUS II selects the appropriate
Configuration EPROM to most efficiently store the data for each FLEX 8000
device.
Hexadecimal (Intel-Format) File

The Hexadecimal File (.hex) is an ASCII file in the Intel Hex format. This
file contains the configuration and formatting data for an industry-standard
byte-wide parallel EPROM that is used to configure a FLEX 8000 device in
an APU or APD configuration scheme. The data in the Hex File is interpreted

I Page 412

Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

by the programming software when it is programmed into a parallel
EPROM.
The usual base address for FLEX 8000 configuration data is the origin of
the EPROM. In some applications, the origin of the EPROM is required by
other system resources, so some offset is necessary. In an APU configuration
scheme, the FLEX 8000 device generates ascending addresses starting at
OOOOOH; in an APD configuration scheme, it generates descending addresses
starting at 3FFFFH. The FLEX 8000 device provides these base addresses
for the configuration data during configuration, but any needed offset
address must be generated externally, as shown earlier in Figure 6. The
APU scheme is appropriate if the FLEX 8000 configuration data can be
stored at the beginning of an EPROM or at some known offset in an
EPROM larger than 256 Kbytes. The APD scheme is appropriate if the
FLEX 8000 configuration data is placed in an EPROM in which the low
addresses are not available (as shown in Figure 7), or in an EPROM that
also stores other information that is expected to increase as an application
evolves.
Tabular Text File
The Tabular Text File (.Uf) is a tabular ASCII file that provides a commaseparated version of the configuration data for the PPA, PPS, and bit-wide
PS configuration schemes. In some applications, the storage device that
contains the FLEX 8000 configuration data is neither dedicated to nor
connected directly to the FLEX 8000 device. For example, an EPROM can
also contain executable code for a system (e.g., BIOS routines) and other
data. The TTF allows you to include the FLEX 8000 configuration data as
part of the source code for the intelligent host (using "include" or "source"
commands). The host can access this data from an EPROM or a massstorage device and load it into the FLEX 8000 device.
A TTF can be imported into nearly any Assembly Language or high-level
language compiler. Consult the documentation for your compiler or
assembler for information on including other source files.
If you do not include the TTF in the source code for an intelligent host, the
file's comma-separated ASCII representation of the binary data must be
converted into its equivalent 8-bit binary format (e.g., 85 would become
01010101) before it is loaded into the FLEX 8000 device. Data must be
stored so that .the least significant bit (LSB) of each byte of data is loaded
first. You can convert the ASCII decimal values into a binary image and
store it on a mass storage device. The intelligent host can then read data
from the binary file and load it into the FLEX 8000 device. You can also use
the intelligent host to perform real-time conversion during configuration.
In the PPA and PPS configuration schemes, the FLEX 8000 device receives
its information in parallel from the data bus, a data port on the CPU, or

I Altera Corporation

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I Configuring FLEX 8000 Devices

Application Note 33

some other byte-wide channel. In the bit-wide PS configuration scheme,
the data is shifted in serially.

Programming a Serial Configuration EPROM
You can program Altera Configuration EPROMs with MAX+PLUS II, the
PL-MPU Master Programming Unit, and the appropriate Configuration
EPROM programming adapter. The PLMJl213 adapter programs
Configuration EPROMs in B-pin plastic dual in-line package (PDIP) and
20-pin plastic J-Iead chip carrier (PLCC) packages; the PLMTI064 adapter
programs Configuration EPROMs in 32-pin thin quad flat pack (TQFP)
adapters.
To program an Altera serial Configuration EPROM:
1.
2.

Choose the Programmer command (MAX +PLUS II menu) to open the
Programmer window.
By default, the Programmer loads the POF for the current project. If
necessary, load a different POF with the Select Programming File
command (File menu). The appropriate device for the current
programming file is displayed in the Device field.
Insert a blank Configuration EPROM into the B-pin DIP, 20-pin J-Iead,
or 32-pin QFP socket on the programming adapter. The socket for the
FLEX 8000 device (if any) must be empty.
Choose the Program button.

After successful programming, you can place the Configuration EPROM
on the target board to configure a FLEX BOOO device in the AS configuration
scheme.

Configuring a FLEX 8000 Device In-System with MAX+PLUS II & the
FLEX Download Cable
To configure a FLEX BOOO device with the FLEX Download Cable:
1.
2.
3.
4.
5.

6.
7.

I Page 414

Connect the FLEX Download Cable to the 9-pin D-type connector on a
Configuration EPROM programming adapter.
Connect the other end of the FLEX Download Cable to the 10-pin male
header on the target board.
Start MAX+PLUS II and choose the Programmer command
(MAX+PLUS II menu) to open the Programmer window.
Choose the Select Programming File command (File menu).
Select the desired SOF filename in the Files box or type a name in the
File Name box. If you choose a programming file from another project,
you are asked if you wish to change the current project name.
Choose OK.
Choose the Program button to configure the device.
Altera Corporation

I Application Note 33

Configuring FLEX 8000 Devices

After the device is configured and initialized, it enters user mode and
operates as a logic device. The FLEX Download Cable is electrically removed
from the circuit and does not influence circuit operation. You can also
physically disconnect the FLEX Download Cable without disturbing the
FLEX 8000 configuration data or device operation.

Combining & Converting Programming Files
MAX+PLUS II automatically generates a POF and an SOF for every
FLEX 8000 device in a project, as described earlier in this application note.
The POF can be programmed into an Altera serial Configuration EPROM
used in an AS configuration scheme; by default, each FLEX 8000 device has
one dedicated Configuration EPROM.
You may wish to combine and/or convert the automatically generated
SOFs into a different format for the following purposes:
D

To use a configuration scheme other than AS. You must convert an
SOF into a Hex File or a TTF for programming a parallel EPROM,
BIOS EPROM, or another data source.
To combine multiple sets of configuration data to be used for in-circuit
reconfiguration in any configuration scheme.

To convert an SOF into a Hex File or TTF:
1.

2.
3.

Refer to Table 2 to calculate the required data space in a parallel or
serial data source.
Choose the Combine Programming Files command (File menu) in
the MAX+PLUS II Programmer or Compiler.
Select the desired SOF name in the Files box or type a name in the File
Name box under Input Files. Choose the Add button to add it to the
Selected Files box.
Specify information for the desired configuration scheme:
If the FLEX 8000 device will be configured with a parallel EPROM
in the APU or APD configuration scheme, select .hex (Active
Parallel) in the File Format drop-down list box under Output File.

In addition, if the FLEX 8000 configuration data will not start at
the origin of the EPROM, specify the base address for the
configuration data in the Address box under Input Files. Choose
Up or Down under Count to specify whether the FLEX 8000 device
should count up or down. The counting sequence can be either
ascending (OOOOOH to 3FFFFH) for APU configuration or
descending (3FFFFH to OOOOOH) for APD configuration, as
described in "Hexadecimal (Intel-Format) File" earlier in this
application note.

I Altera Corporation

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I Configuring FLEX 8000 Devices

Application Note 33

or:
If the FLEX 8000 device will be configured with a PPA, PPS, or

bit-wide PS scheme, select .ttj (Passive Parallel) in the File Format
drop-down list box under Output File. The TTF can be incorporated
as source code for a data structure in a high-level programming
language. Otherwise, the TTF data must be converted into its
equivalent 8-bit binary format before it is loaded into the
FLEX 8000 device, as described in "Tabular Text File" earlier in
this application note.
5.

The default name for the output file is the current project name plus
the extension .hex or .uf. To give a different name to the file, type a
name in the File Name box under Output File.
Choose OK to generate the Hex File or TTF. The file is placed in the
current project directory.

You can use in-circuit reconfiguration to load multiple sets of configuration
data into the FLEX 8000 device in a system. The following procedure
describes how to combine SOFs for in-circuit reconfiguration of a FLEX 8000
device.
To combine SOFs for in-circuit reconfiguration with multiple sets of
configuration data:
1.

2.
3.
4.
5.

I Page 416

Refer to Table 2 to calculate the required data space in a parallel or
serial data source.
Choose the Combine Programming Files command (File menu) in
the MAX+PLUS II Programmer or Compiler.
Select the SOF with the first set of configuration data and choose the
Add button to add it to the Selected Files box.
Repeat step 3 until all SOFs have been added to the Selected Files box.
Arrange the selected files in the order in which the different sets of
configuration data will be used by selecting each SOF filename and
choosing the Up or Down button under Order.
Specify information for the desired configuration scheme, select the
output filename, and choose OK. (The default name for the output file
is the current project name plus the extension .hex, .Uf, or .pof. To give
a different name to the file, type a name in thge File Name box under
Output File. If multiple POFs are generated, they are uniquely identified
by a sequence number appended to the filename (e.g., the first is
device.pof, the second is devicel.pof, etc. You can specify an output
filename that has less than the maximum of eight characters to leave
room for the numerical index; otherwise, the last character(s) are
truncated to include it.)

Altera Corporation

I Application Note 33

Configuration
Reliability

Configuring FLEX 8000 Devices

The FLEX architecture has been designed to minimize the effects of power
supply and data noise in a system, and to ensure that the configuration
data is not corrupted during configuration or normal user-mode operation.
A number of circuit design features are provided to ensure the highest
possible level of reliability from this SRAM technology.
Cyclic redundancy check (CRC) circuitry is used to validate every data
frame (i.e., sequence of data bits) as it is loaded into the FLEX 8000 device.
If the CRC generated by the FLEX 8000 device does not match the data
stored in the data stream, the configuration process is halted, and the
nSTATUS pin is pulled and held low to indicate an error condition. This
CRC circuitry ensures that noisy systems will not cause errors that yield an
incorrect or incomplete configuration.
The FLEX architecture also provides a very high level of reliability in lowvoltage brown-out conditions. The SRAM cells require a certain Vcc level
to maintain accurate data. Since this voltage threshold is significantly
lower than that required to activate the power-on reset (POR) circuitry in
the FLEX 8000 device, the FLEX 8000 device stops operating if the Vcc
starts to fail, and indicates an operation error by pulling and holding the
nSTATUS pin low. The device must then be reconfigured before it can
resume operation as a logic device. In active configuration schemes, reconfiguration begins as soon as Vcc returns to an acceptable level if the
nCONFIG pin is tied to Vcc. Otherwise, the host system must start the
reconfiguration process.
These device features ensure that FLEX 8000 devices have the highest
possible reliability in a wide variety of environments, and provide the
same high level of system reliability that exists in other families of Altera
programmable logic devices.

I Altera Corporation

Page 417

Notes:

Understanding
EPLD Timing
August 1993, ver. 2

Introduction

Application Brief 100

Altera EPLDs provide device performance that is consistent from simulation
to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays
either with the MAX+PLUS II Timing Analyzer or with the timing models
given in this application brief and the timing parameters listed in individual
device data sheets. Both methods yield the same results.
This application brief defines device internal delay parameters and AC
timing characteristics, and illustrates the timing models for the Classic,
MAX 5000/EPS464, and MAX 7000 device families. For information on
FLEX 8000 timing, refer to the FLEX 8000 Programmable Logic Device Family
Data Sheet in this data book.
Familiarity with EPLD architecture and characteristics is assumed. Refer
to individual device data sheets in this data book for complete descriptions
of the architectures.

Internal EPLD
Delay
Parameters

Within an EPLD, timing delays contributed by individual architectural
elements are called microparameters. The following list defines
microparameters for Classic, MAX 5000/EPS464, and MAX 7000 EPLDs.
Individual device data sheets for MAX 5000 /EPS464 and MAX 7000 EPLDs
give the values for these parameters; microparameters for Classic EPLDs
are listed in this application brief.
Input pad and buffer delay. In Classic and MAX 5000/EPS464
EPLDs, it is the time required for a dedicated input pin to drive
the true and complement data input signal into the logic array(s).
In MAX 7000 devices, it is the time required for a dedicated input
pin to drive the input signal into the Programmable Interconnect
Array (PIA) or into the global control array.
I/O input pad and buffer delay. This delay applies to I/O pins
used as inputs. In Classic EPLDs, it is the delay added to tIN' In
MAX 5000 /EPS464 EPLDs with a single Logic Array Block (LAB),
it is the delay from the I/O pin to the logic arrays. In MAX 7000
and multi-LAB MAX 5000 EPLDs, it is the delay from the I/O pin
to the PIA.

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I Understanding EPLD Timing

Application Brief 100 I

tpIA

Programmable Interconnect Array delay. The delay incurred by
signals that require routing through the PIA. MAX 7000 and
multi-LAB MAX 5000 EPLDs only.

tEXP

Expander array delay. The delay of a signal through the AND-NOT
structure of the shared expander product-term array that is fed
back into the logic array. MAX 5000/EPS464 EPLDs only.

t SEXP

Shared expander array delay. The delay of a signal through the
structure of the shared expander product-term array
that is fed back into the logic array. MAX 7000 EPLDs only.
AND-NOT

I Page 420

tpEXP

Parallel expander delay. The additional delay incurred by adding
parallel expander product terms to the macrocell product terms.
For each group of up to five parallel expanders added to a single
function, an additional tpEXP delay is added to the timing path.
MAX 7000 EPLDs only.

tICS

Global Clock delay. The delay from the dedicated Clock pin to a
register's Clock input. Classic and MAX 5000 EPLDs only.

tCLOB

Global control delay. The delay from a dedicated input pin to any
global control function in a macro cell or 1/ 0 control block. EPS464
and MAX 7000 EPLDs only.

tLAC

Logic array control delay. The AND array delay for register control
functions such as Preset, Clear, and Output Enable. MAX 5000/
EPS464 and MAX 7000 EPLDs only.

tIC

Array Clock delay. The delay through a macrocell's Clock product
term to the register's Clock input.

tEN

tCLR

Register Clear time. The delay from the time when the register's
asynchronous Clear input is asserted to the time the register
output stabilizes at logical low.

tpRE

Register Preset time. The delay from the time when the register's
asynchronous Preset input is asserted to the time the register
output stabilizes at logical high.

tLAD

Logic array delay. The time a logic signal requires to propagate
through a macrocell's AND-OR-XOR structure.

tRD

Register delay. The delay from the rising edge of the register's
Clock to the time the data appears at the register output.
MAX 5000/EPS464 and MAX 7000 EPLDs only.

Altera Corporation

I Application Brief 100

AC Timing
Characteristics

I Altera Corporation

Understanding EPLD Timing

tsu

Register setup time. The time required for a signal to be stable at
the register input before the Clock's rising edge to ensure that the
register correctly stores the input data.

Register hold time. The time required for a signal to be stable at
the register input after the register Clock's rising edge to ensure
that the register correctly stores the input data.

tCOMB

Combinatorial buffer delay. The delay from the time when a
combinatorial logic signal bypasses the programmable register to
the time it becomes available at the macrocell output. MAX 5000 j
EPS464 and MAX 7000 EPLDs only.

t LATCH

Latch delay. The propagation delay through the programmable
register when it is configured as a flow-through latch. MAX 5000
EPLDs only.

tFD

Feedback delay. In Classic EPLDs, it is the delay of a macrocell
output fed back into the logic array. In single-LAB
MAX 5000 jEPS464 EPLDs, it is the delay of a macrocell output
fed back into the logic array. In multi-LAB MAX 5000 EPLDs, it is
the delay of a macrocell output fed back into the LAB's logic array
or to a PIA input.

tOD

Output buffer and pad delay. The delay from the macro cell
output, through the tri-state output buffer, to the output pin.

txz

Output buffer disable delay. The delay required for high
impedance to appear at the output pin after the output buffer's
Enable control is disabled.

tzx

Output buffer enable delay. The delay required for the macrocell
output to appear at the output pin after the output buffer's
Enable control is enabled.

tLPA

Low-power adder. The delay associated with macrocells in lowpower operation. In low-power mode, tLPA must be added to the
logic array delay (tLAd, register control delay (tLAC' tIC, tACV or
tEN)' and the shared expander delay (tSEXP) paths. MAX 7000
EPLDs only.

AC timing characteristics, called macroparameters, represent actual pinto-pin timing characteristics. Each macroparameter consists of a
combination of internal delay elements (microparameters). The data sheet
for each EPLD gives timing macroparameters that characterize the AC
operating specifications. These are worst-case values, derived from
extensive performance measurements and guaranteed by testing. The
following list defines macroparameters for Classic, MAX 5000 jEPS464,
and MAX 7000 EPLDs.

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I Understanding EPLD Timing

EPLD Timing
Models
I Page 422

Application Brief 100

tpDl

Dedicated input pin to non-registered output delay. The time
required for a signal on any dedicated input pin to propagate
through the combinatorial logic in a macrocell and appear at an
external EPLD output pin.

tpD2

I/O pin input to non-registered output delay. The time required
for a signal on any I/O pin input to propagate through the
combinatorial logic in a macrocell and appear at an external
EPLD output pin.

tpzx

Tri-state to active output delay. The time required for an input
transition to change an external output from a tri-state (highimpedance) logic level to a valid high or low logic level.

tpxz

Active output to tri-state delay. The time required for an input
transition to change an external output from a valid high or low
logic level to a tri-state (high-impedance) logic level.

tCLR

Time to clear register delay. The time required for a low signal to
appear at the external output, measured from the input transition.

tsu

Global Clock setup time. The time data must be present at the
input pin before the global (synchronous) Clock signal is asserted
at the Clock pin.

Global Clock hold time. The time the data must be present at the
input pin after the global Clock signal is asserted at the Clock pin.

t COl

Global Clock to output delay. The time required to obtain a valid
output after the global Clock is asserted at the Clock pin.

tCNT

Minimum global Clock period. The minimum period maintained
by a globally Clocked counter.

t ASU

Array Clock setup time. The time data must be present at the
input pin before an array (asynchronous) Clock signal is asserted
at an input pin.

tAH

Array Clock hold time. The time data must be present at the input
pin after an array Clock signal is asserted at an input pin.

t ACOl

Array Clock to output delay. The time required to obtain a valid
output after an array Clock signal is asserted at an input pin.

t ACNT

Minimum array Clock period. The minimum period maintained
by a counter when it is clocked by a signal from the array.

Timing models are simplified block diagrams that illustrate propagation
delays through Altera EPLDs. Logic can be implemented in different
paths. You can trace the actual paths used in your Altera device design by
examining the equations listed in the MAX+PLUS II Report File (.rpt) for
Altera Corporation

I Application Brief 100

Understanding EPLD Timing

the project. You then add up the appropriate microparameters to calculate
the propagation delays through the EPLD.

Classic EPLDs
The Classic architecture provides registered and combinatorial capabilities.
Registers can be clocked from a global Clock or through an array (productterm) Clock, and can be asynchronously cleared. When the global Clock is
used, the Output Enable can be controlled by a product term. Figure 1
shows the timing model for Classic devices.

Figure 1. Classic EPLO Timing Model
If the register is bypassed, the delay between the logic array and the output buffer is zero.

Input

I----I~I

~Delay

Output
Delay

tsu

1----....1

too

tIN

txz

tzx

IQI-+

Feedback
Delay

I/O
Delay

tFD

tlO

Tables 1 through 6 show the internal delay parameters for all Classic
EPLDs.

Table 1. EP330 Timing Parameters (in ns)
EP330-12

EP330-15

tIN

tlO

tLAO

too

tzx

Parameter

I Altera Corporation

txz

tsu

tIC

n/a

tICS

t FO

tCLR

n/a

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I Understanding EPLD Timing

Application Brief 100 I

Table 2. EP610 Timing Parameters (in ns)
EP61O-15

EP61O-2o

EP61 0-25

EP61 0-30

EP61 0-35

t,N

t,O

tLAD

too

tzx

9
9
12

Parameter

txz

tsu

t,C

t,CS

tFD

tCLR

Table 3. EP610A Timing Parameters (in ns)
Parameter

I Page 424

EP61oA-7

EP61oA-1o

EP61OA-12

EP61OA-15

tIN

t ,O

tLAD

3.5

too

tzx

txz

tsu

3.5

2.5

t,C

t,CS

tFD

tCLR

3.5

Altera Corporation

I Application

Understanding EPLD Timing I

Brief 100

Table 4. EP910 Timing Parameters (in ns)
EP91 0-30

EP91o-35

EP91 0-40

tiN

tlO

tLAO

too

tzx

txz

tsu

tiC

tiCS

tFO

tCLR

EP91oA-1o

EP91oA-12

EP91oA-15

tIN

Parameter

Table 5. EP910A Timing Parameters (in ns)

Parameter

I Altera Corporation

tlO

tLAO

too

tzx

txz

tsu

tiC

tiCS

tFO

tCLR

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I Understanding EPLD Timing

Application Brief 100 I

Table 6. EP1810 Timing Parameters (in ns)
Parameter

EP1810-20

EP1810-25

EP1810-35

EP1810-45

tLAD

5
2
9

3
12

too

tzx

txz

tsu

8
5
9
4
3
9

5
19
9
9
9
10
15
19
4

5
28
11
11
11
10
18
28
8

tiN
tlO

tH
tiC
tiCS
tFD
tCLR

12
5
3
12

MAX 5000/EPS464 EPLDs
The MAX 5000 architecture supports many functions. The macrocell array
provides registered, combinatorial, or flow-through latch operation. The
registers can be clocked from a global Clock or through product-term array
Clocks, and can be asynchronously preset and cleared. Separate product
terms control the Output Enable and logic inversion. The array of shared
expander product terms provides additional product terms to implement
complex logic.
The EPS464 is an advanced general-purpose EPLD based on the
MAX 5000 architecture. It has 64 enhanced macrocells and 256 shared
expanders, all of which are routed globally to implement complex projects.
MAX 5000 EPLDs are divided into two categories: single- and multi-LAB
EPLDs. Figure 2 shows the timing model for the single-LAB EPM5016 and
EPM5032 EPLDs.

I Page 426

Altera Corporation

I Application Brief 100

Understanding EPLD Timing

Figure 2. Single-LAB MAX 5000 EPLD Timing Model

~ Input
Delay

tIN

Output
Delay

too
txz
tzx
I/O
Delay
t lO

Figure 3 shows the timing model for the multi-LAB MAX 5000 EPLDs: the
EPM5064, EPM5128, EPM5128A, EPM5130, EPM5192, and EPM5192A
EPLDs. In multi-LAB devices, the Programmable Interconnect Array (PIA)
routes signals between different LABs. AnI! a inputs come into the logic
array through the PIA. Signals routed through the PIA incur an additional
delay.

Figure 3. Multi-LAB MAX 5000 EPLD Timing Model

~ Input
Delay

tIN

Output
Delay

too
txz
tzx
PIA
Delay
tplA

I Altera Corporation

Page 427

I Understanding EPLD Timing

Application Brief 100

The timing model for the EPS464 EPLD is shown in Figure 4.

Figure 4. EPS464 EPLO Timing Model

tsu

Output
Delay

tH
tpRE

too
txz

tCLR
t RO
tCOMB

tzx

MAX 7000 EPLDs
The MAX 7000 architecture differs from the MAX 5000 architecture in
several ways. MAX 7000 architecture has globally routed register Clock
and Clear and tri-state buffer Output Enable signals. Two types of expander
product terms-shared and parallel-can be used to implement complex
logic. Each macro cell can be set for low-power operation to reduce power
dissipation in the EPLD. Figure 5 shows the timing model for MAX 7000
EPLDs.

Figure 5. MAX 7000 EPLO Timing Model

tsu
tH
tpRE

Output
Delay
too

tCLR

txz

t RO

tzx

tCOMB

I Page 428

Altera Corporation

I Application Brief 100

Calculating
Timing Delays

Understanding EPLD Timing

You can calculate pin-to-pin timing delays for any device with the
appropriate timing model and internal delay parameters. Each AC timing
macroparameter is calculated from a combination of internal delays.
Figure 6 illustrates the various macroparameters. To calculate the delay for
a signal that follows a different path through the EPLD, refer to the timing
models shown in Figures 1 through 5 to determine which microparameters
to add together.

Figure 6. AC Timing Parameters (Part 1 of 3)
Combinatorial Delay

c:::>>-------II com~~~f~orial 1-1------!~>-------1C>
Classic
MAX 5000
(single-LAB)
MAX 5000

t pD1

tIN + t LAo + too

t pD2

t lO + tiN + t LAo + too

t pD1

tiN + t LAo + tCOMB + too

t pD2

t lO + t LAo + tCOMB + too

t pD1

tiN + t LAo + tCOMB + too

t pD2

t lO + tplA + t LAo + tCOMB + too

EPS464

t pD1

tIN + t LAD + t COMB + too

tpD2
t pD1

t lO + t LAo + tCOMB + too

MAX 7000

tpD2

t lO + t plA + t LAo + tCOMB + too

(multi-LAB)

tiN + tplA + t LAo + tCOMB + too

Tri-State Enable/Disable Delay

c:: >

=t1

Classic

t pxz , tpzx

tIN + t LAo + (txz or t zx )

MAX 5000

t pxz , tpzx
t pxz , tpzx

tIN+tLAC+(txzor t zx )

EPS464

c:: >

I Altera Corporation

ICombin~torial
I
LogiC

Global
Control

t,N + t LAC + (txz or t zx )

=t1

MAX 7000

tpxz, tpzx

tIN + tGLOB + (txz or tz>d

EPS464

t pxz , tpzx

tiN + tGLOB + (tXZ or t zx )

Page 429

I Understanding EPLD Timing

Application Brief 100

Figure 6. AC Timing Parameters (Part 2 of 3)
Register Clear & Preset Time

c::::::>

Icom~",to,'a' ~t----~C::::::>
.

logiC

Classic

tClR

MAX 5000

tpRE,tClR

tiN + t LAC + (tPREor t CLR ) + too

EPS464

t pRE , tClR

tiN + t LAC + (tPREor t CLR ) + too

MAX 7000

t pRE , tClR

tiN + tplA + t LAC + (tPREor t CLR ) + too

c::::::>>-----I

Global
Control

tiN + tCLR + too

~f----C::::::>
~

MAX 7000

t GCLR

tIN + t GLOB + t CLR + too

EPS464

t GPRE ' t GCLR

tiN + tGLOB + (tPREOr t CLR ) + too

Setup Time

:>-~_-_-_-_-_" _'_c_om_~_~ _f~_or_ia_1,_--Jnt----c::::::>
Classic

tsu

(tIN + t LAD ) - (t,N + tiCS) + tsu

MAX 5000

tsu

(t,N + t LAD ) - (t,N + tiCS) + tsu

EPS464

tsu

(tIN + t LAD ) - (t,N + tGLOB) + tsu

MAX 7000

tsu

(tIN + tplA + t LAD ) - (tIN + t GLOB ) + tsu

Hold Time
' Combin?torial ,
logiC

Classic

(tIN + tiCS) - (tIN + t LAD ) + tH

MAX 5000

(tIN + tiCS ) - (t,N + t LAD ) +tH

EPS464

(tIN + t GLOB ) - (tIN + t LAD ) + tH

MAX 7000

(tIN + t GLOB ) - (tIN + tplA + t LAD ) + tH

Counter Frequency

~ COmbin?toriall

I Page 430

logiC

Classic

tCNT

tFO + tLAD + tsu

MAX 5000

tCNT

tRD + tFD + tLAD + tsu

EPS464

tCNT

tRD + tFD + tLAD + tsu

MAX 7000

tCNT

tRD + t plA + tLAD + tsu

Altera Corporation

I Application Brief 100

Understanding EPLD Timing I

Figure 6. AC Timing Parameters (Part 3 of 3)
Asynchronous Setup Time

Classic

t ASU

(t IN + t LAD) - (tIN + tIC) + t su

MAX 5000

t ASU

(tIN + t LAD ) - (tIN + tIC) + tsu

EPS464

t ASU

(tIN + t LAD ) - (tIN + tIC) + tsu

MAX 7000

t ASU

(t IN + t PIA + t LAD ) - (tIN + t PIA + tIe) + t su

Asynchronous Hold Time

Classic

tAH

(tIN + tIC) - (tIN + t LAD ) + tH

MAX 5000

tAH

(tIN + tIC) - (tIN + t LAD ) + tH

EPS464

tAH

(tIN + tIC) - (tIN + t LAD) + t H

MAX 7000

tAH

(t IN + t PIA + tIC) - (tIN + t PIA + t LAD) + t H

Clock-to-Output Delay

c::::::>
Classic

tC01

tIN + tICS + too

MAX 5000

tC01

tIN + tICS + t RD + too

EPS464

tC01

tIN + t GLOB + t RD + too

MAX 7000

tC01

tIN + tGLOB + tRD + too

c::::::>

Array Clock-to-Output Delay
c::::::>

I Altera Corporation

ICombin~torial
I
LogiC

c::::::>

Classic

t AC01

tIN + tIC + too

MAX 5000

t AC01

tIN + tIC + tRD + too

EPS464

t AC01

tIN + tIC + tRD + too

MAX 7000

t AC01

tIN + t PIA + tIC + t RD + too

Page 431

I Understanding EPLD Timing

Examples

Application Brief 100

The following examples show how to use microparameters to calculate the
delays for real applications.

Example 1: 7483 TTL Macrofunction
You can analyze the timing delays for macrofunctions that have been
subjected to minimization and logic synthesis. A MAX+PLUS II Report
File that includes the optional Equations Section lists the synthesized logic
equations. These equations are structured so that you can quickly determine
the logic configuration. For example, Figure 7 shows part of a 7483 TTL
macrofunction (a 4-bit full adder). The Report File gives the following
equations for 81, the least significant bit of the adder:
81
_LC021
_EQ026

OUTPUT (_LC021

VCC)i

LCELL (_EQ026 $ CO
Bl & tAl
# ! Bl & Al i

Figure 7. Adder Logic Timing for MAX 5000/EPS464 & MAX 7000 Architecture
A1

c:=>---._---,

81 is the output of macrocell21 CLC021), which contains combinatorial
logic. The combinatorial logic LCELL (_EQ02 6 $ co ) represents the XOR of
the intermediate equation _EQ026 and the carry-in co. In turn, _EQ026 is
logically equivalent to the XOR of inputs B1 and Al. Therefore:

Timing delay for 81 in MAX 5000 jEPS464 EPLDs:
tIN + t LAO + tcoMB + too
Timing delay for 81 in MAX 7000 EPLDs:
tIN + tpIA + t LAO + tCOMB + too

I Page 432

Altera Corporation

I Application Brief 100

Understanding EPLD Timing

Example 2: 82 Adder Bit
For complex logic that requires expanders (represented as _x in
Report Files), the expander array delay, tEXP (or tSEXP for MAX 7000
EPLDs), is added to the delay element. The second bit of the 7483 adder
macrofunction, 82, requires shared expanders. The equations are:
S2
- LC019

_EQ023
- X029
- X030
- X031
_EQ024
- X032
- X033

_LC019;
LCELL( _EQ023 $ _EQ024 )
_X031;
&
&
- X029
- X030
EXP( !Bl & !Al ) ;
EXP( !Bl &
!CO ) ;
EXP( !Al &
!CO ) ;
_X032 & _X033;
EXP( !B2 & A2
) ;
EXP( B2 & A2
) ;

;

Figure 8 shows how you can map the logic structure onto the MAX 5000/
EPS464 and MAX 7000 architectures with these equations. Therefore:
Timing delay for 82 in MAX 5000/EPS464 EPLDs:
tIN + t EXP + tLAD + tCOMB + taD
Timing delay for 82 in MAX 7000 EPLDs:
tIN + tpIA + t SEXP + tLAD + tCOMB + taD'

Figure 8. Adder Equations Mapped to MAX 5000/EPS464 & MAX 7000 Architecture

]031

CO
A1
81
A2

MAX 5000/
EPS464:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.

MAX 7000:

I Altera Corporation

Page 433

I Understanding EPLD Timing

Application Brief 100 I

Example 3: 82 Adder Bit With Parallel Expanders (MAX 7000)
The Compiler uses parallel expanders if the Parallel Expanders logic
synthesis option is turned on when a project is compiled for MAX 7000
EPLDs. When parallel expanders are used, no shareable expanders are
used, and the timing delay for the 82 bit of the 7483 becomes:
tIN + tpIA + t LAO + t pExP + tCOMB + too

Example 4: 81 Adder Bit in Low-Power Mode (MAX 7000)
If a macrocell in a MAX 7000 EPLD is set for low-power mode, then you
must add the low-power adder delay to the total delay through that
macrocell. In Figure 7, the 81 delay thus becomes:
tIN + tpIA + t LPA + t LAO + tCOMB + too

Conclusion

I Page 434

The architectures of Altera EPLDs have fixed internal timing delays that
are independent of routing. You can determine the worst-case timing
delays for any design before programming a device. Total delay paths
(macroparameters) can be expressed as the sums of internal timing delays
(microparameters). Timing models illustrate the internal delay paths for
EPLDs and show how these microparameters affect each other. You can
use MAX+PLUS II development tools to automatically calculate delay
paths, or hand-calculate delay paths by adding the microparameters for an
appropriate timing model. With this ability to predict worst-case timing
delays, you can be confident of a design's in-system timing performance.

Altera Corporation

Contents
I August 1993

Section 11

Development Tools
MAX+PLUS II Programmable Logic Development System
& Software .......................................................................................... 437
MAX+PLUS II Selection Guide .................................................................... 449
Altera Programming Hardware .................................................................. 453
CAE Software Support .................................................................................. 459
Programming Hardware Manufacturers .................................................. .463

I A/tera Corporation

Page 4351

MAX+PLUS II
Programmable Logic Development
System & Software
I August 1993, ver. 4

Introduction

Data Sheet I

A programmable logic design environment ideally satisfies a large variety
of design requirements: it should support devices with different
architectures, run on multiple platforms, provide an easy-to-use interface,
and offer a broad range of features. Moreover, the design environment
should give designers the freedom to use the tools of their choice. The
Altera MAX+PLUS II development system, a fully integrated
programmable logic design environment, meets all of these requirements.
The MAX+PLUS II design environment offers unmatched flexibility and
performance. The rich graphical user interface is complemented by complete
and instantly accessible on-line documentation, which makes learning and
using MAX+PLUS II quick and easy.

Modular Tools Designers can customize their development
environment by choosing from a variety of design entry, design
processing, and design verification options, all of which are described
in this data sheet. New features can be added as they are needed,
preserving the initial tools investment. Since MAX+PLUS II supports
multiple device families, designers can add support for new
architectures without having to learn new tools.

Architecture-Independence The MAX+PLUS II Compiler, the heart of
the MAX+PLUS II system, supports Altera's Classic, MAX 5000/
EPS464, MAX 7000, and FLEX 8000 programmable logic device families,
offering the industry's only truly architecture-independent
programmable logic design environment. The Compiler also provides
powerful logic synthesis and minimization to efficiently fit designs
with minimal user effort.

o Multiple Platforms

MAX+ PLUS II runs under Microsoft Windows on
386- or 486-based pes and under X Windows on Sun SPARCstations
and HP 9000 Series 700 workstations.

I Altera Corporation

Open Interfaces Altera works closely with CAE manufacturers to link
MAX+PLUS II with other industry-standard design entry, synthesis,
and verification tools. The interfaces to CAE tools comply with
EDIF 2 a a or 2 9 0, library of parameterized modules (LPM), Verilog,
VHDL, and other standards. They allow designers to create a logic
design with Altera or standard CAE design entry tools, compile the
design for an Altera device with the MAX+PLUS II Compiler, and
Page 437

I MAX+PLUS II Programmable Logic Development System & Software

Data Sheet

perform device- or board-level simulation with Altera or other CAE
verification tools. MAX+PLUS II currently supports interfaces to tools
from Cadence, Exemplar, Data I/O, Intergraph, Mentor Graphics,
Minc, Ore AD, Synopsys, Viewlogic, and others.

o Full Integration Together, the MAX +PLUS II design entry, processing,
and verification features offer the most fully integrated suite of
programmable logic development tools available, allowing faster
debug and shorter development cycles.
The MAX+PLUS II design process, shown in Figure I, consists of four
phases: design entry, design processing, design verification, and device
programming.

Figure 1. MAX+PLUS 1/ Design Environment
Design Entry
r~1
1+;
~

Waveform
Design Entry (1)
Hierarchical
Design Entry

EDIF
LPM
Others

Verification & Programming

Graphic
Design Entry
Text Design
Entry

Design Processing

Standard CAE Design Entry:
Cadence
Mentor Graphics
OrCAD
Synopsys
Viewlogic
Others

Timing
Simulation (1)
Functional
Simulation (1)

MAXtPLUS /I Compiler

Design-Rule
Checking

Multi-Device
Simulation (1)

!C~

Logic
Synthesis &
Fitting

Timing
Analysis

Multi-Device
Partitioning

Device
Programming

ill -

'ilt;
-'":-

,,~~!

Automatic
Error
Location (1)

EDIF
Verilog
VHDL
Others

Standard CAE
Design Verification:
Cadence
Mentor Graphics
Logic Modeling
Synopsys
Viewlogic
Others

Device Support
Options
Note:
(1) Available only in the PC-based version of MAX+PLUS II.

I Page 438

Altera Corporation

I Data Sheet

Design Entry

MAX+PLUS II Programmable Logic Development System & Software

MAX+PLUS II can integrate design files-generated with the
MAX+PLUS II design entry tools or with a variety of other industrystandard CAE design entry tools-into a single design hierarchy. The high
degree of integration between MAX+PLUS II applications allows
information to flow freely to and from each application. For example,
errors identified during compilation, simulation, and timing analysis can
be automatically located and highlighted in the original design file. If a
design (called a project in MAX+PLUS II) consists of two or more
hierarchical levels, the designer can go from one design file directly to all
other design files in the hierarchy, regardless of whether they are graphic-,
text-, or waveform-based.

Schematic Capture & Symbol Editing
The MAX+PLUS II Graphic Editor (shown in Figure 2) makes schematic
design entry fast and easy. Drag-and-drop editing quickly moves one or
more objects or an entire area. During a move, a net can be preserved with
the rubberbanding feature. The designer can also make a design more
compact by connecting primitives with buses to create arrays of symbols.
Over 300 74-series and other macro functions are available.
MAX+PLUS II can automatically create a symbol for any design file. With
the Symbol Editor (also shown in Figure 2), the designer can modify a
symbol to customize its appearance, or create an entirely new symbol.

Figure 2. MAX+PLUS 1/ Graphic & Symbol Editors

-1
a

MAX+plus 11- d:\max2work\tutorial\chiptrip - [Graphic Editor - chiptrip.gdf]
MAX+plu5 II File fdit View Symbol Assign Utilities Options Window

..=!~~..

:1.5

· ·If

:::.:~;;;;r~.::.:.~.:':i.~~:':'1'~5

DIR[1_ - 8 l

5PEED

I'"

R:::~::::=t=

:~:OT

~c'I~ .•

: ••.

I-=-

'~Q

'---

r.;;;1B

•

..._.. o.n--r-:::

i. .•~~~~~::J:~:: ~~ ~s~:i ~~;~c.::~§ ;
r----

Help;

E
F

<<-

'liE

--J
--J
--J
--J

COUT

--3

GOUT

'liE

QF
Q"

It-C

IE--

DNUP

DHUP

'5ETN
CLRN
DLK

I-

SETN
CLAN

r'-C_LK"--_--'
IooUP/DN

COUNTER

I Altera Corporation

Page 439

I MAX+PLUS II Programmable Logic Development System & Software

Data Sheet

Text Design Entry
With the MAX+PLUS II Text Editor, the designer can view and edit any
ASCII text file, including EDIF netlists. The Text Editor is ideal for entering
and editing design files written in the Altera Hardware Description
Language (AHDL).

AHDL
The Altera Hardware Description Language (AHDL) is a high-level modular
language used to create logic designs for Altera devices. It can implement
state machines, truth tables, conditional logic, and Boolean equations.
AHDL syntax supports arithmetic and relational operations such as
addition, subtraction, equality, and magnitude comparisons. Standard
Boolean functions (e.g., AND, OR, NAND, NOR, XOR, and XNOR) are also available.
Since AHDL supports groups, operations can be performed on a byte- or
word-wide basis as well as on single variables. Together, these features
make it easy to implement complex projects in a concise, high-level
description.

Waveform Design Entry
The MAX+PLUS II Waveform Editor (shown in Figure 3) is used to create
and edit waveform design files, as well as input vectors for simulation and
functional testing. The Waveform Editor also functions as a logic analyzer
that allows the designer to view simulation results.
Waveform design entry is best suited for sequential and repeating functions.
The Compiler's advanced waveform synthesis algorithms automatically
generate logic from user-defined input and output waveforms that represent
registered, combinatorial, and state machine logic. The Compiler
automatically assigns state bits and state variables for state machines.
Waveform Editor features allow the designer to copy, cut, paste, repeat,
and stretch waveforms; to create design files with internal nodes, flipflops,
and state machines; to combine waveforms into groups that display binary,
octal, decimal, or hexadecimal values; and to compare two sets of simulation
results by superimposing one set of waveforms on another.

Page 440

Altera Corporation

IData Sheet

MAX+PLUS II Programmable Logic Development System & Software

Figure 3. MAX+PLUS II Waveform Editor
-I
= 1

I" ...

t.4AX+plus 11- d:\mllx2work\tutorial\chiptrip -l\'Yllveform Editor - speed ch.wdfl
MAX+plus II file .I;dlt ~Iew Node Assign .!,!tilities Qptions Window

liEIacceUn
IiEIreset
IiEIclk
[JI]speed
[;IijJget_ticket

I::~T I
INPUT

IDIIT

tlelp ;

r l ~

I-I--

rI
rI
Enter Node

I
Default ~alue: Ix

Node Name:

1/0 I y p e -

o Input Pin
o O.!!.tput Pin

1c::L
!l al
I=-----

~
I.c.ancel

@ Buried Node

For Waveform Design Rle (WDF) Only
Node I y p e -

o fin Input
o Registered
o Combin§.torial
@ Machine

Secondary Inputs
Clock:

R~set:

1
1

10
10

pre~etl

8
3

Time: 10.Ons

lEG

RetlO.ons

Iffi

Interval: 10.ons

,.I

"'i"

Industry-Standard CAE Design Entry
The MAX+PLUS II Compiler can interface with other standard CAE tools
that generate EDIF 2 0 0 and EDIF 2 9 0 netlist files. The Compiler uses
Library Mapping Files (.lmf) to map proprietary symbol and pin names
from other CAE tools to MAX+PLUS II macrofunction and basic-gate
library elements. Altera provides LMFs for over 100 74-series and custom
macrofunctions for files generated by tools from companies such as Cadence,
Mentor Graphics, Minc, OrCAD, and Viewlogic. VHDL and Verilog design
support is also available through Cadence, Exemplar, Intergraph, Mentor
Graphics, Racal-Redac, Synopsys, and Viewlogic. For more information on
other industry-standard design entry tools, see CAE Software Support in
this data book.
MAX+PLUS II also supports design entry using the Library of
Parameterized Modules (LPM). The LPM standard is built upon and
follows the syntax for the EDIF 2 0 0 standard. The Compiler processes
LPM netlists automatically, translating them into a MAX+PLUS IIcompatible format. All LPM gate, arithmetic, and storage components are
supported.
MAX+PLUS II can also read OrCAD Schematic Files (.sch) and Xilinx
Netlist Format Files (.xnf) for compilation or integration into designs for
Altera devices.

IAltera Corporation

Page 441

Data Sheet I

MAX+PLUS II Programmable Logic Development System & Software

Hierarchical Design Entry
Hierarchical designs can consist of design files created with several different
formats, including schematic capture, text design entry (with AHDL),
waveform design entry, and EDIF. MAX+PLUS II supports multiple levels
of hierarchy in a single design. This flexibility allows designers to use the
design entry method best suited to each portion of the design. The
MAX+PLUS II Hierarchy Display, which displays the hierarchy of the
project, allows designers to easily traverse the hierarchy, automatically
opening the appropriate editor for each design file.

Design
Processing

When MAX+PLUS II processes a design, the Compiler reads in design files
and produces programming and simulation files, the Timing Analyzer
analyzes the timing of a design, and the Message Processor automatically
locates errors.

Automatic Error Location
The MAX+PLUS II Message Processor communicates with all
MAX+PLUS II applications, recording error, information, and warning
messages for problems such as connection. and syntax errors. Designers
can use the Message Processor to automatically open the file that contains
the source of an error and highlight its location. See Figure 4.

Figure 4. MAX+PLUS /I Compiler &Message Processor
-I
MAX+plus II

Elle

Complier

Compiler
Netllst
Extractor

IF~9iC ~,
@ !t&

Database
Builder

I· ...

MAX+plus 11- d:\max2work\tutorial\chiptrip
Erocesslng [!evlce lnterlaces .options

yntheslze

Partltloner

Finer

I· ...

liming
SNF
Extractor

Start

Help

Window

Assembler

Id
100,

Stop

Messages - Complier
I· ...
Info: State 'aHera' in state machine4Iauto_max:llstreet_map' is never exited
~
Info: Design Doctor has given the project a clean bill of heaHh based on the EPLD Rules set
Info: Selecting a device from 'MAX5000' family for AUTO device 'chlptrlp'
fInfo: Chip 'chiptrip' successfully fit into AUTO device 'EPM5032'

II ~
I~

Page 442

Message ~ 0 of 4
Locate

~ 10 of 0

H~lp

on Message

Altera Corporation

I Data Sheet

MAX+PLUS II Programmable Logic Development System & Software

Logic Synthesis & Fitting
The Compiler's Logic Synthesizer module supports both synthesized and
what-you-see-is-what-you-get (WYSIWYG) design implementation. It
selects appropriate logic reduction algorithms to minimize and remove
redundant logic, ensuring that the device logic resources are used as
efficiently as possible for a specified device architecture. It also removes
unused logic from the project.
Logic synthesis options help the designer guide the outcome of logic
synthesis. Altera provides three "ready-made" synthesis styles, which
specify the settings for multiple logic synthesis options. The designer can
apply a style to set default synthesis options, create custom styles, and
specify individual synthesis options on selected logic functions. Synthesis
options can be tailored for a specific device family to take advantage of its
architecture. A number of advanced logic options further expand the
designer's ability to influence logic synthesis.
The Compiler's Fitter module applies heuristic rules to select the best
possible implementation for the synthesized project in one or more devices.
This automatic fitting relieves the designer of tedious place-and-route
tasks. The Fitter generates a Report File (.rpt) that shows project
implementation as well as any unused resources in the device(s).

....

---~."

Design-Rule Checking
The MAX+PLUS II Compiler includes the Design Doctor, a design-rulechecker utility. This utility checks each design file for logic that may cause
system-level reliability problems usually discovered only after a design
has entered production. The user can choose one of three predefined sets
of design rules with increasingly thorough design-rule checking, or create
a custom set of rules.
Design rules are based on reliability guidelines that cover logic containing
features such as asynchronous inputs, ripple Clocks, multi-level logic on
Clocks, Preset and Clear configurations, and race conditions. Rule violations
are explained to help the designer determine which edits are needed in the
design files.

Multi-Device Partitioning
If a project does not fit into a single device, the Compiler's Partitioner
module divides it into multiple devices from the same device family. It
attempts to split the project into the smallest possible number of devices
while minimizing the number of pins used for inter-device communication.
The Fitter automatically fits the logic into the specified devices.

I Altera Corporation

Page 443

I MAX+PLUS II Programmable Logic Development System & Software

Data Sheet

Partitioning can be totally automatic, partially user-controlled, or fully
user-controlled. If a project is too large to fit into a specified device, the
designer can specify the type and number of additional devices.

Industry-Standard Output Formats
The Compiler provides netlist writers that can create netlists that can be
used in a variety of simulation environments. These netlists contain postsynthesis functional and timing information that can be used with other
standard design verification tools for device- or board-level simulation.
The following interfaces are available:

o
o

EDIF Interface Creates EDIF 2 0 0 and EDIF 2 9 0 netlists.
Verilog Interface Creates Verilog netlists that can be used with VerilogXL simulators.
VHDL Interface Creates VHDL netlists that can be used with VHDL
simulators.

Programming File Generation
The Assembler module creates one or more Programmer Object Files
(.pof), SRAM Object Files (.sof), and/ or JEDEC Files (.jed) for a compiled
project. The MAX+PLUS II Programmer uses these files and standard
Altera hardware to program the desired devices. Device programming is
also available with other industry-standard programming equipment. In
addition, MAX+PLUS II can generate Intel-format Hexadecimal Files (.hex)
and Tabular Text Files (.Uf) for configuring FLEX 8000 devices. See
Application Note 33 (Configuring FLEX 8000 Devices) in this data book for
more information.

Design
Verification

Design verification processes include design simulation and timing analysis
to test the logical operation and internal timing of a design. Design
verification is available from Altera and from a variety of CAE vendors.

Simulation
The MAX+PLUS II Simulator provides flexibility and control for modeling
single- or multi-device projects. The Simulator uses the Simulator Netlist
File (.snf) generated during compilation to perform functional, timing, or
combined linked multi-device simulation for a project. Figure 5 shows the
Simulator window.
The designer either defines input stimuli with a straightforward vector
input language or draws waveforms directly with the MAX+PLUS II
Waveform Editor. Simulation results can be viewed in the Waveform
Editor or Text Editor and printed as waveform or text files.
Page 444

Altera Corporation

I Data Sheet

MAX+PLUS II Programmable Logic Development System & Software

Figure 5. MAX+PLUS /I Simulator

Simulator: Timing Simulation

1-"1'"

Simulation Time: O.Ons

St~rt Time: 10.Ons

o Use Device
o Setup/Hoi!!
D Qheck Outputs

o Oscillation I
D glitch I
50

£tart

E!ause

I
I
I

I [nd Time: 1200.0ns

I
II Ope!! SCF I
10°1

Slop

The designer specifies commands either interactively or in a Command
File (.cmd) to perform a variety of tasks, such as monitoring the project for
glitches, oscillation, and register setup and hold time violations; halting
the simulation when user-defined conditions are met; forcing flipflops
high or low; and performing functional testing. If a setup or hold time,
minimum pulse width, or oscillation period is violated, the Message
Processor reports the problem. The designer can then use the Message
Processor to locate the time at which the problem occurred in the Waveform
Editor and to locate the error in the original design file.
For easy comparison, the designer can superimpose the results of two
simulations in the Waveform Editor.
Functional Simulation
The MAX+PLUS II Simulator supports functional simulation that tests the
logical operation of a project before it is synthesized, allowing the designer
to quickly identify and correct logical errors. The MAX+PLUS II Waveform
Editor displays the results of functional simulation and provides easy
access to all nodes in the project, including combinatorial functions.
Timing Simulation
In a timing simulation, the MAX+PLUS II Simulator tests the project after
it has been fully synthesized and optimized. Timing simulation is performed
at D.l-ns resolution.

I Altera Corporation

Page 445

Data Sheet I

MAX+PLUS II Programmable Logic Development System & Software

Multi-Device Simulation
MAX+PLUS II can combine the timing and/or functional information
from multiple Altera devices, allowing the designer to simulate several
devices operating together. These projects can be implemented in different
device families.

Timing Analysis
The MAX+PLUS II Timing Analyzer can calculate a matrix of point-topoint device delays, determine setup and hold time requirements at device
pins, and calculate maximum Clock frequency. MAX+PLUS II design
entry tools are integrated with the Timing Analyzer, allowing the designer
to simply tag start and end points in the design to determine the shortest
and longest propagation delays. In addition, the Message Processor can
locate critical paths identified by the Timing Analyzer in the design files
and display them in the appropriate design editor. See Figure 6.

Figure 6. MAX+PLUS II Timing Analyzer

1-"'1'"

Timing Analyzer

Delay Matrix

I--

Destination

I--

81: ALTERA

ticketO

ticket

accel

S
0
y

clock

16.Ons

llOns

dirO

dir1
r
c enable
e reset

42.0ns

., ,
I

I
Device
Programming

Page 446

I--

I.
'0

100

Start

8~oJ~

I j)~)1 P~lths I

The MAX+PLUS II Programmer, shown in Figure 7, uses programming
files generated by the Compiler to program Altera devices. It allows the
designer to program, verify, examine, blank-check, and functionally test
devices. The programming hardware includes an add-on Logic Programmer
card (for PC-AT, PS/2, or compatible computers) that drives the Altera
Master Programming Unit (MPU). The MPU performs continuity checking
to ensure adequate electrical contact between the programming adapter
and the device. With the appropriate programming adapter, the MPU also
Altera Corporation

I Data Sheet

MAX+PLUS II Programmable Logic Development System & Software

Figure 7. MAX+PLUS II Programmer

I'" I'"'

Programmer

Examine

Program

Erogram

o .security Bit

~erify

File: chllJtrip.lJof

E:l:£amlne

I fllank-Check I
T~st

Device: EPL17032
Checksum: 00136295
Copyright: ALTERA88 (3)

supports functional testing, so that vectors created for simulation can be
applied to a programmed device to verify its functionality.
All hardware and software necessary for programming and verifying
devices is available from Altera (see Altera Programming Hardware in this
data book). Programming support is also available from many other
programming hardware manufacturers (see Programming Hardware
Manufacturers in this data book).

On-Line Help

On-line help provides access to all information on MAX +PLUS II. It includes
complete, up-to-date documentation on all MAX+PLUS II applications,
causes and suggested actions for messages, references to related Altera
documentation, text file formats (e.g., AHDL), and information on Altera
devices and adapters.
On-line help is only a keystroke or a mouse click away. The FI key
provides instant access to information on a dialog box, highlighted menu
command, or pop-up message. Typing Shift+ FI turns the mouse pointer
into a question mark pointer that allows the designer to click on any item
on the screen-including primitives, macrofunctions, and AHDL
keywords-for context-sensitive help on that item.

Software
Maintenance
Agreement
I Altera Corporation

To guarantee timely upgrades to software and documentation, Altera
offers a Software Maintenance Agreement that entitles the customer to
software updates, discounts on selected software products, Applications
Engineering support, and access to Altera's electronic bulletin board service
(BBS).

Page 447

I MAX+PLUS II Programmable Logic Development System & Software

Recommended
System
Configurations

Data Sheet

To run MAX+PLUS II with optimum results, Altera recommends the
following system configurations:

PC System Configuration

o 386- or 486-based PC-AT, PS/2 Model 70 or higher, or compatible
o
o

o
o
o
o

computer
16 Mbytes of RAM
DOS version 5.0 or higher
Microsoft Windows version 3.1
Microsoft Windows-compatible graphics card and monitor
35 Mbytes free disk space
1.44-Mbyte 3 1f2-inch floppy disk drive
2- or 3-button mouse compatible with Microsoft Windows 3.1
Full-length 8-bit ISA or Micro Channel Adapter slot for Logic
Programmer card
Parallel port

Sun Workstation System Configuration

o Sun SPARC2 workstation with color or monochrome monitor
o 32 Mbytes of RAM
o Sun OS 4.1.2 (or Solaris 1.0), Note (1)

Sun OpenWindows 3.0 (or Solaris 1.0), Note (1)

o
o

30 Mbytes swap space
ISO 9660-compatible CD-ROM drive

o 50 Mbytes free disk space

Hewlett-Packard Workstation System Configuration

o HP 9000 Series 700 workstation with color or monochrome monitor
o HP-UX 8.07, Note (1)
o HP-VUE

50 Mbytes free disk space

o 32 Mbytes of RAM
o ISO 9660-compatible CD-ROM drive
Note:
(1)

Package
Options

I Page 448

Contact Altera Applications for information on current operating system support.

Altera offers a variety of tool configurations and migration products for
PC- and workstation-based versions of MAX+PLUS II. For up-to-date
information on MAX+PLUS II software packages and development systems,
refer to Ordering Information in this data book or contact Altera Marketing
at (408) 894-7000. For detailed information on package options, refer to the
MAX+PLUS II Selection Guide in this section.

Altera Corporation

MAX+PLUS II
Selection Guide
I August 1993, ver. 1

Development
Systems &
Add-On
Products

Altera offers a variety of system configurations and add-on products for
MAX+PLUS II. MAX+PLUS II supports all of Altera's general-purpose
programmable logic devices, including EPROM-, EEPROM- and SRAMbased devices, for true technology-independent design. Once designers
purchase a device support option, they can add to it at any time. Four
device support options are available:

Classic+Plus Supports the low-power Classic family, and the EPM5016,
EPM5032, EPM7032, and EPM7032V devices.

MAX5000/EPS464 Supports the mid-range MAX5000/EPS464 family.

MAX 7000 Supports the high-performance MAX 7000 family.

FLEX 8000
Supports the register-intensive, high-gate-count,
SRAM-based FLEX 8000 family.

The first decision to make in selecting a MAX +PLUS II system is to
determine the device support needed. The second is to select the desired
features. Table 1 shows the available features and AHera device support
provided by each MAX +PLUS II configuration. Refer to the Device Support
columns in this table, and then use the Design Entry and Compilation and
Verification columns to select the configuration with the appropriate design
development features. The Ordering Codes column provides the necessary
codes for ordering MAX+PLUS II systems and add-on products that provide
features not included in the initial package purchased by the user.
For up-to-date information on available features and device support, contact
Altera Marketing at (408) 894-7000 for a copy of the most current
MAX+PLUS II selection guide.
For a detailed description of MAX +PLUS II development software, see the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet in this data book.

I Altera Corporation

Page 449

I MAX+PLUS II Selection Guide
Table 1. Altera Development Systems, Software &Device Support
Design Entry

Ordering Codes

Device Support

Compilation &Verification

Base Systems (PC Platform)
PLS-ES
PLS-STD
PLS-ADV
PLS-FLEX8
PLS-HPS
PLDS-HPS

v'
v'
v'
v'
v'
v'

v'
v'

v'
v'
v'
v'
v'
v'

v'
v'

v'
v'
v'
v'
v'
v'

v'
v'
v'
v'

v'
v'

v'
v'
v'
v'
v'

v'
v'
v'
v'
v'
v'

Add-On Products (PC Platform)
v'

PLSM-5K

PLSM-7K

PLSM-8K
PLSM-ADE

Base Systems (Workstation Platform)
PLS-WS/HP
PLS-WS/SN

v'
v'

Add-On Products (Workstation Platform)
PLSM-WS/SN
PLSM-WS/HP

PLSM-TA

MAX+PLUS II
Package
Options

This section describes the various MAX+PLU5 II products shown in Table I,
as well as software maintenance products that provide registered users
with regular upgrades to software and documentation. For information on
ordering Altera products, see Ordering Information in this data book.

PC-Based System Configurations
PLS-ES

Contains logic synthesis and fitting support for the Classic family and the
EPM5016, EPM5032, EPM7032, and EPM7032V devices. Also includes
schematic capture, text design entry with AHDL, interface through
EDIF 2 0 0 and 2 9 0 input and output files, LPM netlist reader, hierarchical

Page 450

Altera Corporation

MAX+PLUS II Selection Guide I

design management, on-line help, automatic error location, and timing
analysis.
PLS-STD
Contains logic synthesis and fitting support for the MAX 5000 /EPS464
and Classic families, and the EPM7032 and EPM7032V devices. Also
includes schematic capture, text design entry with AHDL, interface through
EDIF 2 a a and 29 ainput and output files, LPM netlistreader, hierarchical
design management, on-line help, automatic error location, and timing
analysis.
PLS-ADV
Contains logic synthesis and fitting support for the MAX 7000,
MAX 5000 /EPS464, and Classic families. Also includes schematic capture,
text design entry with AHDL, interface through EDIF 2 a a and 2 9 a input
and output files, LPM netlist reader, hierarchical design management, online help, automatic error location, and timing analysis.
PLS-FLEX8
Contains logic synthesis and fitting support for the FLEX SOOO,
MAX 5000 /EPS464, and Classic families, and the EPM7032 and EPM7032V
devices. Also includes schematic capture, text design entry with AHDL,
interface through EDIF 2 a a and 2 9 a input and output files, LPM netlist
reader, hierarchical design management, on-line help, automatic error
location, and timing analysis.
PLS-HPS/PLDS-HPS
Contains all features and device support of PLS-ADV, plus waveform
design entry, design-rule checking, multi-device partitioning, timing
simulation, multi-device simulation, functional simulation, and waveform
editing. PLDS-HPS also includes selected programming hardware,
including the Altera Master Programming Unit (MPU).

PC-Based Add-On Products
PLSM-5K
Adds compilation support for the Altera MAX 5000/EPS464 family to
PLS-ES.
PLSM-7K
Adds compilation support for the Altera MAX 7000 family to PLS-ES,
PLS-STD, and PLS-FLEXS.
PLSM-8K
Adds compilation support for the Altera FLEX
PLS-STD, PLS-ADV, PLS-HPS, and PLDS-HPS.

I Altera Corporation

saoa family

to PLS-ES,

Page 451

MAX+PLUS II Selection Guide

PLSM-ADE
Adds waveform design entry/editing; design-rule checking; functional,
timing, and multi-device simulation; and multi-device partitioning to
PLS-ES, PLS-STD, PLS-ADV, and PLS-FLEXB.
PLAESW-xxx
Software maintenance products for PC-based MAX+PLUS II. Software
Maintenance Agreements ensure that registered users receive all upgrades
to software and documentation when development software is upgraded
or modified to provide new features and/ or to support new devices. To
order a Software Maintenance Agreement, use the PLAESW- prefix followed
by the appropriate product extension (e.g., PLAESW-HPS).

Workstation-Based System Configurations
PLS-WS/SN and PLS-WS/HP
Contains logic synthesis and fitting support for the Classic, MAX 5000/
EPS464, MAX 7000, and FLEX BOOO families. Interface provided to Mentor
Graphics, Cadence, Synopsys, Viewlogic, Intergraph, and other CAE
environments through EDIF 200 and 290 input and output files.
Workstation support also includes text design entry with AHDL, designrule checking, and multi-device partitioning. PLS-WS/SN supports
appropriately configured Sun Sparcstations; PLS-WS/HP supports
appropriately configured HP 9000 Series 700 workstations.
PLAESW-WS
Software maintenance product for workstation-based MAX+PLUS II.

Workstation-Based Add-On Products
PLSM·TA
Adds timing analysis capabilities to MAX+PLUS II for workstations. The
MAX+PLUS II Timing Analyzer can calculate a matrix of point-to-point
device delays, determine set-up and hold-time requirements at device
, pins, and calculate maximum Clock frequency.
PLSM-WS/SN and PLSM-WS/HP
Provides additional floating node licenses for workstation-based
MAX+PLUS II.

Page 452

Altera Corporation

Altera Programming
Hardware
I August 1993, ver.

General
Description

Data Sheet

Altera offers a variety of programming hardware to program and configure
Altera devices. The following products are available:

o
o
o

Logic Programmer Cards
Master Programming Unit
Programming Adapters & FLEX Download Cable
Altera Stand-Alone Programmer

Logic Programmer Cards
Logic Programmer cards generate programming waveforms and voltages
for the Master Programming Unit (MPU). Two Logic Programmer cards
are available: the LPS and LP6. The LP6 card interfaces with IBM PC-AT
and compatible computers; the LPS card interfaces with IBM PS/2 Model
SO, 60, 70, and 80 and compatible Micro Channel computers. Both cards are
software-controlled and can be installed into any full-length expansion slot
in a computer.
Ordering Codes: PLPS, PLP6

Master Programming Unit
The Master Programming Unit (MPU) is a hardware module that is used
together with an appropriate adapter to program Altera devices. The MPU
connects to a Logic Programmer card via a 2S-pin ribbon cable. The MPU
receives power from the Logic Programmer card and does not require an
external power supply. Programming and functional test information is
transmitted from the Logic Programmer card through the ribbon cable to
the MPU. A programming indicator LED on the MPU lights up when the
unit is active.
When used with the appropriate adapter, the MPU automatically tests for
continuity between the device leads and the programming socket before
programming. It can also apply test vectors to functionally test and verify
programmed Altera devices. Test vectors can be created in waveform or
text format in the MAX+PLUS II Waveform Editor or Text Editor and
applied to the device; results can be viewed in waveform or text format.
Ordering Code:

I Altera Corporation

PL-MPU

Page 453

Altera Programming Hardware

Data Sheet

Altera Stand-Alone Programmer
The Altera Stand-Alone Programmer, PL-ASAP2, provides the hardware
and software needed for programming all Altera devices. PL-ASAP2
includes an LP6 Logic Programmer card, an MPU, MAX+PLUS II
Programmer software (which requires Microsoft Windows version 3.1 or
higher), and complete documentation.
Ordering Code:

PL-ASAP2

Programming Adapters & FLEX Download Cable
Altera provides programming adapters for all Altera devices. Two types of
adapters plug directly into the MPU: PLM-prefix and PLAD3-l2 adapters.
PLM-prefix programming adapters contain a socket that supports a specific
device package. The PLAD3-l2 compatibility adapter allows PLE-prefix
programming adapters to be used with the MPU. The PLAD3-l2 adapter
also directly supports programming of the EP330.
Adapters for Configuration EPROMs (PLMJ12l3 and PLMTl064) program
the Configuration EPROMs used to configure FLEX 8000 devices. These
adapters are also used to download configuration data directly to
FLEX 8000 devices via the FLEX Download Cable, which is provided with
Configuration EPROM adapters.
Each adapter contains a zero-insertion-force dual in-line package (DIP),
J-Iead, pin-grid array (PGA), small-outline integrated circuit (SOIC), or
quad flat pack (QFP) socket. The adapters for QFP devices with 100 or
more pins support Altera's QFP carrier technology. See the QFP Carrier &
Development Socket Data Sheet in this data book for more information.
All PLM-prefix adapters, except the Configuration EPROM adapters, allow
functional test vectors to be applied to and read from programmed Altera
devices. Both PLM- and PLE-prefix adapters support open-circuit testing.
Table 1 lists Altera devices, package options, and required adapters.
Ordering Codes: PLExxxx, PLMxxxx, PLAD3-l2

Page 454

Altera Corporation

Altera Programming Hardware I

Data Sheet

Table 1. Oevice Adapter Support (Part 1 of 2)

Device

Altera Corporation

Package

Adapter

EP330

DIP
J-Lead
SOIC

PLAD3-12
PLEJ330
PLES330

EP600/61 0/61 0A/61 OT

DIP
J-Iead
SOIC

PLED610
PLEJ610
PLES610

EP900/91 0/91 0A/91 OT

DIP
J-Iead

PLED910
PLEJ910

EP1800/181 0/181 OT

J-Iead
PGA

PLMJ1810
PLEG1810

EPB2001

J-Iead

PLEJ2001

EPM5016

DIP
J-Iead
SOIC

PLED5016
PLEJ5016
PLES5016

EPM5032

DIP
J-Iead
SOIC

PLMD5032
PLMJ5032
PLES5032

EPM5064

J-Iead

PLMJ5064

EPM5128/5128A

J-Iead
PGA

PLMJ5128A
PLMG5128A

EPM5130

J-Iead
PGA
QFP

PLMJ5130
PLEG5130
PLMQ5130

EPM5192/5192A

J-Iead
PGA
QFP (EPM5192A
only)

PLMJ5192
PLMG5192
PLMQ5192A

EPM7032, EPM7032V

J-Iead
QFP
TQFP

PLMJ7032-44
PLMQ7032-44
PLMT7032-44

EPM7064

J-Iead (68-pin)
J-Iead (84-pin)
PQFP

PLMJ7000-68
PLMJ7000-84
PLMQ7000-1 00

EPM7096

J-Iead (68-pin)
J-Iead (84-pin)
QFP

PLMJ7000-68
PLMJ7000-84
PLMQ7000-100

EPM7128

J-Iead (68-pin)
J-Iead (84-pin)
QFP (100-pin)
QFP (160-pin)

PLMJ7000-68
PLMJ7000-84
PLMQ7000-1 00
PLMQ7128-160

Page 4551

I Altera Programming Hardware

Data Sheet

Table 1. Device Adapter Support (Part 2 of 2)

Device

Package

Adapter

EPM7160

J-Iead
OFP (1 ~O-pin)
OFP (160-pin)

PLMJ7000-84
PLM07000-100
PLM07160-160

EPM7192

PGA
OFP

PLMG7192-160
PLM07192-160

EPM7256

PGA
OFP (160-pin)
OFP (208-pin)

PLMG7256-192
PLM07256-160
PLM07256-208

All FLEX 8000 devices

all

Note (1)

EPC1064

DIP
J-Iead
TOFP

PLMJ1213
PLMJ1213
PLMT1064

EPC1213

DIP
J-Iead

PLMJ1213
PLMJ1213

EPS448

DIP
J-Iead

PLED448
PLEJ448

EPS464

J-Iead
OFP

PLMJ464
PLM0464

Note to table:
(1)

Programming
Support

Configuration of FLEX 8000 devices is supported by Configuration EPROMs and
the FLEX Download Cable.

Altera customers can obtain or increase device support with the hardware
shown in Table 2. By matching his or her current programming hardware
setup with the desired device support, the designer can determine additional
programming hardware that is required for device programming.

Table 2. Programming Hardware Requirements (Part 1 of 2)

Current Programming
Hardware

Desired Device Support

Additional Programming Hardware Required
IBM PC-AT & Compatible

IBM PS/2 & Compatible

None

All Altera devices

PL-ASAP2;
Appropriate programming
adapters

PLP5;
PL-MPU;
Appropriate programming
adapters

LP5 or LP6 Logic
Programmer card

All Altera devices

PL-MPU;
Appropriate programming
adapters

I Page 456

Altera Corporation

Data Sheet

Altera Programming Hardware I

Table 2. Programming Hardware Requirements (Part 2 of 2)
Current Programming
Hardware

Desired Device Support

Additional Programming Hardware Required
IBM PC-AT & Compatible

Appropriate programming
adapters

EPM5032 (DIP & J-Iead)
EPM5064
EPM5128
EPM5128A
EPS464
EPM5192
EPM5192A
All MAX 7000 devices
All Configuration
EPROMs

Appropriate programming
adapters

All Classic devices
EPM5016
EPM5032 (SOIC)
EPM5130
EPS448
EPB2001

PLAD3-12 adapter;
Appropriate programming
adapters

EPM5032 (DIP & J-Iead)
EPM5064
EPM5128
EPM5128A
EPS464
EPM5192
EPM5192A
All MAX 7000 devices
All Configuration
EPROMs

PL-MPU;
Appropriate programming
adapters

All Classic devices
EPM5016
EPM5032 (SOIC)
PLE3-12A or PLE3-12,
EPM5130
programming unit or
EPS448
PL-MPU programming EPB2001
unit (with PLAD3-12
adapter)
LP5 or LP6 Logic
Programmer card;
PL-MPU programming
unit

LP5 or LP6 Logic
Programmer card;
PL-MPU programming
unit (no PLAD3-12
adapter)
LP5 or LP6 Logic
Programmer card;
PLE3-12A or PLE3-12
Programming unit

1 Altera Corporation

IBM PS/2 & Compatible

Appropriate programming
adapters

LP5 or LP6 Logic
Programmer card;

Page 4571

Notes:

CAE Software Support
August 1993

Introduction

Altera recognizes the importance of supporting other industry-standard
design tools, and works closely with leading CAE software manufacturers
to provide high-quality development support for Altera programmable
logic devices. To ensure strategic partnerships with CAE tool manufacturers,
Altera has established the ACCESS program. Through this program, Altera
and its CAE partners work together to develop either direct support for
Altera devices or seamless integration with Altera's MAX+PLUS II
development software.
Table 1 summarizes each company's design entry, compilation/synthesis,
and simulation/verification products that support Altera devices directly
or provide an interface to MAX+PLUS II. As shown in Table I, Altera also
supplies design interface kits for several CAE tools. Altera recommends
contacting CAE software manufacturers directly for details on product
features, specific device support, and product availability. While Altera
provides technical assistance to these companies, final responsibility for
the quality and accuracy of these products rests with these manufacturers.
Contact the Altera Applications Department by telephone at
(800) 800-EPLD or by fax at (408) 954-0348 for the most up-to-date
information on CAE support.

Altera Corporation

Page 4591

I CAE Software Support

Table 1. Standard CAE Support for Altera Oevices (Part 1 of 2)

Company

Product

Design
Entry

Compilationl
Synthesis

Simulationl
Verification

./
./

Accel Technologies, Inc.
TEL: (619) 554-1000
FAX: (619) 554-1019

Tango-PLD
Tango-Schematic

Acugen Software, Inc.
TEL: (603) 881-8821
FAX: (603) 881-8906

AADELAY
AAMAX
ATGEN

Aldec, Inc.
TEL: (805) 499-6867
FAX: (805) 498-7945

Susie

Cadence Design Systems, Inc.
TEL: (408) 943-1234
FAX: (408) 943-0402

Composer (1)
Concept (1)
RapidSIM (1)
SystemPGA
Synergy (2)
Verilog, Verilog-XL (1)
Leapfrog (2)

Data I/O Corp.
TEL: (800) 247-5700
FAX: (206) 882-1043

ABEL-FPGA
ABEL
FutureNet

./
./
./

Exemplar Logic, Inc.
TEL: (510) 849-0937
FAX: (510) 849-9935

CORE Solution

Flynn Systems Corp.
TEL: (603) 891-1111
FAX: (603) 891-1074

FS-High Density
FS-PALibrary

./
./

GenRad (U.K.)
TEL: 329 822240
FAX: 329822305

Hilo

Intergraph Corp.
TEL: (800) 239-4111
FAX: (303) 581-9972

ACEPlus
AdvanSIM-1076
DLAB
Synovation

ISDATA GmbH (Germany)
TEL: 0721/751087
FAX: 07211752634

LOG/ic

Logic Modeling Corp.
TEL: (503) 690-6900
FAX: (503) 690-6906

SmartModels

I Page 460

./
./
./
./

./
./
./

./
./

./
./
./

./
./
./
./

./
./
./

Altera Corporation

CAE Software SuppCii!J

Table 1. Standard CAE Support for A/tera Devices (Part 2 of 2)

Company

Product

Design
Entry

Compilation!
Synthesis

Simulation!
Verification
v'

Logical Devices, Inc.
TEL: (800) 331-7766
FAX: (305) 428-1811

CUPL

Mentor Graphics Corp.
TEL: (503) 626-7000
FAX: (503) 685-1268

AutoLogic (1)
Design Architect (1)
PLD Synthesis
QuickSim II (1)

v'
v'

Minc Inc.
TEL: (719) 590-1155
FAX: (719) 590-7330

PLDesigner-XL

OrCAD Systems Corp.
TEL: (503) 690-9881
FAX: (503) 690-9891

PLD
MOD
SDT
VST

v'
v'

Quad Design
TEL: (800) 988-8250
FAX: (805) 988-8259

Motive

Racal-Redac
TEL: (201) 848-8000
FAX: (201) 848-7953

Cadat
System Expert
Visula

Synopsys, Inc.
TEL: (415) 962-5000
FAX: (415) 694-4249

FPGA Compiler (1)
DC/Pro
DC/Expert
VSS Simulator

Viewlogic Systems, Inc.
TEL: (800) 422-4600
FAX: (508) 480-0882

Viewdraw (1)
ViewPLD
Viewsim (1)
VHDL Designer

v'
v'

v'
v'
v'

v'
v'
v'
v'
v'

v'
v'

Notes:
(1)

(2)

Interface design kits are available from Altera.
Interface under development. Contact Altera Corporation for more information.

Altera Corporation

Page 461

Notes:

Programming Hardware
Manufacturers
I

August 1993

Introduction

Table 1 lists the manufacturers that offer programming hardware support
for Altera devices. These companies are continually developing support
for Altera programmable logic and configuration devices. Altera
recommends contacting manufacturers directly for details on product
features, specific device support, and product availability. While Altera
provides technical assistance to these companies, final responsibility for
the quality and accuracy of these products rests with these manufacturers.

Table 1. Programming Hardware Manufacturers (Part 1 of 2)
Manufacturer

Country

Telephone

Fax
(408) 245-8268

Advantech

U.S.A.

(408) 245-6678

Advin Systems, Inc.

U.S.A.

(408) 243-7000

(408) 736-2503

Ando Electric Co. Ltd.

Japan

33733 1161

337397310

Aval Data Corp.

Japan

353757321

353757717

B&C Microsystems, Inc.

U.S.A.

(408) 730-5511

(408) 730-5521

BP Microsystems

U.S.A.

(713) 688-4600

(713) 688-0920

Bytek Corporation

U.S.A.

(407) 994-3520

(407) 994-3615

Celectronic GmbH

Germany

304136075

304136078

Cornelius Consult

Germany

234361206

234356698

DATA I/O

U.S.A.

(206) 881-6444

(206) 882-1043

Elan Digital Systems Limited, U.K.

U.K.

(489) 579799

(489) 577516

ertec GmbH

Germany

9131 75570

9131 755710

HAMIS Haase, Menrad & Co. GmbH

Germany

531 70231

531 74020

ICE Technical Ltd.

U.K.

226767404

226370434

Instronic Peripherals & Systems

India

812324967

812324848

Leap Electronic Co., Ltd.

Taiwan

29991860

29990015

Link Computer Graphics, Inc.

U.S.A.

(201) 808-8990

(201) 808-8786

Logical Devices, Inc.

U.S.A.

(305) 428-6868

(305) 428-1811

Micro EDA

U.S.A.

(818) 912-7617

(818) 964-4989

MicroPross

France

20479040

20479369

Owen Electronic GmbH

Germany

6381 42020

63B1 420285

Prologic Systems

U.S.A.

(303) 460-0103

(303) 469-5565

SMS Micro Systems

U.S.A.

(206) 8B3-8447

(206) 883-B601

Altera Corporation

Page 4631

I Programming Hardware Manufacturers
Table 1. Programming Hardware Manufacturers (Part 2 of 2)
Manufacturer

Country

Telephone

Fax

Stag Microsystems

U.S.A.

(408) 988-1118

(408) 988-1232

Sunrise Electronic Inc.

U.S.A.

(818) 914-1926

(818) 914-1583

Sunshine Electronics Co., Ltd.

Taiwan

27633732

27654065

System General

U.S.A.

(408) 263-6667

(408) 262-9220

Tribal Microsystems/HiLo Systems

U.S.A.

(510) 623-8859

(510) 623-9925

Xeltek

U.S.A.

(408) 524-1935

(408) 295-7084

I Page 464

Altera Corporation

Contents
I

August 1993

Section 12

General Information
Technology & Reliability .............................................................................. 467
QFP Carrier & Development Socket ........................................................... 479
Altera Device Package Outlines .................................................................. 489
Ordering Information ................................................................................... 521
Technical Support from Altera Applications ............................................ 529
Sales Offices, Distributors & Representatives ........................................... 531

Altera Corporation

Page 4651

Technology & Reliability
I August 1993, ver. 1

Data Sheet

Introduction

Altera's broad range of programmable logic devices incorporates three
memory technologies: EPROM, EEPROM, and SRAM. To ensure the highest
level of device performance and reliability, Altera maintains a
comprehensive testing program that carefully monitors the factors affecting
the basic programming elements of each device technology. Altera maintains
rigorous quality standards both before a device technology is put into
production and throughout the manufacturing process.

EPROM

The EPROM transistor is a modified NMOS transistor in which the threshold
voltage is easily changed between a low voltage (near Vss) and a high
voltage (greater than Vcd. The different threshold voltages represent the
EPROM cell in the on and off states.

Technology

The EPROM transistor has a floating polysilicon gate between the access
gate and the substrate, as shown in Figure 1. The floating gate is electrically
isolated from the substrate by a thin-gate oxide that is approximately 200 A
thick, and from the access gate by a thicker dielectric inter-poly oxide that
typically consists of oxides and/ or nitrides.

Figure 1. EPROM Cell Construction
Inter-Poly Oxide

Access Gate

Gate Oxide

Floating Gate
P-Type Silicon

EPROM transistors are programmed to a high-threshold voltage with hot
electron injection. When a programming voltage Vpp (normally 12.5 V) is
applied to the access gate of an EPROM cell and a slightly lower voltage is
applied to its drain, electrons flow from the source to the drain. As these
electrons pick up kinetic energy, their path is altered by an electric field
located between the access gate and substrate. This electric field is generated
1

Altera Corporation

Page 4671

I Technology & Reliability

Data Sheet

by the potential difference between Vpp on the access gate and the slightly
lower drain voltage. Electrons that achieve a kinetic energy of 3.2 eV or
more, accelerate vertically toward the floating gate, pass through the gate
oxide, and are trapped on the floating-gate electrode. These excess electrons
create a net negative voltage on the floating gate that opposes the electrical
field created by the positive voltage on the access gate. The result is a
substantial increase in the threshold voltage required to change the EPROM
cell into a conducting state. See Figure 2.

Figure 2. EPROM Cell Programming
Vee

= Vpp
Access Gate

Floating Gate

P-Type Silicon

Figure 3 shows the current-voltage (I-V) relationships for programmed
(high-threshold voltage) and erased (low-threshold voltage) EPROM cells.
The programmed EPROM cell behaves as a transistor that is turned off,
since source-drain current does not flow for access-gate voltages ranging
from 0 to Vcc. In contrast, an erased cell produces source-drain current
when its access gate is brought to approximately 1 V (on).
Programmed EPROM cells in the off state are erased by exposing the
device to ultraviolet (UV) radiation with wavelengths of 2,540 A. The
excess electrons on the floating gate absorb radiant energy from this UV
exposure, raising their energy levels above the 3.2-eVbarrier. The increased
energy levels enable the electrons to overcome the oxide-silicon potential
barrier and migrate into the substrate, where they are neutralized.

I Page 468

Altera Corporation

Technology & Reliabil1tY]

Data Sheet

Figure 3. Current vs. Voltage Relationships of Erased & Programmed EPROM Cells
EEPROM Cell I-V Characteristics

Equivalent Cell for Margin Testing

Programmed (1) Cell
After Programming

Erased (0) Cell

1:
~

Program
Voltage

Erased

~_M~~ _______ _M~~_~

a:
a..

Sense Amp
Trip Point

5.5
Voltage (VGS) on Access Gate

EEPROM
Technology

Like the EPROM transistor, the EEPROM transistor is an MOS transistor
that is either on or off, depending on the threshold voltage. Unlike EPROM
devices, however, EEPROM devices can be electrically erased. The EEPROM
cell consists of a single floating polysilicon gate structure that is used to
change the threshold voltage of the transistor. See Figure 4. The threshold
voltage is changed when a tunneling mechanism traps an excess of electrons
on the floating gate. Fowler-Nordheim tunneling occurs when the floating
gate is raised to a high voltage (12 V to 13 V) via capacitive coupling to the
N+ implant region. Once the electrons have been trapped on the floating
gate, they present a negative shielding voltage and increase the threshold
voltage of the transistor, making it impossible to turn the transistor on
under normal operating voltages. This process allows the floating gate to
act as an onloff switch for the read transistor.
The EEPROM cell is erased with the same tunneling mechanism. Since the
electrons are removed from the floating gate, the gate has a net positive
charge that allows the EEPROM transistor to be turned on or off, depending
on the voltage on the control gate.
For a complete operational description of the EEPROM cell, see the
EPM7032 Process, Assembly, and Reliability Information Package, available
from Altera or from an Altera sales representative.

Altera Corporation

Page 4691

I Technology & Reliability

Data Sheet

Figure 4. EEPROM Cell Construction
Control-Gate
Node (Metal)
Floating Polysilicon Gate,
Capacitively Coupled to N+

Word-Line Polysilicon
Sense Amp
(+) Input

' " Write Column
(Data Input)

MD Implant, N+
Thin-Gate Oxide,
200 A

Source/Drain Implant

Field Oxide
Isolation
MD Implant, N+
Sense Amp
(-) Input
Field Oxide
Isolation

Tunnel Oxide, 80 A
for Fowler-Nordheim
Tunneling

J = AE 2exp(-8/E)

Figure 5 shows a 2-electrode structure in which one electrode is formed by
polysilicon and another is formed by a heavily doped N-type silicon
diffusion. These electrodes are separated by a tunnel oxide that is
approximately 80 A thick. When typical operating voltages of 5 V or less
are applied across the tunnel oxide, it acts as a dielectric and does not
conduct electricity. When 12 V to 14 V are applied, however, electrons
tunnel through the oxide. This process is characterized by an extremely
small tunneling current (less than 10-20 A) at typical operating voltages of
5 V or less. At higher voltages that are used to erase or program the cell
(i.e., charge or discharge the floating gate), the exponential rise in current
produces approximately 1 IlA of current flow through the tunnel oxide.
Depending on the voltage's polarity, this current is sufficient to charge or
discharge the cell within a few milliseconds.

I Page 470

Altera Corporation

Data Sheet

Technology & Reliability I

Figure 5. EEPROM Floating-Gate Electrode, Tunnel Oxide & Heavily Doped
Diffusion Electrode

POIYSiHcon···

The I-V relationships for programmed and erased EEPROM cells are
similar to those of EPROM cells (see Figure 6). Unlike the EPROM cell,
however, the threshold voltage of a discharged EEPROM cell is negative
(less than a V) because electrons are removed from the floating gate.
Electron removal gives the floating gate a net positive charge.

Figure 6. Current vs. Voltage Relationships of an Erased & of a Programmed EEPROM Cell
EEPROM Cell I-V Characteristics

Equivalent Circuit for Margin Testing
Sense Amp (+) Input~

Discharged Cell (0)
I
I
I
I
I
I

:I /

V DD

= 2.0 V

Charged Cell (1)
V WL

= 3.5 V

c::::J~----i.

Program
Margin

Erase
Margin ~

--~~-------------

_ Sense Amp
Trip Point

o
5.5
Voltage (V CG) on Control Gate

I Altera Corporation

Page 471

I Technology & Reliability

SRAM
Technology

Data Sheet

Altera's FLEX 8000 programmable logic devices use static RAM (SRAM)
memory cells as the basic programming element. Figure 7 shows the
standard CMOS five-transistor cell that comprises the memory element.
The process used to manufacture FLEX 8000 devices is a subset of the
EEPROM fabrication process. Therefore, all process development and
reliability enhancements used to manufacture EEPROM devices also apply
to SRAM-based devices.

Figure 7. SRAM Memory Cell
Voo

Address

Data In

Data Out

Address

Failure
Mechanisms &
Reliability
Screens

Both EPROM and EEPROM cells function through a change in threshold
voltage. Reliable EPROM and EEPROM cells maintain their charge by
holding excess electrons placed on the floating gate over the expected life
of the device, thus maintaining a high-threshold voltage (off state).
Discharged cells maintain a low-threshold voltage (on state) in which no
electrons move onto the floating gate over the life of the device.

Voltage Margin Testing
Voltage margin testing is used to measure the threshold voltage of EPROM
or EEPROM cells. This testing is essential for monitoring the
programmability and erasability of a device, as well as its long-term
stability after programming or erasure. Altera devices incorporate special
test-mode circuitry that enables the threshold voltage (i.e., voltage margin)
of each EPROM or EEPROM cell on a device to be measured. (Since SRAM
cells are configured at system power-up by a Configuration EPROM or an
external host, voltage margin testing does not apply.) This circuitry is used
to measure the programmability of all devices and to implement screens
that detect charge loss from programmed devices. During this screening
process, any degradation of the threshold voltage is measured for each cell
as a function of time, temperature~ and voltage.

I Page 472

Altera Corporation

I Data Sheet

Technology & Reliability I

The first voltage margin test is performed during wafer sort. Wafer testing
at Altera consists of multiple wafer sort operations. At Wafer Sort I,
devices are tested for combinatorial and registered logic functionality and
cell programming to ensure that all EPROM or EEPROM cells are fully
programmable. Each cell is "voltage-margined" to ensure that its threshold
voltage exceeds 5.5 V, which is the maximum Vee value encountered
during normal operation. After this process, each cell's access gate is raised
to a high voltage (12 V) to pull electrons off the floating gate through any
defects in the inter-poly oxide between the floating and access gates. See
Figure 8.

Figure 8. DC Erase Stress for an EPROM Cell
Po/ysi/icon 2
Access Gate

Polysilicon 1
F/oating Gate

As shown in Figures 1 and 2, the floating gate is completely surrounded by
oxide. Any defect in the oxide or contamination by mobile ionic charges
such as Na+ can cause electrons to migrate off the gate. This" cell stress," or
DC erase stress, lowers the threshold voltage of any cell with a defective
oxide. A cell's base threshold voltage is determined by performing a
voltage margin test immediately after programming and before the DC
erase stress. After the DC erase stress is applied, each cell's voltage margin
is tested again. If any cell shows a significant reduction in threshold
voltage, the device is rejected from the manufacturing flow.
Thermally activated charge-loss mechanisms are also reliability hazards.
To detect material defects, every device is baked at a high temperature
with all cells in the charged state after Wafer Sort 1. Depending on the
device, this bake is performed at 3000 C for 12 hours or 245 0 C for 96 hours.
After the bake, the threshold voltage for each cell is remeasured during
Wafer Sort 2 and compared to its pre-bake values. Devices with cells that
exhibit a reduced threshold voltage are rejected from the manufacturing
flow. Additional margin testing is performed on packaged devices after
assembly.
Figure 9 shows a typical wafer-sort process.

I Altera Corporation

Page 473

I Technology & Reliability

Data Sheet

Figure 9. Wafer-Sort, Assembly &Final Test Flow for Altera Devices
Electrical Test
100%: 3 Sites/Wafer

Ie Package Assembly

Wafer Sort 1

Final Electrical Test

Verify Functionality/
Programmability

Verify Functionality/
Programmability/Speed

SRAM Devices

EPROM and
EEPROM Devices

Electrical QA

Data Retention Bake
245 0 C/96 Hours or
300 0 C/12 Hours

Wafer Sort 2
Verify Margins and
Check for Charge Loss/Gain

Erasure
(UV or Electrical)

Wafer Sort 3
Verify Erasure

Mark

MechanicallVisual
Inspection: 100%

MechanicallVisual
QA: Sample

Ship

Reliability Screening
The various wafer-sort operations also include reliability screening. Voltage
and temperature-accelerated stresses are applied to activate potential
charge-loss failure mechanisms within the device. Reliability testing is an
integral part of the standard production test flow for all Altera devices. To
ensure the effectiveness of Altera's testing program, test results are
continuously verified.
After the Ie package assembly operation, during which the individual dice
are removed from the wafers and placed into packages, each device is
tested, and the results are compared against data-sheet specifications. This
test is performed at elevated temperatures to ensure that specifications are

I Page 474

Altera Corporation

I Data Sheet

Technology & Reliability

met for the maximum guaranteed operating temperature: 70° C for
commercial, 85° C for industrial, and 125 0 C for military devices.

Altera
Reliability
Program

Altera's integrated circuits must meet rigorous reliability standards. Altera
uses a two-phase approach to ensure a consistent high level of reliability
from its manufacturing processes and devices:

New product/production process qualification
Reliability monitoring

New Product/Production Process Qualification
Altera performs rigorous reliability tests on new devices and subjects new
or substantially modified processes to a rigorous series of reliability tests
before production. Tests are perfomed to Altera, industry, and
MIL-STD-883 (rev. C) standards. This qualification procedure ensures that
all manufacturing processes and products meet Altera's minimum reliability
requirements. Tables 1 and 2 show the reliability tests for hermetic and
plastic package devices, respectively.

Altera Corporation

Page 4751

I Technology & Reliability

Data Sheet

Table 1. Hermetic Package Qualification Requirements
Sequence

MIL-STD-BB3
(Rev. C)
Method

Test

~\.~

Requirements
s,

~v~~

~~ ~ ~~

~~... ~

.~ ~~ ~~

~~<§' ~~«~#~ ~v't>
.s~<::>~~~ C:,~~;F~~~~~'~'b~'t>
~ ,,~ ~'t> ,,~ ~«. ~'t>

~~~ e:,~~ ~i~ ~~~ ~~~ ~~~ ~~~~ «~

~ ~

Latch-up

~ ~

Retention bake

~ ~

ESO sensitivity

3015.7

B2 Mark permanency

2015

B3 Solderability

2003

~ ~ ~ ~

B5 Bond strength

2011

~ ~ ~

C1 Lifetest 1,000/2,000 hours 1005 (125° C)

~
~ ~

01 Physical dimensions

2016

~ ~ ~

02 Lead fatigue

2004 B2

~ ~ ~ ~

~ ~ ~

~ ~

~ ~ ~

Fine & gross leak
03 Thermal shock
Temperature cycle

1014
1011.7B

~ ~

1010.7 C

Moisture resistance
Fine & gross leak

1014

External visual

1004

End point electrical

Altera

04 Mechanical shock
Vibration variable

2002 B

2007 A

Frequency
Constant acceleration

2001 E (30 kg)

Fine & gross leak

1014

External visual
End point electrical

Altera

04 Internal water vapor

1018 (5000
ppm maximum)

3/5 0/1

~ ~ ~

08 Lid torque

2024

~ ~ ~ ~

Note:
(1) LTPD: Lot Tolerance Percent Defective

I Page 476

Altera Corporation

Technology & Reliability I

Data Sheet

Table 2. Plastic Package Qualification Requirements
Sequence

MIL-STD-883
(Rev. C)
Method

Test

\
I\)\'?J

Requirements
~

~~~~ ~~~

~~ ~

~.~ ~~~ fV~~ ~~~

~~ ~C:,~~ ~~~ q,,'~~Ib~ ~Ib~~«~~\'~:~~~~~~

;fi' £ ~..", ,,~.. "~~~ ~'Ii
~~~c:>Ib~.~

B1 Physical dimension

2016

B2 Mark permanency

2015

B3 Solderability

2003

B4 Autoclave 121 ° C/100% rh
15 psi, unbiased: 168 hours

../
../
10 22 0 ../
5 77 1 ../

../ ../
../
../
../ ../ ../
../ ../ ../ ../

../ ../
../ ../

0 ../

../
../
../
../

../ ../
../ ../ ../
../ ../ ../

B5 Bond strength

2011

C1 Lifetest 1,000/2,000 hours

1005 (125° C)

5 77

C2 85/85 with bias: 1,000 hours

85° C/85%
relative
humidity

5 77

01 Lead integrity

2004.5

15 15

10 22

../ ../ ../
../ ../ ../ ../

1011.7B

5 77

../ ../ ../

1010.7 C

5 77

../ ../ ../ ../ ../ ../ ../

02 Resistance to solder heat:

15 15

../ ../

260° C for 10 seconds
03 Thermal shock

../ ../ ../

-55° C to +125° C,
100 cycles
04 Temperature cycle
-65° C to +125° C,
1,000 cycles

Note:
(1) LTPD: Lot Tolerance Percent Defective

Reliability Monitoring
Once a device or process is qualified for production, Altera routinely
conducts reliability tests throughout its manufacturing life cycle. Reliability
tests are conducted under the careful supervision of trained reliability
engineers and technicians, and are perfomed to Altera, industry, and
MIL-STD-883 (rev. C) standards. Table 3 describes the reliability tests and
shows how often they are performed.

1 Altera Corporation

Page 4771

ITechnology & Reliability

Data Sheet

Table 3. Reliability Test Program
Test Type

MIL-STD-883C
Method/Condition

Lifetest

2,000 hours at 1250 C at rated
voltages

Data retention bake
Temperature cycling

Test Frequency

Plastic Hermetic
Package Package

1 time per month per process

1,000 hours (minimum) at 1700 C

1 time per month per process

1,000 cycles

1 time per month per process

2 times per year per package

1010.7, condition C
-55 0 C to + 1500 C (plastic)
-65 0 C to + 150 0 C (hermetic)
Thermal shock

1011.7, condition 8
-55 0 C to +125 0 C

Constant acceleration

2001 E, 30,000G force, Y1 only

2 times per year per package

Mechanical shock

20028, 1500G force, 0.5-ms

2 times per year per package

pulse peak
Lid torque

2024

1 time per month per package

Lead integrity

200482

2 times per year per package

1018, 5000 ppm maximum at

1 time per month per package

Internal water vapor content

1000 C
Temperature/humidity/bias

85 0 C/85% relative humidity, 5 V,
1,000 hours minimum

1 time per month per package

Autoclave (pressure cooker)

121 0 C, 2 atm, 96 hours

1 time per month per package

minimum

Altera's Reliability Engineering Lab uses the latest equipment for reliability
testing, allowing Altera engineers and technicians to perform accurate
reliability qualifications and monitoring on a timely basis. This equipment
provides engineers and technicians with the control and precision required
to perform rigorous semiconductor stress tests.
Results from Altera's reliability monitoring program are published several
times each year in the Altera Reliability Report. This report summarizes the
test results for all Altera devices over a IS-month period. It includes
detailed descriptions of the reliability tests, their implementation, and
useful information about semiconductor reliability. For a copy of the Altera
Reliability Report, contact the Altera Literature Department at
(408) 894-7134.

I Page 478

Altera Corporation

QFP Carrier &
Development Socket
I August 1993, ver. 5

Features

Data Sheet

o
o

General
Description

Quad flat pack (QFP) carriers protect fragile leads on Altera QFP
devices.
Development socket allows on-board electrical and mechanical
prototype testing with QFP packages.
QFP carriers eliminate damage to leads caused by device handling.
Carriers and sockets are available in 100-, 160-, and 208-pin counts.
Development socket footprints match QFP footprints, making
migration to production easier.

The Altera QFP carrier and development socket protect the fragile leads on
QFP devices during shipping and throughout the development cycle. The
socket has the same lead footprint as the device, so it can be used both
during mechanical and electrical prototyping.
The material used in the carrier and development socket helps prevent
electrostatic damage to the devices while providing excellent AC circuit
performance. QFP carriers and development sockets are currently available
for 100-, 160-, and 208-pin QFP packages. Figure 1 shows the 100-pin QFP
carrier and development socket.

Figure 1. 100-Pin QFP
Carrier & Development
Socket

Development Socket
Lid
________

QFPCarrier

Development
Socket

Altera Corporation

Page 4791

I QFP Carrier & Development Socket

QFP Carrier

Data Sheet

The carrier is a static-dissipative, molded plastic shell that holds the device
and leads in a secure frame to prevent mechanical damage. The device is
held in the carrier by recessed plastic clips (2 clips on the 100-pin carrier
and 4 clips on the 160-pin and 208-pin carriers).
All MAX 5000 and MAX 7000 QFP devices with 100 or more pins are
shipped from the factory in carriers, thus eliminating the need to handle
the delicate device leads. The carriers are packaged either in anti-static
rails or strip packs. Devices can be programmed and erased while in the
carrier. EPROM-based QFP devices are erased with a UV lamp; EEPROMbased QFP devices are erased in the programming adapter. Figure 2 shows
the dimensions of the QFP carriers.

QFP devices without protective carriers should be handled with a
vacuum wand at an electrostatically protected workplace to reduce
the possibility of mechanical or electrical device damage.

Figure 2. QFP Carrier Dimensions
Dimensions are shown in millimeters.
1~O-Pin QFP Carrier

160- and 208-Pin QFP Carrier

Pin Count

100

25.2

21.2

4.2

160

33.2

35.2

5.1

208

33.2

35.2

5.1

QFP
Development
Socket

I Page 480

The QFP development socket footprint is compatible with the lead footprint
of the QFP device. It ensures the device's electrical connection to the
printed circuit board and provides excellent AC circuit performance: low
noise, low capacitance, and low inductance. (A device mounted directly on
the printed circuit board will provide better interconnect capacitance and
inductance than a device loaded into the carrier / socket.) See Figure 3.

Altera Corporation

I Data Sheet

QFP Carrier & Development Socket

Figure 3. QFP Development Socket Dimensions
Dimensions are shown
in millimeters.

Board layout

Contact & Lid Detail
OFP

Lid
Carrier
Package
Lead

Contact

Alignment
Post

Pin Count

100

0.20

0.93

25.0

19.0

12.0 31.51

25.54

23.30

17.30 30 Pads @ 0.65 20 Pads @ 0.65

1.0

1.5

160

0.20

0.93 33.8

33.8

12.8 39.60

39.60

32.08

32.08 40 Pads @ 0.65 40 Pads @ 0.65

1.0

1.5

0.20

0.93 33.8

33.8

12.8 39.60

39.60

31.68

1.0

1.5

±0.02 ±0.12 ±0.12 ±0.12 ±OAO ±0.20 ±0.20

±0.12

208
Tolerance

[[l?

31.68 52 Pads @ 0.50 52 Pads @ 0.50
±0.12

±0.03 ±0.12

To ensure correct board layout, pad sizes must be compatible
with the development socket and the QFP device leads.

The development socket withstands the temperatures required by reflow
technology. With the appropriate solder mask, multiple development
sockets can be closely spaced on the board. Three alignment posts ensure
correct orientation and provide sufficient registration for reflow soldering.
When other components must be placed near the development socket, the
designer must ensure that component leads do not conflict with the outline
of the development socket.
Altera Corporation

Page 481

I QFP Carrier & Development Socket

Data Sheet

The QFP carrier is held in the development socket by the socket lid, which
braces the carrier against the electrical contacts in the socket. These contacts
connect the device leads to the development socket, ensuring a positive
electrical connection that is not susceptible to mechanical interruption
caused by jarring or impulsive shocks. The carrier design ensures that the
pressure of the socket contacts does not significantly affect the coplanarity
of the device leads. This carrier / socket combination allows the designer to
perform mechanical analysis during the functional prototyping cycle.
Altera also provides a tool to extract the QFP device from the carrier.
Although it is possible to extract a QFP device from the carrier without the
tool, Altera recommends using the tool for QFP devices with 160 or more
pins. Two extraction tools are available: one for 100-pin QFPs and one for
160- and 20B-pin QFPs. See "Extracting a Device with the Extraction Tool"
later in this data sheet for complete details.

Step-by-Step
Instructions

The following step-by-step instructions describe how to:
1.

2.
3.
4.
5.
6.

Insert the QFP carrier into the development socket
Remove the QFP carrier from the development socket
Program a device in the QFP carrier
Extract a device from the QFP carrier
Extract a device from the QFP carrier with the extraction tool
Insert a device into the QFP carrier

IV?

The device should be removed from the QFP carrier only after it
has been programmed and is ready to be soldered onto the board.

Inserting the QFP Carrier into the Development Socket
To insert the QFP carrier into the development socket:
1.

I Page 482

Align the QFP carrier on the development socket by matching the
beveled comer of the carrier to the beveled corner of the socket and
aligning the alignment dots.
Place the socket lid over the socket and press down firmly on all four
corners of the lid. Clicking sounds will be clearly audible. See Figure 4.

Altera Corporation I

QFP Carrier & Development Socket

Data Sheet

Figure 4. Inserting the QFP Carrier into the Development Socket

Removing the QFP Carrier from the Development Socket
To remove the QFP carrier from the development socket:
1.

2.
3.
4.

Place the removal tool over the QFP socket lid, as shown in Figure 5.
Gently press down, making sure that the edges of the tool fit into the
slots on the top of the lid. Clicking sounds will be clearly audible.
While maintaining pressure, lift the lid and removal tool together.
Remove the carrier.

Figure 5. Removing the QFP Carrier from the Development Socket
160- and 208-Pin Carrier

100-Pin Carrier

---Altera Corporation

Page 4831

QFP Carrier & Development Socket

Data Sheet

Programming a Device in the OFP Carrier
QFP devices that are shipped in the protective QFP carriers are ready to be
programmed with the Altera Master Programming Unit (MPU) and the
appropriate PLMQ-type programming adapter. With Altera programming
software and hardware, test vectors can be directly applied to the device
for programming verification and functional testing. Devices in QFP
packages can also be programmed with industry-standard programming
hardware from other manufacturers (e.g., Data I/O).
To program a device in the QFP carrier:
1.

Place the QFP carrier with the device into the programming adapter,
making sure that carrier and adapter are aligned correctly.
Close the retaining latch by pressing the latch against the socket.
A clicking sound is clearly audible as the latch fastens over the socket.

lG?

The retaining latch on the clamshell-style programming adapter
socket ensures good electrical contact between the device leads
and the socket. The retaining latch must be shut after the QFP
carrier is placed into the programming adapter; otherwise,
programming problems may occur.

Extracting a Device from the QFP Carrier
Altera recommends using the extraction tool to extract QFP devices with
more than 160 pins from the QFP carriers. To extract a device from the QFP
carrier:
1.
2.

Place the QFP carrier against a flat surface.
Without applying pressure, hold down the device with the blunt end
of a pencil or another similar tooL
Bend up the yellow retaining clips located on diagonal corners of the
QFP carrier. See Figure 6.

Figure 6. Bending the
Retaining Clips to Extract
the QFP Device from the
QFP Carrier

I Page 484

Altera Corporation

Data Sheet

QFP Carrier & Development Socket

Lift the QFP carrier straight up. See Figure 7.

Figure 7. Lifting the QFP Carrier to Extract the QFP Device

Extracting a Device from the QFP Carrier with the Extraction Tool
The QFP carrier extraction tool has a floating platform set into the base of
the tool. The QFP device rests on this platform. The lever is connected to a
shaft whose head pushes the device out of the carrier. The shaft is mounted
on a vertical support that can be rotated to permit easy insertion and
removal of the device. The shaft mount incorporates a carrier holder that
secures the carrier after it has been extracted from the QFP device. See
Figure 8.
To extract a QFP device from the carrier:
1.

2.
3.

5.
6.
7.
8.

Altera Corporation

Place the tool on a flat surface with the lever facing you.
Rotate the vertical support so that it does not block access to the device
platform.
Place the QFP device in the carrier on the floating platform (the Altera
logo on the carrier should be located in the upper right hand corner).
The carrier will not fit into the tool if it is inserted improperly.
Rotate the vertical support back over the QFP until the shaft head is
positioned directly over the QFP in the carrier. A click is clearly
audible.
Press down the lever so that the shaft head pushes the QFP out of the
carrier. Keep the lever down.
Pull the carrier straight up until it snaps onto the black plastic carrier
holder.
Pull the lever up to disengage the shaft head from the QFP device.
Rotate the vertical support away from the base.

Page 4851

I OFP Carrier & Development Socket
9.

Data Sheet

With a vacuum wand or another handling device, pick up the device.

Do not handle the device with your fingers to avoid damage to the leads.

A QFP device should not be re-inserted into the QFP carrier with
the extraction tool.

Figure 8. Extracting the QFP Device from the Carrier with the Extraction Tool

Q
Vertical Support

Lever

Floating Platform

Inserting a Device into the QFP Carrier
To insert a QFP device into the QFP carrier:
1.
2.
3.

I Page 486

Hold the carrier bottom side up.
With thumb and forefinger, bend the yellow retaining clips outward.
Place the device into the carrier so that the device leads fit into the
molded channels. The beveled comer of the device must be aligned
with the beveled corner of the QFP carrier. When the device is securely
seated in the carrier, the clips will snap back over the comers of the
device and hold it in place.

Altera Corporation I

QFP Carrier & Development Socket

Data Sheet

The yellow plastic clips hold the device securely in place without hindering
access to the leads. The open carrier top allows the EPROM-based QFP
device to be placed under a UV lamp for device erasure.
[l?

Ordering
Information

Altera Corporation

Altera recommends that the QFP device not be re-inserted into
the QFP carrier once it has been removed.

QFP carriers and development sockets are rated from -65 0 C to 155 0 C, and
are qualified to handle commercial, industrial, and military operating
temperatures. For up-to-date information on available QFP carriers and
development sockets, refer to Ordering Information in this data book.

Page 4871

Notes:

Altera Device
Package Outlines
I August 1993, ver. 4

Introduction

Data Sheet I

This data sheet provides package outlines for all Altera devices. Table 1
shows the type of packages, lead materials, and lead finishes available.

Table 1. Altera Device Packages
Package
Code

Lead
Material

Ceramic dual in-line

Alloy 42

Plastic dual in-line

Copper

Solder dip (60/40)

Ceramic J-Iead

Alloy 42

Solder dip (60/40)

Package Type

Lead Finish
Solder dip

Plastic J-Iead

Copper

Solder plate (60/40)

Ceramic pin-grid array

Alloy 42

Gold over nickel plate

Plastic small-outline IC

Copper

Solder plate (80/20)

Ceramic quad flat pack

Alloy 42

Matte tin plate
Solder plate (80/20)

Plastic quad flat pack

Copper

Metal quad flat pack

Copper

Solder plate (80/20)

Plastic thin quad flat pack

Copper

Solder plate (80/20)

Power quad flat pack

Copper

Solder plate (80/20)

Package outlines are listed here in ascending pin count order. Maximum
lead coplanarity is 0.004 in. (0.10 mm). For information on device package
ordering codes, see Ordering Information in this data book. Package outline
dimensions are shown in the following formats:

min. inches (min. millimeters)
max. inches (max. millimeters)
or:

nominal inches ± tolerance
(nominal millimeters ± tolerance)
or:

inches
-----BSC, Min., Max., Ref.
( millimeters)
I Altera Corporation

Page 489

Altera Device Package Outlines

Data Sheet

20-Pin Plastic Dual In-Line Package (PDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.
0.300 (7.62)
0.325 (S.26)

tJ
"

_I~
0.027 (0.69)
0.37 (0.94)

0.24 (6.10)
0.26 (6.60)

0.130
0.360 (9.14)

~ BSC

~O~·~:.J(1~::4) ~

(3.30) 0.170

~)M~

7°4 Pies
Base plane
Seating
plane

~lll ~:~::~~::~l

0.065(1.65)

Pin 1

0.016 (0.020)
0.41 (0.51)

O.OOS (0.20)
0.012 (0.30)

0!125 (3.1S)

-I

0°_15°

\.-'

\
0.300 BSC
(7.62)

0.135 (3.43)

20-Pin Ceramic Dual In-Line Package (CerDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STO-1835.
Window

11 TO.290 ± 0.010

m-r"T"T"~""T'T"""'T""'T'"T"'T"T"'T"'1mO _(7.37 ± 0.25)
-.J

~ L O.OSO

0.950 ± 0.01 0 --=~r
(24.13 ± 0.25)

Max

(2.03)

•

J------I

0.200 Max.
(5.0S)
0.025 ± 0.010
(0.64 ± 0.25)

~ -I~

0.100 BSC
(2.54)

Page 490

m
~.7::':.~~~,
~I +

~MMRMM~~:;:;:::;;::::;:::::;;;Il

UII~ L.

0.01S ± 0.002
(3.1S)
(0.46 ± 0.05) 0.05S ± 0.007
(1.47 ± 0.1S)

MI ".

0.305 ± 0.015

15 -0

-L

(0.25 ± 0.05)

0.3S0±0.015
(9.65 ± 0.3S)

Altera Corporation

I Data Sheet

Altera Device Package Outlines

20-Pin Plastic Dual In-Line Package (PDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.
0.045 (1.14)

0.020 Min.

_11_

o.o~(1 ~:::: ~~:]I ::~~:::::
~

Pin 1

1.025(26.02) _
1.035 (26.28)
0.125 (3.18)
0.135 (3.43)

\---------~I

0.140(3.56)
0.170 (4.32)
(0.51) 1yp.

_+--.1
t

-110.100 esc
(2.54)

-110.016 (0.40)
0.020 (0.51)

0.295 (7.49)

I ,.-=---\ I 0.325 (8.26)

~ 0.020

trBi

~L
-\1-

0.125 (3.18)
0.135 (3.43)

0.008 (0.20)
0.012 (0.30)

0.310 (7.87)
0.330 (8.38)

20-Pin Plastic J-Lead Chip Carrier (PLCC)

See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

~;~~X45.'O

O.~(1.0~ T
0.048 (1.22)

0.032 (0.81)

0.356 (9.04) q.

_ 0.385 (9.78) S . _
0.395 (10.03) q

_11_

0.050 esc
(1.27)

/' 0.013 (0.33)
0.290 (7.37)

0.021 (0.53)

0.026 (0.66)

1_0.350 (8.89)s

See
Delail

~ ~ /

/Pin1

0.320 (8.13)

=-~~~t'----~~-L*

LI
-I

0.090 (2.29)
0.120 (3.04)
0.165 (4.19)
0.180 (4.57)

0.020 Min.
(0.51)

0.025 (0.64)
0.04 (1.14) R

Detail A

Altera Corporation

Page 491

Altera Device Package Outlines

Data Sheet I

20-Pin Plastic Small-Outline Integrated Circuit (SOIC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.
_

0.496 (12.59)
0.512 (13.00)

0.291~

0.299 (7.59)

~~·nT~~~~Tn~

0.394 (10.0)
- - 0.419(10.64) ---+

Pin 1

_~_ 50 Typ.

0.013
x 450 -I (0.33)

0.093 (2.36)
0.104 (2.64)

In'Ti;t:~=-==~

......n-n-n-n-n-n-n-n-n~rt. 1

:1 L~ ~

:IL~ ~
0.013 (0.33)
0.020 (0.51)

0.050 T
(1.27) yp.

:.001(0.10)

0.016 (0.41)
0.050 (1.27)

0.012 (0.30)

24-Pin Ceramic Dual In-Line Package (CerDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.
Window

1 3 } 0.295 ± 0.015
12
(7.49 ± 0.38)
~~~~~~~~~~

0.005.
I~ U U L
(0.13) MIn.-~

0.028 ± 0.013

(o.nr~)

_1_

1.26±0.02 _ _
(32.00 ± 0.51)

mMMMmi

0.200
(5.08) Max.

I I-

0.100
BSC(2.54)

-110.018 ± 0.003
(0.46 ± 0.08)

i----I 0.305 ± 0.015
1,,-,-, I (7.75±0.38)

-0.125 Mi n.
(3.18)

_LfrS-~;
__.

.. _15

0.057 ± 0.008
-

Page 492

0.090 Max
(2.29)
.

'1_

0.012 ± 0.004
(0.30 ± 0.10)

0.380 ±0.015
(9.65 ± 0.38)

(1.45 ± 0.20)

Altera Corporation

I Data Sheet

Altera Device Package Outlines

24-Pin Plastic Oualln-Line Package (POIP)

-I r

See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

-11-

.J;:: :~:(1:0: :(:::] ::::~~::
Pm 1

0.045 (1.14)

0.020 Min

l-r

1.240 (31.48)
1.255 (31.88)

•

r------.

0.140 (5.51)
0.170 (4.32)

~ 0.020 Min.
0.125(3.18) L~'--------------'
(0.51)
0.145 (3.68)
__ ~

0.020 .'n. _

(0.51)

-Il-

(2.54)

0.295 (7.49)
0.325 (8.26)

~-~-

~ -;.'~SC

,.-=---\

:~:::::~: o.,~t(3.18:

0.135 (3.43)

0.008 (0.20)
0.012 (0.30)

0.310 (7.87)
0.330 (8.38)

24-Pin Plastic Small-Outline Integrated Circuit (SOIC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

r-----

0.599(15.21)

Q Q Q Q 0.614 (15.59)

0.394 (10.00)
- - 0.419 (10.64) - -

_~~;50 Typ.

0.093 (2~~
0.104 (2.64)

~~n-~n-~n-~n-~n-~n-~n-~n-~n-~n-~n---'JL~ 1

0.013 (0.33)
0.020 (0.51)

_11_

0.004 (0.10)
0.012 (0.30)
_

I Altera Corporation

~~~;~ x 45'

10° Typ.

-11-

~--------J\

-IJJI

.
0.016 (0.41)
0.50 (1.27)

- ~ --=::! 0° - 8° Typ.
t

0.050 Typ.
(1.27)

Page 493

Data Sheet

Altera Device Package Outlines

28-Pin Ceramic Oualln-Line Package (CerOIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

r~::~~ E§ ::::::11 ~~~::::
0.005.
(0.13) Mm. -

-11-

1.450 ± 0.010
(36.83 ± 0.25)

•

0.090 Max
(3.54)
.

0.200 Max
(5.08)
.

0.025 ± 0.010

(O'Mr~)~~
0.100 BSC _
(2.54)

I I_

I-

0.305 ± 0.015
(7.75 ± 0.38)

iOO\-~-

0.010 ± 0.002
(0.25 ± 0.05)

0.018 ± 0.002
(0.46 ± 0.05)

0.125 Min.
(3.18)
0.057 ± 0.008
(1.45 ± 0.20)

W-,50LI

0.380 ± 0.015
(9.65 ± 0.38)

28-Pin Plastic Oualln-Line Package (POIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

_11_ ~
0.045 (1.14)

0.020

(0,51) Mm.

-11-

::~::s~~\::::::::::::
:11 :::~::::
pm1~1
t
1.345 (34.16)
1.355 (34.42)

•

0.140 (3.56)
0.170 (4.32)
~

0.125(3.18)
0.145(3.68)

0.020 Typ.

t ~r---------------'
(0.51)
~
_ _ +~

f
0.020 Min._I
(0.51)

1_ I I
-

Page 494

0.100
(2.54) BSC

_I~

0.016 (0.41)
0.020 (0.51)

t
t

0.125 (3.18)
0.135 (3.43)

_I
I~

0.295 (7.49)
0.325 (8.26)

-~
,I

0.008(0.2}
0.012 (0.3)

0.310 (7.87)
0.330 (8.38)

Altera Corporation

I Data Sheet

Altera Device Package Outlines

28-Pin Plastic Small-Outline Integrated Circuit (SOIC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

r-----~
I

0.697 (17.70)

[d [d [d [d

0.713 (18.11)

~~ ~:=:J~ ::::::::::::)

0.394 (10.0)
- - 0.419 (10.64) 0.013 x 45 0
(0.33)

Pin 1

50 Typ.

0.093 (2.36)
0.104(2.64)

;

10 TyP·------W-

~(-----\)'W 00~80Typ.

nn n n n n n n n n n n n n H~
~ 0~1~0.;) ~-ll-~ ~ ~ ~I ~ ~ ~
0.020 (0.51)

_11:t

0.016 (0.41)
0.050 (1.27)

:004 (0.10)
0.012 (0.30)

0.050 Typ.(1.27)

_11_

28-Pin Ceramic J-Lead Chip Carrier (JLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in Altera Military Product Drawing 02D-00194.
See

Detail

0.045 x 450
(1.14)

/~ -/

Pin 1 \

\/,D.DJ::u+J.DJ:::u:::J/lr/~ Window
0.026 (0.66)
0.032 (0.81)

- ~ J[----+++-

0.390 (9.91)
0.430 (10.92)
0.017 (0.43)
0.043 (0.58)

_ _t

~--

--t
0.050 BSC
(1.27)
0.442 (11.23) S . ______
0.458 (11.63) q

0.485 (12.32) S . _____
0.495 (12.58) q

0
0.035 X; j
_5
(0.89)
~

"--.1-

0.006 (0.15)
0.10 (0.25)

0.020 R Min.
.------,---...../ (0.51)

0.030 (0.762)
- - 0.040 (1.02)
0.090 (2.29)
0.120 (3.05)
0.155 (3.94)
0.180 (4.57)

0.008
(0.20)

Detail A

I Altera Corporation

Page 495

I Altera Device Package Outlines

Data Sheet

28-Pin Plastic J-Lead Chip Carrier (PLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

x 45°

0.045
(1.14)

Pin 1
0.050
(1.27)

0.390 (9.91)
0.430 (10.92)

b
I

Bse

-t

0.300 Ref.
(7.62)

-~
s

0.450 (11.43)

I-- 0.456 (11.58)

.-1

0.026 (0.66)
0.032 (0.81)

0.485 (12.32) S
0.495 (12.57) q.-+

0.020 Min.
(0.51)

-I
I

0.020
(0.51)
0.090 (2.29)
0.120 (3.05)

0.165 (4.19)
0.180 (4.57)

"'------- 0.025 (0.64) R
0.04 (1.14)

Detail A

28-Pin Plastic Small-Outline Integrated Circuit (SOIC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

'
I

0.697 (17.70)
0.713 (18.11)

: :~ : J~ : : : : : : : : : : : : )

0.394 (10.0)
- - 0.419 (10.64) - +

Pm1

50 Typ.

0.013 x 45
(0.33)
0.093 (2.36)
0.104 (2.64)

Qn n n n n n n n n n n n n H~
~ 0~1~0.;) ~_I~~ ~ ~ ~I ~I ~ ~
0.020 (0.51)

0.012 (0.30)
0.050 Typ.(1.27)

Page 496

:004t(0.10)

_11_

10° TYP'_I / -

lJ(--------) \\J ~
0°

0.016 (0.41)
0.050 (1.27)

8° Typ.

-11:t

Altera Corporation

Altera Device Package Outlines

Data Sheet

40-Pin Ceramic Dual In-Line Package (CerDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.

0.090 Max.
(2.29)

[::: :':~:~::::::: :J~::I~:

_11_
0.005 Min.
•
(0.13)

•

2.050 ± 0.020
(52.07 ± 0.51)

0.225 M

~~~:::~~ ~T
0.:"

(2.54)

esc

I
I-

O.057±M08
(1.45 ± 0.20)

0.018 ± 0.002
(0.46 ± 0.05) - -

0.610 ± 0.010
(15.49 ± 0.25)

0.125

MI •.

(3.18)

-I

~l-~

00_150_~1_ 0.660
I

0.010±0.002
(0.25 ± 0.05)

± 0.020 __

(16.76 ± 0.51)

40-Pin Plastic Dual In-Line Package (PDIP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

--I III

0.045 (1.14)
0.055 (1.40)

0.020 Min.
(0.51)

11-

.l~~~~~~~~~~~~~~~~~~] :~i: :.:

Pml

I_ - - - - •

0.145 (3.68)
0.155 (3.94)

2.058 (52.27) _ _ _ _ _ __.1
2.070 (52.58)
• 0.165 (4.19)
0.175 (4.45)

~J~~-~r
0.020 Min.
(0.51)

I Altera Corporation

0.100
(2.54)

esc

I.-

0.1213.05)
0.13 (3.30)
0.016 (0.41)
0.020 (0.51 )

rr
I

0.020 Typ.

0.595 (15.11)
0.60' (15.3~

--I
\

0.008 (0.2)
0.012 (0.3) -- . -

L J
0.610(15.49)
0.640 (16.26)

Page 497

I Altera Device Package Outlines

Data Sheet

44-Pin Ceramic J-Lead Chip Carrier (JLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.
0.045 x 450
(1.14)

Pin 1 \

/WindOW

--+-tt-----+J(

0.026 (0.66)
0.032 (0.81)

~3----

0.590 (15.0)
0.630 (16.0)
----E;;;=t--

0.017 (0.43)
0.023 (0.58)

-t
1_0.642(16.3) S
0.658 (16.7) q.

_ _ _ 0.685 (17.4) S q . 0.695 (17.7)

:l-1--I r

0.035 X45
(0.089)
-

_I I-

0.030 (0.762)
0.040 (1.02)

0.050 BSC
(1.27)

0.006 (0.15)
0.01 0 (0.25)
0.020
(0.51) R Min.

0.90 (2.29)
0.120 (3.05)

0.155 (3.94)
0.180 (4.57)

Detail A

Page 498

Altera Corporation

I Data Sheet

Altera Device Package Outlines

44-Pin Plastic J-Lead Chip Carrier (PLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

0.045 x 450
(1.14)

Pin 1

,.r::L.D.I:J.DJ~iD..c:J.D.DCL....,
Y
0

- - - -

0.500
(12.7)

See
Detail
A

Ref.-I

-I
"

-;------,

-t0.042 (1.07)
0.048 (1.22)

0.590 (14.98)
0.630 (16.0)
0.013 (0.33)
0.021 (0.53)

-t

1___

0.650(16.51) S
0.656 (16.66) q

.-1

0.050
(1.27)

Bsc-I

0.025 Min.
(0.64)
0.09 (2.29)
0.120 (3.05)

_ _ 0.685 (17.39) Sq _
.
0.695 (17.65)
__ 0.020 Min.
(0.508)

0.165 (4.19)
- - 0.180 (4.57)

0.025 (0.64) R
0.045 (1.14)

Detail A

I Altera Corporation

Page 499

I Altera Device Package Outlines

Data Sheet

44-Pin Plastic Quad Flat Pack (PQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.on(1.95)

0.083 (2.10)
+-

0.012 (0.30)
0.18 (0.45)

esc

0.096 Max.
(2.45)

'..... See

Detail
A

~
~

r
0.031
(0.80)

0.510 (12.95) S
1 - - - - - 0.530 (13.45) q.

esc

0.006 ± 0.001 --+
(0.165 ± 0.035)

· CB-~

-i/-oo _7

0.031 ± 0.007
(0.80 ± 0.15)

0.063 ± 0.008
(1.6±0.2)

II-

0.25
(0.010) Min.

Detail A

Page 500

Altera Corporation

I Data Sheet

Altera Device Package Outlines

44-Pin Thin Plastic Quad Flat Pack (TQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
.0--

0.002 (0.05)
0.006 (0.15) Min .

.o--~

Pin 1

(1.27)

0.012 (0.30)
0.18 (0.45) BSC

-+
~

Max.

,"'--.. See
Detail
A

-+
t
0.31
(0.80) BSC

1_ (:~~:)BSCSq. ~~
0.472
(12.00) BSC Sq.

0.003 (0.09)
0.008 (0.20) -- - -

0.039 Ref.
(1.00)

_~__

:0 _

7°

~0'45)
0.295 (0.75)

Detail A

I Altera Corporation

Page 501

I Altera Device Package Outlines

Data Sheet I

68-Pin Ceramic J-Lead Chip Carrier (JLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For militaryqualified product, see case outline C-J2 in Appendix Cof MIL -M-3851 o.
0.045
(1143) x 45°

See
Detail

Window

Pin 1 \

/
/

0.985 (25.02)
0.995 25.27 Sq.

0.026 (0.66)
0.032 (0.81)

--+
0.890 (22.61)
0.930 (23.62)

0.942 (23.93) S
0.958 (24.33) q.

_ (

rl(
/.

--.

I I--

0.050
(1.27)

esc

0.006 (0.15)
0.010 (0.25)

0.030 (0.762)
0.040 (1.02)
0.090 (2.29)
0.120 (3.05)
0.155 (3.94)
0.200 (5.08)

0.020
(0.508) R Min.

0.008
(0.203)

Detail A

Page 502

Altera Corporation

I Data Sheet

Altera Device Package Outlines

6B-Pin Plastic J-Lead Chip Carrier (PLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.
0.042 (1.07)
0.056 (1.42)

See
Detail

0.042 (1.07)
0.048 (1.22)

0.045 x45 0
(1.143)

0.800 Ref.
(20.32)

Pln1\

l,...o.o.D.DD.D.DD.oQooD.D.D.DD.DL......,

A
/

~ ~

-+--------0----

0.026 (0.66)
0.032 (0.81)

t
0.890 (22.61)
0.930 (23.62)

0.013 (0.33)
0.021 (0.53)

I·

::: !:::::: ..

JDOD

I.- (1.27)
0.050 BSC

1 _ - - - - 0.985 (25.00) Sq.

0.995 (25.27)
0.020
.
(0.508) Mm.

___

0.020 Min.
(0.51)

0.090 (2.29)
0.130 (3.3)
0.165 (4.19)
0.200 (5.08)

0.025 (0.64) R
0.045 (1.14)

Detail A

I Altera Corporation

Page 503

I Altera Device Package Outlines

Data Sheet

68-Pin Small Outline Ceramic Pin-Grid Array (PGA)

See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in Altera Military Product Drawing 020-00205.
1.005 ± 0.005
(25.53 ± 0.13)
-

~;.~;: ~:~~~

111 - r

0.085 ± 0.010

(~5.37±~.13) Sq . . -

(2.16±O~5)

0.180 ± 0.005
(4.57 ± 0.13)

0.005
R
(0.13)

__
t
--t

0.605 ± 0.005
(15.37 ± 0.13)

0.018 ± 0.002
(0.46 ± 0.05)

-r

H
G

0.070
(1.78) Ola. Typ.
0.008 R f.
(0.20) e

Window

0.050 ± 0.005
(1.27 ± 0.13)

0.050
(1.27) Ola.

68-Pin Large Outline Ceramic Pin-Grid Array (PGA)

See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.
1.005 ± 0.005

_1.160±0.020Sq. ,

0.730 Max. Sq.

0.127±0.013
(3.23 ± 0.33)

I ':

H
G
F

o,r----+-----{

@@
o @@
C @@
B @(@@@@
A
@@@@
E

@
Window

0.180 ± 0.005
(4.57 ± 0.13)

2 3 4 5

°
0

@@
@@
@@
@@@(@@
@@@@

6 7 8 9 10 11

0.730 Max.

"""

0.005
R
(0.13)

0.018 ± 0.002
(0.46 ± 0.05)

__
t

--t

"
_ _ I]

0.070 , T
(1.78) 0 la. yp.

o.ooa R f.~_

(0.20) e

0.050
(1.27) Oia.

0.050 ± 0.005
(1.27 ± 0.13)

Page 504

Altera Corporation

1Data Sheet

Altera Device Package Outlines

84-Pin Ceramic J-Lead Chip Carrier (JLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.
0.045
(1.143)

x 45

,;Pinl

5ee

~Ref.-I
(25.4)

Window

Detail
./
/

1.185 (30.10) 5
1.195 (30.35) q.

"+---------.-t
1.090 (27.69)
1.130 (28.70)

~ti-------+--------tliffi--

1.142(29.01)5
1.158 (29.41) q.

0.26 (0.66)
0.32 (0.81)

rl{
I·

_I
.

0.006 (0.15)
0.010 (0.25)

. . " x45"(0.889)

_11_

11_ (1.27)
0.050

0.030 (0.762)
0.040 (1.02)

0.090 (2.29)
0.120 (3.05)

0.155 (3.94)
0.200 (5.08)

B5C

W(~:~~~)RMin.

0.008
(0.203)

Detail A

Altera Corporation

Page 505

I Altera Device Package Outlines

Data Sheet

84-Pin Plastic J-Lead Chip Carrier (PLCC)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

0.042 (1.07)
0.056 (1.42)

0.045

(1.143) x 45°

0.042

Pin 1

M48

(1~7)
(1.22)

rrmnnrmn'"T1lJ[f"llJJ""!urrurnrrnrrnrm,rmrrnrrnn"1lITllln1mlrmrm

lJjt~~~~~~~

1 ,I- _(0":"
See

1.090 (27.69)
1.130 (28.70)

t
~

:;,=t=:: ~C= T

t??

1.150(29.20)
1.158 (29.41)

U"""I

0.026 (0,66):
0.032 (0.81)

0.013 (0.33)
0.021 (0.53)

0.20 Min.
(0.51)

0.090 (2.29)
0.130 (3.30)

1.185 (30.09) S
1.195 (30.35) q.

0.008
(0.203) Max.

-1'-

0.165 (4.19)
0.200 (5.08)

O.020 .
(0.51) Mm.

0.025 (0.64) R Mi
0.045 (1.14)
n.

Detail A

Page 506

Altera Corporation

I Data Sheet

Altera Device Package Outlines

84-Pin Small Outline Ceramic Pin-Grid Array (PGA)

See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.

1.100 ± 0.020 S.
(27.94 ± 0.51) q
0710 +0 005
(; 8.03-± ~.13) Sq.

1.005 ± 0.005
(25.53 ± 0.13)

0.127±0.013
(3.23 ± 0.33)

0.085 ± 0.010
(2.16 ± 0.25)

'----- 0.005 R
(0.13)

Err

Window

0.180±0.005
(4.57 ± 0.13)

J
H
G

0.018 ± 0.002
(0.46 ± 0.05)

0.710 ± 0.005

--t

(l&

0.070 Oia. Typ.
(1.78)

0
1

2 3

4 5

6 7 8 9 10 11
0.050 ± 0.005
(1.27± 0.13)

~-:RM
(0.20)

84-Pin Large Outline Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-1835.
1.160 ± 0.020 Sq.

1.005 ± 0.005
(25.53 ± 0.13)

0.127±0.013 - .
(3.23 ± 0.33)

0.830 Max. Sq. - -

-1

Wmdow

(4.57 ± 0.13)

F~**~~~+-~~~~r

0.830 Max.

0.005 R
(0.13)

----.l

---+7-----F~E-=----=----=-----=:=t0-

0.070 Oia. Typ.
(1.78)

0
1
A1

2 3

4 5

6 7 8 9 10 11
0.050 ± 0.005
(1.27 ± 0.13)

I Altera Corporation

0.180 ± 0.005

0.018 ± 0.002
(0.46 ± 0.05)

>LJ

(

~II

-t

0.008
__ O l a. .
(0.20)

Page 507

I Altera Device Package Outlines

Data Sheet

100-Pin Small Outline Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-t835.
1.320±0.020 S .~
(33.53 ± 0.51) q

1.200±0.015 _ _~
(30.48 ± 0.30)

0710 + 0 005

(~8.03~ ~.13)

[

0.128 ± 0.012
(3.24 ± 0.32)
0.085 ± 0.010

Sq.

(2.16 ± 0.25)

0.180 ± 0.005

(4.57 ± 0.13)

N
M

L
K

" - 0.005 R
(0.13)
0.018 ± 0.002
(0.46 ± 0.05)

E8
I

H
G~~~r---r---~~~

o
C

0.070 Ola. Typ.
(1.79)

I
Window

--.l

0.710 ± 0.005
(18.03 ± 0.13)

1 2 3 4 5

6 7 8 9 10 11 12 13
0.050 ± 0.005
(1.27 ± 0.13)

0.008
_Ref.
(0.21)

100-Pin Large Outline Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches. For military-qualified
product, see case outline in MIL-STD-t835.

·i

1.200±0.015 _ _~

- - - 1.360±0.020Sq

0.128±0.012
(3.24 ± 0.32)

_
I

- - 0.830 Max. S q . - L I

0.180 ± 0.005
(4.57 ± 0.13)

~0.005R

(0.13)
K

--+------------

/
WlndOw/

0.018 ± 0.002
(0.46 ± 0.05)

T;I---+----I---

--.l

G~~~---~--~~~

II
A1

2 3 4 5

--t

@@@
@@
@@

F
E

@@@@@@
@@@@@@

6 7 8 9 10 11 12 13

0.070 Oia. Typ.
(1.79)

0.050 ± 0.005
(1.27 ± 0.13)

0.008 Ref. _ _
(0.21)

I Page 508

Altera Corporation

I Data Sheet

Altera Device Package Outlines

100-Pin Ceramic Quad Flat Pack (CQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.096 ± 0.012
(2.45 ± 0.30)
0.049 ± 0.010
(1.25 ± 0.25)

0.677 ± 0.008
(17.20 ± 0.20

0.016 ± 0.008
- : - - (0.40 ± 0.20)
\

J1-""""'-'!-n

-.L

-t~

\
/____

See
Detail
A

0.012
(0.30)

0.026 BSC

-t- (0.65)
0.756 ± 0.008
(19.20 ± 0.20)

----:===o:===rt--

0.913 ± 0.008
(23.20 ± 0.20)

Window

0.520 ± 0.008 _ _ _ _....
(13.20 ± 0.20)

0.008 ± 0.002
(0.20 ± 0.05)

0.079-,±,-0~.0~0~8
-I/H; -'0
(2.00 ± 0.20) _ _-+t-_ _
~

.-----,-;0'=====1'-,-,

---t
0.023 ± 0.008
(0.58 ± 0.20)

Detail A

I Altera Corporation

Page 509

I Altera Device Package Outlines

Data Sheet

100-Pin Plastic Quad Flat Pack (PQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.134
(3.40) Max.

~_ _ _ _ _ 0.667(16.95) - - - - - - + 1

PI"

0.687(17.44)

0.010
(0.025) Min.

'__ See
Detail
A

--.l 0.009 (0.22)

0.904 (22.95)
0.923 (23.45)

O.015 (0.38)

--.l

0.026

-t- (0.65) Bse

0.783 (19.90)
0.791 (20.10)

1 _ - - - - 0.547 (13.90)
0.555 (14.10)

0.026 (0.65)
0.037 (0.95)

Detail A

Page 510

Altera Corporation I

I Data Sheet

Altera Device Package Outlines

1~O-Pin Thin Plastic Quad Flat Pack (TQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.002 (0.05) M'
0.006 (0.15) In.
0.05
(1.27) Max.

Detail
A

0.019
(0.50)

~escsq.~
~
0.63
(16.00)

esc

-[f- :0 -

0.003 (0.09)
0.008 (0.20)

esc Sq.

0.039
(1.00) Ref.

~0.45)

0.295 (0.75)

Detail A

I Altera Corporation

Page 511

I Altera Device Package Outlines

Data Sheet I

160-Pin Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

1560±020

1";.624 ± 0.51) Sq.

1.400 ± 0.12 - - -....1
(35.56 ± 3.05)

1.250 ± 0.012
(31.75 ± 0.30) Sq. -

1-I
1

0.090 ± 0.010
(2.286 ± 0.25)
I-- 0.180
I
(4.572)

H -ttElHel-tettet---

,P
Indicates location
of Pin A1

0.018 ± 0.002 D'
(0.457 ± 0.05) la.

@@@@
@@@
@@@
@
@@@@
@@@@@@@
@@@@@@@
@@@@@@@l

I Page 512

0.140 ± 0.020
(3.56 ± 0.51)

2 3 4

Orientation
Index

5 6 7

--t

8 9 10 11 12 13 14 15

0.050
(1.27)

0.008
(0.20) Ref.

Altera Corporation

I Data Sheet

Altera Device Package Outlines

160-Pin Plastic Quad Flat Pack (PQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.160
(4.07) Max.

0.015 x 45° Chamfer
, / (0.38)
Typ. (3 Places)

G
"

0.010 .
(0.25) Min.

See ~"
Detail
A

---.l
---t

0.009 (0.22) T
0.15.(0.38) yp.
0.998
(25.35) Ref.

---.l

--t
0.0256
(0.65)

1.098(27.90) S
1.106 (28.10) q.

ssc

1.219 (30.95) S
1.238 (31.45) q.

0.350
(8.89)-

0.700
(17.78)
0.0045
(0.1143)-

0.025 .
(0.635) Min.

0.026 (0.65)
fL------'~ 0.037 (0.95)

~~--------l---------~~

Detail A

0.125 x 0.005
(3.18 x 0.13)

I Altera Corporation

Page 513

I Altera Device Package Outlines

Data Sheet I

192-Pin Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

I---

/
/

Window

1450+0010
(3.68;0:25) -

•

1.760 ± 0.018
(45.15 ± 0.46)

1.600±0.015 _ _ _ _~

0.100

T -- (2.5s) Typ.

(41.03 ± 0.38)

+fe-l-fet-f€»tet---

p
/

Indicates location
of PinAl

Oia. Typ.

@@@@@@@ 0
@@@@@@@@
@@@@@@@@
@@
@@@@
@@@
@@@
@@@@
@@@@

H @@@@
G @@@@
F @@@
E @@@
D @@@@
@@
C@@@@@@@@
B@@@@@@@@
A 0 @@@@@@@
1

0.070

L fiT9)

U 0 @@@@@@@
T @@@@@@@@
R@@@@@@@@
P @@@@
@@
N @@@
M @@@
L @@@@
K @@@@
1

----~

_10.180 ± 0.010
(4.62 ± 0.25)

' \ 0.005 R
(0.128)
0.018 ± 0.002 01
(0.46 ± 0.05)
a.

---.1.
-t

@@@@
@@@@
@@@
@@@
@@
@@@@
@@@@@@@@
@@@@@@@@
@@@@@@@@

J
--

Page 514

0.085 ± 0.004
(2.18±0.10)

----feH<*el--feH-

2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17

Orientation
Index

0.142 ± 0.015
(3.64 ± 0.38)

l-::±0.005
(1.28 ± 0.13)
0.008
(0.21) Ref.

Altera Corporation

I Data Sheet

Altera Device Package Outlines

20B-Pin Ceramic Quad Flat Pack (QFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.127 ± 0.012
(3.22 ± 0.30)

0.05 ± 0.003
(1.27 ± 0.08)

1.204 ± 0.008 S
(30.6 ± 0.2)
q.
1.071±0.01 (Cap)Sq. - - - - - - - - - 1
(27.2 ± 0.25)

0.05± 0.003 _ _ _
(1.27 ± 0'08)~!
See
Detail

Pin 1

0.008
(0.20)

-+
-t

WindOW~

-t
0.02
(0.50)

~T
(12.7)

0.012 T
(0.3) yp.

yp.
0.006 _ 0.009
(0.15 - 0.23)

_II: 5"1-1
t

0.02 ±0.008
(0.5 ±0.2)

Detail A

I Altera Corporation

Page 515

I Altera Device Package Outlines

Data Sheet

20B-Pin Metal Quad Flat Pack (MQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.125 (3.17)
0.195 (3.43) -

1.197 (30.40) S
1.213 (30.80) q.

0.140 (3.55)
0.155 (3.93) -

1.086 (27.59) S
1.094 (27.79) q.

0.014 (0.35) - -__ I
0.021 (0.53)
/...-.!

See ~
Detail
A

0.006 (0.16)
0.011 (0.27)

-t

0.02
(0.50) BSC

0.006 (0.15) T
0.008 (0.20) yp.

--I L

0.014 - 0.021
(0.35 - 0.53)

Detail A

I Page 516

Altera Corporation

I Data Sheet

Altera Device Package Outlines

20B-Pin Power Quad Flat Pack (RQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.160
(4.07) Max--.
0.125 (3.17)
0.144 (3.67) --.
/

0.060
0
(1.52) x 45

0.010 .
(0.25) Mm. - - - - +

~~~~~~~~~~~~~

See
Detail
A

Pin 1

0.007 (0.17)
0.011 (0.27)

~-+--

-t

~-------+-------~
-~

-t
0.020
(0.50)

0.866 (22.0)

Sq. - - - - - - -

esc

0.015 x 45 0 Chamfer
(0.38)
Typ. (3 Places)

1.098 (27.90) S
1.106 (28.10) q.
1.195 (30.35) S
1.215 (30.85) q.

0.016 (0.40)
0.024 (0.60)

Detail A

I Altera Corporation

Page 517

I Altera Device Package Outlines

Data Sheet

232-Pin Ceramic Pin-Grid Array (PGA)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in inches.

1.760 ± 0.018
(44.704±0.457) Sq.

1.450 ± 0.012 S
(36.83 ± 0.30) q . -

-tI

0,,:-::.1,--::-42=-c±,--:::0-"7.00'::7-8
(3.61 ± 0.20)

0.1 00
~)

0.050 ± 0.005
(1.27±0.127)(4X)

~
0.05
./
(1.27) Index
0.100(2.54)

0.090 ± 0.009
(2.286 ± 0.228)

--*--

"'1TT
'cLOo~:~
t

0.010
(0.25) x 45
-+I.
0.050 ± 0.005
(1.27 ± 0.127) :

Ref.

0.180 ± 0.010
(4.572 ± 0.254)

1.600 ± 0.010
1 4 - - - - - (40.64 ± 0.254) Sq.

0.070

/-(1.778) 018. Typ.
-"-1--+-_ _ _ _-+_ ,/_

0.020
0
(0.5) x 45 (4 x)

@@@@@@@o
@@@@@@@@
@@@@@@@@
@@@@ @@@
@@
@@@@
@@@@@
@@@@@
@@@@@

@@@@@
@@@@@
@@@@@
@@@@
@@
o@@@ @@@@
c@@@@@@@@
s@@@@@@@@
H

G
F
E

~@@@@@@@

@@@@@
@@@@@
@@@@@
@@
@@@@
@@@@ @@@
@@@@@@@@
@@@@@@@@
@@@@@@@@

0.070
/ 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 17
(1.778) Index

Page 518

Altera Corporation

I Data Sheet

Altera Device Package Outlines I

240-Pin Metal Quad Flat Pack (MQFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.135 (3.43)
0.155 (3.93)

0.007 (0.18)
0.010 (0.27)

-t

1.244 (31.60)
1.248 (31.70)

1.354 (34.40)
1.370 (34.80)

I~~~~~~~~~~~~~~~~~~~~ ~ 1:
q.

•

0.005(0.13) T
0.007 (0.18) yp.

•
q.

00_70_~

~'8(0.45)
~

0.30(0.75)

Detail A

I Altera Corporation

Page 5191

I Altera Device Package Outlines

Data Sheet

240-Pin Power Quad Flat Pack (ROFP)
See "Introduction" in this data sheet for dimension formats. Controlling measurement is in millimeters.
0.165
(4.20) Max. - 0.130 (3.30)
0.138 (3.50) - 0.010
(0.25) Min. ------:=---.1

Pin 1

,------------+------------,

liiiiiiiiiiiiiiiliBiiiii (')~
0.984 (25.0) Sq.
1.256 (31.90) S
1.264 (32.10) q.
1.352 (34.35) S

1.372 (34.85)

0.015 x 45° Chamfer
(0.38)
Typ. (3 Places)

1-1""-"

0.025 Min.

0.016 (0.40)
0.024 (0.60)

Detail A

I Page 520

Altera Corporation

Ordering Information
I August 1993, ver. 6

Altera Devices

Figure 1 explains the ordering codes for Altera devices. Since many devices
are available with different pin counts for the same package type, many of
the the ordering codes include pin count. Some devices use relative numbers
(e.g.,-l,-2) to designate speed grades, while others use actual propagation
delay times (e.g., -15, -20). For information on specific package, speed
grade, and operating temperature combinations, refer to individual device
data sheets in this data book, or contact Altera Marketing at (408) 894-7000.

Figure 1. Device Package Ordering Codes
EPM 7032 L C 44 -7
Family Signature:
EP:
Classic device
EPM: MAX 5000 or MAX 7000 device
EPF: FLEX 8000 device
EPC: Configuration EPROM device
EPS: EPS464 or SAM device
EPB: Micro Channel device

Device Type:
EP:
330,610, 610A, 910, 910A, 1810
EPM: 5016, 5032, 5064, 5128, 5128A, 5130,5192,
5192A, 7032, 7032~ 7064, 7096, 7128, 7160,
7192,7256
EPF: 8282,8282~8452,8820, 81188,81500
EPC: 1064,1213
EPS: 448, 464
EPB: 2001

Package Type: - - - - - - - - - - - - - '
D:
Ceramic dual in-line package (CerDIP)
P:
Plastic dual in-line package (PDIP)
J:
Ceramic J-Iead chip carrier (JLCC)
L:
Plastic J-Iead chip carrier (PLCC)
G:
Ceramic pin-grid array (PGA)
B:
Ball-grid array (BGA)
S:
Plastic small-outline integrated circuit (SOIC)
W:
Ceramic quad flat pack (CQFP), Note (1)
M:
Metal quad flat pack (MQFP), Note (1)
Q:
Plastic quad flat pack (PQFP), Note (1)
T:
Thin plastic quad flat pack (TQFP), Note (1)
R:
Power quad flat pack (RQFP), Note (1)

I L

Speed Grade:
See individual data sheets in this data book for
speed/product relationships (e.g., ·2, -15T, or blank).
Pin Count:
Number of pins for devices with different pin-count
options (MAX 7000, FLEX 8000, and Configuration
EPROM devices only).

L -_ _ _

Operating Temperature/Military Processing:
C:
Commercial temperature (0° C to 70° C)
I:
Industrial temperature (-40° C to 85° C)
M:
Military temperature (-55° C to 125° C)
M883B
Processed to MIL-STD·883, current revision
M883BX: Processed to MIL-STD-883, current revision
with modified J-Iead package dimension
MB:
Fully compliant with deviation to
MIL-STD-883, current revision (consult A/tera
for specific deviations)
DESC Standard Military Drawing (SMD)
5962:
Examples:
EPF81188GC232-3

EPM5130GM8838

EPF81188 in a ceramic 232-pin
PGA package, commercial
temperature range, -3 speed grade
EPM5130 in a ceramic 100-pin
PGA package,
MI L-STD-883B-qualified

Note:
(1) MAX 5000 and MAX 7000 devices in QFP packages with 100 or more pins are shipped in QFP carriers. For more
information on QFP carriers, see the QFP Carrier & Development Socket Data Sheet in this data book.

I Altera Corporation

Page 521

I Ordering Information
MIL-STD-883-compliant product specifications are provided in Military
Product Drawings (MPDs) available from Altera Marketing. These MPDs
should be used to prepare Source Control Drawings (SCDs).
Table 1 provides ordering codes for Altera's MAX+PLUS II development
systems and software and lists the Altera devices supported by each
configuration. Refer to the MAX+PLUS II Programmable Logic Development
System & Software Data Sheet for details on each package. To order add-on
products, the base system must be covered by a current software
maintenance agreement.

Development
Tools

Table 1. Altera Development Systems, Software & Device Support
Development System & Software Features
Ordering
Codes

Device Compilation Support (1)

Base
Advanced Workstation Programming FLEX MAX MAX
Design
Design
Design
Hardware
8000 7000 5000
Environment Environment Environment
EPS464
(2)
(3)
(4)

Classic
EPM5016
EPM5032
EPM7032
EPM7032V

MAX+PlUS II Base Systems (PC Platform)
PLS·ES
PLS-STD
PLS-ADV
PLS-FLEX8
PLS-HPS
PLDS-HPS

../
../
../
../
../
../

../

../
../

../

../
../
../
../

MAX+PlUS II Add-On Products (PC Platform)

../

PLSM-5K

../

PLSM-7K

../

PLSM-8K
PLSM-ADE

../

MAX+PLUS II Base Systems (Workstation Platform)
PLS-WS/HP
PLS-WS/SN

../
../

MAX+PLUS II Add-On Products (Workstation Platform)
PLSM-TA (5)

I Page 522

../

Altera Corporation

Ordering Information

Notes to table:
(1)
(2)

(3)

(4)

(5)

Floating Node
Licenses for
Workstations

Device compilation support includes logic synthesis and fitting.
The base design environment includes the following features:
Schematic capture
Text design entry with the Altera Hardware Description Language (AHDL)
Bidirectional EDIF 2 0 0 and EDIF 2 9 0 interface
LPMinput
Hierarchical design management
Automatic error location
Timing analysis
Extensive on-line help
The advanced design environment includes the following additional features:
Waveform design entry and editing
Design-rule checking
Multi-device partitioning within a device family
Functional, timing, and multi-device simulation across device families
Timing analysis across device families
The workstation design environment includes the following features:
Text design entry with AHDL
Bidirectional EDIF 2 0 0 and EDIF 2 9 0 interface
LPMinput
Multi-device partitioning within a device family
Standard CAE interfaces
Extensive on-line help
This add-on product provides timing analysis across device families for
MAX+PLUS II for workstations.

In addition to the base system, users can purchase floating nodes that are
tied to a license manager on a workstation network. These extra nodes can
be obtained by purchasing one or more floating node licenses (see Table 2).
Each floating node includes a unique Altera identification number that is
associated with the original base system purchased. To purchase a floating
node, the original base system must be covered by a current software
maintenance agreement.

Table 2. Floating Node Licenses for Workstations

I Altera Corporation

Product

Ordering Code

PLS-WS/SN

PLSM-WS/SN

PLS-WS/HP

PLSM-WS/HP

Page 5231

I Ordering Information
Software
Maintenance
Agreement

Renewable, one-year software maintenance agreements for development
products provide software and documentation updates for all registered
users of Altera development systems. Table 3 shows the codes for ordering
software maintenance agreements.

Table 3. Software Maintenance Agreement
Product

Programming
Hardware &
Adapters

Ordering Code

PLS-ES

PLAESW-ES

PLS-STD

PLAESW-STD

PLS-ADV

PLAESW-ADV

PLS-FLEX8

PLAESW-FLEX8

PLS-HPS, PLDS-HPS

PLAESW-HPS

PLSM-5K

PLAESW-5K

PLSM-7K

PLAESW-7K

PLSM-8K

PLAESW-8K

PLSM-ADE

PLAESW-ADE

PLS-WS/SN, PLSM-WS/SN,
PLS-WS/HP, PLSM-WS/HP

PLAESW-WS

PLSM-TA

PLAESW-TA

This section provides the ordering codes for Altera programming hardware.
Table 4 lists the ordering codes for the programming card and units. For
complete information on programming hardware and adapters, see the
Altera Programming Hardware Data Sheet in this data book.

Table 4. Programming Hardware
Product

I Page 524

Ordering Code

Description

LP6 Logic
Programmer Card

PLP6

Interfaces with IBM PC-AT or compatible
computer.

LP5 Logic
Programmer Card

PLP5

Interfaces with IBM PS/2 or compatible
Micro Channel computer.

Master Programming
Unit (MPU)

PL-MPU

Programs all Altera devices (with the
appropriate device adapter).

Compatibility Adapter

PLAD3-12

Interfaces PLE- prefix adapters to MPU.
Together with MPU, directly supports
EP330 devices.

Altera Stand-Alone
Programmer

PL-ASAP2

Includes programming software, a Logic
Programmer card, and the MPU.

Altera Corporation

Ordering Information

Table 5 lists the ordering codes for programming adapters. PLAD3-12 and
PLM-prefix programming adapters plug directly into the Master
Programming Unit (MPU). PLM-prefix adapters provide programming
support, device-to-socket continuity testing, and device functional testing
(except for FLEX 8000 and Configuration EPROM devices). PLAD3-12
compatibility adapters allow PLE-prefix adapters, which provide
programming support, to be used with the MPU.
Table 5. Device Adapter Support (Part 1 of 2)

Device

I Altera Corporation

Package

Adapter

EP330

DIP
J-Lead
SOIC

PLAD3-12
PLEJ330
PLES330

EP600/61 0/61 ON61 OT

DIP
J-Iead
SOIC

PLED610
PLEJ610
PLES610

EP900/91 0/91 ON91 OT

DIP
J-Iead

PLED910
PLEJ910

EP1800/181 0/181 OT

J-Iead
PGA

PLMJ1810
PLEG1810

EPB2001

J-Iead

PLEJ2001

EPMS016

DIP
J-Iead
SOIC

PLEDS016
PLEJ5016
PLESS016

EPMS032

DIP
J-Iead
SOIC

PLMDS032
PLMJ5032
PLES5032

EPMS064

J-Iead

PLMJ5064

EPMS128/S128A

J-Iead
PGA

PLMJ5128A
PLMGS128A

EPMS130

J-Iead
PGA
OFP

PLMJ5130
PLEGS130
PLM05130

EPMS192/S192A

J-Iead
PGA
OFP (EPMS192A
only)

PLMJ5192
PLMG5192
PLM05192A

EPM7032, EPM7032V

J-Iead
OFP
TOFP

PLMJ7032-44
PLM07032-44
PLMT7032-44

EPM7064

J-Iead (68-pin)
J-Iead (84-pin)
POFP

PLMJ7000-68
PLMJ7000-84
PLM07000-100

Page s2s1

I Ordering Information
Table 5. Device Adapter Support (Part 2 of 2)
Device

Package

Adapter

EPM7096

J-Iead (68-pin)
J-Iead (84-pin)
OFP

PLMJ7000-68
PLMJ7000-84
PLM07000-100

EPM7128

J-Iead (68-pin)
J-Iead (84-pin)
OFP (100-pin)
OFP (160-pin)

PLMJ7000-68
PLMJ7000-84
PLM07000-100
PLM07128-160

EPM7160

J-Iead
OFP (1 DO-pin)
OFP (160-pin)

PLMJ7000-84
PLM07000-100
PLM07160-160

EPM7192

PGA
OFP

PLMG7192-160
PLM07192-160

EPM7256

PGA
OFP (160-pin)
OFP (208-pin)

PLMG7256-192
PLM07256-160
PLM07256-208

All FLEX 8000 devices

all

Note (1)

EPC1064

DIP
J-Iead
TOFP

PLMJ1213
PLMJ1213
PLMT1D64

EPC1213

DIP
J-Iead

PLMJ1213
PLMJ1213

EPS448

DIP
J-Iead

PLED448
PLEJ448

EPS464

J-Iead
OFP

PLMJ464
PLM0464

Note:
(1)

I Page 526

Configuration of FLEX 8000 devices is supported by Configuration EPROMs and
the FLEX Download Cable, which is provided with Configuration EPROM adapters.

Altera Corporation

Ordering Information I

Development
Sockets for
QFP Carriers

Table 6 shows the ordering codes for QFP device development sockets. All
MAX 5000/EPS464 and MAX 7000 QFP devices with 100 or more pins are
shipped in QFP carriers. QFP carriers and development sockets are rated
from -65 0 C to 155 0 C and are qualified to handle commercial (C), industrial
(I), and military (M) operating temperatures.

Table 6. QFP Device Sockets

Product

Ordering Code

100-pin development socket (includes removal tool)

PL-SKT/Q100

160-pin development socket (includes removal tool)

PL-SKT/Q160

208-pin development socket (includes removal tool)

PL-SKT/Q208

Table 7 shows the ordering codes for the QFP carrier extraction tools.

Table 7. QFP Carrier Extraction Tools

Product

I Altera Corporation

Ordering Code

100-pin QFP carrier extraction tool

PL-EXT1

160- and 208-pin QFP carrier extraction tool

PL-EXT2

Page 5271

Notes:

Technical Support
from Altera Applications
I August 1993, ver.

Introduction

Altera's technical support team includes over 30 Applications Engineers
dedicated to promptly resolving customers' technical issues. These
Applications Engineers are located at Altera's headquarters in San Jose,
California, and at several locations around the world.
In addition, Altera Applications offers the following services:

o
o

Training
Courses

Training courses
Electronic bulletin board service
Applications publications
Design evaluations
Technical support hotline

Altera provides a variety of training courses that help customers efficiently
use Altera products. With these courses, customers can fine-tune their
skills with Altera development tools or simply learn more about Altera
products. Courses include device architectures, MAX+PLUS II
demonstrations, and how-to sessions. All training courses can be tailored
to fit customer needs.
Training courses are held at Altera in San Jose; in some cases, they can be
held at customer sites. For more information, contact Altera Applications
at (408) 894-7000.

Electronic
Bulletin Board
Service

Altera maintains a 24-hour electronic bulletin board service (BBS) for
instant access to the latest Altera product information. On-line versions of
Altera application notes and briefs, as well as recent quarterly newsletters,
are available from the BBS. Software utility programs are also available.
The telephone number for the BBS is (408) 249-1100. To connect to the BBS
via modem, the following equipment and configuration is required:

o
o

I Altera Corporation

1200 or 2400 baud rate
Bell Standard 212A or compatible modem
8 data bits, 1 stop bit, no parity

Page 529

I Technical Support from Altera Applications
The following file transfer protocols are supported:

o
o
o
o
o
o

ASCII (non-binary)
Xmodem (checksum)
Xmodem-CRC (CRC)
Ymodem-G (lK-Xmodem-G)
Ymodem (lK-Xmodem)
Kermit

Applications
Publications

Altera Applications produces technical application notes and briefs to help
customers select and use programmable logic. All technical literature
currently available from Altera is listed in the Applications quarterly
customer newsletter, News & Views. The News & Views newsletter also
includes technical articles written by Altera Applications engineers, a
question and answer section that addresses many commonly asked
questions, and the latest information on Altera products. All registered
users of Altera products receive News & Views each quarter.

Design
Evaluations

If customers are considering using Altera devices, Altera Applications

Technical
Support Hotline

Engineers can evaluate their designs and recommend a device that will
best fit their needs. Applications engineers will also estimate device
performance. For more information, contact your local Altera sales office.
From 7:30 a.m. to 5:00 p.m. Pacific Standard Time, customers can talk
directly to Applications Engineers when they call (BOO) BOO-EPLD. Questions
are handled promptly and completely, ensuring that the design process
keeps moving forward. If customers are outside of the United States, they
can contact their local Altera distributor or sales office, or send a fax to
(40B) 954-034B.

I Page 530

Altera Corporation

Sales Offices,
Distributors
& Representatives
I August 1993

Altera U.S.
Sales Offices

NORTHERN CALIFORNIA

MASSACHUSETTS

Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
TEL: (408) 894-7900
FAX: (408) 428-0463

Altera Corporation
238 Littleton Road
Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157

SOUTHERN CALIFORNIA
Altera Corporation
6 Morgan, Suite 100
Irvine, CA 92718
TEL: (714) 587-3002
FAX: (714) 587-9789

NEW JERSEY
Altera Corporation
981 U.S. Highway 22, Suite 2000
Bridgewater, NJ 08807
TEL: (908) 526-9400
FAX: (908) 526-5471

GEORGIA
Altera Corporation
1080 Holcomb Bridge Road
Bldg. 100, Suite 300
Roswell, GA 30076
TEL: (404) 594-7621
FAX: (404) 998-9830

TEXAS
Altera Corporation
5080 Spectrum Drive, Suite 812W
Dallas, TX 75248
TEL: (214) 701-2330
FAX: (214) 701-2331

ILLINOIS
Altera Corporation
150 N. Martingale Road, Suite 838
Schaumburg, IL 60173
TEL: (708) 240-0313
FAX: (708) 240-0266

Altera
International
Sales Offices

UNITED STATES
(CORPORATE HEADQUARTERS)
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
USA
TEL: (408) 894-7000
TLX: 888496
FAX: (408) 433-3943

FRANCE
Altera France
Zac La Sabliere
4, Rue Maryse Bastie
91430-IGNY
France
TEL: (33) 1 69 85 5630
FAX: (33) 1 69855614

GERMANY
UNITED KINGDOM
(EUROPEAN HEADQUARTERS)
Altera U.K. Limited
Solar House
Globe Park, Fieldhouse Lane
Marlow, Bucks SL71TB
England
TEL: (44) 628 488800
FAX: (44) 628 890078

I Altera Corporation

Altera GmbH
BahnhofstraBe 9
0-85386 Eching
Germany
TEL: (49) 89/3196014
TLX: (841) 5213250
FAX: (49) 89/3192193

Page 531

ISales Offices, Distributors & Representatives

Altera
International
Sales Offices
(continued)

North American
Distributors

ITALY

JAPAN

Altera Italia
Corso Lombardia 75
Autoporto Pescarito
10099 San Mauro, Torinese
(Torino)
Italy
TEL: (39) 11 2238588
FAX: (39) 11 2238589

Altera Japan K.K.
Ichikawa Gakugeidai Building
2nd Floor
12-8 Takaban 3-chome
Meguro-ku, Tokyo 152
Japan
TEL: (81) 33 716-2241
FAX: (81) 33 716-7924

Alliance Electronics

Pioneer-Standard Electronics

Almac/Arrow

Pioneer Technologies Group

Arrow/Schweber Electronics Group

Semad (Canada only)

Future Electronics (Canada only)

Wyle Laboratories

Newark Electronics

u.s. Sales
Representatives

ALABAMA

COLORADO

EnVision, Inc.
1009 Henderson Road, Suite 400B
Huntsville, AL 35816
TEL: (205) 721-1788
FAX: (205) 721-1789

Compass Marketing
5600 S. Quebec Street, Suite 350D
Englewood, CO 80111
TEL: (303) 721-9663
FAX: (303) 721-0195

ARIZONA

CONNECTICUT

Oasis Sales, Inc.
301 E. Bethany Home Road #A 135
Phoenix, AZ 85012
TEL: (602) 277-2714
FAX: (602) 263-9352

Technology Sales, Inc.
237 Hall Avenue
Wallingford, CT 06492
TEL: (203) 269-8853
FAX: (203) 269-2099

ARKANSAS

DELAWARE

Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
TEL: (214) 387-3601
FAX: (214) 387-3605

BGR Associates
Evesham Commons
525 Route 73, Suite 100
Marlton, NJ 08053
TEL: (609) 983-1020
FAX: (609) 983-1879

CALIFORNIA
Addem
1015 Chestnut Street #F2
Carlsbad, CA 92008
TEL: (619) 729-9216
FAX: (619) 729-6408
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
TEL: (408) 894-7900
FAX: (408) 428-0463
Infinity Sales
20 Corporate Park, Suite 100
Irvine, CA 92714
TEL: (714) 833-0300
FAX: (714) 833-0303
Sierra Technical Sales
23566 Woodhaven Place
Auburn, CA 95602
TEL: (916) 268-3357
FAX: (916) 268-0192

I Page 532

DISTRICT OF COLUMBIA
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
TEL: (410) 995-1900
FAX: (410) 964-3364

FLORIDA
EIR, Inc.
1057 Maitland Center Commons
Maitland, FL 32751
TEL: (407) 660-9600
FAX: (407) 660-9091

GEORGIA
EnVision, Inc.
3220 Pointe Parkway
Norcross, GA 30092
TEL: (404) 840-1055
FAX: (404) 840-1048

Altera Corporation

Sales Offices, Distributors &Representatives
IDAHO

MAINE

Compass Marketing
5 Triad Center, Suite 320
Salt Lake City, UT 84180
TEL: (801) 322-0391
FAX: (801) 322-0392

Altera Corporation
238 Littleton Road, Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157

Phase II Technical Sales
550 Kirkland Way, Suite 100
Kirkland, WA 98033
TEL: (206) 828-8182
FAX: (206) 828-7472

MARYLAND
Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
TEL: (410) 995-1900
FAX: (410) 964-3364

ILLINOIS
AEM, Inc.
11520 St. Charles Rock Road, Suite 131
Bridgeton, MO 63044
TEL: (314) 298-9900
FAX: (314) 298-8660
Oasis Sales Corporation
1101 Tonne Road
Elk Grove Village, IL 60007
TEL: (708) 640-1850
FAX: (708) 640-9432

MASSACHUSETIS
Altera Corporation
238 Littleton Road, Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157
Technology Sales, Inc.
332 Second Avenue
Waltham, MA 02154
TEL: (617) 890-5700
FAX: (617) 890-3913

INDIANA
Electro Reps, Inc.
7240 Shadeland Station, Suite 275
Indianapolis, IN 46256
TEL: (317) 842-7202
FAX: (317) 841-0230

MICHIGAN
Rathsburg Associates, Inc.
34605 Twelve Mile Road
Farmington Hills, MI 48331
TEL: (313) 489-1500
FAX: (313) 489-1480

IOWA
AEM, Inc.
4001 Shady Oak Drive
Marion, IA 52302
TEL: (319) 377-1129
FAX: (319) 377-1539

MINNESOTA
Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
TEL: (612) 646-7217
FAX: (612) 646-4484

KANSAS
AEM, Inc.
8843 Long Street
Lenexa, KS 66215
TEL: (913) 888-0022
FAX: (913) 888-4848

MISSISSIPPI
EnVision, Inc.
3220 Pointe Parkway
Norcross, GA 30092
TEL: (404) 840-1055
FAX: (404) 840-1048

KENTUCKY
Electro Reps, Inc.
7240 Shadeland Station, Suite 275
Indianapolis, IN 46256
TEL: (317) 842-7202
FAX: (317) 841-0230
Lyons Corp.
4812 Frederick Road, Suite 101
Dayton, OH 45414
TEL: (513) 278-0714
FAX: (513) 278-3609

LOUISIANA
Technical Marketing, Inc.
2901 Wilcrest Drive, Suite 139
Houston, TX 77042
TEL: (713) 783-4497
FAX: (713) 783-5307

I Altera Corporation

MISSOURI
AEM, Inc.
11520 St. Charles Rock Road, Suite 131
Bridgeton, MO 63044
TEL: (314) 298-9900
FAX: (314) 298-8660

MONTANA
Compass Marketing
5 Triad Center, Suite 320
Salt Lake City, UT 84180
TEL: (801) 322-0391
FAX: (801) 322-0392

NEBRASKA
AEM, Inc.
4001 Shady Oak Drive
Marion, IA 52302
TEL: (319) 377-1129
FAX: (319) 377-1539

Page 533

I Sales Offices, Distributors & Representatives

u.s. Sales
Representatives
(continued)

NEVADA

NORTH DAKOTA

Oasis Sales Corporation
301 E. Bethany Home Road #A135
Phoenix, AZ 85012
TEL: (602) 277-2714
FAX: (602) 263-9352

Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
TEL: (612) 646-7217
FAX: (612) 646-4484

SierraTechnical Sales
23566 Woodhaven Place
Auburn, CA 95602
TEL: (916) 268-3357
FAX: (916) 268-0192

OHIO
The Lyons Corporation
4812 Frederick Road, Suite 101
Dayton, OH 45414
TEL: (513) 278-0714
FAX: (513) 278-3609

NEW HAMPSHIRE
Altera Corporation
238 Littleton Road, Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157

The Lyons Corporation
4615 W. Streetsboro Road
Richfield, OH 44286
TEL: (216) 659-9224
FAX: (216) 659-9227

NEW JERSEY

The Lyons Corporation
248 N. State Street
Westerville,OH 43081
TEL: (614) 895-1447
FAX: (513) 278-3609

BGR Associates
Evesham Commons
525 Route 73, Suite100
Marlton, NJ 08053
TEL: (609) 983-1020
FAX: (609) 983-1879
ERA, Inc.
354 Veterans Memorial Highway
Commack, NY 11725
TEL: (516) 543-0510
FAX: (516) 543-0758

OKLAHOMA
Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
TEL: (214) 387-3601
FAX: (214) 387-3605

OREGON
NEW MEXICO
Nelco Electronix
3240 C Juan Tabo Blvd. NE
Albuquerque, NM 87111
TEL: (505) 293-1399
FAX: (505) 293-1011

Phase II Technical Sales
4900 SW Griffith Drive, Suite 110
Beaverton, OR 97005
TEL: (503) 643-6455
FAX: (503) 626-7442

PENNSYlVANIA
NEW YORK
ERA, Inc.
354 Veterans Memorial Highway
Commack, NY 11725
TEL: (516) 543-0510
FAX: (516) 543-0758

BGR Associates
Evesham Commons
525 Route 73, Suite 100
Marlton, NJ 08053
TEL: (609) 983-1020
FAX: (609) 983-1879

Technology Sales, Inc.
903 Hanshaw Road
Ithica, NY 14850
TEL: (607) 257-7070
FAX: (607) 257-8080

The Lyons Corporation
248 N. State Street
Westerville,OH 43081
TEL: (614) 895-1447
FAX: (513) 278-3609

Technology Sales, Inc.
920 Perinton Hills Office Park
Fairport, NY 14450
TEL: (716) 223-7500
FAX: (716) 223-5526

RHODE ISLAND
Altera Corporation
238 Littleton Road, Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157

NORTH CAROLINA
EnVision, Inc.
5337 Trestlewood Lane
Raleigh, NC 27610
TEL: (919) 231-9939
FAX: (919) 231-9949

Page 534

SOUTH CAROLINA
EnVision, Inc.
1009 Henderson Road, Suite 400B
Huntsville, AL 35816
TEL: (205) 721-1788
FAX: (205) 721-1789

Altera Corporation

Sales Offices, Distributors & Representatives
SOUTH DAKOTA

VIRGINIA

Cahill, Schmitz & Cahill, Inc.
315 North Pierce
St. Paul, MN 55104
TEL: (612) 646-7217
FAX: (612) 646-4484

Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
TEL: (410) 995-1900
FAX: (410) 964-3364

TENNESSEE

WASHINGTON

EnVision, Inc.
1009 Henderson Road, Suite 400B
Huntsville, AL 35816
TEL: (205) 721-1788
FAX: (205) 721-1789

Phase II Technical Sales
550 Kirkland Way, Suite 100
Kirkland, WA 98033
TEL: (206) 828-8182
FAX: (206) 828-7472

TEXAS

WEST VIRGINIA

Technical Marketing, Inc.
3701 Executive Center Drive #205
Austin, TX 78731
TEL: (512) 343-6976
FAX: (512) 343-7986

Robert Electronic Sales
5525 Twin Knolls Road, Suite 325
Columbia, MD 21045
TEL: (410) 995-1900
FAX: (410) 964-3364

Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
TEL: (214) 387-3601
FAX: (214) 387-3605

WISCONSIN

Technical Marketing, Inc.
2901 Wilcrest Drive, Suite 139
Houston, TX 77042
TEL: (713) 783-4497
FAX: (713) 783-5307

Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
St. Paul, MN 55104
TEL: (612) 646-7217
FAX: (612) 646-4484
Oasis Sales Corporation
1305 N. Barker Road
Brookfield, WI 53005
TEL: (414) 782-6660
FAX: (414) 782-7921

UTAH
Compass Marketing
5 Triad Center, Suite 320
Salt Lake City, UT 84180
TEL: (801) 322-0391
FAX: (801) 322-0392

WYOMING
Compass Marketing
5600 S. Quebec Street, Suite 3500
Englewood, CO 80111
TEL: (303) 721-9663
FAX: (303) 721-0195

VERMONT
Altera Corporation
238 Littleton Road, Suite 204
Westford, MA 01886
TEL: (508) 392-1100
FAX: (508) 392-1157

Canadian Sales
Representatives

ALBERTA

ONTARIO (continued)

Kaytronics
6815-8th Street NE, Suite 179
Calgary, Alberta T2E 7H7
Canada
TEL: (403) 275-7000

Kaytronics
5935 Airport Road #200
Mississauga, Ontario L4V 1W5
Canada
TEL: (416) 612-9200

BRITISH COLUMBIA

QUEBEC

Kaytronics
#102-4585 Canada Way
Burnaby, BC V5G 4L6
Canada
TEL: (604) 294-2000

Kaytronics
5800 Thimens Boulevard
Ville St. Laurent, Quebec H4S 1S5
Canada
TEL: (514) 745-5800

ONTARIO
Kaytronics
405 Britannia Road E #206
Mississauga, Ontario L4Z 3E6
Canada
TEL: (416) 507-6400

I Altera

Corporation

Page 535

I Sales Offices, Distributors & Representatives

International
Distributors

ARGENTINA

FINLAND

YEL S.R.L.
Virrey Cevallos 143
1077 Buenos Aires
Argentina
TEL: (54) 1-372-7140
TLX: (390) 18605 (YEL AR)
FAX: (54) 1-476-2551

Yleiselektroniikka Oy
P.O. Box 73
Luomannotko 6
SF-02201 Espoo
Finland
TEL: (358) 0-452-621
TLX: (857) 123212 (YLEOY SF)
FAX: (358) 0-452-62231

AUSTRALIA
Veltek Pty. Ltd.
18 Harker St.
Burwood, Victoria 3125
Australia
TEL: (61) 3-808-7511
FAX: (61) 3-808-5473

AUSTRIA
Transistor Hitronik Vertriebs GmbH
GudrunstraBe 184/2/2
A-1100 Wi en
Austria
TEL: (43) 601 290
TLX: (847) 134404 (HIT)
FAX: (43) 601 2950

BELGIUM
0&0 Electronics
Vile Olympiadelaan 93
B-2020 Antwerpen
Belgium
TEL: (32) 3-827-7934
TLX: (846) 73121 (DDELEC BU)
FAX: (32) 3-828-7254

FRANCE
Tekelec Airtronic SA
Cite des Bruyeres
Rue-Carle Vernet
9231 0 Sevres
France
TEL: (33) 1 46 23 24 25
TLX: (842) 634018 (TKLEC A F)
FAX: (33) 1 4507 21 91

GERMANY
Avnet E2000 Vertriebs AG
Stahlgruberring 12
0-81829 MOnchen
Germany
TEL: (49) 89/45110-01
TLX: (841) 522561 (ELEC D)
FAX: (49) 89/45110-129
SASCOGmbH
Hermann-Oberth-Str. 16
0-85640 Putzbrunn
Germany
TEL: (49) 89/46110
FAX: (49) 89/4611270

BRAZIL
Uniao Digital Ltda.
Rua Georgia 69
04559-010
Sao Paulo - SP
Brazil
TEL: (55) 11 536-4121
FAX: (55) 11 533-6780

GREECE
Micronics Limited
46 Kritis Street
16451-Argyroupolis
Athens
Greece
TEL: (30) 1 991-4786
FAX: (30) 1 995-1814

CHINA
CIDC
No.1, Gao Jia Yuan
Dongzhimenwai, Chao Yang Qu
Beijing 100015
People's Republic of China
TEL: (86) 1-436-5577
FAX: (86) 1-466-9492

HONG KONG
Eastele Technology Ltd.
A 16, 6/F Proficient Industrial Center
6 Wang Kwun Road
Kowloon
Hong Kong
TEL: (852) 798-8860
FAX: (852) 305-0640

DENMARK
E.V. Johanssen Elektronik AlS
Titangade 15
DK-2200 Koebenhavn N
Denmark
TEL: (45) 31 83 90 22
TLX: (855) 16522 (EVICAS OK)
FAX: (45) 31 839222

I Page 536

INDIA
Sritech Information Technology Ltd.
744/51, 2nd Floor, Chintal Plaza

33rd Cross, 10th Main
4th Block, Jayanagar
Bangalore 560 011
India
TEL: (91) 80-640-661
TLX: (953) 08458162 (SRIS IN)
FAX: (91) 80-633-508

Altera Corporation

Sales Offices, Distributors & Representatives
INDIA (continued)

KOREA (continued)

Capricorn Systems International
1340 Tully Road
San Jose, CA 95122
TEL: (408) 294-2833
FAX: (408) 294-0355

Rosedale Business Group
622 Rosedale Road
Princeton, NJ 08540
USA
TEL: (609) 683-1700
FAX: (609) 683-7447

IRAN
BBS Electronics Pte. Ltd.
1 Genting Link
Perfect Industrial Building #05-03
Singapore 1334
TEL: (65) 748-8400
FAX: (65) 748-8466

MEXICO
Intectra
Avenida 1, #100
Col. San Pedro de los Pinos
Mexico 03800, D.F.
TEL: (52) 5 272 7898
FAX: (52) 2 516 2468

ISRAEL
Active Technologies
80 Express Street
Plainview, NY 11803
USA
TEL: (516) 938-4848
FAX: (516) 938-4141
Vectronics Ltd.
60 Medinat Hayehudim Street
P.O. Box 2024
Herzlia B 46120
Israel
TEL: (972) 9-556-070
TLX: (922) 342579 (VECO IL)
FAX: (972) 9-556-508

ITALY
Lasi Elettronica Div. Silverstar Ltd. S.PA
Viale Fulvio Testi, 280
20126 Milano
Italy
TEL: (39) 2 661 431
FAX: (39) 2 661 01385

JAPAN
Altima Corporation
Hakusan High-Tech Park
1-22-2 Hakusan, Midori-Ku
Yokohama City 226
Japan
TEL: (81) 45-939-6113
FAX: (81) 45-939-6114
Paltek Corporation
1-3-3 Azamino-Minami
Midori-Ku, Yokohama City
Kanagawa-Ken, 225
Japan
TEL: (81) 45-910-1381
TLX: (781) 02425205 (PALTEK J)
FAX: (81) 45-910-1390

KOREA
MJL Korea, Ltd.
Bookook Security Building, 11 th Floor
34-2 Youido Dong
Yeungdeungpo Ku
Seoul, 150-010
Korea
TEL: (82) 2-784-8000
TLX: 843457 (MJL MORV)
FAX: (82) 2-784-4644

I Altera Corporation

NETHERLANDS
Koning en Hartman
1 Energieweg
2627 AP Delft
Netherlands
TEL: (31) 15 609906
TLX: 38250 (KOHA NL)
FAX: (31) 15619194

NORWAY
N.C. ScandComp Norway AlS
Aslakveien 20 F
0753 Oslo 7
Norway
TEL: (47) 2-500650
TLX: (856) 77144 (ELTRO N)
FAX: (47) 2-502777

SINGAPORE
Serial System Pte. Ltd.
11 Jalan Mesin
Standard Industrial Building #06-00
Singapore 1336
TEL: (65) 280-0200
FAX: (65) 286-1812

SPAIN
Selco
Paseo de la Habana, 190
28036 Madrid
Spain
TEL: (34) 1-359-4346
TLX: (831) 45458 (EPAR E)
FAX: (34) 1-359-2284

SWEDEN
Avnet Nortec AB
Parkvagen,2A
Box 1830
S-171 27 Solna
Sweden
TEL: (46) 8 705 18 00
FAX: (46) 8 83 6918

SWITZERLAND
Elbatex
HardstraBe 72
5430 Wettingen
Switzerland
TEL: (41) 56 27 57 77
FAX: (41) 56261486

Page 537

I Sales Offices, Distributors & Representatives

International
Distributors
(continued)

SWITZERLAND (continued)
MPI Distribution AG
TaJernstraBe 20
5405 Dattwil
Switzerland
TEL: (41) 56 83 55 55
FAX: (41) 56 83 30 20

THAILAND
Nu-Era Co. Ltd.

2077/8 Ramkhamhang 37
Huamark, Bangapi
Bangkok 10240
Thailand
TEL: (66) 2-318-6453
FAX: (66) 2-318-6454

TAIWAN

I Page 538

UNITED KINGDOM

Galaxy Far East Corp.
8F-6, 390 Sec. 1
Fu Hsing South Road
Taipei
Taiwan R.O.C.
TEL: (886) 2-705-7266
TLX: (785) 26110 (GALAXYER)
FAX: (886) 2-708-7901

Ambar Cascom Ltd.
Rabans Close
Aylesbury, Bucks HP193RS
England
TEL: (44) 296 434141
TLX: (851) 837427 (AM BAR G)
FAX: (44) 296 29670

Jeritronics Ltd.
Floor 7B, #267, Sec. 3
Cheng-Teh Road
Taipei
Taiwan R.O.C.
TEL: (886) 2-585-1636
FAX: (886) 2-586-4736

Thame Components Ltd.
Thame Park Road
Thame,Oxon OX93UQ
England
TEL: (44) 844 261188
TLX: (851) 837917 (MEMEC G)
FAX: (44) 844 261681

Altera Corporation

Glossary
I August 1993
A
Active Parallel Down (APD) A configuration
scheme in which a byte-wide parallel PROM
loads the design data into a FLEX 8000 device.
The FLEX 8000 device first generates an address;
the PROM subsequently returns the next byte of
data. Addresses are generated by the FLEX 8000
device sequentially in descending order (3FFFFh
to OOOOOh). MAX+PLUS II can generate
Hexadecimal (Intel-Format) Files (.hex) that
contain the data for configuring FLEX 8000
devices in an APD configuration scheme.
Active Parallel Up (APU) A configuration scheme
in which a byte-wide parallel PROM loads the
design data into a FLEX 8000 device. The
FLEX 8000 device first generates an address; the
PROM subsequently returns the next byte of data.
Addresses are generated by the FLEX 8000 device
sequentially in ascending order (OOOOOh to
3FFFFh). MAX+PLUS II can generate
Hexadecimal (Intel-Format) Files (.hex) that
contain the data for configuring FLEX 8000
devices in an APU configuration scheme.
Active Serial (AS) A configuration scheme in
which a serial EPROM loads the design data into
a FLEX 8000 device. The MAX +PLUS II Compiler
automatically generates a Programmer Object
File (.pof) for programming serial EPROM
devices, e.g., the EPC1213 Configuration EPROM,
whenever a FLEX 8000 project is compiled.
Altera Hardware Description Language (AHDL)
Altera's design entry language. AHDL is
completely integrated into MAX+PLUS II, and
allows the designer to enter and edit Text Design
Files (.tdf) with the MAX+PLUS II Text Editor or
any standard text editor, then compile, simulate,

I Altera Corporation

and program projects within MAX+PLUS II.
AHDL supports Boolean equation, state machine,
conditional, and decode logic. AHDL also
provides access to all Altera macrofunctions.

array Clock A Clock signal that passes through
the logic array of a device before arriving at the
Clock input of a register.
Assembler The Compiler module that creates one
or more Programmer Object Files (.pof), SRAM
Object Files (.sof), and optionalJEDEC Files (.jed)
for programming Altera devices.
authorization code A code that enables
MAX+PLUS II applications and features. This
code, provided by Altera, is shown on the Altera
Registration card shipped with new
MAX+PLUS II systems.

c
Carry Chain option A FLEX 8000 logic synthesis
option that controls the use of carry chain logic.
When this option is set to AUTO, it directs the
Compiler's Logic Synthesizer module to insert
carry chain logic-i.e., insert CARRY bufferswherever it is useful. When defining a logic
synthesis style, designers can specify the
maximum allowable length of a chain of these
synthesized CARRY buffers. The AUTO setting does
not force the Logic Synthesizer to use carry logic
and has no effect on CARRY primitives that have
been entered in design files.
When the Carry Chain option is set to IGNORE, it
directs the Logic Synthesizer to ignore CARRY
buffers that have been entered manually in design
files. When this option is set to MANUAL, the Logic

Page 539

I Glossary
Synthesizer uses only the CARRY primitives that
have been manually entered in design files.

Cascade Chain option A FLEX 8000 logic synthesis
option that controls the use of cascade chain
logic. When this option is set to AUTO, it directs
the Compiler's Logic Synthesizer module to insert
cascade logic-Le., insert CASCADE bufferswherever it is useful. When defining a logic
synthesis style, designers can specify the
maximum allowable length of a chain of these
synthesized CASCADE buffers. The AUTO setting
does not force the Logic Synthesizer to use
cascade logic and has no effect on CASCADE
primitives that have been entered in design files.
When the Cascade Chain option is set to IGNORE,
it directs the Logic Synthesizer to ignore CASCADE
buffers that have been entered manually in design
files. When this option is set to MANUAL, the Logic
Synthesizer uses only the CASCADE primitives
that have been manually entered in design files.

CerDIP Ceramic Dual In-Line Package. A device
package offered by Altera. See Altera Device
Package Outlines and Ordering Information for more
information.
Classic An Altera device family based on Altera's
original EPLD architecture. This EEPROM- and
EPROM-based family includes EP330, EP610,
EP610A, EP91O, EP91OA, and EP1810 devices.
Compiler Netlist Extractor The MAX+PLUS II
Compiler module that creates Compiler Netlist
Files (.cnf), Hierarchy Interconnect FilesL(.hif),
and Symbol Files (.sym) from the design files for
a project. This module includes built-in EDIF
and Xilinx Netlist Readers that convert EDIF
Netlist Files (.edf) and Xilinx Netlist Format Files
(.xnf) created with industry-standard CAE
software. The Compiler Netlist Extractor also
checks each design file in a project for problems
such as duplicate node names, missing inputs
and outputs, and outputs that are tied together.
Configuration EPROM A serial EPROM supplied
by Altera for configuring FLEX 8000 devices.

I Page 540

configuration scheme The method used to load
data into a FLEX 8000 device. Six configuration
schemes are available:
Active Serial (AS)
Active Parallel Up (APU)
Active Parallel Down (APD)
Passive Parallel Asynchronous (PPA)
Passive Parallel Synchronous (PPS)
Passive Serial (PS)
For complete information on FLEX 8000
configuration schemes, see Application Brief 33

(Configuring FLEX 8000 Devices).
continuity checking
A test for open circuits
between device pins and programming adapter
sockets. This test verifies that a device is properly
seated in the socket of the adapter.
CQFP Ceramic Quad Flat Pack. A device package
offered by Altera. See Altera Device Package
Outlines and Ordering Information for more
information.

o
Database Builder The MAX+PLUS II Compiler
module that builds a single, fully flattened
database that integrates all files in a project
hierarchy. It also examines the logical
completeness and consistency of the project and
checks for boundary connectivity and syntactical
errors.
dedicated input pin A pin that may only be used
as an input to the device.
device An Altera programmable logic device,
including Classic, MAX 5000 /EPS464, MAX 7000,
FLEX 8000, EPS448, EPB2001, and Configuration
EPROM devices.
device family A group of Altera programmable
logic devices with the same fundamental
architecture. Altera device families are the Classic,
MAX 5000 jEPS464, MAX 7000, FLEX 8000, and
Configuration EPROM families.
Altera Corporation

Glossary

E
EDIF Electronic Design Interchange Format. An
industry-standard format for transmitting design
data. AN EDIF 2 a a or 2 9 a netlist filke is
generated from a schematic design or a VHDL or
Verilog design that has been processed with an
industry-standard synthesis tool. The netlist file
is then imported into MAX+PLUS II as an EDIF
Input File (.edf). The MAX+PLUS II Compiler
can generated one or more EDIF Output Files
(.edo) in EDIF 2 a a or 2 9 a format that contain
functional and timing information for simulation
with a standard EDIF simulator.
EEPROM Electrically Erasable Programmable
Read-Only Memory. A form of reprogrammable
semiconductor memory in which the contents
can be erased by subjecting the device to
appropriate electrical signals.
EPLD Erasable Programmable Logic Device, i.e.,
an Altera device that is a member of the Classic,
MAX 5000 /EPS464, or MAX 7000 family.
EPROM Erasable Programmable Read-Only
Memory. A form of reprogrammable semiconductor memory whose contents can be erased
by subjecting the device to ultraviolet light of the
proper wavelength. See Operating Requirements
for Altera Devices and Technology & Reliability for
more information.
expander product term A single product term with
an inverted output that feeds back into the Logic
Array Block (LAB) of a MAX 5000 /EPS464 or
MAX 7000 device. An uncommitted expander
product term that can be shared with other logic
cells in the same LAB is called a shareable
expander; a product term that has been shared in
this manner is called a shared expander. In MAX
7000 devices only, an expander product term
borrowed from an adjacent logic cell in the same
LAB is called a parallel expander.
external timing parameters Factory-tested,
guaranteed worst-case values. Examples: tpDlI
tCOlI f CNT ' In FLEX 8000 device data sheets,

I Altera Corporation

external timing parameters are listed under
"External Reference Timing Characteristics."

extraction tool A tool to extract QFP devices from
QFP carriers. Two extraction tools are available
from Altera: one for lOa-pin QFPs and one for
160- and 208-pin QFPs.

F
family-specific macrofunction An AHera-provided
macrofunction that contains logic optimized for
the architecture of a specific device family. The
functionality of a family-specific macro function
is always the same, regardless of the device family
for which it is designed. However, primitives
and nodes used within the macro function file
can vary from family to family to take advantage
of different device architectures, providing higher
performance and more efficient implementation.
FastTrack Interconnect Dedicated connection
paths that span the entire width and height of a
FLEX 8000 device. These connection paths allow
signals to travel between all Logic Array Blocks
(LABs) in a device.
Fitter The MAX+PLUS II Compiler module that
fits a project into one or more devices. The Fitter
selects appropriate interconnection paths, and
pin and logic cell assignments. It also creates a
Report File (.rpt) and Fit File (.fit) for the project.
FLEX Download Cable A cable used to download
SRAM Object File (.80f) data in a passive serial
(PS) configuration scheme to a FLEX 8000 device
in an in-system circuit. FLEX 8000 devices can be
configured with the FLEX Download Cable to
allow functional testing and prototyping on the
circuit board.
FLEX 8000 An AHera device family based on
Flexible Logic Element MatriX architecture. This
SRAM-based family offers high-performance,
register-intensive, high-gate-count devices. The
family includes the EPF8282, EPF8282V, EPF8452,
EPF8820, EPF81188, and EPF81500 devices.
Page 541

I Glossary
flipflop or register An edge-triggered, clocked
storage unit that stores a single bit of data. A
low-to-high transition on the Clock signal changes
the output of the flipflop, based on the value of
the data input(s). This value is maintained until
the next low-to-high transition of the Clock, or
until the flipflop is preset or cleared. Depending
on the architecture of the device family, a register
can be programmed as a level-sensitive flowthrough latch or as an edge-triggered D,T, JK, or
SR flipflop.
functional simulation A MAX+PLUS II Simulator
mode that uses a functional Simulator Netlist
File (.snf) to simulate the logical performance of
a project without timing information.
Functional SNF Extractor The MAX+PLUS II
Compiler module that creates the functional
Simulator Netlist File (.snf) required for
functional simulation.

G
global Clear A signal from a dedicated input pin
that does not pass through the logic array before
arriving at the Clear input ofa register. In
FLEX 8000 devices, a global Clear can come from
any of the dedicated inputs. MAX 7000 devices
have input pins that can be used either as global
Clear sources or dedicated inputs to the device.
global Clock A signal from a dedicated input pin
that does not pass through the logic array before
arriving at the Clock input of a register. In
FLEX 8000 devices, a global Clock can come from
any of the four dedicated input pins. MAX 7000,
MAX 5000, EPS464, and EP1810 devices have
input pins that can be used either as global Clock
sources or dedicated inputs to the device. EP910,
EP91OA, EP610, EP610A, and EP330 devices have
dedicated Clock iput pins.

H
Hexadecimal (Intel-Format) File (.hex) A
hexadecimal file that supports the Active Parallel

I Page 542

Up (APU) and Active Parallel Down (APD)
configuration schemes for FLEX 8000 devices.

interconnect timing parameters Internal timing
parameters for the interconnect in FLEX 8000
devices.
internal timing parameters Worst-case delays
based on external timing parameters. Internal
timing parameters cannot be measured explicitly,
and should be used only for estimating device
performance. Post-compilation timing simulation
or timing analysis is required to determine actual
worst-case performance. Examples: tLAD, tCGEN'
tCLR ' In FLEX 8000 device data sheets, internal
timing parameters are listed under "Internal
Timing Characteristics."

J
JEDEC File (.jed) An ASCII file that contains
programming information. JEDEC Files provide
an industry-standard format for transferring
information between a data preparation system
and a logic device programmer. The
MAX+PLUS II Programmer can optionally save
programming data in JEDEC File format and use
a JEDEC File to program the following Altera
devices: EP330, EP610, EP61OA, EP910, EP910A,
EP1810, EPM5016, and EPM5032 devices.
The Programmer can also use JEDEC Files
generated by A+PLUS software to program
Classic devices.

JLCC Ceramic J-Lead Chip Carrier. A device
package offered by Altera. See Altera Device
Package Outlines and Ordering Information for more
information.

JTAG Joint Test Action Group. A set of
specifications that enables board- and chip-level
functional verification of a board during
production.

Altera Corporation

Glossary I

L
library of parameterized modules (LPM) A
technology-independent library of logic
functions. The LPM standard is built upon and
follows the syntax of the EDIF 2 0 0 standard.
Parameterized modules from the LPM support
architecture-independent design entry for Altera
Classic, MAX 5000 /EPS464, MAX 7000, and FLEX
8000 devices. The MAX+PLUS II Compiler's EDIF
Netlist Reader module includes built-in
compilation support for many parameterized
modules in the LPM.
linked simulation A MAX+PLUS II Simulator
mode that uses a linked Simulator Netlist File
(.snf) to simulate the logical performance of a
project consisting of multiple, linked individual
projects. A linked simulation uses the timing
and/ or functional netlist information from the
combined SNFs of these individual projects.
linked SNF Extractor The MAX+PLUS II Compiler
module that creates the linked Simulator Netlist
File (.snf) required for multi-project simulation.
Logic Array Block (LAB) A physically grouped set
of logic resources in an Altera device. The LAB
consists of a logic cell array and, in some device
families, an expander product term array. Any
signal that is available to anyone logic cell in the
LAB is available to the entire LAB. In Classic
devices, the logic in the LAB shares a global
Clock signal. The LAB is fed by a global bus and
a dedicated input bus. (In the EP1810 Data Sheet,
a LAB is called a quadrant.) In MAX 5000 and
MAX 7000 devices, the LAB is fed by a
Programmable Interconnect Array (PIA) and a
dedicated input bus; in FLEX 8000 devices, the
LAB is fed by row interconnect paths and a
dedicated input bus.
logic cell The generic term for a basic building
block of an Altera general-purpose logic device.
In EPLDs (Classic, MAX 5000/EPS464, and
MAX 7000 devices), the logic cell is called a
macrocell. In FLEX 8000 devices, the logic cell is
called a logic element.

I Altera Corporation

logic element (LE) A basic building block of an
Altera FLEX 8000 device. A logic element consists
of a look-up table (LUT)-i.e., a function
generator that quickly computes any function of
four variables-and a programmable register to
support sequential functions. The register can be
programmed to emulate a flow-through latch; a
D, T, JK, or SR flipflop; or it can be bypassed
entirely for pure combinatorial logic. The register
can feed other logic elements or feed back to the
logic element itself. Some logic elements feed
output or bidirectional II 0 pins on the device.
Logic elements have "numbers" of the format
LC _, where
ranges from 1 to 8 and consists of
the row letter and column number of the Logic
Array Block (LAB).

logic element timing parameters Internal timing
parameters for the logic elements in FLEX 8000
devices.
Logic Programmer card The LP4, LP5, or LP6
expansion card required to run the MAX +PLUS II
Programmer and program Altera devices.
Logic Synthesizer The Compiler module that uses
several algorithms to minimize gate count,
remove redundant logic, and utilize the device
architecture as efficiently as possible.
look-up table (LUT) A function that generates
outputs based on-inputs and a set of stored data.
The logic element of FLEX 8000 devices includes
a four-input LUT that can be configured to
emulate any logical function of four inputs.

M
macrocell A basic building block in Altera
Classic, MAX 5000/EPS464, and MAX 7000
devices. A macrocell consists of two parts:
combinatorial logic and a configurable register.
The combinatorial logic allows a wide variety of
logic functions. Depending on the architecture of
the device family, the register can be programmed
to emulate a flow-through latch; a D, T, JK, or SR
Page 543

I Glossary
flipflop; or it can be bypassed entirely for pure
combinatorial logic. The register can feed other
macrocells or feed back to the macrocell itself.
Some macrocells feed output or bidirectional
II 0 pins on the device. Macrocells have numbers
of the format LC.

MQFP Metal Quad Flat Pack. A device package
offered by Altera. See Altera Device Package
Outlines and Ordering Information for more
information.

Master Programming Unit (MPU) A logic device
programming box. The MPU works with zeroinsertion-force sockets and individual adapters
to program and test Altera devices. The PL-MPU
base unit and adapters with the prefix "PLM"
support both device programming and device
testing. The PLE3-12A unit and other adapters
(e.g., adapters with the prefix "PLE" and the
PLAD3-12 adapter) support device programming
only.

parallel expander An expander product term that
is borrowed from an adjacent logic cell in the
same MAX 7000 Logic Array Block (LAB). Parallel
Expanders is also a logic option that can be
applied to a logic function to allow it to borrow
such parallel expanders. This option can reduce
the number of expander product terms required
in a project and increase the speed of the project.
However, the project may use additional logic
cells, and may be more difficult to fit.

MAX 5000/EPS464 An Altera device family based
on the first generation of Multiple Array MatriX
architecture. This EPROM-based device family
includes EPM5016, EPM5032, EPM5064, EPS464,
EPM5128, EPM5128A, EPM5130, EPM5192, and
EPM5192A devices.

Passive Parallel Asynchronous (PPA) A
configuration scheme in which a CPU loads the
FLEX 8000 device via a common data bus. This
configuration scheme is used for a system in
which multiple devices require initialization. In
this scheme, the FLEX 8000 device accepts a
parallel byte of input data, and then serializes
that byte using its internal synchronization Clock.
Intelligent handshaking between the CPU and
the FLEX 8000 device allows the CPU to configure
multiple FLEX 8000 devices simultaneously.
MAX+PLUS II can generate Tabular Text Files
(.Uf) that contain the data for configuring
FLEX 8000 devices in an PPA configuration
scheme.

MAX 7000 An Altera device family based on the
second generation of Multiple Array MatriX
architecture. These EPROM- and EEPROM-based
devices include EPM7032, EPM7032V, EPM7064,
EPM7096, EPM7128, EPM7160, EPM7192, and
EPM7256 devices.
MAX+PLUS II Altera's Multiple Array MatriX
Programmable Logic User System. MAX+PLUS II
is a set of computer programs and hardware
support products that allow design and
implementation of custom logic circuits with
Classic, MAX 5000/EPS464, MAX 7000, and
FLEX 8000 devices.
MPLD Mask-Programmed Logic Device, i.e., a
custom Altera device created by converting a
design originally created for an EPLD or
FLEX 8000 device. Altera offers a program for
converting customer designs into MPLDs, which
are cost-effective alternatives for high-volume
production.

Page 544

Passive Parallel Synchronous (PPS) A
configuration scheme in which a CPU loads the
FLEX 8000 device via a common data bus. Data
is latched by the FLEX 8000 device on the first
rising edge of a CPU-driven Clock signal. The
next eight Clock pulses serialize this latched data
within the FLEX 8000 device. The tenth rising
edge of the Clock signal causes the FLEX 8000 to
latch the next 8-bit byte of data. MAX+PLUS II
can generate Tabular Text Files (.Uf) that contain
the data for configuring FLEX 8000 devices in a
PPS configuration scheme.

Altera Corporation

Glossary

Passive Serial (PS) A configuration scheme in
which an external controller is used to configure
a FLEX 8000 device with a serial bit-stream. The
external controller can be the MAX+PLUS II
Programmer or an intelligent host, such as a
micro controller or a CPU.
PDIP Plastic Dual In-Line Package. A device
package offered by Altera. See Altera Device
Package Outlines and Ordering Information for more
information.
peripheral register A register that exists on the
periphery of a FLEX 8000 device. Peripheral
Register is also a logic option that specifies that a
register should be implemented in a peripheral
register.
PGA Ceramic Pin-Grid Array. A device package
offered by Altera. See Altera Device Package
Outlines and Ordering Information for more
information.
PLAD3-12 An adapter that plugs into the Master
Programming Unit (MPU). It allows the designer
to use adapters with the prefix "PLE" designed
for use with the PLE3-l2A programming unit. It
also directly supports programming of EP330
devices in DIP packages.
PLCC Plastic J-Lead Chip Carrier. A device
package offered by Altera. See Altera Device
Package Outlines and Ordering Information for more
information.
Programmable Interconnect Array (PIA) The portion
of a MAX 5000 or MAX 7000 device that routes
signals between different Logic Array Blocks
(LABs).
Programmer Object File (.pof) A binary file
generated by the Compiler's Assembler module.
It contains the data used by the MAX+PLUS II
Programmer to program an Altera device.
PQFP Plastic Quad Flat Pack. A device package
offered by Altera. See Altera Device Package

I Altera Corporation

Outlines and Ordering Information for more
information.
product term Two or more factors in a Boolean
expression combined with an AND operator
constitute a product term, where "product"
means "logic product."
programming file A file containing data for
programming Altera devices. Both the
MAX+PLUS II Compiler and Programmer can
genera te programming files. The following
programming file formats are available in
MAX +PLUS II:
Hexadecimal (Intel-Format) File (.hex)
JEDEC File (.jed)
Programmer Object File (.pof)
SRAM Object File (.sof)
Tabular Text File (.ttf)
POFs, SOFs, and JEDEC Files are used to program
devices with the MAX+PLUS II Programmer. Hex
files and TTFs are used to configure FLEX 8000
devices by other means. JEDEC Files generated
by A +PLUS software can also be used to program
Classic devices. The Programmer can save data
read from an examined device in POF or JEDEC
File format.

project A project consists of all files that are
associated with a particular design, including all
subdesign files and related ancillary files created
by the user or by MAX+PLUSII software. The
project name is the same as the name of the toplevel design file in the project. MAX +PLUS II
performs compilation, simulation, timing
analysis, and programming on only one project
at a time.

R
removal tool A tool to remove a QFP device in a
carrier from a development socket. Two removal
tools are available from Altera: one for lOa-pin
QFPs and one for 160- and 208-pin QFPs.

Page 545

I Glossary
RQFP Power Quad Flat Pack. A device package
offered by Altera. See Altera Device Package
Outlines and Ordering Information for more
information.

configuring an Altera FLEX 8000 device via the
FLEX Download Cable.

Tabular Text File (.ttf) An ASCII text file in tabular
format that supports the Passive Parallel
Synchronous (PPS) and Passive Parallel
Asynchronous (PPA) configuration schemes for
configuring FLEX 8000 devices.

SAM+PLUS Altera's Stand-Alone Microsequencer (SAM) Programmable Logic User
System. SAM+PLUS is a set of computer
programs and hardware support products that
facilitate design and implementation of custom
logic circuits with the EPS448 device.
Security Bit A bit that prevents an Altera device
from being interrogated or inadvertently
reprogrammed. It can be turned on or off for
each device in a project, or for the entire project.
shared expanders and shareable expanders A
feature of MAX 5000 /EPS464 and MAX 7000
device architecture that allows logic cells to use
uncommitted product terms within the same
Logic Array Block (LAB). A product term that
can be shared in this manner is called a shareable
expander; a product term that is shared in this
manner is called a shared expander. The
MAX+PLUS II Compiler automatically allocates
shareable expanders when a project is compiled.
A shared expander can be allocated with an EXP
primitive.
software guard A device that attaches to the
parallel printer port on a computer. It is required
to run MAX+PLUS II software.

sOle Plastic Small-Outline Integrated Circuit. A
device package offered by Altera. See Altera Device
Package Outlines and Ordering Information for more
information.
SRAM Static Read-Only Memory. A read-write
memory that stores data in integrated flipflops.
See Technology & Reliability for more information.

timing simulation A MAX+PLUS II Simulator
mode that uses a timing Simulator Netlist File
(.snf) to simulate the logical and timing
performance of a project. Since the timing SNF is
generated after logic synthesis, partitioning, and
fitting are performed, only the nodes that have
not been removed by logic optimization are
simulated.
Timing SNF Extractor The Compiler module that
creates the timing Simulator Netlist File (.snf),
which contains the functional and timing data
for the fully optimized project. This file is used
for timing simulation and timing analysis. The
Compiler's EDIF Netlist Writer module also uses
timing SNFs to generate EDIF Output Files (.edo).
TQFP Thin Quad Flat Pack. A device package
offered by Altera. See Altera Device Package
Outlines and Ordering Information for more
information.
Turbo Bit A control bit for choosing speed and
power characteristics of Altera Classic and
MAX 7000 devices. If the Turbo Bit is on, the
speed increases; if it is off, the power consumed
decreases. The Turbo Bit may be turned on or off
in a design file or the Compiler. In Classic devices,
the Turbo Bit applies to the entire device. In
MAX 7000 devices, it applies to individual logic
cells within a device. The Turbo Bit is not available
in MAX 5000 /EPS464 and FLEX 8000 devices.

SRAM Object File (.sof) A binary file, generated
by MAX+PLUS II, that contains the data for

Page 546

Altera Corporation

Glossary

u
user I/O The total number of I/O pins and
dedicated inputs on a device.

v
Verilog A hardware description language from
Cadence. You can generate an EDIF 2 a a or 2 9 a
netlist file from a Verilog design that has been
processed with a Verilog synthesis tool, then
import the file into MAX+PLUS II as an EDIF
Input File (.edf). The MAX+PLUS II Compiler
can also generate a Verilog Output File (.vo) that
contains functional and timing information for
simulation with a standard Verilog simulator.

VHDL Very High Speed Integrated Circuit
(VHSIC) Hardware Description Language. You
can generate an EDIF 2 aaor 2 9 anetlist file from
a VHDL design that has been processed with a
VHDL synthesis tool, then import the file into
MAX+PLUS II as an EDIF Input File (.edf). The
MAX+PLUS II Compiler can also generate a
VHDL Output File (.vho) that contains functional
and timing information for simulation with a
standard VHDL simulator.

I Altera Corporation

Page 547

Notes:

Index
I August 1993
Symbols
3.3-V devices
EPF8282V 29,43,313
EP117032V 69,303
general description 301
selection guide 22

A
AADELAY 460
AA11AX 460
ABEL 460
ABEL-FPGA 460
AC timing characteristics. See timing
parameters
Accel Technologies, Inc. 460
ACCESS alliance 16,459
ACEPlus 460
active parallel up & down (APU & APD)
configuration schemes. See configuration
(FLEX 8000 devices)
active serial (AS) configuration scheme. See
configuration (FLEX 8000 devices)
Acugen Software, Inc. 460
adapters. See programming hardware
AdvanSI11-1076 460
Advantech 463
Advin Systems, Inc. 463
AHDL 440
Aldec, Inc. 460
Altera Hardware Description Language
(AHDL) 440
Altera Stand-Alone Programmer
(PL-ASAP2) 454,456
Altera State 11achine Input Language
(ASMILE) 322
Ando Electric Co. Ltd. 463
APD configuration scheme. See configuration
(FLEX 8000 devices)

I Altera Corporation

Applications Department, technical
support 529
APU configuration scheme. See configuration
(FLEX 8000 devices)
architecture. See device architecture
arithmetic mode (FLEX 8000 logic element) 37
array Clock signals 74,78, 153,239
array control signals 11
AS configuration scheme. See configuration
(FLEX 8000 devices)
AS11 323,329,334
AS11ILE 322
Assembly Language (ASM) 323,329,334
ATGEN 460
AutoLogic 461
Aval Data Corp. 463

B
B&C Microsystems, Inc. 463
BBS 529
boundary-scan test. See JTAG Boundary-Scan
Test
BP 11icrosystems 463
branch-control logic block 325
branching, multiway 333
bulletin board service (BBS) 529
buried flipflops 13
BYP ASS (JTAG instruction) 43
Bytek Corporation 463

c
Cadat 461
Cadence Design Systems, Inc.
CAE hardware support 463
CAE software support 459
carry chain 32,33,36
cascade chain 32, 33, 35, 36

460

Page 549

!Index

cascading (SAM devices)
horizontal 329
vertical 329
Celectronic GmbH 463
Classic devices
architecture 5, 236
CAE software support 459
EP330 235,245,393,423
EP610 235,249,424
EP610 MIL-STD-883-compliant 265
EP610A 235, 257, 424
EP610T 235,261
EP910 235,269,425
EP910A 235,275,425
EP910T 235, 279
EP1810 235,283,426
EP1810 MIL-STD-883-compliant 295
EP1810T 235,291
functional testing 243
general description 235
ordering information 521
package outlines 489
pin-out information 245,249,257,261,
265,269,275,279,283,290,291,298
programming 244
programming hardware 453
reliability 467
Security Bit 240
selection guide 21
timing model 241, 423
timing parameters 419,421
Turbo Bit 237, 240
Clear signals
Classic devices 237
EPS464 devices 223
FLEX 8000 I/O elements 42
FLEX 8000 logic elements 36,38,40
MAX 5000 devices 154
MAX 7000 devices 73
timing parameter definition 420
clearable counter mode (FLEX 8000 logic
element) 37
CLKUSR pin (FLEX 8000 devices) 411
Clock signals
Classic devices 237,238,239
EPS464 devices 223
FLEX 8000 1/0 elements 42
Page 550

Clock signals (continued)
FLEX 8000 logic elements 36,40
MAX 5000 devices 154
MAX 7000 devices 73, 306
timing delay parameters 420, 422
timing parameter definition 422
combinatorial logic
general description 10
timing delay parameters 421
Command File (.cmd) 445
command mode (FLEX 8000 devices) 383
compilation. See design processing
Compiler (MAX+PLUS II) 443
component selection guide 17
Composer 460
Concept 460
CONF_DONE pin (FLEX 8000 devices) 410
configuration (FLEX 8000 deVices). See also
Configuration EPROM devices
active parallel up & down (APU &
APD) 390,412
active serial (AS) 343, 387, 412
compatible Configuration EPROMs 342
configuration files 411, 415
configuration option bits 405
configuration pins 407
general description 383,384
in-circuit reconfiguration 404,415,416
in-system configuration with FLEX
Download Cable 414
passive parallel asynchronous (PPA) 396,
413
passive parallel synchronous (PPS) 394,
413
passive serial (PS) 400, 413
real-time reconfiguration 386
reliability 417
source of data 384
Configuration EPROM devices
architecture 342
configuring FLEX 8000 devices 343,387
EPCI064 341, 347
EPC1213 341, 347
ordering information 521
overview 341
package outlines 489
packages 341
Altera Corporation !

Index I

Configuration EPROM devices (continued)
pin-out information 341
programming 412,414
programming hardware 453
selection guide 18
CORE Solution 460
Cornelius Consult 463
CRC circuitry 417
CUPL 461
customer training 529
cyclic redundancy check (CRC) circuitry 417

D
Data I/O Corp. 460,463
DC/Expert 461
DC/Pro 461
De Morgan's inversion 11
dedicated global Clocks 12
dedicated input pins
Classic devices 237
EPS464 devices 220, 223
FLEX 8000 devices 41
MAX 5000 devices 152
MAX 7000 devices 71
SAM devices 327
DESC 352
Design Architect 461
Design Doctor (MAX+PLUS II) 443
design entry
Altera Hardware Description Language
(AHDL) 440
Altera State Machine Input Language
(ASMILE) 322
Assembly Language (ASM) 323,329,334
CAE software support 441,459
hierarchical 442
schematic capture 439
symbol generation 439
waveform design entry 440
design evaluations 530
design processing
CAE software support 459
design-rule checking 443
error location 442
industry-standard output formats 444
logic synthesis & fitting 443

I Altera Corporation

design processing (continued)
multi-device partitioning 443
programming file generation 444
SAM+PLUS 322
design security 78
design verification
CAE software support 459
SAM+PLUS 322
simulation 444
timing analysis 446
development tools
CAE software support 459
MAX+PLUS II 437
SAM+PLUS 322
device adapters 524
device architecture
Classic 237
Configuration EPROM 342
EPS464 5, 222
FLEX 8000 6,31
general description 4, 6, 9
MAX 5000 5, 152
MAX 7000 6, 71
SAM 323
device configuration. See configuration
(FLEX 8000 devices)
device erasure 468
device packages
Classic devices 236
Configuration EPROM devices 341
density & pin count range 4
EPS464 devices 150
FLEX 8000 devices 29
MAX 5000 devices 150
MAX 7000 devices 70
ordering information 521
package outlines 489
QFP carrier & development sockets 527
SAM devices 321
device programming
CAE hardware support 463
MAX+ PLUS II 446
programming hardware 453
SAM+PLUS 322
device selection guide 17
distributors, sales 532
DLAB 460

Page 551

!Index

E
EDIF 2 0 0 & 2 9 0 support 441
EEPROM cells 71, 469
Elan Digital Systems Limited, U.K. 463
electronic bulletin board service (BBS) 529
Enable signal, timing parameter
definition 420
EPCxxxx. See Configuration EPROM devices
EPFxxxx. See FLEX 8000 devices
EPLDs. See Erasable Programmable Logic
Devices (EPLDs)
EPM5xxx devices. See MAX 5000 devices
EPM7xxx devices. See MAX 7000 devices
EPROM cells 71, 467
EPS448 devices. See SAM devices
EPS464 devices
architecture 5, 222
CAE software support 459
development tools 227
general description 219
ordering information 521
package outlines 489
packages 150
reliability 467
Security Bit 224
selection guide 20
timing model 224
timing parameter definition 419,421
EPxxxx devices. See Classic devices
Erasable Programmable Logic Devices
(EPLDs) 9, 10, 12, 13. See also Classic
devices; EPS464 devices; MAX 5000 devices;
MAX 7000 devices; Micro Channel devices;
SAM devices
ertec GmbH 463
evaluations, design 530
Exemplar Logic, Inc. 460
EXTEST (JTAG instruction) 43
extraction tool 485

fitting. See MAX+PLUS II: design processing
FLEX 8000 devices
architecture 4,6, 13, 15, 31
CAE software support 459
configuration. See configuration
(FLEX 8000 devices)
development tools 62
EPF8282 29,43,58,63
EPF8282V 29,43,313
EPF8452 29,56,63
EPF8820 29,43,54
EPF81188 29,50,52
EPF81500 29/43
general description 30
Icc calculations 60
MPLD conversion 357
ordering information 521
package outlines 489
packages 29
pin-out information 63
programming hardware 453
reliability 417,467
selection guide 18
timing model 46
flipflops 12, 13
floating node licenses 523
Flynn Systems Corp. 460
Fowler-Nordheim tunneling 469
FPGA Compiler 461
FS-High Density 460
FS-PALibrary 460
functional simulation 322/ 445
functional testing. See testing
FutureNet 460

G
generic testing. See testing
GenRad 460
global Clock signals 12/74,80,154
global program length counter (FLEX 8000
devices) 388

FastTrack Interconnect 15,32,40,46
feedback
dual I/O 13,77,156
selection 240
timing parameter definition 421

I Page 552

Altera Corporation

Index I

global signals
Classic devices 239
FLEX 8000 40, 41
MAX 5000 devices 152
MAX 7000 devices 71
timing parameter definition 420,422
Graphic Editor (MAX+PLUS II) 439

H
HAMIS Haase, Menrad & Co. GmbH 463
hardware requirements (MAX+PLUS II) 448
Hexadecimal (Intel-Format) File (.hex) 411,
412,415,446
Hi/Lo Systems/Tribal Microsystems 464
Hilo 460
hold time, timing parameter definition 421,
422
horizontal cascading (SAM devices) 329
HP workstations 448

I/O control block 13, 77, 156,224
I/ a element (IOE)
FLEX 8000 31,41
FLEX 8000 JTAG 44
ICE Technical Ltd. 463
in-circuit reconfiguration (FLEX 8000
devices) 404,415,416
initialization (FLEX 8000 devices). See
configuration (FLEX 8000 devices)
Instronic Peripherals & Systems 463
Intergraph Corp. 460
IOE. See I/O element
ISDATA GmbH 460

J
JEDEC File (.jed) 446
JTAG Boundary-Scan Test 43

L
LAB. See Logic Array Block (LAB)
latches, timing delay parameters 421
LE. See logic element
Leap Electronic Co. Ltd. 463
/ Altera Corporation

Leapfrog 460
library of parameterized modules (LPM)
support 441
Link Computer Graphics, Inc. 463
LOG/ic 460
Logic Array Block (LAB)
FLEX 8000 devices 31,38,40
MAX 5000 devices 152
MAX 7000 devices 72
logic element (LE)
general description 9, 13,31,32
operating modes 35
logic expander. See product terms: expanders
logic minimization 11
Logic Modeling Corp. 460
Logic Programmer cards 453, 456
logic synthesis. See MAX+PLUS II: design
processing
Logical Devices, Inc. 461,463
look-up table (LUT) 31,32
loop counter 327
low-power devices. See 3.3-V devices
low-power mode 78,240,421
LP5 & LP6 cards 453, 456
LPM support 441
LUT. See look-up table (LUT)

M
macrocells
architecture 9, 72, 153, 222, 237
general description 9, 10
low-power mode 78
timing parameter definition 421
maintenance agreements 524
Mask-Programmed Logic Devices (MPLDs)
357
Master Programming Unit (MPU) 81,453,
456,525
MAX 5000 devices
architecture 4,5, 152
CAE software support 459
clocking modes 154
EPM5016 149,161
EPM5032 149, 167
EPM5064 149,175
EPM5128 149,181

Page 553/

I Index
MAX 5000 devices (continued)
EPM5128A 149, 189
EPM5130 149, 193
EPM5192 149,203
EPM5192A 149,211
general description 149
MPLD conversion 357
ordering information 521
package outlines 489
packages 150
programming hardware 453
reliability 467
Security Bit 156
selection guide 20
timing model 156,427
timing parameter definition 419,421
MAX 7000 devices
architecture 4,6,71
CAE software support 459
clocking modes 74
EPM7032 69, 83
EPM7032V 69,303
EPM7064 69, 93
EPM7096 69, 99
EPM7128 69,107
EPM7160 69, 117
EPM7192 69, 127
EPM7256 69,137
general description 69
MPLD conversion 357
ordering information 521
package outlines 489
packages 70,521
power-down mode 305
programmable speed/power control 78
programming hardware 453
reliability 467
Security Bit 78
selection guide 19
timing model 78,428
timing parameter definition 419,421
Turbo Bit 78, 305
MAX+PLUSII
Altera Hardware Description Language
(AHDL) 440
CAE software support 16, 459
design entry 15,439

MAX+PLUS II (continued)
design processing 15,442,446
design verification 15,419,444
device programming 15,412,414,446
general description 8, 15
ordering information 522
programming hardware 453
selection guide 449
system requirements 448
Mentor Graphics Corp. 460
Micro Channel devices
EPB2001 339
general descriptin 339
ordering information 521
package outlines 489
programming hardware 453
selection guide 22
Micro EDA 463
microcode EPROM (SAM devices) 324
microcoded controllers (SAM devices) 322
microparameters. See timmg parameters
MicroPross 463
military devices
DESC 352
EP1810 MIL-STD-883-Compliant 295
EP610 MIL-STD-883-Compliant 265
general description 351
MIL-STD-883B-compliant description 352
Military Product Drawings (MPDs) 352,
522
military-temperature-range 351
ordering information 522
qualification 352
selection guide 24
Source Control Drawings (SCDs) 354
Minc Inc. 461
MOD 461
modem access 529
Motive 461
MPDs 352, 522
MPLDs 5, 357. See also Mask-Programmed
Logic Devices
MPU 81,453,525-526
multiway branching 333

N
normal mode (FLEX 8000 logic element)

I Page 554

Altera Corporation

Index I

o
OrCAD Systems Corp. 461
ordering information 521
outlines, package 489
Output Enable control (SAM devices)
Output Enable signals
Classic devices 237, 238
EPS464 devices 223
FLEX 8000 I/O elements 42
MAX 5000 devices 154
MAX 7000 devices 77, 306
output slew-rate 42
Owen Electronic GmbH 463

328

p
package outlines 489
packages, device. See device packages
parallel EPROM (FLEX 8000
configuration) 390,412,415
passive parallel asynchronous & synchronous
(PPA & PPS configuration schemes). See
configuration (FLEX 8000 devices)
passive serial (PS). See configuration
(FLEX 8000 devices)
PC system configuration (MAX+PLUS II) 448
PIA. See Programmable Interconnect Array
pin-out information
Classic devices 245,249,257,261,265,
269,275,279,283,290,291,298
Configuration EPROM devices 341
EPS464 devices 173,219,231
FLEX 8000 devices 63
MAX 5000 devices 161, 167, 175, 181, 186,
189,193,199,203,208,211,214
MAX 7000 devices 83,93,97,99, 104, 107,
113, 117, 123, 127, 137, 143
SAM devices 321
pins
configuration (FLEX 8000 devices) 386,
407,410
dedicated input 41, 71, 152, 220, 223, 237,
327
JTAG Boundary-Scan Test 43
timing delay parameters 419,421,422
pipeline register 324
PL-EXTx 527
1

Altera Corporation

PL-SKT / Qxxx 527
PLAD3-12 454
PLAESW-xxx 452
PLAESW-xxxx 524
PLD (OrCAD) 461
PLD Option 460
PLD Synthesis 461
PLDesigner-XL 461
PLDs 3. See also Classic devices; EPS464
devices; FLEX 8000 devices;MAX 5000
devices; MAX 7000 devices; MaskProgrammed Logic devices; Micro Channel
devices; SAM devices
PLDS-HPS 450,522
PLE-prefix adapters. See programming
hardware
PLM-prefix adapters. See programming
hardware
PLS-ADV 450,522
PLS-ES 450, 522
PLS-FLEX8 450, 522
PLS-HPS 450, 522
PLS-STD 450, 522
PLS-WS/HP 450,522,523
PLS-WS/SN 450,522,523
PLSM-5K 450, 522
PLSM-7K 450,522
PLSM-8K 450, 522
PLSM-ADE 450,522
PLSM-TA 450,522
PLSM-WS/HP 450
PLSM-WS/SN 450
POR circuitry 390,417
power-down mode (MAX 7000 devices) 78,
305
power-on reset (POR) circuitry 390,417
PPA & PPS configuration schemes. See
configuration (FLEX 8000 devices)
Preset signals
EPS464 devices 223
FLEX 8000 logic elements 36,38,40
MAX 5000 devices 154
MAX 7000 devices 73
timing parameter definition 420
product reliability 467

Page 5551

I Index
product terms
allocatable 12
Classic devices 237
control signal generation 11
EPS464 devices 222
expanders 74, 420
general description 10
MAX 7000 devices 71, 73
parallel expanders 12,75,420,434
SAM devices 326
secondary 154
shared & shareable expanders 12,74, 154,
223,420
timing parameter definition 420,434
product-term array 153, 222
product-term select matrix 72,73,74,222
program length counter (FLEX 8000
devices) 388
Programmable Interconnect Array (PIA) 13,
76,155,420
programmable logic
advantages 7
introduction 3
programmable logic devices 3. See also
Classic devices; EPS464 devices; FLEX 8000
devices; MAX 5000 devices; MAX 7000
devices; Mask-Programmed Logic devices;
Micro Channel devices; SAM devices
programmable speed/power control 304,305
Programmer Object File (.pof) 411,412,415,
446
programming. See device programming
programming hardware
adapters 454,524
Altera Stand-Alone Programmer (PLASAP2) 454
development tool support 446
FLEX Download Cable 386,400,414,454
Logic Programmer cards 453
Master Programming Unit (MPU) 453
ordering information 524
requirements 456
Prologic Systems 463
propagation delays. See timing parameters
PS configuration scheme. See configuration
(FLEX 8000 devices)

I Page 556

Q
QFP carrier & development socket
dimensions 480,481
general description 81,480
ordering information 527
QFP device extraction tool 486
Quad Design 461
quality standards 467
QuickSim II 461

R
Racal-Redac 461
RapidSIM 460
reconfiguration, real-time. See configuration
(FLEX 8000 devices)
register feedback, timing parameter
definition 421
reliability
configuration (FLEX 8000 devices) 417
standards 467
testing 474
Report File (.rpt), Equations Section 432
representatives, sales 532
routing, signal 13

s
sales offices, representatives &
distributors 531
SAM (EPS448) devices
architecture 323
development tools 322
general description 321
instruction set 329
nRESET pin 328
ordering information 521
package outlines 489
packages 321
programming hardware 453
Security Bit 334
selection guide 22
SAM+PLUS 322
SAMPLE (JTAG instruction) 43
SAMSIM 321
SCDs 354, 522

Altera Corporation

Index

schematic capture. See design entry
SDT 461
Security Bit 78
selection guide
component (device) 17
MAX+PLUS II 449
sequential functions
EPLDs 12
FLEX 8000 devices 14
setup time, timing parameter definition 421
simulation
functional 322, 445
timing 445
Vector Files (.vee) 444
Simulator (MAX+PLUS II) 444
Simulator Netlist File (.snf) 444
slew-rate 42
SmartModels 460
SMS Micro Systems 463
sockets, QFP device 486, 527
software maintenance agreement 524
Source Control Drawings (SCDs) 354, 522
SRAM Object File (.sof) 411,412,415,446
stack (SAM devices) 327
Stag Microsystems 464
standard CAE support. See CAE hardware
support & CAE software support
state machines 322, 440
Sun SPARCstations 448
Sunrise Electronic Inc. 464
Sunshine Electronics Co. Ltd. 464
Susie 460
switching waveforms. See waveforms
Symbol Editor (MAX+PLUS II) 439
Synergy 460
Synopsys, Inc. 461
Synovation 460
System Expert 461
System General 464
system requirements (MAX+PLUS II) 448
SystemPGA 460

T
Tabular Text File (.Uf) 411,413,415,446
Tango-PLD 460
Tango-Schematic 460

Altera Corporation

TAP Controller 45
technical support 529, 530
Test Access Port (TAP) Controller 45
testing
functional 80, 334, 453
generic 47,80
reliability 474
scan-based (MPLDs) 358
voltage margin 472
wafer 473
Text Editor (MAX+PLUS II) 440,444
Timing Analyzer (MAX+PLUS II) 446
timing model
Classic devices 241
EPS464 devices 224
FLEX 8000 devices 46
MAX 5000 devices 156
MAX 7000 devices 78
timing parameters
internal delay parameter definitions 419
pin-to-pin delay parameter
definitions 421
timing simulation 445
training courses 529
Tribal Microsystems/HiLo Systems 464
tunneling, Fowler-Nordheim 469
Turbo Bit 78,240,305

u
up I down counter mode (FLEX 8000 logic
element) 37
user mode (FLEX 8000 devices) 383

v
Verilog & Verilog-XL 460
vertical cascading (SAM devices)
VHDL Designer 461
Viewdraw 461
Viewlogic Systems, Inc. 461
ViewPLD 461
Viewsim 461
Visula 461
voltage margin testing 472
VSS Simulator 461
VST 461

329

Page 5571

I Index

w
wafer testing 473
Waveform Editor (MAX+PLUS II) 440,444,
445
waveforms, configuration (FLEX 8000 devices)
active parallel up & down (APU &
APD) 392
active serial (AS) 345,388
passive parallel asynchronous (PPA) 397,
398
passive parallel synchronous (PPS) 395
passive serial (PS) 403
waveforms, timing
Classic devices 242
EPS464 devices 226
MAX 5000 devices 158
MAX 7000 devices 79, 305
SAM devices 335
workstation configuration requirements
(MAX +PLUS II) 448

x
Xeltek 464

I Page 558

Altera Corporation

Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
Telephone: (408) 894-7000

Altera Europe
Solar House
Globe Park
Fieldhouse Lane
Marlow
Bucks SL7ITB, U.K.
Telephone: 0628 488800

Altera Japan K.K.

...

Ichikawa Gakugeidai Bldg.
Second Floor
12-8 Takaban 3-Chome
Meguro-Ku, Tokyo 152
Telephone: 03 (3716)1241

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